2188 files changed, 59257 insertions, 92201 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6f28e1ec10..1377679ac9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 config ARM
 	bool
 	select HAS_KALLSYMS
@@ -5,8 +7,9 @@ config ARM
 	select HAVE_CONFIGURABLE_TEXT_BASE if !RELOCATABLE
 	select HAVE_IMAGE_COMPRESSION
 	select HAVE_ARCH_KASAN
-	select HAS_ARCH_SJLJ
+	select ARCH_HAS_SJLJ
 	select ARM_OPTIMZED_STRING_FUNCTIONS if KASAN
+	select HAVE_EFI_STUB
 	default y
 
 config ARM_LINUX
@@ -14,9 +17,6 @@ config ARM_LINUX
 	default y
 	depends on CMD_BOOTZ || CMD_BOOTU || BOOTM
 
-config HAVE_MACH_ARM_HEAD
-	bool
-
 config ARM_USE_COMPRESSED_DTB
        bool
        select USE_COMPRESSED_DTB
@@ -27,49 +27,56 @@ config TEXT_BASE
 
 menu "System Type"
 
+config ARCH_STM32
+	bool
+	help
+	  Selected by both STM32 MCUs and MPUs to restrict driver
+	  visibility.
+
+config ARCH_OMAP
+	bool
+	select HAS_DEBUG_LL
+	select GPIOLIB
+
 choice
 	prompt "ARM system type"
 
+config ARCH_MULTIARCH
+	bool "Allow multiple archs to be selected"
+
 config ARCH_AT91
 	bool "Atmel AT91"
+	depends on 32BIT
 	select GPIOLIB
 	select CLKDEV_LOOKUP
+	select HAVE_PBL_MULTI_IMAGES
 	select HAS_DEBUG_LL
 	select HAVE_CLK
 	select COMMON_CLK_AT91 if COMMON_CLK_OF_PROVIDER
 
-
-config ARCH_BCM283X
-	bool "Broadcom BCM283x based boards"
-	select GPIOLIB
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select COMMON_CLK_OF_PROVIDER
-	select CLOCKSOURCE_BCM283X
-	select ARM_AMBA
-	select HAS_DEBUG_LL
-	select RELOCATABLE
-	select OFTREE
-	select OFDEVICE
-	select HAVE_PBL_MULTI_IMAGES
-
 config ARCH_CLPS711X
 	bool "Cirrus Logic EP711x/EP721x/EP731x"
-	select CLKDEV_LOOKUP
+	depends on 32BIT
 	select CLOCKSOURCE_CLPS711X
 	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
 	select CPU_32v4T
 	select GPIOLIB
+	select HAS_DEBUG_LL
+	select HAVE_PBL_MULTI_IMAGES
 	select MFD_SYSCON
+	select RELOCATABLE
 
 config ARCH_DAVINCI
 	bool "TI Davinci"
+	depends on 32BIT
 	select CPU_ARM926T
 	select HAS_DEBUG_LL
 	select GPIOLIB
 
 config ARCH_DIGIC
 	bool "Canon DIGIC-based cameras"
+	depends on 32BIT
 	select CPU_ARM946E
 	select HAS_DEBUG_LL
 	select CLOCKSOURCE_DIGIC
@@ -79,37 +86,17 @@ config ARCH_DIGIC
 
 config ARCH_EP93XX
 	bool "Cirrus Logic EP93xx"
+	depends on 32BIT
 	select CPU_ARM920T
 	select GENERIC_GPIO
 
-config ARCH_IMX
-	bool "Freescale iMX-based"
-	select GPIOLIB
-	select COMMON_CLK
-	select CLKDEV_LOOKUP
-	select WATCHDOG_IMX_RESET_SOURCE
-	select HAS_DEBUG_LL
-
-config ARCH_LAYERSCAPE
-	bool "NXP Layerscape based"
-	select GPIOLIB
-	select HAS_DEBUG_LL
-	select HAVE_PBL_MULTI_IMAGES
-	select COMMON_CLK
-	select CLKDEV_LOOKUP
-	select COMMON_CLK_OF_PROVIDER
-	select HW_HAS_PCI
-	select OFTREE
-	select OFDEVICE
-
 config ARCH_MVEBU
 	bool "Marvell EBU platforms"
+	depends on 32BIT
 	select COMMON_CLK
 	select COMMON_CLK_OF_PROVIDER
-	select CLKDEV_LOOKUP
 	select GPIOLIB
 	select HAS_DEBUG_LL
-	select HAVE_MACH_ARM_HEAD
 	select HAVE_PBL_MULTI_IMAGES
 	select HW_HAS_PCI
 	select MVEBU_MBUS
@@ -119,80 +106,169 @@ config ARCH_MVEBU
 
 config ARCH_MXS
 	bool "Freescale i.MX23/28 (mxs) based"
+	depends on 32BIT
 	select GPIOLIB
 	select GENERIC_GPIO
 	select COMMON_CLK
-	select CLKDEV_LOOKUP
 	select HAS_DEBUG_LL
 	select HAVE_PBL_MULTI_IMAGES
 
 config ARCH_NOMADIK
 	bool "STMicroelectronics Nomadik"
+	depends on 32BIT
 	select CPU_ARM926T
 	select CLOCKSOURCE_NOMADIK
-	select HAVE_CLK
+	select HAVE_LEGACY_CLK
 	help
 	  Support for the Nomadik platform by ST-Ericsson
 
-config ARCH_OMAP
+config ARCH_OMAP_SINGLE
 	bool "TI OMAP"
-	select HAS_DEBUG_LL
-	select GPIOLIB
+	depends on 32BIT
+	select ARCH_OMAP
 
 config ARCH_PXA
 	bool "Intel/Marvell PXA based"
+	depends on 32BIT
 	select GENERIC_GPIO
 
-config ARCH_ROCKCHIP
-	bool "Rockchip RX3xxx"
-	select CPU_V7
+config ARCH_SOCFPGA
+	bool "Altera SOCFPGA"
+	depends on 32BIT
+	select HAS_DEBUG_LL
 	select ARM_SMP_TWD
+	select CPU_V7
+	select COMMON_CLK
+
+config ARCH_TEGRA
+	bool "NVIDIA Tegra"
+	depends on 32BIT
+	select CPU_V7
+	select HAS_DEBUG_LL
+	select HW_HAS_PCI
 	select COMMON_CLK
-	select CLKDEV_LOOKUP
 	select COMMON_CLK_OF_PROVIDER
 	select GPIOLIB
+	select GPIO_TEGRA
+	select HAVE_PBL_MULTI_IMAGES
+	select OFDEVICE
+	select OFTREE
+	select RELOCATABLE
+	select RESET_CONTROLLER
 	select PINCTRL
-	select PINCTRL_ROCKCHIP
+
+config ARCH_UEMD
+	bool "RC Module UEMD Platform"
+	depends on 32BIT
+	select CPU_ARM1176
+	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
+	select OFDEVICE
 	select OFTREE
+	select CLOCKSOURCE_UEMD
+	select HAS_DEBUG_LL
+
+config ARCH_ZYNQ
+	bool "Xilinx Zynq-based boards"
+	depends on 32BIT
+	select HAS_DEBUG_LL
+	select PBL_IMAGE
+	select GPIOLIB
+
+endchoice
+
+config ARCH_ARM64_VIRT
+	bool "ARM64 QEMU Virt board"
+	depends on 64BIT
+	select CPU_V8
 	select HAVE_PBL_MULTI_IMAGES
+	select OFDEVICE
+	select OFTREE
+	select RELOCATABLE
+	select ARM_AMBA
+	select BOARD_ARM_VIRT
+	select HW_HAS_PCI
 	select HAS_DEBUG_LL
-	select ARCH_HAS_L2X0
 
-config ARCH_SOCFPGA
-	bool "Altera SOCFPGA"
+config ARCH_BCM283X
+	bool "Broadcom BCM283x based boards"
+	select GPIOLIB
+	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
+	select CLOCKSOURCE_BCM283X
+	select ARM_AMBA
 	select HAS_DEBUG_LL
-	select ARM_SMP_TWD
-	select CPU_V7
+	select RELOCATABLE
+	select OFTREE
+	select OFDEVICE
+	select HAVE_PBL_MULTI_IMAGES
+
+config ARCH_IMX
+	bool "Freescale iMX-based"
+	depends on ARCH_MULTIARCH
+	select GPIOLIB
 	select COMMON_CLK
-	select CLKDEV_LOOKUP
+	select WATCHDOG_IMX_RESET_SOURCE
+	select HAS_DEBUG_LL
+	select HAVE_PBL_MULTI_IMAGES
+	select RELOCATABLE
 
-config ARCH_S3C24xx
-	bool "Samsung S3C2410, S3C2440"
-	select ARCH_SAMSUNG
-	select CPU_ARM920T
-	select GENERIC_GPIO
+config ARCH_K3
+	bool "Texas Instruments Inc. K3 multicore SoC architecture"
+	depends on 64BIT
+	select CPU_V8
+	select GPIOLIB
+	select COMMON_CLK
+	select HAVE_PBL_MULTI_IMAGES
+	select HAS_DEBUG_LL
+	select COMMON_CLK_OF_PROVIDER
+	select PM_GENERIC_DOMAINS
 
-config ARCH_S5PCxx
-	bool "Samsung S5PC110, S5PV210"
-	select ARCH_SAMSUNG
-	select CPU_V7
-	select GENERIC_GPIO
+config ARCH_LAYERSCAPE
+	bool "NXP Layerscape based"
+	depends on ARCH_MULTIARCH
+	select GPIOLIB
+	select HAS_DEBUG_LL
+	select HAVE_PBL_MULTI_IMAGES
+	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
+	select HW_HAS_PCI
+	select OFTREE
+	select OFDEVICE
+	select ARM_USE_COMPRESSED_DTB
+	select OF_DMA_COHERENCY
 
-config ARCH_S3C64xx
-	bool "Samsung S3C64xx"
-	select ARCH_SAMSUNG
-	select CPU_V6
-	select GENERIC_GPIO
+config ARCH_OMAP_MULTI
+	bool "TI OMAP"
+	depends on 32BIT
+	depends on ARCH_MULTIARCH
+	select OMAP_MULTI_BOARDS
+	select ARCH_OMAP
+	select HAS_DEBUG_LL
+	select GPIOLIB
+
+config ARCH_ROCKCHIP
+	bool "Rockchip RX3xxx"
+	depends on ARCH_MULTIARCH
+	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
+	select GPIOLIB
+	select PINCTRL
+	select PINCTRL_ROCKCHIP
+	select OFTREE
+	select HAVE_PBL_MULTI_IMAGES
+	select HAS_DEBUG_LL
+	imply GPIO_ROCKCHIP
 
 config ARCH_STM32MP
 	bool "STMicroelectronics STM32MP"
+	depends on 32BIT
+	select ARCH_STM32
 	select CPU_V7
 	select HAVE_PBL_MULTI_IMAGES
-	select CLKDEV_LOOKUP
 	select COMMON_CLK
 	select COMMON_CLK_OF_PROVIDER
 	select HAS_DEBUG_LL
-	select HAVE_CLK
 	select GPIOLIB
 	select ARCH_HAS_RESET_CONTROLLER
 	select ARM_AMBA
@@ -201,17 +277,22 @@ config ARCH_STM32MP
 
 config ARCH_VERSATILE
 	bool "ARM Versatile boards (ARM926EJ-S)"
+	depends on 32BIT
 	select GPIOLIB
-	select HAVE_CLK
+	select ARM_AMBA
+	select AMBA_SP804
 	select HAS_DEBUG_LL
+	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
+	select HAVE_PBL_MULTI_IMAGES
 
 config ARCH_VEXPRESS
 	bool "ARM Vexpress & virt boards"
+	depends on 32BIT
 	select HAS_DEBUG_LL
 	select CPU_V7
 	select ARM_AMBA
 	select AMBA_SP804
-	select CLKDEV_LOOKUP
 	select COMMON_CLK
 	select COMMON_CLK_OF_PROVIDER
 	select OFTREE
@@ -219,67 +300,21 @@ config ARCH_VEXPRESS
 	select RELOCATABLE
 	select HAVE_PBL_MULTI_IMAGES
 
-config ARCH_TEGRA
-	bool "NVIDIA Tegra"
-	select CPU_V7
-	select HAS_DEBUG_LL
-	select HW_HAS_PCI
-	select COMMON_CLK
-	select COMMON_CLK_OF_PROVIDER
-	select CLKDEV_LOOKUP
-	select GPIOLIB
-	select GPIO_TEGRA
-	select HAVE_PBL_MULTI_IMAGES
-	select OFDEVICE
-	select OFTREE
-	select RELOCATABLE
-	select RESET_CONTROLLER
-	select PINCTRL
-
-config ARCH_UEMD
-	bool "RC Module UEMD Platform"
-	select CPU_ARM1176
-	select COMMON_CLK
-	select COMMON_CLK_OF_PROVIDER
-	select CLKDEV_LOOKUP
-	select OFDEVICE
-	select OFTREE
-	select CLOCKSOURCE_UEMD
-	select HAS_DEBUG_LL
-
-config ARCH_ZYNQ
-	bool "Xilinx Zynq-based boards"
-	select HAS_DEBUG_LL
-	select PBL_IMAGE
-
 config ARCH_ZYNQMP
 	bool "Xilinx ZynqMP-based boards"
+	depends on 64BIT
 	select CPU_V8
 	select HAS_DEBUG_LL
 	select HAVE_PBL_MULTI_IMAGES
 	select ARM_SMCCC
 	select COMMON_CLK
 	select COMMON_CLK_OF_PROVIDER
-	select CLKDEV_LOOKUP
+	select GPIOLIB
 	select OFDEVICE
 	select OFTREE
 	select RELOCATABLE
-	select SYS_SUPPORTS_64BIT_KERNEL
 	select HAS_MACB
 
-config ARCH_ARM64_VIRT
-	bool "ARM64 QEMU Virt board"
-	select CPU_V8
-	select HAVE_PBL_MULTI_IMAGES
-	select OFDEVICE
-	select OFTREE
-	select RELOCATABLE
-	select SYS_SUPPORTS_64BIT_KERNEL
-	select ARM_AMBA
-	select BOARD_ARM_VIRT
-
-endchoice
-
 source "arch/arm/cpu/Kconfig"
 source "arch/arm/mach-at91/Kconfig"
 source "arch/arm/mach-bcm283x/Kconfig"
@@ -292,10 +327,10 @@ source "arch/arm/mach-layerscape/Kconfig"
 source "arch/arm/mach-mxs/Kconfig"
 source "arch/arm/mach-mvebu/Kconfig"
 source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/mach-k3/Kconfig"
 source "arch/arm/mach-omap/Kconfig"
 source "arch/arm/mach-pxa/Kconfig"
 source "arch/arm/mach-rockchip/Kconfig"
-source "arch/arm/mach-samsung/Kconfig"
 source "arch/arm/mach-socfpga/Kconfig"
 source "arch/arm/mach-stm32mp/Kconfig"
 source "arch/arm/mach-versatile/Kconfig"
@@ -308,6 +343,7 @@ source "arch/arm/mach-zynqmp/Kconfig"
 config BOARD_ARM_VIRT
 	bool
 	select BOARD_ARM_GENERIC_DT
+	select BOARD_QEMU_VIRT
 	select OF_OVERLAY
 
 config BOARD_ARM_GENERIC_DT
@@ -373,28 +409,18 @@ config ARM_BOARD_PREPEND_ATAG
 
 endmenu
 
-choice
-	prompt "Barebox code model"
-	help
-	  You should only select this option if you have a workload that
-	  actually benefits from 64-bit processing or if your machine has
-	  large memory. You will only be presented a single option in this
-	  menu if your system does not support both 32-bit and 64-bit modes.
-
-config 32BIT
-	bool "32-bit barebox"
-	depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
-	help
-	  Select this option if you want to build a 32-bit barebox.
-
 config 64BIT
-	bool "64-bit barebox"
-	depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
+	bool "64bit barebox" if "$(ARCH)" != "arm64"
+	default "$(ARCH)" = "arm64"
 	select ARCH_DMA_ADDR_T_64BIT
 	help
 	  Select this option if you want to build a 64-bit barebox.
 
-endchoice
+config 32BIT
+	bool
+	default !64BIT
+	help
+	  Select this option if you want to build a 32-bit barebox.
 
 menu "ARM specific settings"
 
@@ -499,4 +525,7 @@ config ARM_MODULE_PLTS
 	  Say y if your memory configuration puts the heap to far away from the
 	  barebox image, causing relocation out of range errors
 
+config ARM_ATF
+	bool
+
 endmenu
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f4b0e8d6b6..ecc74838f6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -1,11 +1,15 @@
-KBUILD_DEFCONFIG := qemu_virt64_defconfig
+# SPDX-License-Identifier: GPL-2.0-only
+
+KBUILD_DEFCONFIG := multi_v8_defconfig
 
 KBUILD_CPPFLAGS	+= -D__ARM__ -fno-strict-aliasing
 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
-ifeq ($(CONFIG_CPU_V8),y)
+ifeq ($(CONFIG_CPU_64),y)
 KBUILD_CPPFLAGS	+=$(call cc-option,-maarch64,)
-else
+endif
+ifeq ($(CONFIG_CPU_32),y)
 KBUILD_CPPFLAGS	+=$(call cc-option,-marm,)
+KBUILD_CPPFLAGS	+= -msoft-float
 endif
 
 ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
@@ -24,14 +28,12 @@ endif
 # at least some of the code would be executed with MMU off, lets be
 # conservative and instruct the compiler not to generate any unaligned
 # accesses
-ifneq ($(CONFIG_CPU_V8),y)
+ifeq ($(CONFIG_CPU_32),y)
 KBUILD_CFLAGS += -mno-unaligned-access
-else
-KBUILD_CFLAGS += -mstrict-align
 endif
-
+ifeq ($(CONFIG_CPU_64),y)
+KBUILD_CFLAGS += -mstrict-align
 # Prevent use of floating point and Advanced SIMD registers.
-ifeq ($(CONFIG_CPU_V8),y)
 KBUILD_CFLAGS += -mgeneral-regs-only
 endif
 
@@ -39,6 +41,7 @@ endif
 # Note that GCC does not numerically define an architecture version
 # macro, but instead defines a whole series of macros which makes
 # testing for a specific architecture or later rather impossible.
+arch-y				:= -include asm/arch-check.h
 arch-$(CONFIG_CPU_64v8)		:= -D__LINUX_ARM_ARCH__=8 $(call cc-option,-march=armv8-a)
 arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
 arch-$(CONFIG_CPU_32v6)		:=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
@@ -50,19 +53,11 @@ tune-$(CONFIG_CPU_ARM920T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM926T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_XSCALE)	:=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
 
-ifeq ($(CONFIG_CPU_V8), y)
-CFLAGS_ABI	:=-mabi=lp64
-else
-ifeq ($(CONFIG_AEABI),y)
-CFLAGS_ABI	:=-mabi=aapcs-linux
-else
-CFLAGS_ABI	:=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,)
-endif
-endif
+CFLAGS_ABI-$(CONFIG_CPU_64)	:=-mabi=lp64
+CFLAGS_ABI-$(CONFIG_CPU_32)	:=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,)
+CFLAGS_ABI-$(CONFIG_AEABI)	:=-mabi=aapcs-linux
 
-ifeq ($(CONFIG_ARM_UNWIND),y)
-CFLAGS_ABI	+=-funwind-tables
-endif
+CFLAGS_ABI-$(CONFIG_ARM_UNWIND)	+=-funwind-tables
 
 ifeq ($(CONFIG_THUMB2_BAREBOX),y)
 AFLAGS_AUTOIT	:=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mauto-it)
@@ -71,63 +66,46 @@ CFLAGS_THUMB2	:=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
 AFLAGS_THUMB2	:=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
 endif
 
-ifeq ($(CONFIG_CPU_V8), y)
-KBUILD_CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y)
+KBUILD_CPPFLAGS += $(CFLAGS_ABI-y) $(arch-y) $(tune-y)
+
+ifeq ($(CONFIG_CPU_64), y)
 KBUILD_AFLAGS   += -include asm/unified.h
-export S64 = _64
-else
-KBUILD_CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float $(CFLAGS_THUMB2)
+export S64_32 = 64
+export S64 = 64
+endif
+ifeq ($(CONFIG_CPU_32), y)
+KBUILD_CPPFLAGS += $(CFLAGS_THUMB2)
 KBUILD_AFLAGS   += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
+export S64_32 = 32
+export S32 = 32
 endif
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_AT91)		:= at91
-machine-$(CONFIG_ARCH_BCM283X)		:= bcm283x
-machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
-machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
-machine-$(CONFIG_ARCH_DIGIC)		:= digic
-machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
-machine-$(CONFIG_ARCH_IMX)		:= imx
-machine-$(CONFIG_ARCH_LAYERSCAPE)	:= layerscape
-machine-$(CONFIG_ARCH_MXS)		:= mxs
-machine-$(CONFIG_ARCH_MVEBU)		:= mvebu
-machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik
-machine-$(CONFIG_ARCH_OMAP)		:= omap
-machine-$(CONFIG_ARCH_PXA)		:= pxa
-machine-$(CONFIG_ARCH_ROCKCHIP)		:= rockchip
-machine-$(CONFIG_ARCH_SAMSUNG)		:= samsung
-machine-$(CONFIG_ARCH_SOCFPGA)		:= socfpga
-machine-$(CONFIG_ARCH_STM32MP)		:= stm32mp
-machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
-machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
-machine-$(CONFIG_ARCH_TEGRA)		:= tegra
-machine-$(CONFIG_ARCH_UEMD)		:= uemd
-machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
-machine-$(CONFIG_ARCH_ZYNQMP)		:= zynqmp
-
-
-# Board directory name.  This list is sorted alphanumerically
-# by CONFIG_* macro name.
-#
-# DO NOT ADD NEW ENTRIES TO THIS LIST!
-# Add to arch/arm/boards/Makefile instead.
-#
-# These are here only because they have a board specific config.h.
-# TODO: Get rid of board specific config.h and move these to
-# arch/arm/boards/Makefile aswell.
-board-$(CONFIG_MACH_A9M2410)			+= a9m2410
-board-$(CONFIG_MACH_A9M2440)			+= a9m2440
-board-$(CONFIG_MACH_AT91RM9200EK)		+= at91rm9200ek
-board-$(CONFIG_MACH_MINI2440)			+= friendlyarm-mini2440
-board-$(CONFIG_MACH_MINI6410)			+= friendlyarm-mini6410
-board-$(CONFIG_MACH_PCM027)			+= phytec-phycore-pxa270
-board-$(CONFIG_MACH_TINY210)			+= friendlyarm-tiny210
-board-$(CONFIG_MACH_TINY6410)			+= friendlyarm-tiny6410
-
-machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
-
-KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
+machine-$(CONFIG_ARCH_AT91)		+= at91
+machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
+machine-$(CONFIG_ARCH_CLPS711X)		+= clps711x
+machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
+machine-$(CONFIG_ARCH_DIGIC)		+= digic
+machine-$(CONFIG_ARCH_EP93XX)		+= ep93xx
+machine-$(CONFIG_ARCH_IMX)		+= imx
+machine-$(CONFIG_ARCH_K3)		+= k3
+machine-$(CONFIG_ARCH_LAYERSCAPE)	+= layerscape
+machine-$(CONFIG_ARCH_MXS)		+= mxs
+machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
+machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
+machine-$(CONFIG_ARCH_OMAP)		+= omap
+machine-$(CONFIG_ARCH_PXA)		+= pxa
+machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
+machine-$(CONFIG_ARCH_SAMSUNG)		+= samsung
+machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
+machine-$(CONFIG_ARCH_STM32MP)		+= stm32mp
+machine-$(CONFIG_ARCH_VERSATILE)	+= versatile
+machine-$(CONFIG_ARCH_VEXPRESS)		+= vexpress
+machine-$(CONFIG_ARCH_TEGRA)		+= tegra
+machine-$(CONFIG_ARCH_UEMD)		+= uemd
+machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
+machine-$(CONFIG_ARCH_ZYNQMP)		+= zynqmp
 
 TEXT_BASE = $(CONFIG_TEXT_BASE)
 
@@ -155,13 +133,6 @@ endif
 
 KBUILD_BINARY := barebox.bin
 
-barebox.s5p: $(KBUILD_BINARY)
-	$(Q)scripts/s5p_cksum $< barebox.s5p
-
-ifeq ($(CONFIG_ARCH_S5PCxx),y)
-KBUILD_IMAGE := barebox.s5p
-endif
-
 quiet_cmd_mlo ?= IFT     $@
 	cmd_mlo ?= scripts/omap_signGP -o MLO -l $(TEXT_BASE) -c $<
 
@@ -184,29 +155,6 @@ ifeq ($(CONFIG_ARCH_DAVINCI),y)
 KBUILD_IMAGE := barebox.ubl
 endif
 
-quiet_cmd_am35xx_spi_image = SPI-IMG $@
-      cmd_am35xx_spi_image = scripts/mk-omap-image -s -a $(TEXT_BASE) $< > $@
-
-barebox.spi: $(KBUILD_BINARY) FORCE
-	$(call if_changed,am35xx_spi_image)
-
-MLO.spi: MLO FORCE
-	$(call if_changed,am35xx_spi_image)
-
-ifeq ($(CONFIG_OMAP_BUILD_SPI),y)
-KBUILD_IMAGE := MLO.spi
-endif
-
-quiet_cmd_zynq_image = ZYNQ-IMG $@
-      cmd_zynq_image = scripts/zynq_mkimage $< $@
-
-barebox.zynq: $(KBUILD_BINARY) FORCE
-	$(call if_changed,zynq_image)
-
-ifeq ($(machine-y),zynq)
-KBUILD_IMAGE := barebox.zynq
-endif
-
 quiet_cmd_canon_a1100_image = DD      $@
       cmd_canon_a1100_image = scripts/canon-a1100-image $< $@ || \
 	echo "WARNING: Couldn't create Canon A1100 image due to previous errors."
@@ -217,44 +165,6 @@ ifeq ($(CONFIG_MACH_CANON_A1100),y)
 KBUILD_IMAGE := barebox.canon-a1100.bin
 endif
 
-KWBIMAGE_OPTS = \
-	-c -i $(srctree)/$(BOARD)/kwbimage.cfg -d $(TEXT_BASE) -e $(TEXT_BASE)
-
-quiet_cmd_kwbimage = KWB     $@
-      cmd_kwbimage = scripts/kwbimage -p $< $(KWBIMAGE_OPTS) -o $@ || \
-	echo "WARNING: Couldn't create KWB image due to previous errors."
-
-quiet_cmd_kwbimage_uart = KWBUART $@
-      cmd_kwbimage_uart = scripts/kwbimage -m uart -p $< $(KWBIMAGE_OPTS) -o $@ || \
-	echo "WARNING Couldn't create KWB image due to previous errors."
-
-barebox.kwb: $(KBUILD_BINARY) FORCE
-	$(call if_changed,kwbimage)
-
-barebox.kwbuart: $(KBUILD_BINARY) FORCE
-	$(call if_changed,kwbimage_uart)
-
-ifeq ($(CONFIG_ARCH_MVEBU),y)
-KBUILD_IMAGE  := barebox.kwb barebox.kwbuart
-endif
-
-barebox.imximg: $(KBUILD_BINARY) FORCE
-	$(call if_changed,imx_image,$(CFG_$(@F)),)
-
-boarddir = $(srctree)/arch/arm/boards
-imxcfg-$(CONFIG_MACH_FREESCALE_MX53_SMD) += $(boarddir)/freescale-mx53-smd/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += $(boarddir)/eukrea_cpuimx51/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_FREESCALE_MX25_3STACK) += $(boarddir)/freescale-mx25-3ds/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_FREESCALE_MX35_3STACK) += $(boarddir)/freescale-mx35-3ds/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX25) += $(boarddir)/eukrea_cpuimx25/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX35) += $(boarddir)/eukrea_cpuimx35/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_PCM043) += $(boarddir)/phytec-phycore-imx35/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_KINDLE3) += $(boarddir)/kindle3/flash-header.imxcfg
-ifneq ($(imxcfg-y),)
-CFG_barebox.imximg := $(imxcfg-y)
-KBUILD_IMAGE  := barebox.imximg
-endif
-
 archclean:
 	$(MAKE) $(clean)=$(pbl)
 
@@ -265,36 +175,25 @@ dts := arch/arm/dts
 
 KBUILD_IMAGE ?= $(KBUILD_BINARY)
 
-archprepare: maketools
-maketools:
-	$(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h
-
-PHONY += maketools
-
-ifneq ($(board-y),)
-BOARD := arch/arm/boards/$(board-y)/
-else
-BOARD :=
-endif
-
 ifneq ($(machine-y),)
-MACH := arch/arm/mach-$(machine-y)/
+MACH := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 else
 MACH :=
 endif
 
-common-y += $(BOARD) arch/arm/boards/ $(MACH)
+common-y += arch/arm/boards/ $(MACH)
 common-y += arch/arm/cpu/
+common-y += arch/arm/crypto/
 
-ifeq ($(CONFIG_CPU_V8), y)
+ifeq ($(CONFIG_CPU_64), y)
 common-y += arch/arm/lib64/
 else
-common-y += arch/arm/lib32/ arch/arm/crypto/
+common-y += arch/arm/lib32/
 endif
 
 common-$(CONFIG_OFTREE) += arch/arm/dts/
 
-ifeq ($(CONFIG_CPU_V8), y)
+ifeq ($(CONFIG_CPU_64), y)
 lds-y	:= arch/arm/lib64/barebox.lds
 else
 lds-y	:= arch/arm/lib32/barebox.lds
@@ -302,6 +201,6 @@ endif
 
 common- += $(patsubst %,arch/arm/boards/%/,$(board-))
 
-CLEAN_FILES += include/generated/mach-types.h barebox-flash-image
+CLEAN_FILES += barebox-flash-image
 CLEAN_FILES += arch/arm/lib64/barebox.lds
 CLEAN_FILES += arch/arm/lib32/barebox.lds
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 40b0af8d30..05fbcca175 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -1,8 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 # keep sorted by CONFIG_* macro name.
 obj-$(CONFIG_MACH_ADVANTECH_ROM_742X)		+= advantech-mx6/
 obj-$(CONFIG_MACH_AFI_GF)			+= afi-gf/
 obj-$(CONFIG_MACH_ANIMEO_IP)			+= animeo_ip/
 obj-$(CONFIG_MACH_ARCHOSG9)			+= archosg9/
+obj-$(CONFIG_MACH_AT91RM9200EK)			+= at91rm9200ek/
 obj-$(CONFIG_MACH_AT91SAM9260EK)		+= at91sam9260ek/
 obj-$(CONFIG_MACH_AT91SAM9261EK)		+= at91sam9261ek/
 obj-$(CONFIG_MACH_AT91SAM9263EK)		+= at91sam9263ek/
@@ -14,9 +17,12 @@ obj-$(CONFIG_MACH_AT91SAM9N12EK)		+= at91sam9n12ek/
 obj-$(CONFIG_MACH_AT91SAM9X5EK)			+= at91sam9x5ek/
 obj-$(CONFIG_MACH_BEAGLE)			+= beagle/
 obj-$(CONFIG_MACH_BEAGLEBONE)			+= beaglebone/
+obj-$(CONFIG_MACH_BEAGLEPLAY)			+= beagleplay/
+obj-$(CONFIG_MACH_CALAO)			+= calao/
 obj-$(CONFIG_MACH_CANON_A1100)			+= canon-a1100/
 obj-$(CONFIG_MACH_CM_FX6)			+= cm-fx6/
 obj-$(CONFIG_MACH_NITROGEN6)			+= boundarydevices-nitrogen6/
+obj-$(CONFIG_MACH_NOVENA)			+= novena/
 obj-$(CONFIG_MACH_CCMX51)			+= ccxmx51/
 obj-$(CONFIG_MACH_CCMX53)			+= ccxmx53/
 obj-$(CONFIG_MACH_CFA10036)			+= crystalfontz-cfa10036/
@@ -38,33 +44,25 @@ obj-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK)		+= efika-mx-smartbook/
 obj-$(CONFIG_MACH_EMBEDSKY_E9)			+= embedsky-e9/
 obj-$(CONFIG_MACH_EMBEST_MARSBOARD)		+= embest-marsboard/
 obj-$(CONFIG_MACH_EMBEST_RIOTBOARD)		+= embest-riotboard/
-obj-$(CONFIG_MACH_EUKREA_CPUIMX25)		+= eukrea_cpuimx25/
-obj-$(CONFIG_MACH_EUKREA_CPUIMX27)		+= eukrea_cpuimx27/
-obj-$(CONFIG_MACH_EUKREA_CPUIMX35)		+= eukrea_cpuimx35/
-obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD)		+= eukrea_cpuimx51/
 obj-$(CONFIG_MACH_ELTEC_HIPERCAM)		+= eltec-hipercam/
-obj-$(CONFIG_MACH_FREESCALE_MX25_3STACK)	+= freescale-mx25-3ds/
-obj-$(CONFIG_MACH_FREESCALE_MX35_3STACK)	+= freescale-mx35-3ds/
 obj-y						+= freescale-mx51-babbage/
 obj-$(CONFIG_MACH_FREESCALE_MX53_LOCO)		+= freescale-mx53-qsb/
-obj-$(CONFIG_MACH_FREESCALE_MX53_SMD)		+= freescale-mx53-smd/
 obj-$(CONFIG_MACH_FREESCALE_MX53_VMX53)		+= freescale-mx53-vmx53/
 obj-$(CONFIG_MACH_FREESCALE_MX7_SABRESD)	+= freescale-mx7-sabresd/
+obj-$(CONFIG_MACH_MEERKAT96)			+= meerkat96/
 obj-$(CONFIG_MACH_GE863)			+= telit-evk-pro3/
 obj-$(CONFIG_MACH_GK802)			+= gk802/
 obj-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG)		+= globalscale-guruplug/
 obj-$(CONFIG_MACH_GLOBALSCALE_MIRABOX)		+= globalscale-mirabox/
 obj-$(CONFIG_MACH_GRINN_LITEBOARD)		+= grinn-liteboard/
-obj-$(CONFIG_MACH_GUF_CUPID)			+= guf-cupid/
 obj-$(CONFIG_MACH_GUF_SANTARO)			+= guf-santaro/
 obj-$(CONFIG_MACH_GUF_VINCELL)			+= guf-vincell/
 obj-$(CONFIG_MACH_GW_VENTANA)			+= gateworks-ventana/
 obj-$(CONFIG_MACH_HABA_KNX_LITE)		+= haba-knx/
-obj-$(CONFIG_MACH_IMX21ADS)			+= freescale-mx21-ads/
 obj-$(CONFIG_MACH_IMX233_OLINUXINO)		+= imx233-olinuxino/
-obj-$(CONFIG_MACH_IMX27ADS)			+= freescale-mx27-ads/
+obj-$(CONFIG_MACH_INNOCOMM_WB15)			+= innocomm-imx8mm-wb15/
 obj-$(CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR)	+= kamstrup-mx7-concentrator/
-obj-$(CONFIG_MACH_KINDLE3)			+= kindle3/
+obj-$(CONFIG_MACH_KARO_QSXP_ML81)		+= karo-qsxp-ml81/
 obj-$(CONFIG_MACH_KONTRON_SAMX6I)		+= kontron-samx6i/
 obj-$(CONFIG_MACH_LENOVO_IX4_300D)		+= lenovo-ix4-300d/
 obj-$(CONFIG_MACH_LUBBOCK)			+= lubbock/
@@ -75,7 +73,7 @@ obj-$(CONFIG_MACH_MB7707)			+= module-mb7707/
 obj-$(CONFIG_MACH_MIOA701)			+= mioa701/
 obj-$(CONFIG_MACH_MX23EVK)			+= freescale-mx23-evk/
 obj-$(CONFIG_MACH_MX28EVK)			+= freescale-mx28-evk/
-obj-$(CONFIG_MACH_NESO)				+= guf-neso/
+obj-$(CONFIG_MACH_MYIRTECH_X335X)		+= myirtech-x335x/
 obj-$(CONFIG_MACH_NETGEAR_RN104)		+= netgear-rn104/
 obj-$(CONFIG_MACH_NETGEAR_RN2120)		+= netgear-rn2120/
 obj-$(CONFIG_MACH_NOMADIK_8815NHK)		+= nhk8815/
@@ -84,27 +82,34 @@ obj-$(CONFIG_MACH_NVIDIA_JETSON)		+= nvidia-jetson-tk1/
 obj-$(CONFIG_MACH_NXP_IMX6ULL_EVK)		+= nxp-imx6ull-evk/
 obj-$(CONFIG_MACH_NXP_IMX8MQ_EVK)		+= nxp-imx8mq-evk/
 obj-$(CONFIG_MACH_NXP_IMX8MM_EVK)		+= nxp-imx8mm-evk/
+obj-$(CONFIG_MACH_NXP_IMX8MN_EVK)		+= nxp-imx8mn-evk/
 obj-$(CONFIG_MACH_NXP_IMX8MP_EVK)		+= nxp-imx8mp-evk/
+obj-$(CONFIG_MACH_CONGATEC_QMX8P_SOM)		+= congatec-qmx8p/
+obj-$(CONFIG_MACH_TQ_MBA8MPXL)			+= tqma8mpxl/
 obj-$(CONFIG_MACH_OMAP343xSDP)			+= omap343xdsp/
 obj-$(CONFIG_MACH_OMAP3EVM)			+= omap3evm/
 obj-$(CONFIG_MACH_PANDA)			+= panda/
 obj-$(CONFIG_MACH_PCA100)			+= phytec-phycard-imx27/
 obj-$(CONFIG_MACH_PCAAL1)			+= phytec-phycard-omap3/
 obj-$(CONFIG_MACH_PCAAXL2)			+= phytec-phycard-omap4/
-obj-$(CONFIG_MACH_PCM037)			+= phytec-phycore-imx31/
+obj-$(CONFIG_MACH_PCM027)			+= phytec-phycore-pxa270/
 obj-$(CONFIG_MACH_PCM038)			+= phytec-phycore-imx27/
-obj-$(CONFIG_MACH_PCM043)			+= phytec-phycore-imx35/
 obj-$(CONFIG_MACH_PCM049)			+= phytec-phycore-omap4460/
 obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X)		+= phytec-som-am335x/
 obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6)		+= phytec-som-imx6/
 obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7)		+= phytec-phycore-imx7/
+obj-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1)	+= phytec-phycore-stm32mp1/
+obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MM)		+= phytec-som-imx8mm/
 obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ)		+= phytec-som-imx8mq/
 obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3)	+= plathome-openblocks-ax3/
 obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6)	+= plathome-openblocks-a6/
 obj-$(CONFIG_MACH_PM9261)			+= pm9261/
 obj-$(CONFIG_MACH_PM9263)			+= pm9263/
 obj-$(CONFIG_MACH_PM9G45)			+= pm9g45/
+obj-$(CONFIG_MACH_POLYHEX_DEBIX)		+= polyhex-debix/
 obj-$(CONFIG_MACH_PROTONIC_IMX6)		+= protonic-imx6/
+obj-$(CONFIG_MACH_PROTONIC_IMX8M)		+= protonic-imx8m/
+obj-$(CONFIG_MACH_PROTONIC_STM32MP1)		+= protonic-stm32mp1/
 obj-$(CONFIG_MACH_QIL_A9260)			+= qil-a926x/
 obj-$(CONFIG_MACH_QIL_A9G20)			+= qil-a926x/
 obj-$(CONFIG_MACH_RADXA_ROCK)			+= radxa-rock/
@@ -115,24 +120,30 @@ obj-$(CONFIG_MACH_SABRELITE)			+= freescale-mx6-sabrelite/
 obj-$(CONFIG_MACH_SABRESD)			+= freescale-mx6-sabresd/
 obj-$(CONFIG_MACH_AC_SXB)			+= ac-sxb/
 obj-$(CONFIG_MACH_SKOV_IMX6)			+= skov-imx6/
+obj-$(CONFIG_MACH_SKOV_IMX8MP)			+= skov-imx8mp/
 obj-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB)	+= freescale-mx6sx-sabresdb/
 obj-$(CONFIG_MACH_SAMA5D27_GIANTBOARD)		+= sama5d27-giantboard/
 obj-$(CONFIG_MACH_SAMA5D27_SOM1)		+= sama5d27-som1/
 obj-$(CONFIG_MACH_SAMA5D3XEK)			+= sama5d3xek/
 obj-$(CONFIG_MACH_SAMA5D3_XPLAINED)		+= sama5d3_xplained/
 obj-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB)	+= microchip-ksz9477-evb/
+obj-$(CONFIG_MACH_MICROCHIP_SAMA5D3_EDS)	+= microchip-sama5d3-eds/
 obj-$(CONFIG_MACH_SAMA5D4_XPLAINED)		+= sama5d4_xplained/
+obj-$(CONFIG_MACH_SAMA5D4_WIFX)			+= sama5d4_wifx/
 obj-$(CONFIG_MACH_SAMA5D4EK)			+= sama5d4ek/
 obj-$(CONFIG_MACH_SCB9328)			+= scb9328/
 obj-$(CONFIG_MACH_SEEED_ODYSSEY)		+= seeed-odyssey/
 obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK)		+= altera-socdk/
 obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES)		+= ebv-socrates/
+obj-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1)	+= enclustra-aa1/
 obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES)	+= reflex-achilles/
 obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC)	+= terasic-de0-nano-soc/
+obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO)	+= terasic-de10-nano/
 obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT)	+= terasic-sockit/
 obj-$(CONFIG_MACH_SOLIDRUN_CUBOX)		+= solidrun-cubox/
 obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM)		+= solidrun-microsom/
 obj-$(CONFIG_MACH_STM32MP15XX_DKX)		+= stm32mp15xx-dkx/
+obj-$(CONFIG_MACH_STM32MP13XX_DK)		+= stm32mp13xx-dk/
 obj-$(CONFIG_MACH_LXA_MC1)			+= lxa-mc1/
 obj-$(CONFIG_MACH_STM32MP15X_EV1)		+= stm32mp15x-ev1/
 obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT)	+= technexion-pico-hobbit/
@@ -144,6 +155,7 @@ obj-$(CONFIG_MACH_KINDLE_MX50)			+= kindle-mx50/
 obj-$(CONFIG_MACH_TORADEX_COLIBRI_T20)		+= toradex-colibri-t20/
 obj-$(CONFIG_MACH_TOSHIBA_AC100)		+= toshiba-ac100/
 obj-$(CONFIG_MACH_TQMA53)			+= tqma53/
+obj-$(CONFIG_MACH_TQMA6UL)			+= tqma6ulx/
 obj-$(CONFIG_MACH_TQMA6X)			+= tqma6x/
 obj-$(CONFIG_MACH_TURRIS_OMNIA)			+= turris-omnia/
 obj-$(CONFIG_MACH_TX25)				+= karo-tx25/
@@ -162,12 +174,14 @@ obj-$(CONFIG_MACH_VIRT2REAL)			+= virt2real/
 obj-$(CONFIG_MACH_ZEDBOARD)			+= avnet-zedboard/
 obj-$(CONFIG_MACH_ZYLONITE)			+= zylonite/
 obj-$(CONFIG_MACH_VARISCITE_MX6)		+= variscite-mx6/
+obj-$(CONFIG_MACH_VARISCITE_SOM_MX7)		+= variscite-som-mx7/
 obj-$(CONFIG_MACH_VSCOM_BALTOS)			+= vscom-baltos/
-obj-$(CONFIG_BOARD_ARM_VIRT)			+= qemu-virt/
 obj-$(CONFIG_MACH_WARP7)			+= element14-warp7/
 obj-$(CONFIG_MACH_WEBASTO_CCBV2)		+= webasto-ccbv2/
 obj-$(CONFIG_MACH_VF610_TWR)			+= freescale-vf610-twr/
+obj-$(CONFIG_MACH_XILINX_ZCU102)		+= xilinx-zcu102/
 obj-$(CONFIG_MACH_XILINX_ZCU104)		+= xilinx-zcu104/
+obj-$(CONFIG_MACH_XILINX_ZCU106)		+= xilinx-zcu106/
 obj-$(CONFIG_MACH_ZII_COMMON)			+= zii-common/
 obj-$(CONFIG_MACH_ZII_RDU1)			+= zii-imx51-rdu1/
 obj-$(CONFIG_MACH_ZII_RDU2)			+= zii-imx6q-rdu2/
@@ -175,7 +189,17 @@ obj-$(CONFIG_MACH_ZII_IMX8MQ_DEV)		+= zii-imx8mq-dev/
 obj-$(CONFIG_MACH_ZII_VF610_DEV)		+= zii-vf610-dev/
 obj-$(CONFIG_MACH_ZII_IMX7D_DEV)		+= zii-imx7d-dev/
 obj-$(CONFIG_MACH_WAGO_PFC_AM35XX)		+= wago-pfc-am35xx/
+obj-$(CONFIG_MACH_LS1028ARDB)			+= ls1028ardb/
 obj-$(CONFIG_MACH_LS1046ARDB)			+= ls1046ardb/
 obj-$(CONFIG_MACH_TQMLS1046A)			+= tqmls1046a/
+obj-$(CONFIG_MACH_LS1021AIOT)			+= ls1021aiot/
 obj-$(CONFIG_MACH_MNT_REFORM)			+= mnt-reform/
 obj-$(CONFIG_MACH_SKOV_ARM9CPU)			+= skov-arm9cpu/
+obj-$(CONFIG_MACH_RK3568_EVB)			+= rockchip-rk3568-evb/
+obj-$(CONFIG_MACH_RK3568_BPI_R2PRO)			+= rockchip-rk3568-bpi-r2pro/
+obj-$(CONFIG_MACH_PINE64_QUARTZ64)		+= pine64-quartz64/
+obj-$(CONFIG_MACH_RADXA_ROCK3)			+= radxa-rock3/
+obj-$(CONFIG_MACH_RADXA_ROCK5)			+= radxa-rock5/
+obj-$(CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP)	+= variscite-dt8mcustomboard-imx8mp/
+obj-$(CONFIG_MACH_RADXA_CM3)			+= radxa-cm3/
+obj-$(CONFIG_MACH_TQMA93XX)			+= tqma93xx/
diff --git a/arch/arm/boards/a9m2410/Makefile b/arch/arm/boards/a9m2410/Makefile
deleted file mode 100644
index 4bf737c1fc..0000000000
--- a/arch/arm/boards/a9m2410/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-lwl-y += lowlevel_init.o
-obj-y += a9m2410.o
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
deleted file mode 100644
index ef727f664d..0000000000
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ /dev/null
@@ -1,137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <asm/sections.h>
-#include <partition.h>
-#include <nand.h>
-#include <io.h>
-#include <mach/devices-s3c24xx.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c24xx-nand.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
-static struct s3c24x0_nand_platform_data nand_info = {
-	.nand_timing = CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
-};
-
-static int a9m2410_mem_init(void)
-{
-	resource_size_t size;
-
-	/*
-	 * Note: On this card the second SDRAM page is not used
-	 */
-	s3c24xx_disable_second_sdram_bank();
-	size = s3c24xx_get_memory_size();
-
-	/* ---------- configure the GPIOs ------------- */
-	writel(0x007FFFFF, S3C_GPACON);
-	writel(0x00000000, S3C_GPCCON);
-	writel(0x00000000, S3C_GPCUP);
-	writel(0x00000000, S3C_GPDCON);
-	writel(0x00000000, S3C_GPDUP);
-	writel(0xAAAAAAAA, S3C_GPECON);
-	writel(0x0000E03F, S3C_GPEUP);
-	writel(0x00000000, S3C_GPBCON);	/* all inputs */
-	writel(0x00000007, S3C_GPBUP);	/* pullup disabled for GPB0..3 */
-	writel(0x00009000, S3C_GPFCON);	/* GPF7 CLK_INT#, GPF6 Debug-LED */
-	writel(0x000000FF, S3C_GPFUP);
-	writel(readl(S3C_GPGDAT) | 0x0010, S3C_GPGDAT);	/* switch off LCD backlight */
-	writel(0xFF00A938, S3C_GPGCON);	/* switch off USB device */
-	writel(0x0000F000, S3C_GPGUP);
-	writel(readl(S3C_GPHDAT) | 0x100, S3C_GPHDAT);	/* switch BOOTINT/GPIO_ON# to high */
-	writel(0x000007FF, S3C_GPHUP);
-	writel(0x0029FAAA, S3C_GPHCON);
-	/*
-	 * USB port1 normal, USB port0 normal, USB1 pads for device
-	 * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
-	 * 2nd SDRAM bank off (only bank 1 is used)
-	 */
-	writel(0x40140, S3C_MISCCR);
-
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, size);
-
-	return 0;
-}
-mem_initcall(a9m2410_mem_init);
-
-static const struct devfs_partition a9m2410_nand0_partitions[] = {
-	{
-		.offset = 0,
-		.size = 0x40000,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "self_raw",
-		.bbname = "self0",
-	}, {
-		.offset = DEVFS_PARTITION_APPEND,
-		.size = 0x20000,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "env_raw",
-		.bbname = "env0",
-	}, {
-		/* sentinel */
-	}
-};
-
-static int a9m2410_devices_init(void)
-{
-	uint32_t reg;
-
-	/* ----------- configure the access to the outer space ---------- */
-	reg = readl(S3C_BWSCON);
-
-	/* CS#1 to access the network controller */
-	reg &= ~0xf0;
-	reg |= 0xe0;
-	writel(0x1350, S3C_BANKCON1);
-
-	/* CS#2 to the dual 16550 UART */
-	reg &= ~0xf00;
-	reg |= 0x400;
-	writel(0x0d50, S3C_BANKCON2);
-
-	writel(reg, S3C_BWSCON);
-
-	/* release the reset signal to the network and UART device */
-	reg = readl(S3C_MISCCR);
-	reg |= 0x10000;
-	writel(reg, S3C_MISCCR);
-
-	/* ----------- the devices the boot loader should work with -------- */
-	s3c24xx_add_nand(&nand_info);
-	/*
-	 * SMSC 91C111 network controller on the baseboard
-	 * connected to CS line 1 and interrupt line
-	 * GPIO3, data width is 32 bit
-	 */
-	add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, S3C_CS1_BASE + 0x300,
-			16, IORESOURCE_MEM, NULL);
-
-	if (IS_ENABLED(CONFIG_NAND))
-		devfs_create_partitions("nand0", a9m2410_nand0_partitions);
-
-	armlinux_set_architecture(MACH_TYPE_A9M2410);
-
-	return 0;
-}
-
-device_initcall(a9m2410_devices_init);
-
-static int a9m2410_console_init(void)
-{
-	barebox_set_model("Digi A9M2410");
-	barebox_set_hostname("a9m2410");
-
-	s3c24xx_add_uart1();
-	return 0;
-}
-
-console_initcall(a9m2410_console_init);
diff --git a/arch/arm/boards/a9m2410/config.h b/arch/arm/boards/a9m2410/config.h
deleted file mode 100644
index dbe4bb32cb..0000000000
--- a/arch/arm/boards/a9m2410/config.h
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/**
- * @file
- * @brief Global defintions for the ARM S3C2410 based a9m2410 CPU card
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/**
- * The external clock reference is a 12.0MHz crystal
- */
-#define S3C24XX_CLOCK_REFERENCE 12000000
-
-/**
- * Define the main clock configuration to be used in register CLKDIVN
- *
- * We must limit the frequency of the connected SDRAMs with the clock ratio
- * setup to 1:2:4. This will result into FCLK:HCLK:PCLK = 200Mhz:100MHz:50MHz
- */
-#define BOARD_SPECIFIC_CLKDIVN 0x003
-
-/**
- * Define the MPLL configuration to be used in register MPLLCON
- *
- * We want the MPLL to run at 202.80MHz
- */
-#define BOARD_SPECIFIC_MPLL ((0xA1 << 12) + (3 << 4) + 1)
-
-/**
- * Define the UPLL configuration to be used in register UPLLCON
- *
- * We want the UPLL to run at 48.0MHz
- */
-#define BOARD_SPECIFIC_UPLL ((0x78 << 12) + (2 << 4) + 3)
-
-/*
- * SDRAM configuration for Samsung K4M563233E
- *  - 2M x 32Bit x 4 Banks Mobile SDRAM
- *  - 90 pin FBGA
- *  - CL2@100MHz
- */
-/*
- * SDRAM uses 32bit width
- */
-#define BOARD_SPECIFIC_BWSCON ((0x02 << 24) + (0x02 << 28))
-/*
- * 32MiB SDRAM in bank6
- *  - MT = 11 (= sync dram type)
- *  - Trcd = 00 (= CL2)
- *  - SCAN = 01 (= 9 bit columns)
- */
-#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + 0x1)
-/*
- * No memory in bank7
- */
-#define BOARD_SPECIFIC_BANKCON7 ((0x3 << 15) + (0x0 << 2) + 0x1)
-/*
- * SDRAM refresh settings
- *  - REFEN = 1 (= refresh enabled)
- *  - TREFMD = 0 (= auto refresh)
- *  - Trp = 00 (= 2 RAS precharge clocks)
- *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
- *  - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
- */
-#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
-/*
- * SDRAM banksize
- *  - BURST_EN = 1 (= burst mode enabled)
- *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
- *  - SCLK_EN = 1 (= clock active only during accesses)
- *  - BK67MAP = 000 (= 32MiB)
- */
-#define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (0 << 4) + 0)
-/*
- * SDRAM mode register bank6
- * CL = 010 (= 2 clocks)
- */
-#define BOARD_SPECIFIC_MRSRB6 (0x2 << 4)
-/*
- * SDRAM mode register bank7
- * CL = 010 (= 2 clocks)
- */
-#define BOARD_SPECIFIC_MRSRB7 (0x2 << 4)
-
-/*
- * Flash access timings
- * Tacls  = 0ns (but 20ns data setup time)
- * Twrph0 = 25ns (write) 35ns (read)
- * Twrph1 = 10ns (10ns data hold time)
- * Read cycle time = 50ns
- *
- * Assumed HCLK is 100MHz
- * Tacls = 1 (-> 20ns)
- * Twrph0 = 3 (-> 40ns)
- * Twrph1 = 1 (-> 20ns)
- * Cycle time = 80ns
- */
-#define A9M2410_TACLS 1
-#define A9M2410_TWRPH0 3
-#define A9M2410_TWRPH1 1
-
-/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C_NAND_BOOT
-# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/a9m2410/env/bin/_update b/arch/arm/boards/a9m2410/env/bin/_update
deleted file mode 100644
index 014bce3512..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/_update
+++ /dev/null
@@ -1,36 +0,0 @@
-#!/bin/sh
-
-if [ -z "$part" -o -z "$image" ]; then
-	echo "define \$part and \$image"
-	exit 1
-fi
-
-if [ ! -e "$part" ]; then
-	echo "Partition $part does not exist"
-	exit 1
-fi
-
-if [ $# = 1 ]; then
-	image=$1
-fi
-
-if [ x$ip = xdhcp ]; then
-	dhcp
-fi
-
-ping $eth0.serverip
-if [ $? -ne 0 ] ; then
-	echo "update aborted"
-	exit 1
-fi
-
-unprotect $part
-
-echo
-echo "erasing partition $part"
-erase $part
-
-echo
-echo "flashing $image to $part"
-echo
-tftp $image $part
diff --git a/arch/arm/boards/a9m2410/env/bin/boot b/arch/arm/boards/a9m2410/env/bin/boot
deleted file mode 100644
index 59fa60e4e9..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/boot
+++ /dev/null
@@ -1,38 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = xnand ]; then
-	root=nand
-	kernel=nand
-fi
-
-if [ x$1 = xnet ]; then
-	root=net
-	kernel=net
-fi
-
-if [ x$ip = xdhcp ]; then
-	bootargs="$bootargs ip=dhcp"
-else
-	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
-fi
-
-if [ x$root = xnand ]; then
-	bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
-else
-	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
-fi
-
-bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\""
-
-if [ x$kernel = xnet ]; then
-	if [ x$ip = xdhcp ]; then
-		dhcp
-	fi
-	tftp $uimage uImage || exit 1
-	bootm uImage
-else
-	bootm /dev/nand0.kernel.bb
-fi
-
diff --git a/arch/arm/boards/a9m2410/env/bin/init b/arch/arm/boards/a9m2410/env/bin/init
deleted file mode 100644
index dd94ef6be0..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/init
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/bin/sh
-
-PATH=/env/bin
-export PATH
-
-. /env/config
-
-if [ -e /dev/nand0 ]; then
-	addpart /dev/nand0 $nand_parts
-fi
-
-if [ -z $eth0.ethaddr ]; then
-	while [ -z $eth0.ethaddr ]; do
-		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-	done
-	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-fi
-
-echo
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
-	echo
-	echo "type update_kernel [<imagename>] to update kernel into flash"
-	echo "type update_root [<imagename>] to update rootfs into flash"
-	echo
-	exit
-fi
-
-boot
diff --git a/arch/arm/boards/a9m2410/env/bin/update_kernel b/arch/arm/boards/a9m2410/env/bin/update_kernel
deleted file mode 100644
index c43a55785b..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/update_kernel
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-part=/dev/nand0.kernel.bb
-
-if [ x$1 = x ]; then
-	image=$uimage
-else
-	image=$1
-fi
-
-. /env/bin/_update $image
diff --git a/arch/arm/boards/a9m2410/env/bin/update_root b/arch/arm/boards/a9m2410/env/bin/update_root
deleted file mode 100644
index 34139e5dce..0000000000
--- a/arch/arm/boards/a9m2410/env/bin/update_root
+++ /dev/null
@@ -1,11 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = x ]; then
-	image=$jffs2
-else
-	image=$1
-fi
-
-. /env/bin/_update $image
diff --git a/arch/arm/boards/a9m2410/env/config b/arch/arm/boards/a9m2410/env/config
deleted file mode 100644
index 2b09318934..0000000000
--- a/arch/arm/boards/a9m2410/env/config
+++ /dev/null
@@ -1,26 +0,0 @@
-#!/bin/sh
-
-# can be either 'net' or 'nand''
-kernel=net
-root=net
-
-uimage=uImage-a9m2410
-jffs2=root-a9m2410.jffs2
-
-autoboot_timeout=3
-
-nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2410/root"
-bootargs="console=ttySAC0,38400"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
-rootpart_nand="/dev/mtdblock3"
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-#ip=dhcp
-
-# or set your networking parameters here
-eth0.ipaddr=192.168.42.31
-eth0.netmask=255.255.0.0
-eth0.gateway=192.168.23.1
-eth0.serverip=192.168.23.2
-#eth0.ethaddr=
diff --git a/arch/arm/boards/a9m2410/lowlevel_init.S b/arch/arm/boards/a9m2410/lowlevel_init.S
deleted file mode 100644
index b772b1f7f0..0000000000
--- a/arch/arm/boards/a9m2410/lowlevel_init.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *
- */
-
-#include <config.h>
-#include <linux/sizes.h>
-#include <mach/s3c-iomap.h>
-#include <asm/barebox-arm-head.h>
-
-	.section ".text_bare_init.barebox_arm_reset_vector","ax"
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-
-	bl arm_cpu_lowlevel_init
-
-	bl s3c24x0_disable_wd
-
-	/* skip everything here if we are already running from SDRAM */
-	cmp pc, #S3C_SDRAM_BASE
-	blo 1f
-	cmp pc, #S3C_SDRAM_END
-	bhs 1f
-
-	b out
-
-/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
-1:
-	bl s3c24x0_pll_init
-
-	bl s3c24x0_sdram_init
-
-#ifdef CONFIG_S3C_NAND_BOOT
-/* up to here we are running from the internal SRAM area */
-	bl s3c24x0_nand_boot
-#endif
-out:
-	mov r0, #S3C_SDRAM_BASE
-	mov r1, #SZ_32M
-	mov r2, #0
-	b barebox_arm_entry
diff --git a/arch/arm/boards/a9m2440/Makefile b/arch/arm/boards/a9m2440/Makefile
deleted file mode 100644
index f21d389c14..0000000000
--- a/arch/arm/boards/a9m2440/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-
-lwl-y += lowlevel_init.o
-obj-y += a9m2440.o
-obj-$(CONFIG_MACH_A9M2410DEV) += a9m2410dev.o
diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c
deleted file mode 100644
index 627a8c6158..0000000000
--- a/arch/arm/boards/a9m2440/a9m2410dev.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Juergen Beisert
-
-/**
- * @file
- * @brief a9m2410dev Baseboad specific initialization routines
- *
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-#include "baseboards.h"
-
-/**
- * Initialize the CPU to be able to work with the a9m2410dev evaluation board
- */
-int a9m2410dev_devices_init(void)
-{
-	unsigned int reg;
-
-	/* ---------- configure the GPIOs ------------- */
-	writel(0x007FFFFF, S3C_GPACON);
-	writel(0x00000000, S3C_GPCCON);
-	writel(0x00000000, S3C_GPCUP);
-	writel(0x00000000, S3C_GPDCON);
-	writel(0x00000000, S3C_GPDUP);
-	writel(0xAAAAAAAA, S3C_GPECON);
-	writel(0x0000E03F, S3C_GPEUP);
-	writel(0x00000000, S3C_GPBCON);	/* all inputs */
-	writel(0x00000007, S3C_GPBUP);	/* pullup disabled for GPB0..3 */
-	writel(0x00009000, S3C_GPFCON);	/* GPF7 CLK_INT#, GPF6 Debug-LED */
-	writel(0x000000FF, S3C_GPFUP);
-	writel(readl(S3C_GPGDAT) | 0x1010, S3C_GPGDAT);	/* switch off IDLE_SW#, switch off LCD backlight */
-	writel(0x0100A93A, S3C_GPGCON);	/* switch on USB device */
-	writel(0x0000F000, S3C_GPGUP);
-	writel(0x0029FAAA, S3C_GPHCON);
-
-	writel((1 << 12) | (0 << 11), S3C_GPJDAT);
-	writel(0x0016aaaa, S3C_GPJCON);
-	writel(~((0<<12)| (1<<11)), S3C_GPJUP);
-
-	writel((0 << 12) | (0 << 11), S3C_GPJDAT);
-	writel(0x0016aaaa, S3C_GPJCON);
-	writel(0x00001fff, S3C_GPJUP);
-
-	writel(0x00000000, S3C_DSC0);
-	writel(0x00000000, S3C_DSC1);
-
-	/*
-	 * USB port1 normal, USB port0 normal, USB1 pads for device
-	 * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
-	 */
-	writel((readl(S3C_MISCCR) & ~0xFFFF) | 0x0140, S3C_MISCCR);
-
-	/* ----------- configure the access to the outer space ---------- */
-	reg = readl(S3C_BWSCON);
-
-	/* CS#1 to access the network controller */
-	reg &= ~0xf0;
-	reg |= 0xe0;
-	writel(0x1350, S3C_BANKCON1);
-
-	/* CS#2 to the dual 16550 UART */
-	reg &= ~0xf00;
-	reg |= 0x400;
-	writel(0x0d50, S3C_BANKCON2);
-
-	writel(reg, S3C_BWSCON);
-
-	/* release the reset signal to the network and UART device */
-	reg = readl(S3C_MISCCR);
-	reg |= 0x10000;
-	writel(reg, S3C_MISCCR);
-
-	return 0;
-}
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
deleted file mode 100644
index de18ea0120..0000000000
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ /dev/null
@@ -1,144 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <nand.h>
-#include <io.h>
-#include <mach/devices-s3c24xx.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c24xx-nand.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-#include "baseboards.h"
-
-static struct s3c24x0_nand_platform_data nand_info = {
-	.nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
-};
-
-static int a9m2440_check_for_ram(uint32_t addr)
-{
-	uint32_t tmp1, tmp2;
-	int rc = 0;
-
-	tmp1 = readl(addr);
-	tmp2 = readl(addr + sizeof(uint32_t));
-
-	writel(0xaaaaaaaa, addr);
-	writel(0x55555555, addr + sizeof(uint32_t));
-	if ((readl(addr) != 0xaaaaaaaa) || (readl(addr + sizeof(uint32_t)) != 0x55555555))
-		rc = 1;	/* seems no RAM */
-
-	writel(0x55555555, addr);
-	writel(0xaaaaaaaa, addr + sizeof(uint32_t));
-	if ((readl(addr) != 0x55555555) || (readl(addr + sizeof(uint32_t)) != 0xaaaaaaaa))
-		rc = 1;	/* seems no RAM */
-
-	writel(tmp1, addr);
-	writel(tmp2, addr + sizeof(uint32_t));
-
-	return rc;
-}
-
-static int a9m2440_mem_init(void)
-{
-	/*
-	 * The special SDRAM setup code for this machine will always enable
-	 * both SDRAM banks. But the second SDRAM device may not exists!
-	 * So we must check here, if the second bank is populated to get the
-	 * correct RAM size.
-	 */
-	switch (readl(S3C_BANKSIZE) & 0x7) {
-	case 0:
-		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 32 * 1024 * 1024))
-			s3c24xx_disable_second_sdram_bank();
-		break;
-	case 1:
-		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 64 * 1024 * 1024))
-			s3c24xx_disable_second_sdram_bank();
-		break;
-	case 2:
-		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 128 * 1024 * 1024))
-			s3c24xx_disable_second_sdram_bank();
-		break;
-	case 4:
-	case 5:
-	case 6:		/* not supported on this machine */
-		break;
-	default:
-		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 16 * 1024 * 1024))
-			s3c24xx_disable_second_sdram_bank();
-		break;
-	}
-
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());
-
-	return 0;
-}
-mem_initcall(a9m2440_mem_init);
-
-static int a9m2440_devices_init(void)
-{
-	uint32_t reg;
-
-	/* ----------- configure the access to the outer space ---------- */
-	reg = readl(S3C_BWSCON);
-
-	/* CS#5 to access the network controller */
-	reg &= ~0x00f00000;
-	reg |=  0x00d00000;	/* 16 bit */
-	writel(0x1f4c, S3C_BANKCON5);
-
-	writel(reg, S3C_BWSCON);
-
-#ifdef CONFIG_MACH_A9M2410DEV
-	a9m2410dev_devices_init();
-#endif
-
-	/* release the reset signal to external devices */
-	reg = readl(S3C_MISCCR);
-	reg |= 0x10000;
-	writel(reg, S3C_MISCCR);
-
-	/* ----------- the devices the boot loader should work with -------- */
-	s3c24xx_add_nand(&nand_info);
-	/*
-	 * cs8900 network controller onboard
-	 * Connected to CS line 5 + A24 and interrupt line EINT9,
-	 * data width is 16 bit
-	 */
-	add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL,
-			S3C_CS5_BASE + (1 << 24) + 0x300, 16, IORESOURCE_MEM, NULL);
-
-#ifdef CONFIG_NAND
-	/* ----------- add some vital partitions -------- */
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-
-	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-#endif
-	armlinux_set_architecture(MACH_TYPE_A9M2440);
-
-	return 0;
-}
-
-device_initcall(a9m2440_devices_init);
-
-static int a9m2440_console_init(void)
-{
-	barebox_set_model("Digi A9M2440");
-	barebox_set_hostname("a9m2440");
-
-	s3c24xx_add_uart1();
-	return 0;
-}
-
-console_initcall(a9m2440_console_init);
diff --git a/arch/arm/boards/a9m2440/baseboards.h b/arch/arm/boards/a9m2440/baseboards.h
deleted file mode 100644
index be4ae65e82..0000000000
--- a/arch/arm/boards/a9m2440/baseboards.h
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Juergen Beisert
-
-#ifdef CONFIG_MACH_A9M2410DEV
-extern int a9m2410dev_devices_init(void);
-#endif
diff --git a/arch/arm/boards/a9m2440/config.h b/arch/arm/boards/a9m2440/config.h
deleted file mode 100644
index c22ff53036..0000000000
--- a/arch/arm/boards/a9m2440/config.h
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/**
- * @file
- * @brief Global defintions for the ARM S3C2440 based a9m2440 CPU card
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/**
- * The external clock reference is a 16.9344 MHz crystal
- */
-#define S3C24XX_CLOCK_REFERENCE 16934400
-
-/**
- * Define the main clock configuration to be used in register CLKDIVN
- *
- * We must limit the frequency of the connected SDRAMs with the clock ratio
- * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 400Mhz:100MHz:50MHz
- */
-#define BOARD_SPECIFIC_CLKDIVN 0x05
-
-/**
- * Define the MPLL configuration to be used in register MPLLCON
- *
- * We want the MPLL to run at 399.65 MHz
- */
-#define BOARD_SPECIFIC_MPLL ((0x6e << 12) + (3 << 4) + 1)
-
-/**
- * Define the UPLL configuration to be used in register UPLLCON
- *
- * We want the UPLL to run at 47.98 MHz
- */
-#define BOARD_SPECIFIC_UPLL ((0x3c << 12) + (4 << 4) + 2)
-
-/*
- * Flash access timings
- * Tacls  = 0ns (but 20ns data setup time)
- * Twrph0 = 25ns (write) 35ns (read)
- * Twrph1 = 10ns (10ns data hold time)
- * Read cycle time = 50ns
- *
- * Assumed HCLK is 100MHz
- * Tacls = 1 (-> 20ns)
- * Twrph0 = 3 (-> 40ns)
- * Twrph1 = 1 (-> 20ns)
- * Cycle time = 80ns
- */
-#define A9M2440_TACLS 1
-#define A9M2440_TWRPH0 3
-#define A9M2440_TWRPH1 1
-
-/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C_NAND_BOOT
-# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/a9m2440/env/bin/_update b/arch/arm/boards/a9m2440/env/bin/_update
deleted file mode 100644
index b10682ece4..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/_update
+++ /dev/null
@@ -1,34 +0,0 @@
-#!/bin/sh
-
-if [ -z "$part" -o -z "$image" ]; then
-	echo "define \$part and \$image"
-	exit 1
-fi
-
-if [ ! -e "$part" ]; then
-	echo "Partition $part does not exist"
-	exit 1
-fi
-
-if [ $# = 1 ]; then
-	image=$1
-fi
-
-if [ x$ip = xdhcp ]; then
-	dhcp
-fi
-
-ping $eth0.serverip
-if [ $? -ne 0 ] ; then
-	echo "update aborted"
-	exit 1
-fi
-
-echo
-echo "erasing partition $part"
-erase $part
-
-echo
-echo "flashing $image to $part"
-echo
-tftp $image $part
diff --git a/arch/arm/boards/a9m2440/env/bin/boot b/arch/arm/boards/a9m2440/env/bin/boot
deleted file mode 100644
index 86e22cf9ff..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/boot
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = xnand ]; then
-	root=nand
-	kernel=nand
-fi
-
-if [ x$1 = xnet ]; then
-	root=net
-	kernel=net
-fi
-
-if [ x$root = xnand ]; then
-	bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
-fi
-if [ x$root = xnet ]; then
-	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
-	if [ x$ip = xdhcp ]; then
-		bootargs="$bootargs ip=dhcp"
-	else
-		bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
-	fi
-fi
-
-bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\""
-
-bootargs="$bootargs cs89x0_media=rj45 cs89x0_mac=$eth0.ethaddr"
-
-if [ x$kernel = xnet ]; then
-	if [ x$ip = xdhcp ]; then
-		dhcp
-	fi
-	tftp $uimage uImage || exit 1
-	bootm uImage
-else
-	bootm /dev/nand0.kernel.bb
-fi
-
diff --git a/arch/arm/boards/a9m2440/env/bin/init b/arch/arm/boards/a9m2440/env/bin/init
deleted file mode 100644
index dd94ef6be0..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/init
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/bin/sh
-
-PATH=/env/bin
-export PATH
-
-. /env/config
-
-if [ -e /dev/nand0 ]; then
-	addpart /dev/nand0 $nand_parts
-fi
-
-if [ -z $eth0.ethaddr ]; then
-	while [ -z $eth0.ethaddr ]; do
-		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-	done
-	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-fi
-
-echo
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
-	echo
-	echo "type update_kernel [<imagename>] to update kernel into flash"
-	echo "type update_root [<imagename>] to update rootfs into flash"
-	echo
-	exit
-fi
-
-boot
diff --git a/arch/arm/boards/a9m2440/env/bin/update_kernel b/arch/arm/boards/a9m2440/env/bin/update_kernel
deleted file mode 100644
index c43a55785b..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/update_kernel
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-part=/dev/nand0.kernel.bb
-
-if [ x$1 = x ]; then
-	image=$uimage
-else
-	image=$1
-fi
-
-. /env/bin/_update $image
diff --git a/arch/arm/boards/a9m2440/env/bin/update_root b/arch/arm/boards/a9m2440/env/bin/update_root
deleted file mode 100644
index 46cbca5beb..0000000000
--- a/arch/arm/boards/a9m2440/env/bin/update_root
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-part=/dev/nand0.root.bb
-
-if [ x$1 = x ]; then
-	image=$jffs2
-else
-	image=$1
-fi
-
-. /env/bin/_update $image
diff --git a/arch/arm/boards/a9m2440/env/config b/arch/arm/boards/a9m2440/env/config
deleted file mode 100644
index d1fb01b731..0000000000
--- a/arch/arm/boards/a9m2440/env/config
+++ /dev/null
@@ -1,26 +0,0 @@
-#!/bin/sh
-
-# can be either 'net' or 'nand''
-kernel=net
-root=net
-
-uimage=uImage-a9m2440
-jffs2=root-a9m2440.jffs2
-
-autoboot_timeout=3
-
-nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2440/root"
-bootargs="console=ttySAC0,38400"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
-rootpart_nand="/dev/mtdblock3"
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-#ip=dhcp
-
-# or set your networking parameters here
-eth0.ipaddr=192.168.42.32
-eth0.netmask=255.255.0.0
-eth0.gateway=192.168.23.1
-eth0.serverip=192.168.23.2
-#eth0.ethaddr=
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
deleted file mode 100644
index 2c51e05806..0000000000
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- *
- */
-
-#include <config.h>
-#include <linux/sizes.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c24xx-gpio.h>
-#include <asm/barebox-arm-head.h>
-
-	.section ".text_bare_init.barebox_arm_reset_vector","ax"
-
-/*
- * To be able to setup the SDRAM interface correctly, we need some
- * external information about the connected SDRAM devices.
- *
- * When we set GPH8, we can read at GPB:
- * Bit 0..1: Memory device size -> 00=16M, 01=64M, 10=32M, 11=128M
- * Bit 2: CL setting
- *
- * Some remarks: The CL setting seems useless. It always signals a CL3
- * requirement, but the SDRAM types I found on the cards are supporting
- * CL2 @ 100 MHz. But also these SDRAM types are only support 105 MHz max.
- * So, we never need CL3 because we can't run the CPU at 533 MHz (which
- * implies an 133 MHz SDRAM clock).
- * All devices are connected via 32 bit databus
- *
- * Note: I was able to check the 32 MiB and 64 MiB configuration only. I didn't
- * had access to a 16 MiB nor 128 MiB config.
- *
- */
-
-sdram_init:
-	/*
-	 * Read the configuration. After reset until any GPIO port is
-	 * configured yet, these pins show external settings, to detect
-	 * the SDRAM size.
-	 */
-	ldr r1, =S3C_GPBDAT
-	ldr r4, [r1]
-	and r4, r4, #0x3
-
-	ldr r1, =S3C_MEMCTL_BASE
-	/* configure both SDRAM areas with 32 bit data bus width */
-	ldr r0, =((0x2 << 24) + (0x2 << 28))
-	str r0, [r1], #0x1c	/* post add register offset for bank6 */
-
-	/*
-	 * With the configuration we simply need to calculate an offset into
-	 * our table with the predefined SDRAM settings
-	 */
-	adr r0, SDRAMDATA
-	mov r2, #6*4		/* # of bytes per table entry */
-	mul r3, r4, r2
-	add r0, r0, r3		/* start address of the entry */
-
-	/*
-	 * store the table entry data into the registers
-	 */
-1:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	subs    r2, r2, #4
-	bne     1b
-
-/* TODO: Check if the second bank is populated, and switch it off if not */
-
-	mov pc, lr
-
-/*
- * we need 4 sets of memory settings per main CPU clock speed
- *
- * 400MHz main speed:
- * - 16 MiB in the first bank, maybe 16 MiB in the second bank (untested!)
- * - 32 MiB in the first bank, maybe 32 MiB in the second bank (CL=2)
- * - 64 MiB in the first bank, maybe 64 MiB in the second bank (CL=2)
- * - 128 MiB in the first bank, maybe 128 MiB in the second bank (untested!)
- *
- * Note: SDRAM clock runs at 100MHz
- */
-
-SDRAMDATA:
-/* --------------------------- 16 MiB @ 100MHz --------------------------- */
-	/*
-	 *  - MT = 11 (= sync dram type)
-	 *  - Trcd = 01 (= CL3)
-	 *  - SCAN = 00 (= 8 bit columns)
-	 */
-	.word ((0x3 << 15) + (0x1 << 2) + (0x0))
-	.word ((0x3 << 15) + (0x1 << 2) + (0x0))
-	/*
-	 * SDRAM refresh settings
-	 *  - REFEN = 1 (= refresh enabled)
-	 *  - TREFMD = 0 (= auto refresh)
-	 *  - Trp = 00 (= 2 RAS precharge clocks)
-	 *  - Tsrc = 11 (= 7 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
-	 *  - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = FIXME
-	 */
-	.word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x3 << 18) + 468)
-	/*
-	 * SDRAM banksize
-	 *  - BURST_EN = 0 (= burst mode disabled)
-	 *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
-	 *  - SCLK_EN = 1 (= clock active only during accesses)
-	 *  - BK67MAP = 010 (= 128MiB) FIXME?????
-	 */
-	.word ((0 << 7) + (1 << 5) + (1 << 4) + 2)
-	/*
-	 * SDRAM mode register
-	 * CL = 010 (= 2 clocks)
-	 */
-	.word (0x2 << 4)
-	.word (0x2 << 4)
-
-/* ------------- one or two banks with 64 MiB @ 100MHz -------------------- */
-
-	/*
-	 *  - MT = 11 (= sync dram type)
-	 *  - Trcd = 00 (= CL2)
-	 *  - SCAN = 01 (= 9 bit columns)
-	 */
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	/*
-	 * SDRAM refresh settings
-	 *  - REFEN = 1 (= refresh enabled)
-	 *  - TREFMD = 0 (= auto refresh)
-	 *  - Trp = 00 (= 2 RAS precharge clocks)
-	 *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
-	 *  - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
-	 */
-	.word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
-	/*
-	 * SDRAM banksize
-	 *  - BURST_EN = 1 (= burst mode enabled)
-	 *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
-	 *  - SCLK_EN = 1 (= clock active only during accesses)
-	 *  - BK67MAP = 001 (= 64 MiB)
-	 */
-	.word ((1 << 7) + (1 << 5) + (1 << 4) + 1)
-	/*
-	 * SDRAM mode register
-	 * CL = 010 (= 2 clocks)
-	 */
-	.word (0x2 << 4)
-	.word (0x2 << 4)
-
-/* ------------- one or two banks with 32 MiB @ 100MHz -------------------- */
-
-	/*
-	 *  - MT = 11 (= sync dram type)
-	 *  - Trcd = 00 (= CL2)
-	 *  - SCAN = 01 (= 9 bit columns)
-	 */
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	/*
-	 * SDRAM refresh settings
-	 *  - REFEN = 1 (= refresh enabled)
-	 *  - TREFMD = 0 (= auto refresh)
-	 *  - Trp = 00 (= 2 RAS precharge clocks)
-	 *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
-	 *  - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
-	 */
-	.word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
-	/*
-	 * SDRAM banksize
-	 *  - BURST_EN = 1 (= burst mode enabled)
-	 *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
-	 *  - SCLK_EN = 1 (= clock active only during accesses)
-	 *  - BK67MAP = 000 (= 32 MiB)
-	 */
-	.word ((1 << 7) + (1 << 5) + (1 << 4) + 0)
-	/*
-	 * SDRAM mode register
-	 * CL = 010 (= 2 clocks)
-	 */
-	.word (0x2 << 4)
-	.word (0x2 << 4)
-
-/* ------------ one or two banks with 128 MiB @ 100MHz -------------------- */
-
-	/*
-	 *  - MT = 11 (= sync dram type)
-	 *  - Trcd = 00 (= CL2)
-	 *  - SCAN = 01 (= 9 bit columns)
-	 */
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	.word ((0x3 << 15) + (0x0 << 2) + (0x1))
-	/*
-	 * SDRAM refresh settings
-	 *  - REFEN = 1 (= refresh enabled)
-	 *  - TREFMD = 0 (= auto refresh)
-	 *  - Trp = 00 (= 2 RAS precharge clocks)
-	 *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
-	 *  - Refrsh = 2^11 + 1 - 100 * 7.5 = 2049 - FIXME = 1259
-	 */
-	.word ((0x1 << 23) + (0x0 << 22) + (0x1 << 20) + (0x3 << 18) + 1259)
-	/*
-	 * SDRAM banksize
-	 *  - BURST_EN = 0 (= burst mode disabled)
-	 *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
-	 *  - SCLK_EN = 1 (= clock active only during accesses)
-	 *  - BK67MAP = 010 (= 128MiB)
-	 */
-	.word (0x32)
-	/*
-	 * SDRAM mode register
-	 * CL = 010 (= 2 clocks)
-	 */
-	.word (0x2 << 4)
-	.word (0x2 << 4)
-
-/* ------------------------------------------------------------------------ */
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-
-	bl arm_cpu_lowlevel_init
-
-	bl s3c24x0_disable_wd
-
-	/* skip everything here if we are already running from SDRAM */
-	cmp pc, #S3C_SDRAM_BASE
-	blo 1f
-	cmp pc, #S3C_SDRAM_END
-	bhs 1f
-
-	b out
-
-/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
-1:
-	bl s3c24x0_pll_init
-
-	bl sdram_init
-
-#ifdef CONFIG_S3C_NAND_BOOT
-/* up to here we are running from the internal SRAM area */
-	bl s3c24x0_nand_boot
-#endif
-out:
-	mov r0, #S3C_SDRAM_BASE
-	mov r1, #SZ_32M
-	mov r2, #0
-	b barebox_arm_entry
diff --git a/arch/arm/boards/ac-sxb/Makefile b/arch/arm/boards/ac-sxb/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/ac-sxb/Makefile
+++ b/arch/arm/boards/ac-sxb/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/ac-sxb/board.c b/arch/arm/boards/ac-sxb/board.c
index 3ea40dfb7d..d631bb543a 100644
--- a/arch/arm/boards/ac-sxb/board.c
+++ b/arch/arm/boards/ac-sxb/board.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
 static int sxb_coredevices_init(void)
 {
diff --git a/arch/arm/boards/ac-sxb/lowlevel.c b/arch/arm/boards/ac-sxb/lowlevel.c
index a910555f9b..713d8ce5f8 100644
--- a/arch/arm/boards/ac-sxb/lowlevel.c
+++ b/arch/arm/boards/ac-sxb/lowlevel.c
@@ -5,19 +5,20 @@
  */
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <io.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx7-ccm-regs.h>
-#include <mach/iomux-mx7.h>
-#include <mach/debug_ll.h>
+#include <mach/imx/imx7-ccm-regs.h>
+#include <mach/imx/iomux-mx7.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
-#include <mach/esdctl.h>
-#include <mach/xload.h>
-#include <mach/imx7-ddr-regs.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/imx7-ddr-regs.h>
 
 struct reginit {
 	u32 address;
@@ -93,7 +94,7 @@ extern char __dtb_z_ac_sxb_start[];
 
 static inline void setup_uart(void)
 {
-	imx7_early_setup_uart_clock();
+	imx7_early_setup_uart_clock(1);
 
 	imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX);
 
diff --git a/arch/arm/boards/advantech-mx6/Makefile b/arch/arm/boards/advantech-mx6/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/advantech-mx6/Makefile
+++ b/arch/arm/boards/advantech-mx6/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/advantech-mx6/board.c b/arch/arm/boards/advantech-mx6/board.c
index 67149d8994..8261875d63 100644
--- a/arch/arm/boards/advantech-mx6/board.c
+++ b/arch/arm/boards/advantech-mx6/board.c
@@ -5,7 +5,7 @@
 #include <init.h>
 #include <platform_data/eth-fec.h>
 #include <bootsource.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
 static int ar8035_phy_fixup(struct phy_device *dev)
 {
diff --git a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg
index aefdf68e89..91a8babafd 100644
--- a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg
+++ b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
diff --git a/arch/arm/boards/advantech-mx6/lowlevel.c b/arch/arm/boards/advantech-mx6/lowlevel.c
index d762f0e9a7..edd5971c35 100644
--- a/arch/arm/boards/advantech-mx6/lowlevel.c
+++ b/arch/arm/boards/advantech-mx6/lowlevel.c
@@ -2,13 +2,14 @@
 // SPDX-FileCopyrightText: 2018 Christoph Fritz <chf.fritz@googlemail.com>
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <image-metadata.h>
-#include <mach/generic.h>
-#include <mach/esdctl.h>
-#include <mach/iomux-mx6.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/iomux-mx6.h>
 #include <linux/sizes.h>
 
 static inline void setup_uart(void)
diff --git a/arch/arm/boards/afi-gf/Makefile b/arch/arm/boards/afi-gf/Makefile
index 399a4b8cc0..8d1041650e 100644
--- a/arch/arm/boards/afi-gf/Makefile
+++ b/arch/arm/boards/afi-gf/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
 bbenv-y += defaultenv-gf
diff --git a/arch/arm/boards/afi-gf/board.c b/arch/arm/boards/afi-gf/board.c
index 53d3b67008..66288ca5b7 100644
--- a/arch/arm/boards/afi-gf/board.c
+++ b/arch/arm/boards/afi-gf/board.c
@@ -8,8 +8,8 @@
 #include <envfs.h>
 #include <bootsource.h>
 #include <asm/armlinux.h>
-#include <mach/bbu.h>
-#include <mach/am33xx-generic.h>
+#include <mach/omap/bbu.h>
+#include <mach/omap/am33xx-generic.h>
 
 static int board_console_init(void)
 {
diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c
index da4a000675..5c38198a36 100644
--- a/arch/arm/boards/afi-gf/lowlevel.c
+++ b/arch/arm/boards/afi-gf/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <init.h>
 #include <linux/sizes.h>
 #include <io.h>
@@ -5,15 +7,17 @@
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <linux/bitops.h>
-#include <mach/am33xx-generic.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/am33xx-clock.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/am33xx-mux.h>
-#include <mach/wdt.h>
+#include <mach/omap/am33xx-generic.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/am33xx-clock.h>
+#include <mach/omap/emif4.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/am33xx-mux.h>
 #include <debug_ll.h>
+#include <mach/omap/debug_ll.h>
 
 /* AM335X EMIF Register values */
 #define	VTP_CTRL_READY		(0x1 << 5)
@@ -128,34 +132,35 @@ static void board_config_vtp(void)
 
 static void board_config_emif_ddr(void)
 {
+	const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE);
 	u32 i;
 
 	/*Program EMIF0 CFG Registers*/
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
-
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+	__raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1);
+	__raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW);
+	__raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_2);
+	__raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1);
+	__raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW);
+	__raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2);
+	__raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW);
+	__raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3);
+	__raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW);
+
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG);
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2);
+
+	__raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL);
+	__raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
 
 	for (i = 0; i < 5000; i++) {
 
 	}
 
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+	__raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL);
+	__raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
 
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG);
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2);
 }
 
 static void board_config_ddr(void)
@@ -207,13 +212,7 @@ static noinline int gf_sram_init(void)
 
 	fdt = __dtb_z_am335x_afi_gf_start;
 
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
 
 	/* Setup the PLLs and the clocks for the peripherals */
 	am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_200);
@@ -228,7 +227,7 @@ static noinline int gf_sram_init(void)
 
 	am33xx_uart_soft_reset((void *)AM33XX_UART2_BASE);
 	am33xx_enable_uart2_pin_mux();
-	omap_uart_lowlevel_init((void *)AM33XX_UART2_BASE);
+	omap_debug_ll_init();
 	putc_ll('>');
 
 	barebox_arm_entry(0x80000000, SZ_256M, fdt);
diff --git a/arch/arm/boards/altera-socdk/Makefile b/arch/arm/boards/altera-socdk/Makefile
index 8c927fe291..ea898309d7 100644
--- a/arch/arm/boards/altera-socdk/Makefile
+++ b/arch/arm/boards/altera-socdk/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += lowlevel.o board.o
 pbl-y += lowlevel.o
diff --git a/arch/arm/boards/altera-socdk/board.c b/arch/arm/boards/altera-socdk/board.c
index f4b1dcd324..bf0a5664fe 100644
--- a/arch/arm/boards/altera-socdk/board.c
+++ b/arch/arm/boards/altera-socdk/board.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <types.h>
 #include <driver.h>
@@ -8,7 +10,7 @@
 #include <linux/sizes.h>
 #include <fcntl.h>
 #include <fs.h>
-#include <mach/cyclone5-regs.h>
+#include <mach/socfpga/cyclone5-regs.h>
 
 static int ksz9021rn_phy_fixup(struct phy_device *dev)
 {
diff --git a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
index 9777d15dfe..982bef52bf 100644
--- a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <mach/cyclone5-scan-manager.h>
+#include <mach/socfpga/cyclone5-scan-manager.h>
 
 static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]
     = {
diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c
index 822c3d8ee6..1e62ab70e7 100644
--- a/arch/arm/boards/altera-socdk/lowlevel.c
+++ b/arch/arm/boards/altera-socdk/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include "sdram_config.h"
 #include "pinmux_config.c"
 #include "pll_config.h"
@@ -7,7 +9,7 @@
 #include "sequencer_auto_ac_init.c"
 #include "iocsr_config_cyclone5.c"
 
-#include <mach/lowlevel.h>
+#include <mach/socfpga/lowlevel.h>
 
 SOCFPGA_C5_ENTRY(start_socfpga_socdk, socfpga_cyclone5_socdk, SZ_1G);
 SOCFPGA_C5_XLOAD_ENTRY(start_socfpga_socdk_xload, SZ_1G);
diff --git a/arch/arm/boards/animeo_ip/Makefile b/arch/arm/boards/animeo_ip/Makefile
index 61c714b45d..149c41024a 100644
--- a/arch/arm/boards/animeo_ip/Makefile
+++ b/arch/arm/boards/animeo_ip/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c
index ed0b9b7f87..452e005046 100644
--- a/arch/arm/boards/animeo_ip/init.c
+++ b/arch/arm/boards/animeo_ip/init.c
@@ -9,24 +9,23 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/clk.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
 #include <local_mac_address.h>
 
 static bool animeo_ip_is_buco;
@@ -56,7 +55,7 @@ static int animeo_ip_get_pio_revision(int gpio, char *name)
 
 static void animeo_ip_detect_version(void)
 {
-	struct device_d *dev = NULL;
+	struct device *dev = NULL;
 	char *model, *version;
 	int val;
 
@@ -312,7 +311,7 @@ static int animeo_ip_devices_init(void)
 
 device_initcall(animeo_ip_devices_init);
 
-static struct device_d *usart0, *usart1;
+static struct device *usart0, *usart1;
 
 static void animeo_ip_shutdown_uart(void __iomem *base)
 {
diff --git a/arch/arm/boards/animeo_ip/lowlevel.c b/arch/arm/boards/animeo_ip/lowlevel.c
index 7f52f824df..df02e834c3 100644
--- a/arch/arm/boards/animeo_ip/lowlevel.c
+++ b/arch/arm/boards/animeo_ip/lowlevel.c
@@ -7,14 +7,13 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
 
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9260.h>
-#include <mach/hardware.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9260.h>
+#include <mach/at91/hardware.h>
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_animeo_ip, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/archosg9/Makefile b/arch/arm/boards/archosg9/Makefile
index a78956f4e4..790ff623f5 100644
--- a/arch/arm/boards/archosg9/Makefile
+++ b/arch/arm/boards/archosg9/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 obj-$(CONFIG_ARM_BOARD_APPEND_ATAG) += archos_features.o
 lwl-y += lowlevel.o mux.o
diff --git a/arch/arm/boards/archosg9/archos_features.h b/arch/arm/boards/archosg9/archos_features.h
index 5769c6c668..f46b9e9eb8 100644
--- a/arch/arm/boards/archosg9/archos_features.h
+++ b/arch/arm/boards/archosg9/archos_features.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ARCHOS_FEATURES_H
 #define __ARCHOS_FEATURES_H
 
diff --git a/arch/arm/boards/archosg9/board.c b/arch/arm/boards/archosg9/board.c
index 3289cfda3d..fbf05a4408 100644
--- a/arch/arm/boards/archosg9/board.c
+++ b/arch/arm/boards/archosg9/board.c
@@ -4,11 +4,11 @@
 #include <clock.h>
 #include <init.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-devices.h>
-#include <mach/omap4_rom_usb.h>
-#include <mach/omap-fb.h>
+#include <asm/mach-types.h>
+#include <mach/omap/devices.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-devices.h>
+#include <mach/omap/omap4_rom_usb.h>
 #include <linux/sizes.h>
 #include <i2c/i2c.h>
 #include <gpio.h>
@@ -33,13 +33,17 @@
 
 static int archosg9_console_init(void)
 {
+	int ret;
+
 	barebox_set_model("Archos G9");
 	barebox_set_hostname("g9");
 
-	if (IS_ENABLED(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT) &&
-			omap4_usbboot_ready()) {
-		add_generic_device("serial_omap4_usbboot", DEVICE_ID_DYNAMIC
-			, NULL, 0, 0, 0, NULL);
+	if (IS_ENABLED(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)) {
+		ret = omap4_usbboot_open();
+		if (!ret) {
+			add_generic_device("serial_omap4_usbboot", DEVICE_ID_DYNAMIC
+				, NULL, 0, 0, 0, NULL);
+		}
 	}
 	if (IS_ENABLED(CONFIG_DRIVER_SERIAL_NS16550)) {
 		omap44xx_add_uart1();
diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
index f31ef1a7f2..2c3d0e1ee4 100644
--- a/arch/arm/boards/archosg9/lowlevel.c
+++ b/arch/arm/boards/archosg9/lowlevel.c
@@ -4,12 +4,12 @@
 #include <io.h>
 #include <init.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
-#include <mach/omap4-mux.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-generic.h>
-#include <mach/omap4-clock.h>
-#include <mach/syslib.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/omap4-mux.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-generic.h>
+#include <mach/omap/omap4-clock.h>
+#include <mach/omap/syslib.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
 #include "mux.h"
diff --git a/arch/arm/boards/archosg9/mux.c b/arch/arm/boards/archosg9/mux.c
index dc85271208..d51ccefba4 100644
--- a/arch/arm/boards/archosg9/mux.c
+++ b/arch/arm/boards/archosg9/mux.c
@@ -3,9 +3,9 @@
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-mux.h>
-#include <mach/omap4-clock.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-mux.h>
+#include <mach/omap/omap4-clock.h>
 #include "mux.h"
 
 static const struct pad_conf_entry core_padconf_array[] = {
diff --git a/arch/arm/boards/archosg9/mux.h b/arch/arm/boards/archosg9/mux.h
index 4ee5415871..d4b0c9da86 100644
--- a/arch/arm/boards/archosg9/mux.h
+++ b/arch/arm/boards/archosg9/mux.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef _MUX_H
 #define _MUX_H
 
diff --git a/arch/arm/boards/at91rm9200ek/Makefile b/arch/arm/boards/at91rm9200ek/Makefile
index a07c06a6d9..da5c1038b2 100644
--- a/arch/arm/boards/at91rm9200ek/Makefile
+++ b/arch/arm/boards/at91rm9200ek/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/at91rm9200ek/config.h b/arch/arm/boards/at91rm9200ek/config.h
index 5f4f6fe1ae..a3a0be18ec 100644
--- a/arch/arm/boards/at91rm9200ek/config.h
+++ b/arch/arm/boards/at91rm9200ek/config.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c
index 8c61a72e0b..49a227805a 100644
--- a/arch/arm/boards/at91rm9200ek/init.c
+++ b/arch/arm/boards/at91rm9200ek/init.c
@@ -6,18 +6,17 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <gpio.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
 #include <linux/sizes.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
 #include <spi/spi.h>
 
 static struct macb_platform_data ether_pdata = {
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c
index b132ccc084..f412de7d4a 100644
--- a/arch/arm/boards/at91rm9200ek/lowlevel.c
+++ b/arch/arm/boards/at91rm9200ek/lowlevel.c
@@ -7,21 +7,22 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
 
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91rm9200.h>
-#include <mach/at91_pio.h>
-#include <mach/at91_pmc.h>
-#include <mach/hardware.h>
+#include <mach/at91/at91rm9200_mc.h>
+#include <mach/at91/at91rm9200.h>
+#include <mach/at91/at91_pio.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/hardware.h>
+
+#include "config.h"
 
 void static inline access_sdram(void)
 {
 	writel(0x00000000, AT91_CHIPSELECT_1);
 }
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_at91rm9200ek, r0, r1, r2)
 {
 	u32 r;
 	int i;
diff --git a/arch/arm/boards/at91sam9260ek/Makefile b/arch/arm/boards/at91sam9260ek/Makefile
index 9cc933a287..7aa83a7736 100644
--- a/arch/arm/boards/at91sam9260ek/Makefile
+++ b/arch/arm/boards/at91sam9260ek/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c
index 92526c072a..eab3649883 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -6,16 +6,16 @@
 #include <envfs.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <nand.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/sizes.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_rstc.h>
 #include <linux/clk.h>
 
 /*
diff --git a/arch/arm/boards/at91sam9260ek/lowlevel.c b/arch/arm/boards/at91sam9260ek/lowlevel.c
index 7f52f824df..c574e4aeb0 100644
--- a/arch/arm/boards/at91sam9260ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9260ek/lowlevel.c
@@ -7,14 +7,24 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
 
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9260.h>
-#include <mach/hardware.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9260.h>
+#include <mach/at91/hardware.h>
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_at91sam9260ek, r0, r1, r2)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}
+
+AT91_ENTRY_FUNCTION(start_at91sam9g20ek, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/at91sam9261ek/Makefile b/arch/arm/boards/at91sam9261ek/Makefile
index e7a9cde419..91e0037d6d 100644
--- a/arch/arm/boards/at91sam9261ek/Makefile
+++ b/arch/arm/boards/at91sam9261ek/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel_init.o
diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c
index 3904cbf9ca..da305fe9ed 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -7,21 +7,20 @@
 #include <envfs.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <platform_data/eth-dm9000.h>
 #include <gpio_keys.h>
 #include <readkey.h>
diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c
index bb9b905c65..55393567ea 100644
--- a/arch/arm/boards/at91sam9261ek/lowlevel_init.c
+++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c
@@ -4,10 +4,9 @@
  * Under GPLv2
  */
 
-#include <asm/barebox-arm.h>
-
-#include <mach/at91sam926x_board_init.h>
-#include <mach/at91sam9261_matrix.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam926x_board_init.h>
+#include <mach/at91/at91sam9261_matrix.h>
 
 #define MASTER_CLOCK		200
 
@@ -117,7 +116,16 @@ static void __bare_init at91sam9261ek_init(void)
 	                  NULL);
 }
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_at91sam9261ek, r0, r1, r2)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE);
+
+	at91sam9261ek_init();
+}
+
+AT91_ENTRY_FUNCTION(start_at91sam9g10ek, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile
index d4d5e76395..7f4c1bfac3 100644
--- a/arch/arm/boards/at91sam9263ek/Makefile
+++ b/arch/arm/boards/at91sam9263ek/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_OFDEVICE),)
 obj-y += init.o
 endif
diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c
index bf2f1e8f9a..6b618e9d00 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -8,20 +8,19 @@
 #include <envfs.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
 #include <gpio.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/at91sam9_smc.h>
 
 static struct atmel_nand_data nand_pdata = {
 	.ale		= 21,
diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
index 0bf0e0fb4e..aea772c743 100644
--- a/arch/arm/boards/at91sam9263ek/lowlevel_init.c
+++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
@@ -6,10 +6,9 @@
 
 #include <linux/sizes.h>
 
-#include <asm/barebox-arm.h>
-
-#include <mach/at91sam926x_board_init.h>
-#include <mach/at91sam9263_matrix.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam926x_board_init.h>
+#include <mach/at91/at91sam9263_matrix.h>
 
 #define MASTER_PLL_MUL		171
 #define MASTER_PLL_DIV		14
@@ -117,7 +116,7 @@ static void __bare_init at91sam9263ek_init(void *fdt)
 
 extern char __dtb_z_at91sam9263ek_start[];
 
-ENTRY_FUNCTION(start_at91sam9263ek, r0, r1, r2)
+AT91_ENTRY_FUNCTION(start_at91sam9263ek, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/at91sam9263ek/of_init.c b/arch/arm/boards/at91sam9263ek/of_init.c
index 3cb2fe22c9..7bdc6cc0f0 100644
--- a/arch/arm/boards/at91sam9263ek/of_init.c
+++ b/arch/arm/boards/at91sam9263ek/of_init.c
@@ -7,14 +7,17 @@
 #include <gpio.h>
 #include <io.h>
 
-#include <mach/at91sam9263_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_rtt.h>
-#include <mach/hardware.h>
-#include <mach/iomux.h>
+#include <mach/at91/at91sam9263_matrix.h>
+#include <mach/at91/at91sam9_smc.h>
+#include <mach/at91/at91_rtt.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/iomux.h>
 
 static int add_smc_devices(void)
 {
+	if (!of_machine_is_compatible("atmel,at91sam9263ek"))
+		return 0;
+
 	add_generic_device("at91sam9-smc", 0, NULL, AT91SAM9263_BASE_SMC0, 0x200,
 			   IORESOURCE_MEM, NULL);
 	add_generic_device("at91sam9-smc", 1, NULL, AT91SAM9263_BASE_SMC1, 0x200,
diff --git a/arch/arm/boards/at91sam9m10g45ek/Makefile b/arch/arm/boards/at91sam9m10g45ek/Makefile
index da011f825b..291716cbf0 100644
--- a/arch/arm/boards/at91sam9m10g45ek/Makefile
+++ b/arch/arm/boards/at91sam9m10g45ek/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c
index dcb8f9b17f..821228c2e1 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -10,20 +10,19 @@
 #include <envfs.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio_keys.h>
 #include <readkey.h>
 #include <spi/spi.h>
diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
index 755e7ec029..a24b26e5cb 100644
--- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
@@ -7,13 +7,11 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_ddrsdrc.h>
 
-#include <mach/hardware.h>
-#include <mach/at91_ddrsdrc.h>
-
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_at91sam9m10g45ek, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/at91sam9m10ihd/Makefile b/arch/arm/boards/at91sam9m10ihd/Makefile
index 06193007ad..8bf9a102fe 100644
--- a/arch/arm/boards/at91sam9m10ihd/Makefile
+++ b/arch/arm/boards/at91sam9m10ihd/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 obj-y += hw_version.o
 
diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.c b/arch/arm/boards/at91sam9m10ihd/hw_version.c
index 1387c13718..0b8b7cc884 100644
--- a/arch/arm/boards/at91sam9m10ihd/hw_version.c
+++ b/arch/arm/boards/at91sam9m10ihd/hw_version.c
@@ -133,7 +133,7 @@ static void at91sam9m10ihd_devices_detect_one(const char *name)
 	struct one_wire_info info;
 	struct board_info* binfo;
 	struct vendor_info* vinfo;
-	struct device_d *dev = NULL;
+	struct device *dev = NULL;
 	char str[16];
 	u8 vendor_id = 0;
 
diff --git a/arch/arm/boards/at91sam9m10ihd/init.c b/arch/arm/boards/at91sam9m10ihd/init.c
index e629900d5a..763dffb6ce 100644
--- a/arch/arm/boards/at91sam9m10ihd/init.c
+++ b/arch/arm/boards/at91sam9m10ihd/init.c
@@ -10,20 +10,19 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/board.h>
+#include <mach/at91/board.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <input/qt1070.h>
 #include <readkey.h>
 #include <linux/w1-gpio.h>
diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
index 817c7548c9..7eba24f3e4 100644
--- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
@@ -7,14 +7,12 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/at91sam9g45.h>
+#include <mach/at91/hardware.h>
 
-#include <mach/at91_ddrsdrc.h>
-#include <mach/at91sam9g45.h>
-#include <mach/hardware.h>
-
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_at91sam9m10ihd, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/at91sam9n12ek/Makefile b/arch/arm/boards/at91sam9n12ek/Makefile
index 458b055918..6ba8b4e38f 100644
--- a/arch/arm/boards/at91sam9n12ek/Makefile
+++ b/arch/arm/boards/at91sam9n12ek/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c
index edc45819b2..4503e96af9 100644
--- a/arch/arm/boards/at91sam9n12ek/init.c
+++ b/arch/arm/boards/at91sam9n12ek/init.c
@@ -6,24 +6,23 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91sam9x5_matrix.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
+#include <mach/at91/at91sam9x5_matrix.h>
 #include <input/qt1070.h>
 #include <readkey.h>
 #include <spi/spi.h>
diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c b/arch/arm/boards/at91sam9n12ek/lowlevel.c
index 4353555d0d..4b981fd49f 100644
--- a/arch/arm/boards/at91sam9n12ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c
@@ -7,13 +7,11 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/hardware.h>
 
-#include <mach/at91_ddrsdrc.h>
-#include <mach/hardware.h>
-
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_at91sam9n12ek, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/at91sam9x5ek/Makefile b/arch/arm/boards/at91sam9x5ek/Makefile
index 4939b7e17e..c6c1ad9670 100644
--- a/arch/arm/boards/at91sam9x5ek/Makefile
+++ b/arch/arm/boards/at91sam9x5ek/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 obj-y += hw_version.o
 bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-at91sam9x5ek
diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.c b/arch/arm/boards/at91sam9x5ek/hw_version.c
index 4038f42ec2..1224f4753c 100644
--- a/arch/arm/boards/at91sam9x5ek/hw_version.c
+++ b/arch/arm/boards/at91sam9x5ek/hw_version.c
@@ -149,7 +149,7 @@ static void at91sam9x5ek_devices_detect_one(const char *name)
 	struct one_wire_info info;
 	struct board_info* binfo;
 	struct vendor_info* vinfo;
-	struct device_d *dev = NULL;
+	struct device *dev = NULL;
 	char str[16];
 	u8 vendor_id = 0;
 
diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c
index a1c80bf441..c3d0f2ce89 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -6,23 +6,22 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91sam9x5_matrix.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
+#include <mach/at91/at91sam9x5_matrix.h>
 #include <input/qt1070.h>
 #include <readkey.h>
 #include <linux/w1-gpio.h>
diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c b/arch/arm/boards/at91sam9x5ek/lowlevel.c
index ebd417b19c..5dbac307ac 100644
--- a/arch/arm/boards/at91sam9x5ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c
@@ -1,14 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/at91_ddrsdrc.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/barebox-arm.h>
 #include <io.h>
 #include <debug_ll.h>
 
 extern char __dtb_z_at91sam9x5ek_start[];
 
-ENTRY_FUNCTION(start_at91sam9x5ek, r0, r1, r2)
+AT91_ENTRY_FUNCTION(start_at91sam9x5ek, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/avnet-zedboard/Makefile b/arch/arm/boards/avnet-zedboard/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/avnet-zedboard/Makefile
+++ b/arch/arm/boards/avnet-zedboard/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/avnet-zedboard/board.c b/arch/arm/boards/avnet-zedboard/board.c
index b8396d1996..15332189ca 100644
--- a/arch/arm/boards/avnet-zedboard/board.c
+++ b/arch/arm/boards/avnet-zedboard/board.c
@@ -4,9 +4,9 @@
 #include <asm/armlinux.h>
 #include <common.h>
 #include <environment.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <init.h>
-#include <mach/zynq7000-regs.h>
+#include <mach/zynq/zynq7000-regs.h>
 #include <linux/sizes.h>
 
 
diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c
index f7bdceb42a..6e5a17d7ef 100644
--- a/arch/arm/boards/avnet-zedboard/lowlevel.c
+++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
@@ -5,8 +5,8 @@
 #include <io.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
-#include <mach/init.h>
-#include <mach/zynq7000-regs.h>
+#include <mach/zynq/init.h>
+#include <mach/zynq/zynq7000-regs.h>
 #include <serial/cadence.h>
 
 #define DCI_DONE	(1 << 13)
@@ -14,7 +14,7 @@
 #define PLL_DDR_LOCK	(1 << 1)
 #define PLL_IO_LOCK	(1 << 2)
 
-extern char __dtb_zynq_zed_start[];
+extern char __dtb_z_zynq_zed_start[];
 
 static void avnet_zedboard_ps7_init(void)
 {
@@ -289,7 +289,7 @@ static void avnet_zedboard_pbl_console_init(void)
 ENTRY_FUNCTION(start_avnet_zedboard, r0, r1, r2)
 {
 
-	void *fdt = __dtb_zynq_zed_start + get_runtime_offset();
+	void *fdt = __dtb_z_zynq_zed_start + get_runtime_offset();
 
 	/* MIO_07 in GPIO Mode 3.3V VIO, can be uncomented because it is the default value */
 	writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK);
diff --git a/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg b/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg
index 3f8808d3d7..c6a96aec7b 100644
--- a/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg
+++ b/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg
@@ -1,4 +1,4 @@
-#include <mach/zynq7000-header-regs.h>
+#include <zynq/zynq7000-header-regs.h>
 
 wm 32 ZYNQ_SLCR_UNLOCK		0x0000DF0D
 wm 32 ZYNQ_CLK_621_TRUE		0x00000001
@@ -21,4 +21,4 @@ wm 32 ZYNQ_IO_PLL_CTRL		0x0001E000
 wm 32 ZYNQ_SDIO_CLK_CTRL	0x00000a03
 
 /* stop */
-wm 32 0xFFFFFFFF			0x00000000
\ No newline at end of file
+wm 32 0xFFFFFFFF			0x00000000
diff --git a/arch/arm/boards/beagle/Makefile b/arch/arm/boards/beagle/Makefile
index 3bee9a22ab..e273f4a3da 100644
--- a/arch/arm/boards/beagle/Makefile
+++ b/arch/arm/boards/beagle/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-beagle
diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c
index 7caac5727f..f9d7f74288 100644
--- a/arch/arm/boards/beagle/board.c
+++ b/arch/arm/boards/beagle/board.c
@@ -11,14 +11,14 @@
 #include <filetype.h>
 #include <envfs.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <mach/gpmc.h>
-#include <mach/gpmc_nand.h>
-#include <mach/ehci.h>
-#include <mach/omap3-devices.h>
+#include <asm/mach-types.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/gpmc_nand.h>
+#include <mach/omap/ehci.h>
+#include <mach/omap/omap3-devices.h>
 #include <i2c/i2c.h>
 #include <linux/err.h>
-#include <usb/ehci.h>
+#include <linux/usb/ehci.h>
 #include <asm/barebox-arm.h>
 
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c
index 30cc1f2c54..e4610722f6 100644
--- a/arch/arm/boards/beagle/lowlevel.c
+++ b/arch/arm/boards/beagle/lowlevel.c
@@ -1,18 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <init.h>
+#include <mach/omap/debug_ll.h>
 #include <debug_ll.h>
 #include <io.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/control.h>
-#include <mach/generic.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap3-generic.h>
-#include <mach/omap3-mux.h>
-#include <mach/sdrc.h>
-#include <mach/syslib.h>
-#include <mach/sys_info.h>
-#include <generated/mach-types.h>
+#include <mach/omap/control.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap3-generic.h>
+#include <mach/omap/omap3-mux.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/sys_info.h>
+#include <asm/mach-types.h>
 
 /**
  * @brief Do the pin muxing required for Board operation.
@@ -194,7 +197,7 @@ static noinline int beagle_board_init(void)
 
 	mux_config();
 
-	omap_uart_lowlevel_init((void *)OMAP3_UART3_BASE);
+	omap_debug_ll_init();
 
 	/* Dont reconfigure SDRAM while running in SDRAM! */
 	if (!in_sdram)
diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile
index 21a1a29d0b..108e481be3 100644
--- a/arch/arm/boards/beaglebone/Makefile
+++ b/arch/arm/boards/beaglebone/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
 bbenv-y += defaultenv-beaglebone
diff --git a/arch/arm/boards/beaglebone/beaglebone.h b/arch/arm/boards/beaglebone/beaglebone.h
index a4f48e5b0b..c95936a84f 100644
--- a/arch/arm/boards/beaglebone/beaglebone.h
+++ b/arch/arm/boards/beaglebone/beaglebone.h
@@ -1,7 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __BOARD_BEAGLEBONE_H
 #define __BOARD_BEAGLEBONE_H
 
-#include <mach/am33xx-generic.h>
+#include <mach/omap/am33xx-generic.h>
 
 static inline int is_beaglebone_black(void)
 {
diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
index 6d2144f95b..43e2d81f38 100644
--- a/arch/arm/boards/beaglebone/board.c
+++ b/arch/arm/boards/beaglebone/board.c
@@ -17,13 +17,13 @@
 #include <net.h>
 #include <bootsource.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/gpmc.h>
+#include <asm/mach-types.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/gpmc.h>
 #include <linux/err.h>
-#include <mach/bbu.h>
+#include <mach/omap/bbu.h>
 
 #include "beaglebone.h"
 
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index 91d143e415..5dc49dfaaf 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -1,19 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <init.h>
 #include <linux/sizes.h>
 #include <io.h>
 #include <linux/string.h>
 #include <debug_ll.h>
+#include <mach/omap/debug_ll.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/am33xx-clock.h>
-#include <mach/generic.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/am33xx-mux.h>
-#include <mach/am33xx-generic.h>
-#include <mach/wdt.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/am33xx-clock.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/am33xx-mux.h>
+#include <mach/omap/am33xx-generic.h>
 
 #include "beaglebone.h"
 
@@ -116,13 +118,7 @@ static noinline int beaglebone_sram_init(void)
 	else
 		sdram_size = SZ_256M;
 
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
 
 	/* Setup the PLLs and the clocks for the peripherals */
 	if (is_beaglebone_black()) {
@@ -137,7 +133,7 @@ static noinline int beaglebone_sram_init(void)
 
 	am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
 	am33xx_enable_uart0_pin_mux();
-	omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
+	omap_debug_ll_init();
 	putc_ll('>');
 
 	barebox_arm_entry(0x80000000, sdram_size, fdt);
diff --git a/arch/arm/boards/beagleplay/Makefile b/arch/arm/boards/beagleplay/Makefile
new file mode 100644
index 0000000000..69935cc168
--- /dev/null
+++ b/arch/arm/boards/beagleplay/Makefile
@@ -0,0 +1 @@
+pbl-y += lowlevel.o entry.o
diff --git a/arch/arm/boards/beagleplay/entry.S b/arch/arm/boards/beagleplay/entry.S
new file mode 100644
index 0000000000..6e4c7196f3
--- /dev/null
+++ b/arch/arm/boards/beagleplay/entry.S
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/linkage.h>
+#include <asm/barebox-arm64.h>
+#include <asm/image.h>
+
+#define IMAGE_FLAGS \
+	(ARM64_IMAGE_FLAG_PAGE_SIZE_4K << ARM64_IMAGE_FLAG_PAGE_SIZE_SHIFT) | \
+	(ARM64_IMAGE_FLAG_PHYS_BASE << ARM64_IMAGE_FLAG_PHYS_BASE_SHIFT)
+
+.section .text_head_entry_start_beagleplay
+ENTRY("start_beagleplay")
+	adr x1, 0	   	   /* code0 */
+	b 2f                       /* code1 */
+	.xword 0x80000             /* Image load offset */
+	.xword _barebox_image_size /* Effective Image size */
+	.xword IMAGE_FLAGS	   /* Kernel flags */
+	.xword 0                   /* reserved */
+	.xword 0                   /* reserved */
+	.xword 0                   /* reserved */
+	.ascii ARM64_IMAGE_MAGIC   /* magic number */
+	.int   0                   /* reserved (PE-COFF offset) */
+	.asciz "barebox"	   /* unused for now */
+2:
+	mov sp, x1
+	/* Stack now grows into the 0x80000 image load offset specified
+	 * above. This is more than enough until FDT /memory is decoded.
+	 */
+	b beagleplay
+ENTRY_PROC_END(start_beagleplay)
diff --git a/arch/arm/boards/beagleplay/lowlevel.c b/arch/arm/boards/beagleplay/lowlevel.c
new file mode 100644
index 0000000000..9d76dbd0a2
--- /dev/null
+++ b/arch/arm/boards/beagleplay/lowlevel.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <debug_ll.h>
+#include <pbl.h>
+
+/* Called from assembly */
+void beagleplay(void);
+
+static noinline void beagleplay_continue(void)
+{
+	unsigned long membase, memsize;
+	extern char __dtb_k3_am625_beagleplay_start[];
+
+	fdt_find_mem(__dtb_k3_am625_beagleplay_start, &membase, &memsize);
+
+	barebox_arm_entry(membase, memsize, __dtb_k3_am625_beagleplay_start);
+}
+
+void beagleplay(void)
+{
+	putc_ll('>');
+
+	arm_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+
+	setup_c();
+
+	beagleplay_continue();
+}
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/Makefile b/arch/arm/boards/boundarydevices-nitrogen6/Makefile
index 0ec04ce898..da63d2625f 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/Makefile
+++ b/arch/arm/boards/boundarydevices-nitrogen6/Makefile
@@ -1,2 +1,4 @@
-obj-y += board.o 
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/board.c b/arch/arm/boards/boundarydevices-nitrogen6/board.c
index dc2d5aa41c..a57cef4fbe 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/board.c
+++ b/arch/arm/boards/boundarydevices-nitrogen6/board.c
@@ -4,10 +4,10 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
-#include <mach/imx6.h>
+#include <mach/imx/imx6.h>
 
 static int nitrogen6x_devices_init(void)
 {
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg
index 5da5fd9419..8aa14f3080 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 #include "ram-base.imxcfg"
 #include "800mhz_4x128mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg
index 3ccf7591c5..5544c25e36 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 #include "ram-base.imxcfg"
 #include "800mhz_4x256mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg
index 7bdc0e736c..4cde5c0818 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 #include "ram-base.imxcfg"
 #include "1066mhz_4x128mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg
index c6f5aa8484..4b38b1bfc9 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 #include "ram-base.imxcfg"
 #include "1066mhz_4x256mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg
index 797b9717e7..2d43222530 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 #include "ram-base.imxcfg"
 #include "1066mhz_4x512mx16-qp.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c b/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c
index 74ff71fc24..8ab5116d8e 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c
+++ b/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c
@@ -1,6 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <mach/generic.h>
-#include <mach/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/esdctl.h>
 #include <asm/barebox-arm.h>
 
 extern char __dtb_imx6q_nitrogen6x_start[];
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg
index 5d675883fd..bf2aec5d96 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 wm 32 MX6_IOM_DRAM_SDQS0		0x00000030
 wm 32 MX6_IOM_DRAM_SDQS1		0x00000030
 wm 32 MX6_IOM_DRAM_SDQS2		0x00000030
diff --git a/arch/arm/boards/calao/Makefile b/arch/arm/boards/calao/Makefile
new file mode 100644
index 0000000000..da63d2625f
--- /dev/null
+++ b/arch/arm/boards/calao/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/calao/board.c b/arch/arm/boards/calao/board.c
new file mode 100644
index 0000000000..cc369c4cf1
--- /dev/null
+++ b/arch/arm/boards/calao/board.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <deep-probe.h>
+#include <of.h>
+
+static const struct of_device_id calao_of_match[] = {
+	{ .compatible = "calao,tny-a9260" },
+	{ .compatible = "calao,tny-a9g20" },
+	{ .compatible = "calao,usb-a9260" },
+	{ .compatible = "calao,usb-a9g20" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(calao_of_match);
diff --git a/arch/arm/boards/calao/lowlevel.c b/arch/arm/boards/calao/lowlevel.c
new file mode 100644
index 0000000000..2a081a97a4
--- /dev/null
+++ b/arch/arm/boards/calao/lowlevel.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <init.h>
+#include <debug_ll.h>
+#include <asm/reloc.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9260.h>
+#include <mach/at91/hardware.h>
+
+static void dbgu_init(void)
+{
+	/* pinmux/clocks/uart already configured by first stage */
+	putc_ll('>');
+}
+
+#define CALAO_ENTRY_2ND(entrypoint, dtbname) \
+AT91_ENTRY_FUNCTION(entrypoint, r0, r1, r2) { \
+	extern char __dtb_z_##dtbname##_start[]; \
+	arm_cpu_lowlevel_init(); \
+	arm_setup_stack(AT91SAM9260_SRAM_END); \
+	dbgu_init(); \
+	at91sam9260_barebox_entry(runtime_address(__dtb_z_##dtbname##_start)); \
+}
+
+CALAO_ENTRY_2ND(start_tny_a9260, tny_a9260);
+CALAO_ENTRY_2ND(start_tny_a9g20, tny_a9g20);
+CALAO_ENTRY_2ND(start_usb_a9260, usb_a9260);
+CALAO_ENTRY_2ND(start_usb_a9g20, usb_a9g20);
diff --git a/arch/arm/boards/canon-a1100/Makefile b/arch/arm/boards/canon-a1100/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/canon-a1100/Makefile
+++ b/arch/arm/boards/canon-a1100/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/canon-a1100/lowlevel.c b/arch/arm/boards/canon-a1100/lowlevel.c
index b75a1bfa60..47a9564e0f 100644
--- a/arch/arm/boards/canon-a1100/lowlevel.c
+++ b/arch/arm/boards/canon-a1100/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
diff --git a/arch/arm/boards/ccxmx51/Makefile b/arch/arm/boards/ccxmx51/Makefile
index 50cf929c5d..9fbde144a5 100644
--- a/arch/arm/boards/ccxmx51/Makefile
+++ b/arch/arm/boards/ccxmx51/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y					+= ccxmx51.o
 lwl-y					+= lowlevel.o
 bbenv-$(CONFIG_DEFAULT_ENVIRONMENT)	+= defaultenv-ccxmx51
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c
index 09437b047f..4ea71fe26b 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51.c
+++ b/arch/arm/boards/ccxmx51/ccxmx51.c
@@ -16,12 +16,12 @@
 #include <mfd/mc13xxx.h>
 #include <mfd/mc13892.h>
 
-#include <mach/bbu.h>
-#include <mach/esdctl.h>
-#include <mach/iim.h>
-#include <mach/imx5.h>
-#include <mach/imx51-regs.h>
-#include <mach/revision.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/iim.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/imx51-regs.h>
+#include <mach/imx/revision.h>
 
 static const struct ccxmx_ident {
 	char		*id_string;
@@ -174,7 +174,7 @@ static void ccxmx51_power_init(struct mc13xxx *mc13xxx)
 
 static void ccxmx51_disable_device(struct device_node *root, const char *label)
 {
-	struct device_node *np = of_find_node_by_name(root, label);
+	struct device_node *np = of_find_node_by_name_address(root, label);
 	if (np)
 		of_device_disable(np);
 }
@@ -189,11 +189,15 @@ static int ccxmx51_board_fixup(struct device_node *root, void *unused)
 	if (!ccxmx_id->eth0)
 		ccxmx51_disable_device(root, "ethernet@83fec000");
 
-	if (!ccxmx_id->eth1)
+	if (!ccxmx_id->eth1) {
 		ccxmx51_disable_device(root, "lan9221@5,0");
+		ccxmx51_disable_device(root, "ethernet@5,0");
+	}
 
-	if (!ccxmx_id->wless)
+	if (!ccxmx_id->wless) {
 		ccxmx51_disable_device(root, "esdhc@70008000");
+		ccxmx51_disable_device(root, "mmc@70008000");
+	}
 
 	serial = basprintf("%08x%08x", 0, boardserial);
 	of_set_property(root, "serial-number", serial, strlen(serial) + 1, 1);
@@ -245,8 +249,6 @@ static __init int ccxmx51_init(void)
 		hang();
 	}
 
-	ccxmx_id = &ccxmx51_ids[hwid[0]];
-
 	switch (hwid[2] & 0xc0) {
 	case 0x00:
 		manloc = 'B';
diff --git a/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg b/arch/arm/boards/ccxmx51/flash-header-x16.imxcfg
index 85c128c8fd..6d77324fc8 100644
--- a/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg
+++ b/arch/arm/boards/ccxmx51/flash-header-x16.imxcfg
@@ -1,6 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx51
-ivtofs 0x400
 loadaddr 0x90000000
+ivtofs 0x400
 wm 32 0x73fa88a0 0x00000200
 wm 32 0x73fa850c 0x000020c5
 wm 32 0x73fa8510 0x000020c5
@@ -23,8 +25,8 @@ wm 32 0x73fa882c 0x00000004
 wm 32 0x73fa88a4 0x00000004
 wm 32 0x73fa88ac 0x00000004
 wm 32 0x73fa88b8 0x00000004
-wm 32 0x83fd9000 0x82a20000
-wm 32 0x83fd9008 0x82a20000
+wm 32 0x83fd9000 0x82a10000
+wm 32 0x83fd9008 0x82a10000
 wm 32 0x83fd9010 0x000ad0d0
 wm 32 0x83fd9004 0x3f3584ab
 wm 32 0x83fd900c 0x3f3584ab
@@ -52,8 +54,8 @@ wm 32 0x83fd9014 0x0632801c
 wm 32 0x83fd9014 0x0380801d
 wm 32 0x83fd9014 0x0040801d
 wm 32 0x83fd9014 0x00008004
-wm 32 0x83fd9000 0xb2a20000
-wm 32 0x83fd9008 0xb2a20000
+wm 32 0x83fd9000 0xb2a10000
+wm 32 0x83fd9008 0xb2a10000
 wm 32 0x83fd9010 0x000ad6d0
 wm 32 0x83fd9034 0x90000000
 wm 32 0x83fd9014 0x00000000
diff --git a/arch/arm/boards/ccxmx51/flash-header.imxcfg b/arch/arm/boards/ccxmx51/flash-header-x32.imxcfg
index 3b1df11133..6480aa590e 100644
--- a/arch/arm/boards/ccxmx51/flash-header.imxcfg
+++ b/arch/arm/boards/ccxmx51/flash-header-x32.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx51
 loadaddr 0x90000000
 ivtofs 0x400
@@ -57,4 +59,3 @@ wm 32 0x83fd9008 0xb2a20000
 wm 32 0x83fd9010 0x000ad6d0
 wm 32 0x83fd9034 0x90000000
 wm 32 0x83fd9014 0x00000000
-
diff --git a/arch/arm/boards/ccxmx51/lowlevel.c b/arch/arm/boards/ccxmx51/lowlevel.c
index adcb30a7ff..b0881f9c5b 100644
--- a/arch/arm/boards/ccxmx51/lowlevel.c
+++ b/arch/arm/boards/ccxmx51/lowlevel.c
@@ -2,22 +2,61 @@
 /* Author: Alexander Shiyan <shc_work@mail.ru> */
 
 #include <common.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/clock-imx51_53.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/iomux-mx51.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
-#include <mach/imx51-regs.h>
+#include <mach/imx/imx51-regs.h>
 
-ENTRY_FUNCTION(start_ccxmx51, r0, r1, r2)
+static inline void setup_uart(void)
+{
+	void __iomem *iomuxbase = IOMEM(MX51_IOMUXC_BASE_ADDR);
+	void __iomem *ccmbase = IOMEM(MX51_CCM_BASE_ADDR);
+
+	/*
+	 * Restore CCM values that might be changed by the Mask ROM
+	 * code.
+	 *
+	 * Source: RealView debug scripts provided by Freescale
+	 */
+	writel(MX5_CCM_CBCDR_RESET_VALUE,  ccmbase + MX5_CCM_CBCDR);
+	writel(MX5_CCM_CSCMR1_RESET_VALUE, ccmbase + MX5_CCM_CSCMR1);
+	writel(MX5_CCM_CSCDR1_RESET_VALUE, ccmbase + MX5_CCM_CSCDR1);
+
+	imx_setup_pad(iomuxbase, MX51_PAD_UART1_TXD__UART1_TXD);
+
+	imx51_uart_setup_ll();
+
+	putc_ll('>');
+}
+
+static inline void start_ccxmx51(void)
 {
 	extern char __dtb_imx51_ccxmx51_start[];
 	void *fdt;
 
 	imx5_cpu_lowlevel_init();
 
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
 	arm_setup_stack(0x20000000);
 
 	fdt = __dtb_imx51_ccxmx51_start + get_runtime_offset();
 
 	barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, fdt);
 }
+
+ENTRY_FUNCTION(start_ccxmx51_x16, r0, r1, r2)
+{
+	start_ccxmx51();
+}
+
+ENTRY_FUNCTION(start_ccxmx51_x32, r0, r1, r2)
+{
+	start_ccxmx51();
+}
diff --git a/arch/arm/boards/ccxmx53/Makefile b/arch/arm/boards/ccxmx53/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/ccxmx53/Makefile
+++ b/arch/arm/boards/ccxmx53/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/ccxmx53/board.c b/arch/arm/boards/ccxmx53/board.c
index b0faf8d280..26654193ad 100644
--- a/arch/arm/boards/ccxmx53/board.c
+++ b/arch/arm/boards/ccxmx53/board.c
@@ -9,14 +9,14 @@
 #include <i2c/i2c.h>
 #include <gpio.h>
 
-#include <generated/mach-types.h>
-#include <mach/imx5.h>
-#include <mach/generic.h>
-#include <mach/imx53-regs.h>
-#include <mach/esdctl.h>
+#include <asm/mach-types.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/esdctl.h>
 #include <asm/armlinux.h>
-#include <mach/bbu.h>
-#include <mach/iim.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/iim.h>
 
 
 struct ccwmx53_ident {
diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg
index 390b75b4f2..c049b2a10f 100644
--- a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg
+++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x70000000
 soc imx53
 ivtofs 0x400
diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg
index c32ab9c162..a6460e0333 100644
--- a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg
+++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x70000000
 soc imx53
 ivtofs 0x400
diff --git a/arch/arm/boards/ccxmx53/lowlevel.c b/arch/arm/boards/ccxmx53/lowlevel.c
index 5833ad4739..74fde99337 100644
--- a/arch/arm/boards/ccxmx53/lowlevel.c
+++ b/arch/arm/boards/ccxmx53/lowlevel.c
@@ -5,9 +5,9 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <io.h>
-#include <mach/imx53-regs.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 #include <image-metadata.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
diff --git a/arch/arm/boards/chumby_falconwing/Makefile b/arch/arm/boards/chumby_falconwing/Makefile
index cf92c6a9ea..6aaff6cdf7 100644
--- a/arch/arm/boards/chumby_falconwing/Makefile
+++ b/arch/arm/boards/chumby_falconwing/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y = falconwing.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c
index 82b9415e80..9221590455 100644
--- a/arch/arm/boards/chumby_falconwing/falconwing.c
+++ b/arch/arm/boards/chumby_falconwing/falconwing.c
@@ -9,18 +9,17 @@
 #include <errno.h>
 #include <mci.h>
 #include <linux/sizes.h>
-#include <usb/ehci.h>
+#include <linux/usb/ehci.h>
 #include <asm/armlinux.h>
 #include <asm/barebox-arm.h>
 #include <io.h>
 #include <asm/mmu.h>
-#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
-#include <mach/clock.h>
-#include <mach/mci.h>
-#include <mach/fb.h>
-#include <mach/usb.h>
-#include <mach/iomux.h>
+#include <asm/mach-types.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/mci.h>
+#include <mach/mxs/fb.h>
+#include <mach/mxs/usb.h>
+#include <mach/mxs/iomux.h>
 
 static struct mxs_mci_platform_data mci_pdata = {
 	.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED,
diff --git a/arch/arm/boards/chumby_falconwing/lowlevel.c b/arch/arm/boards/chumby_falconwing/lowlevel.c
index 0277b5d083..fdda6ba5f2 100644
--- a/arch/arm/boards/chumby_falconwing/lowlevel.c
+++ b/arch/arm/boards/chumby_falconwing/lowlevel.c
@@ -1,12 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx23-regs.h>
-#include <generated/mach-types.h>
+#include <mach/mxs/imx23-regs.h>
+#include <asm/mach-types.h>
+
+static noinline void continue_imx_entry(size_t size)
+{
+	static struct barebox_arm_boarddata boarddata = {
+		.magic = BAREBOX_ARM_BOARDDATA_MAGIC,
+		.machine = MACH_TYPE_CHUMBY,
+	};
+
+	barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata);
+}
 
 ENTRY_FUNCTION(start_chumby_falconwing, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
-	barebox_arm_entry(IMX_MEMORY_BASE, SZ_64M, (void *)MACH_TYPE_CHUMBY);
+
+	relocate_to_current_adr();
+	setup_c();
+
+	continue_imx_entry(SZ_64M);
 }
diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile
index a5001df9b5..85d92c8a7f 100644
--- a/arch/arm/boards/clep7212/Makefile
+++ b/arch/arm/boards/clep7212/Makefile
@@ -1,3 +1,5 @@
-obj-y += clep7212.o
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
 lwl-y += lowlevel.o
-bbenv-y += defaultenv-clep7212
+bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-clep7212
diff --git a/arch/arm/boards/clep7212/board.c b/arch/arm/boards/clep7212/board.c
new file mode 100644
index 0000000000..b3983f2f49
--- /dev/null
+++ b/arch/arm/boards/clep7212/board.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru>
+
+#include <envfs.h>
+#include <init.h>
+#include <of.h>
+
+static __init int clep7212_init(void)
+{
+	if (of_machine_is_compatible("cirrus,clep7212"))
+		defaultenv_append_directory(defaultenv_clep7212);
+
+	return 0;
+}
+device_initcall(clep7212_init);
diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c
deleted file mode 100644
index 3b497a6bd2..0000000000
--- a/arch/arm/boards/clep7212/clep7212.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2012 Alexander Shiyan <shc_work@mail.ru>
-
-#include <common.h>
-#include <driver.h>
-#include <envfs.h>
-#include <init.h>
-#include <partition.h>
-#include <io.h>
-#include <linux/sizes.h>
-#include <asm/armlinux.h>
-#include <asm/mmu.h>
-#include <generated/mach-types.h>
-
-#include <mach/clps711x.h>
-#include <mach/devices.h>
-
-static int clps711x_devices_init(void)
-{
-	u32 serial_h = 0, serial_l = readl(UNIQID);
-	void *cfi_io;
-
-	/* Setup Chipselects */
-	clps711x_setup_memcfg(0, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_16);
-	clps711x_setup_memcfg(1, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_8);
-	clps711x_setup_memcfg(2, MEMCFG_WAITSTATE_8_3 | MEMCFG_BUS_WIDTH_16 |
-			      MEMCFG_CLKENB);
-	clps711x_setup_memcfg(3, MEMCFG_WAITSTATE_7_1 | MEMCFG_BUS_WIDTH_32);
-
-	cfi_io = map_io_sections(CS0_BASE, (void *)0x90000000, SZ_32M);
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_io, SZ_32M,
-			     IORESOURCE_MEM);
-
-	devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED,
-			    "self0");
-	devfs_add_partition("nor0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED,
-			    "env0");
-
-	armlinux_set_architecture(MACH_TYPE_CLEP7212);
-	armlinux_set_serial(((u64)serial_h << 32) | serial_l);
-
-	defaultenv_append_directory(defaultenv_clep7212);
-
-	return 0;
-}
-device_initcall(clps711x_devices_init);
-
-static int clps711x_console_init(void)
-{
-	barebox_set_model("Cirrus Logic CLEP7212");
-	barebox_set_hostname("clep7212");
-
-	clps711x_add_uart(0);
-
-	return 0;
-}
-console_initcall(clps711x_console_init);
diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
index 41827dfa16..ba402cecea 100644
--- a/arch/arm/boards/clep7212/lowlevel.c
+++ b/arch/arm/boards/clep7212/lowlevel.c
@@ -1,22 +1,21 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2012 Alexander Shiyan <shc_work@mail.ru>
+// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru>
 
 #include <common.h>
-#include <init.h>
+#include <asm/barebox-arm.h>
+#include <linux/sizes.h>
+#include <mach/clps711x/clps711x.h>
 
-#include <asm/barebox-arm-head.h>
+extern char __dtb_ep7212_clep7212_start[];
 
-#include <mach/clps711x.h>
-
-#ifdef CONFIG_CLPS711X_RAISE_CPUFREQ
-# define CLPS711X_CPU_PLL_MULT	50
-#else
-# define CLPS711X_CPU_PLL_MULT	40
-#endif
-
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+ENTRY_FUNCTION_WITHSTACK(start_ep7212_clep7212,
+			 CS6_BASE + 48 * SZ_1K, r0, r1, r2)
 {
+	void *fdt;
+
 	arm_cpu_lowlevel_init();
 
-	clps711x_barebox_entry(CLPS711X_CPU_PLL_MULT, NULL);
+	fdt = __dtb_ep7212_clep7212_start;
+
+	clps711x_start(fdt + get_runtime_offset());
 }
diff --git a/arch/arm/boards/cm-fx6/Makefile b/arch/arm/boards/cm-fx6/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/cm-fx6/Makefile
+++ b/arch/arm/boards/cm-fx6/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/cm-fx6/board.c b/arch/arm/boards/cm-fx6/board.c
index 5a1110860f..c70989476b 100644
--- a/arch/arm/boards/cm-fx6/board.c
+++ b/arch/arm/boards/cm-fx6/board.c
@@ -4,13 +4,13 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/imx6-regs.h>
-#include <mach/bbu.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/bbu.h>
 #include <asm/armlinux.h>
 #include <linux/phy.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
-#include <mach/imx6.h>
+#include <mach/imx/imx6.h>
 #include <net.h>
 
 static int phy_fixup(struct phy_device *phydev)
diff --git a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg
index 4bb615ebb0..da4cd4bebf 100644
--- a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg
+++ b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x00907000
 max_load_size 0x11000
diff --git a/arch/arm/boards/cm-fx6/lowlevel.c b/arch/arm/boards/cm-fx6/lowlevel.c
index fd86e159aa..029586294f 100644
--- a/arch/arm/boards/cm-fx6/lowlevel.c
+++ b/arch/arm/boards/cm-fx6/lowlevel.c
@@ -1,17 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define pr_fmt(fmt) "cm-fx6: " fmt
 
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <io.h>
-#include <mach/imx6-mmdc.h>
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6.h>
-#include <mach/xload.h>
-#include <mach/esdctl.h>
+#include <mach/imx/imx6-mmdc.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/esdctl.h>
 #include <serial/imx-uart.h>
 
 enum ddr_config {
@@ -332,7 +335,7 @@ static noinline void cm_fx6_start(void)
 
 ENTRY_FUNCTION(start_imx6_cm_fx6, r0, r1, r2)
 {
-	arm_cpu_lowlevel_init();
+	imx6_cpu_lowlevel_init();
 
 	relocate_to_current_adr();
 	setup_c();
@@ -359,7 +362,7 @@ static noinline void utilite_start(void)
 
 ENTRY_FUNCTION(start_imx6_utilite, r0, r1, r2)
 {
-	arm_cpu_lowlevel_init();
+	imx6_cpu_lowlevel_init();
 
 	relocate_to_current_adr();
 	setup_c();
diff --git a/arch/arm/boards/congatec-qmx8p/Makefile b/arch/arm/boards/congatec-qmx8p/Makefile
new file mode 100644
index 0000000000..b3ae72be3e
--- /dev/null
+++ b/arch/arm/boards/congatec-qmx8p/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y += board.o
+lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/congatec-qmx8p/board.c b/arch/arm/boards/congatec-qmx8p/board.c
new file mode 100644
index 0000000000..fcec2a17c4
--- /dev/null
+++ b/arch/arm/boards/congatec-qmx8p/board.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: 2023 Juergen Borleis, Pengutronix
+// SPDX-FileCopyrightText: 2023 Johannes Zink, Pengutronix
+
+#include <asm/memory.h>
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <gpio.h>
+#include <envfs.h>
+
+/* Phy regulator handling in Linux is broken for the MX8 EQOs, as the
+ * 'phy-regulators' properties are not handed down properly, so this is
+ * currently not set in the kernel DT.
+ * As a workaround, enable the regulator manually via GPIO. */
+#define EQOS_PWR_PIN IMX_GPIO_NR(1, 5) /* ENET_PWREN# */
+static void setup_ethernet_phy(void)
+{
+	u32 val;
+
+	of_device_ensure_probed_by_alias("gpio0");
+
+	if (gpio_direction_output(EQOS_PWR_PIN, 0)) {
+		pr_err("eqos phy power: failed to request pin\n");
+		return;
+	}
+
+	/* the phy needs roughly 200ms delay after power-on */
+	mdelay(200);
+
+	/* Enable RGMII TX clk output */
+	val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
+	val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN;
+	writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
+}
+
+static int congatec_qmx8p_probe(struct device *dev)
+{
+	setup_ethernet_phy();
+
+	imx8m_bbu_internal_flexspi_nor_register_handler("QSPI",
+		"/dev/m25p0.boot", BBU_HANDLER_FLAG_DEFAULT);
+
+	return 0;
+}
+
+static const struct of_device_id congatec_qmx8p_of_match[] = {
+	{ .compatible = "congatec,qmx8p" },
+	{ /* Sentinel */ }
+};
+BAREBOX_DEEP_PROBE_ENABLE(congatec_qmx8p_of_match);
+
+static struct driver congatec_qmx8p_som_driver = {
+	.name = "som-congatec-qmx8p",
+	.probe = congatec_qmx8p_probe,
+	.of_compatible = congatec_qmx8p_of_match,
+};
+coredevice_platform_driver(congatec_qmx8p_som_driver);
diff --git a/arch/arm/boards/congatec-qmx8p/flash-header-congatec-qmx8p.imxcfg b/arch/arm/boards/congatec-qmx8p/flash-header-congatec-qmx8p.imxcfg
new file mode 100644
index 0000000000..70c57768eb
--- /dev/null
+++ b/arch/arm/boards/congatec-qmx8p/flash-header-congatec-qmx8p.imxcfg
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+soc imx8mp
+
+loadaddr 0x920000
+max_load_size 0x3f000
+ivtofs 0x0
+
+flexspi_ivtofs 0x0
+flexspi_fcfbofs 0x400
diff --git a/arch/arm/boards/congatec-qmx8p/lowlevel.c b/arch/arm/boards/congatec-qmx8p/lowlevel.c
new file mode 100644
index 0000000000..1889b9bb33
--- /dev/null
+++ b/arch/arm/boards/congatec-qmx8p/lowlevel.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: 2023 Pengutronix
+
+#include <common.h>
+#include <debug_ll.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <asm/sections.h>
+#include <image-metadata.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <mach/imx/imx8mp-regs.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/xload.h>
+#include <mfd/pca9450.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <soc/fsl/fsl_udc.h>
+#include <soc/imx8m/ddr.h>
+
+extern char __dtb_z_imx8mp_koenigbauer_alphajet_start[];
+
+#define UART_PAD_CTRL   MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+				     MX8MP_PAD_CTL_FSEL)
+/*
+ * SoC UART 1 is the standard console on the KB base board
+ */
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mp_setup_pad(MX8MP_PAD_UART1_TXD__UART1_DCE_TX | UART_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_UART1_RXD__UART1_DCE_RX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+
+	putc_ll('>');
+}
+
+#define I2C_PAD_CTRL	MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+				     MX8MP_PAD_CTL_HYS | \
+				     MX8MP_PAD_CTL_PUE | \
+				     MX8MP_PAD_CTL_PE)
+
+static struct pmic_config pca9450_cfg[] = {
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	{ PCA9450_BUCK123_DVS, 0x29 },
+	/*
+	 * increase VDD_SOC to typical value 0.95V before first
+	 * DRAM access, set DVS1 to 0.85v for suspend.
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+	 */
+	{ PCA9450_BUCK1OUT_DVS0, 0x1C },
+	{ PCA9450_BUCK1OUT_DVS1, 0x14 },
+	{ PCA9450_BUCK1CTRL, 0x59 },
+	/* Kernel uses OD/OD freq for SOC */
+	/* To avoid timing risk from SOC to ARM, increase
+	 * VDD_ARM to OD voltage 0.95v
+	 */
+	{ PCA9450_BUCK2OUT_DVS0, 0x1C },
+	/* set WDOG_B_CFG to cold reset */
+	{ PCA9450_RESET_CTRL, 0xA1 },
+};
+
+static void power_init_board(void)
+{
+	struct pbl_i2c *i2c;
+
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
+
+	pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+}
+
+extern struct dram_timing_info dram_timing_4g;
+
+static void start_tfa(void)
+{
+	/*
+	 * If we are in EL3 we are running for the first time and need to
+	 * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
+	 * to DRAM in EL2.
+	 */
+	if (current_el() != 3)
+		return;
+
+	imx8mp_early_clock_init();
+	power_init_board();
+
+	imx8mp_ddr_init(&dram_timing_4g, DRAM_TYPE_LPDDR4);
+
+	imx8mp_load_and_start_image_via_tfa();
+}
+
+static __noreturn noinline void congatec_qmx8p_start(char dtb[])
+{
+	setup_uart();
+
+	start_tfa();
+
+	/*
+	 * Standard entry we hit once we initialized both DDR and ATF
+	 */
+	imx8mp_barebox_entry(dtb);
+}
+
+ENTRY_FUNCTION(start_koenigbauer_alphajet, r0, r1, r2)
+{
+	imx8mp_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	congatec_qmx8p_start(__dtb_z_imx8mp_koenigbauer_alphajet_start);
+}
diff --git a/arch/arm/boards/congatec-qmx8p/lpddr4-timing.c b/arch/arm/boards/congatec-qmx8p/lpddr4-timing.c
new file mode 100644
index 0000000000..6d10b530ba
--- /dev/null
+++ b/arch/arm/boards/congatec-qmx8p/lpddr4-timing.c
@@ -0,0 +1,1832 @@
+// SPDX-License-Identifier: GPL-2.0+
+// SPDX-FileCopyrightText: 2019 NXP
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg_4g[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400020, 0x1322 },
+	{ 0x3d400024, 0x1e84800 },
+	{ 0x3d400064, 0x3d0118 },
+	{ 0x3d400070, 0x61027f10 },
+	{ 0x3d400074, 0x7b0 },
+	{ 0x3d4000d0, 0xc00307a3 },
+	{ 0x3d4000d4, 0xc50000 },
+	{ 0x3d4000dc, 0xf4003f },
+	{ 0x3d4000e0, 0x330000 },
+	{ 0x3d4000e8, 0x660048 },
+	{ 0x3d4000ec, 0x160048 },
+	{ 0x3d400100, 0x2028112a },
+	{ 0x3d400104, 0x8083f },
+	{ 0x3d40010c, 0xe0e000 },
+	{ 0x3d400110, 0x12040a12 },
+	{ 0x3d400114, 0x2050f0f },
+	{ 0x3d400118, 0x1010009 },
+	{ 0x3d40011c, 0x501 },
+	{ 0x3d400130, 0x20800 },
+	{ 0x3d400134, 0xe100002 },
+	{ 0x3d400138, 0x120 },
+	{ 0x3d400144, 0xc80064 },
+	{ 0x3d400180, 0x3e8001e },
+	{ 0x3d400184, 0x3207a12 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x49f820e },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x1f0e },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x9121c1c },
+	{ 0x3d400200, 0x17 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1020 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0x6001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x330000 },
+	{ 0x3d4020e8, 0x660048 },
+	{ 0x3d4020ec, 0x160048 },
+	{ 0x3d402100, 0xa040105 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x1020 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x330000 },
+	{ 0x3d4030e8, 0x660048 },
+	{ 0x3d4030ec, 0x160048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x18 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x3e8 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+static struct dram_cfg_param ddr_fsp0_cfg_4g[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_cfg_param ddr_fsp1_cfg_4g[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_cfg_param ddr_fsp2_cfg_4g[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_cfg_param ddr_fsp0_2d_cfg_4g[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x8 },
+	{ 0x90159, 0xe8 },
+	{ 0x9015a, 0x109 },
+	{ 0x9015b, 0x0 },
+	{ 0x9015c, 0x8140 },
+	{ 0x9015d, 0x10c },
+	{ 0x9015e, 0x10 },
+	{ 0x9015f, 0x8138 },
+	{ 0x90160, 0x104 },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0x448 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0xf },
+	{ 0x90165, 0x7c0 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0x0 },
+	{ 0x90168, 0xe8 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x47 },
+	{ 0x9016b, 0x630 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x618 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0xe0 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x0 },
+	{ 0x90174, 0x7c8 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x8140 },
+	{ 0x90178, 0x10c },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x478 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x1 },
+	{ 0x9017e, 0x8 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x4 },
+	{ 0x90181, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x68 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x7d },
+	{ 0x2000c, 0xfa },
+	{ 0x2000d, 0x9c4 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg_4g[] = {
+	{
+		/* P0 4000mts 1D */
+		.drate = 4000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg_4g,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_4g),
+	}, {
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg_4g,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_4g),
+	}, {
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg_4g,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_4g),
+	}, {
+		/* P0 4000mts 2D */
+		.drate = 4000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg_4g,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_4g),
+	},
+};
+
+struct dram_timing_info dram_timing_4g = {
+	.ddrc_cfg = ddr_ddrc_cfg_4g,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_4g),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg_4g,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_4g),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 4000, 400, 100, },
+};
diff --git a/arch/arm/boards/crystalfontz-cfa10036/Makefile b/arch/arm/boards/crystalfontz-cfa10036/Makefile
index 5b764a6981..3cd1cecaa7 100644
--- a/arch/arm/boards/crystalfontz-cfa10036/Makefile
+++ b/arch/arm/boards/crystalfontz-cfa10036/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += cfa10036.o hwdetect.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c
index 5a951d1abf..dd6d62b165 100644
--- a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c
+++ b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c
@@ -19,18 +19,17 @@
 #include <i2c/i2c-gpio.h>
 #include <i2c/at24.h>
 
-#include <mach/clock.h>
-#include <mach/imx-regs.h>
-#include <mach/iomux.h>
-#include <mach/mci.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/iomux.h>
+#include <mach/mxs/mci.h>
 
 #include <asm/armlinux.h>
 #include <asm/mmu.h>
 #include <asm/barebox-arm.h>
 
-#include <mach/fb.h>
+#include <mach/mxs/fb.h>
 
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 
 #include "hwdetect.h"
 
diff --git a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c
index 1bc5947682..447ef0dc66 100644
--- a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c
+++ b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c
@@ -1,12 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx28-regs.h>
-#include <generated/mach-types.h>
+#include <mach/mxs/imx28-regs.h>
+#include <asm/mach-types.h>
+
+static noinline void continue_imx_entry(size_t size)
+{
+	static struct barebox_arm_boarddata boarddata = {
+		.magic = BAREBOX_ARM_BOARDDATA_MAGIC,
+		.machine = MACH_TYPE_CFA10036,
+	};
+
+	barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata);
+}
 
 ENTRY_FUNCTION(start_cfa10036, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
-	barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, (void *)MACH_TYPE_CFA10036);
+
+	relocate_to_current_adr();
+	setup_c();
+
+	continue_imx_entry(SZ_128M);
 }
diff --git a/arch/arm/boards/datamodul-edm-qmx6/Makefile b/arch/arm/boards/datamodul-edm-qmx6/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/datamodul-edm-qmx6/Makefile
+++ b/arch/arm/boards/datamodul-edm-qmx6/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c
index 5a24ca0806..8680485de2 100644
--- a/arch/arm/boards/datamodul-edm-qmx6/board.c
+++ b/arch/arm/boards/datamodul-edm-qmx6/board.c
@@ -1,10 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 // SPDX-FileCopyrightText: 2012 Steffen Trumtrar, Pengutronix
 
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <environment.h>
 #include <bootsource.h>
-#include <partition.h>
 #include <common.h>
 #include <envfs.h>
 #include <linux/sizes.h>
@@ -12,18 +11,19 @@
 #include <gpio.h>
 #include <of.h>
 
+#include <linux/mdio.h>
 #include <linux/micrel_phy.h>
 #include <mfd/stmpe-i2c.h>
 
 #include <asm/armlinux.h>
 #include <asm/io.h>
 
-#include <mach/devices-imx6.h>
-#include <mach/imx6-regs.h>
-#include <mach/iomux-mx6.h>
-#include <mach/generic.h>
-#include <mach/imx6.h>
-#include <mach/bbu.h>
+#include <mach/imx/devices-imx6.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/iomux-mx6.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/bbu.h>
 
 #define RQ7_GPIO_ENET_PHYADD2	IMX_GPIO_NR(6, 30)
 #define RQ7_GPIO_ENET_MODE0	IMX_GPIO_NR(6, 25)
@@ -49,9 +49,9 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev)
 	 * min rx data delay, max rx/tx clock delay,
 	 * min rx/tx control delay
 	 */
-	phy_write_mmd_indirect(dev, 4, 2, 0);
-	phy_write_mmd_indirect(dev, 5, 2, 0);
-	phy_write_mmd_indirect(dev, 8, 2, 0x03ff);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 4, 0);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 5, 0);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 8, 0x03ff);
 
 	return 0;
 }
diff --git a/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg
index 14146bed22..139e6df792 100644
--- a/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg
+++ b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x00907000
 ivtofs 0x400
diff --git a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
index 8ac9317cb0..9566e492e3 100644
--- a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
+++ b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
@@ -9,8 +9,8 @@
 #include <asm/mmu.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx6-mmdc.h>
-#include <mach/generic.h>
+#include <mach/imx/imx6-mmdc.h>
+#include <mach/imx/generic.h>
 
 static void sdram_init(void)
 {
diff --git a/arch/arm/boards/dfi-fs700-m60/Makefile b/arch/arm/boards/dfi-fs700-m60/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/dfi-fs700-m60/Makefile
+++ b/arch/arm/boards/dfi-fs700-m60/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/dfi-fs700-m60/board.c b/arch/arm/boards/dfi-fs700-m60/board.c
index 99e36da2ec..a0cdc5b93a 100644
--- a/arch/arm/boards/dfi-fs700-m60/board.c
+++ b/arch/arm/boards/dfi-fs700-m60/board.c
@@ -3,7 +3,7 @@
 
 #define pr_fmt(fmt)  "dfi-fs700-m60: " fmt
 
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <environment.h>
 #include <bootsource.h>
 #include <globalvar.h>
@@ -20,9 +20,9 @@
 #include <asm/mmu.h>
 #include <asm/io.h>
 
-#include <mach/imx6-regs.h>
-#include <mach/generic.h>
-#include <mach/bbu.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/bbu.h>
 
 /*
  * This board can have 512MiB, 1GiB or 2GiB of SDRAM. The actual amount of SDRAM
diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg
index fe8bd8cbd6..8eec14b014 100644
--- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg
+++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg
@@ -1,9 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x27800000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_DRAM_SDQS5 0x00000030
 wm 32 MX6_IOM_DRAM_DQM5 0x00020030
diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg
index 6919bd8c3f..9573459bd5 100644
--- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg
+++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg
@@ -1,9 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x27800000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg
index 709c11974b..b6318e8812 100644
--- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg
+++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x17800000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/dfi-fs700-m60/lowlevel.c b/arch/arm/boards/dfi-fs700-m60/lowlevel.c
index d898cb5c1e..1ca0d6f090 100644
--- a/arch/arm/boards/dfi-fs700-m60/lowlevel.c
+++ b/arch/arm/boards/dfi-fs700-m60/lowlevel.c
@@ -8,8 +8,8 @@
 #include <asm/mmu.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx6-regs.h>
-#include <mach/generic.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/generic.h>
 
 #include <debug_ll.h>
 
diff --git a/arch/arm/boards/digi-ccimx6ulsom/Makefile b/arch/arm/boards/digi-ccimx6ulsom/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/digi-ccimx6ulsom/Makefile
+++ b/arch/arm/boards/digi-ccimx6ulsom/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/digi-ccimx6ulsom/board.c b/arch/arm/boards/digi-ccimx6ulsom/board.c
index b4fcc17e09..ef6828c02c 100644
--- a/arch/arm/boards/digi-ccimx6ulsom/board.c
+++ b/arch/arm/boards/digi-ccimx6ulsom/board.c
@@ -3,8 +3,8 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/generic.h>
-#include <mach/bbu.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/bbu.h>
 
 static int digi_ccimx6ulsbcpro_device_init(void)
 {
diff --git a/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg
index 7b2a198672..6f1c5bc8a7 100644
--- a/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg
+++ b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x80000000
 soc imx6
 ivtofs 0x400
diff --git a/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c b/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c
index 7bf1db8120..08651f0779 100644
--- a/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c
+++ b/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c
@@ -1,7 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm.h>
-#include <mach/esdctl.h>
+#include <mach/imx/esdctl.h>
 #include <asm/cache.h>
 
 
diff --git a/arch/arm/boards/dss11/Makefile b/arch/arm/boards/dss11/Makefile
index e11fd5b692..d59545033d 100644
--- a/arch/arm/boards/dss11/Makefile
+++ b/arch/arm/boards/dss11/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c
index 6ce986fc39..41c2b10972 100644
--- a/arch/arm/boards/dss11/init.c
+++ b/arch/arm/boards/dss11/init.c
@@ -7,20 +7,19 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/mtd/nand.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_rstc.h>
 #include <linux/clk.h>
 
 static struct atmel_nand_data nand_pdata = {
diff --git a/arch/arm/boards/dss11/lowlevel.c b/arch/arm/boards/dss11/lowlevel.c
index 7f52f824df..be2675369c 100644
--- a/arch/arm/boards/dss11/lowlevel.c
+++ b/arch/arm/boards/dss11/lowlevel.c
@@ -7,14 +7,12 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9260.h>
+#include <mach/at91/hardware.h>
 
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9260.h>
-#include <mach/hardware.h>
-
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_dss11, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/duckbill/Makefile b/arch/arm/boards/duckbill/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/duckbill/Makefile
+++ b/arch/arm/boards/duckbill/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/duckbill/board.c b/arch/arm/boards/duckbill/board.c
index dd22c81566..edb9320f0e 100644
--- a/arch/arm/boards/duckbill/board.c
+++ b/arch/arm/boards/duckbill/board.c
@@ -11,14 +11,13 @@
 #include <io.h>
 #include <net.h>
 
-#include <mach/clock.h>
-#include <mach/imx-regs.h>
-#include <mach/iomux-imx28.h>
-#include <mach/iomux.h>
-#include <mach/ocotp.h>
-#include <mach/devices.h>
-#include <mach/usb.h>
-#include <usb/fsl_usb2.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/iomux-imx28.h>
+#include <mach/mxs/iomux.h>
+#include <mach/mxs/ocotp.h>
+#include <mach/mxs/devices.h>
+#include <mach/mxs/usb.h>
+#include <linux/usb/fsl_usb2.h>
 
 #include <asm/armlinux.h>
 #include <asm/mmu.h>
diff --git a/arch/arm/boards/duckbill/lowlevel.c b/arch/arm/boards/duckbill/lowlevel.c
index 22987a6cdb..71862ec4b7 100644
--- a/arch/arm/boards/duckbill/lowlevel.c
+++ b/arch/arm/boards/duckbill/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define pr_fmt(fmt) "I2SE Duckbill: " fmt
 #define DEBUG
 
@@ -5,11 +7,11 @@
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx28-regs.h>
-#include <mach/init.h>
+#include <mach/mxs/imx28-regs.h>
+#include <mach/mxs/init.h>
 #include <io.h>
 #include <debug_ll.h>
-#include <mach/iomux.h>
+#include <mach/mxs/iomux.h>
 #include <stmp-device.h>
 
 extern char __dtb_imx28_duckbill_start[];
diff --git a/arch/arm/boards/ebv-socrates/Makefile b/arch/arm/boards/ebv-socrates/Makefile
index 8c927fe291..ea898309d7 100644
--- a/arch/arm/boards/ebv-socrates/Makefile
+++ b/arch/arm/boards/ebv-socrates/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += lowlevel.o board.o
 pbl-y += lowlevel.o
diff --git a/arch/arm/boards/ebv-socrates/board.c b/arch/arm/boards/ebv-socrates/board.c
index 965150f9a3..79085a5bb5 100644
--- a/arch/arm/boards/ebv-socrates/board.c
+++ b/arch/arm/boards/ebv-socrates/board.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <types.h>
 #include <driver.h>
@@ -11,7 +13,7 @@
 #include <linux/sizes.h>
 #include <fcntl.h>
 #include <fs.h>
-#include <mach/cyclone5-regs.h>
+#include <mach/socfpga/cyclone5-regs.h>
 
 static int phy_fixup(struct phy_device *dev)
 {
diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
index 9a814cba79..a769ff5366 100644
--- a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <mach/cyclone5-scan-manager.h>
+#include <mach/socfpga/cyclone5-scan-manager.h>
 
 static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
 	0x00000000,
diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c
index 3f12ae806f..56b0f43a33 100644
--- a/arch/arm/boards/ebv-socrates/lowlevel.c
+++ b/arch/arm/boards/ebv-socrates/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include "sdram_config.h"
 #include "pinmux_config.c"
 #include "pll_config.h"
@@ -7,7 +9,7 @@
 #include "sequencer_auto_ac_init.c"
 #include "iocsr_config_cyclone5.c"
 
-#include <mach/lowlevel.h>
+#include <mach/socfpga/lowlevel.h>
 
 static inline void ledon(void)
 {
diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto.h b/arch/arm/boards/ebv-socrates/sequencer_auto.h
index 59aa9cf816..d52e19548a 100644
--- a/arch/arm/boards/ebv-socrates/sequencer_auto.h
+++ b/arch/arm/boards/ebv-socrates/sequencer_auto.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #define __RW_MGR_ac_mrs1 0x04
 #define __RW_MGR_ac_mrs3 0x06
 #define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C
diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
index 5b5196ad77..1a19310dcb 100644
--- a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
+++ b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 static const uint32_t ac_rom_init_size = 36;
 static const uint32_t ac_rom_init[36] =
 {
diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c b/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c
index e261ecb6c1..c818d725b8 100644
--- a/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c
+++ b/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 static const uint32_t inst_rom_init_size = 128;
 static const uint32_t inst_rom_init[128] =
 {
diff --git a/arch/arm/boards/ebv-socrates/sequencer_defines.h b/arch/arm/boards/ebv-socrates/sequencer_defines.h
index 1ebbc48011..bef98641aa 100644
--- a/arch/arm/boards/ebv-socrates/sequencer_defines.h
+++ b/arch/arm/boards/ebv-socrates/sequencer_defines.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef _SEQUENCER_DEFINES_H_
 #define _SEQUENCER_DEFINES_H_
 
diff --git a/arch/arm/boards/edb93xx/Makefile b/arch/arm/boards/edb93xx/Makefile
index eec5ed2658..be969bde20 100644
--- a/arch/arm/boards/edb93xx/Makefile
+++ b/arch/arm/boards/edb93xx/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 obj-y += edb93xx.o
 lwl-y += flash_cfg.o pll_cfg.o sdram_cfg.o
diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c
index 4b5db60216..a3fb14822a 100644
--- a/arch/arm/boards/edb93xx/edb93xx.c
+++ b/arch/arm/boards/edb93xx/edb93xx.c
@@ -6,12 +6,11 @@
 #include <environment.h>
 #include <fs.h>
 #include <init.h>
-#include <partition.h>
 #include <asm/armlinux.h>
 #include <io.h>
 #include <malloc.h>
-#include <generated/mach-types.h>
-#include <mach/ep93xx-regs.h>
+#include <asm/mach-types.h>
+#include <mach/ep93xx/ep93xx-regs.h>
 #include <platform_data/eth-ep93xx.h>
 #include "edb93xx.h"
 
diff --git a/arch/arm/boards/edb93xx/flash_cfg.c b/arch/arm/boards/edb93xx/flash_cfg.c
index 8400db69de..2c471c7721 100644
--- a/arch/arm/boards/edb93xx/flash_cfg.c
+++ b/arch/arm/boards/edb93xx/flash_cfg.c
@@ -4,7 +4,7 @@
 /* Flash setup for Cirrus edb93xx boards */
 
 #include <common.h>
-#include <mach/ep93xx-regs.h>
+#include <mach/ep93xx/ep93xx-regs.h>
 #include <io.h>
 
 #define SMC_BCR6_VALUE	(2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
diff --git a/arch/arm/boards/edb93xx/pll_cfg.h b/arch/arm/boards/edb93xx/pll_cfg.h
index b3258b5f7e..662c92337a 100644
--- a/arch/arm/boards/edb93xx/pll_cfg.h
+++ b/arch/arm/boards/edb93xx/pll_cfg.h
@@ -4,7 +4,7 @@
 /* PLL register values for Cirrus edb93xx boards */
 
 #include <config.h>
-#include <mach/ep93xx-regs.h>
+#include <mach/ep93xx/ep93xx-regs.h>
 
 #if defined(CONFIG_MACH_EDB9301)
 /*
diff --git a/arch/arm/boards/edb93xx/sdram_cfg.h b/arch/arm/boards/edb93xx/sdram_cfg.h
index e1f78443e4..ddb9e442ed 100644
--- a/arch/arm/boards/edb93xx/sdram_cfg.h
+++ b/arch/arm/boards/edb93xx/sdram_cfg.h
@@ -3,7 +3,7 @@
 // SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de>
 
 #include <config.h>
-#include <mach/ep93xx-regs.h>
+#include <mach/ep93xx/ep93xx-regs.h>
 
 #define SDRAM_BASE_ADDR		CONFIG_EP93XX_SDRAM_BANK0_BASE
 
diff --git a/arch/arm/boards/efika-mx-smartbook/Makefile b/arch/arm/boards/efika-mx-smartbook/Makefile
index 73d7b9696c..497da461ef 100644
--- a/arch/arm/boards/efika-mx-smartbook/Makefile
+++ b/arch/arm/boards/efika-mx-smartbook/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-efikasb
diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c
index bf58eff718..f5a3f3cec4 100644
--- a/arch/arm/boards/efika-mx-smartbook/board.c
+++ b/arch/arm/boards/efika-mx-smartbook/board.c
@@ -3,7 +3,6 @@
 
 #include <environment.h>
 #include <bootsource.h>
-#include <partition.h>
 #include <common.h>
 #include <envfs.h>
 #include <fcntl.h>
@@ -20,13 +19,13 @@
 
 #include <asm/armlinux.h>
 
-#include <mach/devices-imx51.h>
-#include <mach/imx51-regs.h>
-#include <mach/iomux-mx51.h>
-#include <mach/revision.h>
-#include <mach/generic.h>
-#include <mach/imx5.h>
-#include <mach/bbu.h>
+#include <mach/imx/devices-imx51.h>
+#include <mach/imx/imx51-regs.h>
+#include <mach/imx/iomux-mx51.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/bbu.h>
 
 #define GPIO_BACKLIGHT_POWER	IMX_GPIO_NR(4, 12)
 #define GPIO_BACKLIGHT_PWM	IMX_GPIO_NR(1, 2)
diff --git a/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg b/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg
index 60436e7e37..de28650519 100644
--- a/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg
+++ b/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx51
 loadaddr 0x90000000
 ivtofs 0x400
diff --git a/arch/arm/boards/efika-mx-smartbook/lowlevel.c b/arch/arm/boards/efika-mx-smartbook/lowlevel.c
index 3881678d85..cf2f145e74 100644
--- a/arch/arm/boards/efika-mx-smartbook/lowlevel.c
+++ b/arch/arm/boards/efika-mx-smartbook/lowlevel.c
@@ -1,9 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx5.h>
+#include <mach/imx/imx5.h>
 
 extern char __dtb_imx51_genesi_efika_sb_start[];
 
diff --git a/arch/arm/boards/element14-warp7/Makefile b/arch/arm/boards/element14-warp7/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/element14-warp7/Makefile
+++ b/arch/arm/boards/element14-warp7/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/element14-warp7/board.c b/arch/arm/boards/element14-warp7/board.c
index 9427b467d0..0013421df0 100644
--- a/arch/arm/boards/element14-warp7/board.c
+++ b/arch/arm/boards/element14-warp7/board.c
@@ -4,11 +4,10 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <mach/generic.h>
+#include <asm/mach-types.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
 
 static int warp7_devices_init(void)
diff --git a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg
index 798f2cbcb0..c17321ad3a 100644
--- a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg
+++ b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg
@@ -13,7 +13,7 @@ soc imx7
 loadaddr 0x80000000
 ivtofs 0x400
 
-#include <mach/imx7-ddr-regs.h>
+#include <mach/imx/imx7-ddr-regs.h>
 
 wm 32 0x30340004 0x4F400005
 
diff --git a/arch/arm/boards/element14-warp7/lowlevel.c b/arch/arm/boards/element14-warp7/lowlevel.c
index 6ca733a0be..c6ddfea5a4 100644
--- a/arch/arm/boards/element14-warp7/lowlevel.c
+++ b/arch/arm/boards/element14-warp7/lowlevel.c
@@ -1,12 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define DEBUG
 #include <io.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
+#include <mach/imx/debug_ll.h>
 
 extern char __dtb_imx7s_warp_start[];
 
diff --git a/arch/arm/boards/eltec-hipercam/Makefile b/arch/arm/boards/eltec-hipercam/Makefile
index 092c31d6b2..5678718188 100644
--- a/arch/arm/boards/eltec-hipercam/Makefile
+++ b/arch/arm/boards/eltec-hipercam/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
diff --git a/arch/arm/boards/eltec-hipercam/board.c b/arch/arm/boards/eltec-hipercam/board.c
index e192c4c2f5..b8ad17992c 100644
--- a/arch/arm/boards/eltec-hipercam/board.c
+++ b/arch/arm/boards/eltec-hipercam/board.c
@@ -4,7 +4,7 @@
 #include <common.h>
 #include <init.h>
 #include <bbu.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
 static int hipercam_init(void)
 {
diff --git a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg
index 5b422a7867..3a96910708 100644
--- a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg
+++ b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
diff --git a/arch/arm/boards/eltec-hipercam/lowlevel.c b/arch/arm/boards/eltec-hipercam/lowlevel.c
index 7baed55706..154c0e58f5 100644
--- a/arch/arm/boards/eltec-hipercam/lowlevel.c
+++ b/arch/arm/boards/eltec-hipercam/lowlevel.c
@@ -5,11 +5,12 @@
 #include <linux/sizes.h>
 #include <io.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/sections.h>
 #include <asm/mmu.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 
 static void setup_uart(void)
 {
diff --git a/arch/arm/boards/embedsky-e9/Makefile b/arch/arm/boards/embedsky-e9/Makefile
index 86afde47fb..116bbfb4c2 100644
--- a/arch/arm/boards/embedsky-e9/Makefile
+++ b/arch/arm/boards/embedsky-e9/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-e9
diff --git a/arch/arm/boards/embedsky-e9/board.c b/arch/arm/boards/embedsky-e9/board.c
index 0938a6d096..afc9e3d27e 100644
--- a/arch/arm/boards/embedsky-e9/board.c
+++ b/arch/arm/boards/embedsky-e9/board.c
@@ -13,26 +13,25 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/imx6-regs.h>
+#include <mach/imx/imx6-regs.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <linux/phy.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
 #include <net.h>
-#include <mach/imx6.h>
-#include <mach/devices-imx6.h>
-#include <mach/iomux-mx6.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/devices-imx6.h>
+#include <mach/imx/iomux-mx6.h>
 #include <spi/spi.h>
-#include <mach/spi.h>
-#include <mach/usb.h>
+#include <mach/imx/spi.h>
+#include <mach/imx/usb.h>
 #include <envfs.h>
 #include <bootsource.h>
 #include <bbu.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
 #define PHY_ID_RTL8211E	0x001cc915
 #define PHY_ID_MASK	0xffffffff
diff --git a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg
index d51dc17a12..19e0039980 100644
--- a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg
+++ b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x27800000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/embedsky-e9/lowlevel.c b/arch/arm/boards/embedsky-e9/lowlevel.c
index 845c4ec90c..fddc88df52 100644
--- a/arch/arm/boards/embedsky-e9/lowlevel.c
+++ b/arch/arm/boards/embedsky-e9/lowlevel.c
@@ -1,6 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
diff --git a/arch/arm/boards/embest-marsboard/Makefile b/arch/arm/boards/embest-marsboard/Makefile
index ef5219444c..eaa6ace2f4 100644
--- a/arch/arm/boards/embest-marsboard/Makefile
+++ b/arch/arm/boards/embest-marsboard/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-mars
diff --git a/arch/arm/boards/embest-marsboard/board.c b/arch/arm/boards/embest-marsboard/board.c
index 66893434c2..1a5e5a8491 100644
--- a/arch/arm/boards/embest-marsboard/board.c
+++ b/arch/arm/boards/embest-marsboard/board.c
@@ -8,8 +8,10 @@
 #include <common.h>
 #include <init.h>
 #include <envfs.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
+#include <linux/mdio.h>
 #include <linux/phy.h>
+#include <deep-probe.h>
 
 static int ar8035_phy_fixup(struct phy_device *dev)
 {
@@ -18,37 +20,22 @@ static int ar8035_phy_fixup(struct phy_device *dev)
 	/* Ar803x phy SmartEEE feature cause link status generates glitch,
 	 * which cause ethernet link down/up issue, so disable SmartEEE
 	 */
-	phy_write(dev, 0xd, 0x3);
-	phy_write(dev, 0xe, 0x805d);
-	phy_write(dev, 0xd, 0x4003);
+	val = phy_read_mmd(dev, MDIO_MMD_PCS, 0x805d);
+	phy_write(dev, MII_MMD_DATA, val & ~(1 << 8));
 
-	val = phy_read(dev, 0xe);
-	phy_write(dev, 0xe, val & ~(1 << 8));
+	val = phy_read_mmd(dev, MDIO_MMD_PCS, 0x4003);
+	phy_write(dev, MII_MMD_DATA, val & ~(1 << 8));
 
-	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(dev, 0xd, 0x7);
-	phy_write(dev, 0xe, 0x8016);
-	phy_write(dev, 0xd, 0x4007);
-
-	val = phy_read(dev, 0xe);
+	val = phy_read_mmd(dev, MDIO_MMD_PCS, 0x4007);
 	val &= 0xffe3;
 	val |= 0x18;
-	phy_write(dev, 0xe, val);
-
-	/* introduce tx clock delay */
-	phy_write(dev, 0x1d, 0x5);
-	val = phy_read(dev, 0x1e);
-	val |= 0x0100;
-	phy_write(dev, 0x1e, val);
+	phy_write(dev, MII_MMD_DATA, val);
 
 	return 0;
 }
 
-static int marsboard_device_init(void)
+static int marsboard_device_init(struct device *dev)
 {
-	if (!of_machine_is_compatible("embest,imx6q-marsboard"))
-		return 0;
-
 	barebox_set_hostname("marsboard");
 
 	phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
@@ -60,4 +47,16 @@ static int marsboard_device_init(void)
 
 	return 0;
 }
-device_initcall(marsboard_device_init);
+
+static const struct of_device_id marsboard_of_match[] = {
+	{ .compatible = "embest,imx6q-marsboard" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(marsboard_of_match);
+
+static struct driver marsboard_driver = {
+	.name = "board-mars",
+	.probe = marsboard_device_init,
+	.of_compatible = marsboard_of_match,
+};
+postcore_platform_driver(marsboard_driver);
diff --git a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg
index afc95d9bd9..5cf7201e88 100644
--- a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg
+++ b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
diff --git a/arch/arm/boards/embest-marsboard/lowlevel.c b/arch/arm/boards/embest-marsboard/lowlevel.c
index 9e20a2ec06..84378c00f2 100644
--- a/arch/arm/boards/embest-marsboard/lowlevel.c
+++ b/arch/arm/boards/embest-marsboard/lowlevel.c
@@ -6,10 +6,11 @@
 #include <common.h>
 #include <io.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx6.h>
-#include <mach/esdctl.h>
-#include <mach/iomux-mx6.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/iomux-mx6.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 
 static inline void setup_uart(void)
 {
diff --git a/arch/arm/boards/embest-riotboard/Makefile b/arch/arm/boards/embest-riotboard/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/embest-riotboard/Makefile
+++ b/arch/arm/boards/embest-riotboard/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/embest-riotboard/board.c b/arch/arm/boards/embest-riotboard/board.c
index 2e0cc9f0ab..ebaff48388 100644
--- a/arch/arm/boards/embest-riotboard/board.c
+++ b/arch/arm/boards/embest-riotboard/board.c
@@ -10,59 +10,35 @@
 #include <envfs.h>
 #include <gpio.h>
 #include <init.h>
-#include <mach/generic.h>
-#include <mach/imx6-regs.h>
-#include <mach/imx6.h>
-#include <mach/bbu.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/bbu.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
 #include <linux/sizes.h>
 #include <linux/phy.h>
+#include <deep-probe.h>
 
-static int ar8035_phy_fixup(struct phy_device *dev)
+static int riotboard_probe(struct device *dev)
 {
-	u16 val;
-
-	/* Ar803x phy SmartEEE feature cause link status generates glitch,
-	 * which cause ethernet link down/up issue, so disable SmartEEE
-	 */
-	phy_write(dev, 0xd, 0x3);
-	phy_write(dev, 0xe, 0x805d);
-	phy_write(dev, 0xd, 0x4003);
-
-	val = phy_read(dev, 0xe);
-	phy_write(dev, 0xe, val & ~(1 << 8));
-
-	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(dev, 0xd, 0x7);
-	phy_write(dev, 0xe, 0x8016);
-	phy_write(dev, 0xd, 0x4007);
-
-	val = phy_read(dev, 0xe);
-	val &= 0xffe3;
-	val |= 0x18;
-	phy_write(dev, 0xe, val);
-
-	/* introduce tx clock delay */
-	phy_write(dev, 0x1d, 0x5);
-	val = phy_read(dev, 0x1e);
-	val |= 0x0100;
-	phy_write(dev, 0x1e, val);
-
-	return 0;
-}
-
-static int riotboard_device_init(void)
-{
-	if (!of_machine_is_compatible("riot,imx6s-riotboard"))
-		return 0;
-
-	phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
-
 	imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.barebox",
 			BBU_HANDLER_FLAG_DEFAULT);
+	imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc2", 0);
 
 	barebox_set_hostname("riotboard");
 
 	return 0;
 }
-device_initcall(riotboard_device_init);
+
+static const struct of_device_id riotboard_of_match[] = {
+	{ .compatible = "riot,imx6s-riotboard"},
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(riotboard_of_match);
+
+static struct driver riotboard_board_driver = {
+	.name = "board-riotboard",
+	.probe = riotboard_probe,
+	.of_compatible = DRV_OF_COMPAT(riotboard_of_match),
+};
+device_platform_driver(riotboard_board_driver);
diff --git a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg
index bc30e4c387..5464e2461d 100644
--- a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg
+++ b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x20000000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/embest-riotboard/lowlevel.c b/arch/arm/boards/embest-riotboard/lowlevel.c
index 07f669fc03..9ea92f5091 100644
--- a/arch/arm/boards/embest-riotboard/lowlevel.c
+++ b/arch/arm/boards/embest-riotboard/lowlevel.c
@@ -1,4 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <linux/sizes.h>
 #include <io.h>
@@ -7,7 +10,7 @@
 #include <asm/sections.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <mach/imx6.h>
+#include <mach/imx/imx6.h>
 
 extern char __dtb_imx6s_riotboard_start[];
 
diff --git a/arch/arm/boards/enclustra-aa1/Makefile b/arch/arm/boards/enclustra-aa1/Makefile
new file mode 100644
index 0000000000..5678718188
--- /dev/null
+++ b/arch/arm/boards/enclustra-aa1/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/enclustra-aa1/board.c b/arch/arm/boards/enclustra-aa1/board.c
new file mode 100644
index 0000000000..de886f21aa
--- /dev/null
+++ b/arch/arm/boards/enclustra-aa1/board.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <bbu.h>
+#include <mach/socfpga/arria10-system-manager.h>
+
+static int aa1_init(void)
+{
+	int pbl_index = 0;
+	uint32_t flag_barebox1 = 0;
+	uint32_t flag_barebox2 = 0;
+
+	if (!of_machine_is_compatible("enclustra,mercury-aa1"))
+		return 0;
+
+	pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD);
+
+	pr_debug("Current barebox instance %d\n", pbl_index);
+
+	switch (pbl_index) {
+	case 0:
+		flag_barebox1 |= BBU_HANDLER_FLAG_DEFAULT;
+		break;
+	case 1:
+		flag_barebox2 |= BBU_HANDLER_FLAG_DEFAULT;
+		break;
+	};
+
+	bbu_register_std_file_update("emmc-barebox1-xload", flag_barebox1,
+					"/dev/mmc0.barebox1-xload",
+					filetype_socfpga_xload);
+
+	bbu_register_std_file_update("emmc-barebox1", 0,
+					"/dev/mmc0.barebox1",
+					filetype_arm_barebox);
+
+	bbu_register_std_file_update("emmc-barebox2-xload", flag_barebox2,
+					"/dev/mmc0.barebox2-xload",
+					filetype_socfpga_xload);
+
+	bbu_register_std_file_update("emmc-barebox2", 0,
+					"/dev/mmc0.barebox2",
+					filetype_arm_barebox);
+	return 0;
+}
+postcore_initcall(aa1_init);
diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c
new file mode 100644
index 0000000000..ba4d562e5f
--- /dev/null
+++ b/arch/arm/boards/enclustra-aa1/lowlevel.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <io.h>
+#include <memory.h>
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/unaligned.h>
+#include <debug_ll.h>
+#include <pbl.h>
+#include <mach/socfpga/arria10-sdram.h>
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-reset-manager.h>
+#include <mach/socfpga/arria10-clock-manager.h>
+#include <mach/socfpga/arria10-pinmux.h>
+#include <mach/socfpga/arria10-fpga.h>
+#include <mach/socfpga/init.h>
+#include "pll-config-arria10.c"
+#include "pinmux-config-arria10.c"
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/init.h>
+
+#define BAREBOX_PART 0
+// the bitstream is located in the second partition in the partition table
+#define BITSTREAM_PART 1
+#define BAREBOX1_OFFSET    SZ_1M
+#define BAREBOX2_OFFSET    (BAREBOX1_OFFSET + SZ_1M)
+// Offset from the start of the second partition on the eMMC.
+#define BITSTREAM1_OFFSET  0x0
+#define BITSTREAM2_OFFSET  (BITSTREAM1_OFFSET + SZ_32M)
+
+extern char __dtb_z_socfpga_arria10_mercury_aa1_start[];
+
+#define ARRIA10_STACKTOP   (ARRIA10_OCRAM_ADDR + SZ_256K)
+
+ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_xload, ARRIA10_STACKTOP, r0, r1, r2)
+{
+	int pbl_index = 0;
+	int barebox = 0;
+	int bitstream = 0;
+
+	arm_cpu_lowlevel_init();
+	arria10_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+
+	setup_c();
+
+	arria10_init(&mainpll_cfg, &perpll_cfg, pinmux);
+
+	arria10_prepare_mmc(BAREBOX_PART, BITSTREAM_PART);
+
+	pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD);
+
+	/* Allow booting from both PBL0 and PBL1 to allow atomic updates.
+	 * Bitstreams redundant too and expected to reside in the second
+	 * partition.
+	 * There is a fixed relation between the PBL/barebox instance and its
+	 * bitstream location (offset) that requires to update them together */
+	switch (pbl_index) {
+	case 0:
+		barebox = BAREBOX1_OFFSET;
+		bitstream = BITSTREAM1_OFFSET;
+		break;
+	case 1:
+		barebox = BAREBOX2_OFFSET;
+		bitstream = BITSTREAM2_OFFSET;
+		break;
+	case 2:
+	case 3:
+		/* Left blank for future extension */
+		break;
+	default:
+		/* If we get an undefined pbl index, use the first and hope for the best.
+		 * We could bail out, but user wouldn't see anything on the console
+		 * and wouldn't know what happend anyway. */
+		barebox = BAREBOX1_OFFSET;
+		bitstream = BITSTREAM1_OFFSET;
+		break;
+	}
+
+	arria10_load_fpga(bitstream, SZ_32M);
+
+	arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
+
+	arria10_ddr_calibration_sequence();
+
+	arria10_start_image(barebox);
+}
+
+ENTRY_FUNCTION(start_socfpga_aa1, r0, r1, r2)
+{
+	void *fdt;
+
+	fdt = __dtb_z_socfpga_arria10_mercury_aa1_start + get_runtime_offset();
+
+	barebox_arm_entry(0x0, SZ_2G, fdt);
+}
+
+ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_bringup, ARRIA10_STACKTOP, r0, r1, r2)
+{
+	void *fdt;
+
+	arm_cpu_lowlevel_init();
+	arria10_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	arria10_init(&mainpll_cfg, &perpll_cfg, pinmux);
+
+	/* wait for fpga_usermode */
+	a10_wait_for_usermode(0x1000000);
+
+	arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
+
+	arria10_ddr_calibration_sequence();
+
+	fdt = __dtb_z_socfpga_arria10_mercury_aa1_start + get_runtime_offset();
+
+	barebox_arm_entry(0x0, SZ_2G, fdt);
+}
diff --git a/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c b/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c
new file mode 100644
index 0000000000..fea88e3336
--- /dev/null
+++ b/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <mach/socfpga/arria10-pinmux.h>
+
+static uint32_t pinmux[] = {
+[arria10_pinmux_shared_io_q3_7]	   = 0,
+[arria10_pinmux_shared_io_q3_6]	   = 15,
+[arria10_pinmux_shared_io_q3_5]	   = 15,
+[arria10_pinmux_shared_io_q3_4]	   = 15,
+[arria10_pinmux_shared_io_q3_3]	   = 15,
+[arria10_pinmux_shared_io_q3_2]	   = 15,
+[arria10_pinmux_shared_io_q3_1]	   = 15,
+[arria10_pinmux_shared_io_q2_12]   = 4,
+[arria10_pinmux_shared_io_q2_11]   = 4,
+[arria10_pinmux_shared_io_q2_10]   = 4,
+[arria10_pinmux_shared_io_q2_8]	   = 4,
+[arria10_pinmux_shared_io_q2_9]	   = 4,
+[arria10_pinmux_shared_io_q2_7]	   = 4,
+[arria10_pinmux_shared_io_q2_6]	   = 4,
+[arria10_pinmux_shared_io_q2_5]	   = 4,
+[arria10_pinmux_shared_io_q2_4]	   = 4,
+[arria10_pinmux_shared_io_q2_3]	   = 4,
+[arria10_pinmux_shared_io_q2_2]	   = 4,
+[arria10_pinmux_shared_io_q2_1]	   = 4,
+[arria10_pinmux_shared_io_q1_12]   = 8,
+[arria10_pinmux_shared_io_q1_10]   = 8,
+[arria10_pinmux_shared_io_q1_11]   = 8,
+[arria10_pinmux_shared_io_q1_9]	   = 8,
+[arria10_pinmux_shared_io_q1_8]	   = 8,
+[arria10_pinmux_shared_io_q1_7]	   = 8,
+[arria10_pinmux_shared_io_q1_6]	   = 8,
+[arria10_pinmux_shared_io_q1_5]	   = 8,
+[arria10_pinmux_shared_io_q1_4]	   = 8,
+[arria10_pinmux_shared_io_q1_3]	   = 8,
+[arria10_pinmux_shared_io_q1_2]	   = 8,
+[arria10_pinmux_shared_io_q1_1]	   = 8,
+[arria10_pinmux_shared_io_q4_12]   = 15,
+[arria10_pinmux_shared_io_q4_11]   = 15,
+[arria10_pinmux_shared_io_q4_10]   = 3,
+[arria10_pinmux_shared_io_q4_9]	   = 3,
+[arria10_pinmux_shared_io_q4_8]	   = 3,
+[arria10_pinmux_shared_io_q4_7]	   = 3,
+[arria10_pinmux_shared_io_q4_6]	   = 10,
+[arria10_pinmux_shared_io_q4_4]	   = 10,
+[arria10_pinmux_shared_io_q4_5]	   = 10,
+[arria10_pinmux_shared_io_q4_3]	   = 10,
+[arria10_pinmux_shared_io_q4_2]	   = 10,
+[arria10_pinmux_shared_io_q4_1]	   = 10,
+[arria10_pinmux_shared_io_q3_12]   = 1,
+[arria10_pinmux_shared_io_q3_11]   = 1,
+[arria10_pinmux_shared_io_q3_10]   = 15,
+[arria10_pinmux_shared_io_q3_9]	   = 15,
+[arria10_pinmux_shared_io_q3_8]	   = 0,
+[arria10_pinmux_dedicated_io_7]	   = 8,
+[arria10_pinmux_dedicated_io_8]	   = 8,
+[arria10_pinmux_dedicated_io_9]	   = 8,
+[arria10_pinmux_dedicated_io_10]   = 15,
+[arria10_pinmux_dedicated_io_11]   = 15,
+[arria10_pinmux_dedicated_io_12]   = 8,
+[arria10_pinmux_dedicated_io_13]   = 8,
+[arria10_pinmux_dedicated_io_14]   = 8,
+[arria10_pinmux_dedicated_io_15]   = 8,
+[arria10_pinmux_dedicated_io_16]   = 13,
+[arria10_pinmux_dedicated_io_17]   = 13,
+[arria10_pinmux_dedicated_io_4]	   = 8,
+[arria10_pinmux_dedicated_io_5]	   = 8,
+[arria10_pinmux_dedicated_io_6]	   = 8,
+[arria10_pincfg_dedicated_io_bank] = 0x101,
+[arria10_pincfg_dedicated_io_1]	   = 0xb080a,
+[arria10_pincfg_dedicated_io_2]	   = 0xb080a,
+[arria10_pincfg_dedicated_io_3]	   = 0xb080a,
+[arria10_pincfg_dedicated_io_4]	   = 0xa282a,
+[arria10_pincfg_dedicated_io_5]	   = 0xa282a,
+[arria10_pincfg_dedicated_io_6]	   = 0x8282a,
+[arria10_pincfg_dedicated_io_7]	   = 0xa282a,
+[arria10_pincfg_dedicated_io_8]	   = 0xa282a,
+[arria10_pincfg_dedicated_io_9]	   = 0xa282a,
+[arria10_pincfg_dedicated_io_10]   = 0xa280a,
+[arria10_pincfg_dedicated_io_11]   = 0xa280a,
+[arria10_pincfg_dedicated_io_12]   = 0xa280a,
+[arria10_pincfg_dedicated_io_13]   = 0xa280a,
+[arria10_pincfg_dedicated_io_14]   = 0xa280a,
+[arria10_pincfg_dedicated_io_15]   = 0xa280a,
+[arria10_pincfg_dedicated_io_16]   = 0x8282a,
+[arria10_pincfg_dedicated_io_17]   = 0xa280a,
+[arria10_pinmux_rgmii0_usefpga]	   = 0,
+[arria10_pinmux_rgmii1_usefpga]	   = 0,
+[arria10_pinmux_rgmii2_usefpga]	   = 0,
+[arria10_pinmux_nand_usefpga]	   = 0,
+[arria10_pinmux_qspi_usefpga]	   = 0,
+[arria10_pinmux_sdmmc_usefpga]	   = 0,
+[arria10_pinmux_spim0_usefpga]	   = 0,
+[arria10_pinmux_spim1_usefpga]	   = 0,
+[arria10_pinmux_spis0_usefpga]	   = 0,
+[arria10_pinmux_spis1_usefpga]	   = 0,
+[arria10_pinmux_uart0_usefpga]	   = 0,
+[arria10_pinmux_uart1_usefpga]	   = 0,
+[arria10_pinmux_i2c0_usefpga]	   = 0,
+[arria10_pinmux_i2c1_usefpga]	   = 0,
+[arria10_pinmux_i2cemac0_usefpga]  = 0,
+[arria10_pinmux_i2cemac1_usefpga]  = 0,
+[arria10_pinmux_i2cemac2_usefpga]  = 0,
+};
+
diff --git a/arch/arm/boards/enclustra-aa1/pll-config-arria10.c b/arch/arm/boards/enclustra-aa1/pll-config-arria10.c
new file mode 100644
index 0000000000..8178550d7d
--- /dev/null
+++ b/arch/arm/boards/enclustra-aa1/pll-config-arria10.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <mach/socfpga/arria10-clock-manager.h>
+
+static struct arria10_mainpll_cfg mainpll_cfg = {
+	.cntr15clk_cnt	   = 900,
+	.cntr2clk_cnt	   = 900,
+	.cntr3clk_cnt	   = 900,
+	.cntr4clk_cnt	   = 900,
+	.cntr5clk_cnt	   = 900,
+	.cntr6clk_cnt	   = 7,
+	.cntr7clk_cnt	   = 15,
+	.cntr7clk_src	   = 0,
+	.cntr8clk_cnt	   = 7,
+	.cntr9clk_cnt	   = 900,
+	.cntr9clk_src	   = 0,
+	.mpuclk_cnt	   = 0,
+	.mpuclk_src	   = 0,
+	.nocclk_cnt	   = 0,
+	.nocclk_src	   = 0,
+	.nocdiv_csatclk	   = 0,
+	.nocdiv_cspdbgclk  = 1,
+	.nocdiv_cstraceclk = 0,
+	.nocdiv_l4mainclk  = 0,
+	.nocdiv_l4mpclk	   = 1,
+	.nocdiv_l4spclk	   = 2,
+	.vco0_psrc	   = 0,
+	.vco1_denom	   = 32,
+	.vco1_numer	   = 1584,
+	.mpuclk		   = 0x3840001,
+	.nocclk		   = 0x3840007,
+};
+
+static struct arria10_perpll_cfg perpll_cfg = {
+	.cntr2clk_cnt	   = 5,
+	.cntr2clk_src	   = 1,
+	.cntr3clk_cnt	   = 900,
+	.cntr3clk_src	   = 1,
+	.cntr4clk_cnt	   = 14,
+	.cntr4clk_src	   = 1,
+	.cntr5clk_cnt	   = 374,
+	.cntr5clk_src	   = 1,
+	.cntr6clk_cnt	   = 900,
+	.cntr6clk_src	   = 0,
+	.cntr7clk_cnt	   = 900,
+	.cntr8clk_cnt	   = 900,
+	.cntr8clk_src	   = 0,
+	.cntr9clk_cnt	   = 900,
+	.emacctl_emac0sel  = 0,
+	.emacctl_emac1sel  = 0,
+	.emacctl_emac2sel  = 0,
+	.gpiodiv_gpiodbclk = 32000,
+	.vco0_psrc	   = 0,
+	.vco1_denom	   = 32,
+	.vco1_numer	   = 1485,
+};
diff --git a/arch/arm/boards/eukrea_cpuimx25/Makefile b/arch/arm/boards/eukrea_cpuimx25/Makefile
deleted file mode 100644
index 1d2171fbdc..0000000000
--- a/arch/arm/boards/eukrea_cpuimx25/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2010 Eric Bénard <eric@eukrea.com>, Eukrea Electromatique
-
-obj-y += eukrea_cpuimx25.o
-lwl-y += lowlevel.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-eukrea_cpuimx25
diff --git a/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/bin/init_board b/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/bin/init_board
deleted file mode 100644
index 8f4151c357..0000000000
--- a/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/bin/init_board
+++ /dev/null
@@ -1,41 +0,0 @@
-#!/bin/sh
-
-if [ -f /env/logo.bmp ]; then
-	splash /env/logo.bmp
-	fb0.enable=1
-elif [ -f /env/logo.bmp.lzo ]; then
-	uncompress /env/logo.bmp.lzo /logo.bmp
-	splash /logo.bmp
-	fb0.enable=1
-fi
-
-if [ ! -z $use_dfu ]; then
-	gpio_get_value 82
-	if [ $? -eq 0 ]; then
-		gpio_set_value 83 0
-		usbserial
-		timeout -s -a 2
-		gpio_get_value 82
-		if [ $? -eq 0 ]; then
-			usbserial -d
-			dfu -V 0x1234 -P 0x1234 /dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.root.bb(root)r
-			gpio_get_value 82
-			if [ $? -eq 0 ]; then
-				usbserial
-				autoboot_timeout=60
-			else
-				reset
-			fi
-		else
-			autoboot_timeout=28
-		fi
-	fi
-fi
-
-if [ -z $eth0.ethaddr ]; then
-	while [ -z $eth0.ethaddr ]; do
-		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-	done
-	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-	saveenv
-fi
diff --git a/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/config b/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/config
deleted file mode 100644
index da19677574..0000000000
--- a/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/config
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/bin/sh
-
-# otg port mode : can be 'host' or 'device'
-otg_mode="device"
-# video : can be CMO-QVGA, URT-WVGA, DVI-VGA or DVI-SVGA
-video="CMO-QVGA"
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=none
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=nand
-# can be either 'net', 'nand' or 'initrd'
-rootfs_loc=nand
-
-# rootfs
-rootfs_type=ubifs
-rootfsimage=${global.hostname}/rootfs.$rootfs_type
-
-# kernel
-kernelimage=${global.hostname}/uImage-${global.hostname}.bin
-
-# barebox and it's env
-bareboximage=${global.hostname}/barebox-${global.hostname}.bin
-bareboxenvimage=${global.hostname}/bareboxenv-${global.hostname}.bin
-
-nfsroot="$eth0.serverip:/srv/nfs/${global.hostname}"
-
-autoboot_timeout=1
-
-bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=imxfb:$video"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
-rootfs_mtdblock_nand=3
-nand_device="mxc_nand"
-ubiroot="${global.hostname}-rootfs"
-device_type="nand"
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
deleted file mode 100644
index 494b89f53f..0000000000
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ /dev/null
@@ -1,219 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-// SPDX-FileCopyrightText: 2010 Eric Bénard <eric@eukrea.com>, Eukrea Electromatique
-
-#include <common.h>
-#include <init.h>
-#include <driver.h>
-#include <gpio.h>
-#include <environment.h>
-#include <mach/imx25-regs.h>
-#include <asm/armlinux.h>
-#include <asm/barebox-arm.h>
-#include <asm/sections.h>
-#include <io.h>
-#include <asm/mmu.h>
-#include <led.h>
-#include <envfs.h>
-
-#include <partition.h>
-#include <generated/mach-types.h>
-#include <mach/imx-nand.h>
-#include <mach/imxfb.h>
-#include <mach/iim.h>
-#include <platform_data/eth-fec.h>
-#include <nand.h>
-#include <mach/iomux-mx25.h>
-#include <i2c/i2c.h>
-#include <usb/fsl_usb2.h>
-#include <mach/usb.h>
-#include <mach/devices-imx25.h>
-#include <asm/barebox-arm-head.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type	= PHY_INTERFACE_MODE_RMII,
-	.phy_addr	= 0,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.width	= 1,
-	.hw_ecc	= 1,
-};
-
-static struct fb_videomode imxfb_mode = {
-	.name		= "CMO-QVGA",
-	.refresh	= 60,
-	.xres		= 320,
-	.yres		= 240,
-	.pixclock	= KHZ2PICOS(6500),
-	.hsync_len	= 30,
-	.left_margin	= 38,
-	.right_margin	= 20,
-	.vsync_len	= 3,
-	.upper_margin	= 15,
-	.lower_margin	= 4,
-};
-
-static struct imx_fb_platform_data eukrea_cpuimx25_fb_data = {
-	.mode		= &imxfb_mode,
-	.num_modes	= 1,
-	.pwmr		= 0x00A903FF,
-	.lscr1		= 0x00120300,
-	.dmacr		= 0x80040060,
-	.pcr		= 0xCAD08B80,
-	.bpp		= 16,
-};
-
-struct gpio_led led0 = {
-	.gpio = 2 * 32 + 19,
-	.active_low = 1,
-};
-
-static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
-	MX25_PAD_FEC_MDC__FEC_MDC,
-	MX25_PAD_FEC_MDIO__FEC_MDIO,
-	MX25_PAD_FEC_RDATA0__FEC_RDATA0,
-	MX25_PAD_FEC_RDATA1__FEC_RDATA1,
-	MX25_PAD_FEC_RX_DV__FEC_RX_DV,
-	MX25_PAD_FEC_TDATA0__FEC_TDATA0,
-	MX25_PAD_FEC_TDATA1__FEC_TDATA1,
-	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
-	MX25_PAD_FEC_TX_EN__FEC_TX_EN,
-	/* UART1 */
-	MX25_PAD_UART1_RXD__UART1_RXD,
-	MX25_PAD_UART1_TXD__UART1_TXD,
-	MX25_PAD_UART1_RTS__UART1_RTS,
-	MX25_PAD_UART1_CTS__UART1_CTS,
-	/* LCDC */
-	MX25_PAD_LD0__LD0,
-	MX25_PAD_LD1__LD1,
-	MX25_PAD_LD2__LD2,
-	MX25_PAD_LD3__LD3,
-	MX25_PAD_LD4__LD4,
-	MX25_PAD_LD5__LD5,
-	MX25_PAD_LD6__LD6,
-	MX25_PAD_LD7__LD7,
-	MX25_PAD_LD8__LD8,
-	MX25_PAD_LD9__LD9,
-	MX25_PAD_LD10__LD10,
-	MX25_PAD_LD11__LD11,
-	MX25_PAD_LD12__LD12,
-	MX25_PAD_LD13__LD13,
-	MX25_PAD_LD14__LD14,
-	MX25_PAD_LD15__LD15,
-	MX25_PAD_GPIO_E__LD16,
-	MX25_PAD_GPIO_F__LD17,
-	MX25_PAD_LSCLK__LSCLK,
-	MX25_PAD_OE_ACD__OE_ACD,
-	MX25_PAD_VSYNC__VSYNC,
-	MX25_PAD_HSYNC__HSYNC,
-	/* BACKLIGHT CONTROL */
-	MX25_PAD_PWM__GPIO_1_26,
-	/* I2C */
-	MX25_PAD_I2C1_CLK__I2C1_CLK,
-	MX25_PAD_I2C1_DAT__I2C1_DAT,
-	/* SDCard */
-	MX25_PAD_SD1_CLK__SD1_CLK,
-	MX25_PAD_SD1_CMD__SD1_CMD,
-	MX25_PAD_SD1_DATA0__SD1_DATA0,
-	MX25_PAD_SD1_DATA1__SD1_DATA1,
-	MX25_PAD_SD1_DATA2__SD1_DATA2,
-	MX25_PAD_SD1_DATA3__SD1_DATA3,
-	/* LED */
-	MX25_PAD_POWER_FAIL__GPIO_3_19,
-	/* SWITCH */
-	MX25_PAD_VSTBY_ACK__GPIO_3_18,
-};
-
-#ifdef CONFIG_USB
-#ifndef CONFIG_USB_GADGET
-struct imxusb_platformdata otg_pdata = {
-	.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
-	.mode = USB_DR_MODE_HOST,
-	.phymode = USBPHY_INTERFACE_MODE_UTMI,
-};
-#endif
-
-struct imxusb_platformdata hs_pdata = {
-	.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN,
-	.mode = USB_DR_MODE_HOST,
-};
-#endif
-
-#ifdef CONFIG_USB_GADGET
-static struct fsl_usb2_platform_data usb_pdata = {
-	.operating_mode	= FSL_USB2_DR_DEVICE,
-	.phy_mode	= FSL_USB2_PHY_UTMI,
-};
-#endif
-
-static int eukrea_cpuimx25_devices_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
-		ARRAY_SIZE(eukrea_cpuimx25_pads));
-
-	led_gpio_register(&led0);
-
-	imx25_iim_register_fec_ethaddr();
-	imx25_add_fec(&fec_info);
-
-	nand_info.width = 1;
-	imx25_add_nand(&nand_info);
-
-	devfs_add_partition("nand0", 0x00000, 0x40000,
-		DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-
-	devfs_add_partition("nand0", 0x40000, 0x20000,
-		DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-
-	/* enable LCD */
-	gpio_direction_output(26, 1);
-	gpio_set_value(26, 1);
-
-	/* LED : default OFF */
-	gpio_direction_output(2 * 32 + 19, 1);
-
-	/* Switch : input */
-	gpio_direction_input(2 * 32 + 18);
-
-	imx25_add_fb(&eukrea_cpuimx25_fb_data);
-
-#ifdef CONFIG_USB_GADGET
-	/* Workaround ENGcm09152 */
-	writel(readl(MX25_USB_OTG_BASE_ADDR + 0x608) | (1 << 23), MX25_USB_OTG_BASE_ADDR + 0x608);
-	add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX25_USB_OTG_BASE_ADDR, 0x200,
-			   IORESOURCE_MEM, &usb_pdata);
-#endif
-
-#ifdef CONFIG_USB
-#ifndef CONFIG_USB_GADGET
-	imx_add_usb((void *)MX25_USB_OTG_BASE_ADDR, 0, &otg_pdata);
-#endif
-	imx_add_usb((void *)MX25_USB_HS_BASE_ADDR, 1, &hs_pdata);
-#endif
-
-	imx25_add_mmc0(NULL);
-	imx25_add_i2c0(NULL);
-
-	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX25SD);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_eukrea_cpuimx25);
-
-	return 0;
-}
-
-device_initcall(eukrea_cpuimx25_devices_init);
-
-static int eukrea_cpuimx25_console_init(void)
-{
-	barebox_set_model("Eukrea CPUIMX25");
-	barebox_set_hostname("eukrea-cpuimx25");
-
-	imx25_add_uart0();
-	return 0;
-}
-
-console_initcall(eukrea_cpuimx25_console_init);
diff --git a/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg
deleted file mode 100644
index 129498ca85..0000000000
--- a/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg
+++ /dev/null
@@ -1,17 +0,0 @@
-soc imx25
-loadaddr 0x80000000
-ivtofs 0x400
-
-wm 32 0xb8001008 0x00000000
-wm 32 0xb8001010 0x00000004
-wm 32 0xb8001000 0x92100000
-wm 8 0x80000400 0x12344321
-wm 32 0xb8001000 0xa2100000
-wm 32 0x80000000 0x12344321
-wm 32 0x80000000 0x12344321
-wm 32 0xb8001000 0xb2100000
-wm 8 0x80000033 0xda
-wm 8 0x81000000 0xff
-wm 32 0xb8001000 0x82216080
-wm 32 0xb8001004 0x00295729
-wm 32 0x53f80008 0x20034000
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
deleted file mode 100644
index 93cd64d90f..0000000000
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-// SPDX-FileCopyrightText: 2010 Eric Bénard <eric@eukrea.com>, Eukrea Electromatique
-
-#include <common.h>
-#include <init.h>
-#include <mach/imx25-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <io.h>
-#include <mach/imx-nand.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/sections.h>
-#include <asm-generic/memory_layout.h>
-#include <asm/system.h>
-
-void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	uint32_t r;
-	register uint32_t loops = 0x20000;
-
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE);
-
-	/* restart the MPLL and wait until it's stable */
-	writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27),
-			MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
-	while (readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) & (1 << 27)) {};
-
-	/* Configure dividers and ARM clock source
-	 * 	ARM @ 400 MHz
-	 * 	AHB @ 133 MHz
-	 */
-	writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
-
-	/* Enable UART1 / FEC / */
-/*	writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0);
-	writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1);
-	writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2);*/
-
-	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	writel(0x77777777, 0x43f00000);
-	writel(0x77777777, 0x43f00004);
-	writel(0x77777777, 0x53f00000);
-	writel(0x77777777, 0x53f00004);
-
-	/* MAX (Multi-Layer AHB Crossbar Switch) setup
-	 * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
-	 */
-	writel(0x00002143, 0x43f04000);
-	writel(0x00002143, 0x43f04100);
-	writel(0x00002143, 0x43f04200);
-	writel(0x00002143, 0x43f04300);
-	writel(0x00002143, 0x43f04400);
-	/* SGPCR - always park on last master */
-	writel(0x10, 0x43f04010);
-	writel(0x10, 0x43f04110);
-	writel(0x10, 0x43f04210);
-	writel(0x10, 0x43f04310);
-	writel(0x10, 0x43f04410);
-	/* MGPCR - restore default values */
-	writel(0x0, 0x43f04800);
-	writel(0x0, 0x43f04900);
-	writel(0x0, 0x43f04a00);
-	writel(0x0, 0x43f04b00);
-	writel(0x0, 0x43f04c00);
-
-	/* Configure M3IF registers
-	 * M3IF Control Register (M3IFCTL) for MX25
-	 * MRRP[0] = LCDC           on priority list (1 << 0)  = 0x00000001
-	 * MRRP[1] = MAX1       not on priority list (0 << 1)  = 0x00000000
-	 * MRRP[2] = MAX0       not on priority list (0 << 2)  = 0x00000000
-	 * MRRP[3] = USB HOST   not on priority list (0 << 3)  = 0x00000000
-	 * MRRP[4] = SDMA       not on priority list (0 << 4)  = 0x00000000
-	 * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5)  = 0x00000000
-	 * MRRP[6] = SCMFBC     not on priority list (0 << 6)  = 0x00000000
-	 * MRRP[7] = CSI        not on priority list (0 << 7)  = 0x00000000
-	 *                                                       ----------
-	 *                                                       0x00000001
-	 */
-	writel(0x1, 0xb8003000);
-
-	/* Speed up NAND controller by adjusting the NFC divider */
-	r = readl(MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
-	r &= ~0xf;
-	r |= 0x1;
-	writel(r, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
-
-	/* Skip SDRAM initialization if we run from RAM */
-	r = get_pc();
-	if (r > 0x80000000 && r < 0x90000000)
-		goto out;
-
-	/* Init Mobile DDR */
-	writel(0x0000000E, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	writel(0x00000004, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	__asm__ volatile ("1:\n"
-			"subs %0, %1, #1\n"
-			"bne 1b":"=r" (loops):"0" (loops));
-
-	writel(0x0029572B, MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
-	writel(0x92210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400);
-	writel(0xA2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX25_CSD0_BASE_ADDR);
-	writeb(0xda, MX25_CSD0_BASE_ADDR);
-	writel(0xB2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33);
-	writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000);
-	writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-
-	if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND))
-		imx25_barebox_boot_nand_external();
-
-out:
-	imx25_barebox_entry(NULL);
-}
diff --git a/arch/arm/boards/eukrea_cpuimx27/Makefile b/arch/arm/boards/eukrea_cpuimx27/Makefile
deleted file mode 100644
index 2c3148abd0..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-lwl-y += lowlevel_init.o
-obj-y += eukrea_cpuimx27.o
diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/_update b/arch/arm/boards/eukrea_cpuimx27/env/bin/_update
deleted file mode 100644
index 014bce3512..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/env/bin/_update
+++ /dev/null
@@ -1,36 +0,0 @@
-#!/bin/sh
-
-if [ -z "$part" -o -z "$image" ]; then
-	echo "define \$part and \$image"
-	exit 1
-fi
-
-if [ ! -e "$part" ]; then
-	echo "Partition $part does not exist"
-	exit 1
-fi
-
-if [ $# = 1 ]; then
-	image=$1
-fi
-
-if [ x$ip = xdhcp ]; then
-	dhcp
-fi
-
-ping $eth0.serverip
-if [ $? -ne 0 ] ; then
-	echo "update aborted"
-	exit 1
-fi
-
-unprotect $part
-
-echo
-echo "erasing partition $part"
-erase $part
-
-echo
-echo "flashing $image to $part"
-echo
-tftp $image $part
diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot
deleted file mode 100644
index 0e1c80a932..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot
+++ /dev/null
@@ -1,53 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = xnand ]; then
-	root=nand
-	kernel=nand
-fi
-
-if [ x$1 = xnet ]; then
-	root=net
-	kernel=net
-fi
-
-if [ x$1 = xnor ]; then
-	root=nor
-	kernel=nor
-fi
-
-if [ x$root = xnet ]; then
-	if [ x$ip = xdhcp ]; then
-		bootargs="$bootargs ip=dhcp"
-	else
-		bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
-	fi
-else
-	bootargs="$bootargs ip=off"
-fi
-
-if [ x$rootfstype = xubifs ]; then
-	bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum rootfstype=ubifs"
-else
-	if [ x$root = xnand ]; then
-		bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
-	elif [ x$root = xnor ]; then
-		bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
-	fi
-fi
-
-bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts"
-
-if [ $kernel = net ]; then
-	if [ x$ip = xdhcp ]; then
-		dhcp
-	fi
-	tftp $uimage uImage || exit 1
-	bootm uImage
-elif [ $kernel = nor ]; then
-	bootm /dev/nor0.kernel
-else
-	bootm /dev/nand0.kernel.bb
-fi
-
diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/init b/arch/arm/boards/eukrea_cpuimx27/env/bin/init
deleted file mode 100644
index e3c109135a..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/env/bin/init
+++ /dev/null
@@ -1,43 +0,0 @@
-#!/bin/sh
-
-PATH=/env/bin
-export PATH
-
-. /env/config
-if [ -e /dev/nor0 ]; then
-	addpart /dev/nor0 $nor_parts
-fi
-
-if [ -e /dev/nand0 ]; then
-	addpart /dev/nand0 $nand_parts
-fi
-
-if [ -f /env/logo.bmp ]; then
-	splash /env/logo.bmp
-	fb0.enable=1
-elif [ -f /env/logo.bmp.lzo ]; then
-	uncompress /env/logo.bmp.lzo /logo.bmp
-	splash /logo.bmp
-	fb0.enable=1
-fi
-
-if [ -z $eth0.ethaddr ]; then
-	while [ -z $eth0.ethaddr ]; do
-		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-	done
-	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-	saveenv
-fi
-
-echo
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
-	echo
-	echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
-	echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
-	echo
-	exit
-fi
-
-boot
diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel
deleted file mode 100644
index 05c822d860..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$uimage
-if [ x$1 = xnand ]; then
-	part=/dev/nand0.kernel.bb
-elif [ x$1 = xnor ]; then
-	part=/dev/nor0.kernel
-else
-	echo "usage: $0 nor|nand [imagename]"
-	exit 1
-fi
-
-. /env/bin/_update $2
diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root
deleted file mode 100644
index eaf36ebcea..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root
+++ /dev/null
@@ -1,16 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$uimage
-if [ x$1 = xnand ]; then
-	part=/dev/nand0.root.bb
-elif [ x$1 = xnor ]; then
-	part=/dev/nor0.root
-else
-	echo "usage: $0 nor|nand [imagename]"
-	exit 1
-fi
-
-. /env/bin/_update $2
-
diff --git a/arch/arm/boards/eukrea_cpuimx27/env/config b/arch/arm/boards/eukrea_cpuimx27/env/config
deleted file mode 100644
index 7f5600339f..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/env/config
+++ /dev/null
@@ -1,36 +0,0 @@
-#!/bin/sh
-
-# can be either 'net', 'nor' or 'nand''
-kernel=nor
-root=nor
-rootfstype=ubifs
-
-basedir=cpuimx27
-uimage=$basedir/uImage
-rootfs=$basedir/rootfs
-
-autoboot_timeout=1
-
-# DVI-SVGA DVI-VGA CMO-QVGA
-video="CMO-QVGA"
-bootargs="console=ttymxc0,115200 fec_mac=$eth0.ethaddr video=mxcfb:$video"
-
-nor_parts="256k(barebox)ro,128k(bareboxenv),2432k(kernel),-(root)"
-rootpart_nor="/dev/mtdblock3"
-
-nand_parts="-(nand)"
-rootpart_nand=""
-
-rootpartnum=3
-ubiroot="eukrea-cpuimx27-rootfs"
-
-nfsroot=""
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
deleted file mode 100644
index e8ac0cc8fa..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2009 Eric Benard, Eukrea Electromatique
- * Based on pcm038.c which is :
- * Copyright (C) 2007 Sascha Hauer, Pengutronix
- */
-
-#include <common.h>
-#include <errno.h>
-#include <net.h>
-#include <init.h>
-#include <environment.h>
-#include <mach/imx27-regs.h>
-#include <notifier.h>
-#include <gpio.h>
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <asm/barebox-arm.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <fs.h>
-#include <fcntl.h>
-#include <nand.h>
-#include <command.h>
-#include <io.h>
-#include <mach/imx-nand.h>
-#include <mach/imx-pll.h>
-#include <mach/weim.h>
-#include <mach/imxfb.h>
-#include <platform_data/serial-ns16550.h>
-#include <asm/mmu.h>
-#include <i2c/i2c.h>
-#include <mfd/lp3972.h>
-#include <mach/iomux-mx27.h>
-#include <mach/devices-imx27.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type = PHY_INTERFACE_MODE_MII,
-	.phy_addr = 1,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.width = 1,
-	.hw_ecc = 1,
-	.flash_bbt = 1,
-};
-
-#ifdef CONFIG_DRIVER_SERIAL_NS16550
-static struct NS16550_plat quad_uart_serial_plat = {
-	.clock = 14745600,
-	.shift = 1,
-};
-
-#ifdef CONFIG_EUKREA_CPUIMX27_QUART1
-#define QUART_OFFSET 0x200000
-#elif defined CONFIG_EUKREA_CPUIMX27_QUART2
-#define QUART_OFFSET 0x400000
-#elif defined CONFIG_EUKREA_CPUIMX27_QUART3
-#define QUART_OFFSET 0x800000
-#elif defined CONFIG_EUKREA_CPUIMX27_QUART4
-#define QUART_OFFSET 0x1000000
-#endif
-#endif
-
-static struct i2c_board_info i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("lp3972", 0x34),
-	},
-};
-
-#ifdef CONFIG_DRIVER_VIDEO_IMX
-static struct fb_videomode imxfb_mode = {
-	.name		= "CMO-QVGA",
-	.refresh	= 60,
-	.xres		= 320,
-	.yres		= 240,
-	.pixclock	= 156000,
-	.hsync_len	= 30,
-	.left_margin	= 38,
-	.right_margin	= 20,
-	.vsync_len	= 3,
-	.upper_margin	= 15,
-	.lower_margin	= 4,
-};
-
-static struct imx_fb_platform_data eukrea_cpuimx27_fb_data = {
-	.mode	= &imxfb_mode,
-	.num_modes = 1,
-	.pwmr	= 0x00A903FF,
-	.lscr1	= 0x00120300,
-	.dmacr	= 0x00020010,
-	.pcr	= 0xFAD08B80,
-	.bpp	= 16,
-};
-#endif
-
-static int eukrea_cpuimx27_devices_init(void)
-{
-	char *envdev = "no";
-	int i;
-
-	unsigned int mode[] = {
-		PD0_AIN_FEC_TXD0,
-		PD1_AIN_FEC_TXD1,
-		PD2_AIN_FEC_TXD2,
-		PD3_AIN_FEC_TXD3,
-		PD4_AOUT_FEC_RX_ER,
-		PD5_AOUT_FEC_RXD1,
-		PD6_AOUT_FEC_RXD2,
-		PD7_AOUT_FEC_RXD3,
-		PD8_AF_FEC_MDIO,
-		PD9_AIN_FEC_MDC | GPIO_PUEN,
-		PD10_AOUT_FEC_CRS,
-		PD11_AOUT_FEC_TX_CLK,
-		PD12_AOUT_FEC_RXD0,
-		PD13_AOUT_FEC_RX_DV,
-		PD14_AOUT_FEC_RX_CLK,
-		PD15_AOUT_FEC_COL,
-		PD16_AIN_FEC_TX_ER,
-		PF23_AIN_FEC_TX_EN,
-		PD17_PF_I2C_DATA,
-		PD18_PF_I2C_CLK,
-#ifdef CONFIG_DRIVER_SERIAL_IMX
-		PE12_PF_UART1_TXD,
-		PE13_PF_UART1_RXD,
-		PE14_PF_UART1_CTS,
-		PE15_PF_UART1_RTS,
-#endif
-#ifdef CONFIG_DRIVER_VIDEO_IMX
-		PA5_PF_LSCLK,
-		PA6_PF_LD0,
-		PA7_PF_LD1,
-		PA8_PF_LD2,
-		PA9_PF_LD3,
-		PA10_PF_LD4,
-		PA11_PF_LD5,
-		PA12_PF_LD6,
-		PA13_PF_LD7,
-		PA14_PF_LD8,
-		PA15_PF_LD9,
-		PA16_PF_LD10,
-		PA17_PF_LD11,
-		PA18_PF_LD12,
-		PA19_PF_LD13,
-		PA20_PF_LD14,
-		PA21_PF_LD15,
-		PA22_PF_LD16,
-		PA23_PF_LD17,
-		PA28_PF_HSYNC,
-		PA29_PF_VSYNC,
-		PA31_PF_OE_ACD,
-		GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT,
-		GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT,
-#endif
-	};
-
-	/* configure 16 bit nor flash on cs0 */
-	imx27_setup_weimcs(0, 0x00008F03, 0xA0330D01, 0x002208C0);
-
-	/* initialize gpios */
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx27_gpio_mode(mode[i]);
-
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0);
-#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC2000000, 32 * 1024 * 1024, 0);
-#endif
-	imx27_add_nand(&nand_info);
-
-	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
-	imx27_add_i2c0(NULL);
-
-	devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
-	devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
-	protect_file("/dev/env0", 1);
-	envdev = "NOR";
-
-	printf("Using environment in %s Flash\n", envdev);
-
-#ifdef CONFIG_DRIVER_VIDEO_IMX
-	imx_add_fb((void *)0x10021000, &eukrea_cpuimx27_fb_data);
-	gpio_direction_output(GPIO_PORTE | 5, 0);
-	gpio_set_value(GPIO_PORTE | 5, 1);
-	gpio_direction_output(GPIO_PORTA | 25, 0);
-	gpio_set_value(GPIO_PORTA | 25, 1);
-#endif
-
-	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX27);
-
-	return 0;
-}
-
-device_initcall(eukrea_cpuimx27_devices_init);
-
-static int eukrea_cpuimx27_console_init(void)
-{
-	uint32_t val;
-
-	barebox_set_model("Eukrea CPUIMX27");
-	barebox_set_hostname("eukrea-cpuimx27");
-
-#ifdef CONFIG_DRIVER_SERIAL_IMX
-	imx27_add_uart0();
-#endif
-	/* configure 8 bit UART on cs3 */
-	val = readl(MX27_SYSCTRL_BASE_ADDR + MX27_FMCR);
-	val &= ~0x2;
-	writel(val, MX27_SYSCTRL_BASE_ADDR + MX27_FMCR);
-
-	imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000);
-#ifdef CONFIG_DRIVER_SERIAL_NS16550
-	add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf,
-			   IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
-			   &quad_uart_serial_plat);
-#endif
-	return 0;
-}
-
-console_initcall(eukrea_cpuimx27_console_init);
-
-static int eukrea_cpuimx27_late_init(void)
-{
-#ifdef CONFIG_MFD_LP3972
-	struct i2c_client *client;
-	u8 reg[1];
-#endif
-	console_flush();
-	imx27_add_fec(&fec_info);
-
-#ifdef CONFIG_MFD_LP3972
-	client = lp3972_get_client();
-	if (!client)
-		return -ENODEV;
-	reg[0] = 0xa0;
-	i2c_write_reg(client, 0x39, reg, sizeof(reg));
-#endif
-	return 0;
-}
-
-late_initcall(eukrea_cpuimx27_late_init);
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
deleted file mode 100644
index b3504832d7..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ /dev/null
@@ -1,134 +0,0 @@
-#include <config.h>
-#include <asm-generic/memory_layout.h>
-#include <mach/imx27-regs.h>
-#include <mach/esdctl.h>
-#include <asm/barebox-arm-head.h>
-
-#define writel(val, reg) \
-	ldr		r0,	=reg;	\
-	ldr		r1,	=val;	\
-	str		r1,   [r0];
-
-#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
-#define ROWS0	ESDCTL0_ROW14
-#define CFG0	0x0029572D
-#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
-#define ROWS0	ESDCTL0_ROW13
-#define CFG0	0x00095728
-#endif
-
-#define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10)
-
-.macro sdram_init
-	/*
-	 * DDR on CSD0
-	 */
-	/* Enable DDR SDRAM operation */
-	writel(0x0000000C, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
-
-	/* Set the driving strength   */
-	writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3))
-	writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5))
-	writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6))
-	writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7))
-	writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8))
-
-	/* Initial reset */
-	writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
-	writel(CFG0, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
-
-	/* precharge CSD0 all banks */
-	writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
-			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
-	writel(0x00000000, 0xA0000F00)	/* CSD0 precharge address (A10 = 1) */
-	writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
-			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
-
-	ldr	r0, =0xa0000f00
-	mov	r1, #0
-	mov	r2, #8
-1:
-	str	r1, [r0]
-	subs	r2, #1
-	bne	1b
-
-	writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
-			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
-	ldr		r0, =0xA0000033
-	mov		r1, #0xda
-	strb		r1, [r0]
-#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
-	ldr		r0, =0xA2000000
-#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
-	ldr		r0, =0xA1000000
-#endif
-	mov		r1, #0xff
-	strb		r1, [r0]
-	writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
-			ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
-			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
-.endm
-
-	.section ".text_bare_init","ax"
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-
-	bl		arm_cpu_lowlevel_init
-
-	ldr	sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4;
-
-	/* ahb lite ip interface */
-	writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
-	writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
-	writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
-	writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
-
-	/* disable mpll/spll */
-	ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR
-	ldr r1, [r0]
-	bic r1, r1, #0x03
-	str r1, [r0]
-
-	/*
-	 * pll clock initialization - see section 3.4.3 of the i.MX27 manual
-	 */
-	/* MPLL = 399 MHz */
-	writel(0x00331C23, MX27_CCM_BASE_ADDR + MX27_MPCTL0)
-	/* SPLL = 240 MHz */
-	writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0)
-	writel(0x33F38107 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
-			MX27_CCM_BASE_ADDR + MX27_CSCR)
-
-	/* add some delay here */
-	mov r1, #0x1000
-1:	subs r1, r1, #0x1
-	bne 1b
-
-	/* clock gating enable */
-	writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR)
-
-	/* peripheral clock divider */
-	/* FIXME                            */
-	writel(0x130400c3, MX27_CCM_BASE_ADDR + MX27_PCDR0)
-	/* PERDIV1=08 @133 MHz              */
-	writel(0x09030208, MX27_CCM_BASE_ADDR + MX27_PCDR1)
-	/* PERDIV1=04 @266 MHz              */
-
-	/* skip sdram initialization if we run from ram */
-	cmp	pc, #0xa0000000
-	bls	1f
-	cmp	pc, #0xc0000000
-	bhi	1f
-
-	b	imx27_barebox_entry
-1:
-	sdram_init
-
-#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
-	mov	r0, #0
-	b	imx27_barebox_boot_nand_external
-#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
-
-ret:
-	b	imx27_barebox_entry
diff --git a/arch/arm/boards/eukrea_cpuimx35/Makefile b/arch/arm/boards/eukrea_cpuimx35/Makefile
deleted file mode 100644
index f1a8e7a5d6..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de>
-
-obj-y					+= eukrea_cpuimx35.o
-lwl-y					+= lowlevel.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-eukrea_cpuimx35
diff --git a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/bin/init_board b/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/bin/init_board
deleted file mode 100644
index 2a07a8425a..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/bin/init_board
+++ /dev/null
@@ -1,41 +0,0 @@
-#!/bin/sh
-
-if [ -f /env/logo.bmp ]; then
-	splash /env/logo.bmp
-	fb0.enable=1
-	gpio_set_value 1 1
-elif [ -f /env/logo.bmp.lzo ]; then
-	uncompress /env/logo.bmp.lzo /logo.bmp
-	splash /logo.bmp
-	fb0.enable=1
-	gpio_set_value 1 1
-fi
-
-gpio_get_value 89
-if [ $? -eq 0 ]; then
-	gpio_set_value 93 0
-	usbserial
-	timeout -s -a 2
-	gpio_get_value 89
-	if [ $? -eq 0 ]; then
-		usbserial -d
-		dfu -V 0x1234 -P 0x1234 /dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.root.bb(root)r
-		gpio_get_value 89
-		if [ $? -eq 0 ]; then
-			usbserial
-			autoboot_timeout=60
-		else
-			reset
-		fi
-	else
-		autoboot_timeout=28
-	fi
-fi
-
-if [ -z $eth0.ethaddr ]; then
-	while [ -z $eth0.ethaddr ]; do
-		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-	done
-	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-	saveenv
-fi
diff --git a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/config b/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/config
deleted file mode 100644
index 05c4391d35..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/config
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/bin/sh
-
-# otg port mode : can be 'host' or 'device'
-otg_mode="device"
-# video : can be CMO-QVGA, URT-WVGA, DVI-VGA or DVI-SVGA
-video="CMO-QVGA"
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=none
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=nand
-# can be either 'net', 'nand' or 'initrd'
-rootfs_loc=nand
-
-# rootfs
-rootfs_type=ubifs
-rootfsimage=${global.hostname}/rootfs.$rootfs_type
-
-# kernel
-kernelimage=${global.hostname}/uImage-${global.hostname}.bin
-
-# barebox and it's env
-bareboximage=${global.hostname}/barebox-${global.hostname}.bin
-bareboxenvimage=${global.hostname}/bareboxenv-${global.hostname}.bin
-
-nfsroot="$eth0.serverip:/srv/nfs/${global.hostname}"
-
-autoboot_timeout=1
-
-bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=mx3fb:$video"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
-rootfs_mtdblock_nand=3
-nand_device="mxc_nand"
-ubiroot="${global.hostname}-rootfs"
-device_type="nand"
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
deleted file mode 100644
index 9835452ddf..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ /dev/null
@@ -1,347 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2007 Sascha Hauer, Pengutronix
- *               2009 Marc Kleine-Budde, Pengutronix
- * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
- *
- * Derived from:
- *
- * * mx35_3stack.c - board file for uboot-v1
- *   Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *   (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <environment.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <platform_data/eth-fec.h>
-#include <fs.h>
-#include <init.h>
-#include <nand.h>
-#include <net.h>
-#include <partition.h>
-#include <gpio.h>
-#include <envfs.h>
-
-#include <asm/armlinux.h>
-#include <io.h>
-#include <generated/mach-types.h>
-#include <asm/mmu.h>
-
-#include <mach/imx-nand.h>
-#include <mach/imx35-regs.h>
-#include <mach/iomux-mx35.h>
-#include <mach/iomux-v3.h>
-#include <mach/imx-ipu-fb.h>
-#include <mach/imx-pll.h>
-#include <i2c/i2c.h>
-#include <usb/fsl_usb2.h>
-#include <mach/usb.h>
-#include <mach/devices-imx35.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type	= PHY_INTERFACE_MODE_MII,
-	.phy_addr	= 0,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.width		= 1,
-	.hw_ecc		= 1,
-	.flash_bbt	= 1,
-};
-
-static struct fb_videomode imxfb_mode = {
-	.name		= "CMO_QVGA",
-	.refresh	= 60,
-	.xres		= 320,
-	.yres		= 240,
-	.pixclock	= KHZ2PICOS(7000),
-	.left_margin	= 68,
-	.right_margin	= 20,
-	.upper_margin	= 15,
-	.lower_margin	= 4,
-	.hsync_len	= 30,
-	.vsync_len	= 3,
-	.sync		= 0,
-	.vmode		= FB_VMODE_NONINTERLACED,
-};
-
-static void eukrea_cpuimx35_enable_display(int enable)
-{
-	gpio_direction_output(4, enable);
-}
-
-static struct imx_ipu_fb_platform_data ipu_fb_data = {
-	.mode		= &imxfb_mode,
-	.num_modes	= 1,
-	.bpp		= 16,
-	.enable		= eukrea_cpuimx35_enable_display,
-};
-
-#ifdef CONFIG_USB
-#ifndef CONFIG_USB_GADGET
-struct imxusb_platformdata otg_pdata = {
-	.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
-	.mode = USB_DR_MODE_HOST,
-	.phymode = USBPHY_INTERFACE_MODE_UTMI,
-};
-#endif
-
-struct imxusb_platformdata hs_pdata = {
-	.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN,
-	.mode = USB_DR_MODE_HOST,
-};
-#endif
-
-#ifdef CONFIG_USB_GADGET
-static struct fsl_usb2_platform_data usb_pdata = {
-	.operating_mode	= FSL_USB2_DR_DEVICE,
-	.phy_mode	= FSL_USB2_PHY_UTMI,
-};
-#endif
-
-static int eukrea_cpuimx35_mmu_init(void)
-{
-	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-
-	return 0;
-}
-postmmu_initcall(eukrea_cpuimx35_mmu_init);
-
-static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
-	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
-	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
-	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
-	MX35_PAD_FEC_COL__FEC_COL,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX35_PAD_FEC_MDC__FEC_MDC,
-	MX35_PAD_FEC_MDIO__FEC_MDIO,
-	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
-	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
-	MX35_PAD_FEC_CRS__FEC_CRS,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
-	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
-	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
-	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
-	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
-	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
-
-	MX35_PAD_RXD1__UART1_RXD_MUX,
-	MX35_PAD_TXD1__UART1_TXD_MUX,
-	MX35_PAD_RTS1__UART1_RTS,
-	MX35_PAD_CTS1__UART1_CTS,
-
-	MX35_PAD_LD23__GPIO3_29,
-	MX35_PAD_CONTRAST__GPIO1_1,
-	MX35_PAD_D3_CLS__GPIO1_4,
-
-	MX35_PAD_I2C1_CLK__I2C1_SCL,
-	MX35_PAD_I2C1_DAT__I2C1_SDA,
-
-	MX35_PAD_SD1_CMD__ESDHC1_CMD,
-	MX35_PAD_SD1_CLK__ESDHC1_CLK,
-	MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
-	MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
-	MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
-	MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
-
-	MX35_PAD_LD19__GPIO3_25,
-};
-
-static int eukrea_cpuimx35_devices_init(void)
-{
-#ifdef CONFIG_USB_GADGET
-	unsigned int tmp;
-#endif
-	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
-		ARRAY_SIZE(eukrea_cpuimx35_pads));
-
-	imx35_add_nand(&nand_info);
-
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-
-	imx35_add_fec(&fec_info);
-	imx35_add_fb(&ipu_fb_data);
-
-	imx35_add_i2c0(NULL);
-	imx35_add_mmc0(NULL);
-
-	/* led default off */
-	gpio_direction_output(32 * 2 + 29, 1);
-
-	/* Switch : input */
-	gpio_direction_input(32 * 2 + 25);
-
-	/* screen default on to prevent flicker */
-	gpio_direction_output(4, 0);
-	/* backlight default off */
-	gpio_direction_output(1, 0);
-
-#ifdef CONFIG_USB
-#ifndef CONFIG_USB_GADGET
-	imx_add_usb((void *)MX35_USB_OTG_BASE_ADDR, 0, &otg_pdata);
-#endif
-	imx_add_usb((void *)MX35_USB_HS_BASE_ADDR, 1, &hs_pdata);
-#endif
-
-#ifdef CONFIG_USB_GADGET
-	/* Workaround ENGcm09152 */
-	tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608);
-	writel(tmp | (1 << 23), MX35_USB_OTG_BASE_ADDR + 0x608);
-	add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX35_USB_OTG_BASE_ADDR, 0x200,
-			   IORESOURCE_MEM, &usb_pdata);
-#endif
-	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35SD);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_eukrea_cpuimx35);
-
-	return 0;
-}
-
-device_initcall(eukrea_cpuimx35_devices_init);
-
-static int eukrea_cpuimx35_console_init(void)
-{
-	barebox_set_model("Eukrea CPUIMX35");
-	barebox_set_hostname("eukrea-cpuimx35");
-
-	imx35_add_uart0();
-	return 0;
-}
-
-console_initcall(eukrea_cpuimx35_console_init);
-
-static int eukrea_cpuimx35_core_init(void)
-{
-	u32 reg;
-
-	/* enable clock for I2C1, ESDHC1, USB and FEC */
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
-	reg |= 0x3 << MX35_CCM_CGR0_ESDHC1_SHIFT;
-	reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
-	reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
-	reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
-	reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR2);
-	reg |= 0x3 << MX35_CCM_CGR2_USB_SHIFT;
-	reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR2);
-
-	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
-
-	/*
-	 * Clear the on and off peripheral modules Supervisor Protect bit
-	 * for SDMA to access them. Did not change the AIPS control registers
-	 * (offset 0x20) access type
-	 */
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
-	reg = readl(MX35_AIPS1_BASE_ADDR + 0x50);
-	reg &= 0x00FFFFFF;
-	writel(reg, MX35_AIPS1_BASE_ADDR + 0x50);
-
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
-	reg = readl(MX35_AIPS2_BASE_ADDR + 0x50);
-	reg &= 0x00FFFFFF;
-	writel(reg, MX35_AIPS2_BASE_ADDR + 0x50);
-
-	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-
-	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
-
-	/* SGPCR - always park on last master */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
-
-	/* MGPCR - restore default values */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
-
-	/*
-	 * M3IF Control Register (M3IFCTL)
-	 * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[1] = MAX1 not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[2] = L2CC1 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[3] = USB  not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[4] = SDMA not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[5] = GPU not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
-	 * MRRP[7] = IPU2 not on priority list (0 << 0)		= 0x00000000
-	 *                                                       ------------
-	 *                                                        0x00000040
-	 */
-	writel(0x40, MX35_M3IF_BASE_ADDR);
-
-	return 0;
-}
-
-core_initcall(eukrea_cpuimx35_core_init);
-
-static int do_cpufreq(int argc, char *argv[])
-{
-	unsigned long freq;
-
-	if (argc != 2)
-		return COMMAND_ERROR_USAGE;
-
-	freq = simple_strtoul(argv[1], NULL, 0);
-
-	switch (freq) {
-	case 399:
-		writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
-		break;
-	case 532:
-		writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
-		break;
-	default:
-		return COMMAND_ERROR_USAGE;
-	}
-
-	printf("Switched CPU frequency to %luMHz\n", freq);
-
-	return 0;
-}
-
-BAREBOX_CMD_START(cpufreq)
-	.cmd            = do_cpufreq,
-	BAREBOX_CMD_DESC("adjust CPU frequency")
-	BAREBOX_CMD_OPTS("399|532")
-	BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP)
-BAREBOX_CMD_END
diff --git a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg
deleted file mode 100644
index c1353e2904..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg
+++ /dev/null
@@ -1,19 +0,0 @@
-soc imx35
-loadaddr 0x80000000
-ivtofs 0x400
-
-wm 32 0x53F80004 0x00821000
-wm 32 0x53F80004 0x00821000
-wm 32 0xb8001010 0x00000004
-wm 32 0xB8001010 0x0000000C
-wm 32 0xb8001004 0x0009572B
-wm 32 0xb8001000 0x92220000
-wm 8 0x80000400 0xda
-wm 32 0xb8001000 0xa2220000
-wm 32 0x80000000 0x12344321
-wm 32 0x80000000 0x12344321
-wm 32 0xb8001000 0xb2220000
-wm 8 0x80000033 0xda
-wm 8 0x82000000 0xda
-wm 32 0xb8001000 0x82224080
-wm 32 0xb8001010 0x00000004
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
deleted file mode 100644
index 7970b82136..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-#include <common.h>
-#include <init.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/cache-l2x0.h>
-#include <io.h>
-#include <mach/imx-nand.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/sections.h>
-#include <asm-generic/memory_layout.h>
-#include <asm/system.h>
-
-void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	uint32_t r, s;
-	unsigned long ccm_base = MX35_CCM_BASE_ADDR;
-	register uint32_t loops = 0x20000;
-
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE);
-
-	r = get_cr();
-	r |= CR_Z; /* Flow prediction (Z) */
-	r |= CR_U; /* unaligned accesses  */
-	r |= CR_FI; /* Low Int Latency     */
-
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s));
-	s |= 0x7;
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s));
-
-	set_cr(r);
-
-	r = 0;
-	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
-
-	/*
-	 * Branch predicition is now enabled.  Flush the BTAC to ensure a valid
-	 * starting point.  Don't flush BTAC while it is disabled to avoid
-	 * ARM1136 erratum 408023.
-	 */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r));
-
-	/* invalidate I cache and D cache */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r));
-
-	/* invalidate TLBs */
-	__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r));
-
-	/* Drain the write buffer */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r));
-
-	/* Also setup the Peripheral Port Remap register inside the core */
-	r = 0x40000015; /* start from AIPS 2GB region */
-	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
-
-	/*
-	 * End of ARM1136 init
-	 */
-
-	writel(0x003F4208, ccm_base + MX35_CCM_CCMR);
-
-	/* Set MPLL , arm clock and ahb clock*/
-	writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL);
-
-	writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL);
-	writel(0x00001000, ccm_base + MX35_CCM_PDR0);
-
-	r = readl(ccm_base + MX35_CCM_CGR0);
-	r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR0);
-
-	r = readl(ccm_base + MX35_CCM_CGR1);
-	r |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR1_IOMUX_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR1);
-
-	/* enable watchdog asap */
-	r = readl(ccm_base + MX35_CCM_CGR2);
-	r |= 0x3 << MX35_CCM_CGR2_WDOG_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR2);
-
-	r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
-	r |= 0x1000;
-	writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
-
-	/* Skip SDRAM initialization if we run from RAM */
-	r = get_pc();
-	if (r > 0x80000000 && r < 0x90000000)
-		goto out;
-
-	/* Init Mobile DDR */
-	writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	__asm__ volatile ("1:\n"
-			"subs %0, %1, #1\n"
-			"bne 1b":"=r" (loops):"0" (loops));
-
-	writel(0x0009572B, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
-	writel(0x92220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400);
-	writel(0xA2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX35_CSD0_BASE_ADDR);
-	writeb(0xda, MX35_CSD0_BASE_ADDR);
-	writel(0xB2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33);
-	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000);
-	writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-
-	if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
-		/* Speed up NAND controller by adjusting the NFC divider */
-		r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-		r &= ~(0xf << 28);
-		r |= 0x1 << 28;
-		writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-
-		imx35_barebox_boot_nand_external();
-	}
-
-out:
-	imx35_barebox_entry(NULL);
-}
diff --git a/arch/arm/boards/eukrea_cpuimx51/Makefile b/arch/arm/boards/eukrea_cpuimx51/Makefile
deleted file mode 100644
index e8c84fe17d..0000000000
--- a/arch/arm/boards/eukrea_cpuimx51/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += eukrea_cpuimx51.o
-lwl-y += lowlevel.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-eukrea_cpuimx51
diff --git a/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/bin/init_board b/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/bin/init_board
deleted file mode 100644
index 0af65822f1..0000000000
--- a/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/bin/init_board
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/bin/sh
-
-if [ -f /env/logo.bmp ]; then
-	splash /env/logo.bmp
-	fb0.enable=1
-	gpio_set_value 1 1
-elif [ -f /env/logo.bmp.lzo ]; then
-	uncompress /env/logo.bmp.lzo /logo.bmp
-	splash /logo.bmp
-	fb0.enable=1
-	gpio_set_value 1 1
-fi
-
-if [ -z $eth0.ethaddr ]; then
-	while [ -z $eth0.ethaddr ]; do
-		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-	done
-	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-	saveenv
-fi
diff --git a/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/config b/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/config
deleted file mode 100644
index 57abc1ee3d..0000000000
--- a/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/config
+++ /dev/null
@@ -1,50 +0,0 @@
-#!/bin/sh
-
-# otg port mode : can be 'host' or 'device'
-otg_mode="device"
-# video mode : can be 'CMO-QVGA' or 'URT-WVGA' or any modefb mode
-# ex : 640x480M-16@60 800x600M-24@60 1024x768M-16@60
-video="CMO-QVGA"
-# screen type : can be 'tft' or 'dvi'
-screen_type="tft"
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=none
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=nand
-# can be either 'net', 'nand' or 'initrd'
-rootfs_loc=nand
-
-# rootfs
-rootfs_type=ubifs
-rootfsimage=${global.hostname}/rootfs.$rootfs_type
-
-# kernel
-kernelimage=${global.hostname}/uImage-${global.hostname}.bin
-
-# barebox and it's env
-bareboximage=${global.hostname}/barebox-${global.hostname}.bin
-bareboxenvimage=${global.hostname}/bareboxenv-${global.hostname}.bin
-
-nfsroot="$eth0.serverip:/srv/nfs/${global.hostname}"
-
-autoboot_timeout=1
-
-bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=$video screen_type=$screen_type"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
-rootfs_mtdblock_nand=3
-nand_device="mxc_nand"
-ubiroot="${global.hostname}-rootfs"
-device_type="nand"
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
deleted file mode 100644
index 8d0d4a0e8a..0000000000
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix
-// SPDX-FileCopyrightText: 2011 Eric Bénard <eric@eukrea.com>, Eukrea Electromatique
-
-#include <common.h>
-#include <net.h>
-#include <init.h>
-#include <environment.h>
-#include <mach/imx51-regs.h>
-#include <platform_data/eth-fec.h>
-#include <gpio.h>
-#include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <fs.h>
-#include <envfs.h>
-#include <fcntl.h>
-#include <nand.h>
-#include <spi/spi.h>
-#include <io.h>
-#include <asm/mmu.h>
-#include <mach/imx-nand.h>
-#include <mach/spi.h>
-#include <mach/generic.h>
-#include <mach/imx5.h>
-#include <mach/iomux-mx51.h>
-#include <mach/devices-imx51.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type = PHY_INTERFACE_MODE_MII,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.width		= 1,
-	.hw_ecc		= 1,
-	.flash_bbt	= 1,
-};
-
-static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
-	/* UART1 */
-	MX51_PAD_UART1_RXD__UART1_RXD,
-	MX51_PAD_UART1_TXD__UART1_TXD,
-	MX51_PAD_UART1_RTS__UART1_RTS,
-	MX51_PAD_UART1_CTS__UART1_CTS,
-	/* FEC */
-	NEW_PAD_CTRL(MX51_PAD_DISP2_DAT1__FEC_RX_ER, MX51_PAD_CTRL_5),
-	MX51_PAD_DISP2_DAT15__FEC_TDATA0,
-	MX51_PAD_DISP2_DAT6__FEC_TDATA1,
-	MX51_PAD_DISP2_DAT7__FEC_TDATA2,
-	MX51_PAD_DISP2_DAT8__FEC_TDATA3,
-	MX51_PAD_DISP2_DAT9__FEC_TX_EN,
-	NEW_PAD_CTRL(MX51_PAD_DISP2_DAT10__FEC_COL, MX51_PAD_CTRL_5),
-	NEW_PAD_CTRL(MX51_PAD_DISP2_DAT11__FEC_RX_CLK, MX51_PAD_CTRL_5),
-	NEW_PAD_CTRL(MX51_PAD_DISP2_DAT12__FEC_RX_DV, MX51_PAD_CTRL_5),
-	MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
-	MX51_PAD_DI2_PIN4__FEC_CRS,
-	MX51_PAD_DI2_PIN2__FEC_MDC,
-	NEW_PAD_CTRL(MX51_PAD_DI2_PIN3__FEC_MDIO, MX51_PAD_CTRL_5),
-	MX51_PAD_DISP2_DAT14__FEC_RDATA0,
-	MX51_PAD_DI2_DISP_CLK__FEC_RDATA1,
-	NEW_PAD_CTRL(MX51_PAD_DI_GP4__FEC_RDATA2, MX51_PAD_CTRL_5),
-	NEW_PAD_CTRL(MX51_PAD_DISP2_DAT0__FEC_RDATA3, MX51_PAD_CTRL_5),
-	MX51_PAD_DI_GP3__FEC_TX_ER,
-	MX51_PAD_EIM_DTACK__GPIO2_31, /* LAN8700 reset pin */
-	/* NAND */
-	MX51_PAD_NANDF_D7__NANDF_D7,
-	MX51_PAD_NANDF_D6__NANDF_D6,
-	MX51_PAD_NANDF_D5__NANDF_D5,
-	MX51_PAD_NANDF_D4__NANDF_D4,
-	MX51_PAD_NANDF_D3__NANDF_D3,
-	MX51_PAD_NANDF_D2__NANDF_D2,
-	MX51_PAD_NANDF_D1__NANDF_D1,
-	MX51_PAD_NANDF_D0__NANDF_D0,
-	MX51_PAD_NANDF_RB0__NANDF_RB0,
-	MX51_PAD_NANDF_RB1__NANDF_RB1,
-	MX51_PAD_NANDF_CS0__NANDF_CS0,
-	MX51_PAD_NANDF_CS1__NANDF_CS1,
-	/* LCD BL */
-	MX51_PAD_DI1_D1_CS__GPIO3_4,
-#ifdef CONFIG_MCI_IMX_ESDHC
-	/* SD 1 */
-	MX51_PAD_SD1_CMD__SD1_CMD,
-	MX51_PAD_SD1_CLK__SD1_CLK,
-	MX51_PAD_SD1_DATA0__SD1_DATA0,
-	MX51_PAD_SD1_DATA1__SD1_DATA1,
-	MX51_PAD_SD1_DATA2__SD1_DATA2,
-	MX51_PAD_SD1_DATA3__SD1_DATA3,
-#endif
-};
-
-#define GPIO_LAN8700_RESET	(1 * 32 + 31)
-#define GPIO_LCD_BL		(2 * 32 + 4)
-
-static int eukrea_cpuimx51_devices_init(void)
-{
-	imx51_add_fec(&fec_info);
-#ifdef CONFIG_MCI_IMX_ESDHC
-	imx51_add_mmc0(NULL);
-#endif
-	imx51_add_nand(&nand_info);
-
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-
-	gpio_direction_output(GPIO_LAN8700_RESET, 0);
-	gpio_set_value(GPIO_LAN8700_RESET, 1);
-	gpio_direction_output(GPIO_LCD_BL, 0);
-
-	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX51SD);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_eukrea_cpuimx51);
-
-	return 0;
-}
-
-device_initcall(eukrea_cpuimx51_devices_init);
-
-static int eukrea_cpuimx51_console_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, ARRAY_SIZE(eukrea_cpuimx51_pads));
-
-	barebox_set_model("Eukrea CPUIMX51");
-	barebox_set_hostname("eukrea-cpuimx51");
-
-	imx51_init_lowlevel(800);
-
-	imx51_add_uart0();
-
-	return 0;
-}
-
-console_initcall(eukrea_cpuimx51_console_init);
diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c
deleted file mode 100644
index 6762fdad4b..0000000000
--- a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include <common.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
-#include <asm/barebox-arm-head.h>
-
-void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	imx5_cpu_lowlevel_init();
-	arm_setup_stack(0x20000000);
-	imx51_barebox_entry(NULL);
-}
diff --git a/arch/arm/boards/freescale-mx21-ads/Makefile b/arch/arm/boards/freescale-mx21-ads/Makefile
deleted file mode 100644
index a43425b9ea..0000000000
--- a/arch/arm/boards/freescale-mx21-ads/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-lwl-y += lowlevel_init.o
-obj-y += imx21ads.o
diff --git a/arch/arm/boards/freescale-mx21-ads/env/bin/init b/arch/arm/boards/freescale-mx21-ads/env/bin/init
deleted file mode 100644
index 224a6b40be..0000000000
--- a/arch/arm/boards/freescale-mx21-ads/env/bin/init
+++ /dev/null
@@ -1 +0,0 @@
-# Dummy Init environment script
diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.c b/arch/arm/boards/freescale-mx21-ads/imx21ads.c
deleted file mode 100644
index 92207b02d3..0000000000
--- a/arch/arm/boards/freescale-mx21-ads/imx21ads.c
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2009 Ivo Clarysse
- *
- * Based on imx27ads.c,
- *   Copyright (C) 2007 Sascha Hauer, Pengutronix
- */
-
-#include <common.h>
-#include <net.h>
-#include <init.h>
-#include <environment.h>
-#include <mach/imx21-regs.h>
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <asm/barebox-arm.h>
-#include <io.h>
-#include <gpio.h>
-#include <mach/weim.h>
-#include <partition.h>
-#include <fs.h>
-#include <linux/sizes.h>
-#include <fcntl.h>
-#include <generated/mach-types.h>
-#include <mach/imx-nand.h>
-#include <mach/imxfb.h>
-#include <mach/iomux-mx21.h>
-#include <mach/devices-imx21.h>
-
-#define MX21ADS_IO_REG    0xCC800000
-#define MX21ADS_IO_LCDON  (1 << 9)
-
-struct imx_nand_platform_data nand_info = {
-	.width = 1,
-	.hw_ecc = 1,
-};
-
-/* Sharp LQ035Q7DB02 QVGA display */
-static struct fb_videomode imx_fb_modedata = {
-	.name           = "Sharp-LQ035Q7",
-	.refresh        = 60,
-	.xres           = 240,
-	.yres           = 320,
-	.pixclock       = 188679,
-	.left_margin    = 6,
-	.right_margin   = 16,
-	.upper_margin   = 8,
-	.lower_margin   = 10,
-	.hsync_len      = 2,
-	.vsync_len      = 1,
-	.sync           = 0,
-	.vmode          = FB_VMODE_NONINTERLACED,
-};
-
-static struct imx_fb_platform_data imx_fb_data = {
-	.mode           = &imx_fb_modedata,
-	.num_modes	= 1,
-	.cmap_greyscale = 0,
-	.cmap_inverse   = 0,
-	.cmap_static    = 0,
-	.pwmr           = 0x00a903ff,
-	.lscr1          = 0x00120300,
-	.dmacr          = 0x00020008,
-	.pcr            = 0xfb108bc7,
-	.bpp            = 16,
-};
-
-static int imx21ads_timing_init(void)
-{
-	u32 temp;
-
-	/* Configure External Interface Module */
-	/* CS0: burst flash */
-	imx21_setup_eimcs(0, 0x00003E00, 0x00000E01);
-
-	/* CS1: Ethernet controller, external UART, memory-mapped I/O (16-bit) */
-	imx21_setup_eimcs(1, 0x00002000, 0x11118501);
-
-	/* CS2-CS5: disable */
-	imx21_setup_eimcs(2, 0x0, 0x0);
-	imx21_setup_eimcs(3, 0x0, 0x0);
-	imx21_setup_eimcs(4, 0x0, 0x0);
-	imx21_setup_eimcs(5, 0x0, 0x0);
-
-	temp = readl(MX21_CCM_BASE_ADDR + MX21_PCDR0);
-	temp &= ~0xF000;
-	temp |= 0xA000;  /* Set NFC divider; 0xA yields 24.18MHz */
-	writel(temp, MX21_CCM_BASE_ADDR + MX21_PCDR0);
-
-	return 0;
-}
-
-core_initcall(imx21ads_timing_init);
-
-static int mx21ads_mem_init(void)
-{
-	arm_add_mem_device("ram0", 0xc0000000, SZ_64M);
-
-	return 0;
-}
-mem_initcall(mx21ads_mem_init);
-
-static int mx21ads_devices_init(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PA5_PF_LSCLK,
-		PA6_PF_LD0,
-		PA7_PF_LD1,
-		PA8_PF_LD2,
-		PA9_PF_LD3,
-		PA10_PF_LD4,
-		PA11_PF_LD5,
-		PA12_PF_LD6,
-		PA13_PF_LD7,
-		PA14_PF_LD8,
-		PA15_PF_LD9,
-		PA16_PF_LD10,
-		PA17_PF_LD11,
-		PA18_PF_LD12,
-		PA19_PF_LD13,
-		PA20_PF_LD14,
-		PA21_PF_LD15,
-		PA22_PF_LD16,
-		PA23_PF_LD17,
-		PA24_PF_REV,
-		PA25_PF_CLS,
-		PA26_PF_PS,
-		PA27_PF_SPL_SPR,
-		PA28_PF_HSYNC,
-		PA29_PF_VSYNC,
-		PA30_PF_CONTRAST,
-		PA31_PF_OE_ACD,
-		PE12_PF_UART1_TXD,
-		PE13_PF_UART1_RXD,
-		PE14_PF_UART1_CTS,
-		PE15_PF_UART1_RTS,
-	};
-
-	/* initizalize gpios */
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx21_gpio_mode(mode[i]);
-
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX21_CS0_BASE_ADDR,
-			32 * 1024 * 1024, 0);
-	imx21_add_nand(&nand_info);
-	add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL,
-			MX21_CS1_BASE_ADDR, 0x1000,
-			IORESOURCE_MEM, NULL);
-	imx21_add_fb(&imx_fb_data);
-
-	armlinux_set_architecture(MACH_TYPE_MX21ADS);
-
-	return 0;
-}
-
-device_initcall(mx21ads_devices_init);
-
-static int mx21ads_enable_display(void)
-{
-	u16 tmp;
-
-	tmp = readw(MX21ADS_IO_REG);
-	tmp |= MX21ADS_IO_LCDON;
-	writew(tmp, MX21ADS_IO_REG);
-	return 0;
-}
-
-late_initcall(mx21ads_enable_display);
-
-static int mx21ads_console_init(void)
-{
-	barebox_set_model("Freescale i.MX21 ADS");
-	barebox_set_hostname("mx21ads");
-
-	imx21_add_uart0();
-	return 0;
-}
-
-console_initcall(mx21ads_console_init);
diff --git a/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S
deleted file mode 100644
index 9b6e4bd472..0000000000
--- a/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2010 Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
-
-#include <config.h>
-#include <linux/sizes.h>
-#include <asm-generic/memory_layout.h>
-#include <mach/imx21-regs.h>
-#include <asm/barebox-arm-head.h>
-
-	.section ".text_bare_init","ax"
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-
-	bl	arm_cpu_lowlevel_init
-
-/*
- * Initialize the AHB-Lite IP Interface (AIPI) module (to enable access to
- * on chip peripherals) as described in section 7.2 of rev3 of the i.MX21
- * reference manual.
- */
-	ldr	r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR0
-	ldr	r1, =0x00040304
-	str	r1, [r0]
-	ldr	r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR1
-	ldr     r1, =0xfffbfcfb
-	str	r1, [r0]
-
-	ldr	r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR0
-	ldr	r1, =0x3ffc0000
-	str	r1, [r0]
-	ldr	r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR1
-	ldr     r1, =0xffffffff
-	str	r1, [r0]
-
-/*
- * Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable
- * the clock to peripherals.
- */
-	ldr	r0, =MX21_CCM_BASE_ADDR + MX21_CSCR
-	ldr	r1, =0x17180607
-	str	r1, [r0]
-
-	ldr	r0, =MX21_CCM_BASE_ADDR + MX21_PCCR1
-	ldr	r1, =0x0e000000
-	str	r1, [r0]
-
-
-/*
- * SDRAM and SDRAM controller configuration
- */
-
-	/*
-	 * CSD1 not required, because the MX21ADS board only contains 64Mbyte.
-	 * CS3 can therefore be made available.
-	 */
-	ldr	r0, =MX21_SYSCTRL_BASE_ADDR + MX21_FMCR
-	ldr	r1, =0xffffffc9
-	str	r1, [r0]
-
-	/* Skip SDRAM initialization if we run from RAM */
-	cmp	pc, #0xc0000000
-	bls	1f
-	cmp	pc, #0xc8000000
-	bhi	1f
-
-	b	ret
-1:
-
-	/* Precharge */
-	ldr	r0, =MX21_X_MEMC_BASE_ADDR + MX21_SDCTL0
-	ldr	r1, =0x92120300
-	str	r1, [r0]
-	ldr	r2, =0xc0200000
-	ldr	r1, [r2]
-
-	bl	mem_delay
-
-	/* Auto refresh */
-	ldr	r1, =0xa2120300
-	str	r1, [r0]
-	ldr	r2, =0xc0000000
-	ldr	r1, [r2]
-	ldr	r1, [r2]
-	ldr	r1, [r2]
-	ldr	r1, [r2]
-	ldr	r1, [r2]
-	ldr	r1, [r2]
-	ldr	r1, [r2]
-	ldr	r1, [r2]
-
-	/* Set mode register */
-	ldr	r1, =0xB2120300
-	str	r1, [r0]
-	ldr	r1, =0xC0119800
-	ldr	r2, [r1]
-
-	bl	mem_delay
-
-	/* Back to Normal Mode */
-	ldr	r1, =0x8212F339
-	str	r1, [r0]
-
-	/* Set NFC_CLK to 24MHz */
-	ldr	r0, =MX21_CCM_BASE_ADDR + MX21_PCDR0
-	ldr	r1, =0x6419a007
-	str	r1, [r0]
-
-#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
-
-	/* Setup a temporary stack in SRAM */
-	ldr	sp, =MX21_IRAM_BASE_ADDR + MX21_IRAM_SIZE - 4
-
-	b	imx21_barebox_boot_nand_external
-#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
-
-ret:
-	mov	r0, #0xc0000000
-	mov	r1, #SZ_64M
-	mov	r2, #0
-	b	barebox_arm_entry
-
-/*
- *  spin for a while.  we need to wait at least 200 usecs.
- */
-mem_delay:
-	mov	r4, #0x4000
-spin:	subs	r4, r4, #1
-	bne	spin
-	mov	pc, lr
-
diff --git a/arch/arm/boards/freescale-mx23-evk/Makefile b/arch/arm/boards/freescale-mx23-evk/Makefile
index 3e0026252c..7723ad93b0 100644
--- a/arch/arm/boards/freescale-mx23-evk/Makefile
+++ b/arch/arm/boards/freescale-mx23-evk/Makefile
@@ -1,3 +1,4 @@
-#
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y := mx23-evk.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx23-evk/lowlevel.c b/arch/arm/boards/freescale-mx23-evk/lowlevel.c
index 99e08d88c7..195ade3a7f 100644
--- a/arch/arm/boards/freescale-mx23-evk/lowlevel.c
+++ b/arch/arm/boards/freescale-mx23-evk/lowlevel.c
@@ -1,12 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx23-regs.h>
+#include <mach/mxs/imx23-regs.h>
+
+static noinline void continue_imx_entry(size_t size)
+{
+	static struct barebox_arm_boarddata boarddata = {
+		.magic = BAREBOX_ARM_BOARDDATA_MAGIC,
+		.machine = MACH_TYPE_MX23EVK,
+	};
+
+	barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata);
+}
 
 ENTRY_FUNCTION(start_imx23_evk, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
-	barebox_arm_entry(IMX_MEMORY_BASE, SZ_32M, (void *)MACH_TYPE_MX23EVK);
+
+	relocate_to_current_adr();
+	setup_c();
+
+	continue_imx_entry(SZ_32M);
 }
diff --git a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
index b12bb0dd79..d4de99eafb 100644
--- a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
+++ b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
@@ -9,14 +9,13 @@
 #include <mci.h>
 #include <linux/err.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx-regs.h>
-#include <mach/clock.h>
-#include <mach/mci.h>
-#include <usb/fsl_usb2.h>
-#include <mach/usb.h>
-#include <mach/iomux.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/mci.h>
+#include <linux/usb/fsl_usb2.h>
+#include <mach/mxs/usb.h>
+#include <mach/mxs/iomux.h>
 
 static struct mxs_mci_platform_data mci_pdata = {
 	.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED,
diff --git a/arch/arm/boards/freescale-mx25-3ds/3stack.c b/arch/arm/boards/freescale-mx25-3ds/3stack.c
deleted file mode 100644
index 8707e02a64..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/3stack.c
+++ /dev/null
@@ -1,211 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-#include <common.h>
-#include <init.h>
-#include <driver.h>
-#include <gpio.h>
-#include <environment.h>
-#include <mach/imx25-regs.h>
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <asm/barebox-arm.h>
-#include <io.h>
-#include <envfs.h>
-#include <partition.h>
-#include <generated/mach-types.h>
-#include <mach/imx-nand.h>
-#include <platform_data/eth-fec.h>
-#include <nand.h>
-#include <mach/iomux-mx25.h>
-#include <mach/generic.h>
-#include <mach/iim.h>
-#include <linux/err.h>
-#include <i2c/i2c.h>
-#include <mfd/mc34704.h>
-#include <mach/devices-imx25.h>
-#include <asm/barebox-arm-head.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type	= PHY_INTERFACE_MODE_RMII,
-	.phy_addr	= 1,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.width	= 1,
-	.hw_ecc	= 1,
-};
-
-#ifdef CONFIG_USB
-static void imx25_usb_init(void)
-{
-	unsigned int tmp;
-
-	/* Host 2 */
-	tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x600);
-	tmp &= ~(3 << 21);
-	tmp |= (2 << 21) | (1 << 4) | (1 << 5);
-	writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x600);
-
-	tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x584);
-	tmp |= 3 << 30;
-	writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x584);
-
-	/* Set to Host mode */
-	tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x5a8);
-	writel(tmp | 0x3, MX25_USB_OTG_BASE_ADDR + 0x5a8);
-}
-#endif
-
-static struct i2c_board_info i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("mc34704", 0x54),
-	},
-};
-
-static int imx25_3ds_pmic_init(void)
-{
-	struct mc34704 *pmic;
-
-	pmic = mc34704_get();
-	if (pmic == NULL)
-		return -EIO;
-
-	return mc34704_reg_write(pmic, 0x2, 0x9);
-}
-
-static int imx25_3ds_fec_init(void)
-{
-	int ret;
-
-	ret = imx25_3ds_pmic_init();
-	if (ret < 0)
-		return ret;
-
-	/*
-	 * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
-	 * Assert FEC_RESET_B, then power up the PHY by asserting
-	 * FEC_ENABLE, at the same time lifting FEC_RESET_B.
-	 *
-	 * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
-	 * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12
-	 */
-	writel(0x8, MX25_IOMUXC_BASE_ADDR + 0x0238); /* open drain */
-	writel(0x0, MX25_IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */
-
-#define FEC_ENABLE_GPIO		35
-#define FEC_RESET_B_GPIO	104
-
-	/* make the pins output */
-	gpio_direction_output(FEC_ENABLE_GPIO, 0);  /* drop PHY power */
-	gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
-	udelay(2);
-
-	/* turn on power & lift reset */
-	gpio_set_value(FEC_ENABLE_GPIO, 1);
-	gpio_set_value(FEC_RESET_B_GPIO, 1);
-
-	return 0;
-}
-late_initcall(imx25_3ds_fec_init);
-
-static int imx25_3ds_devices_init(void)
-{
-#ifdef CONFIG_USB
-	/* USB does not work yet. Don't know why. Maybe
-	 * the CPLD has to be initialized.
-	 */
-	imx25_usb_init();
-	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX25_USB_OTG_BASE_ADDR + 0x400, NULL);
-#endif
-
-	imx25_iim_register_fec_ethaddr();
-	imx25_add_fec(&fec_info);
-
-	add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE);
-
-	if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14))
-		nand_info.width = 2;
-
-	imx25_add_nand(&nand_info);
-
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-
-	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-
-	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
-	imx25_add_i2c0(NULL);
-
-	armlinux_set_architecture(MACH_TYPE_MX25_3DS);
-	armlinux_set_serial(imx_uid());
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_freescale_mx25_3ds);
-
-	return 0;
-}
-
-device_initcall(imx25_3ds_devices_init);
-
-static iomux_v3_cfg_t imx25_pads[] = {
-	MX25_PAD_FEC_MDC__FEC_MDC,
-	MX25_PAD_FEC_MDIO__FEC_MDIO,
-	MX25_PAD_FEC_RDATA0__FEC_RDATA0,
-	MX25_PAD_FEC_RDATA1__FEC_RDATA1,
-	MX25_PAD_FEC_RX_DV__FEC_RX_DV,
-	MX25_PAD_FEC_TDATA0__FEC_TDATA0,
-	MX25_PAD_FEC_TDATA1__FEC_TDATA1,
-	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
-	MX25_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX25_PAD_POWER_FAIL__POWER_FAIL,
-	MX25_PAD_A17__GPIO_2_3,
-	MX25_PAD_D12__GPIO_4_8,
-	/* UART1 */
-	MX25_PAD_UART1_RXD__UART1_RXD,
-	MX25_PAD_UART1_TXD__UART1_TXD,
-	MX25_PAD_UART1_RTS__UART1_RTS,
-	MX25_PAD_UART1_CTS__UART1_CTS,
-	/* USBH2 */
-	MX25_PAD_D9__USBH2_PWR,
-	MX25_PAD_D8__USBH2_OC,
-	MX25_PAD_LD0__USBH2_CLK,
-	MX25_PAD_LD1__USBH2_DIR,
-	MX25_PAD_LD2__USBH2_STP,
-	MX25_PAD_LD3__USBH2_NXT,
-	MX25_PAD_LD4__USBH2_DATA0,
-	MX25_PAD_LD5__USBH2_DATA1,
-	MX25_PAD_LD6__USBH2_DATA2,
-	MX25_PAD_LD7__USBH2_DATA3,
-	MX25_PAD_HSYNC__USBH2_DATA4,
-	MX25_PAD_VSYNC__USBH2_DATA5,
-	MX25_PAD_LSCLK__USBH2_DATA6,
-	MX25_PAD_OE_ACD__USBH2_DATA7,
-	/* i2c */
-	MX25_PAD_I2C1_CLK__I2C1_CLK,
-	MX25_PAD_I2C1_DAT__I2C1_DAT,
-};
-
-static int imx25_console_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads));
-
-	writel(0x03010101, 0x53f80024);
-
-	barebox_set_model("Freescale i.MX25 3DS");
-	barebox_set_hostname("mx25-3stack");
-
-	imx25_add_uart0();
-	return 0;
-}
-
-console_initcall(imx25_console_init);
-
-static int imx25_core_setup(void)
-{
-	writel(0x01010103, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
-	return 0;
-
-}
-core_initcall(imx25_core_setup);
diff --git a/arch/arm/boards/freescale-mx25-3ds/Makefile b/arch/arm/boards/freescale-mx25-3ds/Makefile
deleted file mode 100644
index dbb2e77ecb..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de>
-
-lwl-y += lowlevel_init.o
-obj-y += 3stack.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-freescale-mx25-3ds
diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/_update b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/_update
deleted file mode 100644
index 014bce3512..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/_update
+++ /dev/null
@@ -1,36 +0,0 @@
-#!/bin/sh
-
-if [ -z "$part" -o -z "$image" ]; then
-	echo "define \$part and \$image"
-	exit 1
-fi
-
-if [ ! -e "$part" ]; then
-	echo "Partition $part does not exist"
-	exit 1
-fi
-
-if [ $# = 1 ]; then
-	image=$1
-fi
-
-if [ x$ip = xdhcp ]; then
-	dhcp
-fi
-
-ping $eth0.serverip
-if [ $? -ne 0 ] ; then
-	echo "update aborted"
-	exit 1
-fi
-
-unprotect $part
-
-echo
-echo "erasing partition $part"
-erase $part
-
-echo
-echo "flashing $image to $part"
-echo
-tftp $image $part
diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/boot b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/boot
deleted file mode 100644
index 7bbff2d1f6..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/boot
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = xnand ]; then
-	root=nand
-	kernel=nand
-fi
-
-if [ x$1 = xnet ]; then
-	root=net
-	kernel=net
-fi
-
-if [ x$1 = xnor ]; then
-	root=nor
-	kernel=nor
-fi
-
-if [ x$ip = xdhcp ]; then
-	bootargs="$bootargs ip=dhcp"
-else
-	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
-fi
-
-if [ x$root = xnand ]; then
-	bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
-elif [ x$root = xnor ]; then
-	bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
-else
-	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
-fi
-
-bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts"
-
-if [ $kernel = net ]; then
-	if [ x$ip = xdhcp ]; then
-		dhcp
-	fi
-	tftp $uimage uImage || exit 1
-	bootm uImage
-elif [ $kernel = nor ]; then
-	bootm /dev/nor0.kernel
-else
-	bootm /dev/nand0.kernel.bb
-fi
-
diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/init b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/init
deleted file mode 100644
index 8eafa34dc8..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/init
+++ /dev/null
@@ -1,26 +0,0 @@
-#!/bin/sh
-
-PATH=/env/bin
-export PATH
-
-. /env/config
-if [ -e /dev/nor0 ]; then
-	addpart /dev/nor0 $nor_parts
-fi
-
-if [ -e /dev/nand0 ]; then
-	addpart /dev/nand0 $nand_parts
-fi
-
-echo
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
-	echo
-	echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
-	echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
-	echo
-	exit
-fi
-
-boot
diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_kernel b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_kernel
deleted file mode 100644
index 05c822d860..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_kernel
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$uimage
-if [ x$1 = xnand ]; then
-	part=/dev/nand0.kernel.bb
-elif [ x$1 = xnor ]; then
-	part=/dev/nor0.kernel
-else
-	echo "usage: $0 nor|nand [imagename]"
-	exit 1
-fi
-
-. /env/bin/_update $2
diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_root b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_root
deleted file mode 100644
index eaf36ebcea..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_root
+++ /dev/null
@@ -1,16 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$uimage
-if [ x$1 = xnand ]; then
-	part=/dev/nand0.root.bb
-elif [ x$1 = xnor ]; then
-	part=/dev/nor0.root
-else
-	echo "usage: $0 nor|nand [imagename]"
-	exit 1
-fi
-
-. /env/bin/_update $2
-
diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/config b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/config
deleted file mode 100644
index 8469935b20..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/config
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/bin/sh
-
-# can be either 'net', 'nor' or 'nand''
-kernel=net
-root=net
-
-uimage=uImage-pcm043
-jffs2=root-pcm043.jffs2
-
-autoboot_timeout=3
-
-nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root"
-bootargs="console=ttymxc0,115200"
-
-nor_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),-(root)"
-rootpart_nor="/dev/mtdblock3"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),108416k(root),-(kernel1)"
-rootpart_nand="/dev/mtdblock7"
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-#ip=dhcp
-
-# or set your networking parameters here
-eth0.ipaddr=192.168.3.11
-eth0.netmask=255.255.255.0
-#eth0.gateway=a.b.c.d
-eth0.serverip=192.168.3.10
-#eth0.ethaddr=
diff --git a/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg b/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg
deleted file mode 100644
index 8c1a257829..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg
+++ /dev/null
@@ -1,42 +0,0 @@
-soc imx25
-loadaddr 0x80000000
-ivtofs 0x400
-wm 32 0xb8002050 0x0000d843
-wm 32 0xb8002054 0x22252521
-wm 32 0xb8002058 0x22220a00
-#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
-wm 32 0xb8001004 0x0076e83a
-wm 32 0xb8001010 0x00000304
-wm 32 0xb8001000 0x92210000
-wm 32 0x80000f00 0x12344321
-wm 32 0xb8001000 0xb2210000
-wm 8 0x82000000 0xda
-wm 8 0x83000000 0xda
-wm 8 0x81000400 0xda
-wm 8 0x80000333 0xda
-wm 32 0xb8001000 0x92210000
-wm 32 0x80000400 0x12344321
-wm 32 0xb8001000 0xa2210000
-wm 32 0x80000000 0x87654321
-wm 32 0x80000000 0x87654321
-wm 32 0xb8001000 0xb2210000
-wm 8 0x80000233 0xda
-wm 8 0x81000780 0xda
-wm 8 0x81000400 0xda
-wm 32 0xb8001000 0x82216080
-#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
-wm 32 0xb8001010 0x00000004
-wm 32 0xb8001000 0x92100000
-wm 8 0x80000400 0x21
-wm 32 0xb8001000 0xa2100000
-wm 32 0x80000000 0x12344321
-wm 32 0x80000000 0x12344321
-wm 32 0xb8001000 0xb2100000
-wm 8 0x80000033 0xda
-wm 8 0x81000000 0xff
-wm 32 0xb8001000 0x82216880
-wm 32 0xb8001004 0x00295729
-#else
-#error "Unsupported SDRAM type"
-#endif
-wm 32 0x53f80008 0x20034000
diff --git a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S
deleted file mode 100644
index 9be9c1a77b..0000000000
--- a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-#include <linux/sizes.h>
-#include <asm-generic/memory_layout.h>
-#include <mach/imx25-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/barebox-arm-head.h>
-
-#define writel(val, reg) \
-	ldr		r0,	=reg;	\
-	ldr		r1,	=val;	\
-	str		r1,	[r0];
-
-#define writeb(val, reg) \
-	ldr		r0,	=reg;	\
-	ldr		r1,	=val;	\
-	strb		r1,	[r0];
-
-/* Assuming 24MHz input clock */
-#define MPCTL_PARAM_532_MX25 \
-	(IMX_PLL_PD(1) | IMX_PLL_MFD(0) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
-
-.section ".text_bare_init","ax"
-
-ARM_PPMRR:              .word   0x40000015
-L2CACHE_PARAM:          .word   0x00030024
-CCM_CCMR_W:             .word   0x003F4208
-CCM_PDR0_W:             .word   0x00801000
-MPCTL_PARAM_399_W:      .word   MPCTL_PARAM_399
-MPCTL_PARAM_532_W:      .word   MPCTL_PARAM_532_MX25
-PPCTL_PARAM_W:    	.word   PPCTL_PARAM_300
-CCM_BASE_ADDR_W:        .word   MX25_CCM_BASE_ADDR
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-	bl arm_cpu_lowlevel_init
-
-#define MX25_CCM_MCR	0x64
-
-	ldr r0, CCM_BASE_ADDR_W
-	/* default CLKO to 1/32 of the ARM core */
-	ldr r1, [r0, #MX25_CCM_MCR]
-	bic r1, r1, #0x00F00000
-	bic r1, r1, #0x7F000000
-	mov r2,     #0x5F000000
-	add r2, r2, #0x00200000
-	orr r1, r1, r2
-	str r1, [r0, #MX25_CCM_MCR]
-
-	/* enable all the clocks */
-	writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0)
-	writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1)
-	writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2)
-	writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR)
-
-	/* Setup a temporary stack in SRAM */
-	ldr	sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4
-
-	/* Skip SDRAM initialization if we run from RAM */
-	cmp	pc, #0x80000000
-	bls	1f
-	cmp	pc, #0x90000000
-	bhi	1f
-
-	b	imx25_barebox_entry
-
-1:
-	ldr r0, ESDCTL_BASE_W
-	mov r3, #0x2000
-	str r3, [r0, #0x0]
-	str r3, [r0, #0x8]
-
-	mov r12, #0x00
-	mov r2, #0x1	/* mDDR */
-	mov r1, #MX25_CSD0_BASE_ADDR
-	bl setup_sdram_bank
-//	cmp r3, #0x0
-//	orreq r12, r12, #1
-//	eorne r2, r2, #0x1
-//	blne setup_sdram_bank
-
-	ldr r3, ESDCTL_DELAY5
-	str r3, [r0, #0x30]
-
-#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
-
-	mov	r0, #0
-	b	imx25_barebox_boot_nand_external
-#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
-
-ret:
-	b	imx25_barebox_entry
-
-/*
- * r0: control base, r1: ram bank base
- * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working
- */
-setup_sdram_bank:
-	mov r3, #0xE /* 0xA + 0x4 */
-	tst r2, #0x1
-	orreq r3, r3, #0x300 /* DDR2 */
-	str r3, [r0, #0x10]
-	bic r3, r3, #0x00A
-	str r3, [r0, #0x10]
-	beq 2f
-
-	mov r3, #0x20000
-1:	subs r3, r3, #1
-	bne 1b
-
-2:	adr r4, ESDCTL_CONFIG
-	tst r2, #0x1
-	ldreq r3, [r4, #0x0]
-	ldrne r3, [r4, #0x4]
-	cmp r1, #MX25_CSD1_BASE_ADDR
-	strlo r3, [r0, #0x4]
-	strhs r3, [r0, #0xC]
-
-	ldr r3, ESDCTL_0x92220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-	ldr r4, RAM_PARAM1_MDDR
-	strb r3, [r1, r4]
-
-	tst r2, #0x1
-	bne skip_set_mode
-
-	cmp r1, #MX25_CSD1_BASE_ADDR
-	ldr r3, ESDCTL_0xB2220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-	ldr r4, RAM_PARAM4_MDDR
-	strb r3, [r1, r4]
-	ldr r4, RAM_PARAM5_MDDR
-	strb r3, [r1, r4]
-	ldr r4, RAM_PARAM3_MDDR
-	strb r3, [r1, r4]
-	ldr r4, RAM_PARAM2_MDDR
-	strb r3, [r1, r4]
-
-	ldr r3, ESDCTL_0x92220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-	ldr r4, RAM_PARAM1_MDDR
-	strb r3, [r1, r4]
-
-skip_set_mode:
-	cmp r1, #MX25_CSD1_BASE_ADDR
-	ldr r3, ESDCTL_0xA2220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-	strb r3, [r1]
-	strb r3, [r1]
-
-	ldr r3, ESDCTL_0xB2220000
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-	adr r4, RAM_PARAM6_MDDR
-	tst r2, #0x1
-	ldreq r4, [r4, #0x0]
-	ldrne r4, [r4, #0x4]
-	mov r3, #0xDA
-	strb r3, [r1, r4]
-	ldreq r4, RAM_PARAM7_MDDR
-	streqb r3, [r1, r4]
-	adr r4, RAM_PARAM3_MDDR
-	ldreq r4, [r4, #0x0]
-	ldrne r4, [r4, #0x4]
-	strb r3, [r1, r4]
-
-	cmp r1, #MX25_CSD1_BASE_ADDR
-	ldr r3, ESDCTL_0x82226080
-	strlo r3, [r0, #0x0]
-	strhs r3, [r0, #0x8]
-
-	tst r2, #0x1
-	moveq r4, #0x20000
-	movne r4, #0x200
-1:	subs r4, r4, #1
-	bne 1b
-
-	str r3, [r1, #0x100]
-	ldr r4, [r1, #0x100]
-	cmp r3, r4
-	movne r3, #1
-	moveq r3, #0
-
-	mov pc, lr
-
-RAM_PARAM1_MDDR:	.word	0x00000400
-RAM_PARAM2_MDDR:	.word	0x00000333
-RAM_PARAM3_MDDR:	.word	0x02000400
-			.word	0x02000000
-RAM_PARAM4_MDDR:	.word	0x04000000
-RAM_PARAM5_MDDR:	.word	0x06000000
-RAM_PARAM6_MDDR:	.word	0x00000233
-			.word	0x00000033
-RAM_PARAM7_MDDR:	.word	0x02000780
-ESDCTL_0x92220000:	.word	0x92210000
-ESDCTL_0xA2220000:	.word	0xA2210000
-ESDCTL_0xB2220000:	.word	0xB2210000
-ESDCTL_0x82226080:	.word	0x82216080
-ESDCTL_CONFIG:		.word	0x007FFC3F
-			.word	0x007FFC3F
-ESDCTL_DELAY5:		.word	0x00F49F00
-ESDCTL_BASE_W:		.word	MX25_ESDCTL_BASE_ADDR
-
diff --git a/arch/arm/boards/freescale-mx27-ads/Makefile b/arch/arm/boards/freescale-mx27-ads/Makefile
deleted file mode 100644
index 398db9b6b9..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-lwl-y += lowlevel_init.o
-obj-y += imx27ads.o
diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/_update b/arch/arm/boards/freescale-mx27-ads/env/bin/_update
deleted file mode 100644
index 014bce3512..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/env/bin/_update
+++ /dev/null
@@ -1,36 +0,0 @@
-#!/bin/sh
-
-if [ -z "$part" -o -z "$image" ]; then
-	echo "define \$part and \$image"
-	exit 1
-fi
-
-if [ ! -e "$part" ]; then
-	echo "Partition $part does not exist"
-	exit 1
-fi
-
-if [ $# = 1 ]; then
-	image=$1
-fi
-
-if [ x$ip = xdhcp ]; then
-	dhcp
-fi
-
-ping $eth0.serverip
-if [ $? -ne 0 ] ; then
-	echo "update aborted"
-	exit 1
-fi
-
-unprotect $part
-
-echo
-echo "erasing partition $part"
-erase $part
-
-echo
-echo "flashing $image to $part"
-echo
-tftp $image $part
diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/boot b/arch/arm/boards/freescale-mx27-ads/env/bin/boot
deleted file mode 100644
index 3859dc113b..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/env/bin/boot
+++ /dev/null
@@ -1,38 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = xflash ]; then
-	root=flash
-	kernel=flash
-fi
-
-if [ x$1 = xnet ]; then
-	root=net
-	kernel=net
-fi
-
-if [ x$ip = xdhcp ]; then
-	bootargs="$bootargs ip=dhcp"
-else
-	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
-fi
-
-if [ x$root = xflash ]; then
-	bootargs="$bootargs root=$rootpart rootfstype=jffs2"
-else
-	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
-fi
-
-bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts"
-
-if [ $kernel = net ]; then
-	if [ x$ip = xdhcp ]; then
-		dhcp
-	fi
-	tftp $uimage uImage || exit 1
-	bootm uImage
-else
-	bootm /dev/nor0.kernel
-fi
-
diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/init b/arch/arm/boards/freescale-mx27-ads/env/bin/init
deleted file mode 100644
index 48e2139f7d..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/env/bin/init
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/bin/sh
-
-PATH=/env/bin
-export PATH
-
-. /env/config
-addpart /dev/nor0 $mtdparts
-
-echo
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
-	echo
-	echo "type update_kernel [<imagename>] to update kernel into flash"
-	echo "type udate_root [<imagename>] to update rootfs into flash"
-	echo
-	exit
-fi
-
-boot
\ No newline at end of file
diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/update_kernel b/arch/arm/boards/freescale-mx27-ads/env/bin/update_kernel
deleted file mode 100644
index 1ad95fc5d6..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/env/bin/update_kernel
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$uimage
-part=/dev/nor0.kernel
-
-. /env/bin/_update $1
diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/update_root b/arch/arm/boards/freescale-mx27-ads/env/bin/update_root
deleted file mode 100644
index b757a5b922..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/env/bin/update_root
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$jffs2
-part=/dev/nor0.root
-
-. /env/bin/_update $1
diff --git a/arch/arm/boards/freescale-mx27-ads/env/config b/arch/arm/boards/freescale-mx27-ads/env/config
deleted file mode 100644
index f18a86b7c1..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/env/config
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/bin/sh
-
-# can be either 'net' or 'flash'
-kernel=net
-root=net
-
-# use 'dhcp' todo dhcp in barebox and in kernel
-ip=dhcp
-
-eth0.ipaddr=192.168.23.164
-eth0.netmask=255.255.255.0
-eth0.gateway=192.168.23.2
-eth0.serverip=192.168.23.2
-
-uimage=uImage-mx27ads
-jffs2=root-mx27ads.jffs2
-
-autoboot_timeout=3
-
-nfsroot="/tmp/imx27ads"
-bootargs="console=ttymxc0,115200"
-
-mtdparts="128k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
-rootpart="/dev/mtdblock3"
-
diff --git a/arch/arm/boards/freescale-mx27-ads/imx27ads.c b/arch/arm/boards/freescale-mx27-ads/imx27ads.c
deleted file mode 100644
index 670ea2186f..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/imx27ads.c
+++ /dev/null
@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix
-
-#include <common.h>
-#include <net.h>
-#include <init.h>
-#include <environment.h>
-#include <mach/imx27-regs.h>
-#include <asm/armlinux.h>
-#include <io.h>
-#include <platform_data/eth-fec.h>
-#include <gpio.h>
-#include <mach/weim.h>
-#include <partition.h>
-#include <fs.h>
-#include <fcntl.h>
-#include <generated/mach-types.h>
-#include <mach/iomux-mx27.h>
-#include <mach/devices-imx27.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type = PHY_INTERFACE_MODE_MII,
-	.phy_addr = 1,
-};
-
-static int imx27ads_timing_init(void)
-{
-	/* configure cpld on cs4 */
-	imx27_setup_weimcs(4, 0x0000DCF6, 0x444A4541, 0x44443302);
-
-	/* configure synchronous mode for
-	 * 16 bit nor flash on cs0 */
-	imx27_setup_weimcs(0, 0x0000CC03, 0xa0330D01, 0x00220800);
-
-	writew(0x00f0, 0xc0000000);
-	writew(0x00aa, 0xc0000aaa);
-	writew(0x0055, 0xc0000554);
-	writew(0x00d0, 0xc0000aaa);
-	writew(0x66ca, 0xc0000aaa);
-	writew(0x00f0, 0xc0000000);
-
-	imx27_setup_weimcs(0, 0x23524E80, 0x10000D03, 0x00720900);
-
-	/* Select FEC data through data path */
-	writew(0x0020, MX27_CS4_BASE_ADDR + 0x10);
-
-	/* Enable CPLD FEC data path */
-	writew(0x0010, MX27_CS4_BASE_ADDR + 0x14);
-
-	return 0;
-}
-
-core_initcall(imx27ads_timing_init);
-
-static int mx27ads_devices_init(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PD0_AIN_FEC_TXD0,
-		PD1_AIN_FEC_TXD1,
-		PD2_AIN_FEC_TXD2,
-		PD3_AIN_FEC_TXD3,
-		PD4_AOUT_FEC_RX_ER,
-		PD5_AOUT_FEC_RXD1,
-		PD6_AOUT_FEC_RXD2,
-		PD7_AOUT_FEC_RXD3,
-		PD8_AF_FEC_MDIO,
-		PD9_AIN_FEC_MDC | GPIO_PUEN,
-		PD10_AOUT_FEC_CRS,
-		PD11_AOUT_FEC_TX_CLK,
-		PD12_AOUT_FEC_RXD0,
-		PD13_AOUT_FEC_RX_DV,
-		PD14_AOUT_FEC_RX_CLK,
-		PD15_AOUT_FEC_COL,
-		PD16_AIN_FEC_TX_ER,
-		PF23_AIN_FEC_TX_EN,
-		PE12_PF_UART1_TXD,
-		PE13_PF_UART1_RXD,
-		PE14_PF_UART1_CTS,
-		PE15_PF_UART1_RTS,
-	};
-
-	/* initizalize gpios */
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx27_gpio_mode(mode[i]);
-
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0);
-
-	imx27_add_fec(&fec_info);
-	devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0");
-	devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
-	protect_file("/dev/env0", 1);
-
-	armlinux_set_architecture(MACH_TYPE_MX27ADS);
-
-	return 0;
-}
-
-device_initcall(mx27ads_devices_init);
-
-static int mx27ads_console_init(void)
-{
-	barebox_set_model("Freescale i.MX27 ADS");
-	barebox_set_hostname("mx27ads");
-
-	imx27_add_uart0();
-	return 0;
-}
-
-console_initcall(mx27ads_console_init);
-
diff --git a/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S
deleted file mode 100644
index e79b96dd2c..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
- * Applications Processor Reference Manual, Rev. 0.2".
- *
- */
-
-#include <config.h>
-#include <mach/imx27-regs.h>
-#include <asm/barebox-arm-head.h>
-
-#define writel(val, reg) \
-	ldr		r0,	=reg;	\
-	ldr		r1,	=val;	\
-	str		r1,   [r0];
-
-#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn)  (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
-
-.macro sdram_init
-	/*
-	 * DDR on CSD0
-	 */
-	writel(0x00000008, 0xD8001010)
-	writel(0x55555555, 0x10027828)
-	writel(0x55555555, 0x10027830)
-	writel(0x55555555, 0x10027834)
-	writel(0x00005005, 0x10027838)
-	writel(0x15555555, 0x1002783C)
-	writel(0x00000004, 0xD8001010)
-	writel(0x006ac73a, 0xD8001004)
-	writel(0x92100000, 0xD8001000)
-	writel(0x00000000, 0xA0000F00)
-	writel(0xA2100000, 0xD8001000)
-	writel(0x00000000, 0xA0000F00)
-	writel(0x00000000, 0xA0000F00)
-	writel(0x00000000, 0xA0000F00)
-	writel(0x00000000, 0xA0000F00)
-	writel(0xA2200000, 0xD8001000)
-	writel(0x00000000, 0xA0000F00)
-	writel(0x00000000, 0xA0000F00)
-	writel(0x00000000, 0xA0000F00)
-	writel(0x00000000, 0xA0000F00)
-	writel(0xb2100000, 0xD8001000)
-	ldr		r0, =0xA0000033
-	mov		r1, #0xda
-	strb		r1, [r0]
-	ldr		r0, =0xA1000000
-	mov		r1, #0xff
-	strb		r1, [r0]
-	writel(0x82226080, 0xD8001000)
-.endm
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-
-	bl arm_cpu_lowlevel_init
-
-	ldr	sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4;
-
-	/* ahb lite ip interface */
-	writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
-	writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
-	writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
-	writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
-
-	/* disable mpll/spll */
-	ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR
-	ldr r1, [r0]
-	bic r1, r1, #0x03
-	str r1, [r0]
-
-	/*
-	 * pll clock initialization - see section 3.4.3 of the i.MX27 manual
-	 *
-	 * FIXME: Using the 399*2 MHz values from table 3-8 doens't work
-	 *        with 1.2 V core voltage! Find out if this is
-	 *        documented somewhere.
-	 */
-	writel(0x00191403, MX27_CCM_BASE_ADDR + MX27_MPCTL0)	/* MPLL = 199.5*2 MHz               */
-	writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0)	/* SPLL = FIXME (needs review)      */
-
-	/*
-	 * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
-	 * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
-	 * System clock (HCLK) = 133 MHz
-	 */
-	writel(0x33F30307 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
-			MX27_CCM_BASE_ADDR + MX27_CSCR)
-
-	/* add some delay here */
-	mov r1, #0x1000
-1:	subs r1, r1, #0x1
-	bne 1b
-
-	/* clock gating enable */
-	writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR)
-
-	/* peripheral clock divider */
-	/* FIXME                            */
-	writel(0x23C8F403, MX27_CCM_BASE_ADDR + MX27_PCDR0)
-	/* PERDIV1=08 @133 MHz              */
-	/* PERDIV1=04 @266 MHz              */
-	writel(0x09030913, MX27_CCM_BASE_ADDR + MX27_PCDR1)
-	/* skip sdram initialization if we run from ram */
-	cmp	pc, #0xa0000000
-	bls	1f
-	cmp	pc, #0xc0000000
-	bhi	1f
-
-	b imx27_barebox_entry
-1:
-	sdram_init
-
-	b imx27_barebox_entry
-
diff --git a/arch/arm/boards/freescale-mx28-evk/Makefile b/arch/arm/boards/freescale-mx28-evk/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/freescale-mx28-evk/Makefile
+++ b/arch/arm/boards/freescale-mx28-evk/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx28-evk/board.c b/arch/arm/boards/freescale-mx28-evk/board.c
index 92097a2bca..1c5d2da5a6 100644
--- a/arch/arm/boards/freescale-mx28-evk/board.c
+++ b/arch/arm/boards/freescale-mx28-evk/board.c
@@ -9,7 +9,7 @@
 #include <common.h>
 #include <init.h>
 #include <net.h>
-#include <mach/ocotp.h>
+#include <mach/mxs/ocotp.h>
 
 static void mx28_evk_get_ethaddr(void)
 {
diff --git a/arch/arm/boards/freescale-mx28-evk/lowlevel.c b/arch/arm/boards/freescale-mx28-evk/lowlevel.c
index 82411bb516..42ac33fbbd 100644
--- a/arch/arm/boards/freescale-mx28-evk/lowlevel.c
+++ b/arch/arm/boards/freescale-mx28-evk/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define pr_fmt(fmt) "Freescale MX28evk: " fmt
 #define DEBUG
 
@@ -5,11 +7,11 @@
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx28-regs.h>
-#include <mach/init.h>
+#include <mach/mxs/imx28-regs.h>
+#include <mach/mxs/init.h>
 #include <io.h>
 #include <debug_ll.h>
-#include <mach/iomux.h>
+#include <mach/mxs/iomux.h>
 #include <stmp-device.h>
 
 extern char __dtb_imx28_evk_start[];
diff --git a/arch/arm/boards/freescale-mx35-3ds/3stack.c b/arch/arm/boards/freescale-mx35-3ds/3stack.c
deleted file mode 100644
index 5b91c601f8..0000000000
--- a/arch/arm/boards/freescale-mx35-3ds/3stack.c
+++ /dev/null
@@ -1,455 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2007 Sascha Hauer, Pengutronix
- *               2009 Marc Kleine-Budde, Pengutronix
- *
- * Derived from:
- *
- * * mx35_3stack.c - board file for uboot-v1
- *   Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *   (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <environment.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <platform_data/eth-fec.h>
-#include <fs.h>
-#include <init.h>
-#include <nand.h>
-#include <net.h>
-#include <envfs.h>
-#include <linux/sizes.h>
-#include <partition.h>
-#include <gpio.h>
-
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <asm/barebox-arm.h>
-#include <io.h>
-#include <generated/mach-types.h>
-
-#include <mach/weim.h>
-#include <mach/imx-nand.h>
-#include <mach/imx35-regs.h>
-#include <mach/iomux-mx35.h>
-#include <mach/iomux-v3.h>
-#include <mach/imx-ipu-fb.h>
-#include <mach/generic.h>
-#include <mach/devices-imx35.h>
-#include <mach/revision.h>
-
-#include <i2c/i2c.h>
-#include <mfd/mc13xxx.h>
-#include <mfd/mc9sdz60.h>
-
-
-/* Board rev for the PDK 3stack */
-#define MX35PDK_BOARD_REV_1		0
-#define MX35PDK_BOARD_REV_2		1
-
-static struct fec_platform_data fec_info = {
-	.xcv_type	= PHY_INTERFACE_MODE_MII,
-	.phy_addr	= 0x1F,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.hw_ecc		= 1,
-	.flash_bbt	= 1,
-};
-
-static struct i2c_board_info i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("mc13892", 0x08),
-	}, {
-		I2C_BOARD_INFO("mc9sdz60", 0x69),
-	},
-};
-
-/*
- * Generic display, shipped with the PDK
- */
-static struct fb_videomode CTP_CLAA070LC0ACW = {
-	/* 800x480 @ 60 Hz */
-	.name		= "CTP-CLAA070LC0ACW",
-	.refresh	= 60,
-	.xres		= 800,
-	.yres		= 480,
-	.pixclock	= KHZ2PICOS(27000),
-	.left_margin	= 50,
-	.right_margin	= 50,	/* whole line should have 900 clocks */
-	.upper_margin	= 10,
-	.lower_margin	= 10,	/* whole frame should have 500 lines */
-	.hsync_len	= 1,	/* note: DE only display */
-	.vsync_len	= 1,	/* note: DE only display */
-	.sync		= FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
-	.vmode		= FB_VMODE_NONINTERLACED,
-};
-
-static struct imx_ipu_fb_platform_data ipu_fb_data = {
-	.mode		= &CTP_CLAA070LC0ACW,
-	.num_modes	= 1,
-	.bpp		= 16,
-};
-
-/*
- * Revision to be passed to kernel. The kernel provided
- * by freescale relies on this.
- *
- * C --> CPU type
- * S --> Silicon revision
- * B --> Board rev
- *
- * 31    20     16     12    8      4     0
- *        | Cmaj | Cmin | B  | Smaj | Smin|
- *
- * e.g 0x00035120 --> i.MX35, Cpu silicon rev 2.0, Board rev 2
-*/
-static unsigned int imx35_3ds_system_rev = 0x00035000;
-
-static void set_silicon_rev( int rev)
-{
-	imx35_3ds_system_rev = imx35_3ds_system_rev | (rev & 0xFF);
-}
-
-static void set_board_rev(int rev)
-{
-	imx35_3ds_system_rev =  (imx35_3ds_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-
-static const struct devfs_partition f3s_nand0_partitions[] = {
-	{
-		.offset = 0,
-		.size = 0x40000,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "self_raw",
-		.bbname = "self0",
-	}, {
-		.offset = DEVFS_PARTITION_APPEND, /* 0x40000 */
-		.size = 0x80000,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "env_raw",
-		.bbname = "env0",
-	}, {
-		/* sentinel */
-	}
-};
-
-static const struct devfs_partition f3s_nor0_partitions[] = {
-	{
-		.offset = 0,
-		.size = 0x40000,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "self0",
-	}, {
-		.offset = DEVFS_PARTITION_APPEND, /* 0x40000 */
-		.size = 0x80000,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "env0",
-	}, {
-		/* sentinel */
-	}
-};
-
-static int f3s_devices_init(void)
-{
-	uint32_t reg;
-
-	/* CS0: Nor Flash */
-	imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
-
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
-	/* some fuses provide us vital information about connected hardware */
-	if (reg & 0x20000000)
-		nand_info.width = 2;	/* 16 bit */
-	else
-		nand_info.width = 1;	/* 8 bit */
-
-	/*
-	 * This platform supports NOR and NAND
-	 */
-	imx35_add_nand(&nand_info);
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0);
-
-	switch ((reg >> 25) & 0x3) {
-	case 0x01:		/* NAND is the source */
-		devfs_create_partitions("nand0", f3s_nand0_partitions);
-		break;
-
-	case 0x00:		/* NOR is the source */
-		devfs_create_partitions("nor0", f3s_nor0_partitions);
-		protect_file("/dev/env0", 1);
-		break;
-	}
-
-	set_silicon_rev(imx_silicon_revision());
-
-	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
-	imx35_add_i2c0(NULL);
-
-	imx35_add_fec(&fec_info);
-	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL,	MX35_CS5_BASE_ADDR, MX35_CS5_SIZE,
-			IORESOURCE_MEM, NULL);
-
-	imx35_add_mmc0(NULL);
-
-	imx35_add_fb(&ipu_fb_data);
-
-	armlinux_set_architecture(MACH_TYPE_MX35_3DS);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_freescale_mx35_3ds);
-
-	return 0;
-}
-
-device_initcall(f3s_devices_init);
-
-static int f3s_enable_display(void)
-{
-	/* Enable power to the LCD. (bit 6 hi.) */
-	mc9sdz60_set_bits(mc9sdz60_get(), MC9SDZ60_REG_GPIO_1, 0x40, 0x40);
-
-	return 0;
-}
-
-late_initcall(f3s_enable_display);
-
-static iomux_v3_cfg_t f3s_pads[] = {
-	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
-	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
-	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
-	MX35_PAD_FEC_COL__FEC_COL,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX35_PAD_FEC_MDC__FEC_MDC,
-	MX35_PAD_FEC_MDIO__FEC_MDIO,
-	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
-	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
-	MX35_PAD_FEC_CRS__FEC_CRS,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
-	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
-	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
-	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
-	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
-	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
-
-	MX35_PAD_RXD1__UART1_RXD_MUX,
-	MX35_PAD_TXD1__UART1_TXD_MUX,
-	MX35_PAD_RTS1__UART1_RTS,
-	MX35_PAD_CTS1__UART1_CTS,
-
-	MX35_PAD_I2C1_CLK__I2C1_SCL,
-	MX35_PAD_I2C1_DAT__I2C1_SDA,
-
-	MX35_PAD_WDOG_RST__GPIO1_6,
-	MX35_PAD_COMPARE__GPIO1_5,
-
-	/* Display */
-	MX35_PAD_LD0__IPU_DISPB_DAT_0,
-	MX35_PAD_LD1__IPU_DISPB_DAT_1,
-	MX35_PAD_LD2__IPU_DISPB_DAT_2,
-	MX35_PAD_LD3__IPU_DISPB_DAT_3,
-	MX35_PAD_LD4__IPU_DISPB_DAT_4,
-	MX35_PAD_LD5__IPU_DISPB_DAT_5,
-	MX35_PAD_LD6__IPU_DISPB_DAT_6,
-	MX35_PAD_LD7__IPU_DISPB_DAT_7,
-	MX35_PAD_LD8__IPU_DISPB_DAT_8,
-	MX35_PAD_LD9__IPU_DISPB_DAT_9,
-	MX35_PAD_LD10__IPU_DISPB_DAT_10,
-	MX35_PAD_LD11__IPU_DISPB_DAT_11,
-	MX35_PAD_LD12__IPU_DISPB_DAT_12,
-	MX35_PAD_LD13__IPU_DISPB_DAT_13,
-	MX35_PAD_LD14__IPU_DISPB_DAT_14,
-	MX35_PAD_LD15__IPU_DISPB_DAT_15,
-	MX35_PAD_LD16__IPU_DISPB_DAT_16,
-	MX35_PAD_LD17__IPU_DISPB_DAT_17,
-	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
-	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
-	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
-	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
-	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
-	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
-	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
-};
-
-static int f3s_console_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads));
-
-	barebox_set_model("Freescale i.MX35 3DS");
-	barebox_set_hostname("mx35-3stack");
-
-	imx35_add_uart0();
-	return 0;
-}
-
-console_initcall(f3s_console_init);
-
-static int f3s_core_init(void)
-{
-	u32 reg;
-
-	/* CS5: smc9117 */
-	imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00);
-
-	/* enable clock for I2C1 and FEC */
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
-	reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
-	reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
-	reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
-
-	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
-
-	/*
-	 * Clear the on and off peripheral modules Supervisor Protect bit
-	 * for SDMA to access them. Did not change the AIPS control registers
-	 * (offset 0x20) access type
-	 */
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
-	reg = readl(MX35_AIPS1_BASE_ADDR + 0x50);
-	reg &= 0x00FFFFFF;
-	writel(reg, MX35_AIPS1_BASE_ADDR + 0x50);
-
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
-	reg = readl(MX35_AIPS2_BASE_ADDR + 0x50);
-	reg &= 0x00FFFFFF;
-	writel(reg, MX35_AIPS2_BASE_ADDR + 0x50);
-
-	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-
-	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
-
-	/* SGPCR - always park on last master */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
-
-	/* MGPCR - restore default values */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
-
-	return 0;
-}
-
-core_initcall(f3s_core_init);
-
-static int f3s_get_rev(struct mc13xxx *mc13xxx)
-{
-	u32 rev;
-	int err;
-
-	err = mc13xxx_reg_read(mc13xxx, MC13XXX_REG_IDENTIFICATION, &rev);
-	if (err)
-		return err;
-
-	if (rev == 0x00ffffff)
-		return -ENODEV;
-
-	return ((rev >> 6) & 0x7) ? MX35PDK_BOARD_REV_2 : MX35PDK_BOARD_REV_1;
-}
-
-static int f3s_pmic_init_v2(struct mc13xxx *mc13xxx)
-{
-	int err = 0;
-
-	/* COMPARE pin (GPIO1_5) as output and set high */
-	gpio_direction_output( 32*0 + 5 , 1);
-
-	err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_SETTING_0, 0x03, 0x03);
-	err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_MODE_0, 0x01, 0x01);
-	if (err)
-		printf("mc13892 Init sequence failed, the system might not be working!\n");
-
-	return err;
-}
-
-static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60)
-{
-	int err = 0;
-
-	err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_1, 0x04, 0x04);
-
-	err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x00);
-	mdelay(200);
-	err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x80);
-
-	if (err)
-		dev_err(&mc9sdz60->client->dev,
-			"Init sequence failed, the system might not be working!\n");
-
-	return err;
-}
-
-static int f3s_pmic_init(void)
-{
-	struct mc13xxx *mc13xxx;
-	struct mc9sdz60 *mc9sdz60;
-	int rev;
-
-	mc13xxx = mc13xxx_get();
-	if (!mc13xxx) {
-		printf("FAILED to get PMIC handle!\n");
-		return 0;
-	}
-
-	rev = f3s_get_rev(mc13xxx);
-	switch (rev) {
-	case MX35PDK_BOARD_REV_1:
-		break;
-	case MX35PDK_BOARD_REV_2:
-		f3s_pmic_init_v2(mc13xxx);
-		break;
-	default:
-		printf("FAILED to identify board revision!\n");
-		return 0;
-	}
-
-	set_board_rev(rev);
-	printf("i.MX35 PDK CPU board version %d.\n", rev );
-
-	mc9sdz60 = mc9sdz60_get();
-	if (!mc9sdz60) {
-		printf("FAILED to get mc9sdz60 handle!\n");
-		return 0;
-	}
-
-	f3s_pmic_init_all(mc9sdz60);
-
-	armlinux_set_revision(imx35_3ds_system_rev);
-
-	return 0;
-}
-
-late_initcall(f3s_pmic_init);
diff --git a/arch/arm/boards/freescale-mx35-3ds/Makefile b/arch/arm/boards/freescale-mx35-3ds/Makefile
deleted file mode 100644
index c192854f0b..0000000000
--- a/arch/arm/boards/freescale-mx35-3ds/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y					+= 3stack.o
-lwl-y					+= lowlevel_init.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-freescale-mx35-3ds
diff --git a/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h b/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h
deleted file mode 100644
index 9d0d492062..0000000000
--- a/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-// SPDX-FileCopyrightText: 2008 Freescale Semiconductor, Inc.
-
-#ifndef __BOARD_MX35_3STACK_H
-#define __BOARD_MX35_3STACK_H
-
-#define UNALIGNED_ACCESS_ENABLE
-#define LOW_INT_LATENCY_ENABLE
-#define BRANCH_PREDICTION_ENABLE
-
-#define L2CC_AUX_CTL_CONFIG	0x00030024
-
-#define AIPS_MPR_CONFIG		0x77777777
-#define AIPS_OPACR_CONFIG	0x00000000
-
-/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_MPR_CONFIG		0x00302154
-/* SGPCR - always park on last master */
-#define MAX_SGPCR_CONFIG	0x00000010
-/* MGPCR - restore default values */
-#define MAX_MGPCR_CONFIG	0x00000000
-
-/*
- * M3IF Control Register (M3IFCTL)
- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
- *                                               ------------
- *                                                 0x00000040
- */
-#define M3IF_CONFIG	0x00000040
-
-#define DBG_BASE_ADDR		WEIM_CTRL_CS5
-#define DBG_CSCR_U_CONFIG	0x0000D843
-#define DBG_CSCR_L_CONFIG	0x22252521
-#define DBG_CSCR_A_CONFIG	0x22220A00
-
-#define CCM_CCMR_CONFIG		0x003F4208
-#define CCM_PDR0_CONFIG		0x00821000
-
-#define PLL_BRM_OFFSET	31
-#define PLL_PD_OFFSET	26
-#define PLL_MFD_OFFSET	16
-#define PLL_MFI_OFFSET	10
-
-#define _PLL_BRM(x)	((x) << PLL_BRM_OFFSET)
-#define _PLL_PD(x)	(((x) - 1) << PLL_PD_OFFSET)
-#define _PLL_MFD(x)	(((x) - 1) << PLL_MFD_OFFSET)
-#define _PLL_MFI(x)	((x) << PLL_MFI_OFFSET)
-#define _PLL_MFN(x)	(x)
-#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
-	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
-	 _PLL_MFN(mfn))
-
-#define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
-#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
-#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
-
-/*MEMORY SETING*/
-#define ESDCTL_0x92220000	0x92220000
-#define ESDCTL_0xA2220000	0xA2220000
-#define ESDCTL_0xB2220000	0xB2220000
-#define ESDCTL_0x82228080 	0x82228080
-
-#define ESDCTL_PRECHARGE	0x00000400
-
-#define ESDCTL_MDDR_CONFIG 	0x007FFC3F
-#define ESDCTL_MDDR_MR		0x00000033
-#define ESDCTL_MDDR_EMR		0x02000000
-
-#define ESDCTL_DDR2_CONFIG 	0x007FFC3F
-#define ESDCTL_DDR2_EMR2	0x04000000
-#define ESDCTL_DDR2_EMR3	0x06000000
-#define ESDCTL_DDR2_EN_DLL	0x02000400
-#define ESDCTL_DDR2_RESET_DLL	0x00000333
-#define ESDCTL_DDR2_MR		0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-
-#define ESDCTL_DELAY_LINE5	0x00F49F00
-#endif				/* __BOARD_MX35_3STACK_H */
diff --git a/arch/arm/boards/freescale-mx35-3ds/defaultenv-freescale-mx35-3ds/config b/arch/arm/boards/freescale-mx35-3ds/defaultenv-freescale-mx35-3ds/config
deleted file mode 100644
index af2fb6b2bc..0000000000
--- a/arch/arm/boards/freescale-mx35-3ds/defaultenv-freescale-mx35-3ds/config
+++ /dev/null
@@ -1,51 +0,0 @@
-#!/bin/sh
-
-eth0.serverip=
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nor', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${global.hostname}.$rootfs_type
-
-kernelimage=zImage-${global.hostname}
-#kernelimage=uImage-${global.hostname}
-#kernelimage=Image-${global.hostname}
-#kernelimage=Image-${global.hostname}.lzo
-
-if [ -n $user ]; then
-	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
-	rootfsimage="$user"-"$rootfsimage"
-else
-	nfsroot="$eth0.serverip:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-bootargs="console=ttymxc0,115200"
-
-nor_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)"
-rootfs_mtdblock_nor=3
-
-nand_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)"
-rootfs_mtdblock_nand=7
-nand_device=mxc_nand
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
-
diff --git a/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg b/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg
deleted file mode 100644
index ea1803b7de..0000000000
--- a/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg
+++ /dev/null
@@ -1,34 +0,0 @@
-soc imx35
-loadaddr 0x80000000
-ivtofs 0x400
-
-wm 32 0xb8002050 0x0000d843
-wm 32 0xb8002054 0x22252521
-wm 32 0xb8002058 0x22220a00
-wm 32 0xb8001010 0x00000304
-wm 32 0xb8001010 0x0000030c
-wm 32 0xb8001004 0x007ffc3f
-wm 32 0xb800100c 0x007ffc3f
-wm 32 0xb8001000 0x92220000
-wm 32 0xb8001008 0x92220000
-wm 32 0x80000400 0x12345678
-wm 32 0x90000400 0x12345678
-wm 32 0xb8001000 0xa2220000
-wm 32 0xb8001008 0xa2220000
-wm 32 0x80000000 0x87654321
-wm 32 0x90000000 0x87654321
-wm 32 0x80000000 0x87654321
-wm 32 0x90000000 0x87654321
-wm 32 0xb8001000 0xb2220000
-wm 32 0xb8001008 0xb2220000
-wm 8 0x80000233 0xda
-wm 8 0x90000233 0xda
-wm 8 0x82000780 0xda
-wm 8 0x92000780 0xda
-wm 8 0x82000400 0xda
-wm 8 0x92000400 0xda
-wm 32 0xb8001000 0x82226080
-wm 32 0xb8001008 0x82226080
-wm 32 0xb8001004 0x007ffc3f
-wm 32 0xb800100c 0x007ffc3f
-wm 32 0xb8001010 0x00000304
diff --git a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S
deleted file mode 100644
index fbc08d8fae..0000000000
--- a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-#include <mach/imx35-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/cache-l2x0.h>
-#include <asm-generic/memory_layout.h>
-#include <asm/barebox-arm-head.h>
-
-#include "board-mx35_3stack.h"
-
-#define CSD0_BASE_ADDR		0x80000000
-#define CSD1_BASE_ADDR		0x90000000
-#define ESDCTL_BASE_ADDR	0xB8001000
-
-#define writel(val, reg) \
-	ldr		r0,	=reg;	\
-	ldr		r1,	=val;	\
-	str		r1,	[r0];
-
-#define writeb(val, reg) \
-	ldr		r0,	=reg;	\
-	ldr		r1,	=val;	\
-	strb		r1,	[r0];
-
-	.section ".text_bare_init","ax"
-
-ARM_PPMRR:		.word	0x40000015
-L2CACHE_PARAM:		.word	0x00030024
-CCM_CCMR_W:		.word	0x003F4208
-CCM_PDR0_W:		.word	0x00001000
-MPCTL_PARAM_399_W:	.word	MPCTL_PARAM_399
-MPCTL_PARAM_532_W:	.word	MPCTL_PARAM_532
-PPCTL_PARAM_W:		.word	PPCTL_PARAM_300
-CCM_BASE_ADDR_W:	.word	MX35_CCM_BASE_ADDR
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-	bl	arm_cpu_lowlevel_init
-
-	/* Setup a temporary stack in internal SRAM */
-	ldr	sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4
-
-	mrc	15, 0, r1, c1, c0, 0
-
-	mrc	15, 0, r0, c1, c0, 1
-	orr	r0, r0, #7
-	mcr	15, 0, r0, c1, c0, 1
-
-	orr	r1, r1, #(1 << 11)		/* Flow prediction (Z) */
-	orr	r1, r1, #(1 << 22)		/* unaligned accesses */
-	orr	r1, r1, #(1 << 21)		/* Low Int Latency */
-
-	mcr	15, 0, r1, c1, c0, 0
-
-	mov	r0, #0
-	mcr	15, 0, r0, c15, c2, 4
-
-	/*
-	 * Branch predicition is now enabled. Flush the BTAC to ensure a valid
-	 * starting point. Don't flush BTAC while it is disabled to avoid
-	 * ARM1136 erratum 408023.
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 6		/* flush entire BTAC */
-
-	mov	r0, #0
-	mcr	15, 0, r0, c7, c7, 0		/* invalidate I cache and D cache */
-	mcr	15, 0, r0, c8, c7, 0		/* invalidate TLBs */
-	mcr	15, 0, r0, c7, c10, 4		/* Drain the write buffer */
-
-	/* Also setup the Peripheral Port Remap register inside the core */
-	ldr	r0, ARM_PPMRR			/* start from AIPS 2GB region */
-	mcr	p15, 0, r0, c15, c2, 4
-
-/*
- * End of ARM1136 init
- */
-	ldr	r0, CCM_BASE_ADDR_W
-
-	ldr	r2, CCM_CCMR_W
-	str	r2, [r0, #MX35_CCM_CCMR]
-
-	ldr	r3, MPCTL_PARAM_532_W		/* consumer path*/
-
-	/* Set MPLL, arm clock and ahb clock */
-	str	r3, [r0, #MX35_CCM_MPCTL]
-
-	ldr	r1, PPCTL_PARAM_W
-	str	r1, [r0, #MX35_CCM_PPCTL]
-
-	ldr	r1, CCM_PDR0_W
-	str	r1, [r0, #MX35_CCM_PDR0]
-
-	ldr	r1, [r0, #MX35_CCM_CGR0]
-	orr	r1, r1, #0x00300000
-	str	r1, [r0, #MX35_CCM_CGR0]
-
-	ldr	r1, [r0, #MX35_CCM_CGR1]
-	orr	r1, r1, #0x00000C00
-	orr	r1, r1, #0x00000003
-	str	r1, [r0, #MX35_CCM_CGR1]
-
-	/* Skip SDRAM initialization if we run from RAM */
-	cmp	pc, #CSD0_BASE_ADDR
-	bls	1f
-	cmp	pc, #CSD1_BASE_ADDR
-	bhi	1f
-
-	b	imx35_barebox_entry
-
-1:
-	ldr	r0, =ESDCTL_BASE_ADDR
-	mov	r3, #0x2000
-	str	r3, [r0, #0x0]
-	str	r3, [r0, #0x8]
-
-	/* ip(r12) has used to save lr register in upper calling */
-	mov	fp, lr
-
-	/* setup bank 0 */
-	mov	r5, #0x00
-	mov	r2, #0x00
-	mov	r1, #MX35_CSD0_BASE_ADDR
-	bl	setup_sdram_bank
-
-	/* setup bank 1 */
-	mov	r5, #0x00
-	mov	r2, #0x00
-	mov	r1, #MX35_CSD1_BASE_ADDR
-	bl	setup_sdram_bank
-
-	mov	lr, fp
-
-	ldr	r3, =ESDCTL_DELAY_LINE5
-	str	r3, [r0, #0x30]
-
-#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
-	mov	r0, #0
-	b	imx35_barebox_boot_nand_external
-#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
-
-	b	imx35_barebox_entry
-
-/*
- * r0: ESDCTL control base, r1: sdram slot base
- * r2: DDR type (0: DDR2, 1: MDDR) r3, r4: working base
- */
-setup_sdram_bank:
-	mov	r3, #0xE			/* 0xA + 0x4 */
-	tst	r2, #0x1
-	orreq	r3, r3, #0x300			/* DDR2 */
-	str	r3, [r0, #0x10]
-	bic	r3, r3, #0x00A
-	str	r3, [r0, #0x10]
-	beq	2f
-
-	mov	r3, #0x20000
-1:	subs	r3, r3, #1
-	bne	1b
-
-2:	tst	r2, #0x1
-	ldreq	r3, =ESDCTL_DDR2_CONFIG
-	ldrne	r3, =ESDCTL_MDDR_CONFIG
-	cmp	r1, #CSD1_BASE_ADDR
-	strlo	r3, [r0, #0x4]
-	strhs	r3, [r0, #0xC]
-
-	ldr	r3, =ESDCTL_0x92220000
-	strlo	r3, [r0, #0x0]
-	strhs	r3, [r0, #0x8]
-	mov	r3, #0xDA
-	ldr	r4, =ESDCTL_PRECHARGE
-	strb	r3, [r1, r4]
-
-	tst	r2, #0x1
-	bne	skip_set_mode
-
-	cmp	r1, #CSD1_BASE_ADDR
-	ldr	r3, =ESDCTL_0xB2220000
-	strlo	r3, [r0, #0x0]
-	strhs	r3, [r0, #0x8]
-	mov	r3, #0xDA
-	ldr	r4, =ESDCTL_DDR2_EMR2
-	strb	r3, [r1, r4]
-	ldr	r4, =ESDCTL_DDR2_EMR3
-	strb	r3, [r1, r4]
-	ldr	r4, =ESDCTL_DDR2_EN_DLL
-	strb	r3, [r1, r4]
-	ldr	r4, =ESDCTL_DDR2_RESET_DLL
-	strb	r3, [r1, r4]
-
-	ldr	r3, =ESDCTL_0x92220000
-	strlo	r3, [r0, #0x0]
-	strhs	r3, [r0, #0x8]
-	mov	r3, #0xDA
-	ldr	r4, =ESDCTL_PRECHARGE
-	strb	r3, [r1, r4]
-
-skip_set_mode:
-	cmp	r1, #CSD1_BASE_ADDR
-	ldr	r3, =ESDCTL_0xA2220000
-	strlo	r3, [r0, #0x0]
-	strhs	r3, [r0, #0x8]
-	mov	r3, #0xDA
-	strb	r3, [r1]
-	strb	r3, [r1]
-
-	ldr	r3, =ESDCTL_0xB2220000
-	strlo	r3, [r0, #0x0]
-	strhs	r3, [r0, #0x8]
-	tst	r2, #0x1
-	ldreq	r4, =ESDCTL_DDR2_MR
-	ldrne	r4, =ESDCTL_MDDR_MR
-	mov	r3, #0xDA
-	strb	r3, [r1, r4]
-	ldreq	r4, =ESDCTL_DDR2_OCD_DEFAULT
-	streqb	r3, [r1, r4]
-	ldreq	r4, =ESDCTL_DDR2_EN_DLL
-	ldrne	r4, =ESDCTL_MDDR_EMR
-	strb	r3, [r1, r4]
-
-	cmp	r1, #CSD1_BASE_ADDR
-	ldr	r3, =ESDCTL_0x82228080
-	strlo	r3, [r0, #0x0]
-	strhs	r3, [r0, #0x8]
-
-	tst	r2, #0x1
-	moveq	r4, #0x20000
-	movne	r4, #0x200
-1:	subs	r4, r4, #1
-	bne	1b
-
-	str	r3, [r1, #0x100]
-	ldr	r4, [r1, #0x100]
-	cmp	r3, r4
-	movne	r3, #1
-	moveq	r3, #0
-
-	mov	pc, lr
diff --git a/arch/arm/boards/freescale-mx51-babbage/Makefile b/arch/arm/boards/freescale-mx51-babbage/Makefile
index b6e085818f..aed38f2eaa 100644
--- a/arch/arm/boards/freescale-mx51-babbage/Makefile
+++ b/arch/arm/boards/freescale-mx51-babbage/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-$(CONFIG_MACH_FREESCALE_MX51_PDK_POWER) += power.o
 obj-$(CONFIG_MACH_FREESCALE_MX51_PDK) += board.o
 lwl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx51-babbage/board.c b/arch/arm/boards/freescale-mx51-babbage/board.c
index 330d8e4f52..76bdc78b02 100644
--- a/arch/arm/boards/freescale-mx51-babbage/board.c
+++ b/arch/arm/boards/freescale-mx51-babbage/board.c
@@ -6,27 +6,26 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/imx51-regs.h>
+#include <mach/imx/imx51-regs.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <of.h>
 #include <fcntl.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <nand.h>
 #include <notifier.h>
 #include <spi/spi.h>
 #include <io.h>
 #include <asm/mmu.h>
-#include <mach/imx5.h>
-#include <mach/imx-nand.h>
-#include <mach/spi.h>
-#include <mach/generic.h>
-#include <mach/iomux-mx51.h>
-#include <mach/devices-imx51.h>
-#include <mach/revision.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/imx-nand.h>
+#include <mach/imx/spi.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/iomux-mx51.h>
+#include <mach/imx/devices-imx51.h>
+#include <mach/imx/revision.h>
 
 #define MX51_CCM_CACRR 0x10
 
diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg
index b4e11fc227..56e2a9607c 100644
--- a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg
+++ b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x90000000
 soc imx51
 ivtofs 0x400
diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
index e29a647daa..7d219bad78 100644
--- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
+++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
@@ -1,9 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <debug_ll.h>
-#include <mach/clock-imx51_53.h>
-#include <mach/iomux-mx51.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/clock-imx51_53.h>
+#include <mach/imx/iomux-mx51.h>
 #include <common.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
diff --git a/arch/arm/boards/freescale-mx51-babbage/power.c b/arch/arm/boards/freescale-mx51-babbage/power.c
index 6edc672a5a..48dc74dd77 100644
--- a/arch/arm/boards/freescale-mx51-babbage/power.c
+++ b/arch/arm/boards/freescale-mx51-babbage/power.c
@@ -1,10 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define pr_fmt(fmt) "babbage-power: " fmt
 
 #include <common.h>
 #include <init.h>
 #include <notifier.h>
-#include <mach/revision.h>
-#include <mach/imx5.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/imx5.h>
 #include <mfd/mc13xxx.h>
 
 static void babbage_power_init(struct mc13xxx *mc13xxx)
diff --git a/arch/arm/boards/freescale-mx53-qsb/Makefile b/arch/arm/boards/freescale-mx53-qsb/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/freescale-mx53-qsb/Makefile
+++ b/arch/arm/boards/freescale-mx53-qsb/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c
index f2cb5c56e7..a8558eafce 100644
--- a/arch/arm/boards/freescale-mx53-qsb/board.c
+++ b/arch/arm/boards/freescale-mx53-qsb/board.c
@@ -3,7 +3,6 @@
 // SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de>
 
 #include <environment.h>
-#include <partition.h>
 #include <common.h>
 #include <linux/sizes.h>
 #include <gpio.h>
@@ -18,14 +17,14 @@
 #include <asm/armlinux.h>
 #include <asm/mmu.h>
 
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 
-#include <mach/imx53-regs.h>
-#include <mach/revision.h>
-#include <mach/generic.h>
-#include <mach/imx5.h>
-#include <mach/bbu.h>
-#include <mach/iim.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/iim.h>
 
 /*
  * Revision to be passed to kernel. The kernel provided
diff --git a/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg
index 2025f5da08..da08c60739 100644
--- a/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg
+++ b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x70000000
 soc imx53
 ivtofs 0x400
diff --git a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c
index c9044011d5..5870f266d2 100644
--- a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c
+++ b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c
@@ -1,7 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <mach/imx53-regs.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <image-metadata.h>
diff --git a/arch/arm/boards/freescale-mx53-smd/Makefile b/arch/arm/boards/freescale-mx53-smd/Makefile
deleted file mode 100644
index 98ed275396..0000000000
--- a/arch/arm/boards/freescale-mx53-smd/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += board.o
-lwl-y += lowlevel.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-freescale-mx53-smd
diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c
deleted file mode 100644
index 98d3048dac..0000000000
--- a/arch/arm/boards/freescale-mx53-smd/board.c
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix
-// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de>
-
-#include <common.h>
-#include <environment.h>
-#include <fcntl.h>
-#include <platform_data/eth-fec.h>
-#include <fs.h>
-#include <init.h>
-#include <nand.h>
-#include <net.h>
-#include <partition.h>
-#include <linux/sizes.h>
-#include <gpio.h>
-#include <mci.h>
-#include <envfs.h>
-
-#include <generated/mach-types.h>
-
-#include <mach/imx53-regs.h>
-#include <mach/iomux-mx53.h>
-#include <mach/devices-imx53.h>
-#include <mach/generic.h>
-#include <mach/imx-nand.h>
-#include <mach/iim.h>
-#include <mach/imx5.h>
-
-#include <asm/armlinux.h>
-#include <io.h>
-#include <asm/mmu.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type = PHY_INTERFACE_MODE_RMII,
-};
-
-static iomux_v3_cfg_t smd_pads[] = {
-	/* UART1 */
-	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-
-	/* UART2 */
-	MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-	MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-
-	/* UART3 */
-	MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-	MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-	MX53_PAD_PATA_DA_1__UART3_CTS,
-	MX53_PAD_PATA_DA_2__UART3_RTS,
-
-	/* FEC */
-	MX53_PAD_FEC_MDC__FEC_MDC,
-	MX53_PAD_FEC_MDIO__FEC_MDIO,
-	MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-	MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-	MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-	MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-	MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-	MX53_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX53_PAD_FEC_TXD1__FEC_TDATA_1,
-	MX53_PAD_FEC_TXD0__FEC_TDATA_0,
-	/* FEC_nRST */
-	MX53_PAD_PATA_DA_0__GPIO7_6,
-
-	/* SD1 */
-	MX53_PAD_SD1_CMD__ESDHC1_CMD,
-	MX53_PAD_SD1_CLK__ESDHC1_CLK,
-	MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-	MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-	MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-	MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-	/* SD1_CD */
-	MX53_PAD_EIM_DA13__GPIO3_13,
-	/* SD1_WP */
-	MX53_PAD_KEY_ROW2__GPIO4_11,
-
-	/* SD3 */
-	MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-	MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-	MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-	MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-	MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-	MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-	MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-	MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-	MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-	MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-};
-
-#define SMD_FEC_PHY_RST		IMX_GPIO_NR(7, 6)
-
-static void smd_fec_reset(void)
-{
-	gpio_direction_output(SMD_FEC_PHY_RST, 0);
-	mdelay(1);
-	gpio_set_value(SMD_FEC_PHY_RST, 1);
-}
-
-#define LOCO_SD1_CD			IMX_GPIO_NR(3, 13)
-#define LOCO_SD1_WP			IMX_GPIO_NR(4, 11)
-
-static struct esdhc_platform_data loco_sd1_data = {
-	.cd_gpio = LOCO_SD1_CD,
-	.wp_gpio = LOCO_SD1_WP,
-	.cd_type = ESDHC_CD_GPIO,
-	.wp_type = ESDHC_WP_GPIO,
-	.caps    = MMC_CAP_4_BIT_DATA,
-};
-
-static struct esdhc_platform_data loco_sd3_data = {
-	.wp_type = ESDHC_WP_NONE,
-	.cd_type = ESDHC_CD_PERMANENT,
-};
-
-static int smd_devices_init(void)
-{
-	imx53_iim_register_fec_ethaddr();
-	imx53_add_fec(&fec_info);
-	imx53_add_mmc0(&loco_sd1_data);
-	imx53_add_mmc2(&loco_sd3_data);
-
-	smd_fec_reset();
-
-	armlinux_set_architecture(MACH_TYPE_MX53_SMD);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_freescale_mx53_smd);
-
-	return 0;
-}
-device_initcall(smd_devices_init);
-
-static int smd_part_init(void)
-{
-	devfs_add_partition("disk0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
-	devfs_add_partition("disk0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
-
-	return 0;
-}
-late_initcall(smd_part_init);
-
-static int smd_console_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(smd_pads, ARRAY_SIZE(smd_pads));
-
-	barebox_set_model("Freescale i.MX53 SMD");
-	barebox_set_hostname("imx53-smd");
-
-	imx53_init_lowlevel(1000);
-
-	imx53_add_uart0();
-	imx53_add_uart1();
-	imx53_add_uart2();
-	return 0;
-}
-console_initcall(smd_console_init);
diff --git a/arch/arm/boards/freescale-mx53-smd/defaultenv-freescale-mx53-smd/config b/arch/arm/boards/freescale-mx53-smd/defaultenv-freescale-mx53-smd/config
deleted file mode 100644
index 27d2663566..0000000000
--- a/arch/arm/boards/freescale-mx53-smd/defaultenv-freescale-mx53-smd/config
+++ /dev/null
@@ -1,45 +0,0 @@
-#!/bin/sh
-
-eth0.serverip=
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nor', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${global.hostname}.$rootfs_type
-
-kernelimage=zImage-${global.hostname}
-#kernelimage=uImage-${global.hostname}
-#kernelimage=Image-${global.hostname}
-#kernelimage=Image-${global.hostname}.lzo
-
-if [ -n $user ]; then
-	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
-	rootfsimage="$user"-"$rootfsimage"
-else
-	nfsroot="$eth0.serverip:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-bootargs="console=ttymxc0,115200"
-
-disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)"
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg b/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg
deleted file mode 100644
index fac4c29019..0000000000
--- a/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg
+++ /dev/null
@@ -1,54 +0,0 @@
-loadaddr 0x70000000
-soc imx53
-ivtofs 0x400
-wm 32 0x53fa8554 0x00300000
-wm 32 0x53fa8558 0x00300040
-wm 32 0x53fa8560 0x00300000
-wm 32 0x53fa8564 0x00300040
-wm 32 0x53fa8568 0x00300040
-wm 32 0x53fa8570 0x00300000
-wm 32 0x53fa8574 0x00300000
-wm 32 0x53fa8578 0x00300000
-wm 32 0x53fa857c 0x00300040
-wm 32 0x53fa8580 0x00300040
-wm 32 0x53fa8584 0x00300000
-wm 32 0x53fa8588 0x00300000
-wm 32 0x53fa8590 0x00300040
-wm 32 0x53fa8594 0x00300000
-wm 32 0x53fa86f0 0x00300000
-wm 32 0x53fa86f4 0x00000000
-wm 32 0x53fa86fc 0x00000000
-wm 32 0x53fa8714 0x00000000
-wm 32 0x53fa8718 0x00300000
-wm 32 0x53fa871c 0x00300000
-wm 32 0x53fa8720 0x00300000
-wm 32 0x53fa8724 0x04000000
-wm 32 0x53fa8728 0x00300000
-wm 32 0x53fa872c 0x00300000
-wm 32 0x63fd9088 0x35343535
-wm 32 0x63fd9090 0x4d444c44
-wm 32 0x63fd907c 0x01370138
-wm 32 0x63fd9080 0x013b013c
-wm 32 0x63fd9018 0x00011740
-wm 32 0x63fd9000 0xc3190000
-wm 32 0x63fd900c 0x9f5152e3
-wm 32 0x63fd9010 0xb68e8a63
-wm 32 0x63fd9014 0x01ff00db
-wm 32 0x63fd902c 0x000026d2
-wm 32 0x63fd9030 0x009f0e21
-wm 32 0x63fd9008 0x12273030
-wm 32 0x63fd9004 0x0002002d
-wm 32 0x63fd901c 0x00008032
-wm 32 0x63fd901c 0x00008033
-wm 32 0x63fd901c 0x00028031
-wm 32 0x63fd901c 0x052080b0
-wm 32 0x63fd901c 0x04008040
-wm 32 0x63fd901c 0x0000803a
-wm 32 0x63fd901c 0x0000803b
-wm 32 0x63fd901c 0x00028039
-wm 32 0x63fd901c 0x05208138
-wm 32 0x63fd901c 0x04008048
-wm 32 0x63fd9020 0x00005800
-wm 32 0x63fd9040 0x04b80003
-wm 32 0x63fd9058 0x00022227
-wm 32 0x63fd901c 0x00000000
diff --git a/arch/arm/boards/freescale-mx53-smd/lowlevel.c b/arch/arm/boards/freescale-mx53-smd/lowlevel.c
deleted file mode 100644
index fffbfdf0ba..0000000000
--- a/arch/arm/boards/freescale-mx53-smd/lowlevel.c
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <common.h>
-#include <mach/imx53-regs.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
-#include <asm/barebox-arm-head.h>
-
-void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	imx5_cpu_lowlevel_init();
-	arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE);
-	imx53_barebox_entry(NULL);
-}
diff --git a/arch/arm/boards/freescale-mx53-vmx53/Makefile b/arch/arm/boards/freescale-mx53-vmx53/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/freescale-mx53-vmx53/Makefile
+++ b/arch/arm/boards/freescale-mx53-vmx53/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx53-vmx53/board.c b/arch/arm/boards/freescale-mx53-vmx53/board.c
index aa93336ca2..496ce2c112 100644
--- a/arch/arm/boards/freescale-mx53-vmx53/board.c
+++ b/arch/arm/boards/freescale-mx53-vmx53/board.c
@@ -10,10 +10,10 @@
 #include <init.h>
 #include <linux/sizes.h>
 
-#include <generated/mach-types.h>
-#include <mach/imx5.h>
+#include <asm/mach-types.h>
+#include <mach/imx/imx5.h>
 #include <asm/armlinux.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
 static int vmx53_late_init(void)
 {
diff --git a/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg b/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg
index e6f73df30e..20e028691a 100644
--- a/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg
+++ b/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x70000000
 soc imx53
 ivtofs 0x400
diff --git a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c
index ae94538c9e..4543171ec2 100644
--- a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c
+++ b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c
@@ -1,6 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/Makefile b/arch/arm/boards/freescale-mx6-sabrelite/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/Makefile
+++ b/arch/arm/boards/freescale-mx6-sabrelite/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c
index 1b39ef82c6..0f5306cde8 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/board.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c
@@ -8,25 +8,26 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/imx6-regs.h>
+#include <mach/imx/imx6-regs.h>
 #include <gpio.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
+#include <of.h>
+#include <deep-probe.h>
 #include <linux/phy.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
 #include <net.h>
 #include <linux/micrel_phy.h>
-#include <mach/imx6.h>
-#include <mach/devices-imx6.h>
-#include <mach/iomux-mx6.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/devices-imx6.h>
+#include <mach/imx/iomux-mx6.h>
 #include <spi/spi.h>
-#include <mach/spi.h>
-#include <mach/usb.h>
+#include <mach/imx/spi.h>
+#include <mach/imx/usb.h>
 
 static iomux_v3_cfg_t sabrelite_enet_gpio_pads[] = {
 	/* Ethernet */
@@ -98,10 +99,6 @@ static int sabrelite_ksz9021rn_setup(void)
 {
 	int ret;
 
-	if (!of_machine_is_compatible("fsl,imx6q-sabrelite") &&
-	    !of_machine_is_compatible("fsl,imx6dl-sabrelite"))
-		return 0;
-
 	mxc_iomux_v3_setup_multiple_pads(sabrelite_enet_gpio_pads,
 			ARRAY_SIZE(sabrelite_enet_gpio_pads));
 
@@ -118,11 +115,6 @@ static int sabrelite_ksz9021rn_setup(void)
 
 	return 0;
 }
-/*
- * Do this before the fec initializes but after our
- * gpios are available.
- */
-fs_initcall(sabrelite_ksz9021rn_setup);
 
 static void sabrelite_ehci_init(void)
 {
@@ -132,11 +124,22 @@ static void sabrelite_ehci_init(void)
 	gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 }
 
-static int sabrelite_devices_init(void)
+static int sabrelite_probe(struct device *dev)
 {
-	if (!of_machine_is_compatible("fsl,imx6q-sabrelite") &&
-	    !of_machine_is_compatible("fsl,imx6dl-sabrelite"))
-		return 0;
+	int ret;
+
+	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+					   ksz9021rn_phy_fixup);
+
+	barebox_set_hostname("sabrelite");
+
+	ret = of_devices_ensure_probed_by_property("gpio-controller");
+	if (ret)
+		return ret;
+
+	ret = sabrelite_ksz9021rn_setup();
+	if (ret)
+		return ret;
 
 	sabrelite_ehci_init();
 
@@ -147,19 +150,21 @@ static int sabrelite_devices_init(void)
 
 	return 0;
 }
-device_initcall(sabrelite_devices_init);
-
-static int sabrelite_coredevices_init(void)
-{
-	if (!of_machine_is_compatible("fsl,imx6q-sabrelite") &&
-	    !of_machine_is_compatible("fsl,imx6dl-sabrelite"))
-		return 0;
+static const struct of_device_id sabrelite_match[] = {
+	{
+		.compatible = "fsl,imx6q-sabrelite",
+	}, {
+		.compatible = "fsl,imx6dl-sabrelite",
+	},
+	{ /* Sentinel */ },
+};
 
-	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-					   ksz9021rn_phy_fixup);
+static struct driver sabrelite_driver = {
+	.name = "physom-imx6",
+	.probe = sabrelite_probe,
+	.of_compatible = sabrelite_match,
+};
 
-	barebox_set_hostname("sabrelite");
+postcore_platform_driver(sabrelite_driver);
 
-	return 0;
-}
-coredevice_initcall(sabrelite_coredevices_init);
+BAREBOX_DEEP_PROBE_ENABLE(sabrelite_match);
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg
index d635c8b948..7dcaefd697 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg
+++ b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg
@@ -1,9 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
index c2d7a3c8f3..f1ed31ccad 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
@@ -1,12 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx6-regs.h>
+#include <mach/imx/imx6-regs.h>
 #include <io.h>
-#include <mach/debug_ll.h>
-#include <mach/esdctl.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/esdctl.h>
 #include <asm/cache.h>
 
 extern char __dtb_imx6q_sabrelite_start[];
diff --git a/arch/arm/boards/freescale-mx6-sabresd/Makefile b/arch/arm/boards/freescale-mx6-sabresd/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/freescale-mx6-sabresd/Makefile
+++ b/arch/arm/boards/freescale-mx6-sabresd/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx6-sabresd/board.c b/arch/arm/boards/freescale-mx6-sabresd/board.c
index b710c05a47..2b1d005cf2 100644
--- a/arch/arm/boards/freescale-mx6-sabresd/board.c
+++ b/arch/arm/boards/freescale-mx6-sabresd/board.c
@@ -10,22 +10,21 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/imx6-regs.h>
+#include <mach/imx/imx6-regs.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <linux/phy.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
 #include <net.h>
-#include <mach/imx6.h>
-#include <mach/devices-imx6.h>
-#include <mach/iomux-mx6.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/devices-imx6.h>
+#include <mach/imx/iomux-mx6.h>
 #include <spi/spi.h>
-#include <mach/spi.h>
-#include <mach/usb.h>
+#include <mach/imx/spi.h>
+#include <mach/imx/usb.h>
 
 #define PHY_ID_AR8031	0x004dd074
 #define AR_PHY_ID_MASK	0xffffffff
@@ -55,7 +54,9 @@ static int ar8031_phy_fixup(struct phy_device *dev)
 
 static int sabresd_devices_init(void)
 {
-	if (!of_machine_is_compatible("fsl,imx6q-sabresd"))
+	if (!of_machine_is_compatible("fsl,imx6q-sabresd") &&
+	    !of_machine_is_compatible("fsl,imx6qp-sabresd") &&
+	    !of_machine_is_compatible("fsl,imx6dl-sabresd"))
 		return 0;
 
 	armlinux_set_architecture(3980);
@@ -67,7 +68,9 @@ device_initcall(sabresd_devices_init);
 
 static int sabresd_coredevices_init(void)
 {
-	if (!of_machine_is_compatible("fsl,imx6q-sabresd"))
+	if (!of_machine_is_compatible("fsl,imx6q-sabresd") &&
+	    !of_machine_is_compatible("fsl,imx6qp-sabresd") &&
+	    !of_machine_is_compatible("fsl,imx6dl-sabresd"))
 		return 0;
 
 	phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6dl-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6dl-sabresd.imxcfg
new file mode 100644
index 0000000000..303b62ce4f
--- /dev/null
+++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6dl-sabresd.imxcfg
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+loadaddr 0x10000000
+soc imx6
+ivtofs 0x400
+wm 32 0x020e0774 0x000C0000
+wm 32 0x020e0754 0x00000000
+wm 32 0x020e04ac 0x00000030
+wm 32 0x020e04b0 0x00000030
+wm 32 0x020e0464 0x00000030
+wm 32 0x020e0490 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0494 0x00000030
+wm 32 0x020e04a0 0x00000000
+wm 32 0x020e04b4 0x00000030
+wm 32 0x020e04b8 0x00000030
+wm 32 0x020e076c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e04bc 0x00000030
+wm 32 0x020e04c0 0x00000030
+wm 32 0x020e04c4 0x00000030
+wm 32 0x020e04c8 0x00000030
+wm 32 0x020e04cc 0x00000030
+wm 32 0x020e04d0 0x00000030
+wm 32 0x020e04d4 0x00000030
+wm 32 0x020e04d8 0x00000030
+wm 32 0x020e0760 0x00020000
+wm 32 0x020e0764 0x00000030
+wm 32 0x020e0770 0x00000030
+wm 32 0x020e0778 0x00000030
+wm 32 0x020e077c 0x00000030
+wm 32 0x020e0780 0x00000030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e0470 0x00000030
+wm 32 0x020e0474 0x00000030
+wm 32 0x020e0478 0x00000030
+wm 32 0x020e047c 0x00000030
+wm 32 0x020e0480 0x00000030
+wm 32 0x020e0484 0x00000030
+wm 32 0x020e0488 0x00000030
+wm 32 0x020e048c 0x00000030
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b080c 0x001F001F
+wm 32 0x021b0810 0x001F001F
+wm 32 0x021b480c 0x001F001F
+wm 32 0x021b4810 0x001F001F
+wm 32 0x021b083c 0x4220021F
+wm 32 0x021b0840 0x0207017E
+wm 32 0x021b483c 0x4201020C
+wm 32 0x021b4840 0x01660172
+wm 32 0x021b0848 0x4A4D4E4D
+wm 32 0x021b4848 0x4A4F5049
+wm 32 0x021b0850 0x3F3C3D31
+wm 32 0x021b4850 0x3238372B
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b0004 0x0002002D
+wm 32 0x021b0008 0x00333030
+wm 32 0x021b000c 0x3F435313
+wm 32 0x021b0010 0xB66E8B63
+wm 32 0x021b0014 0x01FF00DB
+wm 32 0x021b0018 0x00001740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x00431023
+wm 32 0x021b0040 0x00000027
+wm 32 0x021b0000 0x831A0000
+wm 32 0x021b001c 0x04008032
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x05208030
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b4818 0x00011117
+wm 32 0x021b0004 0x0002556D
+wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+wm 32 0x020c4068 0x00C03F3F
+wm 32 0x020c406c 0x0030FC03
+wm 32 0x020c4070 0x0FFFF000
+wm 32 0x020c4074 0x3FF00000
+wm 32 0x020c4078 0x00FFF300
+wm 32 0x020c407c 0x0F0000C3
+wm 32 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+wm 32 0x020e0010 0xF00000CF
+
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+wm 32 0x020e0018 0x007F007F
+wm 32 0x020e001c 0x007F007F
diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6q-sabresd.imxcfg
index 133f499ab9..39f8950e8e 100644
--- a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg
+++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6q-sabresd.imxcfg
@@ -1,128 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x10000000
 soc imx6
 ivtofs 0x400
+wm 32 0x20e056c 0x00020030
+wm 32 0x20e0578 0x00020030
+wm 32 0x20e0588 0x00020030
+wm 32 0x20e0594 0x00020030
+wm 32 0x20e0798 0x000C0000
+wm 32 0x20e0758 0x00000000
+wm 32 0x20e0588 0x00000030
+wm 32 0x20e0594 0x00000030
+wm 32 0x20e056c 0x00000030
+wm 32 0x20e0578 0x00000030
+wm 32 0x20e074c 0x00000030
+wm 32 0x20e057c 0x00000030
+wm 32 0x20e058c 0x00000000
+wm 32 0x20e059c 0x00000030
+wm 32 0x20e05a0 0x00000030
+wm 32 0x20e078c 0x00000030
+wm 32 0x20e0750 0x00020000
 wm 32 0x20e05a8 0x00000030
 wm 32 0x20e05b0 0x00000030
 wm 32 0x20e0524 0x00000030
 wm 32 0x20e051c 0x00000030
-
 wm 32 0x20e0518 0x00000030
 wm 32 0x20e050c 0x00000030
 wm 32 0x20e05b8 0x00000030
 wm 32 0x20e05c0 0x00000030
-
-wm 32 0x20e05ac 0x00020030
-wm 32 0x20e05b4 0x00020030
-wm 32 0x20e0528 0x00020030
-wm 32 0x20e0520 0x00020030
-
-wm 32 0x20e0514 0x00020030
-wm 32 0x20e0510 0x00020030
-wm 32 0x20e05bc 0x00020030
-wm 32 0x20e05c4 0x00020030
-
-wm 32 0x20e056c 0x00020030
-wm 32 0x20e0578 0x00020030
-wm 32 0x20e0588 0x00020030
-wm 32 0x20e0594 0x00020030
-
-wm 32 0x20e057c 0x00020030
-wm 32 0x20e0590 0x00003000
-wm 32 0x20e0598 0x00003000
-wm 32 0x20e058c 0x00000000
-
-wm 32 0x20e059c 0x00003030
-wm 32 0x20e05a0 0x00003030
+wm 32 0x20e0774 0x00020000
 wm 32 0x20e0784 0x00000030
 wm 32 0x20e0788 0x00000030
-
 wm 32 0x20e0794 0x00000030
 wm 32 0x20e079c 0x00000030
 wm 32 0x20e07a0 0x00000030
 wm 32 0x20e07a4 0x00000030
-
 wm 32 0x20e07a8 0x00000030
 wm 32 0x20e0748 0x00000030
-wm 32 0x20e074c 0x00000030
-wm 32 0x20e0750 0x00020000
-
-wm 32 0x20e0758 0x00000000
-wm 32 0x20e0774 0x00020000
-wm 32 0x20e078c 0x00000030
-wm 32 0x20e0798 0x000C0000
-
+wm 32 0x20e05ac 0x00000030
+wm 32 0x20e05b4 0x00000030
+wm 32 0x20e0528 0x00000030
+wm 32 0x20e0520 0x00000030
+wm 32 0x20e0514 0x00000030
+wm 32 0x20e0510 0x00000030
+wm 32 0x20e05bc 0x00000030
+wm 32 0x20e05c4 0x00000030
+wm 32 0x21b0800 0xa1390003
+wm 32 0x21b080c 0x001F001F
+wm 32 0x21b0810 0x001F001F
+wm 32 0x21b480c 0x001F001F
+wm 32 0x21b4810 0x001F001F
+wm 32 0x21b083c 0x43270338
+wm 32 0x21b0840 0x03200314
+wm 32 0x21b483c 0x431A032F
+wm 32 0x21b4840 0x03200263
+wm 32 0x21b0848 0x4B434748
+wm 32 0x21b4848 0x4445404C
+wm 32 0x21b0850 0x38444542
+wm 32 0x21b4850 0x4935493A
 wm 32 0x21b081c 0x33333333
 wm 32 0x21b0820 0x33333333
 wm 32 0x21b0824 0x33333333
 wm 32 0x21b0828 0x33333333
-
 wm 32 0x21b481c 0x33333333
 wm 32 0x21b4820 0x33333333
 wm 32 0x21b4824 0x33333333
 wm 32 0x21b4828 0x33333333
-
-wm 32 0x21b0018 0x00081740
-
-wm 32 0x21b001c 0x00008000
+wm 32 0x21b08b8 0x00000800
+wm 32 0x21b48b8 0x00000800
+wm 32 0x21b0004 0x00020036
+wm 32 0x21b0008 0x09444040
 wm 32 0x21b000c 0x555A7975
-wm 32 0x21b0010 0xFF538E64
+wm 32 0x21b0010 0xFF538F64
 wm 32 0x21b0014 0x01FF00DB
-wm 32 0x21b002c 0x000026D2
-
-wm 32 0x21b0030 0x005B0E21
-wm 32 0x21b0008 0x09444040
-wm 32 0x21b0004 0x00025576
+wm 32 0x21b0018 0x00001740
+wm 32 0x21b001c 0x00008000
+wm 32 0x21b002c 0x000026d2
+wm 32 0x21b0030 0x005A1023
 wm 32 0x21b0040 0x00000027
 wm 32 0x21b0000 0x831A0000
-
 wm 32 0x21b001c 0x04088032
-wm 32 0x21b001c 0x0408803A
 wm 32 0x21b001c 0x00008033
-wm 32 0x21b001c 0x0000803B
-wm 32 0x21b001c 0x00428031
-wm 32 0x21b001c 0x00428039
+wm 32 0x21b001c 0x00048031
 wm 32 0x21b001c 0x09408030
-wm 32 0x21b001c 0x09408038
-
 wm 32 0x21b001c 0x04008040
-wm 32 0x21b001c 0x04008048
-wm 32 0x21b0800 0xA1380003
-wm 32 0x21b4800 0xA1380003
 wm 32 0x21b0020 0x00005800
-wm 32 0x21b0818 0x00022227
-wm 32 0x21b4818 0x00022227
-
-wm 32 0x21b083c 0x434B0350
-wm 32 0x21b0840 0x034C0359
-wm 32 0x21b483c 0x434B0350
-wm 32 0x21b4840 0x03650348
-wm 32 0x21b0848 0x4436383B
-wm 32 0x21b4848 0x39393341
-wm 32 0x21b0850 0x35373933
-wm 32 0x21b4850 0x48254A36
-
-wm 32 0x21b080c 0x001F001F
-wm 32 0x21b0810 0x001F001F
-
-wm 32 0x21b480c 0x00440044
-wm 32 0x21b4810 0x00440044
-
-wm 32 0x21b08b8 0x00000800
-wm 32 0x21b48b8 0x00000800
-
-wm 32 0x21b001c 0x00000000
+wm 32 0x21b0818 0x00011117
+wm 32 0x21b4818 0x00011117
+wm 32 0x21b0004 0x00025576
 wm 32 0x21b0404 0x00011006
-
-wm 32 0x020c4068 0x00c03f3f
-wm 32 0x020c406c 0x0030fc03
-wm 32 0x020c4070 0x0fffc000
-wm 32 0x020c4074 0x3ff00000
-wm 32 0x020c4078 0x00fff300
-wm 32 0x020c407c 0x0f0000c3
-wm 32 0x020c4080 0x000003ff
-
-# enable AXI cache for VDOA/VPU/IPU
-wm 32 0x20e0010 0xf00000cf
-# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
-wm 32 0x20e0018 0x007f007f
-wm 32 0x20e001c 0x007f007f
+wm 32 0x21b001c 0x00000000
diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6qp-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6qp-sabresd.imxcfg
new file mode 100644
index 0000000000..224ac3207f
--- /dev/null
+++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6qp-sabresd.imxcfg
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+loadaddr 0x10000000
+soc imx6
+ivtofs 0x400
+wm 32 0x20e0798 0x000c0000
+wm 32 0x20e0758 0x00000000
+wm 32 0x20e0588 0x00000030
+wm 32 0x20e0594 0x00000030
+wm 32 0x20e056c 0x00000030
+wm 32 0x20e0578 0x00000030
+wm 32 0x20e074c 0x00000030
+wm 32 0x20e057c 0x00000030
+wm 32 0x20e058c 0x00000000
+wm 32 0x20e059c 0x00000030
+wm 32 0x20e05a0 0x00000030
+wm 32 0x20e078c 0x00000030
+wm 32 0x20e0750 0x00020000
+wm 32 0x20e05a8 0x00000030
+wm 32 0x20e05b0 0x00000030
+wm 32 0x20e0524 0x00000030
+wm 32 0x20e051c 0x00000030
+wm 32 0x20e0518 0x00000030
+wm 32 0x20e050c 0x00000030
+wm 32 0x20e05b8 0x00000030
+wm 32 0x20e05c0 0x00000030
+wm 32 0x20e0774 0x00020000
+wm 32 0x20e0784 0x00000030
+wm 32 0x20e0788 0x00000030
+wm 32 0x20e0794 0x00000030
+wm 32 0x20e079c 0x00000030
+wm 32 0x20e07a0 0x00000030
+wm 32 0x20e07a4 0x00000030
+wm 32 0x20e07a8 0x00000030
+wm 32 0x20e0748 0x00000030
+wm 32 0x20e05ac 0x00000030
+wm 32 0x20e05b4 0x00000030
+wm 32 0x20e0528 0x00000030
+wm 32 0x20e0520 0x00000030
+wm 32 0x20e0514 0x00000030
+wm 32 0x20e0510 0x00000030
+wm 32 0x20e05bc 0x00000030
+wm 32 0x20e05c4 0x00000030
+wm 32 0x21b0800 0xa1390003
+wm 32 0x21b080c 0x001b001e
+wm 32 0x21b0810 0x002e0029
+wm 32 0x21b480c 0x001b002a
+wm 32 0x21b4810 0x0019002c
+wm 32 0x21b083c 0x43240334
+wm 32 0x21b0840 0x0324031a
+wm 32 0x21b483c 0x43340344
+wm 32 0x21b4840 0x03280276
+wm 32 0x21b0848 0x44383A3E
+wm 32 0x21b4848 0x3C3C3846
+wm 32 0x21b0850 0x2e303230
+wm 32 0x21b4850 0x38283E34
+wm 32 0x21b081c 0x33333333
+wm 32 0x21b0820 0x33333333
+wm 32 0x21b0824 0x33333333
+wm 32 0x21b0828 0x33333333
+wm 32 0x21b481c 0x33333333
+wm 32 0x21b4820 0x33333333
+wm 32 0x21b4824 0x33333333
+wm 32 0x21b4828 0x33333333
+wm 32 0x21b08c0 0x24912249
+wm 32 0x21b48c0 0x24914289
+wm 32 0x21b08b8 0x00000800
+wm 32 0x21b48b8 0x00000800
+wm 32 0x21b0004 0x00020036
+wm 32 0x21b0008 0x24444040
+wm 32 0x21b000c 0x555A7955
+wm 32 0x21b0010 0xFF320F64
+wm 32 0x21b0014 0x01ff00db
+wm 32 0x21b0018 0x00001740
+wm 32 0x21b001c 0x00008000
+wm 32 0x21b002c 0x000026d2
+wm 32 0x21b0030 0x005A1023
+wm 32 0x21b0040 0x00000027
+wm 32 0x21b0400 0x14420000
+wm 32 0x21b0000 0x831A0000
+wm 32 0x21b0890 0x00400C58
+wm 32 0x0bb0008 0x00000000
+wm 32 0x0bb000c 0x2891E41A
+wm 32 0x0bb0038 0x00000564
+wm 32 0x0bb0014 0x00000040
+wm 32 0x0bb0028 0x00000020
+wm 32 0x0bb002c 0x00000020
+wm 32 0x21b001c 0x04088032
+wm 32 0x21b001c 0x00008033
+wm 32 0x21b001c 0x00048031
+wm 32 0x21b001c 0x09408030
+wm 32 0x21b001c 0x04008040
+wm 32 0x21b0020 0x00005800
+wm 32 0x21b0818 0x00011117
+wm 32 0x21b4818 0x00011117
+wm 32 0x21b0004 0x00025576
+wm 32 0x21b0404 0x00011006
+wm 32 0x21b001c 0x00000000
diff --git a/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c
index ae847feaa6..7cc08b47d5 100644
--- a/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c
@@ -1,8 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
-#include <mach/iomux-mx6.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/iomux-mx6.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
@@ -35,3 +38,35 @@ ENTRY_FUNCTION(start_imx6q_sabresd, r0, r1, r2)
 
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
+
+extern char __dtb_imx6qp_sabresd_start[];
+
+ENTRY_FUNCTION(start_imx6qp_sabresd, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = __dtb_imx6qp_sabresd_start + get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
+
+extern char __dtb_imx6dl_sabresd_start[];
+
+ENTRY_FUNCTION(start_imx6dl_sabresd, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = __dtb_imx6dl_sabresd_start + get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile b/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile
+++ b/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c
index 3285e1f290..4749981265 100644
--- a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c
+++ b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c
@@ -4,24 +4,23 @@
 #define pr_fmt(fmt) "imx6sx-sdb: " fmt
 
 #include <environment.h>
-#include <partition.h>
 #include <common.h>
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <init.h>
 #include <io.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <i2c/i2c.h>
 
 #include <asm/armlinux.h>
 
-#include <mach/devices-imx6.h>
-#include <mach/imx6-regs.h>
-#include <mach/iomux-mx6.h>
-#include <mach/generic.h>
-#include <mach/imx6.h>
-#include <mach/bbu.h>
+#include <mach/imx/devices-imx6.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/iomux-mx6.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/bbu.h>
 
 #define PFUZE100_DEVICEID	0x0
 #define PFUZE100_REVID		0x3
diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg b/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg
index 5536f342b4..ebae00b8ea 100644
--- a/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg
+++ b/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x80000000
 soc imx6
 ivtofs 0x400
diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
index d3b58ac1be..721743dadb 100644
--- a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
@@ -2,9 +2,10 @@
 // SPDX-FileCopyrightText: 2014 Sascha Hauer, Pengutronix
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
diff --git a/arch/arm/boards/freescale-mx7-sabresd/Makefile b/arch/arm/boards/freescale-mx7-sabresd/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/freescale-mx7-sabresd/Makefile
+++ b/arch/arm/boards/freescale-mx7-sabresd/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx7-sabresd/board.c b/arch/arm/boards/freescale-mx7-sabresd/board.c
index e41d67017f..03658ddc7c 100644
--- a/arch/arm/boards/freescale-mx7-sabresd/board.c
+++ b/arch/arm/boards/freescale-mx7-sabresd/board.c
@@ -6,7 +6,7 @@
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/imx7-regs.h>
+#include <mach/imx/imx7-regs.h>
 #include <linux/phy.h>
 #include <mfd/imx7-iomuxc-gpr.h>
 
diff --git a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
index 41e0e9ca61..0b0780ed9b 100644
--- a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
+++ b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
@@ -1,5 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx7
 loadaddr 0x80000000
 ivtofs 0x400
 
-#include <mach/flash-header/imx7d-ddr-sabresd.imxcfg>
\ No newline at end of file
+#include <mach/imx/flash-header/imx7d-ddr-sabresd.imxcfg>
diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
index 8db46ca696..5a7508143e 100644
--- a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
+++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
@@ -1,21 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <io.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx7-ccm-regs.h>
-#include <mach/iomux-mx7.h>
-#include <mach/debug_ll.h>
+#include <mach/imx/imx7-ccm-regs.h>
+#include <mach/imx/iomux-mx7.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
-#include <mach/esdctl.h>
+#include <mach/imx/esdctl.h>
 
 extern char __dtb_imx7d_sdb_start[];
 
 static inline void setup_uart(void)
 {
-	imx7_early_setup_uart_clock();
+	imx7_early_setup_uart_clock(1);
 
 	imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX);
 
diff --git a/arch/arm/boards/freescale-vf610-twr/Makefile b/arch/arm/boards/freescale-vf610-twr/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/freescale-vf610-twr/Makefile
+++ b/arch/arm/boards/freescale-vf610-twr/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
index bcef9921fa..bad742831a 100644
--- a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
+++ b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
@@ -1,14 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc vf610
 loadaddr 0x80000000
 ivtofs 0x400
 
-#include <mach/vf610-iomux-regs.h>
-#include <mach/vf610-ddrmc-regs.h>
+#include <mach/imx/vf610-iomux-regs.h>
+#include <mach/imx/vf610-ddrmc-regs.h>
 
-#include <mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg>
-#include <mach/flash-header/vf610-iomux-ddr-default.imxcfg>
-#include <mach/flash-header/vf610-ddr-cr-default.imxcfg>
-#include <mach/flash-header/vf610-ddr-phy-default.imxcfg>
+#include <mach/imx/flash-header/vf610-ddr-pll2-400mhz.imxcfg>
+#include <mach/imx/flash-header/vf610-iomux-ddr-default.imxcfg>
+#include <mach/imx/flash-header/vf610-ddr-cr-default.imxcfg>
+#include <mach/imx/flash-header/vf610-ddr-phy-default.imxcfg>
 
 wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3_START
 
diff --git a/arch/arm/boards/freescale-vf610-twr/lowlevel.c b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
index 8fec9f4b91..c7714f29a2 100644
--- a/arch/arm/boards/freescale-vf610-twr/lowlevel.c
+++ b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
@@ -1,13 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/esdctl.h>
-#include <mach/vf610-regs.h>
-#include <mach/clock-vf610.h>
-#include <mach/iomux-vf610.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/vf610-regs.h>
+#include <mach/imx/clock-vf610.h>
+#include <mach/imx/iomux-vf610.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 
 static inline void setup_uart(void)
 {
diff --git a/arch/arm/boards/friendlyarm-mini2440/Kconfig b/arch/arm/boards/friendlyarm-mini2440/Kconfig
deleted file mode 100644
index feb905e96e..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-
-if MACH_MINI2440
-
-config MINI2440_VIDEO
-	bool
-	select VIDEO
-	select DRIVER_VIDEO_S3C24XX
-
-config MINI2440_VIDEO_N35
-	bool "Support N35 display (240x320)"
-	select MINI2440_VIDEO
-	help
-	  This adds support for NEC 3.5 inch TFT display,
-	  the most common one used with MINI2440 board.
-
-config MINI2440_VIDEO_A70
-	bool "Support A70 display (800x480)"
-	select MINI2440_VIDEO
-	help
-	  This adds support for Innolux 7.0 inch TFT display.
-
-config MINI2440_VIDEO_SVGA
-	bool "Support SVGA video adapter"
-	select MINI2440_VIDEO
-	help
-	  This adds support for MINI2440 SVGA (1024x768) video output adapter.
-
-config MINI2440_VIDEO_W35
-	bool "Support W35 display (320x240)"
-	select MINI2440_VIDEO
-	help
-	  This adds support for Sharp 3.5 inch TFT display.
-
-endif
diff --git a/arch/arm/boards/friendlyarm-mini2440/Makefile b/arch/arm/boards/friendlyarm-mini2440/Makefile
deleted file mode 100644
index da3520cc81..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-obj-y += mini2440.o
-lwl-y += lowlevel_init.o
diff --git a/arch/arm/boards/friendlyarm-mini2440/config.h b/arch/arm/boards/friendlyarm-mini2440/config.h
deleted file mode 100644
index 86c78e54f6..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/config.h
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/**
- * @file
- * @brief Global defintions for the ARM S3C2440 based mini2440 CPU card
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/**
- * The external clock reference is a 12.00 MHz crystal
- */
-#define S3C24XX_CLOCK_REFERENCE 12000000
-
-/**
- * Define the main clock configuration to be used in register CLKDIVN
- *
- * We must limit the frequency of the connected SDRAMs with the clock ratio
- * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 405Mhz:102MHz:51MHz
- */
-#define BOARD_SPECIFIC_CLKDIVN 0x05
-
-/**
- * Define the MPLL configuration to be used in register MPLLCON
- *
- * We want the MPLL to run at 405.0 MHz
- */
-#define BOARD_SPECIFIC_MPLL ((0x7f << 12) + (2 << 4) + 1)
-
-/**
- * Define the UPLL configuration to be used in register UPLLCON
- *
- * We want the UPLL to run at 48.0 MHz
- */
-#define BOARD_SPECIFIC_UPLL ((0x38 << 12) + (2 << 4) + 2)
-
-/*
- * Flash access timings
- * Tacls  = 0ns (but 20ns data setup time)
- * Twrph0 = 25ns (write) 35ns (read)
- * Twrph1 = 10ns (10ns data hold time)
- * Read cycle time = 50ns
- *
- * Assumed HCLK is 100MHz
- * Tacls = 1 (-> 20ns)
- * Twrph0 = 3 (-> 40ns)
- * Twrph1 = 1 (-> 20ns)
- * Cycle time = 80ns
- */
-#define MINI2440_TACLS 1
-#define MINI2440_TWRPH0 3
-#define MINI2440_TWRPH1 1
-
-/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C_NAND_BOOT
-# define BOARD_DEFAULT_NAND_TIMING \
-	CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0, MINI2440_TWRPH1)
-#endif
-
-/*
- * Needed in the generic SDRAM boot code only
- *
- * SDRAM configuration
- * Two types of SDRAM devices are common on mini2440:
- * - Two devices of HY57V561620 to form 64 MiB in bank 6 only
- *   - http://friendlyarm.net/dl.php?file=HY57V561620.pdf
- * - Two devices of MT48LC16M16 to form 64 MiB in bank 6 only
- *   - http://friendlyarm.net/dl.php?file=MT48LC16M16.pdf
-
- * Most of the time the CPU is specified for 400 MHz only. As the CPU frequency
- * and the SDRAM frequency are fix coupled by 4:1, the SDRAM runs at HCLCK.
- * So, we need a 100 MHz timing setup with CL=2 for the SDRAMs.
- */
-
-/*
- * - ST7/WS7/DW7: reserved, this SDRAM bank is not used
- * - ST6/WS6/DW6: 32 bit data bus (for SDRAM usage)
- * - ST5/WS5/DW5: reserved, to be set by the board init code
- * - ST4/WS4/DW4: reserved, to be set by the board init code
- * - ST3/WS3/DW3: reserved, to be set by the board init code
- * - ST2/WS2/DW2: reserved, to be set by the board init code
- * - ST1/WS1/DW1: reserved, to be set by the board init code
- * - DW0: not to be changed
- */
-#define BOARD_SPECIFIC_BWSCON ((0x3 << 28) | (0x2 << 24) | 0x333330)
-/*
- *  - MT = 11 (= sync dram type)
- *  - Trcd = 00 (= CL2)
- *  - SCAN = 01 (= 9 bit columns)
- */
-#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + (0x1))
-#define BOARD_SPECIFIC_BANKCON7 0 /* disabled */
-/*
- * SDRAM refresh settings
- *  - REFEN = 1 (= refresh enabled)
- *  - TREFMD = 0 (= auto refresh)
- *  - Trp = 00 (= 2 RAS precharge clocks)
- *  - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
- *  - Refresh = 2^11 + 1 - 100 * 7.8 = 2049 - 780 = 1269
- */
-#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 1269)
-/*
- * SDRAM banksize
- *  - BURST_EN = 1 (= burst mode enabled)
- *  - SCKE_EN = 1 (= SDRAM SCKE enabled)
- *  - SCLK_EN = 1 (= clock active only during accesses)
- *  - BK67MAP = 001 (= 64 MiB)
- */
-# define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (1 << 4) + 1)
-/*
- * SDRAM mode register
- * CL = 010 (= 2 clocks)
- */
-# define BOARD_SPECIFIC_MRSRB6 (0x2 << 4)
-# define BOARD_SPECIFIC_MRSRB7 0	/* not used */
-
-#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/boot/nand b/arch/arm/boards/friendlyarm-mini2440/env/boot/nand
deleted file mode 100644
index e0ef904432..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/env/boot/nand
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/sh
-
-global.bootm.image="/dev/nand0.kernel.bb"
-global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs"
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/config-board b/arch/arm/boards/friendlyarm-mini2440/env/config-board
deleted file mode 100644
index 3e07a015b0..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/env/config-board
+++ /dev/null
@@ -1,16 +0,0 @@
-#!/bin/sh
-
-# board defaults, do not change in running system. Change /env/config
-# instead
-
-global.linux.bootargs.console="console=ttySAC0,115200"
-
-#
-# "mini2440" kernel parameter
-# 0 .. 9 = screen type
-# b = backlight enabled
-# t = touch enabled
-# c = camera enabled
-# Note: can be "minit2440= " if nothing of these components are connected
-#
-global.linux.bootargs.base="mini2440=6tb"
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand b/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
deleted file mode 100644
index b51104ad76..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-mtdparts="256k(nand0.barebox),128k(nand0.bareboxenv),1536k(nand0.kernel),-(nand0.root)"
-kernelname="nand"
-
-mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S b/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
deleted file mode 100644
index 43bf49c12c..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Low level initialization for the FriendlyARM mini2440 board
- */
-
-#include <config.h>
-#include <linux/sizes.h>
-#include <mach/s3c-iomap.h>
-#include <asm/barebox-arm-head.h>
-
-	.section ".text_bare_init.barebox_arm_reset_vector","ax"
-
-/* ------------------------------------------------------------------------ */
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
-	bl arm_cpu_lowlevel_init
-
-	bl s3c24x0_disable_wd
-
-	/* skip everything here if we are already running from SDRAM */
-	cmp pc, #S3C_SDRAM_BASE
-	blo 1f
-	cmp pc, #S3C_SDRAM_END
-	bhs 1f
-
-	b out
-
-/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
-1:
-	bl s3c24x0_pll_init
-
-	bl s3c24x0_sdram_init
-
-#ifdef CONFIG_S3C_NAND_BOOT
-/* up to here we are running from the internal SRAM area */
-	bl s3c24x0_nand_boot
-#endif
-out:
-	mov r0, #S3C_SDRAM_BASE
-	mov r1, #SZ_32M
-	mov r2, #0
-	b barebox_arm_entry
diff --git a/arch/arm/boards/friendlyarm-mini2440/mini2440.c b/arch/arm/boards/friendlyarm-mini2440/mini2440.c
deleted file mode 100644
index 413537d247..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/mini2440.c
+++ /dev/null
@@ -1,342 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2010 Marek Belisko <marek.belisko@open-nandra.com>
- *
- * Based on a9m2440.c board init by Juergen Beisert, Pengutronix
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <platform_data/eth-dm9000.h>
-#include <nand.h>
-#include <mci.h>
-#include <fb.h>
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <io.h>
-#include <gpio.h>
-#include <mach/bbu.h>
-#include <mach/iomux.h>
-#include <mach/s3c-iomap.h>
-#include <mach/devices-s3c24xx.h>
-#include <mach/s3c24xx-nand.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-mci.h>
-#include <mach/s3c24xx-fb.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-static struct s3c24x0_nand_platform_data nand_info = {
-	.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
-							MINI2440_TWRPH1),
-	.flash_bbt = 1,	/* same as the kernel */
-};
-
-/*
- * dm9000 network controller onboard
- * Connected to CS line 4 and interrupt line EINT7,
- * data width is 16 bit
- * Area 1: Offset 0x300...0x303
- * Area 2: Offset 0x304...0x307
- */
-static struct dm9000_platform_data dm9000_data = {
-	.srom     = 1,
-};
-
-static struct s3c_mci_platform_data mci_data = {
-	.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED,
-	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
-	.gpio_detect = 232,	/* GPG8_GPIO */
-	.detect_invert = 0,
-};
-
-static struct fb_videomode s3c24x0_fb_modes[] = {
-#ifdef CONFIG_MINI2440_VIDEO_N35
-	{
-		.name		= "N35",
-		.refresh	= 60,
-		.xres		= 240,
-		.left_margin	= 21,
-		.right_margin	= 38,
-		.hsync_len	= 6,
-		.yres		= 320,
-		.upper_margin	= 4,
-		.lower_margin	= 4,
-		.vsync_len	= 2,
-		.pixclock	= 115913,
-		.sync		= FB_SYNC_USE_PWREN,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-#endif
-#ifdef CONFIG_MINI2440_VIDEO_A70
-	{
-		.name		= "A70",
-		.refresh	= 50,
-		.xres		= 800,
-		.left_margin	= 40,
-		.right_margin	= 40,
-		.hsync_len	= 48,
-		.yres		= 480,
-		.upper_margin	= 29,
-		.lower_margin	= 3,
-		.vsync_len	= 3,
-		.pixclock	= 41848,
-		.sync		= FB_SYNC_USE_PWREN | FB_SYNC_DE_HIGH_ACT,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-#endif
-#ifdef CONFIG_MINI2440_VIDEO_SVGA
-	{
-		.name		= "SVGA",
-		.refresh	= 24,
-		.xres		= 1024,
-		.left_margin	= 1,
-		.right_margin	= 2,
-		.hsync_len	= 2,
-		.yres		= 768,
-		.upper_margin	= 200,
-		.lower_margin	= 16,
-		.vsync_len	= 16,
-		.pixclock	= 40492,
-		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_DE_HIGH_ACT
-                                  /* | FB_SYNC_SWAP_HW */ /* FIXME maybe */ ,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-#endif
-#ifdef CONFIG_MINI2440_VIDEO_W35
-	{
-		.name		= "W35",
-		.refresh	= 60,
-		.xres		= 320,
-		.left_margin	= 68,
-		.right_margin	= 66,
-		.hsync_len	= 4,
-		.yres		= 240,
-		.upper_margin	= 4,
-		.lower_margin	= 4,
-		.vsync_len	= 9,
-		.pixclock	= 115913,
-		.sync		= FB_SYNC_USE_PWREN | FB_SYNC_CLK_INVERT,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-#endif
-};
-
-static struct s3c_fb_platform_data s3c24x0_fb_data = {
-	.mode_list		= s3c24x0_fb_modes,
-	.mode_cnt		= sizeof(s3c24x0_fb_modes) / sizeof(struct fb_videomode),
-	.bits_per_pixel		= 16,
-	.passive_display	= 0,
-};
-
-static const unsigned pin_usage[] = {
-	/* address bus, used by NOR, SDRAM */
-	GPA1_ADDR16,
-	GPA2_ADDR17,
-	GPA3_ADDR18,
-	GPA4_ADDR19,
-	GPA5_ADDR20,
-	GPA6_ADDR21,
-	GPA7_ADDR22,
-
-	GPA8_ADDR23_GPIO | GPIO_IN,
-	GPA9_ADDR24,	/* BA0 */
-	GPA10_ADDR25,	/* BA1 */
-	GPA11_ADDR26_GPIO | GPIO_IN,	/* not connected */
-
-	/* DM9000 requirements */
-	GPA15_NGCS4,
-	GPF7_EINT7,
-
-	/* de-activate the speaker */
-	GPB0_GPIO | GPIO_OUT | GPIO_VAL(0),
-
-	/* SD socket */
-	GPE5_SDCLK,
-	GPE6_SDCMD,
-	GPE7_SDDAT0,
-	GPE8_SDDAT1,
-	GPE9_SDDAT2,
-	GPE10_SDDAT3,
-	GPG8_GPIO | GPIO_IN,	/* change detection */
-	GPH8_GPIO | GPIO_IN,	/* write protection sense */
-
-	/* NAND requirements */
-	GPA17_CLE,
-	GPA18_ALE,
-	GPA19_NFWE,
-	GPA20_NFRE,
-	GPA21_NRSTOUT,
-	GPA22_NFCE,
-
-	/* Video out */
-	GPC0_LEND,
-	GPC1_VCLK,
-	GPC2_VLINE,
-	GPC3_VFRAME,
-	GPC4_VM,
-	GPC5_LPCOE,
-	GPC6_LPCREV,
-	GPC7_LPCREVB,
-	GPG4_LCD_PWREN,
-
-	GPC8_VD0,
-	GPC9_VD1,
-	GPC10_VD2,
-	GPC11_VD3,
-	GPC12_VD4,
-	GPC13_VD5,
-	GPC14_VD6,
-	GPC15_VD7,
-	GPD0_VD8,
-	GPD1_VD9,
-	GPD2_VD10,
-	GPD3_VD11,
-	GPD4_VD12,
-	GPD5_VD13,
-	GPD6_VD14,
-	GPD7_VD15,
-	GPD8_VD16,
-	GPD9_VD17,
-	GPD10_VD18,
-	GPD11_VD19,
-	GPD12_VD20,
-	GPD13_VD21,
-	GPD14_VD22,
-	GPD15_VD23,
-
-	/* K6 or CON12, pin 6, external pull up  */
-	GPG11_EINT19 | GPIO_IN,
-	/* K5 or CON12, pin 5*/
-	GPG7_EINT15 | GPIO_IN,
-	/* K4 or CON12, pin 4 */
-	GPG6_EINT14 | GPIO_IN,
-	/* K3 or CON12, pin 3 */
-	GPG5_EINT13 | GPIO_IN,
-	/* K2 or CON12, pin 2 */
-	GPG3_EINT11 | GPIO_IN,
-	/* K1 or CON12, pin 1, external pull up */
-	GPG0_EINT8 | GPIO_IN,
-
-	/* LED 1 1=off */
-	GPB5_GPIO | GPIO_OUT | GPIO_VAL(1),
-	/* LED 2 1=off */
-	GPB6_GPIO | GPIO_OUT | GPIO_VAL(1),
-	/* LED 3 1=off */
-	GPB7_GPIO | GPIO_OUT | GPIO_VAL(1),
-	/* LED 4 1=off */
-	GPB8_GPIO | GPIO_OUT | GPIO_VAL(1),
-
-	/* camera interface (ignore it) */
-	GPJ0_GPIO | GPIO_IN,
-	GPJ1_GPIO | GPIO_IN,
-	GPJ2_GPIO | GPIO_IN,
-	GPJ3_GPIO | GPIO_IN,
-	GPJ4_GPIO | GPIO_IN,
-	GPJ5_GPIO | GPIO_IN,
-	GPJ6_GPIO | GPIO_IN,
-	GPJ7_GPIO | GPIO_IN,
-	GPJ8_GPIO | GPIO_IN,
-	GPJ9_GPIO | GPIO_IN,
-	GPJ10_GPIO | GPIO_IN,
-	GPJ11_GPIO | GPIO_IN,
-	GPJ12_GPIO | GPIO_IN,
-
-	/* I2C bus */
-	GPE14_IICSCL,	/* external pull up */
-	GPE15_IICSDA,	/* external pull up */
-
-	GPA12_NGCS1,	/* CON5, pin 7 */
-	GPA13_NGCS2,	/* CON5, pin 8 */
-	GPA14_NGCS3,	/* CON5, pin 9 */
-	GPA16_NGCS5,	/* CON5, pin 10 */
-
-	/* UART2 (spare) */
-	GPH4_TXD1,
-	GPH5_RXD1,
-
-	/* UART3 (spare) */
-	GPH6_TXD2,
-	GPH7_RXD2,
-};
-
-static int mini2440_mem_init(void)
-{
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());
-
-	return 0;
-}
-mem_initcall(mini2440_mem_init);
-
-static int mini2440_devices_init(void)
-{
-	uint32_t reg;
-	int i;
-
-	/* ----------- configure the access to the outer space ---------- */
-	for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
-		s3c_gpio_mode(pin_usage[i]);
-
-	reg = readl(S3C_BWSCON);
-
-	/* CS#4 to access the network controller */
-	reg &= ~0x000f0000;
-	reg |=  0x000d0000;	/* 16 bit */
-	writel(0x1f4c, S3C_BANKCON4);
-
-	writel(reg, S3C_BWSCON);
-
-	/* release the reset signal to external devices */
-	reg = readl(S3C_MISCCR);
-	reg |= 0x10000;
-	writel(reg, S3C_MISCCR);
-
-	s3c24xx_add_nand(&nand_info);
-
-	add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
-			  IORESOURCE_MEM_16BIT, &dm9000_data);
-#ifdef CONFIG_NAND
-	/* ----------- add some vital partitions -------- */
-	devfs_del_partition("self_raw");
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-
-	devfs_del_partition("env_raw");
-	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-
-	s3c24x0_bbu_nand_register_handler();
-#endif
-	s3c24xx_add_mci(&mci_data);
-	s3c24xx_add_fb(&s3c24x0_fb_data);
-	s3c24xx_add_ohci();
-	armlinux_set_architecture(MACH_TYPE_MINI2440);
-
-	return 0;
-}
-
-device_initcall(mini2440_devices_init);
-
-static int mini2440_console_init(void)
-{
-	/*
-	 * configure the UART1 right now, as barebox will
-	 * start to send data immediately
-	 */
-	s3c_gpio_mode(GPH0_NCTS0);
-	s3c_gpio_mode(GPH1_NRTS0);
-	s3c_gpio_mode(GPH2_TXD0);
-	s3c_gpio_mode(GPH3_RXD0);
-
-	barebox_set_model("Friendlyarm mini2440");
-	barebox_set_hostname("mini2440");
-
-	s3c24xx_add_uart1();
-	return 0;
-}
-
-console_initcall(mini2440_console_init);
diff --git a/arch/arm/boards/friendlyarm-mini6410/Makefile b/arch/arm/boards/friendlyarm-mini6410/Makefile
deleted file mode 100644
index c04150e97f..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += mini6410.o
-lwl-y += lowlevel.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-friendlyarm-mini6410
diff --git a/arch/arm/boards/friendlyarm-mini6410/config.h b/arch/arm/boards/friendlyarm-mini6410/config.h
deleted file mode 100644
index ee38192041..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/config.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* FriendlyARM Mini6410 specific global settings */
-
-#ifndef _MINI6410_CONFIG_H_
-# define _MINI6410_CONFIG_H_
-
-#define S3C64XX_CLOCK_REFERENCE 12000000
-
-#endif /* _MINI6410_CONFIG_H_ */
diff --git a/arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config b/arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config
deleted file mode 100644
index 924d7b8cc7..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config
+++ /dev/null
@@ -1,52 +0,0 @@
-#!/bin/sh
-
-machine=mini6410
-eth0.serverip=a.b.c.d.e
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d.e
-#eth0.netmask=a.b.c.d.e
-#eth0.gateway=a.b.c.d.e
-#eth0.ethaddr=
-
-# can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${machine}.${rootfs_type}
-
-# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
-kernelimage=zImage-${machine}
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
-
-if [ -n $user ]; then
-	kernelimage="${user}"-"${kernelimage}"
-	nfsroot="${eth0.serverip}:/home/${user}/nfsroot/${machine}"
-	rootfsimage="${user}"-"${rootfsimage}"
-else
-	nfsroot="${eth0.serverip}:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-#
-# "mini6410" kernel parameter
-# 0 .. 9 = screen type
-# i = touchscreen with propritary FriendlyARM protocol
-# Note: can be "minit6410= " if nothing of these components are connected
-#
-bootargs="console=ttySAC0,115200 mini6410=0"
-
-nand_device="nand"
-nand_parts="256k(barebox),128k(bareboxenv),1536k(kernel),-(root)"
-rootfs_mtdblock_nand=3
diff --git a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c b/arch/arm/boards/friendlyarm-mini6410/lowlevel.c
deleted file mode 100644
index ccbdd13795..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/s3c-iomap.h>
-
-void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	arm_cpu_lowlevel_init();
-	barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL);
-}
diff --git a/arch/arm/boards/friendlyarm-mini6410/mini6410.c b/arch/arm/boards/friendlyarm-mini6410/mini6410.c
deleted file mode 100644
index 3f5e8ca2a3..0000000000
--- a/arch/arm/boards/friendlyarm-mini6410/mini6410.c
+++ /dev/null
@@ -1,302 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2012 Juergen Beisert
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <platform_data/eth-dm9000.h>
-#include <gpio.h>
-#include <envfs.h>
-#include <generated/mach-types.h>
-#include <asm/armlinux.h>
-#include <mach/s3c-iomap.h>
-#include <mach/devices-s3c64xx.h>
-#include <mach/s3c-generic.h>
-#include <mach/iomux.h>
-
-/*
- * dm9000 network controller onboard
- * Connected to CS line 1 and interrupt line EINT7,
- * data width is 16 bit
- * Area 1: Offset 0x300...0x301
- * Area 2: Offset 0x304...0x305
- */
-static struct dm9000_platform_data dm9000_data = {
-	.srom = 0,	/* no serial ROM for the ethernet address */
-};
-
-static const unsigned pin_usage[] = {
-	/* UART2 (spare, 3,3 V TTL level only) */
-	GPA4_RXD1 | ENABLE_PU,
-	GPA5_TXD1,
-	GPA6_NCTS1 | ENABLE_PU,
-	GPA7_NRTS1,
-	/* UART3 (spare, 3,3 V TTL level only) */
-	GPB0_RXD2 | ENABLE_PU,
-	GPB1_TXD2,
-	/* UART4 (spare, 3,3 V TTL level only) */
-	GPB2_RXD3 | ENABLE_PU,
-	GPB3_TXD3,
-
-	GPB4_GPIO | GPIO_IN | ENABLE_PU,
-
-	/* I2C bus */
-	GPB5_IIC0_SCL,	/* external PU */
-	GPB6_IIC0_SDA,	/* external PU */
-
-	GPC0_SPI0_MISO | ENABLE_PU,
-	GPC1_SPI0_CLK,
-	GPC2_SPI0_MOSI,
-	GPC3_SPI0_NCS,
-
-	GPC4_SPI1_MISO | ENABLE_PU,
-	GPC5_SPI1_CLK,
-	GPC6_SPI1_MOSI,
-	GPC7_SPI1_NCS,
-
-	GPD0_AC97_BITCLK,
-	GPD1_AC97_NRST,
-	GPD2_AC97_SYNC,
-	GPD3_AC97_SDI | ENABLE_PU,
-	GPD4_AC97_SDO,
-
-	GPE0_GPIO | GPIO_OUT | GPIO_VAL(0), /* LCD backlight off */
-	GPE1_GPIO | GPIO_IN | ENABLE_PU,
-	GPE2_GPIO | GPIO_IN | ENABLE_PU,
-	GPE3_GPIO | GPIO_IN | ENABLE_PU,
-	GPE4_GPIO | GPIO_IN | ENABLE_PU,
-
-	/* keep all camera signals at reasonable values */
-	GPF0_GPIO | GPIO_IN | ENABLE_PU,
-	GPF1_GPIO | GPIO_IN | ENABLE_PU,
-	GPF2_GPIO | GPIO_IN | ENABLE_PU,
-	GPF3_GPIO | GPIO_IN | ENABLE_PU,
-	GPF4_GPIO | GPIO_IN | ENABLE_PU,
-	GPF5_GPIO | GPIO_IN | ENABLE_PU,
-	GPF6_GPIO | GPIO_IN | ENABLE_PU,
-	GPF7_GPIO | GPIO_IN | ENABLE_PU,
-	GPF8_GPIO | GPIO_IN | ENABLE_PU,
-	GPF9_GPIO | GPIO_IN | ENABLE_PU,
-	GPF10_GPIO | GPIO_IN | ENABLE_PU,
-	GPF11_GPIO | GPIO_IN | ENABLE_PU,
-	GPF12_GPIO | GPIO_IN | ENABLE_PU,
-	GPF13_GPIO | GPIO_OUT | GPIO_VAL(0), /* USB power off */
-#if 0
-	GPF14_CLKOUT, /* for testing purposes, but very noisy */
-#else
-	GPF14_GPIO | GPIO_OUT | GPIO_VAL(0), /* Buzzer off */
-#endif
-	GPF15_GPIO | GPIO_OUT | GPIO_VAL(0), /* Backlight PWM inactive */
-
-	/* SD card slot (all signals have external 10k PU) */
-	GPG0_MMC0_CLK,
-	GPG1_MMC0_CMD,
-	GPG2_MMC0_DAT0,
-	GPG3_MMC0_DAT1,
-	GPG4_MMC0_DAT2,
-	GPG5_MMC0_DAT3,
-	GPG6_MMC0_NCD,
-
-	/* SDIO slot (all used signals have external PU) */
-	GPH0_GPIO | GPIO_IN,	/* CLK */
-	GPH1_GPIO | GPIO_IN,	/* CMD */
-	GPH2_GPIO | GPIO_IN,	/* DAT0 */
-	GPH3_GPIO | GPIO_IN,	/* DAT1 */
-	GPH4_GPIO | GPIO_IN,	/* DAT2 */
-	GPH5_GPIO | GPIO_IN,	/* DAT3 */
-	GPH6_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
-	GPH7_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
-	GPH8_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
-	GPH9_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
-
-	/* as long as we are not using the LCD controller, disable the pins */
-	GPI0_GPIO | GPIO_IN | ENABLE_PD,
-	GPI1_GPIO | GPIO_IN | ENABLE_PD,
-	GPI2_GPIO | GPIO_IN | ENABLE_PD,
-	GPI3_GPIO | GPIO_IN | ENABLE_PD,
-	GPI4_GPIO | GPIO_IN | ENABLE_PD,
-	GPI5_GPIO | GPIO_IN | ENABLE_PD,
-	GPI6_GPIO | GPIO_IN | ENABLE_PD,
-	GPI7_GPIO | GPIO_IN | ENABLE_PD,
-	GPI8_GPIO | GPIO_IN | ENABLE_PD,
-	GPI9_GPIO | GPIO_IN | ENABLE_PD,
-	GPI10_GPIO | GPIO_IN | ENABLE_PD,
-	GPI11_GPIO | GPIO_IN | ENABLE_PD,
-	GPI12_GPIO | GPIO_IN | ENABLE_PD,
-	GPI13_GPIO | GPIO_IN | ENABLE_PD,
-	GPI14_GPIO | GPIO_IN | ENABLE_PD,
-	GPI15_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ0_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ1_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ2_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ3_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ4_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ5_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ6_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ7_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ8_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ9_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ10_GPIO | GPIO_IN | ENABLE_PD,
-	GPJ11_GPIO | GPIO_IN | ENABLE_PD,
-
-	GPK0_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK1_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK2_GPIO | GPIO_IN,
-	GPK3_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK4_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #1 (high = LED off) */
-	GPK5_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #2 (high = LED off) */
-	GPK6_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #3 (high = LED off) */
-	GPK7_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #4 (high = LED off) */
-	GPK8_GPIO | GPIO_IN, 			/* (external PU) */
-	GPK9_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK10_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK11_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK12_GPIO | GPIO_IN,			/* OCT_DET */
-	GPK13_GPIO | GPIO_IN,			/* WIFI power (external PU) */
-	GPK14_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPK15_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-
-	GPL0_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL1_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL2_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL3_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL4_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL5_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL6_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL7_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPL8_GPIO | GPIO_IN,			/* EINT16 (external PU) */
-	GPL9_GPIO | GPIO_IN | ENABLE_PU,	/* EINT17 */
-	GPL10_GPIO | GPIO_IN | ENABLE_PU,	/* EINT18 */
-	GPL11_GPIO | GPIO_IN,			/* EINT19 + K7 (external PU) */
-	GPL12_GPIO | GPIO_IN,			/* EINT20 + K6 (external PU) */
-	GPL13_GPIO | GPIO_IN,			/* SD0 WP (external PU) */
-	GPL14_GPIO | GPIO_IN,			/* SD1 WP (external PU) */
-
-	GPM0_GPIO | GPIO_IN,			/* (external PU) */
-	GPM1_GPIO | GPIO_IN,			/* (external PU) */
-	GPM2_GPIO | GPIO_IN,			/* (external PU) */
-	GPM3_GPIO | GPIO_IN,			/* (external PU) */
-	GPM4_GPIO | GPIO_IN,			/* (external PU) */
-	GPM5_GPIO | GPIO_IN,			/* (external PU) */
-
-	GPN0_GPIO | GPIO_IN,			/* EINT0 (external PU) */
-	GPN1_GPIO | GPIO_IN,			/* EINT1 (external PU) */
-	GPN2_GPIO | GPIO_IN,			/* EINT2 (external PU) */
-	GPN3_GPIO | GPIO_IN,			/* EINT3 (external PU) */
-	GPN4_GPIO | GPIO_IN,			/* EINT4 (external PU) */
-	GPN5_GPIO | GPIO_IN,			/* EINT5 (external PU) */
-	GPN6_GPIO | GPIO_IN,			/* EINT6 (external PU) */
-	GPN7_GPIO | GPIO_IN | ENABLE_PU,	/* EINT7 DM9000 interrupt */
-	GPN8_GPIO | GPIO_IN,			/* EINT8 USB detect (external PU) */
-	GPN9_GPIO | GPIO_IN,			/* EINT9 (external PU) */
-	GPN10_GPIO | GPIO_IN,			/* SD1 CD (external PU) */
-	GPN11_GPIO | GPIO_IN,			/* EINT11 (external PU) */
-	GPN12_GPIO | GPIO_IN,			/* EINT12 IR in (external PU) */
-	GPN13_GPIO | GPIO_IN,			/* BOOT0/EINT13 (externally fixed) */
-	GPN14_GPIO | GPIO_IN,			/* BOOT1/EINT14 (externally fixed) */
-	GPN15_GPIO | GPIO_IN,			/* BOOT2/EINT15 (externally fixed) */
-
-	GPO0_NCS2,				/* NAND */
-	GPO1_NCS3,				/* NAND */
-	GPO2_NCS4,				/* CON5 */
-	GPO3_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO4_GPIO | GPIO_IN | ENABLE_PU,	/* CON5 pin 8 */
-	GPO5_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO6_ADDR6,				/* CON5 */
-	GPO7_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO8_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO9_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO10_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO11_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO12_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO13_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO14_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPO15_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-
-	GPP0_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP1_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP2_NWAIT | ENABLE_PU,			/* CON5 */
-	GPP3_FALE,				/* NAND */
-	GPP4_FCLE,				/* NAND */
-	GPP5_FWE,				/* NAND */
-	GPP6_FRE,				/* NAND */
-	GPP7_RNB,				/* NAND (external PU) */
-	GPP8_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP9_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP10_GPIO | GPIO_IN,			/* (external PU) */
-	GPP11_GPIO | GPIO_IN,			/* (external PU) */
-	GPP12_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP13_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-	GPP14_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
-
-	GPQ0_GPIO | GPIO_IN | ENABLE_PU,	/* not used as LADDR18 */
-	GPQ1_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ2_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ3_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ4_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ5_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ6_GPIO | GPIO_IN,			/* (external PU) */
-	GPQ7_GPIO | GPIO_IN | ENABLE_PU,	/* not used as LADDR17 */
-	GPQ8_GPIO | GPIO_IN | ENABLE_PU,	/* not used as LADDR16 */
-};
-
-static int mini6410_mem_init(void)
-{
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c6410_get_memory_size());
-
-	return 0;
-}
-mem_initcall(mini6410_mem_init);
-
-static const struct s3c6410_chipselect dm900_cs = {
-	.adr_setup_t = 0,
-	.access_setup_t = 0,
-	.access_t = 20,
-	.cs_hold_t = 3,
-	.adr_hold_t = 20, /* CS must be de-asserted for at least 20 ns */
-	.width = 16,
-};
-
-static void mini6410_setup_dm9000_cs(void)
-{
-	s3c6410_setup_chipselect(1, &dm900_cs);
-}
-
-static int mini6410_devices_init(void)
-{
-	int i;
-
-	/* ----------- configure the access to the outer space ---------- */
-	for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
-		s3c_gpio_mode(pin_usage[i]);
-
-	mini6410_setup_dm9000_cs();
-	add_dm9000_device(0, S3C_CS1_BASE + 0x300, S3C_CS1_BASE + 0x304,
-				IORESOURCE_MEM_16BIT, &dm9000_data);
-
-	armlinux_set_architecture(MACH_TYPE_MINI6410);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_friendlyarm_mini6410);
-
-	return 0;
-}
-
-device_initcall(mini6410_devices_init);
-
-static int mini6410_console_init(void)
-{
-	s3c_gpio_mode(GPA0_RXD0 | ENABLE_PU);
-	s3c_gpio_mode(GPA1_TXD0);
-	s3c_gpio_mode(GPA2_NCTS0 | ENABLE_PU);
-	s3c_gpio_mode(GPA3_NRTS0);
-
-	barebox_set_model("Friendlyarm mini6410");
-	barebox_set_hostname("mini6410");
-
-	s3c64xx_add_uart1();
-
-	return 0;
-}
-
-console_initcall(mini6410_console_init);
diff --git a/arch/arm/boards/friendlyarm-tiny210/config.h b/arch/arm/boards/friendlyarm-tiny210/config.h
deleted file mode 100644
index 86aedf0a64..0000000000
--- a/arch/arm/boards/friendlyarm-tiny210/config.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#define S5PCXX_CLOCK_REFERENCE 24000000
-
-#define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
-
-#define BOARD_APLL_VAL	set_pll(0x7d, 0x3, 0x1)
-#define BOARD_MPLL_VAL	set_pll(0x29b, 0xc, 0x1)
-#define BOARD_EPLL_VAL	set_pll(0x60, 0x6, 0x2)
-#define BOARD_VPLL_VAL	set_pll(0x6c, 0x6, 0x3)
-
-#define BOARD_CLK_DIV0_MASK	0xFFFFFFFF
-#define BOARD_CLK_DIV0_VAL	0x14131440
-#define BOARD_APLL_LOCKTIME	0x2cf
-
-#define S5P_DRAM_WR	3
-#define S5P_DRAM_CAS	4
-#define DMC_TIMING_AREF	0x00000618
-#define DMC_TIMING_ROW	0x2B34438A
-#define DMC_TIMING_DATA	0x24240000
-#define DMC_TIMING_PWR	0x0BDC0343
diff --git a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
deleted file mode 100644
index d79661b222..0000000000
--- a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: 2012 Alexey Galakhov
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <io.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/sections.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-clocks.h>
-#include <mach/s3c-generic.h>
-
-#define IRAM_CODE_BASE		0xD0020010
-
-/* Tiny210 has 4 leds numbered from 0 to 3 at GPJ2 */
-static inline void __bare_init debug_led(int led, bool state)
-{
-	uint32_t r;
-	/* GPJ2CON: mode 0001=output */
-	r = readl(0xE0200280);
-	r &= ~(0xF << (4 * led));
-	r |=  (0x1 << (4 * led));
-	writel(r, 0xE0200280);
-	/* GPJ2DAT: active low */
-	r = readl(0xE0200284);
-	r &= ~(1 << led);
-	r |= (state ? 0 : 1) << led;
-	writel(r, 0xE0200284);
-}
-
-/*
- * iROM boot from MMC
- * TODO: replace this by native boot
- */
-
-#define ADDR_V210_SDMMC_BASE	0xD0037488
-#define ADDR_CopySDMMCtoMem	0xD0037F98
-
-static int __bare_init s5p_irom_load_mmc(void *dest, uint32_t start_block,
-					 uint16_t block_count)
-{
-	typedef uint32_t (*func_t) (int32_t, uint32_t, uint16_t, uint32_t*, int8_t);
-	uint32_t chbase = readl(ADDR_V210_SDMMC_BASE);
-	func_t func = (func_t)readl(ADDR_CopySDMMCtoMem);
-	int chan = (chbase - 0xEB000000) >> 20;
-	if (chan != 0 && chan != 2)
-		return 0;
-	return func(chan, start_block, block_count, (uint32_t*)dest, 0) ? 1 : 0;
-}
-
-static __bare_init __naked void jump_sdram(unsigned long offset)
-{
-	__asm__ __volatile__ (
-			"sub lr, lr, %0;"
-			"mov pc, lr;" : : "r"(offset)
-			);
-}
-
-static __bare_init bool load_stage2(void *dest, size_t size)
-{
-	/* TODO add other ways to boot */
-	return s5p_irom_load_mmc(dest, 1, (size+ 511) / 512);
-}
-
-void __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	arm_cpu_lowlevel_init();
-
-#ifdef CONFIG_S3C_PLL_INIT
-	s5p_init_pll();
-#endif
-
-	debug_led(0, 1);
-
-	if (get_pc() < IRAM_CODE_BASE) /* Are we running from iRAM? */
-		/* No, we don't. */
-		goto boot;
-
-	s5p_init_dram_bank_ddr2(S5P_DMC0_BASE, 0x20E00323, 0, 0);
-
-	debug_led(1, 1);
-
-	if (! load_stage2((void*)(_text - 16),
-				barebox_image_size + 16)) {
-		debug_led(3, 1);
-		while (1) { } /* hang */
-	}
-
-	debug_led(2, 1);
-
-	jump_sdram(IRAM_CODE_BASE - (unsigned long)_text);
-
-	debug_led(1, 0);
-
-boot:
-	barebox_arm_entry(S3C_SDRAM_BASE, SZ_256M, NULL);
-}
diff --git a/arch/arm/boards/friendlyarm-tiny210/tiny210.c b/arch/arm/boards/friendlyarm-tiny210/tiny210.c
deleted file mode 100644
index c96aa83059..0000000000
--- a/arch/arm/boards/friendlyarm-tiny210/tiny210.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2012 Alexey Galakhov
- * Based on Mini6410 code by Juergen Beisert
- *
- * Copyright (C) 2012 Juergen Beisert, Pengutronix
- *
- * In some ways inspired by code
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <linux/sizes.h>
-#include <generated/mach-types.h>
-#include <gpio.h>
-#include <led.h>
-#include <io.h>
-#include <nand.h>
-#include <asm/armlinux.h>
-#include <mach/iomux.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-clocks.h>
-#include <mach/s3c-generic.h>
-
-
-static const unsigned pin_usage[] = {
-	/* TODO */
-};
-
-static struct gpio_led leds[] = {
-	{
-		.gpio = GPJ20,
-		.led = {
-			.name = "led1",
-		}
-	}, {
-		.gpio = GPJ21,
-		.led = {
-			.name = "led2",
-		}
-	}, {
-		.gpio = GPJ22,
-		.led = {
-			.name = "led3",
-		}
-	}, {
-		.gpio = GPJ23,
-		.led = {
-			.name = "led4",
-		}
-	}
-};
-
-static int tiny210_mem_init(void)
-{
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s5p_get_memory_size());
-	return 0;
-}
-mem_initcall(tiny210_mem_init);
-
-static int tiny210_console_init(void)
-{
-	/*
-	 * configure the UART1 right now, as barebox will
-	 * start to send data immediately
-	 */
-	s3c_gpio_mode(GPA00_RXD0 | ENABLE_PU);
-	s3c_gpio_mode(GPA01_TXD0);
-	s3c_gpio_mode(GPA02_NCTS0 | ENABLE_PU);
-	s3c_gpio_mode(GPA03_NRTS0);
-
-	barebox_set_model("Friendlyarm tiny210");
-	barebox_set_hostname("tiny210");
-
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL,
-			   S3C_UART1_BASE, S3C_UART1_SIZE,
-			   IORESOURCE_MEM, NULL);
-	return 0;
-}
-console_initcall(tiny210_console_init);
-
-static int tiny210_devices_init(void)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
-		s3c_gpio_mode(pin_usage[i]);
-
-	for (i = 0; i < ARRAY_SIZE(leds); i++) {
-		leds[i].active_low = 1;
-		gpio_direction_output(leds[i].gpio, leds[i].active_low);
-		led_gpio_register(&leds[i]);
-	}
-
-	led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led);
-
-	armlinux_set_architecture(MACH_TYPE_MINI210);
-
-	return 0;
-}
-device_initcall(tiny210_devices_init);
diff --git a/arch/arm/boards/friendlyarm-tiny6410/Kconfig b/arch/arm/boards/friendlyarm-tiny6410/Kconfig
deleted file mode 100644
index 374820f8b3..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if MACH_TINY6410
-
-choice
-	prompt "FriendlyARM Tiny6410 baseboard"
-	help
-	  Since the Tiny6410 is a CPU card only, it requires a basebord to make
-	  it work. Select here the baseboard Barebox should expect and
-	  configure.
-
-config MACH_TINY6410_FA
-	bool
-	select HAS_DM9000
-	prompt "FA development platform"
-	help
-	  FriendlyARM's Tiny6410 evaluation board.
-
-endchoice
-
-endif
diff --git a/arch/arm/boards/friendlyarm-tiny6410/Makefile b/arch/arm/boards/friendlyarm-tiny6410/Makefile
deleted file mode 100644
index ba3f3360f8..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-obj-y += tiny6410.o
-lwl-y += lowlevel.o
-lwl-$(CONFIG_MACH_TINY6410_FA) += development-board.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-friendlyarm-tiny6410
diff --git a/arch/arm/boards/friendlyarm-tiny6410/config.h b/arch/arm/boards/friendlyarm-tiny6410/config.h
deleted file mode 100644
index 04f68579ed..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/config.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* FriendlyARM Tiny6410 specific global settings */
-
-#ifndef _TINY6410_CONFIG_H_
-# define _TINY6410_CONFIG_H_
-
-#define S3C64XX_CLOCK_REFERENCE 12000000
-
-#endif /* _TINY6410_CONFIG_H_ */
diff --git a/arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config b/arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config
deleted file mode 100644
index f38535be48..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config
+++ /dev/null
@@ -1,52 +0,0 @@
-#!/bin/sh
-
-machine=tiny6410
-eth0.serverip=a.b.c.d.e
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d.e
-#eth0.netmask=a.b.c.d.e
-#eth0.gateway=a.b.c.d.e
-#eth0.ethaddr=
-
-# can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${machine}.${rootfs_type}
-
-# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
-kernelimage=zImage-${machine}
-#kernelimage=uImage-$machine
-#kernelimage=Image-$machine
-#kernelimage=Image-$machine.lzo
-
-if [ -n $user ]; then
-	kernelimage="${user}"-"${kernelimage}"
-	nfsroot="${eth0.serverip}:/home/${user}/nfsroot/${machine}"
-	rootfsimage="${user}"-"${rootfsimage}"
-else
-	nfsroot="${eth0.serverip}:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-#
-# "tiny6410" kernel parameter
-# 0 .. 9 = screen type
-# i = touchscreen with propritary FriendlyARM protocol
-# Note: can be "tiny6410= " if nothing of these components are connected
-#
-bootargs="console=ttySAC0,115200 tiny6410=0"
-
-nand_device="nand"
-nand_parts="256k(barebox),128k(bareboxenv),1536k(kernel),-(root)"
-rootfs_mtdblock_nand=3
diff --git a/arch/arm/boards/friendlyarm-tiny6410/development-board.c b/arch/arm/boards/friendlyarm-tiny6410/development-board.c
deleted file mode 100644
index 69c9768405..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/development-board.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2012 Juergen Beisert
-
-/*
- * The FriendlyARM's Tiny6410 evaluation board comes with all connectors and
- * devices to make the Tiny6410 CPU card work. This includes:
- *
- * - the DM9000 network controller
- * - USB/MCI connectors
- * - display connector
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <gpio.h>
-#include <platform_data/eth-dm9000.h>
-#include <mach/devices-s3c64xx.h>
-#include <mach/s3c-generic.h>
-#include <mach/iomux.h>
-
-#include "tiny6410.h"
-
-/*
- * dm9000 network controller onboard
- * Connected to CS line 1 and interrupt line EINT7,
- * data width is 16 bit
- * Area 1: Offset 0x300...0x301
- * Area 2: Offset 0x304...0x305
- */
-static struct dm9000_platform_data dm9000_data = {
-	.srom = 0,	/* no serial ROM for the ethernet address */
-};
-
-static const struct s3c6410_chipselect dm900_cs = {
-	.adr_setup_t = 0,
-	.access_setup_t = 0,
-	.access_t = 20,
-	.cs_hold_t = 3,
-	.adr_hold_t = 20, /* CS must be de-asserted for at least 20 ns */
-	.width = 16,
-};
-
-static void tiny6410evk_setup_dm9000_cs(void)
-{
-	s3c6410_setup_chipselect(1, &dm900_cs);
-}
-
-static const unsigned tiny6410evk_pin_usage[] = {
-	/* UART1 (V24) */
-	GPA4_RXD1 | ENABLE_PU,
-	GPA5_TXD1,
-	GPA6_NCTS1 | ENABLE_PU,
-	GPA7_NRTS1,
-	/* UART2 (V24) */
-	GPB0_RXD2 | ENABLE_PU,
-	GPB1_TXD2,
-	/* UART3 (spare, 3,3 V TTL level only) */
-	GPB2_RXD3 | ENABLE_PU,
-	GPB3_TXD3,
-};
-
-static int tiny6410evk_devices_init(void)
-{
-	int i;
-
-	/* init CPU card specific devices first */
-	tiny6410_init("FA EVK");
-
-	/* ----------- configure the access to the outer space ---------- */
-	for (i = 0; i < ARRAY_SIZE(tiny6410evk_pin_usage); i++)
-		s3c_gpio_mode(tiny6410evk_pin_usage[i]);
-
-	tiny6410evk_setup_dm9000_cs();
-	add_dm9000_device(0, S3C_CS1_BASE + 0x300, S3C_CS1_BASE + 0x304,
-				IORESOURCE_MEM_16BIT, &dm9000_data);
-	return 0;
-}
-device_initcall(tiny6410evk_devices_init);
-
-static int tiny6410evk_console_init(void)
-{
-	/* note: UART0 has no RTS/CTS connected */
-	s3c_gpio_mode(GPA0_RXD0 | ENABLE_PU);
-	s3c_gpio_mode(GPA1_TXD0);
-
-	barebox_set_model("Friendlyarm tiny6410");
-	barebox_set_hostname("tiny6410");
-
-	s3c64xx_add_uart1();
-
-	return 0;
-}
-console_initcall(tiny6410evk_console_init);
diff --git a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c b/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c
deleted file mode 100644
index ccbdd13795..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/s3c-iomap.h>
-
-void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	arm_cpu_lowlevel_init();
-	barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL);
-}
diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c
deleted file mode 100644
index a1126b7893..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2012 Juergen Beisert
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <gpio.h>
-#include <generated/mach-types.h>
-#include <asm/armlinux.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/iomux.h>
-
-#include "tiny6410.h"
-
-static const unsigned tiny6410_pin_usage[] = {
-	/* UART0 */
-	GPA2_GPIO | GPIO_IN | ENABLE_PU, /* CTS not connected */
-	GPA3_GPIO | GPIO_IN | ENABLE_PU, /* RTS not connected */
-
-	/* local bus' D0 ... D15 are always active */
-	/* local bus' A0...A5 are always active */
-
-	/* internal NAND memory */
-	GPO0_NCS2,	/* NAND's first chip select line */
-	/* NAND's second chip select line, not used */
-	GPO1_GPIO | GPIO_OUT | GPIO_VAL(1),
-	GPP3_FALE,
-	GPP4_FCLE,
-	GPP5_FWE,
-	GPP6_FRE,
-	GPP7_RNB, /* external pull-up */
-
-	GPF13_GPIO  | GPIO_OUT | GPIO_VAL(0), /* OTG power supply, 0 = off */
-
-	/* nowhere connected */
-	GPO2_GPIO | GPIO_IN | ENABLE_PU,
-	GPO3_GPIO | GPIO_IN | ENABLE_PU,
-	GPO4_GPIO | GPIO_IN | ENABLE_PU,
-	GPO5_GPIO | GPIO_IN | ENABLE_PU,
-
-	/* local bus address lines 6...15 are nowhere connected */
-	GPO6_GPIO | GPIO_IN | ENABLE_PU,
-	GPO7_GPIO | GPIO_IN | ENABLE_PU,
-	GPO8_GPIO | GPIO_IN | ENABLE_PU,
-	GPO9_GPIO | GPIO_IN | ENABLE_PU,
-	GPO10_GPIO | GPIO_IN | ENABLE_PU,
-	GPO11_GPIO | GPIO_IN | ENABLE_PU,
-	GPO12_GPIO | GPIO_IN | ENABLE_PU,
-	GPO13_GPIO | GPIO_IN | ENABLE_PU,
-	GPO14_GPIO | GPIO_IN | ENABLE_PU,
-	GPO15_GPIO | GPIO_IN | ENABLE_PU,
-};
-
-static int tiny6410_mem_init(void)
-{
-	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c6410_get_memory_size());
-
-	return 0;
-}
-mem_initcall(tiny6410_mem_init);
-
-void tiny6410_init(const char *bb_name)
-{
-	int i;
-
-	/* ----------- configure the access to the outer space ---------- */
-	for (i = 0; i < ARRAY_SIZE(tiny6410_pin_usage); i++)
-		s3c_gpio_mode(tiny6410_pin_usage[i]);
-
-	armlinux_set_architecture(MACH_TYPE_TINY6410);
-}
diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h
deleted file mode 100644
index bbe8877ca0..0000000000
--- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h
+++ /dev/null
@@ -1,4 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/* to be called by the base board */
-void tiny6410_init(const char*);
diff --git a/arch/arm/boards/gateworks-ventana/Makefile b/arch/arm/boards/gateworks-ventana/Makefile
index 7d195eebd6..4e1cefbc4c 100644
--- a/arch/arm/boards/gateworks-ventana/Makefile
+++ b/arch/arm/boards/gateworks-ventana/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o gsc.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/gateworks-ventana/board.c b/arch/arm/boards/gateworks-ventana/board.c
index 163f8338c6..aa2137a971 100644
--- a/arch/arm/boards/gateworks-ventana/board.c
+++ b/arch/arm/boards/gateworks-ventana/board.c
@@ -8,8 +8,8 @@
 #include <linux/marvell_phy.h>
 #include <linux/pci.h>
 #include <linux/phy.h>
-#include <mach/bbu.h>
-#include <mach/imx6.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/imx6.h>
 #include <net.h>
 
 #include "gsc.h"
@@ -19,9 +19,14 @@ static int gw54xx_wdog_of_fixup(struct device_node *root, void *context)
 	struct device_node *np;
 
 	/* switch to the watchdog with internal reset capabilities */
-	np = of_find_node_by_name(root, "wdog@020c0000");
+	np = of_find_node_by_name_address(root, "wdog@020c0000");
 	of_device_disable(np);
-	np = of_find_node_by_name(root, "wdog@020bc000");
+	np = of_find_node_by_name_address(root, "watchdog@20c0000");
+	of_device_disable(np);
+
+	np = of_find_node_by_name_address(root, "wdog@020bc000");
+	of_device_enable(np);
+	np = of_find_node_by_name_address(root, "watchdog@20bc000");
 	of_device_enable(np);
 
 	return 0;
diff --git a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
index 98c7ae6095..cde49ef029 100644
--- a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
+++ b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
@@ -1,9 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 #include "ram-base.imxcfg"
 #include "quad_128x64.imxcfg"
diff --git a/arch/arm/boards/gateworks-ventana/lowlevel.c b/arch/arm/boards/gateworks-ventana/lowlevel.c
index 0a79d82049..db18b53139 100644
--- a/arch/arm/boards/gateworks-ventana/lowlevel.c
+++ b/arch/arm/boards/gateworks-ventana/lowlevel.c
@@ -1,6 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
diff --git a/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg b/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg
index daf01a8ad1..66a7876649 100644
--- a/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg
+++ b/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 wm 32 MX6_MMDC_P0_MPWLDECTRL0	0x00190017
 wm 32 MX6_MMDC_P0_MPWLDECTRL1	0x00140026
 wm 32 MX6_MMDC_P1_MPWLDECTRL0	0x0021001C
diff --git a/arch/arm/boards/gateworks-ventana/ram-base.imxcfg b/arch/arm/boards/gateworks-ventana/ram-base.imxcfg
index 07dc34c0bb..c482f60b09 100644
--- a/arch/arm/boards/gateworks-ventana/ram-base.imxcfg
+++ b/arch/arm/boards/gateworks-ventana/ram-base.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 wm 32 MX6_IOM_DRAM_SDQS0	0x00000030
 wm 32 MX6_IOM_DRAM_SDQS1	0x00000030
 wm 32 MX6_IOM_DRAM_SDQS2	0x00000030
diff --git a/arch/arm/boards/gk802/Makefile b/arch/arm/boards/gk802/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/gk802/Makefile
+++ b/arch/arm/boards/gk802/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/gk802/board.c b/arch/arm/boards/gk802/board.c
index 2713d6e756..c4a90306e8 100644
--- a/arch/arm/boards/gk802/board.c
+++ b/arch/arm/boards/gk802/board.c
@@ -9,9 +9,9 @@
 #include <envfs.h>
 #include <gpio.h>
 #include <init.h>
-#include <mach/generic.h>
-#include <mach/imx6-regs.h>
-#include <mach/imx6.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx6.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
 #include <linux/sizes.h>
 #include <of.h>
diff --git a/arch/arm/boards/gk802/flash-header.imxcfg b/arch/arm/boards/gk802/flash-header.imxcfg
index acc7a36785..e77f4601cb 100644
--- a/arch/arm/boards/gk802/flash-header.imxcfg
+++ b/arch/arm/boards/gk802/flash-header.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x10000000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
diff --git a/arch/arm/boards/gk802/lowlevel.c b/arch/arm/boards/gk802/lowlevel.c
index a41b711e36..7c56a6a1a6 100644
--- a/arch/arm/boards/gk802/lowlevel.c
+++ b/arch/arm/boards/gk802/lowlevel.c
@@ -1,6 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
diff --git a/arch/arm/boards/globalscale-guruplug/Makefile b/arch/arm/boards/globalscale-guruplug/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/globalscale-guruplug/Makefile
+++ b/arch/arm/boards/globalscale-guruplug/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/globalscale-guruplug/lowlevel.c b/arch/arm/boards/globalscale-guruplug/lowlevel.c
index 964d3510ee..a54d848c04 100644
--- a/arch/arm/boards/globalscale-guruplug/lowlevel.c
+++ b/arch/arm/boards/globalscale-guruplug/lowlevel.c
@@ -4,12 +4,12 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 
 extern char __dtb_kirkwood_guruplug_server_plus_bb_start[];
 
-ENTRY_FUNCTION(start_globalscale_guruplug, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_globalscale_guruplug, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/globalscale-mirabox/Makefile b/arch/arm/boards/globalscale-mirabox/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/globalscale-mirabox/Makefile
+++ b/arch/arm/boards/globalscale-mirabox/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/globalscale-mirabox/lowlevel.c b/arch/arm/boards/globalscale-mirabox/lowlevel.c
index 094792d461..da08e80d74 100644
--- a/arch/arm/boards/globalscale-mirabox/lowlevel.c
+++ b/arch/arm/boards/globalscale-mirabox/lowlevel.c
@@ -4,12 +4,12 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 
 extern char __dtb_armada_370_mirabox_bb_start[];
 
-ENTRY_FUNCTION(start_globalscale_mirabox, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_globalscale_mirabox, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/grinn-liteboard/Makefile b/arch/arm/boards/grinn-liteboard/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/grinn-liteboard/Makefile
+++ b/arch/arm/boards/grinn-liteboard/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/grinn-liteboard/board.c b/arch/arm/boards/grinn-liteboard/board.c
index 3e69ea520a..6d390a5287 100644
--- a/arch/arm/boards/grinn-liteboard/board.c
+++ b/arch/arm/boards/grinn-liteboard/board.c
@@ -9,8 +9,8 @@
 #include <common.h>
 #include <envfs.h>
 #include <init.h>
-#include <mach/bbu.h>
-#include <mach/imx6.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/imx6.h>
 #include <malloc.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
 #include <of.h>
@@ -25,7 +25,7 @@ static void bbu_register_handler_emmc(bool is_boot_source)
 {
 	int emmc_boot_flag = 0, emmc_flag = 0;
 	const char *bootpart;
-	struct device_d *dev;
+	struct device *dev;
 	int ret;
 
 	if (!is_boot_source)
diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg
index 1b980c7846..c2d4b2875b 100644
--- a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg
+++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 #define SETUP_MDASP_MDCTL		\
 	wm 32 0x021B0040 0x00000047;	\
diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg
index c93a2cc0fa..45bc841ab5 100644
--- a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg
+++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 #define SETUP_MDASP_MDCTL		\
 	wm 32 0x021B0040 0x0000004F;	\
diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h
index 82f5c627a3..776a69f8b6 100644
--- a/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h
+++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 loadaddr 0x80000000
 soc imx6
diff --git a/arch/arm/boards/grinn-liteboard/lowlevel.c b/arch/arm/boards/grinn-liteboard/lowlevel.c
index d3ee212ca9..6851a678bc 100644
--- a/arch/arm/boards/grinn-liteboard/lowlevel.c
+++ b/arch/arm/boards/grinn-liteboard/lowlevel.c
@@ -4,6 +4,7 @@
 /* Author: Marcin Niestroj <m.niestroj@grinn-global.com> */
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <linux/sizes.h>
 #include <io.h>
@@ -13,8 +14,8 @@
 #include <asm/sections.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <mach/esdctl.h>
-#include <mach/imx6.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/imx6.h>
 
 static inline void setup_uart(void)
 {
diff --git a/arch/arm/boards/guf-cupid/Makefile b/arch/arm/boards/guf-cupid/Makefile
deleted file mode 100644
index 86a27f301d..0000000000
--- a/arch/arm/boards/guf-cupid/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de>
-
-lwl-y += lowlevel.o
-obj-y += board.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-guf-cupid
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
deleted file mode 100644
index 0c62b573c9..0000000000
--- a/arch/arm/boards/guf-cupid/board.c
+++ /dev/null
@@ -1,340 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-// SPDX-FileCopyrightText: 2009 Juergen Beisert <kernel@pengutronix.de>, Pengutronix
-
-/* Board support for the Garz+Fricke Cupid board */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <driver.h>
-#include <environment.h>
-#include <fs.h>
-#include <envfs.h>
-#include <mach/imx35-regs.h>
-#include <asm/armlinux.h>
-#include <io.h>
-#include <gpio.h>
-#include <partition.h>
-#include <nand.h>
-#include <generated/mach-types.h>
-#include <mach/imx-nand.h>
-#include <platform_data/eth-fec.h>
-#include <fb.h>
-#include <asm/mmu.h>
-#include <mach/weim.h>
-#include <mach/imx-ipu-fb.h>
-#include <mach/imx-pll.h>
-#include <mach/iomux-mx35.h>
-#include <mach/devices-imx35.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type = PHY_INTERFACE_MODE_MII,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.width	= 1,
-	.hw_ecc	= 1,
-	.flash_bbt = 1,
-};
-
-static struct fb_videomode guf_cupid_fb_mode = {
-	/* 800x480 @ 70 Hz */
-	.name		= "CPT CLAA070LC0JCT",
-	.refresh	= 70,
-	.xres		= 800,
-	.yres		= 480,
-	.pixclock	= 30761,
-	.left_margin	= 24,
-	.right_margin	= 47,
-	.upper_margin	= 5,
-	.lower_margin	= 3,
-	.hsync_len	= 24,
-	.vsync_len	= 3,
-	.sync		= FB_SYNC_VERT_HIGH_ACT | FB_SYNC_CLK_INVERT |
-			  FB_SYNC_OE_ACT_HIGH,
-	.vmode		= FB_VMODE_NONINTERLACED,
-};
-
-#define GPIO_LCD_ENABLE		(2 * 32 + 24)
-#define GPIO_LCD_BACKLIGHT	(0 * 32 + 19)
-
-static void cupid_fb_enable(int enable)
-{
-	if (enable) {
-		gpio_direction_output(GPIO_LCD_ENABLE, 1);
-		mdelay(100);
-		gpio_direction_output(GPIO_LCD_BACKLIGHT, 1);
-	} else {
-		gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
-		mdelay(100);
-		gpio_direction_output(GPIO_LCD_ENABLE, 0);
-	}
-}
-
-static struct imx_ipu_fb_platform_data ipu_fb_data = {
-	.mode		= &guf_cupid_fb_mode,
-	.num_modes	= 1,
-	.bpp		= 16,
-	.enable		= cupid_fb_enable,
-};
-
-static int cupid_mmu_init(void)
-{
-	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-
-	return 0;
-}
-postmmu_initcall(cupid_mmu_init);
-
-static int cupid_devices_init(void)
-{
-	uint32_t reg;
-
-	gpio_direction_output(GPIO_LCD_ENABLE, 0);
-	gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
-
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
-	/* some fuses provide us vital information about connected hardware */
-	if (reg & 0x20000000)
-		nand_info.width = 2;    /* 16 bit */
-	else
-		nand_info.width = 1;    /* 8 bit */
-
-	imx35_add_fec(&fec_info);
-	imx35_add_nand(&nand_info);
-
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-	devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-
-	imx35_add_fb(&ipu_fb_data);
-	imx35_add_mmc0(NULL);
-
-	armlinux_set_architecture(MACH_TYPE_GUF_CUPID);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_guf_cupid);
-
-	return 0;
-}
-
-device_initcall(cupid_devices_init);
-
-static iomux_v3_cfg_t cupid_pads[] = {
-	/* UART1 */
-	MX35_PAD_CTS1__UART1_CTS,
-	MX35_PAD_RTS1__UART1_RTS,
-	MX35_PAD_TXD1__UART1_TXD_MUX,
-	MX35_PAD_RXD1__UART1_RXD_MUX,
-	/* UART2 */
-	MX35_PAD_CTS2__UART2_CTS,
-	MX35_PAD_RTS2__UART2_RTS,
-	MX35_PAD_TXD2__UART2_TXD_MUX,
-	MX35_PAD_RXD2__UART2_RXD_MUX,
-	/* FEC */
-	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
-	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
-	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
-	MX35_PAD_FEC_COL__FEC_COL,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX35_PAD_FEC_MDC__FEC_MDC,
-	MX35_PAD_FEC_MDIO__FEC_MDIO,
-	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
-	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
-	MX35_PAD_FEC_CRS__FEC_CRS,
-	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
-	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
-	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
-	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
-	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
-	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
-	/* I2C1 */
-	MX35_PAD_I2C1_CLK__I2C1_SCL,
-	MX35_PAD_I2C1_DAT__I2C1_SDA,
-	/* Display */
-	MX35_PAD_LD0__IPU_DISPB_DAT_0,
-	MX35_PAD_LD1__IPU_DISPB_DAT_1,
-	MX35_PAD_LD2__IPU_DISPB_DAT_2,
-	MX35_PAD_LD3__IPU_DISPB_DAT_3,
-	MX35_PAD_LD4__IPU_DISPB_DAT_4,
-	MX35_PAD_LD5__IPU_DISPB_DAT_5,
-	MX35_PAD_LD6__IPU_DISPB_DAT_6,
-	MX35_PAD_LD7__IPU_DISPB_DAT_7,
-	MX35_PAD_LD8__IPU_DISPB_DAT_8,
-	MX35_PAD_LD9__IPU_DISPB_DAT_9,
-	MX35_PAD_LD10__IPU_DISPB_DAT_10,
-	MX35_PAD_LD11__IPU_DISPB_DAT_11,
-	MX35_PAD_LD12__IPU_DISPB_DAT_12,
-	MX35_PAD_LD13__IPU_DISPB_DAT_13,
-	MX35_PAD_LD14__IPU_DISPB_DAT_14,
-	MX35_PAD_LD15__IPU_DISPB_DAT_15,
-	MX35_PAD_LD16__IPU_DISPB_DAT_16,
-	MX35_PAD_LD17__IPU_DISPB_DAT_17,
-	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
-	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
-	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
-	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
-	MX35_PAD_LD18__GPIO3_24,		/* LCD enable */
-	MX35_PAD_CSPI1_SS1__GPIO1_19,		/* LCD backligtht PWM */
-	/* USB Host*/
-	MX35_PAD_MLB_CLK__GPIO3_3,		/* USB Host PWR */
-	MX35_PAD_MLB_DAT__GPIO3_4,		/* USB Host Overcurrent */
-	/* USB OTG */
-	MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
-	MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
-	/* SSI */
-	MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
-	MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
-	MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
-	MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
-	/* UCB1400 IRQ */
-	MX35_PAD_ATA_INTRQ__GPIO2_29,
-	/* Speaker On */
-	MX35_PAD_LD20__GPIO3_26,
-	/* LEDs */
-	MX35_PAD_TX1__GPIO1_14,
-	/* ESDHC1 */
-	MX35_PAD_SD1_CMD__ESDHC1_CMD,
-	MX35_PAD_SD1_CLK__ESDHC1_CLK,
-	MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
-	MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
-	MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
-	MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
-	/* ESDHC1 CD */
-	MX35_PAD_ATA_DATA5__GPIO2_18,
-	/* ESDHC1 WP */
-	MX35_PAD_ATA_DATA6__GPIO2_19,
-};
-
-static int cupid_console_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(cupid_pads, ARRAY_SIZE(cupid_pads));
-
-	barebox_set_model("Garz & Fricke CUPID");
-	barebox_set_hostname("cupid");
-
-	imx35_add_uart0();
-
-	return 0;
-}
-
-console_initcall(cupid_console_init);
-
-static int cupid_core_setup(void)
-{
-	u32 tmp;
-
-	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
-
-	/*
-	 * Clear the on and off peripheral modules Supervisor Protect bit
-	 * for SDMA to access them. Did not change the AIPS control registers
-	 * (offset 0x20) access type
-	 */
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
-	tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50);
-	tmp &= 0x00FFFFFF;
-	writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50);
-
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
-	tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50);
-	tmp &= 0x00FFFFFF;
-	writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50);
-
-	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-
-	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0);   /* for S0 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
-
-	/* SGPCR - always park on last master */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
-
-	/* MGPCR - restore default values */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
-
-	/* CS0: NOR Flash */
-	imx35_setup_weimcs(0, 0x0000DCF6, 0x444A4541, 0x44443302);
-
-	/*
-	 * M3IF Control Register (M3IFCTL)
-	 * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[1] = MAX1 not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[2] = L2CC1 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[3] = USB  not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[4] = SDMA not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[5] = GPU not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
-	 * MRRP[7] = IPU2 not on priority list (0 << 0)		= 0x00000000
-	 *                                                       ------------
-	 *                                                        0x00000040
-	 */
-	writel(0x40, MX35_M3IF_BASE_ADDR);
-
-	return 0;
-}
-
-core_initcall(cupid_core_setup);
-
-static int do_cpufreq(int argc, char *argv[])
-{
-	unsigned long freq;
-
-	if (argc != 2)
-		return COMMAND_ERROR_USAGE;
-
-	freq = simple_strtoul(argv[1], NULL, 0);
-
-	switch (freq) {
-	case 399:
-		writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
-		break;
-	case 532:
-		writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
-		break;
-	default:
-		return COMMAND_ERROR_USAGE;
-	}
-
-	printf("Switched CPU frequency to %luMHz\n", freq);
-
-	return 0;
-}
-
-BAREBOX_CMD_START(cpufreq)
-	.cmd            = do_cpufreq,
-	BAREBOX_CMD_DESC("adjust CPU frequency")
-	BAREBOX_CMD_OPTS("399|532")
-	BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP)
-BAREBOX_CMD_END
diff --git a/arch/arm/boards/guf-cupid/defaultenv-guf-cupid/config b/arch/arm/boards/guf-cupid/defaultenv-guf-cupid/config
deleted file mode 100644
index dc289b39f2..0000000000
--- a/arch/arm/boards/guf-cupid/defaultenv-guf-cupid/config
+++ /dev/null
@@ -1,50 +0,0 @@
-#!/bin/sh
-
-eth0.serverip=
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nor', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${global.hostname}.$rootfs_type
-
-kernelimage=zImage-${global.hostname}
-#kernelimage=uImage-${global.hostname}
-#kernelimage=Image-${global.hostname}
-#kernelimage=Image-${global.hostname}.lzo
-
-if [ -n $user ]; then
-	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
-	rootfsimage="$user"-"$rootfsimage"
-else
-	nfsroot="$eth0.serverip:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-bootargs="console=ttymxc0,115200"
-
-bootargs="$bootargs video=mx3fb:CTP-CLAA070LC0ACW"
-
-nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
-nand_device=mxc_nand
-rootfs_mtdblock_nand=3
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
-
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
deleted file mode 100644
index 6b6590f5d8..0000000000
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ /dev/null
@@ -1,301 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-#include <common.h>
-#include <init.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/cache-l2x0.h>
-#include <io.h>
-#include <mach/imx-nand.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/sections.h>
-#include <asm-generic/memory_layout.h>
-#include <asm/system.h>
-
-#define SDRAM_MODE_BL_8	0x0003
-#define SDRAM_MODE_BSEQ	0x0000
-#define SDRAM_MODE_CL_3	0x0030
-#define MDDR_DS_HALF	0x20
-#define SDRAM_COMPARE_CONST1	0x55555555
-#define SDRAM_COMPARE_CONST2	0xaaaaaaaa
-
-static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_addr)
-{
-	volatile int loop;
-	void *r9 = (void *)MX35_CSD0_BASE_ADDR;
-	u32 r11 = 0xda; /* dummy constant */
-	u32 r1, r0;
-
-	/* disable second SDRAM region to save power */
-	r1 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
-	r1 &= ~ESDCTL0_SDE;
-	writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
-
-	mode |= ESDMISC_RST | ESDMISC_MDDR_DL_RST;
-	writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-
-	mode &= ~(ESDMISC_RST | ESDMISC_MDDR_DL_RST);
-	writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-
-	/* wait for esdctl reset */
-	for (loop = 0; loop < 0x20000; loop++);
-
-	r1 = ESDCFGx_tXP_4 | ESDCFGx_tWTR_1 |
-		ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 |
-		ESDCFGx_tWR_1_2 | ESDCFGx_tRAS_6 |
-		ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 |
-		ESDCFGx_tRCD_3 | ESDCFGx_tRC_20;
-
-	writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
-
-	/* enable SDRAM controller */
-	writel(memsize | ESDCTL0_SMODE_NORMAL,
-			MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-
-	/* Micron Datasheet Initialization Step 3: Wait 200us before first command */
-	for (loop = 0; loop < 1000; loop++);
-
-	/* Micron Datasheet Initialization Step 4: PRE CHARGE ALL */
-	writel(memsize | ESDCTL0_SMODE_PRECHARGE,
-			MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(r11, sdram_addr);
-
-	/* Micron Datasheet Initialization Step 5: NOP for tRP (at least 22.5ns)
-	 * The CPU is not fast enough to cause a problem here
-	 */
-
-	/* Micron Datasheet Initialization Step 6: 2 AUTO REFRESH and tRFC NOP
-	 * (at least 140ns)
-	 */
-	writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH,
-			MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(r11, r9); /* AUTO REFRESH #1 */
-
-	for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */
-
-	writeb(r11, r9); /* AUTO REFRESH #2 */
-
-	for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */
-
-	/* Micron Datasheet Initialization Step 7: LOAD MODE REGISTER */
-	writel(memsize | ESDCTL0_SMODE_LOAD_MODE,
-			MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(r11, r9 + (SDRAM_MODE_BL_8 | SDRAM_MODE_BSEQ | SDRAM_MODE_CL_3));
-
-	/* Micron Datasheet Initialization Step 8: tMRD = 2 tCK NOP
-	 * (The memory controller will take care of this delay)
-	 */
-
-	/* Micron Datasheet Initialization Step 9: LOAD MODE REGISTER EXTENDED */
-	writeb(r11, 0x84000000 | MDDR_DS_HALF);  /*we assume 14 Rows / 10 Cols here */
-
-	/* Micron Datasheet Initialization Step 9: tMRD = 2 tCK NOP
-	 * (The memory controller will take care of this delay)
-	 */
-
-	/* Now configure SDRAM-Controller and check that it works */
-	writel(memsize | ESDCTL0_BL | ESDCTL0_REF4,
-			MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-
-	/* Freescale asks for first access to be a write to properly
-	 * initialize DQS pin-state and keepers
-	 */
-	writel(0xdeadbeef, r9);
-
-	/* test that the RAM is in fact working */
-	writel(SDRAM_COMPARE_CONST1, r9);
-	writel(SDRAM_COMPARE_CONST2, r9 + 0x4);
-
-	if (readl(r9) != SDRAM_COMPARE_CONST1)
-		while (1);
-
-	/* Verify that the correct row and coloumn is selected */
-
-	/* So far we asssumed that we have 14 rows, verify this */
-	writel(SDRAM_COMPARE_CONST1, r9);
-	writel(SDRAM_COMPARE_CONST2, r9 + (1 << 25));
-
-	/* if both value are identical, we don't have 14 rows. assume 13 instead */
-	if (readl(r9) == readl(r9 + (1 << 25))) {
-		r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-		r0 &= ~ESDCTL0_ROW_MASK;
-		r0 |= ESDCTL0_ROW13;
-		writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	}
-
-	/* So far we asssumed that we have 10 columns, verify this */
-	writel(SDRAM_COMPARE_CONST1, r9);
-	writel(SDRAM_COMPARE_CONST2, r9 + (1 << 11));
-
-	/* if both value are identical, we don't have 10 cols. assume 9 instead */
-	if (readl(r9) == readl(r9 + (1 << 11))) {
-		r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-		r0 &= ~ESDCTL0_COL_MASK;
-		r0 |= ESDCTL0_COL9;
-		writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	}
-}
-
-#define BRANCH_PREDICTION_ENABLE
-#define UNALIGNED_ACCESS_ENABLE
-#define LOW_INT_LATENCY_ENABLE
-
-void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	void *iomuxc_base = (void *)MX35_IOMUXC_BASE_ADDR;
-	int i;
-
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(0x10000000 + 128 * 1024);
-
-	/*
-	 *       ARM1136 init
-	 *       - invalidate I/D cache/TLB and drain write buffer;
-	 *       - invalidate L2 cache
-	 *       - unaligned access
-	 *       - branch predictions
-	 */
-#ifdef TURN_OFF_IMPRECISE_ABORT
-	__asm__ __volatile__("mrs %0, cpsr":"=r"(r0));
-	r0 &= ~0x100;
-	__asm__ __volatile__("msr cpsr, %0" : : "r"(r0));
-#endif
-	/* ensure L1 caches and MMU are turned-off for now */
-	r1 = get_cr();
-	r1 &= ~(CR_I | CR_M | CR_C);
-
-	/* setup core features */
-	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1":"=r"(r0));
-#ifdef BRANCH_PREDICTION_ENABLE
-	r0 |= 7;
-	r1 |= CR_Z;
-#else
-	r0 &= ~7;
-	r1 &= ~CR_Z;
-#endif
-	__asm__ __volatile__("mcr p15, 0, r0, c1, c0, 1" : : "r"(r0));
-
-#ifdef UNALIGNED_ACCESS_ENABLE
-	r1 |= CR_U;
-#else
-	r1 &= ~CR_U;
-#endif
-
-#ifdef LOW_INT_LATENCY_ENABLE
-	r1 |= CR_FI;
-#else
-	r1 &= ~CR_FI;
-#endif
-	set_cr(r1);
-
-	r0 = 0;
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r0));
-
-	/* invalidate I cache and D cache */
-	__asm__ __volatile__("mcr p15, 0, r0, c7, c7, 0" : : "r"(r0));
-	/* invalidate TLBs */
-	__asm__ __volatile__("mcr p15, 0, r0, c8, c7, 0" : : "r"(r0));
-	/* Drain the write buffer */
-	__asm__ __volatile__("mcr p15, 0, r0, c7, c10, 4" : : "r"(r0));
-
-	/* Also setup the Peripheral Port Remap register inside the core */
-	r0 = 0x40000015; /* start from AIPS 2GB region */
-	__asm__ __volatile__("mcr p15, 0, r0, c15, c2, 4" : : "r"(r0));
-
-#define	WDOG_WMCR 0x8
-	/* silence reset WDOG */
-	writew(0, MX35_WDOG_BASE_ADDR + WDOG_WMCR);
-
-	/* Skip SDRAM initialization if we run from RAM */
-	r0 = get_pc();
-	if (r0 > 0x80000000 && r0 < 0x90000000)
-		goto out;
-
-	/* Configure drive strength */
-
-	/* Configure DDR-pins to correct mode */
-	r0 = 0x00001800;
-	writel(r0, iomuxc_base + 0x794);
-	writel(r0, iomuxc_base + 0x798);
-	writel(r0, iomuxc_base + 0x79c);
-	writel(r0, iomuxc_base + 0x7a0);
-	writel(r0, iomuxc_base + 0x7a4);
-
-	/* Set drive strength for DDR-pins */
-	for (i = 0x368; i <= 0x4c8; i += 4) {
-		r0 = readl(iomuxc_base + i);
-		r0 &= ~0x6;
-		r0 |= 0x2;
-		writel(r0, iomuxc_base + i);
-		if (i == 0x468)
-			i = 0x4a4;
-	}
-
-	r0 = readl(iomuxc_base + 0x480);
-	r0 &= ~0x6;
-	r0 |= 0x2;
-	writel(r0, iomuxc_base + 0x480);
-
-	r0 = readl(iomuxc_base + 0x4b8);
-	r0 &= ~0x6;
-	r0 |= 0x2;
-	writel(r0, iomuxc_base + 0x4b8);
-
-	/* Configure static chip-selects */
-	r0 = readl(iomuxc_base + 0x000);
-	r0 &= ~1; /* configure CS2/CSD0 for SDRAM */
-	writel(r0, iomuxc_base + 0x000);
-
-	/* start-up code doesn't need any static chip-select.
-	 * Leave their initialization to high-level code that
-	 * can initialize them depending on the baseboard.
-	 */
-
-	/* Configure clocks */
-
-	/* setup cpu/bus clocks */
-	writel(0x003f4208, MX35_CCM_BASE_ADDR + MX35_CCM_CCMR);
-
-	/* configure MPLL */
-	writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
-
-	/* configure PPLL */
-	writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + MX35_CCM_PPCTL);
-
-	/* configure core dividers */
-	r0 = MX35_PDR0_CCM_PER_AHB(1) | MX35_PDR0_HSP_PODF(2);
-
-	writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR0);
-
-	/* configure clock-gates */
-	r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
-	r0 |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT;
-	writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
-
-	r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
-	r0 |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
-	r0 |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
-	writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
-
-	/* Configure SDRAM */
-	/* Try 32-Bit 256 MB DDR memory */
-	r0 = ESDCTL0_SDE | ESDCTL0_ROW14 | ESDCTL0_COL10 | ESDCTL0_DSIZ_31_0; /* 1024 MBit DDR-SDRAM */
-	setup_sdram(r0, ESDMISC_MDDR_EN, 0x80000f00);
-
-	if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
-		/* Speed up NAND controller by adjusting the NFC divider */
-		r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-		r0 &= ~(0xf << 28);
-		r0 |= 0x1 << 28;
-		writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-
-		imx35_barebox_boot_nand_external();
-	}
-
-out:
-	imx35_barebox_entry(NULL);
-}
diff --git a/arch/arm/boards/guf-neso/Makefile b/arch/arm/boards/guf-neso/Makefile
deleted file mode 100644
index af90c36c7e..0000000000
--- a/arch/arm/boards/guf-neso/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-lwl-y += lowlevel.o
-obj-y += board.o
-obj-y += pll_init.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-guf-neso
diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c
deleted file mode 100644
index 9eb862db64..0000000000
--- a/arch/arm/boards/guf-neso/board.c
+++ /dev/null
@@ -1,319 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2010 Sascha Hauer, Pengutronix
-
-#include <common.h>
-#include <net.h>
-#include <init.h>
-#include <environment.h>
-#include <platform_data/eth-fec.h>
-#include <notifier.h>
-#include <partition.h>
-#include <gpio.h>
-#include <fs.h>
-#include <envfs.h>
-#include <fcntl.h>
-#include <nand.h>
-#include <command.h>
-#include <spi/spi.h>
-#include <usb/ulpi.h>
-
-#include <io.h>
-#include <asm/mmu.h>
-#include <asm/armlinux.h>
-#include <generated/mach-types.h>
-
-#include <mach/spi.h>
-#include <mach/imx27-regs.h>
-#include <mach/iomux-mx27.h>
-#include <mach/imx-nand.h>
-#include <mach/imx-pll.h>
-#include <mach/imxfb.h>
-#include <mach/devices-imx27.h>
-
-/* two pins are controlling the CS signals to the USB phys */
-#define USBH2_PHY_CS_GPIO (GPIO_PORTF + 20)
-#define OTG_PHY_CS_GPIO (GPIO_PORTF + 19)
-
-/* two pins are controlling the display and its backlight */
-#define LCD_POWER_GPIO (GPIO_PORTF + 18)
-#define BACKLIGHT_POWER_GPIO (GPIO_PORTE + 5)
-
-static struct fec_platform_data fec_info = {
-	.xcv_type = PHY_INTERFACE_MODE_MII,
-	.phy_addr = 31,
-};
-
-static struct imx_nand_platform_data nand_info = {
-	.width		= 1,
-	.hw_ecc		= 1,
-	.flash_bbt	= 1,
-};
-
-static struct fb_videomode imxfb_mode = {
-	.name		= "CPT CLAA070LC0JCT",
-	.refresh	= 60,
-	.xres		= 800,
-	.yres		= 480,
-	.pixclock	= KHZ2PICOS(27000),
-	.hsync_len	= 1,	/* DE only sync */
-	.left_margin	= 50,
-	.right_margin	= 50,
-	.vsync_len	= 1,	/* DE only sync */
-	.upper_margin	= 10,
-	.lower_margin	= 10,
-};
-
-static void neso_fb_enable(int enable)
-{
-	gpio_direction_output(LCD_POWER_GPIO, enable);
-	gpio_direction_output(BACKLIGHT_POWER_GPIO, enable);
-}
-
-static struct imx_fb_platform_data neso_fb_data = {
-	.mode	= &imxfb_mode,
-	.num_modes = 1,
-	.pwmr	= 0x00000000,	/* doesn't matter */
-	.lscr1	= 0x00120300,	/* doesn't matter */
-	/* dynamic mode -> using the reset values (as recommended in the datasheet) */
-	.dmacr	= (0 << 31) | (4 << 16) | 96,
-	.enable	= neso_fb_enable,
-	.framebuffer_ovl = (void *)0xa7f00000,
-	/*
-	 * - TFT style panel
-	 * - clk enabled while idle
-	 * - clock inverted
-	 * - data not inverted
-	 * - data enable high active
-	 */
-	.pcr = PCR_TFT |
-		PCR_COLOR |
-		PCR_PBSIZ_8 |
-		PCR_BPIX_16 |
-		PCR_CLKPOL |
-		PCR_SCLK_SEL |
-		PCR_LPPOL |
-		PCR_FLMPOL,
-	.bpp = 16,	/* TODO 32 bit does not work: The 'green' component is lacking in this mode */
-};
-
-#if defined(CONFIG_USB) && defined(CONFIG_USB_ULPI)
-static void neso_usbh_init(void)
-{
-	uint32_t temp;
-
-	temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600);
-	temp &= ~((3 << 21) | 1);
-	temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20) | (1<<11);
-	writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600);
-
-	temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584);
-	temp &= ~(3 << 30);
-	temp |= 2 << 30;
-	writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584);
-
-	mdelay(10);
-
-	gpio_set_value(USBH2_PHY_CS_GPIO, 0);
-	mdelay(10);
-	ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
-	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC,
-				    MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
-}
-#else
-static void neso_usbh_init(void) { }
-#endif
-
-static int neso_devices_init(void)
-{
-	int i;
-
-	unsigned int mode[] = {
-		/* UART1 */
-		PE12_PF_UART1_TXD,
-		PE13_PF_UART1_RXD,
-		PE14_PF_UART1_CTS,
-		PE15_PF_UART1_RTS,
-		/* FEC */
-		PD0_AIN_FEC_TXD0,
-		PD1_AIN_FEC_TXD1,
-		PD2_AIN_FEC_TXD2,
-		PD3_AIN_FEC_TXD3,
-		PD4_AOUT_FEC_RX_ER,
-		PD5_AOUT_FEC_RXD1,
-		PD6_AOUT_FEC_RXD2,
-		PD7_AOUT_FEC_RXD3,
-		PD8_AF_FEC_MDIO,
-		PD9_AIN_FEC_MDC,
-		PD10_AOUT_FEC_CRS,
-		PD11_AOUT_FEC_TX_CLK,
-		PD12_AOUT_FEC_RXD0,
-		PD13_AOUT_FEC_RX_DV,
-		PD14_AOUT_FEC_RX_CLK,
-		PD15_AOUT_FEC_COL,
-		PD16_AIN_FEC_TX_ER,
-		PF23_AIN_FEC_TX_EN,
-
-		/* SSI1 connected in AC97 style */
-		PC20_PF_SSI1_FS,
-		PC21_PF_SSI1_RXD,
-		PC22_PF_SSI1_TXD,
-		PC23_PF_SSI1_CLK,
-
-		/* LED 1 */
-		(GPIO_PORTB | 15 | GPIO_GPIO | GPIO_OUT),
-		/* LED 2 */
-		(GPIO_PORTB | 16 | GPIO_GPIO | GPIO_OUT),
-		/* CTOUCH reset */
-		(GPIO_PORTB | 17 | GPIO_GPIO | GPIO_OUT),
-		/* CTOUCH IRQ */
-		(GPIO_PORTB | 14 | GPIO_GPIO | GPIO_IN),
-		/* RTC IRQ */
-		(GPIO_PORTF | 14 | GPIO_GPIO | GPIO_IN),
-		/* SD change card detection */
-		(GPIO_PORTF | 17 | GPIO_GPIO | GPIO_IN),
-		/* SDHC1*/
-		PE18_PF_SD1_D0,
-		PE19_PF_SD1_D1,
-		PE20_PF_SD1_D2,
-		PE21_PF_SD1_D3,
-		PE22_PF_SD1_CMD,
-		PE23_PF_SD1_CLK,
-		/* I2C1 */
-		PD17_PF_I2C_DATA,
-		PD18_PF_I2C_CLK,
-		/* I2C2, for CTOUCH */
-		PC5_PF_I2C2_SDA,
-		PC6_PF_I2C2_SCL,
-
-		/* Connected to: Both USB phys and ethernet phy FIXME 1 = RESET? */
-		PE17_PF_RESET_OUT,
-
-		/* USB host */
-		(USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT),
-		PA0_PF_USBH2_CLK,
-		PA1_PF_USBH2_DIR,
-		PA3_PF_USBH2_NXT,
-		PA4_PF_USBH2_STP,
-		PD22_AF_USBH2_DATA0,
-		PD24_AF_USBH2_DATA1,
-		PD23_AF_USBH2_DATA2,
-		PD20_AF_USBH2_DATA3,
-		PD19_AF_USBH2_DATA4,
-		PD26_AF_USBH2_DATA5,
-		PD21_AF_USBH2_DATA6,
-		PA2_PF_USBH2_DATA7,
-
-		/* USB OTG */
-		(OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT),
-		PE24_PF_USBOTG_CLK,
-		PE2_PF_USBOTG_DIR,
-		PE0_PF_USBOTG_NXT,
-		PE1_PF_USBOTG_STP,
-		PC9_PF_USBOTG_DATA0,
-		PC11_PF_USBOTG_DATA1,
-		PC10_PF_USBOTG_DATA2,
-		PC13_PF_USBOTG_DATA3,
-		PC12_PF_USBOTG_DATA4,
-		PC7_PF_USBOTG_DATA5,
-		PC8_PF_USBOTG_DATA6,
-		PE25_PF_USBOTG_DATA7,
-
-		/* Display signals */
-		(LCD_POWER_GPIO | GPIO_GPIO | GPIO_OUT), /* LCD power: 1 = LCD on */
-		PA5_PF_LSCLK,
-		PA6_PF_LD0,
-		PA7_PF_LD1,
-		PA8_PF_LD2,
-		PA9_PF_LD3,
-		PA10_PF_LD4,
-		PA11_PF_LD5,
-		PA12_PF_LD6,
-		PA13_PF_LD7,
-		PA14_PF_LD8,
-		PA15_PF_LD9,
-		PA16_PF_LD10,
-		PA17_PF_LD11,
-		PA18_PF_LD12,
-		PA19_PF_LD13,
-		PA20_PF_LD14,
-		PA21_PF_LD15,
-		PA22_PF_LD16,
-		PA23_PF_LD17,
-		PA31_PF_OE_ACD,	/* DE */
-
-		/* Backlight PWM (Use as gpio) */
-		(BACKLIGHT_POWER_GPIO | GPIO_GPIO | GPIO_OUT),
-	};
-
-	/* reset the chip select lines to the USB/OTG phys to avoid any hang */
-	gpio_direction_output(OTG_PHY_CS_GPIO, 1);
-	gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
-
-	/* initialize gpios */
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx27_gpio_mode(mode[i]);
-
-	imx27_add_nand(&nand_info);
-	imx27_add_fb(&neso_fb_data);
-
-	neso_usbh_init();
-
-	imx27_add_fec(&fec_info);
-
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-
-	devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-
-	armlinux_set_architecture(MACH_TYPE_NESO);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_guf_neso);
-
-	return 0;
-}
-
-device_initcall(neso_devices_init);
-
-static int neso_console_init(void)
-{
-	barebox_set_model("Garz & Fricke NESO");
-	barebox_set_hostname("neso");
-
-	imx27_add_uart0();
-
-	return 0;
-}
-
-console_initcall(neso_console_init);
-
-extern void *neso_pll_init, *neso_pll_init_end;
-
-static int neso_pll(void)
-{
-	void *vram = (void *)0xffff4c00;
-	void (*pllfunc)(void) = vram;
-
-	printf("initialising PLLs\n");
-
-	memcpy(vram, &neso_pll_init, 0x100);
-
-	console_flush();
-
-	pllfunc();
-
-	/* clock gating enable */
-	writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR);
-
-	writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0);
-	writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1);
-
-	/* Clocks have changed. Notify clients */
-	clock_notifier_call_chain();
-
-	return 0;
-}
-
-late_initcall(neso_pll);
-
diff --git a/arch/arm/boards/guf-neso/defaultenv-guf-neso/config b/arch/arm/boards/guf-neso/defaultenv-guf-neso/config
deleted file mode 100644
index bd44a555d9..0000000000
--- a/arch/arm/boards/guf-neso/defaultenv-guf-neso/config
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/bin/sh
-
-eth0.serverip=
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nor', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${global.hostname}.$rootfs_type
-
-kernelimage=zImage-${global.hostname}
-#kernelimage=uImage-${global.hostname}
-#kernelimage=Image-${global.hostname}
-#kernelimage=Image-${global.hostname}.lzo
-
-if [ -n $user ]; then
-	kernelimage="$user"-"$kernelimage"
-	nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
-	rootfsimage="$user"-"$rootfsimage"
-else
-	nfsroot="$eth0.serverip:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-bootargs="console=ttymxc0,115200"
-
-nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
-rootfs_mtdblock_nand=3
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
-
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
deleted file mode 100644
index df91bc329f..0000000000
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-#include <common.h>
-#include <init.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/cache-l2x0.h>
-#include <io.h>
-#include <mach/imx-nand.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/system.h>
-#include <asm/sections.h>
-#include <asm-generic/memory_layout.h>
-
-#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
-
-void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	uint32_t r;
-	int i;
-
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE);
-
-	/* ahb lite ip interface */
-	writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
-	writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
-	writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
-	writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
-
-	/* Skip SDRAM initialization if we run from RAM */
-	r = get_pc();
-	if (r > 0xa0000000 && r < 0xb0000000)
-		goto out;
-
-	/*
-	 * DDR on CSD0
-	 */
-	/* Enable DDR SDRAM operation */
-	writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-
-	/* Set the driving strength   */
-	writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
-	writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
-	writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
-	writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
-	writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
-
-	/* Initial reset */
-	writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
-
-	/* precharge CSD0 all banks */
-	writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
-			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writel(0x00000000, 0xA0000F00);	/* CSD0 precharge address (A10 = 1) */
-	writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
-			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-
-	for (i = 0; i < 8; i++)
-		writel(0, 0xa0000f00);
-
-	writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
-			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-
-	writeb(0xda, 0xa0000033);
-	writeb(0xff, 0xa1000000);
-	writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
-			ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
-			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-
-	if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND))
-		imx27_barebox_boot_nand_external();
-
-out:
-	imx27_barebox_entry(NULL);
-}
diff --git a/arch/arm/boards/guf-neso/pll_init.S b/arch/arm/boards/guf-neso/pll_init.S
deleted file mode 100644
index 4c6cb67fd4..0000000000
--- a/arch/arm/boards/guf-neso/pll_init.S
+++ /dev/null
@@ -1,51 +0,0 @@
-#include <config.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx-pll.h>
-#include <linux/linkage.h>
-
-#define writel(val, reg) \
-	ldr		r0,	=reg;	\
-	ldr		r1,	=val;	\
-	str		r1,   [r0];
-
-#define CSCR_VAL MX27_CSCR_USB_DIV(3) |	\
-		 MX27_CSCR_SD_CNT(3) |	\
-		 MX27_CSCR_MSHC_SEL |	\
-		 MX27_CSCR_H264_SEL |	\
-		 MX27_CSCR_SSI1_SEL |	\
-		 MX27_CSCR_SSI2_SEL |	\
-		 MX27_CSCR_MCU_SEL |		\
-		 MX27_CSCR_ARM_SRC_MPLL |	\
-		 MX27_CSCR_SP_SEL |		\
-		 MX27_CSCR_ARM_DIV(0) |	\
-		 MX27_CSCR_FPM_EN |		\
-		 MX27_CSCR_SPEN |		\
-		 MX27_CSCR_MPEN |		\
-		 MX27_CSCR_AHB_DIV(1)
-
-ENTRY(neso_pll_init)
-
-	/* 399 MHz */
-	writel(IMX_PLL_PD(0) |
-		 IMX_PLL_MFD(51) |
-		 IMX_PLL_MFI(7) |
-		 IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0)
-
-	/* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
-	writel(IMX_PLL_PD(1) |
-		 IMX_PLL_MFD(12) |
-		 IMX_PLL_MFI(9) |
-		 IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0)
-
-	writel(CSCR_VAL | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
-			MX27_CCM_BASE_ADDR + MX27_CSCR)
-
-	ldr r2, =16000
-1:
-	subs    r2, r2, #1
-	nop
-	bcs 1b
-
-	mov     pc, lr
-ENDPROC(neso_pll_init)
-
diff --git a/arch/arm/boards/guf-santaro/Makefile b/arch/arm/boards/guf-santaro/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/guf-santaro/Makefile
+++ b/arch/arm/boards/guf-santaro/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/guf-santaro/board.c b/arch/arm/boards/guf-santaro/board.c
index 34005ff7bf..acc3fc7f07 100644
--- a/arch/arm/boards/guf-santaro/board.c
+++ b/arch/arm/boards/guf-santaro/board.c
@@ -6,28 +6,27 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/imx6-regs.h>
+#include <mach/imx/imx6-regs.h>
 #include <asm/armlinux.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
 #include <bootsource.h>
 #include <bbu.h>
-#include <mach/bbu.h>
-#include <mach/imx6.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/imx6.h>
 #include <i2c/i2c.h>
 #include <gpio.h>
 
 static int i2c_device_present(struct i2c_adapter *adapter, int addr)
 {
 	struct i2c_client client = {};
-	u8 reg;
 
 	client.adapter = adapter;
 	client.addr = addr;
 
-	return i2c_write_reg(&client, 0x00, &reg, 0) < 0 ? false : true;
+	return i2c_write_reg(&client, 0x00, NULL, 0) < 0 ? false : true;
 }
 
 #define TOUCH_RESET_GPIO	IMX_GPIO_NR(1, 20)
diff --git a/arch/arm/boards/guf-santaro/flash-header.imxcfg b/arch/arm/boards/guf-santaro/flash-header.imxcfg
index 4505d81ea1..6d5bbae5d8 100644
--- a/arch/arm/boards/guf-santaro/flash-header.imxcfg
+++ b/arch/arm/boards/guf-santaro/flash-header.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x10000000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/guf-santaro/lowlevel.c b/arch/arm/boards/guf-santaro/lowlevel.c
index 30c5e9054a..72401eb32c 100644
--- a/arch/arm/boards/guf-santaro/lowlevel.c
+++ b/arch/arm/boards/guf-santaro/lowlevel.c
@@ -1,14 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <io.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <asm/cache.h>
-#include <mach/generic.h>
-#include <mach/imx6-regs.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6-regs.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <console.h>
-#include <mach/esdctl.h>
+#include <mach/imx/esdctl.h>
 
 static inline void setup_uart(void)
 {
diff --git a/arch/arm/boards/guf-vincell/Makefile b/arch/arm/boards/guf-vincell/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/guf-vincell/Makefile
+++ b/arch/arm/boards/guf-vincell/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c
index c0bb9d9e74..00a343ef99 100644
--- a/arch/arm/boards/guf-vincell/board.c
+++ b/arch/arm/boards/guf-vincell/board.c
@@ -11,11 +11,11 @@
 #include <io.h>
 #include <linux/clk.h>
 
-#include <mach/devices-imx53.h>
-#include <mach/generic.h>
-#include <mach/iim.h>
-#include <mach/bbu.h>
-#include <mach/imx5.h>
+#include <mach/imx/devices-imx53.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/iim.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/imx5.h>
 
 static int vincell_devices_init(void)
 {
diff --git a/arch/arm/boards/guf-vincell/flash-header.imxcfg b/arch/arm/boards/guf-vincell/flash-header.imxcfg
index c17dcbab6e..f5f2eceb5d 100644
--- a/arch/arm/boards/guf-vincell/flash-header.imxcfg
+++ b/arch/arm/boards/guf-vincell/flash-header.imxcfg
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x71000000
 soc imx53
 ivtofs 0x400
diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c
index 04060b2003..e691aeca3e 100644
--- a/arch/arm/boards/guf-vincell/lowlevel.c
+++ b/arch/arm/boards/guf-vincell/lowlevel.c
@@ -1,14 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <io.h>
 #include <init.h>
-#include <mach/imx53-regs.h>
-#include <mach/clock-imx51_53.h>
-#include <mach/imx5.h>
-#include <mach/iomux-v3.h>
-#include <mach/esdctl-v4.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/clock-imx51_53.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/iomux-v3.h>
+#include <mach/imx/esdctl-v4.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/cache.h>
diff --git a/arch/arm/boards/haba-knx/Makefile b/arch/arm/boards/haba-knx/Makefile
index b1c469dcf9..f2cf1123ed 100644
--- a/arch/arm/boards/haba-knx/Makefile
+++ b/arch/arm/boards/haba-knx/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/haba-knx/init.c b/arch/arm/boards/haba-knx/init.c
index d55739ee2a..d86e84e71a 100644
--- a/arch/arm/boards/haba-knx/init.c
+++ b/arch/arm/boards/haba-knx/init.c
@@ -7,25 +7,24 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/clk.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
 #include <led.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
 #include <spi/spi.h>
 #include <i2c/i2c.h>
 #include <libfile.h>
diff --git a/arch/arm/boards/haba-knx/lowlevel.c b/arch/arm/boards/haba-knx/lowlevel.c
index 7f52f824df..f71e0098e8 100644
--- a/arch/arm/boards/haba-knx/lowlevel.c
+++ b/arch/arm/boards/haba-knx/lowlevel.c
@@ -7,14 +7,12 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9260.h>
+#include <mach/at91/hardware.h>
 
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9260.h>
-#include <mach/hardware.h>
-
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_haba_knx_lite, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/imx233-olinuxino/Makefile b/arch/arm/boards/imx233-olinuxino/Makefile
index 987b34394a..1288c8c1de 100644
--- a/arch/arm/boards/imx233-olinuxino/Makefile
+++ b/arch/arm/boards/imx233-olinuxino/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y = imx23-olinuxino.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-imx233-olinuxino
diff --git a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c
index 14100747e0..cf92e2bb63 100644
--- a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c
+++ b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c
@@ -18,14 +18,12 @@
 #include <mci.h>
 #include <asm/armlinux.h>
 #include <asm/barebox-arm.h>
-#include <usb/ehci.h>
-#include <mach/usb.h>
-#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
-#include <mach/clock.h>
-#include <mach/mci.h>
-#include <mach/iomux.h>
-#include <generated/mach-types.h>
+#include <linux/usb/ehci.h>
+#include <mach/mxs/usb.h>
+#include <asm/mach-types.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/mci.h>
+#include <mach/mxs/iomux.h>
 
 static struct mxs_mci_platform_data mci_pdata = {
 	.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED,
diff --git a/arch/arm/boards/imx233-olinuxino/lowlevel.c b/arch/arm/boards/imx233-olinuxino/lowlevel.c
index 253cf1257b..91c1ba3dba 100644
--- a/arch/arm/boards/imx233-olinuxino/lowlevel.c
+++ b/arch/arm/boards/imx233-olinuxino/lowlevel.c
@@ -1,17 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx23-regs.h>
-#include <mach/init.h>
+#include <mach/mxs/imx23-regs.h>
+#include <mach/mxs/init.h>
 #include <io.h>
 #include <debug_ll.h>
-#include <mach/iomux.h>
-#include <generated/mach-types.h>
+#include <mach/mxs/iomux.h>
+#include <asm/mach-types.h>
+
+static noinline void continue_imx_entry(size_t size)
+{
+	static struct barebox_arm_boarddata boarddata = {
+		.magic = BAREBOX_ARM_BOARDDATA_MAGIC,
+		.machine = MACH_TYPE_IMX233_OLINUXINO,
+	};
+
+	barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata);
+}
 
 ENTRY_FUNCTION(start_barebox_olinuxino_imx23, r0, r1, r2)
 {
-	barebox_arm_entry(IMX_MEMORY_BASE, SZ_64M, (void *)MACH_TYPE_IMX233_OLINUXINO);
+	relocate_to_current_adr();
+	setup_c();
+
+	continue_imx_entry(SZ_64M);
 }
 
 static const uint32_t pad_setup[] = {
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/Makefile b/arch/arm/boards/innocomm-imx8mm-wb15/Makefile
new file mode 100644
index 0000000000..10abebc539
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o lpddr4-timing.o
+obj-y += board.o
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/board.c b/arch/arm/boards/innocomm-imx8mm-wb15/board.c
new file mode 100644
index 0000000000..5bb285b189
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/board.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <mach/imx/bbu.h>
+
+static int innocomm_wb15_evk_probe(struct device *dev)
+{
+	int emmc_bbu_flag = 0;
+	int sd_bbu_flag = 0;
+
+	if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) {
+		of_device_enable_path("/chosen/environment-sd");
+		sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	} else {
+		of_device_enable_path("/chosen/environment-emmc");
+		emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", emmc_bbu_flag);
+	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
+
+	return 0;
+}
+
+static const struct of_device_id innocomm_wb15_evk_of_match[] = {
+	{ .compatible = "innocomm,wb15-evk" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(innocomm_wb15_evk_of_match);
+
+static struct driver innocomm_wb15_evkboard_driver = {
+	.name = "board-innocomm-wb15-evk",
+	.probe = innocomm_wb15_evk_probe,
+	.of_compatible = DRV_OF_COMPAT(innocomm_wb15_evk_of_match),
+};
+coredevice_platform_driver(innocomm_wb15_evkboard_driver);
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg b/arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg
new file mode 100644
index 0000000000..8aff991618
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mm
+
+loadaddr 0x007e1000
+max_load_size 0x3f000
+ivtofs 0x400
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c
new file mode 100644
index 0000000000..a779c1f0ac
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <asm/barebox-arm.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/iomux-mx8mm.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mfd/bd71837.h>
+#include <mach/imx/xload.h>
+#include <soc/imx8m/ddr.h>
+
+#include "lowlevel.h"
+
+extern char __dtb_z_imx8mm_innocomm_wb15_evk_start[];
+
+#define UART_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
+
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mm_setup_pad(IMX8MM_PAD_UART2_TXD_UART2_TX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+	putc_ll('>');
+}
+
+static struct pmic_config bd71837_cfg[] = {
+	/* unlock the PMIC regs */
+	{ BD718XX_REGLOCK, 0x0 },
+	/* retry powering up indefinitely every 250ms after VR fault */
+	{ BD718XX_RCVCFG, 0xfc },
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	{ BD718XX_PWRONCONFIG1, 0x0 },
+	/* WDOG_B: Warm Reset */
+	{ BD718XX_PWRCTRL0, 0xa3 },
+	/* READY=>SNVS on PMIC_ON_REQ, SNVS=>RUN on VSYS_UVLO */
+	{ BD718XX_TRANS_COND0, 0x48 },
+	/* WDOG_B: Go to SNVS power state after deassert */
+	{ BD718XX_TRANS_COND1, 0xc0 },
+	/* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */
+	{ BD718XX_BUCK1_VOLT_RUN, 0xf },
+	/* increase VDD_DRAM to 0.900v for 2400MT/s DDR */
+	{ BD718XX_1ST_NODVS_BUCK_VOLT, 0x02 },
+	/* set BUCK8 to 1.10v */
+	{ BD718XX_4TH_NODVS_BUCK_VOLT, 0x1e },
+	/* lock the PMIC regs */
+	{ BD718XX_REGLOCK, 0x11 },
+};
+
+void innocomm_wb15_power_init_board(void)
+{
+	struct pbl_i2c *i2c;
+
+	imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL);
+	imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA);
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MM_I2C1_BASE_ADDR));
+
+	pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg));
+}
+
+ENTRY_FUNCTION(start_innocomm_wb15_evk, r0, r1, r2)
+{
+	imx8mm_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	setup_uart();
+
+	/*
+	 * If we are in EL3 we are running for the first time out of OCRAM,
+	 * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A
+	 * will then jump to DRAM in EL2
+	 */
+	if (current_el() == 3) {
+		imx8mm_early_clock_init();
+
+		innocomm_wb15_power_init_board();
+
+		imx8mm_ddr_init(&innocomm_wb15_dram_timing, DRAM_TYPE_LPDDR4);
+
+		imx8mm_load_and_start_image_via_tfa();
+	}
+
+	/* Standard entry we hit once we initialized both DDR and ATF */
+	imx8mm_barebox_entry(__dtb_z_imx8mm_innocomm_wb15_evk_start);
+}
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h
new file mode 100644
index 0000000000..3b0ea9ccc3
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef INNOCOMM_WB15_LOWLEVEL_H_
+#define INNOCOMM_WB15_LOWLEVEL_H_
+
+void innocomm_wb15_power_init_board(void);
+extern struct dram_timing_info innocomm_wb15_dram_timing;
+
+#endif
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c b/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c
new file mode 100644
index 0000000000..54c8442673
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c
@@ -0,0 +1,1132 @@
+/*
+ * Copyright 2018 InnoComm Mobile Technology Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+#define DDR_ONE_RANK
+#include <soc/imx8m/lpddr4_define.h>
+
+#include "lowlevel.h"
+
+static struct dram_cfg_param ddr_ddrc_cfg_1g_2ch1cs15r10cx32[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304,0x1},
+	{0x3d400030,0x1},
+	{0x3d400000,0xa1080020},
+	{0x3d400020,0x223},
+	{0x3d400024,0x2ee00},
+	{0x3d400064,0x49006c},
+	{0x3d4000d0,0xc0030495},
+	{0x3d4000d4,0x770000},
+	{0x3d4000dc,0xc40024},
+	{0x3d4000e0,0x310000},
+	{0x3d4000e8,0x66004d},
+	{0x3d4000ec,0x16004d},
+	{0x3d400100,0x1618141a},
+	{0x3d400104,0x504a6},
+	{0x3d40010c,0x909000},
+	{0x3d400110,0xb04060b},
+	{0x3d400114,0x2030909},
+	{0x3d400118,0x1010006},
+	{0x3d40011c,0x301},
+	{0x3d400130,0x20500},
+	{0x3d400134,0xb100002},
+	{0x3d400138,0x71},
+	{0x3d400144,0x78003c},
+	{0x3d400180,0x2580012},
+	{0x3d400184,0x1e0493e},
+	{0x3d400188,0x0},
+	{0x3d400190,0x4938208},
+	{0x3d400194,0x80303},
+	{0x3d4001b4,0x1308},
+	{0x3d4001a0,0xe0400018},
+	{0x3d4001a4,0xdf00e4},
+	{0x3d4001a8,0x80000000},
+	{0x3d4001b0,0x11},
+	{0x3d4001c0,0x1},
+	{0x3d4001c4,0x1},
+	{0x3d4000f4,0xc99},
+	{0x3d400108,0x60c1514},
+	{0x3d400200,0x1f},
+	{0x3d40020c,0x0},
+	{0x3d400210,0x1f1f},
+	{0x3d400204,0x80808},
+	{0x3d400214,0x7070707},
+	{0x3d400218,0xf070707},
+	{0x3d40021c,0xf0f},
+	{0x3d400250,0x29001701},
+	{0x3d400254,0x2c},
+	{0x3d40025c,0x4000030},
+	{0x3d400264,0x900093e7},
+	{0x3d40026c,0x2005574},
+	{0x3d400400,0x111},
+	{0x3d400408,0x72ff},
+	{0x3d400494,0x2100e07},
+	{0x3d400498,0x620096},
+	{0x3d40049c,0x1100e07},
+	{0x3d4004a0,0xc8012c},
+	{0x3d402020,0x21},
+	{0x3d402024,0x7d00},
+	{0x3d402050,0x20d040},
+	{0x3d402064,0xc0012},
+	{0x3d4020dc,0x840000},
+	{0x3d4020e0,0x310000},
+	{0x3d4020e8,0x66004d},
+	{0x3d4020ec,0x16004d},
+	{0x3d402100,0xa040305},
+	{0x3d402104,0x30407},
+	{0x3d402108,0x203060b},
+	{0x3d40210c,0x505000},
+	{0x3d402110,0x2040202},
+	{0x3d402114,0x2030202},
+	{0x3d402118,0x1010004},
+	{0x3d40211c,0x301},
+	{0x3d402130,0x20300},
+	{0x3d402134,0xa100002},
+	{0x3d402138,0x13},
+	{0x3d402144,0x14000a},
+	{0x3d402180,0x640004},
+	{0x3d402190,0x3818200},
+	{0x3d402194,0x80303},
+	{0x3d4021b4,0x100},
+	{0x3d4020f4,0xc99},
+	{0x3d403020,0x21},
+	{0x3d403024,0x1f40},
+	{0x3d403050,0x20d040},
+	{0x3d403064,0x30005},
+	{0x3d4030dc,0x840000},
+	{0x3d4030e0,0x310000},
+	{0x3d4030e8,0x66004d},
+	{0x3d4030ec,0x16004d},
+	{0x3d403100,0xa010102},
+	{0x3d403104,0x30404},
+	{0x3d403108,0x203060b},
+	{0x3d40310c,0x505000},
+	{0x3d403110,0x2040202},
+	{0x3d403114,0x2030202},
+	{0x3d403118,0x1010004},
+	{0x3d40311c,0x301},
+	{0x3d403130,0x20300},
+	{0x3d403134,0xa100002},
+	{0x3d403138,0x5},
+	{0x3d403144,0x50003},
+	{0x3d403180,0x190004},
+	{0x3d403190,0x3818200},
+	{0x3d403194,0x80303},
+	{0x3d4031b4,0x100},
+	{0x3d4030f4,0xc99},
+	{0x3d400028,0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0,0x0},
+	{0x100a1,0x1},
+	{0x100a2,0x2},
+	{0x100a3,0x3},
+	{0x100a4,0x4},
+	{0x100a5,0x5},
+	{0x100a6,0x6},
+	{0x100a7,0x7},
+	{0x110a0,0x0},
+	{0x110a1,0x1},
+	{0x110a2,0x3},
+	{0x110a3,0x4},
+	{0x110a4,0x5},
+	{0x110a5,0x2},
+	{0x110a6,0x7},
+	{0x110a7,0x6},
+	{0x120a0,0x0},
+	{0x120a1,0x1},
+	{0x120a2,0x3},
+	{0x120a3,0x2},
+	{0x120a4,0x5},
+	{0x120a5,0x4},
+	{0x120a6,0x7},
+	{0x120a7,0x6},
+	{0x130a0,0x0},
+	{0x130a1,0x1},
+	{0x130a2,0x2},
+	{0x130a3,0x3},
+	{0x130a4,0x4},
+	{0x130a5,0x5},
+	{0x130a6,0x6},
+	{0x130a7,0x7},
+	{0x1005f,0x1ff},
+	{0x1015f,0x1ff},
+	{0x1105f,0x1ff},
+	{0x1115f,0x1ff},
+	{0x1205f,0x1ff},
+	{0x1215f,0x1ff},
+	{0x1305f,0x1ff},
+	{0x1315f,0x1ff},
+	{0x11005f,0x1ff},
+	{0x11015f,0x1ff},
+	{0x11105f,0x1ff},
+	{0x11115f,0x1ff},
+	{0x11205f,0x1ff},
+	{0x11215f,0x1ff},
+	{0x11305f,0x1ff},
+	{0x11315f,0x1ff},
+	{0x21005f,0x1ff},
+	{0x21015f,0x1ff},
+	{0x21105f,0x1ff},
+	{0x21115f,0x1ff},
+	{0x21205f,0x1ff},
+	{0x21215f,0x1ff},
+	{0x21305f,0x1ff},
+	{0x21315f,0x1ff},
+	{0x55,0x1ff},
+	{0x1055,0x1ff},
+	{0x2055,0x1ff},
+	{0x3055,0x1ff},
+	{0x4055,0x1ff},
+	{0x5055,0x1ff},
+	{0x6055,0x1ff},
+	{0x7055,0x1ff},
+	{0x8055,0x1ff},
+	{0x9055,0x1ff},
+	{0x200c5,0xa},
+	{0x1200c5,0x7},
+	{0x2200c5,0x7},
+	{0x2002e,0x2},
+	{0x12002e,0x2},
+	{0x22002e,0x2},
+	{0x90204,0x0},
+	{0x190204,0x0},
+	{0x290204,0x0},
+	{0x20024,0x1ab},
+	{0x2003a,0x0},
+	{0x120024,0x1ab},
+	{0x2003a,0x0},
+	{0x220024,0x1ab},
+	{0x2003a,0x0},
+	{0x20056,0x2},
+	{0x120056,0xa},
+	{0x220056,0xa},
+	{0x1004d,0xe00},
+	{0x1014d,0xe00},
+	{0x1104d,0xe00},
+	{0x1114d,0xe00},
+	{0x1204d,0xe00},
+	{0x1214d,0xe00},
+	{0x1304d,0xe00},
+	{0x1314d,0xe00},
+	{0x11004d,0xe00},
+	{0x11014d,0xe00},
+	{0x11104d,0xe00},
+	{0x11114d,0xe00},
+	{0x11204d,0xe00},
+	{0x11214d,0xe00},
+	{0x11304d,0xe00},
+	{0x11314d,0xe00},
+	{0x21004d,0xe00},
+	{0x21014d,0xe00},
+	{0x21104d,0xe00},
+	{0x21114d,0xe00},
+	{0x21204d,0xe00},
+	{0x21214d,0xe00},
+	{0x21304d,0xe00},
+	{0x21314d,0xe00},
+	{0x10049,0xeba},
+	{0x10149,0xeba},
+	{0x11049,0xeba},
+	{0x11149,0xeba},
+	{0x12049,0xeba},
+	{0x12149,0xeba},
+	{0x13049,0xeba},
+	{0x13149,0xeba},
+	{0x110049,0xeba},
+	{0x110149,0xeba},
+	{0x111049,0xeba},
+	{0x111149,0xeba},
+	{0x112049,0xeba},
+	{0x112149,0xeba},
+	{0x113049,0xeba},
+	{0x113149,0xeba},
+	{0x210049,0xeba},
+	{0x210149,0xeba},
+	{0x211049,0xeba},
+	{0x211149,0xeba},
+	{0x212049,0xeba},
+	{0x212149,0xeba},
+	{0x213049,0xeba},
+	{0x213149,0xeba},
+	{0x43,0x63},
+	{0x1043,0x63},
+	{0x2043,0x63},
+	{0x3043,0x63},
+	{0x4043,0x63},
+	{0x5043,0x63},
+	{0x6043,0x63},
+	{0x7043,0x63},
+	{0x8043,0x63},
+	{0x9043,0x63},
+	{0x20018,0x3},
+	{0x20075,0x4},
+	{0x20050,0x0},
+	{0x20008,0x258},
+	{0x120008,0x64},
+	{0x220008,0x19},
+	{0x20088,0x9},
+	{0x200b2,0xdc},
+	{0x10043,0x5a1},
+	{0x10143,0x5a1},
+	{0x11043,0x5a1},
+	{0x11143,0x5a1},
+	{0x12043,0x5a1},
+	{0x12143,0x5a1},
+	{0x13043,0x5a1},
+	{0x13143,0x5a1},
+	{0x1200b2,0xdc},
+	{0x110043,0x5a1},
+	{0x110143,0x5a1},
+	{0x111043,0x5a1},
+	{0x111143,0x5a1},
+	{0x112043,0x5a1},
+	{0x112143,0x5a1},
+	{0x113043,0x5a1},
+	{0x113143,0x5a1},
+	{0x2200b2,0xdc},
+	{0x210043,0x5a1},
+	{0x210143,0x5a1},
+	{0x211043,0x5a1},
+	{0x211143,0x5a1},
+	{0x212043,0x5a1},
+	{0x212143,0x5a1},
+	{0x213043,0x5a1},
+	{0x213143,0x5a1},
+	{0x200fa,0x1},
+	{0x1200fa,0x1},
+	{0x2200fa,0x1},
+	{0x20019,0x1},
+	{0x120019,0x1},
+	{0x220019,0x1},
+	{0x200f0,0x660},
+	{0x200f1,0x0},
+	{0x200f2,0x4444},
+	{0x200f3,0x8888},
+	{0x200f4,0x5665},
+	{0x200f5,0x0},
+	{0x200f6,0x0},
+	{0x200f7,0xf000},
+	{0x20025,0x0},
+	{0x2002d,0x0},
+	{0x12002d,0x0},
+	{0x22002d,0x0},
+	{0x200c7,0x21},
+	{0x1200c7,0x21},
+	{0x2200c7,0x21},
+	{0x200ca,0x24},
+	{0x1200ca,0x24},
+	{0x2200ca,0x24},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg_1g_2ch1cs15r10cx32[] = {
+	{0xd0000, 0x0},
+	{0x54003,0x960},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x131f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x24c4},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x24c4},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xc400},
+	{0x54033,0x3124},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0xc400},
+	{0x54039,0x3124},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg_1g_2ch1cs15r10cx32[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x101},
+	{0x54003,0x190},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x84},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x84},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0x8400},
+	{0x54033,0x3100},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0x8400},
+	{0x54039,0x3100},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg_1g_2ch1cs15r10cx32[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x102},
+	{0x54003,0x64},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x84},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x84},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0x8400},
+	{0x54033,0x3100},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0x8400},
+	{0x54039,0x3100},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32[] = {
+	{0xd0000, 0x0},
+	{0x54003,0x960},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x61},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400f,0x100},
+	{0x54010,0x1f7f},
+	{0x54012,0x110},
+	{0x54019,0x24c4},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x24c4},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xc400},
+	{0x54033,0x3124},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0xc400},
+	{0x54039,0x3124},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000,0x10},
+	{0x90001,0x400},
+	{0x90002,0x10e},
+	{0x90003,0x0},
+	{0x90004,0x0},
+	{0x90005,0x8},
+	{0x90029,0xb},
+	{0x9002a,0x480},
+	{0x9002b,0x109},
+	{0x9002c,0x8},
+	{0x9002d,0x448},
+	{0x9002e,0x139},
+	{0x9002f,0x8},
+	{0x90030,0x478},
+	{0x90031,0x109},
+	{0x90032,0x0},
+	{0x90033,0xe8},
+	{0x90034,0x109},
+	{0x90035,0x2},
+	{0x90036,0x10},
+	{0x90037,0x139},
+	{0x90038,0xf},
+	{0x90039,0x7c0},
+	{0x9003a,0x139},
+	{0x9003b,0x44},
+	{0x9003c,0x630},
+	{0x9003d,0x159},
+	{0x9003e,0x14f},
+	{0x9003f,0x630},
+	{0x90040,0x159},
+	{0x90041,0x47},
+	{0x90042,0x630},
+	{0x90043,0x149},
+	{0x90044,0x4f},
+	{0x90045,0x630},
+	{0x90046,0x179},
+	{0x90047,0x8},
+	{0x90048,0xe0},
+	{0x90049,0x109},
+	{0x9004a,0x0},
+	{0x9004b,0x7c8},
+	{0x9004c,0x109},
+	{0x9004d,0x0},
+	{0x9004e,0x1},
+	{0x9004f,0x8},
+	{0x90050,0x0},
+	{0x90051,0x45a},
+	{0x90052,0x9},
+	{0x90053,0x0},
+	{0x90054,0x448},
+	{0x90055,0x109},
+	{0x90056,0x40},
+	{0x90057,0x630},
+	{0x90058,0x179},
+	{0x90059,0x1},
+	{0x9005a,0x618},
+	{0x9005b,0x109},
+	{0x9005c,0x40c0},
+	{0x9005d,0x630},
+	{0x9005e,0x149},
+	{0x9005f,0x8},
+	{0x90060,0x4},
+	{0x90061,0x48},
+	{0x90062,0x4040},
+	{0x90063,0x630},
+	{0x90064,0x149},
+	{0x90065,0x0},
+	{0x90066,0x4},
+	{0x90067,0x48},
+	{0x90068,0x40},
+	{0x90069,0x630},
+	{0x9006a,0x149},
+	{0x9006b,0x10},
+	{0x9006c,0x4},
+	{0x9006d,0x18},
+	{0x9006e,0x0},
+	{0x9006f,0x4},
+	{0x90070,0x78},
+	{0x90071,0x549},
+	{0x90072,0x630},
+	{0x90073,0x159},
+	{0x90074,0xd49},
+	{0x90075,0x630},
+	{0x90076,0x159},
+	{0x90077,0x94a},
+	{0x90078,0x630},
+	{0x90079,0x159},
+	{0x9007a,0x441},
+	{0x9007b,0x630},
+	{0x9007c,0x149},
+	{0x9007d,0x42},
+	{0x9007e,0x630},
+	{0x9007f,0x149},
+	{0x90080,0x1},
+	{0x90081,0x630},
+	{0x90082,0x149},
+	{0x90083,0x0},
+	{0x90084,0xe0},
+	{0x90085,0x109},
+	{0x90086,0xa},
+	{0x90087,0x10},
+	{0x90088,0x109},
+	{0x90089,0x9},
+	{0x9008a,0x3c0},
+	{0x9008b,0x149},
+	{0x9008c,0x9},
+	{0x9008d,0x3c0},
+	{0x9008e,0x159},
+	{0x9008f,0x18},
+	{0x90090,0x10},
+	{0x90091,0x109},
+	{0x90092,0x0},
+	{0x90093,0x3c0},
+	{0x90094,0x109},
+	{0x90095,0x18},
+	{0x90096,0x4},
+	{0x90097,0x48},
+	{0x90098,0x18},
+	{0x90099,0x4},
+	{0x9009a,0x58},
+	{0x9009b,0xa},
+	{0x9009c,0x10},
+	{0x9009d,0x109},
+	{0x9009e,0x2},
+	{0x9009f,0x10},
+	{0x900a0,0x109},
+	{0x900a1,0x5},
+	{0x900a2,0x7c0},
+	{0x900a3,0x109},
+	{0x900a4,0x10},
+	{0x900a5,0x10},
+	{0x900a6,0x109},
+	{0x40000,0x811},
+	{0x40020,0x880},
+	{0x40040,0x0},
+	{0x40060,0x0},
+	{0x40001,0x4008},
+	{0x40021,0x83},
+	{0x40041,0x4f},
+	{0x40061,0x0},
+	{0x40002,0x4040},
+	{0x40022,0x83},
+	{0x40042,0x51},
+	{0x40062,0x0},
+	{0x40003,0x811},
+	{0x40023,0x880},
+	{0x40043,0x0},
+	{0x40063,0x0},
+	{0x40004,0x720},
+	{0x40024,0xf},
+	{0x40044,0x1740},
+	{0x40064,0x0},
+	{0x40005,0x16},
+	{0x40025,0x83},
+	{0x40045,0x4b},
+	{0x40065,0x0},
+	{0x40006,0x716},
+	{0x40026,0xf},
+	{0x40046,0x2001},
+	{0x40066,0x0},
+	{0x40007,0x716},
+	{0x40027,0xf},
+	{0x40047,0x2800},
+	{0x40067,0x0},
+	{0x40008,0x716},
+	{0x40028,0xf},
+	{0x40048,0xf00},
+	{0x40068,0x0},
+	{0x40009,0x720},
+	{0x40029,0xf},
+	{0x40049,0x1400},
+	{0x40069,0x0},
+	{0x4000a,0xe08},
+	{0x4002a,0xc15},
+	{0x4004a,0x0},
+	{0x4006a,0x0},
+	{0x4000b,0x623},
+	{0x4002b,0x15},
+	{0x4004b,0x0},
+	{0x4006b,0x0},
+	{0x4000c,0x4028},
+	{0x4002c,0x80},
+	{0x4004c,0x0},
+	{0x4006c,0x0},
+	{0x4000d,0xe08},
+	{0x4002d,0xc1a},
+	{0x4004d,0x0},
+	{0x4006d,0x0},
+	{0x4000e,0x623},
+	{0x4002e,0x1a},
+	{0x4004e,0x0},
+	{0x4006e,0x0},
+	{0x4000f,0x4040},
+	{0x4002f,0x80},
+	{0x4004f,0x0},
+	{0x4006f,0x0},
+	{0x40010,0x2604},
+	{0x40030,0x15},
+	{0x40050,0x0},
+	{0x40070,0x0},
+	{0x40011,0x708},
+	{0x40031,0x5},
+	{0x40051,0x0},
+	{0x40071,0x2002},
+	{0x40012,0x8},
+	{0x40032,0x80},
+	{0x40052,0x0},
+	{0x40072,0x0},
+	{0x40013,0x2604},
+	{0x40033,0x1a},
+	{0x40053,0x0},
+	{0x40073,0x0},
+	{0x40014,0x708},
+	{0x40034,0xa},
+	{0x40054,0x0},
+	{0x40074,0x2002},
+	{0x40015,0x4040},
+	{0x40035,0x80},
+	{0x40055,0x0},
+	{0x40075,0x0},
+	{0x40016,0x60a},
+	{0x40036,0x15},
+	{0x40056,0x1200},
+	{0x40076,0x0},
+	{0x40017,0x61a},
+	{0x40037,0x15},
+	{0x40057,0x1300},
+	{0x40077,0x0},
+	{0x40018,0x60a},
+	{0x40038,0x1a},
+	{0x40058,0x1200},
+	{0x40078,0x0},
+	{0x40019,0x642},
+	{0x40039,0x1a},
+	{0x40059,0x1300},
+	{0x40079,0x0},
+	{0x4001a,0x4808},
+	{0x4003a,0x880},
+	{0x4005a,0x0},
+	{0x4007a,0x0},
+	{0x900a7,0x0},
+	{0x900a8,0x790},
+	{0x900a9,0x11a},
+	{0x900aa,0x8},
+	{0x900ab,0x7aa},
+	{0x900ac,0x2a},
+	{0x900ad,0x10},
+	{0x900ae,0x7b2},
+	{0x900af,0x2a},
+	{0x900b0,0x0},
+	{0x900b1,0x7c8},
+	{0x900b2,0x109},
+	{0x900b3,0x10},
+	{0x900b4,0x2a8},
+	{0x900b5,0x129},
+	{0x900b6,0x8},
+	{0x900b7,0x370},
+	{0x900b8,0x129},
+	{0x900b9,0xa},
+	{0x900ba,0x3c8},
+	{0x900bb,0x1a9},
+	{0x900bc,0xc},
+	{0x900bd,0x408},
+	{0x900be,0x199},
+	{0x900bf,0x14},
+	{0x900c0,0x790},
+	{0x900c1,0x11a},
+	{0x900c2,0x8},
+	{0x900c3,0x4},
+	{0x900c4,0x18},
+	{0x900c5,0xe},
+	{0x900c6,0x408},
+	{0x900c7,0x199},
+	{0x900c8,0x8},
+	{0x900c9,0x8568},
+	{0x900ca,0x108},
+	{0x900cb,0x18},
+	{0x900cc,0x790},
+	{0x900cd,0x16a},
+	{0x900ce,0x8},
+	{0x900cf,0x1d8},
+	{0x900d0,0x169},
+	{0x900d1,0x10},
+	{0x900d2,0x8558},
+	{0x900d3,0x168},
+	{0x900d4,0x70},
+	{0x900d5,0x788},
+	{0x900d6,0x16a},
+	{0x900d7,0x1ff8},
+	{0x900d8,0x85a8},
+	{0x900d9,0x1e8},
+	{0x900da,0x50},
+	{0x900db,0x798},
+	{0x900dc,0x16a},
+	{0x900dd,0x60},
+	{0x900de,0x7a0},
+	{0x900df,0x16a},
+	{0x900e0,0x8},
+	{0x900e1,0x8310},
+	{0x900e2,0x168},
+	{0x900e3,0x8},
+	{0x900e4,0xa310},
+	{0x900e5,0x168},
+	{0x900e6,0xa},
+	{0x900e7,0x408},
+	{0x900e8,0x169},
+	{0x900e9,0x6e},
+	{0x900ea,0x0},
+	{0x900eb,0x68},
+	{0x900ec,0x0},
+	{0x900ed,0x408},
+	{0x900ee,0x169},
+	{0x900ef,0x0},
+	{0x900f0,0x8310},
+	{0x900f1,0x168},
+	{0x900f2,0x0},
+	{0x900f3,0xa310},
+	{0x900f4,0x168},
+	{0x900f5,0x1ff8},
+	{0x900f6,0x85a8},
+	{0x900f7,0x1e8},
+	{0x900f8,0x68},
+	{0x900f9,0x798},
+	{0x900fa,0x16a},
+	{0x900fb,0x78},
+	{0x900fc,0x7a0},
+	{0x900fd,0x16a},
+	{0x900fe,0x68},
+	{0x900ff,0x790},
+	{0x90100,0x16a},
+	{0x90101,0x8},
+	{0x90102,0x8b10},
+	{0x90103,0x168},
+	{0x90104,0x8},
+	{0x90105,0xab10},
+	{0x90106,0x168},
+	{0x90107,0xa},
+	{0x90108,0x408},
+	{0x90109,0x169},
+	{0x9010a,0x58},
+	{0x9010b,0x0},
+	{0x9010c,0x68},
+	{0x9010d,0x0},
+	{0x9010e,0x408},
+	{0x9010f,0x169},
+	{0x90110,0x0},
+	{0x90111,0x8b10},
+	{0x90112,0x168},
+	{0x90113,0x0},
+	{0x90114,0xab10},
+	{0x90115,0x168},
+	{0x90116,0x0},
+	{0x90117,0x1d8},
+	{0x90118,0x169},
+	{0x90119,0x80},
+	{0x9011a,0x790},
+	{0x9011b,0x16a},
+	{0x9011c,0x18},
+	{0x9011d,0x7aa},
+	{0x9011e,0x6a},
+	{0x9011f,0xa},
+	{0x90120,0x0},
+	{0x90121,0x1e9},
+	{0x90122,0x8},
+	{0x90123,0x8080},
+	{0x90124,0x108},
+	{0x90125,0xf},
+	{0x90126,0x408},
+	{0x90127,0x169},
+	{0x90128,0xc},
+	{0x90129,0x0},
+	{0x9012a,0x68},
+	{0x9012b,0x9},
+	{0x9012c,0x0},
+	{0x9012d,0x1a9},
+	{0x9012e,0x0},
+	{0x9012f,0x408},
+	{0x90130,0x169},
+	{0x90131,0x0},
+	{0x90132,0x8080},
+	{0x90133,0x108},
+	{0x90134,0x8},
+	{0x90135,0x7aa},
+	{0x90136,0x6a},
+	{0x90137,0x0},
+	{0x90138,0x8568},
+	{0x90139,0x108},
+	{0x9013a,0xb7},
+	{0x9013b,0x790},
+	{0x9013c,0x16a},
+	{0x9013d,0x1f},
+	{0x9013e,0x0},
+	{0x9013f,0x68},
+	{0x90140,0x8},
+	{0x90141,0x8558},
+	{0x90142,0x168},
+	{0x90143,0xf},
+	{0x90144,0x408},
+	{0x90145,0x169},
+	{0x90146,0xc},
+	{0x90147,0x0},
+	{0x90148,0x68},
+	{0x90149,0x0},
+	{0x9014a,0x408},
+	{0x9014b,0x169},
+	{0x9014c,0x0},
+	{0x9014d,0x8558},
+	{0x9014e,0x168},
+	{0x9014f,0x8},
+	{0x90150,0x3c8},
+	{0x90151,0x1a9},
+	{0x90152,0x3},
+	{0x90153,0x370},
+	{0x90154,0x129},
+	{0x90155,0x20},
+	{0x90156,0x2aa},
+	{0x90157,0x9},
+	{0x90158,0x0},
+	{0x90159,0x400},
+	{0x9015a,0x10e},
+	{0x9015b,0x8},
+	{0x9015c,0xe8},
+	{0x9015d,0x109},
+	{0x9015e,0x0},
+	{0x9015f,0x8140},
+	{0x90160,0x10c},
+	{0x90161,0x10},
+	{0x90162,0x8138},
+	{0x90163,0x10c},
+	{0x90164,0x8},
+	{0x90165,0x7c8},
+	{0x90166,0x101},
+	{0x90167,0x8},
+	{0x90168,0x0},
+	{0x90169,0x8},
+	{0x9016a,0x8},
+	{0x9016b,0x448},
+	{0x9016c,0x109},
+	{0x9016d,0xf},
+	{0x9016e,0x7c0},
+	{0x9016f,0x109},
+	{0x90170,0x0},
+	{0x90171,0xe8},
+	{0x90172,0x109},
+	{0x90173,0x47},
+	{0x90174,0x630},
+	{0x90175,0x109},
+	{0x90176,0x8},
+	{0x90177,0x618},
+	{0x90178,0x109},
+	{0x90179,0x8},
+	{0x9017a,0xe0},
+	{0x9017b,0x109},
+	{0x9017c,0x0},
+	{0x9017d,0x7c8},
+	{0x9017e,0x109},
+	{0x9017f,0x8},
+	{0x90180,0x8140},
+	{0x90181,0x10c},
+	{0x90182,0x0},
+	{0x90183,0x1},
+	{0x90184,0x8},
+	{0x90185,0x8},
+	{0x90186,0x4},
+	{0x90187,0x8},
+	{0x90188,0x8},
+	{0x90189,0x7c8},
+	{0x9018a,0x101},
+	{0x90006,0x0},
+	{0x90007,0x0},
+	{0x90008,0x8},
+	{0x90009,0x0},
+	{0x9000a,0x0},
+	{0x9000b,0x0},
+	{0xd00e7,0x400},
+	{0x90017,0x0},
+	{0x9001f,0x2a},
+	{0x90026,0x6a},
+	{0x400d0,0x0},
+	{0x400d1,0x101},
+	{0x400d2,0x105},
+	{0x400d3,0x107},
+	{0x400d4,0x10f},
+	{0x400d5,0x202},
+	{0x400d6,0x20a},
+	{0x400d7,0x20b},
+	{0x2003a,0x2},
+	{0x2000b,0x4b},
+	{0x2000c,0x96},
+	{0x2000d,0x5dc},
+	{0x2000e,0x2c},
+	{0x12000b,0xc},
+	{0x12000c,0x19},
+	{0x12000d,0xfa},
+	{0x12000e,0x10},
+	{0x22000b,0x3},
+	{0x22000c,0x6},
+	{0x22000d,0x3e},
+	{0x22000e,0x10},
+	{0x9000c,0x0},
+	{0x9000d,0x173},
+	{0x9000e,0x60},
+	{0x9000f,0x6110},
+	{0x90010,0x2152},
+	{0x90011,0xdfbd},
+	{0x90012,0x60},
+	{0x90013,0x6152},
+	{0x20010,0x5a},
+	{0x20011,0x3},
+	{0x120010,0x5a},
+	{0x120011,0x3},
+	{0x220010,0x5a},
+	{0x220011,0x3},
+	{0x40080,0xe0},
+	{0x40081,0x12},
+	{0x40082,0xe0},
+	{0x40083,0x12},
+	{0x40084,0xe0},
+	{0x40085,0x12},
+	{0x140080,0xe0},
+	{0x140081,0x12},
+	{0x140082,0xe0},
+	{0x140083,0x12},
+	{0x140084,0xe0},
+	{0x140085,0x12},
+	{0x240080,0xe0},
+	{0x240081,0x12},
+	{0x240082,0xe0},
+	{0x240083,0x12},
+	{0x240084,0xe0},
+	{0x240085,0x12},
+	{0x400fd,0xf},
+	{0x10011,0x1},
+	{0x10012,0x1},
+	{0x10013,0x180},
+	{0x10018,0x1},
+	{0x10002,0x6209},
+	{0x100b2,0x1},
+	{0x101b4,0x1},
+	{0x102b4,0x1},
+	{0x103b4,0x1},
+	{0x104b4,0x1},
+	{0x105b4,0x1},
+	{0x106b4,0x1},
+	{0x107b4,0x1},
+	{0x108b4,0x1},
+	{0x11011,0x1},
+	{0x11012,0x1},
+	{0x11013,0x180},
+	{0x11018,0x1},
+	{0x11002,0x6209},
+	{0x110b2,0x1},
+	{0x111b4,0x1},
+	{0x112b4,0x1},
+	{0x113b4,0x1},
+	{0x114b4,0x1},
+	{0x115b4,0x1},
+	{0x116b4,0x1},
+	{0x117b4,0x1},
+	{0x118b4,0x1},
+	{0x12011,0x1},
+	{0x12012,0x1},
+	{0x12013,0x180},
+	{0x12018,0x1},
+	{0x12002,0x6209},
+	{0x120b2,0x1},
+	{0x121b4,0x1},
+	{0x122b4,0x1},
+	{0x123b4,0x1},
+	{0x124b4,0x1},
+	{0x125b4,0x1},
+	{0x126b4,0x1},
+	{0x127b4,0x1},
+	{0x128b4,0x1},
+	{0x13011,0x1},
+	{0x13012,0x1},
+	{0x13013,0x180},
+	{0x13018,0x1},
+	{0x13002,0x6209},
+	{0x130b2,0x1},
+	{0x131b4,0x1},
+	{0x132b4,0x1},
+	{0x133b4,0x1},
+	{0x134b4,0x1},
+	{0x135b4,0x1},
+	{0x136b4,0x1},
+	{0x137b4,0x1},
+	{0x138b4,0x1},
+	{0x2003a,0x2},
+	{0xc0080,0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg_1g_2ch1cs15r10cx32[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg_1g_2ch1cs15r10cx32,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1g_2ch1cs15r10cx32),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg_1g_2ch1cs15r10cx32,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1g_2ch1cs15r10cx32),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg_1g_2ch1cs15r10cx32,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1g_2ch1cs15r10cx32),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info innocomm_wb15_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg_1g_2ch1cs15r10cx32,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1g_2ch1cs15r10cx32),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg_1g_2ch1cs15r10cx32,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1g_2ch1cs15r10cx32),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 400, 100, },
+};
diff --git a/arch/arm/boards/kamstrup-mx7-concentrator/Makefile b/arch/arm/boards/kamstrup-mx7-concentrator/Makefile
index 7ab9f52747..458f520900 100644
--- a/arch/arm/boards/kamstrup-mx7-concentrator/Makefile
+++ b/arch/arm/boards/kamstrup-mx7-concentrator/Makefile
@@ -1 +1,3 @@
-lwl-y += lowlevel.o
\ No newline at end of file
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/kamstrup-mx7-concentrator/flash-header-tqma7d.imxcfg b/arch/arm/boards/kamstrup-mx7-concentrator/flash-header-tqma7d.imxcfg
index 4b36324110..12e0754912 100644
--- a/arch/arm/boards/kamstrup-mx7-concentrator/flash-header-tqma7d.imxcfg
+++ b/arch/arm/boards/kamstrup-mx7-concentrator/flash-header-tqma7d.imxcfg
@@ -1,8 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx7
 loadaddr 0xbfbff000
 ivtofs 0x400
 
-#include <mach/imx7-ddr-regs.h>
+#include <mach/imx/imx7-ddr-regs.h>
 
 wm 32 0x30340004 0x4F400005 /* IOMUXC_GPR_GPR1 */
 /* Clear then set bit30 to ensure exit from DDR retention */
diff --git a/arch/arm/boards/kamstrup-mx7-concentrator/lowlevel.c b/arch/arm/boards/kamstrup-mx7-concentrator/lowlevel.c
index 8cd6d67f7e..e1ba327251 100644
--- a/arch/arm/boards/kamstrup-mx7-concentrator/lowlevel.c
+++ b/arch/arm/boards/kamstrup-mx7-concentrator/lowlevel.c
@@ -1,21 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <io.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx7-ccm-regs.h>
-#include <mach/iomux-mx7.h>
-#include <mach/debug_ll.h>
+#include <mach/imx/imx7-ccm-regs.h>
+#include <mach/imx/iomux-mx7.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
-#include <mach/esdctl.h>
+#include <mach/imx/esdctl.h>
 
 extern char __dtb_z_imx7d_flex_concentrator_mfg_start[];
 
 static inline void setup_uart(void)
 {
-	imx7_early_setup_uart_clock();
+	imx7_early_setup_uart_clock(4);
 
 	imx7_setup_pad(MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX);
 
diff --git a/arch/arm/boards/karo-qsxp-ml81/Makefile b/arch/arm/boards/karo-qsxp-ml81/Makefile
new file mode 100644
index 0000000000..10abebc539
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o lpddr4-timing.o
+obj-y += board.o
diff --git a/arch/arm/boards/karo-qsxp-ml81/board.c b/arch/arm/boards/karo-qsxp-ml81/board.c
new file mode 100644
index 0000000000..e9e3d46bf1
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/board.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <mach/imx/bbu.h>
+
+static int karo_qsxp_ml81_probe(struct device *dev)
+{
+	int emmc_bbu_flag = 0;
+
+	if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 2) {
+		of_device_enable_path("/chosen/environment-emmc");
+		emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+
+	return 0;
+}
+
+static const struct of_device_id karo_qsxp_ml81_of_match[] = {
+	{ .compatible = "karo,imx8mp-qsxp-ml81-qsbase4" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(karo_qsxp_ml81_of_match);
+
+static struct driver karo_qsxp_ml81_board_driver = {
+	.name = "board-karo-qsxp-ml81",
+	.probe = karo_qsxp_ml81_probe,
+	.of_compatible = DRV_OF_COMPAT(karo_qsxp_ml81_of_match),
+};
+coredevice_platform_driver(karo_qsxp_ml81_board_driver);
diff --git a/arch/arm/boards/karo-qsxp-ml81/flash-header-karo-qsxp-ml81.imxcfg b/arch/arm/boards/karo-qsxp-ml81/flash-header-karo-qsxp-ml81.imxcfg
new file mode 100644
index 0000000000..da0892e52d
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/flash-header-karo-qsxp-ml81.imxcfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mp
+
+loadaddr 0x00920000
+max_load_size 0x3f000
+ivtofs 0x0
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/karo-qsxp-ml81/lowlevel.c b/arch/arm/boards/karo-qsxp-ml81/lowlevel.c
new file mode 100644
index 0000000000..506a9c9930
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/lowlevel.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <asm/barebox-arm.h>
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <mach/imx/xload.h>
+#include <mfd/pca9450.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <soc/imx8m/ddr.h>
+
+#include "lowlevel.h"
+
+extern char __dtb_z_imx8mp_karo_qsxp_ml81_qsbase4_start[];
+
+#define UART_PAD_CTRL	MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+				     MX8MP_PAD_CTL_FSEL)
+
+#define I2C_PAD_CTRL	MUX_PAD_CTRL(MX8MP_PAD_CTL_PE | \
+				     MX8MP_PAD_CTL_HYS | \
+				     MX8MP_PAD_CTL_PUE | \
+				     MX8MP_PAD_CTL_DSE6)
+
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+
+	putc_ll('>');
+}
+
+#define pca9450_mV_to_reg(mV)	(((mV) - 600) * 10 / 125)
+#define pca9450_reg_to_mV(val)	(((val) * 125 / 10) + 600)
+
+#define VDD_SOC_VAL	pca9450_mV_to_reg(950)
+#define VDD_SOC_SLP_VAL	pca9450_mV_to_reg(850)
+#define VDD_ARM_VAL	pca9450_mV_to_reg(950)
+#define VDD_DRAM_VAL	pca9450_mV_to_reg(950)
+
+static struct pmic_config pca9450_cfg[] = {
+	{ PCA9450_BUCK123_DVS, 0x29 },
+	{ PCA9450_BUCK1OUT_DVS0, VDD_SOC_VAL },
+	{ PCA9450_BUCK1OUT_DVS1, VDD_SOC_SLP_VAL },
+	{ PCA9450_BUCK2OUT_DVS0, VDD_ARM_VAL },
+	{ PCA9450_BUCK3OUT_DVS0, VDD_DRAM_VAL },
+	{ PCA9450_BUCK1CTRL, 0x59 },
+	{ PCA9450_RESET_CTRL, 0xA1 },
+};
+
+static void power_init_board(void)
+{
+	struct pbl_i2c *i2c;
+
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
+
+	pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+}
+
+ENTRY_FUNCTION(start_karo_qsxp_ml81, r0, r1, r2)
+{
+	imx8mp_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	setup_uart();
+
+	/*
+	 * If we are in EL3 we are running for the first time out of OCRAM,
+	 * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A
+	 * will then jump to DRAM in EL2
+	 */
+	if (current_el() == 3) {
+		imx8mp_early_clock_init();
+
+		power_init_board();
+
+		imx8mp_ddr_init(&karo_qsxp_ml81_dram_timing, DRAM_TYPE_LPDDR4);
+
+		imx8mp_load_and_start_image_via_tfa();
+	}
+
+	/* Standard entry we hit once we initialized both DDR and ATF */
+	imx8mp_barebox_entry(__dtb_z_imx8mp_karo_qsxp_ml81_qsbase4_start);
+}
diff --git a/arch/arm/boards/karo-qsxp-ml81/lowlevel.h b/arch/arm/boards/karo-qsxp-ml81/lowlevel.h
new file mode 100644
index 0000000000..37e5269653
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/lowlevel.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef KARO_QSXP_ML81_LOWLEVEL_H_
+#define KARO_QSXP_ML81_LOWLEVEL_H_
+
+extern struct dram_timing_info karo_qsxp_ml81_dram_timing;
+
+#endif
diff --git a/arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c b/arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c
new file mode 100644
index 0000000000..e151bcf01a
--- /dev/null
+++ b/arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c
@@ -0,0 +1,872 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+#include <soc/imx8m/lpddr4_define.h>
+
+#include "lowlevel.h"
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x1203 },
+	{ 0x3d400024, 0x186a000 },
+	{ 0x3d400064, 0x6100e0 },
+	{ 0x3d400070, 0x7027f90 },
+	{ 0x3d400074, 0x790 },
+	{ 0x3d4000d0, 0xc003061c },
+	{ 0x3d4000d4, 0x9e0000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x210000 },
+	{ 0x3d4000e8, 0x630048 },
+	{ 0x3d4000ec, 0x140025 },
+	{ 0x3d400100, 0x1a201b22 },
+	{ 0x3d400104, 0x60633 },
+	{ 0x3d40010c, 0xc0c000 },
+	{ 0x3d400110, 0xf04080f },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xe100002 },
+	{ 0x3d400138, 0xe6 },
+	{ 0x3d400144, 0xa00050 },
+	{ 0x3d400180, 0x3200018 },
+	{ 0x3d400184, 0x28061a8 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x1 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x5 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x2 },
+	{ 0x100a5, 0x4 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x7 },
+	{ 0x110a1, 0x6 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x5 },
+	{ 0x110a4, 0x4 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x1 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x4 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x2 },
+	{ 0x120a6, 0x6 },
+	{ 0x120a7, 0x7 },
+	{ 0x130a0, 0x1 },
+	{ 0x130a1, 0x6 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x7 },
+	{ 0x130a7, 0x0 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x2002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x20024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x1004d, 0x600 },
+	{ 0x1014d, 0x600 },
+	{ 0x1104d, 0x600 },
+	{ 0x1114d, 0x600 },
+	{ 0x1204d, 0x600 },
+	{ 0x1214d, 0x600 },
+	{ 0x1304d, 0x600 },
+	{ 0x1314d, 0x600 },
+	{ 0x10049, 0x69a },
+	{ 0x10149, 0x69a },
+	{ 0x11049, 0x69a },
+	{ 0x11149, 0x69a },
+	{ 0x12049, 0x69a },
+	{ 0x12149, 0x69a },
+	{ 0x13049, 0x69a },
+	{ 0x13149, 0x69a },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x200f0, 0x0 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x303c },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x21 },
+	{ 0x5401b, 0x4863 },
+	{ 0x5401c, 0x2500 },
+	{ 0x5401e, 0x14 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x21 },
+	{ 0x54021, 0x4863 },
+	{ 0x54022, 0x2500 },
+	{ 0x54024, 0x14 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x212d },
+	{ 0x54034, 0x6300 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x25 },
+	{ 0x54037, 0x1400 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x212d },
+	{ 0x5403a, 0x6300 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x25 },
+	{ 0x5403d, 0x1400 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x303c },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x21 },
+	{ 0x5401b, 0x4863 },
+	{ 0x5401c, 0x2500 },
+	{ 0x5401e, 0x14 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x21 },
+	{ 0x54021, 0x4863 },
+	{ 0x54022, 0x2500 },
+	{ 0x54024, 0x14 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x212d },
+	{ 0x54034, 0x6300 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x25 },
+	{ 0x54037, 0x1400 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x212d },
+	{ 0x5403a, 0x6300 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x25 },
+	{ 0x5403d, 0x1400 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x8 },
+	{ 0x90159, 0xe8 },
+	{ 0x9015a, 0x109 },
+	{ 0x9015b, 0x0 },
+	{ 0x9015c, 0x8140 },
+	{ 0x9015d, 0x10c },
+	{ 0x9015e, 0x10 },
+	{ 0x9015f, 0x8138 },
+	{ 0x90160, 0x104 },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0x448 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0xf },
+	{ 0x90165, 0x7c0 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0x0 },
+	{ 0x90168, 0xe8 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x47 },
+	{ 0x9016b, 0x630 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x618 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0xe0 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x0 },
+	{ 0x90174, 0x7c8 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x8140 },
+	{ 0x90178, 0x10c },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x478 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x1 },
+	{ 0x9017e, 0x8 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x4 },
+	{ 0x90181, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x68 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x384 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info karo_qsxp_ml81_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, },
+};
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 6086da53cc..f58767a7a3 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -9,20 +9,19 @@
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <environment.h>
-#include <mach/imx25-regs.h>
+#include <mach/imx/imx25-regs.h>
 #include <asm/armlinux.h>
 #include <asm/sections.h>
 #include <asm/barebox-arm.h>
 #include <io.h>
-#include <partition.h>
-#include <generated/mach-types.h>
-#include <mach/imx-nand.h>
-#include <mach/iomux-mx25.h>
-#include <mach/generic.h>
-#include <mach/iim.h>
+#include <asm/mach-types.h>
+#include <mach/imx/imx-nand.h>
+#include <mach/imx/iomux-mx25.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/iim.h>
 #include <linux/err.h>
-#include <mach/devices-imx25.h>
-#include <mach/bbu.h>
+#include <mach/imx/devices-imx25.h>
+#include <mach/imx/bbu.h>
 #include <asm/mmu.h>
 
 #define TX25_FEC_PWR_GPIO	IMX_GPIO_NR(4, 9)
diff --git a/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg b/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg
index 6f8eaf0fc5..0786017a85 100644
--- a/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg
+++ b/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 #
 # currently unused in barebox, but useful to generate
 # a imx-image to use with imx-usb-loader
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index f20c659d5d..d6658b535f 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -3,11 +3,11 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/imx25-regs.h>
-#include <mach/esdctl.h>
+#include <mach/imx/imx25-regs.h>
+#include <mach/imx/esdctl.h>
 #include <io.h>
 #include <linux/sizes.h>
-#include <mach/imx-nand.h>
+#include <mach/imx/imx-nand.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/system.h>
diff --git a/arch/arm/boards/karo-tx28/Makefile b/arch/arm/boards/karo-tx28/Makefile
index c7d7398cf3..b13ffc8f3c 100644
--- a/arch/arm/boards/karo-tx28/Makefile
+++ b/arch/arm/boards/karo-tx28/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += tx28.o
 obj-$(CONFIG_MACH_TX28STK5) += tx28-stk5.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/karo-tx28/lowlevel.c b/arch/arm/boards/karo-tx28/lowlevel.c
index 84cc681816..3be5f521e1 100644
--- a/arch/arm/boards/karo-tx28/lowlevel.c
+++ b/arch/arm/boards/karo-tx28/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define pr_fmt(fmt) "KARO TX28: " fmt
 #define DEBUG
 
@@ -5,17 +7,30 @@
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx28-regs.h>
-#include <mach/init.h>
+#include <mach/mxs/imx28-regs.h>
+#include <mach/mxs/init.h>
 #include <io.h>
 #include <debug_ll.h>
-#include <mach/iomux.h>
+#include <mach/mxs/iomux.h>
 #include <stmp-device.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
+
+static noinline void continue_imx_entry(size_t size)
+{
+	static struct barebox_arm_boarddata boarddata = {
+		.magic = BAREBOX_ARM_BOARDDATA_MAGIC,
+		.machine = MACH_TYPE_TX28,
+	};
+
+	barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata);
+}
 
 ENTRY_FUNCTION(start_barebox_karo_tx28, r0, r1, r2)
 {
-	barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, (void *)MACH_TYPE_TX28);
+	relocate_to_current_adr();
+	setup_c();
+
+	continue_imx_entry(SZ_128M);
 }
 
 static const uint32_t iomux_pads[] = {
diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c
index 56211d7a3a..d1fd526c00 100644
--- a/arch/arm/boards/karo-tx28/tx28-stk5.c
+++ b/arch/arm/boards/karo-tx28/tx28-stk5.c
@@ -14,13 +14,12 @@
 #include <asm/sections.h>
 #include <asm/barebox-arm.h>
 #include <linux/err.h>
-#include <mach/imx-regs.h>
-#include <mach/clock.h>
-#include <mach/mci.h>
-#include <mach/fb.h>
-#include <mach/ocotp.h>
-#include <mach/iomux.h>
-#include <generated/mach-types.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/mci.h>
+#include <mach/mxs/fb.h>
+#include <mach/mxs/ocotp.h>
+#include <mach/mxs/iomux.h>
+#include <asm/mach-types.h>
 
 #include "tx28.h"
 
diff --git a/arch/arm/boards/karo-tx28/tx28.c b/arch/arm/boards/karo-tx28/tx28.c
index 8bd2252410..ef3c42b5f6 100644
--- a/arch/arm/boards/karo-tx28/tx28.c
+++ b/arch/arm/boards/karo-tx28/tx28.c
@@ -9,10 +9,10 @@
 #include <asm/armlinux.h>
 #include <asm/barebox-arm.h>
 #include <io.h>
-#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
-#include <mach/devices.h>
-#include <mach/iomux.h>
+#include <asm/mach-types.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/devices.h>
+#include <mach/mxs/iomux.h>
 #include <asm/mmu.h>
 
 #include "tx28.h"
diff --git a/arch/arm/boards/karo-tx28/tx28.h b/arch/arm/boards/karo-tx28/tx28.h
index 5fb1e13412..2e14211b7a 100644
--- a/arch/arm/boards/karo-tx28/tx28.h
+++ b/arch/arm/boards/karo-tx28/tx28.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 void base_board_init(void);
 
diff --git a/arch/arm/boards/karo-tx53/Makefile b/arch/arm/boards/karo-tx53/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/karo-tx53/Makefile
+++ b/arch/arm/boards/karo-tx53/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c
index 738faf8f18..f5450def4c 100644
--- a/arch/arm/boards/karo-tx53/board.c
+++ b/arch/arm/boards/karo-tx53/board.c
@@ -10,21 +10,20 @@
 #include <init.h>
 #include <nand.h>
 #include <net.h>
-#include <partition.h>
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <mci.h>
 
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 
-#include <mach/imx53-regs.h>
-#include <mach/iomux-mx53.h>
-#include <mach/devices-imx53.h>
-#include <mach/generic.h>
-#include <mach/imx-nand.h>
-#include <mach/iim.h>
-#include <mach/imx5.h>
-#include <mach/bbu.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/iomux-mx53.h>
+#include <mach/imx/devices-imx53.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx-nand.h>
+#include <mach/imx/iim.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/bbu.h>
 
 #include <asm/armlinux.h>
 #include <io.h>
diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg
index 4bcb3b8b5e..158233cc86 100644
--- a/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg
+++ b/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x71000000
 soc imx53
 ivtofs 0x400
diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg
index a4e3fab9a3..d7da89beef 100644
--- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg
+++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x71000000
 soc imx53
 ivtofs 0x400
diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg
index 5b6b79f705..d516da3770 100644
--- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg
+++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x71000000
 soc imx53
 ivtofs 0x400
diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c
index 230f60ebd9..914ef69de9 100644
--- a/arch/arm/boards/karo-tx53/lowlevel.c
+++ b/arch/arm/boards/karo-tx53/lowlevel.c
@@ -1,11 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx5.h>
-#include <mach/imx53-regs.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 #include <asm/cache.h>
 
 extern char __dtb_imx53_tx53_xx30_start[];
diff --git a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
index 7e244edfd3..bd869ec29e 100644
--- a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
+++ b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
@@ -1,12 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 /* MDMISC	mirroring	interleaved (row/bank/col) */
 wm 32 MX6_MMDC_P0_MDMISC		0x00000742
-check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
 
 wm 32 MX6_MMDC_P0_MDSCR			0x00008000
-check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
 
 wm 32 MX6_MMDC_P0_MDCTL			0x831a0000
-check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
 
 wm 32 MX6_MMDC_P0_MDCFG0		0x3f435333
 wm 32 MX6_MMDC_P0_MDCFG1		0x926e8a63
@@ -34,7 +36,7 @@ wm 32 MX6_MMDC_P0_MDSCR			0x04008010
 wm 32 MX6_MMDC_P0_MDSCR			0x04008040
 
 wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xA1390001
-check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
 wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xA1380000
 
 wm 32 MX6_MMDC_P0_MPWLDECTRL0	0x001e001e
@@ -62,11 +64,11 @@ wm 32 MX6_MMDC_P1_MPWRDLCTL		0x40404040
 wm 32 MX6_MMDC_P0_MPMUR0		0x00000800
 
 wm 32 MX6_MMDC_P0_MPDGCTRL0		0x80000000
-check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
 wm 32 MX6_MMDC_P0_MPDGCTRL0		0x80000000
-check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
 wm 32 MX6_MMDC_P0_MPDGCTRL0		0x50800000
-check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x10001000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000
 
 wm 32 MX6_IOM_DRAM_SDQS0		0x00000030
 wm 32 MX6_IOM_DRAM_SDQS1		0x00000030
@@ -81,16 +83,16 @@ wm 32 MX6_MMDC_P0_MDSCR			0x04008050
 wm 32 MX6_MMDC_P0_MPRDDLHWCTL		0x00000030
 wm 32 MX6_MMDC_P1_MPRDDLHWCTL		0x00000030
 
-check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
-check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
 
 wm 32 MX6_MMDC_P0_MDSCR			0x04008050
 wm 32 MX6_MMDC_P0_MPWRDLHWCTL		0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
 
 wm 32 MX6_MMDC_P0_MDSCR			0x04008050
 wm 32 MX6_MMDC_P1_MPWRDLHWCTL		0x00000030
-check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR			0x00008033
 wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xa138002b
 wm 32 MX6_MMDC_P0_MDREF			0x00001800
@@ -98,4 +100,4 @@ wm 32 MX6_MMDC_P0_MAPSR			0x00001006
 wm 32 MX6_MMDC_P0_MDPDC			0x0002556d
 wm 32 MX6_MMDC_P1_MDPDC			0x0002556d
 wm 32 MX6_MMDC_P0_MDSCR			0x00000000
-check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/karo-tx6x/Makefile b/arch/arm/boards/karo-tx6x/Makefile
index 51b7c2d449..bfd7eed20a 100644
--- a/arch/arm/boards/karo-tx6x/Makefile
+++ b/arch/arm/boards/karo-tx6x/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 obj-y += pmic-ltc3676.o pmic-rn5t567.o pmic-rn5t618.o
diff --git a/arch/arm/boards/karo-tx6x/board.c b/arch/arm/boards/karo-tx6x/board.c
index 2a141be61a..f964ddefd1 100644
--- a/arch/arm/boards/karo-tx6x/board.c
+++ b/arch/arm/boards/karo-tx6x/board.c
@@ -16,8 +16,8 @@
 #include <linux/clk.h>
 #include <linux/kernel.h>
 #include <environment.h>
-#include <mach/bbu.h>
-#include <mach/imx6.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/imx6.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
 #include "pmic.h"
 
@@ -112,12 +112,12 @@ static int tx6x_devices_init(void)
 	if (sbmr1 & (1 << 7)) {
 		imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
 		of_device_enable_and_register_by_name("environment-nand");
-		of_device_enable_and_register_by_name("gpmi-nand@00112000");
+		of_device_enable_and_register_by_alias("nand");
 	} else {
 		imx6_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc3.boot0",
 						       BBU_HANDLER_FLAG_DEFAULT);
 		of_device_enable_and_register_by_name("environment-emmc");
-		of_device_enable_and_register_by_name("usdhc@0219c000");
+		of_device_enable_and_register_by_alias("mmc3");
 	}
 
 
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg
index 7d77f54f00..3d15238c20 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg
@@ -1,9 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 #include "ram-base.imxcfg"
 #include "1600mhz_4x128mx16.imxcfg"
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg
index eb63fa34d3..bfc9a80a3e 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg
@@ -1,9 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 wm 32 0x020e0158 0x00000016
 wm 32 0x020e0174 0x00000011
@@ -92,11 +94,10 @@ wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
 wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
 wm 32 MX6_MMDC_P0_MDSCR 0x00008000
 check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
 wm 32 MX6_MMDC_P0_MDCTL 0x83190000
-check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
 wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333
 wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8a63
 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db
@@ -117,7 +118,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001
 wm 32 MX6_MMDC_P0_MDSCR 0x04008010
 wm 32 MX6_MMDC_P0_MDSCR 0x04008040
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
-check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000
 wm 32 MX6_MMDC_P0_MDSCR 0x00048033
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
@@ -126,14 +127,14 @@ wm 32 MX6_IOM_DRAM_SDQS2 0x00000030
 wm 32 MX6_IOM_DRAM_SDQS3 0x00000030
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x00008033
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
 wm 32 MX6_MMDC_P0_MDREF 0x00001800
 wm 32 MX6_MMDC_P0_MAPSR 0x00001000
 wm 32 MX6_MMDC_P0_MDPDC 0x0002556d
 wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg
index e5a1ed2331..b05c4a186b 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 0x020e00a4 0x00000016
 wm 32 0x020e00c4 0x00000011
@@ -119,11 +121,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
 wm 32 MX6_MMDC_P0_MDSCR 0x00008000
-check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
 wm 32 MX6_MMDC_P0_MDCTL 0x831a0000
-check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
 wm 32 MX6_MMDC_P0_MDCFG0 0x545a79a4
 wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64
 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00dd
@@ -145,7 +147,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001
 wm 32 MX6_MMDC_P0_MDSCR 0x04008010
 wm 32 MX6_MMDC_P0_MDSCR 0x04008040
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
-check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000
 wm 32 MX6_MMDC_P0_MDSCR 0x00048033
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
@@ -159,19 +161,19 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
-check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x00008033
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
 wm 32 MX6_MMDC_P0_MDREF 0x00001800
 wm 32 MX6_MMDC_P0_MAPSR 0x00001000
 wm 32 MX6_MMDC_P0_MDPDC 0x00025576
 wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
 
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg
index 889416b849..bbb9e01022 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg
@@ -1,9 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 0x020e00a4 0x00000016
 wm 32 0x020e00c4 0x00000011
@@ -128,11 +130,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
 wm 32 MX6_MMDC_P0_MDSCR 0x00008000
-check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
 wm 32 MX6_MMDC_P0_MDCTL 0x841a0000
-check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
 wm 32 MX6_MMDC_P0_MDCFG0 0x898f78f4
 wm 32 MX6_MMDC_P0_MDCFG1 0xff328e64
 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db
@@ -155,7 +157,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001
 wm 32 MX6_MMDC_P0_MDSCR 0x04008010
 wm 32 MX6_MMDC_P0_MDSCR 0x04008040
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
-check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000
 wm 32 MX6_MMDC_P0_MDSCR 0x00048033
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
@@ -169,18 +171,18 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
-check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030
-check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x00008033
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
 wm 32 MX6_MMDC_P0_MDREF 0x00001800
 wm 32 MX6_MMDC_P0_MAPSR 0x00001000
 wm 32 MX6_MMDC_P0_MDPDC 0x00025576
 wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c
index a80862025a..082307626b 100644
--- a/arch/arm/boards/karo-tx6x/lowlevel.c
+++ b/arch/arm/boards/karo-tx6x/lowlevel.c
@@ -2,12 +2,13 @@
 // SPDX-FileCopyrightText: 2014 Steffen Trumtrar, Pengutronix
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <image-metadata.h>
-#include <mach/generic.h>
-#include <mach/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/esdctl.h>
 #include <linux/sizes.h>
 
 static inline void setup_uart(void)
diff --git a/arch/arm/boards/karo-tx6x/pmic.h b/arch/arm/boards/karo-tx6x/pmic.h
index 2427a52e50..5e5616e8c7 100644
--- a/arch/arm/boards/karo-tx6x/pmic.h
+++ b/arch/arm/boards/karo-tx6x/pmic.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <i2c/i2c.h>
 
diff --git a/arch/arm/boards/karo-tx6x/ram-base.imxcfg b/arch/arm/boards/karo-tx6x/ram-base.imxcfg
index e912fb0f2b..9f15806b55 100644
--- a/arch/arm/boards/karo-tx6x/ram-base.imxcfg
+++ b/arch/arm/boards/karo-tx6x/ram-base.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 wm 32 MX6_IOM_DRAM_DQM0			0x00020030
 wm 32 MX6_IOM_DRAM_DQM1			0x00020030
 wm 32 MX6_IOM_DRAM_DQM2			0x00020030
diff --git a/arch/arm/boards/kindle-mx50/Makefile b/arch/arm/boards/kindle-mx50/Makefile
index 2cc614a878..14cf83793d 100644
--- a/arch/arm/boards/kindle-mx50/Makefile
+++ b/arch/arm/boards/kindle-mx50/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-kindle-mx50
diff --git a/arch/arm/boards/kindle-mx50/board.c b/arch/arm/boards/kindle-mx50/board.c
index 8fc5af8320..a5c81ac8e7 100644
--- a/arch/arm/boards/kindle-mx50/board.c
+++ b/arch/arm/boards/kindle-mx50/board.c
@@ -10,17 +10,16 @@
 #include <driver.h>
 #include <param.h>
 #include <magicvar.h>
-#include <partition.h>
 #include <libfile.h>
 #include <globalvar.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <linux/sizes.h>
-#include <usb/fsl_usb2.h>
-#include <mach/generic.h>
-#include <mach/imx50-regs.h>
-#include <mach/imx5.h>
-#include <mach/revision.h>
+#include <linux/usb/fsl_usb2.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx50-regs.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/revision.h>
 
 /* 16 byte id for serial number */
 #define ATAG_SERIAL16   0x5441000a
@@ -84,10 +83,9 @@ static char *mac;
 static void kindle_rev_init(void)
 {
 	int ret;
-	size_t size;
 	void *buf;
 	const char userdata[] = "/dev/mmc2.boot0.userdata";
-	ret = read_file_2(userdata, &size, &buf, 128);
+	ret = read_file_2(userdata, NULL, &buf, 128);
 	if (ret && ret != -EFBIG) {
 		pr_err("Could not read board info from %s\n", userdata);
 		return;
@@ -142,7 +140,7 @@ mem_initcall(kindle_mx50_mem_init);
 
 static int kindle_mx50_devices_init(void)
 {
-	struct device_d *dev;
+	struct device *dev;
 
 	if (!is_mx50_kindle())
 		return 0;
diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg
index b8a4e824ef..5f1f8ef6b0 100644
--- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg
+++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 # DCD i.MX50 SoC setup using 256MiB LPDDR1
 # Copyright (C) 2017 Alexander Kurz <akurz@blala.de>
 #
diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg
index 527d91dc78..520e61be58 100644
--- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg
+++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
 # DCD i.MX50 SoC setup using 256MiB LPDDR2
 # Copyright (C) 2017 Alexander Kurz <akurz@blala.de>
 #
diff --git a/arch/arm/boards/kindle-mx50/lowlevel.c b/arch/arm/boards/kindle-mx50/lowlevel.c
index 992d1fd1a8..61d2b037fe 100644
--- a/arch/arm/boards/kindle-mx50/lowlevel.c
+++ b/arch/arm/boards/kindle-mx50/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <io.h>
@@ -6,8 +8,8 @@
 #include <asm/sections.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <mach/imx50-regs.h>
-#include <mach/generic.h>
+#include <mach/imx/imx50-regs.h>
+#include <mach/imx/generic.h>
 
 extern char __dtb_imx50_kindle_d01100_start[];
 extern char __dtb_imx50_kindle_d01200_start[];
diff --git a/arch/arm/boards/kindle3/env/boot/mmc_kernel b/arch/arm/boards/kindle3/env/boot/mmc_kernel
deleted file mode 100644
index c6145b85ac..0000000000
--- a/arch/arm/boards/kindle3/env/boot/mmc_kernel
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-# Boot the Amazon factory-shipped kernel uimage stored on
-# the eMMC at MOVINAND_OFFSET_KERNEL=266240.
-
-global linux.bootargs.dyn.root="root=/dev/mmcblk0p1 ro"
-
-bootm -c -a 0x80008000 /dev/disk0.kernel
diff --git a/arch/arm/boards/kindle3/env/init/serials b/arch/arm/boards/kindle3/env/init/serials
deleted file mode 100644
index 76580aeece..0000000000
--- a/arch/arm/boards/kindle3/env/init/serials
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/sh
-
-global board.serial16
-global board.revision16
-
-# 16-byte alphanumeric containing the serial number
-# SN is the first 16 bytes before the bootloader
-if test -b /dev/disk0.serial; then
-	if memcpy -s /dev/disk0.serial -d tmp_serial16 -b 0 0 16; then
-		readf tmp_serial16 global.board.serial16
-	fi
-fi
-[ -f tmp_serial16 ] && rm tmp_serial16
-
-# 16-byte alphanumeric containing the board revision
-if test -b /dev/disk0.imx_header; then
-	if memcpy -s /dev/disk0.imx_header -d tmp_revision16 -b 2032 0 16; then
-		readf tmp_revision16 global.board.revision16
-	fi
-fi
-[ -f tmp_revision16 ] && rm tmp_revision16
diff --git a/arch/arm/boards/kindle3/env/init/usbconsole b/arch/arm/boards/kindle3/env/init/usbconsole
deleted file mode 100644
index 87a8f9bf8c..0000000000
--- a/arch/arm/boards/kindle3/env/init/usbconsole
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-# Fiveway device select key activates usbserial access for 60s
-echo
-if gpio_get_value 63; then
-	usbserial
-	global.autoboot_timeout=60
-fi
diff --git a/arch/arm/boards/kindle3/env/nv/autoboot_timeout b/arch/arm/boards/kindle3/env/nv/autoboot_timeout
deleted file mode 100644
index 00750edc07..0000000000
--- a/arch/arm/boards/kindle3/env/nv/autoboot_timeout
+++ /dev/null
@@ -1 +0,0 @@
-3
diff --git a/arch/arm/boards/kindle3/env/nv/boot.default b/arch/arm/boards/kindle3/env/nv/boot.default
deleted file mode 100644
index 3118b7af45..0000000000
--- a/arch/arm/boards/kindle3/env/nv/boot.default
+++ /dev/null
@@ -1 +0,0 @@
-mmc_kernel
diff --git a/arch/arm/boards/kindle3/env/nv/linux.bootargs.base b/arch/arm/boards/kindle3/env/nv/linux.bootargs.base
deleted file mode 100644
index 3a940d88fa..0000000000
--- a/arch/arm/boards/kindle3/env/nv/linux.bootargs.base
+++ /dev/null
@@ -1 +0,0 @@
-mem=256M ip=none
diff --git a/arch/arm/boards/kindle3/env/nv/linux.bootargs.console b/arch/arm/boards/kindle3/env/nv/linux.bootargs.console
deleted file mode 100644
index d775310b40..0000000000
--- a/arch/arm/boards/kindle3/env/nv/linux.bootargs.console
+++ /dev/null
@@ -1 +0,0 @@
-console=ttymxc0,115200
diff --git a/arch/arm/boards/kindle3/env/nv/linux.bootargs.lpj b/arch/arm/boards/kindle3/env/nv/linux.bootargs.lpj
deleted file mode 100644
index aa3ba59e55..0000000000
--- a/arch/arm/boards/kindle3/env/nv/linux.bootargs.lpj
+++ /dev/null
@@ -1 +0,0 @@
-lpj=2555904
diff --git a/arch/arm/boards/kindle3/flash-header.imxcfg b/arch/arm/boards/kindle3/flash-header.imxcfg
deleted file mode 100644
index 74b65d6a5c..0000000000
--- a/arch/arm/boards/kindle3/flash-header.imxcfg
+++ /dev/null
@@ -1,24 +0,0 @@
-soc imx35
-loadaddr 0x87eff400
-ivtofs 0x400
-
-wm 32 0x53f80004 0x00821000
-wm 32 0x53f80004 0x00821000
-wm 32 0xb8001010 0x00000002
-wm 32 0xb8001010 0x00000004
-wm 32 0xb8001004 0x0019672f
-wm 32 0xb8001000 0x93100000
-wm 8 0x80000400 0xda
-wm 32 0xb8001000 0xa3100000
-wm 32 0x80000000 0x12344321
-wm 32 0x80000000 0x12344321
-wm 32 0xb8001000 0xb3100000
-wm 8 0x80000033 0xda
-wm 8 0x82000000 0xff
-wm 32 0xb8001000 0x83226080
-wm 32 0xb8001010 0x0000000c
-wm 32 0x80000000 0xdeadbeef
-wm 32 0xb8001030 0x00e78000
-wm 32 0x43fac004 0x00000004
-wm 32 0x43fac328 0x00002100
-wm 32 0x43fac7d0 0x00000000
diff --git a/arch/arm/boards/kindle3/kindle3.c b/arch/arm/boards/kindle3/kindle3.c
deleted file mode 100644
index a593dc424d..0000000000
--- a/arch/arm/boards/kindle3/kindle3.c
+++ /dev/null
@@ -1,304 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-// SPDX-FileCopyrightText: 2016 Alexander Kurz <akurz@blala.de>
-
-/* Board support for the Amazon Kindle 3rd generation */
-
-#include <common.h>
-#include <command.h>
-#include <driver.h>
-#include <init.h>
-#include <bootsource.h>
-#include <io.h>
-#include <environment.h>
-#include <generated/mach-types.h>
-#include <asm/armlinux.h>
-#include <asm/mmu.h>
-#include <asm/setup.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/iomux-mx35.h>
-#include <mach/devices-imx35.h>
-#include <mach/generic.h>
-#include <usb/fsl_usb2.h>
-#include <mach/usb.h>
-#include <mach/spi.h>
-#include <spi/spi.h>
-#include <magicvar.h>
-
-/* 16 byte id for serial number */
-#define ATAG_SERIAL16   0x5441000a
-/* 16 byte id for a board revision */
-#define ATAG_REVISION16 0x5441000b
-
-struct char16_tag {
-	char data[16];
-};
-
-static struct tag *setup_16char_tag(struct tag *params, uint32_t tag,
-				    const char *value)
-{
-	struct char16_tag *target;
-	target = ((void *) params) + sizeof(struct tag_header);
-	params->hdr.tag = tag;
-	params->hdr.size = tag_size(char16_tag);
-	memcpy(target->data, value, sizeof target->data);
-	return tag_next(params);
-}
-
-static const char *get_env_16char_tag(const char *tag)
-{
-	static const char *default16 = "0000000000000000";
-	const char *value;
-	value = getenv(tag);
-	if (!value) {
-		printf("env var %s not found, using default\n", tag);
-		return default16;
-	}
-	if (strlen(value) != 16) {
-		printf("env var %s: expecting 16 characters, using default\n",
-			tag);
-		return default16;
-	}
-	printf("%s: %s\n", tag, value);
-	return value;
-}
-
-BAREBOX_MAGICVAR(global.board.serial16,
-	"Pass the kindle Serial as vendor-specific ATAG to linux");
-BAREBOX_MAGICVAR(global.board.revision16,
-	"Pass the kindle BoardId as vendor-specific ATAG to linux");
-
-/* The Kindle3 Kernel expects two custom ATAGs, ATAG_REVISION16 describing
- * the board and ATAG_SERIAL16 to identify the individual device.
- */
-static struct tag *kindle3_append_atags(struct tag *params)
-{
-	params = setup_16char_tag(params, ATAG_SERIAL16,
-				get_env_16char_tag("global.board.serial16"));
-	params = setup_16char_tag(params, ATAG_REVISION16,
-				get_env_16char_tag("global.board.revision16"));
-	return params;
-}
-
-static struct fsl_usb2_platform_data kindle3_usb_info = {
-	.operating_mode = FSL_USB2_DR_DEVICE,
-	.phy_mode = FSL_USB2_PHY_UTMI,
-};
-
-/* SPI master devices. */
-static int kindle3_spi0_internal_chipselect[] = {
-	IMX_GPIO_NR(1, 18),
-};
-
-static struct spi_imx_master kindle3_spi0_info = {
-	.chipselect	= kindle3_spi0_internal_chipselect,
-	.num_chipselect	= ARRAY_SIZE(kindle3_spi0_internal_chipselect),
-};
-
-static const struct spi_board_info kindle3_spi_board_info[] = {
-	{
-		.name		= "mc13892",
-		.bus_num	= 0,
-		.chip_select	= 0,
-		.mode		= SPI_CS_HIGH,
-	},
-};
-
-static int kindle3_mmu_init(void)
-{
-	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-
-	return 0;
-}
-postmmu_initcall(kindle3_mmu_init);
-
-static int kindle3_devices_init(void)
-{
-	imx35_add_mmc0(NULL);
-
-	if (IS_ENABLED(CONFIG_USB_GADGET)) {
-		unsigned int tmp;
-		/* Workaround ENGcm09152 */
-		tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608);
-		writel(tmp | (1 << 23), MX35_USB_OTG_BASE_ADDR + 0x608);
-		add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL,
-				   MX35_USB_OTG_BASE_ADDR, 0x200,
-				   IORESOURCE_MEM, &kindle3_usb_info);
-	}
-
-	/* The kindle3 related linux patch published by amazon bluntly
-	 * renamed MACH_MX35_3DS to MACH_MX35_LUIGI
-	 */
-	armlinux_set_architecture(MACH_TYPE_MX35_3DS);
-
-	/* Compatibility ATAGs for original kernel */
-	armlinux_set_atag_appender(kindle3_append_atags);
-	return 0;
-}
-device_initcall(kindle3_devices_init);
-
-#define FIVEWAY_PAD_CTL (PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_DVS)
-static iomux_v3_cfg_t kindle3_pads[] = {
-	/* UART1 */
-	MX35_PAD_RXD1__UART1_RXD_MUX,
-	MX35_PAD_TXD1__UART1_TXD_MUX,
-
-	/* eMMC */
-	MX35_PAD_SD1_CMD__ESDHC1_CMD,
-	MX35_PAD_SD1_CLK__ESDHC1_CLK,
-	MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
-	MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
-	MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
-	MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
-
-	/* USB */
-	MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
-	MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
-
-	/* I2C 1+2 */
-	MX35_PAD_I2C1_CLK__I2C1_SCL,
-	MX35_PAD_I2C1_DAT__I2C1_SDA,
-	MX35_PAD_I2C2_CLK__I2C2_SCL,
-	MX35_PAD_I2C2_DAT__I2C2_SDA,
-
-	/* SPI */
-	MX35_PAD_CSPI1_SS0__GPIO1_18,
-	MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
-	MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
-	MX35_PAD_CSPI1_MISO__CSPI1_MISO,
-	MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY,
-
-	/* fiveway device: up, down, left, right, select */
-	IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, FIVEWAY_PAD_CTL),
-	IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, FIVEWAY_PAD_CTL),
-	IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, FIVEWAY_PAD_CTL),
-	IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, FIVEWAY_PAD_CTL),
-	IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, FIVEWAY_PAD_CTL),
-
-	/* Volume keys: up, down */
-	MX35_PAD_SCKR__GPIO1_4,
-	MX35_PAD_FSR__GPIO1_5,
-
-};
-
-static int kindle3_part_init(void)
-{
-	devfs_add_partition("disk0", SZ_1K, 2 * SZ_1K,
-			    DEVFS_PARTITION_FIXED, "disk0.imx_header");
-	devfs_add_partition("disk0", 4 * SZ_1K, (192 - 1) * SZ_1K,
-			    DEVFS_PARTITION_FIXED, "disk0.self");
-	devfs_add_partition("disk0", (192 + 3) * SZ_1K, SZ_64K,
-			    DEVFS_PARTITION_FIXED, "env0");
-	devfs_add_partition("disk0", (256 + 3) * SZ_1K, SZ_1K,
-			    DEVFS_PARTITION_FIXED, "disk0.serial");
-	devfs_add_partition("disk0", (256 + 4) * SZ_1K, 3407872,
-			    DEVFS_PARTITION_FIXED, "disk0.kernel");
-	devfs_add_partition("disk0", 3674112, SZ_256K,
-			    DEVFS_PARTITION_FIXED, "disk0.waveform");
-	return 0;
-}
-
-late_initcall(kindle3_part_init);
-
-static int imx35_console_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(kindle3_pads,
-					 ARRAY_SIZE(kindle3_pads));
-
-	barebox_set_model("Kindle3");
-	barebox_set_hostname("kindle3");
-
-	imx35_add_uart0();
-
-	spi_register_board_info(kindle3_spi_board_info,
-				ARRAY_SIZE(kindle3_spi_board_info));
-	imx35_add_spi0(&kindle3_spi0_info);
-
-	imx35_add_i2c0(NULL);
-	imx35_add_i2c1(NULL);
-	return 0;
-}
-console_initcall(imx35_console_init);
-
-static int kindle3_core_setup(void)
-{
-	u32 tmp;
-
-	/* AIPS setup - Only setup MPROTx registers.
-	 * The PACR default values are good.
-	 */
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
-
-	/*
-	 * Clear the on and off peripheral modules Supervisor Protect bit
-	 * for SDMA to access them. Did not change the AIPS control registers
-	 * (offset 0x20) access type
-	 */
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
-	tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50);
-	tmp &= 0x00FFFFFF;
-	writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50);
-
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
-	tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50);
-	tmp &= 0x00FFFFFF;
-	writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50);
-
-	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-
-	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0);   /* for S0 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
-
-	/* SGPCR - always park on last master */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
-
-	/* MGPCR - restore default values */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
-
-	/*
-	 * M3IF Control Register (M3IFCTL)
-	 * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[1] = MAX1 not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[2] = L2CC1 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[3] = USB  not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[4] = SDMA not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[5] = GPU not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
-	 * MRRP[7] = IPU2 not on priority list (0 << 0)		= 0x00000000
-	 *                                                       ------------
-	 *                                                        0x00000040
-	 */
-	writel(0x40, MX35_M3IF_BASE_ADDR);
-
-	return 0;
-}
-
-core_initcall(kindle3_core_setup);
diff --git a/arch/arm/boards/kindle3/lowlevel.c b/arch/arm/boards/kindle3/lowlevel.c
deleted file mode 100644
index 251bcf9d42..0000000000
--- a/arch/arm/boards/kindle3/lowlevel.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-// SPDX-FileCopyrightText: 2016 Alexander Kurz <akurz@blala.de>
-
-#include <common.h>
-#include <init.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/cache-l2x0.h>
-#include <io.h>
-#include <mach/imx-nand.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/sections.h>
-#include <asm-generic/memory_layout.h>
-#include <asm/system.h>
-
-void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	uint32_t r, s;
-	unsigned long ccm_base = MX35_CCM_BASE_ADDR;
-	register uint32_t loops = 0x20000;
-
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE);
-
-	r = get_cr();
-	r |= CR_Z; /* Flow prediction (Z) */
-	r |= CR_U; /* unaligned accesses  */
-	r |= CR_FI; /* Low Int Latency     */
-
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r"(s));
-	s |= 0x7;
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s));
-
-	set_cr(r);
-
-	r = 0;
-	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
-
-	/*
-	 * Branch predicition is now enabled.  Flush the BTAC to ensure a valid
-	 * starting point.  Don't flush BTAC while it is disabled to avoid
-	 * ARM1136 erratum 408023.
-	 */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r));
-
-	/* invalidate I cache and D cache */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r));
-
-	/* invalidate TLBs */
-	__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r));
-
-	/* Drain the write buffer */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r));
-
-	/* Also setup the Peripheral Port Remap register inside the core */
-	r = 0x40000015; /* start from AIPS 2GB region */
-	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
-
-	/*
-	 * End of ARM1136 init
-	 */
-
-	writel(0x003F4208, ccm_base + MX35_CCM_CCMR);
-
-	/* Set MPLL , arm clock and ahb clock*/
-	writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL);
-
-	writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL);
-	writel(0x00001000, ccm_base + MX35_CCM_PDR0);
-
-	r = readl(ccm_base + MX35_CCM_CGR0);
-	r |= 0x3 << MX35_CCM_CGR0_CSPI1_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR0_ESDHC1_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR0);
-
-	r = readl(ccm_base + MX35_CCM_CGR1);
-	r |= 0x3 << MX35_CCM_CGR1_IOMUX_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR1_I2C2_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR1_GPIO1_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR1_GPIO2_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR1);
-
-	r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
-	r |= 0x1000;
-	writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
-
-	/* Skip SDRAM initialization if we run from RAM */
-	r = get_pc();
-	if (r > 0x80000000 && r < 0x90000000)
-		goto out;
-
-	/* Init Mobile DDR */
-	writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	/* ESD_MISC: Enable DDR SDRAM */
-	writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	__asm__ volatile ("1:\n"
-			"subs %0, %1, #1\n"
-			"bne 1b" : "=r" (loops) : "0" (loops));
-
-	writel(0x0019672f, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
-	/* ESD_ESDCTL0 : select Prechare-All mode */
-	writel(0x93220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400);
-	/* ESD_ESDCTL0: Auto Refresh command */
-	writel(0xA3220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX35_CSD0_BASE_ADDR);
-	writeb(0xda, MX35_CSD0_BASE_ADDR);
-	/* ESD_ESDCTL0: Load Mode Register */
-	writel(0xB3220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33);
-	writeb(0xff, MX35_CSD0_BASE_ADDR + 0x2000000);
-	/* ESD_ESDCTL0: enable Auto-Refresh */
-	writel(0x83228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-
-	writel(0x0000000c, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	writel(0xdeadbeef, MX35_CSD0_BASE_ADDR);
-	writel(0x00e78000, MX35_CSD0_BASE_ADDR + 0x1030);
-
-out:
-	imx35_barebox_entry(NULL);
-}
diff --git a/arch/arm/boards/kontron-samx6i/Makefile b/arch/arm/boards/kontron-samx6i/Makefile
index 816962241a..d753ff5f18 100644
--- a/arch/arm/boards/kontron-samx6i/Makefile
+++ b/arch/arm/boards/kontron-samx6i/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o mem.o
 lwl-y += lowlevel.o mem.o
diff --git a/arch/arm/boards/kontron-samx6i/board.c b/arch/arm/boards/kontron-samx6i/board.c
index b4b0eac824..376548f549 100644
--- a/arch/arm/boards/kontron-samx6i/board.c
+++ b/arch/arm/boards/kontron-samx6i/board.c
@@ -18,8 +18,8 @@
 #include <common.h>
 #include <init.h>
 #include <of.h>
-#include <mach/bbu.h>
-#include <mach/esdctl.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/esdctl.h>
 
 #include <asm/armlinux.h>
 
diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
index db1698d272..1ff4caccfa 100644
--- a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
+++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
index 99608d0fe8..a8cc0d512b 100644
--- a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
+++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
diff --git a/arch/arm/boards/kontron-samx6i/lowlevel.c b/arch/arm/boards/kontron-samx6i/lowlevel.c
index afb7372323..59694e72f9 100644
--- a/arch/arm/boards/kontron-samx6i/lowlevel.c
+++ b/arch/arm/boards/kontron-samx6i/lowlevel.c
@@ -10,6 +10,7 @@
  */
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <io.h>
 #include <asm/barebox-arm-head.h>
@@ -17,8 +18,8 @@
 #include <asm/sections.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <mach/imx6.h>
-#include <mach/esdctl.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/esdctl.h>
 
 #include "mem.h"
 
diff --git a/arch/arm/boards/kontron-samx6i/mem.c b/arch/arm/boards/kontron-samx6i/mem.c
index 08dceb55c0..19e2ac2dd8 100644
--- a/arch/arm/boards/kontron-samx6i/mem.c
+++ b/arch/arm/boards/kontron-samx6i/mem.c
@@ -11,9 +11,9 @@
 
 #include <linux/sizes.h>
 #include <common.h>
-#include <mach/iomux-mx6.h>
-#include <mach/imx-gpio.h>
-#include <mach/imx6.h>
+#include <mach/imx/iomux-mx6.h>
+#include <mach/imx/imx-gpio.h>
+#include <mach/imx/imx6.h>
 
 #include "mem.h"
 
diff --git a/arch/arm/boards/kontron-samx6i/mem.h b/arch/arm/boards/kontron-samx6i/mem.h
index 57e3c0cecc..25faf38490 100644
--- a/arch/arm/boards/kontron-samx6i/mem.h
+++ b/arch/arm/boards/kontron-samx6i/mem.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __BOARD_KONTRON_SAMX6I_MEM_H
 #define __BOARD_KONTRON_SAMX6I_MEM_H
 
diff --git a/arch/arm/boards/lenovo-ix4-300d/Makefile b/arch/arm/boards/lenovo-ix4-300d/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/lenovo-ix4-300d/Makefile
+++ b/arch/arm/boards/lenovo-ix4-300d/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/lenovo-ix4-300d/lowlevel.c b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c
index c0a695908f..d76e4af30d 100644
--- a/arch/arm/boards/lenovo-ix4-300d/lowlevel.c
+++ b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c
@@ -3,13 +3,13 @@
 
 #include <common.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
+#include <mach/mvebu/barebox-arm-head.h>
 #include <linux/sizes.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/lowlevel.h>
 
 extern char __dtb_armada_xp_lenovo_ix4_300d_bb_start[];
 
-ENTRY_FUNCTION(start_lenovo_ix4_300d, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_lenovo_ix4_300d, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/ls1021aiot/Makefile b/arch/arm/boards/ls1021aiot/Makefile
new file mode 100644
index 0000000000..df69ce814b
--- /dev/null
+++ b/arch/arm/boards/ls1021aiot/Makefile
@@ -0,0 +1,3 @@
+lwl-y += lowlevel.o
+obj-y += board.o
+lwl-y += start.o
diff --git a/arch/arm/boards/ls1021aiot/board.c b/arch/arm/boards/ls1021aiot/board.c
new file mode 100644
index 0000000000..70070a4e75
--- /dev/null
+++ b/arch/arm/boards/ls1021aiot/board.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+// SPDX-FileCopyrightText: (C) Copyright 2023 Ametek Inc.
+// SPDX-FileCopyrightText: 2023 Renaud Barbier <renaud.barbier@ametek.com>,
+
+#include <common.h>
+#include <init.h>
+#include <bbu.h>
+#include <net.h>
+#include <crc.h>
+#include <fs.h>
+#include <io.h>
+#include <envfs.h>
+#include <libfile.h>
+#include <asm/memory.h>
+#include <linux/sizes.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <asm/system.h>
+#include <mach/layerscape/layerscape.h>
+#include <of_address.h>
+#include <soc/fsl/immap_lsch2.h>
+
+static int iot_mem_init(void)
+{
+	if (!of_machine_is_compatible("fsl,ls1021a"))
+		return 0;
+
+	arm_add_mem_device("ram0", 0x80000000, 0x40000000);
+
+	return 0;
+}
+mem_initcall(iot_mem_init);
+
+static int iot_postcore_init(void)
+{
+	struct ls102xa_ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR);
+
+	if (!of_machine_is_compatible("fsl,ls1021a"))
+		return 0;
+
+	/* clear BD & FR bits for BE BD's and frame data */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+
+	return 0;
+}
+coredevice_initcall(iot_postcore_init);
diff --git a/arch/arm/boards/ls1021aiot/lowlevel.c b/arch/arm/boards/ls1021aiot/lowlevel.c
new file mode 100644
index 0000000000..6bba528635
--- /dev/null
+++ b/arch/arm/boards/ls1021aiot/lowlevel.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+// SPDX-FileCopyrightText: (C) Copyright 2023 Ametek Inc.
+// SPDX-FileCopyrightText: 2023 Renaud Barbier <renaud.barbier@ametek.com>
+
+/*
+ * Derived from Freescale LSDK-19.09-update-311219
+ */
+#include <common.h>
+#include <clock.h>
+#include <debug_ll.h>
+#include <soc/fsl/fsl_ddr_sdram.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/syscounter.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <linux/sizes.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/lowlevel.h>
+#include <mach/layerscape/xload.h>
+#include <mach/layerscape/layerscape.h>
+
+static struct fsl_ddr_controller ddrc[] = {
+	{
+		.memctl_opts.ddrtype = SDRAM_TYPE_DDR3,
+		.base = IOMEM(LSCH2_DDR_ADDR),
+		.ddr_freq = LS1021A_DDR_FREQ,
+		.erratum_A009942 = 1,
+		.chip_selects_per_ctrl = 4,
+		.fsl_ddr_config_reg = {
+			.cs[0].bnds         = 0x008000bf,
+			.cs[0].config       = 0x80014302,
+			.cs[0].config_2     = 0x00000000,
+			.cs[1].bnds         = 0x00000000,
+			.cs[1].config       = 0x00000000,
+			.cs[1].config_2     = 0x00000000,
+			.cs[2].bnds         = 0x00000000,
+			.cs[2].config       = 0x00000000,
+			.cs[2].config_2     = 0x00000000,
+			.cs[3].bnds         = 0x00000000,
+			.cs[3].config       = 0x00000000,
+			.cs[3].config_2     = 0x00000000,
+			.timing_cfg_3       = 0x010e1000,
+			.timing_cfg_0       = 0x50550004,
+			.timing_cfg_1       = 0xbcb38c56,
+			.timing_cfg_2       = 0x0040d120,
+			.ddr_sdram_cfg      = 0x470c0008,
+			.ddr_sdram_cfg_2    = 0x00401010,
+			.ddr_sdram_mode     = 0x00061c60,
+			.ddr_sdram_mode_2   = 0x00180000,
+			.ddr_sdram_interval = 0x18600618,
+			.ddr_data_init      = 0xDEADBEEF,
+			.ddr_sdram_clk_cntl = 0x02000000,
+			.ddr_init_addr      = 0x00000000,
+			.ddr_init_ext_addr  = 0x00000000,
+			.timing_cfg_4       = 0x00000001,
+			.timing_cfg_5       = 0x03401400,
+			.ddr_zq_cntl        = 0x89080600,
+			.ddr_wrlvl_cntl     = 0x8655f605,
+			.ddr_wrlvl_cntl_2   = 0x05060607,
+			.ddr_wrlvl_cntl_3   = 0x05050505,
+			.ddr_sr_cntr        = 0x00000000,
+			.ddr_sdram_rcw_1    = 0x00000000,
+			.ddr_sdram_rcw_2    = 0x00000000,
+			.ddr_sdram_rcw_3    = 0x00000000,
+			.ddr_cdr1           = 0x80040000,
+			.ddr_cdr2           = 0x000000C0,
+			.dq_map_0           = 0x00000000,
+			.dq_map_1           = 0x00000000,
+			.dq_map_2           = 0x00000000,
+			.dq_map_3           = 0x00000000,
+			.debug[28]          = 0x00700046,
+		},
+	},
+};
+
+extern char __dtb_fsl_ls1021a_iot_start[];
+
+static noinline __noreturn void ls1021aiot_r_entry(void)
+{
+	unsigned long membase = LS1021A_DDR_SDRAM_BASE;
+
+	if (get_pc() >= membase) {
+		barebox_arm_entry(membase, SZ_1G - SZ_64M,
+				  __dtb_fsl_ls1021a_iot_start);
+	}
+
+	ls102xa_init_lowlevel();
+	ls102xa_debug_ll_init();
+
+	udelay(500);
+	putc_ll('>');
+
+	fsl_ddr_set_memctl_regs(&ddrc[0], 0, false);
+
+	ls1021a_errata_post_ddr();
+
+	ls1021a_xload_start_image(SZ_1G, 0, 0);
+
+	pr_err("Booting failed\n");
+
+	while (1)
+		;
+}
+
+void ls1021aiot_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+
+__noreturn void
+ls1021aiot_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+{
+	relocate_to_current_adr();
+	setup_c();
+
+	ls1021aiot_r_entry();
+}
diff --git a/arch/arm/boards/ls1021aiot/ls102xa_pbi.cfg b/arch/arm/boards/ls1021aiot/ls102xa_pbi.cfg
new file mode 100644
index 0000000000..840299be8d
--- /dev/null
+++ b/arch/arm/boards/ls1021aiot/ls102xa_pbi.cfg
@@ -0,0 +1,11 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
diff --git a/arch/arm/boards/ls1021aiot/ls102xa_rcw_sd_qspi.cfg b/arch/arm/boards/ls1021aiot/ls102xa_rcw_sd_qspi.cfg
new file mode 100644
index 0000000000..3b5300501d
--- /dev/null
+++ b/arch/arm/boards/ls1021aiot/ls102xa_rcw_sd_qspi.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#disable IFC, enable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+20000000 08407900 e0025a00 21046000
+00000000 00000000 00000000 20038000
+20024800 881b1340 00000000 00000000
diff --git a/arch/arm/boards/ls1021aiot/start.S b/arch/arm/boards/ls1021aiot/start.S
new file mode 100644
index 0000000000..c907777ca1
--- /dev/null
+++ b/arch/arm/boards/ls1021aiot/start.S
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/linkage.h>
+#include <asm/barebox-arm64.h>
+
+#define STACK_TOP 0x10020000
+
+ENTRY_PROC(start_ls1021aiot)
+	ldr r3, =STACK_TOP
+	mov sp, r3
+	b ls1021aiot_entry
+ENTRY_PROC_END(start_ls1021aiot)
diff --git a/arch/arm/boards/ls1028ardb/Makefile b/arch/arm/boards/ls1028ardb/Makefile
new file mode 100644
index 0000000000..df60a21844
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
+lwl-y += start.o
+obj-y += board.o
diff --git a/arch/arm/boards/ls1028ardb/board.c b/arch/arm/boards/ls1028ardb/board.c
new file mode 100644
index 0000000000..094d72e6fc
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/board.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <deep-probe.h>
+#include <bootsource.h>
+#include <driver.h>
+#include <init.h>
+#include <of.h>
+#include <asm/memory.h>
+#include <mach/layerscape/layerscape.h>
+#include <mach/layerscape/bbu.h>
+#include <linux/sizes.h>
+
+static int ls1028ardb_probe(struct device *dev)
+{
+	unsigned long sd_bbu_flags = 0;
+	unsigned long emmc_bbu_flags = 0;
+
+	arm_add_mem_device("ram1", LS1028A_DDR_SDRAM_HIGHMEM_BASE, SZ_2G);
+
+	if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 0) {
+		sd_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+		of_device_enable_path("/chosen/environment-sd");
+	} else {
+		emmc_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+		of_device_enable_path("/chosen/environment-emmc");
+	}
+
+	ls1028a_bbu_mmc_register_handler("sd", "/dev/mmc0.barebox", sd_bbu_flags);
+	ls1028a_bbu_mmc_register_handler("emmc", "/dev/mmc1.barebox", emmc_bbu_flags);
+
+	return 0;
+}
+
+static const struct of_device_id ls1028a_of_match[] = {
+	{ .compatible = "fsl,ls1028a-rdb" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(ls1028a_of_match);
+
+static struct driver ls1028ardb_board_driver = {
+	.name = "ls1028a-rdb",
+	.probe = ls1028ardb_probe,
+	.of_compatible = ls1028a_of_match,
+};
+device_platform_driver(ls1028ardb_board_driver);
diff --git a/arch/arm/boards/ls1028ardb/lowlevel.c b/arch/arm/boards/ls1028ardb/lowlevel.c
new file mode 100644
index 0000000000..00db0b1cf8
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/lowlevel.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <debug_ll.h>
+#include <ddr_spd.h>
+#include <image-metadata.h>
+#include <platform_data/mmc-esdhc-imx.h>
+#include <soc/fsl/fsl_ddr_sdram.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/syscounter.h>
+#include <asm/cache.h>
+#include <mach/layerscape/lowlevel.h>
+#include <mach/layerscape/xload.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/layerscape.h>
+#include <linux/bitfield.h>
+
+static struct fsl_ddr_controller ddrc = {
+	.memctl_opts.ddrtype = SDRAM_TYPE_DDR4,
+	.base = IOMEM(LSCH2_DDR_ADDR),
+	.ddr_freq = 1600000000,
+	.erratum_A009942 = 1,
+	.erratum_A009663 = 1,
+	.chip_selects_per_ctrl = 4,
+	.fsl_ddr_config_reg = {
+		.cs[0].bnds		= 0x000000ff,
+		.cs[0].config		= 0x80040422,
+		.cs[0].config_2		= 0,
+		.cs[1].bnds		= 0,
+		.cs[1].config		= 0,
+		.cs[1].config_2		= 0,
+
+		.timing_cfg_3		= 0x01111000,
+		.timing_cfg_0		= 0xd0550018,
+		.timing_cfg_1		= 0xFAFC0C42,
+		.timing_cfg_2		= 0x0048c114,
+		.ddr_sdram_cfg		= 0xe50c000c,
+		.ddr_sdram_cfg_2	= 0x00401110,
+		.ddr_sdram_mode		= 0x01010230,
+		.ddr_sdram_mode_2	= 0x0,
+
+		.ddr_sdram_md_cntl	= 0x0600001f,
+		.ddr_sdram_interval	= 0x18600618,
+		.ddr_data_init		= 0xdeadbeef,
+
+		.ddr_sdram_clk_cntl	= 0x02000000,
+		.ddr_init_addr		= 0,
+		.ddr_init_ext_addr	= 0,
+
+		.timing_cfg_4		= 0x00000002,
+		.timing_cfg_5		= 0x07401400,
+		.timing_cfg_6		= 0x0,
+		.timing_cfg_7		= 0x23300000,
+
+		.ddr_zq_cntl		= 0x8A090705,
+		.ddr_wrlvl_cntl		= 0x86550607,
+		.ddr_sr_cntr		= 0,
+		.ddr_sdram_rcw_1	= 0,
+		.ddr_sdram_rcw_2	= 0,
+		.ddr_wrlvl_cntl_2	= 0x0708080A,
+		.ddr_wrlvl_cntl_3	= 0x0A0B0C09,
+
+		.ddr_sdram_mode_9	= 0x00000400,
+		.ddr_sdram_mode_10	= 0x04000000,
+
+		.timing_cfg_8		= 0x06115600,
+
+		.dq_map_0		= 0x5b65b658,
+		.dq_map_1		= 0xd96d8000,
+		.dq_map_2		= 0,
+		.dq_map_3		= 0x01600000,
+
+		.ddr_cdr1		= 0x80040000,
+		.ddr_cdr2		= 0x000000C1
+	},
+};
+
+extern char __dtb_z_fsl_ls1028a_rdb_start[];
+
+#define MEM_PLL_RAT	GENMASK(15, 10)
+
+static unsigned long get_ddr_freq(void)
+{
+	unsigned long freq = 100000000;
+	u32 rcwsr1 = readl(0x1e00100);
+	u32 mult;
+
+	mult = FIELD_GET(MEM_PLL_RAT, rcwsr1);
+
+	return freq * mult;
+}
+
+struct dram_regions_info dram_info = {
+	.num_dram_regions = 2,
+	.total_dram_size = SZ_4G,
+	.region = {
+		{
+			.addr = LS1028A_DDR_SDRAM_BASE,
+			.size = SZ_2G,
+		}, {
+			.addr = LS1028A_DDR_SDRAM_HIGHMEM_BASE,
+			.size = SZ_2G,
+		},
+	},
+};
+
+static noinline __noreturn void ls1028ardb_r_entry(unsigned long memsize)
+{
+	unsigned long membase = LS1028A_DDR_SDRAM_BASE;
+
+	if (get_pc() >= membase)
+		barebox_arm_entry(membase, SZ_2G - LS1028A_TFA_RESERVED_SIZE,
+				  __dtb_z_fsl_ls1028a_rdb_start);
+
+	arm_cpu_lowlevel_init();
+	ls1028a_init_lowlevel();
+	ddrc.ddr_freq = get_ddr_freq();
+
+	fsl_ddr_set_memctl_regs(&ddrc, 0, true);
+
+	ls1028a_tzc400_init(SZ_4G);
+
+	ls1028a_errata_post_ddr();
+
+	ls1028a_esdhc1_start_image(&dram_info);
+
+	hang();
+}
+
+void ls1028ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2);
+
+__noreturn void ls1028ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2)
+{
+	ls1028a_uart_setup(IOMEM(LSCH2_NS16550_COM1));
+
+	relocate_to_current_adr();
+	setup_c();
+
+	ls1028ardb_r_entry(r0);
+}
diff --git a/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg b/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg
new file mode 100644
index 0000000000..53cfb20327
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+31e00400 18010000
+31e00404 00000000
+33400890 00800401
+33500890 00800401
+334008bc 00000001
+33400154 47474747
+33400158 47474747
+335008bc 00000001
+33500154 47474747
+33500158 47474747
+334008bc 00000000
+335008bc 00000000
diff --git a/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg b/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg
new file mode 100644
index 0000000000..2183991112
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+#PBL preamble and RCW header
+aa55aa55 80100000
+# RCW
+34004010 00000030 00000000 00000000
+00000000 00bf0000 0030c000 00000000
+01e03150 00002580 00000000 00003496
+00000000 00000010 00000000 00000000
+00000000 00000000 00000000 00000000
+00000000 00000000 00000000 00000000
+00000000 00000000 200e705a 00000000
+bb580000 00000000 00000000 00000000
+
diff --git a/arch/arm/boards/ls1028ardb/start.S b/arch/arm/boards/ls1028ardb/start.S
new file mode 100644
index 0000000000..fd410b744a
--- /dev/null
+++ b/arch/arm/boards/ls1028ardb/start.S
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/linkage.h>
+#include <asm/barebox-arm64.h>
+#include <asm/assembler64.h>
+
+#define STACK_TOP 0x18040000
+
+ENTRY_PROC(start_ls1028ardb)
+	switch_el x3, 3f, 2f, 1f
+3:
+	mov x3, #STACK_TOP
+	mov sp, x3
+	b ls1028ardb_entry
+2:
+1:
+	mov x3, 0x90000000
+	mov sp, x3
+	b ls1028ardb_entry
+ENTRY_PROC_END(start_ls1028ardb)
diff --git a/arch/arm/boards/ls1046ardb/Makefile b/arch/arm/boards/ls1046ardb/Makefile
index 03ac4ecca3..829be5327a 100644
--- a/arch/arm/boards/ls1046ardb/Makefile
+++ b/arch/arm/boards/ls1046ardb/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
 lwl-y += start.o
diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c
index ef68e9c7f9..ee70171ca3 100644
--- a/arch/arm/boards/ls1046ardb/board.c
+++ b/arch/arm/boards/ls1046ardb/board.c
@@ -13,8 +13,10 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <asm/system.h>
-#include <mach/layerscape.h>
-#include <mach/bbu.h>
+#include <mach/layerscape/layerscape.h>
+#include <mach/layerscape/bbu.h>
+#include <of_address.h>
+#include <linux/fsl_ifc.h>
 
 #define MAX_NUM_PORTS 16
 struct nxid {
@@ -31,7 +33,7 @@ struct nxid {
 	u8 mac_count;     /* 0x40        Number of MAC addresses */
 	u8 mac_flag;      /* 0x41        MAC table flags */
 	u8 mac[MAX_NUM_PORTS][6];     /* 0x42 - 0xa1 MAC addresses */
-	u8 res_2[90];     /* 0xa2 - 0xfb Reserved */	
+	u8 res_2[90];     /* 0xa2 - 0xfb Reserved */
 	u32 crc;          /* 0xfc - 0xff CRC32 checksum */
 } __packed;
 
@@ -147,6 +149,40 @@ static int rdb_mem_init(void)
 }
 mem_initcall(rdb_mem_init);
 
+static int rdb_nand_init(void)
+{
+	struct device_node *np;
+	void __iomem *ifc;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ifc");
+	if (!np)
+		return -EINVAL;
+
+	ifc = of_iomap(np, 0);
+	if (!ifc)
+		return -EINVAL;
+
+	set_ifc_cspr(ifc, IFC_CS0, CSPR_PHYS_ADDR(0x7e800000) |
+			CSPR_PORT_SIZE_8 | CSPR_MSEL_NAND | CSPR_V);
+	set_ifc_csor(ifc, IFC_CS0, CSOR_NAND_ECC_ENC_EN | CSOR_NAND_ECC_DEC_EN |
+			CSOR_NAND_ECC_MODE_8 |
+			CSOR_NAND_RAL_3 | CSOR_NAND_PGS_4K |
+			CSOR_NAND_SPRZ_224 |  CSOR_NAND_PB(64) |
+			CSOR_NAND_TRHZ_20);
+	set_ifc_amask(ifc, IFC_CS0, IFC_AMASK(64*1024));
+	set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM0, FTIM0_NAND_TCCST(0x07) |
+			FTIM0_NAND_TWP(0x18) | FTIM0_NAND_TWCHT(0x07) |
+			FTIM0_NAND_TWH(0x0a));
+	set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM1, FTIM1_NAND_TADLE(0x32) |
+			FTIM1_NAND_TWBE(0x39) | FTIM1_NAND_TRR(0x0e)|
+			FTIM1_NAND_TRP(0x18));
+	set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM2, FTIM2_NAND_TRAD(0xf) |
+			FTIM2_NAND_TREH(0xa) | FTIM2_NAND_TWHRE(0x1e));
+	set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM3, 0);
+
+	return 0;
+}
+
 static int rdb_postcore_init(void)
 {
 	if (!of_machine_is_compatible("fsl,ls1046a-rdb"))
@@ -157,7 +193,7 @@ static int rdb_postcore_init(void)
 	ls1046a_bbu_mmc_register_handler("sd", "/dev/mmc0.barebox",
 					 BBU_HANDLER_FLAG_DEFAULT);
 
-	return 0;
+	return rdb_nand_init();
 }
 
 postcore_initcall(rdb_postcore_init);
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c
index 0a30f05aa2..408e6017f6 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -5,17 +5,17 @@
 #include <ddr_spd.h>
 #include <image-metadata.h>
 #include <platform_data/mmc-esdhc-imx.h>
-#include <i2c/i2c-early.h>
+#include <pbl/i2c.h>
 #include <soc/fsl/fsl_ddr_sdram.h>
 #include <soc/fsl/immap_lsch2.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <asm/syscounter.h>
 #include <asm/cache.h>
-#include <mach/errata.h>
-#include <mach/lowlevel.h>
-#include <mach/xload.h>
-#include <mach/layerscape.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/lowlevel.h>
+#include <mach/layerscape/xload.h>
+#include <mach/layerscape/layerscape.h>
 
 struct board_specific_parameters {
 	u32 n_ranks;
@@ -147,7 +147,7 @@ found:
 	popts->cpo_sample = 0x61;
 }
 
-extern char __dtb_fsl_ls1046a_rdb_start[];
+extern char __dtb_z_fsl_ls1046a_rdb_start[];
 
 static struct spd_eeprom spd_eeprom[] = {
 	{
@@ -187,7 +187,7 @@ static struct fsl_ddr_info ls1046a_info = {
 static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize)
 {
 	unsigned long membase = LS1046A_DDR_SDRAM_BASE;
-	struct fsl_i2c *i2c;
+	struct pbl_i2c *i2c;
 	int ret;
 
 	if (get_pc() >= membase) {
@@ -195,23 +195,21 @@ static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize)
 			memsize = 0x100000000 - membase;
 
 		barebox_arm_entry(membase, 0x80000000 - SZ_64M,
-				  __dtb_fsl_ls1046a_rdb_start);
+				  __dtb_z_fsl_ls1046a_rdb_start);
 	}
 
 	arm_cpu_lowlevel_init();
-	debug_ll_init();
+	ls1046a_debug_ll_init();
 	ls1046a_init_lowlevel();
 
-	IMD_USED_OF(fsl_ls1046a_rdb);
-
 	i2c = ls1046_i2c_init(IOMEM(LSCH2_I2C1_BASE_ADDR));
-	ret = spd_read_eeprom(i2c, i2c_fsl_xfer, 0x51, &spd_eeprom);
+	ret = spd_read_eeprom(i2c, 0x51, &spd_eeprom, SPD_MEMTYPE_DDR4);
 	if (ret) {
 		pr_err("Cannot read SPD EEPROM: %d\n", ret);
 		goto err;
 	}
 
-	memsize = fsl_ddr_sdram(&ls1046a_info);
+	memsize = fsl_ddr_sdram(&ls1046a_info, false);
 
 	ls1046a_errata_post_ddr();
 
diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg
index 5478217524..0ed997031e 100644
--- a/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg
+++ b/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #Configure Scratch register
 09570600 00000000
 09570604 10000000
diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg
index 735d46c9f9..b9e455da9e 100644
--- a/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg
+++ b/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #QSPI clk
 0957015c 40100000
 #Configure Scratch register
diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg
index ccedf87e84..debb6479a8 100644
--- a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg
+++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg
index 7b9be0ad3f..2167a71b7f 100644
--- a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg
+++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg
index d3b152282f..ec18028c4b 100644
--- a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg
+++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
diff --git a/arch/arm/boards/lubbock/Makefile b/arch/arm/boards/lubbock/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/lubbock/Makefile
+++ b/arch/arm/boards/lubbock/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/lubbock/board.c b/arch/arm/boards/lubbock/board.c
index 2f3b6ad16b..af046e110a 100644
--- a/arch/arm/boards/lubbock/board.c
+++ b/arch/arm/boards/lubbock/board.c
@@ -6,24 +6,23 @@
 #include <environment.h>
 #include <fs.h>
 #include <init.h>
-#include <partition.h>
 #include <led.h>
 #include <gpio.h>
 #include <pwm.h>
 #include <linux/sizes.h>
 
-#include <mach/devices.h>
-#include <mach/mfp-pxa27x.h>
-#include <mach/pxa-regs.h>
-#include <mach/udc_pxa2xx.h>
-#include <mach/mci_pxa2xx.h>
+#include <mach/pxa/devices.h>
+#include <mach/pxa/mfp-pxa27x.h>
+#include <mach/pxa/pxa-regs.h>
+#include <mach/pxa/udc_pxa2xx.h>
+#include <mach/pxa/mci_pxa2xx.h>
 
 #include <platform_data/eth-smc91111.h>
 #include <asm/armlinux.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
 
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 
 #define ECOR            0x8000
 #define ECOR_RESET      0x80
diff --git a/arch/arm/boards/lubbock/lowlevel.c b/arch/arm/boards/lubbock/lowlevel.c
index abf9e7a98a..ef6b544a26 100644
--- a/arch/arm/boards/lubbock/lowlevel.c
+++ b/arch/arm/boards/lubbock/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <io.h>
@@ -5,8 +7,8 @@
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <linux/sizes.h>
-#include <mach/pxa-regs.h>
-#include <mach/regs-ost.h>
+#include <mach/pxa/pxa-regs.h>
+#include <mach/pxa/regs-ost.h>
 
 /*
  * Memory settings
diff --git a/arch/arm/boards/lxa-mc1/Makefile b/arch/arm/boards/lxa-mc1/Makefile
index 092c31d6b2..5678718188 100644
--- a/arch/arm/boards/lxa-mc1/Makefile
+++ b/arch/arm/boards/lxa-mc1/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
diff --git a/arch/arm/boards/lxa-mc1/board.c b/arch/arm/boards/lxa-mc1/board.c
index 9126973dcb..b377d4323e 100644
--- a/arch/arm/boards/lxa-mc1/board.c
+++ b/arch/arm/boards/lxa-mc1/board.c
@@ -3,8 +3,9 @@
 #include <linux/sizes.h>
 #include <init.h>
 #include <asm/memory.h>
-#include <mach/bbu.h>
+#include <mach/stm32mp/bbu.h>
 #include <bootsource.h>
+#include <deep-probe.h>
 #include <of.h>
 
 static int of_fixup_regulator_supply_disable(struct device_node *root, void *path)
@@ -28,7 +29,7 @@ static int of_fixup_regulator_supply_disable(struct device_node *root, void *pat
 	return 0;
 }
 
-static int mc1_probe(struct device_d *dev)
+static int mc1_probe(struct device *dev)
 {
 	int flags;
 
@@ -58,8 +59,9 @@ static const struct of_device_id mc1_of_match[] = {
 	{ .compatible = "lxa,stm32mp157c-mc1" },
 	{ /* sentinel */ },
 };
+BAREBOX_DEEP_PROBE_ENABLE(mc1_of_match);
 
-static struct driver_d mc1_board_driver = {
+static struct driver mc1_board_driver = {
 	.name = "board-lxa-mc1",
 	.probe = mc1_probe,
 	.of_compatible = mc1_of_match,
diff --git a/arch/arm/boards/lxa-mc1/lowlevel.c b/arch/arm/boards/lxa-mc1/lowlevel.c
index 274f824a16..86211bf9d8 100644
--- a/arch/arm/boards/lxa-mc1/lowlevel.c
+++ b/arch/arm/boards/lxa-mc1/lowlevel.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include <common.h>
-#include <mach/entry.h>
+#include <mach/stm32mp/entry.h>
 #include <debug_ll.h>
 
 extern char __dtb_z_stm32mp157c_lxa_mc1_start[];
diff --git a/arch/arm/boards/mainstone/Makefile b/arch/arm/boards/mainstone/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/mainstone/Makefile
+++ b/arch/arm/boards/mainstone/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/mainstone/board.c b/arch/arm/boards/mainstone/board.c
index f95bf057a7..979a4f3609 100644
--- a/arch/arm/boards/mainstone/board.c
+++ b/arch/arm/boards/mainstone/board.c
@@ -6,24 +6,23 @@
 #include <environment.h>
 #include <fs.h>
 #include <init.h>
-#include <partition.h>
 #include <led.h>
 #include <gpio.h>
 #include <pwm.h>
 #include <linux/sizes.h>
 
-#include <mach/devices.h>
-#include <mach/mfp-pxa27x.h>
-#include <mach/pxa-regs.h>
-#include <mach/udc_pxa2xx.h>
-#include <mach/mci_pxa2xx.h>
+#include <mach/pxa/devices.h>
+#include <mach/pxa/mfp-pxa27x.h>
+#include <mach/pxa/pxa-regs.h>
+#include <mach/pxa/udc_pxa2xx.h>
+#include <mach/pxa/mci_pxa2xx.h>
 
 #include <platform_data/eth-smc91111.h>
 #include <asm/armlinux.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
 
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 
 static struct smc91c111_pdata smsc91x_pdata = {
 	.word_aligned_short_writes = true,
diff --git a/arch/arm/boards/mainstone/lowlevel.c b/arch/arm/boards/mainstone/lowlevel.c
index 31f9d76513..29d12f7424 100644
--- a/arch/arm/boards/mainstone/lowlevel.c
+++ b/arch/arm/boards/mainstone/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <io.h>
@@ -5,8 +7,8 @@
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <linux/sizes.h>
-#include <mach/pxa-regs.h>
-#include <mach/regs-ost.h>
+#include <mach/pxa/pxa-regs.h>
+#include <mach/pxa/regs-ost.h>
 
 /*
  * Memory settings
diff --git a/arch/arm/boards/marvell-armada-xp-db/Makefile b/arch/arm/boards/marvell-armada-xp-db/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/marvell-armada-xp-db/Makefile
+++ b/arch/arm/boards/marvell-armada-xp-db/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/marvell-armada-xp-db/lowlevel.c b/arch/arm/boards/marvell-armada-xp-db/lowlevel.c
index 4752bbf1b4..14059fe8c5 100644
--- a/arch/arm/boards/marvell-armada-xp-db/lowlevel.c
+++ b/arch/arm/boards/marvell-armada-xp-db/lowlevel.c
@@ -7,13 +7,13 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 #include <io.h>
 
 extern char __dtb_armada_xp_db_bb_start[];
 
-ENTRY_FUNCTION(start_marvell_armada_xp_db, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_marvell_armada_xp_db, r0, r1, r2)
 {
 	void *fdt;
 	uint32_t reg;
diff --git a/arch/arm/boards/marvell-armada-xp-gp/Makefile b/arch/arm/boards/marvell-armada-xp-gp/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/marvell-armada-xp-gp/Makefile
+++ b/arch/arm/boards/marvell-armada-xp-gp/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c
index 43b1ba8c9a..ae5ad2822a 100644
--- a/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c
+++ b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c
@@ -4,12 +4,12 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 
 extern char __dtb_armada_xp_gp_bb_start[];
 
-ENTRY_FUNCTION(start_marvell_armada_xp_gp, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_marvell_armada_xp_gp, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/meerkat96/Makefile b/arch/arm/boards/meerkat96/Makefile
new file mode 100644
index 0000000000..5678718188
--- /dev/null
+++ b/arch/arm/boards/meerkat96/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/meerkat96/board.c b/arch/arm/boards/meerkat96/board.c
new file mode 100644
index 0000000000..49e9c06f78
--- /dev/null
+++ b/arch/arm/boards/meerkat96/board.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <of.h>
+#include <deep-probe.h>
+
+static const struct of_device_id meerkat96_match[] = {
+	{ .compatible = "novtech,imx7d-meerkat96" },
+	{ /* Sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(meerkat96_match);
diff --git a/arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg b/arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg
new file mode 100644
index 0000000000..a49b816178
--- /dev/null
+++ b/arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ */
+
+soc imx7
+loadaddr 0x80000000
+ivtofs 0x400
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable OCRAM EPDC */
+wm 32 0x30340004 0x4F400005
+
+/* =============================================================================
+ * DDR Controller Registers
+ * =============================================================================
+ * Memory type:           DDR3
+ * Manufacturer:          ISSI
+ * Device Part Number:    IS43TR16256AL-125KBL
+ * Clock Freq.:           533MHz
+ * Density per CS in Gb:  4
+ * Chip Selects used:     1
+ * Number of Banks:       8
+ * Row address:          15
+ * Column address:       10
+ * Data bus width:       16
+ * ROW-BANK interleave:  ENABLED
+ * =============================================================================
+ */
+
+wm 32 0x30391000 0x00000002    // deassert presetn
+wm 32 0x307A0000 0x01041001    // DDRC_MSTR
+wm 32 0x307A0064 0x00400046    // DDRC_RFSHTMG
+wm 32 0x307a0490 0x00000001    // DDRC_PCTRL_0
+wm 32 0x307A00D4 0x00690000    // DDRC_INIT1
+wm 32 0x307A00D0 0x00020083    // DDRC_INIT0
+wm 32 0x307A00DC 0x09300004    // DDRC_INIT3
+wm 32 0x307A00E0 0x04080000    // DDRC_INIT4
+wm 32 0x307A00E4 0x00100004    // DDRC_INIT5
+wm 32 0x307A00F4 0x0000033F    // DDRC_RANKCTL
+wm 32 0x307A0100 0x090B1109    // DDRC_DRAMTMG0
+wm 32 0x307A0104 0x0007020D    // DDRC_DRAMTMG1
+wm 32 0x307A0108 0x03040407    // DDRC_DRAMTMG2
+wm 32 0x307A010C 0x00002006    // DDRC_DRAMTMG3
+wm 32 0x307A0110 0x04020205    // DDRC_DRAMTMG4
+wm 32 0x307A0114 0x03030202    // DDRC_DRAMTMG5
+wm 32 0x307A0120 0x00000803    // DDRC_DRAMTMG8
+wm 32 0x307A0180 0x00800020    // DDRC_ZQCTL0
+wm 32 0x307A0190 0x02098204    // DDRC_DFITMG0
+wm 32 0x307A0194 0x00030303    // DDRC_DFITMG1
+wm 32 0x307A01A0 0x80400003    // DDRC_DFIUPD0
+wm 32 0x307A01A4 0x00100020    // DDRC_DFIUPD1
+wm 32 0x307A01A8 0x80100004    // DDRC_DFIUPD2
+wm 32 0x307A0200 0x00000015    // DDRC_ADDRMAP0
+wm 32 0x307A0204 0x00070707    // DDRC_ADDRMAP1
+wm 32 0x307A0210 0x00000F0F    // DDRC_ADDRMAP4
+wm 32 0x307A0214 0x06060606    // DDRC_ADDRMAP5
+wm 32 0x307A0218 0x0F060606    // DDRC_ADDRMAP6
+wm 32 0x307A0240 0x06000604    // DDRC_ODTCFG
+wm 32 0x307A0244 0x00000001    // DDRC_ODTMAP
+
+
+/* =============================================================================
+ * PHY Control Register
+ * =============================================================================
+ */
+
+wm 32 0x30391000 0x00000000    // deassert presetn
+wm 32 0x30790000 0x17420F40    // DDR_PHY_PHY_CON0
+wm 32 0x30790004 0x10210100    // DDR_PHY_PHY_CON1
+wm 32 0x30790010 0x00060807    // DDR_PHY_PHY_CON4
+wm 32 0x307900B0 0x1010007E    // DDR_PHY_MDLL_CON0
+wm 32 0x3079009C 0x00000D6E    // DDR_PHY_DRVDS_CON0
+wm 32 0x30790030 0x08080808    // DDR_PHY_OFFSET_WR_CON0
+wm 32 0x30790020 0x08080808    // DDR_PHY_OFFSET_RD_CON0
+wm 32 0x30790050 0x01000010    // DDR_PHY_OFFSETD_CON0
+wm 32 0x30790050 0x00000010    // DDR_PHY_OFFSETD_CON0
+wm 32 0x30790018 0x0000000F    // DDR_PHY_LP_CON0
+wm 32 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - Start Manual ZQ
+wm 32 0x307900C0 0x0E447304
+wm 32 0x307900C0 0x0E447306
+wm 32 0x307900C0 0x0E447304    // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
+wm 32 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - End Manual ZQ
+
+
+/* =============================================================================
+ * Final Initialization start sequence
+ * =============================================================================
+ */
+
+wm 32 0x30384130 0x00000000    // Disable Clock
+wm 32 0x30340020 0x00000178    // IOMUX_GRP_GRP8 - Start input to PHY
+wm 32 0x30384130 0x00000002    // Enable Clock
+/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */
diff --git a/arch/arm/boards/meerkat96/lowlevel.c b/arch/arm/boards/meerkat96/lowlevel.c
new file mode 100644
index 0000000000..03a1a11466
--- /dev/null
+++ b/arch/arm/boards/meerkat96/lowlevel.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <debug_ll.h>
+#include <io.h>
+#include <linux/sizes.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/iomux-mx7.h>
+#include <mach/imx/imx7-ccm-regs.h>
+#include <mach/imx/generic.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
+extern char __dtb_z_imx7d_meerkat96_start[];
+
+static void setup_uart(void)
+{
+	/* FIXME: Below UART6 is muxed, not UART1 */
+	imx7_early_setup_uart_clock(1);
+	imx7_setup_pad(MX7D_PAD_SD1_WP__UART6_DCE_TX);
+	imx7_uart_setup_ll();
+	putc_ll('>');
+}
+
+ENTRY_FUNCTION_WITHSTACK(start_imx7d_meerkat96, 0, r0, r1, r2)
+{
+	void *fdt;
+
+	imx7_cpu_lowlevel_init();
+
+	setup_uart();
+
+	fdt = __dtb_z_imx7d_meerkat96_start + get_runtime_offset();
+
+	barebox_arm_entry(0x80000000, SZ_512M, fdt);
+}
diff --git a/arch/arm/boards/microchip-ksz9477-evb/Makefile b/arch/arm/boards/microchip-ksz9477-evb/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/Makefile
+++ b/arch/arm/boards/microchip-ksz9477-evb/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
index 93ae481975..aa2161daee 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
+++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
@@ -9,11 +9,11 @@
 
 #include <asm/barebox-arm-head.h>
 #include <debug_ll.h>
-#include <mach/barebox-arm.h>
-#include <mach/iomux.h>
-#include <mach/sama5d3.h>
-#include <mach/sama5d3-xplained-ddramc.h>
-#include <mach/xload.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/sama5d3.h>
+#include <mach/at91/sama5d3-xplained-ddramc.h>
+#include <mach/at91/xload.h>
 
 /* PCK = 528MHz, MCK = 132MHz */
 #define MASTER_CLOCK	132000000
@@ -32,7 +32,7 @@ static void dbgu_init(void)
 	putc_ll('>');
 }
 
-SAMA5_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071_xload_mmc, r4)
+SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071_xload_mmc, r4)
 {
 	sama5d3_lowlevel_init();
 
@@ -49,16 +49,14 @@ SAMA5_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071_xload_mmc, r4)
 
 extern char __dtb_z_at91_microchip_ksz9477_evb_start[];
 
-SAMA5_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r4)
+SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r4)
 {
 	void *fdt;
 
-	arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE);
-
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		dbgu_init();
 
 	fdt = __dtb_z_at91_microchip_ksz9477_evb_start + get_runtime_offset();
 
-	barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
+	sama5d3_barebox_entry(r4, fdt);
 }
diff --git a/arch/arm/boards/microchip-sama5d3-eds/Makefile b/arch/arm/boards/microchip-sama5d3-eds/Makefile
new file mode 100644
index 0000000000..458f520900
--- /dev/null
+++ b/arch/arm/boards/microchip-sama5d3-eds/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/microchip-sama5d3-eds/lowlevel.c b/arch/arm/boards/microchip-sama5d3-eds/lowlevel.c
new file mode 100644
index 0000000000..79346a9b6a
--- /dev/null
+++ b/arch/arm/boards/microchip-sama5d3-eds/lowlevel.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
+/*
+ * Copyright (C) 2014, Atmel Corporation
+ * Copyright (C) 2018 Ahmad Fatoum, Pengutronix
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/barebox-arm-head.h>
+#include <debug_ll.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/sama5d3.h>
+#include <mach/at91/sama5d3-xplained-ddramc.h>
+#include <mach/at91/xload.h>
+
+/* PCK = 528MHz, MCK = 132MHz */
+#define MASTER_CLOCK	132000000
+
+static void dbgu_init(void)
+{
+	void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
+
+	sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB);
+
+	at91_mux_pio3_pin(pio, pin_to_mask(AT91_PIN_PB31), AT91_MUX_PERIPH_A, 0);
+
+	sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU);
+	at91_dbgu_setup_ll(IOMEM(AT91_BASE_DBGU1), MASTER_CLOCK, 115200);
+
+	putc_ll('>');
+}
+
+SAMA5D3_ENTRY_FUNCTION(start_microchip_sama5d3_eds_xload_mmc, r4)
+{
+	sama5d3_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	sama5d3_udelay_init(MASTER_CLOCK);
+	sama5d3_xplained_ddrconf();
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		dbgu_init();
+
+	sama5d3_atmci_start_image(0, MASTER_CLOCK, 0);
+}
+
+extern char __dtb_z_at91_microchip_sama5d3_eds_start[];
+
+SAMA5D3_ENTRY_FUNCTION(start_microchip_sama5d3_eds, r4)
+{
+	void *fdt;
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		dbgu_init();
+
+	fdt = __dtb_z_at91_microchip_sama5d3_eds_start + get_runtime_offset();
+
+	sama5d3_barebox_entry(r4, fdt);
+}
diff --git a/arch/arm/boards/mioa701/Makefile b/arch/arm/boards/mioa701/Makefile
index 3072706237..bf17869fb2 100644
--- a/arch/arm/boards/mioa701/Makefile
+++ b/arch/arm/boards/mioa701/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o gpio0_poweroff.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/mioa701/board.c b/arch/arm/boards/mioa701/board.c
index 963fefbf77..685c78611b 100644
--- a/arch/arm/boards/mioa701/board.c
+++ b/arch/arm/boards/mioa701/board.c
@@ -6,20 +6,19 @@
 #include <environment.h>
 #include <fs.h>
 #include <init.h>
-#include <partition.h>
 #include <led.h>
 #include <gpio.h>
 #include <pwm.h>
 
-#include <mach/devices.h>
-#include <mach/mfp-pxa27x.h>
-#include <mach/pxa-regs.h>
-#include <mach/udc_pxa2xx.h>
-#include <mach/mci_pxa2xx.h>
+#include <mach/pxa/devices.h>
+#include <mach/pxa/mfp-pxa27x.h>
+#include <mach/pxa/pxa-regs.h>
+#include <mach/pxa/udc_pxa2xx.h>
+#include <mach/pxa/mci_pxa2xx.h>
 
 #include <asm/armlinux.h>
 #include <asm/io.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <asm/mmu.h>
 
 #include "mioa701.h"
diff --git a/arch/arm/boards/mioa701/lowlevel.c b/arch/arm/boards/mioa701/lowlevel.c
index ee0546ea63..6116990402 100644
--- a/arch/arm/boards/mioa701/lowlevel.c
+++ b/arch/arm/boards/mioa701/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
diff --git a/arch/arm/boards/mnt-reform/Makefile b/arch/arm/boards/mnt-reform/Makefile
index a3da88fbe6..35d8640087 100644
--- a/arch/arm/boards/mnt-reform/Makefile
+++ b/arch/arm/boards/mnt-reform/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
-lwl-y += lowlevel.o lpddr4-timing.o
\ No newline at end of file
+lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/mnt-reform/board.c b/arch/arm/boards/mnt-reform/board.c
index feb874c0a0..8b56d108e6 100644
--- a/arch/arm/boards/mnt-reform/board.c
+++ b/arch/arm/boards/mnt-reform/board.c
@@ -5,10 +5,11 @@
 
 #include <bootsource.h>
 #include <common.h>
+#include <deep-probe.h>
 #include <init.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
-static int mnt_reform_probe(struct device_d *dev)
+static int mnt_reform_probe(struct device *dev)
 {
 	int emmc_bbu_flag = 0;
 	int sd_bbu_flag = 0;
@@ -31,8 +32,9 @@ static const struct of_device_id mnt_reform_of_match[] = {
 	{ .compatible = "mntre,reform2"},
 	{ /* sentinel */ },
 };
+BAREBOX_DEEP_PROBE_ENABLE(mnt_reform_of_match);
 
-static struct driver_d mnt_reform_board_driver = {
+static struct driver mnt_reform_board_driver = {
 	.name = "board-mnt-reform",
 	.probe = mnt_reform_probe,
 	.of_compatible = DRV_OF_COMPAT(mnt_reform_of_match),
diff --git a/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg b/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg
index 80ce03e22c..f82759f849 100644
--- a/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg
+++ b/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg
@@ -1,6 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx8mq
 
 loadaddr 0x007E1000
 max_load_size 0x3F000
 ivtofs 0x400
-#include <mach/habv4-imx8-gencsf.h>
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/mnt-reform/lowlevel.c b/arch/arm/boards/mnt-reform/lowlevel.c
index 268dfb611a..9f951508df 100644
--- a/arch/arm/boards/mnt-reform/lowlevel.c
+++ b/arch/arm/boards/mnt-reform/lowlevel.c
@@ -6,19 +6,21 @@
 #include <asm/barebox-arm.h>
 #include <common.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <firmware.h>
-#include <i2c/i2c-early.h>
-#include <mach/atf.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
-#include <mach/imx-gpio.h>
-#include <mach/imx8m-ccm-regs.h>
-#include <mach/imx8mq-regs.h>
-#include <mach/iomux-mx8mq.h>
-#include <mach/xload.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx-gpio.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/imx8mq-regs.h>
+#include <mach/imx/iomux-mx8mq.h>
+#include <mach/imx/xload.h>
 #include <soc/imx8m/ddr.h>
 
-extern char __dtb_imx8mq_mnt_reform2_start[];
+extern char __dtb_z_imx8mq_mnt_reform2_start[];
 
 #define UART_PAD_CTRL	MUX_PAD_CTRL(MX8MQ_PAD_CTL_DSE_65R)
 
@@ -36,7 +38,7 @@ static void mnt_reform_setup_uart(void)
 	putc_ll('>');
 }
 
-static void i2c_mux_set(void *i2c, u8 channel)
+static void i2c_mux_set(struct pbl_i2c *i2c, u8 channel)
 {
 	int ret;
 	u8 buf[1];
@@ -50,29 +52,14 @@ static void i2c_mux_set(void *i2c, u8 channel)
 
 	buf[0] = 1 << channel;
 
-	ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
+	ret = pbl_i2c_xfer(i2c, msgs, ARRAY_SIZE(msgs));
 	if (ret != 1)
 		pr_err("failed to set i2c mux\n");
 }
 
-static void i2c_regulator_set_voltage(void *i2c, u8 reg, u8 voffs)
+static void i2c_regulator_set_voltage(struct pbl_i2c *i2c, u8 reg, u8 voffs)
 {
-	int ret;
-	u8 buf[2];
-	struct i2c_msg msgs[] = {
-		{
-			.addr = 0x60,
-			.buf = buf,
-			.len = 2,
-		},
-	};
-
-	buf[0] = reg;
-	buf[1] = 0x80 + voffs;
-
-	ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
-	if (ret != 1)
-		pr_err("failed to set voltage\n");
+	pmic_reg_write8(i2c, 0x60, reg, 0x80 + voffs);
 }
 
 #define I2C_PAD_CTRL	MUX_PAD_CTRL(MX8MQ_PAD_CTL_DSE_45R | \
@@ -81,7 +68,7 @@ static void i2c_regulator_set_voltage(void *i2c, u8 reg, u8 voffs)
 
 static void mnt_reform_init_power(void)
 {
-	void *i2c;
+	struct pbl_i2c *i2c;
 
 	imx8mq_setup_pad(IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
 	imx8mq_setup_pad(IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
@@ -130,50 +117,19 @@ static __noreturn noinline void mnt_reform_start(void)
 	 * The TF-A will then jump to DRAM in EL2.
 	 */
 	if (current_el() == 3) {
-		size_t bl31_size;
-		const u8 *bl31;
-		enum bootsource src;
-		int instance;
-
 		mnt_reform_setup_uart();
 
 		mnt_reform_init_power();
 
-		imx8mq_ddr_init(&mnt_reform_dram_timing);
-
-		imx8mq_get_boot_source(&src, &instance);
-		switch (src) {
-		case BOOTSOURCE_MMC:
-			imx8m_esdhc_load_image(instance, false);
-			break;
-		case BOOTSOURCE_SERIAL:
-			imx8m_esdhc_load_image(1, false);
-			break;
-		default:
-			printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
-			hang();
-		}
-
-		/*
-		 * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
-		 * in EL2. Copy the image there, but replace the PBL part of
-		 * that image with ourselves. On a high assurance boot only the
-		 * currently running code is validated and contains the checksum
-		 * for the piggy data, so we need to ensure that we are running
-		 * the same code in DRAM.
-		 */
-		memcpy((void *)MX8M_ATF_BL33_BASE_ADDR,
-		       __image_start, barebox_pbl_size);
-
-		get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size);
-
-		imx8mq_atf_load_bl31(bl31, bl31_size);
+		imx8mq_ddr_init(&mnt_reform_dram_timing, DRAM_TYPE_LPDDR4);
+
+		imx8mq_load_and_start_image_via_tfa();
 	}
 
 	/*
 	 * Standard entry we hit once we initialized both DDR and ATF
 	 */
-	imx8mq_barebox_entry(__dtb_imx8mq_mnt_reform2_start);
+	imx8mq_barebox_entry(__dtb_z_imx8mq_mnt_reform2_start);
 }
 
 ENTRY_FUNCTION(start_mnt_reform, r0, r1, r2)
diff --git a/arch/arm/boards/module-mb7707/Makefile b/arch/arm/boards/module-mb7707/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/module-mb7707/Makefile
+++ b/arch/arm/boards/module-mb7707/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/module-mb7707/board.c b/arch/arm/boards/module-mb7707/board.c
index c4f78a8135..366baddf81 100644
--- a/arch/arm/boards/module-mb7707/board.c
+++ b/arch/arm/boards/module-mb7707/board.c
@@ -6,8 +6,8 @@
 #include <common.h>
 #include <init.h>
 #include <driver.h>
-#include <usb/ehci.h>
-#include <mach/hardware.h>
+#include <linux/usb/ehci.h>
+#include <mach/uemd/hardware.h>
 
 static int hostname_init(void)
 {
diff --git a/arch/arm/boards/myirtech-x335x/Makefile b/arch/arm/boards/myirtech-x335x/Makefile
new file mode 100644
index 0000000000..05d9fc7bc3
--- /dev/null
+++ b/arch/arm/boards/myirtech-x335x/Makefile
@@ -0,0 +1,3 @@
+lwl-y					+= lowlevel.o
+obj-y					+= board.o
+bbenv-$(CONFIG_DEFAULT_ENVIRONMENT)	+= defaultenv-myirtech-x335x
diff --git a/arch/arm/boards/myirtech-x335x/board.c b/arch/arm/boards/myirtech-x335x/board.c
new file mode 100644
index 0000000000..82bb612032
--- /dev/null
+++ b/arch/arm/boards/myirtech-x335x/board.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> */
+
+#include <bootsource.h>
+#include <common.h>
+#include <driver.h>
+#include <envfs.h>
+#include <init.h>
+#include <linux/sizes.h>
+#include <mach/omap/am33xx-generic.h>
+
+static struct omap_barebox_part myir_barebox_part = {
+	.nand_offset = SZ_128K * 4,
+	.nand_size = SZ_1M,
+};
+
+static __init int myir_devices_init(void)
+{
+	if (!of_machine_is_compatible("myir,myc-am335x"))
+		return 0;
+
+	am33xx_register_ethaddr(0, 0);
+	am33xx_register_ethaddr(1, 1);
+
+	switch (bootsource_get()) {
+	case BOOTSOURCE_MMC:
+		omap_set_bootmmc_devname("mmc0");
+		break;
+	case BOOTSOURCE_NAND:
+		omap_set_barebox_part(&myir_barebox_part);
+		break;
+	default:
+		break;
+	}
+
+	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT))
+		defaultenv_append_directory(defaultenv_myirtech_x335x);
+
+	if (IS_ENABLED(CONFIG_SHELL_NONE))
+		return am33xx_of_register_bootdevice();
+
+	return 0;
+}
+coredevice_initcall(myir_devices_init);
diff --git a/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/boot/nand b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/boot/nand
new file mode 100644
index 0000000000..c000041095
--- /dev/null
+++ b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/boot/nand
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+global.bootm.image="/dev/nand0.system.ubi.kernel"
+global.linux.bootargs.dyn.root="ubi.mtd=system ubi.block=0,root root=fe00 ro"
diff --git a/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/nv/boot.default b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/nv/boot.default
new file mode 100644
index 0000000000..026a25cc7e
--- /dev/null
+++ b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/nv/boot.default
@@ -0,0 +1 @@
+nand
diff --git a/arch/arm/boards/myirtech-x335x/lowlevel.c b/arch/arm/boards/myirtech-x335x/lowlevel.c
new file mode 100644
index 0000000000..0ac2370e57
--- /dev/null
+++ b/arch/arm/boards/myirtech-x335x/lowlevel.c
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> */
+
+#include <common.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <debug_ll.h>
+#include <mach/omap/debug_ll.h>
+#include <init.h>
+#include <linux/sizes.h>
+#include <mach/omap/am33xx-clock.h>
+#include <mach/omap/am33xx-generic.h>
+#include <mach/omap/am33xx-mux.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/sys_info.h>
+
+#define AM335X_ZCZ_1000		0x1c2f
+
+static const struct am33xx_ddr_data ddr3_data = {
+	.rd_slave_ratio0	= 0x38,
+	.wr_dqs_slave_ratio0	= 0x44,
+	.fifo_we_slave_ratio0	= 0x94,
+	.wr_slave_ratio0	= 0x7d,
+	.use_rank0_delay	= 0x01,
+	.dll_lock_diff0		= 0x00,
+};
+
+static const struct am33xx_cmd_control ddr3_cmd_ctrl = {
+	.slave_ratio0	= 0x80,
+	.dll_lock_diff0	= 0x01,
+	.invert_clkout0	= 0x00,
+	.slave_ratio1	= 0x80,
+	.dll_lock_diff1	= 0x01,
+	.invert_clkout1	= 0x00,
+	.slave_ratio2	= 0x80,
+	.dll_lock_diff2	= 0x01,
+	.invert_clkout2	= 0x00,
+};
+
+/* CPU module contains 512MB (2*256MB) DDR3 SDRAM (2*128MB compatible),
+ * so we configure EMIF for 512MB then detect real size of memory.
+ */
+static struct am33xx_emif_regs ddr3_regs = {
+	.emif_read_latency	= 0x00100007,
+	.emif_tim1		= 0x0aaad4db,
+	.emif_tim2		= 0x266b7fda,
+	.emif_tim3		= 0x501f867f,
+	.zq_config		= 0x50074be4,
+	/* MT41K256M8DA */
+	.sdram_config		= 0x61c05332,
+	.sdram_config2		= 0x00,
+	.sdram_ref_ctrl		= 0xc30,
+};
+
+extern char __dtb_z_am335x_myirtech_myd_start[];
+
+ENTRY_FUNCTION(start_am33xx_myirtech_sram, bootinfo, r1, r2)
+{
+	int mpupll;
+	void *fdt;
+
+	am33xx_save_bootinfo((void *)bootinfo);
+
+	arm_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	fdt = __dtb_z_am335x_myirtech_myd_start;
+
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
+
+	mpupll = MPUPLL_M_800;
+	if (am33xx_get_cpu_rev() == AM335X_ES2_1) {
+		u32 deviceid = readl(AM33XX_EFUSE_SMA) & 0x1fff;
+		if (deviceid == AM335X_ZCZ_1000)
+			mpupll = MPUPLL_M_1000;
+	}
+
+	am33xx_pll_init(mpupll, DDRPLL_M_400);
+
+	am335x_sdram_init(0x18b, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data);
+
+	if (get_ram_size((void *)AM33XX_DRAM_ADDR_SPACE_START, SZ_512M) < SZ_512M) {
+		/* MT41K128M8DA */
+		ddr3_regs.sdram_config = 0x61c04ab2;
+		am335x_sdram_init(0x18b, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data);
+	}
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
+		am33xx_uart_soft_reset(IOMEM(AM33XX_UART0_BASE));
+		am33xx_enable_uart0_pin_mux();
+		omap_debug_ll_init();
+		putc_ll('>');
+	}
+
+	am335x_barebox_entry(fdt);
+}
+
+ENTRY_FUNCTION(start_am33xx_myirtech_sdram, r0, r1, r2)
+{
+	void *fdt;
+
+	fdt = __dtb_z_am335x_myirtech_myd_start;
+
+	fdt += get_runtime_offset();
+
+	am335x_barebox_entry(fdt);
+}
diff --git a/arch/arm/boards/netgear-rn104/Makefile b/arch/arm/boards/netgear-rn104/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/netgear-rn104/Makefile
+++ b/arch/arm/boards/netgear-rn104/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/netgear-rn104/lowlevel.c b/arch/arm/boards/netgear-rn104/lowlevel.c
index 8a53615018..e693d13993 100644
--- a/arch/arm/boards/netgear-rn104/lowlevel.c
+++ b/arch/arm/boards/netgear-rn104/lowlevel.c
@@ -1,15 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 /*
  * Copyright (C) 2014  Uwe Kleine-Koenig <uwe@kleine-koenig.org>
  */
 
 #include <common.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 
 extern char __dtb_armada_370_rn104_bb_start[];
 
-ENTRY_FUNCTION(start_netgear_rn104, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_netgear_rn104, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/netgear-rn2120/Makefile b/arch/arm/boards/netgear-rn2120/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/netgear-rn2120/Makefile
+++ b/arch/arm/boards/netgear-rn2120/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/netgear-rn2120/board.c b/arch/arm/boards/netgear-rn2120/board.c
index caf106af50..8689202ba6 100644
--- a/arch/arm/boards/netgear-rn2120/board.c
+++ b/arch/arm/boards/netgear-rn2120/board.c
@@ -1,11 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <clock.h>
 #include <init.h>
 #include <of.h>
 #include <gpio.h>
-#include <printk.h>
+#include <linux/printk.h>
 #include <linux/kernel.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 
 static int rn2120_init(void)
 {
diff --git a/arch/arm/boards/netgear-rn2120/lowlevel.c b/arch/arm/boards/netgear-rn2120/lowlevel.c
index c78d3644b5..f923be5a27 100644
--- a/arch/arm/boards/netgear-rn2120/lowlevel.c
+++ b/arch/arm/boards/netgear-rn2120/lowlevel.c
@@ -3,14 +3,14 @@
 
 #include <common.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
+#include <mach/mvebu/barebox-arm-head.h>
 #include <asm/io.h>
-#include <mach/lowlevel.h>
-#include <mach/common.h>
+#include <mach/mvebu/lowlevel.h>
+#include <mach/mvebu/common.h>
 
 extern char __dtb_armada_xp_rn2120_bb_start[];
 
-ENTRY_FUNCTION(start_netgear_rn2120, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_netgear_rn2120, r0, r1, r2)
 {
 	void *fdt;
 	void __iomem *base = mvebu_get_initial_int_reg_base();
diff --git a/arch/arm/boards/nhk8815/Makefile b/arch/arm/boards/nhk8815/Makefile
index 56f2013e22..0367fa7dd5 100644
--- a/arch/arm/boards/nhk8815/Makefile
+++ b/arch/arm/boards/nhk8815/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += setup.o
 lwl-y += lowlevel.o
 bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-nhk8815
diff --git a/arch/arm/boards/nhk8815/lowlevel.c b/arch/arm/boards/nhk8815/lowlevel.c
index a9ccf1fff5..9ba5bbffad 100644
--- a/arch/arm/boards/nhk8815/lowlevel.c
+++ b/arch/arm/boards/nhk8815/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
diff --git a/arch/arm/boards/nhk8815/setup.c b/arch/arm/boards/nhk8815/setup.c
index ed32218ac8..c7a2afdbfe 100644
--- a/arch/arm/boards/nhk8815/setup.c
+++ b/arch/arm/boards/nhk8815/setup.c
@@ -5,17 +5,16 @@
 #include <init.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
-#include <partition.h>
 #include <nand.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <io.h>
 #include <envfs.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/nand.h>
-#include <mach/fsmc.h>
+#include <mach/nomadik/hardware.h>
+#include <mach/nomadik/board.h>
+#include <mach/nomadik/nand.h>
+#include <mach/nomadik/fsmc.h>
 
 static int nhk8815_nand_init(void)
 {
@@ -53,7 +52,7 @@ static struct resource nhk8815_nand_resources[] = {
 	}
 };
 
-static struct device_d nhk8815_nand_device = {
+static struct device nhk8815_nand_device = {
 	.id		= DEVICE_ID_DYNAMIC,
 	.name		= "nomadik_nand",
 	.num_resources	= ARRAY_SIZE(nhk8815_nand_resources),
diff --git a/arch/arm/boards/novena/Makefile b/arch/arm/boards/novena/Makefile
new file mode 100644
index 0000000000..3111392bf9
--- /dev/null
+++ b/arch/arm/boards/novena/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/novena/board.c b/arch/arm/boards/novena/board.c
new file mode 100644
index 0000000000..b6c59aff44
--- /dev/null
+++ b/arch/arm/boards/novena/board.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2023 John Watts <contact@jookia.org>
+
+#include <common.h>
+#include <deep-probe.h>
+#include <fs.h>
+#include <libfile.h>
+#include <net.h>
+
+struct novena_eeprom {
+	uint8_t signature[6]; /* 'Novena' */
+	uint8_t version; /* 1 or 2, not checked */
+	uint8_t page_size; /* v2 only: EEPROM read/write page */
+	uint32_t serial; /* 32-bit serial number */
+	uint8_t mac[6]; /* Gigabit MAC address */
+	uint16_t features; /* features */
+	/* ... extra fields omitted ... */
+} __packed;
+
+static void power_on_audio_codec(void)
+{
+	int rc = of_devices_ensure_probed_by_name("regulator-audio-codec");
+
+	if (rc < 0)
+		pr_err("Unable to power on audio codec: %s\n", strerror(-rc));
+}
+
+static struct novena_eeprom *novena_read_eeprom(void)
+{
+	size_t read;
+	loff_t max = sizeof(struct novena_eeprom);
+	void *eeprom;
+	int rc;
+
+	/*
+	 * When powered off the audio codec pulls down the EEPROM's I2C line.
+	 * Power it on so we can actually read data.
+	 */
+	power_on_audio_codec();
+
+	rc = of_device_ensure_probed_by_alias("eeprom0");
+	if (rc < 0) {
+		pr_err("Unable to probe eeprom0: %s\n", strerror(-rc));
+		return NULL;
+	}
+
+	rc = read_file_2("/dev/eeprom0", &read, &eeprom, max);
+
+	if (rc < 0 && rc != -EFBIG) {
+		pr_err("Unable to read Novena EEPROM: %s\n", strerror(-rc));
+		return NULL;
+	} else if (read != max) {
+		pr_err("Short read from Novena EEPROM?\n");
+		free(eeprom);
+		return NULL;
+	}
+
+	return eeprom;
+}
+
+static bool novena_check_eeprom(struct novena_eeprom *eeprom)
+{
+	char *sig = eeprom->signature;
+	size_t size = sizeof(eeprom->signature);
+
+	if (memcmp("Novena", sig, size) != 0) {
+		pr_err("Unknown Novena EEPROM signature\n");
+		return false;
+	}
+
+	return true;
+}
+
+static void novena_set_mac(struct novena_eeprom *eeprom)
+{
+	struct device_node *dnode;
+
+	dnode = of_find_node_by_alias(of_get_root_node(), "ethernet0");
+	if (dnode)
+		of_eth_register_ethaddr(dnode, eeprom->mac);
+	else
+		pr_err("Unable to find ethernet node\n");
+}
+
+static int novena_probe(struct device *dev)
+{
+	struct novena_eeprom *eeprom = novena_read_eeprom();
+
+	if (eeprom && novena_check_eeprom(eeprom))
+		novena_set_mac(eeprom);
+
+	free(eeprom);
+
+	return 0;
+}
+
+static const struct of_device_id novena_of_match[] = {
+	{ .compatible = "kosagi,imx6q-novena", },
+	{ /* sentinel */ }
+};
+
+static struct driver novena_board_driver = {
+	.name = "board-novena",
+	.probe = novena_probe,
+	.of_compatible = novena_of_match,
+};
+coredevice_platform_driver(novena_board_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(novena_of_match);
diff --git a/arch/arm/boards/novena/ddr_regs.h b/arch/arm/boards/novena/ddr_regs.h
new file mode 100644
index 0000000000..5f18d5e0e4
--- /dev/null
+++ b/arch/arm/boards/novena/ddr_regs.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-FileCopyrightText: 2014 Marek Vasut <marex@denx.de> */
+
+#ifndef NOVENA_DDR_REGS_H
+#define NOVENA_DDR_REGS_H
+
+/* MEMORY CONTROLLER CONFIGURATION */
+
+static struct mx6dq_iomux_ddr_regs novena_ddr_regs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0		= 0x00020038,
+	.dram_sdclk_1		= 0x00020038,
+	.dram_cas		= 0x00000038,
+	.dram_ras		= 0x00000038,
+	.dram_reset		= 0x00000038,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0		= 0x00003000,
+	.dram_sdcke1		= 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2		= 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0		= 0x00000038,
+	.dram_sdodt1		= 0x00000038,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0		= 0x00000038,
+	.dram_sdqs1		= 0x00000038,
+	.dram_sdqs2		= 0x00000038,
+	.dram_sdqs3		= 0x00000038,
+	.dram_sdqs4		= 0x00000038,
+	.dram_sdqs5		= 0x00000038,
+	.dram_sdqs6		= 0x00000038,
+	.dram_sdqs7		= 0x00000038,
+
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0		= 0x00000038,
+	.dram_dqm1		= 0x00000038,
+	.dram_dqm2		= 0x00000038,
+	.dram_dqm3		= 0x00000038,
+	.dram_dqm4		= 0x00000038,
+	.dram_dqm5		= 0x00000038,
+	.dram_dqm6		= 0x00000038,
+	.dram_dqm7		= 0x00000038,
+};
+
+static struct mx6dq_iomux_grp_regs novena_grp_regs = {
+	/* DDR3 */
+	.grp_ddr_type		= 0x000c0000,
+	.grp_ddrmode_ctl	= 0x00020000,
+	/* Disable DDR pullups */
+	.grp_ddrpke		= 0x00000000,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds		= 0x00000038,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds		= 0x00000038,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode		= 0x00020000,
+	.grp_b0ds		= 0x00000038,
+	.grp_b1ds		= 0x00000038,
+	.grp_b2ds		= 0x00000038,
+	.grp_b3ds		= 0x00000038,
+	.grp_b4ds		= 0x00000038,
+	.grp_b5ds		= 0x00000038,
+	.grp_b6ds		= 0x00000038,
+	.grp_b7ds		= 0x00000038,
+};
+
+/* MEMORY STICK CONFIGURATION */
+
+static struct mx6_mmdc_calibration novena_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0		= 0x00420048,
+	.p0_mpwldectrl1		= 0x006f0059,
+	.p1_mpwldectrl0		= 0x005a0104,
+	.p1_mpwldectrl1		= 0x01070113,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0		= 0x437c040b,
+	.p0_mpdgctrl1		= 0x0413040e,
+	.p1_mpdgctrl0		= 0x444f0446,
+	.p1_mpdgctrl1		= 0x044d0422,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl		= 0x4c424249,
+	.p1_mprddlctl		= 0x4e48414f,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl		= 0x42414641,
+	.p1_mpwrdlctl		= 0x46374b43,
+};
+
+static struct mx6_ddr_sysinfo novena_ddr_info = {
+	/* Width of data bus: 0=16, 1=32, 2=64 */
+	.dsize		= 2,
+	/* Config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,	/* 32Gb per CS */
+	/* Single chip select */
+	.ncs		= 1,
+	.cs1_mirror	= 0,
+	.rtt_wr		= 1,	/* RTT_Wr = RZQ/4 */
+	.rtt_nom	= 2,	/* RTT_Nom = RZQ/2 */
+	.walat		= 3,	/* Write additional latency */
+	.ralat		= 7,	/* Read additional latency */
+	.mif3_mode	= 3,	/* Command prediction working mode */
+	.bi_on		= 0,	/* Bank interleaving disabled */
+	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+};
+
+static struct mx6_ddr3_cfg novena_ddr_cfg = {
+	.mem_speed	= 1600,
+	.density	= 4,
+	.width		= 64,
+	.banks		= 8,
+	.rowaddr	= 16,
+	.coladdr	= 10,
+	.pagesz		= 1,
+	.trcd		= 1300,
+	.trcmin		= 4900,
+	.trasmin	= 3590,
+};
+
+#endif
diff --git a/arch/arm/boards/novena/flash-header-novena.imxcfg b/arch/arm/boards/novena/flash-header-novena.imxcfg
new file mode 100644
index 0000000000..0612542c19
--- /dev/null
+++ b/arch/arm/boards/novena/flash-header-novena.imxcfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+loadaddr 0x00907000
+soc imx6
+max_load_size 0x11000
+ivtofs 0x400
diff --git a/arch/arm/boards/novena/lowlevel.c b/arch/arm/boards/novena/lowlevel.c
new file mode 100644
index 0000000000..70aa92d5b4
--- /dev/null
+++ b/arch/arm/boards/novena/lowlevel.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2023 John Watts <contact@jookia.org>
+
+#include <asm/barebox-arm.h>
+#include <common.h>
+#include <ddr_dimms.h>
+#include <ddr_spd.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/imx6-mmdc.h>
+#include <mach/imx/iomux-mx6.h>
+#include <mach/imx/xload.h>
+#include <pbl/i2c.h>
+#include <soc/fsl/fsl_udc.h>
+#include "ddr_regs.h"
+
+#define STACK_TOP (MX6_OCRAM_BASE_ADDR + MX6_OCRAM_MAX_SIZE)
+
+extern char __dtb_z_imx6q_novena_start[];
+
+static struct spd_eeprom spd_eeprom;
+static struct dimm_params dimm_params;
+
+static struct pbl_i2c *setup_spd_i2c(void)
+{
+	void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+	void __iomem *i2c1base = IOMEM(MX6_I2C1_BASE_ADDR);
+
+	imx_setup_pad(iomuxbase, MX6Q_PAD_CSI0_DAT8__I2C1_SDA);
+	imx_setup_pad(iomuxbase, MX6Q_PAD_CSI0_DAT9__I2C1_SCL);
+
+	return imx6_i2c_early_init(i2c1base);
+}
+
+static struct spd_eeprom *read_spd(void)
+{
+	struct spd_eeprom *eeprom = &spd_eeprom;
+	struct pbl_i2c *i2c = setup_spd_i2c();
+	int rc;
+
+	rc = spd_read_eeprom(i2c, 0x50, eeprom, SPD_MEMTYPE_DDR3);
+	if (rc < 0) {
+		pr_err("Couldn't read SPD EEPROM: %i\n", rc);
+		return NULL;
+	}
+
+	rc = ddr3_spd_check(&eeprom->ddr3);
+	if (rc < 0) {
+		pr_err("Couldn't verify SPD data: %i\n", rc);
+		return NULL;
+	}
+
+	return eeprom;
+}
+
+static void setup_dimm_settings(struct dimm_params *params,
+				struct mx6_ddr_sysinfo *info,
+				struct mx6_ddr3_cfg *cfg)
+{
+	int capacity_gbit = params->capacity / 0x8000000;
+	int density_rank = capacity_gbit / params->n_ranks;
+
+	info->ncs = params->n_ranks;
+	info->cs_density = density_rank;
+	cfg->mem_speed = params->tckmin_x_ps;
+	cfg->density = density_rank / params->n_banks_per_sdram_device;
+	cfg->width = params->data_width;
+	cfg->banks = params->n_banks_per_sdram_device;
+	cfg->rowaddr = params->n_row_addr;
+	cfg->coladdr = params->n_col_addr;
+	cfg->trcd = params->trcd_ps / 10;
+	cfg->trcmin = params->trc_ps / 10;
+	cfg->trasmin = params->tras_ps / 10;
+	cfg->SRT = params->extended_op_srt;
+
+	if (params->device_width >= 16)
+		cfg->pagesz = 2;
+}
+
+static void read_dimm_settings(void)
+{
+	struct spd_eeprom *eeprom = read_spd();
+	struct dimm_params *params = &dimm_params;
+	int rc;
+
+	if (!eeprom) {
+		pr_err("Couldn't read SPD EEPROM, using default settings\n");
+		return;
+	}
+
+	rc = ddr3_compute_dimm_parameters(&eeprom->ddr3, params);
+	if (rc < 0) {
+		pr_err("Couldn't compute DIMM params: %i\n", rc);
+		return;
+	}
+
+	pr_info("Found DIMM: %s\n", params->mpart);
+
+	if (params->primary_sdram_width != 64) {
+		pr_err("ERROR: DIMM stick memory width is not 64 bits\n");
+		hang();
+	}
+
+	setup_dimm_settings(params, &novena_ddr_info, &novena_ddr_cfg);
+}
+
+static bool running_from_ram(void)
+{
+	return (get_pc() >= MX6_MMDC_PORT01_BASE_ADDR);
+}
+
+static void setup_uart(void)
+{
+	void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+	void __iomem *uart2base = IOMEM(MX6_UART2_BASE_ADDR);
+
+	/* NOTE: RX is needed for TX to work on this board */
+	imx_setup_pad(iomuxbase, MX6Q_PAD_EIM_D26__UART2_RXD);
+	imx_setup_pad(iomuxbase, MX6Q_PAD_EIM_D27__UART2_TXD);
+
+	imx6_uart_setup(uart2base);
+	pbl_set_putc(imx_uart_putc, uart2base);
+
+	pr_debug(">");
+}
+
+static void setup_ram(void)
+{
+	read_dimm_settings();
+
+	mx6dq_dram_iocfg(64, &novena_ddr_regs, &novena_grp_regs);
+	mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &novena_ddr_cfg);
+
+	mmdc_do_write_level_calibration();
+	mmdc_do_dqs_calibration();
+}
+
+static void load_barebox(void)
+{
+	enum bootsource bootsrc;
+	int bootinstance;
+
+	imx6_get_boot_source(&bootsrc, &bootinstance);
+
+	if (bootsrc == BOOTSOURCE_SERIAL)
+		imx6_barebox_start_usb(IOMEM(MX6_MMDC_PORT01_BASE_ADDR));
+	else if (bootsrc == BOOTSOURCE_MMC)
+		imx6_esdhc_start_image(bootinstance);
+
+	pr_err("Unsupported boot source %i instance %i\n",
+	        bootsrc, bootinstance);
+	hang();
+}
+
+ENTRY_FUNCTION_WITHSTACK(start_imx6q_novena, STACK_TOP, r0, r1, r2)
+{
+	imx6_cpu_lowlevel_init();
+	relocate_to_current_adr();
+	setup_c();
+
+	imx6_ungate_all_peripherals();
+	setup_uart();
+
+	if (!running_from_ram()) {
+		setup_ram();
+		load_barebox();
+	} else {
+		imx6q_barebox_entry(__dtb_z_imx6q_novena_start);
+	}
+}
diff --git a/arch/arm/boards/nvidia-beaver/Makefile b/arch/arm/boards/nvidia-beaver/Makefile
index 1b90eb13fd..6485e5d2da 100644
--- a/arch/arm/boards/nvidia-beaver/Makefile
+++ b/arch/arm/boards/nvidia-beaver/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t
 soc := tegra30
 lwl-y += entry.o
diff --git a/arch/arm/boards/nvidia-beaver/board.c b/arch/arm/boards/nvidia-beaver/board.c
index 0ef37780b4..2537e75337 100644
--- a/arch/arm/boards/nvidia-beaver/board.c
+++ b/arch/arm/boards/nvidia-beaver/board.c
@@ -6,7 +6,7 @@
 #include <gpio.h>
 #include <i2c/i2c.h>
 #include <init.h>
-#include <mach/tegra-bbu.h>
+#include <mach/tegra/tegra-bbu.h>
 
 static int nvidia_beaver_fs_init(void)
 {
diff --git a/arch/arm/boards/nvidia-beaver/entry.c b/arch/arm/boards/nvidia-beaver/entry.c
index a89d419797..c79057cd9d 100644
--- a/arch/arm/boards/nvidia-beaver/entry.c
+++ b/arch/arm/boards/nvidia-beaver/entry.c
@@ -2,8 +2,8 @@
 // SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de>
 
 #include <common.h>
-#include <mach/lowlevel.h>
-#include <mach/lowlevel-dvc.h>
+#include <mach/tegra/lowlevel.h>
+#include <mach/tegra/lowlevel-dvc.h>
 
 extern char __dtb_tegra30_beaver_start[];
 
diff --git a/arch/arm/boards/nvidia-jetson-tk1/Makefile b/arch/arm/boards/nvidia-jetson-tk1/Makefile
index d38001c158..7d9402f9b3 100644
--- a/arch/arm/boards/nvidia-jetson-tk1/Makefile
+++ b/arch/arm/boards/nvidia-jetson-tk1/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t
 soc := tegra124
 lwl-y += entry.o
diff --git a/arch/arm/boards/nvidia-jetson-tk1/board.c b/arch/arm/boards/nvidia-jetson-tk1/board.c
index fca3038170..6f72466d76 100644
--- a/arch/arm/boards/nvidia-jetson-tk1/board.c
+++ b/arch/arm/boards/nvidia-jetson-tk1/board.c
@@ -6,7 +6,7 @@
 #include <gpio.h>
 #include <i2c/i2c.h>
 #include <init.h>
-#include <mach/tegra-bbu.h>
+#include <mach/tegra/tegra-bbu.h>
 
 #define AS3722_SD_VOLTAGE(n)	(0x00 + (n))
 #define AS3722_GPIO_CONTROL(n)	(0x08 + (n))
diff --git a/arch/arm/boards/nvidia-jetson-tk1/entry.c b/arch/arm/boards/nvidia-jetson-tk1/entry.c
index 22b6c743ee..db9b1d9ebf 100644
--- a/arch/arm/boards/nvidia-jetson-tk1/entry.c
+++ b/arch/arm/boards/nvidia-jetson-tk1/entry.c
@@ -2,8 +2,8 @@
 // SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de>
 
 #include <common.h>
-#include <mach/lowlevel.h>
-#include <mach/lowlevel-dvc.h>
+#include <mach/tegra/lowlevel.h>
+#include <mach/tegra/lowlevel-dvc.h>
 
 extern char __dtb_tegra124_jetson_tk1_start[];
 
diff --git a/arch/arm/boards/nxp-imx6ull-evk/Makefile b/arch/arm/boards/nxp-imx6ull-evk/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/nxp-imx6ull-evk/Makefile
+++ b/arch/arm/boards/nxp-imx6ull-evk/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/nxp-imx6ull-evk/board.c b/arch/arm/boards/nxp-imx6ull-evk/board.c
index 5959501a26..fb168662b9 100644
--- a/arch/arm/boards/nxp-imx6ull-evk/board.c
+++ b/arch/arm/boards/nxp-imx6ull-evk/board.c
@@ -3,7 +3,7 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <linux/phy.h>
 
 #include <linux/micrel_phy.h>
diff --git a/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c
index afef4c4498..0a12eb9b68 100644
--- a/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c
@@ -2,13 +2,14 @@
 
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx6-regs.h>
+#include <mach/imx/imx6-regs.h>
 #include <io.h>
 #include <debug_ll.h>
-#include <mach/esdctl.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/esdctl.h>
 #include <asm/cache.h>
 #include <asm/sections.h>
 #include <image-metadata.h>
diff --git a/arch/arm/boards/nxp-imx8mm-evk/Makefile b/arch/arm/boards/nxp-imx8mm-evk/Makefile
index 4d0d989015..35d8640087 100644
--- a/arch/arm/boards/nxp-imx8mm-evk/Makefile
+++ b/arch/arm/boards/nxp-imx8mm-evk/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/nxp-imx8mm-evk/board.c b/arch/arm/boards/nxp-imx8mm-evk/board.c
index 6e4df60065..c8e17570ca 100644
--- a/arch/arm/boards/nxp-imx8mm-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mm-evk/board.c
@@ -7,7 +7,8 @@
 #include <init.h>
 #include <linux/phy.h>
 #include <linux/sizes.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
+#include <deep-probe.h>
 
 #include <envfs.h>
 
@@ -30,14 +31,11 @@ static int ar8031_phy_fixup(struct phy_device *phydev)
 	return 0;
 }
 
-static int nxp_imx8mm_evk_init(void)
+static int imx8mm_evk_probe(struct device *dev)
 {
 	int emmc_bbu_flag = 0;
 	int sd_bbu_flag = 0;
 
-	if (!of_machine_is_compatible("fsl,imx8mm-evk"))
-		return 0;
-
 	barebox_set_hostname("imx8mm-evk");
 
 	if (bootsource_get() == BOOTSOURCE_MMC) {
@@ -55,9 +53,24 @@ static int nxp_imx8mm_evk_init(void)
 
 	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
 	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+	imx8m_bbu_internal_flexspi_nor_register_handler("QSPI", "/dev/m25p0.barebox", 0);
 
 	phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
 				   ar8031_phy_fixup);
 	return 0;
 }
-device_initcall(nxp_imx8mm_evk_init);
+
+static const struct of_device_id imx8mm_evk_of_match[] = {
+	{ .compatible = "fsl,imx8mm-evk", },
+	{ .compatible = "fsl,imx8mm-evkb", },
+	{ /* sentinel */ }
+};
+
+static struct driver imx8mm_evk_board_driver = {
+	.name = "board-imx8mm-evk",
+	.probe = imx8mm_evk_probe,
+	.of_compatible = imx8mm_evk_of_match,
+};
+coredevice_platform_driver(imx8mm_evk_board_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(imx8mm_evk_of_match);
diff --git a/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg
index b013173113..d1d223a8ee 100644
--- a/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg
+++ b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg
@@ -1,5 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx8mm
 
 loadaddr 0x007e1000
 max_load_size 0x3f000
 ivtofs 0x400
+
+#include <mach/imx/flexspi-imx8mm-cfg.h>
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c
index 4bd29c2269..881d8285b6 100644
--- a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c
@@ -3,26 +3,23 @@
 #include <io.h>
 #include <common.h>
 #include <debug_ll.h>
-#include <firmware.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/mmu.h>
 #include <asm/cache.h>
-#include <asm/sections.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
-#include <i2c/i2c-early.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
 #include <linux/sizes.h>
-#include <mach/atf.h>
-#include <mach/xload.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
-#include <mach/imx8mm-regs.h>
-#include <mach/iomux-mx8mm.h>
-#include <mach/imx8m-ccm-regs.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8mm-regs.h>
+#include <mach/imx/iomux-mx8mm.h>
+#include <mach/imx/imx8m-ccm-regs.h>
 #include <mfd/bd71837.h>
+#include <mfd/pca9450.h>
+#include <mach/imx/xload.h>
 #include <soc/imx8m/ddr.h>
-#include <soc/fsl/fsl_udc.h>
-
-extern char __dtb_imx8mm_evk_start[];
 
 #define UART_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
 
@@ -40,66 +37,66 @@ static void setup_uart(void)
 	putc_ll('>');
 }
 
-static void pmic_reg_write(void *i2c, int reg, uint8_t val)
-{
-	int ret;
-	u8 buf[32];
-	struct i2c_msg msgs[] = {
-		{
-			.addr = 0x4b,
-			.buf = buf,
-		},
-	};
-
-	buf[0] = reg;
-	buf[1] = val;
-
-	msgs[0].len = 2;
-
-	ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
-	if (ret != 1)
-		pr_err("Failed to write to pmic\n");
-}
+static struct pmic_config pca9450_cfg[] = {
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	{ PCA9450_BUCK123_DVS, 0x29 },
 
-static int power_init_board(void)
-{
-	void *i2c;
+	/* Buck 1 DVS control through PMIC_STBY_REQ */
+	{ PCA9450_BUCK1CTRL, 0x59 },
 
-	imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL);
-	imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA);
+	/* Set DVS1 to 0.8v for suspend */
+	{ PCA9450_BUCK1OUT_DVS1, 0x10 },
 
-	imx8mm_early_clock_init();
-	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+	/* increase VDD_DRAM to 0.95v for 3Ghz DDR */
+	{ PCA9450_BUCK3OUT_DVS0, 0x1c },
 
-	i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR));
+	/*
+	 * VDD_DRAM needs off in suspend, set B1_ENMODE=10
+	 * (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L)
+	 */
+	{ PCA9450_BUCK3CTRL, 0x4a },
 
-	/* decrease RESET key long push time from the default 10s to 10ms */
-	pmic_reg_write(i2c, BD718XX_PWRONCONFIG1, 0x0);
+	/* set VDD_SNVS_0V8 from default 0.85V */
+	{ PCA9450_LDO2CTRL, 0xc0 },
 
-	/* unlock the PMIC regs */
-	pmic_reg_write(i2c, BD718XX_REGLOCK, 0x1);
+	/* set WDOG_B_CFG to cold reset */
+	{ PCA9450_RESET_CTRL, 0xa1 },
+};
 
+static struct pmic_config bd71837_cfg[] = {
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	{ BD718XX_PWRONCONFIG1, 0x0 },
+	/* unlock the PMIC regs */
+	{ BD718XX_REGLOCK, 0x1 },
 	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
-	pmic_reg_write(i2c, BD718XX_BUCK1_VOLT_RUN, 0x0f);
-
+	{ BD718XX_BUCK1_VOLT_RUN, 0x0f },
 	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
-	pmic_reg_write(i2c, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
-
+	{ BD718XX_1ST_NODVS_BUCK_VOLT, 0x83 },
 	/* lock the PMIC regs */
-	pmic_reg_write(i2c, BD718XX_REGLOCK, 0x11);
+	{ BD718XX_REGLOCK, 0x11 },
+};
+
+static void power_init_board(void)
+{
+	struct pbl_i2c *i2c;
 
-	return 0;
+	imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL);
+	imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA);
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR));
+
+	if (i2c_dev_probe(i2c, 0x25, true) == 0)
+		pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+	else
+		pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg));
 }
 
 extern struct dram_timing_info imx8mm_evk_dram_timing;
 
 static void start_atf(void)
 {
-	size_t bl31_size;
-	const u8 *bl31;
-	enum bootsource src;
-	int instance;
-
 	/*
 	 * If we are in EL3 we are running for the first time and need to
 	 * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
@@ -108,38 +105,11 @@ static void start_atf(void)
 	if (current_el() != 3)
 		return;
 
+	imx8mm_early_clock_init();
 	power_init_board();
-	imx8mm_ddr_init(&imx8mm_evk_dram_timing);
-
-	imx8mm_get_boot_source(&src, &instance);
-	switch (src) {
-	case BOOTSOURCE_MMC:
-		imx8m_esdhc_load_image(instance, false);
-		break;
-	case BOOTSOURCE_SERIAL:
-		imx8mm_barebox_load_usb((void *)MX8M_ATF_BL33_BASE_ADDR);
-	break;
-	default:
-		printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
-		hang();
-	}
+	imx8mm_ddr_init(&imx8mm_evk_dram_timing, DRAM_TYPE_LPDDR4);
 
-	/*
-	 * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
-	 * in EL2. Copy the image there, but replace the PBL part of
-	 * that image with ourselves. On a high assurance boot only the
-	 * currently running code is validated and contains the checksum
-	 * for the piggy data, so we need to ensure that we are running
-	 * the same code in DRAM.
-	 */
-	memcpy((void *)MX8M_ATF_BL33_BASE_ADDR,
-	       __image_start, barebox_pbl_size);
-
-	get_builtin_firmware(imx8mm_bl31_bin, &bl31, &bl31_size);
-
-	imx8mm_atf_load_bl31(bl31, bl31_size);
-
-	/* not reached */
+	imx8mm_load_and_start_image_via_tfa();
 }
 
 /*
@@ -160,14 +130,26 @@ static void start_atf(void)
  */
 static __noreturn noinline void nxp_imx8mm_evk_start(void)
 {
+	extern char __dtb_z_imx8mm_evk_start[], __dtb_z_imx8mm_evkb_start[];
+	struct pbl_i2c *i2c;
+	void *fdt;
+
 	setup_uart();
 
 	start_atf();
 
 	/*
-	 * Standard entry we hit once we initialized both DDR and ATF
+	 * Standard entry we hit once we initialized both DDR and ATF. I2C pad
+	 * and clock setup already done during power_init_board().
 	 */
-	imx8mm_barebox_entry(__dtb_imx8mm_evk_start);
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR));
+
+	if (i2c_dev_probe(i2c, 0x25, true) == 0)
+		fdt = __dtb_z_imx8mm_evkb_start;
+	else
+		fdt = __dtb_z_imx8mm_evk_start;
+
+	imx8mm_barebox_entry(fdt);
 }
 
 ENTRY_FUNCTION(start_nxp_imx8mm_evk, r0, r1, r2)
diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
index e7c01f9cc9..c9d11a2408 100644
--- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
+++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
@@ -320,729 +320,6 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x2200ca, 0x24 },
 };
 
-/* ddr phy trained csr */
-static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
-	{ 0x200b2, 0x0 },
-	{ 0x1200b2, 0x0 },
-	{ 0x2200b2, 0x0 },
-	{ 0x200cb, 0x0 },
-	{ 0x10043, 0x0 },
-	{ 0x110043, 0x0 },
-	{ 0x210043, 0x0 },
-	{ 0x10143, 0x0 },
-	{ 0x110143, 0x0 },
-	{ 0x210143, 0x0 },
-	{ 0x11043, 0x0 },
-	{ 0x111043, 0x0 },
-	{ 0x211043, 0x0 },
-	{ 0x11143, 0x0 },
-	{ 0x111143, 0x0 },
-	{ 0x211143, 0x0 },
-	{ 0x12043, 0x0 },
-	{ 0x112043, 0x0 },
-	{ 0x212043, 0x0 },
-	{ 0x12143, 0x0 },
-	{ 0x112143, 0x0 },
-	{ 0x212143, 0x0 },
-	{ 0x13043, 0x0 },
-	{ 0x113043, 0x0 },
-	{ 0x213043, 0x0 },
-	{ 0x13143, 0x0 },
-	{ 0x113143, 0x0 },
-	{ 0x213143, 0x0 },
-	{ 0x80, 0x0 },
-	{ 0x100080, 0x0 },
-	{ 0x200080, 0x0 },
-	{ 0x1080, 0x0 },
-	{ 0x101080, 0x0 },
-	{ 0x201080, 0x0 },
-	{ 0x2080, 0x0 },
-	{ 0x102080, 0x0 },
-	{ 0x202080, 0x0 },
-	{ 0x3080, 0x0 },
-	{ 0x103080, 0x0 },
-	{ 0x203080, 0x0 },
-	{ 0x4080, 0x0 },
-	{ 0x104080, 0x0 },
-	{ 0x204080, 0x0 },
-	{ 0x5080, 0x0 },
-	{ 0x105080, 0x0 },
-	{ 0x205080, 0x0 },
-	{ 0x6080, 0x0 },
-	{ 0x106080, 0x0 },
-	{ 0x206080, 0x0 },
-	{ 0x7080, 0x0 },
-	{ 0x107080, 0x0 },
-	{ 0x207080, 0x0 },
-	{ 0x8080, 0x0 },
-	{ 0x108080, 0x0 },
-	{ 0x208080, 0x0 },
-	{ 0x9080, 0x0 },
-	{ 0x109080, 0x0 },
-	{ 0x209080, 0x0 },
-	{ 0x10080, 0x0 },
-	{ 0x110080, 0x0 },
-	{ 0x210080, 0x0 },
-	{ 0x10180, 0x0 },
-	{ 0x110180, 0x0 },
-	{ 0x210180, 0x0 },
-	{ 0x11080, 0x0 },
-	{ 0x111080, 0x0 },
-	{ 0x211080, 0x0 },
-	{ 0x11180, 0x0 },
-	{ 0x111180, 0x0 },
-	{ 0x211180, 0x0 },
-	{ 0x12080, 0x0 },
-	{ 0x112080, 0x0 },
-	{ 0x212080, 0x0 },
-	{ 0x12180, 0x0 },
-	{ 0x112180, 0x0 },
-	{ 0x212180, 0x0 },
-	{ 0x13080, 0x0 },
-	{ 0x113080, 0x0 },
-	{ 0x213080, 0x0 },
-	{ 0x13180, 0x0 },
-	{ 0x113180, 0x0 },
-	{ 0x213180, 0x0 },
-	{ 0x10081, 0x0 },
-	{ 0x110081, 0x0 },
-	{ 0x210081, 0x0 },
-	{ 0x10181, 0x0 },
-	{ 0x110181, 0x0 },
-	{ 0x210181, 0x0 },
-	{ 0x11081, 0x0 },
-	{ 0x111081, 0x0 },
-	{ 0x211081, 0x0 },
-	{ 0x11181, 0x0 },
-	{ 0x111181, 0x0 },
-	{ 0x211181, 0x0 },
-	{ 0x12081, 0x0 },
-	{ 0x112081, 0x0 },
-	{ 0x212081, 0x0 },
-	{ 0x12181, 0x0 },
-	{ 0x112181, 0x0 },
-	{ 0x212181, 0x0 },
-	{ 0x13081, 0x0 },
-	{ 0x113081, 0x0 },
-	{ 0x213081, 0x0 },
-	{ 0x13181, 0x0 },
-	{ 0x113181, 0x0 },
-	{ 0x213181, 0x0 },
-	{ 0x100d0, 0x0 },
-	{ 0x1100d0, 0x0 },
-	{ 0x2100d0, 0x0 },
-	{ 0x101d0, 0x0 },
-	{ 0x1101d0, 0x0 },
-	{ 0x2101d0, 0x0 },
-	{ 0x110d0, 0x0 },
-	{ 0x1110d0, 0x0 },
-	{ 0x2110d0, 0x0 },
-	{ 0x111d0, 0x0 },
-	{ 0x1111d0, 0x0 },
-	{ 0x2111d0, 0x0 },
-	{ 0x120d0, 0x0 },
-	{ 0x1120d0, 0x0 },
-	{ 0x2120d0, 0x0 },
-	{ 0x121d0, 0x0 },
-	{ 0x1121d0, 0x0 },
-	{ 0x2121d0, 0x0 },
-	{ 0x130d0, 0x0 },
-	{ 0x1130d0, 0x0 },
-	{ 0x2130d0, 0x0 },
-	{ 0x131d0, 0x0 },
-	{ 0x1131d0, 0x0 },
-	{ 0x2131d0, 0x0 },
-	{ 0x100d1, 0x0 },
-	{ 0x1100d1, 0x0 },
-	{ 0x2100d1, 0x0 },
-	{ 0x101d1, 0x0 },
-	{ 0x1101d1, 0x0 },
-	{ 0x2101d1, 0x0 },
-	{ 0x110d1, 0x0 },
-	{ 0x1110d1, 0x0 },
-	{ 0x2110d1, 0x0 },
-	{ 0x111d1, 0x0 },
-	{ 0x1111d1, 0x0 },
-	{ 0x2111d1, 0x0 },
-	{ 0x120d1, 0x0 },
-	{ 0x1120d1, 0x0 },
-	{ 0x2120d1, 0x0 },
-	{ 0x121d1, 0x0 },
-	{ 0x1121d1, 0x0 },
-	{ 0x2121d1, 0x0 },
-	{ 0x130d1, 0x0 },
-	{ 0x1130d1, 0x0 },
-	{ 0x2130d1, 0x0 },
-	{ 0x131d1, 0x0 },
-	{ 0x1131d1, 0x0 },
-	{ 0x2131d1, 0x0 },
-	{ 0x10068, 0x0 },
-	{ 0x10168, 0x0 },
-	{ 0x10268, 0x0 },
-	{ 0x10368, 0x0 },
-	{ 0x10468, 0x0 },
-	{ 0x10568, 0x0 },
-	{ 0x10668, 0x0 },
-	{ 0x10768, 0x0 },
-	{ 0x10868, 0x0 },
-	{ 0x11068, 0x0 },
-	{ 0x11168, 0x0 },
-	{ 0x11268, 0x0 },
-	{ 0x11368, 0x0 },
-	{ 0x11468, 0x0 },
-	{ 0x11568, 0x0 },
-	{ 0x11668, 0x0 },
-	{ 0x11768, 0x0 },
-	{ 0x11868, 0x0 },
-	{ 0x12068, 0x0 },
-	{ 0x12168, 0x0 },
-	{ 0x12268, 0x0 },
-	{ 0x12368, 0x0 },
-	{ 0x12468, 0x0 },
-	{ 0x12568, 0x0 },
-	{ 0x12668, 0x0 },
-	{ 0x12768, 0x0 },
-	{ 0x12868, 0x0 },
-	{ 0x13068, 0x0 },
-	{ 0x13168, 0x0 },
-	{ 0x13268, 0x0 },
-	{ 0x13368, 0x0 },
-	{ 0x13468, 0x0 },
-	{ 0x13568, 0x0 },
-	{ 0x13668, 0x0 },
-	{ 0x13768, 0x0 },
-	{ 0x13868, 0x0 },
-	{ 0x10069, 0x0 },
-	{ 0x10169, 0x0 },
-	{ 0x10269, 0x0 },
-	{ 0x10369, 0x0 },
-	{ 0x10469, 0x0 },
-	{ 0x10569, 0x0 },
-	{ 0x10669, 0x0 },
-	{ 0x10769, 0x0 },
-	{ 0x10869, 0x0 },
-	{ 0x11069, 0x0 },
-	{ 0x11169, 0x0 },
-	{ 0x11269, 0x0 },
-	{ 0x11369, 0x0 },
-	{ 0x11469, 0x0 },
-	{ 0x11569, 0x0 },
-	{ 0x11669, 0x0 },
-	{ 0x11769, 0x0 },
-	{ 0x11869, 0x0 },
-	{ 0x12069, 0x0 },
-	{ 0x12169, 0x0 },
-	{ 0x12269, 0x0 },
-	{ 0x12369, 0x0 },
-	{ 0x12469, 0x0 },
-	{ 0x12569, 0x0 },
-	{ 0x12669, 0x0 },
-	{ 0x12769, 0x0 },
-	{ 0x12869, 0x0 },
-	{ 0x13069, 0x0 },
-	{ 0x13169, 0x0 },
-	{ 0x13269, 0x0 },
-	{ 0x13369, 0x0 },
-	{ 0x13469, 0x0 },
-	{ 0x13569, 0x0 },
-	{ 0x13669, 0x0 },
-	{ 0x13769, 0x0 },
-	{ 0x13869, 0x0 },
-	{ 0x1008c, 0x0 },
-	{ 0x11008c, 0x0 },
-	{ 0x21008c, 0x0 },
-	{ 0x1018c, 0x0 },
-	{ 0x11018c, 0x0 },
-	{ 0x21018c, 0x0 },
-	{ 0x1108c, 0x0 },
-	{ 0x11108c, 0x0 },
-	{ 0x21108c, 0x0 },
-	{ 0x1118c, 0x0 },
-	{ 0x11118c, 0x0 },
-	{ 0x21118c, 0x0 },
-	{ 0x1208c, 0x0 },
-	{ 0x11208c, 0x0 },
-	{ 0x21208c, 0x0 },
-	{ 0x1218c, 0x0 },
-	{ 0x11218c, 0x0 },
-	{ 0x21218c, 0x0 },
-	{ 0x1308c, 0x0 },
-	{ 0x11308c, 0x0 },
-	{ 0x21308c, 0x0 },
-	{ 0x1318c, 0x0 },
-	{ 0x11318c, 0x0 },
-	{ 0x21318c, 0x0 },
-	{ 0x1008d, 0x0 },
-	{ 0x11008d, 0x0 },
-	{ 0x21008d, 0x0 },
-	{ 0x1018d, 0x0 },
-	{ 0x11018d, 0x0 },
-	{ 0x21018d, 0x0 },
-	{ 0x1108d, 0x0 },
-	{ 0x11108d, 0x0 },
-	{ 0x21108d, 0x0 },
-	{ 0x1118d, 0x0 },
-	{ 0x11118d, 0x0 },
-	{ 0x21118d, 0x0 },
-	{ 0x1208d, 0x0 },
-	{ 0x11208d, 0x0 },
-	{ 0x21208d, 0x0 },
-	{ 0x1218d, 0x0 },
-	{ 0x11218d, 0x0 },
-	{ 0x21218d, 0x0 },
-	{ 0x1308d, 0x0 },
-	{ 0x11308d, 0x0 },
-	{ 0x21308d, 0x0 },
-	{ 0x1318d, 0x0 },
-	{ 0x11318d, 0x0 },
-	{ 0x21318d, 0x0 },
-	{ 0x100c0, 0x0 },
-	{ 0x1100c0, 0x0 },
-	{ 0x2100c0, 0x0 },
-	{ 0x101c0, 0x0 },
-	{ 0x1101c0, 0x0 },
-	{ 0x2101c0, 0x0 },
-	{ 0x102c0, 0x0 },
-	{ 0x1102c0, 0x0 },
-	{ 0x2102c0, 0x0 },
-	{ 0x103c0, 0x0 },
-	{ 0x1103c0, 0x0 },
-	{ 0x2103c0, 0x0 },
-	{ 0x104c0, 0x0 },
-	{ 0x1104c0, 0x0 },
-	{ 0x2104c0, 0x0 },
-	{ 0x105c0, 0x0 },
-	{ 0x1105c0, 0x0 },
-	{ 0x2105c0, 0x0 },
-	{ 0x106c0, 0x0 },
-	{ 0x1106c0, 0x0 },
-	{ 0x2106c0, 0x0 },
-	{ 0x107c0, 0x0 },
-	{ 0x1107c0, 0x0 },
-	{ 0x2107c0, 0x0 },
-	{ 0x108c0, 0x0 },
-	{ 0x1108c0, 0x0 },
-	{ 0x2108c0, 0x0 },
-	{ 0x110c0, 0x0 },
-	{ 0x1110c0, 0x0 },
-	{ 0x2110c0, 0x0 },
-	{ 0x111c0, 0x0 },
-	{ 0x1111c0, 0x0 },
-	{ 0x2111c0, 0x0 },
-	{ 0x112c0, 0x0 },
-	{ 0x1112c0, 0x0 },
-	{ 0x2112c0, 0x0 },
-	{ 0x113c0, 0x0 },
-	{ 0x1113c0, 0x0 },
-	{ 0x2113c0, 0x0 },
-	{ 0x114c0, 0x0 },
-	{ 0x1114c0, 0x0 },
-	{ 0x2114c0, 0x0 },
-	{ 0x115c0, 0x0 },
-	{ 0x1115c0, 0x0 },
-	{ 0x2115c0, 0x0 },
-	{ 0x116c0, 0x0 },
-	{ 0x1116c0, 0x0 },
-	{ 0x2116c0, 0x0 },
-	{ 0x117c0, 0x0 },
-	{ 0x1117c0, 0x0 },
-	{ 0x2117c0, 0x0 },
-	{ 0x118c0, 0x0 },
-	{ 0x1118c0, 0x0 },
-	{ 0x2118c0, 0x0 },
-	{ 0x120c0, 0x0 },
-	{ 0x1120c0, 0x0 },
-	{ 0x2120c0, 0x0 },
-	{ 0x121c0, 0x0 },
-	{ 0x1121c0, 0x0 },
-	{ 0x2121c0, 0x0 },
-	{ 0x122c0, 0x0 },
-	{ 0x1122c0, 0x0 },
-	{ 0x2122c0, 0x0 },
-	{ 0x123c0, 0x0 },
-	{ 0x1123c0, 0x0 },
-	{ 0x2123c0, 0x0 },
-	{ 0x124c0, 0x0 },
-	{ 0x1124c0, 0x0 },
-	{ 0x2124c0, 0x0 },
-	{ 0x125c0, 0x0 },
-	{ 0x1125c0, 0x0 },
-	{ 0x2125c0, 0x0 },
-	{ 0x126c0, 0x0 },
-	{ 0x1126c0, 0x0 },
-	{ 0x2126c0, 0x0 },
-	{ 0x127c0, 0x0 },
-	{ 0x1127c0, 0x0 },
-	{ 0x2127c0, 0x0 },
-	{ 0x128c0, 0x0 },
-	{ 0x1128c0, 0x0 },
-	{ 0x2128c0, 0x0 },
-	{ 0x130c0, 0x0 },
-	{ 0x1130c0, 0x0 },
-	{ 0x2130c0, 0x0 },
-	{ 0x131c0, 0x0 },
-	{ 0x1131c0, 0x0 },
-	{ 0x2131c0, 0x0 },
-	{ 0x132c0, 0x0 },
-	{ 0x1132c0, 0x0 },
-	{ 0x2132c0, 0x0 },
-	{ 0x133c0, 0x0 },
-	{ 0x1133c0, 0x0 },
-	{ 0x2133c0, 0x0 },
-	{ 0x134c0, 0x0 },
-	{ 0x1134c0, 0x0 },
-	{ 0x2134c0, 0x0 },
-	{ 0x135c0, 0x0 },
-	{ 0x1135c0, 0x0 },
-	{ 0x2135c0, 0x0 },
-	{ 0x136c0, 0x0 },
-	{ 0x1136c0, 0x0 },
-	{ 0x2136c0, 0x0 },
-	{ 0x137c0, 0x0 },
-	{ 0x1137c0, 0x0 },
-	{ 0x2137c0, 0x0 },
-	{ 0x138c0, 0x0 },
-	{ 0x1138c0, 0x0 },
-	{ 0x2138c0, 0x0 },
-	{ 0x100c1, 0x0 },
-	{ 0x1100c1, 0x0 },
-	{ 0x2100c1, 0x0 },
-	{ 0x101c1, 0x0 },
-	{ 0x1101c1, 0x0 },
-	{ 0x2101c1, 0x0 },
-	{ 0x102c1, 0x0 },
-	{ 0x1102c1, 0x0 },
-	{ 0x2102c1, 0x0 },
-	{ 0x103c1, 0x0 },
-	{ 0x1103c1, 0x0 },
-	{ 0x2103c1, 0x0 },
-	{ 0x104c1, 0x0 },
-	{ 0x1104c1, 0x0 },
-	{ 0x2104c1, 0x0 },
-	{ 0x105c1, 0x0 },
-	{ 0x1105c1, 0x0 },
-	{ 0x2105c1, 0x0 },
-	{ 0x106c1, 0x0 },
-	{ 0x1106c1, 0x0 },
-	{ 0x2106c1, 0x0 },
-	{ 0x107c1, 0x0 },
-	{ 0x1107c1, 0x0 },
-	{ 0x2107c1, 0x0 },
-	{ 0x108c1, 0x0 },
-	{ 0x1108c1, 0x0 },
-	{ 0x2108c1, 0x0 },
-	{ 0x110c1, 0x0 },
-	{ 0x1110c1, 0x0 },
-	{ 0x2110c1, 0x0 },
-	{ 0x111c1, 0x0 },
-	{ 0x1111c1, 0x0 },
-	{ 0x2111c1, 0x0 },
-	{ 0x112c1, 0x0 },
-	{ 0x1112c1, 0x0 },
-	{ 0x2112c1, 0x0 },
-	{ 0x113c1, 0x0 },
-	{ 0x1113c1, 0x0 },
-	{ 0x2113c1, 0x0 },
-	{ 0x114c1, 0x0 },
-	{ 0x1114c1, 0x0 },
-	{ 0x2114c1, 0x0 },
-	{ 0x115c1, 0x0 },
-	{ 0x1115c1, 0x0 },
-	{ 0x2115c1, 0x0 },
-	{ 0x116c1, 0x0 },
-	{ 0x1116c1, 0x0 },
-	{ 0x2116c1, 0x0 },
-	{ 0x117c1, 0x0 },
-	{ 0x1117c1, 0x0 },
-	{ 0x2117c1, 0x0 },
-	{ 0x118c1, 0x0 },
-	{ 0x1118c1, 0x0 },
-	{ 0x2118c1, 0x0 },
-	{ 0x120c1, 0x0 },
-	{ 0x1120c1, 0x0 },
-	{ 0x2120c1, 0x0 },
-	{ 0x121c1, 0x0 },
-	{ 0x1121c1, 0x0 },
-	{ 0x2121c1, 0x0 },
-	{ 0x122c1, 0x0 },
-	{ 0x1122c1, 0x0 },
-	{ 0x2122c1, 0x0 },
-	{ 0x123c1, 0x0 },
-	{ 0x1123c1, 0x0 },
-	{ 0x2123c1, 0x0 },
-	{ 0x124c1, 0x0 },
-	{ 0x1124c1, 0x0 },
-	{ 0x2124c1, 0x0 },
-	{ 0x125c1, 0x0 },
-	{ 0x1125c1, 0x0 },
-	{ 0x2125c1, 0x0 },
-	{ 0x126c1, 0x0 },
-	{ 0x1126c1, 0x0 },
-	{ 0x2126c1, 0x0 },
-	{ 0x127c1, 0x0 },
-	{ 0x1127c1, 0x0 },
-	{ 0x2127c1, 0x0 },
-	{ 0x128c1, 0x0 },
-	{ 0x1128c1, 0x0 },
-	{ 0x2128c1, 0x0 },
-	{ 0x130c1, 0x0 },
-	{ 0x1130c1, 0x0 },
-	{ 0x2130c1, 0x0 },
-	{ 0x131c1, 0x0 },
-	{ 0x1131c1, 0x0 },
-	{ 0x2131c1, 0x0 },
-	{ 0x132c1, 0x0 },
-	{ 0x1132c1, 0x0 },
-	{ 0x2132c1, 0x0 },
-	{ 0x133c1, 0x0 },
-	{ 0x1133c1, 0x0 },
-	{ 0x2133c1, 0x0 },
-	{ 0x134c1, 0x0 },
-	{ 0x1134c1, 0x0 },
-	{ 0x2134c1, 0x0 },
-	{ 0x135c1, 0x0 },
-	{ 0x1135c1, 0x0 },
-	{ 0x2135c1, 0x0 },
-	{ 0x136c1, 0x0 },
-	{ 0x1136c1, 0x0 },
-	{ 0x2136c1, 0x0 },
-	{ 0x137c1, 0x0 },
-	{ 0x1137c1, 0x0 },
-	{ 0x2137c1, 0x0 },
-	{ 0x138c1, 0x0 },
-	{ 0x1138c1, 0x0 },
-	{ 0x2138c1, 0x0 },
-	{ 0x10020, 0x0 },
-	{ 0x110020, 0x0 },
-	{ 0x210020, 0x0 },
-	{ 0x11020, 0x0 },
-	{ 0x111020, 0x0 },
-	{ 0x211020, 0x0 },
-	{ 0x12020, 0x0 },
-	{ 0x112020, 0x0 },
-	{ 0x212020, 0x0 },
-	{ 0x13020, 0x0 },
-	{ 0x113020, 0x0 },
-	{ 0x213020, 0x0 },
-	{ 0x20072, 0x0 },
-	{ 0x20073, 0x0 },
-	{ 0x20074, 0x0 },
-	{ 0x100aa, 0x0 },
-	{ 0x110aa, 0x0 },
-	{ 0x120aa, 0x0 },
-	{ 0x130aa, 0x0 },
-	{ 0x20010, 0x0 },
-	{ 0x120010, 0x0 },
-	{ 0x220010, 0x0 },
-	{ 0x20011, 0x0 },
-	{ 0x120011, 0x0 },
-	{ 0x220011, 0x0 },
-	{ 0x100ae, 0x0 },
-	{ 0x1100ae, 0x0 },
-	{ 0x2100ae, 0x0 },
-	{ 0x100af, 0x0 },
-	{ 0x1100af, 0x0 },
-	{ 0x2100af, 0x0 },
-	{ 0x110ae, 0x0 },
-	{ 0x1110ae, 0x0 },
-	{ 0x2110ae, 0x0 },
-	{ 0x110af, 0x0 },
-	{ 0x1110af, 0x0 },
-	{ 0x2110af, 0x0 },
-	{ 0x120ae, 0x0 },
-	{ 0x1120ae, 0x0 },
-	{ 0x2120ae, 0x0 },
-	{ 0x120af, 0x0 },
-	{ 0x1120af, 0x0 },
-	{ 0x2120af, 0x0 },
-	{ 0x130ae, 0x0 },
-	{ 0x1130ae, 0x0 },
-	{ 0x2130ae, 0x0 },
-	{ 0x130af, 0x0 },
-	{ 0x1130af, 0x0 },
-	{ 0x2130af, 0x0 },
-	{ 0x20020, 0x0 },
-	{ 0x120020, 0x0 },
-	{ 0x220020, 0x0 },
-	{ 0x100a0, 0x0 },
-	{ 0x100a1, 0x0 },
-	{ 0x100a2, 0x0 },
-	{ 0x100a3, 0x0 },
-	{ 0x100a4, 0x0 },
-	{ 0x100a5, 0x0 },
-	{ 0x100a6, 0x0 },
-	{ 0x100a7, 0x0 },
-	{ 0x110a0, 0x0 },
-	{ 0x110a1, 0x0 },
-	{ 0x110a2, 0x0 },
-	{ 0x110a3, 0x0 },
-	{ 0x110a4, 0x0 },
-	{ 0x110a5, 0x0 },
-	{ 0x110a6, 0x0 },
-	{ 0x110a7, 0x0 },
-	{ 0x120a0, 0x0 },
-	{ 0x120a1, 0x0 },
-	{ 0x120a2, 0x0 },
-	{ 0x120a3, 0x0 },
-	{ 0x120a4, 0x0 },
-	{ 0x120a5, 0x0 },
-	{ 0x120a6, 0x0 },
-	{ 0x120a7, 0x0 },
-	{ 0x130a0, 0x0 },
-	{ 0x130a1, 0x0 },
-	{ 0x130a2, 0x0 },
-	{ 0x130a3, 0x0 },
-	{ 0x130a4, 0x0 },
-	{ 0x130a5, 0x0 },
-	{ 0x130a6, 0x0 },
-	{ 0x130a7, 0x0 },
-	{ 0x2007c, 0x0 },
-	{ 0x12007c, 0x0 },
-	{ 0x22007c, 0x0 },
-	{ 0x2007d, 0x0 },
-	{ 0x12007d, 0x0 },
-	{ 0x22007d, 0x0 },
-	{ 0x400fd, 0x0 },
-	{ 0x400c0, 0x0 },
-	{ 0x90201, 0x0 },
-	{ 0x190201, 0x0 },
-	{ 0x290201, 0x0 },
-	{ 0x90202, 0x0 },
-	{ 0x190202, 0x0 },
-	{ 0x290202, 0x0 },
-	{ 0x90203, 0x0 },
-	{ 0x190203, 0x0 },
-	{ 0x290203, 0x0 },
-	{ 0x90204, 0x0 },
-	{ 0x190204, 0x0 },
-	{ 0x290204, 0x0 },
-	{ 0x90205, 0x0 },
-	{ 0x190205, 0x0 },
-	{ 0x290205, 0x0 },
-	{ 0x90206, 0x0 },
-	{ 0x190206, 0x0 },
-	{ 0x290206, 0x0 },
-	{ 0x90207, 0x0 },
-	{ 0x190207, 0x0 },
-	{ 0x290207, 0x0 },
-	{ 0x90208, 0x0 },
-	{ 0x190208, 0x0 },
-	{ 0x290208, 0x0 },
-	{ 0x10062, 0x0 },
-	{ 0x10162, 0x0 },
-	{ 0x10262, 0x0 },
-	{ 0x10362, 0x0 },
-	{ 0x10462, 0x0 },
-	{ 0x10562, 0x0 },
-	{ 0x10662, 0x0 },
-	{ 0x10762, 0x0 },
-	{ 0x10862, 0x0 },
-	{ 0x11062, 0x0 },
-	{ 0x11162, 0x0 },
-	{ 0x11262, 0x0 },
-	{ 0x11362, 0x0 },
-	{ 0x11462, 0x0 },
-	{ 0x11562, 0x0 },
-	{ 0x11662, 0x0 },
-	{ 0x11762, 0x0 },
-	{ 0x11862, 0x0 },
-	{ 0x12062, 0x0 },
-	{ 0x12162, 0x0 },
-	{ 0x12262, 0x0 },
-	{ 0x12362, 0x0 },
-	{ 0x12462, 0x0 },
-	{ 0x12562, 0x0 },
-	{ 0x12662, 0x0 },
-	{ 0x12762, 0x0 },
-	{ 0x12862, 0x0 },
-	{ 0x13062, 0x0 },
-	{ 0x13162, 0x0 },
-	{ 0x13262, 0x0 },
-	{ 0x13362, 0x0 },
-	{ 0x13462, 0x0 },
-	{ 0x13562, 0x0 },
-	{ 0x13662, 0x0 },
-	{ 0x13762, 0x0 },
-	{ 0x13862, 0x0 },
-	{ 0x20077, 0x0 },
-	{ 0x10001, 0x0 },
-	{ 0x11001, 0x0 },
-	{ 0x12001, 0x0 },
-	{ 0x13001, 0x0 },
-	{ 0x10040, 0x0 },
-	{ 0x10140, 0x0 },
-	{ 0x10240, 0x0 },
-	{ 0x10340, 0x0 },
-	{ 0x10440, 0x0 },
-	{ 0x10540, 0x0 },
-	{ 0x10640, 0x0 },
-	{ 0x10740, 0x0 },
-	{ 0x10840, 0x0 },
-	{ 0x10030, 0x0 },
-	{ 0x10130, 0x0 },
-	{ 0x10230, 0x0 },
-	{ 0x10330, 0x0 },
-	{ 0x10430, 0x0 },
-	{ 0x10530, 0x0 },
-	{ 0x10630, 0x0 },
-	{ 0x10730, 0x0 },
-	{ 0x10830, 0x0 },
-	{ 0x11040, 0x0 },
-	{ 0x11140, 0x0 },
-	{ 0x11240, 0x0 },
-	{ 0x11340, 0x0 },
-	{ 0x11440, 0x0 },
-	{ 0x11540, 0x0 },
-	{ 0x11640, 0x0 },
-	{ 0x11740, 0x0 },
-	{ 0x11840, 0x0 },
-	{ 0x11030, 0x0 },
-	{ 0x11130, 0x0 },
-	{ 0x11230, 0x0 },
-	{ 0x11330, 0x0 },
-	{ 0x11430, 0x0 },
-	{ 0x11530, 0x0 },
-	{ 0x11630, 0x0 },
-	{ 0x11730, 0x0 },
-	{ 0x11830, 0x0 },
-	{ 0x12040, 0x0 },
-	{ 0x12140, 0x0 },
-	{ 0x12240, 0x0 },
-	{ 0x12340, 0x0 },
-	{ 0x12440, 0x0 },
-	{ 0x12540, 0x0 },
-	{ 0x12640, 0x0 },
-	{ 0x12740, 0x0 },
-	{ 0x12840, 0x0 },
-	{ 0x12030, 0x0 },
-	{ 0x12130, 0x0 },
-	{ 0x12230, 0x0 },
-	{ 0x12330, 0x0 },
-	{ 0x12430, 0x0 },
-	{ 0x12530, 0x0 },
-	{ 0x12630, 0x0 },
-	{ 0x12730, 0x0 },
-	{ 0x12830, 0x0 },
-	{ 0x13040, 0x0 },
-	{ 0x13140, 0x0 },
-	{ 0x13240, 0x0 },
-	{ 0x13340, 0x0 },
-	{ 0x13440, 0x0 },
-	{ 0x13540, 0x0 },
-	{ 0x13640, 0x0 },
-	{ 0x13740, 0x0 },
-	{ 0x13840, 0x0 },
-	{ 0x13030, 0x0 },
-	{ 0x13130, 0x0 },
-	{ 0x13230, 0x0 },
-	{ 0x13330, 0x0 },
-	{ 0x13430, 0x0 },
-	{ 0x13530, 0x0 },
-	{ 0x13630, 0x0 },
-	{ 0x13730, 0x0 },
-	{ 0x13830, 0x0 },
-};
-
 /* P0 message block paremeter for training firmware */
 static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
 	{ 0xd0000, 0x0 },
@@ -1971,8 +1248,7 @@ struct dram_timing_info imx8mm_evk_dram_timing = {
 	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
 	.fsp_msg = lpddr4_dram_fsp_msg,
 	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
-	.ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
-	.ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
 	.ddrphy_pie = lpddr4_phy_pie,
 	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 4000, 400, 100, },
 };
diff --git a/arch/arm/boards/nxp-imx8mn-evk/Makefile b/arch/arm/boards/nxp-imx8mn-evk/Makefile
new file mode 100644
index 0000000000..d74c5845ef
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mn-evk/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel.o ddr4-timing.o lpddr4-timing.o
diff --git a/arch/arm/boards/nxp-imx8mn-evk/board.c b/arch/arm/boards/nxp-imx8mn-evk/board.c
new file mode 100644
index 0000000000..3e90ba284c
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mn-evk/board.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
+ */
+
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <mach/imx/bbu.h>
+#include <envfs.h>
+
+#define PHY_ID_AR8031	0x004dd074
+#define AR_PHY_ID_MASK	0xffffffff
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	/*
+	 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	 * Phy control debug reg 0
+	 */
+	phy_write(phydev, 0x1d, 0x1f);
+	phy_write(phydev, 0x1e, 0x8);
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, 0x1d, 0x05);
+	phy_write(phydev, 0x1e, 0x100);
+
+	return 0;
+}
+
+static int imx8mn_evk_probe(struct device *dev)
+{
+	int emmc_bbu_flag = 0;
+	int sd_bbu_flag = 0;
+
+	if (bootsource_get() == BOOTSOURCE_MMC) {
+		if (bootsource_get_instance() == 2) {
+			of_device_enable_path("/chosen/environment-emmc");
+			emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+		} else {
+			of_device_enable_path("/chosen/environment-sd");
+			sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+		}
+	} else {
+		of_device_enable_path("/chosen/environment-emmc");
+		emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+	imx8m_bbu_internal_flexspi_nor_register_handler("QSPI", "/dev/m25p0.barebox", 0);
+
+	phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
+				   ar8031_phy_fixup);
+
+	return 0;
+}
+
+static const struct of_device_id imx8mn_evk_of_match[] = {
+	{ .compatible = "fsl,imx8mn-evk" },
+	{ .compatible = "fsl,imx8mn-ddr4-evk" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(imx8mn_evk_of_match);
+
+static struct driver imx8mn_evkboard_driver = {
+	.name = "board-imx8mn-evk",
+	.probe = imx8mn_evk_probe,
+	.of_compatible = DRV_OF_COMPAT(imx8mn_evk_of_match),
+};
+coredevice_platform_driver(imx8mn_evkboard_driver);
diff --git a/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c b/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c
new file mode 100644
index 0000000000..626d7e1c08
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c
@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400000, 0x81040010 },
+	{ 0x3d400030, 0x20 },
+	{ 0x3d400034, 0x221306 },
+	{ 0x3d400050, 0x210070 },
+	{ 0x3d400054, 0x10008 },
+	{ 0x3d400060, 0x0 },
+	{ 0x3d400064, 0x92014a },
+	{ 0x3d4000c0, 0x0 },
+	{ 0x3d4000c4, 0x1000 },
+	{ 0x3d4000d0, 0xc0030126 },
+	{ 0x3d4000d4, 0x770000 },
+	{ 0x3d4000dc, 0x8340105 },
+	{ 0x3d4000e0, 0x180200 },
+	{ 0x3d4000e4, 0x110000 },
+	{ 0x3d4000e8, 0x2000600 },
+	{ 0x3d4000ec, 0x810 },
+	{ 0x3d4000f0, 0x20 },
+	{ 0x3d4000f4, 0xec7 },
+	{ 0x3d400100, 0x11122914 },
+	{ 0x3d400104, 0x4051c },
+	{ 0x3d400108, 0x608050d },
+	{ 0x3d40010c, 0x400c },
+	{ 0x3d400110, 0x8030409 },
+	{ 0x3d400114, 0x6060403 },
+	{ 0x3d40011c, 0x606 },
+	{ 0x3d400120, 0x7070d0c },
+	{ 0x3d400124, 0x2040a },
+	{ 0x3d40012c, 0x1809010e },
+	{ 0x3d400130, 0x8 },
+	{ 0x3d40013c, 0x0 },
+	{ 0x3d400180, 0x1000040 },
+	{ 0x3d400184, 0x493e },
+	{ 0x3d400190, 0x38b8207 },
+	{ 0x3d400194, 0x2020303 },
+	{ 0x3d400198, 0x7f04011 },
+	{ 0x3d40019c, 0xb0 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0x48005a },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x1 },
+	{ 0x3d4001b4, 0xb07 },
+	{ 0x3d4001b8, 0x4 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x3f1f },
+	{ 0x3d400204, 0x3f0909 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf07 },
+	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400240, 0x6000610 },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d400400, 0x100 },
+
+	/* performance setting */
+	{ 0x3d400250, 0x00001f05 },
+	{ 0x3d400254, 0x1f },
+	{ 0x3d400264, 0x900003ff },
+	{ 0x3d40026c, 0x200003ff },
+	{ 0x3d400494, 0x01000e00 },
+	{ 0x3d400498, 0x03ff0000 },
+	{ 0x3d40049c, 0x01000e00 },
+	{ 0x3d4004a0, 0x03ff0000 },
+
+	{ 0x3d402050, 0x210070 },
+	{ 0x3d402064, 0x400093 },
+	{ 0x3d4020dc, 0x105 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d4020e8, 0x2000600 },
+	{ 0x3d4020ec, 0x10 },
+	{ 0x3d402100, 0xb081209 },
+	{ 0x3d402104, 0x2020d },
+	{ 0x3d402108, 0x5050309 },
+	{ 0x3d40210c, 0x400c },
+	{ 0x3d402110, 0x5030206 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d40211c, 0x303 },
+	{ 0x3d402120, 0x4040d06 },
+	{ 0x3d402124, 0x20208 },
+	{ 0x3d40212c, 0x1205010e },
+	{ 0x3d402130, 0x8 },
+	{ 0x3d40213c, 0x0 },
+	{ 0x3d402180, 0x1000040 },
+	{ 0x3d402190, 0x3848204 },
+	{ 0x3d402194, 0x2020303 },
+	{ 0x3d4021b4, 0x404 },
+	{ 0x3d4021b8, 0x4 },
+	{ 0x3d402240, 0x6000600 },
+	{ 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2fd },
+	{ 0x1015f, 0x2fd },
+	{ 0x1105f, 0x2fd },
+	{ 0x1115f, 0x2fd },
+	{ 0x11005f, 0x2fd },
+	{ 0x11015f, 0x2fd },
+	{ 0x11105f, 0x2fd },
+	{ 0x11115f, 0x2fd },
+	{ 0x55, 0x355 },
+	{ 0x1055, 0x355 },
+	{ 0x2055, 0x355 },
+	{ 0x3055, 0x355 },
+	{ 0x4055, 0x55 },
+	{ 0x5055, 0x55 },
+	{ 0x6055, 0x355 },
+	{ 0x7055, 0x355 },
+	{ 0x8055, 0x355 },
+	{ 0x9055, 0x355 },
+	{ 0x200c5, 0xa },
+	{ 0x1200c5, 0x6 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x6 },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x1a },
+	{ 0x1014d, 0x1a },
+	{ 0x1104d, 0x1a },
+	{ 0x1114d, 0x1a },
+	{ 0x11004d, 0x1a },
+	{ 0x11014d, 0x1a },
+	{ 0x11104d, 0x1a },
+	{ 0x11114d, 0x1a },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x2 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x258 },
+	{ 0x120008, 0x10a },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x268 },
+	{ 0x10043, 0x5b1 },
+	{ 0x10143, 0x5b1 },
+	{ 0x11043, 0x5b1 },
+	{ 0x11143, 0x5b1 },
+	{ 0x1200b2, 0x268 },
+	{ 0x110043, 0x5b1 },
+	{ 0x110143, 0x5b1 },
+	{ 0x111043, 0x5b1 },
+	{ 0x111143, 0x5b1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x2005b, 0x7529 },
+	{ 0x2005c, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x200cc, 0x1f7 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x1200cc, 0x1f7 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x810 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x42a },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x10 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x810 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xb },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x633 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x633 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x633 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x633 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xb },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x1 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x5 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x0 },
+	{ 0x900a2, 0x8140 },
+	{ 0x900a3, 0x10c },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x8138 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7c8 },
+	{ 0x900a9, 0x101 },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x448 },
+	{ 0x900ac, 0x109 },
+	{ 0x900ad, 0xf },
+	{ 0x900ae, 0x7c0 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x47 },
+	{ 0x900b1, 0x630 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x8 },
+	{ 0x900b4, 0x618 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0xe0 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x0 },
+	{ 0x900ba, 0x7c8 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x8140 },
+	{ 0x900be, 0x10c },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x1 },
+	{ 0x900c1, 0x8 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x8 },
+	{ 0x900c5, 0x8 },
+	{ 0x900c6, 0x7c8 },
+	{ 0x900c7, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2b },
+	{ 0x2000b, 0x4b },
+	{ 0x2000c, 0x96 },
+	{ 0x2000d, 0x5dc },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x21 },
+	{ 0x12000c, 0x42 },
+	{ 0x12000d, 0x29a },
+	{ 0x12000e, 0x21 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1066mts 1D */
+		.drate = 1066,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info imx8mn_evk_ddr4_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 1066, },
+};
diff --git a/arch/arm/boards/nxp-imx8mn-evk/flash-header-imx8mn-evk.imxcfg b/arch/arm/boards/nxp-imx8mn-evk/flash-header-imx8mn-evk.imxcfg
new file mode 100644
index 0000000000..f47ea08266
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mn-evk/flash-header-imx8mn-evk.imxcfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mn
+
+loadaddr 0x912000
+max_load_size 0x3f000
+ivtofs 0x0
+
+#include <mach/imx/flexspi-imx8mp-cfg.h>
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
new file mode 100644
index 0000000000..a1a501b1d9
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <io.h>
+#include <image-metadata.h>
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <firmware.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <linux/sizes.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8mn-regs.h>
+#include <mach/imx/iomux-mx8mn.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mfd/pca9450.h>
+#include <mfd/bd71837.h>
+#include <soc/imx8m/ddr.h>
+
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mn_setup_pad(IMX8MN_PAD_UART2_TXD__UART2_DCE_TX);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+
+	putc_ll('>');
+}
+
+static struct pmic_config pca9450_cfg[] = {
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	{ PCA9450_BUCK123_DVS, 0x29 },
+	/*
+	 * increase VDD_SOC to typical value 0.95V before first
+	 * DRAM access, set DVS1 to 0.85v for suspend.
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+	 */
+	{ PCA9450_BUCK1OUT_DVS0, 0x1C },
+	/* Set DVS1 to 0.85v for suspend */
+	/* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
+	{ PCA9450_BUCK1OUT_DVS1, 0x14 },
+	{ PCA9450_BUCK1CTRL, 0x59 },
+	/* set VDD_SNVS_0V8 from default 0.85V */
+	{ PCA9450_LDO2CTRL, 0xC0 },
+	/* enable LDO4 to 1.2v */
+	{ PCA9450_LDO4CTRL, 0x44 },
+	/* set WDOG_B_CFG to cold reset */
+	{ PCA9450_RESET_CTRL, 0xA1 },
+};
+
+static struct pmic_config bd71837_cfg[] = {
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	{ BD718XX_PWRONCONFIG1, 0x0 },
+	/* unlock the PMIC regs */
+	{ BD718XX_REGLOCK, 0x1 },
+	/* Set VDD_ARM to typical value 0.85v for 1.2Ghz */
+	{ BD718XX_BUCK2_VOLT_RUN, 0xf },
+	/* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */
+	{ BD718XX_BUCK1_VOLT_RUN, 0xf },
+	/* Set VDD_SOC 0.85v for suspend */
+	{ BD718XX_BUCK1_VOLT_SUSP, 0xf },
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	{ BD718XX_4TH_NODVS_BUCK_CTRL, 0x28 },
+	/* lock the PMIC regs */
+	{ BD718XX_REGLOCK, 0x11 },
+};
+
+extern struct dram_timing_info imx8mn_evk_ddr4_timing, imx8mn_evk_lpddr4_timing;
+
+static void start_atf(void)
+{
+	struct pbl_i2c *i2c;
+
+	/*
+	 * If we are in EL3 we are running for the first time and need to
+	 * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
+	 * to DRAM in EL2.
+	 */
+	if (current_el() != 3)
+		return;
+
+	imx8mn_early_clock_init();
+
+	imx8mn_setup_pad(IMX8MN_PAD_I2C1_SCL__I2C1_SCL);
+	imx8mn_setup_pad(IMX8MN_PAD_I2C1_SDA__I2C1_SDA);
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MN_I2C1_BASE_ADDR));
+
+	if (i2c_dev_probe(i2c, 0x25, true) == 0) {
+		pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+		imx8mn_ddr_init(&imx8mn_evk_lpddr4_timing, DRAM_TYPE_LPDDR4);
+	} else {
+		pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg));
+		imx8mn_ddr_init(&imx8mn_evk_ddr4_timing, DRAM_TYPE_DDR4);
+	}
+
+	imx8mn_load_and_start_image_via_tfa();
+}
+
+/*
+ * Power-on execution flow of start_nxp_imx8mn_evk() might not be
+ * obvious for a very first read, so here's, hopefully helpful,
+ * summary:
+ *
+ * 1. MaskROM uploads PBL into OCRAM and that's where this function is
+ *    executed for the first time. At entry the exception level is EL3.
+ *
+ * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL
+ *    part is copied from OCRAM to the TF-A return address in DRAM.
+ *
+ * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us
+ *    from EL3 to EL2.
+ *
+ * 4. Standard barebox boot flow continues
+ */
+static __noreturn noinline void nxp_imx8mn_evk_start(void)
+{
+	extern char __dtb_z_imx8mn_evk_start[], __dtb_z_imx8mn_ddr4_evk_start[];
+	void *fdt;
+
+	setup_uart();
+
+	start_atf();
+
+	/* Check if we configured DDR4 in EL3 */
+	if (readl(MX8M_DDRC_CTL_BASE_ADDR) & BIT(4))
+		fdt = __dtb_z_imx8mn_ddr4_evk_start;
+	else
+		fdt = __dtb_z_imx8mn_evk_start;
+
+	/*
+	 * Standard entry we hit once we initialized both DDR and ATF
+	 */
+	imx8mn_barebox_entry(fdt);
+}
+
+ENTRY_FUNCTION(start_nxp_imx8mn_evk, r0, r1, r2)
+{
+	imx8mn_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	nxp_imx8mn_evk_start();
+}
diff --git a/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c
new file mode 100644
index 0000000000..902c607a82
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c
@@ -0,0 +1,1185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+#define DDR_ONE_RANK
+#include <soc/imx8m/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	{0x3d400020, 0x00000213},
+	{0x3d400024, 0x0003e800},
+	{0x3d400030, 0x00000120},
+	{0x3d400000, 0xa3080020},
+	{0x3d400064, 0x006100e0},
+	{0x3d4000d0, 0xc003061c},
+	{0x3d4000d4, 0x009e0000},
+	{0x3d4000dc, 0x00d4002d},
+	{0x3d4000e0, 0x00310000},
+	{0x3d4000e8, 0x0066004d},
+	{0x3d4000ec, 0x0016004a},
+	{0x3d400100, 0x1a201b22},
+	{0x3d400104, 0x00060633},
+	{0x3d40010c, 0x00c0c000},
+	{0x3d400110, 0x0f04080f},
+	{0x3d400114, 0x02040c0c},
+	{0x3d400118, 0x01010007},
+	{0x3d40011c, 0x00000401},
+	{0x3d400130, 0x00020600},
+	{0x3d400134, 0x0c100002},
+	{0x3d400138, 0x000000e6},
+	{0x3d400144, 0x00a00050},
+	{0x3d400180, 0x03200018},
+	{0x3d400184, 0x028061a8},
+	{0x3d400188, 0x00000000},
+	{0x3d400190, 0x0497820a},
+	{0x3d4001b4, 0x0000170a},
+	{0x3d400108, 0x070e1617},
+	{0x3d4001c0, 0x00000001},
+	{0x3d400194, 0x00080303},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0x00df00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x00000011},
+	{0x3d4001c4, 0x00000001},
+	{0x3d4000f4, 0x00000c99},
+	{0x3d400200, 0x00000017},
+	{0x3d400204, 0x00080808},
+	{0x3d400208, 0x00000000},
+	{0x3d40020c, 0x00000000},
+	{0x3d400210, 0x00001f1f},
+	{0x3d400214, 0x07070707},
+	{0x3d400218, 0x07070707},
+	{0x3d40021c, 0x00000f0f},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x0000002c},
+	{0x3d40025c, 0x04000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x20005574},
+	{0x3d400400, 0x00000111},
+	{0x3d400408, 0x000072ff},
+	{0x3d400494, 0x02100e07},
+	{0x3d400498, 0x00620096},
+	{0x3d40049c, 0x01100e07},
+	{0x3d4004a0, 0x00c8012c},
+	{0x3d402020, 0x00000011},
+	{0x3d402024, 0x00007d00},
+	{0x3d402050, 0x0020d040},
+	{0x3d402064, 0x000c001d},
+	{0x3d4020f4, 0x00000c99},
+	{0x3d402100, 0x0a040305},
+	{0x3d402104, 0x00030407},
+	{0x3d402108, 0x0203060b},
+	{0x3d40210c, 0x00505000},
+	{0x3d402110, 0x02040202},
+	{0x3d402114, 0x02030202},
+	{0x3d402118, 0x01010004},
+	{0x3d40211c, 0x00000301},
+	{0x3d402130, 0x00020300},
+	{0x3d402134, 0x0a100002},
+	{0x3d402138, 0x0000001d},
+	{0x3d402144, 0x0014000a},
+	{0x3d402180, 0x00650004},
+	{0x3d402190, 0x03818200},
+	{0x3d402194, 0x00080303},
+	{0x3d4021b4, 0x00000100},
+	{0x3d4020dc, 0x00840000},
+	{0x3d4020e0, 0x00310000},
+	{0x3d4020e8, 0x0066004d},
+	{0x3d4020ec, 0x0016004a},
+	{0x3d403020, 0x00000011},
+	{0x3d403024, 0x00001f40},
+	{0x3d403050, 0x0020d040},
+	{0x3d403064, 0x00030007},
+	{0x3d4030f4, 0x00000c99},
+	{0x3d403100, 0x0a010102},
+	{0x3d403104, 0x00030404},
+	{0x3d403108, 0x0203060b},
+	{0x3d40310c, 0x00505000},
+	{0x3d403110, 0x02040202},
+	{0x3d403114, 0x02030202},
+	{0x3d403118, 0x01010004},
+	{0x3d40311c, 0x00000301},
+	{0x3d403130, 0x00020300},
+	{0x3d403134, 0x0a100002},
+	{0x3d403138, 0x00000008},
+	{0x3d403144, 0x00050003},
+	{0x3d403180, 0x00190004},
+	{0x3d403190, 0x03818200},
+	{0x3d403194, 0x00080303},
+	{0x3d4031b4, 0x00000100},
+	{0x3d4030dc, 0x00840000},
+	{0x3d4030e0, 0x00310000},
+	{0x3d4030e8, 0x0066004d},
+	{0x3d4030ec, 0x0016004a},
+
+	/* default boot point */
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x000100a0, 0x00000000},
+	{0x000100a1, 0x00000001},
+	{0x000100a2, 0x00000002},
+	{0x000100a3, 0x00000003},
+	{0x000100a4, 0x00000004},
+	{0x000100a5, 0x00000005},
+	{0x000100a6, 0x00000006},
+	{0x000100a7, 0x00000007},
+	{0x000110a0, 0x00000000},
+	{0x000110a1, 0x00000001},
+	{0x000110a2, 0x00000003},
+	{0x000110a3, 0x00000004},
+	{0x000110a4, 0x00000005},
+	{0x000110a5, 0x00000002},
+	{0x000110a6, 0x00000007},
+	{0x000110a7, 0x00000006},
+	{0x0001005f, 0x0000015f},
+	{0x0001015f, 0x0000015f},
+	{0x0001105f, 0x0000015f},
+	{0x0001115f, 0x0000015f},
+	{0x0011005f, 0x0000015f},
+	{0x0011015f, 0x0000015f},
+	{0x0011105f, 0x0000015f},
+	{0x0011115f, 0x0000015f},
+	{0x0021005f, 0x0000015f},
+	{0x0021015f, 0x0000015f},
+	{0x0021105f, 0x0000015f},
+	{0x0021115f, 0x0000015f},
+	{0x00000055, 0x0000016f},
+	{0x00001055, 0x0000016f},
+	{0x00002055, 0x0000016f},
+	{0x00003055, 0x0000016f},
+	{0x00004055, 0x0000016f},
+	{0x00005055, 0x0000016f},
+	{0x00006055, 0x0000016f},
+	{0x00007055, 0x0000016f},
+	{0x00008055, 0x0000016f},
+	{0x00009055, 0x0000016f},
+	{0x000200c5, 0x00000019},
+	{0x001200c5, 0x00000007},
+	{0x002200c5, 0x00000007},
+	{0x0002002e, 0x00000002},
+	{0x0012002e, 0x00000002},
+	{0x0022002e, 0x00000002},
+	{0x00090204, 0x00000000},
+	{0x00190204, 0x00000000},
+	{0x00290204, 0x00000000},
+	{0x00020024, 0x000001a3},
+	{0x0002003a, 0x00000002},
+	{0x0002007d, 0x00000212},
+	{0x0002007c, 0x00000061},
+	{0x00120024, 0x000001a3},
+	{0x0002003a, 0x00000002},
+	{0x0012007d, 0x00000212},
+	{0x0012007c, 0x00000061},
+	{0x00220024, 0x000001a3},
+	{0x0002003a, 0x00000002},
+	{0x0022007d, 0x00000212},
+	{0x0022007c, 0x00000061},
+	{0x00020056, 0x00000003},
+	{0x00120056, 0x00000003},
+	{0x00220056, 0x00000003},
+	{0x0001004d, 0x00000f80},
+	{0x0001014d, 0x00000f80},
+	{0x0001104d, 0x00000f80},
+	{0x0001114d, 0x00000f80},
+	{0x0011004d, 0x00000f80},
+	{0x0011014d, 0x00000f80},
+	{0x0011104d, 0x00000f80},
+	{0x0011114d, 0x00000f80},
+	{0x0021004d, 0x00000f80},
+	{0x0021014d, 0x00000f80},
+	{0x0021104d, 0x00000f80},
+	{0x0021114d, 0x00000f80},
+	{0x00010049, 0x00000fbe},
+	{0x00010149, 0x00000fbe},
+	{0x00011049, 0x00000fbe},
+	{0x00011149, 0x00000fbe},
+	{0x00110049, 0x00000fbe},
+	{0x00110149, 0x00000fbe},
+	{0x00111049, 0x00000fbe},
+	{0x00111149, 0x00000fbe},
+	{0x00210049, 0x00000fbe},
+	{0x00210149, 0x00000fbe},
+	{0x00211049, 0x00000fbe},
+	{0x00211149, 0x00000fbe},
+	{0x00000043, 0x00000063},
+	{0x00001043, 0x00000063},
+	{0x00002043, 0x00000063},
+	{0x00003043, 0x00000063},
+	{0x00004043, 0x00000063},
+	{0x00005043, 0x00000063},
+	{0x00006043, 0x00000063},
+	{0x00007043, 0x00000063},
+	{0x00008043, 0x00000063},
+	{0x00009043, 0x00000063},
+	{0x00020018, 0x00000001},
+	{0x00020075, 0x00000004},
+	{0x00020050, 0x00000000},
+	{0x00020008, 0x00000320},
+	{0x00120008, 0x00000064},
+	{0x00220008, 0x00000019},
+	{0x00020088, 0x00000009},
+	{0x000200b2, 0x000000dc},
+	{0x00010043, 0x000005a1},
+	{0x00010143, 0x000005a1},
+	{0x00011043, 0x000005a1},
+	{0x00011143, 0x000005a1},
+	{0x001200b2, 0x000000dc},
+	{0x00110043, 0x000005a1},
+	{0x00110143, 0x000005a1},
+	{0x00111043, 0x000005a1},
+	{0x00111143, 0x000005a1},
+	{0x002200b2, 0x000000dc},
+	{0x00210043, 0x000005a1},
+	{0x00210143, 0x000005a1},
+	{0x00211043, 0x000005a1},
+	{0x00211143, 0x000005a1},
+	{0x000200fa, 0x00000001},
+	{0x001200fa, 0x00000001},
+	{0x002200fa, 0x00000001},
+	{0x00020019, 0x00000001},
+	{0x00120019, 0x00000001},
+	{0x00220019, 0x00000001},
+	{0x000200f0, 0x00000660},
+	{0x000200f1, 0x00000000},
+	{0x000200f2, 0x00004444},
+	{0x000200f3, 0x00008888},
+	{0x000200f4, 0x00005665},
+	{0x000200f5, 0x00000000},
+	{0x000200f6, 0x00000000},
+	{0x000200f7, 0x0000f000},
+	{0x0001004a, 0x00000500},
+	{0x0001104a, 0x00000500},
+	{0x00020025, 0x00000000},
+	{0x0002002d, 0x00000000},
+	{0x0012002d, 0x00000000},
+	{0x0022002d, 0x00000000},
+	{0x0002002c, 0x00000000},
+	{0x000200c7, 0x00000021},
+	{0x000200ca, 0x00000024},
+	{0x000200cc, 0x000001f7},
+	{0x001200c7, 0x00000021},
+	{0x001200ca, 0x00000024},
+	{0x001200cc, 0x000001f7},
+	{0x002200c7, 0x00000021},
+	{0x002200ca, 0x00000024},
+	{0x002200cc, 0x000001f7},
+	{0x00020060, 0x00000002},
+	{0x000d0000, 0x00000001},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000000},
+	{0x00054003, 0x00000c80},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x0000131f},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00002dd4},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00002dd4},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x0000d400},
+	{0x00054033, 0x0000312d},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x0000d400},
+	{0x00054039, 0x0000312d},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000101},
+	{0x00054003, 0x00000190},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x0000121f},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00000084},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00000084},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x00008400},
+	{0x00054033, 0x00003100},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x00008400},
+	{0x00054039, 0x00003100},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000102},
+	{0x00054003, 0x00000064},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x0000121f},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00000084},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00000084},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x00008400},
+	{0x00054033, 0x00003100},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x00008400},
+	{0x00054039, 0x00003100},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000000},
+	{0x00054003, 0x00000c80},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x00000061},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00001f7f},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00002dd4},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00002dd4},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x0000d400},
+	{0x00054033, 0x0000312d},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x0000d400},
+	{0x00054039, 0x0000312d},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xb},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x633},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x633},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x633},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x633},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x633},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x633},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x633},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x633},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x633},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x633},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x633},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x633},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x633},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xb},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x1},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x625},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x625},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a4, 0x0},
+	{0x900a5, 0x790},
+	{0x900a6, 0x11a},
+	{0x900a7, 0x8},
+	{0x900a8, 0x7aa},
+	{0x900a9, 0x2a},
+	{0x900aa, 0x10},
+	{0x900ab, 0x7b2},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x0},
+	{0x900ae, 0x7c8},
+	{0x900af, 0x109},
+	{0x900b0, 0x10},
+	{0x900b1, 0x10},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x1},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xd},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x448},
+	{0x90169, 0x109},
+	{0x9016a, 0xf},
+	{0x9016b, 0x7c0},
+	{0x9016c, 0x109},
+	{0x9016d, 0x0},
+	{0x9016e, 0xe8},
+	{0x9016f, 0x109},
+	{0x90170, 0x47},
+	{0x90171, 0x630},
+	{0x90172, 0x109},
+	{0x90173, 0x8},
+	{0x90174, 0x618},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0xe0},
+	{0x90178, 0x109},
+	{0x90179, 0x0},
+	{0x9017a, 0x7c8},
+	{0x9017b, 0x109},
+	{0x9017c, 0x8},
+	{0x9017d, 0x8140},
+	{0x9017e, 0x10c},
+	{0x9017f, 0x0},
+	{0x90180, 0x1},
+	{0x90181, 0x8},
+	{0x90182, 0x8},
+	{0x90183, 0x4},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x7c8},
+	{0x90187, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x29},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x64},
+	{0x2000c, 0xc8},
+	{0x2000d, 0x7d0},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x2060},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x20089, 0x1},
+	{0x20088, 0x19},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info imx8mn_evk_lpddr4_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 400, 100, },
+};
diff --git a/arch/arm/boards/nxp-imx8mp-evk/Makefile b/arch/arm/boards/nxp-imx8mp-evk/Makefile
index 4d0d989015..35d8640087 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/Makefile
+++ b/arch/arm/boards/nxp-imx8mp-evk/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/nxp-imx8mp-evk/board.c b/arch/arm/boards/nxp-imx8mp-evk/board.c
index a3ff598108..2aa551e504 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mp-evk/board.c
@@ -6,23 +6,21 @@
 #include <asm/memory.h>
 #include <bootsource.h>
 #include <common.h>
+#include <deep-probe.h>
 #include <init.h>
 #include <linux/phy.h>
 #include <linux/sizes.h>
-#include <mach/bbu.h>
-#include <mach/iomux-mx8mp.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/iomux-mx8mp.h>
 #include <gpio.h>
 #include <envfs.h>
 
-static int nxp_imx8mp_evk_init(void)
+static int nxp_imx8mp_evk_probe(struct device *dev)
 {
 	int emmc_bbu_flag = 0;
 	int sd_bbu_flag = 0;
 	u32 val;
 
-	if (!of_machine_is_compatible("fsl,imx8mp-evk"))
-		return 0;
-
 	if (bootsource_get() == BOOTSOURCE_MMC) {
 		if (bootsource_get_instance() == 2) {
 			of_device_enable_path("/chosen/environment-emmc");
@@ -37,12 +35,26 @@ static int nxp_imx8mp_evk_init(void)
 	}
 
 	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
-	imx8m_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+	imx8m_bbu_internal_flexspi_nor_register_handler("QSPI", "/dev/m25p0.barebox", 0);
 
+	/* Enable RGMII TX clk output */
 	val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
 	val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN;
 	writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
 
 	return 0;
 }
-coredevice_initcall(nxp_imx8mp_evk_init);
+
+static const struct of_device_id nxp_imx8mp_evk_of_match[] = {
+	{ .compatible = "fsl,imx8mp-evk" },
+	{ /* Sentinel */ }
+};
+BAREBOX_DEEP_PROBE_ENABLE(nxp_imx8mp_evk_of_match);
+
+static struct driver nxp_imx8mp_evk_board_driver = {
+	.name = "board-nxp-imx8mp-evk",
+	.probe = nxp_imx8mp_evk_probe,
+	.of_compatible = nxp_imx8mp_evk_of_match,
+};
+coredevice_platform_driver(nxp_imx8mp_evk_board_driver);
diff --git a/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg b/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg
index 7739fe5be6..c896c9f248 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg
+++ b/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg
@@ -1,5 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx8mp
 
 loadaddr 0x920000
 max_load_size 0x3f000
 ivtofs 0x0
+
+#include <mach/imx/flexspi-imx8mp-cfg.h>
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
index 3298ded586..969947d2ec 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
@@ -3,26 +3,28 @@
 #include <io.h>
 #include <common.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <firmware.h>
 #include <asm/mmu.h>
 #include <asm/cache.h>
 #include <asm/sections.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
-#include <i2c/i2c-early.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
 #include <linux/sizes.h>
-#include <mach/atf.h>
-#include <mach/xload.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
-#include <mach/imx8mp-regs.h>
-#include <mach/iomux-mx8mp.h>
-#include <mach/imx8m-ccm-regs.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8mp-regs.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <mach/imx/imx8m-ccm-regs.h>
 #include <mfd/pca9450.h>
 #include <soc/imx8m/ddr.h>
 #include <soc/fsl/fsl_udc.h>
 
-extern char __dtb_imx8mp_evk_start[];
+extern char __dtb_z_imx8mp_evk_start[];
 
 #define UART_PAD_CTRL   MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
 				     MX8MP_PAD_CTL_FSEL)
@@ -47,67 +49,46 @@ static void setup_uart(void)
 	putc_ll('>');
 }
 
-static void pmic_reg_write(void *i2c, int reg, uint8_t val)
-{
-	int ret;
-	u8 buf[32];
-	struct i2c_msg msgs[] = {
-		{
-			.addr = 0x25,
-			.buf = buf,
-		},
-	};
-
-	buf[0] = reg;
-	buf[1] = val;
-
-	msgs[0].len = 2;
-
-	ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
-	if (ret != 1)
-		pr_err("Failed to write to pmic\n");
-}
+static struct pmic_config pca9450_cfg[] = {
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	{ PCA9450_BUCK123_DVS, 0x29 },
+	/*
+	 * increase VDD_SOC to typical value 0.95V before first
+	 * DRAM access, set DVS1 to 0.85v for suspend.
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+	 */
+	{ PCA9450_BUCK1OUT_DVS0, 0x1C },
+	{ PCA9450_BUCK1OUT_DVS1, 0x14 },
+	{ PCA9450_BUCK1CTRL, 0x59 },
+	/*
+	 * Increase VDD_ARM to 0.95V to avoid issues in case software after
+	 * Barebox switches to the OD ARM frequency without reprogramming the
+	 * PMIC first.
+	 */
+	{ PCA9450_BUCK2OUT_DVS0, 0x1C },
+	/* set WDOG_B_CFG to cold reset */
+	{ PCA9450_RESET_CTRL, 0xA1 },
+};
 
-static int power_init_board(void)
+static void power_init_board(void)
 {
-	void *i2c;
+	struct pbl_i2c *i2c;
 
 	imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
 	imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
 
-	imx8mm_early_clock_init();
 	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
 
 	i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
 
-	/* BUCKxOUT_DVS0/1 control BUCK123 output */
-	pmic_reg_write(i2c, PCA9450_BUCK123_DVS, 0x29);
-
-	/*
-	 * increase VDD_SOC to typical value 0.95V before first
-	 * DRAM access, set DVS1 to 0.85v for suspend.
-	 * Enable DVS control through PMIC_STBY_REQ and
-	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
-	 */
-	pmic_reg_write(i2c, PCA9450_BUCK1OUT_DVS0, 0x1C);
-	pmic_reg_write(i2c, PCA9450_BUCK1OUT_DVS1, 0x14);
-	pmic_reg_write(i2c, PCA9450_BUCK1CTRL, 0x59);
-
-	/* set WDOG_B_CFG to cold reset */
-	pmic_reg_write(i2c, PCA9450_RESET_CTRL, 0xA1);
-
-	return 0;
+	pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
 }
 
 extern struct dram_timing_info imx8mp_evk_dram_timing;
 
 static void start_atf(void)
 {
-	size_t bl31_size;
-	const u8 *bl31;
-	enum bootsource src;
-	int instance;
-
 	/*
 	 * If we are in EL3 we are running for the first time and need to
 	 * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
@@ -116,37 +97,13 @@ static void start_atf(void)
 	if (current_el() != 3)
 		return;
 
-	power_init_board();
-
-	imx8mp_ddr_init(&imx8mp_evk_dram_timing);
+	imx8mp_early_clock_init();
 
-	imx8mp_get_boot_source(&src, &instance);
-	switch (src) {
-	case BOOTSOURCE_MMC:
-		imx8mp_esdhc_load_image(instance, false);
-		break;
-	default:
-		printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
-		hang();
-	}
-
-
-	/*
-	 * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
-	 * in EL2. Copy the image there, but replace the PBL part of
-	 * that image with ourselves. On a high assurance boot only the
-	 * currently running code is validated and contains the checksum
-	 * for the piggy data, so we need to ensure that we are running
-	 * the same code in DRAM.
-	 */
-	memcpy((void *)MX8M_ATF_BL33_BASE_ADDR,
-	       __image_start, barebox_pbl_size);
-
-	get_builtin_firmware(imx8mp_bl31_bin, &bl31, &bl31_size);
+	power_init_board();
 
-	imx8mp_atf_load_bl31(bl31, bl31_size);
+	imx8mp_ddr_init(&imx8mp_evk_dram_timing, DRAM_TYPE_LPDDR4);
 
-	/* not reached */
+	imx8mp_load_and_start_image_via_tfa();
 }
 
 /*
@@ -174,16 +131,11 @@ static __noreturn noinline void nxp_imx8mp_evk_start(void)
 	/*
 	 * Standard entry we hit once we initialized both DDR and ATF
 	 */
-	imx8mp_barebox_entry(__dtb_imx8mp_evk_start);
+	imx8mp_barebox_entry(__dtb_z_imx8mp_evk_start);
 }
 
 ENTRY_FUNCTION(start_nxp_imx8mp_evk, r0, r1, r2)
 {
-	void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
-
-	writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
-	       ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_SCTR));
-
 	imx8mp_cpu_lowlevel_init();
 
 	relocate_to_current_adr();
diff --git a/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c
index 3028bc084c..d929890e15 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c
+++ b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c
@@ -325,729 +325,6 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{ 0x2002c, 0x0 },
 };
 
-/* ddr phy trained csr */
-static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
-	{ 0x200b2, 0x0 },
-	{ 0x1200b2, 0x0 },
-	{ 0x2200b2, 0x0 },
-	{ 0x200cb, 0x0 },
-	{ 0x10043, 0x0 },
-	{ 0x110043, 0x0 },
-	{ 0x210043, 0x0 },
-	{ 0x10143, 0x0 },
-	{ 0x110143, 0x0 },
-	{ 0x210143, 0x0 },
-	{ 0x11043, 0x0 },
-	{ 0x111043, 0x0 },
-	{ 0x211043, 0x0 },
-	{ 0x11143, 0x0 },
-	{ 0x111143, 0x0 },
-	{ 0x211143, 0x0 },
-	{ 0x12043, 0x0 },
-	{ 0x112043, 0x0 },
-	{ 0x212043, 0x0 },
-	{ 0x12143, 0x0 },
-	{ 0x112143, 0x0 },
-	{ 0x212143, 0x0 },
-	{ 0x13043, 0x0 },
-	{ 0x113043, 0x0 },
-	{ 0x213043, 0x0 },
-	{ 0x13143, 0x0 },
-	{ 0x113143, 0x0 },
-	{ 0x213143, 0x0 },
-	{ 0x80, 0x0 },
-	{ 0x100080, 0x0 },
-	{ 0x200080, 0x0 },
-	{ 0x1080, 0x0 },
-	{ 0x101080, 0x0 },
-	{ 0x201080, 0x0 },
-	{ 0x2080, 0x0 },
-	{ 0x102080, 0x0 },
-	{ 0x202080, 0x0 },
-	{ 0x3080, 0x0 },
-	{ 0x103080, 0x0 },
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-	{ 0x400c0, 0x0 },
-	{ 0x90201, 0x0 },
-	{ 0x190201, 0x0 },
-	{ 0x290201, 0x0 },
-	{ 0x90202, 0x0 },
-	{ 0x190202, 0x0 },
-	{ 0x290202, 0x0 },
-	{ 0x90203, 0x0 },
-	{ 0x190203, 0x0 },
-	{ 0x290203, 0x0 },
-	{ 0x90204, 0x0 },
-	{ 0x190204, 0x0 },
-	{ 0x290204, 0x0 },
-	{ 0x90205, 0x0 },
-	{ 0x190205, 0x0 },
-	{ 0x290205, 0x0 },
-	{ 0x90206, 0x0 },
-	{ 0x190206, 0x0 },
-	{ 0x290206, 0x0 },
-	{ 0x90207, 0x0 },
-	{ 0x190207, 0x0 },
-	{ 0x290207, 0x0 },
-	{ 0x90208, 0x0 },
-	{ 0x190208, 0x0 },
-	{ 0x290208, 0x0 },
-	{ 0x10062, 0x0 },
-	{ 0x10162, 0x0 },
-	{ 0x10262, 0x0 },
-	{ 0x10362, 0x0 },
-	{ 0x10462, 0x0 },
-	{ 0x10562, 0x0 },
-	{ 0x10662, 0x0 },
-	{ 0x10762, 0x0 },
-	{ 0x10862, 0x0 },
-	{ 0x11062, 0x0 },
-	{ 0x11162, 0x0 },
-	{ 0x11262, 0x0 },
-	{ 0x11362, 0x0 },
-	{ 0x11462, 0x0 },
-	{ 0x11562, 0x0 },
-	{ 0x11662, 0x0 },
-	{ 0x11762, 0x0 },
-	{ 0x11862, 0x0 },
-	{ 0x12062, 0x0 },
-	{ 0x12162, 0x0 },
-	{ 0x12262, 0x0 },
-	{ 0x12362, 0x0 },
-	{ 0x12462, 0x0 },
-	{ 0x12562, 0x0 },
-	{ 0x12662, 0x0 },
-	{ 0x12762, 0x0 },
-	{ 0x12862, 0x0 },
-	{ 0x13062, 0x0 },
-	{ 0x13162, 0x0 },
-	{ 0x13262, 0x0 },
-	{ 0x13362, 0x0 },
-	{ 0x13462, 0x0 },
-	{ 0x13562, 0x0 },
-	{ 0x13662, 0x0 },
-	{ 0x13762, 0x0 },
-	{ 0x13862, 0x0 },
-	{ 0x20077, 0x0 },
-	{ 0x10001, 0x0 },
-	{ 0x11001, 0x0 },
-	{ 0x12001, 0x0 },
-	{ 0x13001, 0x0 },
-	{ 0x10040, 0x0 },
-	{ 0x10140, 0x0 },
-	{ 0x10240, 0x0 },
-	{ 0x10340, 0x0 },
-	{ 0x10440, 0x0 },
-	{ 0x10540, 0x0 },
-	{ 0x10640, 0x0 },
-	{ 0x10740, 0x0 },
-	{ 0x10840, 0x0 },
-	{ 0x10030, 0x0 },
-	{ 0x10130, 0x0 },
-	{ 0x10230, 0x0 },
-	{ 0x10330, 0x0 },
-	{ 0x10430, 0x0 },
-	{ 0x10530, 0x0 },
-	{ 0x10630, 0x0 },
-	{ 0x10730, 0x0 },
-	{ 0x10830, 0x0 },
-	{ 0x11040, 0x0 },
-	{ 0x11140, 0x0 },
-	{ 0x11240, 0x0 },
-	{ 0x11340, 0x0 },
-	{ 0x11440, 0x0 },
-	{ 0x11540, 0x0 },
-	{ 0x11640, 0x0 },
-	{ 0x11740, 0x0 },
-	{ 0x11840, 0x0 },
-	{ 0x11030, 0x0 },
-	{ 0x11130, 0x0 },
-	{ 0x11230, 0x0 },
-	{ 0x11330, 0x0 },
-	{ 0x11430, 0x0 },
-	{ 0x11530, 0x0 },
-	{ 0x11630, 0x0 },
-	{ 0x11730, 0x0 },
-	{ 0x11830, 0x0 },
-	{ 0x12040, 0x0 },
-	{ 0x12140, 0x0 },
-	{ 0x12240, 0x0 },
-	{ 0x12340, 0x0 },
-	{ 0x12440, 0x0 },
-	{ 0x12540, 0x0 },
-	{ 0x12640, 0x0 },
-	{ 0x12740, 0x0 },
-	{ 0x12840, 0x0 },
-	{ 0x12030, 0x0 },
-	{ 0x12130, 0x0 },
-	{ 0x12230, 0x0 },
-	{ 0x12330, 0x0 },
-	{ 0x12430, 0x0 },
-	{ 0x12530, 0x0 },
-	{ 0x12630, 0x0 },
-	{ 0x12730, 0x0 },
-	{ 0x12830, 0x0 },
-	{ 0x13040, 0x0 },
-	{ 0x13140, 0x0 },
-	{ 0x13240, 0x0 },
-	{ 0x13340, 0x0 },
-	{ 0x13440, 0x0 },
-	{ 0x13540, 0x0 },
-	{ 0x13640, 0x0 },
-	{ 0x13740, 0x0 },
-	{ 0x13840, 0x0 },
-	{ 0x13030, 0x0 },
-	{ 0x13130, 0x0 },
-	{ 0x13230, 0x0 },
-	{ 0x13330, 0x0 },
-	{ 0x13430, 0x0 },
-	{ 0x13530, 0x0 },
-	{ 0x13630, 0x0 },
-	{ 0x13730, 0x0 },
-	{ 0x13830, 0x0 },
-};
-
 /* P0 message block paremeter for training firmware */
 static struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0xd0000, 0x0 },
@@ -1840,8 +1117,6 @@ struct dram_timing_info imx8mp_evk_dram_timing = {
 	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
 	.fsp_msg = ddr_dram_fsp_msg,
 	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
-	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
-	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
 	.ddrphy_pie = ddr_phy_pie,
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 4000, 400, 100, },
diff --git a/arch/arm/boards/nxp-imx8mq-evk/.gitignore b/arch/arm/boards/nxp-imx8mq-evk/.gitignore
index ef13747c92..cafa52b207 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/.gitignore
+++ b/arch/arm/boards/nxp-imx8mq-evk/.gitignore
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 *.ddr-phy-fw*
diff --git a/arch/arm/boards/nxp-imx8mq-evk/Makefile b/arch/arm/boards/nxp-imx8mq-evk/Makefile
index 2995f06f0f..17d769f330 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/Makefile
+++ b/arch/arm/boards/nxp-imx8mq-evk/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o ddr_init.o ddrphy_train.o
diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c
index c28107cb17..d86666958a 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -7,7 +7,7 @@
 #include <init.h>
 #include <linux/phy.h>
 #include <linux/sizes.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
 #include <envfs.h>
 
@@ -40,7 +40,7 @@ static int nxp_imx8mq_evk_init(void)
 	barebox_set_hostname("imx8mq-evk");
 
 	flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0;
-	imx8m_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0.barebox", flags);
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", flags);
 
 	flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0;
 	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", flags);
diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
index 39addea973..b1f752c4cb 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
@@ -81,6 +81,7 @@ void ddr_init(void)
 	reg32_write(0x3d400200,0x15);
 	reg32_write(0x3d40020c,0x0);
 	reg32_write(0x3d400210,0x1f1f);
+	reg32_write(0x3d40021c,0xf0f);
 	reg32_write(0x3d400204,0x80808);
 	reg32_write(0x3d400214,0x7070707);
 	reg32_write(0x3d400218,0x48080707);
@@ -222,4 +223,4 @@ void ddr_init(void)
 	/* enable DDR auto-refresh mode */
 	tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
 	reg32_write(DDRC_RFSHCTL3(0), tmp);
-}
\ No newline at end of file
+}
diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
index 1b30ff7257..bac7d0a517 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
@@ -11,6 +11,8 @@
 void ddr_cfg_phy(void) {
 	unsigned int tmp, tmp_t;
 
+	ddr_get_firmware(DRAM_TYPE_LPDDR4);
+
 	//Init DDRPHY register...
 	reg32_write(0x3c080440,0x2);
 	reg32_write(0x3c080444,0x3);
@@ -142,7 +144,7 @@ void ddr_cfg_phy(void) {
 	//enable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	//load the 1D training image
-	ddr_load_train_code(FW_1D_IMAGE);
+	imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE);
 
 	//configure DDRPHY-FW DMEM structure @clock0...
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
@@ -187,7 +189,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
+	imx8m_wait_ddrphy_training_complete();
 
 	//configure DDRPHY-FW DMEM structure @clock1...
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
@@ -256,7 +258,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
+	imx8m_wait_ddrphy_training_complete();
 
 	//set the PHY input clock to the desired frequency for pstate 0
 	reg32_write(0x3038a088,0x7070000);
@@ -289,7 +291,7 @@ void ddr_cfg_phy(void) {
 	//enable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	//load the 2D training image
-	ddr_load_train_code(FW_2D_IMAGE);
+	imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE);
 
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11);
@@ -330,7 +332,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
+	imx8m_wait_ddrphy_training_complete();
 
 	//Halt MPU
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
@@ -932,4 +934,4 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0);
 	//disable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-}
\ No newline at end of file
+}
diff --git a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
index 80ce03e22c..f82759f849 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
+++ b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
@@ -1,6 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx8mq
 
 loadaddr 0x007E1000
 max_load_size 0x3F000
 ivtofs 0x400
-#include <mach/habv4-imx8-gencsf.h>
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index 564621abef..d1a517dddb 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -3,24 +3,25 @@
 #include <common.h>
 #include <firmware.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx8m-ccm-regs.h>
-#include <mach/iomux-mx8mq.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/iomux-mx8mq.h>
 #include <soc/imx8m/ddr.h>
-#include <mach/xload.h>
+#include <mach/imx/xload.h>
 #include <io.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
 #include <asm/sections.h>
 #include <asm/mmu.h>
-#include <mach/atf.h>
-#include <mach/esdctl.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/esdctl.h>
 
 #include "ddr.h"
 
-extern char __dtb_imx8mq_evk_start[];
+extern char __dtb_z_imx8mq_evk_start[];
 
 #define UART_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
 
@@ -64,39 +65,15 @@ static __noreturn noinline void nxp_imx8mq_evk_start(void)
 	 * to DRAM in EL2.
 	 */
 	if (current_el() == 3) {
-		enum bootsource src = BOOTSOURCE_UNKNOWN;
-		int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
-		int ret = -ENOTSUPP;
-		size_t bl31_size;
-		const u8 *bl31;
-
 		ddr_init();
 
-		/*
-		 * On completion the TF-A will jump to MX8MQ_ATF_BL33_BASE_ADDR
-		 * in EL2. Copy the image there, but replace the PBL part of
-		 * that image with ourselves. On a high assurance boot only the
-		 * currently running code is validated and contains the checksum
-		 * for the piggy data, so we need to ensure that we are running
-		 * the same code in DRAM.
-		 */
-		imx8mq_get_boot_source(&src, &instance);
-		if (src == BOOTSOURCE_MMC)
-			ret = imx8m_esdhc_load_image(instance, false);
-		BUG_ON(ret);
-
-		memcpy((void *)MX8MQ_ATF_BL33_BASE_ADDR,
-		       __image_start, barebox_pbl_size);
-
-		get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size);
-		imx8mq_atf_load_bl31(bl31, bl31_size);
-		/* not reached */
+		imx8mq_load_and_start_image_via_tfa();
 	}
 
 	/*
 	 * Standard entry we hit once we initialized both DDR and ATF
 	 */
-	imx8mq_barebox_entry(__dtb_imx8mq_evk_start);
+	imx8mq_barebox_entry(__dtb_z_imx8mq_evk_start);
 }
 
 ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
diff --git a/arch/arm/boards/omap343xdsp/Makefile b/arch/arm/boards/omap343xdsp/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/omap343xdsp/Makefile
+++ b/arch/arm/boards/omap343xdsp/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c
index 045a8b1bca..ca1cf9c58c 100644
--- a/arch/arm/boards/omap343xdsp/board.c
+++ b/arch/arm/boards/omap343xdsp/board.c
@@ -7,9 +7,9 @@
 #include <driver.h>
 #include <io.h>
 #include <asm/armlinux.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap3-devices.h>
-#include <mach/gpmc.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap3-devices.h>
+#include <mach/omap/gpmc.h>
 #include <errno.h>
 
 /**
diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c
index fb99ea9278..3a8165f885 100644
--- a/arch/arm/boards/omap343xdsp/lowlevel.c
+++ b/arch/arm/boards/omap343xdsp/lowlevel.c
@@ -1,17 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <io.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/generic.h>
-#include <mach/omap3-mux.h>
-#include <mach/sdrc.h>
-#include <mach/control.h>
-#include <mach/syslib.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap3-generic.h>
-#include <mach/sys_info.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/omap3-mux.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/control.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap3-generic.h>
+#include <mach/omap/sys_info.h>
 
 /**
  * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0
diff --git a/arch/arm/boards/omap3evm/Makefile b/arch/arm/boards/omap3evm/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/omap3evm/Makefile
+++ b/arch/arm/boards/omap3evm/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/omap3evm/board.c b/arch/arm/boards/omap3evm/board.c
index 62b1a1c00f..37dbc0044e 100644
--- a/arch/arm/boards/omap3evm/board.c
+++ b/arch/arm/boards/omap3evm/board.c
@@ -32,12 +32,12 @@
 #include <io.h>
 #include <linux/sizes.h>
 #include <asm/armlinux.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap3-mux.h>
-#include <mach/gpmc.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap3-mux.h>
+#include <mach/omap/gpmc.h>
 #include <errno.h>
-#include <generated/mach-types.h>
-#include <mach/omap3-devices.h>
+#include <asm/mach-types.h>
+#include <mach/omap/omap3-devices.h>
 
 /**
  * @brief Initialize the serial port to be used as console.
diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c
index e06ece2560..5797acc14e 100644
--- a/arch/arm/boards/omap3evm/lowlevel.c
+++ b/arch/arm/boards/omap3evm/lowlevel.c
@@ -1,16 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <io.h>
 #include <init.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/generic.h>
-#include <mach/omap3-mux.h>
-#include <mach/sdrc.h>
-#include <mach/control.h>
-#include <mach/syslib.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap3-generic.h>
-#include <mach/sys_info.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/omap3-mux.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/control.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap3-generic.h>
+#include <mach/omap/sys_info.h>
 
 
 /*
diff --git a/arch/arm/boards/panda/Makefile b/arch/arm/boards/panda/Makefile
index 5d4eb10b9b..3bd91350ce 100644
--- a/arch/arm/boards/panda/Makefile
+++ b/arch/arm/boards/panda/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o mux.o
diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c
index a0a00782d3..55836d2331 100644
--- a/arch/arm/boards/panda/board.c
+++ b/arch/arm/boards/panda/board.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <console.h>
 #include <init.h>
@@ -5,14 +7,14 @@
 #include <io.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-devices.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/control.h>
-#include <usb/ehci.h>
+#include <asm/mach-types.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-devices.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/control.h>
+#include <linux/usb/ehci.h>
 #include <linux/err.h>
 #include <linux/sizes.h>
 #include <asm/mmu.h>
diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
index 4fe445b17d..f535e7f9a4 100644
--- a/arch/arm/boards/panda/lowlevel.c
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -5,12 +5,12 @@
 #include <init.h>
 #include <io.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
-#include <mach/omap4-mux.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-generic.h>
-#include <mach/omap4-clock.h>
-#include <mach/syslib.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/omap4-mux.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-generic.h>
+#include <mach/omap/omap4-clock.h>
+#include <mach/omap/syslib.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
 
diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c
index 76d1c51005..b5e1e79c8f 100644
--- a/arch/arm/boards/panda/mux.c
+++ b/arch/arm/boards/panda/mux.c
@@ -1,9 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-mux.h>
-#include <mach/omap4-clock.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-mux.h>
+#include <mach/omap/omap4-clock.h>
 
 #include "mux.h"
 
diff --git a/arch/arm/boards/panda/mux.h b/arch/arm/boards/panda/mux.h
index 11f2848a27..540d4e5d34 100644
--- a/arch/arm/boards/panda/mux.h
+++ b/arch/arm/boards/panda/mux.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __BOARD_MUX_H
 #define __BOARD_MUX_H
 
diff --git a/arch/arm/boards/phytec-phycard-imx27/Makefile b/arch/arm/boards/phytec-phycard-imx27/Makefile
index 34492bb127..0e6411d588 100644
--- a/arch/arm/boards/phytec-phycard-imx27/Makefile
+++ b/arch/arm/boards/phytec-phycard-imx27/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 lwl-y += lowlevel.o
 obj-y += pca100.o
diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
index 40d39680fd..a43406e1a2 100644
--- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 /*
  * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
  * Applications Processor Reference Manual, Rev. 0.2".
@@ -10,10 +12,10 @@
 #include <config.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <mach/imx-nand.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/imx-pll.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/imx-nand.h>
 
 enum {
 	PHYCARD_MICRON_64MB,
diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.c b/arch/arm/boards/phytec-phycard-imx27/pca100.c
index ed243fa01e..2d0ae7cf80 100644
--- a/arch/arm/boards/phytec-phycard-imx27/pca100.c
+++ b/arch/arm/boards/phytec-phycard-imx27/pca100.c
@@ -5,26 +5,25 @@
 #include <net.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/imx27-regs.h>
+#include <mach/imx/imx27-regs.h>
 #include <gpio.h>
 #include <linux/sizes.h>
 #include <asm/armlinux.h>
 #include <asm/sections.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <nand.h>
 #include <spi/spi.h>
 #include <io.h>
-#include <mach/imx-nand.h>
-#include <mach/imx-pll.h>
-#include <mach/imxfb.h>
+#include <mach/imx/imx-nand.h>
+#include <mach/imx/imx-pll.h>
+#include <platform_data/imxfb.h>
 #include <asm/mmu.h>
-#include <usb/ulpi.h>
-#include <mach/bbu.h>
-#include <mach/iomux-mx27.h>
-#include <mach/devices-imx27.h>
+#include <linux/usb/ulpi.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/iomux-mx27.h>
+#include <mach/imx/devices-imx27.h>
 
 #if defined(CONFIG_USB) && defined(CONFIG_USB_ULPI)
 static void pca100_usb_register(void)
diff --git a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c
index 54d8eaaddf..56fbdf12ad 100644
--- a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c
@@ -1,17 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <io.h>
 #include <init.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/omap3-mux.h>
-#include <mach/generic.h>
-#include <mach/sdrc.h>
-#include <mach/control.h>
-#include <mach/syslib.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap3-generic.h>
-#include <mach/sys_info.h>
+#include <mach/omap/omap3-mux.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/control.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap3-generic.h>
+#include <mach/omap/sys_info.h>
 
 /* Slower full frequency range default timings for x32 operation */
 #define SDP_SDRC_SHARING	0x00000100
@@ -98,7 +100,7 @@ static void config_sdram_ddr(u8 cs, u8 cfg)
 static void pcaal1_sdrc_init(void)
 {
 	u32 test0, test1;
-	char cfg;
+	signed char cfg;
 
 	init_sdram_ddr();
 
diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c
index e3b148a0ed..d878dba082 100644
--- a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c
+++ b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c
@@ -37,19 +37,18 @@
 #include <errno.h>
 #include <init.h>
 #include <nand.h>
-#include <partition.h>
 #include <linux/sizes.h>
 #include <asm/armlinux.h>
 #include <asm/io.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <linux/err.h>
-#include <mach/gpmc.h>
-#include <mach/gpmc_nand.h>
-#include <mach/omap_hsmmc.h>
-#include <mach/sdrc.h>
-#include <mach/omap3-silicon.h>
-#include <mach/sys_info.h>
-#include <mach/omap3-devices.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/gpmc_nand.h>
+#include <mach/omap/omap_hsmmc.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/omap3-devices.h>
 
 #define SMC911X_BASE 0x2c000000
 
diff --git a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c
index 6ccaf3e342..b5906234d3 100644
--- a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c
@@ -5,12 +5,12 @@
 #include <init.h>
 #include <io.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
-#include <mach/omap4-mux.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-generic.h>
-#include <mach/omap4-clock.h>
-#include <mach/syslib.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/omap4-mux.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-generic.h>
+#include <mach/omap/omap4-clock.h>
+#include <mach/omap/syslib.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
 
diff --git a/arch/arm/boards/phytec-phycard-omap4/mux.c b/arch/arm/boards/phytec-phycard-omap4/mux.c
index 564944d1ba..a545ca5948 100644
--- a/arch/arm/boards/phytec-phycard-omap4/mux.c
+++ b/arch/arm/boards/phytec-phycard-omap4/mux.c
@@ -1,9 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-mux.h>
-#include <mach/omap4-clock.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-mux.h>
+#include <mach/omap/omap4-clock.h>
 
 #include "mux.h"
 
diff --git a/arch/arm/boards/phytec-phycard-omap4/mux.h b/arch/arm/boards/phytec-phycard-omap4/mux.h
index 8b1a3d37e9..46a2434ad0 100644
--- a/arch/arm/boards/phytec-phycard-omap4/mux.h
+++ b/arch/arm/boards/phytec-phycard-omap4/mux.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __BOARD_MUX_H
 #define __BOARD_MUX_H
 
diff --git a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c
index ab5976ff8a..f18f11c331 100644
--- a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c
+++ b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c
@@ -8,21 +8,20 @@
 #include <io.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <mach/omap4-silicon.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/control.h>
+#include <asm/mach-types.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/control.h>
 #include <linux/err.h>
 #include <linux/sizes.h>
-#include <partition.h>
 #include <nand.h>
 #include <asm/mmu.h>
-#include <mach/gpmc.h>
-#include <mach/gpmc_nand.h>
-#include <mach/omap_hsmmc.h>
-#include <mach/omap4-devices.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/gpmc_nand.h>
+#include <mach/omap/omap_hsmmc.h>
+#include <mach/omap/omap4-devices.h>
 #include <i2c/i2c.h>
 
 static int pcaaxl2_console_init(void)
diff --git a/arch/arm/boards/phytec-phycore-imx27/Makefile b/arch/arm/boards/phytec-phycore-imx27/Makefile
index 4723c77818..ce7b990407 100644
--- a/arch/arm/boards/phytec-phycore-imx27/Makefile
+++ b/arch/arm/boards/phytec-phycore-imx27/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y	+= pcm038.o pcm970.o
 lwl-y	+= lowlevel.o
 bbenv-y += defaultenv-pcm038
diff --git a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c
index 4e2f44d216..a42b30a7bb 100644
--- a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c
@@ -3,11 +3,11 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/imx-pll.h>
+#include <mach/imx/esdctl.h>
 #include <io.h>
-#include <mach/imx-nand.h>
+#include <mach/imx/imx-nand.h>
 #include <asm/barebox-arm.h>
 #include <asm/system.h>
 #include <asm-generic/memory_layout.h>
diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm038.c b/arch/arm/boards/phytec-phycore-imx27/pcm038.c
index 90ce579684..69a0458f05 100644
--- a/arch/arm/boards/phytec-phycore-imx27/pcm038.c
+++ b/arch/arm/boards/phytec-phycore-imx27/pcm038.c
@@ -11,13 +11,13 @@
 #include <notifier.h>
 #include <linux/sizes.h>
 #include <envfs.h>
-#include <mach/devices-imx27.h>
-#include <mach/imx-pll.h>
-#include <mach/imx27-regs.h>
-#include <mach/imxfb.h>
-#include <mach/iomux-mx27.h>
+#include <mach/imx/devices-imx27.h>
+#include <mach/imx/imx-pll.h>
+#include <mach/imx/imx27-regs.h>
+#include <platform_data/imxfb.h>
+#include <mach/imx/iomux-mx27.h>
 #include <mfd/mc13xxx.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
 #include "pll.h"
 
diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm970.c b/arch/arm/boards/phytec-phycore-imx27/pcm970.c
index b7fad6dcbc..1e466e0ec8 100644
--- a/arch/arm/boards/phytec-phycore-imx27/pcm970.c
+++ b/arch/arm/boards/phytec-phycore-imx27/pcm970.c
@@ -6,8 +6,8 @@
 #include <io.h>
 #include <platform_data/ide.h>
 #include <linux/sizes.h>
-#include <mach/imx27-regs.h>
-#include <mach/iomux-mx27.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/iomux-mx27.h>
 
 #define GPIO_IDE_POWER	(GPIO_PORTE + 18)
 #define GPIO_IDE_PCOE	(GPIO_PORTF + 7)
@@ -28,7 +28,7 @@ static struct ide_port_info pcm970_ide_pdata = {
 	.reset		= &pcm970_ide_reset,
 };
 
-static struct device_d pcm970_ide_device = {
+static struct device pcm970_ide_device = {
 	.id		= DEVICE_ID_DYNAMIC,
 	.name		= "ide_intf",
 	.num_resources	= ARRAY_SIZE(pcm970_ide_resources),
diff --git a/arch/arm/boards/phytec-phycore-imx31/Makefile b/arch/arm/boards/phytec-phycore-imx31/Makefile
deleted file mode 100644
index 1a5be8e81f..0000000000
--- a/arch/arm/boards/phytec-phycore-imx31/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de>
-
-lwl-y += lowlevel.o
-obj-y += pcm037.o
diff --git a/arch/arm/boards/phytec-phycore-imx31/env/boot/nand-ubi b/arch/arm/boards/phytec-phycore-imx31/env/boot/nand-ubi
deleted file mode 100644
index d555a538d1..0000000000
--- a/arch/arm/boards/phytec-phycore-imx31/env/boot/nand-ubi
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/sh
-
-global.bootm.image="/dev/nand0.kernel.bb"
-#global.bootm.oftree="/env/oftree"
-global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs"
diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand
deleted file mode 100644
index 540277cdeb..0000000000
--- a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
-kernelname="mxc_nand"
-
-mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor
deleted file mode 100644
index 940eb86c95..0000000000
--- a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-mtdparts="256k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
-kernelname="physmap-flash.0"
-
-mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c
deleted file mode 100644
index 7e1c6efd3f..0000000000
--- a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-#include <common.h>
-#include <init.h>
-#include <io.h>
-#include <mach/imx-nand.h>
-#include <asm/barebox-arm.h>
-#include <asm/system.h>
-#include <asm-generic/memory_layout.h>
-#include <asm-generic/sections.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/imx31-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-
-#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
-
-void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	uint32_t r;
-	volatile int v;
-
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE);
-
-	writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
-
-	writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
-
-	for (v = 0; v < 0x4000; v++);
-
-	writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
-			MX31_CCM_CCMR);
-	writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
-			MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
-
-	writel(MX31_PDR0_CSI_PODF(0xff1) | \
-		MX31_PDR0_PER_PODF(7) | \
-		MX31_PDR0_HSP_PODF(3) | \
-		MX31_PDR0_NFC_PODF(5) | \
-		MX31_PDR0_IPG_PODF(1) | \
-		MX31_PDR0_MAX_PODF(3) | \
-		MX31_PDR0_MCU_PODF(0), \
-		MX31_CCM_BASE_ADDR + MX31_CCM_PDR0);
-
-	writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) |
-			IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd),
-			MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL);
-	writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
-			IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
-			MX31_CCM_SPCTL);
-
-	/*
-	 * Configure IOMUXC
-	 * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched),
-	 * 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
-	 * (behaviour copied by sha, source unknown)
-	 */
-	writel(0, 0x43fac26c);
-	writel(0, 0x43fac270);
-	writel(0, 0x43fac274);
-
-	writel(0x1000, 0x43fac27c);
-
-	for (r = 0x43fac284; r <= 0x43fac2dc; r += 4)
-		writel(0, r);
-
-	/* Skip SDRAM initialization if we run from RAM */
-	r = get_pc();
-	if (r > 0x80000000 && r < 0xa0000000)
-		imx31_barebox_entry(NULL);
-
-#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
-#define ROWS0	ESDCTL0_ROW13
-#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
-#define ROWS0	ESDCTL0_ROW14
-#endif
-	writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
-	writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00);
-	writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writel(0x12344321, MX31_CSD0_BASE_ADDR);
-	writel(0x12344321, MX31_CSD0_BASE_ADDR);
-	writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33);
-	writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000);
-	writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR);
-	writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-
-#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
-#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
-#define ROWS1	ESDCTL0_ROW13
-#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
-#define ROWS1	ESDCTL0_ROW14
-#endif
-	writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1);
-	writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
-	writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00);
-	writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
-	writel(0x12344321, MX31_CSD1_BASE_ADDR);
-	writel(0x12344321, MX31_CSD1_BASE_ADDR);
-	writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
-	writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33);
-	writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000);
-	writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
-	writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR);
-	writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-#endif
-
-	if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND))
-		imx31_barebox_boot_nand_external();
-	else
-		imx31_barebox_entry(NULL);
-}
diff --git a/arch/arm/boards/phytec-phycore-imx31/pcm037.c b/arch/arm/boards/phytec-phycore-imx31/pcm037.c
deleted file mode 100644
index 52b97fe777..0000000000
--- a/arch/arm/boards/phytec-phycore-imx31/pcm037.c
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-/* Board support for Phytec's, i.MX31 based CPU card, called: PCM037 */
-
-#include <common.h>
-#include <init.h>
-#include <driver.h>
-#include <fs.h>
-#include <gpio.h>
-#include <environment.h>
-#include <usb/ulpi.h>
-#include <mach/imx31-regs.h>
-#include <mach/iomux-mx31.h>
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <mach/weim.h>
-#include <io.h>
-#include <platform_data/eth-smc911x.h>
-#include <asm/mmu.h>
-#include <partition.h>
-#include <generated/mach-types.h>
-#include <asm/barebox-arm.h>
-#include <mach/imx-nand.h>
-#include <mach/devices-imx31.h>
-
-struct imx_nand_platform_data nand_info = {
-	.width = 1,
-	.hw_ecc = 1,
-	.flash_bbt = 1,
-};
-
-#ifdef CONFIG_USB
-static void pcm037_usb_init(void)
-{
-	u32 tmp;
-
-	/* enable clock */
-	tmp = readl(0x53f80000);
-	tmp |= (1 << 9);
-	writel(tmp, 0x53f80000);
-
-	/* Host 1 */
-	tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
-	tmp &= ~((3 << 21) | 1);
-	tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20);
-	writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
-
-	tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x184);
-	tmp &= ~(3 << 30);
-	tmp |= 2 << 30;
-	writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x184);
-
-	imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0);
-	imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1);
-	imx_iomux_mode(MX31_PIN_USBOTG_DATA2__USBOTG_DATA2);
-	imx_iomux_mode(MX31_PIN_USBOTG_DATA3__USBOTG_DATA3);
-	imx_iomux_mode(MX31_PIN_USBOTG_DATA4__USBOTG_DATA4);
-	imx_iomux_mode(MX31_PIN_USBOTG_DATA5__USBOTG_DATA5);
-	imx_iomux_mode(MX31_PIN_USBOTG_DATA6__USBOTG_DATA6);
-	imx_iomux_mode(MX31_PIN_USBOTG_DATA7__USBOTG_DATA7);
-	imx_iomux_mode(MX31_PIN_USBOTG_CLK__USBOTG_CLK);
-	imx_iomux_mode(MX31_PIN_USBOTG_DIR__USBOTG_DIR);
-	imx_iomux_mode(MX31_PIN_USBOTG_NXT__USBOTG_NXT);
-	imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP);
-
-	mdelay(50);
-	ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1);
-
-	/* Host 2 */
-	tmp = readl(MX31_IOMUXC_GPR);
-	tmp |= 1 << 11;	/* IOMUX GPR: enable USBH2 signals */
-	writel(tmp, MX31_IOMUXC_GPR);
-
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC));
-	imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC));
-
-#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-	imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
-	imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
-	imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
-	imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
-	imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
-	imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
-	imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);	/* USBH2_DATA2 */
-	imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);	/* USBH2_DATA3 */
-	imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);	/* USBH2_DATA4 */
-	imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
-	imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
-	imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */
-
-	tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
-	tmp &= ~((3 << 21) | 1);
-	tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
-	writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
-
-	tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584);
-	tmp &= ~(3 << 30);
-	tmp |= 2 << 30;
-	writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584);
-
-	mdelay(50);
-	ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1);
-
-	/* Set to Host mode */
-	tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8);
-	writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8);
-
-}
-#endif
-
-static int pcm037_mmu_init(void)
-{
-	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-
-	return 0;
-}
-postmmu_initcall(pcm037_mmu_init);
-
-static struct smc911x_plat smsc9217_pdata = {
-	.flags = SMC911X_FORCE_INTERNAL_PHY,
-};
-
-static int pcm037_devices_init(void)
-{
-	/* CS0: Nor Flash */
-	imx31_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
-	/* CS1: Network Controller */
-	imx31_setup_weimcs(1, 0x0000df06, 0x444a4541, 0x44443302);
-	/* CS4: SRAM */
-	imx31_setup_weimcs(4, 0x0000d843, 0x22252521, 0x22220a00);
-	/* CS5: SJA1000 */
-	imx31_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302);
-
-	/*
-	 * Up to 32MiB NOR type flash, connected to
-	 * CS line 0, data width is 16 bit
-	 */
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
-
-	imx31_add_mmc0(NULL);
-
-	/*
-	 * Create partitions that should be
-	 * not touched by any regular user
-	 */
-	devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");	/* ourself */
-	devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");	/* environment */
-
-	protect_file("/dev/env0", 1);
-
-	/*
-	 * up to 2MiB static RAM type memory, connected
-	 * to CS4, data width is 16 bit
-	 */
-	add_mem_device("sram0", MX31_CS4_BASE_ADDR, MX31_CS4_SIZE, /* area size */
-				   IORESOURCE_MEM_WRITEABLE);
-	imx31_add_nand(&nand_info);
-
-	/*
-	 * SMSC 9217 network controller
-	 * connected to CS line 1 and interrupt line
-	 * GPIO3, data width is 16 bit
-	 */
-	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL,	MX31_CS1_BASE_ADDR,
-			MX31_CS1_SIZE, IORESOURCE_MEM, &smsc9217_pdata);
-
-#ifdef CONFIG_USB
-	pcm037_usb_init();
-	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_OTG_BASE_ADDR, NULL);
-	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_HS2_BASE_ADDR, NULL);
-#endif
-	armlinux_set_architecture(MACH_TYPE_PCM037);
-
-	return 0;
-}
-
-device_initcall(pcm037_devices_init);
-
-static unsigned int pcm037_iomux[] = {
-	/* UART1 */
-	MX31_PIN_RXD1__RXD1,
-	MX31_PIN_TXD1__TXD1,
-	MX31_PIN_CTS1__CTS1,
-	MX31_PIN_RTS1__RTS1,
-	/* I2C */
-	MX31_PIN_CSPI2_MOSI__SCL,
-	MX31_PIN_CSPI2_MISO__SDA,
-	MX31_PIN_CSPI2_SS2__I2C3_SDA,
-	MX31_PIN_CSPI2_SCLK__I2C3_SCL,
-	/* SDHC1 */
-	MX31_PIN_SD1_DATA3__SD1_DATA3,
-	MX31_PIN_SD1_DATA2__SD1_DATA2,
-	MX31_PIN_SD1_DATA1__SD1_DATA1,
-	MX31_PIN_SD1_DATA0__SD1_DATA0,
-	MX31_PIN_SD1_CLK__SD1_CLK,
-	MX31_PIN_SD1_CMD__SD1_CMD,
-	IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
-	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
-	/* SPI1 */
-	MX31_PIN_CSPI1_MOSI__MOSI,
-	MX31_PIN_CSPI1_MISO__MISO,
-	MX31_PIN_CSPI1_SCLK__SCLK,
-	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
-	MX31_PIN_CSPI1_SS0__SS0,
-	MX31_PIN_CSPI1_SS1__SS1,
-	MX31_PIN_CSPI1_SS2__SS2,
-	/* UART2 */
-	MX31_PIN_TXD2__TXD2,
-	MX31_PIN_RXD2__RXD2,
-	MX31_PIN_CTS2__CTS2,
-	MX31_PIN_RTS2__RTS2,
-	/* UART3 */
-	MX31_PIN_CSPI3_MOSI__RXD3,
-	MX31_PIN_CSPI3_MISO__TXD3,
-	MX31_PIN_CSPI3_SCLK__RTS3,
-	MX31_PIN_CSPI3_SPI_RDY__CTS3,
-};
-
-static int imx31_console_init(void)
-{
-	imx_iomux_setup_multiple_pins(pcm037_iomux, ARRAY_SIZE(pcm037_iomux));
-
-	barebox_set_model("Phytec phyCORE-i.MX31");
-	barebox_set_hostname("phycore-imx31");
-
-	imx31_add_uart0();
-	return 0;
-}
-
-console_initcall(imx31_console_init);
diff --git a/arch/arm/boards/phytec-phycore-imx35/Makefile b/arch/arm/boards/phytec-phycore-imx35/Makefile
deleted file mode 100644
index 5029714421..0000000000
--- a/arch/arm/boards/phytec-phycore-imx35/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de>
-
-lwl-y += lowlevel.o
-obj-y += pcm043.o
diff --git a/arch/arm/boards/phytec-phycore-imx35/env/boot/nand-ubi b/arch/arm/boards/phytec-phycore-imx35/env/boot/nand-ubi
deleted file mode 100644
index d555a538d1..0000000000
--- a/arch/arm/boards/phytec-phycore-imx35/env/boot/nand-ubi
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/sh
-
-global.bootm.image="/dev/nand0.kernel.bb"
-#global.bootm.oftree="/env/oftree"
-global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs"
diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand
deleted file mode 100644
index c7185db7f7..0000000000
--- a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-mtdparts="512k(nand0.barebox),256k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
-kernelname="mxc_nand"
-
-mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor
deleted file mode 100644
index 09c3ba9842..0000000000
--- a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-mtdparts="512k(nor0.barebox),128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
-kernelname="physmap-flash.0"
-
-mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg b/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg
deleted file mode 100644
index d3049369d9..0000000000
--- a/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg
+++ /dev/null
@@ -1,37 +0,0 @@
-soc imx35
-ivtofs 0x400
-loadaddr 0x80000000
-wm 32 0x53f80004 0x00821000
-wm 32 0x53f80004 0x00821000
-
-wm 32 0x43fac794 0x00000800
-wm 32 0x43fac798 0x00000800
-wm 32 0x43fac79c 0x00000800
-wm 32 0x43fac7a0 0x00000800
-wm 32 0x43fac7a4 0x00000800
-
-wm 32 0xb8001010 0x00000304
-wm 32 0xb8001004 0x0025541f
-wm 32 0xb8001000 0x92220000
-wm 32 0x80000400 0x12345678
-
-wm 32 0xb8001000 0xb8001000
-wm 8  0x84000000 0xda
-wm 8  0x86000000 0xda
-wm 8  0x82000400 0xda
-wm 8  0x80000333 0xda
-
-wm 32 0xb8001000 0x92220000
-wm 32 0x80000400 0x12345678
-
-wm 32 0xb8001000 0xa2220000
-wm 32 0x80000000 0x12344321
-wm 32 0x80000000 0x12344321
-wm 32 0xb8001000 0xb2220000
-wm 8  0x80000233 0xda
-wm 8  0x82000780 0xda
-wm 8  0x82000400 0xda
-wm 32 0xb8001000 0x82220080
-wm 32 0xb8001000 0x82228080
-wm 32 0xb8001008 0x00002000
-
diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c
deleted file mode 100644
index 73097eea10..0000000000
--- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c
+++ /dev/null
@@ -1,179 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-#include <common.h>
-#include <init.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/cache-l2x0.h>
-#include <io.h>
-#include <mach/imx-nand.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/sections.h>
-#include <asm-generic/memory_layout.h>
-#include <asm/system.h>
-
-#define IMX35_CHIP_REVISION_2_1		0x11
-
-#define CCM_PDR0_399	0x00011000
-#define CCM_PDR0_532	0x00001000
-
-void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	uint32_t r, s;
-	unsigned long ccm_base = MX35_CCM_BASE_ADDR;
-	unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR;
-	unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR;
-
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE);
-
-	r = get_cr();
-	r |= CR_Z; /* Flow prediction (Z) */
-	r |= CR_U; /* unaligned accesses  */
-	r |= CR_FI; /* Low Int Latency     */
-
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s));
-	s |= 0x7;
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s));
-
-	set_cr(r);
-
-	r = 0;
-	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
-
-	/*
-	 * Branch predicition is now enabled.  Flush the BTAC to ensure a valid
-	 * starting point.  Don't flush BTAC while it is disabled to avoid
-	 * ARM1136 erratum 408023.
-	 */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r));
-
-	/* invalidate I cache and D cache */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r));
-
-	/* invalidate TLBs */
-	__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r));
-
-	/* Drain the write buffer */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r));
-
-	/* Also setup the Peripheral Port Remap register inside the core */
-	r = 0x40000015; /* start from AIPS 2GB region */
-	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
-
-	/*
-	 * End of ARM1136 init
-	 */
-
-	writel(0x003F4208, ccm_base + MX35_CCM_CCMR);
-
-	/* Set MPLL , arm clock and ahb clock*/
-	writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL);
-
-	writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL);
-
-	/* Check silicon revision and use 532MHz if >=2.1 */
-	r = readl(MX35_IIM_BASE_ADDR + 0x24);
-	if (r >= IMX35_CHIP_REVISION_2_1)
-		writel(CCM_PDR0_532, ccm_base + MX35_CCM_PDR0);
-	else
-		writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0);
-
-	r = readl(ccm_base + MX35_CCM_CGR0);
-	r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR0);
-
-	r = readl(ccm_base + MX35_CCM_CGR1);
-	r |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR1);
-
-	r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
-	r |= 0x1000;
-	writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
-
-	/* Skip SDRAM initialization if we run from RAM */
-	r = get_pc();
-	if (r > 0x80000000 && r < 0x90000000)
-		goto out;
-
-	/* Set DDR Type to SDRAM, drive strength workaround	*
-	 * 0x00000000	MDDR					*
-	 * 0x00000800	3,3V SDRAM				*/
-
-	r = 0x00000800;
-	writel(r, iomuxc_base + 0x794);
-	writel(r, iomuxc_base + 0x798);
-	writel(r, iomuxc_base + 0x79c);
-	writel(r, iomuxc_base + 0x7a0);
-	writel(r, iomuxc_base + 0x7a4);
-
-	/* MDDR init, enable mDDR*/
-	writel(0x00000304, esdctl_base + IMX_ESDMISC); /* was 0x00000004 */
-
-	/* set timing paramters */
-	writel(0x0025541F, esdctl_base + IMX_ESDCFG0);
-	/* select Precharge-All mode */
-	writel(0x92220000, esdctl_base + IMX_ESDCTL0);
-	/* Precharge-All */
-	writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
-
-	/* select Load-Mode-Register mode */
-	writel(0xB8001000, esdctl_base + IMX_ESDCTL0);
-	/* Load reg EMR2 */
-	writeb(0xda, 0x84000000);
-	/* Load reg EMR3 */
-	writeb(0xda, 0x86000000);
-	/* Load reg EMR1 -- enable DLL */
-	writeb(0xda, 0x82000400);
-	/* Load reg MR -- reset DLL */
-	writeb(0xda, 0x80000333);
-
-	/* select Precharge-All mode */
-	writel(0x92220000, esdctl_base + IMX_ESDCTL0);
-	/* Precharge-All */
-	writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
-
-	/* select Manual-Refresh mode */
-	writel(0xA2220000, esdctl_base + IMX_ESDCTL0);
-	/* Manual-Refresh 2 times */
-	writel(0x87654321, MX35_CSD0_BASE_ADDR);
-	writel(0x87654321, MX35_CSD0_BASE_ADDR);
-
-	/* select Load-Mode-Register mode */
-	writel(0xB2220000, esdctl_base + IMX_ESDCTL0);
-	/* Load reg MR -- CL3, BL8, end DLL reset */
-	writeb(0xda, 0x80000233);
-	/* Load reg EMR1 -- OCD default */
-	writeb(0xda, 0x82000780);
-	/* Load reg EMR1 -- OCD exit */
-	writeb(0xda, 0x82000400);
-
-	/* select normal-operation mode
-	 * DSIZ32-bit, BL8, COL10-bit, ROW13-bit
-	 * disable PWT & PRCT
-	 * disable Auto-Refresh */
-	writel(0x82220080, esdctl_base + IMX_ESDCTL0);
-
-	/* enable Auto-Refresh */
-	writel(0x82228080, esdctl_base + IMX_ESDCTL0);
-	/* enable Auto-Refresh */
-	writel(0x00002000, esdctl_base + IMX_ESDCTL1);
-
-	if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
-		/* Speed up NAND controller by adjusting the NFC divider */
-		r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-		r &= ~(0xf << 28);
-		r |= 0x1 << 28;
-		writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-
-		imx35_barebox_boot_nand_external();
-	}
-
-out:
-	imx35_barebox_entry(NULL);
-}
diff --git a/arch/arm/boards/phytec-phycore-imx35/pcm043.c b/arch/arm/boards/phytec-phycore-imx35/pcm043.c
deleted file mode 100644
index 360a607bd5..0000000000
--- a/arch/arm/boards/phytec-phycore-imx35/pcm043.c
+++ /dev/null
@@ -1,314 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-// SPDX-FileCopyrightText: 2009 Juergen Beisert <kernel@pengutronix.de>, Pengutronix
-
-/* Board support for Phytec's, i.MX35 based CPU card, called: PCM043 */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <driver.h>
-#include <environment.h>
-#include <fs.h>
-#include <gpio.h>
-#include <linux/sizes.h>
-#include <mach/imx35-regs.h>
-#include <asm/armlinux.h>
-#include <io.h>
-#include <partition.h>
-#include <nand.h>
-#include <generated/mach-types.h>
-#include <mach/imx-nand.h>
-#include <fb.h>
-#include <led.h>
-#include <bootsource.h>
-#include <asm/mmu.h>
-#include <mach/weim.h>
-#include <mach/imx-ipu-fb.h>
-#include <mach/imx-pll.h>
-#include <mach/iomux-mx35.h>
-#include <mach/devices-imx35.h>
-#include <mach/generic.h>
-#include <mach/bbu.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type = PHY_INTERFACE_MODE_MII,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.width	= 1,
-	.hw_ecc	= 1,
-	.flash_bbt = 1,
-};
-
-static struct fb_videomode pcm043_fb_mode[] = {
-	{
-		/* 240x320 @ 60 Hz */
-		.name		= "TX090",
-		.refresh	= 60,
-		.xres		= 240,
-		.yres		= 320,
-		.pixclock	= 38255,
-		.left_margin	= 144,
-		.right_margin	= 0,
-		.upper_margin	= 7,
-		.lower_margin	= 40,
-		.hsync_len	= 96,
-		.vsync_len	= 1,
-		.sync		= FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	}, {
-		/* 240x320 @ 60 Hz */
-		.name		= "Sharp-LQ035Q7",
-		.refresh	= 60,
-		.xres		= 240,
-		.yres		= 320,
-		.pixclock	= 185925,
-		.left_margin	= 9,
-		.right_margin	= 16,
-		.upper_margin	= 7,
-		.lower_margin	= 9,
-		.hsync_len	= 1,
-		.vsync_len	= 1,
-		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | \
-				 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	}
-};
-
-static struct imx_ipu_fb_platform_data ipu_fb_data = {
-	.mode			= pcm043_fb_mode,
-	.num_modes		= ARRAY_SIZE(pcm043_fb_mode),
-	.framebuffer_ovl	= (void *) (MX35_CSD0_BASE_ADDR + SZ_128M - SZ_1M),
-	.bpp			= 16,
-};
-
-static int pcm043_mmu_init(void)
-{
-	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-
-	return 0;
-}
-postmmu_initcall(pcm043_mmu_init);
-
-struct gpio_led led0 = {
-	.gpio = 1 * 32 + 6,
-};
-
-static int pcm043_devices_init(void)
-{
-	uint32_t reg;
-	char *envstr;
-	unsigned long bbu_nand_flags = 0;
-
-	/* CS0: Nor Flash */
-	imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900);
-
-	led_gpio_register(&led0);
-
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
-	/* some fuses provide us vital information about connected hardware */
-	if (reg & 0x20000000)
-		nand_info.width = 2;    /* 16 bit */
-	else
-		nand_info.width = 1;    /* 8 bit */
-
-	imx35_add_fec(&fec_info);
-	/*
-	 * This platform supports NOR and NAND
-	 */
-	imx35_add_nand(&nand_info);
-	/*
-	 * Up to 32MiB NOR type flash, connected to
-	 * CS line 0, data width is 16 bit
-	 */
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
-
-	switch (bootsource_get()) {
-	case BOOTSOURCE_NAND:
-		devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
-		dev_add_bb_dev("self_raw", "self0");
-		devfs_add_partition("nand0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw");
-		dev_add_bb_dev("env_raw", "env0");
-		envstr = "NAND";
-		bbu_nand_flags = BBU_HANDLER_FLAG_DEFAULT;
-		break;
-	case BOOTSOURCE_NOR:
-	default:
-		devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
-		devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0");  /* environment */
-		protect_file("/dev/env0", 1);
-		envstr = "NOR";
-		break;
-	}
-
-	pr_info("using environment from %s flash\n", envstr);
-
-	imx35_add_fb(&ipu_fb_data);
-
-	armlinux_set_architecture(MACH_TYPE_PCM043);
-
-	imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox",
-			bbu_nand_flags);
-
-	return 0;
-}
-
-device_initcall(pcm043_devices_init);
-
-static iomux_v3_cfg_t pcm043_pads[] = {
-	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
-	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
-	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
-	MX35_PAD_FEC_COL__FEC_COL,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX35_PAD_FEC_MDC__FEC_MDC,
-	MX35_PAD_FEC_MDIO__FEC_MDIO,
-	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
-	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
-	MX35_PAD_FEC_CRS__FEC_CRS,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
-	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
-	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
-	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
-	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
-	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
-	MX35_PAD_RXD1__UART1_RXD_MUX,
-	MX35_PAD_TXD1__UART1_TXD_MUX,
-	MX35_PAD_RTS1__UART1_RTS,
-	MX35_PAD_CTS1__UART1_CTS,
-	MX35_PAD_I2C1_CLK__I2C1_SCL,
-	MX35_PAD_I2C1_DAT__I2C1_SDA,
-	MX35_PAD_ATA_CS0__GPIO2_6, /* LED */
-};
-
-static int imx35_console_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
-
-	barebox_set_model("Phytec phyCORE-i.MX35");
-	barebox_set_hostname("phycore-imx35");
-
-	imx35_add_uart0();
-
-	return 0;
-}
-
-console_initcall(imx35_console_init);
-
-static int pcm043_core_setup(void)
-{
-	u32 tmp;
-
-	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
-
-	/*
-	 * Clear the on and off peripheral modules Supervisor Protect bit
-	 * for SDMA to access them. Did not change the AIPS control registers
-	 * (offset 0x20) access type
-	 */
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
-	tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50);
-	tmp &= 0x00FFFFFF;
-	writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50);
-
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
-	tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50);
-	tmp &= 0x00FFFFFF;
-	writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50);
-
-	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-
-	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0);   /* for S0 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
-
-	/* SGPCR - always park on last master */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
-
-	/* MGPCR - restore default values */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
-
-	/*
-	 * M3IF Control Register (M3IFCTL)
-	 * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[1] = MAX1 not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[2] = L2CC1 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[3] = USB  not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[4] = SDMA not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[5] = GPU not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
-	 * MRRP[7] = IPU2 not on priority list (0 << 0)		= 0x00000000
-	 *                                                       ------------
-	 *                                                        0x00000040
-	 */
-	writel(0x40, MX35_M3IF_BASE_ADDR);
-
-	return 0;
-}
-
-core_initcall(pcm043_core_setup);
-
-static int do_cpufreq(int argc, char *argv[])
-{
-	unsigned long freq;
-
-	if (argc != 2)
-		return COMMAND_ERROR_USAGE;
-
-	freq = simple_strtoul(argv[1], NULL, 0);
-
-	switch (freq) {
-	case 399:
-		writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
-		break;
-	case 532:
-		writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
-		break;
-	default:
-		return COMMAND_ERROR_USAGE;
-	}
-
-	printf("Switched CPU frequency to %luMHz\n", freq);
-
-	return 0;
-}
-
-BAREBOX_CMD_START(cpufreq)
-	.cmd            = do_cpufreq,
-	BAREBOX_CMD_DESC("adjust CPU frequency")
-	BAREBOX_CMD_OPTS("399|532")
-	BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP)
-BAREBOX_CMD_END
-
diff --git a/arch/arm/boards/phytec-phycore-imx7/Makefile b/arch/arm/boards/phytec-phycore-imx7/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/phytec-phycore-imx7/Makefile
+++ b/arch/arm/boards/phytec-phycore-imx7/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/phytec-phycore-imx7/board.c b/arch/arm/boards/phytec-phycore-imx7/board.c
index f173ee233f..4d8b938f17 100644
--- a/arch/arm/boards/phytec-phycore-imx7/board.c
+++ b/arch/arm/boards/phytec-phycore-imx7/board.c
@@ -4,15 +4,14 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <mach/generic.h>
+#include <asm/mach-types.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
 #include <asm/psci.h>
 #include <io.h>
-#include <mach/imx7-regs.h>
+#include <mach/imx/imx7-regs.h>
 #include <serial/imx-uart.h>
 #include <asm/secure.h>
 
diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
index a18f3dbed1..03cdbe8bc8 100644
--- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
+++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
@@ -13,7 +13,7 @@ soc imx7
 loadaddr 0x80000000
 ivtofs 0x400
 
-#include <mach/imx7-ddr-regs.h>
+#include <mach/imx/imx7-ddr-regs.h>
 
 wm 32 0x30340004 0x4F400005
 /* Clear then set bit30 to ensure exit from DDR retention */
diff --git a/arch/arm/boards/phytec-phycore-imx7/lowlevel.c b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c
index 3d2038e4a8..1f3c08ac62 100644
--- a/arch/arm/boards/phytec-phycore-imx7/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c
@@ -1,11 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define DEBUG
 #include <io.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
 
 extern char __dtb_imx7d_phyboard_zeta_start[];
diff --git a/arch/arm/boards/phytec-phycore-omap4460/Makefile b/arch/arm/boards/phytec-phycore-omap4460/Makefile
index 5e78e11ec1..c5d3950bc3 100644
--- a/arch/arm/boards/phytec-phycore-omap4460/Makefile
+++ b/arch/arm/boards/phytec-phycore-omap4460/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o mux.o
 bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-phytec-phycore-omap4460
diff --git a/arch/arm/boards/phytec-phycore-omap4460/board.c b/arch/arm/boards/phytec-phycore-omap4460/board.c
index 9e8b9e56a7..2a176f156e 100644
--- a/arch/arm/boards/phytec-phycore-omap4460/board.c
+++ b/arch/arm/boards/phytec-phycore-omap4460/board.c
@@ -9,22 +9,21 @@
 #include <io.h>
 #include <envfs.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-devices.h>
-#include <mach/omap4-clock.h>
-#include <mach/omap-fb.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/control.h>
+#include <asm/mach-types.h>
+#include <mach/omap/devices.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-devices.h>
+#include <mach/omap/omap4-clock.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/control.h>
 #include <linux/err.h>
 #include <linux/sizes.h>
-#include <partition.h>
 #include <nand.h>
 #include <asm/mmu.h>
-#include <mach/gpmc.h>
-#include <mach/gpmc_nand.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/gpmc_nand.h>
 #include <i2c/i2c.h>
 
 static int pcm049_console_init(void)
@@ -292,8 +291,7 @@ static int pcm049_devices_init(void)
 
 	armlinux_set_architecture(MACH_TYPE_PCM049);
 
-	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_OMAP))
-		omap_add_display(&pcm049_fb_data);
+	omap_add_display(&pcm049_fb_data);
 
 	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
 		defaultenv_append_directory(defaultenv_phytec_phycore_omap4460);
diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
index 2a65e40e6b..17194c6562 100644
--- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
@@ -5,12 +5,12 @@
 #include <init.h>
 #include <io.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
-#include <mach/omap4-mux.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-generic.h>
-#include <mach/omap4-clock.h>
-#include <mach/syslib.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/omap4-mux.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-generic.h>
+#include <mach/omap/omap4-clock.h>
+#include <mach/omap/syslib.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
 
diff --git a/arch/arm/boards/phytec-phycore-omap4460/mux.c b/arch/arm/boards/phytec-phycore-omap4460/mux.c
index ca4ccf39f0..287c2a4826 100644
--- a/arch/arm/boards/phytec-phycore-omap4460/mux.c
+++ b/arch/arm/boards/phytec-phycore-omap4460/mux.c
@@ -1,9 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-mux.h>
-#include <mach/omap4-clock.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-mux.h>
+#include <mach/omap/omap4-clock.h>
 
 #include "mux.h"
 
diff --git a/arch/arm/boards/phytec-phycore-omap4460/mux.h b/arch/arm/boards/phytec-phycore-omap4460/mux.h
index 64d4478b2c..c84ecd32c8 100644
--- a/arch/arm/boards/phytec-phycore-omap4460/mux.h
+++ b/arch/arm/boards/phytec-phycore-omap4460/mux.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __BOARD_MUX_H
 #define __BOARD_MUX_H
 
diff --git a/arch/arm/boards/phytec-phycore-pxa270/Makefile b/arch/arm/boards/phytec-phycore-pxa270/Makefile
index 040cf93944..e00d1cfd7f 100644
--- a/arch/arm/boards/phytec-phycore-pxa270/Makefile
+++ b/arch/arm/boards/phytec-phycore-pxa270/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel_init.o
diff --git a/arch/arm/boards/phytec-phycore-pxa270/board.c b/arch/arm/boards/phytec-phycore-pxa270/board.c
index 9740a3a7af..0283659a4e 100644
--- a/arch/arm/boards/phytec-phycore-pxa270/board.c
+++ b/arch/arm/boards/phytec-phycore-pxa270/board.c
@@ -7,18 +7,17 @@
 #include <environment.h>
 #include <fs.h>
 #include <init.h>
-#include <partition.h>
 #include <linux/sizes.h>
 
 #include <gpio.h>
-#include <mach/mfp-pxa27x.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxafb.h>
-#include <mach/devices.h>
+#include <mach/pxa/mfp-pxa27x.h>
+#include <mach/pxa/pxa-regs.h>
+#include <mach/pxa/pxafb.h>
+#include <mach/pxa/devices.h>
 
 #include <asm/armlinux.h>
 #include <asm/io.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <asm/mmu.h>
 
 #define PCM990_CTRL_PHYS	(void *)PXA_CS1_PHYS
diff --git a/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S b/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S
index 9c6366cc2a..f8f1a037e0 100644
--- a/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S
+++ b/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S
@@ -13,10 +13,11 @@
 
 #include <config.h>
 #include <linux/sizes.h>
-#include <mach/pxa-regs.h>
-#include <mach/regs-ost.h>
-#include <mach/regs-intc.h>
+#include <mach/pxa/pxa-regs.h>
+#include <mach/pxa/regs-ost.h>
+#include <mach/pxa/regs-intc.h>
 #include <asm/barebox-arm-head.h>
+#include "config.h"
 
 #define GPSR0		0x40E00018	/* GPIO Pin Output Set Register GPIO <31:00> */
 #define GPSR1		0x40E0001C	/* GPIO Pin Output Set Register GPIO <63:32> */
diff --git a/arch/arm/boards/phytec-phycore-stm32mp1/Makefile b/arch/arm/boards/phytec-phycore-stm32mp1/Makefile
new file mode 100644
index 0000000000..1d052d28c9
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-stm32mp1/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+lwl-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/phytec-phycore-stm32mp1/board.c b/arch/arm/boards/phytec-phycore-stm32mp1/board.c
new file mode 100644
index 0000000000..6690e36ca7
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-stm32mp1/board.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include <common.h>
+#include <driver.h>
+#include <bootsource.h>
+#include <mach/stm32mp/bbu.h>
+
+static int phycore_stm32mp1_probe(struct device *dev)
+{
+	int sd_bbu_flags = 0, emmc_bbu_flags = 0;
+
+	if (bootsource_get_instance() == 0) {
+		of_device_enable_path("/chosen/environment-sd");
+		sd_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+	} else {
+		of_device_enable_path("/chosen/environment-emmc");
+		emmc_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", sd_bbu_flags);
+	stm32mp_bbu_mmc_fip_register("emmc", "/dev/mmc1", emmc_bbu_flags);
+
+	barebox_set_hostname("phyCORE-STM32MP1");
+
+	return 0;
+}
+
+static const struct of_device_id phycore_stm32mp1_of_match[] = {
+	{ .compatible = "phytec,phycore-stm32mp1-3" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, phycore_stm32mp1_of_match);
+
+static struct driver phycore_stm32mp1_board_driver = {
+	.name = "board-phycore-stm32mp1",
+	.probe = phycore_stm32mp1_probe,
+	.of_compatible = phycore_stm32mp1_of_match,
+};
+device_platform_driver(phycore_stm32mp1_board_driver);
diff --git a/arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c b/arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c
new file mode 100644
index 0000000000..8174e060af
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <common.h>
+#include <mach/stm32mp/entry.h>
+#include <debug_ll.h>
+
+extern char __dtb_z_stm32mp157c_phycore_stm32mp1_3_start[];
+
+ENTRY_FUNCTION(start_phycore_stm32mp1_3, r0, r1, r2)
+{
+	void *fdt;
+
+	stm32mp_cpu_lowlevel_init();
+
+	putc_ll('>');
+
+	fdt = __dtb_z_stm32mp157c_phycore_stm32mp1_3_start + get_runtime_offset();
+
+	stm32mp1_barebox_entry(fdt);
+}
diff --git a/arch/arm/boards/phytec-som-am335x/Kconfig b/arch/arm/boards/phytec-som-am335x/Kconfig
index 52fa723a21..054a1d219f 100644
--- a/arch/arm/boards/phytec-som-am335x/Kconfig
+++ b/arch/arm/boards/phytec-som-am335x/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 if MACH_PHYTEC_SOM_AM335X
 
diff --git a/arch/arm/boards/phytec-som-am335x/Makefile b/arch/arm/boards/phytec-som-am335x/Makefile
index 78397bd59f..82dd631c9f 100644
--- a/arch/arm/boards/phytec-som-am335x/Makefile
+++ b/arch/arm/boards/phytec-som-am335x/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
 bbenv-y += defaultenv-physom-am335x
diff --git a/arch/arm/boards/phytec-som-am335x/board.c b/arch/arm/boards/phytec-som-am335x/board.c
index 11acd06c53..f3caa5d50a 100644
--- a/arch/arm/boards/phytec-som-am335x/board.c
+++ b/arch/arm/boards/phytec-som-am335x/board.c
@@ -18,12 +18,12 @@
 #include <envfs.h>
 #include <state.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
-#include <mach/am33xx-generic.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/bbu.h>
+#include <mach/omap/am33xx-generic.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/bbu.h>
 
 static int physom_coredevice_init(void)
 {
diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c
index bffb3ad880..267f30b638 100644
--- a/arch/arm/boards/phytec-som-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c
@@ -7,16 +7,16 @@
 #include <init.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/am33xx-clock.h>
-#include <mach/generic.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/am33xx-mux.h>
-#include <mach/am33xx-generic.h>
-#include <mach/wdt.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/am33xx-clock.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/am33xx-mux.h>
+#include <mach/omap/am33xx-generic.h>
 #include <debug_ll.h>
+#include <mach/omap/debug_ll.h>
 
 #include "ram-timings.h"
 
@@ -136,15 +136,7 @@ static noinline void physom_board_init(void *fdt, int sdram, int module_family)
 	struct am335x_sdram_timings *timing = NULL;
 	u32 ramsize;
 
-	/*
-	 * WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-
-	writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
 
 	am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400);
 
@@ -172,7 +164,7 @@ static noinline void physom_board_init(void *fdt, int sdram, int module_family)
 
 	am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
 	am33xx_enable_uart0_pin_mux();
-	omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
+	omap_debug_ll_init();
 	putc_ll('>');
 
 	am335x_barebox_entry(fdt);
diff --git a/arch/arm/boards/phytec-som-imx6/Makefile b/arch/arm/boards/phytec-som-imx6/Makefile
index 73456aed8b..0780da79b9 100644
--- a/arch/arm/boards/phytec-som-imx6/Makefile
+++ b/arch/arm/boards/phytec-som-imx6/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-physom-imx6
diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c
index bac3e8a8a1..2db3fa1db8 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -14,16 +14,17 @@
 #include <gpio.h>
 #include <init.h>
 #include <of.h>
+#include <deep-probe.h>
 #include <i2c/i2c.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <platform_data/eth-fec.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
 #include <linux/micrel_phy.h>
 
 #include <globalvar.h>
 
-#include <mach/iomux-mx6.h>
-#include <mach/imx6.h>
+#include <mach/imx/iomux-mx6.h>
+#include <mach/imx/imx6.h>
 
 #define PHYFLEX_MODULE_REV_1	0x1
 #define PHYFLEX_MODULE_REV_2	0x2
@@ -106,10 +107,14 @@ static int phycore_da9062_setup_buck_mode(void)
 	unsigned char value;
 	int ret;
 
-	pmic_np = of_find_node_by_name(NULL, "pmic@58");
+	pmic_np = of_find_node_by_name_address(NULL, "pmic@58");
 	if (!pmic_np)
 		return -ENODEV;
 
+	ret = of_device_ensure_probed(pmic_np);
+	if (ret)
+		return ret;
+
 	adapter = of_find_i2c_adapter_by_node(pmic_np->parent);
 	if (!adapter)
 		return -ENODEV;
@@ -141,15 +146,29 @@ err_out:
 	return ret;
 }
 
-static int physom_imx6_devices_init(void)
+#define IS_PHYFLEX	BIT(0)
+#define IS_PHYCORE	BIT(1)
+#define IS_PHYCARD	BIT(2)
+#define IS_PHYCORE_UL	BIT(3)
+#define HAS_MMC3	BIT(4)
+#define HAS_MMC1	BIT(5)
+
+struct board_data {
+	unsigned flags;
+};
+
+static int physom_imx6_probe(struct device *dev)
 {
 	int ret;
 	char *environment_path, *default_environment_path;
 	char *envdev, *default_envdev;
+	const struct board_data *brd = device_get_match_data(dev);
+	unsigned flags = brd->flags;
 
-	if (of_machine_is_compatible("phytec,imx6q-pfla02")
-		|| of_machine_is_compatible("phytec,imx6dl-pfla02")
-		|| of_machine_is_compatible("phytec,imx6s-pfla02")) {
+	if (flags & IS_PHYFLEX) {
+		ret = of_devices_ensure_probed_by_property("gpio-controller");
+		if (ret)
+			return ret;
 
 		phyflex_err006282_workaround();
 
@@ -164,21 +183,14 @@ static int physom_imx6_devices_init(void)
 		imx6_bbu_internal_mmc_register_handler("mmc2",
 						"/dev/mmc2", 0);
 
-	} else if (of_machine_is_compatible("phytec,imx6q-pcaaxl3")) {
-
+	} else if (flags & IS_PHYCARD) {
 		barebox_set_hostname("phyCARD-i.MX6");
 		default_environment_path = "/chosen/environment-nand";
 		default_envdev = "NAND flash";
 
 		imx6_bbu_internal_mmc_register_handler("mmc2",
 						"/dev/mmc2", 0);
-
-	} else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand")
-		|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
-		|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
-		|| of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
-		|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
-
+	} else if (flags & IS_PHYCORE) {
 		if (phycore_da9062_setup_buck_mode())
 			pr_err("Setting PMIC BUCK mode failed\n");
 
@@ -189,8 +201,7 @@ static int physom_imx6_devices_init(void)
 		imx6_bbu_internal_mmc_register_handler("mmc0",
 						"/dev/mmc0", 0);
 
-	} else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")
-		|| of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
+	} else if (flags & IS_PHYCORE_UL) {
 		barebox_set_hostname("phyCORE-i.MX6UL");
 		default_environment_path = "/chosen/environment-nand";
 		default_envdev = "NAND flash";
@@ -201,8 +212,9 @@ static int physom_imx6_devices_init(void)
 		imx6_bbu_internal_mmc_register_handler("mmc0",
 						"/dev/mmc0", 0);
 
-	} else
-		return 0;
+	} else {
+		return -EINVAL;
+	}
 
 	switch (bootsource_get()) {
 	case BOOTSOURCE_MMC:
@@ -219,7 +231,7 @@ static int physom_imx6_devices_init(void)
 		envdev = "SPI NOR flash";
 		break;
 	default:
-		environment_path = basprintf(default_environment_path);
+		environment_path = strdup(default_environment_path);
 		envdev = default_envdev;
 		break;
 	}
@@ -234,14 +246,13 @@ static int physom_imx6_devices_init(void)
 
 	pr_notice("Using environment in %s\n", envdev);
 
-	if (of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
-		|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
+	if (flags & HAS_MMC3) {
 		imx6_bbu_internal_mmc_register_handler("mmc3",
 						"/dev/mmc3",
 						BBU_HANDLER_FLAG_DEFAULT);
 		imx6_bbu_internal_mmcboot_register_handler("mmc3-boot",
 						"mmc3", 0);
-	} else if (of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
+	} else if (flags & HAS_MMC1) {
 		imx6_bbu_internal_mmc_register_handler("mmc1",
 						"/dev/mmc1",
 						BBU_HANDLER_FLAG_DEFAULT);
@@ -254,23 +265,107 @@ static int physom_imx6_devices_init(void)
 	defaultenv_append_directory(defaultenv_physom_imx6);
 
 	/* Overwrite file /env/init/automount */
-	if (of_machine_is_compatible("phytec,imx6q-pfla02")
-		|| of_machine_is_compatible("phytec,imx6dl-pfla02")
-		|| of_machine_is_compatible("phytec,imx6s-pfla02")
-		|| of_machine_is_compatible("phytec,imx6q-pcaaxl3")) {
+	if (flags & IS_PHYCARD || flags & IS_PHYFLEX) {
 		defaultenv_append_directory(defaultenv_physom_imx6);
-	} else if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
-		|| of_machine_is_compatible("phytec,imx6q-pcm058-nand")
-		|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
-		|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
-		|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
+	} else if (flags & IS_PHYCORE) {
 		defaultenv_append_directory(defaultenv_physom_imx6);
 		defaultenv_append_directory(defaultenv_physom_imx6_phycore);
-	} else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")
-		|| of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
+	} else if (flags & IS_PHYCORE_UL) {
 		defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
 	}
 
 	return 0;
 }
-device_initcall(physom_imx6_devices_init);
+
+static struct board_data imx6q_pfla02 = {
+	.flags = IS_PHYFLEX,
+};
+
+static struct board_data imx6dl_pfla02 = {
+	.flags = IS_PHYFLEX,
+};
+
+static struct board_data imx6s_pfla02 = {
+	.flags = IS_PHYFLEX,
+};
+
+static struct board_data imx6q_pcaaxl3 = {
+	.flags = IS_PHYCARD,
+};
+
+static struct board_data imx6q_pcm058_nand = {
+	.flags = IS_PHYCORE,
+};
+
+static struct board_data imx6q_pcm058_emmc = {
+	.flags = IS_PHYCORE | HAS_MMC3,
+};
+
+static struct board_data imx6dl_pcm058_nand = {
+	.flags = IS_PHYCORE,
+};
+
+static struct board_data imx6qp_pcm058_nand = {
+	.flags = IS_PHYCORE,
+};
+
+static struct board_data imx6dl_pcm058_emmc = {
+	.flags = IS_PHYCORE | HAS_MMC3,
+};
+
+static struct board_data imx6ul_pcl063_nand = {
+	.flags = IS_PHYCORE_UL,
+};
+
+static struct board_data imx6ul_pcl063_emmc = {
+	.flags = IS_PHYCORE_UL | HAS_MMC1,
+};
+
+
+static const struct of_device_id physom_imx6_match[] = {
+	{
+		.compatible = "phytec,imx6q-pfla02",
+		.data = &imx6q_pfla02,
+	}, {
+		.compatible = "phytec,imx6dl-pfla02",
+		.data = &imx6dl_pfla02,
+	}, {
+		.compatible = "phytec,imx6s-pfla02",
+		.data = &imx6s_pfla02,
+	}, {
+		.compatible = "phytec,imx6q-pcaaxl3",
+		.data = &imx6q_pcaaxl3,
+	}, {
+		.compatible = "phytec,imx6q-pcm058-nand",
+		.data = &imx6q_pcm058_nand,
+	}, {
+		.compatible = "phytec,imx6q-pcm058-emmc",
+		.data = &imx6q_pcm058_emmc,
+	}, {
+		.compatible = "phytec,imx6dl-pcm058-nand",
+		.data = &imx6dl_pcm058_nand,
+	}, {
+		.compatible = "phytec,imx6qp-pcm058-nand",
+		.data = &imx6qp_pcm058_nand,
+	}, {
+		.compatible = "phytec,imx6dl-pcm058-emmc",
+		.data = &imx6dl_pcm058_emmc,
+	}, {
+		.compatible = "phytec,imx6ul-pcl063-nand",
+		.data = &imx6ul_pcl063_nand,
+	}, {
+		.compatible = "phytec,imx6ul-pcl063-emmc",
+		.data = &imx6ul_pcl063_emmc,
+	},
+	{ /* Sentinel */ },
+};
+
+static struct driver physom_imx6_driver = {
+	.name = "physom-imx6",
+	.probe = physom_imx6_probe,
+	.of_compatible = physom_imx6_match,
+};
+
+postcore_platform_driver(physom_imx6_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(physom_imx6_match);
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg
index bb4fbeb205..3b3e290fbe 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x54597955;	\
 
@@ -7,4 +9,4 @@
 	wm 32 0x021b0000 0x831a0000
 
 #include "flash-header-phytec-pcaaxl3.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg
index 990c34b3af..4c8c527043 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x3a3f7975;	\
 
@@ -7,4 +9,4 @@
 	wm 32 0x021b0000 0xc21a0000
 
 #include "flash-header-phytec-pcaaxl3.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg
index 7c56c24ed7..a2f932e12a 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x54597955;	\
 
@@ -7,4 +9,4 @@
 	wm 32 0x021b0000 0xc31a0000
 
 #include "flash-header-phytec-pcaaxl3.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h
index 1876a5aa9d..c6cd180176 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000028
 wm 32 MX6_IOM_DRAM_SDQS1 0x00000028
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.h
index c4122d245d..c7ee1aaeeb 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 #define SETUP_MDCFG0			\
 	wm 32 0x021B000C 0x676B52F3
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h
index 9a8f5f18e1..9847954693 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h
@@ -1,8 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 loadaddr 0x80000000
 soc imx6
 ivtofs 0x400
 
+wm 32 0x020c8140 0x00580012
+
 wm 32 0x020c4068 0xffffffff
 wm 32 0x020c406c 0xffffffff
 wm 32 0x020c4070 0xffffffff
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg
index f629a8e7b2..1a987c2c1f 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 #include "flash-header-phytec-pcl063-512mb.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-256mb.imxcfg
index e6871d8534..f519abf1a0 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-256mb.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-256mb.imxcfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 #define SETUP_MDCFG0			\
 	wm 32 0x021B000C 0x676B52F3
@@ -7,4 +8,4 @@
 	wm 32 0x021B0000 0x83180000
 
 #include "flash-header-phytec-pcl063.h"
-#include <mach/habv4-imx6ull-gencsf.h>
+#include <mach/imx/habv4-imx6ull-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg
index d2d7183843..6935bd2ef3 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 #include "flash-header-phytec-pcl063-512mb.h"
-#include <mach/habv4-imx6ull-gencsf.h>
+#include <mach/imx/habv4-imx6ull-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg
index 0042909c95..131e08cf4b 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x555A7955
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x831A0000
 
 #include "flash-header-phytec-pcm058.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg
index 8a09036992..be638ab1c1 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x8c929b85
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x841A0000
 
 #include "flash-header-phytec-pcm058.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h
index d32ee836a8..eaa2a3da6e 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg
index c949f98503..83f8480bfe 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x8c929b85
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x84190000
 
 #include "flash-header-phytec-pcm058dl.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg
index 3ac7e4e7ff..708e5bb21d 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x555A7955
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x831A0000
 
 #include "flash-header-phytec-pcm058dl.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg
index bb8cdc9e4d..be3cd5a20d 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x3c409b85
 
@@ -6,5 +8,5 @@
 	wm 32 0x021b0000 0x82190000
 
 #include "flash-header-phytec-pcm058dl.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
 
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg
index 5b92e5809c..4fcf36990d 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x3c409b85
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x83190000
 
 #include "flash-header-phytec-pcm058dl.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h
index e820cbf86b..2d90faad4c 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg
index 3ed5b346ae..e15d220428 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x555A7955
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x831A0000
 
 #include "flash-header-phytec-pcm058qp.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h
index f3174f9bb7..aae646e75c 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg
index 02f3fa7b33..48b1321b51 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0                    \
 	wm 32 0x021b000c 0x565c9b85
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x831a0000
 
 #include "flash-header-phytec-pfla02.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg
index dd142a20a9..8bd6a83786 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x3c409b85
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0xc21a0000
 
 #include "flash-header-phytec-pfla02.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg
index 3f9d11dc49..fe2fa2c637 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0                    \
 	wm 32 0x021b000c 0x565c9b85
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0xC31A0000
 
 #include "flash-header-phytec-pfla02.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg
index fdb1d15538..6f8645c4e6 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0                    \
 	wm 32 0x021b000c 0x8c929b85
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0xC41A0000
 
 #include "flash-header-phytec-pfla02.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg
index f4f150ee68..edafe2d47c 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x555a7975
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x821a0000
 
 #include "flash-header-phytec-pfla02.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h
index 4a9b179f59..26a9341dda 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
index b2a0521bbc..553ba8d40a 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0                    \
 	wm 32 0x021b000c 0x41447525
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x831a0000
 
 #include "flash-header-phytec-pfla02dl.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
index e03e25eae2..5c37061853 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x2d307525
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0xc21a0000
 
 #include "flash-header-phytec-pfla02dl.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
index be4084c161..537a93eda9 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
index 58c1576219..331692af49 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0                    \
         wm 32 0x021b000c 0x2D307525
 
@@ -6,4 +8,4 @@
         wm 32 0x021b0000 0x82180000
 
 #include "flash-header-phytec-pfla02dl.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
index 9975e2197b..bd830865ec 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0                    \
         wm 32 0x021b000c 0x2D307525
 
@@ -6,4 +8,4 @@
         wm 32 0x021b0000 0x82190000
 
 #include "flash-header-phytec-pfla02dl.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
index edc396bc5d..7e57e7cd9e 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 #define SETUP_MDCFG0			\
 	wm 32 0x021b000c 0x41447525
 
@@ -6,4 +8,4 @@
 	wm 32 0x021b0000 0x83190000
 
 #include "flash-header-phytec-pfla02dl.h"
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 62a1c8de73..da5665a716 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -6,6 +6,7 @@
  * Author: Stefan Christ <s.christ@phytec.de>
  */
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <linux/sizes.h>
 #include <io.h>
@@ -15,7 +16,7 @@
 #include <asm/sections.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <mach/imx6.h>
+#include <mach/imx/imx6.h>
 
 static inline void setup_uart(void)
 {
@@ -75,7 +76,6 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
 		extern char __dtb_##fdt_name##_start[];			\
 									\
 		IMD_USED(physom_mx6_memsize_##memory_size);		\
-		IMD_USED_OF(fdt_name);					\
 									\
 		start_imx6_phytec_common(memory_size, do_early_uart_config, \
 					 __dtb_##fdt_name##_start);	\
diff --git a/arch/arm/boards/phytec-som-imx8mm/Makefile b/arch/arm/boards/phytec-som-imx8mm/Makefile
new file mode 100644
index 0000000000..10abebc539
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o lpddr4-timing.o
+obj-y += board.o
diff --git a/arch/arm/boards/phytec-som-imx8mm/board.c b/arch/arm/boards/phytec-som-imx8mm/board.c
new file mode 100644
index 0000000000..52f821f5fa
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/board.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <mach/imx/bbu.h>
+
+static int phyboard_polis_rdk_probe(struct device *dev)
+{
+	int emmc_bbu_flag = 0;
+	int sd_bbu_flag = 0;
+
+	if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) {
+		of_device_enable_path("/chosen/environment-sd");
+		sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	} else {
+		of_device_enable_path("/chosen/environment-emmc");
+		emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
+
+	return 0;
+}
+
+static const struct of_device_id phyboard_polis_rdk_of_match[] = {
+	{ .compatible = "phytec,imx8mm-phyboard-polis-rdk" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(phyboard_polis_rdk_of_match);
+
+static struct driver phyboard_polis_rdkboard_driver = {
+	.name = "board-phyboard-polis-rdk",
+	.probe = phyboard_polis_rdk_probe,
+	.of_compatible = DRV_OF_COMPAT(phyboard_polis_rdk_of_match),
+};
+coredevice_platform_driver(phyboard_polis_rdkboard_driver);
diff --git a/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
new file mode 100644
index 0000000000..8aff991618
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mm
+
+loadaddr 0x007e1000
+max_load_size 0x3f000
+ivtofs 0x400
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx8mm/lowlevel.c b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
new file mode 100644
index 0000000000..26f0f4d3e1
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <asm/barebox-arm.h>
+#include <boards/phytec/phytec-som-imx8m-detection.h>
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/iomux-mx8mm.h>
+#include <mach/imx/xload.h>
+#include <mfd/bd71837.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <soc/imx8m/ddr.h>
+
+#include "lowlevel.h"
+
+extern char __dtb_z_imx8mm_phyboard_polis_rdk_start[];
+
+#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
+
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART3_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mm_setup_pad(IMX8MM_PAD_UART3_TXD_UART3_TX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+	putc_ll('>');
+}
+
+#define EEPROM_ADDR 0x51
+#define EEPROM_ADDR_FALLBACK 0x59
+
+static void phyboard_polis_rdk_ddr_init(enum phytec_imx8m_ddr_size size)
+{
+	int ret;
+
+	if (size == PHYTEC_IMX8M_DDR_AUTODETECT) {
+		struct pbl_i2c *i2c;
+
+		imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL);
+		imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA);
+		imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+		i2c = imx8m_i2c_early_init(IOMEM(MX8MM_I2C1_BASE_ADDR));
+
+		ret = phytec_eeprom_data_setup(i2c, NULL, EEPROM_ADDR,
+					       EEPROM_ADDR_FALLBACK, IMX_CPU_IMX8MM);
+		if (ret) {
+			pr_err("Could not detect correct RAM size. Fallback to default.\n");
+		} else {
+			phytec_print_som_info(NULL);
+			size = phytec_get_imx8m_ddr_size(NULL);
+		}
+	}
+
+	switch (size) {
+	case PHYTEC_IMX8M_DDR_1G:
+		phyboard_polis_rdk_dram_timing.ddrc_cfg[5].val = 0x2d0087;
+		phyboard_polis_rdk_dram_timing.ddrc_cfg[21].val = 0x8d;
+		phyboard_polis_rdk_dram_timing.ddrc_cfg[42].val = 0xf070707;
+		phyboard_polis_rdk_dram_timing.ddrc_cfg[58].val = 0x60012;
+		phyboard_polis_rdk_dram_timing.ddrc_cfg[73].val = 0x13;
+		phyboard_polis_rdk_dram_timing.ddrc_cfg[83].val = 0x30005;
+		phyboard_polis_rdk_dram_timing.ddrc_cfg[98].val = 0x5;
+		break;
+	default:
+	case PHYTEC_IMX8M_DDR_AUTODETECT:
+	case PHYTEC_IMX8M_DDR_2G:
+		break;
+	case PHYTEC_IMX8M_DDR_4G:
+		phyboard_polis_rdk_dram_timing.ddrc_cfg[2].val = 0xa3080020;
+		phyboard_polis_rdk_dram_timing.ddrc_cfg[37].val = 0x17;
+		phyboard_polis_rdk_dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x310;
+		phyboard_polis_rdk_dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x3;
+		phyboard_polis_rdk_dram_timing.fsp_msg[1].fsp_cfg[9].val = 0x310;
+		phyboard_polis_rdk_dram_timing.fsp_msg[1].fsp_cfg[21].val = 0x3;
+		phyboard_polis_rdk_dram_timing.fsp_msg[2].fsp_cfg[9].val = 0x310;
+		phyboard_polis_rdk_dram_timing.fsp_msg[2].fsp_cfg[21].val = 0x3;
+		phyboard_polis_rdk_dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+		phyboard_polis_rdk_dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+		break;
+	}
+
+	imx8mm_ddr_init(&phyboard_polis_rdk_dram_timing, DRAM_TYPE_LPDDR4);
+}
+
+static void start_phyboard_polis_rdk_common(enum phytec_imx8m_ddr_size size)
+{
+	imx8mm_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	setup_uart();
+
+	/*
+	 * If we are in EL3 we are running for the first time out of OCRAM,
+	 * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A
+	 * will then jump to DRAM in EL2
+	 */
+	if (current_el() == 3) {
+		imx8mm_early_clock_init();
+
+		phyboard_polis_rdk_ddr_init(size);
+
+		imx8mm_load_and_start_image_via_tfa();
+	}
+
+	/* Standard entry we hit once we initialized both DDR and ATF */
+	imx8mm_barebox_entry(__dtb_z_imx8mm_phyboard_polis_rdk_start);
+}
+
+ENTRY_FUNCTION(start_phyboard_polis_rdk_ddr_autodetect, r0, r1, r2)
+{
+	start_phyboard_polis_rdk_common(PHYTEC_IMX8M_DDR_AUTODETECT);
+}
+
+ENTRY_FUNCTION(start_phyboard_polis_rdk_ddr_1g, r0, r1, r2)
+{
+	start_phyboard_polis_rdk_common(PHYTEC_IMX8M_DDR_1G);
+}
+
+ENTRY_FUNCTION(start_phyboard_polis_rdk_ddr_2g, r0, r1, r2)
+{
+	start_phyboard_polis_rdk_common(PHYTEC_IMX8M_DDR_1G);
+}
+
+ENTRY_FUNCTION(start_phyboard_polis_rdk_ddr_4g, r0, r1, r2)
+{
+	start_phyboard_polis_rdk_common(PHYTEC_IMX8M_DDR_4G);
+}
diff --git a/arch/arm/boards/phytec-som-imx8mm/lowlevel.h b/arch/arm/boards/phytec-som-imx8mm/lowlevel.h
new file mode 100644
index 0000000000..9982a822b7
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/lowlevel.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef PHYBOARD_POLIS_RDK_LOWLEVEL_H_
+#define PHYBOARD_POLIS_RDK_LOWLEVEL_H_
+
+extern struct dram_timing_info phyboard_polis_rdk_dram_timing;
+
+#endif
diff --git a/arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c b/arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c
new file mode 100644
index 0000000000..7d01c181c0
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c
@@ -0,0 +1,1125 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 NXP
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+#define DDR_ONE_RANK
+#include <soc/imx8m/lpddr4_define.h>
+
+#include "lowlevel.h"
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x222 },
+	{ 0x3d400024, 0x3a980 },
+	{ 0x3d400064, 0x2d00d2 },
+	{ 0x3d4000d0, 0xc00305ba },
+	{ 0x3d4000d4, 0x940000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x191e0c20 },
+	{ 0x3d400104, 0x60630 },
+	{ 0x3d40010c, 0xb0b000 },
+	{ 0x3d400110, 0xe04080e },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x402 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xd8 },
+	{ 0x3d400144, 0x96004b },
+	{ 0x3d400180, 0x2ee0017 },
+	{ 0x3d400184, 0x2605b8e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0x699 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x20 },
+	{ 0x3d402024, 0x7d00 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0x6001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040105 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x302 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0x599 },
+	{ 0x3d403020, 0x20 },
+	{ 0x3d403024, 0x1f40 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x302 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0x599 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x1200c7, 0x21 },
+	{ 0x2200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x34b },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x70 },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x1c },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info phyboard_polis_rdk_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100,},
+};
diff --git a/arch/arm/boards/phytec-som-imx8mq/.gitignore b/arch/arm/boards/phytec-som-imx8mq/.gitignore
index ef13747c92..cafa52b207 100644
--- a/arch/arm/boards/phytec-som-imx8mq/.gitignore
+++ b/arch/arm/boards/phytec-som-imx8mq/.gitignore
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 *.ddr-phy-fw*
diff --git a/arch/arm/boards/phytec-som-imx8mq/Makefile b/arch/arm/boards/phytec-som-imx8mq/Makefile
index 2995f06f0f..17d769f330 100644
--- a/arch/arm/boards/phytec-som-imx8mq/Makefile
+++ b/arch/arm/boards/phytec-som-imx8mq/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o ddr_init.o ddrphy_train.o
diff --git a/arch/arm/boards/phytec-som-imx8mq/board.c b/arch/arm/boards/phytec-som-imx8mq/board.c
index 6d331281e6..45ed9cf5ad 100644
--- a/arch/arm/boards/phytec-som-imx8mq/board.c
+++ b/arch/arm/boards/phytec-som-imx8mq/board.c
@@ -9,8 +9,9 @@
 #include <common.h>
 #include <init.h>
 #include <linux/sizes.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <mfd/pfuze.h>
+#include <linux/regmap.h>
 
 #include <envfs.h>
 
diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr_init.c b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c
index aa327d3fb0..c6812e3efa 100644
--- a/arch/arm/boards/phytec-som-imx8mq/ddr_init.c
+++ b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c
@@ -84,6 +84,7 @@ void ddr_init(void)
 	reg32_write(0x3d400204,0x80808);
 	reg32_write(0x3d400214,0x7070707);
 	reg32_write(0x3d400218,0xf070707);
+	reg32_write(0x3d40021c,0xf0f);
 	reg32_write(0x3d402020,0x1);
 	reg32_write(0x3d402024,0x518b00);
 	reg32_write(0x3d402050,0x20d040);
diff --git a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
index cc00527649..fac9e184ae 100644
--- a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
+++ b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c
@@ -12,6 +12,8 @@
 void ddr_cfg_phy(void) {
 	unsigned int tmp, tmp_t;
 
+	ddr_get_firmware(DRAM_TYPE_LPDDR4);
+
 	//Init DDRPHY register...
 	reg32_write(0x3c080440,0x2);
 	reg32_write(0x3c080444,0x3);
@@ -146,7 +148,7 @@ void ddr_cfg_phy(void) {
 	//enable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	//load the 1D training image
-	ddr_load_train_code(FW_1D_IMAGE);
+	imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE);
 
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
@@ -188,7 +190,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
+	imx8m_wait_ddrphy_training_complete();
 
 	//configure DDRPHY-FW DMEM structure @clock1...
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
@@ -222,7 +224,7 @@ void ddr_cfg_phy(void) {
 	//enable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	//load the 1D training image
-	ddr_load_train_code(FW_1D_IMAGE);
+	imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE);
 
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x29c);
@@ -265,7 +267,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
+	imx8m_wait_ddrphy_training_complete();
 
 	//set the PHY input clock to the desired frequency for pstate 0
 	reg32_write(0x3038a088,0x7070000);
@@ -298,7 +300,7 @@ void ddr_cfg_phy(void) {
 	//enable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	//load the 2D training image
-	ddr_load_train_code(FW_2D_IMAGE);
+	imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE);
 
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
@@ -341,7 +343,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
+	imx8m_wait_ddrphy_training_complete();
 
 	//Halt MPU
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
diff --git a/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg
index 8921f32110..f82759f849 100644
--- a/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg
+++ b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg
@@ -1,5 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx8mq
 
 loadaddr 0x007E1000
 max_load_size 0x3F000
 ivtofs 0x400
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
index 05226866f8..362b3ed823 100644
--- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
@@ -6,24 +6,25 @@
 #include <common.h>
 #include <firmware.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx8m-ccm-regs.h>
-#include <mach/iomux-mx8mq.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/iomux-mx8mq.h>
 #include <soc/imx8m/ddr.h>
-#include <mach/xload.h>
+#include <mach/imx/xload.h>
 #include <io.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
 #include <asm/sections.h>
 #include <asm/mmu.h>
-#include <mach/atf.h>
-#include <mach/esdctl.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/esdctl.h>
 
 #include "ddr.h"
 
-extern char __dtb_imx8mq_phytec_phycore_som_start[];
+extern char __dtb_z_imx8mq_phytec_phycore_som_start[];
 
 #define UART_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
 
@@ -42,22 +43,6 @@ static void setup_uart(void)
 	putc_ll('>');
 }
 
-static void phytec_imx8mq_som_sram_setup(void)
-{
-	enum bootsource src = BOOTSOURCE_UNKNOWN;
-	int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
-	int ret = -ENOTSUPP;
-
-	ddr_init();
-
-	imx8mq_get_boot_source(&src, &instance);
-
-	if (src == BOOTSOURCE_MMC)
-		ret = imx8m_esdhc_load_image(instance, true);
-
-	BUG_ON(ret);
-}
-
 static __noreturn noinline void phytec_phycore_imx8mq_start(void)
 {
 	setup_uart();
@@ -69,7 +54,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void)
 		 * that means DDR needs to be initialized for the
 		 * first time.
 		 */
-		phytec_imx8mq_som_sram_setup();
+		ddr_init();
 	}
 	/*
 	 * Straight from the power-on we are at EL3, so the following
@@ -79,18 +64,13 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void)
 	 * initialization routine, it is EL2 which means we'll skip
 	 * loadting ATF blob again
 	 */
-	if (current_el() == 3) {
-		const u8 *bl31;
-		size_t bl31_size;
-
-		get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size);
-		imx8mq_atf_load_bl31(bl31, bl31_size);
-	}
+	if (current_el() == 3)
+		imx8mq_load_and_start_image_via_tfa();
 
 	/*
 	 * Standard entry we hit once we initialized both DDR and ATF
 	 */
-	imx8mq_barebox_entry(__dtb_imx8mq_phytec_phycore_som_start);
+	imx8mq_barebox_entry(__dtb_z_imx8mq_phytec_phycore_som_start);
 }
 
 /*
@@ -108,7 +88,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void)
  *
  * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
  *
- * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
+ * 5. BL31 exits EL3 into EL2 at address MX8M_ATF_BL33_BASE_ADDR,
  *    executing start_phytec_phycore_imx8mq() the third time
  *
  * 6. Standard barebox boot flow continues
diff --git a/arch/arm/boards/phytec-som-rk3288/Makefile b/arch/arm/boards/phytec-som-rk3288/Makefile
index 6f34c9a2f2..e4ba704dea 100644
--- a/arch/arm/boards/phytec-som-rk3288/Makefile
+++ b/arch/arm/boards/phytec-som-rk3288/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-physom-rk3288
diff --git a/arch/arm/boards/phytec-som-rk3288/lowlevel.c b/arch/arm/boards/phytec-som-rk3288/lowlevel.c
index 1a60959562..12044b6039 100644
--- a/arch/arm/boards/phytec-som-rk3288/lowlevel.c
+++ b/arch/arm/boards/phytec-som-rk3288/lowlevel.c
@@ -7,10 +7,11 @@
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/rk3288-regs.h>
-#include <mach/grf_rk3288.h>
-#include <mach/hardware.h>
+#include <mach/rockchip/rk3288-regs.h>
+#include <mach/rockchip/grf_rk3288.h>
+#include <mach/rockchip/hardware.h>
 #include <debug_ll.h>
+#include <mach/rockchip/debug_ll.h>
 
 extern char __dtb_rk3288_phycore_som_start[];
 
@@ -26,7 +27,7 @@ ENTRY_FUNCTION(start_rk3288_phycore_som, r0, r1, r2)
 			     GPIO7C6_MASK << GPIO7C6_SHIFT,
 			     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 			     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
-		INIT_LL();
+		rockchip_debug_ll_init();
 	}
 	fdt = __dtb_rk3288_phycore_som_start + get_runtime_offset();
 
diff --git a/arch/arm/boards/pine64-quartz64/.gitignore b/arch/arm/boards/pine64-quartz64/.gitignore
new file mode 100644
index 0000000000..f458f794b5
--- /dev/null
+++ b/arch/arm/boards/pine64-quartz64/.gitignore
@@ -0,0 +1 @@
+sdram-init.bin
diff --git a/arch/arm/boards/pine64-quartz64/Makefile b/arch/arm/boards/pine64-quartz64/Makefile
new file mode 100644
index 0000000000..b37b6c870b
--- /dev/null
+++ b/arch/arm/boards/pine64-quartz64/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/pine64-quartz64/board.c b/arch/arm/boards/pine64-quartz64/board.c
new file mode 100644
index 0000000000..1573dd8674
--- /dev/null
+++ b/arch/arm/boards/pine64-quartz64/board.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <common.h>
+#include <init.h>
+
+struct quartz64_model {
+	const char *name;
+	const char *shortname;
+};
+
+static int quartz64_probe(struct device *dev)
+{
+	const struct quartz64_model *model;
+
+	model = device_get_match_data(dev);
+
+	barebox_set_model(model->name);
+	barebox_set_hostname(model->shortname);
+
+	return 0;
+}
+
+static const struct quartz64_model quartz64a = {
+	.name = "Pine64 Quartz64 Model A",
+	.shortname = "quartz64a",
+};
+
+static const struct of_device_id quartz64_of_match[] = {
+	{
+		.compatible = "pine64,quartz64-a",
+		.data = &quartz64a,
+	},
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, quartz64_of_match);
+
+static struct driver quartz64_board_driver = {
+	.name = "board-quartz64",
+	.probe = quartz64_probe,
+	.of_compatible = quartz64_of_match,
+};
+coredevice_platform_driver(quartz64_board_driver);
diff --git a/arch/arm/boards/pine64-quartz64/lowlevel.c b/arch/arm/boards/pine64-quartz64/lowlevel.c
new file mode 100644
index 0000000000..7723d47860
--- /dev/null
+++ b/arch/arm/boards/pine64-quartz64/lowlevel.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <asm/barebox-arm.h>
+#include <mach/rockchip/hardware.h>
+#include <mach/rockchip/atf.h>
+#include <debug_ll.h>
+
+extern char __dtb_rk3566_quartz64_a_start[];
+
+ENTRY_FUNCTION(start_quartz64a, r0, r1, r2)
+{
+	putc_ll('>');
+
+	if (current_el() == 3)
+		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
+	else
+		relocate_to_current_adr();
+
+	setup_c();
+
+	rk3568_barebox_entry(__dtb_rk3566_quartz64_a_start);
+}
diff --git a/arch/arm/boards/plathome-openblocks-a6/Makefile b/arch/arm/boards/plathome-openblocks-a6/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/plathome-openblocks-a6/Makefile
+++ b/arch/arm/boards/plathome-openblocks-a6/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/plathome-openblocks-a6/lowlevel.c b/arch/arm/boards/plathome-openblocks-a6/lowlevel.c
index a480c966a4..8a58d692d8 100644
--- a/arch/arm/boards/plathome-openblocks-a6/lowlevel.c
+++ b/arch/arm/boards/plathome-openblocks-a6/lowlevel.c
@@ -3,12 +3,12 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 
 extern char __dtb_kirkwood_openblocks_a6_bb_start[];
 
-ENTRY_FUNCTION(start_plathome_openblocks_a6, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_plathome_openblocks_a6, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/plathome-openblocks-ax3/Makefile b/arch/arm/boards/plathome-openblocks-ax3/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/plathome-openblocks-ax3/Makefile
+++ b/arch/arm/boards/plathome-openblocks-ax3/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c
index 42b291df9f..35888a0b83 100644
--- a/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c
+++ b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c
@@ -4,12 +4,12 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 
 extern char __dtb_armada_xp_openblocks_ax3_4_bb_start[];
 
-ENTRY_FUNCTION(start_plathome_openblocks_ax3, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_plathome_openblocks_ax3, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile
index e9bf1212fe..5b501a548f 100644
--- a/arch/arm/boards/pm9261/Makefile
+++ b/arch/arm/boards/pm9261/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel_init.o
diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
index b316b85d7d..e87c8ad27b 100644
--- a/arch/arm/boards/pm9261/init.c
+++ b/arch/arm/boards/pm9261/init.c
@@ -8,20 +8,19 @@
 #include <gpio.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <platform_data/eth-dm9000.h>
 #include <linux/w1-gpio.h>
 #include <w1_mac_address.h>
diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c
index b18cd067b7..6a44981cc1 100644
--- a/arch/arm/boards/pm9261/lowlevel_init.c
+++ b/arch/arm/boards/pm9261/lowlevel_init.c
@@ -4,10 +4,9 @@
  * Under GPLv2
  */
 
-#include <asm/barebox-arm.h>
-
-#include <mach/at91sam926x_board_init.h>
-#include <mach/at91sam9261_matrix.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam926x_board_init.h>
+#include <mach/at91/at91sam9261_matrix.h>
 
 #define MASTER_PLL_DIV		15
 #define MASTER_PLL_MUL		162
@@ -111,7 +110,7 @@ static void __bare_init pm9261_init(void)
 	                  NULL);
 }
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_pm9261, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/pm9263/Makefile b/arch/arm/boards/pm9263/Makefile
index 68bfbfa926..7220ee11f3 100644
--- a/arch/arm/boards/pm9263/Makefile
+++ b/arch/arm/boards/pm9263/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel_init.o
diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c
index bce612d001..026a8bfe8d 100644
--- a/arch/arm/boards/pm9263/init.c
+++ b/arch/arm/boards/pm9263/init.c
@@ -7,20 +7,19 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <gpio.h>
 #include <fcntl.h>
 #include <io.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <linux/w1-gpio.h>
 #include <w1_mac_address.h>
 
diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c
index 8f44adee99..d06573d1cc 100644
--- a/arch/arm/boards/pm9263/lowlevel_init.c
+++ b/arch/arm/boards/pm9263/lowlevel_init.c
@@ -6,10 +6,9 @@
 
 #include <linux/sizes.h>
 
-#include <asm/barebox-arm.h>
-
-#include <mach/at91sam926x_board_init.h>
-#include <mach/at91sam9263_matrix.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam926x_board_init.h>
+#include <mach/at91/at91sam9263_matrix.h>
 
 #define MASTER_PLL_DIV		6
 #define MASTER_PLL_MUL		65
@@ -132,7 +131,7 @@ static void __bare_init pm9263_board_init(void)
 	                  NULL);
 }
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_pm9263, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/pm9g45/Makefile b/arch/arm/boards/pm9g45/Makefile
index abf50243e5..148ae4a252 100644
--- a/arch/arm/boards/pm9g45/Makefile
+++ b/arch/arm/boards/pm9g45/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
index b347de4157..ee60cf8f00 100644
--- a/arch/arm/boards/pm9g45/init.c
+++ b/arch/arm/boards/pm9g45/init.c
@@ -7,21 +7,20 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <gpio.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <linux/w1-gpio.h>
 #include <w1_mac_address.h>
 
diff --git a/arch/arm/boards/pm9g45/lowlevel.c b/arch/arm/boards/pm9g45/lowlevel.c
index 5f66b28254..9cdc2711e6 100644
--- a/arch/arm/boards/pm9g45/lowlevel.c
+++ b/arch/arm/boards/pm9g45/lowlevel.c
@@ -7,14 +7,11 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/hardware.h>
 
-#include <mach/at91_ddrsdrc.h>
-
-#include <mach/hardware.h>
-
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_pm9g45, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c b/arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c
new file mode 100644
index 0000000000..db75a424b7
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c
@@ -0,0 +1,1125 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+#include <soc/imx8m/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400020, 0x1323 },
+	{ 0x3d400024, 0x1e84800 },
+	{ 0x3d400064, 0x7a017c },
+	{ 0x3d400070, 0x7027f90 },
+	{ 0x3d400074, 0x790 },
+	{ 0x3d4000d0, 0xc00307a3 },
+	{ 0x3d4000d4, 0xc50000 },
+	{ 0x3d4000dc, 0xf4003f },
+	{ 0x3d4000e0, 0x330000 },
+	{ 0x3d4000e8, 0x660048 },
+	{ 0x3d4000ec, 0x160048 },
+	{ 0x3d400100, 0x2028222a },
+	{ 0x3d400104, 0x8083f },
+	{ 0x3d40010c, 0xe0e000 },
+	{ 0x3d400110, 0x12040a12 },
+	{ 0x3d400114, 0x2050f0f },
+	{ 0x3d400118, 0x1010009 },
+	{ 0x3d40011c, 0x501 },
+	{ 0x3d400130, 0x20800 },
+	{ 0x3d400134, 0xe100002 },
+	{ 0x3d400138, 0x184 },
+	{ 0x3d400144, 0xc80064 },
+	{ 0x3d400180, 0x3e8001e },
+	{ 0x3d400184, 0x3207a12 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x49f820e },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x1f0e },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x9121c1c },
+	{ 0x3d400200, 0x18 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf07 },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1021 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0xc0026 },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x330000 },
+	{ 0x3d4020e8, 0x660048 },
+	{ 0x3d4020ec, 0x160048 },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x27 },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x1021 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x3000a },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x330000 },
+	{ 0x3d4030e8, 0x660048 },
+	{ 0x3d4030ec, 0x160048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0xa },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x18 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x3e8 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x8 },
+	{ 0x90159, 0xe8 },
+	{ 0x9015a, 0x109 },
+	{ 0x9015b, 0x0 },
+	{ 0x9015c, 0x8140 },
+	{ 0x9015d, 0x10c },
+	{ 0x9015e, 0x10 },
+	{ 0x9015f, 0x8138 },
+	{ 0x90160, 0x104 },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0x448 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0xf },
+	{ 0x90165, 0x7c0 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0x0 },
+	{ 0x90168, 0xe8 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x47 },
+	{ 0x9016b, 0x630 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x618 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0xe0 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x0 },
+	{ 0x90174, 0x7c8 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x8140 },
+	{ 0x90178, 0x10c },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x478 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x1 },
+	{ 0x9017e, 0x8 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x4 },
+	{ 0x90181, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x68 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x465 },
+	{ 0x2000c, 0xfa },
+	{ 0x2000d, 0x9c4 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x70 },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x1c },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 4000mts 1D */
+		.drate = 4000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 4000mts 2D */
+		.drate = 4000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info imx8mp_debix_8g_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 4000, 400, 100, },
+};
diff --git a/arch/arm/boards/polyhex-debix/Makefile b/arch/arm/boards/polyhex-debix/Makefile
new file mode 100644
index 0000000000..725cb1f8b5
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel.o lpddr4-timing.o 8g-lpddr4-timing.o
diff --git a/arch/arm/boards/polyhex-debix/board.c b/arch/arm/boards/polyhex-debix/board.c
new file mode 100644
index 0000000000..ea4fc26a0c
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/board.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <envfs.h>
+#include <init.h>
+#include <io.h>
+#include <linux/nvmem-consumer.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <net.h>
+
+struct debix_polyhex_machine_data {
+	void (*ethernet_setup)(void);
+};
+
+#define ETH_ALEN_ASCII	12
+
+static int polyhex_debix_eth_register_ethaddr(struct device_node *np)
+{
+	u8 mac[ETH_ALEN];
+	u8 *data;
+	int ret;
+
+	data = nvmem_cell_get_and_read(np, "mac-address", ETH_ALEN_ASCII);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	ret = hex2bin(mac, data, ETH_ALEN);
+	if (ret)
+		goto err;
+
+	of_eth_register_ethaddr(np, mac);
+err:
+	free(data);
+
+	return ret;
+}
+
+static void polyhex_debix_ethernet_init(void)
+{
+	static const char * const aliases[] = { "ethernet0", "ethernet1" };
+	struct device_node *np, *root;
+	unsigned int i;
+
+	root = of_get_root_node();
+
+	for (i = 0; i < ARRAY_SIZE(aliases); i++) {
+		const char *alias = aliases[i];
+		int ret;
+
+		np = of_find_node_by_alias(root, alias);
+		if (!np) {
+			pr_warn("Failed to find %s\n", alias);
+			continue;
+		}
+
+		ret = polyhex_debix_eth_register_ethaddr(np);
+		if (ret) {
+			pr_warn("Failed to register MAC for %s\n", alias);
+			continue;
+		}
+	}
+}
+
+static int polyhex_debix_probe(struct device *dev)
+{
+	const struct debix_polyhex_machine_data *machine_data;
+	int emmc_bbu_flag = 0;
+	int sd_bbu_flag = 0;
+	u32 val;
+
+	if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) {
+		of_device_enable_path("/chosen/environment-sd");
+		sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	} else {
+		of_device_enable_path("/chosen/environment-emmc");
+		emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+
+	/* Enable RGMII TX clk output */
+	val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
+	val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN |
+	       MX8MP_IOMUXC_GPR1_ENET_QOS_RGMII_EN;
+	writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
+
+	machine_data = device_get_match_data(dev);
+	if (machine_data && machine_data->ethernet_setup)
+		machine_data->ethernet_setup();
+
+	return 0;
+}
+
+static const struct debix_polyhex_machine_data debix_som_a_bmb_08 = {
+	.ethernet_setup = polyhex_debix_ethernet_init,
+};
+
+static const struct of_device_id polyhex_debix_of_match[] = {
+	{ .compatible = "polyhex,imx8mp-debix" },
+	{ .compatible = "polyhex,imx8mp-debix-som-a-bmb-08", .data = &debix_som_a_bmb_08 },
+	{ /* Sentinel */ }
+};
+BAREBOX_DEEP_PROBE_ENABLE(polyhex_debix_of_match);
+
+static struct driver polyhex_debix_board_driver = {
+	.name = "board-imx8mp-debix",
+	.probe = polyhex_debix_probe,
+	.of_compatible = polyhex_debix_of_match,
+};
+coredevice_platform_driver(polyhex_debix_board_driver);
diff --git a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
new file mode 100644
index 0000000000..6ea2e6c68e
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mp
+
+loadaddr 0x920000
+max_load_size 0x3f000
+ivtofs 0x0
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/polyhex-debix/lowlevel.c b/arch/arm/boards/polyhex-debix/lowlevel.c
new file mode 100644
index 0000000000..fa49fcb5c1
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/lowlevel.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/imx8mp-regs.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <mach/imx/xload.h>
+#include <mfd/pca9450.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <soc/imx8m/ddr.h>
+
+extern char __dtb_z_imx8mp_debix_model_a_start[];
+extern char __dtb_z_imx8mp_debix_som_a_bmb_08_start[];
+
+#define UART_PAD_CTRL   MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+				     MX8MP_PAD_CTL_FSEL | \
+				     MX8MP_PAD_CTL_PUE | \
+				     MX8MP_PAD_CTL_PE)
+
+#define I2C_PAD_CTRL	MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+				     MX8MP_PAD_CTL_HYS | \
+				     MX8MP_PAD_CTL_PUE | \
+				     MX8MP_PAD_CTL_PE)
+
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_UART2_RXD__UART2_DCE_RX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+
+	putc_ll('>');
+}
+
+static struct pmic_config pca9450_cfg[] = {
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	{ PCA9450_BUCK123_DVS, 0x29 },
+	/*
+	 * increase VDD_SOC to typical value 0.95V before first
+	 * DRAM access, set DVS1 to 0.85v for suspend.
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+	 */
+	{ PCA9450_BUCK1OUT_DVS0, 0x1C },
+	{ PCA9450_BUCK1OUT_DVS1, 0x14 },
+	{ PCA9450_BUCK1CTRL, 0x59 },
+	/*
+	 * Increase VDD_ARM to 0.95V to avoid issues in case software after
+	 * Barebox switches to the OD ARM frequency without reprogramming the
+	 * PMIC first.
+	 */
+	{ PCA9450_BUCK2OUT_DVS0, 0x1C },
+	/* set WDOG_B_CFG to cold reset */
+	{ PCA9450_RESET_CTRL, 0xA1 },
+};
+
+static void power_init_board(void)
+{
+	struct pbl_i2c *i2c;
+
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
+
+	pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+}
+
+extern struct dram_timing_info imx8mp_debix_dram_timing;
+extern struct dram_timing_info imx8mp_debix_8g_dram_timing;
+
+static void start_atf(struct dram_timing_info *dram_timing)
+{
+	/*
+	 * If we are in EL3 we are running for the first time and need to
+	 * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
+	 * to DRAM in EL2.
+	 */
+	if (current_el() != 3)
+		return;
+
+	imx8mp_early_clock_init();
+
+	power_init_board();
+
+	imx8mp_ddr_init(dram_timing, DRAM_TYPE_LPDDR4);
+
+	imx8mp_load_and_start_image_via_tfa();
+}
+
+/*
+ * Power-on execution flow of start_imx8mp_debix() might not be
+ * obvious for a very first read, so here's, hopefully helpful,
+ * summary:
+ *
+ * 1. MaskROM uploads PBL into OCRAM and that's where this function is
+ *    executed for the first time. At entry the exception level is EL3.
+ *
+ * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL
+ *    part is copied from OCRAM to the TF-A return address in DRAM.
+ *
+ * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us
+ *    from EL3 to EL2.
+ *
+ * 4. Standard barebox boot flow continues
+ */
+static __noreturn noinline void
+imx8mp_debix_start(struct dram_timing_info *dram_timing, void *dtb)
+{
+	setup_uart();
+
+	start_atf(dram_timing);
+
+	/*
+	 * Standard entry we hit once we initialized both DDR and ATF
+	 */
+	imx8mp_barebox_entry(dtb);
+}
+
+ENTRY_FUNCTION(start_polyhex_debix, r0, r1, r2)
+{
+	imx8mp_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	imx8mp_debix_start(&imx8mp_debix_dram_timing,
+			   __dtb_z_imx8mp_debix_model_a_start);
+}
+
+ENTRY_FUNCTION(start_polyhex_debix_som_a_8g, r0, r1, r2)
+{
+	imx8mp_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	imx8mp_debix_start(&imx8mp_debix_8g_dram_timing,
+			   __dtb_z_imx8mp_debix_som_a_bmb_08_start);
+}
diff --git a/arch/arm/boards/polyhex-debix/lpddr4-timing.c b/arch/arm/boards/polyhex-debix/lpddr4-timing.c
new file mode 100644
index 0000000000..2724b893d6
--- /dev/null
+++ b/arch/arm/boards/polyhex-debix/lpddr4-timing.c
@@ -0,0 +1,1123 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+#include <soc/imx8m/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x1323 },
+	{ 0x3d400024, 0x1c61a00 },
+	{ 0x3d400064, 0x710105 },
+	{ 0x3d400070, 0x61027f10 },
+	{ 0x3d400074, 0x7b0 },
+	{ 0x3d4000d0, 0xc003071a },
+	{ 0x3d4000d4, 0xb70000 },
+	{ 0x3d4000dc, 0xe40036 },
+	{ 0x3d4000e0, 0x330000 },
+	{ 0x3d4000e8, 0x660048 },
+	{ 0x3d4000ec, 0x160048 },
+	{ 0x3d400100, 0x1e261f28 },
+	{ 0x3d400104, 0x7073b },
+	{ 0x3d40010c, 0xe0e000 },
+	{ 0x3d400110, 0x11040a11 },
+	{ 0x3d400114, 0x2050e0e },
+	{ 0x3d400118, 0x1010008 },
+	{ 0x3d40011c, 0x501 },
+	{ 0x3d400130, 0x20700 },
+	{ 0x3d400134, 0xe100002 },
+	{ 0x3d400138, 0x10c },
+	{ 0x3d400144, 0xba005d },
+	{ 0x3d400180, 0x3a2001c },
+	{ 0x3d400184, 0x2f07187 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x49b820c },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x1b0c },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x810191a },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1021 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x330000 },
+	{ 0x3d4020e8, 0x660048 },
+	{ 0x3d4020ec, 0x160048 },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x1021 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x330000 },
+	{ 0x3d4030e8, 0x660048 },
+	{ 0x3d4030ec, 0x160048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x3a2 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xe88 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x36e4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x36e4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xe400 },
+	{ 0x54033, 0x3336 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xe400 },
+	{ 0x54039, 0x3336 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xe88 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x36e4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x36e4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xe400 },
+	{ 0x54033, 0x3336 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xe400 },
+	{ 0x54039, 0x3336 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x8 },
+	{ 0x90159, 0xe8 },
+	{ 0x9015a, 0x109 },
+	{ 0x9015b, 0x0 },
+	{ 0x9015c, 0x8140 },
+	{ 0x9015d, 0x10c },
+	{ 0x9015e, 0x10 },
+	{ 0x9015f, 0x8138 },
+	{ 0x90160, 0x104 },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0x448 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0xf },
+	{ 0x90165, 0x7c0 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0x0 },
+	{ 0x90168, 0xe8 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x47 },
+	{ 0x9016b, 0x630 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x618 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0xe0 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x0 },
+	{ 0x90174, 0x7c8 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x8140 },
+	{ 0x90178, 0x10c },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x478 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x1 },
+	{ 0x9017e, 0x8 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x4 },
+	{ 0x90181, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x68 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x74 },
+	{ 0x2000c, 0xe8 },
+	{ 0x2000d, 0x915 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3720mts 1D */
+		.drate = 3720,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3720mts 2D */
+		.drate = 3720,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* Samsung K4F6E3S4HM-MGCJ ddr timing config params */
+struct dram_timing_info imx8mp_debix_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3720, 400, 100, },
+};
diff --git a/arch/arm/boards/protonic-imx6/Makefile b/arch/arm/boards/protonic-imx6/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/protonic-imx6/Makefile
+++ b/arch/arm/boards/protonic-imx6/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/protonic-imx6/board.c b/arch/arm/boards/protonic-imx6/board.c
index a718d54df4..9e62dc1544 100644
--- a/arch/arm/boards/protonic-imx6/board.c
+++ b/arch/arm/boards/protonic-imx6/board.c
@@ -4,22 +4,27 @@
 // SPDX-FileCopyrightText: 2020 Oleksij Rempel, Pengutronix
 
 #include <bbu.h>
+#include <boot.h>
+#include <bootm.h>
 #include <common.h>
+#include <deep-probe.h>
 #include <environment.h>
 #include <fcntl.h>
+#include <globalvar.h>
 #include <gpio.h>
 #include <i2c/i2c.h>
-#include <mach/bbu.h>
-#include <mach/imx6.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/ocotp-fusemap.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
 #include <mfd/syscon.h>
 #include <net.h>
 #include <of_device.h>
-#include <regmap.h>
+#include <linux/regmap.h>
 #include <sys/mount.h>
 #include <sys/stat.h>
 #include <unistd.h>
-#include <usb/usb.h>
+#include <linux/usb/usb.h>
 
 #define GPIO_HW_REV_ID  {\
 	{IMX_GPIO_NR(2, 8), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "rev_id0"}, \
@@ -50,6 +55,8 @@ enum {
 	HW_TYPE_LANMCU = 23,
 	HW_TYPE_PLYBAS = 24,
 	HW_TYPE_VICTGO = 28,
+	HW_TYPE_JOZACP = 30,
+	HW_TYPE_JOZACPP = 31,
 };
 
 enum prt_imx6_kvg_pw_mode {
@@ -70,18 +77,20 @@ struct prt_machine_data {
 	unsigned int hw_rev;
 	unsigned int i2c_addr;
 	unsigned int i2c_adapter;
+	unsigned int emmc_usdhc;
+	unsigned int sd_usdhc;
 	unsigned int flags;
 	int (*init)(struct prt_imx6_priv *priv);
 };
 
 struct prt_imx6_priv {
-	struct device_d *dev;
+	struct device *dev;
 	const struct prt_machine_data *dcfg;
 	unsigned int hw_id;
 	unsigned int hw_rev;
 	const char *name;
-	struct poller_async poller;
-	unsigned int usb_delay;
+	unsigned int no_usb_check;
+	char *ocotp_serial;
 };
 
 struct prti6q_rfid_contents {
@@ -118,11 +127,27 @@ static const struct gpio prt_imx6_kvg_gpios[] = {
 	},
 };
 
+static int prt_of_fixup_hwrev(struct prt_imx6_priv *priv)
+{
+	const char *compat;
+	char *buf;
+
+	compat = of_device_get_match_compatible(priv->dev);
+
+	buf = xasprintf("%s-m%u-r%u", compat, priv->hw_id,
+			priv->hw_rev);
+	barebox_set_of_machine_compatible(buf);
+
+	free(buf);
+
+	return 0;
+}
+
 static int prt_imx6_read_rfid(struct prt_imx6_priv *priv, void *buf,
 			      size_t size)
 {
 	const struct prt_machine_data *dcfg = priv->dcfg;
-	struct device_d *dev = priv->dev;
+	struct device *dev = priv->dev;
 	struct i2c_client cl;
 	int ret;
 
@@ -136,7 +161,7 @@ static int prt_imx6_read_rfid(struct prt_imx6_priv *priv, void *buf,
 	/* 0x6000 user storage in the RFID tag */
 	ret = i2c_read_reg(&cl, 0x6000 | I2C_ADDR_16_BIT, buf, size);
 	if (ret < 0) {
-		dev_err(dev, "Failed to read the RFID: %i\n", ret);
+		dev_err(dev, "Failed to read the RFID: %pe\n", ERR_PTR(ret));
 		return ret;
 	}
 
@@ -162,7 +187,7 @@ static u8 prt_imx6_calc_rfid_cs(void *buf, size_t size)
 static int prt_imx6_set_mac(struct prt_imx6_priv *priv,
 			    struct prti6q_rfid_contents *rfid)
 {
-	struct device_d *dev = priv->dev;
+	struct device *dev = priv->dev;
 	struct device_node *node;
 
 	node = of_find_node_by_alias(of_get_root_node(), "ethernet0");
@@ -171,11 +196,11 @@ static int prt_imx6_set_mac(struct prt_imx6_priv *priv,
 		return -ENODEV;
 	}
 
-	if (!is_valid_ether_addr(&rfid->mac[0])) {
-		unsigned char ethaddr_str[sizeof("xx:xx:xx:xx:xx:xx")];
+	if (!of_device_is_available(node))
+		return 0;
 
-		ethaddr_to_string(&rfid->mac[0], ethaddr_str);
-		dev_err(dev, "bad MAC addr: %s\n", ethaddr_str);
+	if (!is_valid_ether_addr(&rfid->mac[0])) {
+		dev_err(dev, "bad MAC addr: %pM\n", &rfid->mac[0]);
 
 		return -EILSEQ;
 	}
@@ -185,37 +210,18 @@ static int prt_imx6_set_mac(struct prt_imx6_priv *priv,
 	return 0;
 }
 
-static int prt_of_fixup_serial(struct device_node *dstroot, void *arg)
-{
-	struct device_node *srcroot = arg;
-	const char *ser;
-	int len;
-
-	ser = of_get_property(srcroot, "serial-number", &len);
-	return of_set_property(dstroot, "serial-number", ser, len, 1);
-}
-
-static void prt_oftree_fixup_serial(const char *serial)
-{
-	struct device_node *root = of_get_root_node();
-
-	of_set_property(root, "serial-number", serial, strlen(serial) + 1, 1);
-	of_register_fixup(prt_of_fixup_serial, root);
-}
-
-static int prt_imx6_set_serial(struct prt_imx6_priv *priv,
-			       struct prti6q_rfid_contents *rfid)
+static int prt_imx6_set_serial(struct prt_imx6_priv *priv, char *serial)
 {
-	rfid->serial[9] = 0; /* Failsafe */
-	dev_info(priv->dev, "Serial number: %s\n", rfid->serial);
-	prt_oftree_fixup_serial(rfid->serial);
+	serial[9] = 0; /* Failsafe */
+	dev_info(priv->dev, "Serial number: %s\n", serial);
+	barebox_set_serial_number(serial);
 
 	return 0;
 }
 
 static int prt_imx6_read_i2c_mac_serial(struct prt_imx6_priv *priv)
 {
-	struct device_d *dev = priv->dev;
+	struct device *dev = priv->dev;
 	struct prti6q_rfid_contents rfid;
 	int ret;
 
@@ -232,16 +238,60 @@ static int prt_imx6_read_i2c_mac_serial(struct prt_imx6_priv *priv)
 	if (ret)
 		return ret;
 
-	ret = prt_imx6_set_serial(priv, &rfid);
+	ret = prt_imx6_set_serial(priv, rfid.serial);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+#define PRT_IMX6_GP1_FMT_DEC		BIT(31)
+
+static int prt_imx6_read_ocotp_serial(struct prt_imx6_priv *priv)
+{
+	int ret;
+	unsigned val;
+
+	ret = imx_ocotp_read_field(OCOTP_GP1, &val);
+	if (ret) {
+		dev_err(priv->dev, "Failed to read ocotp serial (%i)\n", ret);
+		return ret;
+	}
+
+	if (!(val & PRT_IMX6_GP1_FMT_DEC))
+		return -EINVAL;
+	val &= PRT_IMX6_GP1_FMT_DEC - 1;
+
+	priv->ocotp_serial = xasprintf("%u", val);
+
+	return prt_imx6_set_serial(priv, priv->ocotp_serial);
+}
+
+static int prt_imx6_set_ocotp_serial(struct param_d *param, void *driver_priv)
+{
+	struct prt_imx6_priv *priv = driver_priv;
+	int ret;
+	unsigned val;
+
+	ret = kstrtouint(priv->ocotp_serial, 10, &val);
+	if (ret)
+		return ret;
+
+	if (val & PRT_IMX6_GP1_FMT_DEC)
+		return -ERANGE;
+	val |= PRT_IMX6_GP1_FMT_DEC;
+
+	ret = imx_ocotp_write_field(OCOTP_GP1, val);
 	if (ret)
 		return ret;
 
+	barebox_set_serial_number(priv->ocotp_serial);
 	return 0;
 }
 
-static int prt_imx6_usb_mount(struct prt_imx6_priv *priv, char **usbdisk)
+static int prt_imx6_usb_mount(struct prt_imx6_priv *priv)
 {
-	struct device_d *dev = priv->dev;
+	struct device *dev = priv->dev;
 	const char *path;
 	struct stat s;
 	int ret;
@@ -258,8 +308,6 @@ static int prt_imx6_usb_mount(struct prt_imx6_priv *priv, char **usbdisk)
 		ret = mount(path, NULL, "usb", NULL);
 		if (ret)
 			goto exit_usb_mount;
-
-		*usbdisk = strdup("disk0.0");
 		return 0;
 	}
 
@@ -269,8 +317,6 @@ static int prt_imx6_usb_mount(struct prt_imx6_priv *priv, char **usbdisk)
 		ret = mount(path, NULL, "usb", NULL);
 		if (ret)
 			goto exit_usb_mount;
-
-		*usbdisk = strdup("disk0");
 		return 0;
 	}
 
@@ -281,25 +327,21 @@ exit_usb_mount:
 
 #define OTG_PORTSC1 (MX6_OTG_BASE_ADDR+0x184)
 
-static void prt_imx6_check_usb_boot(void *data)
+static int prt_imx6_usb_boot(struct bootentry *entry, int verbose, int dryrun)
 {
-	struct prt_imx6_priv *priv = data;
-	struct device_d *dev = priv->dev;
-	char *second_word, *bootsrc, *usbdisk;
+	struct prt_imx6_priv *priv = prt_priv;
+	struct device *dev = priv->dev;
+	char *second_word;
 	char buf[sizeof("vicut1q recovery")] = {};
-	unsigned int v;
+	struct bootm_data bootm_data = {};
 	ssize_t size;
 	int fd, ret;
 
-	v = readl(OTG_PORTSC1);
-	if ((v & 0x0c00) == 0) /* LS == SE0 ==> nothing connected */
-		return;
-
 	usb_rescan();
 
-	ret = prt_imx6_usb_mount(priv, &usbdisk);
+	ret = prt_imx6_usb_mount(priv);
 	if (ret)
-		return;
+		return ret;
 
 	fd = open("/usb/boot_target", O_RDONLY);
 	if (fd < 0) {
@@ -338,60 +380,125 @@ static void prt_imx6_check_usb_boot(void *data)
 		goto exit_usb_boot;
 	}
 
+	bootm_data_init_defaults(&bootm_data);
+
 	second_word++;
 	if (strncmp(second_word, "usb", 3) == 0) {
-		bootsrc = usbdisk;
+		dev_info(dev, "Booting from USB drive\n");
+		bootm_data.os_file = "/usb/linuximage.fit";
 	} else if (strncmp(second_word, "recovery", 8) == 0) {
-		bootsrc = "recovery";
+		dev_info(dev, "Booting internal recovery OS\n");
+		bootm_data.os_file = "/dev/mmc2.5";
 	} else {
 		dev_err(dev, "Unknown boot target!\n");
 		ret = -ENODEV;
 		goto exit_usb_boot;
 	}
 
-	dev_info(dev, "detected valid usb boot target file, overwriting boot to: %s\n", bootsrc);
-	ret = setenv("global.boot.default", bootsrc);
+	ret = globalvar_add_simple("linux.bootargs.root",
+		"root=/dev/ram rw rootwait ramdisk_size=196608");
+	if (ret)
+		goto exit_usb_boot;
+
+	if (verbose)
+		bootm_data.verbose = verbose;
+	if (dryrun)
+		bootm_data.dryrun = dryrun;
+
+	ret = bootm_boot(&bootm_data);
 	if (ret)
 		goto exit_usb_boot;
 
-	free(usbdisk);
-	return;
+	return 0;
 
 exit_usb_boot:
 	dev_err(dev, "Failed to run usb boot: %s\n", strerror(-ret));
-	free(usbdisk);
 
-	return;
+	return ret;
+}
+
+static void prt_imx6_bootentry_release(struct bootentry *entry)
+{
+	free(entry);
+}
+
+static int prt_imx6_bootentry_create(struct bootentries *bootentries, const char *name)
+{
+	struct bootentry *entry;
+
+	entry = xzalloc(sizeof(*entry));
+	if (!entry)
+		return -ENOMEM;
+
+	entry->me.type = MENU_ENTRY_NORMAL;
+	entry->release = prt_imx6_bootentry_release;
+	entry->boot = prt_imx6_usb_boot;
+	entry->title = xstrdup(name);
+	entry->description = xstrdup("Boot FIT image of a USB drive");
+	bootentries_add_entry(bootentries, entry);
+
+	return 0;
+}
+
+static int prt_imx6_bootentry_provider(struct bootentries *bootentries,
+				     const char *name)
+{
+	int found = 0;
+	unsigned int v;
+
+	if (strncmp(name, "prt-usb", 7))
+		return found;
+
+	v = readl(OTG_PORTSC1);
+	if ((v & 0x0c00) == 0)	/* No usb device detected */
+		return found;
+
+	if (!prt_imx6_bootentry_create(bootentries, name))
+		found = 1;
+
+	return found;
 }
 
 static int prt_imx6_env_init(struct prt_imx6_priv *priv)
 {
 	const struct prt_machine_data *dcfg = priv->dcfg;
-	struct device_d *dev = priv->dev;
-	char *delay, *bootsrc;
+	struct device *dev = priv->dev;
+	char *delay, *bootsrc, *boot_targets;
+	unsigned int autoboot_timeout;
 	int ret;
 
 	ret = setenv("global.linux.bootargs.base", "consoleblank=0 vt.color=0x00");
 	if (ret)
 		goto exit_env_init;
 
-	if (dcfg->flags & PRT_IMX6_USB_LONG_DELAY)
-		priv->usb_delay = 4;
-	else
-		priv->usb_delay = 1;
-
-	/* the usb_delay value is used for poller_call_async() */
-	delay = basprintf("%d", priv->usb_delay);
-	ret = setenv("global.autoboot_timeout", delay);
-	if (ret)
-		goto exit_env_init;
+	if (priv->no_usb_check) {
+		set_autoboot_state(AUTOBOOT_BOOT);
+	} else {
+		if (dcfg->flags & PRT_IMX6_USB_LONG_DELAY)
+			autoboot_timeout = 4;
+		else
+			autoboot_timeout = 1;
+
+		/* the usb_delay value is used for poller_call_async() */
+		delay = basprintf("%d", autoboot_timeout);
+		ret = setenv("global.autoboot_timeout", delay);
+		free(delay);
+		if (ret)
+			goto exit_env_init;
+	}
 
 	if (dcfg->flags & PRT_IMX6_BOOTCHOOSER)
 		bootsrc = "bootchooser";
 	else
 		bootsrc = "mmc2";
 
-	ret = setenv("global.boot.default", bootsrc);
+	if (!priv->no_usb_check)
+		boot_targets = xasprintf("prt-usb %s", bootsrc);
+	else
+		boot_targets = xstrdup(bootsrc);
+
+	ret = setenv("global.boot.default", boot_targets);
+	free(boot_targets);
 	if (ret)
 		goto exit_env_init;
 
@@ -399,7 +506,7 @@ static int prt_imx6_env_init(struct prt_imx6_priv *priv)
 	return 0;
 
 exit_env_init:
-	dev_err(dev, "Failed to set env: %i\n", ret);
+	dev_err(dev, "Failed to set env: %pe\n", ERR_PTR(ret));
 
 	return ret;
 }
@@ -408,6 +515,7 @@ static int prt_imx6_bbu(struct prt_imx6_priv *priv)
 {
 	const struct prt_machine_data *dcfg = priv->dcfg;
 	u32 emmc_flags = 0;
+	char *devicefile;
 	int ret;
 
 	if (dcfg->flags & PRT_IMX6_BOOTSRC_SPI_NOR) {
@@ -419,25 +527,37 @@ static int prt_imx6_bbu(struct prt_imx6_priv *priv)
 		emmc_flags = BBU_HANDLER_FLAG_DEFAULT;
 	}
 
-	ret = imx6_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2",
+	devicefile = basprintf("/dev/mmc%d", dcfg->emmc_usdhc);
+	if (!devicefile) {
+		ret = -ENOMEM;
+		goto exit_bbu;
+	}
+	ret = imx6_bbu_internal_mmcboot_register_handler("eMMC", devicefile,
 						   emmc_flags);
 	if (ret)
 		goto exit_bbu;
 
-	ret = imx6_bbu_internal_mmc_register_handler("SD", "/dev/mmc0", 0);
+	devicefile = basprintf("/dev/mmc%d", dcfg->sd_usdhc);
+	if (!devicefile) {
+		ret = -ENOMEM;
+		goto exit_bbu;
+	}
+
+	ret = imx6_bbu_internal_mmc_register_handler("SD", devicefile, 0);
 	if (ret)
 		goto exit_bbu;
 
 	return 0;
 exit_bbu:
-	dev_err(priv->dev, "Failed to register bbu: %i\n", ret);
+	dev_err(priv->dev, "Failed to register bbu: %pe\n", ERR_PTR(ret));
 	return ret;
 }
 
 static int prt_imx6_devices_init(void)
 {
 	struct prt_imx6_priv *priv = prt_priv;
-	int ret;
+	struct device *ocotp_dev;
+	struct param_d *p;
 
 	if (!priv)
 		return 0;
@@ -447,19 +567,28 @@ static int prt_imx6_devices_init(void)
 
 	prt_imx6_bbu(priv);
 
-	prt_imx6_read_i2c_mac_serial(priv);
+	/*
+	 * Read serial number from fuses. On success we'll assume the imx_ocotp
+	 * driver takes care of providing the mac address if needed. On
+	 * failure we'll fallback to reading and setting serial and mac from an
+	 * attached RFID eeprom.
+	 */
+	if (prt_imx6_read_ocotp_serial(priv) != 0)
+		prt_imx6_read_i2c_mac_serial(priv);
+
+	bootentry_register_provider(prt_imx6_bootentry_provider);
 
 	prt_imx6_env_init(priv);
 
-	ret = poller_async_register(&priv->poller, "usb-boot");
-	if (ret) {
-		dev_err(priv->dev, "can't setup poller\n");
-		return ret;
+	ocotp_dev = get_device_by_name("ocotp0");
+	if (ocotp_dev) {
+		p = dev_add_param_string(ocotp_dev, "serial_number",
+				 prt_imx6_set_ocotp_serial, NULL,
+				 &priv->ocotp_serial, priv);
+		if (IS_ERR(p))
+			return PTR_ERR(p);
 	}
 
-	poller_call_async(&priv->poller, priv->usb_delay * SECOND,
-			  &prt_imx6_check_usb_boot, priv);
-
 	return 0;
 }
 late_initcall(prt_imx6_devices_init);
@@ -483,7 +612,7 @@ static int prt_imx6_yaco_set_kvg_power_mode(struct prt_imx6_priv *priv,
 					    const char *serial)
 {
 	static const char command[] = "{\"command\":\"mode\",\"value\":\"kvg\",\"on2\":true}";
-	struct device_d *dev = priv->dev;
+	struct device *dev = priv->dev;
 	struct console_device *yccon;
 	int ret;
 
@@ -503,7 +632,7 @@ static int prt_imx6_yaco_set_kvg_power_mode(struct prt_imx6_priv *priv,
 	return 0;
 
 exit_yaco_set_kvg_power_mode:
-	dev_err(dev, "Failed to set YaCO pw mode: %i", ret);
+	dev_err(dev, "Failed to set YaCO pw mode: %pe", ERR_PTR(ret));
 
 	return ret;
 }
@@ -611,6 +740,34 @@ static int prt_imx6_init_kvg_yaco(struct prt_imx6_priv *priv)
 	return prt_imx6_init_kvg_power(priv, PW_MODE_KVG_WITH_YACO);
 }
 
+#define GPIO_KEY_F6     (0xe0 + 5)
+#define GPIO_KEY_CYCLE  (0xe0 + 2)
+
+static int prt_imx6_init_prtvt7(struct prt_imx6_priv *priv)
+{
+	/* This function relies heavely on the gpio-pca9539 driver */
+
+	gpio_direction_input(GPIO_KEY_F6);
+	gpio_direction_input(GPIO_KEY_CYCLE);
+
+	if (gpio_get_value(GPIO_KEY_CYCLE) && gpio_get_value(GPIO_KEY_F6))
+		priv->no_usb_check = 1;
+
+	return 0;
+}
+
+static int prt_imx6_init_prtwd3(struct prt_imx6_priv *priv)
+{
+	void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
+	uint32_t val;
+
+	val = readl(iomux + IOMUXC_GPR1);
+	val |= IMX6Q_GPR1_ENET_CLK_SEL_ANATOP;
+	writel(val, iomux + IOMUXC_GPR1);
+
+	return 0;
+}
+
 static int prt_imx6_rfid_fixup(struct prt_imx6_priv *priv,
 			       struct device_node *root)
 {
@@ -628,24 +785,22 @@ static int prt_imx6_rfid_fixup(struct prt_imx6_priv *priv,
 	}
 
 	i2c_node = of_find_node_by_alias(root, alias);
+	kfree(alias);
 	if (!i2c_node) {
 		dev_err(priv->dev, "Unsupported i2c adapter\n");
-		ret = -ENODEV;
-		goto free_alias;
+		return -ENODEV;
 	}
 
 	eeprom_node_name = basprintf("/eeprom@%x", dcfg->i2c_addr);
 	if (!eeprom_node_name) {
-		ret = -ENOMEM;
-		goto free_alias;
+		return -ENOMEM;
 	}
 
 	node = of_create_node(i2c_node, eeprom_node_name);
 	if (!node) {
 		dev_err(priv->dev, "Failed to create node %s\n",
 			eeprom_node_name);
-		ret = -ENOMEM;
-		goto free_eeprom;
+		return -ENOMEM;
 	}
 
 	ret = of_property_write_string(node, "compatible", "atmel,24c256");
@@ -669,10 +824,8 @@ static int prt_imx6_rfid_fixup(struct prt_imx6_priv *priv,
 	return 0;
 free_eeprom:
 	kfree(eeprom_node_name);
-free_alias:
-	kfree(alias);
 exit_error:
-	dev_err(priv->dev, "Failed to apply fixup: %i\n", ret);
+	dev_err(priv->dev, "Failed to apply fixup: %pe\n", ERR_PTR(ret));
 	return ret;
 }
 
@@ -693,7 +846,7 @@ static int prt_imx6_of_fixup(struct device_node *root, void *data)
 
 	return 0;
 exit_of_fixups:
-	dev_err(priv->dev, "Failed to apply OF fixups: %i\n", ret);
+	dev_err(priv->dev, "Failed to apply OF fixups: %pe\n", ERR_PTR(ret));
 	return ret;
 }
 
@@ -701,8 +854,17 @@ static int prt_imx6_get_id(struct prt_imx6_priv *priv)
 {
 	struct gpio gpios_type[] = GPIO_HW_TYPE_ID;
 	struct gpio gpios_rev[] = GPIO_HW_REV_ID;
+	struct device_node *gpio_np = NULL;
 	int ret;
 
+	gpio_np = of_find_node_by_name_address(NULL, "gpio@20a0000");
+	if (!gpio_np)
+		return -ENODEV;
+
+	ret = of_device_ensure_probed(gpio_np);
+	if (ret)
+		return ret;
+
 	ret = gpio_array_to_id(gpios_type, ARRAY_SIZE(gpios_type), &priv->hw_id);
 	if (ret)
 		goto exit_get_id;
@@ -713,7 +875,7 @@ static int prt_imx6_get_id(struct prt_imx6_priv *priv)
 
 	return 0;
 exit_get_id:
-	dev_err(priv->dev, "Failed to read gpio ID: %i\n", ret);
+	dev_err(priv->dev, "Failed to read gpio ID: %pe\n", ERR_PTR(ret));
 	return ret;
 }
 
@@ -749,10 +911,9 @@ exit_get_dcfg:
 	return ret;
 }
 
-static int prt_imx6_probe(struct device_d *dev)
+static int prt_imx6_probe(struct device *dev)
 {
 	struct prt_imx6_priv *priv;
-	const char *name, *ptr;
 	struct param_d *p;
 	int ret;
 
@@ -761,9 +922,7 @@ static int prt_imx6_probe(struct device_d *dev)
 		return -ENOMEM;
 
 	priv->dev = dev;
-	name = of_device_get_match_compatible(priv->dev);
-	ptr = strchr(name, ',');
-	priv->name =  ptr ? ptr + 1 : name;
+	priv->name = of_get_machine_compatible();
 
 	pr_info("Detected machine type: %s\n", priv->name);
 
@@ -773,6 +932,7 @@ static int prt_imx6_probe(struct device_d *dev)
 
 	pr_info("  HW type:     %d\n", priv->hw_id);
 	pr_info("  HW revision: %d\n", priv->hw_rev);
+	prt_of_fixup_hwrev(priv);
 
 	ret = prt_imx6_get_dcfg(priv);
 	if (ret)
@@ -794,12 +954,6 @@ static int prt_imx6_probe(struct device_d *dev)
 	if (ret)
 		goto free_priv;
 
-	ret = of_register_fixup(prt_imx6_of_fixup, priv);
-	if (ret) {
-		dev_err(dev, "Failed to register fixup\n");
-		goto free_priv;
-	}
-
 	prt_priv = priv;
 
 	return 0;
@@ -814,6 +968,8 @@ static const struct prt_machine_data prt_imx6_cfg_alti6p[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_EMMC,
 	}, {
 		.hw_id = UINT_MAX
@@ -826,6 +982,8 @@ static const struct prt_machine_data prt_imx6_cfg_victgo[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.init = prt_imx6_init_victgo,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
@@ -839,12 +997,16 @@ static const struct prt_machine_data prt_imx6_cfg_vicut1[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x50,
 		.i2c_adapter = 1,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
 		.hw_id = HW_TYPE_VICUT1,
 		.hw_rev = 1,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.init = prt_imx6_init_kvg_yaco,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
@@ -852,6 +1014,8 @@ static const struct prt_machine_data prt_imx6_cfg_vicut1[] = {
 		.hw_rev = 1,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.init = prt_imx6_init_kvg_new,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
@@ -865,12 +1029,16 @@ static const struct prt_machine_data prt_imx6_cfg_vicut1q[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x50,
 		.i2c_adapter = 1,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
 		.hw_id = HW_TYPE_VICUT1,
 		.hw_rev = 1,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.init = prt_imx6_init_kvg_yaco,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
@@ -878,6 +1046,8 @@ static const struct prt_machine_data prt_imx6_cfg_vicut1q[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.init = prt_imx6_init_kvg_yaco,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
@@ -885,6 +1055,8 @@ static const struct prt_machine_data prt_imx6_cfg_vicut1q[] = {
 		.hw_rev = 1,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.init = prt_imx6_init_kvg_new,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
@@ -898,6 +1070,8 @@ static const struct prt_machine_data prt_imx6_cfg_vicutp[] = {
 		.hw_rev = 1,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.init = prt_imx6_init_kvg_new,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
@@ -911,6 +1085,8 @@ static const struct prt_machine_data prt_imx6_cfg_lanmcu[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER,
 	}, {
 		.hw_id = UINT_MAX
@@ -923,6 +1099,8 @@ static const struct prt_machine_data prt_imx6_cfg_plybas[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR | PRT_IMX6_USB_LONG_DELAY,
 	}, {
 		.hw_id = UINT_MAX
@@ -935,6 +1113,8 @@ static const struct prt_machine_data prt_imx6_cfg_plym2m[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR | PRT_IMX6_USB_LONG_DELAY,
 	}, {
 		.hw_id = UINT_MAX
@@ -947,8 +1127,10 @@ static const struct prt_machine_data prt_imx6_cfg_prti6g[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 1,
+		.sd_usdhc = 0,
 		.init = prt_imx6_init_prti6g,
-		.flags = PRT_IMX6_BOOTSRC_EMMC,
+		.flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER,
 	}, {
 		.hw_id = UINT_MAX
 	},
@@ -960,12 +1142,16 @@ static const struct prt_machine_data prt_imx6_cfg_prti6q[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 2,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
 		.hw_id = HW_TYPE_PRTI6Q,
 		.hw_rev = 1,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
 		.hw_id = UINT_MAX
@@ -978,6 +1164,8 @@ static const struct prt_machine_data prt_imx6_cfg_prtmvt[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
 		.hw_id = UINT_MAX
@@ -990,6 +1178,8 @@ static const struct prt_machine_data prt_imx6_cfg_prtrvt[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_SPI_NOR,
 	}, {
 		.hw_id = UINT_MAX
@@ -1002,7 +1192,11 @@ static const struct prt_machine_data prt_imx6_cfg_prtvt7[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
-		.flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
+		.init = prt_imx6_init_prtvt7,
+		.flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER |
+			PRT_IMX6_USB_LONG_DELAY,
 	}, {
 		.hw_id = UINT_MAX
 	},
@@ -1014,6 +1208,8 @@ static const struct prt_machine_data prt_imx6_cfg_prtwd2[] = {
 		.hw_rev = 0,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
 		.flags = PRT_IMX6_BOOTSRC_EMMC,
 	}, {
 		.hw_id = UINT_MAX
@@ -1026,19 +1222,44 @@ static const struct prt_machine_data prt_imx6_cfg_prtwd3[] = {
 		.hw_rev = 2,
 		.i2c_addr = 0x51,
 		.i2c_adapter = 0,
+		.emmc_usdhc = 2,
+		.sd_usdhc = 0,
+		.init = prt_imx6_init_prtwd3,
 		.flags = PRT_IMX6_BOOTSRC_EMMC,
 	}, {
 		.hw_id = UINT_MAX
 	},
 };
 
+static const struct prt_machine_data prt_imx6_cfg_jozacp[] = {
+	{
+		.hw_id = HW_TYPE_JOZACP,
+		.hw_rev = 1,
+		.i2c_addr = 0x51,
+		.i2c_adapter = 0,
+		.emmc_usdhc = 0,
+		.sd_usdhc = 2,
+		.flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER,
+	}, {
+		.hw_id = HW_TYPE_JOZACPP,
+		.hw_rev = 1,
+		.i2c_addr = 0x51,
+		.i2c_adapter = 0,
+		.emmc_usdhc = 0,
+		.sd_usdhc = 2,
+		.flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER,
+	}, {
+		.hw_id = UINT_MAX
+	},
+};
+
 static const struct of_device_id prt_imx6_of_match[] = {
 	{ .compatible = "alt,alti6p", .data = &prt_imx6_cfg_alti6p },
 	{ .compatible = "kvg,victgo", .data = &prt_imx6_cfg_victgo },
 	{ .compatible = "kvg,vicut1", .data = &prt_imx6_cfg_vicut1 },
 	{ .compatible = "kvg,vicut1q", .data = &prt_imx6_cfg_vicut1q },
 	{ .compatible = "kvg,vicutp", .data = &prt_imx6_cfg_vicutp },
-	{ .compatible = "lan,lanmcu", .data = &prt_imx6_cfg_lanmcu },
+	{ .compatible = "vdl,lanmcu", .data = &prt_imx6_cfg_lanmcu },
 	{ .compatible = "ply,plybas", .data = &prt_imx6_cfg_plybas },
 	{ .compatible = "ply,plym2m", .data = &prt_imx6_cfg_plym2m },
 	{ .compatible = "prt,prti6g", .data = &prt_imx6_cfg_prti6g },
@@ -1048,10 +1269,12 @@ static const struct of_device_id prt_imx6_of_match[] = {
 	{ .compatible = "prt,prtvt7", .data = &prt_imx6_cfg_prtvt7 },
 	{ .compatible = "prt,prtwd2", .data = &prt_imx6_cfg_prtwd2 },
 	{ .compatible = "prt,prtwd3", .data = &prt_imx6_cfg_prtwd3 },
+	{ .compatible = "joz,jozacp", .data = &prt_imx6_cfg_jozacp },
 	{ /* sentinel */ },
 };
+BAREBOX_DEEP_PROBE_ENABLE(prt_imx6_of_match);
 
-static struct driver_d prt_imx6_board_driver = {
+static struct driver prt_imx6_board_driver = {
 	.name = "board-protonic-imx6",
 	.probe = prt_imx6_probe,
 	.of_compatible = DRV_OF_COMPAT(prt_imx6_of_match),
diff --git a/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg b/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg
index 65bd1bc3c6..5bcd6c5f3c 100644
--- a/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg
+++ b/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 /*
  * Timing configuration:
  *
diff --git a/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg
index c778391d75..4e71e493ae 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
diff --git a/arch/arm/boards/protonic-imx6/flash-header-jozacp.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-jozacp.imxcfg
new file mode 100644
index 0000000000..472767611d
--- /dev/null
+++ b/arch/arm/boards/protonic-imx6/flash-header-jozacp.imxcfg
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+soc imx6
+loadaddr 0x80000000
+ivtofs 0x400
+
+#include "ddr3-defines.imxcfg"
+#include "padsetup-ul.imxcfg"
+
+/* Set Read data delay 3 delay units for all bits */
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+
+/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */
+wm 32 0x021b0018 0x00011740
+
+/* CSCR: Configuration mode */
+wm 32 0x021b001c 0x00008000
+
+wm 32 0x021b000c MDCFG0_2G_400MHZ
+wm 32 0x021b0010 MDCFG1_400MHZ
+wm 32 0x021b0014 MDCFG2_400MHZ
+
+/* MDRWD */
+wm 32 0x021b002c 0x000026d2
+
+wm 32 0x021b0030 MDOR_2G_400MHZ
+wm 32 0x021b0008 MDOTC_400MHZ
+wm 32 0x021b0004 MDPDC_400MHZ
+wm 32 0x021b0040 0x00000047	/* MDASP_512MIB */
+wm 32 0x021b0000 MDCTL_2G_16BIT
+
+/* DDR3 MR config */
+wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120
+
+/*
+ * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest).
+ */
+wm 32 0x021b001c 0x00008033
+
+wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40
+wm 32 0x021b001c DDR3_MR0_400MHZ
+
+/*
+ * ZQ calibration, n = 0x10 (Precharge all):
+ * Bit 10 = 1:  Start ZQ calibration
+ * REGISTER: 0x04008040
+ */
+wm 32 0x021b001c 0x04008040
+
+/* MPZQHWCTRL */
+wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
+
+wm 32 0x021b0020 MDREF_64KHZ
+
+wm 32 0x021b0818 0x00000117	/* MPODTCTRL_ODT_120 */
+
+wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ
+
+/* MPRDDLCTL, MPWRDLCTL */
+wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */
+wm 32 0x021b0850 0x40404040 /* For now set all to 50%. */
+
+/* MPWLDECTRL0 */
+wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */
+
+/* MPMUR0 */
+wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */
+
+/* MDSCR */
+wm 32 0x021b001c 0x00000000 /* Disable configuration req */
+
+/* MAPSR */
+wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now  */
+
+/* Enable all clocks */
+wm 32 0x020c4068 0xffffffff
+wm 32 0x020c406c 0xffffffff
+wm 32 0x020c4070 0xffffffff
+wm 32 0x020c4074 0xffffffff
+wm 32 0x020c4078 0xffffffff
+wm 32 0x020c407c 0xffffffff
+wm 32 0x020c4080 0xffffffff
diff --git a/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg
index b08e149834..7deaaa9b7b 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -59,7 +61,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg
index dbbb9818b6..c9c9d076f5 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -61,7 +63,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg
index dbbb9818b6..71df95b968 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -61,7 +63,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg
index ec9fb84108..472767611d 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x80000000
 ivtofs 0x400
diff --git a/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg
index 029edc248a..deced6901b 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -63,7 +65,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg
index 1131174f70..58530910fc 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -61,7 +63,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg
index dbbb9818b6..c9c9d076f5 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -61,7 +63,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg
index 019696295d..5073458a03 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -59,7 +61,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg
index 5f847c004d..035b5f1315 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg
index 054043cc80..be2b9883a8 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
diff --git a/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg
index d3de7b6aab..e3f0f0a19a 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg
index 54f655c4c2..a879229923 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -61,7 +63,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg
index f7e75b47bf..8e41a410df 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -64,7 +66,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg
index e218279239..54a86a0008 100644
--- a/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg
+++ b/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x10000000
 ivtofs 0x400
@@ -124,7 +126,7 @@ wm 32 0x021b001c 0x04008040
 
 /* MPZQHWCTRL */
 wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3  force calibration */
-wm 32 0x021b4800 0xa1390003 
+wm 32 0x021b4800 0xa1390003
 
 wm 32 0x021b0020 MDREF_64KHZ
 
diff --git a/arch/arm/boards/protonic-imx6/lowlevel.c b/arch/arm/boards/protonic-imx6/lowlevel.c
index f5784cc6b1..38e65037e6 100644
--- a/arch/arm/boards/protonic-imx6/lowlevel.c
+++ b/arch/arm/boards/protonic-imx6/lowlevel.c
@@ -6,8 +6,8 @@
 
 #include <asm/barebox-arm.h>
 #include <common.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 
 extern char __dtb_z_imx6q_prti6q_start[];
 extern char __dtb_z_imx6q_prtwd2_start[];
@@ -24,6 +24,7 @@ extern char __dtb_z_imx6dl_vicut1_start[];
 extern char __dtb_z_imx6qp_prtwd3_start[];
 extern char __dtb_z_imx6qp_vicutp_start[];
 extern char __dtb_z_imx6ul_prti6g_start[];
+extern char __dtb_z_imx6ull_jozacp_start[];
 
 ENTRY_FUNCTION(start_imx6q_prti6q, r0, r1, r2)
 {
@@ -189,3 +190,22 @@ ENTRY_FUNCTION(start_imx6ul_prti6g, r0, r1, r2)
 
 	imx6ul_barebox_entry(fdt);
 }
+
+ENTRY_FUNCTION(start_imx6ull_jozacp, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6ul_cpu_lowlevel_init();
+
+	/* Disconnect USDHC2 from SD card */
+	writel(0x5, 0x020e0178);
+	writel(0x5, 0x020e017c);
+	writel(0x5, 0x020e0180);
+	writel(0x5, 0x020e0184);
+	writel(0x5, 0x020e0188);
+	writel(0x5, 0x020e018c);
+
+	fdt = __dtb_z_imx6ull_jozacp_start + get_runtime_offset();
+
+	imx6ul_barebox_entry(fdt);
+}
diff --git a/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg b/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg
index 29c42cc697..b54b9542bd 100644
--- a/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg
+++ b/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 /*
  * Timing configuration:
  *
diff --git a/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg
index f60d37f63e..380ce8863c 100644
--- a/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg
+++ b/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
  * Some defines for PAD setup:
diff --git a/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg
index f5fa3e8d28..c58a481e13 100644
--- a/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg
+++ b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
  * Some defines for PAD setup:
diff --git a/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg
index e36601942d..9cdc9ac9a3 100644
--- a/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg
+++ b/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
  * Some defines for PAD setup:
diff --git a/arch/arm/boards/protonic-imx8m/Makefile b/arch/arm/boards/protonic-imx8m/Makefile
new file mode 100644
index 0000000000..18da0f5a44
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel-prt8mm.o lpddr4-timing-prt8mm.o
+bbenv-y += defaultenv-prt8m
diff --git a/arch/arm/boards/protonic-imx8m/board.c b/arch/arm/boards/protonic-imx8m/board.c
new file mode 100644
index 0000000000..d4bacbc6f0
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/board.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2020 David Jander, Protonic Holland
+
+#include <bootsource.h>
+#include <common.h>
+#include <envfs.h>
+#include <environment.h>
+#include <i2c/i2c.h>
+#include <init.h>
+#include <mach/imx/bbu.h>
+
+static int prt_prt8mm_init_power(void)
+{
+	struct i2c_adapter *adapter = NULL;
+	struct i2c_client client;
+	int ret;
+	char buf[2];
+
+	client.addr = 0x60;
+	adapter = i2c_get_adapter(1);
+	if (!adapter) {
+		printf("i2c bus not found\n");
+		return -ENODEV;
+	}
+	client.adapter = adapter;
+
+	buf[0] = 0xe3;
+	ret = i2c_write_reg(&client, 0x00, buf, 1); // VSEL0 = 0.95V, force PWM
+	if (ret < 0) {
+		printf("i2c write error\n");
+		return -ENODEV;
+	}
+	buf[0] = 0xe0;
+	ret = i2c_write_reg(&client, 0x01, buf, 1); // VSEL1 = 0.92V, force PWM
+	if (ret < 0) {
+		printf("i2c write error\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static int prt_prt8mm_probe(struct device *dev)
+{
+	int emmc_bbu_flag = 0;
+	int sd_bbu_flag = 0;
+
+	prt_prt8mm_init_power();
+
+	barebox_set_hostname("prt8mm");
+
+	if (bootsource_get() == BOOTSOURCE_MMC) {
+		if (bootsource_get_instance() == 2) {
+			of_device_enable_path("/chosen/environment-emmc");
+			emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+		} else {
+			of_device_enable_path("/chosen/environment-sd");
+			sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+		}
+	} else {
+		of_device_enable_path("/chosen/environment-emmc");
+		emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox",
+						sd_bbu_flag);
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2",
+						    emmc_bbu_flag);
+
+	defaultenv_append_directory(defaultenv_prt8m);
+
+	return 0;
+}
+
+static const struct of_device_id prt_imx8mm_of_match[] = {
+	{ .compatible = "prt,prt8mm", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, prt_imx8mm_of_match);
+
+static struct driver prt_prt8mm_board_driver = {
+	.name = "board-protonic-imx8mm",
+	.probe = prt_prt8mm_probe,
+	.of_compatible = DRV_OF_COMPAT(prt_imx8mm_of_match),
+};
+device_platform_driver(prt_prt8mm_board_driver);
diff --git a/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default
new file mode 100644
index 0000000000..ca8bef306d
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+if [ "$bootsource_instance" = "2" ]; then
+	boot mmc2
+else
+	boot mmc3
+fi
diff --git a/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover
new file mode 100644
index 0000000000..18f2446387
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+# PRT8M doesn't have a ETH port, but may have USB network attached
+usb
diff --git a/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default
new file mode 100644
index 0000000000..ba8938923a
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default
@@ -0,0 +1 @@
+prt8mm-default
diff --git a/arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg b/arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg
new file mode 100644
index 0000000000..8aff991618
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mm
+
+loadaddr 0x007e1000
+max_load_size 0x3f000
+ivtofs 0x400
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c b/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c
new file mode 100644
index 0000000000..711316ae4b
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <asm/barebox-arm.h>
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <firmware.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/imx8mm-regs.h>
+#include <mach/imx/iomux-mx8mm.h>
+#include <mach/imx/xload.h>
+#include <soc/fsl/fsl_udc.h>
+#include <soc/imx8m/ddr.h>
+
+extern char __dtb_z_imx8mm_prt8mm_start[];
+
+#define UART_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
+
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART4_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mm_setup_pad(IMX8MM_PAD_UART4_TXD_UART4_TX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+
+	putc_ll('>');
+}
+
+extern struct dram_timing_info prt8mm_dram_timing;
+
+static void start_atf(void)
+{
+	/*
+	 * If we are in EL3 we are running for the first time and need to
+	 * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
+	 * to DRAM in EL2.
+	 */
+	if (current_el() != 3)
+		return;
+
+	imx8mm_early_clock_init();
+
+	imx8mm_ddr_init(&prt8mm_dram_timing, DRAM_TYPE_LPDDR4);
+
+	imx8mm_load_and_start_image_via_tfa();
+}
+
+/*
+ * Power-on execution flow of start_prt_prt8mm() might not be
+ * obvious for a very first read, so here's, hopefully helpful,
+ * summary:
+ *
+ * 1. MaskROM uploads PBL into OCRAM and that's where this function is
+ *    executed for the first time. At entry the exception level is EL3.
+ *
+ * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL
+ *    part is copied from OCRAM to the TF-A return address in DRAM.
+ *
+ * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us
+ *    from EL3 to EL2.
+ *
+ * 4. Standard barebox boot flow continues
+ */
+static __noreturn noinline void prt_prt8mm_start(void)
+{
+	setup_uart();
+
+	start_atf();
+
+	/*
+	 * Standard entry we hit once we initialized both DDR and ATF
+	 */
+	imx8mm_barebox_entry(__dtb_z_imx8mm_prt8mm_start);
+}
+
+ENTRY_FUNCTION(start_prt_prt8mm, r0, r1, r2)
+{
+	imx8mm_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	prt_prt8mm_start();
+}
diff --git a/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c
new file mode 100644
index 0000000000..6fea2f0625
--- /dev/null
+++ b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c
@@ -0,0 +1,1269 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+#define DDR_ONE_RANK
+#include <soc/imx8m/lpddr4_define.h>
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/* Start to config, default 3200mbps */
+	{ DDRC_DBG1(0),	0x00000001 },
+	{ DDRC_PWRCTL(0), 0x00000001 },
+	{ DDRC_MSTR(0),	0xa1080020 },
+	{ DDRC_RFSHTMG(0), 0x005b0087 },
+	{ DDRC_INIT0(0), 0xc00305ba },
+	{ DDRC_INIT1(0), 0x00940000 },
+	{ DDRC_INIT3(0), 0x00D4002D },
+	{ DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+	{ DDRC_INIT6(0), 0x0066004d },
+	{ DDRC_INIT7(0), 0x0016004d },
+
+	{ DDRC_DRAMTMG0(0), 0x191e1920 },
+	{ DDRC_DRAMTMG1(0), 0x00060630 },
+	{ DDRC_DRAMTMG3(0), 0x00B0B000 },
+	{ DDRC_DRAMTMG4(0), 0x0e04080e },
+	{ DDRC_DRAMTMG5(0), 0x02040C0C },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x00000401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0c100002 },
+	{ DDRC_DRAMTMG14(0), 0x0000008d },
+	{ DDRC_DRAMTMG17(0), 0x0090004b },
+
+	//{ DDRC_DERATEEN(0), 0x00000203 },
+	//{ DDRC_DERATEINT(0), 0x0003a980 },
+
+	{ DDRC_ZQCTL0(0), 0x02ee0017 },
+	{ DDRC_ZQCTL1(0), 0x02605b8e },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+
+	{ DDRC_DFITMG0(0), 0x0497820A },
+	{ DDRC_DFITMG2(0), 0x0000170A },
+	{ DDRC_DRAMTMG2(0), 0x070e1617 },
+	{ DDRC_DBICTL(0), 0x00000001 },
+
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xE0400018 },
+	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000011 },
+
+	{ DDRC_DFIPHYMSTR(0), 0x00000000 },
+	{ DDRC_RANKCTL(0), 0x00000c99 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), 0x0000001f },
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	{ DDRC_ADDRMAP2(0), 0x00000000 },
+	{ DDRC_ADDRMAP3(0), 0x00000000 },
+	{ DDRC_ADDRMAP4(0), 0x00001f1f },
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	{ DDRC_ADDRMAP6(0), 0x0F070707 },
+	{ DDRC_ADDRMAP7(0), 0x00000f0f },
+
+	/* performance setting */
+	{ DDRC_SCHED(0), 0x29001701 },
+	{ DDRC_SCHED1(0), 0x0000002c },
+	{ DDRC_PERFHPR1(0), 0x04000030 },
+	{ DDRC_PERFLPR1(0), 0x900093e7 },
+	{ DDRC_PERFWR1(0), 0x02005574 },
+	{ DDRC_PCCFG(0), 0x00000111 },
+	{ DDRC_PCFGW_0(0), 0x000072ff },
+	{ DDRC_PCFGQOS0_0(0), 0x02100e07 },
+	{ DDRC_PCFGQOS1_0(0), 0x00620096 },
+	{ DDRC_PCFGWQOS0_0(0), 0x01100e07 },
+	{ DDRC_PCFGWQOS1_0(0), 0x00c8012c },
+
+	/* frequency P1&P2 */
+	/* Frequency 1: 400MHz */
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0c080609 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x0003040d },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x00000301 },
+	//{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
+	//{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000026 },
+	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x00280014 },
+	//{ DDRC_FREQ1_DERATEEN(0), 0x00000001 },
+	{ DDRC_FREQ1_DERATEINT(0), 0x00007a00 },
+	//{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
+	//{ DDRC_FREQ1_ZQCTL0(0), 0x00c80006 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
+	//{ DDRC_FREQ1_DFITMG1(0), 0x00080303 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x00000502 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x00180024 },
+	{ DDRC_FREQ1_INIT3(0), 0x00940009 },
+	{ DDRC_FREQ1_INIT4(0), 0x00310000 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004d },
+	{ DDRC_FREQ1_INIT7(0), 0x0016004d },
+	// { DDRC_FREQ1_RANKCTL(0), 0x00000c99 },
+
+	/* Frequency 2: 100MHz */
+	{ DDRC_FREQ2_DRAMTMG0(0), 0x0a020103 },
+	{ DDRC_FREQ2_DRAMTMG1(0), 0x00030405 },
+	{ DDRC_FREQ2_DRAMTMG2(0), 0x0203060b },
+	{ DDRC_FREQ2_DRAMTMG3(0), 0x00505000 },
+	{ DDRC_FREQ2_DRAMTMG4(0), 0x02040202 },
+	{ DDRC_FREQ2_DRAMTMG5(0), 0x02030202 },
+	{ DDRC_FREQ2_DRAMTMG6(0), 0x01010004 },
+	{ DDRC_FREQ2_DRAMTMG7(0), 0x00000301 },
+	//{ DDRC_FREQ2_DRAMTMG12(0), 0x00020300 },
+	//{ DDRC_FREQ2_DRAMTMG13(0), 0x0a100002 },
+	{ DDRC_FREQ2_DRAMTMG14(0), 0x0000000a },
+	{ DDRC_FREQ2_DRAMTMG17(0), 0x000a0005 },
+	//{ DDRC_FREQ2_DERATEEN(0), 0x00000001 },
+	{ DDRC_FREQ2_DERATEINT(0), 0x00003e80 },
+	//{ DDRC_FREQ2_RFSHCTL0(0), 0x0020d040 },
+	//{ DDRC_FREQ2_ZQCTL0(0), 0x00320004 },
+	{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+	//{ DDRC_FREQ2_DFITMG1(0), 0x00080303 },
+	{ DDRC_FREQ2_DFITMG2(0), 0x00000100 },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x00060009 },
+	{ DDRC_FREQ2_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ2_INIT4(0), 0x00310008 },
+	//{ DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+	{ DDRC_FREQ2_INIT6(0), 0x0066004d },
+	{ DDRC_FREQ2_INIT7(0), 0x0016004d },
+	// { DDRC_FREQ2_RANKCTL(0), 0x00000c99 },
+
+	/* boot start point */
+	{ DDRC_MSTR2(0), 0x0 }, //DDRC_MSTR2
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+
+	{ 0x20024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x120024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x220024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+
+	{ 0x10049, 0xfbe },
+	{ 0x10149, 0xfbe },
+	{ 0x11049, 0xfbe },
+	{ 0x11149, 0xfbe },
+	{ 0x12049, 0xfbe },
+	{ 0x12149, 0xfbe },
+	{ 0x13049, 0xfbe },
+	{ 0x13149, 0xfbe },
+
+	{ 0x110049, 0xfbe },
+	{ 0x110149, 0xfbe },
+	{ 0x111049, 0xfbe },
+	{ 0x111149, 0xfbe },
+	{ 0x112049, 0xfbe },
+	{ 0x112149, 0xfbe },
+	{ 0x113049, 0xfbe },
+	{ 0x113149, 0xfbe },
+
+	{ 0x210049, 0xfbe },
+	{ 0x210149, 0xfbe },
+	{ 0x211049, 0xfbe },
+	{ 0x211149, 0xfbe },
+	{ 0x212049, 0xfbe },
+	{ 0x212149, 0xfbe },
+	{ 0x213049, 0xfbe },
+	{ 0x213149, 0xfbe },
+
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+
+	{ 0x200b2, 0x1d4 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+
+	{ 0x20025, 0x0 },
+	{ 0x2002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x12002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x22002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200c7, 0x21 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 }, // 3000
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 }, // LPDDR4_HDT_CTL_3200_1D
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x5d },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	}, {
+		/* P1 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+	}, {
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	}, {
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info prt8mm_dram_timing = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+};
diff --git a/arch/arm/boards/protonic-stm32mp1/Makefile b/arch/arm/boards/protonic-stm32mp1/Makefile
new file mode 100644
index 0000000000..5678718188
--- /dev/null
+++ b/arch/arm/boards/protonic-stm32mp1/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/protonic-stm32mp1/board.c b/arch/arm/boards/protonic-stm32mp1/board.c
new file mode 100644
index 0000000000..68297debab
--- /dev/null
+++ b/arch/arm/boards/protonic-stm32mp1/board.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2021 David Jander, Protonic Holland
+// SPDX-FileCopyrightText: 2021 Oleksij Rempel, Pengutronix
+
+#include <bootsource.h>
+#include <common.h>
+#include <init.h>
+#include <mach/stm32mp/bbu.h>
+#include <of_device.h>
+#include <deep-probe.h>
+
+/* board specific flags */
+#define PRT_STM32_BOOTSRC_SD		BIT(2)
+#define PRT_STM32_BOOTSRC_EMMC		BIT(1)
+#define PRT_STM32_BOOTSRC_SPI_NOR	BIT(0)
+
+struct prt_stm32_machine_data {
+	u32 flags;
+};
+
+struct prt_stm32_boot_dev {
+	char *name;
+	char *env;
+	char *dev;
+	int flags;
+	int boot_idx;
+	enum bootsource boot_src;
+};
+
+static const struct prt_stm32_boot_dev prt_stm32_boot_devs[] = {
+	{
+		.name = "emmc",
+		.env = "/chosen/environment-emmc",
+		.dev = "/dev/mmc1.ssbl",
+		.flags = PRT_STM32_BOOTSRC_EMMC,
+		.boot_src = BOOTSOURCE_MMC,
+		.boot_idx = 1,
+	}, {
+		.name = "qspi",
+		.env = "/chosen/environment-qspi",
+		.dev = "/dev/flash.ssbl",
+		.flags = PRT_STM32_BOOTSRC_SPI_NOR,
+		.boot_src = BOOTSOURCE_SPI_NOR,
+		.boot_idx = -1,
+	}, {
+		/* SD is optional boot source and should be last device in the
+		 * list. */
+		.name = "sd",
+		.env = "/chosen/environment-sd",
+		.dev = "/dev/mmc0.ssbl",
+		.flags = PRT_STM32_BOOTSRC_SD,
+		.boot_src = BOOTSOURCE_MMC,
+		.boot_idx = 0,
+	},
+};
+
+static int prt_stm32_probe(struct device *dev)
+{
+	const struct prt_stm32_machine_data *dcfg;
+	char *env_path_back = NULL, *env_path = NULL;
+	int ret, i;
+
+	dcfg = of_device_get_match_data(dev);
+	if (!dcfg) {
+		ret = -EINVAL;
+		goto exit_get_dcfg;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(prt_stm32_boot_devs); i++) {
+		const struct prt_stm32_boot_dev *bd = &prt_stm32_boot_devs[i];
+		int bbu_flags = 0;
+
+		/* skip not supported boot sources */
+		if (!(bd->flags & dcfg->flags))
+			continue;
+
+		/* first device is build-in device */
+		if (!env_path_back)
+			env_path_back = bd->env;
+
+		if (bd->boot_src == bootsource_get() && (bd->boot_idx == -1 ||
+		    bd->boot_idx  == bootsource_get_instance())) {
+			bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+			env_path = bd->env;
+		}
+
+		ret = stm32mp_bbu_mmc_register_handler(bd->name, bd->dev,
+						       bbu_flags);
+		if (ret < 0)
+			dev_warn(dev, "Failed to enable %s bbu (%pe)\n",
+				 bd->name, ERR_PTR(ret));
+	}
+
+	if (!env_path)
+		env_path = env_path_back;
+	ret = of_device_enable_path(env_path);
+	if (ret < 0)
+		dev_warn(dev, "Failed to enable environment partition '%s' (%pe)\n",
+			 env_path, ERR_PTR(ret));
+
+	return 0;
+
+exit_get_dcfg:
+	dev_err(dev, "Failed to get dcfg: %pe\n", ERR_PTR(ret));
+	return ret;
+}
+
+static const struct prt_stm32_machine_data prt_stm32_prtt1a = {
+	.flags = PRT_STM32_BOOTSRC_SD | PRT_STM32_BOOTSRC_SPI_NOR,
+};
+
+static const struct prt_stm32_machine_data prt_stm32_prtt1c = {
+	.flags = PRT_STM32_BOOTSRC_SD | PRT_STM32_BOOTSRC_EMMC,
+};
+
+static const struct of_device_id prt_stm32_of_match[] = {
+	{ .compatible = "prt,prtt1a", .data = &prt_stm32_prtt1a },
+	{ .compatible = "prt,prtt1c", .data = &prt_stm32_prtt1c },
+	{ .compatible = "prt,prtt1s", .data = &prt_stm32_prtt1a },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(prt_stm32_of_match);
+
+static struct driver prt_stm32_board_driver = {
+	.name = "board-protonic-stm32",
+	.probe = prt_stm32_probe,
+	.of_compatible = prt_stm32_of_match,
+};
+postcore_platform_driver(prt_stm32_board_driver);
diff --git a/arch/arm/boards/protonic-stm32mp1/lowlevel.c b/arch/arm/boards/protonic-stm32mp1/lowlevel.c
new file mode 100644
index 0000000000..2fd7f8ba8b
--- /dev/null
+++ b/arch/arm/boards/protonic-stm32mp1/lowlevel.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2021 David Jander, Protonic Holland
+
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/stm32mp/entry.h>
+
+extern char __dtb_z_stm32mp151_prtt1a_start[];
+extern char __dtb_z_stm32mp151_prtt1c_start[];
+extern char __dtb_z_stm32mp151_prtt1s_start[];
+
+static void setup_uart(void)
+{
+	/* first stage has set up the UART, so nothing to do here */
+	putc_ll('>');
+}
+
+ENTRY_FUNCTION(start_prtt1a, r0, r1, r2)
+{
+	void *fdt;
+
+	stm32mp_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = __dtb_z_stm32mp151_prtt1a_start + get_runtime_offset();
+
+	stm32mp1_barebox_entry(fdt);
+}
+
+ENTRY_FUNCTION(start_prtt1c, r0, r1, r2)
+{
+	void *fdt;
+
+	stm32mp_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = __dtb_z_stm32mp151_prtt1c_start + get_runtime_offset();
+
+	stm32mp1_barebox_entry(fdt);
+}
+
+ENTRY_FUNCTION(start_prtt1s, r0, r1, r2)
+{
+	void *fdt;
+
+	stm32mp_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = __dtb_z_stm32mp151_prtt1s_start + get_runtime_offset();
+
+	stm32mp1_barebox_entry(fdt);
+}
diff --git a/arch/arm/boards/qemu-virt/.gitignore b/arch/arm/boards/qemu-virt/.gitignore
deleted file mode 100644
index 5d65b54bf1..0000000000
--- a/arch/arm/boards/qemu-virt/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-*.dtb*
diff --git a/arch/arm/boards/qemu-virt/Makefile b/arch/arm/boards/qemu-virt/Makefile
index 8451c7832d..ad283446ea 100644
--- a/arch/arm/boards/qemu-virt/Makefile
+++ b/arch/arm/boards/qemu-virt/Makefile
@@ -1,2 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
-obj-y += overlay-of-flash.dtb.o
diff --git a/arch/arm/boards/qemu-virt/board.c b/arch/arm/boards/qemu-virt/board.c
deleted file mode 100644
index d0a7e3da4f..0000000000
--- a/arch/arm/boards/qemu-virt/board.c
+++ /dev/null
@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2020 Pengutronix e.K.
- *
- */
-#include <common.h>
-#include <init.h>
-#include <of.h>
-#include <asm/system_info.h>
-#include <asm/barebox-arm.h>
-
-#ifdef CONFIG_64BIT
-#define MACHINE "virt64"
-#else
-#define MACHINE "virt"
-#endif
-
-extern char __dtb_overlay_of_flash_start[];
-
-static int replace_dtb(void) {
-	struct device_node *overlay;
-	void *fdt;
-	struct device_node *root;
-
-	fdt = barebox_arm_boot_dtb();
-	if (fdt)
-		pr_debug("using boarddata provided DTB\n");
-
-	if (!fdt) {
-		pr_debug("No DTB found\n");
-		return 0;
-	}
-
-	root = of_unflatten_dtb(fdt);
-
-	if (!of_device_is_compatible(root, "linux,dummy-virt")) {
-		of_delete_node(root);
-		return 0;
-	}
-
-	overlay = of_unflatten_dtb(__dtb_overlay_of_flash_start);
-	of_overlay_apply_tree(root, overlay);
-	barebox_register_of(root);
-
-	return 0;
-}
-
-pure_initcall(replace_dtb);
-
-static int virt_probe(struct device_d *dev)
-{
-	const char *hostname = MACHINE;
-
-	if (cpu_is_cortex_a7())
-		hostname = "virt-a7";
-	else if (cpu_is_cortex_a15())
-		hostname = "virt-a15";
-
-	barebox_set_model("ARM QEMU " MACHINE);
-	barebox_set_hostname(hostname);
-
-	return 0;
-}
-
-static const struct of_device_id virt_of_match[] = {
-	{ .compatible = "linux,dummy-virt" },
-	{ /* Sentinel */},
-};
-
-static struct driver_d virt_board_driver = {
-	.name = "board-qemu-virt",
-	.probe = virt_probe,
-	.of_compatible = virt_of_match,
-};
-
-postcore_platform_driver(virt_board_driver);
diff --git a/arch/arm/boards/qemu-virt/overlay-of-flash.dts b/arch/arm/boards/qemu-virt/overlay-of-flash.dts
deleted file mode 100644
index e00dc5d7e2..0000000000
--- a/arch/arm/boards/qemu-virt/overlay-of-flash.dts
+++ /dev/null
@@ -1,97 +0,0 @@
-/dts-v1/;
-/plugin/;
-/ {
-	fragment@0 {
-		target-path = "/flash@0";
-		__overlay__ {
-			partitions {
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				partition@0 {
-					label = "initramfs";
-					reg = <0x0 0x3c00000>;
-				};
-
-				environment_flash: partition@3c00000 {
-					label = "barebox-environment";
-					reg = <0x3c00000 0x200000>;
-				};
-
-				backend_state_flash: partition@3e00000 {
-					label = "barebox-state";
-					reg = <0x3e00000 0x200000>;
-				};
-			};
-		};
-	};
-	fragment@1 {
-		target-path="/";
-		__overlay__ {
-			chosen {
-				environment {
-					compatible = "barebox,environment";
-					device-path = "/flash@0/partitions/partition@3c00000";
-				};
-			};
-			aliases {
-				state = "/state";
-			};
-
-			state {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "barebox,state";
-				magic = <0x290cf8c6>;
-				backend-type = "raw";
-				backend = < &backend_state_flash >;
-				backend-stridesize = <0x200>;
-
-				bootstate {
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					system0 {
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						remaining_attempts@0 {
-							reg = <0x0 0x4>;
-							type = "uint32";
-							default = <3>;
-						};
-
-						priority@4 {
-							reg = <0x4 0x4>;
-							type = "uint32";
-							default = <20>;
-						};
-					};
-
-					system1 {
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						remaining_attempts@8 {
-							reg = <0x8 0x4>;
-							type = "uint32";
-							default = <3>;
-						};
-
-						priority@c {
-							reg = <0xc 0x4>;
-							type = "uint32";
-							default = <21>;
-						};
-					};
-
-					last_chosen@10 {
-						reg = <0x10 0x4>;
-						type = "uint32";
-					};
-				};
-			};
-		};
-	};
-};
diff --git a/arch/arm/boards/qil-a926x/Makefile b/arch/arm/boards/qil-a926x/Makefile
index 82e46b369f..bf5ed8b4f4 100644
--- a/arch/arm/boards/qil-a926x/Makefile
+++ b/arch/arm/boards/qil-a926x/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/qil-a926x/init.c b/arch/arm/boards/qil-a926x/init.c
index 63c7089d7d..988657b354 100644
--- a/arch/arm/boards/qil-a926x/init.c
+++ b/arch/arm/boards/qil-a926x/init.c
@@ -10,25 +10,24 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/clk.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
 #include <led.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
 
 static void qil_a9260_set_board_type(void)
 {
diff --git a/arch/arm/boards/qil-a926x/lowlevel.c b/arch/arm/boards/qil-a926x/lowlevel.c
index 7f52f824df..314980e84c 100644
--- a/arch/arm/boards/qil-a926x/lowlevel.c
+++ b/arch/arm/boards/qil-a926x/lowlevel.c
@@ -7,14 +7,23 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9260.h>
+#include <mach/at91/hardware.h>
 
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9260.h>
-#include <mach/hardware.h>
+AT91_ENTRY_FUNCTION(start_qil_a926x, r0, r1, r2)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_qil_a9g20, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/radxa-cm3/.gitignore b/arch/arm/boards/radxa-cm3/.gitignore
new file mode 100644
index 0000000000..f458f794b5
--- /dev/null
+++ b/arch/arm/boards/radxa-cm3/.gitignore
@@ -0,0 +1 @@
+sdram-init.bin
diff --git a/arch/arm/boards/radxa-cm3/Makefile b/arch/arm/boards/radxa-cm3/Makefile
new file mode 100644
index 0000000000..b37b6c870b
--- /dev/null
+++ b/arch/arm/boards/radxa-cm3/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/radxa-cm3/board.c b/arch/arm/boards/radxa-cm3/board.c
new file mode 100644
index 0000000000..14b6784179
--- /dev/null
+++ b/arch/arm/boards/radxa-cm3/board.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <mach/rockchip/bbu.h>
+
+struct cm3_model {
+	const char *name;
+	const char *shortname;
+};
+
+static int cm3_probe(struct device *dev)
+{
+	enum bootsource bootsource = bootsource_get();
+	int instance = bootsource_get_instance();
+	const struct cm3_model *model;
+
+	model = device_get_match_data(dev);
+
+	barebox_set_model(model->name);
+	barebox_set_hostname(model->shortname);
+
+	if (bootsource == BOOTSOURCE_MMC && instance == 1)
+		of_device_enable_path("/chosen/environment-sd");
+	else
+		of_device_enable_path("/chosen/environment-emmc");
+
+	rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT,
+				"/dev/mmc0");
+	rk3568_bbu_mmc_register("sd", 0, "/dev/mmc1");
+
+	return 0;
+}
+
+static const struct cm3_model cm3_io = {
+	.name = "Radxa CM3 on IO Board",
+	.shortname = "cm3-io",
+};
+
+static const struct of_device_id cm3_of_match[] = {
+	{
+		.compatible = "radxa,cm3-io",
+		.data = &cm3_io,
+	},
+	{ /* sentinel */ },
+};
+
+static struct driver cm3_io_board_driver = {
+	.name = "board-cm3-io",
+	.probe = cm3_probe,
+	.of_compatible = cm3_of_match,
+};
+coredevice_platform_driver(cm3_io_board_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(cm3_of_match);
diff --git a/arch/arm/boards/radxa-cm3/lowlevel.c b/arch/arm/boards/radxa-cm3/lowlevel.c
new file mode 100644
index 0000000000..e1b453f21f
--- /dev/null
+++ b/arch/arm/boards/radxa-cm3/lowlevel.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <common.h>
+#include <asm/barebox-arm.h>
+#include <mach/rockchip/hardware.h>
+#include <mach/rockchip/atf.h>
+#include <debug_ll.h>
+
+extern char __dtb_rk3566_cm3_io_start[];
+
+ENTRY_FUNCTION(start_radxa_cm3_io, r0, r1, r2)
+{
+	/*
+	 * Enable vccio4 1.8V and vccio6 1.8V
+	 * Needed for GMAC to work.
+	 * FIXME: This is done by the io-domain driver as well, but there
+	 * currently is no mechanism to make sure the driver gets probed
+	 * before its consumers. Remove this setup once this issue is
+	 * resolved.
+	 */
+	writel(RK_SETBITS(0x50), 0xfdc20140);
+
+	putc_ll('>');
+
+	if (current_el() == 3)
+		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
+	else
+		relocate_to_current_adr();
+
+	setup_c();
+
+	rk3568_barebox_entry(__dtb_rk3566_cm3_io_start);
+}
diff --git a/arch/arm/boards/radxa-rock/Makefile b/arch/arm/boards/radxa-rock/Makefile
index 79c8aec199..79d3969dcd 100644
--- a/arch/arm/boards/radxa-rock/Makefile
+++ b/arch/arm/boards/radxa-rock/Makefile
@@ -1,2 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-$(CONFIG_MACH_RADXA_ROCK) += board.o
 lwl-y += lowlevel.o
+bbenv-y += defaultenv-radxa-rock
diff --git a/arch/arm/boards/radxa-rock/board.c b/arch/arm/boards/radxa-rock/board.c
index 5c87f64897..1c93d6e522 100644
--- a/arch/arm/boards/radxa-rock/board.c
+++ b/arch/arm/boards/radxa-rock/board.c
@@ -4,9 +4,10 @@
 #include <common.h>
 #include <init.h>
 #include <io.h>
+#include <envfs.h>
 #include <i2c/i2c.h>
 #include <i2c/i2c-gpio.h>
-#include <mach/rk3188-regs.h>
+#include <mach/rockchip/rk3188-regs.h>
 #include <mfd/act8846.h>
 #include <asm/armlinux.h>
 
@@ -51,6 +52,8 @@ static int devices_init(void)
 	writel((RK_SOC_CON0_REMAP << 16) | RK_SOC_CON0_REMAP,
 	    RK_GRF_BASE + RK_GRF_SOC_CON0);
 
+	defaultenv_append_directory(defaultenv_radxa_rock);
+
 	return 0;
 }
 device_initcall(devices_init);
diff --git a/arch/arm/boards/radxa-rock/env/boot/mshc1 b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/boot/mshc1
index c24a88edc5..c24a88edc5 100644
--- a/arch/arm/boards/radxa-rock/env/boot/mshc1
+++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/boot/mshc1
diff --git a/arch/arm/boards/radxa-rock/env/boot/mshc1-old b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/boot/mshc1-old
index 2e43a3aafe..2e43a3aafe 100644
--- a/arch/arm/boards/radxa-rock/env/boot/mshc1-old
+++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/boot/mshc1-old
diff --git a/arch/arm/boards/radxa-rock/env/init/bootsource b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/init/bootsource
index 4e8299b8dd..4e8299b8dd 100644
--- a/arch/arm/boards/radxa-rock/env/init/bootsource
+++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/init/bootsource
diff --git a/arch/arm/boards/radxa-rock/env/nv/hostname b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/nv/hostname
index 16523aca12..16523aca12 100644
--- a/arch/arm/boards/radxa-rock/env/nv/hostname
+++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/nv/hostname
diff --git a/arch/arm/boards/radxa-rock/env/nv/linux.bootargs.console b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/nv/linux.bootargs.console
index 37a03fd430..37a03fd430 100644
--- a/arch/arm/boards/radxa-rock/env/nv/linux.bootargs.console
+++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/nv/linux.bootargs.console
diff --git a/arch/arm/boards/radxa-rock3/.gitignore b/arch/arm/boards/radxa-rock3/.gitignore
new file mode 100644
index 0000000000..f458f794b5
--- /dev/null
+++ b/arch/arm/boards/radxa-rock3/.gitignore
@@ -0,0 +1 @@
+sdram-init.bin
diff --git a/arch/arm/boards/radxa-rock3/Makefile b/arch/arm/boards/radxa-rock3/Makefile
new file mode 100644
index 0000000000..b37b6c870b
--- /dev/null
+++ b/arch/arm/boards/radxa-rock3/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/radxa-rock3/board.c b/arch/arm/boards/radxa-rock3/board.c
new file mode 100644
index 0000000000..0d425e2667
--- /dev/null
+++ b/arch/arm/boards/radxa-rock3/board.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <mach/rockchip/bbu.h>
+
+struct rock3_model {
+	const char *name;
+	const char *shortname;
+};
+
+static int rock3_probe(struct device *dev)
+{
+	enum bootsource bootsource = bootsource_get();
+	int instance = bootsource_get_instance();
+	const struct rock3_model *model;
+
+	model = device_get_match_data(dev);
+
+	barebox_set_model(model->name);
+	barebox_set_hostname(model->shortname);
+
+	if (bootsource == BOOTSOURCE_MMC && instance == 1)
+		of_device_enable_path("/chosen/environment-sd");
+	else
+		of_device_enable_path("/chosen/environment-emmc");
+
+	rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/mmc0");
+	rk3568_bbu_mmc_register("sd", 0, "/dev/mmc1");
+
+	return 0;
+}
+
+static const struct rock3_model rock3a = {
+	.name = "Radxa ROCK3 Model A",
+	.shortname = "rock3a",
+};
+
+static const struct of_device_id rock3_of_match[] = {
+	{
+		.compatible = "radxa,rock3a",
+		.data = &rock3a,
+	},
+	{ /* sentinel */ },
+};
+
+static struct driver rock3_board_driver = {
+	.name = "board-rock3",
+	.probe = rock3_probe,
+	.of_compatible = rock3_of_match,
+};
+coredevice_platform_driver(rock3_board_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(rock3_of_match);
diff --git a/arch/arm/boards/radxa-rock3/lowlevel.c b/arch/arm/boards/radxa-rock3/lowlevel.c
new file mode 100644
index 0000000000..ec407404b9
--- /dev/null
+++ b/arch/arm/boards/radxa-rock3/lowlevel.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <asm/barebox-arm.h>
+#include <mach/rockchip/hardware.h>
+#include <mach/rockchip/atf.h>
+#include <debug_ll.h>
+
+extern char __dtb_rk3568_rock_3a_start[];
+
+ENTRY_FUNCTION(start_rock3a, r0, r1, r2)
+{
+	/*
+	 * Enable vccio4 1.8V and vccio6 1.8V
+	 * Needed for GMAC to work.
+	 * FIXME: This is done by the io-domain driver as well, but there
+	 * currently is no mechanism to make sure the driver gets probed
+	 * before its consumers. Remove this setup once this issue is
+	 * resolved.
+	 */
+	writel(RK_SETBITS(0x50), 0xfdc20140);
+
+	putc_ll('>');
+
+	if (current_el() == 3)
+		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
+	else
+		relocate_to_current_adr();
+
+	setup_c();
+
+	rk3568_barebox_entry(__dtb_rk3568_rock_3a_start);
+}
diff --git a/arch/arm/boards/radxa-rock5/.gitignore b/arch/arm/boards/radxa-rock5/.gitignore
new file mode 100644
index 0000000000..f458f794b5
--- /dev/null
+++ b/arch/arm/boards/radxa-rock5/.gitignore
@@ -0,0 +1 @@
+sdram-init.bin
diff --git a/arch/arm/boards/radxa-rock5/Makefile b/arch/arm/boards/radxa-rock5/Makefile
new file mode 100644
index 0000000000..b37b6c870b
--- /dev/null
+++ b/arch/arm/boards/radxa-rock5/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/radxa-rock5/board.c b/arch/arm/boards/radxa-rock5/board.c
new file mode 100644
index 0000000000..6ea6ffeaaf
--- /dev/null
+++ b/arch/arm/boards/radxa-rock5/board.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <mach/rockchip/bbu.h>
+
+struct rock5_model {
+	const char *name;
+	const char *shortname;
+};
+
+static int rock5_probe(struct device *dev)
+{
+	enum bootsource bootsource = bootsource_get();
+	int instance = bootsource_get_instance();
+	const struct rock5_model *model;
+
+	model = device_get_match_data(dev);
+
+	if (bootsource == BOOTSOURCE_MMC && instance == 1)
+		of_device_enable_path("/chosen/environment-sd");
+	else
+		of_device_enable_path("/chosen/environment-emmc");
+
+	rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/mmc0");
+	rk3568_bbu_mmc_register("sd", 0, "/dev/mmc1");
+
+	return 0;
+}
+
+static const struct rock5_model rock5b = {
+	.name = "Radxa ROCK5 Model B",
+	.shortname = "rock5b",
+};
+
+static const struct of_device_id rock5_of_match[] = {
+	{
+		.compatible = "radxa,rock-5b",
+		.data = &rock5b,
+	},
+	{ /* sentinel */ },
+};
+
+static struct driver rock5_board_driver = {
+	.name = "board-rock5",
+	.probe = rock5_probe,
+	.of_compatible = rock5_of_match,
+};
+coredevice_platform_driver(rock5_board_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(rock5_of_match);
diff --git a/arch/arm/boards/radxa-rock5/lowlevel.c b/arch/arm/boards/radxa-rock5/lowlevel.c
new file mode 100644
index 0000000000..6f0ac732cc
--- /dev/null
+++ b/arch/arm/boards/radxa-rock5/lowlevel.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/rockchip/hardware.h>
+#include <mach/rockchip/atf.h>
+#include <debug_ll.h>
+#include <mach/rockchip/rockchip.h>
+
+extern char __dtb_rk3588_rock_5b_start[];
+
+ENTRY_FUNCTION(start_rock5b, r0, r1, r2)
+{
+	putc_ll('>');
+
+	if (current_el() == 3)
+		relocate_to_adr_full(RK3588_BAREBOX_LOAD_ADDRESS);
+	else
+		relocate_to_current_adr();
+
+	setup_c();
+
+	rk3588_barebox_entry(__dtb_rk3588_rock_5b_start);
+}
diff --git a/arch/arm/boards/raspberry-pi/Makefile b/arch/arm/boards/raspberry-pi/Makefile
index ddcf015f08..e4f91b4979 100644
--- a/arch/arm/boards/raspberry-pi/Makefile
+++ b/arch/arm/boards/raspberry-pi/Makefile
@@ -1,3 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-$(CONFIG_MACH_RPI_COMMON) += rpi-common.o
 lwl-y += lowlevel.o
+obj-pbl-y += mbox-helpers.o
 bbenv-y += defaultenv-rpi
diff --git a/arch/arm/boards/raspberry-pi/lowlevel.c b/arch/arm/boards/raspberry-pi/lowlevel.c
index d58beb6052..b3727d930f 100644
--- a/arch/arm/boards/raspberry-pi/lowlevel.c
+++ b/arch/arm/boards/raspberry-pi/lowlevel.c
@@ -1,8 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <asm/barebox-arm.h>
 #include <asm/cache.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/platform.h>
+#include <asm/unaligned.h>
+#include <mach/bcm283x/platform.h>
+#include <debug_ll.h>
+#include <mach/bcm283x/debug_ll.h>
+#include <mach/bcm283x/mbox.h>
 #include <of.h>
 
 #include "lowlevel.h"
@@ -31,52 +37,151 @@ static void copy_vc_fdt(void *dest, void *src, unsigned long max_size)
 	memmove(dest, src, size);
 }
 
-/* Must be inline since stack isn't setup yet. */
 static inline void start_raspberry_pi(unsigned long memsize, void *fdt,
 								void *vc_fdt)
 {
-	void *saved_vc_fdt;
-	unsigned long membase = BCM2835_SDRAM_BASE;
+	unsigned long endmem;
 
-	/* A pointer to the FDT created by VideoCore was passed to us in r2. We
-	 * reserve some memory just above the region used for Basebox and copy
-	 * this FDT there. We fetch it from there later in rpi_devices_init().*/
+	/*
+	 * A pointer to the FDT created by VideoCore was passed to us in x0/r2. We
+	 * reserve some memory at the end of SDRAM copy this FDT there. We fetch it
+	 * from there later in rpi_devices_init().
+	 */
 	memsize -= VIDEOCORE_FDT_SZ;
+	endmem = BCM2835_SDRAM_BASE + memsize;
 
-	arm_cpu_lowlevel_init();
-
-	/* Copied from barebox_arm_entry(). We need stack here early
-	 * for normal function calls to work. */
-	arm_setup_stack(arm_mem_stack_top(membase, membase + memsize));
+	/* leave SZ_1K for the initial stack */
+	copy_vc_fdt((void *)endmem, vc_fdt, VIDEOCORE_FDT_SZ - SZ_1K);
 
 	fdt += get_runtime_offset();
 
-	saved_vc_fdt = (void *)(membase + memsize);
-	copy_vc_fdt(saved_vc_fdt, vc_fdt, VIDEOCORE_FDT_SZ);
+	barebox_arm_entry(BCM2835_SDRAM_BASE, memsize, fdt);
+}
 
-	barebox_arm_entry(membase, memsize, fdt);
+#ifdef CONFIG_CPU_V8
+#define RPI_ENTRY_FUNCTION(name, memsize, fdt) \
+	ENTRY_FUNCTION_WITHSTACK(name, BCM2835_SDRAM_BASE + (memsize), fdt, __x1, __x2)
+#else
+#define RPI_ENTRY_FUNCTION(name, memsize, fdt) \
+	ENTRY_FUNCTION_WITHSTACK(name, BCM2835_SDRAM_BASE + (memsize), __r0, __r1, fdt)
+#endif
+
+extern char __dtb_z_bcm2835_rpi_start[];
+extern char __dtb_z_bcm2836_rpi_2_start[];
+extern char __dtb_z_bcm2837_rpi_3_start[];
+extern char __dtb_z_bcm2837_rpi_cm3_start[];
+extern char __dtb_z_bcm2711_rpi_4_start[];
+extern char __dtb_z_bcm2711_rpi_400_start[];
+extern char __dtb_z_bcm2711_rpi_cm4_io_start[];
+extern char __dtb_z_bcm2711_rpi_cm4s_io_start[];
+
+RPI_ENTRY_FUNCTION(start_raspberry_pi1, SZ_128M, fdt)
+{
+	arm_cpu_lowlevel_init();
+
+	start_raspberry_pi(SZ_128M, __dtb_z_bcm2835_rpi_start, (void *)fdt);
 }
 
-extern char __dtb_bcm2835_rpi_start[];
-ENTRY_FUNCTION(start_raspberry_pi1, r0, r1, r2)
+RPI_ENTRY_FUNCTION(start_raspberry_pi2, SZ_512M, fdt)
 {
-	start_raspberry_pi(SZ_128M, __dtb_bcm2835_rpi_start, (void *)r2);
+	arm_cpu_lowlevel_init();
+
+	start_raspberry_pi(SZ_512M, __dtb_z_bcm2836_rpi_2_start, (void *)fdt);
 }
 
-extern char __dtb_bcm2836_rpi_2_start[];
-ENTRY_FUNCTION(start_raspberry_pi2, r0, r1, r2)
+RPI_ENTRY_FUNCTION(start_raspberry_pi3, SZ_512M, fdt)
 {
-	start_raspberry_pi(SZ_512M, __dtb_bcm2836_rpi_2_start, (void *)r2);
+	arm_cpu_lowlevel_init();
+
+	start_raspberry_pi(SZ_512M, __dtb_z_bcm2837_rpi_3_start, (void *)fdt);
 }
 
-extern char __dtb_bcm2837_rpi_3_start[];
-ENTRY_FUNCTION(start_raspberry_pi3, r0, r1, r2)
+RPI_ENTRY_FUNCTION(start_raspberry_pi_cm3, SZ_512M, fdt)
 {
-	start_raspberry_pi(SZ_512M, __dtb_bcm2837_rpi_3_start, (void *)r2);
+	arm_cpu_lowlevel_init();
+
+	start_raspberry_pi(SZ_512M, __dtb_z_bcm2837_rpi_cm3_start, (void *)fdt);
 }
 
-extern char __dtb_bcm2837_rpi_cm3_start[];
-ENTRY_FUNCTION(start_raspberry_pi_cm3, r0, r1, r2)
+#define DT_IF_ENABLED(dt, cfg) \
+	(IS_ENABLED(cfg) ? (dt) : NULL)
+
+static void *rpi_get_board_fdt(int rev)
 {
-	start_raspberry_pi(SZ_512M, __dtb_bcm2837_rpi_cm3_start, (void *)r2);
+	if (!(rev & 0x800000))
+		return DT_IF_ENABLED(__dtb_z_bcm2835_rpi_start, CONFIG_MACH_RPI);
+
+	switch (((rev >> 4) & 0xff)) {
+	case BCM2835_BOARD_REV_A:
+	case BCM2835_BOARD_REV_B:
+	case BCM2835_BOARD_REV_A_PLUS:
+	case BCM2835_BOARD_REV_B_PLUS:
+	case BCM2835_BOARD_REV_CM1:
+	case BCM2835_BOARD_REV_ZERO:
+	case BCM2835_BOARD_REV_ZERO_W:
+		return DT_IF_ENABLED(__dtb_z_bcm2835_rpi_start, CONFIG_MACH_RPI);
+
+	case BCM2836_BOARD_REV_2_B:
+		return DT_IF_ENABLED(__dtb_z_bcm2836_rpi_2_start, CONFIG_MACH_RPI2);
+
+	case BCM2837_BOARD_REV_3_B:
+	case BCM2837B0_BOARD_REV_3B_PLUS:
+	case BCM2837B0_BOARD_REV_3A_PLUS:
+	case BCM2837B0_BOARD_REV_ZERO_2:
+		return DT_IF_ENABLED(__dtb_z_bcm2837_rpi_3_start, CONFIG_MACH_RPI3);
+
+	case BCM2837_BOARD_REV_CM3:
+	case BCM2837B0_BOARD_REV_CM3_PLUS:
+		return DT_IF_ENABLED(__dtb_z_bcm2837_rpi_cm3_start, CONFIG_MACH_RPI_CM3);
+
+	case BCM2711_BOARD_REV_4_B:
+		return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_4_start, CONFIG_MACH_RPI4);
+	case BCM2711_BOARD_REV_400:
+		return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_400_start, CONFIG_MACH_RPI4);
+	case BCM2711_BOARD_REV_CM4:
+		return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_cm4_io_start, CONFIG_MACH_RPI4);
+	case BCM2711_BOARD_REV_CM4_S:
+		return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_cm4s_io_start, CONFIG_MACH_RPI4);
+	}
+
+	return NULL;
+}
+
+RPI_ENTRY_FUNCTION(start_raspberry_pi_generic, SZ_128M, vc_fdt)
+{
+	void *fdt = NULL;
+	ssize_t memsize;
+	int rev;
+
+	arm_cpu_lowlevel_init();
+
+	debug_ll_init();
+
+	putc_ll('>');
+
+	relocate_to_current_adr();
+	setup_c();
+
+	memsize = rpi_get_arm_mem();
+	if (memsize < 0) {
+		pr_warn("mbox: failed to query ARM memory size. 128M assumed.\n");
+		memsize = SZ_128M;
+	}
+
+	rev = rpi_get_board_rev();
+	if (rev >= 0) {
+		pr_debug("Detected revision %08x\n", rev);
+		fdt = rpi_get_board_fdt(rev);
+	}
+
+	if (!fdt) {
+		fdt = (void *)vc_fdt;
+
+		pr_warn("Unknown Rpi board with rev %08x.\n", rev);
+
+		if (get_unaligned_be32(fdt) != 0xd00dfeed)
+			panic("No suitable built-in or videocore-supplied DT\n");
+	}
+
+	start_raspberry_pi(memsize, fdt, (void *)vc_fdt);
 }
diff --git a/arch/arm/boards/raspberry-pi/lowlevel.h b/arch/arm/boards/raspberry-pi/lowlevel.h
index 9ef9135b2d..a29860d607 100644
--- a/arch/arm/boards/raspberry-pi/lowlevel.h
+++ b/arch/arm/boards/raspberry-pi/lowlevel.h
@@ -1,9 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ARCH_ARM_BOARDS_LOWLEVEL_H__
 #define __ARCH_ARM_BOARDS_LOWLEVEL_H__
 
+#include <linux/types.h>
 #include <linux/sizes.h>
 
 #define VIDEOCORE_FDT_SZ SZ_1M
 #define VIDEOCORE_FDT_ERROR 0xdeadfeed
 
+ssize_t rpi_get_arm_mem(void);
+int rpi_get_usbethaddr(u8 mac[6]);
+int rpi_get_board_rev(void);
+
 #endif /* __ARCH_ARM_BOARDS_LOWLEVEL_H__ */
diff --git a/arch/arm/boards/raspberry-pi/mbox-helpers.c b/arch/arm/boards/raspberry-pi/mbox-helpers.c
new file mode 100644
index 0000000000..3a76ac2b01
--- /dev/null
+++ b/arch/arm/boards/raspberry-pi/mbox-helpers.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2009 Carlo Caione <carlo@carlocaione.org>
+
+#include <mach/bcm283x/mbox.h>
+#include "lowlevel.h"
+
+struct msg_get_arm_mem {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
+	u32 end_tag;
+};
+
+struct msg_get_board_rev {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_board_rev get_board_rev;
+	u32 end_tag;
+};
+
+struct msg_get_mac_address {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_mac_address get_mac_address;
+	u32 end_tag;
+};
+
+ssize_t rpi_get_arm_mem(void)
+{
+	BCM2835_MBOX_STACK_ALIGN(struct msg_get_arm_mem, msg);
+	int ret;
+
+	BCM2835_MBOX_INIT_HDR(msg);
+	BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	if (ret)
+		return ret;
+
+	return msg->get_arm_mem.body.resp.mem_size;
+}
+
+int rpi_get_usbethaddr(u8 mac[6])
+{
+	BCM2835_MBOX_STACK_ALIGN(struct msg_get_mac_address, msg);
+	int ret;
+
+	BCM2835_MBOX_INIT_HDR(msg);
+	BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	if (ret) {
+		pr_info("bcm2835: Could not query MAC address\n");
+		return ret;
+	}
+
+	memcpy(mac, msg->get_mac_address.body.resp.mac, 6);
+	return 0;
+}
+
+int rpi_get_board_rev(void)
+{
+	int ret;
+
+	BCM2835_MBOX_STACK_ALIGN(struct msg_get_board_rev, msg);
+	BCM2835_MBOX_INIT_HDR(msg);
+	BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	if (ret) {
+		pr_err("Could not query board revision\n");
+		return ret;
+	}
+
+	return msg->get_board_rev.body.resp.rev;
+}
diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
index e326732b3a..7c82c740e2 100644
--- a/arch/arm/boards/raspberry-pi/rpi-common.c
+++ b/arch/arm/boards/raspberry-pi/rpi-common.c
@@ -2,9 +2,11 @@
 // SPDX-FileCopyrightText: 2009 Carlo Caione <carlo@carlocaione.org>
 
 #include <common.h>
+#include <deep-probe.h>
 #include <init.h>
 #include <fs.h>
 #include <of.h>
+#include <of_device.h>
 #include <linux/stat.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
@@ -17,101 +19,55 @@
 #include <led.h>
 #include <asm/armlinux.h>
 #include <asm/barebox-arm.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <linux/sizes.h>
 #include <globalvar.h>
 #include <asm/system_info.h>
+#include <reset_source.h>
 
-#include <mach/core.h>
-#include <mach/mbox.h>
-#include <mach/platform.h>
+#include <mach/bcm283x/core.h>
+#include <mach/bcm283x/mbox.h>
+#include <mach/bcm283x/platform.h>
 
-#include "lowlevel.h"
+#include <soc/bcm283x/wdt.h>
 
-struct rpi_model {
-	const char *name;
-	void (*init)(void);
-};
-
-#define RPI_MODEL(_id, _name, _init)	\
-	[_id] = {				\
-		.name			= _name,\
-		.init			= _init,\
-	}
-
-struct msg_get_arm_mem {
-	struct bcm2835_mbox_hdr hdr;
-	struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
-	u32 end_tag;
-};
+#include "lowlevel.h"
 
-struct msg_get_clock_rate {
-	struct bcm2835_mbox_hdr hdr;
-	struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
-	u32 end_tag;
+//https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#BOOT_ORDER
+static const char * const boot_mode_names[] = {
+	[0x0] = "unknown",
+	[0x1] = "sd",
+	[0x2] = "net",
+	[0x3] = "rpiboot",
+	[0x4] = "usbmsd",
+	[0x5] = "usbc",
+	[0x6] = "nvme",
+	[0x7] = "http",
 };
 
-struct msg_get_board_rev {
-	struct bcm2835_mbox_hdr hdr;
-	struct bcm2835_mbox_tag_get_board_rev get_board_rev;
-	u32 end_tag;
+struct rpi_priv;
+struct rpi_machine_data {
+	int (*init)(struct rpi_priv *priv);
+	u8 hw_id;
+#define RPI_OLD_SCHEMA			BIT(0)
+	u8 flags;
 };
 
-struct msg_get_mac_address {
-	struct bcm2835_mbox_hdr hdr;
-	struct bcm2835_mbox_tag_get_mac_address get_mac_address;
-	u32 end_tag;
+struct rpi_priv {
+	struct device *dev;
+	const struct rpi_machine_data *dcfg;
+	unsigned int hw_id;
+	const char *name;
 };
 
-static int rpi_get_arm_mem(u32 *size)
-{
-	BCM2835_MBOX_STACK_ALIGN(struct msg_get_arm_mem, msg);
-	int ret;
-
-	BCM2835_MBOX_INIT_HDR(msg);
-	BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
-
-	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
-	if (ret)
-		return ret;
-
-	*size = msg->get_arm_mem.body.resp.mem_size;
-
-	return 0;
-}
-
-static struct clk *rpi_register_firmware_clock(u32 clock_id, const char *name)
-{
-	BCM2835_MBOX_STACK_ALIGN(struct msg_get_clock_rate, msg);
-	int ret;
-
-	BCM2835_MBOX_INIT_HDR(msg);
-	BCM2835_MBOX_INIT_TAG(&msg->get_clock_rate, GET_CLOCK_RATE);
-	msg->get_clock_rate.body.req.clock_id = clock_id;
-
-	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
-	if (ret)
-		return ERR_PTR(ret);
-
-	return clk_fixed(name, msg->get_clock_rate.body.resp.rate_hz);
-}
-
 static void rpi_set_usbethaddr(void)
 {
-	BCM2835_MBOX_STACK_ALIGN(struct msg_get_mac_address, msg);
-	int ret;
+	u8 mac[ETH_ALEN];
 
-	BCM2835_MBOX_INIT_HDR(msg);
-	BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
-
-	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
-	if (ret) {
-		printf("bcm2835: Could not query MAC address\n");
-		/* Ignore error; not critical */
-		return;
-	}
+	if (rpi_get_usbethaddr(mac))
+		return; /* Ignore error; not critical */
 
-	eth_register_ethaddr(0, msg->get_mac_address.body.resp.mac);
+	eth_register_ethaddr(0, mac);
 }
 
 static void rpi_set_usbotg(const char *alias)
@@ -154,330 +110,300 @@ static void rpi_add_led(void)
 		led_set_trigger(LED_TRIGGER_HEARTBEAT, &l->led);
 }
 
-static void rpi_b_init(void)
+static int rpi_eth_init(struct rpi_priv *priv)
+{
+	rpi_set_usbethaddr();
+	return 0;
+}
+
+static int rpi_b_init(struct rpi_priv *priv)
 {
 	rpi_leds[0].gpio = 16;
 	rpi_leds[0].active_low = 1;
 	rpi_set_usbethaddr();
+
+	return 0;
 }
 
-static void rpi_b_plus_init(void)
+static int rpi_b_plus_init(struct rpi_priv *priv)
 {
 	rpi_leds[0].gpio = 47;
 	rpi_leds[1].gpio = 35;
 	rpi_set_usbethaddr();
+
+	return 0;
 }
 
-static void rpi_0_init(void)
+static int rpi_0_init(struct rpi_priv *priv)
 {
 	rpi_leds[0].gpio = 47;
 	rpi_set_usbotg("usb0");
+
+	return 0;
 }
 
-static void rpi_0_w_init(void)
+static int rpi_0_w_init(struct rpi_priv *priv)
 {
 	struct device_node *np;
 	int ret;
 
-	rpi_0_init();
+	rpi_0_init(priv);
 
 	np = of_find_node_by_path("/chosen");
 	if (!np)
-		return;
+		return -ENODEV;
 
 	if (!of_device_enable_and_register_by_alias("serial1"))
-		return;
+		return -ENODEV;
 
 	ret = of_property_write_string(np, "stdout-path", "serial1:115200n8");
 	if (ret)
-		return;
+		return ret;
 
-	of_device_disable_by_alias("serial0");
+	return of_device_disable_by_alias("serial0");
 }
 
-/* See comments in mbox.h for data source */
-static const struct rpi_model rpi_models_old_scheme[] = {
-	RPI_MODEL(0, "Unknown model", NULL),
-	RPI_MODEL(BCM2835_BOARD_REV_B_I2C0_2, "Model B (no P5)", rpi_b_init),
-	RPI_MODEL(BCM2835_BOARD_REV_B_I2C0_3, "Model B (no P5)", rpi_b_init),
-	RPI_MODEL(BCM2835_BOARD_REV_B_I2C1_4, "Model B", rpi_b_init),
-	RPI_MODEL(BCM2835_BOARD_REV_B_I2C1_5, "Model B", rpi_b_init),
-	RPI_MODEL(BCM2835_BOARD_REV_B_I2C1_6, "Model B", rpi_b_init),
-	RPI_MODEL(BCM2835_BOARD_REV_A_7, "Model A", NULL),
-	RPI_MODEL(BCM2835_BOARD_REV_A_8, "Model A", NULL),
-	RPI_MODEL(BCM2835_BOARD_REV_A_9, "Model A", NULL),
-	RPI_MODEL(BCM2835_BOARD_REV_B_REV2_d, "Model B rev2", rpi_b_init),
-	RPI_MODEL(BCM2835_BOARD_REV_B_REV2_e, "Model B rev2", rpi_b_init),
-	RPI_MODEL(BCM2835_BOARD_REV_B_REV2_f, "Model B rev2", rpi_b_init),
-	RPI_MODEL(BCM2835_BOARD_REV_B_PLUS_10, "Model B+", rpi_b_plus_init),
-	RPI_MODEL(BCM2835_BOARD_REV_CM_11, "Compute Module", NULL),
-	RPI_MODEL(BCM2835_BOARD_REV_A_PLUS_12, "Model A+", NULL),
-	RPI_MODEL(BCM2835_BOARD_REV_B_PLUS_13, "Model B+", rpi_b_plus_init),
-	RPI_MODEL(BCM2835_BOARD_REV_CM_14, "Compute Module", NULL),
-	RPI_MODEL(BCM2835_BOARD_REV_A_PLUS_15, "Model A+", NULL),
-};
+static int rpi_mem_init(void)
+{
+	ssize_t size;
 
-static const struct rpi_model rpi_models_new_scheme[] = {
-	RPI_MODEL(BCM2835_BOARD_REV_A, 		"Model A",	NULL ),
-	RPI_MODEL(BCM2835_BOARD_REV_B, 		"Model B", 	rpi_b_init ),
-	RPI_MODEL(BCM2835_BOARD_REV_A_PLUS, 	"Model A+", 	NULL ),
-	RPI_MODEL(BCM2835_BOARD_REV_B_PLUS, 	"Model B+", 	rpi_b_plus_init ),
-	RPI_MODEL(BCM2836_BOARD_REV_2_B, 	"Model 2B", 	rpi_b_plus_init),
-	RPI_MODEL(BCM283x_BOARD_REV_Alpha, 	"Alpha", 	NULL),
-	RPI_MODEL(BCM2835_BOARD_REV_CM1, 	"Compute Module", NULL ),
-	RPI_MODEL(0x7, "Unknown model", NULL),
-	RPI_MODEL(BCM2837_BOARD_REV_3_B, 	"Model 3B", 	rpi_b_init ),
-	RPI_MODEL(BCM2835_BOARD_REV_ZERO, 	"Zero", 	rpi_0_init),
-	RPI_MODEL(BCM2837_BOARD_REV_CM3, 	"Compute Module 3", NULL ),
-	RPI_MODEL(0xb, "Unknown model", NULL),
-	RPI_MODEL(BCM2835_BOARD_REV_ZERO_W, 	"Zero W", 	rpi_0_w_init),
-	RPI_MODEL(BCM2837B0_BOARD_REV_3B_PLUS, 	"Model 3B+", 	rpi_b_plus_init ),
-	RPI_MODEL(BCM2837B0_BOARD_REV_3A_PLUS, 	"Model 3A+", 	rpi_b_plus_init),
-	RPI_MODEL(0xf, "Unknown model", NULL),
-	RPI_MODEL(BCM2837B0_BOARD_REV_CM3_PLUS, "Compute Module 3+", NULL),
-};
+	if (!of_machine_is_compatible("brcm,bcm2837") &&
+	    !of_machine_is_compatible("brcm,bcm2835") &&
+	    !of_machine_is_compatible("brcm,bcm2711") &&
+	    !of_machine_is_compatible("brcm,bcm2836"))
+		return 0;
+
+	size = rpi_get_arm_mem();
+	if (size < 0) {
+		printf("could not query ARM memory size\n");
+		size = get_ram_size((ulong *) BCM2835_SDRAM_BASE, SZ_128M);
+	}
+
+	bcm2835_add_device_sdram(size);
 
-static int rpi_board_rev = 0;
-static const struct rpi_model *model = NULL;
+	return 0;
+}
+mem_initcall(rpi_mem_init);
 
-static void rpi_get_board_rev(void)
+static int rpi_env_init(void)
 {
+	struct stat s;
+	const char *diskdev;
 	int ret;
-	char *name;
-	const struct rpi_model *rpi_models;
-	size_t rpi_models_size;
 
-	BCM2835_MBOX_STACK_ALIGN(struct msg_get_board_rev, msg);
-	BCM2835_MBOX_INIT_HDR(msg);
-	BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
+	device_detect_by_name("mci0");
 
-	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	diskdev = "/dev/disk0.0";
+	ret = stat(diskdev, &s);
 	if (ret) {
-		printf("bcm2835: Could not query board revision\n");
-		/* Ignore error; not critical */
-		return;
+		device_detect_by_name("mmc0");
+		diskdev = "/dev/mmc0.0";
+		ret = stat(diskdev, &s);
 	}
-
-	/* Comments from u-boot:
-	 * For details of old-vs-new scheme, see:
-	 * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py
-	 * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282
-	 * (a few posts down)
-	 *
-	 * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the
-	 * lower byte to use as the board rev:
-	 * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250
-	 * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594
-	 */
-	rpi_board_rev = msg->get_board_rev.body.resp.rev;
-	if (rpi_board_rev & 0x800000) {
-		rpi_board_rev = (rpi_board_rev >> 4) & 0xff;
-		rpi_models = rpi_models_new_scheme;
-		rpi_models_size = ARRAY_SIZE(rpi_models_new_scheme);
-
-	} else {
-		rpi_board_rev &= 0xff;
-		rpi_models = rpi_models_old_scheme;
-		rpi_models_size = ARRAY_SIZE(rpi_models_old_scheme);
-	}
-
-	if (rpi_board_rev >= rpi_models_size) {
-		printf("RPI: Board rev %u outside known range\n",
-		       rpi_board_rev);
-		goto unknown_rev;
+	if (ret) {
+		printf("no /dev/disk0.0 or /dev/mmc0.0. using default env\n");
+		return 0;
 	}
 
-	if (!rpi_models[rpi_board_rev].name) {
-		printf("RPI: Board rev %u unknown\n", rpi_board_rev);
-		goto unknown_rev;
+	mkdir("/boot", 0666);
+	ret = mount(diskdev, "fat", "/boot", NULL);
+	if (ret) {
+		printf("failed to mount %s\n", diskdev);
+		return 0;
 	}
 
-	if (!rpi_board_rev)
-		goto unknown_rev;
-
-	model = &rpi_models[rpi_board_rev];
-	name = basprintf("RaspberryPi %s", model->name);
-	barebox_set_model(name);
-	free(name);
+	defaultenv_append_directory(defaultenv_rpi);
 
-	return;
+	default_environment_path_set("/boot/barebox.env");
 
-unknown_rev:
-	rpi_board_rev = 0;
-	barebox_set_model("RaspberryPi (unknown rev)");
+	return 0;
 }
 
-static void rpi_model_init(void)
+/* Some string properties in fdt passed to us from vc may be
+ * malformed by not being null terminated, so just create and
+ * return a fixed copy.
+ */
+static char *of_read_vc_string(struct device_node *node,
+			       const char *prop_name)
 {
-	if (!model)
-		return;
-
-	if (!model->init)
-		return;
-
-	model->init();
+	int len;
+	const char *str;
+
+	str = of_get_property(node, prop_name, &len);
+	if (!str) {
+		pr_warn("no property '%s' found in vc fdt's '%pOF' node\n",
+			prop_name, node);
+		return NULL;
+	}
+	return xstrndup(str, len);
 }
 
-static int rpi_mem_init(void)
+static enum reset_src_type rpi_decode_pm_rsts(struct device_node *chosen,
+					      struct device_node *bootloader)
 {
-	u32 size = 0;
+	u32 pm_rsts;
 	int ret;
 
-	ret = rpi_get_arm_mem(&size);
-	if (ret)
-		printf("could not query ARM memory size\n");
-
-	bcm2835_add_device_sdram(size);
+	ret = of_property_read_u32(chosen, "pm_rsts", &pm_rsts);
+	if (ret && bootloader)
+		 ret = of_property_read_u32(bootloader, "rsts", &pm_rsts);
 
-	return ret;
-}
-mem_initcall(rpi_mem_init);
+	if (ret) {
+		pr_warn("'pm_rsts' value not found in vc fdt\n");
+		return RESET_UKWN;
+	}
+	/*
+	 * https://github.com/raspberrypi/linux/issues/932#issuecomment-93989581
+	 */
 
-static int rpi_postcore_init(void)
-{
-	rpi_get_board_rev();
-	barebox_set_hostname("rpi");
-	rpi_model_init();
+	if (pm_rsts & PM_RSTS_HADPOR_SET)
+		return RESET_POR;
+	if (pm_rsts & PM_RSTS_HADDR_SET)
+		return RESET_JTAG;
+	if (pm_rsts & PM_RSTS_HADWR_SET)
+		return RESET_WDG;
+	if (pm_rsts & PM_RSTS_HADSR_SET)
+		return RESET_RST;
 
-	return 0;
+	return RESET_UKWN;
 }
-postcore_initcall(rpi_postcore_init);
 
-static int rpi_clock_init(void)
+static int rpi_vc_fdt_fixup(struct device_node *root, void *data)
 {
-	struct clk *clk;
-
-	clk = rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_EMMC,
-					 "bcm2835_mci0");
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
+	const struct device_node *vc_node = data;
+	struct device_node *node;
+	struct property *pp;
 
-	clkdev_add_physbase(clk, 0x20300000, NULL);
-	clkdev_add_physbase(clk, 0x3f300000, NULL);
+	node = of_create_node(root, vc_node->full_name);
+	if (!node)
+		return -ENOMEM;
 
-	clk = rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_CORE,
-					  "bcm2835_sdhost");
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
-	clkdev_add_physbase(clk, 0x20202000, NULL);
-	clkdev_add_physbase(clk, 0x3f202000, NULL);
+	for_each_property_of_node(vc_node, pp)
+		of_copy_property(vc_node, pp->name, node);
 
 	return 0;
 }
-postconsole_initcall(rpi_clock_init);
 
-static int rpi_console_clock_init(void)
+static struct device_node *register_vc_fixup(struct device_node *root,
+					     const char *path)
 {
-	struct clk *clk;
-
-	clk = clk_fixed("apb_pclk", 0);
-	clk_register_clkdev(clk, "apb_pclk", NULL);
+	struct device_node *ret, *tmp;
 
-	clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000);
-	clk_register_clkdev(clk, NULL, "uart0-pl0110");
-	clkdev_add_physbase(clk, BCM2835_PL011_BASE, NULL);
-	clkdev_add_physbase(clk, BCM2836_PL011_BASE, NULL);
-
-	clk = rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_CORE,
-					  "uart1-8250");
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
-	clkdev_add_physbase(clk, BCM2835_MINIUART_BASE, NULL);
-	clkdev_add_physbase(clk, BCM2836_MINIUART_BASE, NULL);
-
-	clk = clk_fixed("bcm2835-cs", 1 * 1000 * 1000);
-	clk_register_clkdev(clk, NULL, "bcm2835-cs");
+	ret = of_find_node_by_path_from(root, path);
+	if (ret) {
+		tmp = of_dup(ret);
+		tmp->full_name = xstrdup(ret->full_name);
+		of_register_fixup(rpi_vc_fdt_fixup, tmp);
+	} else {
+		pr_info("no '%s' node found in vc fdt\n", path);
+	}
 
-	return 0;
+	return ret;
 }
-postcore_initcall(rpi_console_clock_init);
 
-static int rpi_env_init(void)
+static u32 rpi_boot_mode, rpi_boot_part;
+/* Extract useful information from the VideoCore FDT we got.
+ * Some parameters are defined here:
+ * https://www.raspberrypi.com/documentation/computers/configuration.html#part4
+ */
+static void rpi_vc_fdt_parse(struct device_node *root)
 {
-	struct stat s;
-	const char *diskdev = "/dev/disk0.0";
 	int ret;
+	struct device_node *chosen, *bootloader, *memory;
+	char *str;
 
-	device_detect_by_name("mci0");
-
-	ret = stat(diskdev, &s);
-	if (ret) {
-		printf("no %s. using default env\n", diskdev);
-		return 0;
+	str = of_read_vc_string(root, "serial-number");
+	if (str) {
+		barebox_set_serial_number(str);
+		free(str);
 	}
 
-	mkdir("/boot", 0666);
-	ret = mount(diskdev, "fat", "/boot", NULL);
-	if (ret) {
-		printf("failed to mount %s\n", diskdev);
-		return 0;
+	str = of_read_vc_string(root, "model");
+	if (str) {
+		barebox_set_model(str);
+		free(str);
 	}
 
-	defaultenv_append_directory(defaultenv_rpi);
+	register_vc_fixup(root, "/system");
+	register_vc_fixup(root, "/axi");
+	register_vc_fixup(root, "/reserved-memory");
+	register_vc_fixup(root, "/hat");
+	register_vc_fixup(root, "/chosen/bootloader");
+	chosen = register_vc_fixup(root, "/chosen");
+	if (!chosen) {
+		pr_err("no '/chosen' node found in vc fdt\n");
+		return;
+	}
 
-	default_environment_path_set("/boot/barebox.env");
+	bootloader = of_find_node_by_name(chosen, "bootloader");
 
-	return 0;
-}
-
-/* Extract /chosen/bootargs from the VideoCore FDT into vc.bootargs
- * global variable. */
-static int rpi_vc_fdt_bootargs(void *fdt)
-{
-	int ret = 0;
-	struct device_node *root = NULL, *node;
-	const char *cmdline;
-
-	root = of_unflatten_dtb(fdt);
-	if (IS_ERR(root)) {
-		ret = PTR_ERR(root);
-		root = NULL;
-		goto out;
+	str = of_read_vc_string(chosen, "bootargs");
+	if (str) {
+		globalvar_add_simple("vc.bootargs", str);
+		free(str);
 	}
 
-	node = of_find_node_by_path_from(root, "/chosen");
-	if (!node) {
-		pr_err("no /chosen node\n");
-		ret = -ENOENT;
-		goto out;
+	str = of_read_vc_string(chosen, "overlay_prefix");
+	if (str) {
+		globalvar_add_simple("vc.overlay_prefix", str);
+		free(str);
 	}
 
-	cmdline = of_get_property(node, "bootargs", NULL);
-	if (!cmdline) {
-		pr_err("no bootargs property in the /chosen node\n");
-		ret = -ENOENT;
-		goto out;
+	str = of_read_vc_string(chosen, "os_prefix");
+	if (str) {
+		globalvar_add_simple("vc.os_prefix", str);
+		free(str);
 	}
 
-	globalvar_add_simple("vc.bootargs", cmdline);
+	ret = of_property_read_u32(chosen, "boot-mode", &rpi_boot_mode);
+	if (ret && bootloader)
+		ret = of_property_read_u32(bootloader, "boot-mode", &rpi_boot_mode);
+	if (ret)
+		pr_debug("'boot-mode' property not found in vc fdt\n");
+	else
+		globalvar_add_simple_enum("vc.boot_mode", &rpi_boot_mode,
+					  boot_mode_names,
+					  ARRAY_SIZE(boot_mode_names));
+
+	ret = of_property_read_u32(chosen, "partition", &rpi_boot_part);
+	if (ret && bootloader)
+		ret = of_property_read_u32(bootloader, "partition", &rpi_boot_part);
+	if (ret)
+		pr_debug("'partition' property not found in vc fdt\n");
+	else
+		globalvar_add_simple_int("vc.boot_partition", &rpi_boot_part, "%u");
 
-	switch(cpu_architecture()) {
-	case CPU_ARCH_ARMv6:
-		globalvar_add_simple("vc.kernel", "kernel.img");
-		break;
-	case CPU_ARCH_ARMv7:
-		globalvar_add_simple("vc.kernel", "kernel7.img");
-		break;
-	case CPU_ARCH_ARMv8:
-		globalvar_add_simple("vc.kernel", "kernel7l.img");
-		break;
-	}
+	if (IS_ENABLED(CONFIG_RESET_SOURCE))
+		reset_source_set(rpi_decode_pm_rsts(chosen, bootloader));
 
-out:
-	if (root)
-		of_delete_node(root);
+	/* Parse all available nodes with "memory" device_type */
+	memory = root;
+	while (1) {
+		memory = of_find_node_by_type(memory, "memory");
+		if (!memory)
+			break;
 
-	return ret;
+		of_add_memory(memory, false);
+	}
 }
 
-static void rpi_vc_fdt(void)
+/**
+ * rpi_vc_fdt - unflatten VideoCore provided DT
+ *
+ * If configured via config.txt, the VideoCore firmware will pass barebox PBL
+ * a device-tree in a register. This is saved to a handover memory area by
+ * the Raspberry Pi PBL, which is parsed here. barebox-dt-2nd doesn't
+ * populate this area, instead it uses the VideoCore DT as its own DT.
+ *
+ * Return: an unflattened DT on success, an error pointer if parsing the DT
+ * fails and NULL if a Raspberry Pi PBL has run, but no VideoCore FDT was
+ * saved.
+ */
+static struct device_node *rpi_vc_fdt(void)
 {
 	void *saved_vc_fdt;
 	struct fdt_header *oftree;
 	unsigned long magic, size;
-	int ret;
 
 	/* VideoCore FDT was copied in PBL just above Barebox memory */
 	saved_vc_fdt = (void *)(arm_mem_endmem_get());
@@ -489,37 +415,130 @@ static void rpi_vc_fdt(void)
 		if (oftree->totalsize)
 			pr_err("there was an error copying fdt in pbl: %d\n",
 					be32_to_cpu(oftree->totalsize));
-		return;
+		return NULL;
 	}
 
-	if (magic != FDT_MAGIC) {
-		pr_err("videocore fdt saved in pbl has invalid magic\n");
-		return;
-	}
+	if (magic != FDT_MAGIC)
+		return ERR_PTR(-EINVAL);
 
 	size = be32_to_cpu(oftree->totalsize);
-	if (write_file("/vc.dtb", saved_vc_fdt, size)) {
+	if (write_file("/vc.dtb", saved_vc_fdt, size))
 		pr_err("failed to save videocore fdt to a file\n");
-		return;
+
+	return of_unflatten_dtb(saved_vc_fdt, INT_MAX);
+}
+
+static void rpi_set_kernel_name(void) {
+	switch(cpu_architecture()) {
+	case CPU_ARCH_ARMv6:
+		globalvar_add_simple("vc.kernel", "kernel.img");
+		break;
+	case CPU_ARCH_ARMv7:
+		globalvar_add_simple("vc.kernel", "kernel7.img");
+		break;
+	case CPU_ARCH_ARMv8:
+		globalvar_add_simple("vc.kernel", "kernel8.img");
+		break;
 	}
+}
 
-	ret = rpi_vc_fdt_bootargs(saved_vc_fdt);
-	if (ret) {
-		pr_err("failed to extract bootargs from videocore fdt: %d\n",
-									ret);
-		return;
+static const struct rpi_machine_data *rpi_get_dcfg(struct rpi_priv *priv)
+{
+	const struct rpi_machine_data *dcfg;
+
+	dcfg = of_device_get_match_data(priv->dev);
+	if (!dcfg) {
+		dev_err(priv->dev, "Unknown board. Not applying fixups\n");
+		return NULL;
+	}
+
+	/* Comments from u-boot:
+	 * For details of old-vs-new scheme, see:
+	 * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py
+	 * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282
+	 * (a few posts down)
+	 *
+	 * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the
+	 * lower byte to use as the board rev:
+	 * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250
+	 * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594
+	 */
+
+	for (; dcfg->hw_id != U8_MAX; dcfg++) {
+		if (priv->hw_id & 0x800000) {
+			if (dcfg->hw_id != ((priv->hw_id >> 4) & 0xff))
+				continue;
+		} else {
+			if (!(dcfg->flags & RPI_OLD_SCHEMA))
+				continue;
+			if (dcfg->hw_id != (priv->hw_id & 0xff))
+				continue;
+		}
+
+		return dcfg;
 	}
+
+	dev_err(priv->dev, "dcfg 0x%x for board_id doesn't match DT compatible\n",
+		priv->hw_id);
+	return ERR_PTR(-ENODEV);
 }
 
-static int rpi_devices_init(void)
+static int rpi_devices_probe(struct device *dev)
 {
+	const struct rpi_machine_data *dcfg;
 	struct regulator *reg;
+	struct rpi_priv *priv;
+	struct device_node *vc_root;
+	const char *name, *ptr;
+	char *hostname;
+	int ret;
+
+	priv = xzalloc(sizeof(*priv));
+	priv->dev = dev;
+
+	ret = rpi_get_board_rev();
+	if (ret < 0)
+		goto free_priv;
+
+	priv->hw_id = ret;
+
+	dcfg = rpi_get_dcfg(priv);
+	if (IS_ERR(dcfg))
+		goto free_priv;
+
+	/* construct short recognizable host name */
+	name = of_device_get_match_compatible(priv->dev);
+	ptr = strchr(name, ',');
+	hostname = basprintf("rpi-%s", ptr ? ptr + 1 : name);
+	barebox_set_hostname(hostname);
+	free(hostname);
 
 	rpi_add_led();
 	bcm2835_register_fb();
 	armlinux_set_architecture(MACH_TYPE_BCM2708);
 	rpi_env_init();
-	rpi_vc_fdt();
+
+	vc_root = rpi_vc_fdt();
+	if (!vc_root) {
+		dev_dbg(dev, "No VideoCore FDT was provided\n");
+	} else if (!IS_ERR(vc_root)) {
+		dev_dbg(dev, "VideoCore FDT was provided\n");
+		rpi_vc_fdt_parse(vc_root);
+		of_delete_node(vc_root);
+	} else if (IS_ERR(vc_root)) {
+		/* This is intentionally at a higher logging level, because we can't
+		 * be sure that the external DT is indeed a barebox DT (and not a
+		 * kernel DT that happened to be in the partition). So for ease
+		 * of debugging, we report this at info log level.
+		 */
+		dev_info(dev, "barebox FDT will be used for VideoCore FDT\n");
+		rpi_vc_fdt_parse(priv->dev->device_node);
+	}
+
+	rpi_set_kernel_name();
+
+	if (dcfg && dcfg->init)
+		dcfg->init(priv);
 
 	reg = regulator_get_name("bcm2835_usb");
 	if (IS_ERR(reg))
@@ -528,5 +547,177 @@ static int rpi_devices_init(void)
 	regulator_enable(reg);
 
 	return 0;
+
+free_priv:
+	kfree(priv);
+	return ret;
 }
-late_initcall(rpi_devices_init);
+
+static const struct rpi_machine_data rpi_1_ids[] = {
+	{
+		.hw_id = BCM2835_BOARD_REV_A_7,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_A_8,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_A_9,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_A,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_A_PLUS_12,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_A_PLUS_15,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_A_PLUS,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_I2C1_4,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_I2C1_5,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_I2C1_6,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_I2C0_2,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_I2C0_3,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_REV2_d,
+		.flags = RPI_OLD_SCHEMA,
+		.init = rpi_b_init,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_REV2_e,
+		.flags = RPI_OLD_SCHEMA,
+		.init = rpi_b_init,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_REV2_f,
+		.flags = RPI_OLD_SCHEMA,
+		.init = rpi_b_init,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_PLUS_10,
+		.flags = RPI_OLD_SCHEMA,
+		.init = rpi_b_plus_init,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_PLUS_13,
+		.flags = RPI_OLD_SCHEMA,
+		.init = rpi_b_plus_init,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_B_PLUS,
+		.init = rpi_b_plus_init,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_CM_11,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_CM_14,
+		.flags = RPI_OLD_SCHEMA,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_CM1,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_ZERO,
+		.init = rpi_0_init,
+	}, {
+		.hw_id = BCM2835_BOARD_REV_ZERO_W,
+		.init = rpi_0_w_init,
+	}, {
+		.hw_id = U8_MAX
+	},
+};
+
+static const struct rpi_machine_data rpi_2_ids[] = {
+	{
+		.hw_id = BCM2836_BOARD_REV_2_B,
+		.init = rpi_b_plus_init,
+	}, {
+		.hw_id = U8_MAX
+	},
+};
+
+static const struct rpi_machine_data rpi_3_ids[] = {
+	{
+		.hw_id = BCM2837B0_BOARD_REV_3A_PLUS,
+		.init = rpi_b_plus_init,
+	}, {
+		.hw_id = BCM2837_BOARD_REV_3_B,
+		.init = rpi_b_init,
+	}, {
+		.hw_id = BCM2837B0_BOARD_REV_3B_PLUS,
+		.init = rpi_b_plus_init,
+	}, {
+		.hw_id = BCM2837_BOARD_REV_CM3,
+		.init = rpi_eth_init,
+	}, {
+		.hw_id = BCM2837B0_BOARD_REV_CM3_PLUS,
+	}, {
+		.hw_id = BCM2837B0_BOARD_REV_ZERO_2,
+	}, {
+		.hw_id = U8_MAX
+	},
+};
+
+static const struct rpi_machine_data rpi_4_ids[] = {
+	{
+		.hw_id = BCM2711_BOARD_REV_4_B,
+		.init = rpi_eth_init,
+	}, {
+		.hw_id = BCM2711_BOARD_REV_400,
+		.init = rpi_eth_init,
+	}, {
+		.hw_id = BCM2711_BOARD_REV_CM4,
+		.init = rpi_eth_init,
+	}, {
+		.hw_id = BCM2711_BOARD_REV_CM4_S,
+		.init = rpi_eth_init,
+	}, {
+		.hw_id = U8_MAX
+	},
+};
+
+static const struct of_device_id rpi_of_match[] = {
+	/* BCM2835 based Boards */
+	{ .compatible = "raspberrypi,model-a", .data = rpi_1_ids },
+	{ .compatible = "raspberrypi,model-a-plus", .data = rpi_1_ids },
+	{ .compatible = "raspberrypi,model-b", .data = rpi_1_ids },
+	/* Raspberry Pi Model B (no P5) */
+	{ .compatible = "raspberrypi,model-b-i2c0", .data = rpi_1_ids },
+	{ .compatible = "raspberrypi,model-b-rev2", .data = rpi_1_ids },
+	{ .compatible = "raspberrypi,model-b-plus", .data = rpi_1_ids },
+	{ .compatible = "raspberrypi,compute-module", .data = rpi_1_ids },
+	{ .compatible = "raspberrypi,model-zero", .data = rpi_1_ids },
+	{ .compatible = "raspberrypi,model-zero-w", .data = rpi_1_ids },
+
+	/* BCM2836 based Boards */
+	{ .compatible = "raspberrypi,2-model-b", .data = rpi_2_ids },
+
+	/* BCM2837 based Boards */
+	{ .compatible = "raspberrypi,3-model-a-plus", .data = rpi_3_ids },
+	{ .compatible = "raspberrypi,3-model-b", .data = rpi_3_ids },
+	{ .compatible = "raspberrypi,3-model-b-plus", .data = rpi_3_ids },
+	{ .compatible = "raspberrypi,model-zero-2-w", .data = rpi_3_ids },
+	{ .compatible = "raspberrypi,3-compute-module", .data = rpi_3_ids },
+	{ .compatible = "raspberrypi,3-compute-module-lite", .data = rpi_3_ids },
+
+	/* BCM2711 based Boards */
+	{ .compatible = "raspberrypi,4-model-b", .data = rpi_4_ids },
+	{ .compatible = "raspberrypi,4-compute-module", .data = rpi_4_ids },
+	{ .compatible = "raspberrypi,4-compute-module-s", .data = rpi_4_ids },
+	{ .compatible = "raspberrypi,400", .data = rpi_4_ids },
+
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(rpi_of_match);
+
+static struct driver rpi_board_driver = {
+	.name = "board-rpi",
+	.probe = rpi_devices_probe,
+	.of_compatible = DRV_OF_COMPAT(rpi_of_match),
+};
+late_platform_driver(rpi_board_driver);
diff --git a/arch/arm/boards/reflex-achilles/Makefile b/arch/arm/boards/reflex-achilles/Makefile
index 092c31d6b2..5678718188 100644
--- a/arch/arm/boards/reflex-achilles/Makefile
+++ b/arch/arm/boards/reflex-achilles/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
diff --git a/arch/arm/boards/reflex-achilles/board.c b/arch/arm/boards/reflex-achilles/board.c
index 2b8186e19f..96da18f22e 100644
--- a/arch/arm/boards/reflex-achilles/board.c
+++ b/arch/arm/boards/reflex-achilles/board.c
@@ -1,7 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <io.h>
 #include <bbu.h>
+#include <mach/socfpga/arria10-system-manager.h>
 
 static int achilles_init(void)
 {
@@ -12,7 +15,7 @@ static int achilles_init(void)
 	if (!of_machine_is_compatible("reflex,achilles"))
 		return 0;
 
-	pbl_index = readl(0xFFD06210);
+	pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD);
 
 	pr_debug("Current barebox instance %d\n", pbl_index);
 
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
index f910b67d5f..12ead6d6dd 100644
--- a/arch/arm/boards/reflex-achilles/lowlevel.c
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <io.h>
@@ -8,34 +10,39 @@
 #include <asm/unaligned.h>
 #include <debug_ll.h>
 #include <pbl.h>
-#include <mach/arria10-sdram.h>
-#include <mach/arria10-regs.h>
-#include <mach/arria10-reset-manager.h>
-#include <mach/arria10-clock-manager.h>
-#include <mach/arria10-pinmux.h>
-#include <mach/arria10-fpga.h>
+#include <mach/socfpga/arria10-sdram.h>
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-reset-manager.h>
+#include <mach/socfpga/arria10-clock-manager.h>
+#include <mach/socfpga/arria10-pinmux.h>
+#include <mach/socfpga/arria10-fpga.h>
+#include <mach/socfpga/init.h>
 #include "pll-config-arria10.c"
 #include "pinmux-config-arria10.c"
-#include <mach/generic.h>
+#include <mach/socfpga/generic.h>
 
 #define BAREBOX_PART 0
 #define BITSTREAM_PART 1
 #define BAREBOX1_OFFSET    SZ_1M
-#define BAREBOX2_OFFSET    BAREBOX1_OFFSET + SZ_512K
-#define BAREBOX3_OFFSET    BAREBOX2_OFFSET + SZ_512K
-#define BAREBOX4_OFFSET    BAREBOX3_OFFSET + SZ_512K
+#define BAREBOX2_OFFSET    (BAREBOX1_OFFSET + SZ_512K)
+#define BAREBOX3_OFFSET    (BAREBOX2_OFFSET + SZ_512K)
+#define BAREBOX4_OFFSET    (BAREBOX3_OFFSET + SZ_512K)
+// Offset from the start of the second partition on the eMMC.
 #define BITSTREAM1_OFFSET  0x0
-#define BITSTREAM2_OFFSET  BITSTREAM1_OFFSET + SZ_32M
+#define BITSTREAM2_OFFSET  (BITSTREAM1_OFFSET + SZ_32M)
+
+extern char __dtb_z_socfpga_arria10_achilles_start[];
 
-extern char __dtb_socfpga_arria10_achilles_start[];
+#define ARRIA10_STACKTOP	(ARRIA10_OCRAM_ADDR + SZ_256K)
 
-static noinline void achilles_start(void)
+ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0, r1, r2)
 {
 	int pbl_index = 0;
 	int barebox = 0;
 	int bitstream = 0;
 
-	arm_early_mmu_cache_invalidate();
+	arm_cpu_lowlevel_init();
+	arria10_cpu_lowlevel_init();
 
 	relocate_to_current_adr();
 	setup_c();
@@ -74,31 +81,21 @@ static noinline void achilles_start(void)
 	arria10_start_image(barebox);
 }
 
-ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2)
-{
-	arm_cpu_lowlevel_init();
-	arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K);
-	achilles_start();
-}
-
 ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
 {
 	void *fdt;
 
-	fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
+	fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset();
 
 	barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
 }
 
-ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2)
+ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_bringup, ARRIA10_STACKTOP, r0, r1, r2)
 {
 	void *fdt;
 
 	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K);
-
-	arm_early_mmu_cache_invalidate();
+	arria10_cpu_lowlevel_init();
 
 	relocate_to_current_adr();
 	setup_c();
@@ -112,7 +109,7 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2)
 
 	arria10_ddr_calibration_sequence();
 
-	fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
+	fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset();
 
 	barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
index b6a72304b6..aa65770fdd 100644
--- a/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
+++ b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
@@ -1,4 +1,6 @@
-#include <mach/arria10-pinmux.h>
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <mach/socfpga/arria10-pinmux.h>
 
 static uint32_t pinmux[] = {
 [arria10_pinmux_shared_io_q4_12] = 8,
diff --git a/arch/arm/boards/reflex-achilles/pll-config-arria10.c b/arch/arm/boards/reflex-achilles/pll-config-arria10.c
index 9da41ecdf2..35d475bcfb 100644
--- a/arch/arm/boards/reflex-achilles/pll-config-arria10.c
+++ b/arch/arm/boards/reflex-achilles/pll-config-arria10.c
@@ -1,4 +1,6 @@
-#include <mach/arria10-clock-manager.h>
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <mach/socfpga/arria10-clock-manager.h>
 
 static struct arria10_mainpll_cfg mainpll_cfg = {
 	.cntr15clk_cnt = 900,
diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/.gitignore b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/.gitignore
new file mode 100644
index 0000000000..f458f794b5
--- /dev/null
+++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/.gitignore
@@ -0,0 +1 @@
+sdram-init.bin
diff --git a/arch/arm/boards/friendlyarm-tiny210/Makefile b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/Makefile
index 7deb178739..01c7a259e9 100644
--- a/arch/arm/boards/friendlyarm-tiny210/Makefile
+++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/Makefile
@@ -1,2 +1,2 @@
-obj-y += tiny210.o
+obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c
new file mode 100644
index 0000000000..94d1dac2c2
--- /dev/null
+++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#define pr_fmt(fmt) "rk3568-r2pro: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <mach/rockchip/bbu.h>
+#include <aiodev.h>
+#include <bootsource.h>
+#include <environment.h>
+#include <globalvar.h>
+#include <magicvar.h>
+#include <deep-probe.h>
+
+static bool machine_is_bpi_r2pro = false;
+
+static int rk3568_bpi_r2pro_probe(struct device *dev)
+{
+	enum bootsource bootsource = bootsource_get();
+	int instance = bootsource_get_instance();
+
+	barebox_set_model("BPI R2PRO");
+	barebox_set_hostname("bpi-r2pro");
+	machine_is_bpi_r2pro = true;
+
+	if (bootsource == BOOTSOURCE_MMC && instance == 0)
+		of_device_enable_path("/chosen/environment-sd");
+	else
+		of_device_enable_path("/chosen/environment-emmc");
+
+	rk3568_bbu_mmc_register("sd", 0, "/dev/mmc0");
+	rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT,
+				"/dev/mmc1");
+
+	return 0;
+}
+
+static const struct of_device_id rk3568_bpi_r2pro_of_match[] = {
+	{ .compatible = "rockchip,rk3568-bpi-r2pro" },
+	{ /* Sentinel */},
+};
+
+static struct driver rk3568_bpi_r2pro_board_driver = {
+	.name = "board-rk3568-bpi-r2pro",
+	.probe = rk3568_bpi_r2pro_probe,
+	.of_compatible = rk3568_bpi_r2pro_of_match,
+};
+coredevice_platform_driver(rk3568_bpi_r2pro_board_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(rk3568_bpi_r2pro_of_match);
+
+static int rk3568_bpi_r2pro_detect_hwid(void)
+{
+	int ret;
+	int hwid_voltage;
+	struct aiochannel *hwid_chan;
+	char *hwid;
+
+	if (!IS_ENABLED(CONFIG_AIODEV))
+		return 0;
+
+	if (!machine_is_bpi_r2pro)
+		return 0;
+
+	hwid_chan = aiochannel_by_name("aiodev0.in_value1_mV");
+	if (IS_ERR(hwid_chan)) {
+		ret = PTR_ERR(hwid_chan);
+		goto err_hwid;
+	}
+
+	ret = aiochannel_get_value(hwid_chan, &hwid_voltage);
+	if (ret)
+		goto err_hwid;
+
+	pr_info("hwid_voltage: %d\n", hwid_voltage);
+
+	if (hwid_voltage == 1800)
+		hwid = "V00";
+	else
+		hwid = "unknown";
+
+	pr_info("Detected RK3568 BananaPi R2 Pro %s\n", hwid);
+
+	globalvar_add_simple("board.hwid", hwid);
+
+	return 0;
+
+err_hwid:
+	pr_err("couldn't retrieve hardware ID\n");
+	return ret;
+}
+late_initcall(rk3568_bpi_r2pro_detect_hwid);
+
+BAREBOX_MAGICVAR(global.board.hwid, "The board hardware ID");
diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c
new file mode 100644
index 0000000000..12c2445287
--- /dev/null
+++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <asm/barebox-arm.h>
+#include <mach/rockchip/hardware.h>
+#include <mach/rockchip/atf.h>
+#include <debug_ll.h>
+#include <mach/rockchip/rockchip.h>
+
+extern char __dtb_rk3568_bpi_r2_pro_start[];
+
+ENTRY_FUNCTION(start_rk3568_bpi_r2pro, r0, r1, r2)
+{
+	putc_ll('>');
+
+	/*
+	 * set iodomain vccio6 to 1.8V needed for GMAC1 to work.
+	 * vccio4 (gmac0/switch) needs to stay at 3v3 (default)
+	 * FIXME: This is done by the io-domain driver as well, but there
+	 * currently is no mechanism to make sure the driver gets probed
+	 * before its consumers. Remove this setup once this issue is
+	 * resolved.
+	 */
+	//set bit 6 in PMU_GRF_IO_VSEL0 for vccio6 1v8
+	writel(RK_SETBITS(BIT(6)), PMU_GRF_IO_VSEL0);
+	//clear bit 6 for 3v3 as it was set to 1v8
+	writel(RK_CLRBITS(BIT(6)), PMU_GRF_IO_VSEL1);
+
+	if (current_el() == 3)
+		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
+	else
+		relocate_to_current_adr();
+
+	setup_c();
+
+	rk3568_barebox_entry(__dtb_rk3568_bpi_r2_pro_start);
+}
diff --git a/arch/arm/boards/rockchip-rk3568-evb/.gitignore b/arch/arm/boards/rockchip-rk3568-evb/.gitignore
new file mode 100644
index 0000000000..f458f794b5
--- /dev/null
+++ b/arch/arm/boards/rockchip-rk3568-evb/.gitignore
@@ -0,0 +1 @@
+sdram-init.bin
diff --git a/arch/arm/boards/rockchip-rk3568-evb/Makefile b/arch/arm/boards/rockchip-rk3568-evb/Makefile
new file mode 100644
index 0000000000..da63d2625f
--- /dev/null
+++ b/arch/arm/boards/rockchip-rk3568-evb/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/rockchip-rk3568-evb/board.c b/arch/arm/boards/rockchip-rk3568-evb/board.c
new file mode 100644
index 0000000000..f404af217b
--- /dev/null
+++ b/arch/arm/boards/rockchip-rk3568-evb/board.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#define pr_fmt(fmt) "rk3568-evb: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <mach/rockchip/bbu.h>
+#include <aiodev.h>
+#include <bootsource.h>
+#include <environment.h>
+#include <globalvar.h>
+#include <magicvar.h>
+#include <deep-probe.h>
+
+static bool machine_is_rk3568_evb = false;
+
+static int rk3568_evb_probe(struct device *dev)
+{
+	enum bootsource bootsource = bootsource_get();
+	int instance = bootsource_get_instance();
+
+	barebox_set_model("Rockchip RK3568 EVB");
+	barebox_set_hostname("rk3568-evb");
+	machine_is_rk3568_evb = true;
+
+	if (bootsource == BOOTSOURCE_MMC && instance == 0)
+		of_device_enable_path("/chosen/environment-sd");
+	else
+		of_device_enable_path("/chosen/environment-emmc");
+
+	rk3568_bbu_mmc_register("sd", 0, "/dev/mmc0");
+	rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT,
+				"/dev/mmc1");
+
+	return 0;
+}
+
+static const struct of_device_id rk3568_evb_of_match[] = {
+	{ .compatible = "rockchip,rk3568-evb1-v10" },
+	{ /* Sentinel */},
+};
+
+static struct driver rk3568_evb_board_driver = {
+	.name = "board-rk3568-evb",
+	.probe = rk3568_evb_probe,
+	.of_compatible = rk3568_evb_of_match,
+};
+coredevice_platform_driver(rk3568_evb_board_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(rk3568_evb_of_match);
+
+static int rk3568_evb_detect_hwid(void)
+{
+	int ret;
+	int evb_hwid_voltage;
+	struct aiochannel *evb_hwid_chan;
+	char *evb_hwid;
+
+	if (!IS_ENABLED(CONFIG_AIODEV))
+		return 0;
+
+	if (!machine_is_rk3568_evb)
+		return 0;
+
+	evb_hwid_chan = aiochannel_by_name("aiodev0.in_value1_mV");
+	if (IS_ERR(evb_hwid_chan)) {
+		ret = PTR_ERR(evb_hwid_chan);
+		goto err_hwid;
+	}
+
+	ret = aiochannel_get_value(evb_hwid_chan, &evb_hwid_voltage);
+	if (ret)
+		goto err_hwid;
+
+	if (evb_hwid_voltage > 1650) {
+		evb_hwid = "1";
+	} else if (evb_hwid_voltage > 1350) {
+		evb_hwid = "2";
+	} else if (evb_hwid_voltage > 1050) {
+		evb_hwid = "3";
+	} else if (evb_hwid_voltage > 750) {
+		evb_hwid = "4";
+	} else if (evb_hwid_voltage > 450) {
+		evb_hwid = "5";
+	} else if (evb_hwid_voltage > 150) {
+		evb_hwid = "6";
+	} else {
+		evb_hwid = "7";
+	}
+	pr_info("Detected RK3568 EVB%s\n", evb_hwid);
+
+	globalvar_add_simple("board.hwid", evb_hwid);
+
+	return 0;
+
+err_hwid:
+	pr_err("couldn't retrieve hardware ID\n");
+	return ret;
+}
+late_initcall(rk3568_evb_detect_hwid);
+
+BAREBOX_MAGICVAR(global.board.hwid, "The board hardware ID");
diff --git a/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c
new file mode 100644
index 0000000000..d5ae70049e
--- /dev/null
+++ b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <asm/barebox-arm.h>
+#include <mach/rockchip/hardware.h>
+#include <mach/rockchip/atf.h>
+#include <debug_ll.h>
+
+extern char __dtb_rk3568_evb1_v10_start[];
+
+ENTRY_FUNCTION(start_rk3568_evb, r0, r1, r2)
+{
+	/*
+	 * Enable vccio4 1.8V and vccio6 1.8V
+	 * Needed for GMAC to work.
+	 * FIXME: This is done by the io-domain driver as well, but there
+	 * currently is no mechanism to make sure the driver gets probed
+	 * before its consumers. Remove this setup once this issue is
+	 * resolved.
+	 */
+	writel(RK_SETBITS(0x50), 0xfdc20140);
+
+	putc_ll('>');
+
+	if (current_el() == 3)
+		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
+	else
+		relocate_to_current_adr();
+
+	setup_c();
+
+	rk3568_barebox_entry(__dtb_rk3568_evb1_v10_start);
+}
diff --git a/arch/arm/boards/sama5d27-giantboard/Makefile b/arch/arm/boards/sama5d27-giantboard/Makefile
index f5869c4839..e2c6a3adf6 100644
--- a/arch/arm/boards/sama5d27-giantboard/Makefile
+++ b/arch/arm/boards/sama5d27-giantboard/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
 bbenv-y += defaultenv-giantboard
diff --git a/arch/arm/boards/sama5d27-giantboard/lowlevel.c b/arch/arm/boards/sama5d27-giantboard/lowlevel.c
index ee8297fa45..49540bede0 100644
--- a/arch/arm/boards/sama5d27-giantboard/lowlevel.c
+++ b/arch/arm/boards/sama5d27-giantboard/lowlevel.c
@@ -5,17 +5,17 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/barebox-arm.h>
-#include <mach/sama5d2_ll.h>
-#include <mach/xload.h>
-#include <mach/sama5d2-sip-ddramc.h>
-#include <mach/iomux.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/sama5d2_ll.h>
+#include <mach/at91/xload.h>
+#include <mach/at91/sama5d2-sip-ddramc.h>
+#include <mach/at91/iomux.h>
 #include <debug_ll.h>
 
 /* PCK = 492MHz, MCK = 164MHz */
 #define MASTER_CLOCK	164000000
 
-SAMA5_ENTRY_FUNCTION(start_sama5d27_giantboard_xload_mmc, r4)
+SAMA5D2_ENTRY_FUNCTION(start_sama5d27_giantboard_xload_mmc, r4)
 {
 	void __iomem *dbgu_base;
 
@@ -36,7 +36,7 @@ SAMA5_ENTRY_FUNCTION(start_sama5d27_giantboard_xload_mmc, r4)
 
 extern char __dtb_z_at91_sama5d27_giantboard_start[];
 
-SAMA5_ENTRY_FUNCTION(start_sama5d27_giantboard, r4)
+SAMA5D2_ENTRY_FUNCTION(start_sama5d27_giantboard, r4)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/sama5d27-som1/Makefile b/arch/arm/boards/sama5d27-som1/Makefile
index 092c31d6b2..96cd8f520f 100644
--- a/arch/arm/boards/sama5d27-som1/Makefile
+++ b/arch/arm/boards/sama5d27-som1/Makefile
@@ -1,2 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
+bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-sama5d27-som1
diff --git a/arch/arm/boards/sama5d27-som1/board.c b/arch/arm/boards/sama5d27-som1/board.c
index 00c0e92a5d..6fa903bca4 100644
--- a/arch/arm/boards/sama5d27-som1/board.c
+++ b/arch/arm/boards/sama5d27-som1/board.c
@@ -5,6 +5,7 @@
 #include <init.h>
 #include <asm/memory.h>
 #include <bbu.h>
+#include <envfs.h>
 #include <bootsource.h>
 #include <of.h>
 
@@ -30,6 +31,9 @@ static int ek_device_init(void)
 				     filetype_arm_barebox);
 	bbu_register_std_file_update("microSD", flags_usd, "/mnt/mmc1.0/barebox.bin",
 				     filetype_arm_barebox);
+
+	defaultenv_append_directory(defaultenv_sama5d27_som1);
+
 	return 0;
 }
 device_initcall(ek_device_init);
diff --git a/arch/arm/boards/sama5d27-som1/defaultenv-sama5d27-som1/nv/dev.wdog0.autoping b/arch/arm/boards/sama5d27-som1/defaultenv-sama5d27-som1/nv/dev.wdog0.autoping
new file mode 100644
index 0000000000..d00491fd7e
--- /dev/null
+++ b/arch/arm/boards/sama5d27-som1/defaultenv-sama5d27-som1/nv/dev.wdog0.autoping
@@ -0,0 +1 @@
+1
diff --git a/arch/arm/boards/sama5d27-som1/lowlevel.c b/arch/arm/boards/sama5d27-som1/lowlevel.c
index b093711918..67300587fe 100644
--- a/arch/arm/boards/sama5d27-som1/lowlevel.c
+++ b/arch/arm/boards/sama5d27-som1/lowlevel.c
@@ -5,12 +5,12 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/barebox-arm.h>
-#include <mach/sama5d2_ll.h>
-#include <mach/iomux.h>
-#include <mach/xload.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/sama5d2_ll.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/xload.h>
 #include <debug_ll.h>
-#include <mach/sama5d2-sip-ddramc.h>
+#include <mach/at91/sama5d2-sip-ddramc.h>
 
 #define RGB_LED_GREEN (1 << 0)
 #define RGB_LED_RED   (1 << 1)
@@ -39,7 +39,7 @@ static void ek_turn_led(unsigned color)
 	}
 }
 
-SAMA5_ENTRY_FUNCTION(start_sama5d27_som1_ek_xload_mmc, r4)
+SAMA5D2_ENTRY_FUNCTION(start_sama5d27_som1_ek_xload_mmc, r4)
 {
 	void __iomem *dbgu_base;
 	sama5d2_lowlevel_init();
@@ -60,7 +60,7 @@ SAMA5_ENTRY_FUNCTION(start_sama5d27_som1_ek_xload_mmc, r4)
 
 extern char __dtb_z_at91_sama5d27_som1_ek_start[];
 
-SAMA5_ENTRY_FUNCTION(start_sama5d27_som1_ek, r4)
+SAMA5D2_ENTRY_FUNCTION(start_sama5d27_som1_ek, r4)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/sama5d3_xplained/Makefile b/arch/arm/boards/sama5d3_xplained/Makefile
index fc6d83be8c..b7d6b2e7fa 100644
--- a/arch/arm/boards/sama5d3_xplained/Makefile
+++ b/arch/arm/boards/sama5d3_xplained/Makefile
@@ -1,3 +1,5 @@
-obj-y += init.o
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-sama5d3_xplained
diff --git a/arch/arm/boards/sama5d3_xplained/board.c b/arch/arm/boards/sama5d3_xplained/board.c
new file mode 100644
index 0000000000..4d908e6b9f
--- /dev/null
+++ b/arch/arm/boards/sama5d3_xplained/board.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <common.h>
+#include <init.h>
+#include <envfs.h>
+#include <mach/at91/at91sam9_smc.h>
+#include <mach/at91/hardware.h>
+#include <linux/clk.h>
+
+static struct sam9_smc_config sama5d3_xplained_nand_smc_config = {
+	.ncs_read_setup		= 1,
+	.nrd_setup		= 2,
+	.ncs_write_setup	= 1,
+	.nwe_setup		= 2,
+
+	.ncs_read_pulse		= 5,
+	.nrd_pulse		= 3,
+	.ncs_write_pulse	= 5,
+	.nwe_pulse		= 3,
+
+	.read_cycle		= 8,
+	.write_cycle		= 8,
+
+	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+				  AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
+	.tdf_cycles		= 3,
+
+	.tclr			= 3,
+	.tadl			= 10,
+	.tar			= 3,
+	.ocms			= 0,
+	.trr			= 4,
+	.twb			= 5,
+	.rbnsel			= 3,
+	.nfsel			= 1
+};
+
+static int sama5d3_xplained_probe(struct device *dev)
+{
+	struct clk *clk;
+
+	barebox_set_hostname("sama5d3_xplained");
+
+	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
+		defaultenv_append_directory(defaultenv_sama5d3_xplained);
+
+	add_generic_device("at91sam9-smc", DEVICE_ID_SINGLE, NULL,
+			   SAMA5D3_BASE_HSMC + 0x600, 0xa0,
+			   IORESOURCE_MEM, NULL);
+
+	clk = clk_lookup("hsmc_clk");
+	if (IS_ERR(clk))
+		dev_warn(dev, "couldn't get hsmc_clk: %pe\n", clk);
+
+	clk_enable(clk);
+
+	/* configure chip-select 3 (NAND) */
+	sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config);
+
+	return 0;
+}
+
+static const struct of_device_id sama5d3_xplained_of_match[] = {
+	{ .compatible = "atmel,sama5d3-xplained" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, sama5d3_xplained_of_match);
+
+static struct driver sama5d3_xplained_board_driver = {
+	.name = "board-sama5d3_xplained",
+	.probe = sama5d3_xplained_probe,
+	.of_compatible = sama5d3_xplained_of_match,
+};
+coredevice_platform_driver(sama5d3_xplained_board_driver);
diff --git a/arch/arm/boards/sama5d3_xplained/init.c b/arch/arm/boards/sama5d3_xplained/init.c
deleted file mode 100644
index b648d71722..0000000000
--- a/arch/arm/boards/sama5d3_xplained/init.c
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2014 Bo Shen <voice.shen@gmail.com>
-
-#include <common.h>
-#include <net.h>
-#include <init.h>
-#include <environment.h>
-#include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <fs.h>
-#include <fcntl.h>
-#include <io.h>
-#include <envfs.h>
-#include <mach/hardware.h>
-#include <nand.h>
-#include <linux/sizes.h>
-#include <linux/mtd/nand.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
-#include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91sam9x5_matrix.h>
-#include <linux/mtd/rawnand.h>
-#include <readkey.h>
-#include <poller.h>
-#include <linux/clk.h>
-#include <linux/phy.h>
-#include <linux/micrel_phy.h>
-
-#if defined(CONFIG_NAND_ATMEL)
-static struct atmel_nand_data nand_pdata = {
-	.ale		= 21,
-	.cle		= 22,
-	.det_pin	= -EINVAL,
-	.rdy_pin	= -EINVAL,
-	.enable_pin	= -EINVAL,
-	.ecc_mode	= NAND_ECC_HW,
-	.has_pmecc	= 1,
-	.pmecc_sector_size = 512,
-	.pmecc_corr_cap = 4,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-	.bus_width_16	= 1,
-#endif
-	.on_flash_bbt	= 1,
-};
-
-static struct sam9_smc_config sama5d3_xplained_nand_smc_config = {
-	.ncs_read_setup		= 1,
-	.nrd_setup		= 2,
-	.ncs_write_setup	= 1,
-	.nwe_setup		= 2,
-
-	.ncs_read_pulse		= 5,
-	.nrd_pulse		= 3,
-	.ncs_write_pulse	= 5,
-	.nwe_pulse		= 3,
-
-	.read_cycle		= 8,
-	.write_cycle		= 8,
-
-	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-	.tdf_cycles		= 3,
-
-	.tclr			= 3,
-	.tadl			= 10,
-	.tar			= 3,
-	.ocms			= 0,
-	.trr			= 4,
-	.twb			= 5,
-	.rbnsel			= 3,
-	.nfsel			= 1
-};
-
-static void ek_add_device_nand(void)
-{
-	struct clk *clk = clk_get(NULL, "smc_clk");
-
-	clk_enable(clk);
-
-	/* setup bus-width (8 or 16) */
-	if (nand_pdata.bus_width_16)
-		sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_16;
-	else
-		sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-	/* configure chip-select 3 (NAND) */
-	sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config);
-
-	at91_add_device_nand(&nand_pdata);
-}
-#else
-static void ek_add_device_nand(void) {}
-#endif
-
-#if defined(CONFIG_DRIVER_NET_MACB)
-static struct macb_platform_data gmac_pdata = {
-	.phy_interface = PHY_INTERFACE_MODE_RGMII,
-	.phy_addr = 7,
-};
-
-static struct macb_platform_data macb_pdata = {
-	.phy_interface = PHY_INTERFACE_MODE_RMII,
-	.phy_addr = 0,
-};
-
-static void ek_add_device_eth(void)
-{
-	at91_add_device_eth(0, &gmac_pdata);
-	at91_add_device_eth(1, &macb_pdata);
-}
-#else
-static void ek_add_device_eth(void) {}
-#endif
-
-#if defined(CONFIG_MCI_ATMEL)
-/*
- * MCI (SD/MMC)
- */
-static struct atmel_mci_platform_data mci0_data = {
-	.bus_width	= 8,
-	.detect_pin	= AT91_PIN_PE0,
-	.wp_pin		= -EINVAL,
-};
-
-static void ek_add_device_mci(void)
-{
-	/* MMC0 */
-	at91_add_device_mci(0, &mci0_data);
-}
-#else
-static void ek_add_device_mci(void) {}
-#endif
-
-#ifdef CONFIG_LED_GPIO
-struct gpio_led leds[] = {
-	{
-		.gpio	= AT91_PIN_PE23,
-		.active_low	= 1,
-		.led	= {
-			.name = "d2",
-		},
-	}, {
-		.gpio	= AT91_PIN_PE24,
-		.active_low	= 1,
-		.led	= {
-			.name = "d3",
-		},
-	},
-};
-
-static void ek_add_led(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(leds); i++) {
-		at91_set_gpio_output(leds[i].gpio, leds[i].active_low);
-		led_gpio_register(&leds[i]);
-	}
-	led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led);
-}
-#else
-static void ek_add_led(void) {}
-#endif
-
-static int sama5d3_xplained_mem_init(void)
-{
-	at91_add_device_sdram(0);
-
-	return 0;
-}
-mem_initcall(sama5d3_xplained_mem_init);
-
-static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = {
-	{
-		.offset = 0x00000,
-		.size = SZ_256K,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "at91bootstrap_raw",
-		.bbname = "at91bootstrap",
-	}, {
-		.offset = DEVFS_PARTITION_APPEND, /* 256 KiB */
-		.size = SZ_256K + SZ_128K,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "self_raw",
-		.bbname = "self0",
-	},
-	/* hole of 128 KiB */
-	{
-		.offset = SZ_512K + SZ_256K,
-		.size = SZ_256K,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "env_raw",
-		.bbname = "env0",
-	}, {
-		.offset = DEVFS_PARTITION_APPEND, /* 1 MiB */
-		.size = SZ_256K,
-		.flags = DEVFS_PARTITION_FIXED,
-		.name = "env_raw1",
-		.bbname = "env1",
-	}, {
-		/* sentinel */
-	}
-};
-
-static int sama5d3_xplained_devices_init(void)
-{
-	ek_add_device_nand();
-	ek_add_led();
-	ek_add_device_eth();
-	ek_add_device_mci();
-
-	devfs_create_partitions("nand0", sama5d3_xplained_nand0_partitions);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_sama5d3_xplained);
-
-	return 0;
-}
-device_initcall(sama5d3_xplained_devices_init);
-
-static int sama5d3_xplained_console_init(void)
-{
-	barebox_set_model("Atmel sama5d3_xplained");
-	barebox_set_hostname("sama5d3_xplained");
-
-	at91_register_uart(0, 0);
-
-	return 0;
-}
-console_initcall(sama5d3_xplained_console_init);
-
-static int sama5d3_xplained_main_clock(void)
-{
-	at91_set_main_clock(12000000);
-
-	return 0;
-}
-pure_initcall(sama5d3_xplained_main_clock);
diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c
index 28c07d5053..d66b10fa8f 100644
--- a/arch/arm/boards/sama5d3_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c
@@ -1,23 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
 /*
- * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2
+ * Copyright (C) 2014, Atmel Corporation
+ * Copyright (C) 2018 Ahmad Fatoum, Pengutronix
  */
 
 #include <common.h>
 #include <init.h>
 
 #include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <debug_ll.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/sama5d3.h>
+#include <mach/at91/sama5d3-xplained-ddramc.h>
+#include <mach/at91/xload.h>
 
-#include <mach/at91_ddrsdrc.h>
-#include <mach/hardware.h>
+/* PCK = 528MHz, MCK = 132MHz */
+#define MASTER_CLOCK	132000000
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+static void dbgu_init(void)
 {
-	arm_cpu_lowlevel_init();
+	void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
 
-	arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE);
+	sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB);
 
-	barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(), NULL);
+	at91_mux_pio3_pin(pio, pin_to_mask(AT91_PIN_PB31), AT91_MUX_PERIPH_A, 0);
+
+	sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU);
+	at91_dbgu_setup_ll(IOMEM(AT91_BASE_DBGU1), MASTER_CLOCK, 115200);
+
+	putc_ll('>');
+	pbl_set_putc(at91_dbgu_putc, IOMEM(AT91_BASE_DBGU1));
+}
+
+SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained_xload_mmc, r4)
+{
+	sama5d3_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	dbgu_init();
+
+	sama5d3_udelay_init(MASTER_CLOCK);
+	sama5d3_xplained_ddrconf();
+
+	sama5d3_atmci_start_image(0, MASTER_CLOCK, 0);
+}
+
+extern char __dtb_z_at91_sama5d3_xplained_start[];
+
+SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained, r4)
+{
+	void *fdt;
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		dbgu_init();
+
+	fdt = __dtb_z_at91_sama5d3_xplained_start + get_runtime_offset();
+
+	barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
 }
diff --git a/arch/arm/boards/sama5d3xek/Makefile b/arch/arm/boards/sama5d3xek/Makefile
index 6ed914fc0a..9691f07917 100644
--- a/arch/arm/boards/sama5d3xek/Makefile
+++ b/arch/arm/boards/sama5d3xek/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 obj-$(CONFIG_W1) += hw_version.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/sama5d3xek/hw_version.c b/arch/arm/boards/sama5d3xek/hw_version.c
index 03c8df2cad..c64d4566c6 100644
--- a/arch/arm/boards/sama5d3xek/hw_version.c
+++ b/arch/arm/boards/sama5d3xek/hw_version.c
@@ -151,7 +151,7 @@ static void at91sama5d3xek_devices_detect_one(const char *name)
 	struct one_wire_info info;
 	struct board_info* binfo;
 	struct vendor_info* vinfo;
-	struct device_d *dev = NULL;
+	struct device *dev = NULL;
 	char str[16];
 	char *bname, *vname;
 	u8 vendor_id = 0;
diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c
index 6e8fbea4c8..b75856198e 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -6,24 +6,23 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91sam9x5_matrix.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
+#include <mach/at91/at91sam9x5_matrix.h>
 #include <input/qt1070.h>
 #include <readkey.h>
 #include <poller.h>
diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c
index 28c07d5053..fe5f172127 100644
--- a/arch/arm/boards/sama5d3xek/lowlevel.c
+++ b/arch/arm/boards/sama5d3xek/lowlevel.c
@@ -10,8 +10,8 @@
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
-#include <mach/at91_ddrsdrc.h>
-#include <mach/hardware.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/hardware.h>
 
 void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
 {
diff --git a/arch/arm/boards/sama5d4_wifx/Makefile b/arch/arm/boards/sama5d4_wifx/Makefile
new file mode 100644
index 0000000000..5678718188
--- /dev/null
+++ b/arch/arm/boards/sama5d4_wifx/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/sama5d4_wifx/board.c b/arch/arm/boards/sama5d4_wifx/board.c
new file mode 100644
index 0000000000..028bedcfb0
--- /dev/null
+++ b/arch/arm/boards/sama5d4_wifx/board.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <deep-probe.h>
+#include <bootsource.h>
+#include <driver.h>
+#include <init.h>
+#include <bbu.h>
+#include <of.h>
+
+static int wifx_l1_probe(struct device *dev)
+{
+	int flags_sd = 0;
+
+	if (bootsource_get() == BOOTSOURCE_NAND) {
+		of_device_enable_path("/chosen/environment-nand");
+	} else {
+		of_device_enable_path("/chosen/environment-microsd");
+		flags_sd = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	bbu_register_std_file_update("sd", flags_sd, "/mnt/mmc1.0/barebox.bin",
+				     filetype_arm_barebox);
+
+	return 0;
+}
+
+static const struct of_device_id wifx_l1_of_match[] = {
+	{ .compatible = "wifx,l1" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(wifx_l1_of_match);
+
+static struct driver wifx_l1_board_driver = {
+	.name = "board-lxa-mc1",
+	.probe = wifx_l1_probe,
+	.of_compatible = wifx_l1_of_match,
+};
+device_platform_driver(wifx_l1_board_driver);
diff --git a/arch/arm/boards/sama5d4_wifx/lowlevel.c b/arch/arm/boards/sama5d4_wifx/lowlevel.c
new file mode 100644
index 0000000000..c47b14c55b
--- /dev/null
+++ b/arch/arm/boards/sama5d4_wifx/lowlevel.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+#include <debug_ll.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/ddramc.h>
+
+SAMA5D4_ENTRY_FUNCTION(start_sama5d4_wifx_l1, r4)
+{
+	extern char __dtb_z_at91_sama5d4_wifx_l1_start[];
+	void *fdt;
+
+	putc_ll('>');
+
+	fdt = __dtb_z_at91_sama5d4_wifx_l1_start + get_runtime_offset();
+
+	sama5d4_barebox_entry(r4, fdt);
+}
diff --git a/arch/arm/boards/sama5d4_xplained/Makefile b/arch/arm/boards/sama5d4_xplained/Makefile
index 8873dfc22c..eece4cc381 100644
--- a/arch/arm/boards/sama5d4_xplained/Makefile
+++ b/arch/arm/boards/sama5d4_xplained/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += sama5d4_xplained.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c b/arch/arm/boards/sama5d4_xplained/lowlevel.c
index 3c58a08f3b..183bd9c5a9 100644
--- a/arch/arm/boards/sama5d4_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c
@@ -10,8 +10,8 @@
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
-#include <mach/at91_ddrsdrc.h>
-#include <mach/hardware.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/hardware.h>
 
 void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
 {
diff --git a/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c b/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c
index b7c9c49ded..c88f0d090a 100644
--- a/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c
+++ b/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c
@@ -12,22 +12,21 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <partition.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91sam9x5_matrix.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
+#include <mach/at91/at91sam9x5_matrix.h>
 #include <input/qt1070.h>
 #include <readkey.h>
 #include <spi/spi.h>
diff --git a/arch/arm/boards/sama5d4ek/Makefile b/arch/arm/boards/sama5d4ek/Makefile
index 152750bbe0..82ffe9771c 100644
--- a/arch/arm/boards/sama5d4ek/Makefile
+++ b/arch/arm/boards/sama5d4ek/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += sama5d4ek.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c
index 3c58a08f3b..183bd9c5a9 100644
--- a/arch/arm/boards/sama5d4ek/lowlevel.c
+++ b/arch/arm/boards/sama5d4ek/lowlevel.c
@@ -10,8 +10,8 @@
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
-#include <mach/at91_ddrsdrc.h>
-#include <mach/hardware.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/hardware.h>
 
 void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
 {
diff --git a/arch/arm/boards/sama5d4ek/sama5d4ek.c b/arch/arm/boards/sama5d4ek/sama5d4ek.c
index 3673d4816b..0dda34614a 100644
--- a/arch/arm/boards/sama5d4ek/sama5d4ek.c
+++ b/arch/arm/boards/sama5d4ek/sama5d4ek.c
@@ -12,22 +12,21 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <partition.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91sam9x5_matrix.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
+#include <mach/at91/at91sam9x5_matrix.h>
 #include <input/qt1070.h>
 #include <readkey.h>
 #include <spi/spi.h>
diff --git a/arch/arm/boards/scb9328/Makefile b/arch/arm/boards/scb9328/Makefile
index 8e1c7ef7a5..5c13dddc06 100644
--- a/arch/arm/boards/scb9328/Makefile
+++ b/arch/arm/boards/scb9328/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 lwl-y += lowlevel_init.o lowlevel.o
 obj-y += scb9328.o
diff --git a/arch/arm/boards/scb9328/lowlevel.c b/arch/arm/boards/scb9328/lowlevel.c
index a2057f0c6b..d8b0d1cf18 100644
--- a/arch/arm/boards/scb9328/lowlevel.c
+++ b/arch/arm/boards/scb9328/lowlevel.c
@@ -1,10 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <common.h>
-#include <mach/imx1-regs.h>
-#include <mach/iomux-v1.h>
-#include <mach/iomux-mx1.h>
+#include <mach/imx/imx1-regs.h>
+#include <mach/imx/iomux-v1.h>
+#include <mach/imx/iomux-mx1.h>
 #include <asm/barebox-arm.h>
-#include <mach/esdctl.h>
+#include <mach/imx/esdctl.h>
 
 extern char __dtb_imx1_scb9328_start[];
 
diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S
index eff5a5088f..6c23d2cfea 100644
--- a/arch/arm/boards/scb9328/lowlevel_init.S
+++ b/arch/arm/boards/scb9328/lowlevel_init.S
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 // SPDX-FileCopyrightText: 2004 Sascha Hauer, Synertronixx GmbH
 
-#include <mach/imx1-regs.h>
+#include <mach/imx/imx1-regs.h>
 #include <asm/barebox-arm-head.h>
 
 #define CFG_MPCTL0_VAL 0x00321431
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index 1c78fac441..4c57f47996 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -5,16 +5,15 @@
 #include <net.h>
 #include <init.h>
 #include <environment.h>
-#include <generated/mach-types.h>
-#include <mach/imx1-regs.h>
+#include <asm/mach-types.h>
+#include <mach/imx/imx1-regs.h>
 #include <asm/armlinux.h>
-#include <mach/weim.h>
+#include <mach/imx/weim.h>
 #include <io.h>
-#include <partition.h>
 #include <fs.h>
 #include <envfs.h>
-#include <mach/iomux-mx1.h>
-#include <mach/devices-imx1.h>
+#include <mach/imx/iomux-mx1.h>
+#include <mach/imx/devices-imx1.h>
 
 static int scb9328_devices_init(void)
 {
diff --git a/arch/arm/boards/seeed-odyssey/Makefile b/arch/arm/boards/seeed-odyssey/Makefile
index 092c31d6b2..5678718188 100644
--- a/arch/arm/boards/seeed-odyssey/Makefile
+++ b/arch/arm/boards/seeed-odyssey/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
diff --git a/arch/arm/boards/seeed-odyssey/board.c b/arch/arm/boards/seeed-odyssey/board.c
index 8c011898a3..5befd32664 100644
--- a/arch/arm/boards/seeed-odyssey/board.c
+++ b/arch/arm/boards/seeed-odyssey/board.c
@@ -3,11 +3,11 @@
 #include <linux/sizes.h>
 #include <init.h>
 #include <asm/memory.h>
-#include <mach/bbu.h>
+#include <mach/stm32mp/bbu.h>
 #include <bootsource.h>
 #include <of.h>
 
-static int odyssey_som_probe(struct device_d *dev)
+static int odyssey_som_probe(struct device *dev)
 {
 	int flags;
 	int instance = bootsource_get_instance();
@@ -31,8 +31,9 @@ static const struct of_device_id odyssey_som_of_match[] = {
 	{ .compatible = "seeed,stm32mp157c-odyssey-som" },
 	{ /* sentinel */ },
 };
+MODULE_DEVICE_TABLE(of, odyssey_som_of_match);
 
-static struct driver_d odyssey_som_driver = {
+static struct driver odyssey_som_driver = {
 	.name = "odyssey-som",
 	.probe = odyssey_som_probe,
 	.of_compatible = odyssey_som_of_match,
diff --git a/arch/arm/boards/seeed-odyssey/lowlevel.c b/arch/arm/boards/seeed-odyssey/lowlevel.c
index 5ab1639dfe..a0e6173d49 100644
--- a/arch/arm/boards/seeed-odyssey/lowlevel.c
+++ b/arch/arm/boards/seeed-odyssey/lowlevel.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include <common.h>
-#include <mach/entry.h>
+#include <mach/stm32mp/entry.h>
 #include <debug_ll.h>
 
 extern char __dtb_z_stm32mp157c_odyssey_start[];
diff --git a/arch/arm/boards/skov-arm9cpu/Makefile b/arch/arm/boards/skov-arm9cpu/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/skov-arm9cpu/Makefile
+++ b/arch/arm/boards/skov-arm9cpu/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/skov-arm9cpu/board.c b/arch/arm/boards/skov-arm9cpu/board.c
index 8d5eadbb9a..20507922cb 100644
--- a/arch/arm/boards/skov-arm9cpu/board.c
+++ b/arch/arm/boards/skov-arm9cpu/board.c
@@ -7,32 +7,42 @@
 #include <envfs.h>
 #include <init.h>
 #include <gpio.h>
+#include <bootsource.h>
 
 #include <linux/sizes.h>
 
-#include <mach/at91sam9263_matrix.h>
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/hardware.h>
-#include <mach/iomux.h>
+#include <mach/at91/at91sam9263_matrix.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9_smc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/iomux.h>
 
-static struct sam9_smc_config ek_nand_smc_config = {
-	.ncs_read_setup		= 0,
-	.nrd_setup		= 1,
+static struct sam9_smc_config skov_nor_smc_config = {
+	/* Setup time is 2 cycles after the CS signal */
+	.nwe_setup		= 2,
 	.ncs_write_setup	= 0,
-	.nwe_setup		= 1,
+	.nrd_setup		= 2,
+	.ncs_read_setup		= 0,
 
-	.ncs_read_pulse		= 3,
-	.nrd_pulse		= 3,
-	.ncs_write_pulse	= 3,
-	.nwe_pulse		= 3,
+	/* Set pulse long enough - pulse should be a bit shorter than the cycle */
+	.nwe_pulse		= 10,
+	.ncs_write_pulse	= 12,
+	.nrd_pulse		= 10,
+	.ncs_read_pulse		= 12,
 
-	.read_cycle		= 5,
-	.write_cycle		= 5,
+	/* Set cycle long enougth at least 12 Cycles->120ns plus a little extra */
+	.write_cycle		= 0x13,
+	.read_cycle		= 0x13,
 
+	/* Set mode: 16Bit bus width, enable read and write
+	 *   Note: pagemode + 32 byte pages do not work with the 29GL512P flash
+	 */
 	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-				  AT91_SMC_EXNWMODE_DISABLE,
-	.tdf_cycles		= 2,
+				  AT91_SMC_EXNWMODE_DISABLE |
+				  AT91_SMC_BAT_WRITE |
+				  AT91_SMC_DBW_16 |
+				  AT91_SMC_TDFMODE,
+	.tdf_cycles		= 1,
 };
 
 BAREBOX_MAGICVAR(board.mem, "The detected memory size in MiB");
@@ -45,26 +55,29 @@ static int mem;
  * But is required before we start the other drives.
  * Use device_initcall() to maintain this order.
  */
-static int skov_arm9_probe(struct device_d *dev)
+static int skov_arm9_probe(struct device *dev)
 {
-	unsigned long csa;
+	barebox_set_hostname("skov-arm9cpu");
 
 	add_generic_device("at91sam9-smc", 0, NULL, AT91SAM9263_BASE_SMC0, 0x200,
 			   IORESOURCE_MEM, NULL);
 	add_generic_device("at91sam9-smc", 1, NULL, AT91SAM9263_BASE_SMC1, 0x200,
 			   IORESOURCE_MEM, NULL);
 
-	csa = readl(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
-	csa |= AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
-	writel(csa, AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
-
-	/* configure chip-select 3 (NAND) */
-	sam9_smc_configure(0, 3, &ek_nand_smc_config);
+	/* configure chip-select 0 (NOR) */
+	sam9_smc_configure(0, 0, &skov_nor_smc_config);
 
 	mem = at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC0));
 	mem = mem / SZ_1M;
 	globalvar_add_simple_int("board.mem", &mem, "%u");
 
+	/*
+	 * NOR first stage bootloader is at91bootstrap, so if we find traces
+	 * of barebox in on-chip SRAM, it must mean we have booted from SD
+	 */
+	if (is_barebox_arm_head((void *)AT91SAM9263_SRAM0_BASE))
+		bootsource_set_raw(BOOTSOURCE_MMC, BOOTSOURCE_INSTANCE_UNKNOWN);
+
 	return 0;
 }
 
@@ -75,10 +88,11 @@ static __maybe_unused struct of_device_id skov_arm9_ids[] = {
 		/* sentinel */
 	}
 };
+MODULE_DEVICE_TABLE(of, skov_arm9_ids);
 
-static struct driver_d skov_arm9_driver = {
+static struct driver skov_arm9_driver = {
 	.name = "skov-arm9",
 	.probe = skov_arm9_probe,
 	.of_compatible = DRV_OF_COMPAT(skov_arm9_ids),
 };
-device_platform_driver(skov_arm9_driver);
+coredevice_platform_driver(skov_arm9_driver);
diff --git a/arch/arm/boards/skov-arm9cpu/lowlevel.c b/arch/arm/boards/skov-arm9cpu/lowlevel.c
index d335953a73..baf0b7bfc9 100644
--- a/arch/arm/boards/skov-arm9cpu/lowlevel.c
+++ b/arch/arm/boards/skov-arm9cpu/lowlevel.c
@@ -1,127 +1,133 @@
 // SPDX-License-Identifier: GPL-2.0
-// PDX-FileCopyrightText: 2018 Sam Ravnborg <sam@ravnborg.org>
-
-#include <linux/sizes.h>
-
-#include <asm/barebox-arm.h>
-
-#include <mach/at91sam926x_board_init.h>
-#include <mach/at91sam9263_matrix.h>
-
-#define MASTER_PLL_MUL		171
-#define MASTER_PLL_DIV		14
+// SPDX-FileCopyrightText: 2022 Sam Ravnborg <sam@ravnborg.org>
+
+#include <mach/at91/at91sam926x_board_init.h>
+#include <mach/at91/at91sam9263_matrix.h>
+#include <mach/at91/sam92_ll.h>
+#include <mach/at91/xload.h>
+#include <mach/at91/barebox-arm.h>
+#include <linux/build_bug.h>
+
+/* MCK = 20 MHz */
+#define MAIN_CLOCK	200000000
+#define MASTER_CLOCK	(MAIN_CLOCK / 2)	/* PMC_MCKR divides by 2 */
+
+#define PLLA_SETTINGS	(AT91_PMC_PLLA_WR_ERRATA | AT91_PMC_MUL_(49) | AT91_PMC_OUT_2 | \
+			 AT91_PMC_PLLCOUNT_(48) | AT91_PMC_DIV_(4))
+static_assert(PLLA_SETTINGS == 0x2031B004);
+
+#define PLLB_SETTINGS	(AT91_PMC_USBDIV_2 | AT91_PMC_MUL_(5) | AT91_PMC_OUT_0 | \
+			 AT91_PMC_PLLCOUNT_(48) | AT91_PMC_DIV_BYPASS)
+static_assert(PLLB_SETTINGS == 0x10053001);
+
+/*
+ * Check if target is 64 or 128 MB and adjust AT91_SDRAMC_CR
+ * accordingly.
+ * Size      Start      Size(hex)
+ * 64 MB  => 0x20000000 0x4000000
+ * 128 MB => 0x20000000 0x8000000
+ *
+ * If 64 MiB RAM with NC_10 set, then we see holes in the memory, which
+ * is how we detect if memory is 64 or 128 MiB
+ */
+static int check_if_128mb(void)
+{
+	unsigned int *test_adr = (unsigned int *)AT91_CHIPSELECT_1;
+	unsigned int test_val = 0xdeadbee0;
+	unsigned int *p;
+	int i;
+
+	/* Fill up memory with a known pattern */
+	p = test_adr;
+	for (i = 0; i < 0xb00; i++)
+		*p++ = test_val + i;
+
+	/*
+	 * Check that we can read back the values just written
+	 * If one or more fails, we have only 64 MB
+	 */
+	p = test_adr;
+	for (i = 0; i < 0xb00; i++)
+		if (*p++ != (test_val + i))
+			return false;
+
+	return true;
+}
 
-static void __bare_init skovarm9cpu_board_config(struct at91sam926x_board_cfg *cfg)
+static void sam9263_sdramc_init(void)
 {
-	/* Disable Watchdog */
-	cfg->wdt_mr =
-		AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
-		AT91_WDT_WDV |
-		AT91_WDT_WDDIS |
-		AT91_WDT_WDD;
-
-	/* define PDC[31:16] as DATA[31:16] */
-	cfg->ebi_pio_pdr = 0xFFFF0000;
-	/* no pull-up for D[31:16] */
-	cfg->ebi_pio_ppudr = 0xFFFF0000;
-	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-	cfg->ebi_csa =
-		AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
-		AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
-
-	cfg->smc_cs = 0;
-	cfg->smc_mode =
-		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		AT91_SMC_DBW_16 |
-		AT91_SMC_TDFMODE |
-		AT91_SMC_TDF_(6);
-	cfg->smc_cycle =
-		AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
-	cfg->smc_pulse =
-		AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
-		AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
-	cfg->smc_setup =
-		AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
-		AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
-
-	cfg->pmc_mor =
-		AT91_PMC_MOSCEN |
-		(255 << 8);		/* Main Oscillator Start-up Time */
-	cfg->pmc_pllar =
-		AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
-		AT91_PMC_OUT |
-		AT91_PMC_PLLCOUNT |	/* PLL Counter */
-		(2 << 28) |		/* PLL Clock Frequency Range */
-		((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
-	/* PCK/2 = MCK Master Clock from PLLA */
-	cfg->pmc_mckr1 =
-		AT91_PMC_CSS_SLOW |
-		AT91_PMC_PRES_1 |
-		AT91SAM9_PMC_MDIV_2 |
-		AT91_PMC_PDIV_1;
-	/* PCK/2 = MCK Master Clock from PLLA */
-	cfg->pmc_mckr2 =
-		AT91_PMC_CSS_PLLA |
-		AT91_PMC_PRES_1 |
-		AT91SAM9_PMC_MDIV_2 |
-		AT91_PMC_PDIV_1;
-
-	/* SDRAM */
-	/* SDRAMC_TR - Refresh Timer register */
-	cfg->sdrc_tr1 = 0x13C;
-	/* SDRAMC_CR - Configuration register*/
-	cfg->sdrc_cr =
-		AT91_SDRAMC_NC_10 |	/* Assume 128MiB */
-		AT91_SDRAMC_NR_13 |
-		AT91_SDRAMC_NB_4 |
-		AT91_SDRAMC_CAS_3 |
-		AT91_SDRAMC_DBW_32 |
-		(1 <<  8) |		/* Write Recovery Delay */
-		(7 << 12) |		/* Row Cycle Delay */
-		(2 << 16) |		/* Row Precharge Delay */
-		(2 << 20) |		/* Row to Column Delay */
-		(5 << 24) |		/* Active to Precharge Delay */
-		(1 << 28);		/* Exit Self Refresh to Active Delay */
-
-	/* Memory Device Register -> SDRAM */
-	cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
-	/* SDRAM_TR */
-	cfg->sdrc_tr2 = 1200;
-
-	/* user reset enable */
-	cfg->rstc_rmr =
-		AT91_RSTC_KEY |
-		AT91_RSTC_PROCRST |
-		AT91_RSTC_RSTTYP_WAKEUP |
-		AT91_RSTC_RSTTYP_WATCHDOG;
+	void __iomem *piod = IOMEM(AT91SAM9263_BASE_PIOD);
+	static struct at91sam9_sdramc_config config = {
+		.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0),
+		.mr = 0,
+		.tr = (MASTER_CLOCK * 7) / 1000000, // TODO 140 versus 0x13c (316)?
+		.cr = AT91_SDRAMC_NC_10 | AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_2
+		      | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32
+		      | AT91_SDRAMC_TWR_2 | AT91_SDRAMC_TRC_7
+		      | AT91_SDRAMC_TRP_2 | AT91_SDRAMC_TRCD_2
+		      | AT91_SDRAMC_TRAS_5 | AT91_SDRAMC_TXSR_8,
+		.lpr = 0,
+		.mdr = AT91_SDRAMC_MD_SDRAM,
+	};
+
+	/* Define PD[31:16] as DATA[31:16] */
+	at91_mux_gpio_disable(piod, GENMASK(31, 16));
+	/* No pull-up for D[31:16] */
+	at91_mux_set_pullup(piod, GENMASK(31, 16), false);
+	/* PD16 to PD31 are pheripheral A */
+	at91_mux_set_A_periph(piod, GENMASK(31, 16));
+
+	/* EBI0_CSA, CS1 SDRAM, 3.3V memories */
+	setbits_le32(IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA),
+	       AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V | AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC);
+
+	at91sam9_sdramc_initialize(&config, AT91SAM9263_BASE_EBI0_CS1);
+
+	if (!check_if_128mb()) {
+		/* Change number of columns to 9 for 64MB ram. */
+		/* Other parameters does not need to be changed due to chip size. */
+
+		pr_debug("64M variant detected\n");
+
+		/* Clear NC bits */
+		config.cr &= ~AT91_SDRAMC_NC;
+		config.cr |= AT91_SDRAMC_NC_9;
+		at91sam9_sdramc_initialize(&config, AT91SAM9263_BASE_EBI0_CS1);
+	}
 }
 
-static void __bare_init skov_arm9cpu_init(void *fdt)
+static noinline void continue_skov_arm9cpu_xload_mmc(void)
 {
-	struct at91sam926x_board_cfg cfg;
+	sam9263_lowlevel_init(PLLA_SETTINGS, PLLB_SETTINGS);
+	sam92_dbgu_setup_ll(MASTER_CLOCK);
 
-	cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
-	cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
-	cfg.ebi_pio_is_peripha = true;
-	cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
+	sam92_udelay_init(MASTER_CLOCK);
+	sam9263_sdramc_init();
+	sam9263_atmci_start_image(1, MASTER_CLOCK, 0);
+}
 
-	skovarm9cpu_board_config(&cfg);
-	at91sam9263_board_init(&cfg);
+SAM9_ENTRY_FUNCTION(start_skov_arm9cpu_xload_mmc)
+{
+	/* Configure system so we are less constrained */
+	arm_cpu_lowlevel_init();
+	relocate_to_current_adr();
+	setup_c();
 
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
-			  fdt);
+	continue_skov_arm9cpu_xload_mmc();
 }
 
 extern char __dtb_at91_skov_arm9cpu_start[];
 
-ENTRY_FUNCTION(start_skov_arm9cpu, r0, r1, r2)
+AT91_ENTRY_FUNCTION(start_skov_arm9cpu, r0, r1, r2)
 {
 	void *fdt;
 
+	/*
+	 * We may be running after at91bootstrap, so redo the initialization to
+	 * be sure, everything is as we expect it.
+	 */
 	arm_cpu_lowlevel_init();
 
-	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE);
 	fdt = __dtb_at91_skov_arm9cpu_start + get_runtime_offset();
-
-	skov_arm9cpu_init(fdt);
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9263_get_sdram_size(0), fdt);
 }
diff --git a/arch/arm/boards/skov-imx6/Makefile b/arch/arm/boards/skov-imx6/Makefile
index a5e85bc1e1..b6b8b44b84 100644
--- a/arch/arm/boards/skov-imx6/Makefile
+++ b/arch/arm/boards/skov-imx6/Makefile
@@ -1,3 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 obj-pbl-y += version.o
+bbenv-y += defaultenv-skov-imx6
diff --git a/arch/arm/boards/skov-imx6/board.c b/arch/arm/boards/skov-imx6/board.c
index a58172b2b1..8ebb4a6e58 100644
--- a/arch/arm/boards/skov-imx6/board.c
+++ b/arch/arm/boards/skov-imx6/board.c
@@ -2,18 +2,27 @@
 
 #define pr_fmt(fmt) "skov-imx6: " fmt
 
+#include <bootsource.h>
 #include <common.h>
-#include <init.h>
-#include <mach/bbu.h>
+#include <deep-probe.h>
+#include <envfs.h>
 #include <environment.h>
-#include <bootsource.h>
 #include <globalvar.h>
+#include <gpio.h>
+#include <init.h>
+#include <linux/micrel_phy.h>
+#include <mach/imx/bbu.h>
 #include <net.h>
 #include <of_gpio.h>
-#include <gpio.h>
 
 #include "version.h"
 
+struct skov_imx6_priv {
+	struct device *dev;
+};
+
+static struct skov_imx6_priv *skov_priv;
+
 static int eth_of_fixup_node(struct device_node *root, const char *node_path,
 			     const u8 *ethaddr)
 {
@@ -21,24 +30,21 @@ static int eth_of_fixup_node(struct device_node *root, const char *node_path,
 	int ret;
 
 	if (!is_valid_ether_addr(ethaddr)) {
-		unsigned char ethaddr_str[sizeof("xx:xx:xx:xx:xx:xx")];
-
-		ethaddr_to_string(ethaddr, ethaddr_str);
-		pr_err("The mac-address %s is invalid.\n", ethaddr_str);
+		dev_err(skov_priv->dev, "The mac-address %pM is invalid.\n", ethaddr);
 		return -EINVAL;
 	}
 
 	node = of_find_node_by_path_from(root, node_path);
 	if (!node) {
-		pr_err("Did not find node %s to fix up with stored mac-address.\n",
-		       node_path);
+		dev_err(skov_priv->dev, "Did not find node %s to fix up with stored mac-address.\n",
+		        node_path);
 		return -ENOENT;
 	}
 
 	ret = of_set_property(node, "mac-address", ethaddr, ETH_ALEN, 1);
 	if (ret)
-		pr_err("Setting mac-address property of %s failed with: %s.\n",
-		       node->full_name, strerror(-ret));
+		dev_err(skov_priv->dev, "Setting mac-address property of %pOF failed with: %s.\n",
+		        node, strerror(-ret));
 
 	return ret;
 }
@@ -51,7 +57,7 @@ static int eth_of_fixup_node_from_eth_device(struct device_node *root,
 
 	edev = eth_get_byname(ethname);
 	if (!edev) {
-		pr_err("Did not find eth device \"%s\" to copy mac-address from.\n", ethname);
+		dev_err(skov_priv->dev, "Did not find eth device \"%s\" to copy mac-address from.\n", ethname);
 		return -ENOENT;
 	}
 
@@ -65,14 +71,14 @@ static int get_mac_address_from_env_variable(const char *env, u8 ethaddr[ETH_ALE
 
 	ethaddr_str = getenv(env);
 	if (!ethaddr_str) {
-		pr_err("State variable %s storing the mac-address not found.\n", env);
+		dev_err(skov_priv->dev, "State variable %s storing the mac-address not found.\n", env);
 		return -ENOENT;
 	}
 
 	ret = string_to_ethaddr(ethaddr_str, ethaddr);
 	if (ret < 0) {
-		pr_err("Could not convert \"%s\" in state variable %s into mac-address.\n",
-		       ethaddr_str, env);
+		dev_err(skov_priv->dev, "Could not convert \"%s\" in state variable %s into mac-address.\n",
+		        ethaddr_str, env);
 		return -EINVAL;
 	}
 
@@ -87,13 +93,13 @@ static int get_default_mac_address_from_state_node(const char *state_node_path,
 
 	node = of_find_node_by_path(state_node_path);
 	if (!node) {
-		pr_err("Node %s defining the state variable not found.\n", state_node_path);
+		dev_err(skov_priv->dev, "Node %s defining the state variable not found.\n", state_node_path);
 		return -ENOENT;
 	}
 
 	ret = of_property_read_u8_array(node, "default", ethaddr, ETH_ALEN);
 	if (ret) {
-		pr_err("Node %s has no property \"default\" of proper type.\n", state_node_path);
+		dev_err(skov_priv->dev, "Node %s has no property \"default\" of proper type.\n", state_node_path);
 		return -ENOENT;
 	}
 
@@ -303,20 +309,114 @@ static const struct board_description imx6_variants[] = {
 };
 
 static int skov_board_no = -1;
+static bool skov_have_switch = true;
+static const char *no_switch_suffix = "-noswitch";
 
-static int skov_imx6_fixup(struct device_node *root, void *unused)
+static void fixup_noswitch_machine_compatible(struct device_node *root)
 {
-	int ret;
-	const char *val;
-	uint32_t brightness;
+	const char *compat = imx6_variants[skov_board_no].dts_compatible;
+	const char *generic = "skov,imx6";
+	char *buf;
+
+	/* add generic compatible, so systemd&co can make right decisions */
+	buf = xasprintf("%s%s", generic, no_switch_suffix);
+	of_prepend_machine_compatible(root, buf);
+
+	/* add specific compatible as fallback, in case this board has new
+	 * challenges.
+	 */
+	buf = xasprintf("%s%s", compat, no_switch_suffix);
+	of_prepend_machine_compatible(root, buf);
+
+	free(buf);
+}
+
+static void skov_imx6_no_switch(struct device_node *root)
+{
+	const char *fec_alias = "ethernet0";
 	struct device_node *node;
+	int ret;
+
+	fixup_noswitch_machine_compatible(root);
+
+	node = of_find_node_by_alias(root, fec_alias);
+	if (node) {
+		ret = of_device_disable(node);
+		if (ret)
+			dev_warn(skov_priv->dev, "Can't disable %s\n", fec_alias);
+	} else {
+		dev_warn(skov_priv->dev, "Can't find node by alias: %s\n", fec_alias);
+	}
+
+	node = of_find_node_by_alias(root, "mdio-gpio0");
+	if (node) {
+		ret = of_device_disable(node);
+		if (ret)
+			dev_warn(skov_priv->dev, "Can't disable mdio-gpio0 node\n");
+	} else {
+		dev_warn(skov_priv->dev, "Can't find mdio-gpio0 node\n");
+	}
+}
+
+static int skov_imx6_switch_port(struct device_node *root, const char *path)
+{
+	size_t size;
+	char *buf;
+	int ret;
+
+	/* size is, string + '\0' + port number */
+	size = strlen(path) + 2;
+	buf = xzalloc(size);
+	if (!buf)
+		return -ENOMEM;
+
+	ret = snprintf(buf, size, "%s0", path);
+	if (ret < 0)
+		return ret;
+
+	ret = eth_of_fixup_node_from_eth_device(root, buf, "eth0");
+	if (ret)
+		return ret;
+
+	ret = snprintf(buf, size, "%s1", path);
+	if (ret < 0)
+		return ret;
+
+	ret = eth2_of_fixup_node_individually(root, buf, "eth0",
+					      "state.ethaddr.eth2",
+					      "/state/ethaddr/eth2");
+	return ret;
+}
+
+static void skov_imx6_switch(struct device_node *root)
+{
+	const char *old = "/mdio-gpio/ksz8873@3/ports/ports@";
+	const char *new = "/mdio/switch@0/ports/ports@";
+	int ret;
+
+	/* Old DTS variants (pre kernel mainline) use different path. Try first
+	 * the new variant, then fall back to the old one.
+	 */
+	ret = skov_imx6_switch_port(root, new);
+	if (ret) {
+		ret = skov_imx6_switch_port(root, old);
+		if (ret)
+			dev_err(skov_priv->dev, "Filed to set mac address\n");
+	}
+}
+
+static int skov_imx6_fixup(struct device_node *root, void *unused)
+{
 	struct device_node *chosen = of_create_node(root, "/chosen");
+	struct device_node *node;
+	uint32_t brightness;
+	const char *val;
+	int ret;
 
-	eth_of_fixup_node_from_eth_device(root,
-			"/mdio-gpio/ksz8873@3/ports/ports@0", "eth0");
-	eth2_of_fixup_node_individually(root,
-		"/mdio-gpio/ksz8873@3/ports/ports@1", "eth0",
-		"state.ethaddr.eth2", "/state/ethaddr/eth2");
+	if (skov_have_switch)
+		skov_imx6_switch(root);
+	else
+		skov_imx6_no_switch(root);
 
 	switch (bootsource_get()) {
 	case BOOTSOURCE_MMC:
@@ -326,7 +426,7 @@ static int skov_imx6_fixup(struct device_node *root, void *unused)
 	default:
 		val = getenv("state.display.brightness");
 		if (!val) {
-			pr_err("could not get default display brightness\n");
+			dev_err(skov_priv->dev, "could not get default display brightness\n");
 			return 0;
 		}
 
@@ -337,7 +437,7 @@ static int skov_imx6_fixup(struct device_node *root, void *unused)
 	for_each_compatible_node_from(node, root, NULL, "pwm-backlight") {
 		ret = of_property_write_u32(node, "default-brightness-level", brightness);
 		if (ret)
-			pr_err("error %d while setting default-brightness-level property on node %s to %d\n",
+			dev_err(skov_priv->dev, "error %d while setting default-brightness-level property on node %s to %d\n",
 				ret, node->name, brightness);
 	}
 
@@ -348,6 +448,40 @@ static int skov_imx6_fixup(struct device_node *root, void *unused)
 	return 0;
 }
 
+static void skov_init_parallel_lcd(void)
+{
+	struct device_node *lcd;
+
+	lcd = of_find_compatible_node(NULL, NULL, "fsl,imx-parallel-display");
+	if (!lcd) {
+		dev_err(skov_priv->dev, "Cannot find \"fsl,imx-parallel-display\" node\n");
+		return;
+	}
+
+	of_device_enable_and_register(lcd);
+}
+
+static void skov_init_ldb(void)
+{
+	struct device_node *ldb, *chan;
+
+	ldb = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ldb");
+	if (!ldb) {
+		dev_err(skov_priv->dev, "Cannot find \"fsl,imx6q-ldb\" node\n");
+		return;
+	}
+
+	/* First enable channel 0, prior to enabling parent */
+	chan = of_find_node_by_name_address(ldb, "lvds-channel@0");
+	if (chan)
+		of_device_enable(chan);
+	else
+		dev_err(skov_priv->dev, "Cannot find \"lvds-channel@0\" node\n");
+
+	/* Now probe will see the expected device tree */
+	of_device_enable_and_register(ldb);
+}
+
 /*
  * Some variants need tweaks to make them work
  *
@@ -357,10 +491,19 @@ static int skov_imx6_fixup(struct device_node *root, void *unused)
  */
 static void skov_init_board(const struct board_description *variant)
 {
-	struct device_node *np;
+	struct device_node *gpio_np = NULL;
 	char *environment_path, *envdev;
 	int ret;
 
+	gpio_np = of_find_node_by_name_address(NULL, "gpio@20b4000");
+	if (gpio_np) {
+		ret = of_device_ensure_probed(gpio_np);
+		if (ret)
+			dev_warn(skov_priv->dev, "Can't probe GPIO node\n");
+	} else {
+		dev_warn(skov_priv->dev, "Can't get GPIO node\n");
+	}
+
 	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
 		BBU_HANDLER_FLAG_DEFAULT);
 
@@ -377,12 +520,12 @@ static void skov_init_board(const struct board_description *variant)
 		break;
 	}
 
-	pr_notice("Using environment in %s\n", envdev);
+	dev_notice(skov_priv->dev, "Using environment in %s\n", envdev);
 
 	ret = of_device_enable_path(environment_path);
 	if (ret < 0)
-		pr_warn("Failed to enable environment partition '%s' (%d)\n",
-			environment_path, ret);
+		dev_warn(skov_priv->dev, "Failed to enable environment partition '%s' (%d)\n",
+			 environment_path, ret);
 
 	if (variant->flags & SKOV_NEED_ENABLE_RMII) {
 		/*
@@ -391,11 +534,13 @@ static void skov_init_board(const struct board_description *variant)
 		 */
 		gpio_request(24, "must_be_low");
 		gpio_direction_output(24, 0);
+		gpio_free(24);
 	}
 
 	/* SD card handling */
 	gpio_request(205, "mmc io supply");
 	gpio_direction_output(205, 0); /* select 3.3 V IO voltage */
+	gpio_free(205);
 
 	if (variant->flags & SKOV_ENABLE_MMC_POWER) {
 		/*
@@ -406,61 +551,89 @@ static void skov_init_board(const struct board_description *variant)
 		gpio_direction_output(200, 0); /* switch on */
 		mdelay(1);
 		gpio_direction_output(200, 1); /* switch on */
+		gpio_free(200);
 	}
 
-	if (variant->flags & SKOV_DISPLAY_PARALLEL) {
-		np = of_find_compatible_node(NULL, NULL, "fsl,imx-parallel-display");
-		if (np)
-			of_device_enable_and_register(np);
-		else
-			pr_err("Cannot find \"fsl,imx-parallel-display\" node\n");
+	if (variant->flags & SKOV_DISPLAY_PARALLEL)
+		skov_init_parallel_lcd();
+
+	if (variant->flags & SKOV_DISPLAY_LVDS)
+		skov_init_ldb();
+}
+
+static int skov_set_switch_lan2_mac(struct skov_imx6_priv *priv)
+{
+	const char *state = "/state/ethaddr/eth2";
+	struct device_node *lan2_np;
+	u8 ethaddr[ETH_ALEN];
+	int ret;
+
+	ret = get_mac_address_from_env_variable("state.ethaddr.eth2", ethaddr);
+	if (ret || !is_valid_ether_addr(ethaddr)) {
+		ret = get_default_mac_address_from_state_node(state, ethaddr);
+		if (ret || !is_valid_ether_addr(ethaddr)) {
+			dev_err(priv->dev, "can't get MAC for LAN2\n");
+			return -ENODEV;
+		}
 	}
 
-	if (variant->flags & SKOV_DISPLAY_LVDS) {
-		np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ldb");
-		if (np)
-			of_device_enable_and_register(np);
-		else
-			pr_err("Cannot find \"fsl,imx6q-ldb\" node\n");
-
-		/* ... as well as its channel 0 */
-		np = of_find_node_by_name(np, "lvds-channel@0");
-		if (np)
-			of_device_enable(np);
-		else
-			pr_err("Cannot find \"lvds-channel@0\" node\n");
+	lan2_np = of_find_node_by_path("/mdio/switch@0/ports/ports@1");
+	if (!lan2_np) {
+		dev_err(priv->dev, "LAN2 node not found\n");
+		return -ENODEV;
 	}
+
+	of_eth_register_ethaddr(lan2_np, ethaddr);
+
+	return 0;
 }
 
-static void fixup_machine_compatible(const char *compat)
+static int skov_switch_test(void)
 {
-	const char *curcompat;
-	struct device_node *root;
-	int cclen = 0, clen = strlen(compat) + 1;
-	void *buf;
+	struct device *sw_dev;
+	struct device *eth0;
+	int ret;
 
-	root = of_get_root_node();
-	if (!root)
-		return;
+	if (skov_board_no < 0)
+		return 0;
 
-	curcompat = of_get_property(root, "compatible", &cclen);
+	/* Driver should be able to detect if device do actually
+	 * exist. So, we need only to detect if driver is actually
+	 * probed.
+	 */
+	sw_dev = of_find_device_by_node_path("/mdio/switch@0");
+	if (!sw_dev) {
+		dev_err(skov_priv->dev, "switch@0 device was not created!\n");
+		goto no_switch;
+	}
 
-	buf = xzalloc(cclen + clen);
+	if (dev_is_probed(sw_dev)) {
+		skov_set_switch_lan2_mac(skov_priv);
+		/* even if we fail, continue to boot as good as possible */
+		return 0;
+	}
 
-	memcpy(buf, compat, clen);
-	memcpy(buf + clen, curcompat, cclen);
+no_switch:
+	skov_have_switch = false;
 
-	/*
-	 * Prepend the compatible from board entry to the machine compatible.
-	 * Used to match bootspec entries against it.
-	 */
-	of_set_property(root, "compatible", buf, cclen + clen, true);
+	dev_notice(skov_priv->dev, "No-switch variant is detected\n");
 
-	free(buf);
+	eth0 = get_device_by_name("eth0");
+	if (eth0) {
+		ret = dev_set_param(eth0, "mode", "disabled");
+		if (ret)
+			dev_warn(skov_priv->dev, "Can't set eth0 mode\n");
+	} else {
+		dev_warn(skov_priv->dev, "Can't disable eth0\n");
+	}
+
+	return 0;
 }
+late_initcall(skov_switch_test);
 
-static int skov_imx6_probe(struct device_d *dev)
+static int skov_imx6_probe(struct device *dev)
 {
+	struct skov_imx6_priv *priv;
 	unsigned v = 0;
 	const struct board_description *variant;
 
@@ -480,6 +653,10 @@ static int skov_imx6_probe(struct device_d *dev)
 
 	skov_board_no = v;
 
+	priv = xzalloc(sizeof(*priv));
+	priv->dev = dev;
+	skov_priv = priv;
+
 	globalvar_add_simple_int("board.no", &skov_board_no, "%u");
 	globalvar_add_simple("board.variant", variant->variant);
 	globalvar_add_simple("board.revision",variant->revision);
@@ -487,10 +664,12 @@ static int skov_imx6_probe(struct device_d *dev)
 	globalvar_add_simple("board.dts", variant->dts_compatible);
 	globalvar_add_simple("board.display", variant->display ?: NULL);
 
-	fixup_machine_compatible(variant->dts_compatible);
+	of_prepend_machine_compatible(NULL, variant->dts_compatible);
 
 	skov_init_board(variant);
 
+	defaultenv_append_directory(defaultenv_skov_imx6);
+
 	return 0;
 }
 
@@ -501,8 +680,9 @@ static __maybe_unused struct of_device_id skov_version_ids[] = {
 		/* sentinel */
 	}
 };
+BAREBOX_DEEP_PROBE_ENABLE(skov_version_ids);
 
-static struct driver_d skov_version_driver = {
+static struct driver skov_version_driver = {
 	.name = "skov-imx6",
 	.probe = skov_imx6_probe,
 	.of_compatible = DRV_OF_COMPAT(skov_version_ids),
@@ -518,7 +698,7 @@ static void skov_imx6_devices_shutdown(void)
 
 	external = getenv("state.display.external");
 	if (!external) {
-		pr_err("could not get state variable display.external\n");
+		dev_err(skov_priv->dev, "could not get state variable display.external\n");
 		return;
 	}
 
diff --git a/arch/arm/boards/skov-imx6/defaultenv-skov-imx6/network/eth1-discover b/arch/arm/boards/skov-imx6/defaultenv-skov-imx6/network/eth1-discover
new file mode 100644
index 0000000000..e11a3f9006
--- /dev/null
+++ b/arch/arm/boards/skov-imx6/defaultenv-skov-imx6/network/eth1-discover
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+# Some boards doesn't have a ETH port, but may have USB network attached
+if [ "$eth0.mode" != "disabled" ]; then
+	exit 0;
+fi
+
+usb
diff --git a/arch/arm/boards/skov-imx6/flash-header-mx6-skov-imx6.imxcfg b/arch/arm/boards/skov-imx6/flash-header-mx6-skov-imx6.imxcfg
index 4bb615ebb0..da4cd4bebf 100644
--- a/arch/arm/boards/skov-imx6/flash-header-mx6-skov-imx6.imxcfg
+++ b/arch/arm/boards/skov-imx6/flash-header-mx6-skov-imx6.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x00907000
 max_load_size 0x11000
diff --git a/arch/arm/boards/skov-imx6/lowlevel.c b/arch/arm/boards/skov-imx6/lowlevel.c
index eab797faa1..16809dd4a6 100644
--- a/arch/arm/boards/skov-imx6/lowlevel.c
+++ b/arch/arm/boards/skov-imx6/lowlevel.c
@@ -3,19 +3,20 @@
 #define pr_fmt(fmt) "skov-imx6: " fmt
 
 #include <common.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <io.h>
-#include <mach/imx6-mmdc.h>
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6.h>
-#include <mach/xload.h>
-#include <mach/esdctl.h>
+#include <mach/imx/imx6-mmdc.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/esdctl.h>
 #include <serial/imx-uart.h>
-#include <mach/iomux-mx6.h>
-#include <mach/imx-gpio.h>
+#include <mach/imx/iomux-mx6.h>
+#include <mach/imx/imx-gpio.h>
 #include "version.h"
 
 static void __udelay(int us)
@@ -28,122 +29,6 @@ static void __udelay(int us)
 /* ------------------------------------------------------------------------ */
 
 /*
- * Micron MT41K512M16HA-125 IT:E ->  8 GBit = 64 Meg x 16 x 8 banks
- *
- * Speed Grade   Data Rate (MT/s)  tRCD-tRP-CL   tRCD(ns)  tRP(ns)  CL(ns)
- *    -125          1600            11-11-11      13.75     13.75   13.75
- *               (=800 MHz)
- *
- * Memory configuration used by variant:
- * - "Max Performance", 64 bit data bus, 1066 MHz, 4 GiB memory
- */
-static const struct mx6_ddr3_cfg skov_imx6_cfg_4x512Mb_1066MHz = {
-	.mem_speed = 1066,
-	.density = 8, /* GiBit */
-	.width = 16, /* 16 bit data per device */
-	.banks = 8,
-	.rowaddr = 16, /* 64 k */
-	.coladdr = 10, /* 1 k */
-	.pagesz = 2, /* [kiB] */
-	.trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */
-	.trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */
-	.trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */
-	.SRT = 0,
-};
-
-static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x512Mb_1066MHz = {
-	.dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */
-	.cs_density = 32, /* four 8 GBit devices connected */
-	.ncs = 1, /* one CS line for all devices */
-	.cs1_mirror = 1, /* TODO */
-	.bi_on = 1, /* TODO */
-	.rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */
-	.rtt_wr = 0, /* is LW_EN is 0 in their code */
-	.ralat = 5, /* TODO */
-	.walat = 1, /* TODO */
-	.mif3_mode = 3, /* TODO */
-	.rst_to_cke = 0x23, /* used in their code as well */
-	.sde_to_rst = 0x10, /* used in their code as well */
-	.pd_fast_exit = 0, /* TODO */
-};
-
-static const struct mx6_mmdc_calibration skov_imx6_calib_4x512Mb_1066MHz = {
-	.p0_mpwldectrl0 = 0x001a0017,
-	.p0_mpwldectrl1 = 0x001F001F,
-	.p0_mpdgctrl0 = 0x43040319,
-	.p0_mpdgctrl1 = 0x03040279,
-	.p0_mprddlctl = 0x4d434248,
-	.p0_mpwrdlctl = 0x34424543,
-
-	.p1_mpwldectrl0 = 0x00170027,
-	.p1_mpwldectrl1 = 0x000a001f,
-	.p1_mpdgctrl0 = 0x43040321,
-	.p1_mpdgctrl1 = 0x03030251,
-	.p1_mprddlctl = 0x42413c4d,
-	.p1_mpwrdlctl = 0x49324933,
-};
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * Micron MT41K256M16HA-125 IT:E ->  4 GBit = 32 Meg x 16 x 8 banks
- *
- * Speed Grade   Data Rate (MT/s)  tRCD-tRP-CL   tRCD(ns)  tRP(ns)  CL(ns)
- *    -125          1600            11-11-11      13.75     13.75   13.75
- *               (=800 MHz)
- *
- * Memory configuration used by variant:
- * - "Max Performance", 64 bit data bus, 1066 MHz, 2 GiB memory
- */
-static const struct mx6_ddr3_cfg skov_imx6_cfg_4x256Mb_1066MHz = {
-	.mem_speed = 1066,
-	.density = 4, /* GiBit */
-	.width = 16, /* 16 bit data per device */
-	.banks = 8,
-	.rowaddr = 15, /* 32 k */
-	.coladdr = 10, /* 1 k */
-	.pagesz = 2, /* [kiB] */
-	.trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */
-	.trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */
-	.trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */
-	.SRT = 0,
-};
-
-static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x256Mb_1066MHz = {
-	.dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */
-	.cs_density = 16, /* four 4 GBit devices connected */
-	.ncs = 1, /* one CS line for all devices */
-	.cs1_mirror = 1, /* TODO */
-	.bi_on = 1, /* TODO */
-	.rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */
-	.rtt_wr = 0, /* is LW_EN is 0 in their code */
-	.ralat = 5, /* TODO */
-	.walat = 1, /* TODO */
-	.mif3_mode = 3, /* TODO */
-	.rst_to_cke = 0x23, /* used in their code as well */
-	.sde_to_rst = 0x10, /* used in their code as well */
-	.pd_fast_exit = 0, /* TODO */
-};
-
-static const struct mx6_mmdc_calibration skov_imx6_calib_4x256Mb_1066MHz = {
-	.p0_mpwldectrl0 = 0x001a0017,
-	.p0_mpwldectrl1 = 0x001F001F,
-	.p0_mpdgctrl0 = 0x43040319,
-	.p0_mpdgctrl1 = 0x03040279,
-	.p0_mprddlctl = 0x4d434248,
-	.p0_mpwrdlctl = 0x34424543,
-
-	.p1_mpwldectrl0 = 0x00170027,
-	.p1_mpwldectrl1 = 0x000a001f,
-	.p1_mpdgctrl0 = 0x43040321,
-	.p1_mpdgctrl1 = 0x03030251,
-	.p1_mprddlctl = 0x42413c4d,
-	.p1_mpwrdlctl = 0x49324933,
-};
-
-/* ------------------------------------------------------------------------ */
-
-/*
  * Micron MT41K128M16JT-125 IT:K ->  2 GBit = 16 Meg x 16 x 8 banks
  *
  * Speed Grade   Data Rate (MT/s)  tRCD-tRP-CL   tRCD(ns)  tRP(ns)  CL(ns)
@@ -174,33 +59,33 @@ static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x128Mb_1066MHz = {
 	.dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */
 	.cs_density = 8, /* four 2 GBit devices connected */
 	.ncs = 1, /* one CS line for all devices */
-	.cs1_mirror = 1, /* TODO */
-	.bi_on = 1, /* TODO */
+	.cs1_mirror = 1,
+	.bi_on = 1,
 	.rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */
 	.rtt_wr = 0, /* is LW_EN is 0 in their code */
-	.ralat = 5, /* TODO */
-	.walat = 1, /* TODO */
-	.mif3_mode = 3, /* TODO */
-	.rst_to_cke = 0x23, /* used in their code as well */
-	.sde_to_rst = 0x10, /* used in their code as well */
-	.pd_fast_exit = 0, /* TODO */
+	.ralat = 5,
+	.walat = 0,
+	.mif3_mode = 3,
+	.rst_to_cke = 0x23,
+	.sde_to_rst = 0x10,
+	.pd_fast_exit = 1,
 };
 
 /* calibration info for the "max performance" and "high performance" */
 static const struct mx6_mmdc_calibration skov_imx6_calib_4x128Mb_1066MHz = {
-	.p0_mpwldectrl0 = 0x0011000E,
-	.p0_mpwldectrl1 = 0x000E001B,
-	.p0_mpdgctrl0 = 0x42720306,
-	.p0_mpdgctrl1 = 0x026F0266,
-	.p0_mprddlctl = 0x45393B3E,
-	.p0_mpwrdlctl = 0x40434541,
-
-	.p1_mpwldectrl0 = 0x00190015,
-	.p1_mpwldectrl1 = 0x00070018,
-	.p1_mpdgctrl0 = 0x4273030A,
-	.p1_mpdgctrl1 = 0x02740240,
-	.p1_mprddlctl = 0x403A3747,
-	.p1_mpwrdlctl = 0x473E4A3B,
+	.p0_mpwldectrl0 = 0x00230023,
+	.p0_mpwldectrl1 = 0x0029001E,
+	.p0_mpdgctrl0 = 0x43400350,
+	.p0_mpdgctrl1 = 0x03380330,
+	.p0_mprddlctl = 0x3E323638,
+	.p0_mpwrdlctl = 0x383A3E3A,
+
+	.p1_mpwldectrl0 = 0x001F002A,
+	.p1_mpwldectrl1 = 0x001A0028,
+	.p1_mpdgctrl0 = 0x43300340,
+	.p1_mpdgctrl1 = 0x03340300,
+	.p1_mprddlctl = 0x383A3242,
+	.p1_mpwrdlctl = 0x4232463A,
 };
 
 /* ------------------------------------------------------------------------ */
@@ -214,21 +99,21 @@ static struct mx6dq_iomux_ddr_regs ddr_iomux_q = {
 	.dram_sdqs5 = 0x00000030,
 	.dram_sdqs6 = 0x00000030,
 	.dram_sdqs7 = 0x00000030,
-	.dram_dqm0 = 0x00020030,
-	.dram_dqm1 = 0x00020030,
-	.dram_dqm2 = 0x00020030,
-	.dram_dqm3 = 0x00020030,
-	.dram_dqm4 = 0x00020030,
-	.dram_dqm5 = 0x00020030,
-	.dram_dqm6 = 0x00020030,
-	.dram_dqm7 = 0x00020030,
-	.dram_cas = 0x00020030,
-	.dram_ras = 0x00020030,
-	.dram_sdclk_0 = 0x00020030,
-	.dram_sdclk_1 = 0x00020030,
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_dqm2 = 0x00000030,
+	.dram_dqm3 = 0x00000030,
+	.dram_dqm4 = 0x00000030,
+	.dram_dqm5 = 0x00000030,
+	.dram_dqm6 = 0x00000030,
+	.dram_dqm7 = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdclk_1 = 0x00000030,
 	.dram_sdcke0 = 0x00003000,
 	.dram_sdcke1 = 0x00003000,
-	.dram_reset = 0x00020030,
+	.dram_reset = 0x00000030,
 	.dram_sdba2 = 0x00000000,
 	.dram_sdodt0 = 0x00003030,
 	.dram_sdodt1 = 0x00003030,
@@ -295,25 +180,25 @@ static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_2x128Mb_800MHz = {
 	.dsize = 1, /* 32 bit wide = 2 devices, 16 bit each */
 	.cs_density = 4, /* two 2 GBit devices connected */
 	.ncs = 1, /* one CS line for all devices */
-	.cs1_mirror = 1, /* TODO */
-	.bi_on = 1, /* TODO */
+	.cs1_mirror = 1,
+	.bi_on = 1,
 	.rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */
 	.rtt_wr = 0, /* is LW_EN is 0 in their code */
-	.ralat = 5, /* TODO */
-	.walat = 1, /* TODO */
-	.mif3_mode = 3, /* TODO */
-	.rst_to_cke = 0x23, /* used in their code as well */
-	.sde_to_rst = 0x10, /* used in their code as well */
-	.pd_fast_exit = 0, /* TODO */
+	.ralat = 5,
+	.walat = 0,
+	.mif3_mode = 3,
+	.rst_to_cke = 0x23,
+	.sde_to_rst = 0x10,
+	.pd_fast_exit = 1,
 };
 
 static const struct mx6_mmdc_calibration skov_imx6_calib_2x128Mb_800MHz = {
-	.p0_mpwldectrl0 = 0x0040003C,
-	.p0_mpwldectrl1 = 0x0032003E,
-	.p0_mpdgctrl0 = 0x42350231,
-	.p0_mpdgctrl1 = 0x021A0218,
-	.p0_mprddlctl = 0x4B4B4E49,
-	.p0_mpwrdlctl = 0x3F3F3035,
+	.p0_mpwldectrl0 = 0x004A004B,
+	.p0_mpwldectrl1 = 0x00420046,
+	.p0_mpdgctrl0 = 0x42400240,
+	.p0_mpdgctrl1 = 0x02300230,
+	.p0_mprddlctl = 0x464A4A4A,
+	.p0_mpwrdlctl = 0x32342A32,
 };
 
 /* ------------------------------------------------------------------------ */
@@ -327,21 +212,21 @@ static const struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
 	.dram_sdqs5 = 0x00000030,
 	.dram_sdqs6 = 0x00000030,
 	.dram_sdqs7 = 0x00000030,
-	.dram_dqm0 = 0x00020030,
-	.dram_dqm1 = 0x00020030,
-	.dram_dqm2 = 0x00020030,
-	.dram_dqm3 = 0x00020030,
-	.dram_dqm4 = 0x00020030,
-	.dram_dqm5 = 0x00020030,
-	.dram_dqm6 = 0x00020030,
-	.dram_dqm7 = 0x00020030,
-	.dram_cas = 0x00020030,
-	.dram_ras = 0x00020030,
-	.dram_sdclk_0 = 0x00020030,
-	.dram_sdclk_1 = 0x00020030,
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_dqm2 = 0x00000030,
+	.dram_dqm3 = 0x00000030,
+	.dram_dqm4 = 0x00000030,
+	.dram_dqm5 = 0x00000030,
+	.dram_dqm6 = 0x00000030,
+	.dram_dqm7 = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdclk_1 = 0x0000030,
 	.dram_sdcke0 = 0x00003000,
 	.dram_sdcke1 = 0x00003000,
-	.dram_reset = 0x00020030,
+	.dram_reset = 0x00000030,
 	.dram_sdba2 = 0x00000000,
 	.dram_sdodt0 = 0x00003030,
 	.dram_sdodt1 = 0x00003030,
@@ -529,26 +414,6 @@ static void skov_imx6_init(int cpu_type, unsigned board_variant)
 	int instance;
 
 	switch (board_variant) {
-	case 12: /* P2 i.MX6Q, max performance */
-		if (cpu_type != IMX6_CPUTYPE_IMX6Q) {
-			pr_err("Invalid SoC! i.MX6Q expected\n");
-			return;
-		}
-		pr_debug("Initializing a P2 max performance system...\n");
-		spl_imx6q_dram_init(&skov_imx6_sysinfo_4x256Mb_1066MHz,
-					&skov_imx6_calib_4x256Mb_1066MHz,
-					&skov_imx6_cfg_4x256Mb_1066MHz);
-		break;
-	case 18: /* i.MX6Q+ */
-		if (cpu_type != IMX6_CPUTYPE_IMX6Q) {
-			pr_err("Invalid SoC! i.MX6Q expected\n");
-			return;
-		}
-		pr_debug("Initializing board variant 18\n");
-		spl_imx6q_dram_init(&skov_imx6_sysinfo_4x512Mb_1066MHz,
-					&skov_imx6_calib_4x512Mb_1066MHz,
-					&skov_imx6_cfg_4x512Mb_1066MHz);
-		break;
 	case 19: /* i.MX6S "Solo_R512M_F2G" */
 		if (cpu_type != IMX6_CPUTYPE_IMX6S) {
 			pr_err("Invalid SoC! i.MX6S expected\n");
@@ -618,6 +483,7 @@ static void skov_imx6_init(int cpu_type, unsigned board_variant)
 
 extern char __dtb_z_imx6q_skov_imx6_start[];
 extern char __dtb_z_imx6dl_skov_imx6_start[];
+extern char __dtb_z_imx6s_skov_imx6_start[];
 
 /* called twice: once for SDRAM setup only, second for devicetree setup */
 static noinline void skov_imx6_start(void)
@@ -640,8 +506,11 @@ static noinline void skov_imx6_start(void)
 	/* boot this platform (second call) */
 	switch (cpu_type) {
 	case IMX6_CPUTYPE_IMX6S:
+		pr_debug("Startup i.MX6S based system...\n");
+		imx6q_barebox_entry(__dtb_z_imx6s_skov_imx6_start);
+		break;
 	case IMX6_CPUTYPE_IMX6DL:
-		pr_debug("Startup i.MX6S/DL based system...\n");
+		pr_debug("Startup i.MX6DL based system...\n");
 		imx6q_barebox_entry(__dtb_z_imx6dl_skov_imx6_start);
 		break;
 	case IMX6_CPUTYPE_IMX6D:
@@ -654,7 +523,7 @@ static noinline void skov_imx6_start(void)
 
 ENTRY_FUNCTION(start_imx6_skov_imx6, r0, r1, r2)
 {
-	arm_cpu_lowlevel_init();
+	imx6_cpu_lowlevel_init();
 
 	relocate_to_current_adr();
 	setup_c();
diff --git a/arch/arm/boards/skov-imx6/version.c b/arch/arm/boards/skov-imx6/version.c
index 5a6a0625ca..503a60366f 100644
--- a/arch/arm/boards/skov-imx6/version.c
+++ b/arch/arm/boards/skov-imx6/version.c
@@ -3,9 +3,9 @@
 #define pr_fmt(fmt) "skov-imx6: " fmt
 
 #include <common.h>
-#include <mach/iomux-mx6.h>
-#include <mach/imx-gpio.h>
-#include <mach/imx6.h>
+#include <mach/imx/iomux-mx6.h>
+#include <mach/imx/imx-gpio.h>
+#include <mach/imx/imx6.h>
 
 #include "version.h"
 
diff --git a/arch/arm/boards/skov-imx6/version.h b/arch/arm/boards/skov-imx6/version.h
index 008410490b..a5d205fe2e 100644
--- a/arch/arm/boards/skov-imx6/version.h
+++ b/arch/arm/boards/skov-imx6/version.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __SKOV_VERSION_H
 #define __SKOV_VERSION_H
 
diff --git a/arch/arm/boards/skov-imx8mp/Makefile b/arch/arm/boards/skov-imx8mp/Makefile
new file mode 100644
index 0000000000..35d8640087
--- /dev/null
+++ b/arch/arm/boards/skov-imx8mp/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/skov-imx8mp/board.c b/arch/arm/boards/skov-imx8mp/board.c
new file mode 100644
index 0000000000..3b6eb7b080
--- /dev/null
+++ b/arch/arm/boards/skov-imx8mp/board.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "linux/kernel.h"
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <envfs.h>
+#include <environment.h>
+#include <globalvar.h>
+#include <gpio.h>
+#include <init.h>
+#include <io.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/iomux-mx8mp.h>
+
+struct skov_imx8mp_priv {
+	struct device *dev;
+	int variant_id;
+};
+
+static struct skov_imx8mp_priv *skov_imx8mp_priv;
+
+#define GPIO_HW_VARIANT  {\
+	{IMX_GPIO_NR(1, 8), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var0"}, \
+	{IMX_GPIO_NR(1, 9), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var1"}, \
+	{IMX_GPIO_NR(1, 10), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var2"}, \
+	{IMX_GPIO_NR(1, 11), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var3"}, \
+	{IMX_GPIO_NR(1, 12), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var4"}, \
+	{IMX_GPIO_NR(1, 13), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var5"}, \
+	{IMX_GPIO_NR(1, 14), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var6"}, \
+	{IMX_GPIO_NR(1, 15), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var7"}, \
+}
+
+struct skov_imx8mp_storage {
+	const char *name;
+	const char *env_path;
+	const char *dev_path;
+	enum bootsource bootsource;
+	int bootsource_ext_id;
+	bool mmc_boot_part;
+};
+
+enum skov_imx8mp_boot_source {
+	SKOV_BOOT_SOURCE_EMMC,
+	SKOV_BOOT_SOURCE_SD,
+	SKOV_BOOT_SOURCE_UNKNOWN,
+};
+
+static const struct skov_imx8mp_storage skov_imx8mp_storages[] = {
+	[SKOV_BOOT_SOURCE_EMMC] = {
+		/* default boot source */
+		.name = "eMMC",
+		.env_path = "/chosen/environment-emmc",
+		.dev_path = "/dev/mmc2",
+		.bootsource = BOOTSOURCE_MMC,
+		.bootsource_ext_id = 2,
+		.mmc_boot_part = true,
+	},
+	[SKOV_BOOT_SOURCE_SD] = {
+		.name = "SD",
+		.env_path = "/chosen/environment-sd",
+		.dev_path = "/dev/mmc1.barebox",
+		.bootsource = BOOTSOURCE_MMC,
+		.bootsource_ext_id = 1,
+	},
+};
+
+struct board_description {
+	const char *dts_compatible;
+	const char *dts_compatible_hdmi;
+	unsigned flags;
+};
+
+#define SKOV_IMX8MP_HAS_HDMI	BIT(0)
+
+static const struct board_description imx8mp_variants[] = {
+	[0] = {
+		.dts_compatible = "skov,imx8mp-skov-revb-lt6",
+	},
+	[1] = {
+		.dts_compatible = "skov,imx8mp-skov-revb-mi1010ait-1cp1",
+		.dts_compatible_hdmi = "skov,imx8mp-skov-revb-hdmi",
+		.flags = SKOV_IMX8MP_HAS_HDMI,
+	},
+};
+
+static int skov_imx8mp_fixup(struct device_node *root, void *data)
+{
+	struct device_node *chosen = of_create_node(root, "/chosen");
+	const char *of_board = "skov,imx8mp-board-version";
+	struct skov_imx8mp_priv *priv = data;
+	struct device *dev = priv->dev;
+	int ret;
+
+	ret = of_property_write_u32(chosen, of_board, priv->variant_id);
+	if (ret)
+		dev_err(dev,  "Failed to fixup %s: %pe\n", of_board,
+			ERR_PTR(ret));
+
+	return 0;
+}
+
+static int skov_imx8mp_get_variant_id(uint *id)
+{
+	struct gpio gpios_rev[] = GPIO_HW_VARIANT;
+	struct device_node *gpio_np;
+	u32 hw_rev;
+	int ret;
+
+	gpio_np = of_find_node_by_name_address(NULL, "gpio@30200000");
+	if (!gpio_np)
+		return -ENODEV;
+
+	ret = of_device_ensure_probed(gpio_np);
+	if (ret)
+		return ret;
+
+	ret = gpio_array_to_id(gpios_rev, ARRAY_SIZE(gpios_rev), &hw_rev);
+	if (ret)
+		goto exit_get_id;
+
+	*id = hw_rev;
+
+	return 0;
+exit_get_id:
+	pr_err("Failed to read gpio ID: %pe\n", ERR_PTR(ret));
+	return ret;
+}
+
+static int skov_imx8mp_get_hdmi(struct device *dev)
+{
+	const char *env = "state.display.external";
+	struct device_node *state_np;
+	unsigned int val = 0;
+	int ret;
+
+	state_np = of_find_node_by_name_address(NULL, "state");
+	if (!state_np) {
+		dev_err(dev, "Failed to find state node\n");
+		return -ENODEV;
+	}
+
+	ret = of_device_ensure_probed(state_np);
+	if (ret) {
+		dev_err(dev, "Failed to probe state node: %pe\n", ERR_PTR(ret));
+		return ret;
+	}
+
+	ret = getenv_uint(env, &val);
+	if (ret) {
+		dev_err(dev, "Failed to read %s: %pe\n", env, ERR_PTR(ret));
+		return ret;
+	}
+
+	return val;
+}
+
+static int skov_imx8mp_init_variant(struct skov_imx8mp_priv *priv)
+{
+	const struct board_description *variant;
+	struct device *dev = priv->dev;
+	const char *compatible;
+	unsigned int v = 0;
+	int ret;
+
+	ret = skov_imx8mp_get_variant_id(&v);
+	if (ret)
+		return ret;
+
+	priv->variant_id = v;
+
+	if (v >= ARRAY_SIZE(imx8mp_variants)) {
+		dev_err(dev, "Invalid variant %u\n", v);
+		return -EINVAL;
+	}
+
+	variant = &imx8mp_variants[v];
+
+	if (variant->flags & SKOV_IMX8MP_HAS_HDMI) {
+		ret = skov_imx8mp_get_hdmi(dev);
+		if (ret < 0)
+			return ret;
+
+		if (ret)
+			compatible = variant->dts_compatible_hdmi;
+		else
+			compatible = variant->dts_compatible;
+	} else {
+		compatible = variant->dts_compatible;
+	}
+
+	of_prepend_machine_compatible(NULL, compatible);
+
+	return 0;
+}
+
+static void skov_imx8mp_enable_env(struct device *dev,
+				   const struct skov_imx8mp_storage *st,
+				   bool *enabled)
+{
+	int ret;
+
+	if (bootsource_get() != st->bootsource ||
+	    bootsource_get_instance() != st->bootsource_ext_id)
+		return;
+
+	ret = of_device_enable_path(st->env_path);
+	if (ret) {
+		dev_err(dev, "Failed to enable environment path: %s, %pe\n",
+			st->env_path, ERR_PTR(ret));
+		return;
+	}
+
+	*enabled = true;
+}
+
+static void skov_imx8mp_add_bbu(struct device *dev,
+				const struct skov_imx8mp_storage *st,
+				bool default_env)
+{
+	unsigned long flags = 0;
+	int ret;
+
+	if (default_env)
+		flags |= BBU_HANDLER_FLAG_DEFAULT;
+
+	if (st->mmc_boot_part) {
+		ret = imx8m_bbu_internal_mmcboot_register_handler(st->name,
+								  st->dev_path,
+								  flags);
+	} else {
+		ret = imx8m_bbu_internal_mmc_register_handler(st->name,
+							      st->dev_path,
+							      flags);
+	}
+	if (ret)
+		dev_err(dev, "Failed to register %s BBU handler: %pe\n",
+			st->name, ERR_PTR(ret));
+}
+
+static void skov_imx8mp_init_storage(struct device *dev)
+{
+	int default_boot_src = SKOV_BOOT_SOURCE_EMMC;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(skov_imx8mp_storages); i++) {
+		bool enabled_env = false;
+
+		skov_imx8mp_enable_env(dev, &skov_imx8mp_storages[i],
+				       &enabled_env);
+		if (enabled_env)
+			default_boot_src = i;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(skov_imx8mp_storages); i++)
+		skov_imx8mp_add_bbu(dev, &skov_imx8mp_storages[i],
+				    i == default_boot_src);
+}
+
+static int skov_imx8mp_probe(struct device *dev)
+{
+	struct skov_imx8mp_priv *priv;
+	int ret;
+
+	priv = xzalloc(sizeof(*priv));
+	priv->dev = dev;
+	skov_imx8mp_priv = priv;
+
+	skov_imx8mp_init_storage(dev);
+
+	skov_imx8mp_init_variant(priv);
+
+	ret = of_register_fixup(skov_imx8mp_fixup, priv);
+	if (ret)
+		dev_err(dev, "Failed to register fixup: %pe\n", ERR_PTR(ret));
+
+	return 0;
+}
+
+static const struct of_device_id skov_imx8mp_of_match[] = {
+	/* generic, barebox specific compatible for all board variants */
+	{ .compatible = "skov,imx8mp" },
+	{ /* Sentinel */ }
+};
+BAREBOX_DEEP_PROBE_ENABLE(skov_imx8mp_of_match);
+
+static struct driver skov_imx8mp_board_driver = {
+	.name = "skov-imx8m",
+	.probe = skov_imx8mp_probe,
+	.of_compatible = skov_imx8mp_of_match,
+};
+coredevice_platform_driver(skov_imx8mp_board_driver);
diff --git a/arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg b/arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg
new file mode 100644
index 0000000000..6ea2e6c68e
--- /dev/null
+++ b/arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mp
+
+loadaddr 0x920000
+max_load_size 0x3f000
+ivtofs 0x0
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/skov-imx8mp/lowlevel.c b/arch/arm/boards/skov-imx8mp/lowlevel.c
new file mode 100644
index 0000000000..c35ffe526d
--- /dev/null
+++ b/arch/arm/boards/skov-imx8mp/lowlevel.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/imx8mp-regs.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <mach/imx/xload.h>
+#include <mfd/pca9450.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <soc/imx8m/ddr.h>
+
+extern char __dtb_z_imx8mp_skov_start[];
+
+#define UART_PAD_CTRL   MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+				     MX8MP_PAD_CTL_FSEL | \
+				     MX8MP_PAD_CTL_PUE | \
+				     MX8MP_PAD_CTL_PE)
+
+#define I2C_PAD_CTRL	MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+				     MX8MP_PAD_CTL_HYS | \
+				     MX8MP_PAD_CTL_PUE | \
+				     MX8MP_PAD_CTL_PE)
+
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_UART2_RXD__UART2_DCE_RX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+
+	putc_ll('>');
+}
+
+static struct pmic_config pca9450_cfg[] = {
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	{ PCA9450_BUCK123_DVS, 0x29 },
+	/*
+	 * increase VDD_SOC to typical value 0.95V before first
+	 * DRAM access, set DVS1 to 0.85v for suspend.
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+	 */
+	{ PCA9450_BUCK1OUT_DVS0, 0x1C },
+	{ PCA9450_BUCK1OUT_DVS1, 0x14 },
+	{ PCA9450_BUCK1CTRL, 0x59 },
+	/*
+	 * Increase VDD_ARM to 0.95V to avoid issues in case software after
+	 * Barebox switches to the OD ARM frequency without reprogramming the
+	 * PMIC first.
+	 */
+	{ PCA9450_BUCK2OUT_DVS0, 0x1C },
+	/* set WDOG_B_CFG to cold reset */
+	{ PCA9450_RESET_CTRL, 0xA1 },
+};
+
+static void power_init_board(void)
+{
+	struct pbl_i2c *i2c;
+
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
+
+	pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+}
+
+extern struct dram_timing_info imx8mp_skov_dram_timing;
+
+static void start_atf(struct dram_timing_info *dram_timing)
+{
+	/*
+	 * If we are in EL3 we are running for the first time and need to
+	 * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
+	 * to DRAM in EL2.
+	 */
+	if (current_el() != 3)
+		return;
+
+	imx8mp_early_clock_init();
+
+	power_init_board();
+
+	imx8mp_ddr_init(dram_timing, DRAM_TYPE_LPDDR4);
+
+	imx8mp_load_and_start_image_via_tfa();
+}
+
+/*
+ * Power-on execution flow of imx8mp_skov_start() might not be
+ * obvious for a very first read, so here's, hopefully helpful,
+ * summary:
+ *
+ * 1. MaskROM uploads PBL into OCRAM and that's where this function is
+ *    executed for the first time. At entry the exception level is EL3.
+ *
+ * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL
+ *    part is copied from OCRAM to the TF-A return address in DRAM.
+ *
+ * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us
+ *    from EL3 to EL2.
+ *
+ * 4. Standard barebox boot flow continues
+ */
+static __noreturn noinline void
+imx8mp_skov_start(struct dram_timing_info *dram_timing, void *dtb)
+{
+	setup_uart();
+
+	start_atf(dram_timing);
+
+	/*
+	 * Standard entry we hit once we initialized both DDR and ATF
+	 */
+	imx8mp_barebox_entry(dtb);
+}
+
+ENTRY_FUNCTION(start_skov_imx8mp, r0, r1, r2)
+{
+	imx8mp_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	imx8mp_skov_start(&imx8mp_skov_dram_timing,
+			   __dtb_z_imx8mp_skov_start);
+}
diff --git a/arch/arm/boards/skov-imx8mp/lpddr4-timing.c b/arch/arm/boards/skov-imx8mp/lpddr4-timing.c
new file mode 100644
index 0000000000..a93506b0bd
--- /dev/null
+++ b/arch/arm/boards/skov-imx8mp/lpddr4-timing.c
@@ -0,0 +1,1125 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+#include <soc/imx8m/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x1223 },
+	{ 0x3d400024, 0x16e3600 },
+	{ 0x3d400064, 0x5b00d2 },
+	{ 0x3d400070, 0x7027f90 },
+	{ 0x3d400074, 0x790 },
+	{ 0x3d4000d0, 0xc00305ba },
+	{ 0x3d4000d4, 0x940000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x660048 },
+	{ 0x3d4000ec, 0x160048 },
+	{ 0x3d400100, 0x191e1920 },
+	{ 0x3d400104, 0x60630 },
+	{ 0x3d40010c, 0xb0b000 },
+	{ 0x3d400110, 0xe04080e },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x402 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xd8 },
+	{ 0x3d400144, 0x96004b },
+	{ 0x3d400180, 0x2ee0017 },
+	{ 0x3d400184, 0x2605b8e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0x699 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d400208, 0x0 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1021 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x330000 },
+	{ 0x3d4020e8, 0x660048 },
+	{ 0x3d4020ec, 0x160048 },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x302 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0x599 },
+	{ 0x3d403020, 0x1021 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x330000 },
+	{ 0x3d4030e8, 0x660048 },
+	{ 0x3d4030ec, 0x160048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x302 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0x599 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x8 },
+	{ 0x90159, 0xe8 },
+	{ 0x9015a, 0x109 },
+	{ 0x9015b, 0x0 },
+	{ 0x9015c, 0x8140 },
+	{ 0x9015d, 0x10c },
+	{ 0x9015e, 0x10 },
+	{ 0x9015f, 0x8138 },
+	{ 0x90160, 0x104 },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0x448 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0xf },
+	{ 0x90165, 0x7c0 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0x0 },
+	{ 0x90168, 0xe8 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x47 },
+	{ 0x9016b, 0x630 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x618 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0xe0 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x0 },
+	{ 0x90174, 0x7c8 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x8140 },
+	{ 0x90178, 0x10c },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x478 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x1 },
+	{ 0x9017e, 0x8 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x4 },
+	{ 0x90181, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x68 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x34b },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x70 },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x1c },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* Samsung K4F6E3S4HB-MGCL ddr timing config params */
+struct dram_timing_info imx8mp_skov_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
+
diff --git a/arch/arm/boards/solidrun-cubox/Makefile b/arch/arm/boards/solidrun-cubox/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/solidrun-cubox/Makefile
+++ b/arch/arm/boards/solidrun-cubox/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/solidrun-cubox/board.c b/arch/arm/boards/solidrun-cubox/board.c
index f3cb5c92f5..3c12c28594 100644
--- a/arch/arm/boards/solidrun-cubox/board.c
+++ b/arch/arm/boards/solidrun-cubox/board.c
@@ -3,7 +3,7 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/bbu.h>
+#include <mach/mvebu/bbu.h>
 
 static int cubox_devices_init(void)
 {
diff --git a/arch/arm/boards/solidrun-cubox/lowlevel.c b/arch/arm/boards/solidrun-cubox/lowlevel.c
index 94ed9a4fd7..8f1515e3b2 100644
--- a/arch/arm/boards/solidrun-cubox/lowlevel.c
+++ b/arch/arm/boards/solidrun-cubox/lowlevel.c
@@ -5,12 +5,12 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 
 extern char __dtb_dove_cubox_bb_start[];
 
-ENTRY_FUNCTION(start_solidrun_cubox, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_solidrun_cubox, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/solidrun-microsom/Makefile b/arch/arm/boards/solidrun-microsom/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/solidrun-microsom/Makefile
+++ b/arch/arm/boards/solidrun-microsom/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/solidrun-microsom/board.c b/arch/arm/boards/solidrun-microsom/board.c
index 85e1ab4250..c55dcdd74f 100644
--- a/arch/arm/boards/solidrun-microsom/board.c
+++ b/arch/arm/boards/solidrun-microsom/board.c
@@ -9,10 +9,10 @@
 #include <envfs.h>
 #include <gpio.h>
 #include <init.h>
-#include <mach/bbu.h>
-#include <mach/generic.h>
-#include <mach/imx6-regs.h>
-#include <mach/imx6.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx6.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
 #include <linux/clk.h>
 #include <linux/sizes.h>
diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg
index 2c6a32eed4..b049cfc746 100644
--- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg
+++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x10000000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 #include "800mhz-32b.imxcfg"
 #include "800mhz-2x128mx16.imxcfg"
diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg
index 7f9b2a3988..b6634446f3 100644
--- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg
+++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x10000000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 #include "800mhz-64b.imxcfg"
 #include "800mhz-4x128mx16.imxcfg"
diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg
index 7f75a17a35..e1447b9d5a 100644
--- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg
+++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x10000000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 #include "1066mhz-64b.imxcfg"
 #include "1066mhz-4x128mx16.imxcfg"
diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg
index 9d5bc03c96..ec9c3e385e 100644
--- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg
+++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x10000000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 #include "1066mhz-64b.imxcfg"
 #include "1066mhz-4x256mx16.imxcfg"
diff --git a/arch/arm/boards/solidrun-microsom/lowlevel.c b/arch/arm/boards/solidrun-microsom/lowlevel.c
index ea204e15f3..801678e777 100644
--- a/arch/arm/boards/solidrun-microsom/lowlevel.c
+++ b/arch/arm/boards/solidrun-microsom/lowlevel.c
@@ -1,7 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <asm/barebox-arm.h>
 #include <common.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 
 extern char __dtb_imx6dl_hummingboard_start[];
 extern char __dtb_imx6q_hummingboard_start[];
diff --git a/arch/arm/boards/stm32mp13xx-dk/Makefile b/arch/arm/boards/stm32mp13xx-dk/Makefile
new file mode 100644
index 0000000000..a031ae91bd
--- /dev/null
+++ b/arch/arm/boards/stm32mp13xx-dk/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += board.o
diff --git a/arch/arm/boards/stm32mp13xx-dk/board.c b/arch/arm/boards/stm32mp13xx-dk/board.c
new file mode 100644
index 0000000000..a13d934a27
--- /dev/null
+++ b/arch/arm/boards/stm32mp13xx-dk/board.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <driver.h>
+#include <init.h>
+#include <mach/stm32mp/bbu.h>
+#include <deep-probe.h>
+#include <asm/mach-types.h>
+
+static int stm32mp13xx_dk_probe(struct device *dev)
+{
+	if (machine_is_pcaaxs1())
+		return 1;
+	stm32mp_bbu_mmc_fip_register("sd", "/dev/mmc0", BBU_HANDLER_FLAG_DEFAULT);
+	return 0;
+}
+
+static const struct of_device_id stm32mp13xx_dk_of_match[] = {
+	{ .compatible = "st,stm32mp135f-dk" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(stm32mp13xx_dk_of_match);
+
+static struct driver stm32mp13xx_dk_board_driver = {
+	.name = "board-stm32mp13xx_dk",
+	.probe = stm32mp13xx_dk_probe,
+	.of_compatible = stm32mp13xx_dk_of_match,
+} ;
+device_platform_driver(stm32mp13xx_dk_board_driver);
diff --git a/arch/arm/boards/stm32mp15x-ev1/Makefile b/arch/arm/boards/stm32mp15x-ev1/Makefile
index 092c31d6b2..5678718188 100644
--- a/arch/arm/boards/stm32mp15x-ev1/Makefile
+++ b/arch/arm/boards/stm32mp15x-ev1/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
diff --git a/arch/arm/boards/stm32mp15x-ev1/board.c b/arch/arm/boards/stm32mp15x-ev1/board.c
index b8e26cd37b..fd58e2817b 100644
--- a/arch/arm/boards/stm32mp15x-ev1/board.c
+++ b/arch/arm/boards/stm32mp15x-ev1/board.c
@@ -2,10 +2,11 @@
 
 #include <bootsource.h>
 #include <common.h>
+#include <deep-probe.h>
 #include <init.h>
-#include <mach/bbu.h>
+#include <mach/stm32mp/bbu.h>
 
-static int ed1_probe(struct device_d *dev)
+static int ed1_probe(struct device *dev)
 {
 	int flags;
 
@@ -30,8 +31,9 @@ static const struct of_device_id ed1_of_match[] = {
 	{ .compatible = "st,stm32mp157c-ed1" },
 	{ /* sentinel */ },
 };
+BAREBOX_DEEP_PROBE_ENABLE(ed1_of_match);
 
-static struct driver_d ed1_board_driver = {
+static struct driver ed1_board_driver = {
 	.name = "board-stm32mp15x-ed1",
 	.probe = ed1_probe,
 	.of_compatible = ed1_of_match,
diff --git a/arch/arm/boards/stm32mp15x-ev1/lowlevel.c b/arch/arm/boards/stm32mp15x-ev1/lowlevel.c
index 06ff6291b8..13f16f8dcb 100644
--- a/arch/arm/boards/stm32mp15x-ev1/lowlevel.c
+++ b/arch/arm/boards/stm32mp15x-ev1/lowlevel.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include <common.h>
-#include <mach/entry.h>
+#include <mach/stm32mp/entry.h>
 #include <debug_ll.h>
 
 extern char __dtb_z_stm32mp157c_ev1_start[];
diff --git a/arch/arm/boards/stm32mp15xx-dkx/Makefile b/arch/arm/boards/stm32mp15xx-dkx/Makefile
index 092c31d6b2..5678718188 100644
--- a/arch/arm/boards/stm32mp15xx-dkx/Makefile
+++ b/arch/arm/boards/stm32mp15xx-dkx/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
diff --git a/arch/arm/boards/stm32mp15xx-dkx/board.c b/arch/arm/boards/stm32mp15xx-dkx/board.c
index 1ddfee698d..1783c5ca17 100644
--- a/arch/arm/boards/stm32mp15xx-dkx/board.c
+++ b/arch/arm/boards/stm32mp15xx-dkx/board.c
@@ -1,9 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include <common.h>
 #include <init.h>
-#include <mach/bbu.h>
+#include <mach/stm32mp/bbu.h>
+#include <deep-probe.h>
 
-static int dkx_probe(struct device_d *dev)
+static int dkx_probe(struct device *dev)
 {
 	const void *model;
 
@@ -23,8 +24,9 @@ static const struct of_device_id dkx_of_match[] = {
 	{ .compatible = "st,stm32mp157c-dk2", .data = "STM32MP157C-DK2" },
 	{ /* sentinel */ },
 };
+BAREBOX_DEEP_PROBE_ENABLE(dkx_of_match);
 
-static struct driver_d dkx_board_driver = {
+static struct driver dkx_board_driver = {
 	.name = "board-stm32mp15xx-dkx",
 	.probe = dkx_probe,
 	.of_compatible = dkx_of_match,
diff --git a/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c
index 65f4bbb4da..402658d592 100644
--- a/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c
+++ b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include <common.h>
-#include <mach/entry.h>
+#include <mach/stm32mp/entry.h>
 #include <debug_ll.h>
-#include <mach/revision.h>
+#include <mach/stm32mp/revision.h>
 
 extern char __dtb_z_stm32mp157c_dk2_start[];
 extern char __dtb_z_stm32mp157a_dk1_start[];
@@ -24,7 +24,7 @@ ENTRY_FUNCTION(start_stm32mp15xx_dkx, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	err = __stm32mp_get_cpu_type(&cputype);
+	err = __stm32mp15_get_cpu_type(&cputype);
 	if (!err && cputype == CPU_STM32MP157Axx)
 		fdt = __dtb_z_stm32mp157a_dk1_start;
 	else
diff --git a/arch/arm/boards/technexion-pico-hobbit/Makefile b/arch/arm/boards/technexion-pico-hobbit/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/technexion-pico-hobbit/Makefile
+++ b/arch/arm/boards/technexion-pico-hobbit/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/technexion-pico-hobbit/board.c b/arch/arm/boards/technexion-pico-hobbit/board.c
index a190959d0a..202b76bc8e 100644
--- a/arch/arm/boards/technexion-pico-hobbit/board.c
+++ b/arch/arm/boards/technexion-pico-hobbit/board.c
@@ -9,10 +9,10 @@
 #include <envfs.h>
 #include <gpio.h>
 #include <init.h>
-#include <mach/generic.h>
-#include <mach/imx6-regs.h>
-#include <mach/imx6.h>
-#include <mach/bbu.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/bbu.h>
 #include <linux/sizes.h>
 #include <linux/phy.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg
index 6d2d37de59..00ac4ef8ec 100644
--- a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg
+++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x80000000
 soc imx6
 ivtofs 0x400
diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg
index 201493e6a3..9152039507 100644
--- a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg
+++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x80000000
 soc imx6
 ivtofs 0x400
diff --git a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c
index f59c424dec..7cc7c12d84 100644
--- a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c
+++ b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c
@@ -1,12 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx6-regs.h>
+#include <mach/imx/imx6-regs.h>
 #include <io.h>
 #include <debug_ll.h>
-#include <mach/esdctl.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/esdctl.h>
 #include <asm/cache.h>
 #include <asm/sections.h>
 #include <image-metadata.h>
diff --git a/arch/arm/boards/technexion-wandboard/Makefile b/arch/arm/boards/technexion-wandboard/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/technexion-wandboard/Makefile
+++ b/arch/arm/boards/technexion-wandboard/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/technexion-wandboard/board.c b/arch/arm/boards/technexion-wandboard/board.c
index 8d63b9fff7..a594adb411 100644
--- a/arch/arm/boards/technexion-wandboard/board.c
+++ b/arch/arm/boards/technexion-wandboard/board.c
@@ -8,10 +8,10 @@
 #include <envfs.h>
 #include <gpio.h>
 #include <init.h>
-#include <mach/bbu.h>
-#include <mach/generic.h>
-#include <mach/imx6-regs.h>
-#include <mach/imx6.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx6.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
 #include <linux/sizes.h>
 #include <linux/phy.h>
diff --git a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg
index 5f91bed6f3..61425976ec 100644
--- a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg
+++ b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 loadaddr 0x00907000
 soc imx6
 max_load_size 0x11000
diff --git a/arch/arm/boards/technexion-wandboard/lowlevel.c b/arch/arm/boards/technexion-wandboard/lowlevel.c
index 33babbbb2f..d29e2c9b24 100644
--- a/arch/arm/boards/technexion-wandboard/lowlevel.c
+++ b/arch/arm/boards/technexion-wandboard/lowlevel.c
@@ -1,16 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx6-mmdc.h>
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6.h>
-#include <mach/xload.h>
-#include <mach/esdctl.h>
+#include <mach/imx/imx6-mmdc.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/esdctl.h>
 #include <serial/imx-uart.h>
 
 static void __udelay(int us)
diff --git a/arch/arm/boards/telit-evk-pro3/Makefile b/arch/arm/boards/telit-evk-pro3/Makefile
index e11fd5b692..d59545033d 100644
--- a/arch/arm/boards/telit-evk-pro3/Makefile
+++ b/arch/arm/boards/telit-evk-pro3/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/telit-evk-pro3/init.c b/arch/arm/boards/telit-evk-pro3/init.c
index 4c853c647c..43f9cbdf3a 100644
--- a/arch/arm/boards/telit-evk-pro3/init.c
+++ b/arch/arm/boards/telit-evk-pro3/init.c
@@ -9,10 +9,10 @@
 #include <linux/clk.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
+#include <mach/at91/at91_rstc.h>
+#include <mach/at91/at91sam9_smc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
 #include <nand.h>
 
 #define BOOTSTRAP_SIZE	0xC0000
diff --git a/arch/arm/boards/telit-evk-pro3/lowlevel.c b/arch/arm/boards/telit-evk-pro3/lowlevel.c
index 7f52f824df..550a0740c5 100644
--- a/arch/arm/boards/telit-evk-pro3/lowlevel.c
+++ b/arch/arm/boards/telit-evk-pro3/lowlevel.c
@@ -7,14 +7,12 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9260.h>
+#include <mach/at91/hardware.h>
 
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9260.h>
-#include <mach/hardware.h>
-
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_telit_evk_pro3, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/terasic-de0-nano-soc/Makefile b/arch/arm/boards/terasic-de0-nano-soc/Makefile
index 8c927fe291..ea898309d7 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/Makefile
+++ b/arch/arm/boards/terasic-de0-nano-soc/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += lowlevel.o board.o
 pbl-y += lowlevel.o
diff --git a/arch/arm/boards/terasic-de0-nano-soc/board.c b/arch/arm/boards/terasic-de0-nano-soc/board.c
index 8e69319d17..b4502f552a 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/board.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/board.c
@@ -1,14 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <types.h>
 #include <driver.h>
 #include <init.h>
 #include <asm/armlinux.h>
+#include <linux/mdio.h>
 #include <linux/micrel_phy.h>
 #include <linux/phy.h>
 #include <linux/sizes.h>
 #include <fcntl.h>
 #include <fs.h>
-#include <mach/cyclone5-regs.h>
+#include <mach/socfpga/cyclone5-regs.h>
 
 static int phy_fixup(struct phy_device *dev)
 {
@@ -16,15 +19,15 @@ static int phy_fixup(struct phy_device *dev)
 	 * min rx data delay, max rx/tx clock delay,
 	 * min rx/tx control delay
 	 */
-	phy_write_mmd_indirect(dev, 4, 2, 0);
-	phy_write_mmd_indirect(dev, 5, 2, 0);
-	phy_write_mmd_indirect(dev, 8, 2, 0x003ff);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 4, 0);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 5, 0);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 8, 0x003ff);
 	return 0;
 }
 
 static int socfpga_init(void)
 {
-	if (!of_machine_is_compatible("terasic,de0-nano-soc"))
+	if (!of_machine_is_compatible("terasic,de0-atlas"))
 		return 0;
 
 	if (IS_ENABLED(CONFIG_PHYLIB))
diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
index 1458e76ba8..27af250232 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <mach/cyclone5-scan-manager.h>
+#include <mach/socfpga/cyclone5-scan-manager.h>
 
 static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
 	0x00000000,
diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
index deac0e9cb2..71121b6d4c 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include "sdram_config.h"
 #include "pinmux_config.c"
 #include "pll_config.h"
@@ -7,7 +9,7 @@
 #include "sequencer_auto_ac_init.c"
 #include "iocsr_config_cyclone5.c"
 
-#include <mach/lowlevel.h>
+#include <mach/socfpga/lowlevel.h>
 
 SOCFPGA_C5_ENTRY(start_socfpga_de0_nano_soc, socfpga_cyclone5_de0_nano_soc, SZ_1G);
 SOCFPGA_C5_XLOAD_ENTRY(start_socfpga_de0_nano_soc_xload, SZ_1G);
diff --git a/arch/arm/boards/terasic-de10-nano/Makefile b/arch/arm/boards/terasic-de10-nano/Makefile
new file mode 100644
index 0000000000..ea898309d7
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += lowlevel.o board.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/terasic-de10-nano/board.c b/arch/arm/boards/terasic-de10-nano/board.c
new file mode 100644
index 0000000000..e553e26da8
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/board.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <asm/armlinux.h>
+#include <linux/mdio.h>
+#include <linux/micrel_phy.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <fcntl.h>
+#include <fs.h>
+#include <mach/socfpga/cyclone5-regs.h>
+
+static int phy_fixup(struct phy_device *dev)
+{
+	/*
+	 * min rx data delay, max rx/tx clock delay,
+	 * min rx/tx control delay
+	 */
+	phy_write_mmd(dev, MDIO_MMD_WIS, 4, 0);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 5, 0);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 8, 0x003ff);
+	return 0;
+}
+
+static int socfpga_init(void)
+{
+	if (!of_machine_is_compatible("terasic,de10-nano"))
+		return 0;
+
+	if (IS_ENABLED(CONFIG_PHYLIB))
+		phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, phy_fixup);
+
+	return 0;
+}
+console_initcall(socfpga_init);
diff --git a/arch/arm/boards/terasic-de10-nano/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de10-nano/iocsr_config_cyclone5.c
new file mode 100644
index 0000000000..2f30d836d6
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/iocsr_config_cyclone5.c
@@ -0,0 +1,678 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <mach/socfpga/cyclone5-scan-manager.h>
+
+static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]
+    = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00020000,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]
+    = {
+	0x00100000,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00060180,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x000300C0,
+	0x10000000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00020000,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x00010000,
+	0x04000000,
+	0x00000000,
+	0x00000010,
+	0x00004000,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000008,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]
+    = {
+	0x300C0300,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x000300C0,
+	0x00008000,
+	0x00080000,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00020000,
+	0x00004000,
+	0x200300C0,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x10018060,
+	0x06018000,
+	0x06000000,
+	0x00010018,
+	0x00006018,
+	0x00001000,
+	0x00010000,
+	0x00000000,
+	0x03000000,
+	0x0000800C,
+	0x00C0300C,
+	0x00000800,
+};
+
+static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]
+    = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A034D0,
+	0x180D0000,
+	0x71C06806,
+	0x01450340,
+	0xD000001A,
+	0x0680E380,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A00040,
+	0x180D0002,
+	0x71C06806,
+	0x01450340,
+	0xD00A281A,
+	0x06806180,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x79E47A03,
+	0xCAAAA3DD,
+	0xF6D5551E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x030C0680,
+	0xD559647A,
+	0x1ECAAAA3,
+	0xC8F6D965,
+	0x00034AB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x79E47A03,
+	0x8B2CA3DD,
+	0xF6D9651E,
+	0x034AB2C8,
+	0x821A0041,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0xC8F6D965,
+	0x00034AB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8AAAA3D5,
+	0xF6D9651E,
+	0x034AB2C8,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0xC8F6D965,
+	0x00034AB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8B2CA3D5,
+	0xF6D9651E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0x48F6D965,
+	0x000352D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
diff --git a/arch/arm/boards/terasic-de10-nano/lowlevel.c b/arch/arm/boards/terasic-de10-nano/lowlevel.c
new file mode 100644
index 0000000000..74c8aec99d
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/lowlevel.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "sdram_config.h"
+#include "pinmux_config.c"
+#include "pll_config.h"
+#include "sequencer_defines.h"
+#include "sequencer_auto.h"
+#include "sequencer_auto_inst_init.c"
+#include "sequencer_auto_ac_init.c"
+#include "iocsr_config_cyclone5.c"
+
+#include <mach/socfpga/lowlevel.h>
+
+SOCFPGA_C5_ENTRY(start_socfpga_de10_nano, socfpga_cyclone5_de10_nano, SZ_1G);
+SOCFPGA_C5_XLOAD_ENTRY(start_socfpga_de10_nano_xload, SZ_1G);
diff --git a/arch/arm/boards/terasic-de10-nano/pinmux_config.c b/arch/arm/boards/terasic-de10-nano/pinmux_config.c
new file mode 100644
index 0000000000..7dbe1c1d1f
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/pinmux_config.c
@@ -0,0 +1,241 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <common.h>
+
+/* pin MUX configuration data */
+static unsigned long sys_mgr_init_table[] = {
+	0,			/* EMACIO0 */
+	2,			/* EMACIO1 */
+	2,			/* EMACIO2 */
+	2,			/* EMACIO3 */
+	2,			/* EMACIO4 */
+	2,			/* EMACIO5 */
+	2,			/* EMACIO6 */
+	2,			/* EMACIO7 */
+	2,			/* EMACIO8 */
+	0,			/* EMACIO9 */
+	2,			/* EMACIO10 */
+	2,			/* EMACIO11 */
+	2,			/* EMACIO12 */
+	2,			/* EMACIO13 */
+	0,			/* EMACIO14 */
+	0,			/* EMACIO15 */
+	0,			/* EMACIO16 */
+	0,			/* EMACIO17 */
+	0,			/* EMACIO18 */
+	0,			/* EMACIO19 */
+	3,			/* FLASHIO0 */
+	0,			/* FLASHIO1 */
+	3,			/* FLASHIO2 */
+	3,			/* FLASHIO3 */
+	0,			/* FLASHIO4 */
+	0,			/* FLASHIO5 */
+	0,			/* FLASHIO6 */
+	0,			/* FLASHIO7 */
+	0,			/* FLASHIO8 */
+	3,			/* FLASHIO9 */
+	3,			/* FLASHIO10 */
+	3,			/* FLASHIO11 */
+	0,			/* GENERALIO0 */
+	1,			/* GENERALIO1 */
+	1,			/* GENERALIO2 */
+	1,			/* GENERALIO3 */
+	1,			/* GENERALIO4 */
+	0,			/* GENERALIO5 */
+	0,			/* GENERALIO6 */
+	1,			/* GENERALIO7 */
+	1,			/* GENERALIO8 */
+	0,			/* GENERALIO9 */
+	0,			/* GENERALIO10 */
+	0,			/* GENERALIO11 */
+	0,			/* GENERALIO12 */
+	0,			/* GENERALIO13 */
+	0,			/* GENERALIO14 */
+	1,			/* GENERALIO15 */
+	1,			/* GENERALIO16 */
+	1,			/* GENERALIO17 */
+	1,			/* GENERALIO18 */
+	0,			/* GENERALIO19 */
+	0,			/* GENERALIO20 */
+	0,			/* GENERALIO21 */
+	0,			/* GENERALIO22 */
+	0,			/* GENERALIO23 */
+	0,			/* GENERALIO24 */
+	0,			/* GENERALIO25 */
+	0,			/* GENERALIO26 */
+	0,			/* GENERALIO27 */
+	0,			/* GENERALIO28 */
+	0,			/* GENERALIO29 */
+	0,			/* GENERALIO30 */
+	0,			/* GENERALIO31 */
+	2,			/* MIXED1IO0 */
+	2,			/* MIXED1IO1 */
+	2,			/* MIXED1IO2 */
+	2,			/* MIXED1IO3 */
+	2,			/* MIXED1IO4 */
+	2,			/* MIXED1IO5 */
+	2,			/* MIXED1IO6 */
+	2,			/* MIXED1IO7 */
+	2,			/* MIXED1IO8 */
+	2,			/* MIXED1IO9 */
+	2,			/* MIXED1IO10 */
+	2,			/* MIXED1IO11 */
+	2,			/* MIXED1IO12 */
+	2,			/* MIXED1IO13 */
+	0,			/* MIXED1IO14 */
+	0,			/* MIXED1IO15 */
+	0,			/* MIXED1IO16 */
+	0,			/* MIXED1IO17 */
+	0,			/* MIXED1IO18 */
+	0,			/* MIXED1IO19 */
+	0,			/* MIXED1IO20 */
+	0,			/* MIXED1IO21 */
+	0,			/* MIXED2IO0 */
+	0,			/* MIXED2IO1 */
+	0,			/* MIXED2IO2 */
+	0,			/* MIXED2IO3 */
+	0,			/* MIXED2IO4 */
+	0,			/* MIXED2IO5 */
+	0,			/* MIXED2IO6 */
+	0,			/* MIXED2IO7 */
+	0,			/* GPLINMUX48 */
+	0,			/* GPLINMUX49 */
+	0,			/* GPLINMUX50 */
+	0,			/* GPLINMUX51 */
+	0,			/* GPLINMUX52 */
+	0,			/* GPLINMUX53 */
+	0,			/* GPLINMUX54 */
+	0,			/* GPLINMUX55 */
+	0,			/* GPLINMUX56 */
+	0,			/* GPLINMUX57 */
+	0,			/* GPLINMUX58 */
+	0,			/* GPLINMUX59 */
+	0,			/* GPLINMUX60 */
+	0,			/* GPLINMUX61 */
+	0,			/* GPLINMUX62 */
+	0,			/* GPLINMUX63 */
+	0,			/* GPLINMUX64 */
+	0,			/* GPLINMUX65 */
+	0,			/* GPLINMUX66 */
+	0,			/* GPLINMUX67 */
+	0,			/* GPLINMUX68 */
+	0,			/* GPLINMUX69 */
+	0,			/* GPLINMUX70 */
+	1,			/* GPLMUX0 */
+	1,			/* GPLMUX1 */
+	1,			/* GPLMUX2 */
+	1,			/* GPLMUX3 */
+	1,			/* GPLMUX4 */
+	1,			/* GPLMUX5 */
+	1,			/* GPLMUX6 */
+	1,			/* GPLMUX7 */
+	1,			/* GPLMUX8 */
+	1,			/* GPLMUX9 */
+	1,			/* GPLMUX10 */
+	1,			/* GPLMUX11 */
+	1,			/* GPLMUX12 */
+	1,			/* GPLMUX13 */
+	1,			/* GPLMUX14 */
+	1,			/* GPLMUX15 */
+	1,			/* GPLMUX16 */
+	1,			/* GPLMUX17 */
+	1,			/* GPLMUX18 */
+	1,			/* GPLMUX19 */
+	1,			/* GPLMUX20 */
+	1,			/* GPLMUX21 */
+	1,			/* GPLMUX22 */
+	1,			/* GPLMUX23 */
+	1,			/* GPLMUX24 */
+	1,			/* GPLMUX25 */
+	1,			/* GPLMUX26 */
+	1,			/* GPLMUX27 */
+	1,			/* GPLMUX28 */
+	1,			/* GPLMUX29 */
+	1,			/* GPLMUX30 */
+	1,			/* GPLMUX31 */
+	1,			/* GPLMUX32 */
+	1,			/* GPLMUX33 */
+	1,			/* GPLMUX34 */
+	1,			/* GPLMUX35 */
+	1,			/* GPLMUX36 */
+	1,			/* GPLMUX37 */
+	1,			/* GPLMUX38 */
+	1,			/* GPLMUX39 */
+	1,			/* GPLMUX40 */
+	1,			/* GPLMUX41 */
+	1,			/* GPLMUX42 */
+	1,			/* GPLMUX43 */
+	1,			/* GPLMUX44 */
+	1,			/* GPLMUX45 */
+	1,			/* GPLMUX46 */
+	1,			/* GPLMUX47 */
+	1,			/* GPLMUX48 */
+	1,			/* GPLMUX49 */
+	1,			/* GPLMUX50 */
+	1,			/* GPLMUX51 */
+	1,			/* GPLMUX52 */
+	1,			/* GPLMUX53 */
+	1,			/* GPLMUX54 */
+	1,			/* GPLMUX55 */
+	1,			/* GPLMUX56 */
+	1,			/* GPLMUX57 */
+	1,			/* GPLMUX58 */
+	1,			/* GPLMUX59 */
+	1,			/* GPLMUX60 */
+	1,			/* GPLMUX61 */
+	1,			/* GPLMUX62 */
+	1,			/* GPLMUX63 */
+	1,			/* GPLMUX64 */
+	1,			/* GPLMUX65 */
+	1,			/* GPLMUX66 */
+	1,			/* GPLMUX67 */
+	1,			/* GPLMUX68 */
+	1,			/* GPLMUX69 */
+	1,			/* GPLMUX70 */
+	0,			/* NANDUSEFPGA */
+	0,			/* UART0USEFPGA */
+	0,			/* RGMII1USEFPGA */
+	0,			/* SPIS0USEFPGA */
+	0,			/* CAN0USEFPGA */
+	0,			/* I2C0USEFPGA */
+	0,			/* SDMMCUSEFPGA */
+	0,			/* QSPIUSEFPGA */
+	0,			/* SPIS1USEFPGA */
+	0,			/* RGMII0USEFPGA */
+	0,			/* UART1USEFPGA */
+	0,			/* CAN1USEFPGA */
+	0,			/* USB1USEFPGA */
+	0,			/* I2C3USEFPGA */
+	0,			/* I2C2USEFPGA */
+	0,			/* I2C1USEFPGA */
+	0,			/* SPIM1USEFPGA */
+	0,			/* USB0USEFPGA */
+	0			/* SPIM0USEFPGA */
+};
diff --git a/arch/arm/boards/terasic-de10-nano/pll_config.h b/arch/arm/boards/terasic-de10-nano/pll_config.h
new file mode 100644
index 0000000000..d78eaae98a
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/pll_config.h
@@ -0,0 +1,107 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 (1)
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
+
+#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
+#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)
+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
+#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
+#define CONFIG_HPS_CLK_EMAC0_HZ (1953125)
+#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
+#define CONFIG_HPS_CLK_NAND_HZ (50000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
+#define CONFIG_HPS_CLK_QSPI_HZ (3125000)
+#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
+#define CONFIG_HPS_CLK_CAN0_HZ (12500000)
+#define CONFIG_HPS_CLK_CAN1_HZ (12500000)
+#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK (1)
+#define CONFIG_HPS_ALTERAGRP_MAINCLK (3)
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/arch/arm/boards/terasic-de10-nano/sdram_config.h b/arch/arm/boards/terasic-de10-nano/sdram_config.h
new file mode 100644
index 0000000000..8f084021d5
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/sdram_config.h
@@ -0,0 +1,112 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the name of Altera Corporation nor the
+ *      names of its contributors may be used to endorse or promote products
+ *      derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SDRAM_CONFIG_H
+#define __SDRAM_CONFIG_H
+
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			(2)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			(8)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		(0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		(0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		(1)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		(10)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			(7)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			(7)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			(3)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			(15)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			(120)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		(3120)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		(6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		(6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		(6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		(4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			(3)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			(14)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			(20)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			(4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			(4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		(512)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		(3)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	(0)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	(8)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		(10)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		(15)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		(3)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			(1)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		(32)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		(8)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		(3)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			(2)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		(0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		(2)
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		(0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		(0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	(0x21084210)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	(0x10441)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	(0x78)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	(0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	(0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		(0x200)
+
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		(0x44555)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		(0x2C011000)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		(0xB00088)
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		(0x760210)
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		(0x980543)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		(0x5A56A)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	(0x20820820)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	(0x8208208)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	(0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	(0x41041041)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	(0x410410)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
+(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
+(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
+(0x0101)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			(0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			(1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED	(0xF)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED	(0xF)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED	(0x1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			(0x1FF)
+
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR (2)
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC (2)
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2)
+
+#endif /*#ifndef__SDRAM_CONFIG_H */
diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_auto.h b/arch/arm/boards/terasic-de10-nano/sequencer_auto.h
new file mode 100644
index 0000000000..34dc3108aa
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/sequencer_auto.h
@@ -0,0 +1,225 @@
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Intel Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#define __RW_MGR_ac_mrs1 0x04
+#define __RW_MGR_ac_mrs3 0x06
+#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C
+#define __RW_MGR_ac_act_1 0x11
+#define __RW_MGR_ac_write_postdata 0x1A
+#define __RW_MGR_ac_act_0 0x10
+#define __RW_MGR_ac_des 0x0D
+#define __RW_MGR_ac_init_reset_1_cke_0 0x01
+#define __RW_MGR_ac_write_data 0x19
+#define __RW_MGR_ac_init_reset_0_cke_0 0x00
+#define __RW_MGR_ac_read_bank_0_1_norden 0x22
+#define __RW_MGR_ac_pre_all 0x12
+#define __RW_MGR_ac_mrs0_user 0x02
+#define __RW_MGR_ac_mrs0_dll_reset 0x03
+#define __RW_MGR_ac_read_bank_0_0 0x1D
+#define __RW_MGR_ac_write_bank_0_col_1 0x16
+#define __RW_MGR_ac_read_bank_0_1 0x1F
+#define __RW_MGR_ac_write_bank_1_col_0 0x15
+#define __RW_MGR_ac_write_bank_1_col_1 0x17
+#define __RW_MGR_ac_write_bank_0_col_0 0x14
+#define __RW_MGR_ac_read_bank_1_0 0x1E
+#define __RW_MGR_ac_mrs1_mirr 0x0A
+#define __RW_MGR_ac_read_bank_1_1 0x20
+#define __RW_MGR_ac_des_odt_1 0x0E
+#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09
+#define __RW_MGR_ac_zqcl 0x07
+#define __RW_MGR_ac_write_predata 0x18
+#define __RW_MGR_ac_mrs0_user_mirr 0x08
+#define __RW_MGR_ac_ref 0x13
+#define __RW_MGR_ac_nop 0x0F
+#define __RW_MGR_ac_rdimm 0x23
+#define __RW_MGR_ac_mrs2_mirr 0x0B
+#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B
+#define __RW_MGR_ac_read_en 0x21
+#define __RW_MGR_ac_mrs3_mirr 0x0C
+#define __RW_MGR_ac_mrs2 0x05
+#define __RW_MGR_CONTENT_ac_mrs1 0x10090044
+#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000
+#define __RW_MGR_CONTENT_ac_act_1 0x106B0000
+#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000
+#define __RW_MGR_CONTENT_ac_act_0 0x10680000
+#define __RW_MGR_CONTENT_ac_des 0x30780000
+#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000
+#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000
+#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000
+#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008
+#define __RW_MGR_CONTENT_ac_pre_all 0x10280400
+#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080431
+#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080530
+#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008
+#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008
+#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000
+#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000
+#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000
+#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0024
+#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008
+#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000
+#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100804C8
+#define __RW_MGR_CONTENT_ac_zqcl 0x10380400
+#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000
+#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080449
+#define __RW_MGR_CONTENT_ac_ref 0x10480000
+#define __RW_MGR_CONTENT_ac_nop 0x30780000
+#define __RW_MGR_CONTENT_ac_rdimm 0x10780000
+#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090008
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000
+#define __RW_MGR_CONTENT_ac_read_en 0x33780000
+#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000
+#define __RW_MGR_CONTENT_ac_mrs2 0x100A0010
+
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Intel Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#define __RW_MGR_READ_B2B_WAIT2 0x6B
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define __RW_MGR_REFRESH_ALL 0x14
+#define __RW_MGR_ZQCL 0x06
+#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define __RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define __RW_MGR_MRS2_MIRR 0x0A
+#define __RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define __RW_MGR_ACTIVATE_1 0x0F
+#define __RW_MGR_MRS2 0x04
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define __RW_MGR_MRS1 0x03
+#define __RW_MGR_IDLE_LOOP1 0x7B
+#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define __RW_MGR_MRS3 0x05
+#define __RW_MGR_IDLE_LOOP2 0x7A
+#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define __RW_MGR_RDIMM_CMD 0x79
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define __RW_MGR_GUARANTEED_READ_CONT 0x54
+#define __RW_MGR_REFRESH_DELAY 0x15
+#define __RW_MGR_MRS3_MIRR 0x0B
+#define __RW_MGR_IDLE 0x00
+#define __RW_MGR_READ_B2B 0x59
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define __RW_MGR_GUARANTEED_WRITE 0x18
+#define __RW_MGR_PRECHARGE_ALL 0x12
+#define __RW_MGR_SGLE_READ 0x7D
+#define __RW_MGR_MRS0_USER_MIRR 0x0C
+#define __RW_MGR_RETURN 0x01
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define __RW_MGR_MRS0_USER 0x07
+#define __RW_MGR_GUARANTEED_READ 0x4C
+#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define __RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define __RW_MGR_MRS0_DLL_RESET 0x02
+#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define __RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define __RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define __RW_MGR_MRS1_MIRR 0x09
+#define __RW_MGR_READ_B2B_WAIT1 0x61
+#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
+#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980
+#define __RW_MGR_CONTENT_ZQCL 0x008380
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
+#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580
+#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
+#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880
+#define __RW_MGR_CONTENT_MRS2 0x008280
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
+#define __RW_MGR_CONTENT_MRS1 0x008200
+#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
+#define __RW_MGR_CONTENT_MRS3 0x008300
+#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
+#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
+#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
+#define __RW_MGR_CONTENT_REFRESH_DELAY 0x00A680
+#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600
+#define __RW_MGR_CONTENT_IDLE 0x080000
+#define __RW_MGR_CONTENT_READ_B2B 0x040E88
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
+#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
+#define __RW_MGR_CONTENT_SGLE_READ 0x040F08
+#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
+#define __RW_MGR_CONTENT_RETURN 0x080680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
+#define __RW_MGR_CONTENT_MRS0_USER 0x008100
+#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168
+#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
+#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
+#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
+#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
+#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500
+#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-de10-nano/sequencer_auto_ac_init.c
new file mode 100644
index 0000000000..05f1609674
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/sequencer_auto_ac_init.c
@@ -0,0 +1,67 @@
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Intel Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+static const uint32_t ac_rom_init_size = 36;
+static const uint32_t ac_rom_init[36] = {
+	0x20700000,
+	0x20780000,
+	0x10080431,
+	0x10080530,
+	0x10090044,
+	0x100a0010,
+	0x100b0000,
+	0x10380400,
+	0x10080449,
+	0x100804c8,
+	0x100a0024,
+	0x10090008,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_auto_inst_init.c b/arch/arm/boards/terasic-de10-nano/sequencer_auto_inst_init.c
new file mode 100644
index 0000000000..2ca79c65a5
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/sequencer_auto_inst_init.c
@@ -0,0 +1,158 @@
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Intel Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+static const uint32_t inst_rom_init_size = 127;
+static const uint32_t inst_rom_init[127] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_defines.h b/arch/arm/boards/terasic-de10-nano/sequencer_defines.h
new file mode 100644
index 0000000000..98d0475cbd
--- /dev/null
+++ b/arch/arm/boards/terasic-de10-nano/sequencer_defines.h
@@ -0,0 +1,165 @@
+/*
+Copyright (C) 2016 Intel Corporation
+All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#ifndef _SEQUENCER_DEFINES_H_
+#define _SEQUENCER_DEFINES_H_
+
+#define AC_ROM_MR1_MIRR 0000000100100
+#define AC_ROM_MR1_OCD_ENABLE
+#define AC_ROM_MR2_MIRR 0000000001000
+#define AC_ROM_MR3_MIRR 0000000000000
+#define AC_ROM_MR0_CALIB
+#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000
+#define AC_ROM_MR0_DLL_RESET 0010100110000
+#define AC_ROM_MR0_MIRR 0010001001001
+#define AC_ROM_MR0 0010000110001
+#define AC_ROM_MR1 0000001000100
+#define AC_ROM_MR2 0000000010000
+#define AC_ROM_MR3 0000000000000
+#define AC_ROM_USER_ADD_0 0_0000_0000_0000
+#define AC_ROM_USER_ADD_1 0_0000_0000_1000
+#define AFI_CLK_FREQ 401
+#define AFI_RATE_RATIO 1
+#define AP_MODE 0
+#define ARRIAVGZ 0
+#define ARRIAV 0
+#define AVL_CLK_FREQ 67
+#define BFM_MODE 0
+#define BURST2 0
+#define CALIBRATE_BIT_SLIPS 0
+#define CALIB_LFIFO_OFFSET 8
+#define CALIB_VFIFO_OFFSET 6
+#define CYCLONEV 1
+#define DDR2 0
+#define DDR3 1
+#define DDRX 1
+#define DM_PINS_ENABLED 1
+#define ENABLE_ASSERT 0
+#define ENABLE_BRINGUP_DEBUGGING 0
+#define ENABLE_DELAY_CHAIN_WRITE 0
+#define ENABLE_DQS_IN_CENTERING 1
+#define ENABLE_DQS_OUT_CENTERING 0
+#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
+#define ENABLE_INST_ROM_WRITE 1
+#define ENABLE_MARGIN_REPORT_GEN 0
+#define ENABLE_NON_DESTRUCTIVE_CALIB 0
+#define ENABLE_NON_DES_CAL_TEST 0
+#define ENABLE_NON_DES_CAL 0
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define ENABLE_TCL_DEBUG 0
+#define FAKE_CAL_FAIL 0
+#define FIX_READ_LATENCY 8
+#define FULL_RATE 1
+#define GUARANTEED_READ_BRINGUP_TEST 0
+#define HALF_RATE 0
+#define HARD_PHY 1
+#define HARD_VFIFO 1
+#define HCX_COMPAT_MODE 0
+#define HHP_HPS_SIMULATION 0
+#define HHP_HPS_VERIFICATION 0
+#define HHP_HPS 1
+#define HPS_HW 1
+#define HR_DDIO_OUT_HAS_THREE_REGS 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DM_OUT_RESERVE 0
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_DQ_OUT_RESERVE 0
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define LPDDR1 0
+#define LPDDR2 0
+#define LRDIMM 0
+#define MARGIN_VARIATION_TEST 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define MEM_ADDR_WIDTH 13
+#define MRS_MIRROR_PING_PONG_ATSO 0
+#define MULTIPLE_AFI_WLAT 0
+#define NON_DES_CAL 0
+#define NUM_SHADOW_REGS 1
+#define QDRII 0
+#define QUARTER_RATE 0
+#define RDIMM 0
+#define READ_AFTER_WRITE_CALIBRATION 1
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504c9
+#define RLDRAM3 0
+#define RLDRAMII 0
+#define RLDRAMX 0
+#define RUNTIME_CAL_REPORT 0
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_ADDRESS_WIDTH 15
+#define RW_MGR_MEM_BANK_WIDTH 3
+#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
+#define RW_MGR_MEM_CLK_EN_WIDTH 1
+#define RW_MGR_MEM_CONTROL_WIDTH 1
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_ODT_WIDTH 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_MR0_BL 1
+#define RW_MGR_MR0_CAS_LATENCY 3
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
+#define SET_FIX_READ_LATENCY_ENABLE 0
+#define SKEW_CALIBRATION 0
+#define SKIP_PTAP_0_DQS_EN_CAL 1
+#define STATIC_FULL_CALIBRATION 1
+#define STATIC_SIM_FILESET 0
+#define STATIC_SKIP_MEM_INIT 0
+#define STRATIXV 0
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TINIT_CNTR0_VAL 99
+#define TRACKING_ERROR_TEST 0
+#define TRACKING_WATCH_TEST 0
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+#define TRESET_CNTR0_VAL 99
+#define USE_DQS_TRACKING 1
+#define USE_SHADOW_REGS 0
+#define USE_USER_RDIMM_VALUE 0
+
+#endif /* _SEQUENCER_DEFINES_H_ */
diff --git a/arch/arm/boards/terasic-sockit/Makefile b/arch/arm/boards/terasic-sockit/Makefile
index 8c927fe291..ea898309d7 100644
--- a/arch/arm/boards/terasic-sockit/Makefile
+++ b/arch/arm/boards/terasic-sockit/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += lowlevel.o board.o
 pbl-y += lowlevel.o
diff --git a/arch/arm/boards/terasic-sockit/board.c b/arch/arm/boards/terasic-sockit/board.c
index ec68315998..a3537fe6e3 100644
--- a/arch/arm/boards/terasic-sockit/board.c
+++ b/arch/arm/boards/terasic-sockit/board.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <types.h>
 #include <driver.h>
@@ -25,7 +27,7 @@ static int phy_fixup(struct phy_device *dev)
 
 static int socfpga_console_init(void)
 {
-	if (!of_machine_is_compatible("terasic,sockit"))
+	if (!of_machine_is_compatible("terasic,socfpga-cyclone5-sockit"))
 		return 0;
 
 	if (IS_ENABLED(CONFIG_PHYLIB))
diff --git a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
index 9367b0d110..8e5b02be2f 100644
--- a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <mach/cyclone5-scan-manager.h>
+#include <mach/socfpga/cyclone5-scan-manager.h>
 
 static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
 	0x00000000,
diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c
index 1dd7940aeb..9ce0fd4423 100644
--- a/arch/arm/boards/terasic-sockit/lowlevel.c
+++ b/arch/arm/boards/terasic-sockit/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include "sdram_config.h"
 #include "pinmux_config.c"
 #include "pll_config.h"
@@ -7,7 +9,7 @@
 #include "sequencer_auto_ac_init.c"
 #include "iocsr_config_cyclone5.c"
 
-#include <mach/lowlevel.h>
+#include <mach/socfpga/lowlevel.h>
 
 static inline void ledon(int led)
 {
diff --git a/arch/arm/boards/tny-a926x/Makefile b/arch/arm/boards/tny-a926x/Makefile
index d400788757..1ebe527d60 100644
--- a/arch/arm/boards/tny-a926x/Makefile
+++ b/arch/arm/boards/tny-a926x/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 obj-$(CONFIG_AT91_BOOTSTRAP) += tny_a9263_bootstrap.o
diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c
index 2df8efd448..0a448aa822 100644
--- a/arch/arm/boards/tny-a926x/init.c
+++ b/arch/arm/boards/tny-a926x/init.c
@@ -6,25 +6,24 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/clk.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
+#include <mach/at91/at91sam9_sdramc.h>
 #include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
 #include <spi/eeprom.h>
 
 static void tny_a9260_set_board_type(void)
diff --git a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c
index 7f52f824df..91bf68e798 100644
--- a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c
+++ b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c
@@ -7,14 +7,23 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9260.h>
+#include <mach/at91/hardware.h>
 
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9260.h>
-#include <mach/hardware.h>
+AT91_ENTRY_FUNCTION(start_tny_a9260, r0, r1, r2)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_tny_a9g20, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c
index f26f1eaecb..5739b0f2da 100644
--- a/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c
+++ b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <bootstrap.h>
-#include <mach/bootstrap.h>
+#include <mach/at91/bootstrap.h>
 
 #ifdef CONFIG_MTD_DATAFLASH
 void * bootstrap_board_read_dataflash(void)
diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
index 565ba438d2..d20ffe9c71 100644
--- a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
+++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
@@ -7,11 +7,9 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
-
-#include <mach/at91sam926x_board_init.h>
-#include <mach/at91sam9263_matrix.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam926x_board_init.h>
+#include <mach/at91/at91sam9263_matrix.h>
 
 #define MASTER_CLOCK		180
 
@@ -118,7 +116,7 @@ static void __bare_init tny_a9263_init(void)
 	                  NULL);
 }
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_tny_a9263, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/toradex-colibri-t20/Makefile b/arch/arm/boards/toradex-colibri-t20/Makefile
index cdce48d1f8..aeb4765cf6 100644
--- a/arch/arm/boards/toradex-colibri-t20/Makefile
+++ b/arch/arm/boards/toradex-colibri-t20/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t
 soc := tegra20
 lwl-y += entry.o
diff --git a/arch/arm/boards/toradex-colibri-t20/entry.c b/arch/arm/boards/toradex-colibri-t20/entry.c
index 955052f03f..af55689402 100644
--- a/arch/arm/boards/toradex-colibri-t20/entry.c
+++ b/arch/arm/boards/toradex-colibri-t20/entry.c
@@ -2,7 +2,7 @@
 // SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de>
 
 #include <common.h>
-#include <mach/lowlevel.h>
+#include <mach/tegra/lowlevel.h>
 
 extern char __dtb_tegra20_colibri_iris_start[];
 
diff --git a/arch/arm/boards/toshiba-ac100/Makefile b/arch/arm/boards/toshiba-ac100/Makefile
index e8158cb253..702c86a924 100644
--- a/arch/arm/boards/toshiba-ac100/Makefile
+++ b/arch/arm/boards/toshiba-ac100/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t
 lwl-y += entry.o
 obj-y += board.o
diff --git a/arch/arm/boards/toshiba-ac100/board.c b/arch/arm/boards/toshiba-ac100/board.c
index 01aaf47034..7fb70ca6c9 100644
--- a/arch/arm/boards/toshiba-ac100/board.c
+++ b/arch/arm/boards/toshiba-ac100/board.c
@@ -5,8 +5,8 @@
 
 #include <common.h>
 #include <init.h>
-#include <usb/ehci.h>
-#include <mach/iomap.h>
+#include <linux/usb/ehci.h>
+#include <mach/tegra/iomap.h>
 
 static struct ehci_platform_data ehci_pdata = {
 	.flags = EHCI_HAS_TT,
diff --git a/arch/arm/boards/toshiba-ac100/entry.c b/arch/arm/boards/toshiba-ac100/entry.c
index 918ca4b9d8..1cb5b1c0d0 100644
--- a/arch/arm/boards/toshiba-ac100/entry.c
+++ b/arch/arm/boards/toshiba-ac100/entry.c
@@ -2,7 +2,7 @@
 // SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de>
 
 #include <common.h>
-#include <mach/lowlevel.h>
+#include <mach/tegra/lowlevel.h>
 
 extern char __dtb_tegra20_paz00_start[];
 
diff --git a/arch/arm/boards/tqma53/Makefile b/arch/arm/boards/tqma53/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/tqma53/Makefile
+++ b/arch/arm/boards/tqma53/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c
index 14e514ee78..7d81594df8 100644
--- a/arch/arm/boards/tqma53/board.c
+++ b/arch/arm/boards/tqma53/board.c
@@ -7,8 +7,8 @@
 #include <init.h>
 
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <mach/bbu.h>
+#include <asm/mach-types.h>
+#include <mach/imx/bbu.h>
 
 static int tqma53_devices_init(void)
 {
diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg b/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg
index 50a8f27dc5..6aeff80de5 100644
--- a/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg
+++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #define SETUP_512MIB_1GIB \
 	wm 32 0x63fd9018 0x00011740; \
 	wm 32 0x63fd9000 0xc3190000
diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg b/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg
index 4c8eed40d2..2431d6f039 100644
--- a/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg
+++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #define SETUP_512MIB_1GIB \
 	wm 32 0x63fd9018 0x00101740; \
 	wm 32 0x63fd9000 0x83190000
diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h
index b9492bbcb3..a11855f926 100644
--- a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h
+++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx53
 loadaddr 0x70000000
 ivtofs 0x400
diff --git a/arch/arm/boards/tqma53/flash-header.imxcfg b/arch/arm/boards/tqma53/flash-header.imxcfg
index bbe2300ece..6981a230a5 100644
--- a/arch/arm/boards/tqma53/flash-header.imxcfg
+++ b/arch/arm/boards/tqma53/flash-header.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx53
 loadaddr 0x70000000
 ivtofs 0x400
diff --git a/arch/arm/boards/tqma53/lowlevel.c b/arch/arm/boards/tqma53/lowlevel.c
index 97a7ac556e..898b251d66 100644
--- a/arch/arm/boards/tqma53/lowlevel.c
+++ b/arch/arm/boards/tqma53/lowlevel.c
@@ -1,12 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <debug_ll.h>
 #include <io.h>
-#include <mach/esdctl.h>
+#include <mach/imx/esdctl.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx5.h>
-#include <mach/imx53-regs.h>
-#include <mach/generic.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/generic.h>
 #include <image-metadata.h>
 
 extern char __dtb_imx53_mba53_start[];
diff --git a/arch/arm/boards/kindle3/Makefile b/arch/arm/boards/tqma6ulx/Makefile
index 86c746240e..01c7a259e9 100644
--- a/arch/arm/boards/kindle3/Makefile
+++ b/arch/arm/boards/tqma6ulx/Makefile
@@ -1,2 +1,2 @@
-obj-y += kindle3.o
+obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/tqma6ulx/board.c b/arch/arm/boards/tqma6ulx/board.c
new file mode 100644
index 0000000000..c559568880
--- /dev/null
+++ b/arch/arm/boards/tqma6ulx/board.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2021 Rouven Czerwinski, Pengutronix
+ */
+#define pr_fmt(fmt) "tqma6ul: " fmt
+
+#include <common.h>
+#include <bootsource.h>
+#include <init.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/bbu.h>
+#include <of.h>
+#include <string.h>
+#include <linux/clk.h>
+#include <asm/optee.h>
+#include <asm-generic/memory_layout.h>
+
+#include "tqma6ulx.h"
+
+static const struct of_device_id mba6ulx_of_match[] = {
+	{ .compatible = "tq,imx6ul-tqma6ul2l" },
+	{ .compatible = "tq,imx6ul-tqma6ul2" },
+	{ .compatible = "tq,imx6ull-tqma6ull2" },
+	{ .compatible = "tq,imx6ull-tqma6ull2l" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mba6ulx_of_match);
+
+#ifdef CONFIG_FIRMWARE_TQMA6UL_OPTEE
+
+static int mba6ulx_optee_fixup(void)
+{
+	struct device_node *overlay;
+	struct fdt_header *fdt;
+	struct device_node *root = of_get_root_node();
+	int ret;
+
+	if (!of_match_node(mba6ulx_of_match, root))
+		return 0;
+
+	fdt = (void*)OPTEE_OVERLAY_LOCATION;
+	overlay = of_unflatten_dtb(fdt, INT_MAX);
+
+	if (IS_ERR(overlay))
+		return PTR_ERR(overlay);
+
+	/* register the overlay for fixing up the kernel device tree */
+	ret = of_register_overlay(overlay);
+	if (ret) {
+		printf("cannot apply oftree overlay: %s\n", strerror(-ret));
+		goto err;
+	}
+
+	/*
+	 * Apply the overlay to the live tree to enable OP-TEE support
+	 * for barebox and to reserve the SDRAM regions occupied by
+	 * OP-TEE
+	 */
+	of_overlay_apply_tree(root, overlay);
+
+	return 0;
+err:
+	of_delete_node(overlay);
+
+	return ret;
+}
+postcore_initcall(mba6ulx_optee_fixup);
+
+#endif
+
+static int mba6ulx_probe(struct device *dev)
+{
+	int flags;
+	struct clk *clk;
+
+	clk = clk_lookup("enet_ref_125m");
+	if (IS_ERR(clk))
+		pr_err("Cannot find enet_ref_125m: %pe\n", clk);
+	else
+		clk_enable(clk);
+
+	/* the bootloader is stored in one of the two boot partitions */
+	flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0;
+	imx6_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", flags);
+
+	flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0;
+	imx6_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", flags);
+
+	if (bootsource_get_instance() == 0)
+		of_device_enable_path("/chosen/environment-sd");
+	else
+		of_device_enable_path("/chosen/environment-emmc");
+
+	return 0;
+}
+
+static struct driver mba6ulx_board_driver = {
+	.name = "board-mba6ulx",
+	.probe = mba6ulx_probe,
+	.of_compatible = mba6ulx_of_match,
+};
+device_platform_driver(mba6ulx_board_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(mba6ulx_of_match);
diff --git a/arch/arm/boards/tqma6ulx/flash-header-imx6ul-tqma6ulx.imxcfg b/arch/arm/boards/tqma6ulx/flash-header-imx6ul-tqma6ulx.imxcfg
new file mode 100644
index 0000000000..ac4b853ced
--- /dev/null
+++ b/arch/arm/boards/tqma6ulx/flash-header-imx6ul-tqma6ulx.imxcfg
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+loadaddr 0x80000000
+soc imx6
+ivtofs 0x400
+
+/* Enable all clocks */
+wm 32 0x020c4068 0xffffffff
+wm 32 0x020c406c 0xffffffff
+wm 32 0x020c4070 0xffffffff
+wm 32 0x020c4074 0xffffffff
+wm 32 0x020c4078 0xffffffff
+wm 32 0x020c407c 0xffffffff
+wm 32 0x020c4080 0xffffffff
+
+/* This flash header contains support for the LGA Variant */
+/*
+ * =====================================================================
+ * IOMUX
+ * =====================================================================
+ */
+/* DDR IO TYPE: */
+wm 32 0x020E04B4 0x000C0000	/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+wm 32 0x020E04AC 0x00000000	/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+/* CLOCK: */
+wm 32 0x020E027C 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
+/* Control: */
+wm 32 0x020E0250 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+wm 32 0x020E024C 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+wm 32 0x020E0490 0x00000030	/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+wm 32 0x020E0288 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+wm 32 0x020E0270 0x00000000	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+wm 32 0x020E0260 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
+wm 32 0x020E0264 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
+wm 32 0x020E04A0 0x00000030	/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+/* Data Strobes: */
+wm 32 0x020E0494 0x00020000	/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+wm 32 0x020E0280 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
+wm 32 0x020E0284 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
+/* Data: */
+wm 32 0x020E04B0 0x00020000	/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+wm 32 0x020E0498 0x00000030	/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+wm 32 0x020E04A4 0x00000030	/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+wm 32 0x020E0244 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+wm 32 0x020E0248 0x00000030	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+/*
+ * =====================================================================
+ * DDR Controller Registers
+ * =====================================================================
+ */
+wm 32 0x021B001C 0x00008000	/* MMDC_MDSCR - MMDC Core Special Command Register */
+/*
+ * ======================================================
+ * Calibrations:
+ * ======================================================
+ */
+wm 32 0x021B0800 0xA1390003	/* DDR_PHY_P0_MPZQHWCTRL , enable both one-time & periodic HW ZQ calibration. */
+
+wm 32 0x021B080C 0x00130003	/* MMDC_MPWLDECTRL0 */
+wm 32 0x021B083C 0x41540154	/* MMDC_MPDGCTRL0 */
+wm 32 0x021B0848 0x40405050	/* MMDC_MPRDDLCTL */
+wm 32 0x021B0850 0x40404E4C	/* MMDC_MPWRDLCTL */
+wm 32 0x021B081C 0x33333333	/* MMDC_MPRDDQBY0DL */
+wm 32 0x021B0820 0x33333333	/* MMDC_MPRDDQBY1DL */
+wm 32 0x021B082C 0xf3333333	/* MMDC_MPWRDQBY0DL */
+wm 32 0x021B0830 0xf3333333	/* MMDC_MPWRDQBY1DL */
+wm 32 0x021B08C0 0x00921012	/* MMDC_MPDCCR */
+
+/* Complete calibration by forced measurement: */
+wm 32 0x021B08b8 0x00000800	/* DDR_PHY_P0_MPMUR0, frc_msr */
+
+/*
+ * =====================================================================
+ * MMDC init:
+ * =====================================================================
+ */
+wm 32 0x021B0004 0x0002002D	/* MMDC0_MDPDC */
+wm 32 0x021B0008 0x00333030	/* MMDC0_MDOTC */
+wm 32 0x021B000C 0x676B52F3	/* MMDC0_MDCFG0 */
+wm 32 0x021B0010 0xB66D8B63	/* MMDC0_MDCFG1 */
+wm 32 0x021B0014 0x01FF00DB	/* MMDC0_MDCFG2 */
+wm 32 0x021B0018 0x00201740	/* MMDC0_MDMISC */
+/* TODO: set configuration request again, also done by NXP */
+wm 32 0x021B001C 0x00008000	/* MMDC_MDSCR */
+wm 32 0x021B002C 0x000026D2	/* MMDC0_MDRWD; recommend to maintain the default values */
+wm 32 0x021B0030 0x006B1023	/* MMDC0_MDOR */
+wm 32 0x021B0040 0x00000047	/* CS0_END */
+wm 32 0x021B0000 0x83180000	/* MMDC0_MDCTL */
+/* Mode register writes for CS0 */
+wm 32 0x021B001C 0x02008032	/* MMDC0_MDSCR, MR2 write, CS0 */
+wm 32 0x021B001C 0x00008033	/* MMDC0_MDSCR, MR3 write, CS0 */
+wm 32 0x021B001C 0x00048031	/* MMDC0_MDSCR, MR1 write, CS0 */
+wm 32 0x021B001C 0x15208030	/* MMDC0_MDSCR, MR0 write, CS0 */
+wm 32 0x021B001C 0x04008040	/* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
+/* Mode register writes for CS1, not used / needed */
+/* final DDR setup, before operation start: */
+wm 32 0x021B0020 0x00000800	/* MMDC0_MDREF */
+wm 32 0x021B0818 0x00000227	/* DDR_PHY_P0_MPODTCTRL */
+wm 32 0x021B0004 0x0002552D	/* MMDC0_MDPDC now SDCTL power down enabled */
+wm 32 0x021B0404 0x00011006	/* MMDC0_MAPSR ADOPT power down enabled */
+wm 32 0x021B001C 0x00000000	/* MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete) */
+
+/* Disable TZASC bypass */
+wm 32 0x020E4024 0x00000001
+
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/tqma6ulx/lowlevel.c b/arch/arm/boards/tqma6ulx/lowlevel.c
new file mode 100644
index 0000000000..5fd997d2ec
--- /dev/null
+++ b/arch/arm/boards/tqma6ulx/lowlevel.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019 Rouven Czerwinski, Pengutronix
+ */
+#define pr_fmt(fmt) "tqma6ul: " fmt
+
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <firmware.h>
+#include <mach/imx/generic.h>
+#include <asm/barebox-arm.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/iomux-mx6ul.h>
+#include <asm/cache.h>
+#include <pbl/i2c.h>
+#include <boards/tq/tq_eeprom.h>
+#include <tee/optee.h>
+
+#include "tqma6ulx.h"
+
+extern char __dtb_z_imx6ul_tqma6ul2_mba6ulx_start[];
+extern char __dtb_z_imx6ul_tqma6ul2l_mba6ulx_start[];
+extern char __dtb_z_imx6ull_tqma6ull2_mba6ulx_start[];
+extern char __dtb_z_imx6ull_tqma6ull2l_mba6ulx_start[];
+
+static void setup_uart(void)
+{
+	imx6_ungate_all_peripherals();
+
+	/*
+	 * Default pad configuration on this board, no explicit config needed
+	 */
+	imx6_uart_setup((void *)MX6_UART1_BASE_ADDR);
+	pbl_set_putc(imx_uart_putc, (void *)MX6_UART1_BASE_ADDR);
+
+	pr_debug("\n");
+
+}
+
+static void *read_eeprom(void)
+{
+	struct pbl_i2c *i2c;
+	struct tq_eeprom *eeprom;
+	void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
+	void *fdt = __dtb_z_imx6ul_tqma6ul2l_mba6ulx_start;
+
+	imx_setup_pad(iomux, MX6_PAD_UART2_TX_DATA__I2C4_SCL | MUX_PAD_CTRL(0x1b8b0));
+	imx_setup_pad(iomux, MX6_PAD_UART2_RX_DATA__I2C4_SDA | MUX_PAD_CTRL(0x1b8b0));
+
+	i2c = imx6_i2c_early_init(IOMEM(MX6_I2C4_BASE_ADDR));
+
+	eeprom = pbl_tq_read_eeprom(i2c, 0x50, I2C_ADDR_16_BIT);
+	if (!eeprom) {
+		pr_err("Cannot read EEPROM\n");
+		goto out;
+	}
+
+	pr_info("Board: %s\n", eeprom->id);
+
+	if (!strcmp(eeprom->id, "TQMa6UL2L-AB.0202"))
+		fdt = __dtb_z_imx6ul_tqma6ul2l_mba6ulx_start;
+	else
+		pr_err("Unknown board type\n");
+out:
+	return fdt;
+}
+
+static void noinline start_mba6ulx(u32 r0)
+{
+	void *fdt;
+	int tee_size;
+	void *tee;
+
+	setup_uart();
+
+	fdt = read_eeprom();
+
+	/* Enable normal/secure r/w for TZC380 region0 */
+	writel(0xf0000000, 0x021D0108);
+
+	/*
+	 * Chainloading barebox will pass a device tree within the RAM in r0,
+	 * skip OP-TEE early loading in this case
+	 */
+	if (IS_ENABLED(CONFIG_FIRMWARE_TQMA6UL_OPTEE) &&
+	    !(r0 > MX6_MMDC_P0_BASE_ADDR &&
+	      r0 < MX6_MMDC_P0_BASE_ADDR + SZ_256M)) {
+		get_builtin_firmware(mba6ul_optee_bin, &tee, &tee_size);
+
+		memset((void *)OPTEE_OVERLAY_LOCATION, 0, 0x1000);
+
+		start_optee_early(NULL, tee);
+	}
+
+	imx6ul_barebox_entry(fdt);
+}
+
+ENTRY_FUNCTION(start_imx6ul_mba6ulx, r0, r1, r2)
+{
+
+	imx6ul_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00910000);
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
+		imx6_uart_setup_ll();
+		putc_ll('>');
+	}
+
+	relocate_to_current_adr();
+	setup_c();
+	barrier();
+
+	start_mba6ulx(r0);
+}
diff --git a/arch/arm/boards/tqma6ulx/tqma6ulx.h b/arch/arm/boards/tqma6ulx/tqma6ulx.h
new file mode 100644
index 0000000000..843ad00d31
--- /dev/null
+++ b/arch/arm/boards/tqma6ulx/tqma6ulx.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * tqma6ulx.h - common defines between OP-TEE and barebox
+ *
+ * Copyright (c) 2019 Rouven Czerwinski <r.czerwinski@pengutronix.de>, Pengutronix
+ *
+ */
+#ifndef __TQMA6ULX_H_
+#define __TQMA6ULX_H_
+
+/* MX6UL_MMDC_PORT0_BASE_ADDR + SZ_64M */
+#define OPTEE_OVERLAY_LOCATION 0x84000000
+
+#endif // __TQMA6ULX_H_
diff --git a/arch/arm/boards/tqma6x/Makefile b/arch/arm/boards/tqma6x/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/tqma6x/Makefile
+++ b/arch/arm/boards/tqma6x/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/tqma6x/board.c b/arch/arm/boards/tqma6x/board.c
index 10faadf5a1..1c1ccdf888 100644
--- a/arch/arm/boards/tqma6x/board.c
+++ b/arch/arm/boards/tqma6x/board.c
@@ -1,10 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 // SPDX-FileCopyrightText: 2013 Sascha Hauer, Pengutronix
 
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <environment.h>
 #include <bootsource.h>
-#include <partition.h>
 #include <common.h>
 #include <envfs.h>
 #include <linux/sizes.h>
@@ -12,18 +11,19 @@
 #include <gpio.h>
 #include <of.h>
 
+#include <linux/mdio.h>
 #include <linux/micrel_phy.h>
 #include <mfd/stmpe-i2c.h>
 
 #include <asm/armlinux.h>
 #include <asm/io.h>
 
-#include <mach/devices-imx6.h>
-#include <mach/imx6-regs.h>
-#include <mach/iomux-mx6.h>
-#include <mach/generic.h>
-#include <mach/imx6.h>
-#include <mach/bbu.h>
+#include <mach/imx/devices-imx6.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/iomux-mx6.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/bbu.h>
 
 #define RQ7_GPIO_ENET_PHYADD2	IMX_GPIO_NR(6, 30)
 #define RQ7_GPIO_ENET_MODE0	IMX_GPIO_NR(6, 25)
@@ -47,14 +47,14 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev)
 	 * min rx data delay, max rx/tx clock delay,
 	 * min rx/tx control delay
 	 */
-	phy_write_mmd_indirect(dev, 4, 2, 0);
-	phy_write_mmd_indirect(dev, 5, 2, 0);
-	phy_write_mmd_indirect(dev, 8, 2, 0x003ff);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 4, 0);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 5, 0);
+	phy_write_mmd(dev, MDIO_MMD_WIS, 8, 0x003ff);
 
 	return 0;
 }
 
-static int tqma6x_enet_init(void)
+static int tq_mba6x_enet_init(void)
 {
 	if (!of_machine_is_compatible("tq,mba6x"))
 		return 0;
@@ -78,20 +78,25 @@ static int tqma6x_enet_init(void)
 
 	return 0;
 }
-fs_initcall(tqma6x_enet_init);
+fs_initcall(tq_mba6x_enet_init);
 
-static int tqma6x_env_init(void)
+static int tqma6x_init(void)
 {
-	if (!of_machine_is_compatible("tq,mba6x"))
-		return 0;
-
-	devfs_add_partition("m25p0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "m25p0.barebox");
-
 	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
 		BBU_HANDLER_FLAG_DEFAULT);
 	imx6_bbu_internal_mmcboot_register_handler("emmc", "mmc2", 0);
 
-	device_detect_by_name("mmc2");
+	device_detect_by_name("mmc2"); // eMMC
+
+	return 0;
+}
+
+static int tq_mba6x_env_init(void)
+{
+	if (!of_machine_is_compatible("tq,mba6x"))
+		return 0;
+
+	tqma6x_init();
 
 	default_environment_path_set("/dev/mmc2.boot1");
 
@@ -99,4 +104,4 @@ static int tqma6x_env_init(void)
 
 	return 0;
 }
-late_initcall(tqma6x_env_init);
+late_initcall(tq_mba6x_env_init);
diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg
index 4f557d5db5..e93d53ed79 100644
--- a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg
+++ b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6dl-ddr-regs.h>
 
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg
index deda53b464..ec682e0109 100644
--- a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg
+++ b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
diff --git a/arch/arm/boards/tqma6x/lowlevel.c b/arch/arm/boards/tqma6x/lowlevel.c
index 845390642b..6e9c9bed0b 100644
--- a/arch/arm/boards/tqma6x/lowlevel.c
+++ b/arch/arm/boards/tqma6x/lowlevel.c
@@ -2,6 +2,7 @@
 // SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de>
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <linux/sizes.h>
 #include <io.h>
@@ -10,19 +11,17 @@
 #include <asm/sections.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <mach/imx6.h>
+#include <mach/imx/imx6.h>
 
 extern char __dtb_imx6q_mba6x_start[];
 extern char __dtb_imx6dl_mba6x_start[];
 
-ENTRY_FUNCTION(start_imx6q_mba6x, r0, r1, r2)
+ENTRY_FUNCTION_WITHSTACK(start_imx6q_mba6x, 0x00920000, r0, r1, r2)
 {
 	void *fdt;
 
 	imx6_cpu_lowlevel_init();
 
-	arm_setup_stack(0x00920000);
-
 	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
 		writel(0x2, 0x020e0338);
 		imx6_uart_setup_ll();
@@ -36,14 +35,12 @@ ENTRY_FUNCTION(start_imx6q_mba6x, r0, r1, r2)
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
 
-ENTRY_FUNCTION(start_imx6dl_mba6x, r0, r1, r2)
+ENTRY_FUNCTION_WITHSTACK(start_imx6dl_mba6x, 0x00920000, r0, r1, r2)
 {
 	void *fdt;
 
 	imx6_cpu_lowlevel_init();
 
-	arm_setup_stack(0x00920000);
-
 	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
 		writel(0x2, 0x020e035c);
 		imx6_uart_setup_ll();
diff --git a/arch/arm/boards/tqma8mpxl/Makefile b/arch/arm/boards/tqma8mpxl/Makefile
new file mode 100644
index 0000000000..35d8640087
--- /dev/null
+++ b/arch/arm/boards/tqma8mpxl/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/tqma8mpxl/board.c b/arch/arm/boards/tqma8mpxl/board.c
new file mode 100644
index 0000000000..39d1bd24d4
--- /dev/null
+++ b/arch/arm/boards/tqma8mpxl/board.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Holger Assmann <h.assmann@pengutronix.de>
+ */
+
+#include <asm/memory.h>
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <gpio.h>
+#include <envfs.h>
+
+static int tqma8mpxl_probe(struct device *dev)
+{
+	int emmc_bbu_flag = 0;
+	int sd_bbu_flag = 0;
+
+	if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) {
+		of_device_enable_path("/chosen/environment-sd");
+		sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	} else {
+		of_device_enable_path("/chosen/environment-emmc");
+		emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+
+	return 0;
+}
+
+static const struct of_device_id tqma8mpxl_of_match[] = {
+	{ .compatible = "tq,imx8mp-tqma8mpdl-mba8mpxl"},
+	{ .compatible = "tq,imx8mp-tqma8mpql-mba8mpxl"},
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(tqma8mpxl_of_match);
+
+static struct driver tqma8mpxl_board_driver = {
+	.name = "board-tqma8mpxl",
+	.probe = tqma8mpxl_probe,
+	.of_compatible = DRV_OF_COMPAT(tqma8mpxl_of_match),
+};
+device_platform_driver(tqma8mpxl_board_driver);
diff --git a/arch/arm/boards/tqma8mpxl/flash-header-tqma8mpxl.imxcfg b/arch/arm/boards/tqma8mpxl/flash-header-tqma8mpxl.imxcfg
new file mode 100644
index 0000000000..6ea2e6c68e
--- /dev/null
+++ b/arch/arm/boards/tqma8mpxl/flash-header-tqma8mpxl.imxcfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mp
+
+loadaddr 0x920000
+max_load_size 0x3f000
+ivtofs 0x0
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/tqma8mpxl/lowlevel.c b/arch/arm/boards/tqma8mpxl/lowlevel.c
new file mode 100644
index 0000000000..e0a0f17d3a
--- /dev/null
+++ b/arch/arm/boards/tqma8mpxl/lowlevel.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <io.h>
+#include <common.h>
+#include <firmware.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <linux/sizes.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8mp-regs.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/debug_ll.h>
+#include <mfd/pca9450.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <soc/imx8m/ddr.h>
+
+#define UART_PAD_CTRL   MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+				     MX8MP_PAD_CTL_FSEL)
+
+#define I2C_PAD_CTRL	MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+				     MX8MP_PAD_CTL_HYS | \
+				     MX8MP_PAD_CTL_PUE | \
+				     MX8MP_PAD_CTL_PE)
+
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART4_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mp_setup_pad(MX8MP_PAD_UART4_TXD__UART4_DCE_TX | UART_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_UART4_RXD__UART4_DCE_RX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+
+	putc_ll('>');
+}
+
+static struct pmic_config pca9450_cfg[] = {
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	{ PCA9450_BUCK123_DVS, 0x29 },
+	/*
+	 * increase VDD_SOC to typical value 0.95V before first
+	 * DRAM access, set DVS1 to 0.85v for suspend.
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+	 */
+	{ PCA9450_BUCK1OUT_DVS0, 0x1C },
+	{ PCA9450_BUCK1OUT_DVS1, 0x14 },
+	{ PCA9450_BUCK1CTRL, 0x59 },
+	/*
+	 * Kernel uses OD/OD freq for SOC
+	 * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD
+	 * voltage 0.95v
+	 */
+	{ PCA9450_BUCK2OUT_DVS0, 0x1C },
+	/* set WDOG_B_CFG to cold reset */
+	{ PCA9450_RESET_CTRL, 0xA1 },
+};
+
+static void power_init_board(void)
+{
+	struct pbl_i2c *i2c;
+
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
+
+	pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+}
+
+static __noreturn noinline void tqma8mpxl_start(void)
+{
+	extern char __dtb_z_imx8mp_tqma8mpql_mba8mpxl_start[];
+
+	setup_uart();
+
+	if (current_el() == 3) {
+		extern struct dram_timing_info dram_timing_2gb_no_ecc;
+
+		imx8mp_early_clock_init();
+
+		power_init_board();
+
+		imx8mp_ddr_init(&dram_timing_2gb_no_ecc, DRAM_TYPE_LPDDR4);
+
+		imx8mp_load_and_start_image_via_tfa();
+	}
+
+	imx8mp_barebox_entry(__dtb_z_imx8mp_tqma8mpql_mba8mpxl_start);
+}
+
+ENTRY_FUNCTION(start_tqma8mpxl, x0, x1, x2)
+{
+	imx8mp_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	tqma8mpxl_start();
+}
diff --git a/arch/arm/boards/tqma8mpxl/lpddr4-timing.c b/arch/arm/boards/tqma8mpxl/lpddr4-timing.c
new file mode 100644
index 0000000000..85e21bf69d
--- /dev/null
+++ b/arch/arm/boards/tqma8mpxl/lpddr4-timing.c
@@ -0,0 +1,1131 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
+ *
+ * TQMa8MPxL.2GByte.RAM-Timing.0004.xlsx / 2.0 GHz
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+#include <soc/imx8m/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x1303 },
+	{ 0x3d400024, 0x1e84800 },
+	{ 0x3d400064, 0x7a0118 },
+	{ 0x3d400070, 0x7027f90 },
+	{ 0x3d400074, 0x790 },
+	{ 0x3d4000d0, 0xc00307a3 },
+	{ 0x3d4000d4, 0xc50000 },
+	{ 0x3d4000dc, 0xf4003f },
+	{ 0x3d4000e0, 0x2b0000 },
+	{ 0x3d4000e8, 0x550048 },
+	{ 0x3d4000ec, 0x150048 },
+	{ 0x3d400100, 0x201e222a },
+	{ 0x3d400104, 0x8083f },
+	{ 0x3d40010c, 0xe0e000 },
+	{ 0x3d400110, 0x12040a12 },
+	{ 0x3d400114, 0x2050f0f },
+	{ 0x3d400118, 0x1010009 },
+	{ 0x3d40011c, 0x501 },
+	{ 0x3d400130, 0x20800 },
+	{ 0x3d400134, 0xe100002 },
+	{ 0x3d400138, 0x120 },
+	{ 0x3d400144, 0xc80064 },
+	{ 0x3d400180, 0x3e8001e },
+	{ 0x3d400184, 0x3207a12 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x49f820e },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x1f0e },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x9121c1c },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1001 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x2b0000 },
+	{ 0x3d4020e8, 0x550048 },
+	{ 0x3d4020ec, 0x150048 },
+	{ 0x3d402100, 0xa030305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x1001 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x2b0000 },
+	{ 0x3d4030e8, 0x550048 },
+	{ 0x3d4030ec, 0x150048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x6 },
+	{ 0x100a6, 0x7 },
+	{ 0x100a7, 0x5 },
+	{ 0x110a0, 0x6 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x4 },
+	{ 0x110a5, 0x5 },
+	{ 0x110a6, 0x1 },
+	{ 0x110a7, 0x7 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x6 },
+	{ 0x120a2, 0x4 },
+	{ 0x120a3, 0x3 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x2 },
+	{ 0x120a6, 0x1 },
+	{ 0x120a7, 0x7 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x5 },
+	{ 0x130a3, 0x4 },
+	{ 0x130a4, 0x3 },
+	{ 0x130a5, 0x2 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x18 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0x600 },
+	{ 0x1014d, 0x600 },
+	{ 0x1104d, 0x600 },
+	{ 0x1114d, 0x600 },
+	{ 0x1204d, 0x600 },
+	{ 0x1214d, 0x600 },
+	{ 0x1304d, 0x600 },
+	{ 0x1314d, 0x600 },
+	{ 0x11004d, 0x600 },
+	{ 0x11014d, 0x600 },
+	{ 0x11104d, 0x600 },
+	{ 0x11114d, 0x600 },
+	{ 0x11204d, 0x600 },
+	{ 0x11214d, 0x600 },
+	{ 0x11304d, 0x600 },
+	{ 0x11314d, 0x600 },
+	{ 0x21004d, 0x600 },
+	{ 0x21014d, 0x600 },
+	{ 0x21104d, 0x600 },
+	{ 0x21114d, 0x600 },
+	{ 0x21204d, 0x600 },
+	{ 0x21214d, 0x600 },
+	{ 0x21304d, 0x600 },
+	{ 0x21314d, 0x600 },
+	{ 0x10049, 0x69a },
+	{ 0x10149, 0x69a },
+	{ 0x11049, 0x69a },
+	{ 0x11149, 0x69a },
+	{ 0x12049, 0x69a },
+	{ 0x12149, 0x69a },
+	{ 0x13049, 0x69a },
+	{ 0x13149, 0x69a },
+	{ 0x110049, 0x69a },
+	{ 0x110149, 0x69a },
+	{ 0x111049, 0x69a },
+	{ 0x111149, 0x69a },
+	{ 0x112049, 0x69a },
+	{ 0x112149, 0x69a },
+	{ 0x113049, 0x69a },
+	{ 0x113149, 0x69a },
+	{ 0x210049, 0x69a },
+	{ 0x210149, 0x69a },
+	{ 0x211049, 0x69a },
+	{ 0x211149, 0x69a },
+	{ 0x212049, 0x69a },
+	{ 0x212149, 0x69a },
+	{ 0x213049, 0x69a },
+	{ 0x213149, 0x69a },
+	{ 0x43, 0x21 },
+	{ 0x1043, 0x21 },
+	{ 0x2043, 0x21 },
+	{ 0x3043, 0x21 },
+	{ 0x4043, 0x21 },
+	{ 0x5043, 0x21 },
+	{ 0x6043, 0x21 },
+	{ 0x7043, 0x21 },
+	{ 0x8043, 0x21 },
+	{ 0x9043, 0x21 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x3e8 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x303c },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x2b },
+	{ 0x5401b, 0x4855 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x15 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x2b },
+	{ 0x54021, 0x4855 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x15 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x2b3f },
+	{ 0x54034, 0x5500 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1500 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x2b3f },
+	{ 0x5403a, 0x5500 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1500 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x303c },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x2b },
+	{ 0x5401b, 0x4855 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x15 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x2b },
+	{ 0x54021, 0x4855 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x15 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x2b00 },
+	{ 0x54034, 0x5500 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1500 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x2b00 },
+	{ 0x5403a, 0x5500 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1500 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x303c },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x2b },
+	{ 0x5401b, 0x4855 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x15 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x2b },
+	{ 0x54021, 0x4855 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x15 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x2b00 },
+	{ 0x54034, 0x5500 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1500 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x2b00 },
+	{ 0x5403a, 0x5500 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1500 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x303c },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x2b },
+	{ 0x5401b, 0x4855 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x15 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x2b },
+	{ 0x54021, 0x4855 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x15 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x2b3f },
+	{ 0x54034, 0x5500 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1500 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x2b3f },
+	{ 0x5403a, 0x5500 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1500 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x8 },
+	{ 0x90159, 0xe8 },
+	{ 0x9015a, 0x109 },
+	{ 0x9015b, 0x0 },
+	{ 0x9015c, 0x8140 },
+	{ 0x9015d, 0x10c },
+	{ 0x9015e, 0x10 },
+	{ 0x9015f, 0x8138 },
+	{ 0x90160, 0x104 },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0x448 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0xf },
+	{ 0x90165, 0x7c0 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0x0 },
+	{ 0x90168, 0xe8 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x47 },
+	{ 0x9016b, 0x630 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x618 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0xe0 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x0 },
+	{ 0x90174, 0x7c8 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x8140 },
+	{ 0x90178, 0x10c },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x478 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x1 },
+	{ 0x9017e, 0x8 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x4 },
+	{ 0x90181, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x68 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x465 },
+	{ 0x2000c, 0xfa },
+	{ 0x2000d, 0x9c4 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x70 },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x1c },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 4000mts 1D */
+		.drate = 4000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 4000mts 2D */
+		.drate = 4000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_2gb_no_ecc = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 4000, 400, 100, },
+};
+
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+#error
+#endif
diff --git a/arch/arm/boards/tqma93xx/Makefile b/arch/arm/boards/tqma93xx/Makefile
new file mode 100644
index 0000000000..1bef9e284d
--- /dev/null
+++ b/arch/arm/boards/tqma93xx/Makefile
@@ -0,0 +1,2 @@
+lwl-y += lowlevel.o lpddr4x_tqma93xxca_timing.o lpddr4x_tqma93xxla_timing.o
+obj-y += board.o
diff --git a/arch/arm/boards/tqma93xx/board.c b/arch/arm/boards/tqma93xx/board.c
new file mode 100644
index 0000000000..b181784079
--- /dev/null
+++ b/arch/arm/boards/tqma93xx/board.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#define pr_fmt(fmt) "TQMa93xx: " fmt
+
+#include <common.h>
+#include <gpio.h>
+#include <init.h>
+#include <i2c/i2c.h>
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <environment.h>
+#include <mfd/pca9450.h>
+#include <deep-probe.h>
+#include <mach/imx/bbu.h>
+
+static void tqma93xx_init_pmic(struct regmap *map)
+{
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	regmap_write(map, PCA9450_BUCK123_DVS, 0x29);
+	/* enable DVS control through PMIC_STBY_REQ */
+	regmap_write(map, PCA9450_BUCK1CTRL, 0x59);
+	/* 0.9 V */
+	regmap_write(map, PCA9450_BUCK1OUT_DVS0, 0x18);
+	regmap_write(map, PCA9450_BUCK3OUT_DVS0, 0x18);
+	/* set standby voltage to 0.65v */
+	regmap_write(map, PCA9450_BUCK1OUT_DVS1, 0x4);
+
+	/* I2C_LT_EN*/
+	regmap_write(map, 0xa, 0x3);
+
+	/* set WDOG_B_CFG to cold reset */
+	regmap_write(map, PCA9450_RESET_CTRL, 0xA1);
+}
+
+static int tqma93xx_probe(struct device *dev)
+{
+	pca9450_register_init_callback(tqma93xx_init_pmic);
+
+	imx9_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", 0);
+
+	return 0;
+}
+
+static const struct of_device_id tqma93xx_of_match[] = {
+        {
+                .compatible = "tq,imx93-tqma9352",
+        },
+        { /* sentinel */ },
+};
+
+static struct driver tqma93xx_board_driver = {
+        .name = "board-tqma93xx",
+        .probe = tqma93xx_probe,
+        .of_compatible = tqma93xx_of_match,
+};
+coredevice_platform_driver(tqma93xx_board_driver);
+
+BAREBOX_DEEP_PROBE_ENABLE(tqma93xx_of_match);
diff --git a/arch/arm/boards/tqma93xx/lowlevel.c b/arch/arm/boards/tqma93xx/lowlevel.c
new file mode 100644
index 0000000000..8d89ee530f
--- /dev/null
+++ b/arch/arm/boards/tqma93xx/lowlevel.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/xload.h>
+#include <asm/barebox-arm.h>
+#include <soc/imx9/ddr.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/romapi.h>
+#include <mach/imx/esdctl.h>
+#include <pbl/i2c.h>
+#include <boards/tq/tq_eeprom.h>
+
+extern char __dtb_z_imx93_tqma9352_mba93xxca_start[];
+extern char __dtb_z_imx93_tqma9352_mba93xxla_start[];
+extern struct dram_timing_info tqma93xxca_dram_timing;
+extern struct dram_timing_info tqma93xxla_dram_timing;
+
+static int tqma93xx_get_formfactor(void)
+{
+	struct pbl_i2c *i2c;
+	struct tq_eeprom *eeprom;
+	phys_size_t ramsize;
+	int formfactor;
+
+	i2c = imx93_i2c_early_init(IOMEM(MX9_I2C1_BASE_ADDR));
+
+	eeprom = pbl_tq_read_eeprom(i2c, 0x53, 0);
+	if (!eeprom)
+		return VARD_FORMFACTOR_TYPE_CONNECTOR;
+
+	ramsize = tq_vard_ramsize(&eeprom->vard);
+	if (ramsize != SZ_1G)
+		pr_err("unsupported ram size 0x%08llx\n", ramsize);
+
+	formfactor = tq_vard_get_formfactor(&eeprom->vard);
+
+	switch (formfactor) {
+	case VARD_FORMFACTOR_TYPE_LGA:
+		pr_debug("LGA board type\n");
+		break;
+	case VARD_FORMFACTOR_TYPE_CONNECTOR:
+		pr_debug("CONNECTOR board type\n");
+		break;
+	default:
+		pr_err("Unknown formfactor\n");
+		formfactor = VARD_FORMFACTOR_TYPE_CONNECTOR;
+	}
+
+	return formfactor;
+}
+
+static noinline void tqma93xx_continue(void)
+{
+	void *base = IOMEM(MX9_UART1_BASE_ADDR);
+	void *muxbase = IOMEM(MX9_IOMUXC_BASE_ADDR);
+	int formfactor;
+	void *fdt;
+
+	writel(0x10, muxbase + 0x170);
+	writel(0x10, muxbase + 0x174);
+	writel(0x0, muxbase + 0x184);
+	writel(0xb9e, muxbase + 0x320);
+	writel(0xb9e, muxbase + 0x324);
+
+	imx9_uart_setup(IOMEM(base));
+	pbl_set_putc(lpuart32_putc, base + 0x10);
+
+	formfactor = tqma93xx_get_formfactor();
+
+	if (current_el() == 3) {
+		switch (formfactor) {
+		case VARD_FORMFACTOR_TYPE_LGA:
+			imx93_ddr_init(&tqma93xxla_dram_timing, DRAM_TYPE_LPDDR4);
+			break;
+		case VARD_FORMFACTOR_TYPE_CONNECTOR:
+			imx93_ddr_init(&tqma93xxca_dram_timing, DRAM_TYPE_LPDDR4);
+			break;
+		}
+
+		imx93_romapi_load_image();
+		imx93_load_and_start_image_via_tfa();
+	}
+
+	switch (formfactor) {
+	case VARD_FORMFACTOR_TYPE_LGA:
+		fdt = __dtb_z_imx93_tqma9352_mba93xxla_start;
+		break;
+	case VARD_FORMFACTOR_TYPE_CONNECTOR:
+		fdt = __dtb_z_imx93_tqma9352_mba93xxca_start;
+		break;
+	}
+
+	imx93_barebox_entry(fdt);
+}
+
+ENTRY_FUNCTION(start_imx93_tqma93xx, r0, r1, r2)
+{
+	if (current_el() == 3)
+		imx93_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	tqma93xx_continue();
+}
diff --git a/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxca_timing.c b/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxca_timing.c
new file mode 100644
index 0000000000..68d8da3b5b
--- /dev/null
+++ b/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxca_timing.c
@@ -0,0 +1,755 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 NXP
+ */
+
+#include <common.h>
+#include <soc/imx9/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x4e300110, 0x44100001 },
+	{ 0x4e300000, 0x8000bf },
+	{ 0x4e300008, 0x0 },
+	{ 0x4e300080, 0x80000412 },
+	{ 0x4e300084, 0x0 },
+	{ 0x4e300100, 0x24a0321b },
+	{ 0x4e300104, 0xa8ee001b },
+	{ 0x4e300108, 0x2f2e3233 },
+	{ 0x4e30010c, 0x85c18b },
+	{ 0x4e300114, 0x1002 },
+	{ 0x4e300124, 0x1c77071d },
+	{ 0x4e300160, 0x5402 },
+	{ 0x4e30016c, 0x35f00000 },
+	{ 0x4e300170, 0x8b0b0608 },
+	{ 0x4e300250, 0x28 },
+	{ 0x4e300254, 0x0 },
+	{ 0x4e30025c, 0x400 },
+	{ 0x4e300260, 0x0 },
+	{ 0x4e300300, 0x14281114 },
+	{ 0x4e300304, 0x106110a },
+	{ 0x4e300308, 0xa200e3c },
+	{ 0x4e300f04, 0x80 },
+	{ 0x4e300800, 0x39300002 },
+	{ 0x4e300804, 0x1f1f1f1f },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x4 },
+	{ 0x100a1, 0x5 },
+	{ 0x100a2, 0x6 },
+	{ 0x100a3, 0x7 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x1 },
+	{ 0x100a6, 0x2 },
+	{ 0x100a7, 0x3 },
+	{ 0x110a0, 0x3 },
+	{ 0x110a1, 0x2 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x1 },
+	{ 0x110a4, 0x7 },
+	{ 0x110a5, 0x6 },
+	{ 0x110a6, 0x4 },
+	{ 0x110a7, 0x5 },
+	{ 0x1005f, 0x5ff },
+	{ 0x1015f, 0x5ff },
+	{ 0x1105f, 0x5ff },
+	{ 0x1115f, 0x5ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x2002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x2007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x20056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x10049, 0xe00 },
+	{ 0x10149, 0xe00 },
+	{ 0x11049, 0xe00 },
+	{ 0x11149, 0xe00 },
+	{ 0x43, 0x60 },
+	{ 0x1043, 0x60 },
+	{ 0x2043, 0x60 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x2009b, 0x2 },
+	{ 0x20008, 0x3a5 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x10c },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x200fa, 0x2 },
+	{ 0x20019, 0x1 },
+	{ 0x200f0, 0x0 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x2002c, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xe94 },
+	{ 0x54004, 0x4 },
+	{ 0x54006, 0x15 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xff },
+	{ 0x5400b, 0x4 },
+	{ 0x5400c, 0x1 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x36e4 },
+	{ 0x5401a, 0x32 },
+	{ 0x5401b, 0x1146 },
+	{ 0x5401c, 0x1108 },
+	{ 0x5401e, 0x6 },
+	{ 0x5401f, 0x36e4 },
+	{ 0x54020, 0x32 },
+	{ 0x54021, 0x1146 },
+	{ 0x54022, 0x1108 },
+	{ 0x54024, 0x6 },
+	{ 0x54032, 0xe400 },
+	{ 0x54033, 0x3236 },
+	{ 0x54034, 0x4600 },
+	{ 0x54035, 0x811 },
+	{ 0x54036, 0x11 },
+	{ 0x54037, 0x600 },
+	{ 0x54038, 0xe400 },
+	{ 0x54039, 0x3236 },
+	{ 0x5403a, 0x4600 },
+	{ 0x5403b, 0x811 },
+	{ 0x5403c, 0x11 },
+	{ 0x5403d, 0x600 },
+	{ 0xd0000, 0x1 }
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xe94 },
+	{ 0x54004, 0x4 },
+	{ 0x54006, 0x15 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xff },
+	{ 0x5400b, 0x4 },
+	{ 0x5400c, 0x1 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x2080 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x36e4 },
+	{ 0x5401a, 0x32 },
+	{ 0x5401b, 0x1146 },
+	{ 0x5401c, 0x1108 },
+	{ 0x5401e, 0x6 },
+	{ 0x5401f, 0x36e4 },
+	{ 0x54020, 0x32 },
+	{ 0x54021, 0x1146 },
+	{ 0x54022, 0x1108 },
+	{ 0x54024, 0x6 },
+	{ 0x54032, 0xe400 },
+	{ 0x54033, 0x3236 },
+	{ 0x54034, 0x4600 },
+	{ 0x54035, 0x811 },
+	{ 0x54036, 0x11 },
+	{ 0x54037, 0x600 },
+	{ 0x54038, 0xe400 },
+	{ 0x54039, 0x3236 },
+	{ 0x5403a, 0x4600 },
+	{ 0x5403b, 0x811 },
+	{ 0x5403c, 0x11 },
+	{ 0x5403d, 0x600 },
+	{ 0xd0000, 0x1 }
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x30 },
+	{ 0x90051, 0x65a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x45a },
+	{ 0x90055, 0x9 },
+	{ 0x90056, 0x0 },
+	{ 0x90057, 0x448 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x179 },
+	{ 0x9005c, 0x1 },
+	{ 0x9005d, 0x618 },
+	{ 0x9005e, 0x109 },
+	{ 0x9005f, 0x40c0 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x8 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x4040 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x0 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x48 },
+	{ 0x9006b, 0x40 },
+	{ 0x9006c, 0x633 },
+	{ 0x9006d, 0x149 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x658 },
+	{ 0x90070, 0x109 },
+	{ 0x90071, 0x10 },
+	{ 0x90072, 0x4 },
+	{ 0x90073, 0x18 },
+	{ 0x90074, 0x0 },
+	{ 0x90075, 0x4 },
+	{ 0x90076, 0x78 },
+	{ 0x90077, 0x549 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0xd49 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x159 },
+	{ 0x9007d, 0x94a },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x159 },
+	{ 0x90080, 0x441 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x42 },
+	{ 0x90084, 0x633 },
+	{ 0x90085, 0x149 },
+	{ 0x90086, 0x1 },
+	{ 0x90087, 0x633 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x0 },
+	{ 0x9008a, 0xe0 },
+	{ 0x9008b, 0x109 },
+	{ 0x9008c, 0xa },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x9 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x149 },
+	{ 0x90092, 0x9 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x159 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x10 },
+	{ 0x90097, 0x109 },
+	{ 0x90098, 0x0 },
+	{ 0x90099, 0x3c0 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x18 },
+	{ 0x9009c, 0x4 },
+	{ 0x9009d, 0x48 },
+	{ 0x9009e, 0x18 },
+	{ 0x9009f, 0x4 },
+	{ 0x900a0, 0x58 },
+	{ 0x900a1, 0xb },
+	{ 0x900a2, 0x10 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x1 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x900a7, 0x5 },
+	{ 0x900a8, 0x7c0 },
+	{ 0x900a9, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900aa, 0x0 },
+	{ 0x900ab, 0x790 },
+	{ 0x900ac, 0x11a },
+	{ 0x900ad, 0x8 },
+	{ 0x900ae, 0x7aa },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x7b2 },
+	{ 0x900b2, 0x2a },
+	{ 0x900b3, 0x0 },
+	{ 0x900b4, 0x7c8 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x10 },
+	{ 0x900b7, 0x10 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x10 },
+	{ 0x900ba, 0x2a8 },
+	{ 0x900bb, 0x129 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x370 },
+	{ 0x900be, 0x129 },
+	{ 0x900bf, 0xa },
+	{ 0x900c0, 0x3c8 },
+	{ 0x900c1, 0x1a9 },
+	{ 0x900c2, 0xc },
+	{ 0x900c3, 0x408 },
+	{ 0x900c4, 0x199 },
+	{ 0x900c5, 0x14 },
+	{ 0x900c6, 0x790 },
+	{ 0x900c7, 0x11a },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x4 },
+	{ 0x900ca, 0x18 },
+	{ 0x900cb, 0xe },
+	{ 0x900cc, 0x408 },
+	{ 0x900cd, 0x199 },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x8568 },
+	{ 0x900d0, 0x108 },
+	{ 0x900d1, 0x18 },
+	{ 0x900d2, 0x790 },
+	{ 0x900d3, 0x16a },
+	{ 0x900d4, 0x8 },
+	{ 0x900d5, 0x1d8 },
+	{ 0x900d6, 0x169 },
+	{ 0x900d7, 0x10 },
+	{ 0x900d8, 0x8558 },
+	{ 0x900d9, 0x168 },
+	{ 0x900da, 0x1ff8 },
+	{ 0x900db, 0x85a8 },
+	{ 0x900dc, 0x1e8 },
+	{ 0x900dd, 0x50 },
+	{ 0x900de, 0x798 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x60 },
+	{ 0x900e1, 0x7a0 },
+	{ 0x900e2, 0x16a },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0x8310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0x8 },
+	{ 0x900e7, 0xa310 },
+	{ 0x900e8, 0x168 },
+	{ 0x900e9, 0xa },
+	{ 0x900ea, 0x408 },
+	{ 0x900eb, 0x169 },
+	{ 0x900ec, 0x6e },
+	{ 0x900ed, 0x0 },
+	{ 0x900ee, 0x68 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x408 },
+	{ 0x900f1, 0x169 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0x8310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x0 },
+	{ 0x900f6, 0xa310 },
+	{ 0x900f7, 0x168 },
+	{ 0x900f8, 0x1ff8 },
+	{ 0x900f9, 0x85a8 },
+	{ 0x900fa, 0x1e8 },
+	{ 0x900fb, 0x68 },
+	{ 0x900fc, 0x798 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x78 },
+	{ 0x900ff, 0x7a0 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x68 },
+	{ 0x90102, 0x790 },
+	{ 0x90103, 0x16a },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0x8b10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0x8 },
+	{ 0x90108, 0xab10 },
+	{ 0x90109, 0x168 },
+	{ 0x9010a, 0xa },
+	{ 0x9010b, 0x408 },
+	{ 0x9010c, 0x169 },
+	{ 0x9010d, 0x58 },
+	{ 0x9010e, 0x0 },
+	{ 0x9010f, 0x68 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x408 },
+	{ 0x90112, 0x169 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0x8b10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x1 },
+	{ 0x90117, 0xab10 },
+	{ 0x90118, 0x168 },
+	{ 0x90119, 0x0 },
+	{ 0x9011a, 0x1d8 },
+	{ 0x9011b, 0x169 },
+	{ 0x9011c, 0x80 },
+	{ 0x9011d, 0x790 },
+	{ 0x9011e, 0x16a },
+	{ 0x9011f, 0x18 },
+	{ 0x90120, 0x7aa },
+	{ 0x90121, 0x6a },
+	{ 0x90122, 0xa },
+	{ 0x90123, 0x0 },
+	{ 0x90124, 0x1e9 },
+	{ 0x90125, 0x8 },
+	{ 0x90126, 0x8080 },
+	{ 0x90127, 0x108 },
+	{ 0x90128, 0xf },
+	{ 0x90129, 0x408 },
+	{ 0x9012a, 0x169 },
+	{ 0x9012b, 0xc },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x68 },
+	{ 0x9012e, 0x9 },
+	{ 0x9012f, 0x0 },
+	{ 0x90130, 0x1a9 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x408 },
+	{ 0x90133, 0x169 },
+	{ 0x90134, 0x0 },
+	{ 0x90135, 0x8080 },
+	{ 0x90136, 0x108 },
+	{ 0x90137, 0x8 },
+	{ 0x90138, 0x7aa },
+	{ 0x90139, 0x6a },
+	{ 0x9013a, 0x0 },
+	{ 0x9013b, 0x8568 },
+	{ 0x9013c, 0x108 },
+	{ 0x9013d, 0xb7 },
+	{ 0x9013e, 0x790 },
+	{ 0x9013f, 0x16a },
+	{ 0x90140, 0x1f },
+	{ 0x90141, 0x0 },
+	{ 0x90142, 0x68 },
+	{ 0x90143, 0x8 },
+	{ 0x90144, 0x8558 },
+	{ 0x90145, 0x168 },
+	{ 0x90146, 0xf },
+	{ 0x90147, 0x408 },
+	{ 0x90148, 0x169 },
+	{ 0x90149, 0xd },
+	{ 0x9014a, 0x0 },
+	{ 0x9014b, 0x68 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x408 },
+	{ 0x9014e, 0x169 },
+	{ 0x9014f, 0x0 },
+	{ 0x90150, 0x8558 },
+	{ 0x90151, 0x168 },
+	{ 0x90152, 0x8 },
+	{ 0x90153, 0x3c8 },
+	{ 0x90154, 0x1a9 },
+	{ 0x90155, 0x3 },
+	{ 0x90156, 0x370 },
+	{ 0x90157, 0x129 },
+	{ 0x90158, 0x20 },
+	{ 0x90159, 0x2aa },
+	{ 0x9015a, 0x9 },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x104 },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x448 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0xf },
+	{ 0x90168, 0x7c0 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x0 },
+	{ 0x9016b, 0xe8 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x47 },
+	{ 0x9016e, 0x630 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0x618 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x8 },
+	{ 0x90174, 0xe0 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x0 },
+	{ 0x90177, 0x7c8 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0x8140 },
+	{ 0x9017b, 0x10c },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x478 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x0 },
+	{ 0x90180, 0x1 },
+	{ 0x90181, 0x8 },
+	{ 0x90182, 0x8 },
+	{ 0x90183, 0x4 },
+	{ 0x90184, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2b },
+	{ 0x90026, 0x69 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x75 },
+	{ 0x2000c, 0xe9 },
+	{ 0x2000d, 0x91c },
+	{ 0x2000e, 0x2c },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x400f1, 0xe },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3733mts 1D */
+		.drate = 3733,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P0 3733mts 2D */
+		.drate = 3733,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info tqma93xxca_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3733, },
+};
diff --git a/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxla_timing.c b/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxla_timing.c
new file mode 100644
index 0000000000..7ca8c3aedc
--- /dev/null
+++ b/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxla_timing.c
@@ -0,0 +1,1482 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2022 NXP
+ */
+
+/* generated from TQMa9xxxLA.DDR-Timing.Beta.0001.mex  */
+
+#include <common.h>
+#include <soc/imx9/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x4e300110, 0x44100001 },
+	{ 0x4e300000, 0x8000bf },
+	{ 0x4e300008, 0x0 },
+	{ 0x4e300080, 0x80000412 },
+	{ 0x4e300084, 0x0 },
+	{ 0x4e300100, 0x24a0321b },
+	{ 0x4e300104, 0xa8ee001b },
+	{ 0x4e300108, 0x2f2e3233 },
+	{ 0x4e30010c, 0x85c18b },
+	{ 0x4e300114, 0x1002 },
+	{ 0x4e300124, 0x1c77071d },
+	{ 0x4e300160, 0x5402 },
+	{ 0x4e30016c, 0x35f00000 },
+	{ 0x4e300170, 0x8b0b0608 },
+	{ 0x4e300250, 0x28 },
+	{ 0x4e300254, 0x0 },
+	{ 0x4e30025c, 0x400 },
+	{ 0x4e300260, 0x0 },
+	{ 0x4e300300, 0x14281114 },
+	{ 0x4e300304, 0x106110a },
+	{ 0x4e300308, 0xa200e3c },
+	{ 0x4e300f04, 0x80 },
+	{ 0x4e300800, 0x39300002 },
+	{ 0x4e300804, 0x1f1f1f1f },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x2 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x4 },
+	{ 0x100a4, 0x3 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x4 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x1 },
+	{ 0x110a5, 0x5 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x1005f, 0x5ff },
+	{ 0x1015f, 0x5ff },
+	{ 0x1105f, 0x5ff },
+	{ 0x1115f, 0x5ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x2002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x2007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x20056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x10049, 0xe00 },
+	{ 0x10149, 0xe00 },
+	{ 0x11049, 0xe00 },
+	{ 0x11149, 0xe00 },
+	{ 0x43, 0x60 },
+	{ 0x1043, 0x60 },
+	{ 0x2043, 0x60 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x2009b, 0x2 },
+	{ 0x20008, 0x3a5 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x10c },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x200fa, 0x2 },
+	{ 0x20019, 0x1 },
+	{ 0x200f0, 0x0 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xe94 },
+	{ 0x54004, 0x4 },
+	{ 0x54006, 0x15 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xff },
+	{ 0x5400b, 0x4 },
+	{ 0x5400c, 0x1 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x36e4 },
+	{ 0x5401a, 0x32 },
+	{ 0x5401b, 0x1146 },
+	{ 0x5401c, 0x1108 },
+	{ 0x5401e, 0x6 },
+	{ 0x5401f, 0x36e4 },
+	{ 0x54020, 0x32 },
+	{ 0x54021, 0x1146 },
+	{ 0x54022, 0x1108 },
+	{ 0x54024, 0x6 },
+	{ 0x54032, 0xe400 },
+	{ 0x54033, 0x3236 },
+	{ 0x54034, 0x4600 },
+	{ 0x54035, 0x811 },
+	{ 0x54036, 0x11 },
+	{ 0x54037, 0x600 },
+	{ 0x54038, 0xe400 },
+	{ 0x54039, 0x3236 },
+	{ 0x5403a, 0x4600 },
+	{ 0x5403b, 0x811 },
+	{ 0x5403c, 0x11 },
+	{ 0x5403d, 0x600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xe94 },
+	{ 0x54004, 0x4 },
+	{ 0x54006, 0x15 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xff },
+	{ 0x5400b, 0x4 },
+	{ 0x5400c, 0x1 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x2080 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x36e4 },
+	{ 0x5401a, 0x32 },
+	{ 0x5401b, 0x1146 },
+	{ 0x5401c, 0x1108 },
+	{ 0x5401e, 0x6 },
+	{ 0x5401f, 0x36e4 },
+	{ 0x54020, 0x32 },
+	{ 0x54021, 0x1146 },
+	{ 0x54022, 0x1108 },
+	{ 0x54024, 0x6 },
+	{ 0x54032, 0xe400 },
+	{ 0x54033, 0x3236 },
+	{ 0x54034, 0x4600 },
+	{ 0x54035, 0x811 },
+	{ 0x54036, 0x11 },
+	{ 0x54037, 0x600 },
+	{ 0x54038, 0xe400 },
+	{ 0x54039, 0x3236 },
+	{ 0x5403a, 0x4600 },
+	{ 0x5403b, 0x811 },
+	{ 0x5403c, 0x11 },
+	{ 0x5403d, 0x600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x30 },
+	{ 0x90051, 0x65a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x45a },
+	{ 0x90055, 0x9 },
+	{ 0x90056, 0x0 },
+	{ 0x90057, 0x448 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x179 },
+	{ 0x9005c, 0x1 },
+	{ 0x9005d, 0x618 },
+	{ 0x9005e, 0x109 },
+	{ 0x9005f, 0x40c0 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x8 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x4040 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x0 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x48 },
+	{ 0x9006b, 0x40 },
+	{ 0x9006c, 0x633 },
+	{ 0x9006d, 0x149 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x658 },
+	{ 0x90070, 0x109 },
+	{ 0x90071, 0x10 },
+	{ 0x90072, 0x4 },
+	{ 0x90073, 0x18 },
+	{ 0x90074, 0x0 },
+	{ 0x90075, 0x4 },
+	{ 0x90076, 0x78 },
+	{ 0x90077, 0x549 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0xd49 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x159 },
+	{ 0x9007d, 0x94a },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x159 },
+	{ 0x90080, 0x441 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x42 },
+	{ 0x90084, 0x633 },
+	{ 0x90085, 0x149 },
+	{ 0x90086, 0x1 },
+	{ 0x90087, 0x633 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x0 },
+	{ 0x9008a, 0xe0 },
+	{ 0x9008b, 0x109 },
+	{ 0x9008c, 0xa },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x9 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x149 },
+	{ 0x90092, 0x9 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x159 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x10 },
+	{ 0x90097, 0x109 },
+	{ 0x90098, 0x0 },
+	{ 0x90099, 0x3c0 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x18 },
+	{ 0x9009c, 0x4 },
+	{ 0x9009d, 0x48 },
+	{ 0x9009e, 0x18 },
+	{ 0x9009f, 0x4 },
+	{ 0x900a0, 0x58 },
+	{ 0x900a1, 0xb },
+	{ 0x900a2, 0x10 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x1 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x900a7, 0x5 },
+	{ 0x900a8, 0x7c0 },
+	{ 0x900a9, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900aa, 0x0 },
+	{ 0x900ab, 0x790 },
+	{ 0x900ac, 0x11a },
+	{ 0x900ad, 0x8 },
+	{ 0x900ae, 0x7aa },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x7b2 },
+	{ 0x900b2, 0x2a },
+	{ 0x900b3, 0x0 },
+	{ 0x900b4, 0x7c8 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x10 },
+	{ 0x900b7, 0x10 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x10 },
+	{ 0x900ba, 0x2a8 },
+	{ 0x900bb, 0x129 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x370 },
+	{ 0x900be, 0x129 },
+	{ 0x900bf, 0xa },
+	{ 0x900c0, 0x3c8 },
+	{ 0x900c1, 0x1a9 },
+	{ 0x900c2, 0xc },
+	{ 0x900c3, 0x408 },
+	{ 0x900c4, 0x199 },
+	{ 0x900c5, 0x14 },
+	{ 0x900c6, 0x790 },
+	{ 0x900c7, 0x11a },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x4 },
+	{ 0x900ca, 0x18 },
+	{ 0x900cb, 0xe },
+	{ 0x900cc, 0x408 },
+	{ 0x900cd, 0x199 },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x8568 },
+	{ 0x900d0, 0x108 },
+	{ 0x900d1, 0x18 },
+	{ 0x900d2, 0x790 },
+	{ 0x900d3, 0x16a },
+	{ 0x900d4, 0x8 },
+	{ 0x900d5, 0x1d8 },
+	{ 0x900d6, 0x169 },
+	{ 0x900d7, 0x10 },
+	{ 0x900d8, 0x8558 },
+	{ 0x900d9, 0x168 },
+	{ 0x900da, 0x1ff8 },
+	{ 0x900db, 0x85a8 },
+	{ 0x900dc, 0x1e8 },
+	{ 0x900dd, 0x50 },
+	{ 0x900de, 0x798 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x60 },
+	{ 0x900e1, 0x7a0 },
+	{ 0x900e2, 0x16a },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0x8310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0x8 },
+	{ 0x900e7, 0xa310 },
+	{ 0x900e8, 0x168 },
+	{ 0x900e9, 0xa },
+	{ 0x900ea, 0x408 },
+	{ 0x900eb, 0x169 },
+	{ 0x900ec, 0x6e },
+	{ 0x900ed, 0x0 },
+	{ 0x900ee, 0x68 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x408 },
+	{ 0x900f1, 0x169 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0x8310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x0 },
+	{ 0x900f6, 0xa310 },
+	{ 0x900f7, 0x168 },
+	{ 0x900f8, 0x1ff8 },
+	{ 0x900f9, 0x85a8 },
+	{ 0x900fa, 0x1e8 },
+	{ 0x900fb, 0x68 },
+	{ 0x900fc, 0x798 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x78 },
+	{ 0x900ff, 0x7a0 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x68 },
+	{ 0x90102, 0x790 },
+	{ 0x90103, 0x16a },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0x8b10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0x8 },
+	{ 0x90108, 0xab10 },
+	{ 0x90109, 0x168 },
+	{ 0x9010a, 0xa },
+	{ 0x9010b, 0x408 },
+	{ 0x9010c, 0x169 },
+	{ 0x9010d, 0x58 },
+	{ 0x9010e, 0x0 },
+	{ 0x9010f, 0x68 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x408 },
+	{ 0x90112, 0x169 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0x8b10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x1 },
+	{ 0x90117, 0xab10 },
+	{ 0x90118, 0x168 },
+	{ 0x90119, 0x0 },
+	{ 0x9011a, 0x1d8 },
+	{ 0x9011b, 0x169 },
+	{ 0x9011c, 0x80 },
+	{ 0x9011d, 0x790 },
+	{ 0x9011e, 0x16a },
+	{ 0x9011f, 0x18 },
+	{ 0x90120, 0x7aa },
+	{ 0x90121, 0x6a },
+	{ 0x90122, 0xa },
+	{ 0x90123, 0x0 },
+	{ 0x90124, 0x1e9 },
+	{ 0x90125, 0x8 },
+	{ 0x90126, 0x8080 },
+	{ 0x90127, 0x108 },
+	{ 0x90128, 0xf },
+	{ 0x90129, 0x408 },
+	{ 0x9012a, 0x169 },
+	{ 0x9012b, 0xc },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x68 },
+	{ 0x9012e, 0x9 },
+	{ 0x9012f, 0x0 },
+	{ 0x90130, 0x1a9 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x408 },
+	{ 0x90133, 0x169 },
+	{ 0x90134, 0x0 },
+	{ 0x90135, 0x8080 },
+	{ 0x90136, 0x108 },
+	{ 0x90137, 0x8 },
+	{ 0x90138, 0x7aa },
+	{ 0x90139, 0x6a },
+	{ 0x9013a, 0x0 },
+	{ 0x9013b, 0x8568 },
+	{ 0x9013c, 0x108 },
+	{ 0x9013d, 0xb7 },
+	{ 0x9013e, 0x790 },
+	{ 0x9013f, 0x16a },
+	{ 0x90140, 0x1f },
+	{ 0x90141, 0x0 },
+	{ 0x90142, 0x68 },
+	{ 0x90143, 0x8 },
+	{ 0x90144, 0x8558 },
+	{ 0x90145, 0x168 },
+	{ 0x90146, 0xf },
+	{ 0x90147, 0x408 },
+	{ 0x90148, 0x169 },
+	{ 0x90149, 0xd },
+	{ 0x9014a, 0x0 },
+	{ 0x9014b, 0x68 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x408 },
+	{ 0x9014e, 0x169 },
+	{ 0x9014f, 0x0 },
+	{ 0x90150, 0x8558 },
+	{ 0x90151, 0x168 },
+	{ 0x90152, 0x8 },
+	{ 0x90153, 0x3c8 },
+	{ 0x90154, 0x1a9 },
+	{ 0x90155, 0x3 },
+	{ 0x90156, 0x370 },
+	{ 0x90157, 0x129 },
+	{ 0x90158, 0x20 },
+	{ 0x90159, 0x2aa },
+	{ 0x9015a, 0x9 },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x104 },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x448 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0xf },
+	{ 0x90168, 0x7c0 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x0 },
+	{ 0x9016b, 0xe8 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x47 },
+	{ 0x9016e, 0x630 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0x618 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x8 },
+	{ 0x90174, 0xe0 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x0 },
+	{ 0x90177, 0x7c8 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0x8140 },
+	{ 0x9017b, 0x10c },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x478 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x0 },
+	{ 0x90180, 0x1 },
+	{ 0x90181, 0x8 },
+	{ 0x90182, 0x8 },
+	{ 0x90183, 0x4 },
+	{ 0x90184, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2b },
+	{ 0x90026, 0x69 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x75 },
+	{ 0x2000c, 0xe9 },
+	{ 0x2000d, 0x91c },
+	{ 0x2000e, 0x2c },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x400f1, 0xe },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3732mts 1D */
+		.drate = 3732,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P0 3732mts 2D */
+		.drate = 3732,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info tqma93xxla_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3732, },
+};
diff --git a/arch/arm/boards/tqmls1046a/Makefile b/arch/arm/boards/tqmls1046a/Makefile
index 851a5dcb3d..4af7fc3602 100644
--- a/arch/arm/boards/tqmls1046a/Makefile
+++ b/arch/arm/boards/tqmls1046a/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o start.o
 obj-y += board.o
 bbenv-y += defaultenv-tqmls1046a
diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c
index 028be890e0..36bcae6bc0 100644
--- a/arch/arm/boards/tqmls1046a/board.c
+++ b/arch/arm/boards/tqmls1046a/board.c
@@ -10,14 +10,14 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <soc/fsl/immap_lsch2.h>
-#include <mach/bbu.h>
-#include <mach/layerscape.h>
+#include <mach/layerscape/bbu.h>
+#include <mach/layerscape/layerscape.h>
 
 static int tqmls1046a_mem_init(void)
 {
 	int ret;
 
-	if (!of_machine_is_compatible("tqc,tqmls1046a"))
+	if (!of_machine_is_compatible("tq,ls1046a-tqmls1046a"))
 		return 0;
 
 	arm_add_mem_device("ram0", 0x80000000, SZ_2G);
@@ -36,7 +36,7 @@ static int tqmls1046a_postcore_init(void)
 	enum bootsource bootsource;
 	unsigned long sd_bbu_flags = 0, qspi_bbu_flags = 0;
 
-	if (!of_machine_is_compatible("tqc,tqmls1046a"))
+	if (!of_machine_is_compatible("tq,ls1046a-tqmls1046a"))
 		return 0;
 
 	defaultenv_append_directory(defaultenv_tqmls1046a);
@@ -47,7 +47,7 @@ static int tqmls1046a_postcore_init(void)
 	/* divide CGA1/CGA2 PLL by 24 to get QSPI interface clock */
 	out_be32(&scfg->qspi_cfg, 0x30100000);
 
-	bootsource = ls1046_bootsource_get();
+	bootsource = ls1046a_bootsource_get();
 
 	switch (bootsource) {
 	case BOOTSOURCE_MMC:
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 99dcf1eff7..4a1496078a 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include <common.h>
 #include <debug_ll.h>
-#include <image-metadata.h>
 #include <platform_data/mmc-esdhc-imx.h>
 #include <soc/fsl/fsl_ddr_sdram.h>
 #include <soc/fsl/immap_lsch2.h>
@@ -9,10 +8,10 @@
 #include <asm/barebox-arm.h>
 #include <asm/syscounter.h>
 #include <asm/cache.h>
-#include <mach/errata.h>
-#include <mach/lowlevel.h>
-#include <mach/xload.h>
-#include <mach/layerscape.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/lowlevel.h>
+#include <mach/layerscape/xload.h>
+#include <mach/layerscape/layerscape.h>
 
 static struct fsl_ddr_controller ddrc[] = {
 	{
@@ -91,7 +90,7 @@ static struct fsl_ddr_controller ddrc[] = {
 	},
 };
 
-extern char __dtb_fsl_tqmls1046a_mbls10xxa_start[];
+extern char __dtb_z_fsl_ls1046a_tqmls1046a_mbls10xxa_start[];
 
 static noinline __noreturn void tqmls1046a_r_entry(void)
 {
@@ -99,19 +98,17 @@ static noinline __noreturn void tqmls1046a_r_entry(void)
 
 	if (get_pc() >= membase)
 		barebox_arm_entry(membase, 0x80000000 - SZ_64M,
-				  __dtb_fsl_tqmls1046a_mbls10xxa_start);
+				  __dtb_z_fsl_ls1046a_tqmls1046a_mbls10xxa_start);
 
 	arm_cpu_lowlevel_init();
 	ls1046a_init_lowlevel();
 
-	debug_ll_init();
+	ls1046a_debug_ll_init();
 
 	udelay(500);
 	putc_ll('>');
 
-	IMD_USED_OF(fsl_tqmls1046a_mbls10xxa);
-
-	fsl_ddr_set_memctl_regs(&ddrc[0], 0);
+	fsl_ddr_set_memctl_regs(&ddrc[0], 0, false);
 
 	ls1046a_errata_post_ddr();
 
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg
index 0a04afa770..e4c293ab77 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
 #Configure QSPI clock
 0957015c 40100000
 #Configure Scratch register
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
index 2df229c56c..490d45af9e 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
 # RCW values
 #   0:  1 - SYS_PLL_CFG              :       0 [0x0 / 0b00]
 #   2:  6 - SYS_PLL_RAT              :       6 [0x6 / 0b00110]
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg
index 72ab1cd7d7..645dc4fd22 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
 # RCW values
 #   0:  1 - SYS_PLL_CFG              :       0 [0x0 / 0b00]
 #   2:  6 - SYS_PLL_RAT              :       6 [0x6 / 0b00110]
diff --git a/arch/arm/boards/turris-omnia/Makefile b/arch/arm/boards/turris-omnia/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/turris-omnia/Makefile
+++ b/arch/arm/boards/turris-omnia/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/turris-omnia/lowlevel.c b/arch/arm/boards/turris-omnia/lowlevel.c
index b6520b5775..97d57e6ce0 100644
--- a/arch/arm/boards/turris-omnia/lowlevel.c
+++ b/arch/arm/boards/turris-omnia/lowlevel.c
@@ -3,14 +3,14 @@
 
 #include <common.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 
 #include <asm/io.h>
 
 extern char __dtb_armada_385_turris_omnia_bb_start[];
 
-ENTRY_FUNCTION(start_turris_omnia, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_turris_omnia, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/udoo-neo/Makefile b/arch/arm/boards/udoo-neo/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/udoo-neo/Makefile
+++ b/arch/arm/boards/udoo-neo/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/udoo-neo/board.c b/arch/arm/boards/udoo-neo/board.c
index 5964e92159..d9b9517fc1 100644
--- a/arch/arm/boards/udoo-neo/board.c
+++ b/arch/arm/boards/udoo-neo/board.c
@@ -2,16 +2,116 @@
 // SPDX-FileCopyrightText: 2014 Sascha Hauer, Pengutronix
 
 #include <common.h>
-#include <init.h>
-#include <linux/clk.h>
+#include <deep-probe.h>
+#include <gpio.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/imx6.h>
 
-static int imx6sx_udoneo_coredevices_init(void)
+/**
+ * Detects the board model by checking the R184 and R185 resistors.
+ * A mounted resistor (0Ohm) connects the GPIO to ground, so the
+ * GPIO value will be 0.
+ *
+ * FULL     - Eth, WiFi, motion sensors, 1GB RAM         -> R184 not mounted - R185 mounted
+ * EXTENDED - NO Eth, WiFi, motion sensors, 1GB RAM      -> R184 not mounted - R185 not mounted
+ * BASE     - Eth, NO WiFi, NO motion sensors, 512MB RAM -> R184 mounted     - R185 mounted
+ * BASE KS  - NO Eth, WiFi, NO motion sensors, 512MB RAM -> R184 mounted     - R185 not mounted
+ */
+
+enum imx6sx_udoneo_board_type {
+	UDOO_NEO_BASIC = 0,
+	UDOO_NEO_BASIC_KS = 1,
+	UDOO_NEO_FULL = 2,
+	UDOO_NEO_EXTENDED = 3,
+	UDOO_NEO_UNKNOWN,
+};
+
+#define GPIO_R184 IMX_GPIO_NR(4, 13)
+#define GPIO_R185 IMX_GPIO_NR(4, 0)
+
+static enum imx6sx_udoneo_board_type imx6sx_udoneo_detect(struct device *dev)
 {
-	if (!of_machine_is_compatible("fsl,imx6sx-udoo-neo"))
-		return 0;
+	struct device_node *gpio_np = NULL;
+	int r184, r185;
+	int ret;
+
+	gpio_np = of_find_node_by_name_address(NULL, "gpio@20a8000");
+	if (gpio_np) {
+		ret = of_device_ensure_probed(gpio_np);
+		if (ret) {
+			dev_warn(dev, "Can't probe GPIO node\n");
+			goto detect_error;
+		}
+	} else {
+		dev_warn(dev, "Can't get GPIO node\n");
+		goto detect_error;
+	}
+
+	ret = gpio_request(GPIO_R184, "version r184");
+	if (ret)
+		goto detect_error;
+
+	ret = gpio_request(GPIO_R185, "version r185");
+	if (ret)
+		goto detect_error;
+
+	ret = gpio_direction_input(GPIO_R184);
+	if (ret)
+		goto detect_error;
+
+	ret = gpio_direction_input(GPIO_R185);
+	if (ret)
+		goto detect_error;
+
+	r184 = gpio_get_value(GPIO_R184);
+	r185 = gpio_get_value(GPIO_R185);
+
+	return r184 << 1 | r185 << 0;
 
+detect_error:
+	dev_warn(dev, "Board detection failed\n");
+
+	return UDOO_NEO_UNKNOWN;
+}
+
+static int imx6sx_udoneo_probe(struct device *dev)
+{
+	enum imx6sx_udoneo_board_type type;
+	const char *model;
+
+	type = imx6sx_udoneo_detect(dev);
+	switch (type) {
+	case UDOO_NEO_FULL:
+		model = "UDOO Neo Full";
+		break;
+	case UDOO_NEO_EXTENDED:
+		model = "UDOO Neo Extended";
+		break;
+	case UDOO_NEO_BASIC:
+		model = "UDOO Neo Basic";
+		break;
+	default:
+		model = "UDOO Neo unknown";
+	}
+
+	barebox_set_model(model);
 	barebox_set_hostname("mx6sx-udooneo");
 
+	imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc1.barebox",
+			BBU_HANDLER_FLAG_DEFAULT);
+
 	return 0;
 }
-coredevice_initcall(imx6sx_udoneo_coredevices_init);
+
+static const struct of_device_id imx6sx_udoneo_of_match[] = {
+	{ .compatible = "udoo,neofull" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(imx6sx_udoneo_of_match);
+
+static struct driver imx6sx_udoneo_driver = {
+	.name = "board-udoo-neo",
+	.probe = imx6sx_udoneo_probe,
+	.of_compatible = imx6sx_udoneo_of_match,
+};
+postcore_platform_driver(imx6sx_udoneo_driver);
diff --git a/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg
index a349b1022b..6246e17a73 100644
--- a/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg
+++ b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 /*
  * These values are taken from:
  * repository: https://github.com/UDOOboard/uboot-imx
diff --git a/arch/arm/boards/udoo-neo/lowlevel.c b/arch/arm/boards/udoo-neo/lowlevel.c
index bb6b7d8332..e8712b0c72 100644
--- a/arch/arm/boards/udoo-neo/lowlevel.c
+++ b/arch/arm/boards/udoo-neo/lowlevel.c
@@ -1,10 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/esdctl.h>
+#include <mach/imx/esdctl.h>
 
 static inline void setup_uart(void)
 {
diff --git a/arch/arm/boards/udoo/Makefile b/arch/arm/boards/udoo/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/udoo/Makefile
+++ b/arch/arm/boards/udoo/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/udoo/board.c b/arch/arm/boards/udoo/board.c
index 36dd58cc98..b7ab908427 100644
--- a/arch/arm/boards/udoo/board.c
+++ b/arch/arm/boards/udoo/board.c
@@ -7,25 +7,24 @@
 #include <common.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/imx6-regs.h>
+#include <mach/imx/imx6-regs.h>
 #include <gpio.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <linux/phy.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
 #include <net.h>
 #include <linux/micrel_phy.h>
-#include <mach/imx6.h>
-#include <mach/devices-imx6.h>
-#include <mach/iomux-mx6.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/devices-imx6.h>
+#include <mach/imx/iomux-mx6.h>
 #include <spi/spi.h>
-#include <mach/spi.h>
-#include <mach/usb.h>
+#include <mach/imx/spi.h>
+#include <mach/imx/usb.h>
 
 static iomux_v3_cfg_t udoo_enet_gpio_pads_1[] = {
 	/* RGMII reset */
diff --git a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg
index fc88a0b8b4..95ba1ddc41 100644
--- a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg
+++ b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx6
 loadaddr 0x20000000
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 /* MX6_IOM_DRAM_SDQS0 -> MX6_IOM_DRAM_SDQS7 */
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
diff --git a/arch/arm/boards/udoo/lowlevel.c b/arch/arm/boards/udoo/lowlevel.c
index 1f06f7e37f..2570239b96 100644
--- a/arch/arm/boards/udoo/lowlevel.c
+++ b/arch/arm/boards/udoo/lowlevel.c
@@ -1,6 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
diff --git a/arch/arm/boards/usb-a926x/Makefile b/arch/arm/boards/usb-a926x/Makefile
index 65cc4082fc..022b1a4ab6 100644
--- a/arch/arm/boards/usb-a926x/Makefile
+++ b/arch/arm/boards/usb-a926x/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 
 obj-$(CONFIG_AT91_BOOTSTRAP) += usb_a9263_bootstrap.o
diff --git a/arch/arm/boards/usb-a926x/defaultenv-usb-a926x/config b/arch/arm/boards/usb-a926x/defaultenv-usb-a926x/config
index 49199ba391..f9159cb946 100644
--- a/arch/arm/boards/usb-a926x/defaultenv-usb-a926x/config
+++ b/arch/arm/boards/usb-a926x/defaultenv-usb-a926x/config
@@ -29,10 +29,6 @@ kernelimage=zImage
 #kernelimage=Image
 #kernelimage=Image.lzo
 
-nand_device=atmel_nand
-nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
-rootfs_mtdblock_nand=6
-
 autoboot_timeout=3
 
 bootargs="console=ttyS0,115200"
diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
index c39992c91b..1297b4fe7f 100644
--- a/arch/arm/boards/usb-a926x/init.c
+++ b/arch/arm/boards/usb-a926x/init.c
@@ -6,27 +6,26 @@
 #include <init.h>
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <fs.h>
 #include <fcntl.h>
 #include <io.h>
 #include <envfs.h>
-#include <mach/hardware.h>
-#include <mach/at91sam926x.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91sam926x.h>
 #include <nand.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/clk.h>
-#include <mach/board.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91sam9_smc.h>
+#include <mach/at91/at91sam9_sdramc.h>
 #include <gpio.h>
 #include <led.h>
-#include <mach/iomux.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_rstc.h>
 #include <gpio_keys.h>
 #include <readkey.h>
 #include <spi/spi.h>
@@ -396,7 +395,7 @@ device_initcall(usb_a9260_devices_init);
 #ifndef CONFIG_CONSOLE_NONE
 static int usb_a9260_console_init(void)
 {
-	struct device_d *dev;
+	struct device *dev;
 
 	if (machine_is_usb_a9260()) {
 		barebox_set_model("Calao USB-A9260");
diff --git a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c
index 7f52f824df..66753669d6 100644
--- a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c
+++ b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c
@@ -7,14 +7,23 @@
 #include <common.h>
 #include <init.h>
 
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91sam9260.h>
+#include <mach/at91/hardware.h>
 
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9260.h>
-#include <mach/hardware.h>
+AT91_ENTRY_FUNCTION(start_usb_a9260, r0, r1, r2)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  NULL);
+}
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_usb_a9g20, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c
index f26f1eaecb..5739b0f2da 100644
--- a/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c
+++ b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <bootstrap.h>
-#include <mach/bootstrap.h>
+#include <mach/at91/bootstrap.h>
 
 #ifdef CONFIG_MTD_DATAFLASH
 void * bootstrap_board_read_dataflash(void)
diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
index 2ad88d7f22..eda534c68e 100644
--- a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
+++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
@@ -6,10 +6,9 @@
 
 #include <linux/sizes.h>
 
-#include <asm/barebox-arm.h>
-
-#include <mach/at91sam926x_board_init.h>
-#include <mach/at91sam9263_matrix.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91sam926x_board_init.h>
+#include <mach/at91/at91sam9263_matrix.h>
 
 #define MASTER_CLOCK		180
 
@@ -20,7 +19,7 @@
 #endif
 #define MASTER_PLL_DIV		6
 
-static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg)
+static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg, bool has_mem_128m)
 {
 	/* Disable Watchdog */
 	cfg->wdt_mr =
@@ -88,7 +87,7 @@ static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg
 		(5 << 24) |		/* Active to Precharge Delay */
 		(8 << 28);		/* Exit Self Refresh to Active Delay */
 
-	if (IS_ENABLED(CONFIG_AT91_HAVE_SRAM_128M))
+	if (has_mem_128m)
 		cfg->sdrc_cr |= AT91_SDRAMC_NC_10;
 	else
 		cfg->sdrc_cr |= AT91_SDRAMC_NC_9;
@@ -106,7 +105,7 @@ static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg
 		AT91_RSTC_RSTTYP_WATCHDOG;
 }
 
-static void __bare_init usb_a9263_init(void)
+static void __bare_init usb_a9263_init(bool has_mem_128m)
 {
 	struct at91sam926x_board_cfg cfg;
 
@@ -115,18 +114,27 @@ static void __bare_init usb_a9263_init(void)
 	cfg.ebi_pio_is_peripha = true;
 	cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
 
-	usb_a9263_board_config(&cfg);
+	usb_a9263_board_config(&cfg, has_mem_128m);
 	at91sam9263_board_init(&cfg);
 
 	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
 	                  NULL);
 }
 
-void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+AT91_ENTRY_FUNCTION(start_usb_a9263, r0, r1, r2)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE);
+
+	usb_a9263_init(false);
+}
+
+AT91_ENTRY_FUNCTION(start_usb_a9263_128m, r0, r1, r2)
 {
 	arm_cpu_lowlevel_init();
 
 	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE);
 
-	usb_a9263_init();
+	usb_a9263_init(true);
 }
diff --git a/arch/arm/boards/usi-topkick/Makefile b/arch/arm/boards/usi-topkick/Makefile
index b08c4a93ca..458f520900 100644
--- a/arch/arm/boards/usi-topkick/Makefile
+++ b/arch/arm/boards/usi-topkick/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/usi-topkick/lowlevel.c b/arch/arm/boards/usi-topkick/lowlevel.c
index 0193deadbe..d9118f5d2c 100644
--- a/arch/arm/boards/usi-topkick/lowlevel.c
+++ b/arch/arm/boards/usi-topkick/lowlevel.c
@@ -4,12 +4,12 @@
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/barebox-arm-head.h>
+#include <mach/mvebu/lowlevel.h>
 
 extern char __dtb_kirkwood_topkick_bb_start[];
 
-ENTRY_FUNCTION(start_usi_topkick, r0, r1, r2)
+ENTRY_FUNCTION_MVEBU(start_usi_topkick, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/Makefile b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/Makefile
new file mode 100644
index 0000000000..35d8640087
--- /dev/null
+++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += board.o
+lwl-y += lowlevel.o lpddr4-timing.o
diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/board.c b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/board.c
new file mode 100644
index 0000000000..154931d534
--- /dev/null
+++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/board.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Michael Kopfensteiner, VAHLE Automation GmbH
+ */
+
+#include <asm/memory.h>
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <gpio.h>
+#include <envfs.h>
+
+#define PHY_ID_ADIN1300		0x0283bc30
+#define PHY_ID_MODEL_MASK	0xfffffff0
+
+/*
+ * This fixup is necessary to properly configure the ADIN1300
+ * PHY on the SOM to properly communicate using RGMII.
+ * This fixup disables the PHY's internal 2ns RGMII receive clock
+ * delay. Without this configuration change, the system will
+ * be able to send Ethernet packages, but the MAC won't receive
+ * any response packages.
+ *
+ * This fixup is specific to the ADIN1300 PHY. This implementation
+ * was ported from Variscite's U-Boot sources.
+ */
+static int phy_fixup_adin1300(struct phy_device *dev) {
+	int ret;
+
+	pr_debug("BOARD: applying PHY fixup for ADIN1300\n");
+
+	ret = mdiobus_write(dev->bus, dev->addr, 0x0010, 0xFF23);
+	if (ret) {
+		pr_warn("ADIN1300 PHY fixup: failed to write EXT_REG_PTR\n");
+		return ret;
+	}
+
+	ret = mdiobus_write(dev->bus, dev->addr, 0x0011, 0x0E01);
+	if (ret)  {
+		pr_warn("ADIN1300 PHY fixup: failed to write EXT_REG_DATA\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int var_imx8mp_dart_cb_probe(struct device *dev)
+{
+	int emmc_bbu_flag = 0;
+	int sd_bbu_flag = 0;
+
+	phy_register_fixup_for_uid(PHY_ID_ADIN1300, PHY_ID_MODEL_MASK, phy_fixup_adin1300);
+
+	if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) {
+		of_device_enable_path("/chosen/environment-sd");
+		sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	} else {
+		of_device_enable_path("/chosen/environment-emmc");
+		emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+	}
+
+	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
+	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
+
+	return 0;
+}
+
+static const struct of_device_id var_imx8mp_dart_cb_of_match[] = {
+	{ .compatible = "variscite,imx8mp-var-dart" },
+	{ /* Sentinel */ }
+};
+BAREBOX_DEEP_PROBE_ENABLE(var_imx8mp_dart_cb_of_match);
+
+static struct driver var_imx8mp_dart_cb_board_driver = {
+	.name = "board-var-imx8mp-dart-cb",
+	.probe = var_imx8mp_dart_cb_probe,
+	.of_compatible = var_imx8mp_dart_cb_of_match,
+};
+coredevice_platform_driver(var_imx8mp_dart_cb_board_driver);
diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/flash-header-imx8mp-dart.imxcfg b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/flash-header-imx8mp-dart.imxcfg
new file mode 100644
index 0000000000..c3149a197f
--- /dev/null
+++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/flash-header-imx8mp-dart.imxcfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mp
+
+loadaddr 0x918000
+max_load_size 0x3f000
+ivtofs 0x0
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lowlevel.c b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lowlevel.c
new file mode 100644
index 0000000000..c9907ebf0a
--- /dev/null
+++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lowlevel.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <io.h>
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
+#include <firmware.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <linux/sizes.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8mp-regs.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mfd/pca9450.h>
+#include <soc/imx8m/ddr.h>
+#include <soc/fsl/fsl_udc.h>
+
+extern char __dtb_z_imx8mp_var_dart_dt8mcustomboard_start[];
+
+#define UART_PAD_CTRL   MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | MX8MP_PAD_CTL_FSEL)
+#define I2C_PAD_CTRL	MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+					MX8MP_PAD_CTL_HYS | \
+					MX8MP_PAD_CTL_PUE | \
+					MX8MP_PAD_CTL_PE)
+
+static void setup_uart(void)
+{
+	void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR);
+
+	imx8m_early_setup_uart_clock();
+
+	imx8mp_setup_pad(MX8MP_PAD_UART1_TXD__UART1_DCE_TX | UART_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_UART1_RXD__UART1_DCE_RX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+
+	putc_ll('>');
+}
+
+static struct pmic_config pca9450_cfg[] = {
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	{ PCA9450_BUCK123_DVS, 0x29 },
+	/*
+	 * increase VDD_SOC to typical value 0.95V before first
+	 * DRAM access, set DVS1 to 0.85v for suspend.
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+	 */
+	{ PCA9450_BUCK1OUT_DVS0, 0x1C },
+	{ PCA9450_BUCK1OUT_DVS1, 0x14 },
+	{ PCA9450_BUCK1CTRL, 0x59 },
+	/* set WDOG_B_CFG to cold reset */
+	{ PCA9450_RESET_CTRL, 0xA1 },
+};
+
+static void power_init_board(void)
+{
+	struct pbl_i2c *i2c;
+
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
+	imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+	i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
+
+	pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+}
+
+extern struct dram_timing_info var_dart_imx8mp_dram_timing;
+
+static void start_atf(void)
+{
+	/*
+	 * If we are in EL3 we are running for the first time and need to
+	 * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
+	 * to DRAM in EL2.
+	 */
+	if (current_el() != 3)
+		return;
+
+	imx8mm_early_clock_init();
+
+	power_init_board();
+
+	imx8mp_ddr_init(&var_dart_imx8mp_dram_timing, DRAM_TYPE_LPDDR4);
+
+	imx8mp_load_and_start_image_via_tfa();
+}
+
+static __noreturn noinline void variscite_imx8mp_dart_cb_start(void)
+{
+	setup_uart();
+	start_atf();
+
+	/*
+	 * Standard entry we hit once we initialized both DDR and ATF
+	 */
+	imx8mp_barebox_entry(__dtb_z_imx8mp_var_dart_dt8mcustomboard_start);
+}
+
+/*
+ * Power-on execution flow of nxp_imx8mp_vardart_start() might not be
+ * obvious for a very first read, so here's, hopefully helpful,
+ * summary:
+ *
+ * 1. MaskROM uploads PBL into OCRAM and that's where this function is
+ *    executed for the first time. At entry the exception level is EL3.
+ *
+ * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL
+ *    part is copied from OCRAM to the TF-A return address in DRAM.
+ *
+ * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us
+ *    from EL3 to EL2.
+ *
+ * 4. Standard barebox boot flow continues
+ */
+ENTRY_FUNCTION(start_variscite_imx8mp_dart, r0, r1, r2)
+{
+	imx8mp_cpu_lowlevel_init();
+	relocate_to_current_adr();
+	setup_c();
+
+	variscite_imx8mp_dart_cb_start();
+}
diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lpddr4-timing.c b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lpddr4-timing.c
new file mode 100644
index 0000000000..b85935ca05
--- /dev/null
+++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lpddr4-timing.c
@@ -0,0 +1,1128 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ *
+ * These sources have been migrated from Variscite's public U-Boot sources for
+ * the i.MX8MP DART CustomBoard (= DT8MCustomBoard) eval kit. Solely this
+ * comment and the header-includes have been adapted.
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+#include <soc/imx8m/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400020, 0x1323 },
+	{ 0x3d400024, 0x1e84800 },
+	{ 0x3d400064, 0x7a0118 },
+	{ 0x3d400070, 0x61027f10 },
+	{ 0x3d400074, 0x7b0 },
+	{ 0x3d4000d0, 0xc00307a3 },
+	{ 0x3d4000d4, 0xc50000 },
+	{ 0x3d4000dc, 0xf4003f },
+	{ 0x3d4000e0, 0x330000 },
+	{ 0x3d4000e8, 0x660048 },
+	{ 0x3d4000ec, 0x160048 },
+	{ 0x3d400100, 0x2028222a },
+	{ 0x3d400104, 0x8083f },
+	{ 0x3d40010c, 0xe0e000 },
+	{ 0x3d400110, 0x12040a12 },
+	{ 0x3d400114, 0x2050f0f },
+	{ 0x3d400118, 0x1010009 },
+	{ 0x3d40011c, 0x501 },
+	{ 0x3d400130, 0x20800 },
+	{ 0x3d400134, 0xe100002 },
+	{ 0x3d400138, 0x120 },
+	{ 0x3d400144, 0xc80064 },
+	{ 0x3d400180, 0x3e8001e },
+	{ 0x3d400184, 0x3207a12 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x49f820e },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x1f0e },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x9121c1c },
+	{ 0x3d400200, 0x17 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1021 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x330000 },
+	{ 0x3d4020e8, 0x660048 },
+	{ 0x3d4020ec, 0x160048 },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x1021 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x330000 },
+	{ 0x3d4030e8, 0x660048 },
+	{ 0x3d4030ec, 0x160048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x18 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x3e8 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xfa0 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x3ff4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x3ff4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xf400 },
+	{ 0x54033, 0x333f },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xf400 },
+	{ 0x54039, 0x333f },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x8 },
+	{ 0x90159, 0xe8 },
+	{ 0x9015a, 0x109 },
+	{ 0x9015b, 0x0 },
+	{ 0x9015c, 0x8140 },
+	{ 0x9015d, 0x10c },
+	{ 0x9015e, 0x10 },
+	{ 0x9015f, 0x8138 },
+	{ 0x90160, 0x104 },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0x448 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0xf },
+	{ 0x90165, 0x7c0 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0x0 },
+	{ 0x90168, 0xe8 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x47 },
+	{ 0x9016b, 0x630 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x618 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0xe0 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x0 },
+	{ 0x90174, 0x7c8 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x8140 },
+	{ 0x90178, 0x10c },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x478 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x1 },
+	{ 0x9017e, 0x8 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x4 },
+	{ 0x90181, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x68 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x7d },
+	{ 0x2000c, 0xfa },
+	{ 0x2000d, 0x9c4 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 4000mts 1D */
+		.drate = 4000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 4000mts 2D */
+		.drate = 4000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info var_dart_imx8mp_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 4000, 400, 100, },
+};
diff --git a/arch/arm/boards/variscite-mx6/Makefile b/arch/arm/boards/variscite-mx6/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/variscite-mx6/Makefile
+++ b/arch/arm/boards/variscite-mx6/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/variscite-mx6/board.c b/arch/arm/boards/variscite-mx6/board.c
index 99cd15b1c0..53a453dfa0 100644
--- a/arch/arm/boards/variscite-mx6/board.c
+++ b/arch/arm/boards/variscite-mx6/board.c
@@ -16,17 +16,16 @@
 
 #include <environment.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
+#include <asm/mach-types.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
-#include <mach/imx6.h>
-#include <mach/devices-imx6.h>
-#include <mach/iomux-mx6.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/devices-imx6.h>
+#include <mach/imx/iomux-mx6.h>
 #include <spi/spi.h>
-#include <mach/spi.h>
+#include <mach/imx/spi.h>
 #include <i2c/i2c.h>
 
 #define ETH_PHY_RST	IMX_GPIO_NR(1, 25)
diff --git a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg
index 50968d7940..34790120ac 100644
--- a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg
+++ b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 loadaddr 0x10000000
 soc imx6
 ivtofs 0x400
 
-#include <mach/imx6-ddr-regs.h>
-#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx/imx6-ddr-regs.h>
+#include <mach/imx/imx6q-ddr-regs.h>
 
 wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000
 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c
index 99455b2a45..d0842b1579 100644
--- a/arch/arm/boards/variscite-mx6/lowlevel.c
+++ b/arch/arm/boards/variscite-mx6/lowlevel.c
@@ -6,6 +6,7 @@
  */
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
 #include <linux/sizes.h>
 #include <io.h>
@@ -14,7 +15,7 @@
 #include <asm/sections.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <mach/imx6.h>
+#include <mach/imx/imx6.h>
 
 static inline void setup_uart(void)
 {
diff --git a/arch/arm/boards/variscite-som-mx7/Makefile b/arch/arm/boards/variscite-som-mx7/Makefile
new file mode 100644
index 0000000000..5b7f460c6d
--- /dev/null
+++ b/arch/arm/boards/variscite-som-mx7/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix <rhi@pengutronix.de>
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/variscite-som-mx7/board.c b/arch/arm/boards/variscite-som-mx7/board.c
new file mode 100644
index 0000000000..005228d107
--- /dev/null
+++ b/arch/arm/boards/variscite-som-mx7/board.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix <rhi@pengutronix.de>
+
+#include <common.h>
+#include <deep-probe.h>
+#include <mach/imx/bbu.h>
+
+static int var_som_mx7_probe(struct device_d *dev)
+{
+	imx7_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", BBU_HANDLER_FLAG_DEFAULT);
+	return 0;
+}
+
+static const struct of_device_id var_som_mx7_of_match[] = {
+	{ .compatible = "variscite,var-som-mx7" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(var_som_mx7_of_match);
+
+static struct driver_d var_som_mx7_board_driver = {
+	.name = "board-var-som-mx7",
+	.probe = var_som_mx7_probe,
+	.of_compatible = DRV_OF_COMPAT(var_som_mx7_of_match),
+};
+postcore_platform_driver(var_som_mx7_board_driver);
diff --git a/arch/arm/boards/variscite-som-mx7/flash-header.imxcfg b/arch/arm/boards/variscite-som-mx7/flash-header.imxcfg
new file mode 100644
index 0000000000..a8ed640cb2
--- /dev/null
+++ b/arch/arm/boards/variscite-som-mx7/flash-header.imxcfg
@@ -0,0 +1,100 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * SPDX-FileCopyrightText: 2014-2016 Freescale Semiconductor, Inc.
+ * SPDX-FileCopyrightText: 2016 Variscite Ltd.
+ * SPDX-FileCopyrightText: 2022 Gossen Metrawatt GmbH
+ * SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix <rhi@pengutronix.de>
+ */
+
+soc imx7
+loadaddr 0x80000000
+ivtofs 0x400
+
+#include <mach/imx/imx7-ddr-regs.h>
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* Change DDR freq. to 400Mhz */
+wm 32 0x30360070 0x00703021
+wm 32 0x30360090 0x00000000
+wm 32 0x30360070 0x00603021
+check 32 until_all_bits_set 0x30360070 0x80000000
+wm 32 0x30389880 0x00000001
+
+
+wm 32 0x30340004 0x4F400005    /* Enable OCRAM EPDC */
+/* Clear then set bit30 to ensure exit from DDR retention */
+wm 32 0x30360388 0x40000000
+wm 32 0x30360384 0x40000000
+
+wm 32 0x30391000 0x00000002    /* deassert presetn */
+
+/* ddrc */
+wm 32 0x307a0000 0x01040001    /* mstr */
+wm 32 0x307a01a0 0x80400003    /* dfiupd0 */
+wm 32 0x307a01a4 0x00100020    /* dfiupd1 */
+wm 32 0x307a01a8 0x80100004    /* dfiupd2 */
+wm 32 0x307a0064 0x00400046    /* rfshtmg */
+wm 32 0x307a0490 0x00000001    /* pctrl_0 */
+wm 32 0x307a00d0 0x00020083    /* init0 */
+wm 32 0x307a00d4 0x00690000    /* init1 */
+wm 32 0x307a00dc 0x09300004    /* init3 */
+wm 32 0x307a00e0 0x04080000    /* init4 */
+wm 32 0x307a00e4 0x00100004    /* init5 */
+wm 32 0x307a00f4 0x0000033f    /* rankctl */
+wm 32 0x307a0100 0x09081109    /* dramtmg0 */
+wm 32 0x307a0104 0x0007020d    /* dramtmg1 */
+wm 32 0x307a0108 0x03040407    /* dramtmg2 */
+wm 32 0x307a010c 0x00002006    /* dramtmg3 */
+wm 32 0x307a0110 0x04020205    /* dramtmg4 */
+wm 32 0x307a0114 0x03030202    /* dramtmg5 */
+wm 32 0x307a0120 0x00000803    /* dramtmg8 */
+wm 32 0x307a0180 0x00800020    /* zqctl0 */
+wm 32 0x307a0190 0x02098204    /* dfitmg0 */
+wm 32 0x307a0194 0x00030303    /* dfitmg1 */
+wm 32 0x307a0200 0x00000016    /* addrmap0 */
+wm 32 0x307a0204 0x00080808    /* addrmap1 */
+wm 32 0x307a0210 0x00000f0f    /* addrmap4 */
+wm 32 0x307a0214 0x07070707    /* addrmap5 */
+wm 32 0x307a0218 0x0F070707    /* addrmap6 */
+wm 32 0x307a0240 0x06000604    /* odtcfg */
+wm 32 0x307a0244 0x00000001    /* odtmap */
+
+wm 32 0x30391000 0x00000000    /* deassert presetn */
+
+/* ddr_phy */
+wm 32 0x30790000 0x17420f40    /* phy_con0 */
+wm 32 0x30790004 0x10210100    /* phy_con1 */
+wm 32 0x30790010 0x00060807    /* phy_con4 */
+wm 32 0x307900b0 0x1010007e    /* mdll_con0 */
+wm 32 0x3079009c 0x00000d6e    /* drvds_con0 */
+wm 32 0x30790020 0x08080808    /* offset_rd_con0 */
+wm 32 0x30790030 0x08080808    /* offset_wr_con0 */
+wm 32 0x30790050 0x01000010    /* cmd_sdll_con0 (OFFSETD_CON0) */
+wm 32 0x30790050 0x00000010    /* cmd_sdll_con0 (OFFSETD_CON0) */
+wm 32 0x307900c0 0x0e407304    /* zq_con0 */
+wm 32 0x307900c0 0x0e447304    /* zq_con0 */
+wm 32 0x307900c0 0x0e447306    /* zq_con0 */
+
+check 32 until_all_bits_set 0x307900c4 0x1
+
+wm 32 0x307900c0 0x0e447304    /* zq_con0 */
+wm 32 0x307900c0 0x0e407304    /* zq_con0 */
+
+
+wm 32 0x30384130 0x00000000    /* Disable Clock */
+wm 32 0x30340020 0x00000178    /* IOMUX_GRP_GRP8 - Start input to PHY */
+wm 32 0x30384130 0x00000002    /* Enable Clock */
+wm 32 0x30790018 0x0000000f    /* ddr_phy lp_con0 */
+
+check 32 until_all_bits_set 0x307a0004 0x1
diff --git a/arch/arm/boards/variscite-som-mx7/lowlevel.c b/arch/arm/boards/variscite-som-mx7/lowlevel.c
new file mode 100644
index 0000000000..ef67fc3b5a
--- /dev/null
+++ b/arch/arm/boards/variscite-som-mx7/lowlevel.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix <rhi@pengutronix.de>
+
+#include <io.h>
+#include <common.h>
+#include <console.h>
+#include <debug_ll.h>
+
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+
+#include <linux/sizes.h>
+
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/iomux-mx7.h>
+#include <mach/imx/imx7-ccm-regs.h>
+
+static inline void setup_uart(void)
+{
+	imx7_early_setup_uart_clock(1);
+
+	imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX);
+
+	imx7_uart_setup_ll();
+
+	putc_ll('>');
+}
+
+ENTRY_FUNCTION_WITHSTACK(start_gome_e143_01, 0, r0, r1, r2)
+{
+	extern char __dtb_imx7d_gome_e143_01_start[];
+
+	imx7_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	imx7d_barebox_entry(__dtb_imx7d_gome_e143_01_start + get_runtime_offset());
+}
diff --git a/arch/arm/boards/versatile/Kconfig b/arch/arm/boards/versatile/Kconfig
index 94cba3ba81..66492404e0 100644
--- a/arch/arm/boards/versatile/Kconfig
+++ b/arch/arm/boards/versatile/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 if MACH_VERSATILEPB
 
diff --git a/arch/arm/boards/versatile/Makefile b/arch/arm/boards/versatile/Makefile
index 89232a7884..5a55d0017d 100644
--- a/arch/arm/boards/versatile/Makefile
+++ b/arch/arm/boards/versatile/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-$(CONFIG_MACH_VERSATILEPB) += versatilepb.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/versatile/env/init/mtdparts-nor b/arch/arm/boards/versatile/env/init/mtdparts-nor
deleted file mode 100644
index 20c2b994cc..0000000000
--- a/arch/arm/boards/versatile/env/init/mtdparts-nor
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-mtdparts="512k(nor0.barebox)ro,512k(nor0.bareboxenv),4864k(nor0.kernel),256k(nor0.dtb),3M(nor0.update),-(nor0.root)"
-kernelname="physmap-flash.0"
-
-mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/versatile/lowlevel.c b/arch/arm/boards/versatile/lowlevel.c
index beab04d234..04209dc12c 100644
--- a/arch/arm/boards/versatile/lowlevel.c
+++ b/arch/arm/boards/versatile/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
@@ -5,7 +7,7 @@
 
 extern char __dtb_versatile_pb_start[];
 
-void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+ENTRY_FUNCTION(start_versatile_pb, r0, r1, r2)
 {
 	void *fdt;
 
diff --git a/arch/arm/boards/versatile/versatilepb.c b/arch/arm/boards/versatile/versatilepb.c
index ac6ea9951a..610aa90982 100644
--- a/arch/arm/boards/versatile/versatilepb.c
+++ b/arch/arm/boards/versatile/versatilepb.c
@@ -13,11 +13,9 @@
 #include <init.h>
 #include <asm/armlinux.h>
 #include <asm/system_info.h>
-#include <generated/mach-types.h>
-#include <mach/init.h>
-#include <mach/platform.h>
+#include <asm/mach-types.h>
+#include <mach/versatile/platform.h>
 #include <environment.h>
-#include <partition.h>
 #include <linux/sizes.h>
 #include <platform_data/eth-smc91111.h>
 
@@ -26,6 +24,10 @@ static int vpb_console_init(void)
 	char *hostname = "versatilepb-unknown";
 	char *model = "ARM Versatile PB";
 
+	if (!of_machine_is_compatible("arm,versatile-pb") &&
+	    !of_machine_is_compatible("arm,versatile-ab"))
+		return 0;
+
 	if (cpu_is_arm926()) {
 		hostname = "versatilepb-arm926";
 		model = "ARM Versatile PB (arm926)";
@@ -34,29 +36,10 @@ static int vpb_console_init(void)
 		model = "ARM Versatile PB (arm1176)";
 	}
 
+	armlinux_set_architecture(MACH_TYPE_VERSATILE_PB);
 	barebox_set_hostname(hostname);
 	barebox_set_model(model);
 
-	versatile_register_uart(0);
 	return 0;
 }
 console_initcall(vpb_console_init);
-
-static struct smc91c111_pdata net_pdata = {
-	.qemu_fixup = 1,
-};
-
-static int vpb_devices_init(void)
-{
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0);
-	devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self");
-	devfs_add_partition("nor0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
-
-	add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, VERSATILE_ETH_BASE,
-			64 * 1024, IORESOURCE_MEM, &net_pdata);
-
-	armlinux_set_architecture(MACH_TYPE_VERSATILE_PB);
-
-	return 0;
-}
-device_initcall(vpb_devices_init);
diff --git a/arch/arm/boards/vexpress/Makefile b/arch/arm/boards/vexpress/Makefile
index 2da0494d49..720210d890 100644
--- a/arch/arm/boards/vexpress/Makefile
+++ b/arch/arm/boards/vexpress/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += init.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/vexpress/init.c b/arch/arm/boards/vexpress/init.c
index 6ba23bbb62..f2a1307e45 100644
--- a/arch/arm/boards/vexpress/init.c
+++ b/arch/arm/boards/vexpress/init.c
@@ -8,8 +8,8 @@
 #include <init.h>
 #include <asm/armlinux.h>
 #include <asm/system_info.h>
-#include <generated/mach-types.h>
-#include <mach/devices.h>
+#include <asm/mach-types.h>
+#include <mach/vexpress/devices.h>
 #include <environment.h>
 #include <linux/sizes.h>
 #include <io.h>
@@ -42,7 +42,7 @@ static int of_fixup_virtio_mmio(struct device_node *root, void *unused)
 	return 0;
 }
 
-static int vexpress_probe(struct device_d *dev)
+static int vexpress_probe(struct device *dev)
 {
 	char *hostname = "vexpress-unknown";
 	int ret = 0;
@@ -77,8 +77,9 @@ static const struct of_device_id vexpress_of_match[] = {
 	{ .compatible = "arm,vexpress" },
 	{ /* Sentinel */},
 };
+MODULE_DEVICE_TABLE(of, vexpress_of_match);
 
-static struct driver_d vexpress_board_driver = {
+static struct driver vexpress_board_driver = {
 	.name = "board-vexpress",
 	.probe = vexpress_probe,
 	.of_compatible = vexpress_of_match,
diff --git a/arch/arm/boards/virt2real/Makefile b/arch/arm/boards/virt2real/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/virt2real/Makefile
+++ b/arch/arm/boards/virt2real/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/vscom-baltos/Makefile b/arch/arm/boards/vscom-baltos/Makefile
index 092c31d6b2..5678718188 100644
--- a/arch/arm/boards/vscom-baltos/Makefile
+++ b/arch/arm/boards/vscom-baltos/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 obj-y += board.o
diff --git a/arch/arm/boards/vscom-baltos/board.c b/arch/arm/boards/vscom-baltos/board.c
index 59782d2990..85cf241574 100644
--- a/arch/arm/boards/vscom-baltos/board.c
+++ b/arch/arm/boards/vscom-baltos/board.c
@@ -17,14 +17,14 @@
 #include <net.h>
 #include <bootsource.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <mach/am33xx-generic.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/gpmc.h>
+#include <asm/mach-types.h>
+#include <mach/omap/am33xx-generic.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/gpmc.h>
 #include <linux/err.h>
-#include <mach/bbu.h>
+#include <mach/omap/bbu.h>
 #include <libfile.h>
 #include <gpio.h>
 
@@ -49,6 +49,7 @@ static uint8_t get_dip_switch(uint16_t id, uint32_t rev)
 {
 	uint16_t maj, min;
 	uint8_t dip = 0;
+	int inputs[4];
 
 	maj = rev >> 16;
 	min = rev & 0xffff;
@@ -59,10 +60,14 @@ static uint8_t get_dip_switch(uint16_t id, uint32_t rev)
 	switch(id) {
 		case 214:
 		case 215:
-			dip = !gpio_get_value(44);
-			dip += !gpio_get_value(45) << 1;
-			dip += !gpio_get_value(46) << 2;
-			dip += !gpio_get_value(47) << 3;
+			inputs[0] = gpio_find_by_name("SW2_0_alt");
+			inputs[1] = gpio_find_by_name("SW2_1_alt");
+			inputs[2] = gpio_find_by_name("SW2_2_alt");
+			inputs[3] = gpio_find_by_name("SW2_3_alt");
+			dip = !gpio_get_value(inputs[0]);
+			dip += !gpio_get_value(inputs[1]) << 1;
+			dip += !gpio_get_value(inputs[2]) << 2;
+			dip += !gpio_get_value(inputs[3]) << 3;
 			break;
 		case 212:
 		case 221:
@@ -72,10 +77,14 @@ static uint8_t get_dip_switch(uint16_t id, uint32_t rev)
 		case 226:
 		case 227:
 		case 230:
-			dip = !gpio_get_value(82);
-			dip += !gpio_get_value(83) << 1;
-			dip += !gpio_get_value(105) << 2;
-			dip += !gpio_get_value(106) << 3;
+			inputs[0] = gpio_find_by_name("SW2_0");
+			inputs[1] = gpio_find_by_name("SW2_1");
+			inputs[2] = gpio_find_by_name("SW2_2");
+			inputs[3] = gpio_find_by_name("SW2_3");
+			dip = !gpio_get_value(inputs[0]);
+			dip += !gpio_get_value(inputs[1]) << 1;
+			dip += !gpio_get_value(inputs[2]) << 2;
+			dip += !gpio_get_value(inputs[3]) << 3;
 			break;
 	}
 
@@ -85,17 +94,17 @@ static uint8_t get_dip_switch(uint16_t id, uint32_t rev)
 static int baltos_read_eeprom(void)
 {
 	struct bsp_vs_hwparam hw_param;
-	size_t size;
 	char *buf, var_buf[32];
 	int rc;
 	unsigned char mac_addr[6];
 	uint8_t dip;
+	int mpcie_pwr_pin;
 
 	if (!of_machine_is_compatible("vscom,onrisc"))
 		return 0;
 
 	rc = read_file_2("/dev/eeprom0",
-			 &size,
+			 NULL,
 			 (void *)&buf,
 			 sizeof(hw_param));
 	if (rc && rc != -EFBIG)
@@ -137,14 +146,20 @@ static int baltos_read_eeprom(void)
 	globalvar_add_simple("board.id", var_buf);
 
 	/* enable mPCIe slot */
-	gpio_direction_output(100, 1);
+	mpcie_pwr_pin = gpio_find_by_name("3G_PWR_EN");
+	gpio_direction_output(mpcie_pwr_pin, 1);
 
 	/* configure output signals of the external GPIO controller */
 	if (hw_param.SystemId == 210 || hw_param.SystemId == 211) {
-		gpio_direction_output(132, 0);
-		gpio_direction_output(133, 0);
-		gpio_direction_output(134, 0);
-		gpio_direction_output(135, 0);
+		int outs[4];
+		outs[0] = gpio_find_by_name("GP_OUT0");
+		outs[1] = gpio_find_by_name("GP_OUT1");
+		outs[2] = gpio_find_by_name("GP_OUT2");
+		outs[3] = gpio_find_by_name("GP_OUT3");
+		gpio_direction_output(outs[0], 0);
+		gpio_direction_output(outs[1], 0);
+		gpio_direction_output(outs[2], 0);
+		gpio_direction_output(outs[3], 0);
 	}
 
 	dip = get_dip_switch(hw_param.SystemId, hw_param.HwRev);
diff --git a/arch/arm/boards/vscom-baltos/lowlevel.c b/arch/arm/boards/vscom-baltos/lowlevel.c
index 0a220f2628..aee0cde651 100644
--- a/arch/arm/boards/vscom-baltos/lowlevel.c
+++ b/arch/arm/boards/vscom-baltos/lowlevel.c
@@ -1,20 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <linux/sizes.h>
 #include <io.h>
 #include <linux/string.h>
 #include <debug_ll.h>
+#include <mach/omap/debug_ll.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/am33xx-clock.h>
-#include <mach/generic.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/am33xx-mux.h>
-#include <mach/am33xx-generic.h>
-#include <mach/wdt.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/am33xx-clock.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/am33xx-mux.h>
+#include <mach/omap/am33xx-generic.h>
 
 static const struct am33xx_ddr_data ddr3_data = {
 	.rd_slave_ratio0        = 0x38,
@@ -84,13 +86,7 @@ static noinline void baltos_sram_init(void)
 
 	fdt = __dtb_z_am335x_baltos_minimal_start;
 
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
 
 	/* Setup the PLLs and the clocks for the peripherals */
 	am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400);
@@ -102,7 +98,7 @@ static noinline void baltos_sram_init(void)
 
 	am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
 	am33xx_enable_uart0_pin_mux();
-	omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
+	omap_debug_ll_init();
 	putc_ll('>');
 
 	am335x_barebox_entry(fdt);
diff --git a/arch/arm/boards/wago-pfc-am35xx/Makefile b/arch/arm/boards/wago-pfc-am35xx/Makefile
index 7bd3009f31..35ac0462cb 100644
--- a/arch/arm/boards/wago-pfc-am35xx/Makefile
+++ b/arch/arm/boards/wago-pfc-am35xx/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 lwl-y += lowlevel.o
 ifdef CONFIG_OMAP_BUILD_IFT
 obj-y += board-mlo.o
diff --git a/arch/arm/boards/wago-pfc-am35xx/board-mlo.c b/arch/arm/boards/wago-pfc-am35xx/board-mlo.c
index c940565b4a..c5ccdf7faf 100644
--- a/arch/arm/boards/wago-pfc-am35xx/board-mlo.c
+++ b/arch/arm/boards/wago-pfc-am35xx/board-mlo.c
@@ -8,12 +8,12 @@
 #include <init.h>
 #include <io.h>
 #include <linux/sizes.h>
-#include <mach/omap3-silicon.h>
-#include <mach/gpmc.h>
-#include <mach/gpmc_nand.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/gpmc_nand.h>
 #include <errno.h>
-#include <mach/omap3-devices.h>
-#include <mach/generic.h>
+#include <mach/omap/omap3-devices.h>
+#include <mach/omap/generic.h>
 
 /* map first four erase blocks */
 static struct omap_barebox_part pfc200_mlo_part = {
diff --git a/arch/arm/boards/wago-pfc-am35xx/board.c b/arch/arm/boards/wago-pfc-am35xx/board.c
index c0a039ba50..091e606e21 100644
--- a/arch/arm/boards/wago-pfc-am35xx/board.c
+++ b/arch/arm/boards/wago-pfc-am35xx/board.c
@@ -14,7 +14,7 @@
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
 #include <asm/memory.h>
-#include <mach/generic.h>
+#include <mach/omap/generic.h>
 
 static int pfc200_mem_init(void)
 {
diff --git a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
index 7da8fd0331..5429065c2d 100644
--- a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
+++ b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
@@ -10,22 +10,22 @@
 #include <io.h>
 #include <linux/string.h>
 #include <debug_ll.h>
+#include <mach/omap/debug_ll.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/generic.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/wdt.h>
-#include <mach/omap3-mux.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap3-generic.h>
-#include <mach/omap3-clock.h>
-#include <mach/control.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/omap3-mux.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap3-generic.h>
+#include <mach/omap/omap3-clock.h>
+#include <mach/omap/control.h>
 #include <asm/common.h>
 #include <asm-generic/memory_layout.h>
 
-#include <mach/emif4.h>
+#include <mach/omap/emif4.h>
 
 static void mux_config(void)
 {
@@ -185,7 +185,7 @@ static noinline void pfc200_board_init(void)
 
 	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
 		am33xx_uart_soft_reset(IOMEM(OMAP3_UART3_BASE));
-		omap_uart_lowlevel_init(IOMEM(OMAP3_UART3_BASE));
+		omap_debug_ll_init();
 		putc_ll('>');
 	}
 
@@ -200,7 +200,7 @@ static noinline void pfc200_board_init(void)
 
 	/* Dont reconfigure SDRAM while running in SDRAM */
 	if (!in_sdram)
-		am35xx_emif4_init();
+		am35xx_emif4_init(IOMEM(OMAP3_SDRC_BASE));
 
 	barebox_arm_entry(0x80000000, SZ_256M, NULL);
 }
diff --git a/arch/arm/boards/webasto-ccbv2/Makefile b/arch/arm/boards/webasto-ccbv2/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/webasto-ccbv2/Makefile
+++ b/arch/arm/boards/webasto-ccbv2/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/webasto-ccbv2/board.c b/arch/arm/boards/webasto-ccbv2/board.c
index a78258ea6a..6b2c8b8cb0 100644
--- a/arch/arm/boards/webasto-ccbv2/board.c
+++ b/arch/arm/boards/webasto-ccbv2/board.c
@@ -5,14 +5,14 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/generic.h>
-#include <mach/bbu.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/bbu.h>
 #include <of.h>
 #include <string.h>
 
 #include "ccbv2.h"
 
-static int ccbv2_probe(struct device_d *dev)
+static int ccbv2_probe(struct device *dev)
 {
 	struct device_node *overlay;
 	struct fdt_header *fdt;
@@ -22,13 +22,16 @@ static int ccbv2_probe(struct device_d *dev)
 	imx6_bbu_internal_mmcboot_register_handler("emmc", "/dev/mmc1",
 			BBU_HANDLER_FLAG_DEFAULT);
 
-	barebox_set_hostname("weabsto-ccbv2");
+	if (of_machine_is_compatible("webasto,imx6ul-marvel"))
+		barebox_set_hostname("webasto-marvel");
+	else
+		barebox_set_hostname("webasto-ccbv2");
 
 	if(!IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE))
 		return 0;
 
 	fdt = (void*)OPTEE_OVERLAY_LOCATION;
-	overlay = of_unflatten_dtb(fdt);
+	overlay = of_unflatten_dtb(fdt, INT_MAX);
 
 	if (IS_ERR(overlay))
 		return PTR_ERR(overlay);
@@ -48,10 +51,12 @@ err:
 
 static const struct of_device_id ccbv2_of_match[] = {
 	{ .compatible = "webasto,imx6ul-ccbv2" },
+	{ .compatible = "webasto,imx6ul-marvel" },
 	{ /* sentinel */ },
 };
+MODULE_DEVICE_TABLE(of, ccbv2_of_match);
 
-static struct driver_d ccbv2_board_driver = {
+static struct driver ccbv2_board_driver = {
 	.name = "board-imx6ul-ccbv2",
 	.probe = ccbv2_probe,
 	.of_compatible = ccbv2_of_match,
diff --git a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-256.imxcfg
index ea327b2630..ef73ec71db 100644
--- a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg
+++ b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-256.imxcfg
@@ -85,4 +85,4 @@ wm 32 0x021B001C 0x00000000
 /* Disable TZASC bypass */
 wm 32 0x020E4024 0x00000001
 
-#include <mach/habv4-imx6-gencsf.h>
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512.imxcfg b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512.imxcfg
new file mode 100644
index 0000000000..56ca917d10
--- /dev/null
+++ b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512.imxcfg
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+loadaddr 0x80000000
+soc imx6
+ivtofs 0x400
+
+/* Enable all clocks */
+wm 32 0x020c4068 0xffffffff
+wm 32 0x020c406c 0xffffffff
+wm 32 0x020c4070 0xffffffff
+wm 32 0x020c4074 0xffffffff
+wm 32 0x020c4078 0xffffffff
+wm 32 0x020c407c 0xffffffff
+wm 32 0x020c4080 0xffffffff
+
+/* IOMUX */
+/* DDR IO type */
+wm 32 0x020E04B4 0x000C0000
+wm 32 0x020E04AC 0x00000000
+/* Clock */
+wm 32 0x020E027C 0x00000028
+/* Control */
+wm 32 0x020E0250 0x00000028
+wm 32 0x020E024C 0x00000028
+wm 32 0x020E0490 0x00000028
+wm 32 0x020E0288 0x00000028
+wm 32 0x020E0270 0x00000000
+wm 32 0x020E0260 0x00000028
+wm 32 0x020E0264 0x00000028
+wm 32 0x020E04A0 0x00000028
+/* Data strobe */
+wm 32 0x020E0494 0x00020000
+wm 32 0x020E0280 0x00000028
+wm 32 0x020E0284 0x00000028
+/* Data */
+wm 32 0x020E04B0 0x00020000
+wm 32 0x020E0498 0x00000028
+wm 32 0x020E04A4 0x00000028
+wm 32 0x020E0244 0x00000028
+wm 32 0x020E0248 0x00000028
+
+/* DDR Controller registers */
+wm 32 0x021B001C 0x00008000
+wm 32 0x021B0800 0xA1390003
+/* Calibration values */
+wm 32 0x021B080C 0x00090000
+wm 32 0x021B083C 0x01580158
+wm 32 0x021B0848 0x40405050
+wm 32 0x021B0850 0x4040524C
+wm 32 0x021B081C 0x33333333
+wm 32 0x021B0820 0x33333333
+wm 32 0x021B082C 0xf3333333
+wm 32 0x021B0830 0xf3333333
+/* END of calibration values */
+wm 32 0x021B08C0 0x00921012
+wm 32 0x021B08b8 0x00000800
+
+/* MMDC init */
+wm 32 0x021B0004 0x0002002D
+wm 32 0x021B0008 0x1b333030
+wm 32 0x021B000C 0x676B52F3
+wm 32 0x021B0010 0xB66D0B63
+wm 32 0x021B0014 0x01FF00DB
+/* Consider reducing RALAT (currently set to 5) */
+wm 32 0x021B0018 0x00211740
+wm 32 0x021B001C 0x00008000
+wm 32 0x021B002C 0x000026D2
+wm 32 0x021B0030 0x006B1023
+wm 32 0x021B0040 0x0000004F
+wm 32 0x021B0000 0x84180000
+
+/* Mode registers writes for CS0 */
+wm 32 0x021B001C 0x02008032
+wm 32 0x021B001C 0x00008033
+wm 32 0x021B001C 0x00048031
+wm 32 0x021B001C 0x15208030
+wm 32 0x021B001C 0x04008040
+
+/* Final DDR setup */
+wm 32 0x021B0020 0x00007800
+wm 32 0x021B0818 0x00000227
+wm 32 0x021B0004 0x0002556D
+wm 32 0x021B0404 0x00011006
+wm 32 0x021B001C 0x00000000
+
+/* Disable TZASC bypass */
+wm 32 0x020E4024 0x00000001
+
+#include <mach/imx/habv4-imx6-gencsf.h>
diff --git a/arch/arm/boards/webasto-ccbv2/lowlevel.c b/arch/arm/boards/webasto-ccbv2/lowlevel.c
index 8529ea3735..7a198bd801 100644
--- a/arch/arm/boards/webasto-ccbv2/lowlevel.c
+++ b/arch/arm/boards/webasto-ccbv2/lowlevel.c
@@ -5,18 +5,17 @@
 
 #include <common.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <firmware.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm.h>
-#include <mach/esdctl.h>
-#include <mach/iomux-mx6ul.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/iomux-mx6ul.h>
 #include <asm/cache.h>
 #include <tee/optee.h>
 
 #include "ccbv2.h"
 
-extern char __dtb_z_imx6ul_webasto_ccbv2_start[];
-
 static void configure_uart(void)
 {
 	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
@@ -32,7 +31,7 @@ static void configure_uart(void)
 
 }
 
-static void noinline start_ccbv2(u32 r0)
+static void noinline start_ccbv2(u32 r0, unsigned long mem_size, char *fdt)
 {
 	int tee_size;
 	void *tee;
@@ -48,7 +47,7 @@ static void noinline start_ccbv2(u32 r0)
 	 */
 	if(IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE)
 	   && !(r0 > MX6_MMDC_P0_BASE_ADDR
-	        &&  r0 < MX6_MMDC_P0_BASE_ADDR + SZ_256M)) {
+	        &&  r0 < MX6_MMDC_P0_BASE_ADDR + mem_size)) {
 		get_builtin_firmware(ccbv2_optee_bin, &tee, &tee_size);
 
 		memset((void *)OPTEE_OVERLAY_LOCATION, 0, 0x1000);
@@ -56,10 +55,11 @@ static void noinline start_ccbv2(u32 r0)
 		start_optee_early(NULL, tee);
 	}
 
-	imx6ul_barebox_entry(__dtb_z_imx6ul_webasto_ccbv2_start);
+	imx6ul_barebox_entry(fdt);
 }
 
-ENTRY_FUNCTION(start_imx6ul_ccbv2, r0, r1, r2)
+extern char __dtb_z_imx6ul_webasto_ccbv2_start[];
+ENTRY_FUNCTION(start_imx6ul_ccbv2_256m, r0, r1, r2)
 {
 
 	imx6ul_cpu_lowlevel_init();
@@ -70,5 +70,32 @@ ENTRY_FUNCTION(start_imx6ul_ccbv2, r0, r1, r2)
 	setup_c();
 	barrier();
 
-	start_ccbv2(r0);
+	start_ccbv2(r0, SZ_256M, __dtb_z_imx6ul_webasto_ccbv2_start);
+}
+
+ENTRY_FUNCTION(start_imx6ul_ccbv2_512m, r0, r1, r2)
+{
+	imx6ul_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00910000);
+
+	relocate_to_current_adr();
+	setup_c();
+	barrier();
+
+	start_ccbv2(r0, SZ_512M, __dtb_z_imx6ul_webasto_ccbv2_start);
+}
+
+extern char __dtb_z_imx6ul_webasto_marvel_start[];
+ENTRY_FUNCTION(start_imx6ul_marvel, r0, r1, r2)
+{
+	imx6ul_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00910000);
+
+	relocate_to_current_adr();
+	setup_c();
+	barrier();
+
+	start_ccbv2(r0, SZ_512M, __dtb_z_imx6ul_webasto_marvel_start);
 }
diff --git a/arch/arm/boards/xilinx-zcu102/Makefile b/arch/arm/boards/xilinx-zcu102/Makefile
new file mode 100644
index 0000000000..d83a4793aa
--- /dev/null
+++ b/arch/arm/boards/xilinx-zcu102/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/xilinx-zcu102/board.c b/arch/arm/boards/xilinx-zcu102/board.c
new file mode 100644
index 0000000000..3ef668fdff
--- /dev/null
+++ b/arch/arm/boards/xilinx-zcu102/board.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+#include <mach/zynqmp/zynqmp-bbu.h>
+#include <deep-probe.h>
+
+static int zcu102_probe(struct device *dev)
+{
+	return zynqmp_bbu_register_handler("SD", "/boot/BOOT.BIN",
+					   BBU_HANDLER_FLAG_DEFAULT);
+}
+
+static const struct of_device_id zcu102_of_match[] = {
+	{ .compatible = "xlnx,zynqmp-zcu102-revA" },
+	{ .compatible = "xlnx,zynqmp-zcu102-revB" },
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(zcu102_of_match);
+
+static struct driver zcu102_board_driver = {
+	.name = "board-zynqmp-zcu102",
+	.probe = zcu102_probe,
+	.of_compatible = zcu102_of_match,
+};
+coredevice_platform_driver(zcu102_board_driver);
diff --git a/arch/arm/boards/xilinx-zcu102/lowlevel.c b/arch/arm/boards/xilinx-zcu102/lowlevel.c
new file mode 100644
index 0000000000..4b72c0ec43
--- /dev/null
+++ b/arch/arm/boards/xilinx-zcu102/lowlevel.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <debug_ll.h>
+#include <asm/barebox-arm.h>
+
+ENTRY_FUNCTION_WITHSTACK(start_zynqmp_zcu102, 0x80000000, x0, x1, x2)
+{
+	extern char __dtb_z_zynqmp_zcu102_revB_start[];
+
+	/* Assume that the first stage boot loader configured the UART */
+	putc_ll('>');
+
+	barebox_arm_entry(0, SZ_2G, runtime_address(__dtb_z_zynqmp_zcu102_revB_start));
+}
diff --git a/arch/arm/boards/xilinx-zcu104/Makefile b/arch/arm/boards/xilinx-zcu104/Makefile
index 884d6e63b0..297f77d57a 100644
--- a/arch/arm/boards/xilinx-zcu104/Makefile
+++ b/arch/arm/boards/xilinx-zcu104/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
+obj-y += board.o
 lwl-y += lowlevel.o lowlevel_init.o
diff --git a/arch/arm/boards/xilinx-zcu104/board.c b/arch/arm/boards/xilinx-zcu104/board.c
new file mode 100644
index 0000000000..26dc6c9613
--- /dev/null
+++ b/arch/arm/boards/xilinx-zcu104/board.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Michael Tretter <m.tretter@pengutronix.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/zynqmp/zynqmp-bbu.h>
+
+static int zcu104_register_update_handler(void)
+{
+	if (!of_machine_is_compatible("xlnx,zynqmp-zcu104"))
+		return 0;
+
+	return zynqmp_bbu_register_handler("SD", "/boot/BOOT.BIN",
+					   BBU_HANDLER_FLAG_DEFAULT);
+}
+device_initcall(zcu104_register_update_handler);
diff --git a/arch/arm/boards/xilinx-zcu106/Makefile b/arch/arm/boards/xilinx-zcu106/Makefile
new file mode 100644
index 0000000000..297f77d57a
--- /dev/null
+++ b/arch/arm/boards/xilinx-zcu106/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+obj-y += board.o
+lwl-y += lowlevel.o lowlevel_init.o
diff --git a/arch/arm/boards/xilinx-zcu106/board.c b/arch/arm/boards/xilinx-zcu106/board.c
new file mode 100644
index 0000000000..3c8c3d21f2
--- /dev/null
+++ b/arch/arm/boards/xilinx-zcu106/board.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021, WolfVision GmbH
+ * Author: Michael Riesch <michael.riesch@wolfvision.net>
+ *
+ * Based on the barebox ZCU104 board support code.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/zynqmp/zynqmp-bbu.h>
+
+static int zcu106_register_update_handler(void)
+{
+	if (!of_machine_is_compatible("xlnx,zynqmp-zcu106"))
+		return 0;
+
+	return zynqmp_bbu_register_handler("SD", "/boot/BOOT.BIN",
+					   BBU_HANDLER_FLAG_DEFAULT);
+}
+device_initcall(zcu106_register_update_handler);
diff --git a/arch/arm/boards/xilinx-zcu106/lowlevel.c b/arch/arm/boards/xilinx-zcu106/lowlevel.c
new file mode 100644
index 0000000000..ccc8d61418
--- /dev/null
+++ b/arch/arm/boards/xilinx-zcu106/lowlevel.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, WolfVision GmbH
+ * Author: Michael Riesch <michael.riesch@wolfvision.net>
+ *
+ * Based on the barebox ZCU104 board support code.
+ */
+
+#include <common.h>
+#include <debug_ll.h>
+#include <asm/barebox-arm.h>
+
+extern char __dtb_zynqmp_zcu106_revA_start[];
+
+void zynqmp_zcu106_start(uint32_t, uint32_t, uint32_t);
+
+void noinline zynqmp_zcu106_start(uint32_t r0, uint32_t r1, uint32_t r2)
+{
+	/* Assume that the first stage boot loader configured the UART */
+	putc_ll('>');
+
+	barebox_arm_entry(0, SZ_2G,
+			  __dtb_zynqmp_zcu106_revA_start + global_variable_offset());
+}
diff --git a/arch/arm/boards/xilinx-zcu106/lowlevel_init.S b/arch/arm/boards/xilinx-zcu106/lowlevel_init.S
new file mode 100644
index 0000000000..f3d55dcef2
--- /dev/null
+++ b/arch/arm/boards/xilinx-zcu106/lowlevel_init.S
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/linkage.h>
+#include <asm/barebox-arm64.h>
+
+/* The DRAM is already setup */
+#define STACK_TOP 0x80000000
+
+ENTRY_PROC(start_zynqmp_zcu106)
+	mov x0, #STACK_TOP
+	mov sp, x0
+	b zynqmp_zcu106_start
+ENTRY_PROC_END(start_zynqmp_zcu106)
diff --git a/arch/arm/boards/zii-common/Makefile b/arch/arm/boards/zii-common/Makefile
index 90bdf21e77..7488148cff 100644
--- a/arch/arm/boards/zii-common/Makefile
+++ b/arch/arm/boards/zii-common/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o switch-cmd.o pn-fixup.o
 bbenv-y += defaultenv-zii-common
diff --git a/arch/arm/boards/zii-common/board.c b/arch/arm/boards/zii-common/board.c
index 5d81bd51e9..96f9243591 100644
--- a/arch/arm/boards/zii-common/board.c
+++ b/arch/arm/boards/zii-common/board.c
@@ -68,7 +68,7 @@ late_initcall(rdu_ethernet_init);
 static int rdu_networkconfig(void)
 {
 	static char *rdu_netconfig;
-	struct device_d *sp_dev;
+	struct device *sp_dev;
 
 	if (!of_machine_is_compatible("zii,imx8mq-ultra") &&
 	    !of_machine_is_compatible("zii,imx6q-zii-rdu2") &&
diff --git a/arch/arm/boards/zii-common/pn-fixup.c b/arch/arm/boards/zii-common/pn-fixup.c
index 80785285b7..3c69f1a022 100644
--- a/arch/arm/boards/zii-common/pn-fixup.c
+++ b/arch/arm/boards/zii-common/pn-fixup.c
@@ -11,7 +11,7 @@ char *zii_read_part_number(const char *cell_name, size_t cell_size)
 {
 	struct device_node *np;
 
-	np = of_find_node_by_name(NULL, "device-info");
+	np = of_find_node_by_name_address(NULL, "device-info");
 	if (!np) {
 		pr_warn("No device information found\n");
 		return ERR_PTR(-ENOENT);
diff --git a/arch/arm/boards/zii-common/switch-cmd.c b/arch/arm/boards/zii-common/switch-cmd.c
index df6ed66b23..6aa1c391f4 100644
--- a/arch/arm/boards/zii-common/switch-cmd.c
+++ b/arch/arm/boards/zii-common/switch-cmd.c
@@ -61,7 +61,7 @@ static int do_rdu2_switch_reset(void)
 
 static int do_rdu1_switch_reset(void)
 {
-	struct device_d *sp_dev = get_device_by_name("sp");
+	struct device *sp_dev = get_device_by_name("sp");
 	struct rave_sp *sp = sp_dev->parent->priv;
 	u8 cmd[] = {
 		[0] = RAVE_SP_CMD_RESET_ETH_SWITCH,
diff --git a/arch/arm/boards/zii-imx51-rdu1/Makefile b/arch/arm/boards/zii-imx51-rdu1/Makefile
index 7f2569bda3..96663f9ae8 100644
--- a/arch/arm/boards/zii-imx51-rdu1/Makefile
+++ b/arch/arm/boards/zii-imx51-rdu1/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-rdu1
diff --git a/arch/arm/boards/zii-imx51-rdu1/board.c b/arch/arm/boards/zii-imx51-rdu1/board.c
index 8fdcb76260..b72219b4bc 100644
--- a/arch/arm/boards/zii-imx51-rdu1/board.c
+++ b/arch/arm/boards/zii-imx51-rdu1/board.c
@@ -19,16 +19,14 @@
 #include <envfs.h>
 #include <init.h>
 #include <environment.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include <libfile.h>
-#include <mach/imx5.h>
+#include <mach/imx/imx5.h>
 #include <net.h>
 #include <linux/crc8.h>
 #include <linux/sizes.h>
 #include <linux/nvmem-consumer.h>
 
-#include <envfs.h>
-
 static int zii_rdu1_init(void)
 {
 	const char *hostname;
@@ -99,7 +97,7 @@ static int zii_rdu1_load_config(void)
 			file = "shadow copy in RAVE SP EEPROM";
 
 			root = of_get_root_node();
-			np   = of_find_node_by_name(root, "eeprom@a4");
+			np   = of_find_node_by_name_address(root, "eeprom@a4");
 			if (!np)
 				return -ENODEV;
 
diff --git a/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg b/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg
index 5674e7a6e1..6d40976b83 100644
--- a/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg
+++ b/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx51
 loadaddr 0x90000000
 ivtofs 0x400
diff --git a/arch/arm/boards/zii-imx51-rdu1/lowlevel.c b/arch/arm/boards/zii-imx51-rdu1/lowlevel.c
index c7bb044e0d..2418fe69ae 100644
--- a/arch/arm/boards/zii-imx51-rdu1/lowlevel.c
+++ b/arch/arm/boards/zii-imx51-rdu1/lowlevel.c
@@ -1,9 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <debug_ll.h>
-#include <mach/clock-imx51_53.h>
-#include <mach/iomux-mx51.h>
+#include <mach/imx/debug_ll.h>
+#include <mach/imx/clock-imx51_53.h>
+#include <mach/imx/iomux-mx51.h>
 #include <common.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 
diff --git a/arch/arm/boards/zii-imx6q-rdu2/Makefile b/arch/arm/boards/zii-imx6q-rdu2/Makefile
index c6285362f2..31b592bd36 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/Makefile
+++ b/arch/arm/boards/zii-imx6q-rdu2/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-rdu2
diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c
index b915a05dd2..88912a5108 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/board.c
+++ b/arch/arm/boards/zii-imx6q-rdu2/board.c
@@ -9,8 +9,8 @@
 #include <gpio.h>
 #include <i2c/i2c.h>
 #include <init.h>
-#include <mach/bbu.h>
-#include <mach/imx6.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/imx6.h>
 #include <net.h>
 #include <linux/nvmem-consumer.h>
 #include "../zii-common/pn-fixup.h"
@@ -199,19 +199,19 @@ static int rdu2_fixup_dsa(struct device_node *root, void *context)
 	if (!switch_np)
 		return -ENODEV;
 
-	np = of_find_node_by_name(switch_np, "port@2");
+	np = of_find_node_by_name_address(switch_np, "port@2");
 	if (!np)
 		return -ENODEV;
 
 	of_delete_node(np);
 
-	np = of_find_node_by_name(root, "i210@0");
+	np = of_find_node_by_name_address(root, "i210@0");
 	if (!np)
 		return -ENODEV;
 
 	i210_handle = of_node_create_phandle(np);
 
-	np = of_find_node_by_name(switch_np, "port@0");
+	np = of_find_node_by_name_address(switch_np, "port@0");
 	if (!np)
 		return -ENODEV;
 
@@ -265,7 +265,7 @@ static int rdu2_fixup_lvds(struct device_node *root,
 	/*
 	 * LVDS panels need the correct timings
 	 */
-	np = of_find_node_by_name(root, "panel");
+	np = of_find_node_by_name_address(root, "panel");
 	if (!np)
 		return -ENODEV;
 
@@ -280,7 +280,7 @@ static int rdu2_fixup_lvds(struct device_node *root,
 		 * Delete all mode entries, which aren't suited for the
 		 * current display
 		 */
-		np = of_find_node_by_name(np, "display-timings");
+		np = of_find_node_by_name_address(np, "display-timings");
 		if (!np)
 			return -ENODEV;
 
@@ -305,7 +305,7 @@ static int rdu2_fixup_lvds(struct device_node *root,
 	if (fixup->type == IT_DUAL_LVDS)
 		of_set_property(np, "fsl,dual-channel", NULL, 0, 1);
 
-	np = of_find_node_by_name(np, "lvds-channel@0");
+	np = of_find_node_by_name_address(np, "lvds-channel@0");
 	if (!np)
 		return -ENODEV;
 
diff --git a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg
index fcfef9c234..0b37ab248f 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg
+++ b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx6
 loadaddr 0x00907000
 max_load_size 0x31000
diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
index a80ce0afc5..5c94b120d3 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
+++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
@@ -4,12 +4,13 @@
 /* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */
 
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <common.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
-#include <mach/imx6.h>
-#include <mach/xload.h>
-#include <mach/iomux-mx6.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/iomux-mx6.h>
 #include <asm/barebox-arm.h>
 
 struct reginit {
diff --git a/arch/arm/boards/zii-imx7d-dev/Makefile b/arch/arm/boards/zii-imx7d-dev/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/zii-imx7d-dev/Makefile
+++ b/arch/arm/boards/zii-imx7d-dev/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/zii-imx7d-dev/board.c b/arch/arm/boards/zii-imx7d-dev/board.c
index 5f7314b0b8..2d7b589908 100644
--- a/arch/arm/boards/zii-imx7d-dev/board.c
+++ b/arch/arm/boards/zii-imx7d-dev/board.c
@@ -9,11 +9,11 @@
 #include <init.h>
 #include <io.h>
 #include <gpio.h>
-#include <mach/imx7-regs.h>
+#include <mach/imx/imx7-regs.h>
 #include <mfd/imx7-iomuxc-gpr.h>
 #include <environment.h>
 #include <envfs.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
 static void zii_imx7d_rpu2_init_fec(void)
 {
diff --git a/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg
index 022f9711b2..053680f76d 100644
--- a/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg
+++ b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg
@@ -1,6 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc imx7
 loadaddr 0x80000000
 ivtofs 0x400
 
-#include <mach/flash-header/imx7d-ddr-sabresd.imxcfg>
+#include <mach/imx/flash-header/imx7d-ddr-sabresd.imxcfg>
 
diff --git a/arch/arm/boards/zii-imx7d-dev/lowlevel.c b/arch/arm/boards/zii-imx7d-dev/lowlevel.c
index 7579a2a8a0..2b2ad6aa84 100644
--- a/arch/arm/boards/zii-imx7d-dev/lowlevel.c
+++ b/arch/arm/boards/zii-imx7d-dev/lowlevel.c
@@ -9,21 +9,22 @@
 #include <io.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx7-ccm-regs.h>
-#include <mach/iomux-mx7.h>
-#include <mach/debug_ll.h>
+#include <mach/imx/imx7-ccm-regs.h>
+#include <mach/imx/iomux-mx7.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
-#include <mach/esdctl.h>
+#include <mach/imx/esdctl.h>
 
 extern char __dtb_z_imx7d_zii_rpu2_start[];
 extern char __dtb_z_imx7d_zii_rmu2_start[];
 
 static inline void setup_uart(void)
 {
-	imx7_early_setup_uart_clock();
+	/* FIXME: Below UART2 is muxed, not UART1 */
+	imx7_early_setup_uart_clock(1);
 
 	imx7_setup_pad(MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX);
 
diff --git a/arch/arm/boards/zii-imx8mq-dev/Makefile b/arch/arm/boards/zii-imx8mq-dev/Makefile
index d0148b5067..8894e40b5a 100644
--- a/arch/arm/boards/zii-imx8mq-dev/Makefile
+++ b/arch/arm/boards/zii-imx8mq-dev/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o ddr_init.o ddrphy_train.o
 bbenv-y += defaultenv-imx8mq-zii-dev
diff --git a/arch/arm/boards/zii-imx8mq-dev/board.c b/arch/arm/boards/zii-imx8mq-dev/board.c
index 4ad09663ac..3581c7251d 100644
--- a/arch/arm/boards/zii-imx8mq-dev/board.c
+++ b/arch/arm/boards/zii-imx8mq-dev/board.c
@@ -10,7 +10,7 @@
 #include <init.h>
 #include <asm/memory.h>
 #include <linux/sizes.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 #include "../zii-common/pn-fixup.h"
 
 #define LRU_FLAG_EGALAX		BIT(0)
@@ -81,7 +81,7 @@ static int zii_imx8mq_dev_fixup_egalax_ts(struct device_node *root, void *ctx)
 static int zii_imx8mq_dev_fixup_deb_internal(void)
 {
 	struct device_node *np, *aliases;
-	struct device_d *dev;
+	struct device *dev;
 
 	/*
 	 * In the internal DT remove the complete FEC hierarchy and move the
@@ -106,7 +106,7 @@ static int zii_imx8mq_dev_fixup_deb_internal(void)
 
 	unregister_device(dev);
 
-	np = of_find_node_by_name(NULL, "i210@0");
+	np = of_find_node_by_name_address(NULL, "i210@0");
 	if (!np)
 		return -ENODEV;
 
diff --git a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c
index 7a955193fd..2d4133fb13 100644
--- a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c
+++ b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c
@@ -81,6 +81,7 @@ void ddr_init(void)
 	reg32_write(0x3d400200,0x17);
 	reg32_write(0x3d40020c,0x0);
 	reg32_write(0x3d400210,0x1f1f);
+	reg32_write(0x3d40021c,0xf0f);
 	reg32_write(0x3d400204,0x80808);
 	reg32_write(0x3d400214,0x7070707);
 	reg32_write(0x3d400218,0x7070707);
@@ -177,7 +178,7 @@ void ddr_init(void)
 	reg32_write(DDRC_SWCTL(0), 0x0000);
 	/*
 	 * ------------------- 9 -------------------
-	 * Set DFIMISC.dfi_init_start to 1 
+	 * Set DFIMISC.dfi_init_start to 1
 	 *  -----------------------------------------
 	 */
 	reg32_write(DDRC_DFIMISC(0), 0x00000030);
@@ -222,4 +223,4 @@ void ddr_init(void)
 	/* enable DDR auto-refresh mode */
 	tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
 	reg32_write(DDRC_RFSHCTL3(0), tmp);
-}
\ No newline at end of file
+}
diff --git a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
index 1b30ff7257..bac7d0a517 100644
--- a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
+++ b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
@@ -11,6 +11,8 @@
 void ddr_cfg_phy(void) {
 	unsigned int tmp, tmp_t;
 
+	ddr_get_firmware(DRAM_TYPE_LPDDR4);
+
 	//Init DDRPHY register...
 	reg32_write(0x3c080440,0x2);
 	reg32_write(0x3c080444,0x3);
@@ -142,7 +144,7 @@ void ddr_cfg_phy(void) {
 	//enable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	//load the 1D training image
-	ddr_load_train_code(FW_1D_IMAGE);
+	imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE);
 
 	//configure DDRPHY-FW DMEM structure @clock0...
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
@@ -187,7 +189,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
+	imx8m_wait_ddrphy_training_complete();
 
 	//configure DDRPHY-FW DMEM structure @clock1...
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
@@ -256,7 +258,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
+	imx8m_wait_ddrphy_training_complete();
 
 	//set the PHY input clock to the desired frequency for pstate 0
 	reg32_write(0x3038a088,0x7070000);
@@ -289,7 +291,7 @@ void ddr_cfg_phy(void) {
 	//enable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
 	//load the 2D training image
-	ddr_load_train_code(FW_2D_IMAGE);
+	imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE);
 
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11);
@@ -330,7 +332,7 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
-	wait_ddrphy_training_complete();
+	imx8m_wait_ddrphy_training_complete();
 
 	//Halt MPU
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
@@ -932,4 +934,4 @@ void ddr_cfg_phy(void) {
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0);
 	//disable APB bus to access DDRPHY RAM
 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
-}
\ No newline at end of file
+}
diff --git a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg
index 8921f32110..f82759f849 100644
--- a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg
+++ b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg
@@ -1,5 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 soc imx8mq
 
 loadaddr 0x007E1000
 max_load_size 0x3F000
 ivtofs 0x400
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
index 311e61fb1d..4184748cd8 100644
--- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
+++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
@@ -7,20 +7,21 @@
 #include <common.h>
 #include <firmware.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx8m-ccm-regs.h>
-#include <mach/iomux-mx8mq.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/iomux-mx8mq.h>
 #include <soc/imx8m/ddr.h>
-#include <mach/xload.h>
+#include <mach/imx/xload.h>
 #include <io.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
 #include <asm/sections.h>
 #include <asm/mmu.h>
-#include <mach/atf.h>
-#include <mach/esdctl.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/esdctl.h>
 
 #include "ddr.h"
 
@@ -62,21 +63,10 @@ static __noreturn void ddr_helper_halt(void)
 
 static void zii_imx8mq_dev_sram_setup(void)
 {
-	enum bootsource src = BOOTSOURCE_UNKNOWN;
-	int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
-	int ret = -ENOTSUPP;
-
 	ddr_init();
 
 	if (running_as_ddr_helper())
 		ddr_helper_halt();
-
-	imx8mq_get_boot_source(&src, &instance);
-
-	if (src == BOOTSOURCE_MMC)
-		ret = imx8m_esdhc_load_image(instance, true);
-
-	BUG_ON(ret);
 }
 
 enum zii_platform_imx8mq_type {
@@ -140,13 +130,8 @@ static __noreturn noinline void zii_imx8mq_dev_start(void)
 	 * initialization routine, it is EL2 which means we'll skip
 	 * loadting ATF blob again
 	 */
-	if (current_el() == 3) {
-		const u8 *bl31;
-		size_t bl31_size;
-
-		get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size);
-		imx8mq_atf_load_bl31(bl31, bl31_size);
-	}
+	if (current_el() == 3)
+		imx8mq_load_and_start_image_via_tfa();
 
 	system_type = get_system_type();
 
@@ -189,7 +174,7 @@ static __noreturn noinline void zii_imx8mq_dev_start(void)
  *
  * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
  *
- * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
+ * 5. BL31 exits EL3 into EL2 at address MX8M_ATF_BL33_BASE_ADDR,
  *    executing start_nxp_imx8mq_evk() the third time
  *
  * 6. Standard barebox boot flow continues
diff --git a/arch/arm/boards/zii-vf610-dev/Makefile b/arch/arm/boards/zii-vf610-dev/Makefile
index 1297d815e3..a1a8318e15 100644
--- a/arch/arm/boards/zii-vf610-dev/Makefile
+++ b/arch/arm/boards/zii-vf610-dev/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
 bbenv-y += defaultenv-zii-vf610-dev
diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c
index 3a3ba2d58c..675f13b882 100644
--- a/arch/arm/boards/zii-vf610-dev/board.c
+++ b/arch/arm/boards/zii-vf610-dev/board.c
@@ -10,7 +10,7 @@
 #include <linux/clk.h>
 #include <dt-bindings/clock/vf610-clock.h>
 #include <envfs.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
 
 
 static int expose_signals(const struct gpio *signals,
diff --git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
index 4b73da4c19..aace9e9226 100644
--- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
+++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
@@ -1,13 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 soc vf610
 loadaddr 0x80000000
 ivtofs 0x400
 
-#include <mach/vf610-iomux-regs.h>
-#include <mach/vf610-ddrmc-regs.h>
+#include <mach/imx/vf610-iomux-regs.h>
+#include <mach/imx/vf610-ddrmc-regs.h>
 
-#include <mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg>
-#include <mach/flash-header/vf610-iomux-ddr-default.imxcfg>
-#include <mach/flash-header/vf610-ddr-cr-default.imxcfg>
+#include <mach/imx/flash-header/vf610-ddr-pll2-400mhz.imxcfg>
+#include <mach/imx/flash-header/vf610-iomux-ddr-default.imxcfg>
+#include <mach/imx/flash-header/vf610-ddr-cr-default.imxcfg>
 
 wm 32 DDRMC_CR26 0x0c300068
 wm 32 DDRMC_CR31 0x006c0200
@@ -19,7 +21,7 @@ wm 32 DDRMC_CR73 0x0a010100
  */
 wm 32 DDRMC_CR73 0x0a010100
 
-#include <mach/flash-header/vf610-ddr-phy-default.imxcfg>
+#include <mach/imx/flash-header/vf610-ddr-phy-default.imxcfg>
 
 wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3_START
 
diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c
index a05515db16..e45e31f7d8 100644
--- a/arch/arm/boards/zii-vf610-dev/lowlevel.c
+++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c
@@ -5,14 +5,15 @@
 
 #include <common.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/esdctl.h>
-#include <mach/vf610-regs.h>
-#include <mach/clock-vf610.h>
-#include <mach/iomux-vf610.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/vf610-regs.h>
+#include <mach/imx/clock-vf610.h>
+#include <mach/imx/iomux-vf610.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 
 static inline void setup_uart(void)
 {
diff --git a/arch/arm/boards/zylonite/Makefile b/arch/arm/boards/zylonite/Makefile
index 01c7a259e9..da63d2625f 100644
--- a/arch/arm/boards/zylonite/Makefile
+++ b/arch/arm/boards/zylonite/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += board.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/boards/zylonite/board.c b/arch/arm/boards/zylonite/board.c
index eb69b37549..04cb34754c 100644
--- a/arch/arm/boards/zylonite/board.c
+++ b/arch/arm/boards/zylonite/board.c
@@ -8,7 +8,6 @@
 #include <fs.h>
 #include <gpio.h>
 #include <init.h>
-#include <partition.h>
 #include <led.h>
 #include <platform_data/eth-smc91111.h>
 #include <platform_data/mtd-nand-mrvl.h>
@@ -17,14 +16,14 @@
 #include <linux/clkdev.h>
 #include <linux/sizes.h>
 
-#include <mach/devices.h>
-#include <mach/mfp-pxa3xx.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa/devices.h>
+#include <mach/pxa/mfp-pxa3xx.h>
+#include <mach/pxa/pxa-regs.h>
 
 #include <asm/armlinux.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 
 static struct smc91c111_pdata smsc91x_pdata;
 static struct mrvl_nand_platform_data nand_pdata = {
diff --git a/arch/arm/boards/zylonite/lowlevel.c b/arch/arm/boards/zylonite/lowlevel.c
index 5b95d879fa..972fd34761 100644
--- a/arch/arm/boards/zylonite/lowlevel.c
+++ b/arch/arm/boards/zylonite/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/sizes.h>
 #include <asm/barebox-arm-head.h>
diff --git a/arch/arm/configs/a9m2410_defconfig b/arch/arm/configs/a9m2410_defconfig
deleted file mode 100644
index ea70a121af..0000000000
--- a/arch/arm/configs/a9m2410_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_ARCH_S3C24xx=y
-CONFIG_S3C_NAND_BOOT=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_BAUDRATE=38400
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/a9m2410/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_FLASH=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_SMC91111=y
-# CONFIG_SPI is not set
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/a9m2440_defconfig b/arch/arm/configs/a9m2440_defconfig
deleted file mode 100644
index 5843d29d7f..0000000000
--- a/arch/arm/configs/a9m2440_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_ARCH_S3C24xx=y
-CONFIG_MACH_A9M2440=y
-CONFIG_S3C_SDRAM_INIT=y
-CONFIG_S3C_NAND_BOOT=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_BAUDRATE=38400
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/a9m2440/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_FLASH=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_SMC91111=y
-# CONFIG_SPI is not set
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/am335x_mlo_defconfig b/arch/arm/configs/am335x_mlo_defconfig
index 51d238db3e..1ceb996187 100644
--- a/arch/arm/configs/am335x_mlo_defconfig
+++ b/arch/arm/configs/am335x_mlo_defconfig
@@ -1,15 +1,16 @@
-CONFIG_ARCH_OMAP=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x1b400
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_OMAP_SERIALBOOT=y
 CONFIG_OMAP_MULTI_BOARDS=y
 CONFIG_MACH_AFI_GF=y
 CONFIG_MACH_BEAGLEBONE=y
+CONFIG_MACH_MYIRTECH_X335X=y
 CONFIG_MACH_PHYTEC_SOM_AM335X=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_MEMINFO is not set
 CONFIG_IMAGE_COMPRESSION_XZKERN=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x1b400
 CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_RELOCATABLE=y
@@ -20,7 +21,6 @@ CONFIG_SHELL_NONE=y
 CONFIG_CONSOLE_ACTIVATE_NONE=y
 CONFIG_OFDEVICE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_DRIVER_SPI_OMAP3=y
 CONFIG_MTD=y
 # CONFIG_MTD_WRITE is not set
diff --git a/arch/arm/configs/am35xx_pfc200_xload_defconfig b/arch/arm/configs/am35xx_pfc200_xload_defconfig
index da55382f05..a69d4c9fbc 100644
--- a/arch/arm/configs/am35xx_pfc200_xload_defconfig
+++ b/arch/arm/configs/am35xx_pfc200_xload_defconfig
@@ -1,4 +1,4 @@
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_OMAP_MULTI_BOARDS=y
 CONFIG_MACH_WAGO_PFC_AM35XX=y
@@ -6,7 +6,6 @@ CONFIG_THUMB2_BAREBOX=y
 # CONFIG_ARM_EXCEPTIONS is not set
 # CONFIG_MEMINFO is not set
 CONFIG_MMU=y
-# CONFIG_MMU_EARLY is not set
 CONFIG_STACK_SIZE=0xc00
 CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_DUMMY=y
@@ -17,17 +16,11 @@ CONFIG_SHELL_NONE=y
 # CONFIG_TIMESTAMP is not set
 CONFIG_CONSOLE_SIMPLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
 # CONFIG_MTD_WRITE is not set
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-# CONFIG_NAND_INFO is not set
-# CONFIG_NAND_BBT is not set
 CONFIG_NAND_OMAP_GPMC=y
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
diff --git a/arch/arm/configs/animeo_ip_defconfig b/arch/arm/configs/animeo_ip_defconfig
index 96f73eba2b..930f19ddb5 100644
--- a/arch/arm/configs/animeo_ip_defconfig
+++ b/arch/arm/configs/animeo_ip_defconfig
@@ -1,14 +1,13 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9260=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="Animeo-IP:"
 CONFIG_BAUDRATE=38400
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -57,9 +56,6 @@ CONFIG_NET_USB_ASIX=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_HOST=y
 CONFIG_MCI=y
diff --git a/arch/arm/configs/archosg9_defconfig b/arch/arm/configs/archosg9_defconfig
index aafd849185..288d4bda52 100644
--- a/arch/arm/configs/archosg9_defconfig
+++ b/arch/arm/configs/archosg9_defconfig
@@ -1,5 +1,5 @@
 CONFIG_TEXT_BASE=0x8f000000
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_OMAP4_USBBOOT=y
 CONFIG_MACH_ARCHOSG9=y
 CONFIG_THUMB2_BAREBOX=y
@@ -67,7 +67,6 @@ CONFIG_CMD_TIME=y
 CONFIG_NET=y
 CONFIG_NET_NETCONSOLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT=y
 CONFIG_NET_USB=y
 CONFIG_NET_USB_SMSC95XX=y
diff --git a/arch/arm/configs/archosg9_xload_defconfig b/arch/arm/configs/archosg9_xload_defconfig
index 27f471cf0b..fd475d65ca 100644
--- a/arch/arm/configs/archosg9_xload_defconfig
+++ b/arch/arm/configs/archosg9_xload_defconfig
@@ -1,6 +1,5 @@
 CONFIG_TEXT_BASE=0x40300000
-CONFIG_ARCH_OMAP=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xC000
+CONFIG_ARCH_OMAP_SINGLE=y
 # CONFIG_OMAP_GPMC is not set
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_OMAP4_USBBOOT=y
@@ -8,13 +7,13 @@ CONFIG_MACH_ARCHOSG9=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_BANNER is not set
 # CONFIG_MEMINFO is not set
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xC000
 CONFIG_MALLOC_SIZE=0x2000000
 CONFIG_SHELL_NONE=y
 # CONFIG_ERRNO_MESSAGES is not set
 # CONFIG_TIMESTAMP is not set
 CONFIG_CONSOLE_SIMPLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT=y
 # CONFIG_SPI is not set
 CONFIG_MCI=y
diff --git a/arch/arm/configs/at91_multi_defconfig b/arch/arm/configs/at91_multi_defconfig
index f0a4812f0c..01e4526329 100644
--- a/arch/arm/configs/at91_multi_defconfig
+++ b/arch/arm/configs/at91_multi_defconfig
@@ -1,10 +1,15 @@
+CONFIG_ARCH_AT91=y
 CONFIG_AT91_MULTI_BOARDS=y
+CONFIG_MACH_CALAO=y
 CONFIG_MACH_SKOV_ARM9CPU=y
 CONFIG_MACH_AT91SAM9263EK=y
 CONFIG_MACH_AT91SAM9X5EK=y
 CONFIG_MACH_MICROCHIP_KSZ9477_EVB=y
+CONFIG_MACH_MICROCHIP_SAMA5D3_EDS=y
+CONFIG_MACH_SAMA5D3_XPLAINED=y
 CONFIG_MACH_SAMA5D27_SOM1=y
 CONFIG_MACH_SAMA5D27_GIANTBOARD=y
+CONFIG_MACH_SAMA5D4_WIFX=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
@@ -94,8 +99,7 @@ CONFIG_I2C=y
 CONFIG_I2C_AT91=y
 CONFIG_MTD=y
 CONFIG_NAND=y
-CONFIG_NAND_ECC_BCH=y
-CONFIG_NAND_ECC_HW_OOB_FIRST=y
+CONFIG_MTD_NAND_ECC_SOFT=y
 CONFIG_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_FASTMAP=y
@@ -113,10 +117,8 @@ CONFIG_DRIVER_VIDEO_SIMPLE_PANEL=y
 CONFIG_MCI=y
 CONFIG_MCI_MMC_BOOT_PARTITIONS=y
 CONFIG_MCI_MMC_GPP_PARTITIONS=y
-CONFIG_MCI_ATMEL=y
 CONFIG_MCI_ATMEL_SDHCI=y
 CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_STATE_DRV=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_LED_GPIO_OF=y
@@ -130,6 +132,7 @@ CONFIG_KEYBOARD_QT1070=y
 CONFIG_KEYBOARD_USB=y
 CONFIG_INPUT_SPECIALKEYS=y
 CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_POLLER=y
 CONFIG_WATCHDOG_AT91SAM9=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED=y
@@ -140,6 +143,5 @@ CONFIG_FS_EXT4=y
 CONFIG_FS_TFTP=y
 CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
-CONFIG_FS_FAT_LFN=y
 CONFIG_FS_UBIFS=y
 CONFIG_FS_UBIFS_COMPRESSION_LZO=y
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 3e8d263a24..aa91c0cda6 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -1,10 +1,10 @@
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
+CONFIG_ARCH_AT91=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="9200-EK:"
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
index 3cc92d8fd1..b4a291ed57 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -1,13 +1,12 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_AT91SAM9260EK=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_PROMPT="9260-EK:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -51,9 +50,6 @@ CONFIG_DRIVER_NET_MACB=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/at91sam9261ek_bootstrap_defconfig b/arch/arm/configs/at91sam9261ek_bootstrap_defconfig
index 3de1d78c6f..3811594b1a 100644
--- a/arch/arm/configs/at91sam9261ek_bootstrap_defconfig
+++ b/arch/arm/configs/at91sam9261ek_bootstrap_defconfig
@@ -1,10 +1,10 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9261=y
 CONFIG_AT91_BOOTSTRAP=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x27000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x27000
 CONFIG_MALLOC_DUMMY=y
 CONFIG_PROMPT="9261-EK:"
 CONFIG_SHELL_NONE=y
@@ -15,9 +15,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_WRITE is not set
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 # CONFIG_FS_RAMFS is not set
 CONFIG_BOOTSTRAP_DEVFS=y
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
index d6f547aae5..cf8c74de9e 100644
--- a/arch/arm/configs/at91sam9261ek_defconfig
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -1,13 +1,12 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9261=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="9261-EK:"
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
@@ -54,9 +53,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_MTD_DATAFLASH=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/at91sam9261ek_first_stage_defconfig b/arch/arm/configs/at91sam9261ek_first_stage_defconfig
index e4c9f1d2c9..8e6065de34 100644
--- a/arch/arm/configs/at91sam9261ek_first_stage_defconfig
+++ b/arch/arm/configs/at91sam9261ek_first_stage_defconfig
@@ -1,14 +1,13 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9261=y
 CONFIG_AT91_LOAD_BAREBOX_SRAM=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x27000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x27000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="9261-EK:"
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
@@ -55,9 +54,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_MTD_DATAFLASH=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/at91sam9g10ek_defconfig b/arch/arm/configs/at91sam9g10ek_defconfig
index 17713cdb82..4672efdc57 100644
--- a/arch/arm/configs/at91sam9g10ek_defconfig
+++ b/arch/arm/configs/at91sam9g10ek_defconfig
@@ -1,13 +1,12 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G10=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="9G10-EK:"
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
@@ -52,9 +51,6 @@ CONFIG_DRIVER_NET_DM9K=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
index 6791be2d09..b102d26414 100644
--- a/arch/arm/configs/at91sam9g20ek_defconfig
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -1,13 +1,12 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_AT91_HAVE_2MMC=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_PROMPT="9G20-EK:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -51,9 +50,6 @@ CONFIG_DRIVER_NET_MACB=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/at91sam9m10g45ek_defconfig b/arch/arm/configs/at91sam9m10g45ek_defconfig
index c38df8fa81..9cc66d4e77 100644
--- a/arch/arm/configs/at91sam9m10g45ek_defconfig
+++ b/arch/arm/configs/at91sam9m10g45ek_defconfig
@@ -1,14 +1,13 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G45=y
 CONFIG_MACH_AT91SAM9M10G45EK=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_MALLOC_SIZE=0x800000
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="9M10G45-EK:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2=">"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -66,9 +65,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_MTD_DATAFLASH=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_HOST=y
 CONFIG_USB_EHCI=y
diff --git a/arch/arm/configs/at91sam9m10ihd_defconfig b/arch/arm/configs/at91sam9m10ihd_defconfig
index 490472f889..6428274318 100644
--- a/arch/arm/configs/at91sam9m10ihd_defconfig
+++ b/arch/arm/configs/at91sam9m10ihd_defconfig
@@ -1,9 +1,9 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G45=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_MALLOC_SIZE=0xa00000
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="9M10IHD:"
@@ -67,9 +67,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_MTD_M25P80=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_HOST=y
 CONFIG_USB_EHCI=y
diff --git a/arch/arm/configs/at91sam9n12ek_defconfig b/arch/arm/configs/at91sam9n12ek_defconfig
index b7c3a4b1f4..813934a116 100644
--- a/arch/arm/configs/at91sam9n12ek_defconfig
+++ b/arch/arm/configs/at91sam9n12ek_defconfig
@@ -1,15 +1,15 @@
 CONFIG_TEXT_BASE=0x26f00000
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9N12=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
+CONFIG_IMAGE_COMPRESSION_XZKERN=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_MALLOC_SIZE=0xa00000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="9G20-EK:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -60,9 +60,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_MTD_M25P80=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_NAND_ATMEL_PMECC=y
 CONFIG_USB_GADGET=y
diff --git a/arch/arm/configs/canon-a1100_defconfig b/arch/arm/configs/canon-a1100_defconfig
index 12a3f0af95..53348f6e8a 100644
--- a/arch/arm/configs/canon-a1100_defconfig
+++ b/arch/arm/configs/canon-a1100_defconfig
@@ -2,10 +2,8 @@ CONFIG_TEXT_BASE=0x00300000
 CONFIG_ARCH_DIGIC=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_PBL_IMAGE=y
-CONFIG_IMAGE_COMPRESSION_LZ4=y
 CONFIG_MALLOC_SIZE=0x200000
 CONFIG_PROMPT="canon-a1100 > "
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index d9eab565b9..3a2d8b5a05 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARCH_CLPS711X=y
+CONFIG_CLPS711X_RAISE_CPUFREQ=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 # CONFIG_MEMINFO is not set
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_BAUDRATE=57600
@@ -10,7 +10,6 @@ CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
 CONFIG_BOOTM_SHOW_TYPE=y
 CONFIG_BOOTM_INITRD=y
-CONFIG_DEFAULT_COMPRESSION_LZO=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_CMD_IOMEM=y
 # CONFIG_CMD_BOOTU is not set
@@ -28,6 +27,8 @@ CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_CRC=y
 CONFIG_CMD_CRC_CMP=y
 CONFIG_CMD_FLASH=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
 CONFIG_DRIVER_CFI=y
@@ -36,6 +37,7 @@ CONFIG_DRIVER_CFI=y
 CONFIG_DISK=y
 CONFIG_DISK_WRITE=y
 CONFIG_DISK_INTF_PLATFORM_IDE=y
+# CONFIG_PINCTRL is not set
 CONFIG_FS_CRAMFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/cupid_defconfig b/arch/arm/configs/cupid_defconfig
deleted file mode 100644
index 4e6dd96a97..0000000000
--- a/arch/arm/configs/cupid_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_TEXT_BASE=0x87F00000
-CONFIG_ARCH_IMX=y
-CONFIG_CACHE_L2X0=y
-CONFIG_MACH_GUF_CUPID=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x1000000
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SPLASH=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_TIME=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-# CONFIG_SPI is not set
-CONFIG_MTD=y
-CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-CONFIG_NAND_IMX=y
-CONFIG_VIDEO=y
-CONFIG_DRIVER_VIDEO_IMX_IPU=y
-CONFIG_MCI=y
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/dss11_defconfig b/arch/arm/configs/dss11_defconfig
index 3da42205d1..fe2680e431 100644
--- a/arch/arm/configs/dss11_defconfig
+++ b/arch/arm/configs/dss11_defconfig
@@ -1,3 +1,4 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_DSS11=y
 CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16=y
@@ -24,8 +25,6 @@ CONFIG_DRIVER_NET_MACB=y
 CONFIG_DRIVER_SPI_ATMEL=y
 CONFIG_MTD=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DISK_WRITE=y
 CONFIG_USB_HOST=y
diff --git a/arch/arm/configs/edb93xx_defconfig b/arch/arm/configs/edb93xx_defconfig
index 84c920aa97..0632be1945 100644
--- a/arch/arm/configs/edb93xx_defconfig
+++ b/arch/arm/configs/edb93xx_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARCH_EP93XX=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_GLOB=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
 CONFIG_PARTITION=y
diff --git a/arch/arm/configs/eukrea_cpuimx25_defconfig b/arch/arm/configs/eukrea_cpuimx25_defconfig
deleted file mode 100644
index b296122bc2..0000000000
--- a/arch/arm/configs/eukrea_cpuimx25_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
-CONFIG_MACH_EUKREA_CPUIMX25=y
-CONFIG_IMX_IIM=y
-CONFIG_IMX_IIM_FUSE_BLOW=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_PBL_RELOCATABLE=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x800000
-CONFIG_EXPERIMENTAL=y
-CONFIG_MALLOC_TLSF=y
-CONFIG_RELOCATABLE=y
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_DEFAULT_COMPRESSION_LZO=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_AUTOMOUNT=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SPLASH=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-# CONFIG_SPI is not set
-CONFIG_I2C=y
-CONFIG_I2C_IMX=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_DEVICE=y
-CONFIG_NAND=y
-CONFIG_NAND_IMX=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_USB_HOST=y
-CONFIG_USB_IMX_CHIPIDEA=y
-CONFIG_USB_EHCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_DRIVER_VIDEO_IMX=y
-CONFIG_MCI=y
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_BMP=y
-CONFIG_PNG=y
diff --git a/arch/arm/configs/eukrea_cpuimx27_defconfig b/arch/arm/configs/eukrea_cpuimx27_defconfig
deleted file mode 100644
index cb4a709d42..0000000000
--- a/arch/arm/configs/eukrea_cpuimx27_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_TEXT_BASE=0xa7f00000
-CONFIG_ARCH_IMX=y
-CONFIG_MACH_EUKREA_CPUIMX27=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x800000
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx27/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SPLASH=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_NET=y
-CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-# CONFIG_SPI is not set
-CONFIG_I2C=y
-CONFIG_I2C_IMX=y
-CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-# CONFIG_DRIVER_CFI_AMD is not set
-# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
-# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set
-CONFIG_CFI_BUFFER_WRITE=y
-CONFIG_VIDEO=y
-CONFIG_DRIVER_VIDEO_IMX=y
-CONFIG_MFD_LP3972=y
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig
deleted file mode 100644
index b3d5741c69..0000000000
--- a/arch/arm/configs/eukrea_cpuimx35_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
-CONFIG_MACH_EUKREA_CPUIMX35=y
-CONFIG_IMX_IIM=y
-CONFIG_IMX_IIM_FUSE_BLOW=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_PBL_RELOCATABLE=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x800000
-CONFIG_EXPERIMENTAL=y
-CONFIG_MALLOC_TLSF=y
-CONFIG_RELOCATABLE=y
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_DEFAULT_COMPRESSION_LZO=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_IMD=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_AUTOMOUNT=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MIITOOL=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SPLASH=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_MM=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DETECT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_USBGADGET=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-CONFIG_SMSC_PHY=y
-# CONFIG_SPI is not set
-CONFIG_I2C=y
-CONFIG_I2C_IMX=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_DEVICE=y
-CONFIG_NAND=y
-CONFIG_NAND_ALLOW_ERASE_BAD=y
-CONFIG_NAND_IMX=y
-CONFIG_USB_HOST=y
-CONFIG_USB_IMX_CHIPIDEA=y
-CONFIG_USB_EHCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DFU=y
-CONFIG_USB_GADGET_SERIAL=y
-CONFIG_VIDEO=y
-CONFIG_DRIVER_VIDEO_IMX_IPU=y
-CONFIG_MCI=y
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/eukrea_cpuimx51_defconfig b/arch/arm/configs/eukrea_cpuimx51_defconfig
deleted file mode 100644
index 8d700b1e75..0000000000
--- a/arch/arm/configs/eukrea_cpuimx51_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
-CONFIG_MACH_EUKREA_CPUIMX51SD=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x2000000
-CONFIG_EXPERIMENTAL=y
-CONFIG_MALLOC_TLSF=y
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-# CONFIG_SPI is not set
-CONFIG_I2C=y
-CONFIG_I2C_IMX=y
-CONFIG_MTD=y
-CONFIG_NAND=y
-CONFIG_NAND_IMX=y
-CONFIG_MCI=y
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/freescale-mx21-ads_defconfig b/arch/arm/configs/freescale-mx21-ads_defconfig
deleted file mode 100644
index b1d37f76a8..0000000000
--- a/arch/arm/configs/freescale-mx21-ads_defconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-CONFIG_TEXT_BASE=0xc3000000
-CONFIG_ARCH_IMX=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_MALLOC_SIZE=0x2000000
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx21-ads/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_DRIVER_NET_CS8900=y
-# CONFIG_SPI is not set
-CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-# CONFIG_DRIVER_CFI_INTEL is not set
-CONFIG_CFI_BUFFER_WRITE=y
-CONFIG_NAND=y
-CONFIG_NAND_IMX=y
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/freescale-mx25-3ds_defconfig b/arch/arm/configs/freescale-mx25-3ds_defconfig
deleted file mode 100644
index eca608be40..0000000000
--- a/arch/arm/configs/freescale-mx25-3ds_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_TEXT_BASE=0x87F00000
-CONFIG_ARCH_IMX=y
-CONFIG_MACH_FREESCALE_MX25_3STACK=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x01000000
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-# CONFIG_ERRNO_MESSAGES is not set
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_TIME=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-# CONFIG_SPI is not set
-CONFIG_USB_HOST=y
-CONFIG_USB_EHCI=y
-CONFIG_FS_TFTP=y
-CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/freescale-mx27-ads_defconfig b/arch/arm/configs/freescale-mx27-ads_defconfig
deleted file mode 100644
index ef112d6d5c..0000000000
--- a/arch/arm/configs/freescale-mx27-ads_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-CONFIG_TEXT_BASE=0xa7f00000
-CONFIG_ARCH_IMX=y
-CONFIG_MACH_IMX27ADS=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx27-ads/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_NET=y
-CONFIG_DRIVER_SPI_IMX=y
-CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-# CONFIG_DRIVER_CFI_INTEL is not set
-CONFIG_CFI_BUFFER_WRITE=y
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/freescale-mx35-3ds_defconfig b/arch/arm/configs/freescale-mx35-3ds_defconfig
deleted file mode 100644
index 5399849a54..0000000000
--- a/arch/arm/configs/freescale-mx35-3ds_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_TEXT_BASE=0x87F00000
-CONFIG_ARCH_IMX=y
-CONFIG_MACH_FREESCALE_MX35_3STACK=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
-CONFIG_MALLOC_SIZE=0x1000000
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SPLASH=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_TIME=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-CONFIG_DRIVER_NET_SMC911X=y
-# CONFIG_SPI is not set
-CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-CONFIG_CFI_BUFFER_WRITE=y
-CONFIG_NAND=y
-CONFIG_NAND_IMX=y
-CONFIG_VIDEO=y
-CONFIG_DRIVER_VIDEO_IMX_IPU=y
-CONFIG_FS_TFTP=y
-CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/freescale-mx53-smd_defconfig b/arch/arm/configs/freescale-mx53-smd_defconfig
deleted file mode 100644
index b292b972a3..0000000000
--- a/arch/arm/configs/freescale-mx53-smd_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_MACH_FREESCALE_MX53_SMD=y
-CONFIG_IMX_IIM=y
-CONFIG_IMX_IIM_FUSE_BLOW=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x2000000
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_TIME=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-# CONFIG_SPI is not set
-CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/friendlyarm_mini2440_defconfig b/arch/arm/configs/friendlyarm_mini2440_defconfig
deleted file mode 100644
index 21c931ca05..0000000000
--- a/arch/arm/configs/friendlyarm_mini2440_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_TEXT_BASE=0x33e00000
-CONFIG_ARCH_S3C24xx=y
-CONFIG_MACH_MINI2440=y
-CONFIG_MINI2440_VIDEO_N35=y
-CONFIG_S3C_NAND_BOOT=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PROMPT="mini2440:"
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/friendlyarm-mini2440/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_GLOBAL=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_DM9K=y
-# CONFIG_SPI is not set
-CONFIG_USB_HOST=y
-CONFIG_USB_OHCI=y
-CONFIG_MCI=y
-CONFIG_MCI_S3C=y
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/friendlyarm_mini6410_defconfig b/arch/arm/configs/friendlyarm_mini6410_defconfig
deleted file mode 100644
index 8beee6f194..0000000000
--- a/arch/arm/configs/friendlyarm_mini6410_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_ARCH_S3C64xx=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PROMPT="mini6410:"
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_GPIO=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_DM9K=y
-# CONFIG_SPI is not set
-CONFIG_ZLIB=y
-CONFIG_BZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/friendlyarm_tiny210_defconfig b/arch/arm/configs/friendlyarm_tiny210_defconfig
deleted file mode 100644
index 1d1647931f..0000000000
--- a/arch/arm/configs/friendlyarm_tiny210_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARCH_S5PCxx=y
-CONFIG_S3C_PLL_INIT=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
diff --git a/arch/arm/configs/friendlyarm_tiny6410_defconfig b/arch/arm/configs/friendlyarm_tiny6410_defconfig
deleted file mode 100644
index 12dbea1317..0000000000
--- a/arch/arm/configs/friendlyarm_tiny6410_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-CONFIG_ARCH_S3C64xx=y
-CONFIG_MACH_TINY6410=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PROMPT="tiny6410:"
-CONFIG_GLOB=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_GPIO=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_DM9K=y
-# CONFIG_SPI is not set
-CONFIG_ZLIB=y
-CONFIG_BZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/haba_knx_lite_defconfig b/arch/arm/configs/haba_knx_lite_defconfig
index 233644f24a..a72359931d 100644
--- a/arch/arm/configs/haba_knx_lite_defconfig
+++ b/arch/arm/configs/haba_knx_lite_defconfig
@@ -1,15 +1,14 @@
 CONFIG_TEXT_BASE=0x27f00000
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_HABA_KNX_LITE=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="HABA-KNX-LITE:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -63,9 +62,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_MTD_M25P80=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
 CONFIG_USB_GADGET=y
diff --git a/arch/arm/configs/imx28_defconfig b/arch/arm/configs/imx28_defconfig
index beb0bc2f76..8e66983e35 100644
--- a/arch/arm/configs/imx28_defconfig
+++ b/arch/arm/configs/imx28_defconfig
@@ -92,7 +92,6 @@ CONFIG_NET_USB_ASIX=y
 CONFIG_USB_NET_AX88179_178A=y
 CONFIG_NET_USB_SMSC95XX=y
 CONFIG_DRIVER_SPI_MXS=y
-CONFIG_I2C=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 624698ae3c..d3def0ece0 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -1,54 +1,58 @@
 CONFIG_ARCH_IMX=y
-CONFIG_IMX_MULTI_BOARDS=y
 CONFIG_MACH_KINDLE_MX50=y
 CONFIG_MACH_CCMX51=y
 CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
-CONFIG_MACH_EMBEDSKY_E9=y
 CONFIG_MACH_FREESCALE_MX51_PDK=y
 CONFIG_MACH_CCMX53=y
 CONFIG_MACH_FREESCALE_MX53_LOCO=y
 CONFIG_MACH_GUF_VINCELL=y
+CONFIG_MACH_TX53=y
 CONFIG_MACH_TQMA53=y
 CONFIG_MACH_FREESCALE_MX53_VMX53=y
-CONFIG_MACH_TX53=y
-CONFIG_MACH_PHYTEC_SOM_IMX6=y
-CONFIG_MACH_PROTONIC_IMX6=y
-CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR=y
-CONFIG_MACH_KONTRON_SAMX6I=y
-CONFIG_MACH_DFI_FS700_M60=y
-CONFIG_MACH_GUF_SANTARO=y
+CONFIG_MACH_ZII_RDU1=y
+CONFIG_MACH_ADVANTECH_ROM_742X=y
+CONFIG_MACH_NITROGEN6=y
+CONFIG_MACH_CM_FX6=y
 CONFIG_MACH_REALQ7=y
-CONFIG_MACH_GK802=y
+CONFIG_MACH_DFI_FS700_M60=y
+CONFIG_MACH_DIGI_CCIMX6ULSBCPRO=y
 CONFIG_MACH_ELTEC_HIPERCAM=y
-CONFIG_MACH_TQMA6X=y
-CONFIG_MACH_TX6X=y
+CONFIG_MACH_EMBEDSKY_E9=y
+CONFIG_MACH_EMBEST_MARSBOARD=y
+CONFIG_MACH_EMBEST_RIOTBOARD=y
 CONFIG_MACH_SABRELITE=y
 CONFIG_MACH_SABRESD=y
 CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB=y
-CONFIG_MACH_NITROGEN6=y
+CONFIG_MACH_UDOO=y
+CONFIG_MACH_UDOO_NEO=y
+CONFIG_MACH_GUF_SANTARO=y
+CONFIG_MACH_GW_VENTANA=y
+CONFIG_MACH_GRINN_LITEBOARD=y
+CONFIG_MACH_TX6X=y
+CONFIG_MACH_KONTRON_SAMX6I=y
+CONFIG_MACH_NOVENA=y
+CONFIG_MACH_NXP_IMX6ULL_EVK=y
+CONFIG_MACH_PHYTEC_SOM_IMX6=y
+CONFIG_MACH_PROTONIC_IMX6=y
+CONFIG_MACH_SKOV_IMX6=y
 CONFIG_MACH_SOLIDRUN_MICROSOM=y
 CONFIG_MACH_TECHNEXION_PICO_HOBBIT=y
 CONFIG_MACH_TECHNEXION_WANDBOARD=y
-CONFIG_MACH_EMBEST_MARSBOARD=y
-CONFIG_MACH_EMBEST_RIOTBOARD=y
-CONFIG_MACH_UDOO=y
-CONFIG_MACH_UDOO_NEO=y
+CONFIG_MACH_TQMA6X=y
 CONFIG_MACH_VARISCITE_MX6=y
-CONFIG_MACH_GW_VENTANA=y
-CONFIG_MACH_CM_FX6=y
-CONFIG_MACH_ADVANTECH_ROM_742X=y
-CONFIG_MACH_WARP7=y
 CONFIG_MACH_WEBASTO_CCBV2=y
-CONFIG_MACH_VF610_TWR=y
-CONFIG_MACH_ZII_RDU1=y
+CONFIG_MACH_GK802=y
 CONFIG_MACH_ZII_RDU2=y
-CONFIG_MACH_ZII_VF610_DEV=y
-CONFIG_MACH_ZII_IMX7D_DEV=y
-CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y
+CONFIG_MACH_MEERKAT96=y
+CONFIG_MACH_AC_SXB=y
+CONFIG_MACH_WARP7=y
 CONFIG_MACH_FREESCALE_MX7_SABRESD=y
-CONFIG_MACH_NXP_IMX6ULL_EVK=y
-CONFIG_MACH_GRINN_LITEBOARD=y
-CONFIG_MACH_DIGI_CCIMX6ULSBCPRO=y
+CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y
+CONFIG_MACH_VARISCITE_SOM_MX7=y
+CONFIG_MACH_ZII_IMX7D_DEV=y
+CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR=y
+CONFIG_MACH_VF610_TWR=y
+CONFIG_MACH_ZII_VF610_DEV=y
 CONFIG_IMX_IIM_FUSE_BLOW=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@@ -69,11 +73,13 @@ CONFIG_BOOTM_OFTREE=y
 CONFIG_BOOTM_OFTREE_UIMAGE=y
 CONFIG_BLSPEC=y
 CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
 CONFIG_PARTITION_DISK_EFI=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_STATE=y
 CONFIG_BOOTCHOOSER=y
 CONFIG_RESET_SOURCE=y
+CONFIG_MACHINE_ID=y
 CONFIG_FASTBOOT_CMD_OEM=y
 CONFIG_CMD_DMESG=y
 CONFIG_LONGHELP=y
@@ -83,10 +89,12 @@ CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_ARM_MMUINFO=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_MMC_EXTCSD=y
+CONFIG_CMD_FCB=y
 # CONFIG_CMD_BOOTU is not set
 CONFIG_CMD_GO=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_BOOTCHOOSER=y
 CONFIG_CMD_PARTITION=y
 CONFIG_CMD_UBIFORMAT=y
 CONFIG_CMD_EXPORT=y
@@ -113,6 +121,7 @@ CONFIG_CMD_MENU=y
 CONFIG_CMD_MENU_MANAGEMENT=y
 CONFIG_CMD_MENUTREE=y
 CONFIG_CMD_SPLASH=y
+CONFIG_CMD_FBTEST=y
 CONFIG_CMD_READLINE=y
 CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_CRC=y
@@ -133,19 +142,25 @@ CONFIG_CMD_WD=y
 CONFIG_CMD_BAREBOX_UPDATE=y
 CONFIG_CMD_OF_NODE=y
 CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_DISPLAY_TIMINGS=y
+CONFIG_CMD_OF_FIXUP_STATUS=y
+CONFIG_CMD_OF_OVERLAY=y
 CONFIG_CMD_OFTREE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_STATE=y
-CONFIG_CMD_BOOTCHOOSER=y
 CONFIG_NET=y
 CONFIG_NET_NETCONSOLE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_DRIVER_NET_FEC_IMX=y
-CONFIG_AT803X_PHY=y
 CONFIG_MICREL_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
 CONFIG_NET_USB=y
 CONFIG_NET_USB_ASIX=y
 CONFIG_NET_USB_SMSC95XX=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_MUX=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_DEVICE=y
 CONFIG_MTD_DATAFLASH=y
@@ -174,8 +189,12 @@ CONFIG_VIDEO=y
 CONFIG_DRIVER_VIDEO_IMX_IPUV3=y
 CONFIG_DRIVER_VIDEO_IMX_IPUV3_LVDS=y
 CONFIG_DRIVER_VIDEO_IMX_IPUV3_HDMI=y
+CONFIG_DRIVER_VIDEO_IMX_IPUV3_PARALLEL=y
 CONFIG_DRIVER_VIDEO_SIMPLEFB=y
 CONFIG_DRIVER_VIDEO_EDID=y
+CONFIG_DRIVER_VIDEO_BACKLIGHT=y
+CONFIG_DRIVER_VIDEO_BACKLIGHT_PWM=y
+CONFIG_DRIVER_VIDEO_SIMPLE_PANEL=y
 CONFIG_MCI=y
 CONFIG_MCI_MMC_BOOT_PARTITIONS=y
 CONFIG_MCI_IMX_ESDHC=y
@@ -197,16 +216,23 @@ CONFIG_PWM=y
 CONFIG_PWM_IMX=y
 CONFIG_MXS_APBH_DMA=y
 CONFIG_GPIO_STMPE=y
+CONFIG_IMX_OCOTP_WRITE=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED=y
 CONFIG_GENERIC_PHY=y
 CONFIG_USB_NOP_XCEIV=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_POWER_RESET_SYSCON=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_TFTP=y
+CONFIG_FS_TFTP_MAX_WINDOW_SIZE=8
 CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
 CONFIG_FS_UBIFS=y
 CONFIG_FS_UBIFS_COMPRESSION_LZO=y
+CONFIG_FS_UBIFS_COMPRESSION_ZSTD=y
+CONFIG_FS_SQUASHFS=y
 CONFIG_PNG=y
+CONFIG_DIGEST_SHA1_ARM=y
diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig
index 06d79f594d..e58a2ca13d 100644
--- a/arch/arm/configs/imx_v8_defconfig
+++ b/arch/arm/configs/imx_v8_defconfig
@@ -1,10 +1,21 @@
 CONFIG_ARCH_IMX=y
-CONFIG_IMX_MULTI_BOARDS=y
-CONFIG_MACH_ZII_IMX8MQ_DEV=y
+CONFIG_MACH_INNOCOMM_WB15=y
+CONFIG_MACH_KOENIGBAUER_ALPHAJET=y
+CONFIG_MACH_KARO_QSXP_ML81=y
+CONFIG_MACH_MNT_REFORM=y
 CONFIG_MACH_NXP_IMX8MM_EVK=y
+CONFIG_MACH_NXP_IMX8MN_EVK=y
 CONFIG_MACH_NXP_IMX8MP_EVK=y
 CONFIG_MACH_NXP_IMX8MQ_EVK=y
 CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y
+CONFIG_MACH_POLYHEX_DEBIX=y
+CONFIG_MACH_PROTONIC_IMX8M=y
+CONFIG_MACH_SKOV_IMX8MP=y
+CONFIG_MACH_TQ_MBA8MPXL=y
+CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP=y
+CONFIG_MACH_ZII_IMX8MQ_DEV=y
+CONFIG_64BIT=y
+CONFIG_MACH_TQMA93XX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_MMU=y
 CONFIG_MALLOC_SIZE=0x0
@@ -85,6 +96,8 @@ CONFIG_NET_NETCONSOLE=y
 CONFIG_OFDEVICE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_SERIAL_DEV_BUS=y
+CONFIG_DRIVER_NET_DESIGNWARE_IMX8=y
+CONFIG_DRIVER_SERIAL_LPUART32=y
 CONFIG_DRIVER_NET_FEC_IMX=y
 CONFIG_DP83867_PHY=y
 CONFIG_MICREL_PHY=y
@@ -97,13 +110,16 @@ CONFIG_NET_USB=y
 CONFIG_NET_USB_ASIX=y
 CONFIG_NET_USB_SMSC95XX=y
 CONFIG_DRIVER_SPI_IMX=y
+CONFIG_SPI_NXP_FLEXSPI=y
 CONFIG_I2C=y
 CONFIG_I2C_IMX=y
+CONFIG_I2C_IMX_LPI2C=y
 CONFIG_MTD=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_M25P80=y
 CONFIG_USB_HOST=y
 CONFIG_USB_IMX_CHIPIDEA=y
+CONFIG_USB_EHCI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_SERIAL=y
@@ -112,6 +128,7 @@ CONFIG_MCI=y
 CONFIG_MCI_MMC_BOOT_PARTITIONS=y
 CONFIG_MCI_IMX_ESDHC=y
 CONFIG_RAVE_SP_CORE=y
+CONFIG_MFD_PCA9450=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_LED_GPIO_OF=y
@@ -119,9 +136,12 @@ CONFIG_LED_TRIGGERS=y
 CONFIG_EEPROM_AT25=y
 CONFIG_EEPROM_AT24=y
 CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_POLLER=y
 CONFIG_WATCHDOG_IMX=y
+CONFIG_WATCHDOG_IMXULP=y
 CONFIG_RAVE_SP_WATCHDOG=y
-CONFIG_IMX_OCOTP=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_IMX_OCOTP_ELE=y
 CONFIG_RAVE_SP_EEPROM=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED=y
@@ -134,6 +154,6 @@ CONFIG_FS_TFTP=y
 CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
 CONFIG_FS_RATP=y
 CONFIG_ZLIB=y
+# CONFIG_MISSING_FIRMWARE_ERROR is not set
diff --git a/arch/arm/configs/kindle-mx50_defconfig b/arch/arm/configs/kindle-mx50_defconfig
index 95fafd56e6..1ceef8088a 100644
--- a/arch/arm/configs/kindle-mx50_defconfig
+++ b/arch/arm/configs/kindle-mx50_defconfig
@@ -1,5 +1,4 @@
 CONFIG_ARCH_IMX=y
-CONFIG_IMX_MULTI_BOARDS=y
 CONFIG_MACH_KINDLE_MX50=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
diff --git a/arch/arm/configs/kindle3_defconfig b/arch/arm/configs/kindle3_defconfig
deleted file mode 100644
index 98691c3a81..0000000000
--- a/arch/arm/configs/kindle3_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x30000
-CONFIG_MACH_KINDLE3=y
-CONFIG_IMX_IIM=y
-CONFIG_AEABI=y
-CONFIG_ARM_BOARD_APPEND_ATAG=y
-CONFIG_ARM_BOARD_PREPEND_ATAG=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_PBL_RELOCATABLE=y
-CONFIG_IMAGE_COMPRESSION_XZKERN=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x2000000
-CONFIG_MALLOC_TLSF=y
-CONFIG_RELOCATABLE=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/kindle3/env/"
-CONFIG_RESET_SOURCE=y
-CONFIG_CMD_DMESG=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MMC_EXTCSD=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADY=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_DEFAULTENV=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_READF=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USBGADGET=y
-CONFIG_DRIVER_SPI_IMX=y
-CONFIG_I2C=y
-CONFIG_I2C_IMX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_SERIAL=y
-CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_MFD_MC13XXX=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_ARCH_IMX_USBLOADER=y
diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
index 394cd95c98..8103da3226 100644
--- a/arch/arm/configs/layerscape_defconfig
+++ b/arch/arm/configs/layerscape_defconfig
@@ -1,7 +1,10 @@
 CONFIG_ARCH_LAYERSCAPE=y
 CONFIG_ARCH_LAYERSCAPE_PPA=y
+CONFIG_MACH_LS1028ARDB=y
 CONFIG_MACH_LS1046ARDB=y
 CONFIG_MACH_TQMLS1046A=y
+CONFIG_64BIT=y
+CONFIG_ARM_PSCI_CLIENT=y
 CONFIG_MMU=y
 CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
@@ -34,6 +37,7 @@ CONFIG_CMD_GO=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_UIMAGE=y
 CONFIG_CMD_PARTITION=y
+CONFIG_CMD_UBIFORMAT=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_LOADENV=y
 CONFIG_CMD_PRINTENV=y
@@ -80,6 +84,7 @@ CONFIG_NET=y
 CONFIG_NET_NETCONSOLE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_FSL_ENETC=y
 CONFIG_DRIVER_NET_FSL_FMAN=y
 CONFIG_DP83867_PHY=y
 CONFIG_REALTEK_PHY=y
@@ -91,6 +96,9 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
+CONFIG_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
 CONFIG_MCI=y
 CONFIG_MCI_MMC_BOOT_PARTITIONS=y
 CONFIG_MCI_IMX_ESDHC=y
@@ -106,11 +114,13 @@ CONFIG_WATCHDOG_IMX=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_ECAM_GENERIC=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_TFTP=y
 CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
+CONFIG_FS_UBIFS=y
+CONFIG_FS_UBIFS_COMPRESSION_LZO=y
 CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/phytec-phycore-imx35_defconfig b/arch/arm/configs/layerscape_v7_defconfig
index 2ed2cf9ef3..792e9274b2 100644
--- a/arch/arm/configs/phytec-phycore-imx35_defconfig
+++ b/arch/arm/configs/layerscape_v7_defconfig
@@ -1,17 +1,10 @@
-CONFIG_TEXT_BASE=0x87E00000
-CONFIG_ARCH_IMX=y
-CONFIG_CACHE_L2X0=y
-CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
-CONFIG_MACH_PCM043=y
-CONFIG_IMX_IIM=y
-CONFIG_IMX_IIM_FUSE_BLOW=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_MACH_LS1021AIOT=y
 CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x1000000
+CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
@@ -21,18 +14,22 @@ CONFIG_BOOTM_VERBOSE=y
 CONFIG_BOOTM_INITRD=y
 CONFIG_BOOTM_OFTREE=y
 CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_PARTITION=y
+CONFIG_BLSPEC=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_PBL_CONSOLE=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-imx35/env"
 CONFIG_RESET_SOURCE=y
+CONFIG_CMD_DMESG=y
 CONFIG_LONGHELP=y
 CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
 CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
 CONFIG_CMD_GO=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_UIMAGE=y
 CONFIG_CMD_PARTITION=y
+CONFIG_CMD_UBIFORMAT=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_LOADENV=y
 CONFIG_CMD_PRINTENV=y
@@ -47,40 +44,43 @@ CONFIG_CMD_LET=y
 CONFIG_CMD_MSLEEP=y
 CONFIG_CMD_READF=y
 CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MIITOOL=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_MENU=y
 CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_MENUTREE=y
 CONFIG_CMD_READLINE=y
 CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_CRC=y
 CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DETECT=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_WD=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_BAREBOX_UPDATE=y
 CONFIG_CMD_OF_NODE=y
 CONFIG_CMD_OF_PROPERTY=y
 CONFIG_CMD_OFTREE=y
 CONFIG_CMD_TIME=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-# CONFIG_SPI is not set
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SPI_FSL_QUADSPI=y
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
 CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-CONFIG_CFI_BUFFER_WRITE=y
-CONFIG_NAND=y
-CONFIG_NAND_IMX=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_IMX=y
-CONFIG_FS_TFTP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_UBI=y
+CONFIG_MCI=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_EEPROM_AT25=y
+CONFIG_EEPROM_AT24=y
+CONFIG_GPIO_PCA953X=y
 CONFIG_ZLIB=y
 CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig
index a3f988aec9..78f2236648 100644
--- a/arch/arm/configs/lubbock_defconfig
+++ b/arch/arm/configs/lubbock_defconfig
@@ -1,11 +1,11 @@
 CONFIG_ARCH_PXA=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
 CONFIG_AEABI=y
 CONFIG_ARM_BOARD_APPEND_ATAG=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 # CONFIG_BANNER is not set
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
 CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000
 CONFIG_MALLOC_SIZE=0x1000000
 CONFIG_EXPERIMENTAL=y
diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig
index b685e7fc8d..d452885e6d 100644
--- a/arch/arm/configs/mainstone_defconfig
+++ b/arch/arm/configs/mainstone_defconfig
@@ -1,5 +1,4 @@
 CONFIG_ARCH_PXA=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
 CONFIG_ARCH_PXA27X=y
 CONFIG_AEABI=y
 CONFIG_ARM_BOARD_APPEND_ATAG=y
@@ -7,6 +6,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 # CONFIG_BANNER is not set
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
 CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000
 CONFIG_MALLOC_SIZE=0x1000000
 CONFIG_EXPERIMENTAL=y
diff --git a/arch/arm/configs/mioa701_defconfig b/arch/arm/configs/mioa701_defconfig
index a786d1618e..991fca0d7b 100644
--- a/arch/arm/configs/mioa701_defconfig
+++ b/arch/arm/configs/mioa701_defconfig
@@ -1,5 +1,4 @@
 CONFIG_ARCH_PXA=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
 CONFIG_ARCH_PXA27X=y
 CONFIG_AEABI=y
 CONFIG_ARM_BOARD_APPEND_ATAG=y
@@ -7,12 +6,12 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 # CONFIG_BANNER is not set
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
 CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000
 CONFIG_MALLOC_SIZE=0x1000000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MODULES=y
 CONFIG_KALLSYMS=y
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/module-mb7707_defconfig b/arch/arm/configs/module-mb7707_defconfig
index 9484c39fb8..60be16df74 100644
--- a/arch/arm/configs/module-mb7707_defconfig
+++ b/arch/arm/configs/module-mb7707_defconfig
@@ -6,7 +6,6 @@ CONFIG_PBL_RELOCATABLE=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="MB 77.07: "
 CONFIG_BAUDRATE=38400
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/imx_defconfig b/arch/arm/configs/multi_v5_v6_defconfig
index e6333220b6..0ff8597fde 100644
--- a/arch/arm/configs/imx_defconfig
+++ b/arch/arm/configs/multi_v5_v6_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARCH_IMX=y
-CONFIG_IMX_MULTI_BOARDS=y
+CONFIG_ARCH_VERSATILE=y
 CONFIG_MACH_SCB9328=y
 CONFIG_MACH_TX25=y
 CONFIG_MACH_PCA100=y
 CONFIG_MACH_PCM038=y
 CONFIG_IMX_IIM=y
 CONFIG_IMX_IIM_FUSE_BLOW=y
+CONFIG_BOARD_ARM_GENERIC_DT=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
@@ -75,7 +76,9 @@ CONFIG_NET=y
 CONFIG_NET_NETCONSOLE=y
 CONFIG_OFDEVICE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_DRIVER_NET_SMC91111=y
 CONFIG_NET_USB=y
 CONFIG_NET_USB_ASIX=y
 CONFIG_I2C=y
@@ -85,8 +88,6 @@ CONFIG_MTD_RAW_DEVICE=y
 CONFIG_DRIVER_CFI=y
 CONFIG_CFI_BUFFER_WRITE=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
 CONFIG_NAND_ALLOW_ERASE_BAD=y
 CONFIG_NAND_IMX=y
 CONFIG_MTD_UBI=y
@@ -96,6 +97,7 @@ CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI=y
 CONFIG_MCI=y
 CONFIG_MCI_IMX=y
+CONFIG_CLOCKSOURCE_DW_APB_TIMER=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_LED_GPIO_OF=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
new file mode 100644
index 0000000000..97b01fd812
--- /dev/null
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -0,0 +1,364 @@
+CONFIG_ARCH_BCM283X=y
+CONFIG_ARCH_IMX=y
+CONFIG_ARCH_OMAP_MULTI=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_CACHE_L2X0=y
+CONFIG_MACH_RPI=y
+CONFIG_MACH_RPI2=y
+CONFIG_MACH_RPI3=y
+CONFIG_MACH_RPI_CM3=y
+CONFIG_MACH_RPI4=y
+CONFIG_MACH_KINDLE_MX50=y
+CONFIG_MACH_CCMX51=y
+CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
+CONFIG_MACH_FREESCALE_MX51_PDK=y
+CONFIG_MACH_CCMX53=y
+CONFIG_MACH_FREESCALE_MX53_LOCO=y
+CONFIG_MACH_GUF_VINCELL=y
+CONFIG_MACH_TX53=y
+CONFIG_MACH_TQMA53=y
+CONFIG_MACH_FREESCALE_MX53_VMX53=y
+CONFIG_MACH_ZII_RDU1=y
+CONFIG_MACH_ADVANTECH_ROM_742X=y
+CONFIG_MACH_NITROGEN6=y
+CONFIG_MACH_CM_FX6=y
+CONFIG_MACH_REALQ7=y
+CONFIG_MACH_DFI_FS700_M60=y
+CONFIG_MACH_DIGI_CCIMX6ULSBCPRO=y
+CONFIG_MACH_ELTEC_HIPERCAM=y
+CONFIG_MACH_EMBEDSKY_E9=y
+CONFIG_MACH_EMBEST_MARSBOARD=y
+CONFIG_MACH_EMBEST_RIOTBOARD=y
+CONFIG_MACH_SABRELITE=y
+CONFIG_MACH_SABRESD=y
+CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB=y
+CONFIG_MACH_UDOO=y
+CONFIG_MACH_UDOO_NEO=y
+CONFIG_MACH_GUF_SANTARO=y
+CONFIG_MACH_GW_VENTANA=y
+CONFIG_MACH_GRINN_LITEBOARD=y
+CONFIG_MACH_TX6X=y
+CONFIG_MACH_KONTRON_SAMX6I=y
+CONFIG_MACH_NOVENA=y
+CONFIG_MACH_NXP_IMX6ULL_EVK=y
+CONFIG_MACH_PHYTEC_SOM_IMX6=y
+CONFIG_MACH_PROTONIC_IMX6=y
+CONFIG_MACH_SKOV_IMX6=y
+CONFIG_MACH_SOLIDRUN_MICROSOM=y
+CONFIG_MACH_TECHNEXION_PICO_HOBBIT=y
+CONFIG_MACH_TECHNEXION_WANDBOARD=y
+CONFIG_MACH_TQMA6X=y
+CONFIG_MACH_VARISCITE_MX6=y
+CONFIG_MACH_WEBASTO_CCBV2=y
+CONFIG_MACH_GK802=y
+CONFIG_MACH_ZII_RDU2=y
+CONFIG_MACH_MEERKAT96=y
+CONFIG_MACH_AC_SXB=y
+CONFIG_MACH_WARP7=y
+CONFIG_MACH_FREESCALE_MX7_SABRESD=y
+CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y
+CONFIG_MACH_VARISCITE_SOM_MX7=y
+CONFIG_MACH_ZII_IMX7D_DEV=y
+CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR=y
+CONFIG_MACH_VF610_TWR=y
+CONFIG_MACH_ZII_VF610_DEV=y
+CONFIG_IMX_IIM_FUSE_BLOW=y
+CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO=y
+CONFIG_BAREBOX_UPDATE_AM33XX_NAND=y
+CONFIG_BAREBOX_UPDATE_AM33XX_EMMC=y
+CONFIG_MACH_AFI_GF=y
+CONFIG_MACH_BEAGLE=y
+CONFIG_MACH_BEAGLEBONE=y
+CONFIG_MACH_MYIRTECH_X335X=y
+CONFIG_MACH_PHYTEC_SOM_AM335X=y
+CONFIG_MACH_VSCOM_BALTOS=y
+CONFIG_MACH_WAGO_PFC_AM35XX=y
+CONFIG_MACH_RADXA_ROCK=y
+CONFIG_MACH_PHYTEC_SOM_RK3288=y
+CONFIG_MACH_STM32MP13XX_DK=y
+CONFIG_MACH_STM32MP15XX_DKX=y
+CONFIG_MACH_LXA_MC1=y
+CONFIG_MACH_SEEED_ODYSSEY=y
+CONFIG_MACH_STM32MP15X_EV1=y
+CONFIG_MACH_PROTONIC_STM32MP1=y
+CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1=y
+CONFIG_MACH_VEXPRESS=y
+CONFIG_MACH_VIRT=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_PSCI=y
+CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_PROMPT="barebox> "
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_VERBOSE=y
+CONFIG_BOOTM_INITRD=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_BOOTM_OFTREE_UIMAGE=y
+CONFIG_BOOTM_AIMAGE=y
+CONFIG_BLSPEC=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_PBL_CONSOLE=y
+CONFIG_CONSOLE_RATP=y
+CONFIG_RATP_CMD_I2C=y
+CONFIG_RATP_CMD_GPIO=y
+CONFIG_PARTITION_DISK_EFI=y
+# CONFIG_PARTITION_DISK_EFI_GPT_NO_FORCE is not set
+# CONFIG_PARTITION_DISK_EFI_GPT_COMPARE is not set
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_REBOOT_MODE=y
+CONFIG_STATE=y
+CONFIG_BOOTCHOOSER=y
+CONFIG_RESET_SOURCE=y
+CONFIG_MACHINE_ID=y
+CONFIG_FASTBOOT_CMD_OEM=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_ARM_MMUINFO=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_EXTCSD=y
+CONFIG_CMD_FCB=y
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_BOOTCHOOSER=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_UBIFORMAT=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_MENUTREE=y
+CONFIG_CMD_SPLASH=y
+CONFIG_CMD_FBTEST=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_NANDTEST=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_USBGADGET=y
+CONFIG_CMD_WD=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_OF_DIFF=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_DISPLAY_TIMINGS=y
+CONFIG_CMD_OF_FIXUP_STATUS=y
+CONFIG_CMD_OF_OVERLAY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_STATE=y
+CONFIG_NET=y
+CONFIG_NET_NFS=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_FASTBOOT=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_AIODEV=y
+CONFIG_STM32_ADC=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_DRIVER_SERIAL_STM32=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_DRIVER_NET_CPSW=y
+CONFIG_DRIVER_NET_DAVINCI_EMAC=y
+CONFIG_DRIVER_NET_DESIGNWARE_STM32=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_DRIVER_NET_SMC91111=y
+CONFIG_MICREL_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_ASIX=y
+CONFIG_NET_USB_SMSC95XX=y
+CONFIG_DRIVER_SPI_OMAP3=y
+CONFIG_DRIVER_SPI_STM32=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_OMAP=y
+CONFIG_I2C_STM32=y
+CONFIG_I2C_MUX=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_DEVICE=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SST25L=y
+CONFIG_DRIVER_CFI=y
+CONFIG_NAND=y
+CONFIG_NAND_ALLOW_ERASE_BAD=y
+CONFIG_NAND_IMX=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_OMAP_GPMC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_DISK_AHCI=y
+CONFIG_DISK_AHCI_IMX=y
+CONFIG_DISK_INTF_PLATFORM_IDE=y
+CONFIG_DISK_PATA_IMX=y
+CONFIG_USB_HOST=y
+CONFIG_USB_IMX_CHIPIDEA=y
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_DWC2_GADGET=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DFU=y
+CONFIG_USB_GADGET_SERIAL=y
+CONFIG_USB_GADGET_FASTBOOT=y
+CONFIG_USB_MUSB=y
+CONFIG_USB_MUSB_AM335X=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_VIDEO=y
+CONFIG_DRIVER_VIDEO_FB_SSD1307=y
+CONFIG_DRIVER_VIDEO_STM32_LTDC=y
+CONFIG_DRIVER_VIDEO_IMX_IPUV3=y
+CONFIG_DRIVER_VIDEO_IMX_IPUV3_LVDS=y
+CONFIG_DRIVER_VIDEO_IMX_IPUV3_HDMI=y
+CONFIG_DRIVER_VIDEO_IMX_IPUV3_PARALLEL=y
+CONFIG_DRIVER_VIDEO_SIMPLEFB=y
+CONFIG_DRIVER_VIDEO_EDID=y
+CONFIG_DRIVER_VIDEO_BACKLIGHT=y
+CONFIG_DRIVER_VIDEO_BACKLIGHT_PWM=y
+CONFIG_DRIVER_VIDEO_SIMPLE_PANEL=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_DW=y
+CONFIG_MCI_DW_PIO=y
+CONFIG_MCI_BCM283X=y
+CONFIG_MCI_BCM283X_SDHOST=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_MCI_MMCI=y
+CONFIG_MCI_STM32_SDMMC2=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_MFD_DA9063=y
+CONFIG_MFD_MC34704=y
+CONFIG_MFD_MC9SDZ60=y
+CONFIG_MFD_STMPE=y
+CONFIG_MFD_STPMIC1=y
+CONFIG_MFD_STM32_TIMERS=y
+CONFIG_STATE_DRV=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_PWM=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_EEPROM_AT25=y
+CONFIG_EEPROM_AT24=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_SPECIALKEYS=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_POLLER=y
+CONFIG_WATCHDOG_IMX=y
+CONFIG_WATCHDOG_OMAP=y
+CONFIG_STM32_IWDG_WATCHDOG=y
+CONFIG_STPMIC1_WATCHDOG=y
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_PWM_STM32=y
+CONFIG_HWRNG=y
+CONFIG_HWRNG_STM32=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_MXS_APBH_DMA=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_RASPBERRYPI_EXP=y
+CONFIG_GPIO_STMPE=y
+CONFIG_PINCTRL_BCM283X=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_IMX_OCOTP_WRITE=y
+CONFIG_STM32_BSEC=y
+CONFIG_BUS_OMAP_GPMC=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED=y
+CONFIG_REGULATOR_STM32_PWR=y
+CONFIG_REGULATOR_STM32_VREFBUF=y
+CONFIG_REGULATOR_STPMIC1=y
+CONFIG_REGULATOR_ARM_SCMI=y
+CONFIG_REMOTEPROC=y
+CONFIG_STM32_REMOTEPROC=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_GENERIC_PHY=y
+CONFIG_USB_NOP_XCEIV=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_RESET_STM32=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_TFTP_MAX_WINDOW_SIZE=8
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_FS_UBIFS=y
+CONFIG_FS_UBIFS_COMPRESSION_LZO=y
+CONFIG_FS_UBIFS_COMPRESSION_ZLIB=y
+CONFIG_FS_UBIFS_COMPRESSION_ZSTD=y
+CONFIG_FS_BPKFS=y
+CONFIG_FS_UIMAGEFS=y
+CONFIG_FS_PSTORE=y
+CONFIG_FS_PSTORE_CONSOLE=y
+CONFIG_FS_PSTORE_RAMOOPS=y
+CONFIG_FS_SQUASHFS=y
+CONFIG_FS_RATP=y
+CONFIG_PNG=y
+CONFIG_DIGEST_SHA1_ARM=y
diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig
new file mode 100644
index 0000000000..39d5dd3fc1
--- /dev/null
+++ b/arch/arm/configs/multi_v8_defconfig
@@ -0,0 +1,274 @@
+CONFIG_ARCH_ARM64_VIRT=y
+CONFIG_ARCH_IMX=y
+CONFIG_ARCH_K3=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_MACH_KOENIGBAUER_ALPHAJET=y
+CONFIG_MACH_INNOCOMM_WB15=y
+CONFIG_MACH_KARO_QSXP_ML81=y
+CONFIG_MACH_MNT_REFORM=y
+CONFIG_MACH_NXP_IMX8MM_EVK=y
+CONFIG_MACH_NXP_IMX8MN_EVK=y
+CONFIG_MACH_NXP_IMX8MP_EVK=y
+CONFIG_MACH_NXP_IMX8MQ_EVK=y
+CONFIG_MACH_PHYTEC_SOM_IMX8MM=y
+CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y
+CONFIG_MACH_POLYHEX_DEBIX=y
+CONFIG_MACH_PROTONIC_IMX8M=y
+CONFIG_MACH_SKOV_IMX8MP=y
+CONFIG_MACH_TQ_MBA8MPXL=y
+CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP=y
+CONFIG_MACH_ZII_IMX8MQ_DEV=y
+CONFIG_MACH_TQMA93XX=y
+CONFIG_IMX_IIM=y
+CONFIG_ARCH_LAYERSCAPE_PPA=y
+CONFIG_MACH_LS1028ARDB=y
+CONFIG_MACH_LS1046ARDB=y
+CONFIG_MACH_TQMLS1046A=y
+CONFIG_MACH_BEAGLEPLAY=y
+CONFIG_MACH_RK3568_EVB=y
+CONFIG_MACH_RK3568_BPI_R2PRO=y
+CONFIG_MACH_PINE64_QUARTZ64=y
+CONFIG_MACH_RADXA_ROCK3=y
+CONFIG_MACH_RADXA_ROCK5=y
+CONFIG_MACH_RADXA_CM3=y
+CONFIG_MACH_XILINX_ZCU102=y
+CONFIG_MACH_XILINX_ZCU104=y
+CONFIG_MACH_XILINX_ZCU106=y
+CONFIG_64BIT=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_PSCI_CLIENT=y
+CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_PROMPT="barebox> "
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_VERBOSE=y
+CONFIG_BOOTM_INITRD=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_BOOTM_OFTREE_UIMAGE=y
+CONFIG_BOOTM_AIMAGE=y
+CONFIG_BLSPEC=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_PBL_CONSOLE=y
+CONFIG_CONSOLE_RATP=y
+CONFIG_PARTITION_DISK_EFI=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_STATE=y
+CONFIG_BOOTCHOOSER=y
+CONFIG_RESET_SOURCE=y
+CONFIG_MACHINE_ID=y
+CONFIG_FASTBOOT_SPARSE=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_ARM_MMUINFO=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MMC_EXTCSD=y
+CONFIG_CMD_POLLER=y
+CONFIG_CMD_SLICE=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_BOOTCHOOSER=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_LOGIN=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_MENUTREE=y
+CONFIG_CMD_PASSWD=y
+CONFIG_CMD_SPLASH=y
+CONFIG_CMD_FBTEST=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_USBGADGET=y
+CONFIG_CMD_WD=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_FIRMWARELOAD=y
+CONFIG_CMD_OF_DIFF=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_DISPLAY_TIMINGS=y
+CONFIG_CMD_OF_FIXUP_STATUS=y
+CONFIG_CMD_OF_OVERLAY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_NET=y
+CONFIG_NET_NFS=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_SNTP=y
+CONFIG_NET_FASTBOOT=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_OF_BAREBOX_ENV_IN_FS=y
+CONFIG_OF_OVERLAY_LIVE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_CADENCE=y
+CONFIG_DRIVER_SERIAL_LPUART32=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_DRIVER_NET_DESIGNWARE_IMX8=y
+CONFIG_DRIVER_NET_DESIGNWARE_ROCKCHIP=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_DRIVER_NET_FSL_ENETC=y
+CONFIG_DRIVER_NET_FSL_FMAN=y
+CONFIG_DRIVER_NET_MACB=y
+CONFIG_DRIVER_NET_VIRTIO=y
+CONFIG_DP83867_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_NET_DSA_MV88E6XXX=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_ASIX=y
+CONFIG_USB_NET_AX88179_178A=y
+CONFIG_NET_USB_SMSC95XX=y
+CONFIG_NET_USB_RTL8152=y
+CONFIG_DRIVER_SPI_FSL_QUADSPI=y
+CONFIG_DRIVER_SPI_IMX=y
+CONFIG_SPI_NXP_FLEXSPI=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_IMX_LPI2C=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_M25P80=y
+CONFIG_DRIVER_CFI=y
+CONFIG_CFI_BUFFER_WRITE=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_USB_HOST=y
+CONFIG_USB_IMX_CHIPIDEA=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_SERIAL=y
+CONFIG_USB_GADGET_FASTBOOT=y
+CONFIG_USB_GADGET_MASS_STORAGE=y
+CONFIG_VIDEO=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_DRIVER_VIDEO_BOCHS_PCI=y
+CONFIG_SOUND=y
+CONFIG_MCI=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_DW=y
+CONFIG_MCI_ROCKCHIP_DWCMSHC=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_MCI_ARASAN=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_MFD_ACT8846=y
+CONFIG_RAVE_SP_CORE=y
+CONFIG_MFD_PCA9450=y
+CONFIG_MFD_RK808=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_LED_PCA955X=y
+CONFIG_EEPROM_AT25=y
+CONFIG_EEPROM_AT24=y
+CONFIG_VIRTIO_INPUT=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_POLLER=y
+CONFIG_WATCHDOG_DW=y
+CONFIG_WATCHDOG_IMX=y
+CONFIG_WATCHDOG_IMXULP=y
+CONFIG_RAVE_SP_WATCHDOG=y
+CONFIG_HWRNG=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_ZYNQ=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_NVMEM_RMEM=y
+CONFIG_IMX_OCOTP_ELE=y
+CONFIG_RAVE_SP_EEPROM=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED=y
+CONFIG_REGULATOR_ARM_SCMI=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_RESET_IMX7=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_ECAM_GENERIC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_FIRMWARE_ZYNQMP_FPGA=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_GENERIC_PHY=y
+CONFIG_USB_NOP_XCEIV=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_TI_SCI_PM_DOMAINS=y
+CONFIG_NVMEM_REBOOT_MODE=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_MAILBOX=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_BPKFS=y
+CONFIG_FS_UIMAGEFS=y
+CONFIG_FS_PSTORE=y
+CONFIG_FS_PSTORE_CONSOLE=y
+CONFIG_FS_RATP=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_MISSING_FIRMWARE_ERROR is not set
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index c830cf2f09..6a436f3abd 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -28,7 +28,6 @@ CONFIG_BOOTM_INITRD=y
 CONFIG_BOOTM_OFTREE=y
 CONFIG_BOOTM_OFTREE_UIMAGE=y
 CONFIG_BLSPEC=y
-CONFIG_IMD_TARGET=y
 CONFIG_CONSOLE_ACTIVATE_NONE=y
 CONFIG_CONSOLE_ALLOW_COLOR=y
 CONFIG_PBL_CONSOLE=y
@@ -131,3 +130,4 @@ CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
 CONFIG_BZLIB=y
 CONFIG_LZO_DECOMPRESS=y
+CONFIG_IMD_TARGET=y
diff --git a/arch/arm/configs/neso_defconfig b/arch/arm/configs/neso_defconfig
deleted file mode 100644
index 7d6ab2818e..0000000000
--- a/arch/arm/configs/neso_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
-CONFIG_MACH_NESO=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x1000000
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SPLASH=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_TIME=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-CONFIG_NET_USB=y
-CONFIG_NET_USB_ASIX=y
-CONFIG_DRIVER_SPI_IMX=y
-CONFIG_MTD=y
-CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-CONFIG_NAND_IMX=y
-CONFIG_USB_HOST=y
-CONFIG_USB_EHCI=y
-CONFIG_USB_ULPI=y
-CONFIG_VIDEO=y
-CONFIG_DRIVER_VIDEO_IMX=y
-CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index bc19301249..b2816f563b 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -2,7 +2,6 @@ CONFIG_TEXT_BASE=0x03F80000
 CONFIG_ARCH_NOMADIK=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_PROMPT="Nomadik:"
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/omap3430_sdp3430_per_uart_defconfig b/arch/arm/configs/omap3430_sdp3430_per_uart_defconfig
index d43355cdf1..b41176342f 100644
--- a/arch/arm/configs/omap3430_sdp3430_per_uart_defconfig
+++ b/arch/arm/configs/omap3430_sdp3430_per_uart_defconfig
@@ -1,5 +1,5 @@
 CONFIG_TEXT_BASE=0x40200000
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_PROMPT="X-load 343x> "
 CONFIG_SHELL_SIMPLE=y
@@ -23,5 +23,4 @@ CONFIG_CMD_LOADB=y
 # CONFIG_CMD_CLEAR is not set
 # CONFIG_CMD_ECHO is not set
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
diff --git a/arch/arm/configs/omap3530_beagle_defconfig b/arch/arm/configs/omap3530_beagle_defconfig
index 5d09abf615..5bd6de0cc5 100644
--- a/arch/arm/configs/omap3530_beagle_defconfig
+++ b/arch/arm/configs/omap3530_beagle_defconfig
@@ -1,4 +1,4 @@
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_OMAP_MULTI_BOARDS=y
 CONFIG_MACH_BEAGLE=y
 CONFIG_THUMB2_BAREBOX=y
@@ -20,7 +20,6 @@ CONFIG_BOOTM_INITRD=y
 CONFIG_BOOTM_OFTREE=y
 CONFIG_BOOTM_OFTREE_UIMAGE=y
 CONFIG_BLSPEC=y
-CONFIG_IMD_TARGET=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_RESET_SOURCE=y
 CONFIG_DEBUG_LL=y
@@ -72,7 +71,6 @@ CONFIG_NET=y
 CONFIG_NET_NFS=y
 CONFIG_NET_NETCONSOLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_NET_USB=y
 CONFIG_NET_USB_ASIX=y
 CONFIG_NET_USB_SMSC95XX=y
@@ -96,3 +94,4 @@ CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
+CONFIG_IMD_TARGET=y
diff --git a/arch/arm/configs/omap3530_beagle_per_uart_defconfig b/arch/arm/configs/omap3530_beagle_per_uart_defconfig
index e4112b4910..3a38011f3d 100644
--- a/arch/arm/configs/omap3530_beagle_per_uart_defconfig
+++ b/arch/arm/configs/omap3530_beagle_per_uart_defconfig
@@ -1,5 +1,5 @@
 CONFIG_TEXT_BASE=0x40200000
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_PROMPT="X-load Beagle>"
 CONFIG_SHELL_SIMPLE=y
 # CONFIG_ERRNO_MESSAGES is not set
@@ -22,5 +22,4 @@ CONFIG_CMD_LOADB=y
 # CONFIG_CMD_CLEAR is not set
 # CONFIG_CMD_ECHO is not set
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
diff --git a/arch/arm/configs/omap3530_beagle_xload_defconfig b/arch/arm/configs/omap3530_beagle_xload_defconfig
index e9484ed852..a69989449d 100644
--- a/arch/arm/configs/omap3530_beagle_xload_defconfig
+++ b/arch/arm/configs/omap3530_beagle_xload_defconfig
@@ -1,4 +1,4 @@
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_OMAP3_USBBOOT=y
 CONFIG_OMAP_MULTI_BOARDS=y
@@ -17,17 +17,11 @@ CONFIG_SHELL_NONE=y
 # CONFIG_TIMESTAMP is not set
 CONFIG_CONSOLE_SIMPLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
 # CONFIG_MTD_WRITE is not set
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-# CONFIG_NAND_INFO is not set
-# CONFIG_NAND_BBT is not set
 CONFIG_NAND_OMAP_GPMC=y
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig
index 973acbff68..22ac4b66ec 100644
--- a/arch/arm/configs/omap3_evm_defconfig
+++ b/arch/arm/configs/omap3_evm_defconfig
@@ -1,5 +1,5 @@
 CONFIG_TEXT_BASE=0x40200000
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_MACH_OMAP3EVM=y
 CONFIG_AEABI=y
 CONFIG_PROMPT="OMAP3_EVM> "
@@ -21,5 +21,4 @@ CONFIG_CMD_RESET=y
 # CONFIG_CMD_RM is not set
 # CONFIG_CMD_RMDIR is not set
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
diff --git a/arch/arm/configs/omap_defconfig b/arch/arm/configs/omap_defconfig
index 59892cb231..13b630a978 100644
--- a/arch/arm/configs/omap_defconfig
+++ b/arch/arm/configs/omap_defconfig
@@ -1,4 +1,4 @@
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO=y
 CONFIG_BAREBOX_UPDATE_AM33XX_NAND=y
 CONFIG_BAREBOX_UPDATE_AM33XX_EMMC=y
@@ -6,6 +6,7 @@ CONFIG_OMAP_MULTI_BOARDS=y
 CONFIG_MACH_AFI_GF=y
 CONFIG_MACH_BEAGLE=y
 CONFIG_MACH_BEAGLEBONE=y
+CONFIG_MACH_MYIRTECH_X335X=y
 CONFIG_MACH_PHYTEC_SOM_AM335X=y
 CONFIG_MACH_VSCOM_BALTOS=y
 CONFIG_MACH_WAGO_PFC_AM35XX=y
@@ -46,6 +47,7 @@ CONFIG_CMD_GO=y
 CONFIG_CMD_LOADB=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_BOOTCHOOSER=y
 CONFIG_CMD_PARTITION=y
 CONFIG_CMD_UBIFORMAT=y
 CONFIG_CMD_EXPORT=y
@@ -93,13 +95,11 @@ CONFIG_CMD_OF_FIXUP_STATUS=y
 CONFIG_CMD_OFTREE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_STATE=y
-CONFIG_CMD_BOOTCHOOSER=y
 CONFIG_NET=y
 CONFIG_NET_NFS=y
 CONFIG_NET_NETCONSOLE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_DRIVER_NET_CPSW=y
 CONFIG_DRIVER_NET_DAVINCI_EMAC=y
 CONFIG_MICREL_PHY=y
diff --git a/arch/arm/configs/panda_defconfig b/arch/arm/configs/panda_defconfig
index 9c1efe168a..97118fb837 100644
--- a/arch/arm/configs/panda_defconfig
+++ b/arch/arm/configs/panda_defconfig
@@ -1,5 +1,5 @@
 CONFIG_TEXT_BASE=0x8f000000
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_MACH_PANDA=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@@ -62,7 +62,6 @@ CONFIG_CMD_TIME=y
 CONFIG_NET=y
 CONFIG_NET_NETCONSOLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_NET_USB=y
 CONFIG_NET_USB_SMSC95XX=y
 # CONFIG_SPI is not set
diff --git a/arch/arm/configs/panda_xload_defconfig b/arch/arm/configs/panda_xload_defconfig
index e3d87c42dd..9203734dd6 100644
--- a/arch/arm/configs/panda_xload_defconfig
+++ b/arch/arm/configs/panda_xload_defconfig
@@ -1,5 +1,5 @@
 CONFIG_TEXT_BASE=0x40300000
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 # CONFIG_OMAP_GPMC is not set
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_MACH_PANDA=y
@@ -12,7 +12,6 @@ CONFIG_SHELL_NONE=y
 # CONFIG_TIMESTAMP is not set
 CONFIG_CONSOLE_SIMPLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
diff --git a/arch/arm/configs/phytec-phycard-omap3-xload_defconfig b/arch/arm/configs/phytec-phycard-omap3-xload_defconfig
index 6eab808f7c..24c50694d1 100644
--- a/arch/arm/configs/phytec-phycard-omap3-xload_defconfig
+++ b/arch/arm/configs/phytec-phycard-omap3-xload_defconfig
@@ -1,11 +1,11 @@
 CONFIG_TEXT_BASE=0x40200000
-CONFIG_ARCH_OMAP=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x0000f000
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_MACH_PCAAL1=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_ARM_EXCEPTIONS is not set
 CONFIG_ENVIRONMENT_VARIABLES=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x0000f000
 CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x0000f000
 CONFIG_STACK_SIZE=0xc00
 CONFIG_MALLOC_SIZE=0x1000000
@@ -17,16 +17,11 @@ CONFIG_SHELL_NONE=y
 # CONFIG_TIMESTAMP is not set
 CONFIG_CONSOLE_SIMPLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
 # CONFIG_MTD_WRITE is not set
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-# CONFIG_NAND_BBT is not set
 CONFIG_NAND_OMAP_GPMC=y
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
diff --git a/arch/arm/configs/phytec-phycard-omap3_defconfig b/arch/arm/configs/phytec-phycard-omap3_defconfig
index 6cc1c1e80b..aede243c91 100644
--- a/arch/arm/configs/phytec-phycard-omap3_defconfig
+++ b/arch/arm/configs/phytec-phycard-omap3_defconfig
@@ -1,11 +1,10 @@
 CONFIG_TEXT_BASE=0x85000000
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_MACH_PCAAL1=y
 CONFIG_AEABI=y
 CONFIG_MALLOC_SIZE=0x1000000
 CONFIG_EXPERIMENTAL=y
 CONFIG_PROMPT="phyCARD-A-L1 >"
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
@@ -54,7 +53,6 @@ CONFIG_NET_NFS=y
 CONFIG_NET_NETCONSOLE=y
 CONFIG_NET_RESOLV=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_DRIVER_NET_SMC911X=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
diff --git a/arch/arm/configs/phytec-phycard-omap4-xload_defconfig b/arch/arm/configs/phytec-phycard-omap4-xload_defconfig
index af3ada6343..6c14e4635f 100644
--- a/arch/arm/configs/phytec-phycard-omap4-xload_defconfig
+++ b/arch/arm/configs/phytec-phycard-omap4-xload_defconfig
@@ -1,5 +1,5 @@
 CONFIG_TEXT_BASE=0x40300000
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_MACH_PCAAXL2=y
 CONFIG_THUMB2_BAREBOX=y
@@ -13,17 +13,11 @@ CONFIG_SHELL_NONE=y
 # CONFIG_TIMESTAMP is not set
 CONFIG_CONSOLE_SIMPLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
 # CONFIG_MTD_WRITE is not set
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-# CONFIG_NAND_INFO is not set
-# CONFIG_NAND_BBT is not set
 CONFIG_NAND_OMAP_GPMC=y
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
diff --git a/arch/arm/configs/phytec-phycard-omap4_defconfig b/arch/arm/configs/phytec-phycard-omap4_defconfig
index 2f3970725d..9614b29422 100644
--- a/arch/arm/configs/phytec-phycard-omap4_defconfig
+++ b/arch/arm/configs/phytec-phycard-omap4_defconfig
@@ -1,5 +1,5 @@
 CONFIG_TEXT_BASE=0x8f000000
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_MACH_PCAAXL2=y
 CONFIG_AEABI=y
 CONFIG_ARM_UNWIND=y
@@ -7,7 +7,6 @@ CONFIG_MMU=y
 CONFIG_MALLOC_SIZE=0x2000000
 CONFIG_KALLSYMS=y
 CONFIG_PROMPT="barebox> "
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
@@ -36,7 +35,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_NET=y
 CONFIG_NET_NFS=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_DRIVER_NET_KS8851_MLL=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
diff --git a/arch/arm/configs/phytec-phycore-imx31_defconfig b/arch/arm/configs/phytec-phycore-imx31_defconfig
deleted file mode 100644
index a6bc28c4c7..0000000000
--- a/arch/arm/configs/phytec-phycore-imx31_defconfig
+++ /dev/null
@@ -1,82 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_CACHE_L2X0=y
-CONFIG_MACH_PCM037=y
-CONFIG_IMX_IIM=y
-CONFIG_IMX_IIM_FUSE_BLOW=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x01000000
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-imx31/env"
-CONFIG_RESET_SOURCE=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_LN=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_MSLEEP=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MIITOOL=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_BAREBOX_UPDATE=y
-CONFIG_CMD_TIME=y
-CONFIG_NET=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_DRIVER_NET_SMC911X=y
-CONFIG_NET_USB=y
-CONFIG_NET_USB_ASIX=y
-CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-CONFIG_CFI_BUFFER_WRITE=y
-CONFIG_NAND=y
-CONFIG_NAND_IMX=y
-CONFIG_USB_HOST=y
-CONFIG_USB_EHCI=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_NFS=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/phytec-phycore-omap4460-xload-mmc_defconfig b/arch/arm/configs/phytec-phycore-omap4460-xload-mmc_defconfig
index 61f85c837f..327d212e18 100644
--- a/arch/arm/configs/phytec-phycore-omap4460-xload-mmc_defconfig
+++ b/arch/arm/configs/phytec-phycore-omap4460-xload-mmc_defconfig
@@ -1,12 +1,12 @@
 CONFIG_TEXT_BASE=0x40300000
-CONFIG_ARCH_OMAP=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xC000
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_MACH_PCM049=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_ARM_EXCEPTIONS is not set
 # CONFIG_MEMINFO is not set
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xC000
 CONFIG_MALLOC_SIZE=0x2000000
 CONFIG_MALLOC_DUMMY=y
 CONFIG_PROMPT="barebox> "
@@ -15,7 +15,6 @@ CONFIG_SHELL_NONE=y
 # CONFIG_TIMESTAMP is not set
 CONFIG_CONSOLE_SIMPLE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
diff --git a/arch/arm/configs/phytec-phycore-omap4460-xload-nand_defconfig b/arch/arm/configs/phytec-phycore-omap4460-xload-nand_defconfig
index 77f124b33f..237fa48cfb 100644
--- a/arch/arm/configs/phytec-phycore-omap4460-xload-nand_defconfig
+++ b/arch/arm/configs/phytec-phycore-omap4460-xload-nand_defconfig
@@ -1,12 +1,12 @@
 CONFIG_TEXT_BASE=0x40300000
-CONFIG_ARCH_OMAP=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xC000
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_MACH_PCM049=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_ARM_EXCEPTIONS is not set
 # CONFIG_MEMINFO is not set
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xC000
 CONFIG_MALLOC_SIZE=0x2000000
 CONFIG_MALLOC_DUMMY=y
 CONFIG_PROMPT="barebox> "
@@ -16,17 +16,11 @@ CONFIG_SHELL_NONE=y
 CONFIG_CONSOLE_SIMPLE=y
 CONFIG_PARTITION=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
 # CONFIG_MTD_WRITE is not set
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-# CONFIG_NAND_INFO is not set
-# CONFIG_NAND_BBT is not set
 CONFIG_NAND_OMAP_GPMC=y
 # CONFIG_FS_RAMFS is not set
 # CONFIG_FS_DEVFS is not set
diff --git a/arch/arm/configs/phytec-phycore-omap4460_defconfig b/arch/arm/configs/phytec-phycore-omap4460_defconfig
index e65a76570b..6a3ebea244 100644
--- a/arch/arm/configs/phytec-phycore-omap4460_defconfig
+++ b/arch/arm/configs/phytec-phycore-omap4460_defconfig
@@ -1,14 +1,13 @@
 CONFIG_TEXT_BASE=0x8f000000
-CONFIG_ARCH_OMAP=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x80000
+CONFIG_ARCH_OMAP_SINGLE=y
 CONFIG_MACH_PCM049=y
 CONFIG_AEABI=y
 CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x80000
 CONFIG_MALLOC_SIZE=0x2000000
 CONFIG_KALLSYMS=y
 CONFIG_PROMPT="barebox> "
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
@@ -49,7 +48,6 @@ CONFIG_CMD_TIME=y
 CONFIG_NET=y
 CONFIG_NET_NFS=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_DRIVER_NET_SMC911X=y
 CONFIG_SMSC_PHY=y
 # CONFIG_SPI is not set
diff --git a/arch/arm/configs/pm9261_defconfig b/arch/arm/configs/pm9261_defconfig
index 61595ed506..228b4234f6 100644
--- a/arch/arm/configs/pm9261_defconfig
+++ b/arch/arm/configs/pm9261_defconfig
@@ -1,8 +1,8 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9261=y
 CONFIG_MACH_PM9261=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_PROMPT="PM9261:"
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/pm9263_defconfig b/arch/arm/configs/pm9263_defconfig
index b0eaf9f3e0..2b7149c058 100644
--- a/arch/arm/configs/pm9263_defconfig
+++ b/arch/arm/configs/pm9263_defconfig
@@ -1,6 +1,6 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/pm9g45_defconfig b/arch/arm/configs/pm9g45_defconfig
index c63a1c070b..00f3eeca1c 100644
--- a/arch/arm/configs/pm9g45_defconfig
+++ b/arch/arm/configs/pm9g45_defconfig
@@ -1,12 +1,11 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G45=y
 CONFIG_MACH_PM9G45=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_MALLOC_TLSF=y
-CONFIG_GLOB=y
 CONFIG_GLOB_SORT=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -43,9 +42,6 @@ CONFIG_DRIVER_NET_MACB=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DISK_ATA=y
 CONFIG_USB_HOST=y
diff --git a/arch/arm/configs/qemu_virt64_defconfig b/arch/arm/configs/qemu_virt64_defconfig
deleted file mode 100644
index 17509ce9d6..0000000000
--- a/arch/arm/configs/qemu_virt64_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_ARCH_ARM64_VIRT=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_MMU=y
-# CONFIG_MMU_EARLY is not set
-CONFIG_KALLSYMS=y
-CONFIG_PROMPT=""
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_IMD=y
-CONFIG_CONSOLE_ACTIVATE_NONE=y
-CONFIG_CONSOLE_ALLOW_COLOR=y
-CONFIG_PARTITION_DISK_EFI=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_POLLER=y
-CONFIG_STATE=y
-CONFIG_BOOTCHOOSER=y
-CONFIG_RESET_SOURCE=y
-CONFIG_MACHINE_ID=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_BOOTCHOOSER=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_SHA256SUM=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_LOGIN=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_PASSWD=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_DETECT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_BAREBOX_UPDATE=y
-CONFIG_CMD_OF_DIFF=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OF_DISPLAY_TIMINGS=y
-CONFIG_CMD_OF_FIXUP_STATUS=y
-CONFIG_CMD_OF_OVERLAY=y
-CONFIG_CMD_OFTREE=y
-CONFIG_CMD_STATE=y
-CONFIG_OF_BAREBOX_DRIVERS=y
-CONFIG_OF_BAREBOX_ENV_IN_FS=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_VIRTIO_CONSOLE=y
-# CONFIG_SPI is not set
-CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-CONFIG_CFI_BUFFER_WRITE=y
-CONFIG_DISK=y
-CONFIG_DISK_WRITE=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_HWRNG=y
-CONFIG_HW_RANDOM_VIRTIO=y
-# CONFIG_PINCTRL is not set
-CONFIG_VIRTIO_MMIO=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_FAT=y
-CONFIG_FS_PSTORE=y
-CONFIG_FS_PSTORE_CONSOLE=y
-CONFIG_DIGEST_SHA1_GENERIC=y
diff --git a/arch/arm/configs/qil_a9260_128mib_defconfig b/arch/arm/configs/qil_a9260_128mib_defconfig
deleted file mode 100644
index 3124a71ca9..0000000000
--- a/arch/arm/configs/qil_a9260_128mib_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_MACH_QIL_A9260=y
-CONFIG_AT91_HAVE_SRAM_128M=y
-CONFIG_CALAO_MB_QIL_A9260=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_MMU=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_PROMPT="USB-9G20:"
-CONFIG_GLOB=y
-CONFIG_PROMPT_HUSH_PS2="y"
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-# CONFIG_CMD_ARM_CPUINFO is not set
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_DRIVER_NET_MACB=y
-# CONFIG_SPI is not set
-CONFIG_MTD=y
-# CONFIG_MTD_OOB_DEVICE is not set
-CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DFU=y
-CONFIG_USB_GADGET_SERIAL=y
-CONFIG_MCI=y
-CONFIG_MCI_ATMEL=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/qil_a9260_defconfig b/arch/arm/configs/qil_a9260_defconfig
index 3f5eedb449..c08e59e940 100644
--- a/arch/arm/configs/qil_a9260_defconfig
+++ b/arch/arm/configs/qil_a9260_defconfig
@@ -1,14 +1,13 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_QIL_A9260=y
 CONFIG_CALAO_MB_QIL_A9260=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_PROMPT="USB-9G20:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -57,9 +56,6 @@ CONFIG_DRIVER_NET_MACB=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/qil_a9g20_128mib_defconfig b/arch/arm/configs/qil_a9g20_128mib_defconfig
deleted file mode 100644
index 0b2da05838..0000000000
--- a/arch/arm/configs/qil_a9g20_128mib_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_ARCH_AT91SAM9G20=y
-CONFIG_MACH_QIL_A9G20=y
-CONFIG_AT91_HAVE_SRAM_128M=y
-CONFIG_CALAO_MB_QIL_A9260=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_MMU=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_PROMPT="USB-9G20:"
-CONFIG_GLOB=y
-CONFIG_PROMPT_HUSH_PS2="y"
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-# CONFIG_CMD_ARM_CPUINFO is not set
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_DRIVER_NET_MACB=y
-# CONFIG_SPI is not set
-CONFIG_MTD=y
-# CONFIG_MTD_OOB_DEVICE is not set
-CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DFU=y
-CONFIG_USB_GADGET_SERIAL=y
-CONFIG_MCI=y
-CONFIG_MCI_ATMEL=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/qil_a9g20_defconfig b/arch/arm/configs/qil_a9g20_defconfig
index 5162ecab62..03b96684e4 100644
--- a/arch/arm/configs/qil_a9g20_defconfig
+++ b/arch/arm/configs/qil_a9g20_defconfig
@@ -1,14 +1,13 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_QIL_A9G20=y
 CONFIG_CALAO_MB_QIL_A9260=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_PROMPT="USB-9G20:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -57,9 +56,6 @@ CONFIG_DRIVER_NET_MACB=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/rk3288_defconfig b/arch/arm/configs/rockchip_v7a_defconfig
index 156e07fcb1..5dc41bff35 100644
--- a/arch/arm/configs/rk3288_defconfig
+++ b/arch/arm/configs/rockchip_v7a_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_RK3288=y
+CONFIG_CACHE_L2X0=y
+CONFIG_MACH_RADXA_ROCK=y
 CONFIG_MACH_PHYTEC_SOM_RK3288=y
+CONFIG_BOARD_ARM_GENERIC_DT=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_BOARD_APPEND_ATAG=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@@ -21,10 +23,8 @@ CONFIG_BOOTM_OFTREE=y
 CONFIG_BOOTM_OFTREE_UIMAGE=y
 CONFIG_BOOTM_AIMAGE=y
 CONFIG_CONSOLE_ACTIVATE_NONE=y
-CONFIG_DEFAULT_COMPRESSION_LZO=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_RESET_SOURCE=y
-CONFIG_DEBUG_LL=y
 CONFIG_CMD_DMESG=y
 CONFIG_LONGHELP=y
 CONFIG_CMD_IOMEM=y
diff --git a/arch/arm/configs/rockchip_v8_defconfig b/arch/arm/configs/rockchip_v8_defconfig
new file mode 100644
index 0000000000..35ff8963a7
--- /dev/null
+++ b/arch/arm/configs/rockchip_v8_defconfig
@@ -0,0 +1,153 @@
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_MACH_RK3568_EVB=y
+CONFIG_MACH_RK3568_BPI_R2PRO=y
+CONFIG_MACH_PINE64_QUARTZ64=y
+CONFIG_MACH_RADXA_ROCK3=y
+CONFIG_MACH_RADXA_ROCK5=y
+CONFIG_MACH_RADXA_CM3=y
+CONFIG_BOARD_ARM_GENERIC_DT=y
+CONFIG_64BIT=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_PSCI_CLIENT=y
+CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_PROMPT="barebox> "
+CONFIG_BAUDRATE=1500000
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_VERBOSE=y
+CONFIG_BOOTM_INITRD=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_BOOTM_OFTREE_UIMAGE=y
+CONFIG_BOOTM_AIMAGE=y
+CONFIG_BLSPEC=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_PBL_CONSOLE=y
+CONFIG_PARTITION_DISK_EFI=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_STATE=y
+CONFIG_BOOTCHOOSER=y
+CONFIG_RESET_SOURCE=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_BOOTCHOOSER=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_USBGADGET=y
+CONFIG_CMD_WD=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_OF_DIFF=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_DISPLAY_TIMINGS=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_NET=y
+CONFIG_NET_NFS=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_DESIGNWARE_ROCKCHIP=y
+CONFIG_DRIVER_NET_RTL8169=y
+CONFIG_SMSC_PHY=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_ASIX=y
+CONFIG_USB_NET_AX88179_178A=y
+CONFIG_NET_USB_SMSC95XX=y
+CONFIG_NET_USB_RTL8152=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_RK3X=y
+CONFIG_USB_HOST=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DFU=y
+CONFIG_USB_GADGET_SERIAL=y
+CONFIG_USB_GADGET_FASTBOOT=y
+CONFIG_USB_GADGET_MASS_STORAGE=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_DW=y
+CONFIG_MCI_ROCKCHIP_DWCMSHC=y
+CONFIG_MCI_ARASAN=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_MFD_ACT8846=y
+CONFIG_MFD_RK808=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_POLLER=y
+CONFIG_WATCHDOG_DW=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED=y
+CONFIG_REGULATOR_ARM_SCMI=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_PCI_ROCKCHIP=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_GENERIC_PHY=y
+CONFIG_USB_NOP_XCEIV=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_FS_BPKFS=y
+CONFIG_FS_UIMAGEFS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_MISSING_FIRMWARE_ERROR is not set
diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index f42b8819af..500c92a821 100644
--- a/arch/arm/configs/rpi_defconfig
+++ b/arch/arm/configs/rpi_defconfig
@@ -3,6 +3,7 @@ CONFIG_MACH_RPI=y
 CONFIG_MACH_RPI2=y
 CONFIG_MACH_RPI3=y
 CONFIG_MACH_RPI_CM3=y
+CONFIG_BOARD_ARM_GENERIC_DT=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
@@ -23,7 +24,6 @@ CONFIG_BOOTM_OFTREE=y
 CONFIG_BLSPEC=y
 CONFIG_CONSOLE_ALLOW_COLOR=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH=""
 CONFIG_CMD_DMESG=y
 CONFIG_LONGHELP=y
 CONFIG_CMD_IOMEM=y
@@ -80,8 +80,11 @@ CONFIG_CMD_TIME=y
 CONFIG_NET=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_BCMGENET=y
 CONFIG_NET_USB=y
 CONFIG_NET_USB_SMSC95XX=y
+CONFIG_I2C=y
+CONFIG_I2C_BCM283X=y
 CONFIG_USB_HOST=y
 CONFIG_USB_DWC2_HOST=y
 CONFIG_MCI=y
@@ -96,9 +99,13 @@ CONFIG_WATCHDOG_BCM2835=y
 CONFIG_GPIO_RASPBERRYPI_EXP=y
 CONFIG_PINCTRL_BCM283X=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED=y
+CONFIG_GENERIC_PHY=y
+CONFIG_USB_NOP_XCEIV=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_TFTP=y
 CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
+CONFIG_ZLIB=y
diff --git a/arch/arm/configs/rk3188_defconfig b/arch/arm/configs/rpi_v8a_defconfig
index 318cd9de42..39754f025e 100644
--- a/arch/arm/configs/rk3188_defconfig
+++ b/arch/arm/configs/rpi_v8a_defconfig
@@ -1,36 +1,36 @@
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_CACHE_L2X0=y
-CONFIG_MACH_RADXA_ROCK=y
-CONFIG_THUMB2_BAREBOX=y
-CONFIG_ARM_BOARD_APPEND_ATAG=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_MACH_RPI3=y
+CONFIG_MACH_RPI_CM3=y
+CONFIG_MACH_RPI4=y
+CONFIG_64BIT=y
+CONFIG_IMAGE_COMPRESSION_NONE=y
 CONFIG_MMU=y
 CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
-CONFIG_RELOCATABLE=y
-CONFIG_PROMPT="radxa-rock:"
+CONFIG_PROMPT="R-Pi> "
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
 CONFIG_BOOTM_SHOW_TYPE=y
 CONFIG_BOOTM_VERBOSE=y
 CONFIG_BOOTM_INITRD=y
 CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_BOOTM_AIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_NONE=y
-CONFIG_DEFAULT_COMPRESSION_LZO=y
+CONFIG_BLSPEC=y
+CONFIG_CONSOLE_ACTIVATE_ALL=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_PBL_CONSOLE=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/radxa-rock/env"
 CONFIG_CMD_DMESG=y
 CONFIG_LONGHELP=y
 CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
 CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_ARM_MMUINFO=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_GO=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_UIMAGE=y
 CONFIG_CMD_PARTITION=y
@@ -41,58 +41,72 @@ CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_MAGICVAR=y
 CONFIG_CMD_MAGICVAR_HELP=y
 CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_CMP=y
 CONFIG_CMD_FILETYPE=y
 CONFIG_CMD_LN=y
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SHA224SUM=y
 CONFIG_CMD_SHA256SUM=y
 CONFIG_CMD_UNCOMPRESS=y
 CONFIG_CMD_LET=y
 CONFIG_CMD_MSLEEP=y
-CONFIG_CMD_READF=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MIITOOL=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_EDIT=y
+CONFIG_CMD_LOGIN=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_PASSWD=y
 CONFIG_CMD_READLINE=y
 CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
 CONFIG_CMD_MM=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DETECT=y
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_WD=y
 CONFIG_CMD_OF_NODE=y
 CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OF_DISPLAY_TIMINGS=y
 CONFIG_CMD_OFTREE=y
 CONFIG_CMD_TIME=y
 CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_OFDEVICE=y
-CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_NET_ARC_EMAC=y
-CONFIG_SMSC_PHY=y
-CONFIG_I2C_GPIO=y
+CONFIG_DRIVER_NET_BCMGENET=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_SMSC95XX=y
+CONFIG_I2C=y
+CONFIG_I2C_BCM283X=y
+CONFIG_USB_HOST=y
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_DWC2_GADGET=y
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_AUTOSTART is not set
 CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
-CONFIG_MCI_MMC_BOOT_PARTITIONS=y
-CONFIG_MCI_DW=y
-CONFIG_MCI_DW_PIO=y
+CONFIG_MCI_BCM283X=y
+CONFIG_MCI_BCM283X_SDHOST=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_BCM2835=y
+CONFIG_GPIO_RASPBERRYPI_EXP=y
+CONFIG_PINCTRL_BCM283X=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED=y
 CONFIG_GENERIC_PHY=y
-CONFIG_FS_CRAMFS=y
+CONFIG_USB_NOP_XCEIV=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_TFTP=y
 CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
-CONFIG_FS_BPKFS=y
-CONFIG_FS_UIMAGEFS=y
-CONFIG_LZO_DECOMPRESS=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_ZLIB=y
diff --git a/arch/arm/configs/sama5d3_xplained_defconfig b/arch/arm/configs/sama5d3_xplained_defconfig
deleted file mode 100644
index 498d5af4b7..0000000000
--- a/arch/arm/configs/sama5d3_xplained_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_TEXT_BASE=0x26f00000
-CONFIG_ARCH_SAMA5D3=y
-CONFIG_MACH_SAMA5D3_XPLAINED=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0xA00000
-CONFIG_EXPERIMENTAL=y
-CONFIG_MALLOC_TLSF=y
-CONFIG_PROMPT="A5D3_XPLD:"
-CONFIG_GLOB=y
-CONFIG_PROMPT_HUSH_PS2="y"
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-# CONFIG_CMD_ARM_CPUINFO is not set
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_MIITOOL=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SPLASH=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_DHCP=y
-CONFIG_DRIVER_NET_MACB=y
-CONFIG_MICREL_PHY=y
-# CONFIG_SPI is not set
-CONFIG_I2C=y
-CONFIG_MTD=y
-# CONFIG_MTD_OOB_DEVICE is not set
-CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_NAND_ATMEL_PMECC=y
-CONFIG_VIDEO=y
-CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
-CONFIG_MCI_ATMEL=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_PNG=y
diff --git a/arch/arm/configs/sama5d3xek_defconfig b/arch/arm/configs/sama5d3xek_defconfig
index 54784cc7ad..c868bd0daf 100644
--- a/arch/arm/configs/sama5d3xek_defconfig
+++ b/arch/arm/configs/sama5d3xek_defconfig
@@ -1,15 +1,14 @@
 CONFIG_TEXT_BASE=0x26f00000
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_SAMA5D3=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000
 CONFIG_MALLOC_SIZE=0xA00000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="A5D3X-EK:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -63,9 +62,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_MTD_M25P80=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_NAND_ATMEL_PMECC=y
 CONFIG_VIDEO=y
diff --git a/arch/arm/configs/sama5d4_xplained_defconfig b/arch/arm/configs/sama5d4_xplained_defconfig
index 2f232eeac7..90a45b97c2 100644
--- a/arch/arm/configs/sama5d4_xplained_defconfig
+++ b/arch/arm/configs/sama5d4_xplained_defconfig
@@ -1,11 +1,11 @@
 CONFIG_TEXT_BASE=0x26f00000
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_SAMA5D4=y
 CONFIG_MACH_SAMA5D4_XPLAINED=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000
 CONFIG_MALLOC_SIZE=0xA00000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
@@ -64,8 +64,6 @@ CONFIG_MTD=y
 CONFIG_MTD_RAW_DEVICE=y
 CONFIG_MTD_M25P80=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_NAND_ATMEL_PMECC=y
 CONFIG_VIDEO=y
diff --git a/arch/arm/configs/sama5d4ek_defconfig b/arch/arm/configs/sama5d4ek_defconfig
index 04f080af0a..ba06991c4a 100644
--- a/arch/arm/configs/sama5d4ek_defconfig
+++ b/arch/arm/configs/sama5d4ek_defconfig
@@ -1,10 +1,10 @@
 CONFIG_TEXT_BASE=0x26f00000
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_SAMA5D4=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000
 CONFIG_MALLOC_SIZE=0xA00000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
@@ -63,8 +63,6 @@ CONFIG_MTD=y
 CONFIG_MTD_RAW_DEVICE=y
 CONFIG_MTD_M25P80=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_SOFT is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_NAND_ATMEL_PMECC=y
 CONFIG_VIDEO=y
diff --git a/arch/arm/configs/socfpga-arria10_defconfig b/arch/arm/configs/socfpga-arria10_defconfig
index a37bae6217..8c19b48450 100644
--- a/arch/arm/configs/socfpga-arria10_defconfig
+++ b/arch/arm/configs/socfpga-arria10_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARCH_SOCFPGA=y
+CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1=y
 CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@@ -16,7 +17,6 @@ CONFIG_BOOTM_SHOW_TYPE=y
 CONFIG_BOOTM_VERBOSE=y
 CONFIG_BOOTM_INITRD=y
 CONFIG_BOOTM_OFTREE=y
-CONFIG_DEFAULT_COMPRESSION_LZO=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_STATE=y
 CONFIG_LONGHELP=y
@@ -65,7 +65,6 @@ CONFIG_NET_NETCONSOLE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_OF_BAREBOX_ENV_IN_FS=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_NET_DESIGNWARE=y
 CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA=y
 CONFIG_MICREL_PHY=y
 # CONFIG_SPI is not set
diff --git a/arch/arm/configs/socfpga-xload-2_defconfig b/arch/arm/configs/socfpga-xload-2_defconfig
index 66cc777a7d..78b07aae5b 100644
--- a/arch/arm/configs/socfpga-xload-2_defconfig
+++ b/arch/arm/configs/socfpga-xload-2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARCH_SOCFPGA_XLOAD=y
 CONFIG_MACH_SOCFPGA_ALTERA_SOCDK=y
 CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
+CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 # CONFIG_ARM_EXCEPTIONS is not set
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 2509ad0b42..0050dd2e4f 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -1,6 +1,10 @@
 CONFIG_ARCH_SOCFPGA=y
+CONFIG_MACH_SOCFPGA_ALTERA_SOCDK=y
 CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
+CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1=y
+CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES=y
 CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
+CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO=y
 CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@@ -71,7 +75,6 @@ CONFIG_NET_NETCONSOLE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_OF_BAREBOX_ENV_IN_FS=y
 CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_NET_DESIGNWARE=y
 CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA=y
 CONFIG_MTD=y
 CONFIG_NAND=y
diff --git a/arch/arm/configs/stm32mp_defconfig b/arch/arm/configs/stm32mp_defconfig
index 49041b1f48..df73102ba1 100644
--- a/arch/arm/configs/stm32mp_defconfig
+++ b/arch/arm/configs/stm32mp_defconfig
@@ -1,8 +1,12 @@
 CONFIG_ARCH_STM32MP=y
+CONFIG_MACH_STM32MP13XX_DK=y
 CONFIG_MACH_STM32MP15XX_DKX=y
 CONFIG_MACH_LXA_MC1=y
 CONFIG_MACH_SEEED_ODYSSEY=y
 CONFIG_MACH_STM32MP15X_EV1=y
+CONFIG_MACH_PROTONIC_STM32MP1=y
+CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1=y
+CONFIG_BOARD_ARM_GENERIC_DT=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_BOARD_APPEND_ATAG=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@@ -82,6 +86,7 @@ CONFIG_CMD_FLASH=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_LED=y
 CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_WD=y
 CONFIG_CMD_BAREBOX_UPDATE=y
 CONFIG_CMD_OF_DIFF=y
@@ -97,28 +102,36 @@ CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_AIODEV=y
 CONFIG_STM32_ADC=y
 CONFIG_DRIVER_SERIAL_STM32=y
-CONFIG_DRIVER_NET_DESIGNWARE_EQOS=y
 CONFIG_DRIVER_NET_DESIGNWARE_STM32=y
 CONFIG_AT803X_PHY=y
 CONFIG_MICREL_PHY=y
 CONFIG_REALTEK_PHY=y
-# CONFIG_SPI is not set
+CONFIG_DRIVER_SPI_STM32=y
 CONFIG_I2C=y
 CONFIG_I2C_STM32=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SST25L=y
 CONFIG_USB_HOST=y
 CONFIG_USB_DWC2_HOST=y
 CONFIG_USB_DWC2_GADGET=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_ONBOARD_HUB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
 CONFIG_USB_GADGET_SERIAL=y
 CONFIG_USB_GADGET_FASTBOOT=y
 CONFIG_VIDEO=y
+CONFIG_DRIVER_VIDEO_FB_SSD1307=y
+CONFIG_DRIVER_VIDEO_STM32_LTDC=y
 CONFIG_DRIVER_VIDEO_BACKLIGHT=y
 CONFIG_DRIVER_VIDEO_SIMPLE_PANEL=y
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
 CONFIG_MCI_MMC_BOOT_PARTITIONS=y
 CONFIG_MCI_STM32_SDMMC2=y
+CONFIG_COMMON_CLK_SCMI=y
 CONFIG_MFD_STPMIC1=y
 CONFIG_MFD_STM32_TIMERS=y
 CONFIG_LED=y
@@ -126,6 +139,7 @@ CONFIG_LED_GPIO=y
 CONFIG_LED_PWM=y
 CONFIG_LED_GPIO_OF=y
 CONFIG_LED_TRIGGERS=y
+CONFIG_EEPROM_AT25=y
 CONFIG_EEPROM_AT24=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_SPECIALKEYS=y
@@ -143,12 +157,14 @@ CONFIG_REGULATOR_FIXED=y
 CONFIG_REGULATOR_STM32_PWR=y
 CONFIG_REGULATOR_STM32_VREFBUF=y
 CONFIG_REGULATOR_STPMIC1=y
+CONFIG_REGULATOR_ARM_SCMI=y
 CONFIG_REMOTEPROC=y
 CONFIG_STM32_REMOTEPROC=y
-CONFIG_RESET_STM32=y
+CONFIG_ARM_SCMI_PROTOCOL=y
 CONFIG_GENERIC_PHY=y
 CONFIG_PHY_STM32_USBPHYC=y
 CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_RESET_STM32=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_TFTP=y
 CONFIG_FS_NFS=y
diff --git a/arch/arm/configs/telit_evk_pro3_defconfig b/arch/arm/configs/telit_evk_pro3_defconfig
index 3bf5968bf5..298401a30d 100644
--- a/arch/arm/configs/telit_evk_pro3_defconfig
+++ b/arch/arm/configs/telit_evk_pro3_defconfig
@@ -1,10 +1,10 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_GE863=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_PROMPT="EVK-PRO3:"
 CONFIG_PROMPT_HUSH_PS2="y"
@@ -51,9 +51,6 @@ CONFIG_DRIVER_NET_MACB=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/tny_a9260_defconfig b/arch/arm/configs/tny_a9260_defconfig
index 0886895306..eb9782c446 100644
--- a/arch/arm/configs/tny_a9260_defconfig
+++ b/arch/arm/configs/tny_a9260_defconfig
@@ -1,15 +1,14 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_TNY_A9260=y
 CONFIG_CALAO_MOB_TNY_MD2=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="TNY-9260:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -58,9 +57,6 @@ CONFIG_DRIVER_SPI_ATMEL=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_SERIAL=y
diff --git a/arch/arm/configs/tny_a9263_bootstrap_defconfig b/arch/arm/configs/tny_a9263_bootstrap_defconfig
index d7e541a2b1..80b42f5f86 100644
--- a/arch/arm/configs/tny_a9263_bootstrap_defconfig
+++ b/arch/arm/configs/tny_a9263_bootstrap_defconfig
@@ -1,11 +1,11 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_TNY_A9263=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ENVIRONMENT_VARIABLES=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
 CONFIG_MALLOC_DUMMY=y
 CONFIG_PROMPT="USB-9263:"
 CONFIG_SHELL_NONE=y
@@ -15,8 +15,5 @@ CONFIG_MTD=y
 # CONFIG_MTD_WRITE is not set
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 # CONFIG_FS_RAMFS is not set
diff --git a/arch/arm/configs/tny_a9263_defconfig b/arch/arm/configs/tny_a9263_defconfig
index e050b6d47c..d4a732d94b 100644
--- a/arch/arm/configs/tny_a9263_defconfig
+++ b/arch/arm/configs/tny_a9263_defconfig
@@ -1,15 +1,14 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_TNY_A9263=y
 CONFIG_CALAO_MOB_TNY_MD2=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="TNY-9263:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -59,9 +58,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_MTD_DATAFLASH=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_SERIAL=y
diff --git a/arch/arm/configs/tny_a9g20_defconfig b/arch/arm/configs/tny_a9g20_defconfig
index dc828a24d7..bc145cc2db 100644
--- a/arch/arm/configs/tny_a9g20_defconfig
+++ b/arch/arm/configs/tny_a9g20_defconfig
@@ -1,15 +1,14 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_TNY_A9G20=y
 CONFIG_CALAO_MOB_TNY_MD2=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="TNY-9G20:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -59,9 +58,6 @@ CONFIG_DRIVER_SPI_ATMEL=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_SERIAL=y
diff --git a/arch/arm/configs/usb_a9260_defconfig b/arch/arm/configs/usb_a9260_defconfig
index d87ebaae8e..a94d330568 100644
--- a/arch/arm/configs/usb_a9260_defconfig
+++ b/arch/arm/configs/usb_a9260_defconfig
@@ -1,14 +1,13 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_USB_A9260=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="USB-9G20:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -62,9 +61,6 @@ CONFIG_DRIVER_NET_MACB=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig b/arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig
deleted file mode 100644
index 30794eeec4..0000000000
--- a/arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-CONFIG_ARCH_AT91SAM9263=y
-CONFIG_MACH_USB_A9263=y
-CONFIG_AT91_HAVE_SRAM_128M=y
-CONFIG_AT91_BOOTSTRAP=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ENVIRONMENT_VARIABLES=y
-CONFIG_PBL_IMAGE=y
-CONFIG_MMU=y
-CONFIG_MALLOC_DUMMY=y
-CONFIG_PROMPT="USB-9263:"
-CONFIG_SHELL_NONE=y
-# CONFIG_SPI is not set
-CONFIG_MTD=y
-# CONFIG_MTD_WRITE is not set
-# CONFIG_MTD_OOB_DEVICE is not set
-CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-CONFIG_NAND_ATMEL=y
-# CONFIG_FS_RAMFS is not set
-CONFIG_BOOTSTRAP_DEVFS=y
diff --git a/arch/arm/configs/usb_a9263_128mib_defconfig b/arch/arm/configs/usb_a9263_128mib_defconfig
deleted file mode 100644
index 0795cacbb7..0000000000
--- a/arch/arm/configs/usb_a9263_128mib_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_ARCH_AT91SAM9263=y
-CONFIG_MACH_USB_A9263=y
-CONFIG_AT91_HAVE_SRAM_128M=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_MMU=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_MALLOC_TLSF=y
-CONFIG_PROMPT="USB-9263:"
-CONFIG_GLOB=y
-CONFIG_PROMPT_HUSH_PS2="y"
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-# CONFIG_CMD_ARM_CPUINFO is not set
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_LOGIN=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_PASSWD=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_DRIVER_NET_MACB=y
-CONFIG_DRIVER_SPI_ATMEL=y
-CONFIG_MTD=y
-# CONFIG_MTD_OOB_DEVICE is not set
-CONFIG_MTD_DATAFLASH=y
-CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DFU=y
-CONFIG_USB_GADGET_SERIAL=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_FS_TFTP=y
diff --git a/arch/arm/configs/usb_a9263_bootstrap_defconfig b/arch/arm/configs/usb_a9263_bootstrap_defconfig
index c922cc0342..2adf114389 100644
--- a/arch/arm/configs/usb_a9263_bootstrap_defconfig
+++ b/arch/arm/configs/usb_a9263_bootstrap_defconfig
@@ -1,12 +1,12 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_USB_A9263=y
 CONFIG_AT91_BOOTSTRAP=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ENVIRONMENT_VARIABLES=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
 CONFIG_MALLOC_DUMMY=y
 CONFIG_PROMPT="USB-9263:"
 CONFIG_SHELL_NONE=y
@@ -15,9 +15,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_WRITE is not set
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 # CONFIG_FS_RAMFS is not set
 CONFIG_BOOTSTRAP_DEVFS=y
diff --git a/arch/arm/configs/usb_a9263_defconfig b/arch/arm/configs/usb_a9263_defconfig
index 89726a4ae1..a41e64298c 100644
--- a/arch/arm/configs/usb_a9263_defconfig
+++ b/arch/arm/configs/usb_a9263_defconfig
@@ -1,14 +1,13 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_USB_A9263=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="USB-9263:"
-CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -63,9 +62,6 @@ CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_MTD_DATAFLASH=y
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
diff --git a/arch/arm/configs/usb_a9g20_128mib_defconfig b/arch/arm/configs/usb_a9g20_128mib_defconfig
deleted file mode 100644
index fce3a10061..0000000000
--- a/arch/arm/configs/usb_a9g20_128mib_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_ARCH_AT91SAM9G20=y
-CONFIG_MACH_USB_A9G20=y
-CONFIG_AT91_HAVE_SRAM_128M=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_MMU=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_MALLOC_TLSF=y
-CONFIG_PROMPT="USB-9G20:"
-CONFIG_GLOB=y
-CONFIG_PROMPT_HUSH_PS2="y"
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-# CONFIG_CMD_ARM_CPUINFO is not set
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_LOGIN=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_PASSWD=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_DRIVER_NET_MACB=y
-CONFIG_DRIVER_SPI_ATMEL=y
-CONFIG_MTD=y
-# CONFIG_MTD_OOB_DEVICE is not set
-CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DFU=y
-CONFIG_USB_GADGET_SERIAL=y
-CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
-CONFIG_MCI_SPI=y
-CONFIG_MMC_SPI_CRC_ON=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/usb_a9g20_defconfig b/arch/arm/configs/usb_a9g20_defconfig
index 61412d854b..56f78ba7a8 100644
--- a/arch/arm/configs/usb_a9g20_defconfig
+++ b/arch/arm/configs/usb_a9g20_defconfig
@@ -1,14 +1,15 @@
+CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_USB_A9G20=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
+CONFIG_MALLOC_SIZE=0x800000
 CONFIG_EXPERIMENTAL=y
 CONFIG_MALLOC_TLSF=y
-CONFIG_PROMPT="USB-9G20:"
-CONFIG_GLOB=y
+CONFIG_RELOCATABLE=y
+CONFIG_PROMPT="USB-A9G20:"
 CONFIG_PROMPT_HUSH_PS2="y"
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
@@ -34,16 +35,14 @@ CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_SAVEENV=y
 CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_SHA1SUM=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_DHCP=y
+CONFIG_NET_CMD_IFUP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TFTP=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_LOGIN=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
 CONFIG_CMD_PASSWD=y
 CONFIG_CMD_READLINE=y
 CONFIG_CMD_TIMEOUT=y
@@ -54,17 +53,13 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_LED_TRIGGER=y
 CONFIG_CMD_OFTREE=y
 CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
 CONFIG_NET_RESOLV=y
 CONFIG_DRIVER_NET_MACB=y
 CONFIG_DRIVER_SPI_ATMEL=y
 CONFIG_MTD=y
 # CONFIG_MTD_OOB_DEVICE is not set
 CONFIG_NAND=y
-# CONFIG_NAND_ECC_HW is not set
-# CONFIG_NAND_ECC_HW_SYNDROME is not set
-# CONFIG_NAND_ECC_HW_NONE is not set
+CONFIG_MTD_NAND_ECC_SOFT=y
 CONFIG_NAND_ATMEL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
@@ -76,7 +71,5 @@ CONFIG_MMC_SPI_CRC_ON=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_LED_TRIGGERS=y
+# CONFIG_VIRTIO_MENU is not set
 CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/versatilepb_arm1176_defconfig b/arch/arm/configs/versatilepb_arm1176_defconfig
deleted file mode 100644
index e8c662183a..0000000000
--- a/arch/arm/configs/versatilepb_arm1176_defconfig
+++ /dev/null
@@ -1,89 +0,0 @@
-CONFIG_ARCH_VERSATILE=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x80000
-CONFIG_MACH_VERSATILEPB_ARM1176=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_PBL_RELOCATABLE=y
-CONFIG_MALLOC_SIZE=0xa00000
-CONFIG_PROMPT="versatilepb> "
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_DEFAULT_COMPRESSION_GZIP=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/versatile/env"
-CONFIG_CMD_DMESG=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_UBIFORMAT=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_LOGIN=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_PASSWD=y
-CONFIG_CMD_SPLASH=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_OFDEVICE=y
-CONFIG_OF_BAREBOX_DRIVERS=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_DRIVER_NET_SMC91111=y
-CONFIG_I2C=y
-CONFIG_I2C_VERSATILE=y
-CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-# CONFIG_DRIVER_CFI_AMD is not set
-# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
-# CONFIG_DRIVER_CFI_BANK_WIDTH_2 is not set
-CONFIG_MTD_UBI=y
-CONFIG_USB_HOST=y
-CONFIG_USB_EHCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_GPIO_PL061=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_FS_CRAMFS=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_NFS=y
-CONFIG_PNG=y
-CONFIG_DIGEST_SHA1_GENERIC=y
-CONFIG_DIGEST_SHA256_GENERIC=y
diff --git a/arch/arm/configs/versatilepb_defconfig b/arch/arm/configs/versatilepb_defconfig
deleted file mode 100644
index 14481ea58e..0000000000
--- a/arch/arm/configs/versatilepb_defconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-CONFIG_ARCH_VERSATILE=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x80000
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_PBL_IMAGE=y
-CONFIG_PBL_RELOCATABLE=y
-CONFIG_PROMPT="versatilepb> "
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_COMPRESSION_GZIP=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/versatile/env"
-CONFIG_CMD_DMESG=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_UBIFORMAT=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_LOGIN=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_PASSWD=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_OFDEVICE=y
-CONFIG_OF_BAREBOX_DRIVERS=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_DRIVER_NET_SMC91111=y
-CONFIG_I2C=y
-CONFIG_I2C_VERSATILE=y
-CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-# CONFIG_DRIVER_CFI_AMD is not set
-# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
-# CONFIG_DRIVER_CFI_BANK_WIDTH_2 is not set
-CONFIG_MTD_UBI=y
-CONFIG_GPIO_PL061=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_FS_CRAMFS=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_NFS=y
-CONFIG_DIGEST_SHA1_GENERIC=y
-CONFIG_DIGEST_SHA256_GENERIC=y
diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
deleted file mode 100644
index d58ca7ebd0..0000000000
--- a/arch/arm/configs/vexpress_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_ARCH_VEXPRESS=y
-CONFIG_MACH_VEXPRESS=y
-CONFIG_MACH_VIRT=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_MALLOC_SIZE=0x0
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_PROMPT="vexpress: "
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_CONSOLE_ACTIVATE_ALL=y
-CONFIG_CONSOLE_ALLOW_COLOR=y
-CONFIG_PARTITION_DISK_EFI=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_CMD_DMESG=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_LOGIN=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_PASSWD=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DETECT=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_OF_BAREBOX_DRIVERS=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_DRIVER_NET_SMC91111=y
-# CONFIG_SPI is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_DRIVER_CFI=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_MCI=y
-CONFIG_MCI_MMCI=y
-CONFIG_HWRNG=y
-CONFIG_HW_RANDOM_VIRTIO=y
-# CONFIG_PINCTRL is not set
-CONFIG_VIRTIO_MMIO=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_DIGEST_SHA1_GENERIC=y
-CONFIG_DIGEST_SHA256_GENERIC=y
diff --git a/arch/arm/configs/virt2real_defconfig b/arch/arm/configs/virt2real_defconfig
index 62315b8cb3..6e51f53f19 100644
--- a/arch/arm/configs/virt2real_defconfig
+++ b/arch/arm/configs/virt2real_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_MALLOC_SIZE=0x200000
 CONFIG_MALLOC_TLSF=y
 CONFIG_PROMPT="virt2real: "
-CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/zii_vf610_dev_defconfig b/arch/arm/configs/zii_vf610_dev_defconfig
index 3ed5d37458..5e9fca65e6 100644
--- a/arch/arm/configs/zii_vf610_dev_defconfig
+++ b/arch/arm/configs/zii_vf610_dev_defconfig
@@ -1,5 +1,4 @@
 CONFIG_ARCH_IMX=y
-CONFIG_IMX_MULTI_BOARDS=y
 CONFIG_MACH_ZII_VF610_DEV=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
diff --git a/arch/arm/configs/zylonite310_defconfig b/arch/arm/configs/zylonite310_defconfig
index a8ac92040a..cdbd135081 100644
--- a/arch/arm/configs/zylonite310_defconfig
+++ b/arch/arm/configs/zylonite310_defconfig
@@ -1,5 +1,4 @@
 CONFIG_ARCH_PXA=y
-CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
 CONFIG_ARCH_PXA3XX=y
 CONFIG_AEABI=y
 CONFIG_ARM_BOARD_APPEND_ATAG=y
@@ -7,6 +6,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 # CONFIG_BANNER is not set
 CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
 CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000
 CONFIG_MALLOC_SIZE=0x800000
 CONFIG_EXPERIMENTAL=y
diff --git a/arch/arm/configs/zynq_defconfig b/arch/arm/configs/zynq_defconfig
index a16c57d5ce..226942e6b4 100644
--- a/arch/arm/configs/zynq_defconfig
+++ b/arch/arm/configs/zynq_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_ZYNQ=y
 CONFIG_MACH_ZEDBOARD=y
 CONFIG_AEABI=y
 CONFIG_ARM_UNWIND=y
+CONFIG_IMAGE_COMPRESSION_XZKERN=y
 CONFIG_MMU=y
 CONFIG_STACK_SIZE=0xf000
 CONFIG_MALLOC_SIZE=0x8000000
@@ -42,6 +43,7 @@ CONFIG_NET=y
 CONFIG_DRIVER_SERIAL_CADENCE=y
 CONFIG_DRIVER_NET_MACB=y
 # CONFIG_SPI is not set
+CONFIG_GPIO_ZYNQ=y
 # CONFIG_PINCTRL is not set
 CONFIG_FS_TFTP=y
 CONFIG_DIGEST=y
diff --git a/arch/arm/configs/zynqmp_defconfig b/arch/arm/configs/zynqmp_defconfig
index 762103c541..36a51dc8ad 100644
--- a/arch/arm/configs/zynqmp_defconfig
+++ b/arch/arm/configs/zynqmp_defconfig
@@ -1,5 +1,9 @@
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_MACH_XILINX_ZCU102=y
 CONFIG_MACH_XILINX_ZCU104=y
+CONFIG_MACH_XILINX_ZCU106=y
+CONFIG_64BIT=y
+CONFIG_ARM_PSCI_CLIENT=y
 CONFIG_MMU=y
 CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
@@ -12,30 +16,55 @@ CONFIG_BOOTM_SHOW_TYPE=y
 CONFIG_BOOTM_VERBOSE=y
 CONFIG_BOOTM_INITRD=y
 CONFIG_BOOTM_OFTREE=y
+CONFIG_BLSPEC=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_RESET_SOURCE=y
 CONFIG_LONGHELP=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_GO=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_PARTITION=y
 CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_MAGICVAR=y
 CONFIG_CMD_MAGICVAR_HELP=y
 CONFIG_CMD_SAVEENV=y
 CONFIG_CMD_LN=y
 CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TFTP=y
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_MENU=y
 CONFIG_CMD_MENU_MANAGEMENT=y
 CONFIG_CMD_READLINE=y
 CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_FIRMWARELOAD=y
+CONFIG_CMD_OF_OVERLAY=y
 CONFIG_CMD_OFTREE=y
 CONFIG_CMD_TIME=y
 CONFIG_NET=y
+CONFIG_NET_NFS=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_OF_BAREBOX_ENV_IN_FS=y
+CONFIG_OF_OVERLAY_LIVE=y
 CONFIG_DRIVER_SERIAL_CADENCE=y
 CONFIG_DRIVER_NET_MACB=y
+CONFIG_DP83867_PHY=y
 # CONFIG_SPI is not set
+CONFIG_MCI=y
+CONFIG_MCI_ARASAN=y
+CONFIG_GPIO_ZYNQ=y
 CONFIG_FIRMWARE_ZYNQMP_FPGA=y
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
 CONFIG_DIGEST=y
diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig
index ca3bd98962..e69acaacdf 100644
--- a/arch/arm/cpu/Kconfig
+++ b/arch/arm/cpu/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 comment "Processor Type"
 
 config PHYS_ADDR_T_64BIT
@@ -9,12 +11,17 @@ config CPU_32
 	select HAVE_MOD_ARCH_SPECIFIC
 	select HAS_DMA
 	select HAVE_PBL_IMAGE
+	select ARCH_HAS_ZERO_PAGE
 
 config CPU_64
 	bool
 	select PHYS_ADDR_T_64BIT
 	select HAVE_PBL_IMAGE
+	select HAVE_PBL_MULTI_IMAGES
 	select HAS_DMA
+	select ARCH_WANT_FRAME_POINTERS
+	select ARCH_HAS_ZERO_PAGE
+	select HAVE_EFI_PAYLOAD
 
 # Select CPU types depending on the architecture selected. This selects
 # which CPUs we support in the kernel image, and the compiler instruction
@@ -85,11 +92,9 @@ config CPU_V7
 config CPU_V8
 	bool
 	select CPU_64v8
-	select CPU_SUPPORTS_64BIT_KERNEL
 	select ARM_EXCEPTIONS
 	select GENERIC_FIND_NEXT_BIT
 	select ARCH_HAS_STACK_DUMP
-	select ARCH_HAS_ZERO_PAGE
 
 config CPU_XSC3
         bool
@@ -154,14 +159,3 @@ config CACHE_L2X0
 	bool "Enable L2x0 PrimeCell"
 	depends on MMU && ARCH_HAS_L2X0
 
-config SYS_SUPPORTS_32BIT_KERNEL
-	bool
-
-config SYS_SUPPORTS_64BIT_KERNEL
-	bool
-
-config CPU_SUPPORTS_32BIT_KERNEL
-	bool
-
-config CPU_SUPPORTS_64BIT_KERNEL
-	bool
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index e7a6e3e6fb..28161cd7d7 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,20 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += cpu.o
 
-obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions$(S64).o interrupts$(S64).o
-obj-$(CONFIG_MMU) += mmu$(S64).o mmu-common.o
-obj-pbl-y += lowlevel$(S64).o
-obj-pbl-$(CONFIG_MMU) += mmu-early$(S64).o
+obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions_$(S64_32).o interrupts_$(S64_32).o
+obj-$(CONFIG_MMU) += mmu-common.o
+obj-pbl-$(CONFIG_MMU) += mmu_$(S64_32).o
+obj-$(CONFIG_MMU) += dma_$(S64_32).o
+obj-pbl-y += lowlevel_$(S64_32).o
 obj-pbl-$(CONFIG_CPU_32v7) += hyp.o
 AFLAGS_hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
 AFLAGS_hyp.pbl.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
 
-obj-y += start.o entry.o entry_ll$(S64).o
+obj-y += start.o entry.o entry_ll_$(S64_32).o
 KASAN_SANITIZE_start.o := n
 
+pbl-$(CONFIG_CPU_64) += head_64.o
+
 pbl-$(CONFIG_BOARD_ARM_GENERIC_DT) += board-dt-2nd.o
 pbl-$(CONFIG_BOARD_ARM_GENERIC_DT_AARCH64) += board-dt-2nd-aarch64.o
 
-obj-pbl-y += setupc$(S64).o cache$(S64).o
+obj-pbl-y += setupc_$(S64_32).o cache_$(S64_32).o
 
 obj-$(CONFIG_ARM_PSCI_CLIENT) += psci-client.o
 
@@ -22,8 +27,9 @@ obj-$(CONFIG_ARM_PSCI_CLIENT) += psci-client.o
 # Any variants can be called as start-armxyz.S
 #
 obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o
-obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
+obj-$(CONFIG_MMUINFO) += mmuinfo.o mmuinfo_$(S64_32).o
 obj-$(CONFIG_OFDEVICE) += dtb.o
+obj-$(CONFIG_BOOTM_ELF)	+= bootm-elf.o
 
 ifeq ($(CONFIG_MMU),)
 obj-$(CONFIG_CPU_32v7) += no-mmu.o
@@ -31,9 +37,9 @@ endif
 
 obj-$(CONFIG_ARM_PSCI) += psci.o
 obj-$(CONFIG_ARM_PSCI_OF) += psci-of.o
-obj-pbl-$(CONFIG_ARM_SMCCC) += smccc-call$(S64).o
-AFLAGS_smccc-call$(S64).o :=-Wa,-march=armv$(if $(S64),8,7)-a
-AFLAGS_smccc-call$(S64).pbl.o :=-Wa,-march=armv$(if $(S64),8,7)-a
+obj-pbl-$(CONFIG_ARM_SMCCC) += smccc-call_$(S64_32).o
+AFLAGS_smccc-call_$(S64_32).o :=-Wa,-march=armv$(if $(S64),8,7)-a
+AFLAGS_smccc-call_$(S64_32).pbl.o :=-Wa,-march=armv$(if $(S64),8,7)-a
 obj-$(CONFIG_ARM_SECURE_MONITOR) += sm.o sm_as.o
 AFLAGS_sm_as.o		:=-Wa,-march=armv7-a
 
@@ -48,8 +54,9 @@ obj-pbl-$(CONFIG_CPU_64v8) += cache-armv8.o
 AFLAGS_cache-armv8.o       :=-Wa,-march=armv8-a
 AFLAGS-cache-armv8.pbl.o   :=-Wa,-march=armv8-a
 
-pbl-y += entry.o entry_ll$(S64).o
+pbl-y += entry.o entry_ll_$(S64_32).o
 pbl-y += uncompress.o
+pbl-$(CONFIG_ARM_ATF) += atf.o
 
 obj-pbl-y += common.o sections.o
 KASAN_SANITIZE_common.o := n
diff --git a/arch/arm/cpu/atf.c b/arch/arm/cpu/atf.c
new file mode 100644
index 0000000000..d01e20508c
--- /dev/null
+++ b/arch/arm/cpu/atf.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <asm/atf_common.h>
+#include <asm/system.h>
+
+static inline void raw_write_daif(unsigned int daif)
+{
+	__asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
+}
+
+void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
+		uintptr_t bl33_entry, uintptr_t fdt_addr)
+{
+	struct atf_image_info bl31_image_info = {
+		.h = {
+			.type = ATF_PARAM_IMAGE_BINARY,
+			.version = ATF_VERSION_1,
+			.size = sizeof(bl31_image_info),
+		},
+	};
+	struct atf_image_info bl32_image_info = {
+		.h = {
+			.type = ATF_PARAM_IMAGE_BINARY,
+			.version = ATF_VERSION_1,
+			.size = sizeof(bl32_image_info),
+		},
+	};
+	struct entry_point_info bl32_ep_info = {
+		.h = {
+			.type = ATF_PARAM_EP,
+			.version = ATF_VERSION_1,
+			.attr = ATF_EP_SECURE,
+			.size = sizeof(bl32_ep_info),
+		},
+		.pc = bl32_entry,
+		.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS),
+		.args = {
+			.arg3 = fdt_addr,
+		},
+	};
+	struct atf_image_info bl33_image_info = {
+		.h = {
+			.type = ATF_PARAM_IMAGE_BINARY,
+			.version = ATF_VERSION_1,
+			.size = sizeof(bl33_image_info),
+		},
+	};
+	struct entry_point_info bl33_ep_info = {
+		.h = {
+			.type = ATF_PARAM_EP,
+			.version = ATF_VERSION_1,
+			.attr = ATF_EP_NON_SECURE,
+			.size = sizeof(bl33_ep_info),
+		},
+		.pc = bl33_entry,
+		.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS),
+		.args = {
+			/* BL33 expects to receive the primary CPU MPID (through x0) */
+			.arg0 = 0xffff & read_mpidr(),
+		},
+	};
+	struct bl31_params bl31_params = {
+		.h = {
+			.type = ATF_PARAM_BL31,
+			.version = ATF_VERSION_1,
+			.size = sizeof(bl31_params),
+		},
+		.bl31_image_info = &bl31_image_info,
+		.bl32_ep_info = &bl32_ep_info,
+		.bl32_image_info = &bl32_image_info,
+		.bl33_ep_info = &bl33_ep_info,
+		.bl33_image_info = &bl33_image_info,
+	};
+	void (*atf_entry)(struct bl31_params *params, uintptr_t plat_params);
+
+	raw_write_daif(SPSR_EXCEPTION_MASK);
+
+	atf_entry = (void *)bl31_entry;
+
+	atf_entry(&bl31_params, fdt_addr);
+}
+
+struct bl2_to_bl31_params_mem_v2 *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
+					uintptr_t bl33_entry, uintptr_t fdt_addr)
+{
+	static struct bl2_to_bl31_params_mem_v2 p = {
+		.bl_params = {
+			.h = {
+				.type = ATF_PARAM_BL_PARAMS,
+				.version = ATF_VERSION_2,
+				.size = sizeof(struct bl_params),
+				.attr = 0,
+			},
+			.head = &p.bl31_params_node,
+		},
+		.bl31_params_node = {
+			.image_id = ATF_BL31_IMAGE_ID,
+			.image_info = &p.bl31_image_info,
+			.ep_info = &p.bl31_ep_info,
+			.next_params_info = &p.bl32_params_node,
+		},
+		.bl32_params_node = {
+			.image_id = ATF_BL32_IMAGE_ID,
+			.image_info = &p.bl32_image_info,
+			.ep_info = &p.bl32_ep_info,
+			.next_params_info = &p.bl33_params_node,
+		},
+		.bl33_params_node = {
+			.image_id = ATF_BL33_IMAGE_ID,
+			.image_info = &p.bl33_image_info,
+			.ep_info = &p.bl33_ep_info,
+			.next_params_info = NULL,
+		},
+		.bl32_ep_info = {
+			.h = {
+				.type = ATF_PARAM_EP,
+				.version = ATF_VERSION_2,
+				.size = sizeof(struct entry_point_info),
+				.attr = ATF_EP_SECURE,
+			},
+			.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS),
+		},
+		.bl33_ep_info = {
+			.h = {
+				.type = ATF_PARAM_EP,
+				.version = ATF_VERSION_2,
+				.size = sizeof(struct entry_point_info),
+				.attr = ATF_EP_NON_SECURE,
+			},
+			.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS),
+		},
+		.bl33_image_info = {
+			.h = {
+				.type = ATF_PARAM_IMAGE_BINARY,
+				.version = ATF_VERSION_2,
+				.size = sizeof(struct atf_image_info),
+				.attr = 0,
+			},
+		},
+		.bl32_image_info = {
+			.h = {
+				.type = ATF_PARAM_IMAGE_BINARY,
+				.version = ATF_VERSION_2,
+				.size = sizeof(struct atf_image_info),
+				.attr = ATF_EP_SECURE,
+			},
+		},
+		.bl31_image_info = {
+			.h = {
+				.type = ATF_PARAM_IMAGE_BINARY,
+				.version = ATF_VERSION_2,
+				.size = sizeof(struct atf_image_info),
+				.attr = 0,
+			},
+		},
+	};
+
+	p.bl33_ep_info.args.arg0 = 0xffff & read_mpidr();
+	p.bl33_ep_info.pc = bl33_entry;
+	p.bl32_ep_info.args.arg3 = fdt_addr;
+	p.bl32_ep_info.pc = bl32_entry;
+
+	return &p;
+}
+
+void bl31_entry_v2(uintptr_t bl31_entry, struct bl_params *params, void *fdt_addr)
+{
+	void (*atf_entry)(struct bl_params *params, uintptr_t plat_params);
+
+	raw_write_daif(SPSR_EXCEPTION_MASK);
+
+	atf_entry = (void *)bl31_entry;
+
+	atf_entry(params, (uintptr_t)fdt_addr);
+}
diff --git a/arch/arm/cpu/board-dt-2nd-aarch64.S b/arch/arm/cpu/board-dt-2nd-aarch64.S
index d2c9f132ce..030366c1cb 100644
--- a/arch/arm/cpu/board-dt-2nd-aarch64.S
+++ b/arch/arm/cpu/board-dt-2nd-aarch64.S
@@ -2,6 +2,7 @@
 #include <linux/linkage.h>
 #include <asm/barebox-arm64.h>
 #include <asm/image.h>
+#include "efi-header-aarch64.S"
 
 #define IMAGE_FLAGS \
 	(ARM64_IMAGE_FLAG_PAGE_SIZE_4K << ARM64_IMAGE_FLAG_PAGE_SIZE_SHIFT) | \
@@ -9,7 +10,7 @@
 
 .section .text_head_entry_start_dt_2nd
 ENTRY("start_dt_2nd")
-	adr x1, 0	   	   /* code0 */
+	efi_signature_nop          /* code0 */
 	b 2f                       /* code1 */
 	.xword 0x80000             /* Image load offset */
 	.xword _barebox_image_size /* Effective Image size */
@@ -18,12 +19,15 @@ ENTRY("start_dt_2nd")
 	.xword 0                   /* reserved */
 	.xword 0                   /* reserved */
 	.ascii ARM64_IMAGE_MAGIC   /* magic number */
-	.int   0                   /* reserved (PE-COFF offset) */
+	.int   .Lpe_header_offset  /* reserved (PE-COFF offset) */
 	.asciz "barebox"	   /* unused for now */
 2:
+	adr x1, 0
 	mov sp, x1
 	/* Stack now grows into the 0x80000 image load offset specified
 	 * above. This is more than enough until FDT /memory is decoded.
 	 */
 	b dt_2nd_aarch64
+
+	__EFI_PE_HEADER
 ENTRY_PROC_END(start_dt_2nd)
diff --git a/arch/arm/cpu/board-dt-2nd.c b/arch/arm/cpu/board-dt-2nd.c
index 6f6f535918..6f69a6dd27 100644
--- a/arch/arm/cpu/board-dt-2nd.c
+++ b/arch/arm/cpu/board-dt-2nd.c
@@ -12,29 +12,28 @@
 
 #ifdef CONFIG_CPU_V8
 
-static noinline void dt_2nd_continue_aarch64(void *fdt)
-{
-	unsigned long membase, memsize;
-
-	if (!fdt)
-		hang();
-
-	fdt_find_mem(fdt, &membase, &memsize);
-
-	barebox_arm_entry(membase, memsize, fdt);
-}
-
 /* called from assembly */
 void dt_2nd_aarch64(void *fdt);
 
 void dt_2nd_aarch64(void *fdt)
 {
+	unsigned long membase, memsize;
+
+	putc_ll('>');
+
 	/* entry point already set up stack */
 
+	arm_cpu_lowlevel_init();
+
 	relocate_to_current_adr();
 	setup_c();
 
-	dt_2nd_continue_aarch64(fdt);
+	if (!fdt)
+		hang();
+
+	fdt_find_mem(fdt, &membase, &memsize);
+
+	barebox_arm_entry(membase, memsize, fdt);
 }
 
 #else
@@ -55,6 +54,8 @@ ENTRY_FUNCTION(start_dt_2nd, r0, r1, r2)
 {
 	unsigned long image_start = (unsigned long)_text + global_variable_offset();
 
+	arm_cpu_lowlevel_init();
+
 	arm_setup_stack(image_start);
 
 	relocate_to_current_adr();
diff --git a/arch/arm/cpu/bootm-elf.c b/arch/arm/cpu/bootm-elf.c
new file mode 100644
index 0000000000..bcca3931f2
--- /dev/null
+++ b/arch/arm/cpu/bootm-elf.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#define pr_fmt(fmt) "ELF: " fmt
+
+#include <bootm.h>
+#include <elf.h>
+#include <common.h>
+#include <init.h>
+#include <errno.h>
+
+static int do_bootm_elf(struct image_data *data)
+{
+	void (*fn)(unsigned long x0, unsigned long x1, unsigned long x2,
+		   unsigned long x3);
+	struct elf_image *elf = data->elf;
+	int ret;
+
+	if (elf_hdr_e_machine(elf, elf->hdr_buf) != ELF_ARCH) {
+		pr_err("Unsupported machine: 0x%02x, but 0x%02x expected\n",
+		       elf_hdr_e_machine(elf, elf->hdr_buf), ELF_ARCH);
+
+		return -EINVAL;
+	}
+
+	ret = bootm_load_os(data, data->os_address);
+	if (ret)
+		return ret;
+
+	if (data->dryrun)
+		return ret;
+
+	ret = of_overlay_load_firmware();
+	if (ret)
+		return ret;
+
+	shutdown_barebox();
+
+	fn = (void *) (unsigned long) data->os_address;
+
+	fn(0, 0, 0, 0);
+
+	pr_err("ELF application terminated\n");
+	return -EINVAL;
+}
+
+static struct image_handler elf_handler = {
+	.name = "ELF",
+	.bootm = do_bootm_elf,
+	.filetype = filetype_elf,
+};
+
+static int arm_register_elf_image_handler(void)
+{
+	return register_image_handler(&elf_handler);
+}
+late_initcall(arm_register_elf_image_handler);
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index db87de17e9..78a098b2fe 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <init.h>
 
diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S
index 4267f3e37f..bcb7ebf466 100644
--- a/arch/arm/cpu/cache-armv5.S
+++ b/arch/arm/cpu/cache-armv5.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <init.h>
 
diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S
index 7a06751997..cc720314c0 100644
--- a/arch/arm/cpu/cache-armv6.S
+++ b/arch/arm/cpu/cache-armv6.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <init.h>
 
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 0f6108426c..efd9fe412f 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <init.h>
 
diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index e975ecffc7..82ae16ba4d 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define pr_fmt(fmt) "l2x0: " fmt
 
 #include <common.h>
diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache_32.c
index 2b6e958a4e..0ac50c4d9a 100644
--- a/arch/arm/cpu/cache.c
+++ b/arch/arm/cpu/cache_32.c
@@ -1,10 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <asm/mmu.h>
 #include <asm/cache.h>
 #include <asm/system_info.h>
 
-#include "mmu.h"
+#include "mmu_32.h"
 
 struct cache_fns {
 	void (*dma_clean_range)(unsigned long start, unsigned long end);
@@ -15,8 +17,6 @@ struct cache_fns {
 	void (*mmu_cache_flush)(void);
 };
 
-struct cache_fns *cache_fns;
-
 #define DEFINE_CPU_FNS(arch) \
 	void arch##_dma_clean_range(unsigned long start, unsigned long end);	\
 	void arch##_dma_flush_range(unsigned long start, unsigned long end);	\
@@ -39,50 +39,13 @@ DEFINE_CPU_FNS(v5)
 DEFINE_CPU_FNS(v6)
 DEFINE_CPU_FNS(v7)
 
-void __dma_clean_range(unsigned long start, unsigned long end)
+static struct cache_fns *cache_functions(void)
 {
-	if (cache_fns)
-		cache_fns->dma_clean_range(start, end);
-}
+	static struct cache_fns *cache_fns;
 
-void __dma_flush_range(unsigned long start, unsigned long end)
-{
 	if (cache_fns)
-		cache_fns->dma_flush_range(start, end);
-}
+		return cache_fns;
 
-void __dma_inv_range(unsigned long start, unsigned long end)
-{
-	if (cache_fns)
-		cache_fns->dma_inv_range(start, end);
-}
-
-#ifdef CONFIG_MMU
-
-void __mmu_cache_on(void)
-{
-	if (cache_fns)
-		cache_fns->mmu_cache_on();
-}
-
-void __mmu_cache_off(void)
-{
-	if (cache_fns)
-		cache_fns->mmu_cache_off();
-}
-
-void __mmu_cache_flush(void)
-{
-	if (cache_fns)
-		cache_fns->mmu_cache_flush();
-	if (outer_cache.flush_all)
-		outer_cache.flush_all();
-}
-
-#endif
-
-int arm_set_cache_functions(void)
-{
 	switch (cpu_architecture()) {
 #ifdef CONFIG_CPU_32v4T
 	case CPU_ARCH_ARMv4T:
@@ -111,9 +74,45 @@ int arm_set_cache_functions(void)
 		while(1);
 	}
 
-	return 0;
+	return cache_fns;
+}
+
+void __dma_clean_range(unsigned long start, unsigned long end)
+{
+	cache_functions()->dma_clean_range(start, end);
+}
+
+void __dma_flush_range(unsigned long start, unsigned long end)
+{
+	cache_functions()->dma_flush_range(start, end);
+}
+
+void __dma_inv_range(unsigned long start, unsigned long end)
+{
+	cache_functions()->dma_inv_range(start, end);
+}
+
+#ifdef CONFIG_MMU
+
+void __mmu_cache_on(void)
+{
+	cache_functions()->mmu_cache_on();
+}
+
+void __mmu_cache_off(void)
+{
+	cache_functions()->mmu_cache_off();
 }
 
+void __mmu_cache_flush(void)
+{
+	cache_functions()->mmu_cache_flush();
+	if (outer_cache.flush_all)
+		outer_cache.flush_all();
+}
+
+#endif
+
 /*
  * Early function to flush the caches. This is for use when the
  * C environment is not yet fully initialized.
diff --git a/arch/arm/cpu/cache_64.c b/arch/arm/cpu/cache_64.c
index cb7bc0945c..3a30296128 100644
--- a/arch/arm/cpu/cache_64.c
+++ b/arch/arm/cpu/cache_64.c
@@ -6,11 +6,6 @@
 #include <asm/cache.h>
 #include <asm/system_info.h>
 
-int arm_set_cache_functions(void)
-{
-	return 0;
-}
-
 /*
  * Early function to flush the caches. This is for use when the
  * C environment is not yet fully initialized.
diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 8cfcc8f6ce..e9118b450d 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -23,6 +23,12 @@
  */
 void sync_caches_for_execution(void)
 {
+	/* if caches are disabled, don't do data cache maintenance */
+	if (!(get_cr() & CR_C)) {
+		icache_invalidate();
+		return;
+	}
+
 	/*
 	 * Despite the name arm_early_mmu_cache_flush not only flushes the
 	 * data cache, but also invalidates the instruction cache.
@@ -53,18 +59,21 @@ void pbl_barebox_break(void)
 /*
  * relocate binary to the currently running address
  */
-void relocate_to_current_adr(void)
+void __prereloc relocate_to_current_adr(void)
 {
-	unsigned long offset, offset_var;
+	unsigned long offset;
 	unsigned long __maybe_unused *dynsym, *dynend;
 	void *dstart, *dend;
 
 	/* Get offset between linked address and runtime address */
 	offset = get_runtime_offset();
-	offset_var = global_variable_offset();
 
-	dstart = (void *)__rel_dyn_start + offset_var;
-	dend = (void *)__rel_dyn_end + offset_var;
+	/*
+	 * We have yet to relocate, so using runtime_address
+	 * to compute the relocated address
+	 */
+	dstart = runtime_address(__rel_dyn_start);
+	dend = runtime_address(__rel_dyn_end);
 
 #if defined(CONFIG_CPU_64)
 	while (dstart < dend) {
@@ -84,14 +93,14 @@ void relocate_to_current_adr(void)
 			putc_ll(' ');
 			puthex_ll(rel->r_addend);
 			putc_ll('\n');
-			panic("");
+			__hang();
 		}
 
 		dstart += sizeof(*rel);
 	}
 #elif defined(CONFIG_CPU_32)
-	dynsym = (void *)__dynsym_start + offset_var;
-	dynend = (void *)__dynsym_end + offset_var;
+	dynsym = runtime_address(__dynsym_start);
+	dynend = runtime_address(__dynsym_end);
 
 	while (dstart < dend) {
 		struct elf32_rel *rel = dstart;
@@ -114,7 +123,7 @@ void relocate_to_current_adr(void)
 			putc_ll(' ');
 			puthex_ll(rel->r_offset);
 			putc_ll('\n');
-			panic("");
+			__hang();
 		}
 
 		dstart += sizeof(*rel);
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 5b79dd2a8f..5f1ffe9a3c 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -17,8 +17,7 @@
 #include <asm/cputype.h>
 #include <asm/cache.h>
 #include <asm/ptrace.h>
-
-#include "mmu.h"
+#include <efi/efi-mode.h>
 
 /**
  * Enable processor's instruction cache
@@ -84,6 +83,8 @@ static void disable_interrupts(void)
  */
 static void arch_shutdown(void)
 {
+	if (efi_is_payload())
+		return;
 
 #ifdef CONFIG_MMU
 	mmu_disable();
@@ -98,6 +99,9 @@ extern unsigned long arm_stack_top;
 
 static int arm_request_stack(void)
 {
+	if (efi_is_payload())
+		return 0;
+
 	if (!request_sdram_region("stack", arm_stack_top - STACK_SIZE, STACK_SIZE))
 		pr_err("Error: Cannot request SDRAM region for stack\n");
 
diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c
index a08fc253ef..2d3fe2ac8d 100644
--- a/arch/arm/cpu/cpuinfo.c
+++ b/arch/arm/cpu/cpuinfo.c
@@ -4,6 +4,7 @@
 /* cpuinfo.c - Show information about cp15 registers */
 
 #include <common.h>
+#include <getopt.h>
 #include <command.h>
 #include <complete.h>
 #include <asm/system.h>
@@ -27,6 +28,7 @@
 #define ARM_CPU_PART_CORTEX_A15     0xC0F0
 #define ARM_CPU_PART_CORTEX_A53	    0xD030
 #define ARM_CPU_PART_CORTEX_A57	    0xD070
+#define ARM_CPU_PART_CORTEX_A72	    0xD080
 
 static void decode_cache(unsigned long size)
 {
@@ -48,9 +50,23 @@ static int do_cpuinfo(int argc, char *argv[])
 {
 	unsigned long mainid, cache, cr;
 	char *architecture, *implementer;
-	int i;
+	int opt, i;
 	int cpu_arch;
 
+	while ((opt = getopt(argc, argv, "s")) > 0) {
+		switch (opt) {
+		case 's':
+			if (!IS_ENABLED(CONFIG_ARCH_HAS_STACK_DUMP))
+				return -ENOSYS;
+
+			printf("SP: 0x%08lx\n", get_sp());
+			dump_stack();
+			return 0;
+		default:
+			return COMMAND_ERROR_USAGE;
+		}
+	}
+
 #ifdef CONFIG_CPU_64v8
 	__asm__ __volatile__(
 		"mrs	%0, midr_el1\n"
@@ -191,7 +207,7 @@ static int do_cpuinfo(int argc, char *argv[])
 
 	if (cpu_arch >= CPU_ARCH_ARMv7) {
 		unsigned int major, minor;
-		char *part;
+		const char *part = NULL;
 		major = (mainid >> 20) & 0xf;
 		minor = mainid & 0xf;
 		switch (mainid & 0xfff0) {
@@ -216,12 +232,23 @@ static int do_cpuinfo(int argc, char *argv[])
 		case ARM_CPU_PART_CORTEX_A57:
 			part = "Cortex-A57";
 			break;
+		case ARM_CPU_PART_CORTEX_A72:
+			part = "Cortex-A72";
+			break;
 		default:
-			part = "unknown";
+			printf("core: unknown (0x%08lx) r%up%u\n",
+			       mainid, major, minor);
+			break;
 		}
-		printf("core: %s r%up%u\n", part, major, minor);
+
+		if (part)
+			printf("core: %s r%up%u\n", part, major, minor);
 	}
 
+#ifdef CONFIG_CPU_64v8
+	printf("exception level: %u\n", current_el());
+#endif
+
 	if (cache & (1 << 24)) {
 		/* separate I/D cache */
 		printf("I-cache: ");
@@ -243,10 +270,16 @@ static int do_cpuinfo(int argc, char *argv[])
 	return 0;
 }
 
+BAREBOX_CMD_HELP_START(cpuinfo)
+BAREBOX_CMD_HELP_TEXT("Shows misc info about CPU")
+BAREBOX_CMD_HELP_OPT ("-s", "print call stack info (if supported)")
+BAREBOX_CMD_HELP_END
+
 BAREBOX_CMD_START(cpuinfo)
 	.cmd            = do_cpuinfo,
 	BAREBOX_CMD_DESC("show info about CPU")
+	BAREBOX_CMD_OPTS("[-s]")
 	BAREBOX_CMD_GROUP(CMD_GRP_INFO)
 	BAREBOX_CMD_COMPLETE(empty_complete)
+	BAREBOX_CMD_HELP(cmd_cpuinfo_help)
 BAREBOX_CMD_END
-
diff --git a/arch/arm/cpu/dma_32.c b/arch/arm/cpu/dma_32.c
new file mode 100644
index 0000000000..842ea7033a
--- /dev/null
+++ b/arch/arm/cpu/dma_32.c
@@ -0,0 +1,19 @@
+#include <dma.h>
+#include <asm/mmu.h>
+
+void arch_sync_dma_for_device(void *vaddr, size_t size,
+			      enum dma_data_direction dir)
+{
+	unsigned long start = (unsigned long)vaddr;
+	unsigned long end = start + size;
+
+	if (dir == DMA_FROM_DEVICE) {
+		__dma_inv_range(start, end);
+		if (outer_cache.inv_range)
+			outer_cache.inv_range(start, end);
+	} else {
+		__dma_clean_range(start, end);
+		if (outer_cache.clean_range)
+			outer_cache.clean_range(start, end);
+	}
+}
diff --git a/arch/arm/cpu/dma_64.c b/arch/arm/cpu/dma_64.c
new file mode 100644
index 0000000000..b50572f5e6
--- /dev/null
+++ b/arch/arm/cpu/dma_64.c
@@ -0,0 +1,15 @@
+#include <dma.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+
+void arch_sync_dma_for_device(void *vaddr, size_t size,
+                              enum dma_data_direction dir)
+{
+	unsigned long start = (unsigned long)vaddr;
+	unsigned long end = start + size;
+
+	if (dir == DMA_FROM_DEVICE)
+		v8_inv_dcache_range(start, end);
+	else
+		v8_flush_dcache_range(start, end);
+}
diff --git a/arch/arm/cpu/dtb.c b/arch/arm/cpu/dtb.c
index 35f251d99a..9aa979ca08 100644
--- a/arch/arm/cpu/dtb.c
+++ b/arch/arm/cpu/dtb.c
@@ -26,8 +26,6 @@ static int of_arm_init(void)
 		return 0;
 	}
 
-	barebox_register_fdt(fdt);
-
-	return 0;
+	return barebox_register_fdt(fdt);
 }
 core_initcall(of_arm_init);
diff --git a/arch/arm/cpu/efi-header-aarch64.S b/arch/arm/cpu/efi-header-aarch64.S
new file mode 100644
index 0000000000..941d0d8fdc
--- /dev/null
+++ b/arch/arm/cpu/efi-header-aarch64.S
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 - 2017 Linaro, Ltd.
+ * Copyright (C) 2013, 2014 Red Hat, Inc.
+ */
+
+#include <linux/pe.h>
+#include <linux/sizes.h>
+#include <asm/memory.h>
+
+	.macro	efi_signature_nop
+#ifdef CONFIG_EFI_STUB
+.L_head:
+	/*
+	 * This ccmp instruction has no meaningful effect except that
+	 * its opcode forms the magic "MZ" signature required by UEFI.
+	 */
+	ccmp	x18, #0, #0xd, pl
+#else
+	/*
+	 * Bootloaders may inspect the opcode at the start of the kernel
+	 * image to decide if the kernel is capable of booting via UEFI.
+	 * So put an ordinary NOP here, not the "MZ.." pseudo-nop above.
+	 */
+	nop
+#endif
+	.endm
+
+	.macro	__EFI_PE_HEADER
+#ifdef CONFIG_EFI_STUB
+	.set	.Lpe_header_offset, . - .L_head
+	.long	PE_MAGIC
+	.short	IMAGE_FILE_MACHINE_ARM64		// Machine
+	.short	.Lsection_count				// NumberOfSections
+	.long	0 					// TimeDateStamp
+	.long	0					// PointerToSymbolTable
+	.long	0					// NumberOfSymbols
+	.short	.Lsection_table - .Loptional_header	// SizeOfOptionalHeader
+	.short	IMAGE_FILE_DEBUG_STRIPPED | \
+		IMAGE_FILE_EXECUTABLE_IMAGE | \
+		IMAGE_FILE_LINE_NUMS_STRIPPED		// Characteristics
+
+.Loptional_header:
+	.short	PE_OPT_MAGIC_PE32PLUS			// PE32+ format
+	.byte	0x02					// MajorLinkerVersion
+	.byte	0x14					// MinorLinkerVersion
+	.long	_sdata - .Lefi_header_end		// SizeOfCode
+	.long	__pecoff_data_size			// SizeOfInitializedData
+	.long	0					// SizeOfUninitializedData
+	.long	__efistub_efi_pe_entry - .L_head	// AddressOfEntryPoint
+	.long	.Lefi_header_end - .L_head		// BaseOfCode
+
+	.quad	0					// ImageBase
+	.long	PBL_SEGMENT_ALIGN			// SectionAlignment
+	.long	PECOFF_FILE_ALIGNMENT			// FileAlignment
+	.short	0					// MajorOperatingSystemVersion
+	.short	0					// MinorOperatingSystemVersion
+	.short	LINUX_EFISTUB_MAJOR_VERSION		// MajorImageVersion
+	.short	LINUX_EFISTUB_MINOR_VERSION		// MinorImageVersion
+	.short	0					// MajorSubsystemVersion
+	.short	0					// MinorSubsystemVersion
+	.long	0					// Win32VersionValue
+
+	.long	__image_end - .L_head			// SizeOfImage
+
+	// Everything before the kernel image is considered part of the header
+	.long	.Lefi_header_end - .L_head		// SizeOfHeaders
+	.long	0					// CheckSum
+	.short	IMAGE_SUBSYSTEM_EFI_APPLICATION		// Subsystem
+	.short	0					// DllCharacteristics
+	.quad	0					// SizeOfStackReserve
+	.quad	0					// SizeOfStackCommit
+	.quad	0					// SizeOfHeapReserve
+	.quad	0					// SizeOfHeapCommit
+	.long	0					// LoaderFlags
+	.long	(.Lsection_table - .) / 8		// NumberOfRvaAndSizes
+
+	.quad	0					// ExportTable
+	.quad	0					// ImportTable
+	.quad	0					// ResourceTable
+	.quad	0					// ExceptionTable
+	.quad	0					// CertificationTable
+	.quad	0					// BaseRelocationTable
+
+	// Section table
+.Lsection_table:
+	.ascii	".text\0\0\0"
+	.long	_sdata - .Lefi_header_end		// VirtualSize
+	.long	.Lefi_header_end - .L_head		// VirtualAddress
+	.long	_sdata - .Lefi_header_end		// SizeOfRawData
+	.long	.Lefi_header_end - .L_head		// PointerToRawData
+
+	.long	0					// PointerToRelocations
+	.long	0					// PointerToLineNumbers
+	.short	0					// NumberOfRelocations
+	.short	0					// NumberOfLineNumbers
+	.long	IMAGE_SCN_CNT_CODE | \
+		IMAGE_SCN_MEM_READ | \
+		IMAGE_SCN_MEM_EXECUTE			// Characteristics
+
+	.ascii	".data\0\0\0"
+	.long	__pecoff_data_size			// VirtualSize
+	.long	_sdata - .L_head			// VirtualAddress
+	.long	__pecoff_data_rawsize			// SizeOfRawData
+	.long	_sdata - .L_head			// PointerToRawData
+
+	.long	0					// PointerToRelocations
+	.long	0					// PointerToLineNumbers
+	.short	0					// NumberOfRelocations
+	.short	0					// NumberOfLineNumbers
+	.long	IMAGE_SCN_CNT_INITIALIZED_DATA | \
+		IMAGE_SCN_MEM_READ | \
+		IMAGE_SCN_MEM_WRITE			// Characteristics
+
+	.set	.Lsection_count, (. - .Lsection_table) / 40
+
+	.balign	PBL_SEGMENT_ALIGN
+.Lefi_header_end:
+#else
+	.set	.Lpe_header_offset, 0x0
+#endif
+	.endm
diff --git a/arch/arm/cpu/entry.c b/arch/arm/cpu/entry.c
index 0b447de801..cc08d0ff7e 100644
--- a/arch/arm/cpu/entry.c
+++ b/arch/arm/cpu/entry.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <types.h>
 
 #include <asm/cache.h>
@@ -38,5 +40,8 @@ void NAKED __noreturn barebox_arm_entry(unsigned long membase,
 					unsigned long memsize, void *boarddata)
 {
 	__barebox_arm_entry(membase, memsize, boarddata,
-			    arm_mem_stack_top(membase, membase + memsize));
+			    arm_mem_stack_top(membase + memsize));
 }
+
+void __noreturn barebox_pbl_entry(ulong, ulong, void *)
+	__alias(barebox_arm_entry);
diff --git a/arch/arm/cpu/entry.h b/arch/arm/cpu/entry.h
index 18110eadf3..ba0d3a25fe 100644
--- a/arch/arm/cpu/entry.h
+++ b/arch/arm/cpu/entry.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ENTRY_H__
 #define __ENTRY_H__
 
diff --git a/arch/arm/cpu/entry_ll.S b/arch/arm/cpu/entry_ll_32.S
index 8cc7a84f10..2800174c45 100644
--- a/arch/arm/cpu/entry_ll.S
+++ b/arch/arm/cpu/entry_ll_32.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <asm/sections.h>
 
diff --git a/arch/arm/cpu/entry_ll_64.S b/arch/arm/cpu/entry_ll_64.S
index fb8645e0a0..6530bec5eb 100644
--- a/arch/arm/cpu/entry_ll_64.S
+++ b/arch/arm/cpu/entry_ll_64.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <asm/sections.h>
 
diff --git a/arch/arm/cpu/exceptions.S b/arch/arm/cpu/exceptions_32.S
index 55014c8d46..749c713aab 100644
--- a/arch/arm/cpu/exceptions.S
+++ b/arch/arm/cpu/exceptions_32.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <config.h>
 #include <linux/linkage.h>
 #include <asm-generic/memory_layout.h>
diff --git a/arch/arm/cpu/head_64.S b/arch/arm/cpu/head_64.S
new file mode 100644
index 0000000000..546efc263a
--- /dev/null
+++ b/arch/arm/cpu/head_64.S
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <linux/linkage.h>
+#include <asm/barebox-arm64.h>
+#include <asm/image.h>
+
+/* Linker will point these at board-specific symbols */
+.globl __pbl_board_stack_top
+.globl __pbl_board_entry
+
+.section .text_head_prologue_common, "x"
+ENTRY(__barebox_arm64_head)
+	nop
+	adr x9, __pbl_board_stack_top
+	ldr x9, [x9]
+	cbz x9, 1f
+	mov sp, x9
+1:
+#ifdef CONFIG_PBL_BREAK
+	brk #17
+	nop
+#else
+	nop
+	nop
+#endif
+	b __pbl_board_entry
+	.org 0x20
+	.asciz "barebox"
+	.word 0xffffffff
+	.word _barebox_image_size	/* image size to copy */
+	.rept 8
+	.word 0x55555555
+	.endr
+ENDPROC(__barebox_arm64_head)
diff --git a/arch/arm/cpu/hyp.S b/arch/arm/cpu/hyp.S
index 1314b56eab..b5e4807877 100644
--- a/arch/arm/cpu/hyp.S
+++ b/arch/arm/cpu/hyp.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <asm/system.h>
 #include <asm/opcodes-virt.h>
diff --git a/arch/arm/cpu/interrupts.c b/arch/arm/cpu/interrupts_32.c
index a1728eb353..468dcdd30e 100644
--- a/arch/arm/cpu/interrupts.c
+++ b/arch/arm/cpu/interrupts_32.c
@@ -8,7 +8,9 @@
 
 #include <common.h>
 #include <abort.h>
+#include <linux/sizes.h>
 #include <asm/ptrace.h>
+#include <asm/barebox-arm.h>
 #include <asm/unwind.h>
 #include <init.h>
 
@@ -68,7 +70,7 @@ static void __noreturn do_exception(struct pt_regs *pt_regs)
 {
 	show_regs(pt_regs);
 
-	panic("");
+	panic_no_stacktrace("");
 }
 
 /**
@@ -106,6 +108,22 @@ void do_prefetch_abort (struct pt_regs *pt_regs)
 	do_exception(pt_regs);
 }
 
+static const char *data_abort_reason(ulong far)
+{
+	ulong guard_page;
+
+	if (far < PAGE_SIZE)
+		return "NULL pointer dereference";
+
+	if (IS_ENABLED(CONFIG_STACK_GUARD_PAGE)) {
+		guard_page = arm_mem_guard_page_get();
+		if (guard_page <= far && far < guard_page + PAGE_SIZE)
+			return "stack overflow";
+	}
+
+	return "paging request";
+}
+
 /**
  * The CPU catches a data abort. That really should not happen!
  * @param[in] pt_regs Register set content when the accident happens
@@ -119,8 +137,7 @@ void do_data_abort (struct pt_regs *pt_regs)
 	asm volatile ("mrc     p15, 0, %0, c6, c0, 0" : "=r" (far) : : "cc");
 
 	printf("unable to handle %s at address 0x%08x\n",
-			far < PAGE_SIZE ? "NULL pointer dereference" :
-			"paging request", far);
+	       data_abort_reason(far), far);
 
 	do_exception(pt_regs);
 }
diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index f54fdcd3dd..6262ba8872 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -6,10 +6,12 @@
 #include <common.h>
 #include <abort.h>
 #include <asm/ptrace.h>
+#include <asm/barebox-arm.h>
 #include <asm/unwind.h>
 #include <init.h>
 #include <asm/system.h>
 #include <asm/esr.h>
+#include <efi/efi-mode.h>
 
 /* Avoid missing prototype warning, called from assembly */
 void do_bad_sync (struct pt_regs *pt_regs);
@@ -88,7 +90,7 @@ static void __noreturn do_exception(struct pt_regs *pt_regs)
 
 	unwind_backtrace(pt_regs);
 
-	panic("panic: unhandled exception");
+	panic_no_stacktrace("panic: unhandled exception");
 }
 
 /**
@@ -142,17 +144,38 @@ void do_bad_error(struct pt_regs *pt_regs)
 extern volatile int arm_ignore_data_abort;
 extern volatile int arm_data_abort_occurred;
 
+static const char *data_abort_reason(ulong far)
+{
+	ulong guard_page;
+
+	if (far < PAGE_SIZE)
+		return "NULL pointer dereference: ";
+
+	if (IS_ENABLED(CONFIG_STACK_GUARD_PAGE)) {
+		guard_page = arm_mem_guard_page_get();
+		if (guard_page <= far && far < guard_page + PAGE_SIZE)
+			return "Stack overflow: ";
+	}
+
+	return NULL;
+}
+
 void do_sync(struct pt_regs *pt_regs, unsigned int esr, unsigned long far)
 {
-	if ((esr >> ESR_ELx_EC_SHIFT) == ESR_ELx_EC_DABT_CUR &&
-			arm_ignore_data_abort) {
-		arm_data_abort_occurred = 1;
-		pt_regs->elr += 4;
-		return;
+	const char *extra = NULL;
+
+	if ((esr >> ESR_ELx_EC_SHIFT) == ESR_ELx_EC_DABT_CUR) {
+		if (arm_ignore_data_abort) {
+			arm_data_abort_occurred = 1;
+			pt_regs->elr += 4;
+			return;
+		}
+
+		extra = data_abort_reason(far);
 	}
 
-	printf("%s exception (ESR 0x%08x) at 0x%016lx\n", esr_get_class_string(esr),
-	       esr, far);
+	printf("%s%s exception (ESR 0x%08x) at 0x%016lx\n", extra ?: "",
+	       esr_get_class_string(esr), esr, far);
 	do_exception(pt_regs);
 }
 
@@ -182,6 +205,9 @@ static int aarch64_init_vectors(void)
 {
 	unsigned int el;
 
+	if (efi_is_payload())
+		return 0;
+
 	el = current_el();
 	switch (el) {
 	case 3:
@@ -199,4 +225,4 @@ static int aarch64_init_vectors(void)
 
 	return 0;
 }
-pure_initcall(aarch64_init_vectors);
+core_initcall(aarch64_init_vectors);
diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel_32.S
index 203a4afc47..960a92b78c 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel_32.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <init.h>
 #include <asm/system.h>
@@ -7,6 +9,8 @@
 ENTRY(arm_cpu_lowlevel_init)
 	/* save lr, since it may be banked away with a processor mode change */
 	mov	r2, lr
+	/* save sp, because possible HYP -> SVC transition below clobbers it */
+	mov	r3, sp
 
 #ifdef CONFIG_CPU_32v7
 	/* careful: the hyp install corrupts r0 and r1 */
@@ -75,6 +79,7 @@ THUMB(	orr	r12, r12, #PSR_T_BIT	)
 
 	mcr	p15, 0, r12, c1, c0, 0		/* SCTLR */
 
+	mov	sp, r3
 	mov	pc, r2
 ENDPROC(arm_cpu_lowlevel_init)
 
diff --git a/arch/arm/cpu/lowlevel_64.S b/arch/arm/cpu/lowlevel_64.S
index 6a23132ed1..ed00c8c470 100644
--- a/arch/arm/cpu/lowlevel_64.S
+++ b/arch/arm/cpu/lowlevel_64.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <init.h>
 #include <asm/system.h>
diff --git a/arch/arm/cpu/mmu-common.c b/arch/arm/cpu/mmu-common.c
index 5cc5138cfa..aeaf6c269d 100644
--- a/arch/arm/cpu/mmu-common.c
+++ b/arch/arm/cpu/mmu-common.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 
 #define pr_fmt(fmt)	"mmu: " fmt
 
@@ -7,17 +9,17 @@
 #include <dma.h>
 #include <mmu.h>
 #include <asm/system.h>
+#include <asm/barebox-arm.h>
 #include <memory.h>
-#include "mmu.h"
+#include <zero_page.h>
+#include "mmu-common.h"
+#include <efi/efi-mode.h>
 
-void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
-			     enum dma_data_direction dir)
+void arch_sync_dma_for_cpu(void *vaddr, size_t size,
+			   enum dma_data_direction dir)
 {
-	/*
-	 * FIXME: This function needs a device argument to support non 1:1 mappings
-	 */
 	if (dir != DMA_TO_DEVICE)
-		dma_inv_range((void *)address, size);
+		dma_inv_range(vaddr, size);
 }
 
 void *dma_alloc_map(size_t size, dma_addr_t *dma_handle, unsigned flags)
@@ -32,7 +34,7 @@ void *dma_alloc_map(size_t size, dma_addr_t *dma_handle, unsigned flags)
 	memset(ret, 0, size);
 	dma_flush_range(ret, size);
 
-	arch_remap_range(ret, size, flags);
+	remap_range(ret, size, flags);
 
 	return ret;
 }
@@ -49,21 +51,44 @@ void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
 void dma_free_coherent(void *mem, dma_addr_t dma_handle, size_t size)
 {
 	size = PAGE_ALIGN(size);
-	arch_remap_range(mem, size, MAP_CACHED);
+	remap_range(mem, size, MAP_CACHED);
 
 	free(mem);
 }
 
+void zero_page_access(void)
+{
+	remap_range(0x0, PAGE_SIZE, MAP_CACHED);
+}
+
+void zero_page_faulting(void)
+{
+	remap_range(0x0, PAGE_SIZE, MAP_FAULT);
+}
+
 static int mmu_init(void)
 {
-	if (list_empty(&memory_banks))
+	if (efi_is_payload())
+		return 0;
+
+	if (list_empty(&memory_banks)) {
+		resource_size_t start;
+		int ret;
+
 		/*
 		 * If you see this it means you have no memory registered.
 		 * This can be done either with arm_add_mem_device() in an
 		 * initcall prior to mmu_initcall or via devicetree in the
 		 * memory node.
 		 */
-		panic("MMU: No memory bank found! Cannot continue\n");
+		pr_emerg("No memory bank registered. Limping along with initial memory\n");
+
+		start = arm_mem_membase_get();
+		ret = barebox_add_memory_bank("initmem", start,
+					      arm_mem_endmem_get() - start);
+		if (ret)
+			panic("");
+	}
 
 	__mmu_init(get_cr() & CR_M);
 
diff --git a/arch/arm/cpu/mmu-common.h b/arch/arm/cpu/mmu-common.h
index 0a33b138e1..7a69122ee6 100644
--- a/arch/arm/cpu/mmu-common.h
+++ b/arch/arm/cpu/mmu-common.h
@@ -1,6 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ARM_MMU_COMMON_H
 #define __ARM_MMU_COMMON_H
 
+#include <printk.h>
+#include <linux/types.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+
 void dma_inv_range(void *ptr, size_t size);
 void dma_flush_range(void *ptr, size_t size);
 void *dma_alloc_map(size_t size, dma_addr_t *dma_handle, unsigned flags);
@@ -17,4 +25,14 @@ static inline void arm_mmu_not_initialized_error(void)
 	panic("MMU not initialized\n");
 }
 
-#endif
\ No newline at end of file
+static inline size_t resource_first_page(const struct resource *res)
+{
+	return ALIGN_DOWN(res->start, SZ_4K);
+}
+
+static inline size_t resource_count_pages(const struct resource *res)
+{
+	return ALIGN(resource_size(res), SZ_4K);
+}
+
+#endif
diff --git a/arch/arm/cpu/mmu-early.c b/arch/arm/cpu/mmu-early.c
deleted file mode 100644
index b985aa455f..0000000000
--- a/arch/arm/cpu/mmu-early.c
+++ /dev/null
@@ -1,69 +0,0 @@
-#include <common.h>
-#include <asm/mmu.h>
-#include <errno.h>
-#include <linux/sizes.h>
-#include <asm/memory.h>
-#include <asm/system.h>
-#include <asm/cache.h>
-#include <asm-generic/sections.h>
-
-#include "mmu.h"
-
-static uint32_t *ttb;
-
-static inline void map_region(unsigned long start, unsigned long size,
-			      uint64_t flags)
-
-{
-	start = ALIGN_DOWN(start, SZ_1M);
-	size  = ALIGN(size, SZ_1M);
-
-	create_sections(ttb, start, start + size - 1, flags);
-}
-
-void mmu_early_enable(unsigned long membase, unsigned long memsize,
-		      unsigned long _ttb)
-{
-	ttb = (uint32_t *)_ttb;
-
-	arm_set_cache_functions();
-
-	set_ttbr(ttb);
-
-	/* For the XN bit to take effect, we can't be using DOMAIN_MANAGER. */
-	if (cpu_architecture() >= CPU_ARCH_ARMv7)
-		set_domain(DOMAIN_CLIENT);
-	else
-		set_domain(DOMAIN_MANAGER);
-
-	/*
-	 * This marks the whole address space as uncachable as well as
-	 * unexecutable if possible
-	 */
-	create_flat_mapping(ttb);
-
-	/*
-	 * There can be SoCs that have a section shared between device memory
-	 * and the on-chip RAM hosting the PBL. Thus mark this section
-	 * uncachable, but executable.
-	 * On such SoCs, executing from OCRAM could cause the instruction
-	 * prefetcher to speculatively access that device memory, triggering
-	 * potential errant behavior.
-	 *
-	 * If your SoC has such a memory layout, you should rewrite the code
-	 * here to map the OCRAM page-wise.
-	 */
-	map_region((unsigned long)_stext, _etext - _stext, PMD_SECT_DEF_UNCACHED);
-
-	/* maps main memory as cachable */
-	map_region(membase, memsize, PMD_SECT_DEF_CACHED);
-
-	/*
-	 * With HAB enabled we call into the ROM code later in imx6_hab_get_status().
-	 * Map the ROM cached which has the effect that the XN bit is not set.
-	 */
-	if (IS_ENABLED(CONFIG_HABV4) && IS_ENABLED(CONFIG_ARCH_IMX6))
-		map_region(0x0, SZ_1M, PMD_SECT_DEF_CACHED);
-
-	__mmu_cache_on();
-}
diff --git a/arch/arm/cpu/mmu-early_64.c b/arch/arm/cpu/mmu-early_64.c
deleted file mode 100644
index a7598f28aa..0000000000
--- a/arch/arm/cpu/mmu-early_64.c
+++ /dev/null
@@ -1,91 +0,0 @@
-#include <common.h>
-#include <dma-dir.h>
-#include <init.h>
-#include <mmu.h>
-#include <errno.h>
-#include <linux/sizes.h>
-#include <asm/memory.h>
-#include <asm/pgtable64.h>
-#include <asm/barebox-arm.h>
-#include <asm/system.h>
-#include <asm/cache.h>
-#include <memory.h>
-#include <asm/system_info.h>
-
-#include "mmu_64.h"
-
-static void create_sections(void *ttb, uint64_t virt, uint64_t phys,
-			    uint64_t size, uint64_t attr)
-{
-	uint64_t block_size;
-	uint64_t block_shift;
-	uint64_t *pte;
-	uint64_t idx;
-	uint64_t addr;
-	uint64_t *table;
-
-	addr = virt;
-
-	attr &= ~PTE_TYPE_MASK;
-
-	table = ttb;
-
-	while (1) {
-		block_shift = level2shift(1);
-		idx = (addr & level2mask(1)) >> block_shift;
-		block_size = (1ULL << block_shift);
-
-		pte = table + idx;
-
-		*pte = phys | attr | PTE_TYPE_BLOCK;
-
-		if (size < block_size)
-			break;
-
-		addr += block_size;
-		phys += block_size;
-		size -= block_size;
-	}
-}
-
-#define EARLY_BITS_PER_VA 39
-
-void mmu_early_enable(unsigned long membase, unsigned long memsize,
-		      unsigned long ttb)
-{
-	int el;
-
-	/*
-	 * For the early code we only create level 1 pagetables which only
-	 * allow for a 1GiB granularity. If our membase is not aligned to that
-	 * bail out without enabling the MMU.
-	 */
-	if (membase & ((1ULL << level2shift(1)) - 1))
-		return;
-
-	memset((void *)ttb, 0, GRANULE_SIZE);
-
-	el = current_el();
-	set_ttbr_tcr_mair(el, ttb, calc_tcr(el, EARLY_BITS_PER_VA), MEMORY_ATTRIBUTES);
-	create_sections((void *)ttb, 0, 0, 1UL << (EARLY_BITS_PER_VA - 1),
-			attrs_uncached_mem());
-	create_sections((void *)ttb, membase, membase, memsize, CACHED_MEM);
-	tlb_invalidate();
-	isb();
-	set_cr(get_cr() | CR_M);
-}
-
-void mmu_early_disable(void)
-{
-	unsigned int cr;
-
-	cr = get_cr();
-	cr &= ~(CR_M | CR_C);
-
-	set_cr(cr);
-	v8_flush_dcache_all();
-	tlb_invalidate();
-
-	dsb();
-	isb();
-}
\ No newline at end of file
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu_32.c
index 6af228505d..3a8d025ecd 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu_32.c
@@ -9,6 +9,7 @@
 #include <init.h>
 #include <mmu.h>
 #include <errno.h>
+#include <zero_page.h>
 #include <linux/sizes.h>
 #include <asm/memory.h>
 #include <asm/barebox-arm.h>
@@ -17,13 +18,18 @@
 #include <memory.h>
 #include <asm/system_info.h>
 #include <asm/sections.h>
+#include <linux/pagemap.h>
 
-#include "mmu.h"
+#include "mmu_32.h"
 
 #define PTRS_PER_PTE		(PGDIR_SIZE / PAGE_SIZE)
 #define ARCH_MAP_WRITECOMBINE	((unsigned)-1)
 
-static uint32_t *ttb;
+static inline uint32_t *get_ttb(void)
+{
+	/* Clear unpredictable bits [13:0] */
+	return (uint32_t *)(get_ttbr() & ~0x3fff);
+}
 
 /*
  * Do it the simple way for now and invalidate the entire
@@ -52,29 +58,36 @@ static inline void tlb_invalidate(void)
 			 PMD_SECT_BUFFERABLE | PMD_SECT_XN)
 #define PGD_FLAGS_UNCACHED_V7 (PMD_SECT_DEF_UNCACHED | PMD_SECT_XN)
 
-/*
- * PTE flags to set cached and uncached areas.
- * This will be determined at runtime.
- */
-static uint32_t pte_flags_cached;
-static uint32_t pte_flags_wc;
-static uint32_t pte_flags_uncached;
-static uint32_t pgd_flags_wc;
-static uint32_t pgd_flags_uncached;
-
-#define PTE_MASK ((1 << 12) - 1)
-
 static bool pgd_type_table(u32 pgd)
 {
 	return (pgd & PMD_TYPE_MASK) == PMD_TYPE_TABLE;
 }
 
+#define PTE_SIZE       (PTRS_PER_PTE * sizeof(u32))
+
+#ifdef __PBL__
+static uint32_t *alloc_pte(void)
+{
+	static unsigned int idx = 3;
+
+	idx++;
+
+	if (idx * PTE_SIZE >= ARM_EARLY_PAGETABLE_SIZE)
+		return NULL;
+
+	return get_ttb() + idx * PTE_SIZE;
+}
+#else
+static uint32_t *alloc_pte(void)
+{
+	return xmemalign(PTE_SIZE, PTE_SIZE);
+}
+#endif
+
 static u32 *find_pte(unsigned long adr)
 {
 	u32 *table;
-
-	if (!ttb)
-		arm_mmu_not_initialized_error();
+	uint32_t *ttb = get_ttb();
 
 	if (!pgd_type_table(ttb[pgd_index(adr)]))
 		return NULL;
@@ -92,6 +105,7 @@ void dma_flush_range(void *ptr, size_t size)
 	unsigned long end = start + size;
 
 	__dma_flush_range(start, end);
+
 	if (outer_cache.flush_range)
 		outer_cache.flush_range(start, end);
 }
@@ -103,6 +117,7 @@ void dma_inv_range(void *ptr, size_t size)
 
 	if (outer_cache.inv_range)
 		outer_cache.inv_range(start, end);
+
 	__dma_inv_range(start, end);
 }
 
@@ -111,24 +126,24 @@ void dma_inv_range(void *ptr, size_t size)
  * We initially create a flat uncached mapping on it.
  * Not yet exported, but may be later if someone finds use for it.
  */
-static u32 *arm_create_pte(unsigned long virt, uint32_t flags)
+static u32 *arm_create_pte(unsigned long virt, unsigned long phys,
+			   uint32_t flags)
 {
+	uint32_t *ttb = get_ttb();
 	u32 *table;
 	int i, ttb_idx;
 
 	virt = ALIGN_DOWN(virt, PGDIR_SIZE);
+	phys = ALIGN_DOWN(phys, PGDIR_SIZE);
 
-	table = xmemalign(PTRS_PER_PTE * sizeof(u32),
-			  PTRS_PER_PTE * sizeof(u32));
-
-	if (!ttb)
-		arm_mmu_not_initialized_error();
+	table = alloc_pte();
 
 	ttb_idx = pgd_index(virt);
 
 	for (i = 0; i < PTRS_PER_PTE; i++) {
-		table[i] = virt | PTE_TYPE_SMALL | flags;
+		table[i] = phys | PTE_TYPE_SMALL | flags;
 		virt += PAGE_SIZE;
+		phys += PAGE_SIZE;
 	}
 	dma_flush_range(table, PTRS_PER_PTE * sizeof(u32));
 
@@ -138,44 +153,125 @@ static u32 *arm_create_pte(unsigned long virt, uint32_t flags)
 	return table;
 }
 
-int arch_remap_range(void *start, size_t size, unsigned flags)
+static u32 pmd_flags_to_pte(u32 pmd)
 {
-	u32 addr = (u32)start;
-	u32 pte_flags;
-	u32 pgd_flags;
-
-	BUG_ON(!IS_ALIGNED(addr, PAGE_SIZE));
-
-	switch (flags) {
-	case MAP_CACHED:
-		pte_flags = pte_flags_cached;
-		pgd_flags = PMD_SECT_DEF_CACHED;
-		break;
-	case MAP_UNCACHED:
-		pte_flags = pte_flags_uncached;
-		pgd_flags = pgd_flags_uncached;
-		break;
-	case ARCH_MAP_WRITECOMBINE:
-		pte_flags = pte_flags_wc;
-		pgd_flags = pgd_flags_wc;
-		break;
-	default:
-		return -EINVAL;
+	u32 pte = 0;
+
+	if (pmd & PMD_SECT_BUFFERABLE)
+		pte |= PTE_BUFFERABLE;
+	if (pmd & PMD_SECT_CACHEABLE)
+		pte |= PTE_CACHEABLE;
+
+	if (cpu_architecture() >= CPU_ARCH_ARMv7) {
+		if (pmd & PMD_SECT_nG)
+			pte |= PTE_EXT_NG;
+		if (pmd & PMD_SECT_XN)
+			pte |= PTE_EXT_XN;
+
+		/* TEX[2:0] */
+		pte |= PTE_EXT_TEX((pmd >> 12) & 7);
+		/* AP[1:0] */
+		pte |= ((pmd >> 10) & 0x3) << 4;
+		/* AP[2] */
+		pte |= ((pmd >> 15) & 0x1) << 9;
+	} else {
+		pte |= PTE_SMALL_AP_UNO_SRW;
 	}
 
+	return pte;
+}
+
+static u32 pte_flags_to_pmd(u32 pte)
+{
+	u32 pmd = 0;
+
+	if (pte & PTE_BUFFERABLE)
+		pmd |= PMD_SECT_BUFFERABLE;
+	if (pte & PTE_CACHEABLE)
+		pmd |= PMD_SECT_CACHEABLE;
+
+	if (cpu_architecture() >= CPU_ARCH_ARMv7) {
+		if (pte & PTE_EXT_NG)
+			pmd |= PMD_SECT_nG;
+		if (pte & PTE_EXT_XN)
+			pmd |= PMD_SECT_XN;
+
+		/* TEX[2:0] */
+		pmd |= ((pte >> 6) & 7) << 12;
+		/* AP[1:0] */
+		pmd |= ((pte >> 4) & 0x3) << 10;
+		/* AP[2] */
+		pmd |= ((pte >> 9) & 0x1) << 15;
+	} else {
+		pmd |= PMD_SECT_AP_WRITE | PMD_SECT_AP_READ;
+	}
+
+	return pmd;
+}
+
+static uint32_t get_pte_flags(int map_type)
+{
+	if (cpu_architecture() >= CPU_ARCH_ARMv7) {
+		switch (map_type) {
+		case MAP_CACHED:
+			return PTE_FLAGS_CACHED_V7;
+		case MAP_UNCACHED:
+			return PTE_FLAGS_UNCACHED_V7;
+		case ARCH_MAP_WRITECOMBINE:
+			return PTE_FLAGS_WC_V7;
+		case MAP_FAULT:
+		default:
+			return 0x0;
+		}
+	} else {
+		switch (map_type) {
+		case MAP_CACHED:
+			return PTE_FLAGS_CACHED_V4;
+		case MAP_UNCACHED:
+		case ARCH_MAP_WRITECOMBINE:
+			return PTE_FLAGS_UNCACHED_V4;
+		case MAP_FAULT:
+		default:
+			return 0x0;
+		}
+	}
+}
+
+static uint32_t get_pmd_flags(int map_type)
+{
+	return pte_flags_to_pmd(get_pte_flags(map_type));
+}
+
+static void __arch_remap_range(void *_virt_addr, phys_addr_t phys_addr, size_t size, unsigned map_type)
+{
+	u32 virt_addr = (u32)_virt_addr;
+	u32 pte_flags, pmd_flags;
+	uint32_t *ttb = get_ttb();
+
+	BUG_ON(!IS_ALIGNED(virt_addr, PAGE_SIZE));
+	BUG_ON(!IS_ALIGNED(phys_addr, PAGE_SIZE));
+
+	pte_flags = get_pte_flags(map_type);
+	pmd_flags = pte_flags_to_pmd(pte_flags);
+
+	size = PAGE_ALIGN(size);
+
 	while (size) {
-		const bool pgdir_size_aligned = IS_ALIGNED(addr, PGDIR_SIZE);
-		u32 *pgd = (u32 *)&ttb[pgd_index(addr)];
+		const bool pgdir_size_aligned = IS_ALIGNED(virt_addr, PGDIR_SIZE);
+		u32 *pgd = (u32 *)&ttb[pgd_index(virt_addr)];
 		size_t chunk;
 
 		if (size >= PGDIR_SIZE && pgdir_size_aligned &&
+		    IS_ALIGNED(phys_addr, PGDIR_SIZE) &&
 		    !pgd_type_table(*pgd)) {
 			/*
 			 * TODO: Add code to discard a page table and
 			 * replace it with a section
 			 */
 			chunk = PGDIR_SIZE;
-			*pgd = addr | pgd_flags;
+			*pgd = phys_addr | pmd_flags;
+			if (map_type != MAP_FAULT)
+				*pgd |= PMD_TYPE_SECT;
 			dma_flush_range(pgd, sizeof(*pgd));
 		} else {
 			unsigned int num_ptes;
@@ -190,7 +286,7 @@ int arch_remap_range(void *start, size_t size, unsigned flags)
 			 * was not aligned on PGDIR_SIZE boundary)
 			 */
 			chunk = pgdir_size_aligned ?
-				PGDIR_SIZE : ALIGN(addr, PGDIR_SIZE) - addr;
+				PGDIR_SIZE : ALIGN(virt_addr, PGDIR_SIZE) - virt_addr;
 			/*
 			 * At the same time we want to make sure that
 			 * we don't go on remapping past requested
@@ -200,43 +296,78 @@ int arch_remap_range(void *start, size_t size, unsigned flags)
 			chunk = min(chunk, size);
 			num_ptes = chunk / PAGE_SIZE;
 
-			pte = find_pte(addr);
+			pte = find_pte(virt_addr);
 			if (!pte) {
 				/*
 				 * If PTE is not found it means that
 				 * we needs to split this section and
 				 * create a new page table for it
-				 *
-				 * NOTE: Here we assume that section
-				 * we just split was mapped as cached
 				 */
-				table = arm_create_pte(addr, pte_flags_cached);
-				pte = find_pte(addr);
+				table = arm_create_pte(virt_addr, phys_addr,
+						       pmd_flags_to_pte(*pgd));
+				pte = find_pte(virt_addr);
 				BUG_ON(!pte);
 			}
 
 			for (i = 0; i < num_ptes; i++) {
-				pte[i] &= ~PTE_MASK;
-				pte[i] |= pte_flags | PTE_TYPE_SMALL;
+				pte[i] = phys_addr + i * PAGE_SIZE;
+				pte[i] |= pte_flags;
+				if (map_type != MAP_FAULT)
+					pte[i] |= PTE_TYPE_SMALL;
 			}
 
 			dma_flush_range(pte, num_ptes * sizeof(u32));
 		}
 
-		addr += chunk;
+		virt_addr += chunk;
+		phys_addr += chunk;
 		size -= chunk;
 	}
 
 	tlb_invalidate();
+}
+static void early_remap_range(u32 addr, size_t size, unsigned map_type)
+{
+	__arch_remap_range((void *)addr, addr, size, map_type);
+}
+
+int arch_remap_range(void *virt_addr, phys_addr_t phys_addr, size_t size, unsigned map_type)
+{
+	__arch_remap_range(virt_addr, phys_addr, size, map_type);
+
+	if (map_type == MAP_UNCACHED)
+		dma_inv_range(virt_addr, size);
+
 	return 0;
 }
 
+static void create_sections(unsigned long first, unsigned long last,
+			    unsigned int flags)
+{
+	uint32_t *ttb = get_ttb();
+	unsigned long ttb_start = pgd_index(first);
+	unsigned long ttb_end = pgd_index(last) + 1;
+	unsigned int i, addr = first;
+
+	for (i = ttb_start; i < ttb_end; i++) {
+		ttb[i] = addr | flags;
+		addr += PGDIR_SIZE;
+	}
+}
+
+static inline void create_flat_mapping(void)
+{
+	/* create a flat mapping using 1MiB sections */
+	create_sections(0, 0xffffffff, attrs_uncached_mem());
+}
+
 void *map_io_sections(unsigned long phys, void *_start, size_t size)
 {
 	unsigned long start = (unsigned long)_start, sec;
+	uint32_t *ttb = get_ttb();
 
 	for (sec = start; sec < start + size; sec += PGDIR_SIZE, phys += PGDIR_SIZE)
-		ttb[pgd_index(sec)] = phys | pgd_flags_uncached;
+		ttb[pgd_index(sec)] = phys | get_pmd_flags(MAP_UNCACHED);
 
 	dma_flush_range(ttb, 0x4000);
 	tlb_invalidate();
@@ -277,9 +408,9 @@ static void create_vector_table(unsigned long adr)
 		vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
 		pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
 			 vectors, adr);
-		arm_create_pte(adr, pte_flags_uncached);
+		arm_create_pte(adr, adr, get_pte_flags(MAP_UNCACHED));
 		pte = find_pte(adr);
-		*pte = (u32)vectors | PTE_TYPE_SMALL | pte_flags_cached;
+		*pte = (u32)vectors | PTE_TYPE_SMALL | get_pte_flags(MAP_CACHED);
 	}
 
 	arm_fixup_vectors();
@@ -337,21 +468,28 @@ static int set_vector_table(unsigned long adr)
 
 static void create_zero_page(void)
 {
-	struct resource *zero_sdram;
-	u32 *zero;
+	/*
+	 * In case the zero page is in SDRAM request it to prevent others
+	 * from using it
+	 */
+	request_sdram_region("zero page", 0x0, PAGE_SIZE);
 
-	zero_sdram = request_sdram_region("zero page", 0x0, PAGE_SIZE);
-	if (zero_sdram) {
-		/*
-		 * Here we would need to set the second level page table
-		 * entry to faulting. This is not yet implemented.
-		 */
-		pr_debug("zero page is in SDRAM area, currently not supported\n");
-	} else {
-		zero = arm_create_pte(0x0, pte_flags_uncached);
-		zero[0] = 0;
-		pr_debug("Created zero page\n");
-	}
+	zero_page_faulting();
+	pr_debug("Created zero page\n");
+}
+
+static void create_guard_page(void)
+{
+	ulong guard_page;
+
+	if (!IS_ENABLED(CONFIG_STACK_GUARD_PAGE))
+		return;
+
+	guard_page = arm_mem_guard_page_get();
+	request_sdram_region("guard page", guard_page, PAGE_SIZE);
+	remap_range((void *)guard_page, PAGE_SIZE, MAP_FAULT);
+
+	pr_debug("Created guard page\n");
 }
 
 /*
@@ -359,6 +497,8 @@ static void create_zero_page(void)
  */
 static void vectors_init(void)
 {
+	create_guard_page();
+
 	/*
 	 * First try to use the vectors where they actually are, works
 	 * on ARMv7 and later.
@@ -393,67 +533,44 @@ static void vectors_init(void)
 void __mmu_init(bool mmu_on)
 {
 	struct memory_bank *bank;
+	uint32_t *ttb = get_ttb();
 
-	arm_set_cache_functions();
-
-	if (cpu_architecture() >= CPU_ARCH_ARMv7) {
-		pte_flags_cached = PTE_FLAGS_CACHED_V7;
-		pte_flags_wc = PTE_FLAGS_WC_V7;
-		pgd_flags_wc = PGD_FLAGS_WC_V7;
-		pgd_flags_uncached = PGD_FLAGS_UNCACHED_V7;
-		pte_flags_uncached = PTE_FLAGS_UNCACHED_V7;
-	} else {
-		pte_flags_cached = PTE_FLAGS_CACHED_V4;
-		pte_flags_wc = PTE_FLAGS_UNCACHED_V4;
-		pgd_flags_wc = PMD_SECT_DEF_UNCACHED;
-		pgd_flags_uncached = PMD_SECT_DEF_UNCACHED;
-		pte_flags_uncached = PTE_FLAGS_UNCACHED_V4;
-	}
-
-	if (mmu_on) {
+	if (!request_sdram_region("ttb", (unsigned long)ttb,
+				  ARM_EARLY_PAGETABLE_SIZE))
 		/*
-		 * Early MMU code has already enabled the MMU. We assume a
-		 * flat 1:1 section mapping in this case.
+		 * This can mean that:
+		 * - the early MMU code has put the ttb into a place
+		 *   which we don't have inside our available memory
+		 * - Somebody else has occupied the ttb region which means
+		 *   the ttb will get corrupted.
 		 */
-		/* Clear unpredictable bits [13:0] */
-		ttb = (uint32_t *)(get_ttbr() & ~0x3fff);
-
-		if (!request_sdram_region("ttb", (unsigned long)ttb, SZ_16K))
-			/*
-			 * This can mean that:
-			 * - the early MMU code has put the ttb into a place
-			 *   which we don't have inside our available memory
-			 * - Somebody else has occupied the ttb region which means
-			 *   the ttb will get corrupted.
-			 */
-			pr_crit("Critical Error: Can't request SDRAM region for ttb at %p\n",
+		pr_crit("Critical Error: Can't request SDRAM region for ttb at %p\n",
 					ttb);
-	} else {
-		ttb = xmemalign(ARM_TTB_SIZE, ARM_TTB_SIZE);
-
-		set_ttbr(ttb);
 
-		/* For the XN bit to take effect, we can't be using DOMAIN_MANAGER. */
-		if (cpu_architecture() >= CPU_ARCH_ARMv7)
-			set_domain(DOMAIN_CLIENT);
-		else
-			set_domain(DOMAIN_MANAGER);
+	pr_debug("ttb: 0x%p\n", ttb);
 
-		create_flat_mapping(ttb);
-		__mmu_cache_flush();
-	}
+	/*
+	 * Early mmu init will have mapped everything but the initial memory area
+	 * (excluding final OPTEE_SIZE bytes) uncached. We have now discovered
+	 * all memory banks, so let's map all pages, excluding reserved memory areas,
+	 * cacheable and executable.
+	 */
+	for_each_memory_bank(bank) {
+		struct resource *rsv;
+		resource_size_t pos;
 
-	pr_debug("ttb: 0x%p\n", ttb);
+		pos = bank->start;
 
-	vectors_init();
+		/* Skip reserved regions */
+		for_each_reserved_region(bank, rsv) {
+			remap_range((void *)pos, rsv->start - pos, MAP_CACHED);
+			pos = rsv->end + 1;
+		}
 
-	for_each_memory_bank(bank) {
-		create_sections(ttb, bank->start, bank->start + bank->size - 1,
-				PMD_SECT_DEF_CACHED);
-		__mmu_cache_flush();
+		remap_range((void *)pos, bank->start + bank->size - pos, MAP_CACHED);
 	}
 
-	__mmu_cache_on();
+	vectors_init();
 }
 
 /*
@@ -474,20 +591,33 @@ void *dma_alloc_writecombine(size_t size, dma_addr_t *dma_handle)
 	return dma_alloc_map(size, dma_handle, ARCH_MAP_WRITECOMBINE);
 }
 
-void dma_sync_single_for_device(dma_addr_t address, size_t size,
-				enum dma_data_direction dir)
+void mmu_early_enable(unsigned long membase, unsigned long memsize)
 {
+	uint32_t *ttb = (uint32_t *)arm_mem_ttb(membase + memsize);
+
+	pr_debug("enabling MMU, ttb @ 0x%p\n", ttb);
+
+	if (get_cr() & CR_M)
+		return;
+
+	set_ttbr(ttb);
+
+	/* For the XN bit to take effect, we can't be using DOMAIN_MANAGER. */
+	if (cpu_architecture() >= CPU_ARCH_ARMv7)
+		set_domain(DOMAIN_CLIENT);
+	else
+		set_domain(DOMAIN_MANAGER);
+
 	/*
-	 * FIXME: This function needs a device argument to support non 1:1 mappings
+	 * This marks the whole address space as uncachable as well as
+	 * unexecutable if possible
 	 */
+	create_flat_mapping();
 
-	if (dir == DMA_FROM_DEVICE) {
-		__dma_inv_range(address, address + size);
-		if (outer_cache.inv_range)
-			outer_cache.inv_range(address, address + size);
-	} else {
-		__dma_clean_range(address, address + size);
-		if (outer_cache.clean_range)
-			outer_cache.clean_range(address, address + size);
-	}
+	/* maps main memory as cachable */
+	early_remap_range(membase, memsize - OPTEE_SIZE, MAP_CACHED);
+	early_remap_range(membase + memsize - OPTEE_SIZE, OPTEE_SIZE, MAP_UNCACHED);
+	early_remap_range(PAGE_ALIGN_DOWN((uintptr_t)_stext), PAGE_ALIGN(_etext - _stext), MAP_CACHED);
+
+	__mmu_cache_on();
 }
diff --git a/arch/arm/cpu/mmu.h b/arch/arm/cpu/mmu_32.h
index c85e0ea050..607d9e8608 100644
--- a/arch/arm/cpu/mmu.h
+++ b/arch/arm/cpu/mmu_32.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ARM_MMU_H
 #define __ARM_MMU_H
 
@@ -54,32 +56,17 @@ static inline void set_domain(unsigned val)
 	asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(val) /*:*/);
 }
 
-static inline void
-create_sections(uint32_t *ttb, unsigned long first,
-		unsigned long last, unsigned int flags)
-{
-	unsigned long ttb_start = pgd_index(first);
-	unsigned long ttb_end = pgd_index(last) + 1;
-	unsigned int i, addr = first;
-
-	for (i = ttb_start; i < ttb_end; i++) {
-		ttb[i] = addr | flags;
-		addr += PGDIR_SIZE;
-	}
-}
-
 #define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT)
 #define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED)
 
-static inline void create_flat_mapping(uint32_t *ttb)
+static inline unsigned long attrs_uncached_mem(void)
 {
 	unsigned int flags = PMD_SECT_DEF_UNCACHED;
 
 	if (cpu_architecture() >= CPU_ARCH_ARMv7)
 		flags |= PMD_SECT_XN;
 
-	/* create a flat mapping using 1MiB sections */
-	create_sections(ttb, 0, 0xffffffff, flags);
+	return flags;
 }
 
 #endif /* __ARM_MMU_H */
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 06049e0003..71c0d8930e 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -19,10 +19,15 @@
 #include <asm/cache.h>
 #include <memory.h>
 #include <asm/system_info.h>
+#include <linux/pagemap.h>
+#include <tee/optee.h>
 
 #include "mmu_64.h"
 
-static uint64_t *ttb;
+static uint64_t *get_ttb(void)
+{
+	return (uint64_t *)get_ttbr(current_el());
+}
 
 static void set_table(uint64_t *pt, uint64_t *table_addr)
 {
@@ -32,7 +37,20 @@ static void set_table(uint64_t *pt, uint64_t *table_addr)
 	*pt = val;
 }
 
-static uint64_t *create_table(void)
+#ifdef __PBL__
+static uint64_t *alloc_pte(void)
+{
+	static unsigned int idx;
+
+	idx++;
+
+	if (idx * GRANULE_SIZE >= ARM_EARLY_PAGETABLE_SIZE)
+		return NULL;
+
+	return (void *)get_ttb() + idx * GRANULE_SIZE;
+}
+#else
+static uint64_t *alloc_pte(void)
 {
 	uint64_t *new_table = xmemalign(GRANULE_SIZE, GRANULE_SIZE);
 
@@ -41,6 +59,7 @@ static uint64_t *create_table(void)
 
 	return new_table;
 }
+#endif
 
 static __maybe_unused uint64_t *find_pte(uint64_t addr)
 {
@@ -49,7 +68,7 @@ static __maybe_unused uint64_t *find_pte(uint64_t addr)
 	uint64_t idx;
 	int i;
 
-	pte = ttb;
+	pte = get_ttb();
 
 	for (i = 0; i < 4; i++) {
 		block_shift = level2shift(i);
@@ -81,7 +100,10 @@ static void split_block(uint64_t *pte, int level)
 	/* level describes the parent level, we need the child ones */
 	levelshift = level2shift(level + 1);
 
-	new_table = create_table();
+	new_table = alloc_pte();
+	if (!new_table)
+		panic("Unable to allocate PTE\n");
+
 
 	for (i = 0; i < MAX_PTE_ENTRIES; i++) {
 		new_table[i] = old_pte | (i << levelshift);
@@ -98,6 +120,7 @@ static void split_block(uint64_t *pte, int level)
 static void create_sections(uint64_t virt, uint64_t phys, uint64_t size,
 			    uint64_t attr)
 {
+	uint64_t *ttb = get_ttb();
 	uint64_t block_size;
 	uint64_t block_shift;
 	uint64_t *pte;
@@ -107,13 +130,12 @@ static void create_sections(uint64_t virt, uint64_t phys, uint64_t size,
 	uint64_t type;
 	int level;
 
-	if (!ttb)
-		arm_mmu_not_initialized_error();
-
 	addr = virt;
 
 	attr &= ~PTE_TYPE_MASK;
 
+	size = PAGE_ALIGN(size);
+
 	while (size) {
 		table = ttb;
 		for (level = 0; level < 4; level++) {
@@ -123,7 +145,8 @@ static void create_sections(uint64_t virt, uint64_t phys, uint64_t size,
 
 			pte = table + idx;
 
-			if (size >= block_size && IS_ALIGNED(addr, block_size)) {
+			if (size >= block_size && IS_ALIGNED(addr, block_size) &&
+			    IS_ALIGNED(phys, block_size)) {
 				type = (level == 3) ?
 					PTE_TYPE_PAGE : PTE_TYPE_BLOCK;
 				*pte = phys | attr | type;
@@ -143,23 +166,42 @@ static void create_sections(uint64_t virt, uint64_t phys, uint64_t size,
 	tlb_invalidate();
 }
 
-int arch_remap_range(void *_start, size_t size, unsigned flags)
+static unsigned long get_pte_attrs(unsigned flags)
 {
-	unsigned long attrs;
-
 	switch (flags) {
 	case MAP_CACHED:
-		attrs = CACHED_MEM;
-		break;
+		return CACHED_MEM;
 	case MAP_UNCACHED:
-		attrs = attrs_uncached_mem();
-		break;
+		return attrs_uncached_mem();
+	case MAP_FAULT:
+		return 0x0;
 	default:
-		return -EINVAL;
+		return ~0UL;
 	}
+}
+
+static void early_remap_range(uint64_t addr, size_t size, unsigned flags)
+{
+	unsigned long attrs = get_pte_attrs(flags);
+
+	if (WARN_ON(attrs == ~0UL))
+		return;
+
+	create_sections(addr, addr, size, attrs);
+}
+
+int arch_remap_range(void *virt_addr, phys_addr_t phys_addr, size_t size, unsigned flags)
+{
+	unsigned long attrs = get_pte_attrs(flags);
+
+	if (attrs == ~0UL)
+		return -EINVAL;
+
+	create_sections((uint64_t)virt_addr, phys_addr, (uint64_t)size, attrs);
+
+	if (flags == MAP_UNCACHED)
+		dma_inv_range(virt_addr, size);
 
-	create_sections((uint64_t)_start, (uint64_t)_start, (uint64_t)size,
-			attrs);
 	return 0;
 }
 
@@ -169,14 +211,18 @@ static void mmu_enable(void)
 	set_cr(get_cr() | CR_M | CR_C | CR_I);
 }
 
-void zero_page_access(void)
+static void create_guard_page(void)
 {
-	create_sections(0x0, 0x0, PAGE_SIZE, CACHED_MEM);
-}
+	ulong guard_page;
 
-void zero_page_faulting(void)
-{
-	create_sections(0x0, 0x0, PAGE_SIZE, 0x0);
+	if (!IS_ENABLED(CONFIG_STACK_GUARD_PAGE))
+		return;
+
+	guard_page = arm_mem_guard_page_get();
+	request_sdram_region("guard page", guard_page, PAGE_SIZE);
+	remap_range((void *)guard_page, PAGE_SIZE, MAP_FAULT);
+
+	pr_debug("Created guard page\n");
 }
 
 /*
@@ -184,30 +230,38 @@ void zero_page_faulting(void)
  */
 void __mmu_init(bool mmu_on)
 {
+	uint64_t *ttb = get_ttb();
 	struct memory_bank *bank;
-	unsigned int el;
-
-	if (mmu_on)
-		mmu_disable();
-
-	ttb = create_table();
-	el = current_el();
-	set_ttbr_tcr_mair(el, (uint64_t)ttb, calc_tcr(el, BITS_PER_VA),
-			  MEMORY_ATTRIBUTES);
-
-	pr_debug("ttb: 0x%p\n", ttb);
 
-	/* create a flat mapping */
-	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), attrs_uncached_mem());
+	if (!request_sdram_region("ttb", (unsigned long)ttb,
+				  ARM_EARLY_PAGETABLE_SIZE))
+		/*
+		 * This can mean that:
+		 * - the early MMU code has put the ttb into a place
+		 *   which we don't have inside our available memory
+		 * - Somebody else has occupied the ttb region which means
+		 *   the ttb will get corrupted.
+		 */
+		pr_crit("Can't request SDRAM region for ttb at %p\n", ttb);
+
+	for_each_memory_bank(bank) {
+		struct resource *rsv;
+		resource_size_t pos;
+
+		pos = bank->start;
+
+		/* Skip reserved regions */
+		for_each_reserved_region(bank, rsv) {
+			remap_range((void *)pos, rsv->start - pos, MAP_CACHED);
+			pos = rsv->end + 1;
+		}
 
-	/* Map sdram cached. */
-	for_each_memory_bank(bank)
-		create_sections(bank->start, bank->start, bank->size, CACHED_MEM);
+		remap_range((void *)pos, bank->start + bank->size - pos, MAP_CACHED);
+	}
 
 	/* Make zero page faulting to catch NULL pointer derefs */
 	zero_page_faulting();
-
-	mmu_enable();
+	create_guard_page();
 }
 
 void mmu_disable(void)
@@ -228,7 +282,7 @@ void mmu_disable(void)
 void dma_inv_range(void *ptr, size_t size)
 {
 	unsigned long start = (unsigned long)ptr;
-	unsigned long end = start + size - 1;
+	unsigned long end = start + size;
 
 	v8_inv_dcache_range(start, end);
 }
@@ -236,20 +290,71 @@ void dma_inv_range(void *ptr, size_t size)
 void dma_flush_range(void *ptr, size_t size)
 {
 	unsigned long start = (unsigned long)ptr;
-	unsigned long end = start + size - 1;
+	unsigned long end = start + size;
 
 	v8_flush_dcache_range(start, end);
 }
 
-void dma_sync_single_for_device(dma_addr_t address, size_t size,
-                                enum dma_data_direction dir)
+static void init_range(size_t total_level0_tables)
 {
+	uint64_t *ttb = get_ttb();
+	uint64_t addr = 0;
+
+	while (total_level0_tables--) {
+		early_remap_range(addr, L0_XLAT_SIZE, MAP_UNCACHED);
+		split_block(ttb, 0);
+		addr += L0_XLAT_SIZE;
+		ttb++;
+	}
+}
+
+void mmu_early_enable(unsigned long membase, unsigned long memsize)
+{
+	int el;
+	u64 optee_membase;
+	unsigned long ttb = arm_mem_ttb(membase + memsize);
+
+	if (get_cr() & CR_M)
+		return;
+
+	pr_debug("enabling MMU, ttb @ 0x%08lx\n", ttb);
+
+	el = current_el();
+	set_ttbr_tcr_mair(el, ttb, calc_tcr(el, BITS_PER_VA), MEMORY_ATTRIBUTES);
+	if (el == 3)
+		set_ttbr_tcr_mair(2, ttb, calc_tcr(2, BITS_PER_VA), MEMORY_ATTRIBUTES);
+
+	memset((void *)ttb, 0, GRANULE_SIZE);
+
 	/*
-	 * FIXME: This function needs a device argument to support non 1:1 mappings
+	 * Assume maximum BITS_PER_PA set to 40 bits.
+	 * Set 1:1 mapping of VA->PA. So to cover the full 1TB range we need 2 tables.
 	 */
+	init_range(2);
+
+	early_remap_range(membase, memsize, MAP_CACHED);
+
+	if (optee_get_membase(&optee_membase))
+                optee_membase = membase + memsize - OPTEE_SIZE;
 
-	if (dir == DMA_FROM_DEVICE)
-		v8_inv_dcache_range(address, address + size - 1);
-	else
-		v8_flush_dcache_range(address, address + size - 1);
+	early_remap_range(optee_membase, OPTEE_SIZE, MAP_FAULT);
+
+	early_remap_range(PAGE_ALIGN_DOWN((uintptr_t)_stext), PAGE_ALIGN(_etext - _stext), MAP_CACHED);
+
+	mmu_enable();
+}
+
+void mmu_early_disable(void)
+{
+	unsigned int cr;
+
+	cr = get_cr();
+	cr &= ~(CR_M | CR_C);
+
+	set_cr(cr);
+	v8_flush_dcache_all();
+	tlb_invalidate();
+
+	dsb();
+	isb();
 }
diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
index 9bbb62fc6b..e3959e4407 100644
--- a/arch/arm/cpu/mmu_64.h
+++ b/arch/arm/cpu/mmu_64.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 #include "mmu-common.h"
 
@@ -104,12 +105,27 @@ static inline uint64_t level2mask(int level)
 	return mask;
 }
 
+/**
+ * @brief Returns the TCR (Translation Control Register) value
+ * 
+ * @param el - Exception Level
+ * @param va_bits - Virtual Address bits
+ * @return uint64_t TCR
+ */
 static inline uint64_t calc_tcr(int el, int va_bits)
 {
-	u64 ips;
-	u64 tcr;
+	u64 ips; // Intermediate Physical Address Size
+	u64 tcr; // Translation Control Register
 
+#if (BITS_PER_PA == 40)
 	ips = 2;
+#elif (BITS_PER_PA == 36)
+	ips = 1;
+#elif (BITS_PER_PA == 32)
+	ips = 0;
+#else
+#error "Unsupported"
+#endif
 
 	if (el == 1)
 		tcr = (ips << 32) | TCR_EPD1_DISABLE;
diff --git a/arch/arm/cpu/mmuinfo.c b/arch/arm/cpu/mmuinfo.c
index 1147c0a305..44d6980a75 100644
--- a/arch/arm/cpu/mmuinfo.c
+++ b/arch/arm/cpu/mmuinfo.c
@@ -1,91 +1,85 @@
 // SPDX-License-Identifier: GPL-2.0-only
 // SPDX-FileCopyrightText: 2012 Jan Luebbe <j.luebbe@pengutronix.de>, Pengutronix
 /*
- * mmuinfo.c - Show MMU/cache information from cp15 registers
+ * mmuinfo.c - Show MMU/cache information
  */
 
 #include <common.h>
 #include <command.h>
+#include <getopt.h>
+#include <asm/mmuinfo.h>
+#include <asm/system_info.h>
+#include <zero_page.h>
+#include <mmu.h>
 
-static char *inner_attr[] = {
-	"0b000 Non-cacheable",
-	"0b001 Strongly-ordered",
-	"0b010 (reserved)",
-	"0b011 Device",
-	"0b100 (reserved)",
-	"0b101 Write-Back, Write-Allocate",
-	"0b110 Write-Through",
-	"0b111 Write-Back, no Write-Allocate",
-};
-
-static char *outer_attr[] = {
-	"0b00 Non-cacheable",
-	"0b01 Write-Back, Write-Allocate",
-	"0b10 Write-Through, no Write-Allocate",
-	"0b11 Write-Back, no Write-Allocate",
-};
-
-static void decode_par(unsigned long par)
+int mmuinfo(void *addr)
 {
-	printf("  Physical Address [31:12]: 0x%08lx\n", par & 0xFFFFF000);
-	printf("  Reserved [11]:            0x%lx\n", (par >> 11) & 0x1);
-	printf("  Not Outer Shareable [10]: 0x%lx\n", (par >> 10) & 0x1);
-	printf("  Non-Secure [9]:           0x%lx\n", (par >> 9) & 0x1);
-	printf("  Impl. def. [8]:           0x%lx\n", (par >> 8) & 0x1);
-	printf("  Shareable [7]:            0x%lx\n", (par >> 7) & 0x1);
-	printf("  Inner mem. attr. [6:4]:   0x%lx (%s)\n", (par >> 4) & 0x7,
-		inner_attr[(par >> 4) & 0x7]);
-	printf("  Outer mem. attr. [3:2]:   0x%lx (%s)\n", (par >> 2) & 0x3,
-		outer_attr[(par >> 2) & 0x3]);
-	printf("  SuperSection [1]:         0x%lx\n", (par >> 1) & 0x1);
-	printf("  Failure [0]:              0x%lx\n", (par >> 0) & 0x1);
+	if (IS_ENABLED(CONFIG_CPU_V8))
+		return mmuinfo_v8(addr);
+	if (IS_ENABLED(CONFIG_CPU_V7) && cpu_architecture() == CPU_ARCH_ARMv7)
+		return mmuinfo_v7(addr);
+
+	return -ENOSYS;
 }
 
-static int do_mmuinfo(int argc, char *argv[])
+static __maybe_unused int do_mmuinfo(int argc, char *argv[])
 {
-	unsigned long addr = 0, priv_read, priv_write;
+	unsigned long addr;
+	int access_zero_page = -1;
+	int opt;
 
-	if (argc < 2)
-		return COMMAND_ERROR_USAGE;
+	while ((opt = getopt(argc, argv, "zZ")) > 0) {
+		switch (opt) {
+		case 'z':
+			access_zero_page = true;
+			break;
+		case 'Z':
+			access_zero_page = false;
+			break;
+		default:
+			return COMMAND_ERROR_USAGE;
+		}
+	}
 
-	addr = strtoul_suffix(argv[1], NULL, 0);
+	if (access_zero_page >= 0) {
+		if (argc - optind != 0)
+			return COMMAND_ERROR_USAGE;
 
-	__asm__ __volatile__(
-		"mcr    p15, 0, %0, c7, c8, 0   @ write VA to PA translation (priv read)\n"
-		:
-		: "r" (addr)
-		: "memory");
+		if (!zero_page_remappable()) {
+			pr_warn("No architecture support for zero page remap\n");
+			return -ENOSYS;
+		}
 
-	__asm__ __volatile__(
-		"mrc    p15, 0, %0, c7, c4, 0   @ read PAR\n"
-		: "=r" (priv_read)
-		:
-		: "memory");
+		if (access_zero_page)
+			zero_page_access();
+		else
+			zero_page_faulting();
 
-	__asm__ __volatile__(
-		"mcr    p15, 0, %0, c7, c8, 1   @ write VA to PA translation (priv write)\n"
-		:
-		: "r" (addr)
-		: "memory");
+		return 0;
+	}
 
-	__asm__ __volatile__(
-		"mrc    p15, 0, %0, c7, c4, 0   @ read PAR\n"
-		: "=r" (priv_write)
-		:
-		: "memory");
+	if (argc - optind != 1)
+		return COMMAND_ERROR_USAGE;
 
-	printf("PAR result for 0x%08lx: \n", addr);
-	printf(" privileged read: 0x%08lx\n", priv_read);
-	decode_par(priv_read);
-	printf(" privileged write: 0x%08lx\n", priv_write);
-	decode_par(priv_write);
+	addr = strtoul_suffix(argv[1], NULL, 0);
 
-	return 0;
+	return mmuinfo((void *)addr);
 }
 
+BAREBOX_CMD_HELP_START(mmuinfo)
+BAREBOX_CMD_HELP_TEXT("Show MMU/cache information using the cp15/model-specific registers.")
+BAREBOX_CMD_HELP_TEXT("")
+BAREBOX_CMD_HELP_TEXT("Options:")
+BAREBOX_CMD_HELP_OPT ("-z",  "enable access to zero page")
+BAREBOX_CMD_HELP_OPT ("-Z",  "disable access to zero page")
+BAREBOX_CMD_HELP_END
+
+#ifdef CONFIG_COMMAND_SUPPORT
 BAREBOX_CMD_START(mmuinfo)
 	.cmd            = do_mmuinfo,
 	BAREBOX_CMD_DESC("show MMU/cache information of an address")
-	BAREBOX_CMD_OPTS("ADDRESS")
+	BAREBOX_CMD_OPTS("[-zZ | ADDRESS]")
 	BAREBOX_CMD_GROUP(CMD_GRP_INFO)
+	BAREBOX_CMD_HELP(cmd_mmuinfo_help)
 BAREBOX_CMD_END
+#endif
diff --git a/arch/arm/cpu/mmuinfo_32.c b/arch/arm/cpu/mmuinfo_32.c
new file mode 100644
index 0000000000..e26dabc9b3
--- /dev/null
+++ b/arch/arm/cpu/mmuinfo_32.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2012 Jan Luebbe <j.luebbe@pengutronix.de>, Pengutronix
+/*
+ * mmuinfo_32.c - Show MMU/cache information from cp15 registers
+ */
+
+#include <common.h>
+#include <asm/mmuinfo.h>
+
+static char *inner_attr[] = {
+	"0b000 Non-cacheable",
+	"0b001 Strongly-ordered",
+	"0b010 (reserved)",
+	"0b011 Device",
+	"0b100 (reserved)",
+	"0b101 Write-Back, Write-Allocate",
+	"0b110 Write-Through",
+	"0b111 Write-Back, no Write-Allocate",
+};
+
+static char *outer_attr[] = {
+	"0b00 Non-cacheable",
+	"0b01 Write-Back, Write-Allocate",
+	"0b10 Write-Through, no Write-Allocate",
+	"0b11 Write-Back, no Write-Allocate",
+};
+
+static void decode_par(unsigned long par)
+{
+	printf("  Physical Address [31:12]: 0x%08lx\n", par & 0xFFFFF000);
+	printf("  Reserved [11]:            0x%lx\n", (par >> 11) & 0x1);
+	printf("  Not Outer Shareable [10]: 0x%lx\n", (par >> 10) & 0x1);
+	printf("  Non-Secure [9]:           0x%lx\n", (par >> 9) & 0x1);
+	printf("  Impl. def. [8]:           0x%lx\n", (par >> 8) & 0x1);
+	printf("  Shareable [7]:            0x%lx\n", (par >> 7) & 0x1);
+	printf("  Inner mem. attr. [6:4]:   0x%lx (%s)\n", (par >> 4) & 0x7,
+		inner_attr[(par >> 4) & 0x7]);
+	printf("  Outer mem. attr. [3:2]:   0x%lx (%s)\n", (par >> 2) & 0x3,
+		outer_attr[(par >> 2) & 0x3]);
+	printf("  SuperSection [1]:         0x%lx\n", (par >> 1) & 0x1);
+	printf("  Failure [0]:              0x%lx\n", (par >> 0) & 0x1);
+}
+
+int mmuinfo_v7(void *_addr)
+{
+	unsigned long addr = (unsigned long)_addr;
+	unsigned long priv_read, priv_write;
+
+	__asm__ __volatile__(
+		"mcr    p15, 0, %0, c7, c8, 0   @ write VA to PA translation (priv read)\n"
+		:
+		: "r" (addr)
+		: "memory");
+
+	__asm__ __volatile__(
+		"mrc    p15, 0, %0, c7, c4, 0   @ read PAR\n"
+		: "=r" (priv_read)
+		:
+		: "memory");
+
+	__asm__ __volatile__(
+		"mcr    p15, 0, %0, c7, c8, 1   @ write VA to PA translation (priv write)\n"
+		:
+		: "r" (addr)
+		: "memory");
+
+	__asm__ __volatile__(
+		"mrc    p15, 0, %0, c7, c4, 0   @ read PAR\n"
+		: "=r" (priv_write)
+		:
+		: "memory");
+
+	printf("PAR result for 0x%08lx: \n", addr);
+	printf(" privileged read: 0x%08lx\n", priv_read);
+	decode_par(priv_read);
+	printf(" privileged write: 0x%08lx\n", priv_write);
+	decode_par(priv_write);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/mmuinfo_64.c b/arch/arm/cpu/mmuinfo_64.c
new file mode 100644
index 0000000000..de4945f43e
--- /dev/null
+++ b/arch/arm/cpu/mmuinfo_64.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2023 Ahmad Fatoum <a.fatoum@pengutronix.de>, Pengutronix
+/*
+ * mmuinfo_64.c - Show MMU/cache information via AT instruction
+ */
+
+#include <common.h>
+#include <asm/mmuinfo.h>
+#include <asm/system.h>
+#include <asm/sysreg.h>
+#include <linux/bitfield.h>
+
+#define at_par(reg, addr) ({ \
+		asm volatile("at " reg ", %0\n" :: "r" (addr)); \
+		isb(); \
+		read_sysreg_par(); \
+})
+
+#define BITS(from, to, val) FIELD_GET(GENMASK(from, to), val)
+
+static const char *decode_devmem_attr(u8 attr)
+{
+	switch (attr & ~0x1) {
+	case 0b00000000:
+		return "0b0000 Device-nGnRnE memory";
+	case 0b00000100:
+		return "0b0100 Device-nGnRE memory";
+	case 0b00001000:
+		return "0b1000 Device-nGRE memory";
+	case 0b00001100:
+		return "0b1100 Device-GRE memory";
+	default:
+		return "unknown";
+	};
+}
+
+static char *cache_attr[] = {
+	"0b0000 Wrongly decoded",
+	"0b0001 Write-Through Transient, Write-Allocate, no Read-Allocate",
+	"0b0010 Write-Through Transient, no Write-Allocate",
+	"0b0011 Write-Through Transient, Write-Allocate",
+	"0b0100 Non-Cacheable",
+	"0b0101 Write-Back Transient, Write-Allocate, no Read-Allocate",
+	"0b0110 Write-Back Transient, no Write-Allocate",
+	"0b0111 Write-Back Transient, Write-Allocate",
+	"0b1000 Write-Through Non-transient, no Write-Allocate no Read-Allocate",
+	"0b1001 Write-Through Non-transient, Write-Allocate no Read-Allocate",
+	"0b1010 Write-Through Non-transient, no Write-Allocate",
+	"0b1011 Write-Through Non-transient, Write-Allocate",
+	"0b1100 Write-Back Non-transient, no Write-Allocate no Read-Allocate",
+	"0b1101 Write-Back Non-transient, Write-Allocate no Read-Allocate",
+	"0b1110 Write-Back Non-transient, no Write-Allocate",
+	"0b1111 Write-Back Non-transient, Write-Allocate",
+};
+
+static char *share_attr[] = {
+	"0b00 Non-Shareable",
+	"0b01 Reserved",
+	"0b10 Outer Shareable",
+	"0b11 Inner Shareable",
+};
+
+static char *stage_fault[] = {
+	"stage 1 translation",
+	"stage 2 translation",
+};
+
+static char *fault_status_leveled[] = {
+	"Address size fault",  /* of translation or translation table base register */
+	"Translation fault",
+	"Access flag fault",
+	"Permission fault",
+	"Synchronous External abort", /* level -1 */
+	"Synchronous External abort", /* on translation table walk or hardware update of translation table */
+	"Synchronous parity or ECC error", /* level -1 */
+	"Synchronous parity or ECC error", /* on memory access on translation table walk or hardware update of translation table */
+};
+
+static const char *decode_fault_status_level(u8 fst)
+{
+	if (!(fst & BIT(5)))
+		return "";
+
+	switch (BITS(5, 0, fst)) {
+	case 0b010011:
+	case 0b011011:
+		return ", level -1";
+	}
+
+	switch (BITS(1, 0, fst)) {
+	case 0b00:
+		return ", level 0";
+	case 0b01:
+		return ", level 1";
+	case 0b10:
+		return ", level 2";
+	case 0b11:
+		return ", level 3";
+	}
+
+	BUG();
+}
+
+static const char *decode_fault_status(u8 fst)
+{
+
+	switch (BITS(5, 0, fst)) {
+	case 0b101001: /* When FEAT_LPA2 is implemented */
+		return "Address size fault, level -1";
+	case 0b101011: /* When FEAT_LPA2 is implemented */
+		return "Translation fault, level -1";
+	case 0b110000:
+		return "TLB conflict abort";
+	case 0b110001: /* When FEAT_HAFDBS is implemented */
+		return "Unsupported atomic hardware update fault";
+	case 0b111101: /* When EL1 is capable of using AArch32 */
+		return "Section Domain fault, from an AArch32 stage 1 EL1&0 "
+			"translation regime using Short-descriptor translation "
+			"table format";
+	case 0b111110: /* When EL1 is capable of using AArch32 */
+		return "Page Domain fault, from an AArch32 stage 1 EL1&0 "
+			"translation regime using Short-descriptor translation "
+			"table format";
+	default:
+		if (fst & BIT(5))
+			return fault_status_leveled[BITS(4, 2, fst)];
+
+		return "Reserved";
+	}
+};
+
+static void decode_par(unsigned long par)
+{
+	u8 devmem_attr = BITS(63, 56, par);
+
+	if (par & 1) {
+		printf("  Translation aborted [9:8]: because of a fault in the %s%s\n",
+		       stage_fault[BITS(9, 9, par)],
+		       BITS(8, 8, par) ? " during a stage 1 translation table walk" : "");
+		printf("  Fault Status Code [6:1]:   0x%02lx (%s%s)\n", BITS(6, 1, par),
+		       decode_fault_status(BITS(6, 1, par)),
+		       decode_fault_status_level(BITS(6, 1, par)));
+		printf("  Failure [0]:                0x1\n");
+	} else {
+		if ((devmem_attr & 0xf0) && (devmem_attr & 0x0f)) {
+			printf("  Outer mem. attr. [63:60]:   0x%02lx (%s)\n", BITS(63, 60, par),
+			       cache_attr[BITS(63, 60, par)]);
+			printf("  Inner mem. attr. [59:56]:   0x%02lx (%s)\n", BITS(59, 56, par),
+			       cache_attr[BITS(59, 56, par)]);
+		} else if ((devmem_attr & 0b11110010) == 0) {
+			printf("  Memory attr. [63:56]:     0x%02x (%s)\n",
+			       devmem_attr, decode_devmem_attr(devmem_attr));
+			if (devmem_attr & 1)
+				printf("  (XS == 0 if FEAT_XS implemented)\n");
+		} else if (devmem_attr == 0b01000000) {
+			printf("  Outer mem. attr. [63:56]:   0x%02lx (%s)\n", BITS(63, 56, par),
+			       "Non-Cacheable");
+			printf("  Inner mem. attr. [63:56]:   0x%02lx (%s)\n", BITS(63, 56, par),
+			       "Non-Cacheable");
+			printf("  (XS == 0 if FEAT_XS implemented)\n");
+		} else if (devmem_attr == 0b10100000) {
+			printf("  Outer mem. attr. [63:56]:   0x%02lx (%s)\n", BITS(63, 56, par),
+			       "Write-Through, No Write-Allocate");
+			printf("  Inner mem. attr. [63:56]:   0x%02lx (%s)\n", BITS(63, 56, par),
+			       "Write-Through");
+			printf("  (XS == 0 if FEAT_XS implemented)\n");
+		} else if (devmem_attr == 0b11110000) {
+			printf("  Outer mem. attr. [63:56]:   0x%02lx (%s)\n", BITS(63, 56, par),
+			       "Write-Back");
+			printf("  Inner mem. attr. [63:56]:   0x%02lx (%s)\n", BITS(63, 56, par),
+			       "Write-Back, Write-Allocate, Non-transient");
+			printf("  (if FEAT_MTE2 implemented)\n");
+		}
+		printf("  Physical Address [51:12]: 0x%08lx\n", par & GENMASK(51, 12));
+		printf("  Non-Secure [9]:           0x%lx\n", BITS(9, 9, par));
+		printf("  Shareability attr. [8:7]: 0x%02lx (%s)\n", BITS(8, 7, par),
+			share_attr[BITS(8, 7, par)]);
+		printf("  Failure [0]:              0x0\n");
+	}
+}
+
+int mmuinfo_v8(void *_addr)
+{
+	unsigned long addr = (unsigned long)_addr;
+	unsigned long priv_read, priv_write;
+
+	switch (current_el()) {
+	case 3:
+		priv_read  = at_par("s1e3r", addr);
+		priv_write = at_par("s1e3w", addr);
+		break;
+	case 2:
+		priv_read  = at_par("s1e2r", addr);
+		priv_write = at_par("s1e2w", addr);
+		break;
+	case 1:
+		priv_read  = at_par("s1e1r", addr);
+		priv_write = at_par("s1e1w", addr);
+		break;
+	case 0:
+		priv_read  = at_par("s1e0r", addr);
+		priv_write = at_par("s1e0w", addr);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	printf("PAR result for 0x%08lx: \n", addr);
+	printf(" privileged read: 0x%08lx\n", priv_read);
+	decode_par(priv_read);
+	printf(" privileged write: 0x%08lx\n", priv_write);
+	decode_par(priv_write);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/psci-client.c b/arch/arm/cpu/psci-client.c
index b5d0d37497..c865e754fd 100644
--- a/arch/arm/cpu/psci-client.c
+++ b/arch/arm/cpu/psci-client.c
@@ -15,7 +15,7 @@
 
 static struct restart_handler restart;
 
-static void __noreturn psci_invoke_noreturn(int function)
+static void __noreturn psci_invoke_noreturn(ulong function)
 {
 	int ret;
 
@@ -108,12 +108,12 @@ static u32 invoke_psci_fn_smc(ulong function, ulong arg0, ulong arg1, ulong arg2
 	return res.a0;
 }
 
-static int of_psci_do_fixup(struct device_node *root, void *context)
+static int of_psci_do_fixup(struct device_node *root, void *method)
 {
-	return of_psci_fixup(root, *(u32 *)context);
+	return of_psci_fixup(root, version, (const void *)method);
 }
 
-static int __init psci_probe(struct device_d *dev)
+static int __init psci_probe(struct device *dev)
 {
 	const char *method;
 	ulong of_version, actual_version;
@@ -123,7 +123,7 @@ static int __init psci_probe(struct device_d *dev)
 	if (ret)
 		return -ENODEV;
 
-	ret = of_property_read_string(dev->device_node, "method", &method);
+	ret = of_property_read_string(dev->of_node, "method", &method);
 	if (ret) {
 		dev_warn(dev, "missing \"method\" property\n");
 		return -ENXIO;
@@ -156,7 +156,7 @@ static int __init psci_probe(struct device_d *dev)
 		 version >> 16, version & 0xffff);
 
 	if (actual_version != of_version)
-		of_register_fixup(of_psci_do_fixup, &version);
+		of_register_fixup(of_psci_do_fixup, (void *)method);
 
 	ret = poweroff_handler_register_fn(psci_poweroff);
 	if (ret)
@@ -181,8 +181,9 @@ static __maybe_unused struct of_device_id psci_dt_ids[] = {
 	{ .compatible = "arm,psci-1.0",	.data = (void*)ARM_PSCI_VER(1,0) },
 	{ /* sentinel */ },
 };
+MODULE_DEVICE_TABLE(of, psci_dt_ids);
 
-static struct driver_d psci_driver = {
+static struct driver psci_driver = {
 	.name = "psci",
 	.probe = psci_probe,
 	.of_compatible = DRV_OF_COMPAT(psci_dt_ids),
diff --git a/arch/arm/cpu/psci-of.c b/arch/arm/cpu/psci-of.c
index ef83b0edee..1b6371ddd6 100644
--- a/arch/arm/cpu/psci-of.c
+++ b/arch/arm/cpu/psci-of.c
@@ -7,7 +7,8 @@
 #include <asm/psci.h>
 #include <linux/arm-smccc.h>
 
-int of_psci_fixup(struct device_node *root, unsigned long psci_version)
+int of_psci_fixup(struct device_node *root, unsigned long psci_version,
+		  const char *method)
 {
 	struct device_node *psci;
 	int ret;
@@ -39,14 +40,14 @@ int of_psci_fixup(struct device_node *root, unsigned long psci_version)
 		if (!cpu)
 			break;
 		of_property_write_string(cpu, "enable-method", "psci");
-		pr_debug("Fixed %s\n", cpu->full_name);
+		pr_debug("Fixed %pOF\n", cpu);
 	}
 
 	ret = of_property_write_string(psci, "compatible", compat);
 	if (ret)
 		return ret;
 
-	ret = of_property_write_string(psci, "method", "smc");
+	ret = of_property_write_string(psci, "method", method);
 	if (ret)
 		return ret;
 
diff --git a/arch/arm/cpu/psci.c b/arch/arm/cpu/psci.c
index d1056e0659..70c97e03a5 100644
--- a/arch/arm/cpu/psci.c
+++ b/arch/arm/cpu/psci.c
@@ -189,7 +189,7 @@ static int of_psci_do_fixup(struct device_node *root, void *unused)
 	if (bootm_arm_security_state() < ARM_STATE_NONSECURE)
 		return 0;
 
-	return of_psci_fixup(root, ARM_PSCI_VER_1_0);
+	return of_psci_fixup(root, ARM_PSCI_VER_1_0, "smc");
 }
 
 int psci_cpu_entry_c(void)
diff --git a/arch/arm/cpu/sections.c b/arch/arm/cpu/sections.c
index a53236d900..f310578ba2 100644
--- a/arch/arm/cpu/sections.c
+++ b/arch/arm/cpu/sections.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <asm/sections.h>
 #include <linux/types.h>
 
diff --git a/arch/arm/cpu/setupc.S b/arch/arm/cpu/setupc_32.S
index 55aa105b21..eafc9b52c6 100644
--- a/arch/arm/cpu/setupc.S
+++ b/arch/arm/cpu/setupc_32.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <asm/sections.h>
 
diff --git a/arch/arm/cpu/setupc_64.S b/arch/arm/cpu/setupc_64.S
index ee9ea6cfc0..2138c2a600 100644
--- a/arch/arm/cpu/setupc_64.S
+++ b/arch/arm/cpu/setupc_64.S
@@ -1,4 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/sections.h>
 
 .section .text.setupc
@@ -8,11 +11,11 @@
  */
 ENTRY(setup_c)
 	mov	x15, x30
-	ldr	x0, =__bss_start
+	adr_l	x0, __bss_start
 	mov	x1, #0
-	ldr	x2, =__bss_stop
+	adr_l	x2, __bss_stop
 	sub	x2, x2, x0
-	bl	memset			/* clear bss */
+	bl	__memset		/* clear bss */
 	mov	x30, x15
 	ret
 ENDPROC(setup_c)
@@ -24,9 +27,18 @@ ENDPROC(setup_c)
  * executing at new address.
  */
 .section .text.relocate_to_adr
-ENTRY(relocate_to_adr)
 					/* x0: target address */
+#ifdef __PBL__
+ENTRY(relocate_to_adr_full)
+	adr_l	x2, __image_end
+	b	1f
+#endif
+
+ENTRY(relocate_to_adr)
+	adr_l	x2, __bss_start
+	b	1f
 
+1:
 	stp	x19, x20, [sp, #-16]!
 	stp	x21, x22, [sp, #-16]!
 
@@ -34,34 +46,27 @@ ENTRY(relocate_to_adr)
 
 	mov	x21, x0
 
-	bl	get_runtime_offset
-	mov	x5, x0
-
-	ldr	x0, =_text
-	mov	x20, x0
-
-	add	x1, x0, x5		/* x1: from address */
+	adr_l	x1, _text
+	mov	x20, x1
 
 	cmp	x1, x21			/* already at correct address? */
 	beq	1f			/* yes, skip copy to new address */
 
-	ldr	x2, =__bss_start
-
-	sub	x2, x2, x0		/* x2: size */
+	sub	x2, x2, x1		/* x2: size */
 	mov	x0, x21			/* x0: target */
 
 	/* adjust return address */
 	sub	x19, x19, x1		/* sub address where we are actually running */
 	add	x19, x19, x0		/* add address where we are going to run */
 
-	bl	memcpy			/* copy binary */
+	bl	__memcpy		/* copy binary */
 
 	bl	sync_caches_for_execution
 
 	mov	x0,#0
 	ic	ivau, x0	/* flush icache */
 
-	ldr	x0,=1f
+	adr_l	x0, 1f
 	sub	x0, x0, x20
 	add	x0, x0, x21
 	br	x0			/* jump to relocated address */
diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c
index f5a1edbd4f..53f5142b63 100644
--- a/arch/arm/cpu/sm.c
+++ b/arch/arm/cpu/sm.c
@@ -19,8 +19,7 @@
 #include <linux/arm-smccc.h>
 #include <asm-generic/sections.h>
 #include <asm/secure.h>
-
-#include "mmu.h"
+#include "mmu_32.h"
 
 static unsigned int read_id_pfr1(void)
 {
diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S
index de6cd0406f..f55ac8661c 100644
--- a/arch/arm/cpu/sm_as.S
+++ b/arch/arm/cpu/sm_as.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <asm/ptrace.h>
 #include <asm-generic/memory_layout.h>
diff --git a/arch/arm/cpu/smccc-call.S b/arch/arm/cpu/smccc-call_32.S
index 9875e1f947..9875e1f947 100644
--- a/arch/arm/cpu/smccc-call.S
+++ b/arch/arm/cpu/smccc-call_32.S
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index c61db66865..0351dcb927 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -3,6 +3,10 @@
 
 #define pr_fmt(fmt) "start.c: " fmt
 
+#ifdef CONFIG_DEBUG_INITCALLS
+#define DEBUG
+#endif
+
 #include <common.h>
 #include <init.h>
 #include <linux/sizes.h>
@@ -28,6 +32,7 @@
 unsigned long arm_stack_top;
 static unsigned long arm_barebox_size;
 static unsigned long arm_endmem;
+static unsigned long arm_membase;
 static void *barebox_boarddata;
 static unsigned long barebox_boarddata_size;
 
@@ -38,21 +43,24 @@ static bool blob_is_arm_boarddata(const void *blob)
 	return bd->magic == BAREBOX_ARM_BOARDDATA_MAGIC;
 }
 
+const struct barebox_boarddata *barebox_get_boarddata(void)
+{
+	if (!barebox_boarddata || !blob_is_arm_boarddata(barebox_boarddata))
+		return NULL;
+
+	return barebox_boarddata;
+}
+
 u32 barebox_arm_machine(void)
 {
-	if (barebox_boarddata && blob_is_arm_boarddata(barebox_boarddata)) {
-		const struct barebox_arm_boarddata *bd = barebox_boarddata;
-		return bd->machine;
-	} else {
-		return 0;
-	}
+	const struct barebox_boarddata *bd = barebox_get_boarddata();
+	return bd ? bd->machine : 0;
 }
 
 void *barebox_arm_boot_dtb(void)
 {
 	void *dtb;
-	void *data;
-	int ret;
+	int ret = 0;
 	struct barebox_boarddata_compressed_dtb *compressed_dtb;
 	static void *boot_dtb;
 
@@ -75,10 +83,13 @@ void *barebox_arm_boot_dtb(void)
 	if (!dtb)
 		return NULL;
 
-	data = compressed_dtb + 1;
+	if (IS_ENABLED(CONFIG_IMAGE_COMPRESSION_NONE))
+		memcpy(dtb, compressed_dtb->data,
+		       compressed_dtb->datalen_uncompressed);
+	else
+		ret = uncompress(compressed_dtb->data, compressed_dtb->datalen,
+				 NULL, NULL, dtb, NULL, NULL);
 
-	ret = uncompress(data, compressed_dtb->datalen, NULL, NULL,
-			dtb, NULL, NULL);
 	if (ret) {
 		pr_err("uncompressing dtb failed\n");
 		free(dtb);
@@ -104,7 +115,7 @@ static inline unsigned long arm_mem_boarddata(unsigned long membase,
 
 unsigned long arm_mem_ramoops_get(void)
 {
-	return arm_mem_ramoops(0, arm_stack_top);
+	return arm_mem_ramoops(arm_stack_top);
 }
 EXPORT_SYMBOL_GPL(arm_mem_ramoops_get);
 
@@ -114,17 +125,27 @@ unsigned long arm_mem_endmem_get(void)
 }
 EXPORT_SYMBOL_GPL(arm_mem_endmem_get);
 
+unsigned long arm_mem_membase_get(void)
+{
+	return arm_membase;
+}
+EXPORT_SYMBOL_GPL(arm_mem_membase_get);
+
 static int barebox_memory_areas_init(void)
 {
 	if(barebox_boarddata)
 		request_sdram_region("board data", (unsigned long)barebox_boarddata,
 				     barebox_boarddata_size);
 
+	if (IS_ENABLED(CONFIG_KASAN))
+		request_sdram_region("kasan shadow", kasan_shadow_base,
+				     mem_malloc_start() - kasan_shadow_base);
+
 	return 0;
 }
 device_initcall(barebox_memory_areas_init);
 
-__noreturn __no_sanitize_address void barebox_non_pbl_start(unsigned long membase,
+__noreturn __prereloc void barebox_non_pbl_start(unsigned long membase,
 		unsigned long memsize, void *boarddata)
 {
 	unsigned long endmem = membase + memsize;
@@ -148,23 +169,12 @@ __noreturn __no_sanitize_address void barebox_non_pbl_start(unsigned long membas
 
 	pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize);
 
+	arm_membase = membase;
 	arm_endmem = endmem;
-	arm_stack_top = arm_mem_stack_top(membase, endmem);
+	arm_stack_top = arm_mem_stack_top(endmem);
 	arm_barebox_size = barebox_size;
 	malloc_end = barebox_base;
 
-	if (IS_ENABLED(CONFIG_MMU_EARLY)) {
-		unsigned long ttb = arm_mem_ttb(membase, endmem);
-
-		if (IS_ENABLED(CONFIG_PBL_IMAGE)) {
-			arm_set_cache_functions();
-		} else {
-			pr_debug("enabling MMU, ttb @ 0x%08lx\n", ttb);
-			arm_early_mmu_cache_invalidate();
-			mmu_early_enable(membase, memsize, ttb);
-		}
-	}
-
 	if (boarddata) {
 		uint32_t totalsize = 0;
 		const char *name;
@@ -179,18 +189,6 @@ __noreturn __no_sanitize_address void barebox_non_pbl_start(unsigned long membas
 		} else if (blob_is_arm_boarddata(boarddata)) {
 			totalsize = sizeof(struct barebox_arm_boarddata);
 			name = "machine type";
-		} else if ((unsigned long)boarddata < 8192) {
-			struct barebox_arm_boarddata *bd;
-			uint32_t machine_type = (unsigned long)boarddata;
-			unsigned long mem = arm_mem_boarddata(membase, endmem,
-							      sizeof(*bd));
-			pr_debug("found machine type %d in boarddata\n",
-				 machine_type);
-			bd = barebox_boarddata = (void *)mem;
-			barebox_boarddata_size = sizeof(*bd);
-			bd->magic = BAREBOX_ARM_BOARDDATA_MAGIC;
-			bd->machine = machine_type;
-			malloc_end = mem;
 		}
 
 		if (totalsize) {
@@ -226,6 +224,11 @@ __noreturn __no_sanitize_address void barebox_non_pbl_start(unsigned long membas
 
 	mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1);
 
+	if (IS_ENABLED(CONFIG_MMU) && !IS_ENABLED(CONFIG_PBL_IMAGE)) {
+		arm_early_mmu_cache_invalidate();
+		mmu_early_enable(membase, memsize);
+	}
+
 	if (IS_ENABLED(CONFIG_BOOTM_OPTEE))
 		of_add_reserve_entry(endmem - OPTEE_SIZE, endmem - 1);
 
@@ -250,7 +253,7 @@ void start(unsigned long membase, unsigned long memsize, void *boarddata);
  * First function in the uncompressed image. We get here from
  * the pbl. The stack already has been set up by the pbl.
  */
-void NAKED __no_sanitize_address __section(.text_entry) start(unsigned long membase,
+void NAKED __prereloc __section(.text_entry) start(unsigned long membase,
 		unsigned long memsize, void *boarddata)
 {
 	barebox_non_pbl_start(membase, memsize, boarddata);
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 2250b8ccd3..a481c4634d 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -53,8 +53,8 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
 	unsigned long pc = get_pc();
 
 	/* piggy data is not relocated, so determine the bounds now */
-	pg_start = input_data + global_variable_offset();
-	pg_end = input_data_end + global_variable_offset();
+	pg_start = runtime_address(input_data);
+	pg_end = runtime_address(input_data_end);
 
 	if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) {
 		/*
@@ -81,14 +81,11 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
 
 	pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize);
 
-	if (IS_ENABLED(CONFIG_MMU_EARLY)) {
-		unsigned long ttb = arm_mem_ttb(membase, endmem);
-		pr_debug("enabling MMU, ttb @ 0x%08lx\n", ttb);
-		mmu_early_enable(membase, memsize, ttb);
-	}
+	if (IS_ENABLED(CONFIG_MMU))
+		mmu_early_enable(membase, memsize);
 
-	free_mem_ptr = arm_mem_early_malloc(membase, endmem);
-	free_mem_end_ptr = arm_mem_early_malloc_end(membase, endmem);
+	free_mem_ptr = arm_mem_early_malloc(endmem);
+	free_mem_end_ptr = arm_mem_early_malloc_end(endmem);
 
 	pr_debug("uncompressing barebox binary at 0x%p (size 0x%08x) to 0x%08lx (uncompressed size: 0x%08x)\n",
 			pg_start, pg_len, barebox_base, uncompressed_len);
diff --git a/arch/arm/crypto/.gitignore b/arch/arm/crypto/.gitignore
index b22a068f76..545a1b084d 100644
--- a/arch/arm/crypto/.gitignore
+++ b/arch/arm/crypto/.gitignore
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 /sha256-core.S
diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
index fda4eeafec..55b3ac0538 100644
--- a/arch/arm/crypto/Makefile
+++ b/arch/arm/crypto/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 #
 # Arch-specific CryptoAPI modules.
 #
@@ -8,6 +9,12 @@ obj-$(CONFIG_DIGEST_SHA256_ARM) += sha256-arm.o
 sha1-arm-y	:= sha1-armv4-large.o sha1_glue.o
 sha256-arm-y	:= sha256-core.o sha256_glue.o
 
+obj-$(CONFIG_DIGEST_SHA1_ARM64_CE) += sha1-ce.o
+sha1-ce-y := sha1-ce-glue.o sha1-ce-core.o
+
+obj-$(CONFIG_DIGEST_SHA256_ARM64_CE) += sha2-ce.o
+sha2-ce-y := sha2-ce-glue.o sha2-ce-core.o
+
 quiet_cmd_perl = PERL    $@
       cmd_perl = $(PERL) $(<) > $(@)
 
diff --git a/arch/arm/crypto/sha1-ce-core.S b/arch/arm/crypto/sha1-ce-core.S
new file mode 100644
index 0000000000..dec53c68c8
--- /dev/null
+++ b/arch/arm/crypto/sha1-ce-core.S
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
+ *
+ * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+	.text
+	.arch		armv8-a+crypto
+
+	k0		.req	v0
+	k1		.req	v1
+	k2		.req	v2
+	k3		.req	v3
+
+	t0		.req	v4
+	t1		.req	v5
+
+	dga		.req	q6
+	dgav		.req	v6
+	dgb		.req	s7
+	dgbv		.req	v7
+
+	dg0q		.req	q12
+	dg0s		.req	s12
+	dg0v		.req	v12
+	dg1s		.req	s13
+	dg1v		.req	v13
+	dg2s		.req	s14
+
+	.macro		add_only, op, ev, rc, s0, dg1
+	.ifc		\ev, ev
+	add		t1.4s, v\s0\().4s, \rc\().4s
+	sha1h		dg2s, dg0s
+	.ifnb		\dg1
+	sha1\op		dg0q, \dg1, t0.4s
+	.else
+	sha1\op		dg0q, dg1s, t0.4s
+	.endif
+	.else
+	.ifnb		\s0
+	add		t0.4s, v\s0\().4s, \rc\().4s
+	.endif
+	sha1h		dg1s, dg0s
+	sha1\op		dg0q, dg2s, t1.4s
+	.endif
+	.endm
+
+	.macro		add_update, op, ev, rc, s0, s1, s2, s3, dg1
+	sha1su0		v\s0\().4s, v\s1\().4s, v\s2\().4s
+	add_only	\op, \ev, \rc, \s1, \dg1
+	sha1su1		v\s0\().4s, v\s3\().4s
+	.endm
+
+	.macro		loadrc, k, val, tmp
+	movz		\tmp, :abs_g0_nc:\val
+	movk		\tmp, :abs_g1:\val
+	dup		\k, \tmp
+	.endm
+
+	/*
+	 * int sha1_ce_transform(struct sha1_ce_state *sst, u8 const *src,
+	 *			 int blocks)
+	 */
+SYM_FUNC_START(sha1_ce_transform)
+	/* load round constants */
+	loadrc		k0.4s, 0x5a827999, w6
+	loadrc		k1.4s, 0x6ed9eba1, w6
+	loadrc		k2.4s, 0x8f1bbcdc, w6
+	loadrc		k3.4s, 0xca62c1d6, w6
+
+	/* load state */
+	ld1		{dgav.4s}, [x0]
+	ldr		dgb, [x0, #16]
+
+	/* load sha1_ce_state::finalize */
+	ldr_l		w4, sha1_ce_offsetof_finalize, x4
+	ldr		w4, [x0, x4]
+
+	/* load input */
+0:	ld1		{v8.4s-v11.4s}, [x1], #64
+	sub		w2, w2, #1
+
+CPU_LE(	rev32		v8.16b, v8.16b		)
+CPU_LE(	rev32		v9.16b, v9.16b		)
+CPU_LE(	rev32		v10.16b, v10.16b	)
+CPU_LE(	rev32		v11.16b, v11.16b	)
+
+1:	add		t0.4s, v8.4s, k0.4s
+	mov		dg0v.16b, dgav.16b
+
+	add_update	c, ev, k0,  8,  9, 10, 11, dgb
+	add_update	c, od, k0,  9, 10, 11,  8
+	add_update	c, ev, k0, 10, 11,  8,  9
+	add_update	c, od, k0, 11,  8,  9, 10
+	add_update	c, ev, k1,  8,  9, 10, 11
+
+	add_update	p, od, k1,  9, 10, 11,  8
+	add_update	p, ev, k1, 10, 11,  8,  9
+	add_update	p, od, k1, 11,  8,  9, 10
+	add_update	p, ev, k1,  8,  9, 10, 11
+	add_update	p, od, k2,  9, 10, 11,  8
+
+	add_update	m, ev, k2, 10, 11,  8,  9
+	add_update	m, od, k2, 11,  8,  9, 10
+	add_update	m, ev, k2,  8,  9, 10, 11
+	add_update	m, od, k2,  9, 10, 11,  8
+	add_update	m, ev, k3, 10, 11,  8,  9
+
+	add_update	p, od, k3, 11,  8,  9, 10
+	add_only	p, ev, k3,  9
+	add_only	p, od, k3, 10
+	add_only	p, ev, k3, 11
+	add_only	p, od
+
+	/* update state */
+	add		dgbv.2s, dgbv.2s, dg1v.2s
+	add		dgav.4s, dgav.4s, dg0v.4s
+
+	cbz		w2, 2f
+	b		0b
+
+	/*
+	 * Final block: add padding and total bit count.
+	 * Skip if the input size was not a round multiple of the block size,
+	 * the padding is handled by the C code in that case.
+	 */
+2:	cbz		x4, 3f
+	ldr_l		w4, sha1_ce_offsetof_count, x4
+	ldr		x4, [x0, x4]
+	movi		v9.2d, #0
+	mov		x8, #0x80000000
+	movi		v10.2d, #0
+	ror		x7, x4, #29		// ror(lsl(x4, 3), 32)
+	fmov		d8, x8
+	mov		x4, #0
+	mov		v11.d[0], xzr
+	mov		v11.d[1], x7
+	b		1b
+
+	/* store new state */
+3:	st1		{dgav.4s}, [x0]
+	str		dgb, [x0, #16]
+	mov		w0, w2
+	ret
+SYM_FUNC_END(sha1_ce_transform)
diff --git a/arch/arm/crypto/sha1-ce-glue.c b/arch/arm/crypto/sha1-ce-glue.c
new file mode 100644
index 0000000000..5b49237573
--- /dev/null
+++ b/arch/arm/crypto/sha1-ce-glue.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * sha1-ce-glue.c - SHA-1 secure hash using ARMv8 Crypto Extensions
+ *
+ * Copyright (C) 2014 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
+ */
+
+#include <common.h>
+#include <digest.h>
+#include <init.h>
+#include <crypto/sha.h>
+#include <crypto/sha1_base.h>
+#include <crypto/internal.h>
+#include <linux/linkage.h>
+#include <asm/byteorder.h>
+#include <asm/neon.h>
+
+MODULE_DESCRIPTION("SHA1 secure hash using ARMv8 Crypto Extensions");
+MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_CRYPTO("sha1");
+
+struct sha1_ce_state {
+	struct sha1_state	sst;
+	u32			finalize;
+};
+
+extern const u32 sha1_ce_offsetof_count;
+extern const u32 sha1_ce_offsetof_finalize;
+
+asmlinkage int sha1_ce_transform(struct sha1_ce_state *sst, u8 const *src,
+				 int blocks);
+
+static void __sha1_ce_transform(struct sha1_state *sst, u8 const *src,
+				int blocks)
+{
+	while (blocks) {
+		int rem;
+
+		kernel_neon_begin();
+		rem = sha1_ce_transform(container_of(sst, struct sha1_ce_state,
+						     sst), src, blocks);
+		kernel_neon_end();
+		src += (blocks - rem) * SHA1_BLOCK_SIZE;
+		blocks = rem;
+	}
+}
+
+const u32 sha1_ce_offsetof_count = offsetof(struct sha1_ce_state, sst.count);
+const u32 sha1_ce_offsetof_finalize = offsetof(struct sha1_ce_state, finalize);
+
+static int sha1_ce_update(struct digest *desc, const void *data,
+			  unsigned long len)
+{
+	struct sha1_ce_state *sctx = digest_ctx(desc);
+
+	sctx->finalize = 0;
+	sha1_base_do_update(desc, data, len, __sha1_ce_transform);
+
+	return 0;
+}
+
+static int sha1_ce_final(struct digest *desc, u8 *out)
+{
+	struct sha1_ce_state *sctx = digest_ctx(desc);
+
+	sctx->finalize = 0;
+	sha1_base_do_finalize(desc, __sha1_ce_transform);
+	return sha1_base_finish(desc, out);
+}
+
+static struct digest_algo m = {
+	.base = {
+		.name		=	"sha1",
+		.driver_name	=	"sha1-ce",
+		.priority	=	200,
+		.algo		=	HASH_ALGO_SHA1,
+	},
+
+	.init	=	sha1_base_init,
+	.update	=	sha1_ce_update,
+	.final	=	sha1_ce_final,
+	.digest	=	digest_generic_digest,
+	.verify	=	digest_generic_verify,
+	.length	=	SHA1_DIGEST_SIZE,
+	.ctx_length =	sizeof(struct sha1_ce_state),
+};
+
+static int sha1_ce_mod_init(void)
+{
+	return digest_algo_register(&m);
+}
+coredevice_initcall(sha1_ce_mod_init);
diff --git a/arch/arm/crypto/sha2-ce-core.S b/arch/arm/crypto/sha2-ce-core.S
new file mode 100644
index 0000000000..5a60b13b87
--- /dev/null
+++ b/arch/arm/crypto/sha2-ce-core.S
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
+ *
+ * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+	.text
+	.arch		armv8-a+crypto
+
+	dga		.req	q20
+	dgav		.req	v20
+	dgb		.req	q21
+	dgbv		.req	v21
+
+	t0		.req	v22
+	t1		.req	v23
+
+	dg0q		.req	q24
+	dg0v		.req	v24
+	dg1q		.req	q25
+	dg1v		.req	v25
+	dg2q		.req	q26
+	dg2v		.req	v26
+
+	.macro		add_only, ev, rc, s0
+	mov		dg2v.16b, dg0v.16b
+	.ifeq		\ev
+	add		t1.4s, v\s0\().4s, \rc\().4s
+	sha256h		dg0q, dg1q, t0.4s
+	sha256h2	dg1q, dg2q, t0.4s
+	.else
+	.ifnb		\s0
+	add		t0.4s, v\s0\().4s, \rc\().4s
+	.endif
+	sha256h		dg0q, dg1q, t1.4s
+	sha256h2	dg1q, dg2q, t1.4s
+	.endif
+	.endm
+
+	.macro		add_update, ev, rc, s0, s1, s2, s3
+	sha256su0	v\s0\().4s, v\s1\().4s
+	add_only	\ev, \rc, \s1
+	sha256su1	v\s0\().4s, v\s2\().4s, v\s3\().4s
+	.endm
+
+	/*
+	 * The SHA-256 round constants
+	 */
+	.section	".rodata", "a"
+	.align		4
+.Lsha2_rcon:
+	.word		0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
+	.word		0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
+	.word		0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
+	.word		0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
+	.word		0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
+	.word		0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
+	.word		0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
+	.word		0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
+	.word		0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
+	.word		0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
+	.word		0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
+	.word		0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
+	.word		0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
+	.word		0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
+	.word		0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
+	.word		0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
+
+	/*
+	 * void sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src,
+	 *			  int blocks)
+	 */
+	.text
+SYM_FUNC_START(sha2_ce_transform)
+	/* load round constants */
+	adr_l		x8, .Lsha2_rcon
+	ld1		{ v0.4s- v3.4s}, [x8], #64
+	ld1		{ v4.4s- v7.4s}, [x8], #64
+	ld1		{ v8.4s-v11.4s}, [x8], #64
+	ld1		{v12.4s-v15.4s}, [x8]
+
+	/* load state */
+	ld1		{dgav.4s, dgbv.4s}, [x0]
+
+	/* load sha256_ce_state::finalize */
+	ldr_l		w4, sha256_ce_offsetof_finalize, x4
+	ldr		w4, [x0, x4]
+
+	/* load input */
+0:	ld1		{v16.4s-v19.4s}, [x1], #64
+	sub		w2, w2, #1
+
+CPU_LE(	rev32		v16.16b, v16.16b	)
+CPU_LE(	rev32		v17.16b, v17.16b	)
+CPU_LE(	rev32		v18.16b, v18.16b	)
+CPU_LE(	rev32		v19.16b, v19.16b	)
+
+1:	add		t0.4s, v16.4s, v0.4s
+	mov		dg0v.16b, dgav.16b
+	mov		dg1v.16b, dgbv.16b
+
+	add_update	0,  v1, 16, 17, 18, 19
+	add_update	1,  v2, 17, 18, 19, 16
+	add_update	0,  v3, 18, 19, 16, 17
+	add_update	1,  v4, 19, 16, 17, 18
+
+	add_update	0,  v5, 16, 17, 18, 19
+	add_update	1,  v6, 17, 18, 19, 16
+	add_update	0,  v7, 18, 19, 16, 17
+	add_update	1,  v8, 19, 16, 17, 18
+
+	add_update	0,  v9, 16, 17, 18, 19
+	add_update	1, v10, 17, 18, 19, 16
+	add_update	0, v11, 18, 19, 16, 17
+	add_update	1, v12, 19, 16, 17, 18
+
+	add_only	0, v13, 17
+	add_only	1, v14, 18
+	add_only	0, v15, 19
+	add_only	1
+
+	/* update state */
+	add		dgav.4s, dgav.4s, dg0v.4s
+	add		dgbv.4s, dgbv.4s, dg1v.4s
+
+	/* handled all input blocks? */
+	cbz		w2, 2f
+	b		0b
+
+	/*
+	 * Final block: add padding and total bit count.
+	 * Skip if the input size was not a round multiple of the block size,
+	 * the padding is handled by the C code in that case.
+	 */
+2:	cbz		x4, 3f
+	ldr_l		w4, sha256_ce_offsetof_count, x4
+	ldr		x4, [x0, x4]
+	movi		v17.2d, #0
+	mov		x8, #0x80000000
+	movi		v18.2d, #0
+	ror		x7, x4, #29		// ror(lsl(x4, 3), 32)
+	fmov		d16, x8
+	mov		x4, #0
+	mov		v19.d[0], xzr
+	mov		v19.d[1], x7
+	b		1b
+
+	/* store new state */
+3:	st1		{dgav.4s, dgbv.4s}, [x0]
+	mov		w0, w2
+	ret
+SYM_FUNC_END(sha2_ce_transform)
diff --git a/arch/arm/crypto/sha2-ce-glue.c b/arch/arm/crypto/sha2-ce-glue.c
new file mode 100644
index 0000000000..88cbc7993d
--- /dev/null
+++ b/arch/arm/crypto/sha2-ce-glue.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * sha2-ce-glue.c - SHA-224/SHA-256 using ARMv8 Crypto Extensions
+ *
+ * Copyright (C) 2014 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
+ */
+
+#include <common.h>
+#include <digest.h>
+#include <init.h>
+#include <crypto/sha.h>
+#include <crypto/sha256_base.h>
+#include <crypto/internal.h>
+#include <linux/linkage.h>
+#include <asm/byteorder.h>
+#include <asm/neon.h>
+
+#include <asm/neon.h>
+
+MODULE_DESCRIPTION("SHA-224/SHA-256 secure hash using ARMv8 Crypto Extensions");
+MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_CRYPTO("sha224");
+MODULE_ALIAS_CRYPTO("sha256");
+
+struct sha256_ce_state {
+	struct sha256_state	sst;
+	u32			finalize;
+};
+
+extern const u32 sha256_ce_offsetof_count;
+extern const u32 sha256_ce_offsetof_finalize;
+
+asmlinkage int sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src,
+				 int blocks);
+
+static void __sha2_ce_transform(struct sha256_state *sst, u8 const *src,
+				int blocks)
+{
+	while (blocks) {
+		int rem;
+
+		kernel_neon_begin();
+		rem = sha2_ce_transform(container_of(sst, struct sha256_ce_state,
+						     sst), src, blocks);
+		kernel_neon_end();
+		src += (blocks - rem) * SHA256_BLOCK_SIZE;
+		blocks = rem;
+	}
+}
+
+const u32 sha256_ce_offsetof_count = offsetof(struct sha256_ce_state,
+					      sst.count);
+const u32 sha256_ce_offsetof_finalize = offsetof(struct sha256_ce_state,
+						 finalize);
+
+static int sha256_ce_update(struct digest *desc, const void *data,
+			    unsigned long len)
+{
+	struct sha256_ce_state *sctx = digest_ctx(desc);
+
+	sctx->finalize = 0;
+	sha256_base_do_update(desc, data, len, __sha2_ce_transform);
+
+	return 0;
+}
+
+static int sha256_ce_final(struct digest *desc, u8 *out)
+{
+	struct sha256_ce_state *sctx = digest_ctx(desc);
+
+	sctx->finalize = 0;
+	sha256_base_do_finalize(desc, __sha2_ce_transform);
+	return sha256_base_finish(desc, out);
+}
+
+static struct digest_algo sha224 = {
+	.base = {
+		.name		=	"sha224",
+		.driver_name	=	"sha224-ce",
+		.priority	=	200,
+		.algo		=	HASH_ALGO_SHA224,
+	},
+
+	.length	=	SHA224_DIGEST_SIZE,
+	.init	=	sha224_base_init,
+	.update	=	sha256_ce_update,
+	.final	=	sha256_ce_final,
+	.digest	=	digest_generic_digest,
+	.verify	=	digest_generic_verify,
+	.ctx_length =	sizeof(struct sha256_ce_state),
+};
+
+static int sha224_ce_digest_register(void)
+{
+	return digest_algo_register(&sha224);
+}
+coredevice_initcall(sha224_ce_digest_register);
+
+static struct digest_algo sha256 = {
+	.base = {
+		.name		=	"sha256",
+		.driver_name	=	"sha256-ce",
+		.priority	=	200,
+		.algo		=	HASH_ALGO_SHA256,
+	},
+
+	.length	=	SHA256_DIGEST_SIZE,
+	.init	=	sha256_base_init,
+	.update	=	sha256_ce_update,
+	.final	=	sha256_ce_final,
+	.digest	=	digest_generic_digest,
+	.verify	=	digest_generic_verify,
+	.ctx_length =	sizeof(struct sha256_ce_state),
+};
+
+static int sha256_ce_digest_register(void)
+{
+	return digest_algo_register(&sha256);
+}
+coredevice_initcall(sha256_ce_digest_register);
diff --git a/arch/arm/dts/.gitignore b/arch/arm/dts/.gitignore
deleted file mode 100644
index 077903c50a..0000000000
--- a/arch/arm/dts/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-*dtb*
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a637869fb6..056d4d565b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 # just to build a built-in.o. Otherwise compilation fails when no devicetree is
 # created.
 obj- += dummy.o
@@ -5,7 +7,9 @@ obj- += dummy.o
 lwl-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o
 lwl-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o
 lwl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o
+lwl-$(CONFIG_MACH_BEAGLEPLAY) += k3-am625-beagleplay.dtb.o
 lwl-$(CONFIG_MACH_CANON_A1100) += canon-a1100.dtb.o
+lwl-$(CONFIG_MACH_CLEP7212) += ep7212-clep7212.dtb.o
 lwl-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o
 lwl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o
 lwl-$(CONFIG_MACH_DUCKBILL) += imx28-duckbill.dtb.o
@@ -23,6 +27,7 @@ lwl-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o
 lwl-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += imx6ul-ccimx6ulsbcpro.dtb.o
 lwl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
 lwl-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o
+lwl-$(CONFIG_MACH_MEERKAT96) += imx7d-meerkat96.dtb.o
 lwl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
 lwl-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o
 lwl-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
@@ -31,6 +36,8 @@ lwl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
 lwl-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o
 lwl-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
 lwl-$(CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR) += imx7d-flex-concentrator-mfg.dtb.o
+lwl-$(CONFIG_MACH_KARO_QSXP_ML81) += imx8mp-karo-qsxp-ml81-qsbase4.dtb.o
+lwl-$(CONFIG_MACH_KOENIGBAUER_ALPHAJET) += imx8mp-koenigbauer-alphajet.dtb.o
 lwl-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \
 					imx6dl-samx6i.dtb.o
 lwl-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o
@@ -38,9 +45,11 @@ lwl-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o
 lwl-$(CONFIG_MACH_MARVELL_ARMADA_XP_DB) += armada-xp-db-bb.dtb.o
 lwl-$(CONFIG_MACH_MB7707) += module-mb7707.dtb.o
 lwl-$(CONFIG_MACH_MX28EVK) += imx28-evk.dtb.o
+lwl-$(CONFIG_MACH_MYIRTECH_X335X) += am335x-myirtech-myd.dtb.o
 lwl-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o
 lwl-$(CONFIG_MACH_NETGEAR_RN2120) += armada-xp-rn2120-bb.dtb.o
 lwl-$(CONFIG_MACH_NITROGEN6) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o imx6qp-nitrogen6_max.dtb.o
+lwl-$(CONFIG_MACH_NOVENA) += imx6q-novena.dtb.o
 lwl-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o
 lwl-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o
 lwl-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
@@ -73,9 +82,15 @@ lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \
 				imx6ull-phytec-phycore-som-nand.dtb.o \
 				imx6ull-phytec-phycore-som-emmc.dtb.o
 lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
+lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1) += stm32mp157c-phycore-stm32mp1-3.dtb.o
+lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MM) += imx8mm-phyboard-polis-rdk.dtb.o
 lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
+lwl-$(CONFIG_MACH_PINE64_QUARTZ64) += rk3566-quartz64-a.dtb.o
 lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
 lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
+lwl-$(CONFIG_MACH_POLYHEX_DEBIX) += \
+	imx8mp-debix-model-a.dtb.o \
+	imx8mp-debix-som-a-bmb-08.dtb.o
 lwl-$(CONFIG_MACH_PROTONIC_IMX6) += \
 	imx6q-prti6q.dtb.o \
 	imx6q-prtwd2.dtb.o \
@@ -91,42 +106,66 @@ lwl-$(CONFIG_MACH_PROTONIC_IMX6) += \
 	imx6dl-vicut1.dtb.o \
 	imx6qp-prtwd3.dtb.o \
 	imx6qp-vicutp.dtb.o \
-	imx6ul-prti6g.dtb.o
+	imx6ul-prti6g.dtb.o \
+	imx6ull-jozacp.dtb.o
+lwl-$(CONFIG_MACH_PROTONIC_IMX8M) += imx8mm-prt8mm.dtb.o
+lwl-$(CONFIG_MACH_PROTONIC_STM32MP1) += \
+	stm32mp151-prtt1a.dtb.o \
+	stm32mp151-prtt1c.dtb.o \
+	stm32mp151-prtt1s.dtb.o
 lwl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
+lwl-$(CONFIG_MACH_RADXA_ROCK3) += rk3568-rock-3a.dtb.o
+lwl-$(CONFIG_MACH_RADXA_ROCK5) += rk3588-rock-5b.dtb.o
+lwl-$(CONFIG_MACH_RADXA_CM3) += rk3566-cm3-io.dtb.o
 lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o
 lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
+lwl-$(CONFIG_MACH_RK3568_EVB) += rk3568-evb1-v10.dtb.o
+lwl-$(CONFIG_MACH_RK3568_BPI_R2PRO) += rk3568-bpi-r2-pro.dtb.o
 lwl-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o
 lwl-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o
 lwl-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o
 lwl-$(CONFIG_MACH_RPI_CM3) += bcm2837-rpi-cm3.dtb.o
+lwl-$(CONFIG_MACH_RPI4) += bcm2711-rpi-4.dtb.o bcm2711-rpi-400.dtb.o bcm2711-rpi-cm4-io.dtb.o bcm2711-rpi-cm4s-io.dtb.o
 lwl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
-lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
+lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o imx6qp-sabresd.dtb.o imx6dl-sabresd.dtb.o
 lwl-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
 lwl-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
 lwl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
+lwl-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += socfpga_arria10_mercury_aa1.dtb.o
 lwl-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o
 lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
+lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += socfpga_cyclone5_de10_nano.dtb.o
 lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
 lwl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
 lwl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o \
 				imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \
 				imx6q-h100.dtb.o
-lwl-$(CONFIG_MACH_SKOV_IMX6) += imx6dl-skov-imx6.dtb.o imx6q-skov-imx6.dtb.o
+lwl-$(CONFIG_MACH_SKOV_IMX6) += imx6s-skov-imx6.dtb.o imx6dl-skov-imx6.dtb.o imx6q-skov-imx6.dtb.o
+lwl-$(CONFIG_MACH_SKOV_IMX8MP) += imx8mp-skov.dtb.o
 lwl-$(CONFIG_MACH_SKOV_ARM9CPU) += at91-skov-arm9cpu.dtb.o
 lwl-$(CONFIG_MACH_SEEED_ODYSSEY) += stm32mp157c-odyssey.dtb.o
-lwl-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp157c-dk2.dtb.o stm32mp157a-dk1.dtb.o
-lwl-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o
-lwl-$(CONFIG_MACH_STM32MP15X_EV1) += stm32mp157c-ev1.dtb.o
+lwl-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp157c-dk2.dtb.o stm32mp157a-dk1.dtb.o \
+					stm32mp157c-dk2-scmi.dtb.o stm32mp157a-dk1-scmi.dtb.o
+lwl-$(CONFIG_MACH_STM32MP13XX_DK) += stm32mp135f-dk.dtb.o
+lwl-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o stm32mp157c-lxa-mc1-scmi.dtb.o
+lwl-$(CONFIG_MACH_STM32MP15X_EV1) += stm32mp157c-ev1.dtb.o stm32mp157c-ev1-scmi.dtb.o
 lwl-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o
 lwl-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o
 lwl-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o
 lwl-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o
-lwl-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o
+lwl-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o imx8mm-evkb.dtb.o
+lwl-$(CONFIG_MACH_NXP_IMX8MN_EVK) += imx8mn-evk.dtb.o imx8mn-ddr4-evk.dtb.o
 lwl-$(CONFIG_MACH_NXP_IMX8MP_EVK) += imx8mp-evk.dtb.o
 lwl-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o
+lwl-$(CONFIG_MACH_INNOCOMM_WB15) += imx8mm-innocomm-wb15-evk.dtb.o
+lwl-$(CONFIG_MACH_TQ_MBA8MPXL) += imx8mp-tqma8mpql-mba8mpxl.dtb.o
 lwl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
 lwl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
 lwl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
+lwl-$(CONFIG_MACH_TQMA6UL) += imx6ul-tqma6ul2-mba6ulx.dtb.o \
+			      imx6ul-tqma6ul2l-mba6ulx.dtb.o \
+			      imx6ull-tqma6ull2-mba6ulx.dtb.o \
+			      imx6ull-tqma6ull2l-mba6ulx.dtb.o
 lwl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
 lwl-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o
 lwl-$(CONFIG_MACH_TX6X) += imx6dl-tx6u.dtb.o
@@ -136,6 +175,7 @@ lwl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o
 lwl-$(CONFIG_MACH_UDOO_NEO) += imx6sx-udoo-neo-full.dtb.o
 lwl-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o
 lwl-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o
+lwl-$(CONFIG_MACH_VARISCITE_SOM_MX7) += imx7d-gome-e143_01.dtb.o
 lwl-$(CONFIG_MACH_VERSATILEPB) += versatile-pb.dtb.o
 lwl-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca9.dtb.o
 lwl-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca15.dtb.o
@@ -144,6 +184,7 @@ lwl-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o
 lwl-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o
 lwl-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o
 lwl-$(CONFIG_MACH_WEBASTO_CCBV2) += imx6ul-webasto-ccbv2.dtb.o
+lwl-$(CONFIG_MACH_WEBASTO_CCBV2) += imx6ul-webasto-marvel.dtb.o
 lwl-$(CONFIG_MACH_ZII_RDU1) +=	\
 	imx51-zii-rdu1.dtb.o		\
 	imx51-zii-scu2-mezz.dtb.o	\
@@ -161,18 +202,31 @@ lwl-$(CONFIG_MACH_ZII_VF610_DEV) += \
 	vf610-zii-spb4.dtb.o		\
 	vf610-zii-ssmb-dtu.dtb.o
 lwl-$(CONFIG_MACH_AC_SXB) += ac-sxb.dtb.o
+lwl-$(CONFIG_MACH_CALAO) += \
+	tny_a9260.dtb.o tny_a9g20.dtb.o \
+	usb_a9260.dtb.o usb_a9g20.dtb.o
 lwl-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o
+lwl-$(CONFIG_MACH_SAMA5D3_XPLAINED) += at91-sama5d3_xplained.dtb.o
 lwl-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o
+lwl-$(CONFIG_MACH_MICROCHIP_SAMA5D3_EDS) += at91-microchip-sama5d3-eds.dtb.o
 lwl-$(CONFIG_MACH_SAMA5D27_SOM1) += at91-sama5d27_som1_ek.dtb.o
 lwl-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += at91-sama5d27_giantboard.dtb.o
+lwl-$(CONFIG_MACH_SAMA5D4_WIFX) += at91-sama5d4_wifx_l1.dtb.o
 lwl-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
+lwl-$(CONFIG_MACH_XILINX_ZCU102) += zynqmp-zcu102-revA.dtb.o zynqmp-zcu102-revB.dtb.o
 lwl-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o
+lwl-$(CONFIG_MACH_XILINX_ZCU106) += zynqmp-zcu106-revA.dtb.o
 
 lwl-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o
 lwl-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o
+lwl-$(CONFIG_MACH_LS1028ARDB) += fsl-ls1028a-rdb.dtb.o
 lwl-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o
-lwl-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o
+lwl-$(CONFIG_MACH_TQMLS1046A) += fsl-ls1046a-tqmls1046a-mbls10xxa.dtb.o
+lwl-$(CONFIG_MACH_LS1021AIOT) += fsl-ls1021a-iot.dtb.o
 lwl-$(CONFIG_MACH_ZEDBOARD) += zynq-zed.dtb.o
 lwl-$(CONFIG_MACH_MNT_REFORM) += imx8mq-mnt-reform2.dtb.o
+lwl-$(CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP) += imx8mp-var-dart-dt8mcustomboard.dtb.o
+lwl-$(CONFIG_MACH_TQMA93XX) += imx93-tqma9352-mba93xxca.dtb.o \
+			       imx93-tqma9352-mba93xxla.dtb.o
 
-clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
+clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z
diff --git a/arch/arm/dts/am335x-baltos-minimal.dts b/arch/arm/dts/am335x-baltos-minimal.dts
index dff901f050..28a550aa84 100644
--- a/arch/arm/dts/am335x-baltos-minimal.dts
+++ b/arch/arm/dts/am335x-baltos-minimal.dts
@@ -45,6 +45,18 @@
 };
 
 &am33xx_pinmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dip_switch_pins>;
+
+	dip_switch_pins: pinmux_dip_switch_pins {
+		pinctrl-single,pins = <
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)
+		>;
+	};
+
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
 			0xf0 (INPUT_EN | PULL_UP) MUX_MODE0	/* mmc0_dat3.mmc0_dat3 */
@@ -285,6 +297,10 @@
 		interrupts = <20 GPIO_ACTIVE_LOW>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&tca6416_pins>;
+		gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3",
+				  "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3",
+				  "ModeA0", "ModeA1", "ModeA2", "ModeA3",
+				  "ModeB0", "ModeB1", "ModeB2", "ModeB3";
 	};
 };
 
@@ -399,33 +415,40 @@
 	};
 };
 
-&mac {
+&mac_sw {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&cpsw_default>;
 	pinctrl-1 = <&cpsw_sleep>;
-	dual_emac = <1>;
 
 	status = "okay";
 };
 
-&davinci_mdio {
+&davinci_mdio_sw {
+	status = "okay";
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&davinci_mdio_default>;
 	pinctrl-1 = <&davinci_mdio_sleep>;
 
-	status = "okay";
+	phy1: ethernet-phy@1 {
+		reg = <7>;
+		eee-broken-100tx;
+		eee-broken-1000t;
+	};
 };
 
-&cpsw_emac0 {
-	phy_id = <&davinci_mdio>, <0>;
+&cpsw_port1 {
 	phy-mode = "rmii";
-	dual_emac_res_vlan = <1>;
+	ti,dual-emac-pvid = <1>;
+	fixed-link {
+		speed = <100>;
+		full-duplex;
+	};
 };
 
-&cpsw_emac1 {
-	phy_id = <&davinci_mdio>, <7>;
-	phy-mode = "rgmii-txid";
-	dual_emac_res_vlan = <2>;
+&cpsw_port2 {
+	phy-mode = "rgmii-id";
+	ti,dual-emac-pvid = <2>;
+	phy-handle = <&phy1>;
 };
 
 &mmc1 {
@@ -438,3 +461,111 @@
 &gpio0 {
 	ti,no-reset-on-init;
 };
+
+&gpio1 {
+	gpio-line-names =
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"SW2_0_alt",
+		"SW2_1_alt",
+		"SW2_2_alt",
+		"SW2_3_alt",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC";
+};
+
+&gpio2 {
+	gpio-line-names =
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"SW2_0",
+		"SW2_1",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC";
+};
+
+&gpio3 {
+	gpio-line-names =
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"3G_PWR_EN",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"SW2_2",
+		"SW2_3",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC",
+		"NC";
+};
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index 8711802f57..f6e24d73ae 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -6,4 +6,4 @@
  * published by the Free Software Foundation.
  */
 
-#include <arm/am335x-bone-common.dtsi>
+#include <arm/ti/omap/am335x-bone-common.dtsi>
diff --git a/arch/arm/dts/am335x-myirtech-myd.dts b/arch/arm/dts/am335x-myirtech-myd.dts
new file mode 100644
index 0000000000..647b71cca7
--- /dev/null
+++ b/arch/arm/dts/am335x-myirtech-myd.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
+
+/dts-v1/;
+
+#include <arm/ti/omap/am335x-myirtech-myd.dts>
+
+/ {
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+	};
+
+	chosen {
+		environment {
+			compatible = "barebox,environment";
+			device-path = &nand_environment;
+		};
+	};
+};
+
+&nand_parts {
+	nand_environment: partition@180000 {
+		label = "env";
+		reg = <0x180000 0x40000>;
+	};
+
+	partition@1c0000 {
+		label = "system";
+		reg = <0x1c0000 0>;
+	};
+};
diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dtsi b/arch/arm/dts/am335x-phytec-phycard-som.dtsi
index e459824a77..a80f92f22c 100644
--- a/arch/arm/dts/am335x-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/am335x-phytec-phycard-som.dtsi
@@ -4,7 +4,7 @@
 
 		environment-nand {
 			compatible = "barebox,environment";
-			device-path = &nand, "partname:bareboxenv";
+			device-path = &env_nand;
 			status = "disabled";
 		};
 	};
@@ -211,7 +211,7 @@
 			reg = <0x100000 0x80000>;
 		};
 
-		partition@180000 {
+		env_nand: partition@180000 {
 			label = "bareboxenv";
 			reg = <0x180000 0x40000>;
 		};
diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
index 4b2ff9b2ea..275e146fce 100644
--- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
@@ -4,13 +4,13 @@
 
 		environment-spi {
 			compatible = "barebox,environment";
-			device-path = &flash, "partname:bareboxenv";
+			device-path = &env_nor;
 			status = "disabled";
 		};
 
 		environment-nand {
 			compatible = "barebox,environment";
-			device-path = &nand, "partname:bareboxenv";
+			device-path = &env_nand;
 			status = "disabled";
 		};
 	};
@@ -217,7 +217,7 @@
 			reg = <0x20000 0x80000>;
 		};
 
-		partition@a0000 {
+		env_nor: partition@a0000 {
 			label = "bareboxenv";
 			reg = <0xa0000 0x20000>;
 		};
@@ -333,7 +333,7 @@
 			reg = <0x100000 0x80000>;
 		};
 
-		partition@180000 {
+		env_nand: partition@180000 {
 			label = "bareboxenv";
 			reg = <0x180000 0x40000>;
 		};
diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi
index 29776f4556..2de89f6058 100644
--- a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi
+++ b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi
@@ -4,13 +4,13 @@
 
 		environment-spi {
 			compatible = "barebox,environment";
-			device-path = &flash, "partname:bareboxenv";
+			device-path = &env_nor;
 			status = "disabled";
 		};
 
 		environment-nand {
 			compatible = "barebox,environment";
-			device-path = &nand, "partname:bareboxenv";
+			device-path = &env_nand;
 			status = "disabled";
 		};
 	};
@@ -170,7 +170,7 @@
 			reg = <0x20000 0x80000>;
 		};
 
-		partition@a0000 {
+		env_nor: partition@a0000 {
 			label = "bareboxenv";
 			reg = <0xa0000 0x20000>;
 		};
@@ -312,7 +312,7 @@
 			reg = <0x100000 0x80000>;
 		};
 
-		partition@180000 {
+		env_nand: partition@180000 {
 			label = "bareboxenv";
 			reg = <0x180000 0x40000>;
 		};
diff --git a/arch/arm/dts/am33xx-clocks-strip.dtsi b/arch/arm/dts/am33xx-clocks-strip.dtsi
index e832616765..5560c68e5a 100644
--- a/arch/arm/dts/am33xx-clocks-strip.dtsi
+++ b/arch/arm/dts/am33xx-clocks-strip.dtsi
@@ -25,16 +25,12 @@
 /delete-node/ &dpll_ddr_ck;
 /delete-node/ &dpll_ddr_m2_ck;
 /delete-node/ &dpll_ddr_m2_div2_ck;
-/delete-node/ &dpll_disp_ck;
-/delete-node/ &dpll_disp_m2_ck;
 /delete-node/ &dpll_per_ck;
 /delete-node/ &dpll_per_m2_ck;
 /delete-node/ &dpll_per_m2_div4_wkupdm_ck;
 /delete-node/ &dpll_per_m2_div4_ck;
 /delete-node/ &clk_24mhz;
 /delete-node/ &clkdiv32k_ck;
-/delete-node/ &l3_gclk;
-/delete-node/ &pruss_ocp_gclk;
 /delete-node/ &mmu_fck;
 /delete-node/ &timer1_fck;
 /delete-node/ &timer3_fck;
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
index f1ee7b3c57..34764bb68e 100644
--- a/arch/arm/dts/am33xx.dtsi
+++ b/arch/arm/dts/am33xx.dtsi
@@ -7,7 +7,7 @@
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
  */
-#include <arm/am33xx.dtsi>
+#include <arm/ti/omap/am33xx.dtsi>
 
 / {
 	aliases {
diff --git a/arch/arm/dts/am35xx-pfc-750_820x.dts b/arch/arm/dts/am35xx-pfc-750_820x.dts
index 55c883944b..ad54be4dd6 100644
--- a/arch/arm/dts/am35xx-pfc-750_820x.dts
+++ b/arch/arm/dts/am35xx-pfc-750_820x.dts
@@ -10,7 +10,7 @@
  */
 /dts-v1/;
 
-#include <arm/am3517.dtsi>
+#include <arm/ti/omap/am3517.dtsi>
 
 / {
 	model = "Wago PFC200 (AM3505)";
diff --git a/arch/arm/dts/armada-370-mirabox-bb.dts b/arch/arm/dts/armada-370-mirabox-bb.dts
index 99263d4854..fcd72bda0e 100644
--- a/arch/arm/dts/armada-370-mirabox-bb.dts
+++ b/arch/arm/dts/armada-370-mirabox-bb.dts
@@ -3,11 +3,11 @@
  *   Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  */
 
-#include "arm/armada-370-mirabox.dts"
+#include "arm/marvell/armada-370-mirabox.dts"
 
 / {
 	chosen {
-		stdout-path = "/soc/internal-regs/serial@12000";
+		stdout-path = &uart0;
 	};
 };
 
diff --git a/arch/arm/dts/armada-370-rn104-bb.dts b/arch/arm/dts/armada-370-rn104-bb.dts
index 32f961e529..d59f00b9be 100644
--- a/arch/arm/dts/armada-370-rn104-bb.dts
+++ b/arch/arm/dts/armada-370-rn104-bb.dts
@@ -2,10 +2,10 @@
  * Barebox specific DT overlay for Netgear ReadyNAS 104
  */
 
-#include "arm/armada-370-netgear-rn104.dts"
+#include "arm/marvell/armada-370-netgear-rn104.dts"
 
 / {
 	chosen {
-		stdout-path = "/soc/internal-regs/serial@12000";
+		stdout-path = &uart0;
 	};
 };
diff --git a/arch/arm/dts/armada-385-turris-omnia-bb.dts b/arch/arm/dts/armada-385-turris-omnia-bb.dts
index 53bef01af7..ffea724ac4 100644
--- a/arch/arm/dts/armada-385-turris-omnia-bb.dts
+++ b/arch/arm/dts/armada-385-turris-omnia-bb.dts
@@ -1,7 +1,7 @@
-#include "arm/armada-385-turris-omnia.dts"
+#include "arm/marvell/armada-385-turris-omnia.dts"
 
 / {
 	chosen {
-		stdout-path = "/soc/internal-regs/serial@12000";
+		stdout-path = &uart0;
 	};
 };
diff --git a/arch/arm/dts/armada-xp-db-bb.dts b/arch/arm/dts/armada-xp-db-bb.dts
index 7201f4aaa1..68974de783 100644
--- a/arch/arm/dts/armada-xp-db-bb.dts
+++ b/arch/arm/dts/armada-xp-db-bb.dts
@@ -3,10 +3,10 @@
  *   Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  */
 
-#include "arm/armada-xp-db.dts"
+#include "arm/marvell/armada-xp-db.dts"
 
 / {
 	chosen {
-		stdout-path = "/soc/internal-regs/serial@12000";
+		stdout-path = &uart0;
 	};
 };
diff --git a/arch/arm/dts/armada-xp-gp-bb.dts b/arch/arm/dts/armada-xp-gp-bb.dts
index 3836016425..a863bd5bb1 100644
--- a/arch/arm/dts/armada-xp-gp-bb.dts
+++ b/arch/arm/dts/armada-xp-gp-bb.dts
@@ -3,10 +3,10 @@
  *   Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  */
 
-#include "arm/armada-xp-gp.dts"
+#include "arm/marvell/armada-xp-gp.dts"
 
 / {
 	chosen {
-		stdout-path = "/soc/internal-regs/serial@12000";
+		stdout-path = &uart0;
 	};
 };
diff --git a/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts b/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts
index b43bac37dd..5a883ecdc2 100644
--- a/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts
+++ b/arch/arm/dts/armada-xp-lenovo-ix4-300d-bb.dts
@@ -3,7 +3,7 @@
  *   Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  */
 
-#include "arm/armada-xp-lenovo-ix4-300d.dts"
+#include "arm/marvell/armada-xp-lenovo-ix4-300d.dts"
 
 &{/gpio-leds/power-led} {
 	linux,default-trigger = "heartbeat";
diff --git a/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts
index e57cd8f0ce..b4a80388bc 100644
--- a/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts
+++ b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts
@@ -3,10 +3,10 @@
  *   Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  */
 
-#include "arm/armada-xp-openblocks-ax3-4.dts"
+#include "arm/marvell/armada-xp-openblocks-ax3-4.dts"
 
 / {
 	chosen {
-		stdout-path = "/soc/internal-regs/serial@12000";
+		stdout-path = &uart0;
 	};
 };
diff --git a/arch/arm/dts/armada-xp-rn2120-bb.dts b/arch/arm/dts/armada-xp-rn2120-bb.dts
index 969136b336..30bf4f6229 100644
--- a/arch/arm/dts/armada-xp-rn2120-bb.dts
+++ b/arch/arm/dts/armada-xp-rn2120-bb.dts
@@ -2,10 +2,10 @@
  * Barebox specific DT overlay for Netgear ReadyNAS 2120
  */
 
-#include "arm/armada-xp-netgear-rn2120.dts"
+#include "arm/marvell/armada-xp-netgear-rn2120.dts"
 
 / {
 	chosen {
-		stdout-path = "/soc/internal-regs/serial@12000";
+		stdout-path = &uart0;
 	};
 };
diff --git a/arch/arm/dts/at91-microchip-ksz9477-evb.dts b/arch/arm/dts/at91-microchip-ksz9477-evb.dts
index 3eb2017942..9c2f6d97a6 100644
--- a/arch/arm/dts/at91-microchip-ksz9477-evb.dts
+++ b/arch/arm/dts/at91-microchip-ksz9477-evb.dts
@@ -1,26 +1,10 @@
-/*
- * at91-microchip-ksz9477-evb.dts - Device Tree file for the EVB-KSZ9477 board
- *
- *  Copyright (C) 2014 Atmel,
- *		  2014 Nicolas Ferre <nicolas.ferre@atmel.com>
- *		  2018 Ahmad Fatoum <a.fatoum@pengutronix.de>
- *
- * Licensed under GPLv2 or later.
- */
+/* SPDX-License-Identifier: GPL-2.0 */
 /dts-v1/;
-#include <arm/sama5d36.dtsi>
+#include <arm/microchip/at91-sama5d3_ksz9477_evb.dts>
+#include "sama5d3.dtsi"
 
 / {
-	model = "Microchip EVB-KSZ9477";
-	compatible = "atmel,sama5d3-ksz9477-evb", "atmel,sama5d3", "atmel,sama5";
-
-	aliases {
-		mmc0 = &mmc0;
-	};
-
 	chosen {
-		stdout-path = &dbgu;
-
 		environment {
 			compatible = "barebox,environment";
 			device-path = &mmc0, "partname:0";
@@ -29,125 +13,6 @@
 	};
 };
 
-&{/memory@20000000} {
-	reg = <0x20000000 0x10000000>;
-};
-
-&pinctrl {
-	board {
-		pinctrl_mmc0_cd: mmc0_cd {
-			atmel,pins =
-				<AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
-		};
-
-		pinctrl_spi_ksz: spi_ksz {
-			atmel,pins =
-				<
-				AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH
-				AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH
-				>;
-		};
-	};
-};
-
-&slow_xtal {
-	clock-frequency = <32768>;
-};
-
-&main_xtal {
-	clock-frequency = <12000000>;
-};
-
-&dbgu {
-	status = "okay";
-};
-
-&macb0 {
-	phy-mode = "rgmii";
-	gpios = <&pioB 28 GPIO_ACTIVE_LOW>;
-	status = "okay";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&mmc0 {
-	pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
-	status = "okay";
-	slot@0 {
-		reg = <0>;
-		bus-width = <8>;
-		cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&pmc {
-	main: mainck {
-		clock-frequency = <12000000>;
-	};
-};
-
-&spi1 {
-	pinctrl-0 = <&pinctrl_spi_ksz>;
-	cs-gpios = <&pioC 25 0>;
-	id = <1>;
-	status = "okay";
-
-	ksz9477: ksz9477@0 {
-		compatible = "microchip,ksz9477", "microchip,ksz9893";
-		reg = <0>;
-
-		/* Bus clock is 132 MHz. */
-		spi-max-frequency = <44000000>;
-		spi-cpha;
-		spi-cpol;
-		gpios = <&pioB 28 GPIO_ACTIVE_LOW>;
-		status = "okay";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "lan0";
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "cpu";
-				ethernet = <&macb0>;
-				phy-mode = "rgmii-id";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			/* port 6 is connected to eth0 */
-		};
-	};
+&reg_vcc_mmc0 {
+	status = "disabled";
 };
diff --git a/arch/arm/dts/at91-microchip-sama5d3-eds.dts b/arch/arm/dts/at91-microchip-sama5d3-eds.dts
new file mode 100644
index 0000000000..d35c8c3c6e
--- /dev/null
+++ b/arch/arm/dts/at91-microchip-sama5d3-eds.dts
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/dts-v1/;
+#include <arm/microchip/at91-sama5d3_eds.dts>
+#include "sama5d3.dtsi"
+
+/ {
+	chosen {
+		environment {
+			compatible = "barebox,environment";
+			device-path = &mmc0, "partname:0";
+			file-path = "barebox.env";
+		};
+	};
+};
diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts b/arch/arm/dts/at91-sama5d27_giantboard.dts
index 99fc5a8d4d..3aa28ed501 100644
--- a/arch/arm/dts/at91-sama5d27_giantboard.dts
+++ b/arch/arm/dts/at91-sama5d27_giantboard.dts
@@ -11,8 +11,8 @@
 
 /dts-v1/;
 
-#include <arm/sama5d2.dtsi>
-#include <arm/sama5d2-pinfunc.h>
+#include <arm/microchip/sama5d2.dtsi>
+#include <arm/microchip/sama5d2-pinfunc.h>
 #include <dt-bindings/mfd/atmel-flexcom.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/active-semi,8945a-regulator.h>
diff --git a/arch/arm/dts/at91-sama5d27_som1.dtsi b/arch/arm/dts/at91-sama5d27_som1.dtsi
new file mode 100644
index 0000000000..357f46e309
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d27_som1.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "sama5d2.dtsi"
+
+&macb0 {
+	nvmem-cells = <&macaddr>;
+	nvmem-cell-names = "mac-address";
+};
+
+&{i2c0/at24@50} {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	macaddr: mac-address@fa {
+		reg = <0xfa 6>;
+		label = "mac-address";
+	};
+};
diff --git a/arch/arm/dts/at91-sama5d27_som1_ek.dts b/arch/arm/dts/at91-sama5d27_som1_ek.dts
index 97a326dd2b..44e6305449 100644
--- a/arch/arm/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/dts/at91-sama5d27_som1_ek.dts
@@ -3,8 +3,8 @@
  * Copyright (C) 2019 Oleksij Rempel - Pengutronix
  */
 
-#include <arm/at91-sama5d27_som1_ek.dts>
-#include "sama5d2.dtsi"
+#include <arm/microchip/at91-sama5d27_som1_ek.dts>
+#include "at91-sama5d27_som1.dtsi"
 
 / {
 	chosen {
@@ -30,9 +30,8 @@
 	};
 };
 
+/delete-node/ &{qspi1/flash@0};
 &qspi1 {
-	/delete-node/ flash@0;
-
 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
diff --git a/arch/arm/dts/at91-sama5d3_xplained.dts b/arch/arm/dts/at91-sama5d3_xplained.dts
new file mode 100644
index 0000000000..de47ede7c6
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d3_xplained.dts
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 OR X11 */
+/*
+ *  Copyright (C) 2021 Ahmad Fatoum <a.fatoum@pengutronix.de>
+ */
+
+/dts-v1/;
+
+#include <arm/microchip/at91-sama5d3_xplained.dts>
+#include "sama5d3.dtsi"
+
+/ {
+	model = "Atmel sama5d3_xplained";
+
+	chosen {
+		environment {
+			compatible = "barebox,environment";
+			device-path = &mmc0, "partname:0";
+			file-path = "barebox.env";
+		};
+	};
+};
diff --git a/arch/arm/dts/at91-sama5d4_wifx_l1.dts b/arch/arm/dts/at91-sama5d4_wifx_l1.dts
new file mode 100644
index 0000000000..91c8073343
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d4_wifx_l1.dts
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+// SPDX-FileCopyrightText: 2021 Wifx
+// SPDX-FileCopyrightText: 2021 Yannick Lanz <yannick.lanz@wifx.net>
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+/dts-v1/;
+
+#include <arm/microchip/sama5d4.dtsi>
+#include "sama5d4.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Wifx L1";
+	compatible = "wifx,l1", "atmel,sama5d4", "atmel,sama5";
+
+	chosen {
+		stdout-path = &usart3;
+
+		environment-microsd {
+			compatible = "barebox,environment";
+			device-path = &mmc1;
+			file-path = "barebox.env";
+			status = "disabled";
+		};
+
+		environment-nand {
+			compatible = "barebox,environment";
+			device-path = &env_nand;
+			status = "disabled";
+		};
+	};
+
+	aliases {
+		rtc0 = &ds1339;
+		rtc1 = &rtc_internal;
+		serial1 = &usart1;
+		serial4 = &usart4;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay";
+
+		status_internal {
+			gpios = <&pioE 15 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	pps {
+	      compatible = "pps-gpio";
+	      pinctrl-names = "default";
+	      pinctrl-0 = <&pinctrl_gnss_pps>;
+
+	      gpios = <&pioC 24 GPIO_ACTIVE_HIGH>;
+	      /* assert-falling-edge; */
+	};
+
+	vddbu_2v_reg: regulator-vddbu-2v {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDBU_2V";
+		regulator-min-microvolt = <2000000>;
+		regulator-max-microvolt = <2000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&slow_xtal {
+	clock-frequency = <32768>;
+};
+
+&main_xtal {
+	clock-frequency = <12000000>;
+};
+
+&spi0 {
+	status = "okay";
+	cs-gpios = <&pioC 3 GPIO_ACTIVE_HIGH>;
+
+	sx1302@0 {
+		compatible = "semtech,sx1301";
+		spi-max-frequency = <10000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+	i2c-digital-filter;
+	i2c-analog-filter;
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+	i2c-digital-filter;
+	i2c-analog-filter;
+
+	stts751: temp_sensor@38 {
+		compatible = "stts751";
+		reg = <0x38>;
+	};
+
+	m24c08: eeprom@54 {
+		compatible = "atmel,24c08";
+		reg = <0x54>;
+		pagesize = <16>;
+	};
+
+	mac_at24mac402: eeprom@58 {
+		compatible = "atmel,24mac402";
+		reg = <0x58>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ethaddr: mac-address@9a {
+			reg = <0x9a 6>;
+		};
+	};
+
+	ds1339: rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+		trickle-resistor-ohms = <250>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	clock-frequency = <400000>;
+	i2c-digital-filter;
+	i2c-analog-filter;
+
+	ec@2a {
+		compatible = "wifx,wgw-ec-i2c";
+		reg = <0x2a>;
+
+		interrupt-parent = <&pioE>;
+		interrupts = <27 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_mcu_irq &pinctrl_mcu_cpu_state>;
+
+		cpu-state-gpios = <&pioA 19 0>;
+
+		usb_typec: usbc {
+			compatible = "wifx,wgw-ec-usbc";
+			#trigger-source-cells = <0>;
+		};
+
+		leds {
+			compatible = "wifx,wgw-ec-leds";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			statusled {
+				reg = <0>;
+				label = "status";
+				max-brightness = <255>;
+				linux,default-trigger = "heartbeat";
+			};
+
+			serviceled {
+				reg = <1>;
+				label = "service";
+				max-brightness = <255>;
+				linux,default-trigger = "wgw-usbc-data-mode";
+				trigger-sources = <&usb_typec>;
+			};
+		};
+	};
+};
+
+&macb0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
+	phy-mode = "rmii";
+	phy-handle = <&phy0>;
+	nvmem-cells = <&ethaddr>;
+	nvmem-cell-names = "mac-address";
+	status = "okay";
+
+	phy0: ethernet-phy@1 {
+		interrupt-parent = <&pioA>;
+		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+		reg = <1>;
+	};
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+	status = "okay";
+
+	slot@0 {
+		reg = <0>;
+		bus-width = <4>;
+		cd-gpios = <&pioE 3 0>;
+	};
+};
+
+&usart1 {
+	atmel,use-dma-rx;
+	atmel,use-dma-tx;
+	pinctrl-0 = <&pinctrl_usart1>;
+	status = "okay";
+};
+
+&usart3 {
+	atmel,use-dma-rx;
+	atmel,use-dma-tx;
+	status = "okay";
+};
+
+&tcb0 {
+	timer@0 {
+		compatible = "atmel,tcb-timer";
+		reg = <0>;
+	};
+
+	timer@1 {
+		compatible = "atmel,tcb-timer";
+		reg = <1>;
+	};
+};
+
+/* disable unused TCBs */
+&tcb1 {
+	status = "disabled";
+};
+
+&tcb2 {
+	status = "disabled";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+rtc_internal: &{/ahb/apb/rtc@fc0686b0} {
+	status = "okay";
+};
+
+&usb0 {
+	atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
+	atmel,id-gpio = <&pioD 11 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_vbus>;
+	status = "okay";
+};
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0 0 0 >;
+	atmel,id-gpio = <&pioD 11 GPIO_ACTIVE_HIGH 0 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_id>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&ebi {
+	pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe
+			&pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy
+			&pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&nand_controller {
+	status = "okay";
+	atmel,pmecc-cap = <4>;
+	atmel,pmecc-sector-size = <512>;
+
+	nand@3 {
+		reg = <0x3 0x0 0x2>;
+		atmel,rb = <0>;
+		nand-bus-width = <8>;
+		nand-ecc-mode = "hw";
+		nand-on-flash-bbt;
+		label = "atmel_nand";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			at91bootstrap@0 {
+				label = "at91bootstrap";
+				reg = <0x0 0x40000>;
+			};
+
+			uboot@40000 {
+				label = "uboot";
+				reg = <0x40000 0xC0000>;
+			};
+
+			env_nand: uboot-env@100000 {
+				label = "uboot-env";
+				reg = <0x100000 0x80000>;
+			};
+
+			ubi@180000 {
+				label = "ubi";
+				reg = <0x180000 0x3FE00000>;
+			};
+		};
+	};
+};
+
+&pinctrl {
+	board {
+		pinctrl_mmc1_cd: mmc1_cd {
+			atmel,pins = <AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+		pinctrl_usb_vbus: usb_vbus {
+			atmel,pins = <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+		pinctrl_usb_id: usb_id {
+			atmel,pins = <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+		pinctrl_mcu_irq: mcu_irq_0 {
+			atmel,pins = <AT91_PIOE 27 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+		pinctrl_mcu_cpu_state: mcu_cpu_state {
+			atmel,pins = <AT91_PIOA 19 AT91_PERIPH_GPIO (AT91_PINCTRL_OUTPUT | AT91_PINCTRL_OUTPUT_VAL(1))>;
+		};
+		pinctrl_macb0_phy_irq: macb0_phy_irq_0 {
+			atmel,pins = <AT91_PIOA 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+		pinctrl_sx130x_rst: sx130x_rst {
+			atmel,pins = <AT91_PIOA 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+		pinctrl_rf_front_pwr_en: rf_front_pwr_en {
+			atmel,pins = <AT91_PIOA 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+
+		pinctrl_ext_rst: ext_rst {
+			atmel,pins = <AT91_PIOA 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+		pinctrl_ext_pwr_en: ext_pwr_en {
+			atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>;
+		};
+		pinctrl_ext_boot_n: ext_boot_n {
+			atmel,pins = <AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+		pinctrl_ext_wake: ext_wake {
+			atmel,pins = <AT91_PIOA 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+		};
+		pinctrl_gnss_pps: gnss_pps {
+			atmel,pins = <AT91_PIOC 24 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+		};
+	};
+};
diff --git a/arch/arm/dts/at91-skov-arm9cpu.dts b/arch/arm/dts/at91-skov-arm9cpu.dts
index 8e4fddfd3f..d04d031f40 100644
--- a/arch/arm/dts/at91-skov-arm9cpu.dts
+++ b/arch/arm/dts/at91-skov-arm9cpu.dts
@@ -8,7 +8,7 @@
 
 /dts-v1/;
 
-#include "arm/at91sam9263.dtsi"
+#include <arm/microchip/at91sam9263.dtsi>
 
 / {
 	model = "SKOV ARM9 CPU";
@@ -17,9 +17,10 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 
-		environment {
+		environment-sd {
 			compatible = "barebox,environment";
-			device-path = &environment_nor;
+			device-path = &mmc1;
+			file-path = "barebox.env";
 		};
 	};
 
@@ -36,12 +37,12 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			barebox@0 {
+			u-boot@0 {
 				label = "bootloader";
 				reg = <0x00000 0x80000>;
 			};
 
-			environment_nor: env@80000 {
+			env@80000 {
 				label = "environment";
 				reg = <0x80000 0x20000>;
 			};
@@ -204,13 +205,11 @@
 	};
 };
 
-&{/ahb/apb} {
-	pinctrl: pinctrl@fffff200 {
-	};
+pinctrl: &{/ahb/apb/pinctrl@fffff200} {
+};
 
-	watchdog@fffffd40 {
+&{/ahb/apb/watchdog@fffffd40} {
 		status = "okay";
-	};
 };
 
 &dbgu {
diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi
new file mode 100644
index 0000000000..828ab6646e
--- /dev/null
+++ b/arch/arm/dts/at91sam9260.dtsi
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+&ebi {
+	status = "disabled";
+};
+
+&nand_controller {
+	status = "disabled";
+};
+
+&{/ahb/apb} {
+	nand0: nand@40000000 {
+		compatible = "atmel,at91rm9200-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x40000000 0x10000000
+		       0xffffe800 0x200
+		      >;
+		atmel,nand-addr-offset = <21>;
+		atmel,nand-cmd-offset = <22>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+		gpios = <&pioC 13 GPIO_ACTIVE_HIGH
+			 &pioC 14 GPIO_ACTIVE_HIGH
+			 0
+			>;
+		status = "disabled";
+	};
+};
+
+&usb0 { /* currently hangs with DT-enabled driver */
+	status = "disabled";
+};
diff --git a/arch/arm/dts/at91sam9263ek.dts b/arch/arm/dts/at91sam9263ek.dts
index 29a615f482..77da4479ab 100644
--- a/arch/arm/dts/at91sam9263ek.dts
+++ b/arch/arm/dts/at91sam9263ek.dts
@@ -1,4 +1,4 @@
-#include <arm/at91sam9263ek.dts>
+#include <arm/microchip/at91sam9263ek.dts>
 / {
 	chosen {
 		environment {
@@ -9,39 +9,37 @@
 
 };
 
-&nand_controller {
-	nand@3 {
-		/delete-node/ partitions;
+&{nand_controller/nand@3} {
+	/delete-node/ partitions;
 
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
 
-			at91bootstrap@0 {
-				label = "at91bootstrap";
-				reg = <0x0 0x20000>;
-			};
+		at91bootstrap@0 {
+			label = "at91bootstrap";
+			reg = <0x0 0x20000>;
+		};
 
-			barebox@20000 {
-				label = "barebox";
-				reg = <0x20000 0x100000>;
-			};
+		barebox@20000 {
+			label = "barebox";
+			reg = <0x20000 0x100000>;
+		};
 
-			environment_nand: bareboxenv@120000 {
-				label = "barebox-environment";
-				reg = <0x120000 0x20000>;
-			};
+		environment_nand: bareboxenv@120000 {
+			label = "barebox-environment";
+			reg = <0x120000 0x20000>;
+		};
 
-			rootfs@140000 {
-				label = "root";
-				reg = <0x140000 0x0>;
-			};
+		rootfs@140000 {
+			label = "root";
+			reg = <0x140000 0x0>;
 		};
 	};
 };
 
-&{/ahb/apb/mmc@fff84000} {
+&mmc1 {
 	pinctrl-0 = <
 		&pinctrl_board_mmc1
 		&pinctrl_mmc1_clk
diff --git a/arch/arm/dts/at91sam9g20.dtsi b/arch/arm/dts/at91sam9g20.dtsi
new file mode 100644
index 0000000000..b8301a8ce7
--- /dev/null
+++ b/arch/arm/dts/at91sam9g20.dtsi
@@ -0,0 +1,2 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include "at91sam9260.dtsi"
diff --git a/arch/arm/dts/at91sam9x5ek.dts b/arch/arm/dts/at91sam9x5ek.dts
index 3a6976a7d9..e25fb182cf 100644
--- a/arch/arm/dts/at91sam9x5ek.dts
+++ b/arch/arm/dts/at91sam9x5ek.dts
@@ -3,11 +3,11 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/at91.h>
 
-#include <arm/at91sam9x5.dtsi>
-#include <arm/at91sam9x5_macb0.dtsi>
-#include <arm/at91sam9x5_lcd.dtsi>
-#include <arm/at91sam9x5dm.dtsi>
-#include <arm/at91sam9x5ek.dtsi>
+#include <arm/microchip/at91sam9x5.dtsi>
+#include <arm/microchip/at91sam9x5_macb0.dtsi>
+#include <arm/microchip/at91sam9x5_lcd.dtsi>
+#include <arm/microchip/at91sam9x5dm.dtsi>
+#include <arm/microchip/at91sam9x5ek.dtsi>
 
 / {
 	aliases {
diff --git a/arch/arm/dts/bcm2711-rpi-4.dts b/arch/arm/dts/bcm2711-rpi-4.dts
new file mode 100644
index 0000000000..6d46dd3b83
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi-4.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <arm64/broadcom/bcm2711-rpi-4-b.dts>
+#include "bcm2711-rpi.dtsi"
diff --git a/arch/arm/dts/bcm2711-rpi-400.dts b/arch/arm/dts/bcm2711-rpi-400.dts
new file mode 100644
index 0000000000..fb9cccb2b9
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi-400.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <arm64/broadcom/bcm2711-rpi-400.dts>
+#include "bcm2711-rpi.dtsi"
diff --git a/arch/arm/dts/bcm2711-rpi-cm4-io.dts b/arch/arm/dts/bcm2711-rpi-cm4-io.dts
new file mode 100644
index 0000000000..115491e7a6
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi-cm4-io.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <arm64/broadcom/bcm2711-rpi-cm4-io.dts>
+#include "bcm2711-rpi.dtsi"
diff --git a/arch/arm/dts/bcm2711-rpi-cm4s-io.dts b/arch/arm/dts/bcm2711-rpi-cm4s-io.dts
new file mode 100644
index 0000000000..8302523e47
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi-cm4s-io.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "bcm2711-rpi-cm4-io.dts"
+
+&{/memory@0} {
+	reg = <0x0 0x0 0x0>;
+};
+
+/ {
+	compatible = "raspberrypi,4-compute-module-s", "brcm,bcm2711";
+	model = "Raspberry Pi Compute Module 4S IO Board";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart1 {
+	/delete-property/ clock-frequency;
+};
diff --git a/arch/arm/dts/bcm2711-rpi.dtsi b/arch/arm/dts/bcm2711-rpi.dtsi
new file mode 100644
index 0000000000..cb2952ccac
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+
+&{/memory@0} {
+	reg = <0x0 0x0 0x0>;
+};
+
+&uart1 {
+	/* VPU core clock is reported at 200MHz, but needs to be 500Mhz
+	 * for ns16550 driver to set correct baudrate. Until that's
+	 * figured out, hardcode clock frequency to the expected value
+	 */
+	clock-frequency = <500000000>;
+};
diff --git a/arch/arm/dts/bcm2835-rpi.dts b/arch/arm/dts/bcm2835-rpi.dts
index 8d352a457d..ed03a369bd 100644
--- a/arch/arm/dts/bcm2835-rpi.dts
+++ b/arch/arm/dts/bcm2835-rpi.dts
@@ -1,4 +1,4 @@
-#include <arm/bcm2835-rpi-a.dts>
+#include <arm/broadcom/bcm2835-rpi-a.dts>
 
 &{/aliases} {
 	usb0 = &usb;
diff --git a/arch/arm/dts/bcm2836-rpi-2.dts b/arch/arm/dts/bcm2836-rpi-2.dts
index c9106515ee..783128a549 100644
--- a/arch/arm/dts/bcm2836-rpi-2.dts
+++ b/arch/arm/dts/bcm2836-rpi-2.dts
@@ -1,4 +1,4 @@
-#include <arm/bcm2836-rpi-2-b.dts>
+#include <arm/broadcom/bcm2836-rpi-2-b.dts>
 
 &{/memory@0} {
 	reg = <0x0 0x0>;
diff --git a/arch/arm/dts/bcm2837-rpi-3.dts b/arch/arm/dts/bcm2837-rpi-3.dts
index e82d518fa5..38d673aec4 100644
--- a/arch/arm/dts/bcm2837-rpi-3.dts
+++ b/arch/arm/dts/bcm2837-rpi-3.dts
@@ -3,7 +3,3 @@
 &{/memory@0} {
 	reg = <0x0 0x0>;
 };
-
-&sdhci {
-	status = "disabled";
-};
diff --git a/arch/arm/dts/bcm2837-rpi-cm3.dts b/arch/arm/dts/bcm2837-rpi-cm3.dts
index 85a6ac4661..340fc58882 100644
--- a/arch/arm/dts/bcm2837-rpi-cm3.dts
+++ b/arch/arm/dts/bcm2837-rpi-cm3.dts
@@ -1,4 +1,4 @@
-#include <arm/bcm2837-rpi-cm3-io3.dts>
+#include <arm/broadcom/bcm2837-rpi-cm3-io3.dts>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/calao_nand.dtsi b/arch/arm/dts/calao_nand.dtsi
new file mode 100644
index 0000000000..e42d6cdc8c
--- /dev/null
+++ b/arch/arm/dts/calao_nand.dtsi
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+&nand0 {
+	nand-bus-width = <8>;
+	nand-ecc-mode = "soft";
+	nand-on-flash-bbt;
+	status = "okay";
+
+	at91bootstrap@0 {
+		label = "at91bootstrap";
+		reg = <0x0 0x20000>;
+	};
+
+	barebox@20000 {
+		label = "barebox";
+		reg = <0x20000 0x40000>;
+	};
+
+	bareboxenv@60000 {
+		label = "bareboxenv";
+		reg = <0x60000 0x20000>;
+	};
+
+	bareboxenv2@80000 {
+		label = "bareboxenv2";
+		reg = <0x80000 0x20000>;
+	};
+
+	oftree@80000 {
+		label = "oftree";
+		reg = <0xa0000 0x20000>;
+	};
+
+	kernel@a0000 {
+		label = "kernel";
+		reg = <0xc0000 0x400000>;
+	};
+
+	rootfs@4a0000 {
+		label = "rootfs";
+		reg = <0x4c0000 0x7800000>;
+	};
+
+	data@7ca0000 {
+		label = "data";
+		reg = <0x7cc0000 0x8340000>;
+	};
+};
diff --git a/arch/arm/dts/digic4.dtsi b/arch/arm/dts/digic4.dtsi
index 2db9393b33..051d8aad44 100644
--- a/arch/arm/dts/digic4.dtsi
+++ b/arch/arm/dts/digic4.dtsi
@@ -31,14 +31,14 @@
 	 * Assume that DIGIC4 has at least 96 pins.
 	 * So resource size is 96 * 4 = 0x180.
 	 */
-	gpio: gpio {
+	gpio: gpio@c0220000 {
 		compatible = "canon,digic-gpio";
 		reg = <0xc0220000 0x180>;
 		#gpio-cells = <2>;
 		gpio-controller;
 	};
 
-	uart: uart {
+	uart: uart@c0800000 {
 		compatible = "canon,digic-uart";
 		reg = <0xc0800000 0x1c>;
 	};
diff --git a/arch/arm/dts/dove-cubox-bb.dts b/arch/arm/dts/dove-cubox-bb.dts
index 06966d9c2e..5b93bfd1a0 100644
--- a/arch/arm/dts/dove-cubox-bb.dts
+++ b/arch/arm/dts/dove-cubox-bb.dts
@@ -3,7 +3,7 @@
  *   Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  */
 
-#include "arm/dove-cubox.dts"
+#include "arm/marvell/dove-cubox.dts"
 
 / {
 	chosen {
@@ -11,6 +11,6 @@
 	};
 };
 
-&{/leds/power} {
+&{/leds/led-power} {
 		barebox,default-trigger = "heartbeat";
 };
diff --git a/arch/arm/dts/ep7212-clep7212.dts b/arch/arm/dts/ep7212-clep7212.dts
new file mode 100644
index 0000000000..37a9399464
--- /dev/null
+++ b/arch/arm/dts/ep7212-clep7212.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Author: Alexander Shiyan <shc_work@mail.ru> */
+
+#include <arm/cirrus/ep7211.dtsi>
+
+/ {
+	model = "Cirrus Logic EP7212";
+	compatible = "cirrus,clep7212", "cirrus,ep7212", "cirrus,ep7209";
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0xc0000000 0x02000000>;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+
+		environment {
+			compatible = "barebox,environment";
+			device-path = &env_nor;
+		};
+	};
+};
+
+&bus {
+	/* Setup Memory Timings */
+	/* CS0 = WAITSTATE_6_1 | BUS_WIDTH_16 */
+	/* CS1 = WAITSTATE_6_1 | BUS_WIDTH_8 */
+	/* CS2 = WAITSTATE_8_3 | BUS_WIDTH_16 | CLKENB */
+	/* CS3 = WAITSTATE_7_1 | BUS_WIDTH_32 */
+	barebox,ep7209-memcfg1 = <0x25802b28>;
+
+	flash: nor@0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x02000000>;
+		bank-width = <2>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot";
+				reg = <0x00000 0x80000>;
+			};
+
+			env_nor: partition@80000 {
+				label = "env";
+				reg = <0x80000 0x40000>;
+			};
+
+			partition@c0000 {
+				label = "kernel";
+				reg = <0xc0000 0x340000>;
+			};
+
+			partition@400000 {
+				label = "root";
+				reg = <0x400000 0>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1021a-iot.dts b/arch/arm/dts/fsl-ls1021a-iot.dts
new file mode 100644
index 0000000000..47eebcb6a9
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1021a-iot.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale ls1021a IOT board device tree source
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <arm/nxp/ls/ls1021a-iot.dts>
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+
+		environment {
+			compatible = "barebox,environment";
+			device-path = &environment_qspi;
+		};
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	s70fl01gs: flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+
+		partitions {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			compatible = "fixed-partitions";
+
+			partition@0 {
+				label = "barebox";
+				reg = <0 0x100000>;
+			};
+
+			environment_qspi: partition@100000 {
+				label = "barebox-environment";
+				reg = <0x100000 0x40000>;
+			};
+		};
+	};
+};
+
+&i2c0 {
+	status = "disabled";
+};
+
+&i2c1 {
+	status = "okay";
+	eeprom@51 {
+		compatible = "atmel,24c512";
+		reg = <0x51>;
+	};
+};
+
+/* I2C1 and I2C2 are connected due to Errata on rev1 board */
+&i2c2 {
+	status = "disabled";
+};
+
+&uart0 {
+	status = "okay";
+	clock-frequency = <150000000>;
+};
+
+&uart1 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
new file mode 100644
index 0000000000..671c97413b
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/fsl-ls1028a-rdb.dts>
+#include "fsl-ls1028a.dtsi"
+
+/ {
+	chosen {
+		environment-sd {
+			status = "disabled";
+			compatible = "barebox,environment";
+			device-path = &part_env_sd;
+		};
+
+		environment-emmc {
+			status = "disabled";
+			compatible = "barebox,environment";
+			device-path = &part_env_emmc;
+		};
+	};
+
+	memory@80000000 {
+		/* Upstream dts has size 4GiB here which is wrong */
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+};
+
+/* SD */
+&esdhc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@1000 {
+		label = "barebox";
+		reg = <0x1000 0x1df000>;
+	};
+
+	part_env_sd: partition@1e0000 {
+		label = "barebox-environment";
+		reg = <0x1e0000 0x20000>;
+	};
+};
+
+/* eMMC */
+&esdhc1 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@1000 {
+		label = "barebox";
+		reg = <0x1000 0x1df000>;
+	};
+
+	part_env_emmc: partition@1e0000 {
+		label = "barebox-environment";
+		reg = <0x1e0000 0x20000>;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
new file mode 100644
index 0000000000..a15a219cfa
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -0,0 +1,7 @@
+
+/ {
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index d842387fa0..37023fae9b 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -3,11 +3,11 @@
 /dts-v1/;
 
 #include <arm64/freescale/fsl-ls1046a-rdb.dts>
+#include "fsl-ls1046a.dtsi"
 
 / {
 	aliases {
-		eeprom = &eeprom;
-		mmc0 = &esdhc;
+		eeprom = &{i2c0/eeprom@52};
 	};
 
 	chosen {
@@ -47,17 +47,6 @@
 	status = "okay";
 };
 
-&i2c0 {
-	eeprom: eeprom@52 {
-		compatible = "atmel,24c04";
-	};
-
-	non_existent_eeprom: eeprom@53 {
-	};
-};
-
-/delete-node/ &non_existent_eeprom;
-
 &enet0 {
 	status = "disabled";
 };
@@ -74,35 +63,35 @@
 	phy-mode = "rgmii-id";
 };
 
-&{/soc/fman@1a00000/mdio@e1000} {
+&{fman0/mdio@e1000} {
 	status = "disabled";
 };
 
-&{/soc/fman@1a00000/mdio@e3000} {
+&{fman0/mdio@e3000} {
 	status = "disabled";
 };
 
-&{/soc/fman@1a00000/mdio@e5000} {
+&{fman0/mdio@e5000} {
 	status = "disabled";
 };
 
-&{/soc/fman@1a00000/mdio@e7000} {
+&{fman0/mdio@e7000} {
 	status = "disabled";
 };
 
-&{/soc/fman@1a00000/mdio@e9000} {
+&{fman0/mdio@e9000} {
 	status = "disabled";
 };
 
-&{/soc/fman@1a00000/mdio@eb000} {
+&{fman0/mdio@eb000} {
 	status = "disabled";
 };
 
-&{/soc/fman@1a00000/mdio@f1000} {
+&{fman0/mdio@f1000} {
 	status = "disabled";
 };
 
-&{/soc/fman@1a00000/mdio@f3000} {
+&{fman0/mdio@f3000} {
 	status = "disabled";
 };
 
@@ -120,14 +109,14 @@
 	dr_mode = "host";
 };
 
-&{/soc/pcie@3400000} {
+&pcie1 {
 	status = "okay";
 };
 
-&{/soc/pcie@3500000} {
+&pcie2 {
 	status = "okay";
 };
 
-&{/soc/pcie@3600000} {
+&pcie3 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/fsl-ls1046a-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-ls1046a-tqmls1046a-mbls10xxa.dts
new file mode 100644
index 0000000000..787a85394c
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-tqmls1046a-mbls10xxa.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for TQMLS1046A SoM on MBLS10xxA from TQ
+ */
+
+/dts-v1/;
+
+#include <arm64/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts>
+#include "fsl-ls1046a.dtsi"
+
+/ {
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &environment_sd;
+			status = "disabled";
+		};
+
+		environment-qspi {
+			compatible = "barebox,environment";
+			device-path = &environment_qspi;
+			status = "disabled";
+		};
+	};
+};
+
+&esdhc {
+	partitions {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "fixed-partitions";
+
+		partition@1000 {
+			label = "barebox";
+			reg = <0x1000 0xdf000>;
+		};
+
+		environment_sd: partition@e0000 {
+			label = "barebox-environment";
+			reg = <0xe0000 0x20000>;
+		};
+	};
+};
+
+&qflash0 {
+	partitions {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "fixed-partitions";
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x200000>;
+		};
+
+		environment_qspi: partition@200000 {
+			label = "barebox-environment";
+			reg = <0x200000 0x80000>;
+		};
+
+		partition@280000 {
+			label = "data";
+			reg = <0x280000 0x0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
new file mode 100644
index 0000000000..a661cb0c89
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/ {
+	aliases {
+		mmc0 = &esdhc;
+	};
+};
diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
deleted file mode 100644
index 7f9a764a82..0000000000
--- a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
+++ /dev/null
@@ -1,364 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree Include file for TQMLS1046A SoM on MBLS10xxA from TQ
- *
- * Copyright 2018 TQ-Systems GmbH
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "fsl-tqmls1046a.dtsi"
-
-/ {
-	model = "TQ TQMLS1046A SoM on MBLS10xxA board";
-	compatible = "tqc,tqmls1046a", "fsl,ls1046a";
-
-	aliases {
-		serial0 = &duart0;
-		serial1 = &duart1;
-		mmc0 = &esdhc;
-		qspiflash0 = &qflash0;
-		qspiflash1 = &qflash1;
-		qsgmii_s1_p1 = &qsgmii1_phy1;
-		qsgmii_s1_p2 = &qsgmii1_phy2;
-		qsgmii_s2_p1 = &qsgmii2_phy1;
-		qsgmii_s2_p2 = &qsgmii2_phy2;
-		qsgmii_s2_p3 = &qsgmii2_phy3;
-		qsgmii_s2_p4 = &qsgmii2_phy4;
-	};
-
-	chosen {
-		stdout-path = "serial1:115200n8";
-
-		environment-sd {
-			compatible = "barebox,environment";
-			device-path = &environment_sd;
-			status = "disabled";
-		};
-
-		environment-qspi {
-			compatible = "barebox,environment";
-			device-path = &environment_qspi;
-			status = "disabled";
-		};
-	};
-
-	gpio-keys-polled {
-		compatible = "gpio-keys-polled";
-		gpio-keys,name = "gpio-keys";
-		poll-interval = <100>;
-		autorepeat;
-
-		button0 {
-			label = "button0";
-			gpios = <&gpioexp3 5 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_F1>;
-		};
-
-		button1 {
-			label = "button1";
-			gpios = <&gpioexp3 6 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_F2>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		user {
-			gpios = <&gpioexp3 13 GPIO_ACTIVE_LOW>;
-			label = "led:user";
-			linux,default-trigger = "heartbeat";
-		};
-	};
-
-};
-
-&esdhc {
-	partitions {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		compatible = "fixed-partitions";
-
-		partition@1000 {
-			label = "barebox";
-			reg = <0x1000 0xdf000>;
-		};
-
-		environment_sd: partition@e0000 {
-			label = "barebox-environment";
-			reg = <0xe0000 0x20000>;
-		};
-	};
-};
-
-&duart0 {
-	status = "okay";
-};
-
-&duart1 {
-	status = "okay";
-};
-
-&esdhc {
-	mmc-hs200-1_8v;
-	sd-uhs-sdr104;
-	sd-uhs-sdr50;
-	sd-uhs-sdr25;
-	sd-uhs-sdr12;
-};
-
-&i2c3 {
-	status = "okay";
-
-	i2c-mux@70 {
-		compatible = "nxp,pca9544";
-		reg = <0x70>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		i2c@0 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0>;
-
-			gpioexp1: pca9555@20 {
-				compatible = "nxp,pca9555";
-				reg = <0x20>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				gpio-line-names = "sd1_3_lane_a_mux",
-						  "sd1_2_lane_b_mux",
-						  "sd1_0_lane_d_mux",
-						  "sd2_1_lane_b_mux",
-						  "sd2_3_lane_d_mux1",
-						  "sd2_3_lane_d_mux2",
-						  "sd_mux_shdn",
-						  "sd1_ref_clk2_sel",
-						  "mpcie1_disable_n",
-						  "mpcie1_wake_n",
-						  "mpcie2_disable_n",
-						  "mpcie2_wake_n",
-						  "prsnt_n",
-						  "pcie_pwr_en",
-						  "dcdc_pwr_en",
-						  "dcdc_pgood_1v8";
-			};
-
-			gpioexp2: pca9555@21 {
-				compatible = "nxp,pca9555";
-				reg = <0x21>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				gpio-line-names = "xfi1_tx_dis",
-						  "xfi1_tx_fault",
-						  "xfi1_moddef_det",
-						  "xfi1_rx_loss",
-						  "retimer1_loss",
-						  "xfi1_ensmb",
-						  "qsgmii1_clk_sel0",
-						  "qsgmii_phy1_config3",
-						  "xfi2_tx_fault",
-						  "xfi2_tx_dis",
-						  "xfi2_moddef_det",
-						  "xfi2_rx_loss",
-						  "retimer2_loss",
-						  "xfi2_ensmb",
-						  "qsgmii2_clk_sel0",
-						  "qsgmii_phy2_config3";
-			};
-
-			gpioexp3: pca9555@22 {
-				compatible = "nxp,pca9555";
-				reg = <0x22>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				gpio-line-names = "ec1_phy_pwdn",
-						  "ec2_phy_pwdn",
-						  "usb_c_pwron",
-						  "usb_en_oc_3v3_n",
-						  "usb_h_grst_n",
-						  "gpio_button0",
-						  "gpio_button1",
-						  "sda_pwr_en",
-						  "qsgmii_phy1_int_n",
-						  "qsgmii_phy2_int_n",
-						  "spi_clko_sof",
-						  "spi_int",
-						  "can_sel",
-						  "led_n",
-						  "pcie_rst_3v3_n",
-						  "pcie_wake_3v3_n";
-			};
-		};
-
-		i2c@1 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x1>;
-		};
-
-		i2c@2 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x2>;
-		};
-
-		i2c@3 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x3>;
-		};
-	};
-};
-
-&usb1 {
-	dr_mode = "otg";
-};
-
-#include <arm64/freescale/fsl-ls1046-post.dtsi>
-#include <dt-bindings/net/ti-dp83867.h>
-
-&fman0 {
-	status = "okay";
-};
-
-&enet0 { /* EMAC.1 */
-	phy-connection-type = "sgmii";
-};
-
-&enet1 { /* EMAC.2 */
-	phy-connection-type = "sgmii";
-};
-
-&enet2 { /* EMAC.3 */
-	phy-handle = <&rgmii_phy1>;
-	phy-connection-type = "rgmii";
-	phy-mode = "rgmii-id";
-};
-
-&enet3 { /* EMAC.4 */
-	phy-handle = <&rgmii_phy2>;
-	phy-connection-type = "rgmii";
-	phy-mode = "rgmii-id";
-};
-
-&enet4 { /* EMAC.5 */
-	phy-connection-type = "sgmii";
-};
-
-&enet5 { /* EMAC.6 */
-	phy-connection-type = "sgmii";
-};
-
-&enet6 { /* EMAC.9 */
-	phy-connection-type = "sgmii";
-};
-
-&enet7 { /* EMAC.10 */
-	phy-connection-type = "sgmii";
-};
-
-&{/soc/fman@1a00000/mdio@e1000} {
-	status = "disabled";
-};
-
-&{/soc/fman@1a00000/mdio@e3000} {
-	status = "disabled";
-};
-
-&{/soc/fman@1a00000/mdio@e5000} {
-	status = "disabled";
-};
-
-&{/soc/fman@1a00000/mdio@e7000} {
-	status = "disabled";
-};
-
-&{/soc/fman@1a00000/mdio@e9000} {
-	status = "disabled";
-};
-
-&{/soc/fman@1a00000/mdio@eb000} {
-	status = "disabled";
-};
-
-&{/soc/fman@1a00000/mdio@f1000} {
-	status = "disabled";
-};
-
-&{/soc/fman@1a00000/mdio@f3000} {
-	status = "disabled";
-};
-
-&mdio0 {
-	rgmii_phy1: ethernet-phy@0e {
-		reg = <0x0e>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
-		ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
-	};
-
-	rgmii_phy2: ethernet-phy@0c {
-		reg = <0x0c>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
-		ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
-	};
-
-	qsgmii1_phy1: ethernet-phy@1c {
-		reg = <0x1c>;
-	};
-
-	qsgmii1_phy2: ethernet-phy@1d {
-		reg = <0x1d>;
-	};
-
-	qsgmii2_phy1: ethernet-phy@00 {
-		reg = <0x00>;
-	};
-
-	qsgmii2_phy2: ethernet-phy@01 {
-		reg = <0x01>;
-	};
-
-	qsgmii2_phy3: ethernet-phy@02 {
-		reg = <0x02>;
-	};
-
-	qsgmii2_phy4: ethernet-phy@03 {
-		reg = <0x03>;
-	};
-};
-
-&xmdio0 {
-	status = "disabled";
-};
-
-&qflash0 {
-	partitions {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		compatible = "fixed-partitions";
-
-		partition@0 {
-			label = "barebox";
-			reg = <0x0 0x200000>;
-		};
-
-		environment_qspi: partition@200000 {
-			label = "barebox-environment";
-			reg = <0x200000 0x80000>;
-		};
-
-		partition@280000 {
-			label = "data";
-			reg = <0x280000 0x0>;
-		};
-	};
-};
diff --git a/arch/arm/dts/fsl-tqmls1046a.dtsi b/arch/arm/dts/fsl-tqmls1046a.dtsi
deleted file mode 100644
index 0ea2612cbf..0000000000
--- a/arch/arm/dts/fsl-tqmls1046a.dtsi
+++ /dev/null
@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree Include file for LS1046A based SoM of TQ
- *
- * Copyright 2018 TQ-Systems GmbH
- */
-
-#include <arm64/freescale/fsl-ls1046a.dtsi>
-
-&i2c0 {
-	status = "okay";
-
-	temp-sensor@18 {
-		compatible = "jc42";
-		reg = <0x18>;
-	};
-
-	eeprom@50 {
-		compatible = "atmel,24c02";
-		reg = <0x50>;
-	};
-
-	rtc@51 {
-		compatible = "nxp,pcf85063";
-		reg = <0x51>;
-	};
-
-	eeprom@57 {
-		compatible = "atmel,24c256";
-		reg = <0x57>;
-	};
-};
-
-&qspi {
-	num-cs = <2>;
-	bus-num = <0>;
-	status = "okay";
-
-	qflash0: mx66u51235f@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <62500000>;
-		reg = <0>;
-	};
-
-	qflash1: mx66u51235f@1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <62500000>;
-		reg = <1>;
-	};
-};
diff --git a/arch/arm/dts/imx1-scb9328.dts b/arch/arm/dts/imx1-scb9328.dts
index aac82d0afd..bcc1598e3b 100644
--- a/arch/arm/dts/imx1-scb9328.dts
+++ b/arch/arm/dts/imx1-scb9328.dts
@@ -4,7 +4,7 @@
  */
 
 /dts-v1/;
-#include <arm/imx1.dtsi>
+#include <arm/nxp/imx/imx1.dtsi>
 
 / {
 	model = "Synertronix scb9328";
diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts
index 2785a3c91a..9de8c5a841 100644
--- a/arch/arm/dts/imx25-karo-tx25.dts
+++ b/arch/arm/dts/imx25-karo-tx25.dts
@@ -9,14 +9,14 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx25-karo-tx25.dts>
+#include <arm/nxp/imx/imx25-karo-tx25.dts>
 #include "imx25.dtsi"
 
 / {
 	chosen {
 		environment {
 			compatible = "barebox,environment";
-			device-path = &nfc, "partname:environment";
+			device-path = &env_nand;
 		};
 	};
 };
@@ -34,7 +34,7 @@
 		reg = <0x0 0x80000>;
 	};
 
-	partition@80000 {
+	env_nand: partition@80000 {
 		label = "environment";
 		reg = <0x80000 0x80000>;
 	};
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
index abfbd5061e..d9ba6abae6 100644
--- a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
+++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
@@ -2,7 +2,7 @@
  * Barebox specific DT overlay for Phytec PCA100 RDK
  */
 
-#include <arm/imx27-phytec-phycard-s-rdk.dts>
+#include <arm/nxp/imx/imx27-phytec-phycard-s-rdk.dts>
 
 / {
 	chosen {
@@ -10,7 +10,7 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &nfc, "partname:environment";
+			device-path = &env_nand;
 		};
 	};
 };
@@ -21,7 +21,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_nand: partition@e0000 {
 		label = "environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/dts/imx27-phytec-phycore-rdk.dts
index fff154cb97..04f037bab8 100644
--- a/arch/arm/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/dts/imx27-phytec-phycore-rdk.dts
@@ -2,7 +2,7 @@
  * Barebox specific DT overlay for Phytec PCM-970 RDK
  */
 
-#include <arm/imx27-phytec-phycore-rdk.dts>
+#include <arm/nxp/imx/imx27-phytec-phycore-rdk.dts>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/imx28-duckbill.dts b/arch/arm/dts/imx28-duckbill.dts
index 2a995a7938..31e6f43a22 100644
--- a/arch/arm/dts/imx28-duckbill.dts
+++ b/arch/arm/dts/imx28-duckbill.dts
@@ -1,4 +1,4 @@
-#include <arm/imx28-duckbill.dts>
+#include <arm/nxp/mxs/imx28-duckbill.dts>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/imx28-evk.dts b/arch/arm/dts/imx28-evk.dts
index c82dfa4d8c..15159f2d98 100644
--- a/arch/arm/dts/imx28-evk.dts
+++ b/arch/arm/dts/imx28-evk.dts
@@ -1,4 +1,4 @@
-#include <arm/imx28-evk.dts>
+#include <arm/nxp/mxs/imx28-evk.dts>
 
 / {
 	chosen {
@@ -6,7 +6,7 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &gpmi, "partname:environment";
+			device-path = &env_nand;
 		};
 	};
 };
@@ -21,7 +21,7 @@
 		reg = <0x0 0x80000>;
 	};
 
-	partition@80000 {
+	env_nand: partition@80000 {
 		label = "environment";
 		reg = <0x80000 0x80000>;
 	};
diff --git a/arch/arm/dts/imx50.dtsi b/arch/arm/dts/imx50.dtsi
index b5def2e4f6..e0fe104302 100644
--- a/arch/arm/dts/imx50.dtsi
+++ b/arch/arm/dts/imx50.dtsi
@@ -1,6 +1,6 @@
-#include <arm/imx50.dtsi>
+#include <arm/nxp/imx/imx50.dtsi>
 
-&{/soc/bus@50000000} { /* AIPS1 */
+&aips1 {
 	usbphy1: usbphy@1 {
 		compatible = "usb-nop-xceiv";
 		clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
diff --git a/arch/arm/dts/imx51-babbage.dts b/arch/arm/dts/imx51-babbage.dts
index f85415f6db..bd8ef0c06a 100644
--- a/arch/arm/dts/imx51-babbage.dts
+++ b/arch/arm/dts/imx51-babbage.dts
@@ -10,7 +10,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx51-babbage.dts>
+#include <arm/nxp/imx/imx51-babbage.dts>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/imx51-ccxmx51.dts b/arch/arm/dts/imx51-ccxmx51.dts
index efe5dbf631..d553644730 100644
--- a/arch/arm/dts/imx51-ccxmx51.dts
+++ b/arch/arm/dts/imx51-ccxmx51.dts
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /* Author: Alexander Shiyan <shc_work@mail.ru> */
 
-#include <arm/imx51-digi-connectcore-jsk.dts>
+#include <arm/nxp/imx/imx51-digi-connectcore-jsk.dts>
 
 / {
 	chosen {
@@ -9,7 +9,7 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &nfc, "partname:env";
+			device-path = &env_nand;
 		};
 	};
 };
@@ -24,7 +24,7 @@
 		reg = <0x00000 0x80000>;
 	};
 
-	partition@80000 {
+	env_nand: partition@80000 {
 		label = "env";
 		reg = <0x80000 0x40000>;
 	};
diff --git a/arch/arm/dts/imx51-genesi-efika-sb.dts b/arch/arm/dts/imx51-genesi-efika-sb.dts
index 7e3017f981..1d8183fff1 100644
--- a/arch/arm/dts/imx51-genesi-efika-sb.dts
+++ b/arch/arm/dts/imx51-genesi-efika-sb.dts
@@ -11,7 +11,7 @@
 
 /dts-v1/;
 #include "imx51.dtsi"
-#include <arm/imx51.dtsi>
+#include <arm/nxp/imx/imx51.dtsi>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
@@ -24,13 +24,13 @@
 
 		environment-sd {
 			compatible = "barebox,environment";
-			device-path = &esdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 			status = "disabled";
 		};
 
 		environment-spi {
 			compatible = "barebox,environment";
-			device-path = &flash, "partname:barebox-environment";
+			device-path = &env_nor;
 			status = "disabled";
 		};
 	};
@@ -394,9 +394,10 @@
 
 &ipu_di1 {
 	interface-pix-fmt = "rgb565";
-	endpoint {
-		remote-endpoint = <&mtl017_in>;
-	};
+};
+
+&ipu_di1_disp2 {
+	remote-endpoint = <&mtl017_in>;
 };
 
 &esdhc1 {
@@ -416,7 +417,7 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
@@ -534,7 +535,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		partition@e0000 {
+		env_nor: partition@e0000 {
 			label = "barebox-environment";
 			reg = <0xe0000 0x20000>;
 		};
diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts
index 857c9ad96c..6bb491ec3b 100644
--- a/arch/arm/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/dts/imx51-zii-rdu1.dts
@@ -11,7 +11,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx51-zii-rdu1.dts>
+#include <arm/nxp/imx/imx51-zii-rdu1.dts>
 
 / {
 	compatible = "zii,imx51-rdu1", "fsl,imx51-babbage-power", "fsl,imx51";
@@ -21,7 +21,7 @@
 
 		environment-spi {
 			compatible = "barebox,environment";
-			device-path = &spinor, "partname:barebox-environment";
+			device-path = &env_spinor;
 		};
 
 		ubootenv {
@@ -53,33 +53,31 @@
                  * the switch shared DT node with it, so we use that
                  * fact to create a desirable naming
 		 */
-		switch-eeprom = &switch;
-		microwire-eeprom = &microwire_eeprom;
+		switch-eeprom = &{mdio_gpio/switch@0};
+		microwire-eeprom = &{spi_gpio/eeprom@0};
 	};
 };
 
-&ecspi1 {
-	spinor: flash@1 {
-		partition@0 {
-			/*
-			 * Do not change the size of this
-			 * partition. RDU1's BBU code relies on
-			 * "barebox" partition starting at 1024 byte
-			 * mark to function properly
-			 */
-			label = "config";
-			reg = <0x0 0x400>;
-		};
+spinor: &{ecspi1/flash@1} {
+	partition@0 {
+		/*
+		 * Do not change the size of this
+		 * partition. RDU1's BBU code relies on
+		 * "barebox" partition starting at 1024 byte
+		 * mark to function properly
+		 */
+		label = "config";
+		reg = <0x0 0x400>;
+	};
 
-		partition@400 {
-			label = "barebox";
-			reg = <0x400 0xdfc00>;
-		};
+	partition@400 {
+		label = "barebox";
+		reg = <0x400 0xdfc00>;
+	};
 
-		partition@e0000 {
-			label = "barebox-environment";
-			reg = <0xe0000 0x20000>;
-		};
+	env_spinor: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
 	};
 };
 
@@ -99,33 +97,21 @@
 	};
 };
 
-&mdio_gpio {
-	switch: switch@0 {};
+&{uart3/mcu/watchdog} {
+	nvmem-cells = <&boot_source>;
+	nvmem-cell-names = "boot-source";
 };
 
-&spi_gpio {
-	microwire_eeprom: eeprom@0 {};
-};
-
-&uart3 {
-	rave-sp {
-		watchdog {
-			nvmem-cells = <&boot_source>;
-			nvmem-cell-names = "boot-source";
-		};
+&{uart3/mcu/eeprom@a4} {
+	nvmem-cells = <&shadow_config>;
+	nvmem-cell-names = "shadow-config";
 
-		eeprom@a4 {
-			nvmem-cells = <&shadow_config>;
-			nvmem-cell-names = "shadow-config";
-
-			boot_source: boot-source@83 {
-				reg = <0x83 1>;
-			};
+	boot_source: boot-source@83 {
+		reg = <0x83 1>;
+	};
 
-			shadow_config: shadow-config@1000 {
-				reg = <0x1000 0x400>;
-			};
-		};
+	shadow_config: shadow-config@1000 {
+		reg = <0x1000 0x400>;
 	};
 };
 
@@ -133,44 +119,41 @@
 	status = "disabled";
 };
 
-&iomuxc {
-	pinctrl_usbh1: usbh1grp {
-
-		/*
-		 * Overwrite upstream USBH1,2 iomux settings to match
-		 * the setting U-Boot would set these to. Remove this
-		 * once this is fixed upstream.
-		 */
-		fsl,pins = <
-			MX51_PAD_USBH1_STP__USBH1_STP		0x1e5
-			MX51_PAD_USBH1_CLK__USBH1_CLK		0x1e5
-			MX51_PAD_USBH1_DIR__USBH1_DIR		0x1e5
-			MX51_PAD_USBH1_NXT__USBH1_NXT		0x1e5
-			MX51_PAD_USBH1_DATA0__USBH1_DATA0	0x1e5
-			MX51_PAD_USBH1_DATA1__USBH1_DATA1	0x1e5
-			MX51_PAD_USBH1_DATA2__USBH1_DATA2	0x1e5
-			MX51_PAD_USBH1_DATA3__USBH1_DATA3	0x1e5
-			MX51_PAD_USBH1_DATA4__USBH1_DATA4	0x1e5
-			MX51_PAD_USBH1_DATA5__USBH1_DATA5	0x1e5
-			MX51_PAD_USBH1_DATA6__USBH1_DATA6	0x1e5
-			MX51_PAD_USBH1_DATA7__USBH1_DATA7	0x1e5
-		>;
-	};
+&pinctrl_usbh1 {
+	/*
+	 * Overwrite upstream USBH1,2 iomux settings to match
+	 * the setting U-Boot would set these to. Remove this
+	 * once this is fixed upstream.
+	 */
+	fsl,pins = <
+		MX51_PAD_USBH1_STP__USBH1_STP		0x1e5
+		MX51_PAD_USBH1_CLK__USBH1_CLK		0x1e5
+		MX51_PAD_USBH1_DIR__USBH1_DIR		0x1e5
+		MX51_PAD_USBH1_NXT__USBH1_NXT		0x1e5
+		MX51_PAD_USBH1_DATA0__USBH1_DATA0	0x1e5
+		MX51_PAD_USBH1_DATA1__USBH1_DATA1	0x1e5
+		MX51_PAD_USBH1_DATA2__USBH1_DATA2	0x1e5
+		MX51_PAD_USBH1_DATA3__USBH1_DATA3	0x1e5
+		MX51_PAD_USBH1_DATA4__USBH1_DATA4	0x1e5
+		MX51_PAD_USBH1_DATA5__USBH1_DATA5	0x1e5
+		MX51_PAD_USBH1_DATA6__USBH1_DATA6	0x1e5
+		MX51_PAD_USBH1_DATA7__USBH1_DATA7	0x1e5
+	>;
+};
 
-	pinctrl_usbh2: usbh2grp {
-		fsl,pins = <
-			MX51_PAD_EIM_A26__USBH2_STP		0x1e5
-			MX51_PAD_EIM_A24__USBH2_CLK		0x1e5
-			MX51_PAD_EIM_A25__USBH2_DIR		0x1e5
-			MX51_PAD_EIM_A27__USBH2_NXT		0x1e5
-			MX51_PAD_EIM_D16__USBH2_DATA0		0x1e5
-			MX51_PAD_EIM_D17__USBH2_DATA1		0x1e5
-			MX51_PAD_EIM_D18__USBH2_DATA2		0x1e5
-			MX51_PAD_EIM_D19__USBH2_DATA3		0x1e5
-			MX51_PAD_EIM_D20__USBH2_DATA4		0x1e5
-			MX51_PAD_EIM_D21__USBH2_DATA5		0x1e5
-			MX51_PAD_EIM_D22__USBH2_DATA6		0x1e5
-			MX51_PAD_EIM_D23__USBH2_DATA7		0x1e5
-		>;
-	};
+&pinctrl_usbh2 {
+	fsl,pins = <
+		MX51_PAD_EIM_A26__USBH2_STP		0x1e5
+		MX51_PAD_EIM_A24__USBH2_CLK		0x1e5
+		MX51_PAD_EIM_A25__USBH2_DIR		0x1e5
+		MX51_PAD_EIM_A27__USBH2_NXT		0x1e5
+		MX51_PAD_EIM_D16__USBH2_DATA0		0x1e5
+		MX51_PAD_EIM_D17__USBH2_DATA1		0x1e5
+		MX51_PAD_EIM_D18__USBH2_DATA2		0x1e5
+		MX51_PAD_EIM_D19__USBH2_DATA3		0x1e5
+		MX51_PAD_EIM_D20__USBH2_DATA4		0x1e5
+		MX51_PAD_EIM_D21__USBH2_DATA5		0x1e5
+		MX51_PAD_EIM_D22__USBH2_DATA6		0x1e5
+		MX51_PAD_EIM_D23__USBH2_DATA7		0x1e5
+	>;
 };
diff --git a/arch/arm/dts/imx51-zii-scu2-mezz.dts b/arch/arm/dts/imx51-zii-scu2-mezz.dts
index 68a374bb2b..e44f7f999e 100644
--- a/arch/arm/dts/imx51-zii-scu2-mezz.dts
+++ b/arch/arm/dts/imx51-zii-scu2-mezz.dts
@@ -4,7 +4,7 @@
  * Copyright (C) 2018 Zodiac Inflight Innovations
  */
 
-#include <arm/imx51-zii-scu2-mezz.dts>
+#include <arm/nxp/imx/imx51-zii-scu2-mezz.dts>
 
 &iim {
 	barebox,provide-mac-address = <&fec 1 9>;
diff --git a/arch/arm/dts/imx51-zii-scu3-esb.dts b/arch/arm/dts/imx51-zii-scu3-esb.dts
index c83bf17316..a7cffb60a9 100644
--- a/arch/arm/dts/imx51-zii-scu3-esb.dts
+++ b/arch/arm/dts/imx51-zii-scu3-esb.dts
@@ -5,7 +5,7 @@
  */
 
 
-#include <arm/imx51-zii-scu3-esb.dts>
+#include <arm/nxp/imx/imx51-zii-scu3-esb.dts>
 
 &iim {
 	barebox,provide-mac-address = <&fec 1 9>;
diff --git a/arch/arm/dts/imx51.dtsi b/arch/arm/dts/imx51.dtsi
index 828a6c2e1b..521f182d20 100644
--- a/arch/arm/dts/imx51.dtsi
+++ b/arch/arm/dts/imx51.dtsi
@@ -3,4 +3,11 @@
 		pwm0 = &pwm1;
 		pwm1 = &pwm2;
 	};
+
+	chosen {
+		barebox,bootsource-mmc0 = &esdhc1;
+		barebox,bootsource-mmc1 = &esdhc2;
+		barebox,bootsource-mmc2 = &esdhc3;
+		barebox,bootsource-mmc3 = &esdhc4;
+	};
 };
diff --git a/arch/arm/dts/imx53-ccxmx53.dtsi b/arch/arm/dts/imx53-ccxmx53.dtsi
index d925ba44d7..6024785ff6 100644
--- a/arch/arm/dts/imx53-ccxmx53.dtsi
+++ b/arch/arm/dts/imx53-ccxmx53.dtsi
@@ -11,7 +11,7 @@
  */
 
 #include "imx53.dtsi"
-#include <arm/imx53.dtsi>
+#include <arm/nxp/imx/imx53.dtsi>
 
 
 / {
@@ -20,18 +20,11 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &nfc, "partname:environment";
+			device-path = &env_nand;
 		};
 	};
 };
 
-/ {
-	memory {
-		reg = <0x0 0x0>;
-	};
-
-};
-
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
@@ -236,7 +229,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_nand: partition@e0000 {
 		label = "environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx53-guf-vincell-lt.dts b/arch/arm/dts/imx53-guf-vincell-lt.dts
index d14c0dbf9c..a56a534653 100644
--- a/arch/arm/dts/imx53-guf-vincell-lt.dts
+++ b/arch/arm/dts/imx53-guf-vincell-lt.dts
@@ -13,7 +13,7 @@
 
 /dts-v1/;
 #include "imx53.dtsi"
-#include <arm/imx53.dtsi>
+#include <arm/nxp/imx/imx53.dtsi>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
diff --git a/arch/arm/dts/imx53-guf-vincell.dts b/arch/arm/dts/imx53-guf-vincell.dts
index a5f86ccf7e..f5922c2bf1 100644
--- a/arch/arm/dts/imx53-guf-vincell.dts
+++ b/arch/arm/dts/imx53-guf-vincell.dts
@@ -13,7 +13,7 @@
 
 /dts-v1/;
 #include "imx53.dtsi"
-#include <arm/imx53.dtsi>
+#include <arm/nxp/imx/imx53.dtsi>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
diff --git a/arch/arm/dts/imx53-mba53.dts b/arch/arm/dts/imx53-mba53.dts
index 53b98e30cf..02fdc6fdb3 100644
--- a/arch/arm/dts/imx53-mba53.dts
+++ b/arch/arm/dts/imx53-mba53.dts
@@ -10,7 +10,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx53-mba53.dts>
+#include <arm/nxp/imx/imx53-mba53.dts>
 #include "imx53-tqma53.dtsi"
 #include "imx53.dtsi"
 
@@ -20,7 +20,7 @@
 
 		environment-sd {
 			compatible = "barebox,environment";
-			device-path = &esdhc2, "partname:environment";
+			device-path = &env_sd2;
 			status = "disabled";
 		};
 	};
@@ -30,7 +30,7 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx53-qsb.dts b/arch/arm/dts/imx53-qsb.dts
index 773bc0b578..e035f4fcb9 100644
--- a/arch/arm/dts/imx53-qsb.dts
+++ b/arch/arm/dts/imx53-qsb.dts
@@ -10,6 +10,6 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx53-qsb.dts>
+#include <arm/nxp/imx/imx53-qsb.dts>
 #include "imx53.dtsi"
 #include "imx53-qsb-common.dtsi"
diff --git a/arch/arm/dts/imx53-qsrb.dts b/arch/arm/dts/imx53-qsrb.dts
index b3312786b1..358583ed07 100644
--- a/arch/arm/dts/imx53-qsrb.dts
+++ b/arch/arm/dts/imx53-qsrb.dts
@@ -10,6 +10,6 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx53-qsrb.dts>
+#include <arm/nxp/imx/imx53-qsrb.dts>
 #include "imx53.dtsi"
 #include "imx53-qsb-common.dtsi"
diff --git a/arch/arm/dts/imx53-tx53-1011.dts b/arch/arm/dts/imx53-tx53-1011.dts
index e9b1b3a221..9f2ad398bf 100644
--- a/arch/arm/dts/imx53-tx53-1011.dts
+++ b/arch/arm/dts/imx53-tx53-1011.dts
@@ -1,5 +1,5 @@
 /dts-v1/;
-#include <arm/imx53-tx53.dtsi>
+#include <arm/nxp/imx/imx53-tx53.dtsi>
 
 / {
 	model = "Ka-Ro electronics TX53 module";
diff --git a/arch/arm/dts/imx53-tx53-xx30.dts b/arch/arm/dts/imx53-tx53-xx30.dts
index b9d1c65a2a..cf0fface21 100644
--- a/arch/arm/dts/imx53-tx53-xx30.dts
+++ b/arch/arm/dts/imx53-tx53-xx30.dts
@@ -1,5 +1,5 @@
 /dts-v1/;
-#include <arm/imx53-tx53.dtsi>
+#include <arm/nxp/imx/imx53-tx53.dtsi>
 
 / {
 	model = "Ka-Ro electronics TX53 module";
diff --git a/arch/arm/dts/imx53-voipac-bsb.dts b/arch/arm/dts/imx53-voipac-bsb.dts
index 12ce592a47..316f662f27 100644
--- a/arch/arm/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/dts/imx53-voipac-bsb.dts
@@ -9,6 +9,6 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx53-voipac-bsb.dts>
+#include <arm/nxp/imx/imx53-voipac-bsb.dts>
 #include "imx53-voipac-dmm-668.dtsi"
 #include "imx53.dtsi"
diff --git a/arch/arm/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/dts/imx53-voipac-dmm-668.dtsi
index c4c17c2e8e..16ab865d68 100644
--- a/arch/arm/dts/imx53-voipac-dmm-668.dtsi
+++ b/arch/arm/dts/imx53-voipac-dmm-668.dtsi
@@ -4,7 +4,7 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &nfc, "partname:environment";
+			device-path = &env_nand;
 		};
 	};
 };
@@ -18,7 +18,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_nand: partition@e0000 {
 		label = "environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index 96fdd73ed0..0fd05f9b51 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -4,4 +4,11 @@
 		pwm1 = &pwm2;
 		ipu0 = &ipu;
 	};
+
+	chosen {
+		barebox,bootsource-mmc0 = &esdhc1;
+		barebox,bootsource-mmc1 = &esdhc2;
+		barebox,bootsource-mmc2 = &esdhc3;
+		barebox,bootsource-mmc3 = &esdhc4;
+	};
 };
diff --git a/arch/arm/dts/imx6dl-advantech-rom-7421.dts b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
index f0e3f4aa1f..9a1f3a2bf8 100755
--- a/arch/arm/dts/imx6dl-advantech-rom-7421.dts
+++ b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
@@ -12,7 +12,7 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 
 / {
@@ -24,19 +24,19 @@
 
 		environment-sd2 {			/* Micro SD */
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 			status = "disabled";
 		};
 
 		environment-sd4 {			/* eMMC */
 			compatible = "barebox,environment";
-			device-path = &usdhc4, "partname:barebox-environment";
+			device-path = &env_sd4;
 			status = "disabled";
 		};
 
 		environment-spi {			/* spi nor */
 			compatible = "barebox,environment";
-			device-path = &ecspi1, "partname:barebox-environment";
+			device-path = &env_nor;
 			status = "disabled";
 		};
 	};
@@ -63,7 +63,7 @@
 			reg = <0x0 0xe0000>;
 		};
 
-		partition@e0000 {
+		env_nor: partition@e0000 {
 			label = "barebox-environment";
 			reg = <0xe0000 0x20000>;
 		};
@@ -115,7 +115,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
@@ -147,7 +147,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd4: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6dl-alti6p.dts b/arch/arm/dts/imx6dl-alti6p.dts
index 04a6368f93..93ff66ee9c 100644
--- a/arch/arm/dts/imx6dl-alti6p.dts
+++ b/arch/arm/dts/imx6dl-alti6p.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6dl-alti6p.dts>
+#include <arm/nxp/imx/imx6dl-alti6p.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6dl-cm-fx6.dts b/arch/arm/dts/imx6dl-cm-fx6.dts
index cc426e2a3c..202f4db7d6 100644
--- a/arch/arm/dts/imx6dl-cm-fx6.dts
+++ b/arch/arm/dts/imx6dl-cm-fx6.dts
@@ -12,7 +12,7 @@
  */
 
 /dts-v1/;
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-cm-fx6.dtsi"
 
diff --git a/arch/arm/dts/imx6dl-dfi-fs700-m60-6s.dts b/arch/arm/dts/imx6dl-dfi-fs700-m60-6s.dts
index b6df37f373..b766611279 100644
--- a/arch/arm/dts/imx6dl-dfi-fs700-m60-6s.dts
+++ b/arch/arm/dts/imx6dl-dfi-fs700-m60-6s.dts
@@ -14,7 +14,7 @@
 /dts-v1/;
 #endif
 
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-dfi-fs700-m60.dtsi"
 
diff --git a/arch/arm/dts/imx6dl-eltec-hipercam.dts b/arch/arm/dts/imx6dl-eltec-hipercam.dts
index ce2af4051c..ff13c6679c 100644
--- a/arch/arm/dts/imx6dl-eltec-hipercam.dts
+++ b/arch/arm/dts/imx6dl-eltec-hipercam.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6dl-hummingboard.dts b/arch/arm/dts/imx6dl-hummingboard.dts
index 5bfa4704b2..a0e8ac84c6 100644
--- a/arch/arm/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/dts/imx6dl-hummingboard.dts
@@ -5,7 +5,7 @@
  * License version 2.
  */
 
-#include <arm/imx6dl-hummingboard.dts>
+#include <arm/nxp/imx/imx6dl-hummingboard.dts>
 #include "imx6qdl.dtsi"
 
 / {
@@ -14,7 +14,7 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 		};
 	};
 };
@@ -32,7 +32,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6dl-hummingboard2.dts b/arch/arm/dts/imx6dl-hummingboard2.dts
index 40ef174411..c8ac4cb8eb 100644
--- a/arch/arm/dts/imx6dl-hummingboard2.dts
+++ b/arch/arm/dts/imx6dl-hummingboard2.dts
@@ -43,7 +43,7 @@
  */
 /dts-v1/;
 
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6qdl-hummingboard2.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6dl-lanmcu.dts b/arch/arm/dts/imx6dl-lanmcu.dts
index 1a1fbad326..4780985da0 100644
--- a/arch/arm/dts/imx6dl-lanmcu.dts
+++ b/arch/arm/dts/imx6dl-lanmcu.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6dl-lanmcu.dts>
+#include <arm/nxp/imx/imx6dl-lanmcu.dts>
 #include "imx6qdl-prti6q-emmc.dtsi"
diff --git a/arch/arm/dts/imx6dl-mba6x.dts b/arch/arm/dts/imx6dl-mba6x.dts
index dddc3d384c..612acba323 100644
--- a/arch/arm/dts/imx6dl-mba6x.dts
+++ b/arch/arm/dts/imx6dl-mba6x.dts
@@ -27,6 +27,19 @@
 	};
 };
 
+&flash {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x80000>;
+		};
+	};
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
diff --git a/arch/arm/dts/imx6dl-nitrogen6x.dts b/arch/arm/dts/imx6dl-nitrogen6x.dts
index bc199c3167..7607090876 100644
--- a/arch/arm/dts/imx6dl-nitrogen6x.dts
+++ b/arch/arm/dts/imx6dl-nitrogen6x.dts
@@ -11,6 +11,6 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6dl-nitrogen6x.dts>
+#include <arm/nxp/imx/imx6dl-nitrogen6x.dts>
 #include "imx6dl.dtsi"
 #include "imx6qdl-nitrogen6x.dtsi"
diff --git a/arch/arm/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi
index d951c0bb8d..97586906af 100644
--- a/arch/arm/dts/imx6dl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-phytec-pfla02.dtsi"
 
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index 03df77f41d..133b75f5a7 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
index 0ef6f96bbe..7bb6acb556 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
index 0a4c2e6fb6..6add672644 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
index fa518286c3..ddecfbc2b2 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
diff --git a/arch/arm/dts/imx6dl-plybas.dts b/arch/arm/dts/imx6dl-plybas.dts
index b0e1595a41..20ff7fdf13 100644
--- a/arch/arm/dts/imx6dl-plybas.dts
+++ b/arch/arm/dts/imx6dl-plybas.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6dl-plybas.dts>
+#include <arm/nxp/imx/imx6dl-plybas.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6dl-plym2m.dts b/arch/arm/dts/imx6dl-plym2m.dts
index bf29fc1bce..e1ae8d48b7 100644
--- a/arch/arm/dts/imx6dl-plym2m.dts
+++ b/arch/arm/dts/imx6dl-plym2m.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6dl-plym2m.dts>
+#include <arm/nxp/imx/imx6dl-plym2m.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6dl-prtmvt.dts b/arch/arm/dts/imx6dl-prtmvt.dts
index 64e2f90110..6c49bbf606 100644
--- a/arch/arm/dts/imx6dl-prtmvt.dts
+++ b/arch/arm/dts/imx6dl-prtmvt.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6dl-prtmvt.dts>
+#include <arm/nxp/imx/imx6dl-prtmvt.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6dl-prtrvt.dts b/arch/arm/dts/imx6dl-prtrvt.dts
index e0d9261d27..ee97fa8a65 100644
--- a/arch/arm/dts/imx6dl-prtrvt.dts
+++ b/arch/arm/dts/imx6dl-prtrvt.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6dl-prtrvt.dts>
+#include <arm/nxp/imx/imx6dl-prtrvt.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6dl-prtvt7.dts b/arch/arm/dts/imx6dl-prtvt7.dts
index b1fd13bdd7..a9e0589c2c 100644
--- a/arch/arm/dts/imx6dl-prtvt7.dts
+++ b/arch/arm/dts/imx6dl-prtvt7.dts
@@ -1,5 +1,18 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6dl-prtvt7.dts>
+#include <arm/nxp/imx/imx6dl-prtvt7.dts>
 #include "imx6qdl-prti6q-emmc.dtsi"
+
+&state_emmc {
+	magic = <0x72766467>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	brand@1b0 {
+		reg = <0x1b0 0x4>;
+		type = "enum32";
+		names = "unbranded", "agco", "vermeer";
+		default = <0>;
+	};
+};
diff --git a/arch/arm/dts/imx6dl-sabrelite.dts b/arch/arm/dts/imx6dl-sabrelite.dts
index 849bcdd61a..051100ef42 100644
--- a/arch/arm/dts/imx6dl-sabrelite.dts
+++ b/arch/arm/dts/imx6dl-sabrelite.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-sabrelite.dtsi"
 
diff --git a/arch/arm/dts/imx6dl-sabresd.dts b/arch/arm/dts/imx6dl-sabresd.dts
new file mode 100644
index 0000000000..6de132a64e
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sabresd.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <arm/nxp/imx/imx6dl-sabresd.dts>
+
+/ {
+	model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
+	compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+
+	chosen {
+		stdout-path = &uart1;
+
+		environment {
+			compatible = "barebox,environment";
+			device-path = &environment_usdhc3;
+		};
+	};
+};
+
+&usdhc3 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	environment_usdhc3: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
diff --git a/arch/arm/dts/imx6dl-samx6i.dts b/arch/arm/dts/imx6dl-samx6i.dts
index da648ef5b8..5a752296d0 100644
--- a/arch/arm/dts/imx6dl-samx6i.dts
+++ b/arch/arm/dts/imx6dl-samx6i.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <arm/imx6dl-kontron-samx6i.dtsi>
+#include <arm/nxp/imx/imx6dl-kontron-samx6i.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-smarc-samx6i.dtsi"
 
diff --git a/arch/arm/dts/imx6dl-skov-imx6.dts b/arch/arm/dts/imx6dl-skov-imx6.dts
index c2dac68204..304068cbdb 100644
--- a/arch/arm/dts/imx6dl-skov-imx6.dts
+++ b/arch/arm/dts/imx6dl-skov-imx6.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-skov-imx6.dtsi"
 
diff --git a/arch/arm/dts/imx6dl-tqma6s.dtsi b/arch/arm/dts/imx6dl-tqma6s.dtsi
index 63459ce7ea..13754a6790 100644
--- a/arch/arm/dts/imx6dl-tqma6s.dtsi
+++ b/arch/arm/dts/imx6dl-tqma6s.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-tqma6x.dtsi"
 
diff --git a/arch/arm/dts/imx6dl-tx6u.dts b/arch/arm/dts/imx6dl-tx6u.dts
index 6c26feb978..a41773780c 100644
--- a/arch/arm/dts/imx6dl-tx6u.dts
+++ b/arch/arm/dts/imx6dl-tx6u.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-#include <arm/imx6dl.dtsi>
-#include <arm/imx6qdl-tx6.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6qdl-tx6.dtsi>
 #include "imx6qdl.dtsi"
 #include "imx6qdl-tx6x.dtsi"
 
diff --git a/arch/arm/dts/imx6dl-victgo.dts b/arch/arm/dts/imx6dl-victgo.dts
index 250cd761d4..e3bbda5632 100644
--- a/arch/arm/dts/imx6dl-victgo.dts
+++ b/arch/arm/dts/imx6dl-victgo.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6dl-victgo.dts>
+#include <arm/nxp/imx/imx6dl-victgo.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6dl-vicut1.dts b/arch/arm/dts/imx6dl-vicut1.dts
index 99cc7af2e6..4a2965518c 100644
--- a/arch/arm/dts/imx6dl-vicut1.dts
+++ b/arch/arm/dts/imx6dl-vicut1.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6dl-vicut1.dts>
+#include <arm/nxp/imx/imx6dl-vicut1.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6dl-wandboard.dts b/arch/arm/dts/imx6dl-wandboard.dts
index c4695fb8d8..e8d4a90032 100644
--- a/arch/arm/dts/imx6dl-wandboard.dts
+++ b/arch/arm/dts/imx6dl-wandboard.dts
@@ -1,4 +1,4 @@
-#include <arm/imx6dl-wandboard.dts>
+#include <arm/nxp/imx/imx6dl-wandboard.dts>
 #include <dt-bindings/gpio/gpio.h>
 #include "imx6dl.dtsi"
 
diff --git a/arch/arm/dts/imx6q-cm-fx6.dts b/arch/arm/dts/imx6q-cm-fx6.dts
index aaaa7189d8..d661c074dd 100644
--- a/arch/arm/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/dts/imx6q-cm-fx6.dts
@@ -12,7 +12,7 @@
  */
 
 /dts-v1/;
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6qdl-cm-fx6.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6q-dfi-fs700-m60-6q.dts b/arch/arm/dts/imx6q-dfi-fs700-m60-6q.dts
index 8ecd667e9e..58927097cd 100644
--- a/arch/arm/dts/imx6q-dfi-fs700-m60-6q.dts
+++ b/arch/arm/dts/imx6q-dfi-fs700-m60-6q.dts
@@ -14,7 +14,7 @@
 /dts-v1/;
 #endif
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-dfi-fs700-m60.dtsi"
 
diff --git a/arch/arm/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/dts/imx6q-dmo-edmqmx6.dts
index 2b9097c482..1280837db6 100644
--- a/arch/arm/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/dts/imx6q-dmo-edmqmx6.dts
@@ -11,7 +11,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6q-dmo-edmqmx6.dts>
+#include <arm/nxp/imx/imx6q-dmo-edmqmx6.dts>
 
 / {
 	chosen {
@@ -19,47 +19,36 @@
 
 		environment-sd {
 			compatible = "barebox,environment";
-			device-path = &usdhc3, "partname:barebox-environment";
+			device-path = &env_sd3;
 			status = "disabled";
 		};
 
 		environment-emmc {
 			compatible = "barebox,environment";
-			device-path = &usdhc4, "partname:barebox-environment";
+			device-path = &env_sd4;
 			status = "disabled";
 		};
 
 		environment-spi {
 			compatible = "barebox,environment";
-			device-path = &flash, "partname:barebox-environment";
+			device-path = &env_nor;
 			status = "disabled";
 		};
 	};
 };
 
-&ecspi5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi_5_1>;
-	fsl,spi-num-chipselects = <1>;
-	cs-gpios = <&gpio1 12 0>;
-	status = "okay";
-
-	flash: m25p80@0 {
-		compatible = "m25p80";
-		spi-max-frequency = <40000000>;
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		partition@0 {
-			label = "barebox";
-			reg = <0x0 0xe0000>;
-		};
+&flash {
+	#address-cells = <1>;
+	#size-cells = <1>;
 
-		partition@e0000 {
-			label = "barebox-environment";
-			reg = <0xe0000 0x20000>;
-		};
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	env_nor: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
 	};
 };
 
@@ -71,17 +60,6 @@
 			>;
 		};
 	};
-
-	ecspi5 {
-		pinctrl_ecspi_5_1: ecspi5rp-1 {
-			fsl,pins = <
-				MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
-				MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI  0x80000000
-				MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK  0x80000000
-				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12  0x80000000
-			>;
-		};
-	};
 };
 
 &i2c2 {
@@ -99,7 +77,8 @@
 		label = "barebox";
 		reg = <0x0 0xe0000>;
 	};
-	partition@e0000 {
+
+	env_sd3: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
@@ -113,7 +92,8 @@
 		label = "barebox";
 		reg = <0x0 0xe0000>;
 	};
-	partition@e0000 {
+
+	env_sd4: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6q-embedsky-e9.dts b/arch/arm/dts/imx6q-embedsky-e9.dts
index 76c940b709..7ab2b22e95 100644
--- a/arch/arm/dts/imx6q-embedsky-e9.dts
+++ b/arch/arm/dts/imx6q-embedsky-e9.dts
@@ -12,7 +12,7 @@
 
 /dts-v1/;
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6q-embedsky-e9.dtsi"
 
diff --git a/arch/arm/dts/imx6q-gk802.dts b/arch/arm/dts/imx6q-gk802.dts
index 310d6f0f5e..d40f503936 100644
--- a/arch/arm/dts/imx6q-gk802.dts
+++ b/arch/arm/dts/imx6q-gk802.dts
@@ -6,7 +6,7 @@
  * kind, whether express or implied.
  */
 
-#include <arm/imx6q-gk802.dts>
+#include <arm/nxp/imx/imx6q-gk802.dts>
 #include "imx6q.dtsi"
 
 /* External USB-A port (USBOTG) */
diff --git a/arch/arm/dts/imx6q-guf-santaro.dts b/arch/arm/dts/imx6q-guf-santaro.dts
index e72aacc59b..96ea1dda3b 100644
--- a/arch/arm/dts/imx6q-guf-santaro.dts
+++ b/arch/arm/dts/imx6q-guf-santaro.dts
@@ -13,7 +13,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6q-gw54xx.dts b/arch/arm/dts/imx6q-gw54xx.dts
index ec0f3632ba..316fe3790f 100644
--- a/arch/arm/dts/imx6q-gw54xx.dts
+++ b/arch/arm/dts/imx6q-gw54xx.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-gw54xx.dtsi"
 
diff --git a/arch/arm/dts/imx6q-h100.dts b/arch/arm/dts/imx6q-h100.dts
index bfee186f28..7fda9f1222 100644
--- a/arch/arm/dts/imx6q-h100.dts
+++ b/arch/arm/dts/imx6q-h100.dts
@@ -39,13 +39,13 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <arm/imx6q-h100.dts>
+#include <arm/nxp/imx/imx6q-h100.dts>
 
 / {
 	chosen {
 		environment {
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 		};
 	};
 };
@@ -63,7 +63,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6q-hummingboard.dts b/arch/arm/dts/imx6q-hummingboard.dts
index b10acf2cbb..0bb4a6b48e 100644
--- a/arch/arm/dts/imx6q-hummingboard.dts
+++ b/arch/arm/dts/imx6q-hummingboard.dts
@@ -5,7 +5,7 @@
  * License version 2.
  */
 
-#include <arm/imx6q-hummingboard.dts>
+#include <arm/nxp/imx/imx6q-hummingboard.dts>
 #include "imx6qdl.dtsi"
 
 / {
@@ -14,7 +14,7 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 		};
 	};
 };
@@ -32,7 +32,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6q-hummingboard2.dts b/arch/arm/dts/imx6q-hummingboard2.dts
index 6c41ab7396..6ef7f935e3 100644
--- a/arch/arm/dts/imx6q-hummingboard2.dts
+++ b/arch/arm/dts/imx6q-hummingboard2.dts
@@ -43,7 +43,7 @@
  */
 /dts-v1/;
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6qdl-hummingboard2.dtsi"
 #include "imx6q.dtsi"
 
@@ -54,7 +54,7 @@
 	chosen {
 		environment {
 			compatible = "barebox,environment";
-			device-path = &usdhc3, "partname:barebox-environment";
+			device-path = &env_sd3;
 		};
 	};
 };
@@ -80,7 +80,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd3: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6q-marsboard.dts b/arch/arm/dts/imx6q-marsboard.dts
index 1d9f8f005d..b6fce7c898 100644
--- a/arch/arm/dts/imx6q-marsboard.dts
+++ b/arch/arm/dts/imx6q-marsboard.dts
@@ -3,7 +3,7 @@
  * Copyright (C) 2019 Ahmad Fatoum - Pengutronix
  */
 
-#include <arm/imx6q-marsboard.dts>
+#include <arm/nxp/imx/imx6q-marsboard.dts>
 #include "imx6q.dtsi"
 
 / {
@@ -18,7 +18,7 @@
 };
 
 &ecspi1 {
-	m25p80@0 {
+	flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
@@ -36,6 +36,11 @@
 
 &fec {
 	phy-reset-duration = <2>;
+	phy-mode = "rgmii-id";
+};
+
+&rgmii_phy {
+	qca,clk-out-frequency = <125000000>;
 };
 
 &ocotp {
diff --git a/arch/arm/dts/imx6q-mba6x.dts b/arch/arm/dts/imx6q-mba6x.dts
index 64635b9582..5154580fae 100644
--- a/arch/arm/dts/imx6q-mba6x.dts
+++ b/arch/arm/dts/imx6q-mba6x.dts
@@ -27,6 +27,19 @@
 	};
 };
 
+&flash {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x80000>;
+		};
+	};
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
diff --git a/arch/arm/dts/imx6q-nitrogen6x.dts b/arch/arm/dts/imx6q-nitrogen6x.dts
index 14f7ba2190..294b9d8ce2 100644
--- a/arch/arm/dts/imx6q-nitrogen6x.dts
+++ b/arch/arm/dts/imx6q-nitrogen6x.dts
@@ -11,7 +11,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6q-nitrogen6x.dts>
+#include <arm/nxp/imx/imx6q-nitrogen6x.dts>
 #include "imx6q.dtsi"
 #include "imx6qdl-nitrogen6x.dtsi"
 
diff --git a/arch/arm/dts/imx6q-novena.dts b/arch/arm/dts/imx6q-novena.dts
new file mode 100644
index 0000000000..554b66fb5a
--- /dev/null
+++ b/arch/arm/dts/imx6q-novena.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR X11
+// SPDX-FileCopyrightText: 2023 John Watts <contact@jookia.org>
+
+#include <arm/nxp/imx/imx6q-novena.dts>
+
+/ {
+	aliases {
+		eeprom0 = &eeprom;
+	};
+};
+
+&i2c3 {
+	eeprom: eeprom@56 {
+		compatible = "24c512";
+		reg = <0x56>;
+		pagesize = <128>;
+	};
+};
diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
index 48f1da3cad..10e2c9dc11 100644
--- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-phytec-pfla02.dtsi"
 
diff --git a/arch/arm/dts/imx6q-phytec-phycard.dts b/arch/arm/dts/imx6q-phytec-phycard.dts
index b0e47e9b62..0fbd62af7b 100644
--- a/arch/arm/dts/imx6q-phytec-phycard.dts
+++ b/arch/arm/dts/imx6q-phytec-phycard.dts
@@ -10,7 +10,7 @@
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-phytec-phycard-som.dtsi"
 
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
index 2414befd35..167d68cc8c 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
index 864dc190bc..188197d5b6 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
diff --git a/arch/arm/dts/imx6q-prti6q.dts b/arch/arm/dts/imx6q-prti6q.dts
index 71606b892c..caf1ea746d 100644
--- a/arch/arm/dts/imx6q-prti6q.dts
+++ b/arch/arm/dts/imx6q-prti6q.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6q-prti6q.dts>
+#include <arm/nxp/imx/imx6q-prti6q.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6q-prtwd2.dts b/arch/arm/dts/imx6q-prtwd2.dts
index 78ea4bc15c..a2315f6e2c 100644
--- a/arch/arm/dts/imx6q-prtwd2.dts
+++ b/arch/arm/dts/imx6q-prtwd2.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6q-prtwd2.dts>
+#include <arm/nxp/imx/imx6q-prtwd2.dts>
 #include "imx6qdl-prti6q-emmc.dtsi"
diff --git a/arch/arm/dts/imx6q-sabrelite.dts b/arch/arm/dts/imx6q-sabrelite.dts
index b6d1c09b77..74060f3e79 100644
--- a/arch/arm/dts/imx6q-sabrelite.dts
+++ b/arch/arm/dts/imx6q-sabrelite.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-sabrelite.dtsi"
 
diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts
index 21180df324..c4456e322e 100644
--- a/arch/arm/dts/imx6q-sabresd.dts
+++ b/arch/arm/dts/imx6q-sabresd.dts
@@ -12,7 +12,7 @@
 
 /dts-v1/;
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-sabresd.dtsi"
 
diff --git a/arch/arm/dts/imx6q-samx6i.dts b/arch/arm/dts/imx6q-samx6i.dts
index a2ea076edf..6069db4397 100644
--- a/arch/arm/dts/imx6q-samx6i.dts
+++ b/arch/arm/dts/imx6q-samx6i.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <arm/imx6q-kontron-samx6i.dtsi>
+#include <arm/nxp/imx/imx6q-kontron-samx6i.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-smarc-samx6i.dtsi"
 
diff --git a/arch/arm/dts/imx6q-skov-imx6.dts b/arch/arm/dts/imx6q-skov-imx6.dts
index fea84cb498..7a2063a416 100644
--- a/arch/arm/dts/imx6q-skov-imx6.dts
+++ b/arch/arm/dts/imx6q-skov-imx6.dts
@@ -10,17 +10,13 @@
  */
 
 /dts-v1/;
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-skov-imx6.dtsi"
 
 / {
 	model = "Skov IMX6";
 	compatible = "skov,imx6", "fsl,imx6q";
-
-	chosen {
-		stdout-path = &uart2;
-	};
 };
 
 &i2c2 {
diff --git a/arch/arm/dts/imx6q-tqma6q.dtsi b/arch/arm/dts/imx6q-tqma6q.dtsi
index c2382b07db..cdb486cdff 100644
--- a/arch/arm/dts/imx6q-tqma6q.dtsi
+++ b/arch/arm/dts/imx6q-tqma6q.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-tqma6x.dtsi"
 
diff --git a/arch/arm/dts/imx6q-tx6q.dts b/arch/arm/dts/imx6q-tx6q.dts
index 6063dd4fe5..b5602fa4fd 100644
--- a/arch/arm/dts/imx6q-tx6q.dts
+++ b/arch/arm/dts/imx6q-tx6q.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-#include <arm/imx6q.dtsi>
-#include <arm/imx6qdl-tx6.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
+#include <arm/nxp/imx/imx6qdl-tx6.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-tx6x.dtsi"
 
diff --git a/arch/arm/dts/imx6q-udoo.dts b/arch/arm/dts/imx6q-udoo.dts
index c8a12a38dd..1d2b05c19e 100644
--- a/arch/arm/dts/imx6q-udoo.dts
+++ b/arch/arm/dts/imx6q-udoo.dts
@@ -13,7 +13,7 @@
 
 /dts-v1/;
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-udoo.dtsi"
 
diff --git a/arch/arm/dts/imx6q-utilite.dts b/arch/arm/dts/imx6q-utilite.dts
index 14b65d64a7..79465975d1 100644
--- a/arch/arm/dts/imx6q-utilite.dts
+++ b/arch/arm/dts/imx6q-utilite.dts
@@ -1,5 +1,5 @@
 /dts-v1/;
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6qdl-cm-fx6.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6q-var-custom.dts b/arch/arm/dts/imx6q-var-custom.dts
index ddb220fb0a..cbfe4da7e1 100644
--- a/arch/arm/dts/imx6q-var-custom.dts
+++ b/arch/arm/dts/imx6q-var-custom.dts
@@ -83,7 +83,7 @@
 		fsl,data-width = <24>;
 		status = "okay";
 		display-timings {
-			native-mode = &claawvga;
+			native-mode = <&claawvga>;
 			claawvga: claawvga {
 				native-mode;
 				clock-frequency = <35714000>;
diff --git a/arch/arm/dts/imx6q-var-som.dtsi b/arch/arm/dts/imx6q-var-som.dtsi
index 7dbaa1e3d4..6dc6c51f84 100644
--- a/arch/arm/dts/imx6q-var-som.dtsi
+++ b/arch/arm/dts/imx6q-var-som.dtsi
@@ -10,7 +10,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6q-vicut1.dts b/arch/arm/dts/imx6q-vicut1.dts
index 61fb56d401..cd882b0ed1 100644
--- a/arch/arm/dts/imx6q-vicut1.dts
+++ b/arch/arm/dts/imx6q-vicut1.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6q-vicut1.dts>
+#include <arm/nxp/imx/imx6q-vicut1.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6q-wandboard.dts b/arch/arm/dts/imx6q-wandboard.dts
index d182faf217..2cbaa8d830 100644
--- a/arch/arm/dts/imx6q-wandboard.dts
+++ b/arch/arm/dts/imx6q-wandboard.dts
@@ -1,4 +1,4 @@
-#include <arm/imx6q-wandboard.dts>
+#include <arm/nxp/imx/imx6q-wandboard.dts>
 #include <dt-bindings/gpio/gpio.h>
 #include "imx6q.dtsi"
 
diff --git a/arch/arm/dts/imx6q-zii-rdu2.dts b/arch/arm/dts/imx6q-zii-rdu2.dts
index db75e29f87..dadba5be37 100644
--- a/arch/arm/dts/imx6q-zii-rdu2.dts
+++ b/arch/arm/dts/imx6q-zii-rdu2.dts
@@ -42,7 +42,7 @@
 
 /dts-v1/;
 
-#include <arm/imx6q.dtsi>
+#include <arm/nxp/imx/imx6q.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-zii-rdu2.dtsi"
 
diff --git a/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi
index 73878cde0d..3ce8d0a534 100644
--- a/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi
+++ b/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -1,4 +1,4 @@
-#include <arm/imx6qdl-dfi-fs700-m60.dtsi>
+#include <arm/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi
index 23e08f7d92..569d2cbffe 100644
--- a/arch/arm/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
- #include <arm/imx6qdl-gw54xx.dtsi>
+ #include <arm/nxp/imx/imx6qdl-gw54xx.dtsi>
 
  / {
 	chosen {
@@ -17,7 +17,7 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &gpmi, "partname:barebox-environment";
+			device-path = &env_nand;
 		};
 	};
 };
@@ -31,7 +31,7 @@
 		reg = <0x0 0x400000>;
 	};
 
-	partition@400000 {
+	env_nand: partition@400000 {
 		label = "barebox-environment";
 		reg = <0x400000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/dts/imx6qdl-hummingboard2.dtsi
index 6f37d5afa5..7da33306c6 100644
--- a/arch/arm/dts/imx6qdl-hummingboard2.dtsi
+++ b/arch/arm/dts/imx6qdl-hummingboard2.dtsi
@@ -40,7 +40,7 @@
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
-#include <arm/imx6qdl-sr-som.dtsi>
+#include <arm/nxp/imx/imx6qdl-sr-som.dtsi>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/dts/imx6qdl-nitrogen6_max.dtsi
index 19fe7881b3..0f6d17ad6c 100644
--- a/arch/arm/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/dts/imx6qdl-nitrogen6_max.dtsi
@@ -39,12 +39,12 @@
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
- 
+
 / {
 	chosen {
 		environment {
 			compatible = "barebox,environment";
-			device-path = &flash, "partname:barebox-environment";
+			device-path = &env_nor;
 		};
 	};
 };
@@ -58,7 +58,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_nor: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
@@ -66,4 +66,4 @@
 
 &ocotp {
 	barebox,provide-mac-address = <&fec 0x620>;
-};
\ No newline at end of file
+};
diff --git a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi
index 5c43b16ab1..4411e89ded 100644
--- a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi
@@ -10,7 +10,7 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
-#include <arm/imx6qdl-nitrogen6x.dtsi>
+#include <arm/nxp/imx/imx6qdl-nitrogen6x.dtsi>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
@@ -18,7 +18,7 @@
 	chosen {
 		environment {
 			compatible = "barebox,environment";
-			device-path = &flash, "partname:barebox-environment";
+			device-path = &env_nor;
 		};
 	};
 };
@@ -35,7 +35,7 @@
 	/delete-node/ partition@c0000;
 	/delete-node/ partition@c2000;
 
-	partition@e0000 {
+	env_nor: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/dts/imx6qdl-phytec-mira.dtsi
index 49cbd25fc3..bcda7dd82a 100644
--- a/arch/arm/dts/imx6qdl-phytec-mira.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-mira.dtsi
@@ -4,7 +4,7 @@
  * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
  */
 
-#include <arm/imx6qdl-phytec-mira.dtsi>
+#include <arm/nxp/imx/imx6qdl-phytec-mira.dtsi>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -36,7 +36,7 @@
                         reg = <0x0 0xe0000>;
                 };
 
-                partition@e0000 {
+                env_sd1: partition@e0000 {
                         label = "barebox-environment";
                         reg = <0xe0000 0x20000>;
                 };
diff --git a/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi
index 991c7e4fab..7d5b3bae05 100644
--- a/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi
@@ -9,12 +9,16 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6qdl-phytec-pbab01.dtsi>
+#include <arm/nxp/imx/imx6qdl-phytec-pbab01.dtsi>
 
 &uart1 {
 	status = "okay";
 };
 
+&usbotg {
+	dr_mode = "otg";
+};
+
 #ifdef USE_STATE_EXAMPLE
 #include "state-example.dtsi"
 #endif
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index 0653fcc3c3..56b42cd1ef 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -9,43 +9,25 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6qdl-phytec-pfla02.dtsi>
+#include <arm/nxp/imx/imx6qdl-phytec-pfla02.dtsi>
 
 / {
 	chosen {
 		environment-nand {
 			compatible = "barebox,environment";
-			device-path = &gpmi, "partname:barebox-environment";
+			device-path = &env_nand;
 			status = "disabled";
 		};
 
 		environment-spinor {
 			compatible = "barebox,environment";
-			device-path = &som_flash, "partname:barebox-environment";
-			status = "disabled";
-		};
-
-		environment-sd1 {
-			compatible = "barebox,environment";
-			device-path = &usdhc1, "partname:barebox-environment";
-			status = "disabled";
-		};
-
-		environment-sd2 {
-			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_nor;
 			status = "disabled";
 		};
 
 		environment-sd3 {
 			compatible = "barebox,environment";
-			device-path = &usdhc3, "partname:barebox-environment";
-			status = "disabled";
-		};
-
-		environment-sd4 {
-			compatible = "barebox,environment";
-			device-path = &usdhc4, "partname:barebox-environment";
+			device-path = &env_sd3;
 			status = "disabled";
 		};
 	};
@@ -64,7 +46,7 @@
 			reg = <0x0 0x100000>;
 		};
 
-		partition@100000 {
+		env_nor: partition@100000 {
 			label = "barebox-environment";
 			reg = <0x100000 0x20000>;
 		};
@@ -81,15 +63,6 @@
 	};
 };
 
-&fec {
-	/*
-	 * barebox doesn't have a driver for the PMIC providing the phy-supply
-	 * (dlg,da9063). So remove the phy-supply property and rely on the
-	 * PMIC's reset default which has this supply enabled.
-	 */
-	/delete-property/ phy-supply;
-};
-
 &gpmi {
 	partitions {
 		compatible = "fixed-partitions";
@@ -101,7 +74,7 @@
 			reg = <0x0 0x1000000>;
 		};
 
-		partition@1000000 {
+		env_nand: partition@1000000 {
 			label = "barebox-environment";
 			reg = <0x1000000 0x100000>;
 		};
@@ -147,7 +120,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd3: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
@@ -162,5 +135,8 @@
 		watchdog-priority = <500>;
 		restart-priority = <500>;
 		reset-source-priority = <500>;
+		regulators {
+			barebox,allow-dummy-supply;
+		};
 	};
 };
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index 2c333ce8fe..c66a6a529d 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -4,32 +4,32 @@
  * Author: Christian Hemp <c.hemp@phytec.de>
  */
 
-#include <arm/imx6qdl-phytec-phycore-som.dtsi>
+#include <arm/nxp/imx/imx6qdl-phytec-phycore-som.dtsi>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
 	chosen {
 		environment-sd1 {
 			compatible = "barebox,environment";
-			device-path = &usdhc1, "partname:barebox-environment";
+			device-path = &env_sd1;
 			status = "disabled";
 		};
 
 		environment-sd4 {
 			compatible = "barebox,environment";
-			device-path = &usdhc4, "partname:barebox-environment";
+			device-path = &env_sd4;
 			status = "disabled";
 		};
 
 		environment-nand {
 			compatible = "barebox,environment";
-			device-path = &gpmi, "partname:barebox-environment";
+			device-path = &env_nand;
 			status = "disabled";
 		};
 
 		environment-spinor {
 			compatible = "barebox,environment";
-			device-path = &m25p80, "partname:barebox-environment";
+			device-path = &env_nor;
 			status = "disabled";
 		};
 	};
@@ -53,7 +53,7 @@
 			reg = <0x0 0x1000000>;
 		};
 
-		partition@400000 {
+		env_nand: partition@400000 {
 			label = "barebox-environment";
 			reg = <0x1000000 0x100000>;
 		};
@@ -90,7 +90,7 @@
 			reg = <0x0 0x100000>;
 		};
 
-		partition@100000 {
+		env_nor: partition@100000 {
 			label = "barebox-environment";
 			reg = <0x100000 0x20000>;
 		};
@@ -122,7 +122,7 @@
 			reg = <0x0 0xe0000>;
 		};
 
-		partition@e0000 {
+		env_sd4: partition@e0000 {
 			label = "barebox-environment";
 			reg = <0xe0000 0x20000>;
 		};
diff --git a/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi b/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi
index 4fc7bd6473..c9c75a9ade 100644
--- a/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi
+++ b/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi
@@ -1,23 +1,78 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
 / {
+	aliases {
+		state = &state_emmc;
+	};
+
 	chosen {
 		stdout-path = &uart4;
 
-		environment@0 {
+		environment {
 			compatible = "barebox,environment";
-			device-path = &usdhc3, "partname:barebox-environment";
+			device-path = &env_sd3;
 		};
 	};
 
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
+	state_emmc: state {
+		magic = <0x292D3A3C>;
+		compatible = "barebox,state";
+		backend-type = "raw";
+		backend = <&state_backend_emmc>;
+		backend-stridesize = <0x400>;
 
-		/* Address will be determined by the bootloader */
-		ramoops {
-			compatible = "ramoops";
+		bootstate {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			system0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@0 {
+					reg = <0x0 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+
+				priority@4 {
+					reg = <0x4 0x4>;
+					type = "uint32";
+					default = <21>;
+				};
+			};
+
+			system1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@10 {
+					reg = <0x10 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+
+				priority@14 {
+					reg = <0x14 0x4>;
+					type = "uint32";
+					default = <20>;
+				};
+			};
+
+			last_chosen@20 {
+				reg = <0x20 0x4>;
+				type = "uint32";
+			};
+		};
+
+		blobs {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			data_partitions@26 {
+				reg = <0x26 0x100>;
+				type = "string";
+			};
 		};
 	};
 
@@ -37,12 +92,12 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	partition@40000 {
+	env_sd3: partition@40000 {
 		label = "barebox-environment";
 		reg = <0x40000 0x80000>;
 	};
 
-	partition@c0000 {
+	state_backend_emmc: partition@c0000 {
 		label = "state";
 		reg = <0xc0000 0x40000>;
 	};
diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi b/arch/arm/dts/imx6qdl-sabrelite.dtsi
index ec3d364bde..07e3879d85 100644
--- a/arch/arm/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi
@@ -11,7 +11,7 @@
  */
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <arm/imx6qdl-sabrelite.dtsi>
+#include <arm/nxp/imx/imx6qdl-sabrelite.dtsi>
 
 / {
 
@@ -20,7 +20,7 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &flash, "partname:barebox-environment";
+			device-path = &env_nor;
 		};
 	};
 };
@@ -34,7 +34,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_nor: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi
index 6b10229c88..4e3366f4fe 100644
--- a/arch/arm/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
@@ -10,7 +10,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6qdl-sabresd.dtsi>
+#include <arm/nxp/imx/imx6qdl-sabresd.dtsi>
 
 &ocotp {
 	barebox,provide-mac-address = <&fec 0x620>;
diff --git a/arch/arm/dts/imx6qdl-skov-imx6.dtsi b/arch/arm/dts/imx6qdl-skov-imx6.dtsi
index 03f3cb02fc..b8fc1ec0bc 100644
--- a/arch/arm/dts/imx6qdl-skov-imx6.dtsi
+++ b/arch/arm/dts/imx6qdl-skov-imx6.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <dt-bindings/gpio/gpio.h>
+#include <arm/nxp/imx/imx6qdl-skov-cpu.dtsi>
 
 / {
 	aliases {
@@ -30,29 +30,6 @@
 		};
 	};
 
-	leds {
-		compatible = "gpio-leds";
-
-		led0: D1 {
-			label = "D1";
-			gpios = <&gpio1 2 0>;
-			default-state = "on";
-			linux,default-trigger = "heartbeat";
-		};
-
-		led1: D2 {
-			label = "D2";
-			gpios = <&gpio1 0 0>;
-			default-state = "off";
-		};
-
-		led2: D3 {
-			label = "D3";
-			gpios = <&gpio1 4 0>;
-			default-state = "on";
-		};
-	};
-
 	/* State: mutable part */
 	state: state {
 		magic = <0x34a0fc27>;
@@ -136,7 +113,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			eth2 {
+			eth2@1e {
 				reg = <0x1E 0x6>;
 				type = "mac";
 				default = [00 11 22 33 44 55];
@@ -169,7 +146,7 @@
 		};
 
 		display-timings {
-			native-mode = &l2rt;
+			native-mode = <&l2rt>;
 
 			l2rt: l2rt {
 				native-mode;
@@ -213,7 +190,7 @@
 		/* power-supply = <&reg_3p3v>; */
 
 		display-timings {
-			native-mode = &mi1010ait_1cp1;
+			native-mode = <&mi1010ait_1cp1>;
 
 			mi1010ait_1cp1: mi1010ait-1cp1 {
 				native-mode;
@@ -241,20 +218,6 @@
 	};
 };
 
-&pwm2 {
-	/* used for backlight brightness */
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm2_2>;
-	status = "okay";
-};
-
-&pwm3 {
-	/* used for LCD contrast control */
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm3_2>;
-	status = "okay";
-};
-
 &i2c2 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default";
@@ -273,6 +236,11 @@
 	remote-endpoint = <&display0_in>;
 };
 
+&usbh1 {
+	disable-over-current;
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
@@ -280,10 +248,6 @@
 	pinctrl_hog: hoggrp {
 		/* we need a few pins as GPIOs */
 		fsl,pins = <
-			/* MMC IO voltage select */
-			MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40000058
-			/* MMC Power Supply Switch (since revision C)
-			MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x40000058
 			/* Backlight Power Supply Switch (since revision B)
 			MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x40000058
 			/* Backlight Brightness */
@@ -293,70 +257,6 @@
 		>;
 	};
 
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
-			MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
-		>;
-	};
-
-	pinctrl_ecspi1: ecspi1grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
-			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
-			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
-			MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x40000058 /* CS# signal */
-		>;
-	};
-
-	/* pins for eth0 */
-	pinctrl_enet: enetgrp {
-		fsl,pins = <
-			MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
-			MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
-			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100b0
-			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100b0
-			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100b0
-			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100b0
-			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100b0
-			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100b0
-			MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x400000c0
-		>;
-	};
-
-	pinctrl_usdhc3: usdhc3grp {
-		fsl,pins = <
-			MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
-			MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
-			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
-			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
-			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
-			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
-			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b040 /* WP */
-			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b040 /* CD */
-		>;
-	};
-
-	pinctrl_gpmi_nand: gpminandgrp {
-		fsl,pins = <
-			MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
-			MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
-			MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
-			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
-			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
-			MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
-			MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
-			MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
-			MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
-			MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
-			MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
-			MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
-			MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
-			MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
-			MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
-		>;
-	};
-
 	pinctrl_i2c2_2: i2c2grp-2 {
 		fsl,pins = <
 			/* internal 22 k pull up required */
@@ -404,18 +304,6 @@
 			MX6QDL_PAD_RGMII_TD3__GPIO6_IO23	0x40000058
 		>;
 	};
-
-	pinctrl_pwm2_2: pwm2grp-2 {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_1__PWM2_OUT		0x00058
-		>;
-	};
-
-	pinctrl_pwm3_2: pwm3grp-2 {
-		fsl,pins = <
-			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x00058
-		>;
-	};
 };
 
 &clks {
@@ -425,43 +313,34 @@
 				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
 };
 
-/* console */
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
-	status = "okay";
-};
-
 /* spi */
 &ecspi1 {
-	fsl,spi-num-chipselects = <1>;
-	cs-gpios = <&gpio3 24 0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	status = "okay";
+	flash@0 {
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
 
-	norflash: m25p80@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <54000000>;
-		reg = <0>;
-	};
-};
+			partition@0 {
+				label = "barebox";
+				reg = <0x0 0x100000>;
+			};
 
-/* eth0 */
-&fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet>;
-	phy-mode = "rmii";
-	status = "okay";
-	phy-reset-gpios = <&gpio1 5 0>;
-	phy-reset-duration = <100>;
-	#address-cells = <0>;
-	#size-cells = <1>;
-	fixed-link {
-		speed = <100>;
-		full-duplex;
+			/* space left to let barebox grow */
+
+			/* placed near the end of the NOR memory */
+			barebox_env: partition@780000 {
+				label = "barebox-environment";
+				reg = <0x780000 0x40000>;
+			};
+
+			/* placed at the end of the NOR memory */
+			state_storage: partition@7C0000 {
+				label = "barebox-state";
+				/* four times mirrored */
+				reg = <0x7C0000 0x40000>;
+			};
+		};
 	};
 };
 
@@ -486,21 +365,7 @@
 	status = "okay";
 };
 
-&usdhc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	wp-gpios = <&gpio7 1 0>;
-	cd-gpios = <&gpio7 0 0>;
-	status = "okay";
-	fsl,delay-line;
-};
-
 &gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
-	status = "okay";
-
 	partitions {
 		compatible = "fixed-partitions";
 		#address-cells = <1>;
@@ -513,34 +378,6 @@
 	};
 };
 
-/* define the SPI based 8 MiB NOR flash layout */
-&norflash {
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		partition@0 {
-			label = "barebox";
-			reg = <0x0 0x100000>;
-		};
-
-		/* space left to let barebox grow */
-
-		/* placed near the end of the NOR memory */
-		barebox_env: partition@780000 {
-			label = "barebox-environment";
-			reg = <0x780000 0x40000>;
-		};
-
-		/* placed at the end of the NOR memory */
-		state_storage: partition@7C0000 {
-			label = "barebox-state";
-			reg = <0x7C0000 0x40000>; /* four times mirrored */
-		};
-	};
-};
-
 &ocotp {
 	barebox,provide-mac-address = <&fec 0x620>;
 };
diff --git a/arch/arm/dts/imx6qdl-tx6x.dtsi b/arch/arm/dts/imx6qdl-tx6x.dtsi
index 13102168f7..139b735b6d 100644
--- a/arch/arm/dts/imx6qdl-tx6x.dtsi
+++ b/arch/arm/dts/imx6qdl-tx6x.dtsi
@@ -5,7 +5,7 @@
 		environment-nand {
 			status = "disabled";
 			compatible = "barebox,environment";
-			device-path = &gpmi, "partname:barebox-environment";
+			device-path = &env_nand;
 		};
 
 		environment-emmc {
@@ -14,10 +14,10 @@
 			device-path = &usdhc4, "partname:boot1";
 		};
 	};
+};
 
-	gpio-keys {
-		status = "disabled";
-	};
+&{/gpio-keys} {
+	status = "disabled";
 };
 
 &fec {
@@ -34,7 +34,7 @@
 		reg = <0x0 0x400000>;
 	};
 
-	partition@400000 {
+	env_nand: partition@400000 {
 		label = "barebox-environment";
 		reg = <0x400000 0x100000>;
 	};
diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
index b593545ffe..a01962d0e6 100644
--- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
@@ -39,13 +39,13 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <arm/imx6qdl-zii-rdu2.dtsi>
+#include <arm/nxp/imx/imx6qdl-zii-rdu2.dtsi>
 
 / {
 	chosen {
 		environment {
 			compatible = "barebox,environment";
-			device-path = &nor_flash, "partname:barebox-environment";
+			device-path = &env_nor;
 		};
 
 		ubootenv {
@@ -178,34 +178,27 @@
 	};
 };
 
-&uart4 {
-	rave-sp {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		watchdog {
-			nvmem-cells = <&boot_source>;
-			nvmem-cell-names = "boot-source";
-		};
+&{uart4/mcu/watchdog} {
+	nvmem-cells = <&boot_source>;
+	nvmem-cell-names = "boot-source";
+};
 
-		eeprom@a4 {
-			lru_part_number: lru-part-number@21 {
-				reg = <0x21 15>;
-				read-only;
-			};
+&{uart4/mcu/eeprom@a4} {
+	lru_part_number: lru-part-number@21 {
+		reg = <0x21 15>;
+		read-only;
+	};
 
-			boot_source: boot-source@83 {
-				reg = <0x83 1>;
-			};
+	boot_source: boot-source@83 {
+		reg = <0x83 1>;
+	};
 
-			mac_address_0: mac-address@180 {
-				reg = <0x180 6>;
-			};
+	mac_address_0: mac-address@180 {
+		reg = <0x180 6>;
+	};
 
-			mac_address_1: mac-address@190 {
-				reg = <0x190 6>;
-			};
-		};
+	mac_address_1: mac-address@190 {
+		reg = <0x190 6>;
 	};
 };
 
@@ -219,7 +212,7 @@
 			reg = <0x0 0xc0000>;
 		};
 
-		partition@c0000 {
+		env_nor: partition@c0000 {
 			label = "barebox-environment";
 			reg = <0xc0000 0x40000>;
 		};
@@ -231,36 +224,16 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&i2c1 {
-	edp-bridge@68 {
-		pinctrl-0 = <&pinctrl_tc358767>, <&pinctrl_disp0>;
-
-		ports {
-			port@1 {
-				reg = <1>;
-
-				tc358767_in: endpoint {
-					remote-endpoint = <&disp0_out>;
-				};
-			};
-		};
-	};
+&{i2c1/edp-bridge@68} {
+	pinctrl-0 = <&pinctrl_tc358767>, <&pinctrl_disp0>;
 };
 
-&i2c2 {
-	temp-sense@48 {
-		barebox,sensor-name = "Temp Sensor 1";
-	};
+&{i2c2/temp-sense@48} {
+	barebox,sensor-name = "Temp Sensor 1";
 };
 
-&ipu1_di0_disp0 {
-	remote-endpoint = <&tc358767_in>;
-};
-
-&ldb {
-	lvds-channel@0 {
-		fsl,data-width = <24>;
-	};
+&{ldb/lvds-channel@0} {
+	fsl,data-width = <24>;
 };
 
 &i210 {
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index c3e02d2117..6f58804ed3 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -8,6 +8,13 @@
 		ipu0 = &ipu1;
 		gpr.reboot_mode = &reboot_mode_gpr;
 	};
+
+	chosen {
+		barebox,bootsource-mmc0 = &usdhc1;
+		barebox,bootsource-mmc1 = &usdhc2;
+		barebox,bootsource-mmc2 = &usdhc3;
+		barebox,bootsource-mmc3 = &usdhc4;
+	};
 };
 
 &src {
diff --git a/arch/arm/dts/imx6qp-nitrogen6_max.dts b/arch/arm/dts/imx6qp-nitrogen6_max.dts
index 93f0741062..17ae7c1bd3 100644
--- a/arch/arm/dts/imx6qp-nitrogen6_max.dts
+++ b/arch/arm/dts/imx6qp-nitrogen6_max.dts
@@ -40,5 +40,5 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <arm/imx6qp-nitrogen6_max.dts>
+#include <arm/nxp/imx/imx6qp-nitrogen6_max.dts>
 #include "imx6qdl-nitrogen6_max.dtsi"
diff --git a/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts
index 378806df53..8ed5635199 100644
--- a/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6qp.dtsi>
+#include <arm/nxp/imx/imx6qp.dtsi>
 #include "imx6qdl-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
 
diff --git a/arch/arm/dts/imx6qp-prtwd3.dts b/arch/arm/dts/imx6qp-prtwd3.dts
index 8c56d70b5a..dc52eebc85 100644
--- a/arch/arm/dts/imx6qp-prtwd3.dts
+++ b/arch/arm/dts/imx6qp-prtwd3.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6qp-prtwd3.dts>
+#include <arm/nxp/imx/imx6qp-prtwd3.dts>
 #include "imx6qdl-prti6q-emmc.dtsi"
 
diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts
new file mode 100644
index 0000000000..1811044d94
--- /dev/null
+++ b/arch/arm/dts/imx6qp-sabresd.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <arm/nxp/imx/imx6qp-sabresd.dts>
+
+/ {
+	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
+	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
+
+	chosen {
+		stdout-path = &uart1;
+
+		environment {
+			compatible = "barebox,environment";
+			device-path = &environment_usdhc3;
+		};
+	};
+};
+
+&usdhc3 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	environment_usdhc3: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
diff --git a/arch/arm/dts/imx6qp-vicutp.dts b/arch/arm/dts/imx6qp-vicutp.dts
index 1411071fb3..8827ffdebb 100644
--- a/arch/arm/dts/imx6qp-vicutp.dts
+++ b/arch/arm/dts/imx6qp-vicutp.dts
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6qp-vicutp.dts>
+#include <arm/nxp/imx/imx6qp-vicutp.dts>
 #include "imx6qdl-prti6q-nor.dtsi"
diff --git a/arch/arm/dts/imx6qp-zii-rdu2.dts b/arch/arm/dts/imx6qp-zii-rdu2.dts
index fcf2ee5a10..007428640f 100644
--- a/arch/arm/dts/imx6qp-zii-rdu2.dts
+++ b/arch/arm/dts/imx6qp-zii-rdu2.dts
@@ -42,7 +42,7 @@
 
 /dts-v1/;
 
-#include <arm/imx6qp.dtsi>
+#include <arm/nxp/imx/imx6qp.dtsi>
 #include "imx6q.dtsi"
 #include "imx6qdl-zii-rdu2.dtsi"
 
diff --git a/arch/arm/dts/imx6s-phytec-pfla02.dtsi b/arch/arm/dts/imx6s-phytec-pfla02.dtsi
index 7ef27fb941..d8af37c045 100644
--- a/arch/arm/dts/imx6s-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6s-phytec-pfla02.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6dl.dtsi>
+#include <arm/nxp/imx/imx6dl.dtsi>
 #include "imx6dl.dtsi"
 #include "imx6qdl-phytec-pfla02.dtsi"
 
diff --git a/arch/arm/dts/imx6s-riotboard.dts b/arch/arm/dts/imx6s-riotboard.dts
index 9efef039a7..5ddd30fb96 100644
--- a/arch/arm/dts/imx6s-riotboard.dts
+++ b/arch/arm/dts/imx6s-riotboard.dts
@@ -5,7 +5,7 @@
  * License version 2.
  */
 
-#include <arm/imx6dl-riotboard.dts>
+#include <arm/nxp/imx/imx6dl-riotboard.dts>
 #include "imx6qdl.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6s-skov-imx6.dts b/arch/arm/dts/imx6s-skov-imx6.dts
new file mode 100644
index 0000000000..e05abd3dab
--- /dev/null
+++ b/arch/arm/dts/imx6s-skov-imx6.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2015 Juergen Borleis, Pengutronix <kernel@pengutronix.de>
+ */
+
+/dts-v1/;
+#include <arm/nxp/imx/imx6dl.dtsi>
+#include "imx6dl.dtsi"
+#include "imx6qdl-skov-imx6.dtsi"
+
+/ {
+	model = "Skov IMX6";
+	compatible = "skov,imx6", "fsl,imx6dl";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&hdmi {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts
index 8cf412a39f..f58df62cbd 100644
--- a/arch/arm/dts/imx6sx-sdb.dts
+++ b/arch/arm/dts/imx6sx-sdb.dts
@@ -7,14 +7,14 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx6sx-sdb.dts>
+#include <arm/nxp/imx/imx6sx-sdb.dts>
 #include "imx6sx.dtsi"
 
 / {
 	chosen {
 		environment {
 			compatible = "barebox,environment";
-			device-path = &usdhc4, "partname:barebox-environment";
+			device-path = &env_sd4;
 		};
 	};
 };
@@ -31,7 +31,7 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	partition@e0000 {
+	env_sd4: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6sx-udoo-neo-full.dts b/arch/arm/dts/imx6sx-udoo-neo-full.dts
index 1609781b7f..12fd5073db 100644
--- a/arch/arm/dts/imx6sx-udoo-neo-full.dts
+++ b/arch/arm/dts/imx6sx-udoo-neo-full.dts
@@ -1,6 +1,10 @@
-#include <arm/imx6sx-udoo-neo-full.dts>
+#include <arm/nxp/imx/imx6sx-udoo-neo-full.dts>
+#include "imx6sx.dtsi"
 
 / {
+
+	/delete-node/ memory@80000000;
+
 	chosen {
 		environment {
 			compatible = "barebox,environment";
@@ -27,3 +31,15 @@
 &ocotp {
 	barebox,provide-mac-address = <&fec1 0x620>;
 };
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX6SX_PAD_NAND_READY_B__GPIO4_IO_13	0x1b0b0
+			MX6SX_PAD_NAND_ALE__GPIO4_IO_0		0x1b0b0
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts
index 1139c4b7d6..a9a2581c0e 100644
--- a/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts
+++ b/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts
@@ -1,4 +1,4 @@
-#include <arm/imx6ul-ccimx6ulsbcpro.dts>
+#include <arm/nxp/imx/imx6ul-ccimx6ulsbcpro.dts>
 
 /{
 	chosen {
@@ -6,7 +6,7 @@
 
 		environment-nand {
 			compatible = "barebox,environment";
-			device-path = &gpmi, "partname:barebox-environment";
+			device-path = &env_nand;
 			status = "okay";
 		};
 	};
@@ -28,7 +28,7 @@
 			reg = <0x0 0x400000>;
 		};
 
-		partition@400000 {
+		env_nand: partition@400000 {
 			label = "barebox-environment";
 			reg = <0x400000 0x100000>;
 		};
diff --git a/arch/arm/dts/imx6ul-liteboard.dts b/arch/arm/dts/imx6ul-liteboard.dts
index eb34e11ddb..f9ea9fc023 100644
--- a/arch/arm/dts/imx6ul-liteboard.dts
+++ b/arch/arm/dts/imx6ul-liteboard.dts
@@ -41,7 +41,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <arm/imx6ul-liteboard.dts>
+#include <arm/nxp/imx/imx6ul-liteboard.dts>
 #include "imx6ul-litesom.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts
index 50ce75f12b..b30cd60aa6 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6ul.dtsi>
+#include <arm/nxp/imx/imx6ul.dtsi>
 #include "imx6ul-phytec-phycore-som.dtsi"
 #include "imx6ul-phytec-state.dtsi"
 
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
index c8d43c5e25..c8be386e7f 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6ul.dtsi>
+#include <arm/nxp/imx/imx6ul.dtsi>
 #include "imx6ul-phytec-phycore-som.dtsi"
 #include "imx6ul-phytec-state.dtsi"
 
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index c7c657bcd4..4aea8c1d38 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -16,19 +16,19 @@
 
 		environment-nand {
 			compatible = "barebox,environment";
-			device-path = &gpmi, "partname:barebox-environment";
+			device-path = &env_nand;
 			status = "disabled";
 		};
 
 		environment-sd1 {
 			compatible = "barebox,environment";
-			device-path = &usdhc1, "partname:barebox-environment";
+			device-path = &env_sd1;
 			status = "disabled";
 		};
 
 		environment-sd2 {
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 			status = "disabled";
 		};
 	};
@@ -67,7 +67,7 @@
 			reg = <0x0 0x400000>;
 		};
 
-		partition@400000 {
+		env_nand: partition@400000 {
 			label = "barebox-environment";
 			reg = <0x400000 0x100000>;
 		};
@@ -125,7 +125,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd1: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
@@ -146,7 +146,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx6ul-phytec-state.dtsi b/arch/arm/dts/imx6ul-phytec-state.dtsi
index 78a32ed96b..d0cad1b516 100644
--- a/arch/arm/dts/imx6ul-phytec-state.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-state.dtsi
@@ -18,29 +18,27 @@
 		backend-stridesize = <54>;
 		status = "disabled";
 
-		#address-cells = <1>;
-		#size-cells = <1>;
 		bootstate {
 			#address-cells = <1>;
 			#size-cells = <1>;
-			last_chosen {
+			last_chosen@0 {
 				reg = <0x0 0x4>;
 				type = "uint32";
 			};
 			system0 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				remaining_attempts {
+				remaining_attempts@4 {
 					reg = <0x4 0x4>;
 					type = "uint32";
 					default = <3>;
 				};
-				priority {
+				priority@8 {
 					reg = <0x8 0x4>;
 					type = "uint32";
 					default = <21>;
 				};
-				ok {
+				ok@c {
 					reg = <0xc 0x4>;
 					type = "uint32";
 					default = <0>;
@@ -49,17 +47,17 @@
 			system1 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				remaining_attempts {
+				remaining_attempts@10 {
 					reg = <0x10 0x4>;
 					type = "uint32";
 					default = <3>;
 				};
-				priority {
+				priority@14 {
 					reg = <0x14 0x4>;
 					type = "uint32";
 					default = <20>;
 				};
-				ok {
+				ok@18 {
 					reg = <0x18 0x4>;
 					type = "uint32";
 					default = <0>;
diff --git a/arch/arm/dts/imx6ul-pico-hobbit.dts b/arch/arm/dts/imx6ul-pico-hobbit.dts
index 0c543de8c9..3deb89c448 100644
--- a/arch/arm/dts/imx6ul-pico-hobbit.dts
+++ b/arch/arm/dts/imx6ul-pico-hobbit.dts
@@ -1,4 +1,4 @@
-#include <arm/imx6ul-pico-hobbit.dts>
+#include <arm/nxp/imx/imx6ul-pico-hobbit.dts>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/imx6ul-prti6g.dts b/arch/arm/dts/imx6ul-prti6g.dts
index f720a2518c..262a96742b 100644
--- a/arch/arm/dts/imx6ul-prti6g.dts
+++ b/arch/arm/dts/imx6ul-prti6g.dts
@@ -1,26 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include <arm/imx6ul-prti6g.dts>
+#include <arm/nxp/imx/imx6ul-prti6g.dts>
 
 / {
 	chosen {
 		stdout-path = &uart4;
 
-		environment@0 {
+		environment {
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
-		};
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		/* Address will be determined by the bootloader */
-		ramoops {
-			compatible = "ramoops";
+			device-path = &env_sd2;
 		};
 	};
 
@@ -52,7 +41,7 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	partition@40000 {
+	env_sd2: partition@40000 {
 		label = "barebox-environment";
 		reg = <0x40000 0x80000>;
 	};
diff --git a/arch/arm/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/dts/imx6ul-tqma6ul-common.dtsi
new file mode 100644
index 0000000000..5ff318fcfc
--- /dev/null
+++ b/arch/arm/dts/imx6ul-tqma6ul-common.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2021 Pengutronix e.K.
+ * Author: Rouven Czerwinski
+ */
+
+#include "imx6ul.dtsi"
+
+/ {
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &environment_sd;
+			status = "disabled";
+		};
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &environment_emmc;
+			status = "disabled";
+		};
+	};
+};
+
+&usdhc2 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		environment_emmc: partition@e0000 {
+			label = "barebox-environment";
+			reg = <0xe0000 0x20000>;
+		};
+	};
+};
+
+&usdhc1 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0xe0000>;
+		};
+
+		environment_sd: partition@e0000 {
+			label = "barebox-environment";
+			reg = <0xe0000 0x20000>;
+		};
+	};
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec1 0x620 &fec2 0x632>;
+};
+
+/* include the FIT public key for verifying on demand */
+#ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
+#include CONFIG_BOOTM_FITIMAGE_PUBKEY
+#endif
diff --git a/arch/arm/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/dts/imx6ul-tqma6ul2-mba6ulx.dts
new file mode 100644
index 0000000000..2d49c0e763
--- /dev/null
+++ b/arch/arm/dts/imx6ul-tqma6ul2-mba6ulx.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+
+#include <arm/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts>
+#include "imx6ul-tqma6ul-common.dtsi"
diff --git a/arch/arm/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/dts/imx6ul-tqma6ul2l-mba6ulx.dts
new file mode 100644
index 0000000000..2d49c0e763
--- /dev/null
+++ b/arch/arm/dts/imx6ul-tqma6ul2l-mba6ulx.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+
+#include <arm/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts>
+#include "imx6ul-tqma6ul-common.dtsi"
diff --git a/arch/arm/dts/imx6ul-webasto-ccbv2.dts b/arch/arm/dts/imx6ul-webasto-ccbv2.dts
index 93e9445b48..198088bd44 100644
--- a/arch/arm/dts/imx6ul-webasto-ccbv2.dts
+++ b/arch/arm/dts/imx6ul-webasto-ccbv2.dts
@@ -32,8 +32,6 @@
 	};
 
 	state_emmc: state {
-		#address-cells = <1>;
-		#size-cells = <1>;
 		compatible = "barebox,state";
 		magic = <0x290cf8c6>;
 		backend-type = "raw";
diff --git a/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi b/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi
index 829485de32..5207abea0c 100644
--- a/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi
+++ b/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <arm/imx6ul.dtsi>
+#include <arm/nxp/imx/imx6ul.dtsi>
 
 / {
 	model = "Webasto common communication board version 2";
diff --git a/arch/arm/dts/imx6ul-webasto-marvel.dts b/arch/arm/dts/imx6ul-webasto-marvel.dts
new file mode 100644
index 0000000000..7b5641afbc
--- /dev/null
+++ b/arch/arm/dts/imx6ul-webasto-marvel.dts
@@ -0,0 +1,584 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019, Webasto SE
+ * Author: Johannes Eigner <johannes.eigner@webasto.com>
+ *
+ * Description of the Marvel B2, MK3 Comboard
+ */
+
+/dts-v1/;
+
+#include <arm/nxp/imx/imx6ul.dtsi>
+
+/ {
+	model = "Webasto common communication board Marvel MK3";
+	compatible = "webasto,imx6ul-marvel-b2", "webasto,imx6ul-marvel", "fsl,imx6ul";
+
+	chosen {
+		stdout-path = &uart7;
+		environment {
+			compatible = "barebox,environment";
+			device-path = &environment_emmc;
+		};
+	};
+
+	aliases {
+		state = &state_emmc;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		dt-overlay@84000000 {
+			reg = <0x84000000 0x100000>;
+			no-map;
+		};
+	};
+
+	state_emmc: state {
+		compatible = "barebox,state";
+		magic = <0x290cf8c6>;
+		backend-type = "raw";
+		backend = <&backend_state_emmc>;
+		backend-stridesize = <0x200>;
+
+		bootstate {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			system0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@0 {
+					reg = <0x0 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+
+				priority@4 {
+					reg = <0x4 0x4>;
+					type = "uint32";
+					default = <20>;
+				};
+			};
+
+			system1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@8 {
+					reg = <0x8 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+
+				priority@c {
+					reg = <0xc 0x4>;
+					type = "uint32";
+					default = <21>;
+				};
+			};
+
+			last_chosen@10 {
+				reg = <0x10 0x4>;
+				type = "uint32";
+			};
+		};
+	};
+
+	transceiver1_en: regulator-can1phy {
+		compatible = "regulator-fixed";
+		regulator-name = "can-transceiver1";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctl_can1phy>;
+		vin-supply = <&swbst_reg>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_4v: regulator-4v {
+		compatible = "regulator-fixed";
+		regulator-name = "V_+4V";
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <4000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_wl18xx_vmmc: regulator-wl18xx {
+		compatible = "regulator-fixed";
+		regulator-name = "wl1837";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wifi_reg>;
+		vin-supply = <&reg_4v>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	reg_dp83822_en: regulator-dp83822 {
+		compatible = "regulator-fixed";
+		regulator-name = "dp83822";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_phy_reg>;
+		vin-supply = <&vcc_eth>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&asrc {
+	status = "disabled";
+};
+
+&can1 {
+	xceiver-supply = <&transceiver1_en>; /* CAN side */
+	vdd-supply = <&vgen1_reg>; /* I/O side */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctl_can1>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-supply = <&reg_dp83822_en>;
+	phy-handle = <&dp83822i>;
+	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dp83822i: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			clocks = <&clks IMX6UL_CLK_ENET_REF>;
+			clock-names = "rmii-ref";
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	pmic: mc34pf3000@8 {
+		compatible = "fsl,pfuze3000";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctl_pmic_irq>;
+		interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>;
+		reg = <0x08>;
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-name = "V_+3V3_SW1A";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			vdd_soc_in: sw1b {
+				regulator-name = "V_+1V4_SW1B";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-ramp-delay = <6250>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			sw2_reg: sw2 {
+				regulator-name = "V_+3V3_SW2";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vcc_ddr3: sw3 {
+				regulator-name = "V_+1V35_SW3";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			swbst_reg: swbst {
+				regulator-name = "V_+5V0_SWBST";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+				regulator-always-on; /* due to hardware requirements */
+			};
+			vdd_snvs: vsnvs {
+				regulator-name = "V_+3V0_SNVS";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vrefddr: vrefddr {
+				regulator-name = "V_+0V675_VREFDDR";
+				vin-supply = <&vcc_ddr3>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			/* 3V3 Supply: i.MX6 modules */
+			vgen1_reg: vldo1 {
+				regulator-name = "V_+3V3_LDO1";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vgen2_reg: vldo2 {
+				/* not connected */
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+			};
+			vdd_high_in: v33 {
+				regulator-name = "V_+3V3_V33";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vcc_eth: vldo3 {
+				regulator-name = "V_+1V8_LDO3";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vgen6_reg: vldo4 {
+				regulator-name = "V_+1V8_LDO4";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_phy_reg: phyreggrp {
+		fsl,pins = <
+			/* high = phy enabled */
+			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x13030
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			/* Note: 1.8 V */
+			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
+			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
+			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x13030
+		>;
+	};
+
+	pinctl_pmic_irq: pmicgrp {
+		fsl,pins = <
+			/* 1.8 V level */
+			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x10000
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			/* 1.8 V level for all */
+			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
+			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
+		>;
+	};
+
+	pinctrl_uart6: uart6grp {
+		fsl,pins = <
+			/* 1.8 V level for all */
+			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x1b0b0
+			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x1b0b0
+			MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS	0x1b0b0
+			MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x10030
+		>;
+	};
+
+	pinctrl_uart7: uart7grp {
+		fsl,pins = <
+			/* 3.3 V level for all */
+			MX6UL_PAD_LCD_DATA16__UART7_DCE_TX	0x0b0b0
+			MX6UL_PAD_LCD_DATA17__UART7_DCE_RX	0x1b0b0
+		>;
+	};
+
+	pinctrl_wifi_reg: wifigrp {
+		fsl,pins = <
+			/* 1.8 V level for all */
+			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x10030
+			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x00010
+		>;
+	};
+
+	pinctrl_wifi_irq: wifiirqgrp {
+		fsl,pins = <
+			/* 1.8 V level */
+			MX6UL_PAD_CSI_DATA00__GPIO4_IO21	0x17000
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			/* 1.8 V level for all */
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x10059
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x10059
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x10059
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x10059
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x10059
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp_slow {
+		fsl,pins = <
+			/* 3.3 V level for all, *no* external PU */
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10079
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17029
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17029
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17029
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17029
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17029
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x17029
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x17029
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x17029
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x17029
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B	0x00008
+		>;
+	};
+
+	pinctrl_usdhc2_100MHZ: usdhc2grp_100m {
+		fsl,pins = <
+			/* 3.3 V level for all, *no* external PU */
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100e9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x1b0a9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x1b0a9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x1b0a9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x1b0a9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x1b0a9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x1b0a9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x1b0a9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x1b0a9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x1b0a9
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B	0x00008
+		>;
+	};
+
+	pinctrl_usdhc2_200MHZ: usdhc2grp_200m {
+		fsl,pins = <
+			/* 3.3 V level for all, *no* external PU */
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100e9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x1b0e9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x1b0e9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x1b0e9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x1b0e9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x1b0e9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x1b0e9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x1b0e9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x1b0e9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x1b0e9
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B	0x00008
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x00b0
+		>;
+	};
+
+	pinctl_can1phy: can1phygrp {
+		fsl,pins = <
+			/* 3.3 V level */
+			MX6UL_PAD_LCD_DATA14__GPIO3_IO19	0x00008
+		>;
+	};
+
+	pinctl_can1: can1grp {
+		fsl,pins = <
+			/* 3.3 V level for all */
+			MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX	0x00009
+			MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX	0x17000
+		>;
+	};
+
+	pinctrl_usbotg2: cmgrp {
+		fsl,pins = <
+			MX6UL_PAD_UART2_RTS_B__GPIO1_IO23       0x10800  /* shutdown signal from voltage monitor */
+			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20     0x00028  /* power on signal to modem */
+			MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21     0x00028  /* fast shutdown signal to modem */
+			MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x00028  /* emergency reset signal to modem */
+			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25     0x14000  /* status signal from modem */
+		>;
+	};
+};
+
+&gpio1 {
+	gpio-line-names = "", "", "", "", "", "", "", "",
+		     "", "", "", "", "", "", "", "",
+		     "", "", "", "", "PWRON_CM_UC_DO", "FST_SHDN_CM_UC_DO", "", "INT_VMON_OUT",
+		     "", "STATUS_CM_UC_DI", "RST_EMERG_UC_DO", "", "";
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec1 0x620>;
+};
+
+&reg_arm {
+	vin-supply = <&vdd_soc_in>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&vdd_soc_in>;
+	regulator-allow-bypass;
+};
+
+&uart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart6>;
+	uart-has-rtscts;
+	bluetooth {
+		compatible = "ti,wl1837-st";
+		enable-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&reg_4v>;
+	};
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart7>;
+	status = "okay";
+};
+
+&usbotg1 {
+	/* Micro-USB-plug */
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbotg2 {
+	/* Modem (e.g. internal only) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg2>;
+	vbus-supply = <&swbst_reg>;
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc1 {
+	/* SDIO (WIFI/BT) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_wl18xx_vmmc>;
+	vqmmc-supply = <&vgen6_reg>;
+	non-removable;
+	no-sd;
+	no-mmc;
+	keep-power-in-suspend;
+	cap-power-off-card;
+	max-frequency = <25000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1837";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wifi_irq>;
+		reg = <2>;
+		interrupts-extended = <&gpio4 21 IRQ_TYPE_LEVEL_HIGH>;
+		tcxo-clock-frequency = <26000000>;
+	};
+};
+
+&usdhc2 {
+	/* eMMC */
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100MHZ>;
+	pinctrl-2 = <&pinctrl_usdhc2_200MHZ>;
+	bus-width = <8>;
+	vmmc-supply = <&sw1a_reg>;
+	vqmmc-supply = <&vgen1_reg>;
+	no-1-8-v;
+	non-removable;
+	no-sd;
+	no-sdio;
+	keep-power-in-suspend;
+	cap-mmc-hw-reset;
+	status = "okay";
+	/* bootloader specific */
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x100000>;
+		};
+
+		environment_emmc: partition@100000 {
+			label = "barebox-environment";
+			reg = <0x100000 0x100000>;
+		};
+
+		backend_state_emmc: partition@200000 {
+			label = "barebox-state";
+			reg = <0x200000 0x100000>;
+		};
+	};
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+/* include the FIT public key for verifying on demand */
+#ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
+#include CONFIG_BOOTM_FITIMAGE_PUBKEY
+#endif
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
new file mode 100644
index 0000000000..7d600f505b
--- /dev/null
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -0,0 +1,6 @@
+/ {
+	aliases {
+		barebox,bootsource-mmc0 = &usdhc1;
+		barebox,bootsource-mmc1 = &usdhc2;
+	};
+};
diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts
index 6712e10739..ad283ca968 100644
--- a/arch/arm/dts/imx6ull-14x14-evk.dts
+++ b/arch/arm/dts/imx6ull-14x14-evk.dts
@@ -1,4 +1,4 @@
-#include <arm/imx6ull-14x14-evk.dts>
+#include <arm/nxp/imx/imx6ull-14x14-evk.dts>
 
 /{
 	chosen {
diff --git a/arch/arm/dts/imx6ull-jozacp.dts b/arch/arm/dts/imx6ull-jozacp.dts
new file mode 100644
index 0000000000..612dac67ca
--- /dev/null
+++ b/arch/arm/dts/imx6ull-jozacp.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "imx6ull-jozacp.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+
+		environment {
+			compatible = "barebox,environment";
+			device-path = &env_sd1;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* Address will be determined by the bootloader */
+		ramoops {
+			compatible = "ramoops";
+		};
+	};
+};
+
+&usdhc1 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	env_sd1: partition@40000 {
+		label = "barebox-environment";
+		reg = <0x40000 0x80000>;
+	};
+};
diff --git a/arch/arm/dts/imx6ull-jozacp.dtsi b/arch/arm/dts/imx6ull-jozacp.dtsi
new file mode 100644
index 0000000000..b3529795b8
--- /dev/null
+++ b/arch/arm/dts/imx6ull-jozacp.dtsi
@@ -0,0 +1,519 @@
+/*
+ * Copyright (C) 2020 Protonic Holland
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include <arm/nxp/imx/imx6ull.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "JOZ Access Point";
+	compatible = "joz,jozacp", "fsl,imx6ull";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+
+	reg_5v: 5v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "regulator-5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: 3p3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "regulator-3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&reg_5v>;
+		regulator-always-on;
+	};
+
+	reg_1p4v: 1p4-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "regulator-1P4V";
+		regulator-min-microvolt = <1400000>;
+		regulator-max-microvolt = <1400000>;
+		vin-supply = <&reg_5v>;
+		regulator-always-on;
+	};
+
+	reg_vbus: vbus-regulator {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_vbus>;
+		compatible = "regulator-fixed";
+		regulator-name = "regulator-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&reg_5v>;
+		gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	usdhc2_pwrseq: usdhc2-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wlan0_reg_on>;
+		reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+	};
+
+	pwm_leds {
+		compatible = "pwm-leds";
+
+		rgb1_red {
+			label = "pwm:red:rgb1";
+			pwms = <&pwm1 0 10000000 0>;
+			max-brightness = <255>;
+		};
+
+		rgb1_green {
+			label = "pwm:green:rgb1";
+			pwms = <&pwm3 0 10000000 0>;
+			max-brightness = <255>;
+		};
+
+		rgb1_blue {
+			label = "pwm:blue:rgb1";
+			pwms = <&pwm5 0 10000000 0>;
+			max-brightness = <255>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		rgb2_red {
+			label = "pwm:red:rgb2";
+			pwms = <&pwm2 0 10000000 0>;
+			max-brightness = <255>;
+		};
+
+		rgb2_green {
+			label = "pwm:green:rgb2";
+			pwms = <&pwm4 0 10000000 0>;
+			max-brightness = <255>;
+			linux,default-trigger = "netdev";
+		};
+
+		rgb2_blue {
+			label = "pwm:blue:rgb2";
+			pwms = <&pwm6 0 10000000 0>;
+			max-brightness = <255>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <792000000>;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			/* HW Revision */
+			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x1b0b0
+			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x1b0b0
+
+			/* HW ID */
+			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12	0x1b0b0
+			MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13	0x1b0b0
+			MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14	0x1b0b0
+			MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15	0x1b0b0
+
+			/* Digital inputs */
+			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x11000
+			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x11000
+			MX6UL_PAD_GPIO1_IO05__GPIO1_IO05	0x11000
+			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x11000
+			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x11000
+
+			/* Isolated outputs */
+			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x01020
+			MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21	0x01020
+			MX6UL_PAD_UART2_RTS_B__GPIO1_IO23	0x01020
+			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x01020
+			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x01020
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO07__ENET1_MDC	 0x1b0b0
+			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
+			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+		>;
+	};
+
+	pinctrl_can1: can1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b0b0
+			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001f8b1
+			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001f8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001f8b1
+			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001f8b1
+		>;
+	};
+
+	pinctrl_pwm1: pwm1-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA00__PWM1_OUT		0x01010
+		>;
+	};
+
+	pinctrl_pwm2: pwm2-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA01__PWM2_OUT		0x01010
+		>;
+	};
+
+	pinctrl_pwm3: pwm3-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA02__PWM3_OUT		0x01010
+		>;
+	};
+
+	pinctrl_pwm4: pwm4-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA03__PWM4_OUT		0x01010
+		>;
+	};
+
+	pinctrl_pwm5: pwm5-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA18__PWM5_OUT		0x01010
+		>;
+	};
+
+	pinctrl_pwm6: pwm6-grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA19__PWM6_OUT		0x01010
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
+			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_DATA04__UART2_DCE_TX	0x1b0b0
+			MX6UL_PAD_NAND_DATA05__UART2_DCE_RX	0x1b0b0
+			MX6UL_PAD_NAND_DATA06__GPIO4_IO08	0x1b0b0
+			MX6UL_PAD_NAND_DATA07__GPIO4_IO09	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_CLK__UART4_DCE_TX		0x1b0b0
+			MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX	0x1b0b0
+			MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS	0x1b0b0
+			MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS	0x1b0b0
+			MX6UL_PAD_LCD_RESET__GPIO3_IO04		0x1b0b0
+		>;
+	};
+
+	pinctrl_vbus: vbus0grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x030b0
+		>;
+	};
+
+	pinctrl_usbotg1: usbotg1grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC	0x1b0b0
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B	0x17099
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x1f099
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10099
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17099
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17099
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17099
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17099
+			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17099
+			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17099
+			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17099
+			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17099
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x100b9
+			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x170b9
+			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x170b9
+			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x170b9
+			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x170b9
+			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x170b9
+		>;
+	};
+
+	pinctrl_wlan0_reg_on: wlan0-regon-grp0 {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x03020
+		>;
+	};
+
+	pinctrl_wlan0_host_wake: wlan0-host_wake-grp0 {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x1b0b0
+		>;
+	};
+
+	pinctrl_bt0_reg_on: bt0-regon-grp0 {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA07__GPIO4_IO28	0x03020
+		>;
+	};
+
+	pinctrl_bt0_host_wake: bt0-host_wake-grp0 {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x1b0b0
+		>;
+	};
+
+	pinctrl_etnphy0_rst: etnphy-rstgrp-grp0 {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x038b0
+		>;
+	};
+
+	pinctrl_etnphy0_int: etnphy-intgrp-grp0 {
+		fsl,pins = <
+			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x170b0
+		>;
+	};
+};
+
+&iomuxc_snvs {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_snvs_hog>;
+
+	pinctrl_snvs_hog: snvs-hog-grp {
+		fsl,pins = <
+			/* Digital outputs */
+			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x00020
+			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x00020
+			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x00020
+			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x00020
+			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x00020
+
+			/* Digital outputs fault feedback */
+			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x17000
+			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17000
+			MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x17000
+			MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17000
+			MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x17000
+		>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <11>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			reg = <0>;
+			clocks = <&clks IMX6UL_CLK_ENET_REF>;
+			clock-names = "rmii-ref";
+			interrupt-parent = <&gpio1>;
+			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	rtc: pcf8563@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+};
+
+&snvs_rtc {
+	status = "disabled";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	cts-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+	rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+	status = "disabled";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_bt0_reg_on &pinctrl_bt0_host_wake>;
+		host-wakeup-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+		vbat-supply = <&reg_3p3v>;
+		vddio-supply = <&reg_3p3v>;
+		max-speed = <921600>;
+	};
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbotg1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1>;
+	vbus-supply = <&reg_vbus>;
+	dr_mode = "host";
+	over-current-active-low;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	vmmc-supply = <&reg_3p3v>;
+	bus-width = <8>;
+	no-1-8-v;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	mmc-pwrseq = <&usdhc2_pwrseq>;
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+	pm-ignore-notify;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	brcmf: bcrmf@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wlan0_host_wake>;
+		//interrupt-parent = <&gpio4>;
+		//interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+		//interrupt-names = "host-wake";
+	};
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>;
+	status = "okay";
+};
+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	status = "okay";
+};
+
+&pwm5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm5>;
+	status = "okay";
+};
+
+&pwm6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm6>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
index afd99a3fd9..81f8aea245 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6ull.dtsi>
+#include <arm/nxp/imx/imx6ull.dtsi>
 #include "imx6ul-phytec-phycore-som.dtsi"
 #include "imx6ul-phytec-state.dtsi"
 
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts
index 9c912df4de..b76b60220d 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6ull.dtsi>
+#include <arm/nxp/imx/imx6ull.dtsi>
 #include "imx6ul-phytec-phycore-som.dtsi"
 
 / {
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts
index 224e853e1a..3906e554d5 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts
@@ -8,7 +8,7 @@
 #ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
 #include CONFIG_BOOTM_FITIMAGE_PUBKEY
 #endif
-#include <arm/imx6ull.dtsi>
+#include <arm/nxp/imx/imx6ull.dtsi>
 #include "imx6ul-phytec-phycore-som.dtsi"
 #include "imx6ul-phytec-state.dtsi"
 
diff --git a/arch/arm/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/dts/imx6ull-tqma6ull2-mba6ulx.dts
new file mode 100644
index 0000000000..20eb7a7c1d
--- /dev/null
+++ b/arch/arm/dts/imx6ull-tqma6ull2-mba6ulx.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+
+#include <arm/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts>
+#include "imx6ul-tqma6ul-common.dtsi"
diff --git a/arch/arm/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/dts/imx6ull-tqma6ull2l-mba6ulx.dts
new file mode 100644
index 0000000000..58df3349c7
--- /dev/null
+++ b/arch/arm/dts/imx6ull-tqma6ull2l-mba6ulx.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+
+#include <arm/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts>
+#include "imx6ul-tqma6ul-common.dtsi"
diff --git a/arch/arm/dts/imx7.dtsi b/arch/arm/dts/imx7.dtsi
new file mode 100644
index 0000000000..1c67bdc546
--- /dev/null
+++ b/arch/arm/dts/imx7.dtsi
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include "imx7d-ddrc.dtsi"
+
+/ {
+	aliases {
+		gpr.reboot_mode = &reboot_mode_gpr;
+	};
+};
+
+&src {
+	compatible = "fsl,imx7d-src", "syscon", "simple-mfd";
+
+	reboot_mode_gpr: reboot-mode {
+		compatible = "barebox,syscon-reboot-mode";
+		offset = <0x94>, <0x98>; /* SRC_GPR{9,10} */
+		mask = <0xffffffff>, <0x40000000>;
+		mode-normal = <0>, <0>;
+		mode-serial = <0x00000010>, <0x40000000>;
+	};
+
+	ca7_reset: cortex-a7-reboot {
+		compatible = "syscon-reboot";
+		regmap = <&src>;
+		offset = <0x4>;
+		mask = <1>;
+		value = <1>;
+		/* This is not fit for use as general purpose reset */
+		restart-priority = <5>;
+		/*
+		 * Can't use imxwd-warm due to errata e10574:
+		 * Watchdog: A watchdog timeout or software trigger will
+		 * not reset the SOC
+		 */
+		barebox,restart-warm-bootrom;
+	};
+};
diff --git a/arch/arm/dts/imx7d-ac-sxb.dtsi b/arch/arm/dts/imx7d-ac-sxb.dtsi
index 00b0fd11c6..7154508d07 100644
--- a/arch/arm/dts/imx7d-ac-sxb.dtsi
+++ b/arch/arm/dts/imx7d-ac-sxb.dtsi
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <arm/imx7d.dtsi>
+#include <arm/nxp/imx/imx7d.dtsi>
 
 / {
 	model = "Atlas Copco SXB Board";
@@ -41,9 +41,15 @@
 	keep-power-in-suspend;
 	status = "okay";
 
-	usdhc1_sdcard: state@4100000 {
-		reg = <0x4100000 0xffffff>;
-		label = "state-sdcard";
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		usdhc1_sdcard: state@4100000 {
+			reg = <0x0 0x4100000 0x0 0xffffff>;
+			label = "state-sdcard";
+		};
 	};
 };
 
@@ -56,11 +62,16 @@
 	non-removable;
 	status = "okay";
 
-	usdhc3_emmc: usdhc3_emmc@1e800000 {
-		reg = <0x1e800000 0xffffff>;
-		label = "state-emmc";
-	};
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
 
+		usdhc3_emmc: usdhc3_emmc@1e800000 {
+			reg = <0x0 0x1e800000 0x0 0xffffff>;
+			label = "state-emmc";
+		};
+	};
 };
 
 &wdog1 {
diff --git a/arch/arm/dts/imx7d-ddrc.dtsi b/arch/arm/dts/imx7d-ddrc.dtsi
index b4cd597be9..875fff690b 100644
--- a/arch/arm/dts/imx7d-ddrc.dtsi
+++ b/arch/arm/dts/imx7d-ddrc.dtsi
@@ -1,10 +1,12 @@
 /*
  * Include file to switch board DTS form using hardcoded memory node
- * to dynamic memory size detection based on DDR controller settings
+ * (if specified) to dynamic memory size detection based on DDR
+ * controller settings
  */
 
 / {
 	/delete-node/ memory;
+	/delete-node/ memory@80000000;
 };
 
 &aips2 {
@@ -12,4 +14,4 @@
 		compatible = "fsl,imx7d-ddrc";
 		reg = <0x307a0000 0x10000>;
 	};
-};
\ No newline at end of file
+};
diff --git a/arch/arm/dts/imx7d-flex-concentrator-mfg.dts b/arch/arm/dts/imx7d-flex-concentrator-mfg.dts
index d174ef7250..4b150ba48c 100644
--- a/arch/arm/dts/imx7d-flex-concentrator-mfg.dts
+++ b/arch/arm/dts/imx7d-flex-concentrator-mfg.dts
@@ -7,7 +7,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx7d-flex-concentrator-mfg.dts>
+#include <arm/nxp/imx/imx7d-flex-concentrator-mfg.dts>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/imx7d-gome-e143_01.dts b/arch/arm/dts/imx7d-gome-e143_01.dts
new file mode 100644
index 0000000000..ea118ddc76
--- /dev/null
+++ b/arch/arm/dts/imx7d-gome-e143_01.dts
@@ -0,0 +1,119 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ * SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix
+ */
+
+/dts-v1/;
+
+#include "imx7d-gome-e143_01.kernel.dts"
+
+/ {
+	compatible = "gome,e143_01", "variscite,var-som-mx7", "fsl,imx7d";
+
+	aliases {
+		state = &state;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &emmc_env;
+		};
+	};
+
+	state: state {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		magic = <0x1929603f>;
+		compatible = "barebox,state";
+		backend-type = "raw";
+		backend = <&emmc_state>;
+		backend-stridesize = <0x80>;
+		backend-storage-type = "direct";
+
+		bootstate: bootstate {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			system0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@0 {
+					reg = <0x0 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+
+				priority@4 {
+					reg = <0x4 0x4>;
+					type = "uint32";
+					default = <10>;
+				};
+			};
+
+			system1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@8 {
+					reg = <0x8 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+
+				priority@c {
+					reg = <0xc 0x4>;
+					type = "uint32";
+					default = <20>;
+				};
+			};
+
+			last_chosen@10 {
+				reg = <0x10 0x4>;
+				type = "uint32";
+			};
+		};
+	};
+};
+
+&usdhc3 {
+	partitions {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fixed-partitions";
+
+		/** original storage layout:
+		offset     size  label
+		000000000  512   MBR
+		000000200  512   (empty)
+		000000400  68k   SPL
+		000011400  800k  u-boot
+		0000E0000  3.2M  u-boot-env (only first 8k are used)
+		000400000  2.9G  rootfs1
+		0BA400000  2.9G  rootfs2
+		174400000  1.5G  data
+		1D2000000        (end)
+
+		Keep the original layout for now for possible fallback to u-boot
+		later; put the storage for barebox-env and barebox-state
+		somewhere where it doesn't conflict with u-boot.
+		*/
+
+		emmc_state: partition@200000 {
+			label = "barebox-state";
+			reg = <0x200000 0x100000>;
+		};
+
+		emmc_env: partition@300000 {
+			label = "barebox-environment";
+			reg = <0x300000 0x100000>;
+		};
+	};
+};
+
+&{/leds2/led_netz_rt} {
+	barebox,default-trigger = "default-on";
+};
diff --git a/arch/arm/dts/imx7d-gome-e143_01.kernel.dts b/arch/arm/dts/imx7d-gome-e143_01.kernel.dts
new file mode 100644
index 0000000000..19c7a3d426
--- /dev/null
+++ b/arch/arm/dts/imx7d-gome-e143_01.kernel.dts
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/**
+ * Copyright (C) 2022 Gossen Metrawatt GmbH
+ * Copyright (C) 2022 Marco Felsch, Pengutronix
+ * Copyright (C) 2022 Philipp Zabel, Pengutronix
+ * Copyright (C) 2022 Roland Hieber, Pengutronix
+ */
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "imx7d-var-som-mx7.dtsi"
+
+/ {
+	model = "Gossen Metrawatt Profitest MF (e143_01)";
+	compatible = "gome,e143_01", "variscite,var-som-mx7", "fsl,imx7d";
+
+	aliases {
+		gpio7 = &gpio8;
+		rtc0 = &rtc0;
+	};
+
+	max98357a: audio-codec {
+		compatible = "maxim,max98357a";
+		#sound-dai-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sdmode>;
+		sdmode-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; // Pin 60 AUDIO_SHDN_B
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>, <&pinctrl_gpio_keys_2>;
+		autorepeat;
+
+		button-0 {
+			label = "S0";
+			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; // Pin 183 BTN_S0_ESC
+			linux,code = <KEY_ESC>;
+			wakeup-source;
+		};
+
+		button-1 {
+			label = "S1";
+			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; // Pin 185 BTN_S1_MEM
+			linux,code = <KEY_DOCUMENTS>;
+			wakeup-source;
+		};
+
+		button-2 {
+			label = "S2";
+			gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; // Pin 181 BTN_S2_HLP
+			linux,code = <KEY_HELP>;
+			wakeup-source;
+		};
+
+		button-3 {
+			label = "S3";
+			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; // Pin 1 BTN_S3_STA
+			linux,code = <KEY_PROG1>;
+			wakeup-source;
+		};
+
+		button-4 {
+			label = "S4";
+			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; // Pin 168 BTN_S4_IDN
+			linux,code = <KEY_PROG2>;
+			wakeup-source;
+		};
+
+		button-5 {
+			label = "S5";
+			gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; // Pin 28 BTN_S5
+			linux,code = <KEY_F5>;
+		};
+
+		button-6 {
+			label = "S6";
+			gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; // Pin 40 BTN_S6
+			linux,code = <KEY_F6>;
+		};
+
+		button-7 {
+			label = "S7";
+			gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; // Pin 38 BTN_S7
+			linux,code = <KEY_F7>;
+		};
+
+		button-8 {
+			label = "S8";
+			gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; // Pin 36 BTN_S8
+			linux,code = <KEY_F8>;
+		};
+
+		button-9 {
+			label = "S9";
+			gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; // Pin 20 BTN_S9
+			linux,code = <KEY_F9>;
+		};
+	};
+
+	gpio-poweroff {
+		compatible = "gpio-poweroff";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_poweroff>;
+		gpios = <&gpio7 14 GPIO_ACTIVE_LOW>; // Pin 7 POWER_OFF_B
+		input;
+	};
+
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels = <&adc2 0>, // ARS_VAL
+			      <&adc2 1>, // VBAT_VAL
+			      <&adc2 2>, // LCD_BACKLIGHT_VAL
+			      <&adc2 3>; // VCC_5V0_FB
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_debug_led>;
+
+		test-led-1 {
+			label = "test-led-1:red";
+			gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; // Pin 44 LED_TEST1_B
+			color = <LED_COLOR_ID_RED>;
+			linux,default-trigger = "disk-activity";
+		};
+
+		test-led-2 {
+			label = "test-led-2:red";
+			gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; // Pin 46 LED_TEST2_B
+			color = <LED_COLOR_ID_RED>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	leds2 {
+		compatible = "gpio-leds";
+
+		led_netz_gn {
+			label = "mains:green";
+			gpios = <&gpio8 9 GPIO_ACTIVE_LOW>; // LED_NETZ_GN
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led_netz_rt {
+			label = "mains:red";
+			gpios = <&gpio8 8 GPIO_ACTIVE_LOW>; // LED_NETZ_RT
+			color = <LED_COLOR_ID_RED>;
+			default-state = "on";
+		};
+
+		led_debug_gn {
+			label = "debug:green";
+			gpios = <&gpio8 0 GPIO_ACTIVE_LOW>; // LED_DEBUG_GN
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led_debug_rt {
+			label = "debug:red";
+			gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; // LED_DEBUG_RT
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led_ul_gn {
+			label = "ulrl:green";
+			gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; // LED_UL_GN
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led_ul_rt {
+			label = "ulrl:red";
+			gpios = <&gpio8 6 GPIO_ACTIVE_LOW>; // LED_UL_RT
+			color = <LED_COLOR_ID_RED>;
+			default-state = "on";
+		};
+
+		led_rcd_gn {
+			label = "rcd:green";
+			gpios = <&gpio8 3 GPIO_ACTIVE_LOW>; // LED_RCD_GN
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led_rcd_rt {
+			label = "rcd:red";
+			gpios = <&gpio8 7 GPIO_ACTIVE_LOW>; // LED_RCD_RT
+			color = <LED_COLOR_ID_RED>;
+			default-state = "on";
+		};
+	};
+
+	reg_vled_backlight: regulator-vled-backlight {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_mipi_backlight>;
+		regulator-name = "VLED_BACKLIGHT";
+		gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <20000000>;
+		regulator-max-microvolt = <20000000>;
+		enable-active-high;
+	};
+
+	reg_vcc_3v3_per: regulator-vcc-3v3-per {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_vcc_3v3_per>;
+		regulator-name = "VCC_3V3_PER";
+		gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; // Pin 83 VCC_3V3_PER_EN
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-enable-ramp-delay = <30000>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	reg_vcc_5v0_per: regulator-vcc-5v0-per {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_vcc_5v0_per>;
+		regulator-name = "VCC_5V0_PER";
+		gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; // Pin 75 VCC_5V0_PER_EN
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	reg_imt: regulator-imt {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_imt>;
+		regulator-name = "VCC_IMT";
+		gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>; // Pin 66 MT_EN
+		regulator-min-microvolt = <9000000>;
+		regulator-max-microvolt = <9000000>;
+		enable-active-high;
+	};
+
+	reg_vcc_1v8_alg: regulator-vcc-1v8-alg {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_1V8_ALG";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&reg_vcc_3v3_per>;
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "max98357aaudio";
+		/delete-property/ simple-audio-card,widgets;
+		/delete-property/ simple-audio-card,routing;
+		simple-audio-card,format = "i2s";
+
+		simple-audio-card,cpu {
+			sound-dai = <&sai3>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&max98357a>;
+		};
+	};
+
+	uc-imt-power {
+		compatible = "reg-userspace-consumer";
+		regulator-name = "reg_imt-consumer";
+		regulator-supplies = "vcc";
+		vcc-supply = <&reg_imt>;
+	};
+};
+
+&adc2 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+};
+
+&i2c2 {
+	/delete-node/ wm8731@1a;
+
+	/* DS1339 RTC module */
+	rtc0: rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_rtc>;
+		trickle-resistor-ohms = <250>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <13 GPIO_ACTIVE_LOW>; // Pin 120 RTC_INT_B
+		wakeup-source;
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio4 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; // Pin 175 I2C4_SCL
+	sda-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; // Pin 173 I2C4_SDA
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	gpio8: max7312@23 {
+		compatible = "maxim,max7312";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "LED_DEBUG_GN", "LED_DEBUG_RT", "LED_UL_GN", "LED_RCD_GN",
+				  "", "", "LED_UL_RT", "LED_RCD_RT",
+				  "LED_NETZ_RT", "LED_NETZ_GN", "", "",
+				  "DP_HW_CODE_1", "DP_HW_CODE_2", "DP_HW_CODE_3", "DP_HW_CODE_4";
+		vcc-supply = <&reg_vcc_3v3_per>;
+	};
+};
+
+&gpio1 {
+	gpio-line-names = "GWDOG_RST_B", "BTN_S3_STA", "BTN_S4_IDN", "",
+			  "", "", "", "USB_HOST_PWR_EN",
+			  "", "", "BTN_S2_HLP", "BTN_S1_MEM",
+			  "BTN_S0_ESC", "RTC_INT_B", "SOM: bt reg on";
+};
+
+&gpio2 {
+	gpio-line-names = "", "", "", "",
+			  "DBG_GPIO1", "DBG_GPIO2", "DBG_GPIO3", "DBG_GPIO4",
+			  "", "", "", "",
+			  "MT_RXD", "MT_TXD", "", "",
+			  "", "", "", "",
+			  "", "", "", "",
+			  "", "", "VCC_3V3_PER_EN", "",
+			  "DSI_RESET", "VCC_5V0_PER_EN";
+};
+
+&gpio3 {
+	gpio-line-names = "", "", "LED_TEST1_B", "LED_TEST2_B",
+			  "BTN_S8", "BTN_S6", "MT_RESET", "",
+			  "", "", "MT_EN", "",
+			  "", "", "", "",
+			  "", "", "", "",
+			  "AUDIO_SHDN_B", "", "BTN_S7", "",
+			  "BTN_S5", "", "", "BTN_S9",
+			  "BATT_LOW";
+};
+
+&gpio4 {
+	gpio-line-names = "", "", "", "",
+			  "", "", "", "",
+			  "I2C1_SCL", "I2C1_SDA", "I2C2_SCL", "I2C2_SDA",
+			  "", "", "I2C4_SCL", "I2C4_SDA",
+			  "", "", "", "",
+			  "", "", "", "HIL_SPI_CS0";
+};
+
+&gpio5 {
+	gpio-line-names = "", "", "", "",
+			  "", "", "", "",
+			  "", "", "", "SOM: ethphy0 reset";
+};
+
+&gpio6 {
+	gpio-line-names = "", "", "", "",
+			  "", "", "", "",
+			  "", "", "", "SOM: sd3_pwr (eMMC)";
+};
+
+&gpio7 {
+	gpio-line-names = "", "", "", "",
+			  "", "", "", "",
+			  "", "", "", "",
+			  "LCD_BACKLIGHT_EN", "", "POWER_OFF_B";
+};
+
+&lcdif {
+	assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>,
+			  <&clks IMX7D_PLL_VIDEO_POST_DIV>;
+	assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>;
+	assigned-clock-rates = <0>, <128000000>;
+	fsl,ocram = <&ocram>;
+	fsl,pxp = <&pxp>;
+	status = "okay";
+};
+
+&mipi_dsi {
+	samsung,burst-clock-frequency = <850000000>;
+	status = "okay";
+
+	panel@0 {
+		compatible = "tianma,tm050jdhg33", "ilitek,ili9881c";
+		reg = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_mipi_panel>;
+		reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; // Pin 73 DSI_RESET
+		power-supply = <&reg_vcc_3v3_per>;
+		dsi-lanes = <2>;
+
+		rotation = <90>;
+
+		ilitek,enable-internal-backlight;
+		default-brightness = <2047>;
+		ilitek,pwm-frequency = <50000>;
+		ilitek,backlight-supply = <&reg_vled_backlight>;
+	};
+};
+
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3>;
+	assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
+			  <&clks IMX7D_SAI3_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+	assigned-clock-rates = <0>, <36864000>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart7>;
+	status = "okay";
+};
+
+&usbotg1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbotg2 {
+	status = "okay";
+};
+
+&iomuxc_lpsr {
+	pinctrl_gpio_keys_2: pinctrl_gpio_keys_2grp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1        0x0C
+			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2        0x0C
+		>;
+	};
+
+	pinctrl_usbotg2_pwr: pinctrl_usbotg2_pwrgrp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7        0x14
+		>;
+	};
+};
+
+&iomuxc {
+	pinctrl_gpio_keys: pinctrl-gpio-keysgrp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO10__GPIO1_IO10            0x0000000C
+			MX7D_PAD_GPIO1_IO11__GPIO1_IO11            0x0000000C
+			MX7D_PAD_GPIO1_IO12__GPIO1_IO12            0x0000000C
+			MX7D_PAD_LCD_DATA00__GPIO3_IO5             0x0000000C
+			MX7D_PAD_LCD_DATA17__GPIO3_IO22            0x0000000C
+			MX7D_PAD_LCD_DATA19__GPIO3_IO24            0x0000000C
+			MX7D_PAD_LCD_DATA22__GPIO3_IO27            0x0000000C
+			MX7D_PAD_LCD_RESET__GPIO3_IO4              0x0000000C
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX7D_PAD_I2C4_SCL__I2C4_SCL                0x4000007f
+			MX7D_PAD_I2C4_SDA__I2C4_SDA                0x4000007f
+		>;
+	};
+
+	pinctrl_i2c4_gpio: i2c4-gpiogrp {
+		fsl,pins = <
+			MX7D_PAD_I2C4_SCL__GPIO4_IO14              0x4000007f
+			MX7D_PAD_I2C4_SDA__GPIO4_IO15              0x4000007f
+		>;
+	};
+
+	pinctrl_mipi_backlight: mipi-backlightgrp {
+		fsl,pins = <
+			MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12          0x0000001B
+		>;
+	};
+
+	pinctrl_mipi_panel: mipi-panelgrp {
+		fsl,pins = <
+			MX7D_PAD_EPDC_BDR0__GPIO2_IO28             0x0000001B /* DSI_RESET */
+		>;
+	};
+
+	pinctrl_poweroff: pinctrl_poweroffgrp {
+		fsl,pins = <
+			MX7D_PAD_ENET1_CRS__GPIO7_IO14             0x0000001B
+		>;
+	};
+
+	pinctrl_reg_vcc_3v3_per: pinctrl_reg_vcc_3v3_pergrp {
+		fsl,pins = <
+			MX7D_PAD_EPDC_GDRL__GPIO2_IO26             0x0000001B
+		>;
+	};
+
+	pinctrl_reg_vcc_5v0_per: pinctrl_reg_vcc_5v0_pergrp {
+		fsl,pins = <
+			MX7D_PAD_EPDC_BDR1__GPIO2_IO29             0x0000001B
+		>;
+	};
+
+	pinctrl_reg_imt: pinctrl_reg_imtgrp {
+		fsl,pins = <
+			MX7D_PAD_LCD_DATA05__GPIO3_IO10            0x0000001B
+		>;
+	};
+
+	pinctrl_rtc: pinctrl_rtcgrp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO13__GPIO1_IO13            0x0000001B
+		>;
+	};
+
+	pinctrl_sai3: pinctrl_sai3grp {
+		fsl,pins = <
+			MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK           0x0000001F
+			MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC           0x0000001F
+			MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0          0x00000030
+		>;
+	};
+
+	pinctrl_sdmode: pinctrl_sdmodegrp {
+		fsl,pins = <
+			MX7D_PAD_LCD_DATA15__GPIO3_IO20            0x0000001F
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79 /* DEBUG_UART1_TXD */
+			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79 /* DEBUG_UART1_RXD */
+		>;
+	};
+
+	pinctrl_uart7: uart7grp {
+		fsl,pins = <
+			MX7D_PAD_EPDC_DATA12__UART7_DCE_RX	0x79
+			MX7D_PAD_EPDC_DATA13__UART7_DCE_TX	0x79
+		>;
+	};
+
+	pinctrl_debug_led: pinctrl_debug_ledgrp {
+		fsl,pins = <
+			MX7D_PAD_LCD_HSYNC__GPIO3_IO2              0x00000003
+			MX7D_PAD_LCD_VSYNC__GPIO3_IO3              0x00000003
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx7d-meerkat96.dts b/arch/arm/dts/imx7d-meerkat96.dts
new file mode 100644
index 0000000000..da3a3a6dfc
--- /dev/null
+++ b/arch/arm/dts/imx7d-meerkat96.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+#include <arm/nxp/imx/imx7d-meerkat96.dts>
+
+/ {
+	chosen {
+		environment {
+			compatible = "barebox,environment";
+			device-path = &bareboxenv;
+		};
+	};
+};
+
+&usdhc1 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	barebox@0 {
+		label = "barebox";
+		reg = <0x0 0x180000>;
+	};
+
+	bareboxenv: bareboxenv@180000 {
+		label = "bareboxenv";
+		reg = <0x180000 0x80000>;
+	};
+};
+
+/* FIXME: barebox serial is broken when barebox applies requested reparenting */
+&uart1 {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+};
+
+&uart3  {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+};
+
+&uart6 {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+};
diff --git a/arch/arm/dts/imx7d-peb-av-02.dtsi b/arch/arm/dts/imx7d-peb-av-02.dtsi
index dcf117c71a..2e5af755bb 100644
--- a/arch/arm/dts/imx7d-peb-av-02.dtsi
+++ b/arch/arm/dts/imx7d-peb-av-02.dtsi
@@ -72,7 +72,7 @@
 	lcd-supply = <&lcd_3v3>;
 	status = "disabled";
 
-	display0: display {
+	display0: display0 {
 		bits-per-pixel = <32>;
 		bus-width = <24>;
 
diff --git a/arch/arm/dts/imx7d-peb-eval-02.dtsi b/arch/arm/dts/imx7d-peb-eval-02.dtsi
index 8bde5b13e7..fee0c5972d 100644
--- a/arch/arm/dts/imx7d-peb-eval-02.dtsi
+++ b/arch/arm/dts/imx7d-peb-eval-02.dtsi
@@ -13,21 +13,21 @@
 		pinctrl-0 = <&pinctrl_leds_eval>;
 		status = "disabled";
 
-		led@0 {
+		led-0 {
 			label = "eval_led_1";
 			gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "gpio";
 			default-state = "on";
 		};
 
-		led@1 {
+		led-1 {
 			label = "eval_led_2";
 			gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "gpio";
 			default-state = "on";
 		};
 
-		led@2 {
+		led-2 {
 			label = "eval_led_3";
 			gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "gpio";
@@ -41,18 +41,18 @@
 		pinctrl-0 = <&pinctrl_btns_eval>;
 		status = "disabled";
 
-		userbtn@0 {
+		userbtn-0 {
 			label = "eval_button_1";
 			gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
 			linux,code = <0x100>;	/* BTN_MISC */
 		};
-		userbtn@1 {
+		userbtn-1 {
 			label = "eval_button_2";
 			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
 			linux,code = <0x100>;   /* BTN_MISC */
 		};
 
-		userbtn@2 {
+		userbtn-2 {
 			label = "eval_button_3";
 			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 			linux,code = <0x100>;	/* BTN_MISC */
diff --git a/arch/arm/dts/imx7d-phycore-som.dtsi b/arch/arm/dts/imx7d-phycore-som.dtsi
index e892a54bdd..2dedac83bd 100644
--- a/arch/arm/dts/imx7d-phycore-som.dtsi
+++ b/arch/arm/dts/imx7d-phycore-som.dtsi
@@ -7,7 +7,7 @@
  */
 
 #include <dt-bindings/input/input.h>
-#include <arm/imx7d.dtsi>
+#include <arm/nxp/imx/imx7d.dtsi>
 
 / {
 	model = "Phytec i.MX7D phyCORE";
diff --git a/arch/arm/dts/imx7d-pinfunc.kernel.h b/arch/arm/dts/imx7d-pinfunc.kernel.h
new file mode 100644
index 0000000000..141192404b
--- /dev/null
+++ b/arch/arm/dts/imx7d-pinfunc.kernel.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DTS_IMX7D_PINFUNC_KERNEL_H
+#define __DTS_IMX7D_PINFUNC_KERNEL_H
+
+#define MX7D_PAD_LPSR_GPIO1_IO03__OSC32K_32K_OUT                  0x000C 0x003C 0x0000 0x4 0x0
+
+#endif /* __DTS_IMX7D_PINFUNC_KERNEL_H */
diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts
index 7beb065920..b947e44634 100644
--- a/arch/arm/dts/imx7d-sdb.dts
+++ b/arch/arm/dts/imx7d-sdb.dts
@@ -7,7 +7,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx7d-sdb.dts>
+#include <arm/nxp/imx/imx7d-sdb.dts>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/imx7d-var-som-mx7.dtsi b/arch/arm/dts/imx7d-var-som-mx7.dtsi
new file mode 100644
index 0000000000..029f874e89
--- /dev/null
+++ b/arch/arm/dts/imx7d-var-som-mx7.dtsi
@@ -0,0 +1,6 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ * SPDX-FileCopyrightText: 2023 Roland Hieber, Pengutronix <rhi@pengutronix.de>
+ */
+#include "imx7d-var-som-mx7.kernel.dtsi"
+#include "imx7d-ddrc.dtsi"
diff --git a/arch/arm/dts/imx7d-var-som-mx7.kernel.dtsi b/arch/arm/dts/imx7d-var-som-mx7.kernel.dtsi
new file mode 100644
index 0000000000..591436ffc6
--- /dev/null
+++ b/arch/arm/dts/imx7d-var-som-mx7.kernel.dtsi
@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016-2017 Variscite Ltd.
+ * Copyright (C) 2022 Philipp Zabel, Pengutronix
+ * Copyright (C) 2022 Roland Hieber, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/input/input.h>
+#include "imx7d.kernel.dtsi"
+
+/ {
+	model = "Variscite i.MX7 Dual VAR-SOM-MX7";
+	compatible = "variscite,var-som-mx7", "fsl,imx7d";
+
+	reg_vref_1v8: regulator-vref-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vref-1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	reg_usb_otg1_vbus: regulator-usbotg1-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+		regulator-name = "usb_otg1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usb_otg2_vbus: regulator-usbotg2-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbotg2_vbus>;
+		regulator-name = "usb_otg2_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	wlreg_on: regulator-wlreg-on {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "wlreg_on";
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "wm8731audio";
+		simple-audio-card,widgets =
+			"Headphone", "Headphone Jack",
+			"Line", "Line Jack",
+			"Microphone", "Mic Jack";
+		simple-audio-card,routing =
+			"Headphone Jack", "RHPOUT",
+			"Headphone Jack", "LHPOUT",
+			"LLINEIN", "Line Jack",
+			"RLINEIN", "Line Jack",
+			"MICIN", "Mic Bias",
+			"Mic Bias", "Mic Jack";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&sound_master>;
+		simple-audio-card,frame-master = <&sound_master>;
+
+		sound_master: simple-audio-card,cpu {
+			sound-dai = <&sai1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&wm8731>;
+			system-clock-frequency = <12288000>;
+		};
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+};
+
+&adc2 {
+	vref-supply = <&reg_vref_1v8>;
+};
+
+&cpu0 {
+	cpu-supply = <&sw1a_reg>;
+};
+
+&cpu1 {
+	cpu-supply = <&sw1a_reg>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-supply = <&vgen3_reg>;
+	assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
+			  <&clks IMX7D_ENET_AXI_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+			  <&clks IMX7D_ENET_AXI_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
+				 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	phy-reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+	phy-reset-post-delay = <20>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-supply = <&vgen3_reg>;
+	assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
+			  <&clks IMX7D_ENET_AXI_ROOT_SRC>,
+			  <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
+			  <&clks IMX7D_ENET_AXI_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
+				 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy1>;
+	phy-reset-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
+	phy-reset-post-delay = <20>;
+};
+
+&gpio6 {
+	sd3-pwr-hog {
+		gpio-hog;
+		gpios = <11 0>;
+		output-low;
+		line-name = "sd3_pwr";
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pmic@8 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				status = "disabled";
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <2850000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	eeprom@50 {
+		compatible = "rohm,br24g04", "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
+		num-addresses = <2>;
+		address-width = <8>;
+		read-only;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	wm8731: wm8731@1a {
+		#sound-dai-cells = <0>;
+		AVDD-supply = <&vgen6_reg>;
+		HPVDD-supply = <&vgen6_reg>;
+		DBVDD-supply = <&vgen6_reg>;
+		DCVDD-supply = <&vgen6_reg>;
+		compatible = "wlf,wm8731";
+		reg = <0x1a>;
+		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+		clock-names = "mclk";
+		assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
+				  <&clks IMX7D_PLL_AUDIO_POST_DIV>,
+				  <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
+		assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+		assigned-clock-rates = <0>, <884736000>, <12288000>;
+	};
+};
+
+&sai1 {
+	assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
+			  <&clks IMX7D_PLL_AUDIO_POST_DIV>,
+			  <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
+	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+	assigned-clock-rates = <0>, <884736000>, <12288000>;
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&snvs_rtc {
+	status = "disabled";
+};
+
+&uart1 {
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+};
+
+&uart2 {
+	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+};
+
+&uart3 {
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	dr_mode = "host";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	dr_mode = "host";
+};
+
+&usdhc2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_wlan>, <&pinctrl_bt>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_wlan>, <&pinctrl_bt>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_wlan>, <&pinctrl_bt>;
+	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_wlan_sleep>, <&pinctrl_bt_sleep>;
+	keep-power-in-suspend;
+	non-removable;
+	vmmc-supply = <&wlreg_on>;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3_ctrl>, <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_ctrl>, <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_ctrl>, <&pinctrl_usdhc3_200mhz>;
+	vmmc-supply = <&vgen3_reg>;
+	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+	assigned-clock-rates = <400000000>;
+	no-1-8-v;
+	no-sdio;
+	no-sd;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+};
+
+&iomuxc_lpsr {
+	pinctrl_usbotg1_vbus: usbotg1-vbusgrp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5		0x14
+		>;
+	};
+
+	pinctrl_usbotg2_vbus: usbotg2-vbusgrp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7		0x14
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B		0x74
+		>;
+	};
+
+	pinctrl_wlan: wlangrp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4		0x09 /* WL_REG_ON */
+			MX7D_PAD_LPSR_GPIO1_IO03__OSC32K_32K_OUT	0xb0 /* WIFI Slow clock */
+		>;
+	};
+
+	pinctrl_wlan_sleep: wlan-sleepgrp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4		0x10 /* WL_REG_ON */
+			MX7D_PAD_LPSR_GPIO1_IO03__OSC32K_32K_OUT	0x10 /* WIFI Slow clock */
+		>;
+	};
+};
+
+&iomuxc {
+
+	pinctrl_bt: btgrp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO14__GPIO1_IO14		0x80000000  /* bt reg on */
+		>;
+	};
+
+	pinctrl_bt_sleep: bt-sleepgrp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO14__GPIO1_IO14			0x10  /* bt reg on */
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3
+			MX7D_PAD_SD2_WP__ENET1_MDC			0x3
+			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
+			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
+			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
+			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
+			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
+			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
+			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
+			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
+			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
+			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
+			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
+			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
+			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x59  /* ethphy0 reset */
+		>;
+	};
+
+	pinctrl_enet2: enet2grp {
+		fsl,pins = <
+			MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x1
+			MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x1
+			MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x1
+			MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x1
+			MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x1
+			MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x1
+			MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x1
+			MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x1
+			MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x1
+			MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x1
+			MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x1
+			MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL		0x1
+			MX7D_PAD_UART2_TX_DATA__GPIO4_IO3	0x59  /* ethphy1 reset */
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX7D_PAD_I2C1_SDA__I2C1_SDA	0x4000007f
+			MX7D_PAD_I2C1_SCL__I2C1_SCL	0x4000007f
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1gpiogrp {
+		fsl,pins = <
+			MX7D_PAD_I2C1_SDA__GPIO4_IO9	0x4000007f
+			MX7D_PAD_I2C1_SCL__GPIO4_IO8	0x4000007f
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX7D_PAD_I2C2_SDA__I2C2_SDA	0x4000007f
+			MX7D_PAD_I2C2_SCL__I2C2_SCL	0x4000007f
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2gpiogrp {
+		fsl,pins = <
+			MX7D_PAD_I2C2_SDA__GPIO4_IO11	0x4000007f
+			MX7D_PAD_I2C2_SCL__GPIO4_IO10	0x4000007f
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
+			MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
+			MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS     0x79
+			MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS     0x79
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX7D_PAD_SD2_CMD__SD2_CMD		0x59
+			MX7D_PAD_SD2_CLK__SD2_CLK		0x19
+			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
+			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
+			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
+			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD2_CMD__SD2_CMD		0x5a
+			MX7D_PAD_SD2_CLK__SD2_CLK		0x1a
+			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5a
+			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5a
+			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5a
+			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5a
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD2_CMD__SD2_CMD		0x5b
+			MX7D_PAD_SD2_CLK__SD2_CLK		0x1b
+			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5b
+			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5b
+			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5b
+			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5b
+		>;
+	};
+
+	pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
+		fsl,pins = <
+			MX7D_PAD_SD2_CMD__GPIO5_IO13		0x10
+			MX7D_PAD_SD2_CLK__GPIO5_IO12		0x10
+			MX7D_PAD_SD2_DATA0__GPIO5_IO14		0x10
+			MX7D_PAD_SD2_DATA1__GPIO5_IO15		0x10
+			MX7D_PAD_SD2_DATA2__GPIO5_IO16		0x10
+			MX7D_PAD_SD2_DATA3__GPIO5_IO17		0x10
+		>;
+	};
+
+	pinctrl_usdhc3_ctrl: usdhc3-ctrlgrp {
+		fsl,pins = <
+			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x59
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
+			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
+			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
+			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
+			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
+			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
+			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
+			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
+			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
+			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
+			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
+			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
+			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
+			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
+			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
+			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
+			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
+			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
+			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
+			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
+			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
+			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
+			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
+			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
+			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
+			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
+			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
+			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx7d-zii-rmu2.dts b/arch/arm/dts/imx7d-zii-rmu2.dts
index 41566f54a1..64da9cf55d 100644
--- a/arch/arm/dts/imx7d-zii-rmu2.dts
+++ b/arch/arm/dts/imx7d-zii-rmu2.dts
@@ -4,7 +4,7 @@
  * Copyright (C) 2019 Zodiac Inflight Innovations
  */
 
-#include <arm/imx7d-zii-rmu2.dts>
+#include <arm/nxp/imx/imx7d-zii-rmu2.dts>
 #include "imx7d-ddrc.dtsi"
 
 /* FIXME: barebox serial is broken when barebox applies requested reparenting */
@@ -18,37 +18,28 @@
 	/delete-property/ assigned-clock-parents;
 };
 
-&ecspi1 {
-	nor_flash: flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
+nor_flash: &{ecspi1/flash@0} {
+	#address-cells = <1>;
+	#size-cells = <1>;
 
-		partition@0 {
-			label = "barebox";
-			reg = <0x0 0xc0000>;
-		};
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xc0000>;
+	};
 
-		partition@c0000 {
-			label = "barebox-environment";
-			reg = <0xc0000 0x40000>;
-		};
+	partition@c0000 {
+		label = "barebox-environment";
+		reg = <0xc0000 0x40000>;
 	};
 };
 
-&uart4 {
-	rave-sp {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		watchdog {
-			nvmem-cells = <&boot_source>;
-			nvmem-cell-names = "boot-source";
-		};
-
-		eeprom@a3 {
-			boot_source: boot-source@83 {
-				reg = <0x83 1>;
-			};
-		};
+&{uart4/mcu/watchdog} {
+	nvmem-cells = <&boot_source>;
+	nvmem-cell-names = "boot-source";
+};
+
+&{uart4/mcu/eeprom@a3} {
+	boot_source: boot-source@83 {
+		reg = <0x83 1>;
 	};
 };
diff --git a/arch/arm/dts/imx7d-zii-rpu2.dts b/arch/arm/dts/imx7d-zii-rpu2.dts
index 58b22aa8e8..d8a5ffd194 100644
--- a/arch/arm/dts/imx7d-zii-rpu2.dts
+++ b/arch/arm/dts/imx7d-zii-rpu2.dts
@@ -3,7 +3,7 @@
 /*
  * Copyright (C) 2018 Zodiac Inflight Innovations
  */
-#include <arm/imx7d-zii-rpu2.dts>
+#include <arm/nxp/imx/imx7d-zii-rpu2.dts>
 
 #include "imx7d-ddrc.dtsi"
 
diff --git a/arch/arm/dts/imx7d.kernel.dtsi b/arch/arm/dts/imx7d.kernel.dtsi
new file mode 100644
index 0000000000..bc066b71a3
--- /dev/null
+++ b/arch/arm/dts/imx7d.kernel.dtsi
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Freescale Semiconductor, Inc.
+// Copyright 2016 Toradex AG
+
+#include "imx7s.kernel.dtsi"
+#include <dt-bindings/reset/imx7-reset.h>
+
+/ {
+	aliases {
+		usb0 = &usbotg1;
+		usb1 = &usbotg2;
+		usb2 = &usbh;
+	};
+
+	cpus {
+		cpu0: cpu@0 {
+			clock-frequency = <996000000>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
+			nvmem-cells = <&fuse_grade>;
+			nvmem-cell-names = "speed_grade";
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <1>;
+			clock-frequency = <996000000>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
+			cpu-idle-states = <&cpu_sleep_wait>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	cpu0_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-792000000 {
+			opp-hz = /bits/ 64 <792000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <150000>;
+			opp-supported-hw = <0xd>, <0x7>;
+			opp-suspend;
+		};
+
+		opp-996000000 {
+			opp-hz = /bits/ 64 <996000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <150000>;
+			opp-supported-hw = <0xc>, <0x7>;
+			opp-suspend;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1225000>;
+			clock-latency-ns = <150000>;
+			opp-supported-hw = <0x8>, <0x3>;
+			opp-suspend;
+		};
+	};
+
+	usbphynop2: usbphynop2 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clks IMX7D_USB_PHY2_CLK>;
+		clock-names = "main_clk";
+		#phy-cells = <0>;
+	};
+
+	soc: soc {
+		etm@3007d000 {
+			compatible = "arm,coresight-etm3x", "arm,primecell";
+			reg = <0x3007d000 0x1000>;
+
+			/*
+			 * System will hang if added nosmp in kernel command line
+			 * without arm,primecell-periphid because amba bus try to
+			 * read id and core1 power off at this time.
+			 */
+			arm,primecell-periphid = <0xbb956>;
+			cpu = <&cpu1>;
+			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm1_out_port: endpoint {
+						remote-endpoint = <&ca_funnel_in_port1>;
+					};
+				};
+			};
+		};
+
+		intc: interrupt-controller@31001000 {
+			compatible = "arm,cortex-a7-gic";
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupt-parent = <&intc>;
+			reg = <0x31001000 0x1000>,
+			      <0x31002000 0x2000>,
+			      <0x31004000 0x2000>,
+			      <0x31006000 0x2000>;
+		};
+
+		pcie: pcie@33800000 {
+			compatible = "fsl,imx7d-pcie";
+			reg = <0x33800000 0x4000>,
+			      <0x4ff00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000>, /* downstream I/O */
+				 <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			/*
+			 * Reference manual lists pci irqs incorrectly
+			 * Real hardware ordering is same as imx6: D+MSI, C, B, A
+			 */
+			interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
+				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
+				 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
+			clock-names = "pcie", "pcie_bus", "pcie_phy";
+			assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
+					  <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
+			assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+						 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+
+			fsl,max-link-speed = <2>;
+			power-domains = <&pgc_pcie_phy>;
+			resets = <&src IMX7_RESET_PCIEPHY>,
+				 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "pciephy", "apps", "turnoff";
+			fsl,imx7d-pcie-phy = <&pcie_phy>;
+			status = "disabled";
+		};
+	};
+};
+
+&aips2 {
+	pcie_phy: pcie-phy@306d0000 {
+		  compatible = "fsl,imx7d-pcie-phy";
+		  reg = <0x306d0000 0x10000>;
+		  status = "disabled";
+	};
+
+	pxp: pxp@30700000 {
+		compatible = "fsl,imx7d-pxp";
+		reg = <0x30700000 0x10000>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_PXP_CLK>;
+		clock-names = "axi";
+	};
+};
+
+&aips3 {
+	usbotg2: usb@30b20000 {
+		compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+		reg = <0x30b20000 0x200>;
+		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_USB_CTRL_CLK>;
+		fsl,usbphy = <&usbphynop2>;
+		fsl,usbmisc = <&usbmisc2 0>;
+		phy-clkgate-delay-us = <400>;
+		status = "disabled";
+	};
+
+	usbmisc2: usbmisc@30b20200 {
+		#index-cells = <1>;
+		compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+		reg = <0x30b20200 0x200>;
+	};
+
+	fec2: ethernet@30bf0000 {
+		compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
+		reg = <0x30bf0000 0x10000>;
+		interrupt-names = "int0", "int1", "int2", "pps";
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
+			<&clks IMX7D_ENET_AXI_ROOT_CLK>,
+			<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
+			<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
+			<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+		clock-names = "ipg", "ahb", "ptp",
+			"enet_clk_ref", "enet_out";
+		fsl,num-tx-queues = <3>;
+		fsl,num-rx-queues = <3>;
+		fsl,stop-mode = <&gpr 0x10 4>;
+		status = "disabled";
+	};
+};
+
+&ca_funnel_in_ports {
+	port@1 {
+		reg = <1>;
+		ca_funnel_in_port1: endpoint {
+			remote-endpoint = <&etm1_out_port>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx7s-warp.dts b/arch/arm/dts/imx7s-warp.dts
index 8e645999cf..3cae11b6a2 100644
--- a/arch/arm/dts/imx7s-warp.dts
+++ b/arch/arm/dts/imx7s-warp.dts
@@ -7,7 +7,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <arm/imx7s-warp.dts>
+#include <arm/nxp/imx/imx7s-warp.dts>
 
 / {
 	chosen {
diff --git a/arch/arm/dts/imx7s.kernel.dtsi b/arch/arm/dts/imx7s.kernel.dtsi
new file mode 100644
index 0000000000..6ea9e05f7b
--- /dev/null
+++ b/arch/arm/dts/imx7s.kernel.dtsi
@@ -0,0 +1,1354 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Freescale Semiconductor, Inc.
+// Copyright 2016 Toradex AG
+
+#include <dt-bindings/clock/imx7d-clock.h>
+#include <dt-bindings/power/imx7-power.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/imx7-reset.h>
+#include <arm/nxp/imx/imx7d-pinfunc.h>
+#include "imx7d-pinfunc.kernel.h"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	/*
+	 * The decompressor and also some bootloaders rely on a
+	 * pre-existing /chosen node to be available to insert the
+	 * command line and merge other ATAGS info.
+	 */
+	chosen {};
+
+	aliases {
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		gpio6 = &gpio7;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
+		i2c3 = &i2c4;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		serial4 = &uart5;
+		serial5 = &uart6;
+		serial6 = &uart7;
+		spi0 = &ecspi1;
+		spi1 = &ecspi2;
+		spi2 = &ecspi3;
+		spi3 = &ecspi4;
+		usb0 = &usbotg1;
+		usb1 = &usbh;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu_sleep_wait: cpu-sleep-wait {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <100>;
+				exit-latency-us = <50>;
+				min-residency-us = <1000>;
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+			clock-frequency = <792000000>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clks IMX7D_CLK_ARM>;
+			cpu-idle-states = <&cpu_sleep_wait>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
+			nvmem-cells = <&fuse_grade>;
+			nvmem-cell-names = "speed_grade";
+		};
+	};
+
+	cpu0_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-792000000 {
+			opp-hz = /bits/ 64 <792000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <150000>;
+			opp-supported-hw = <0xf>, <0xf>;
+		};
+	};
+
+	ckil: clock-cki {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "ckil";
+	};
+
+	osc: clock-osc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "osc";
+	};
+
+	usbphynop1: usbphynop1 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clks IMX7D_USB_PHY1_CLK>;
+		clock-names = "main_clk";
+		#phy-cells = <0>;
+	};
+
+	usbphynop3: usbphynop3 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
+		clock-names = "main_clk";
+		power-domains = <&pgc_hsic_phy>;
+		#phy-cells = <0>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupt-parent = <&gpc>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>;
+	};
+
+	replicator {
+		/*
+		 * non-configurable replicators don't show up on the
+		 * AMBA bus.  As such no need to add "arm,primecell"
+		 */
+		compatible = "arm,coresight-static-replicator";
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+				/* replicator output ports */
+			port@0 {
+				reg = <0>;
+				replicator_out_port0: endpoint {
+					remote-endpoint = <&tpiu_in_port>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator_out_port1: endpoint {
+					remote-endpoint = <&etr_in_port>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				replicator_in_port0: endpoint {
+					remote-endpoint = <&etf_out_port>;
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		arm,cpu-registers-not-fw-configured;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc: soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gpc>;
+		ranges;
+
+		ocram: sram@900000 {
+			compatible = "mmio-sram";
+			reg = <0x00900000 0x20000>;
+			ranges = <0 0x00900000 0x20000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&clks IMX7D_OCRAM_CLK>;
+		};
+
+		funnel@30041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x30041000 0x1000>;
+			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+			clock-names = "apb_pclk";
+
+			ca_funnel_in_ports: in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					ca_funnel_in_port0: endpoint {
+						remote-endpoint = <&etm0_out_port>;
+					};
+				};
+
+				/* the other input ports are not connect to anything */
+			};
+
+			out-ports {
+				port {
+					ca_funnel_out_port0: endpoint {
+						remote-endpoint = <&hugo_funnel_in_port0>;
+					};
+				};
+
+			};
+		};
+
+		etm@3007c000 {
+			compatible = "arm,coresight-etm3x", "arm,primecell";
+			reg = <0x3007c000 0x1000>;
+			cpu = <&cpu0>;
+			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm0_out_port: endpoint {
+						remote-endpoint = <&ca_funnel_in_port0>;
+					};
+				};
+			};
+		};
+
+		funnel@30083000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x30083000 0x1000>;
+			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					hugo_funnel_in_port0: endpoint {
+						remote-endpoint = <&ca_funnel_out_port0>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					hugo_funnel_in_port1: endpoint {
+						/* M4 input */
+					};
+				};
+				/* the other input ports are not connect to anything */
+			};
+
+			out-ports {
+				port {
+					hugo_funnel_out_port0: endpoint {
+						remote-endpoint = <&etf_in_port>;
+					};
+				};
+			};
+		};
+
+		etf@30084000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x30084000 0x1000>;
+			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					etf_in_port: endpoint {
+						remote-endpoint = <&hugo_funnel_out_port0>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etf_out_port: endpoint {
+						remote-endpoint = <&replicator_in_port0>;
+					};
+				};
+			};
+		};
+
+		etr@30086000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x30086000 0x1000>;
+			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					etr_in_port: endpoint {
+						remote-endpoint = <&replicator_out_port1>;
+					};
+				};
+			};
+		};
+
+		tpiu@30087000 {
+			compatible = "arm,coresight-tpiu", "arm,primecell";
+			reg = <0x30087000 0x1000>;
+			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tpiu_in_port: endpoint {
+						remote-endpoint = <&replicator_out_port0>;
+					};
+				};
+			};
+		};
+
+		intc: interrupt-controller@31001000 {
+			compatible = "arm,cortex-a7-gic";
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupt-parent = <&intc>;
+			reg = <0x31001000 0x1000>,
+			      <0x31002000 0x2000>,
+			      <0x31004000 0x2000>,
+			      <0x31006000 0x2000>;
+		};
+
+		aips1: bus@30000000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x30000000 0x400000>;
+			ranges;
+
+			gpio1: gpio@30200000 {
+				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+				reg = <0x30200000 0x10000>;
+				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
+					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
+			};
+
+			gpio2: gpio@30210000 {
+				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+				reg = <0x30210000 0x10000>;
+				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 13 32>;
+			};
+
+			gpio3: gpio@30220000 {
+				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+				reg = <0x30220000 0x10000>;
+				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 45 29>;
+			};
+
+			gpio4: gpio@30230000 {
+				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+				reg = <0x30230000 0x10000>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 74 24>;
+			};
+
+			gpio5: gpio@30240000 {
+				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+				reg = <0x30240000 0x10000>;
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 98 18>;
+			};
+
+			gpio6: gpio@30250000 {
+				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+				reg = <0x30250000 0x10000>;
+				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 116 23>;
+			};
+
+			gpio7: gpio@30260000 {
+				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+				reg = <0x30260000 0x10000>;
+				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 139 16>;
+			};
+
+			wdog1: watchdog@30280000 {
+				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+				reg = <0x30280000 0x10000>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
+			};
+
+			wdog2: watchdog@30290000 {
+				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+				reg = <0x30290000 0x10000>;
+				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			wdog3: watchdog@302a0000 {
+				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+				reg = <0x302a0000 0x10000>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			wdog4: watchdog@302b0000 {
+				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+				reg = <0x302b0000 0x10000>;
+				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			iomuxc_lpsr: pinctrl@302c0000 {
+				compatible = "fsl,imx7d-iomuxc-lpsr";
+				reg = <0x302c0000 0x10000>;
+				fsl,input-sel = <&iomuxc>;
+			};
+
+			gpt1: timer@302d0000 {
+				compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
+				reg = <0x302d0000 0x10000>;
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
+					 <&clks IMX7D_GPT1_ROOT_CLK>;
+				clock-names = "ipg", "per";
+			};
+
+			gpt2: timer@302e0000 {
+				compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
+				reg = <0x302e0000 0x10000>;
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
+					 <&clks IMX7D_GPT2_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			gpt3: timer@302f0000 {
+				compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
+				reg = <0x302f0000 0x10000>;
+				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
+					 <&clks IMX7D_GPT3_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			gpt4: timer@30300000 {
+				compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
+				reg = <0x30300000 0x10000>;
+				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
+					 <&clks IMX7D_GPT4_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			kpp: keypad@30320000 {
+				compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
+				reg = <0x30320000 0x10000>;
+				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_KPP_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			iomuxc: pinctrl@30330000 {
+				compatible = "fsl,imx7d-iomuxc";
+				reg = <0x30330000 0x10000>;
+			};
+
+			gpr: iomuxc-gpr@30340000 {
+				compatible = "fsl,imx7d-iomuxc-gpr",
+					"fsl,imx6q-iomuxc-gpr", "syscon",
+					"simple-mfd";
+				reg = <0x30340000 0x10000>;
+
+				mux: mux-controller {
+					compatible = "mmio-mux";
+					#mux-control-cells = <1>;
+					mux-reg-masks = <0x14 0x00000010>;
+				};
+
+				video_mux: csi-mux {
+					compatible = "video-mux";
+					mux-controls = <&mux 0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					status = "disabled";
+
+					port@0 {
+						reg = <0>;
+					};
+
+					port@1 {
+						reg = <1>;
+
+						csi_mux_from_mipi_vc0: endpoint {
+							remote-endpoint = <&mipi_vc0_to_csi_mux>;
+						};
+					};
+
+					port@2 {
+						reg = <2>;
+
+						csi_mux_to_csi: endpoint {
+							remote-endpoint = <&csi_from_csi_mux>;
+						};
+					};
+				};
+			};
+
+			ocotp: efuse@30350000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "fsl,imx7d-ocotp", "syscon";
+				reg = <0x30350000 0x10000>;
+				clocks = <&clks IMX7D_OCOTP_CLK>;
+
+				tempmon_calib: calib@3c {
+					reg = <0x3c 0x4>;
+				};
+
+				fuse_grade: fuse-grade@10 {
+					reg = <0x10 0x4>;
+				};
+			};
+
+			anatop: anatop@30360000 {
+				compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
+					"syscon", "simple-mfd";
+				reg = <0x30360000 0x10000>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+
+				reg_1p0d: regulator-vdd1p0d {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd1p0d";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1200000>;
+					anatop-reg-offset = <0x210>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <8>;
+					anatop-min-voltage = <800000>;
+					anatop-max-voltage = <1200000>;
+					anatop-enable-bit = <0>;
+				};
+
+				reg_1p2: regulator-vdd1p2 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd1p2";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1300000>;
+					anatop-reg-offset = <0x220>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <0x14>;
+					anatop-min-voltage = <1100000>;
+					anatop-max-voltage = <1300000>;
+					anatop-enable-bit = <0>;
+				};
+
+				tempmon: tempmon {
+					compatible = "fsl,imx7d-tempmon";
+					interrupt-parent = <&gpc>;
+					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+					fsl,tempmon = <&anatop>;
+					nvmem-cells = <&tempmon_calib>,	<&fuse_grade>;
+					nvmem-cell-names = "calib", "temp_grade";
+					clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
+				};
+			};
+
+			snvs: snvs@30370000 {
+				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+				reg = <0x30370000 0x10000>;
+
+				snvs_rtc: snvs-rtc-lp {
+					compatible = "fsl,sec-v4.0-mon-rtc-lp";
+					regmap = <&snvs>;
+					offset = <0x34>;
+					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SNVS_CLK>;
+					clock-names = "snvs-rtc";
+				};
+
+				snvs_pwrkey: snvs-powerkey {
+					compatible = "fsl,sec-v4.0-pwrkey";
+					regmap = <&snvs>;
+					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SNVS_CLK>;
+					clock-names = "snvs-pwrkey";
+					linux,keycode = <KEY_POWER>;
+					wakeup-source;
+					status = "disabled";
+				};
+			};
+
+			clks: clock-controller@30380000 {
+				compatible = "fsl,imx7d-ccm";
+				reg = <0x30380000 0x10000>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				#clock-cells = <1>;
+				clocks = <&ckil>, <&osc>;
+				clock-names = "ckil", "osc";
+			};
+
+			src: reset-controller@30390000 {
+				compatible = "fsl,imx7d-src", "syscon";
+				reg = <0x30390000 0x10000>;
+				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+				#reset-cells = <1>;
+			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx7d-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupt-controller;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				#interrupt-cells = <3>;
+				interrupt-parent = <&intc>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_mipi_phy: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <0>;
+						power-supply = <&reg_1p0d>;
+					};
+
+					pgc_pcie_phy: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <1>;
+						power-supply = <&reg_1p0d>;
+					};
+
+					pgc_hsic_phy: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <2>;
+						power-supply = <&reg_1p2>;
+					};
+				};
+			};
+		};
+
+		aips2: bus@30400000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x30400000 0x400000>;
+			ranges;
+
+			adc1: adc@30610000 {
+				compatible = "fsl,imx7d-adc";
+				reg = <0x30610000 0x10000>;
+				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_ADC_ROOT_CLK>;
+				clock-names = "adc";
+				#io-channel-cells = <1>;
+				status = "disabled";
+			};
+
+			adc2: adc@30620000 {
+				compatible = "fsl,imx7d-adc";
+				reg = <0x30620000 0x10000>;
+				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_ADC_ROOT_CLK>;
+				clock-names = "adc";
+				#io-channel-cells = <1>;
+				status = "disabled";
+			};
+
+			ecspi4: spi@30630000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+				reg = <0x30630000 0x10000>;
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
+					<&clks IMX7D_ECSPI4_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			ftm1: pwm@30640000 {
+				compatible = "fsl,vf610-ftm-pwm";
+				reg = <0x30640000 0x10000>;
+				#pwm-cells = <3>;
+				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "ftm_sys", "ftm_ext",
+				"ftm_fix", "ftm_cnt_clk_en";
+				clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
+					<&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
+					<&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
+					<&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			ftm2: pwm@30650000 {
+				compatible = "fsl,vf610-ftm-pwm";
+				reg = <0x30650000 0x10000>;
+				#pwm-cells = <3>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "ftm_sys", "ftm_ext",
+				"ftm_fix", "ftm_cnt_clk_en";
+				clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
+					<&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
+					<&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
+					<&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			pwm1: pwm@30660000 {
+				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+				reg = <0x30660000 0x10000>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
+					 <&clks IMX7D_PWM1_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm2: pwm@30670000 {
+				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+				reg = <0x30670000 0x10000>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
+					 <&clks IMX7D_PWM2_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm3: pwm@30680000 {
+				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+				reg = <0x30680000 0x10000>;
+				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
+					 <&clks IMX7D_PWM3_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm4: pwm@30690000 {
+				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+				reg = <0x30690000 0x10000>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
+					 <&clks IMX7D_PWM4_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			csi: csi@30710000 {
+				compatible = "fsl,imx7-csi";
+				reg = <0x30710000 0x10000>;
+				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
+				clock-names = "mclk";
+				status = "disabled";
+
+				port {
+					csi_from_csi_mux: endpoint {
+						remote-endpoint = <&csi_mux_to_csi>;
+					};
+				};
+			};
+
+			lcdif: lcdif@30730000 {
+				compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif";
+				reg = <0x30730000 0x10000>;
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
+					<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
+				clock-names = "pix", "axi";
+				status = "disabled";
+
+				port {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					lcdif_out_mipi_dsi: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mipi_dsi_in_lcdif>;
+					};
+				};
+			};
+
+			mipi_csi: mipi-csi@30750000 {
+				compatible = "fsl,imx7-mipi-csi2";
+				reg = <0x30750000 0x10000>;
+				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
+					 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+				clock-names = "pclk", "wrap", "phy";
+				power-domains = <&pgc_mipi_phy>;
+				phy-supply = <&reg_1p0d>;
+				resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mipi_vc0_to_csi_mux: endpoint {
+							remote-endpoint = <&csi_mux_from_mipi_vc0>;
+						};
+					};
+				};
+			};
+
+			mipi_dsi: dsi@30760000 {
+				compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x30760000 0x400>;
+				clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
+					 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+				clock-names = "bus_clk", "sclk_mipi";
+				assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,
+						  <&clks IMX7D_PLL_SYS_PFD5_CLK>;
+				assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;
+				assigned-clock-rates = <0>, <333000000>;
+				power-domains = <&pgc_mipi_phy>;
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+				samsung,burst-clock-frequency = <891000000>;
+				samsung,esc-clock-frequency = <20000000>;
+				samsung,pll-clock-frequency = <24000000>;
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						mipi_dsi_in_lcdif: endpoint@0 {
+							reg = <0>;
+							remote-endpoint = <&lcdif_out_mipi_dsi>;
+						};
+					};
+				};
+			};
+		};
+
+		aips3: bus@30800000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x30800000 0x400000>;
+			ranges;
+
+			spba-bus@30800000 {
+				compatible = "fsl,spba-bus", "simple-bus";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x30800000 0x100000>;
+				ranges;
+
+				ecspi1: spi@30820000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+					reg = <0x30820000 0x10000>;
+					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+						<&clks IMX7D_ECSPI1_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ecspi2: spi@30830000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+					reg = <0x30830000 0x10000>;
+					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+						<&clks IMX7D_ECSPI2_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ecspi3: spi@30840000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+					reg = <0x30840000 0x10000>;
+					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+						<&clks IMX7D_ECSPI3_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart1: serial@30860000 {
+					compatible = "fsl,imx7d-uart",
+						     "fsl,imx6q-uart";
+					reg = <0x30860000 0x10000>;
+					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+						<&clks IMX7D_UART1_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart2: serial@30890000 {
+					compatible = "fsl,imx7d-uart",
+						     "fsl,imx6q-uart";
+					reg = <0x30890000 0x10000>;
+					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+						<&clks IMX7D_UART2_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart3: serial@30880000 {
+					compatible = "fsl,imx7d-uart",
+						     "fsl,imx6q-uart";
+					reg = <0x30880000 0x10000>;
+					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+						<&clks IMX7D_UART3_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				sai1: sai@308a0000 {
+					#sound-dai-cells = <0>;
+					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+					reg = <0x308a0000 0x10000>;
+					interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SAI1_IPG_CLK>,
+						 <&clks IMX7D_SAI1_ROOT_CLK>,
+						 <&clks IMX7D_CLK_DUMMY>,
+						 <&clks IMX7D_CLK_DUMMY>;
+					clock-names = "bus", "mclk1", "mclk2", "mclk3";
+					dma-names = "rx", "tx";
+					dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
+					status = "disabled";
+				};
+
+				sai2: sai@308b0000 {
+					#sound-dai-cells = <0>;
+					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+					reg = <0x308b0000 0x10000>;
+					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SAI2_IPG_CLK>,
+						 <&clks IMX7D_SAI2_ROOT_CLK>,
+						 <&clks IMX7D_CLK_DUMMY>,
+						 <&clks IMX7D_CLK_DUMMY>;
+					clock-names = "bus", "mclk1", "mclk2", "mclk3";
+					dma-names = "rx", "tx";
+					dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
+					status = "disabled";
+				};
+
+				sai3: sai@308c0000 {
+					#sound-dai-cells = <0>;
+					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+					reg = <0x308c0000 0x10000>;
+					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SAI3_IPG_CLK>,
+						 <&clks IMX7D_SAI3_ROOT_CLK>,
+						 <&clks IMX7D_CLK_DUMMY>,
+						 <&clks IMX7D_CLK_DUMMY>;
+					clock-names = "bus", "mclk1", "mclk2", "mclk3";
+					dma-names = "rx", "tx";
+					dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
+					status = "disabled";
+				};
+			};
+
+			crypto: crypto@30900000 {
+				compatible = "fsl,sec-v4.0";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x30900000 0x40000>;
+				ranges = <0 0x30900000 0x40000>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_CAAM_CLK>,
+					 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+				clock-names = "ipg", "aclk";
+
+				sec_jr0: jr@1000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x1000 0x1000>;
+					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr1: jr@2000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x2000 0x1000>;
+					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr2: jr@3000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x3000 0x1000>;
+					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				};
+			};
+
+			flexcan1: can@30a00000 {
+				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
+				reg = <0x30a00000 0x10000>;
+				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_CLK_DUMMY>,
+					<&clks IMX7D_CAN1_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				fsl,stop-mode = <&gpr 0x10 1>;
+				status = "disabled";
+			};
+
+			flexcan2: can@30a10000 {
+				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
+				reg = <0x30a10000 0x10000>;
+				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_CLK_DUMMY>,
+					<&clks IMX7D_CAN2_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				fsl,stop-mode = <&gpr 0x10 2>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@30a20000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+				reg = <0x30a20000 0x10000>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@30a30000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+				reg = <0x30a30000 0x10000>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@30a40000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+				reg = <0x30a40000 0x10000>;
+				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@30a50000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+				reg = <0x30a50000 0x10000>;
+				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
+				status = "disabled";
+			};
+
+			uart4: serial@30a60000 {
+				compatible = "fsl,imx7d-uart",
+					     "fsl,imx6q-uart";
+				reg = <0x30a60000 0x10000>;
+				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_UART4_ROOT_CLK>,
+					<&clks IMX7D_UART4_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			uart5: serial@30a70000 {
+				compatible = "fsl,imx7d-uart",
+					     "fsl,imx6q-uart";
+				reg = <0x30a70000 0x10000>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_UART5_ROOT_CLK>,
+					<&clks IMX7D_UART5_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			uart6: serial@30a80000 {
+				compatible = "fsl,imx7d-uart",
+					     "fsl,imx6q-uart";
+				reg = <0x30a80000 0x10000>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_UART6_ROOT_CLK>,
+					<&clks IMX7D_UART6_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			uart7: serial@30a90000 {
+				compatible = "fsl,imx7d-uart",
+					     "fsl,imx6q-uart";
+				reg = <0x30a90000 0x10000>;
+				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_UART7_ROOT_CLK>,
+					<&clks IMX7D_UART7_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			mu0a: mailbox@30aa0000 {
+				compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
+				reg = <0x30aa0000 0x10000>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_MU_ROOT_CLK>;
+				#mbox-cells = <2>;
+				status = "disabled";
+			};
+
+			mu0b: mailbox@30ab0000 {
+				compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
+				reg = <0x30ab0000 0x10000>;
+				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_MU_ROOT_CLK>;
+				#mbox-cells = <2>;
+				fsl,mu-side-b;
+				status = "disabled";
+			};
+
+			usbotg1: usb@30b10000 {
+				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+				reg = <0x30b10000 0x200>;
+				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_USB_CTRL_CLK>;
+				fsl,usbphy = <&usbphynop1>;
+				fsl,usbmisc = <&usbmisc1 0>;
+				phy-clkgate-delay-us = <400>;
+				status = "disabled";
+			};
+
+			usbh: usb@30b30000 {
+				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+				reg = <0x30b30000 0x200>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_USB_CTRL_CLK>;
+				fsl,usbphy = <&usbphynop3>;
+				fsl,usbmisc = <&usbmisc3 0>;
+				phy_type = "hsic";
+				dr_mode = "host";
+				phy-clkgate-delay-us = <400>;
+				status = "disabled";
+			};
+
+			usbmisc1: usbmisc@30b10200 {
+				#index-cells = <1>;
+				compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+				reg = <0x30b10200 0x200>;
+			};
+
+			usbmisc3: usbmisc@30b30200 {
+				#index-cells = <1>;
+				compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+				reg = <0x30b30200 0x200>;
+			};
+
+			usdhc1: mmc@30b40000 {
+				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
+				reg = <0x30b40000 0x10000>;
+				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
+					<&clks IMX7D_USDHC1_ROOT_CLK>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				fsl,tuning-step = <2>;
+				fsl,tuning-start-tap = <20>;
+				status = "disabled";
+			};
+
+			usdhc2: mmc@30b50000 {
+				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
+				reg = <0x30b50000 0x10000>;
+				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
+					<&clks IMX7D_USDHC2_ROOT_CLK>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				fsl,tuning-step = <2>;
+				fsl,tuning-start-tap = <20>;
+				status = "disabled";
+			};
+
+			usdhc3: mmc@30b60000 {
+				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
+				reg = <0x30b60000 0x10000>;
+				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
+					<&clks IMX7D_USDHC3_ROOT_CLK>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				fsl,tuning-step = <2>;
+				fsl,tuning-start-tap = <20>;
+				status = "disabled";
+			};
+
+			qspi: spi@30bb0000 {
+				compatible = "fsl,imx7d-qspi";
+				reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
+				reg-names = "QuadSPI", "QuadSPI-memory";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
+					<&clks IMX7D_QSPI_ROOT_CLK>;
+				clock-names = "qspi_en", "qspi";
+				status = "disabled";
+			};
+
+			sdma: dma-controller@30bd0000 {
+				compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
+				reg = <0x30bd0000 0x10000>;
+				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					 <&clks IMX7D_SDMA_CORE_CLK>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <3>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+			};
+
+			fec1: ethernet@30be0000 {
+				compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
+				reg = <0x30be0000 0x10000>;
+				interrupt-names = "int0", "int1", "int2", "pps";
+				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
+					<&clks IMX7D_ENET_AXI_ROOT_CLK>,
+					<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+					<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
+					<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+				clock-names = "ipg", "ahb", "ptp",
+					"enet_clk_ref", "enet_out";
+				fsl,num-tx-queues = <3>;
+				fsl,num-rx-queues = <3>;
+				fsl,stop-mode = <&gpr 0x10 3>;
+				status = "disabled";
+			};
+		};
+
+		dma_apbh: dma-controller@33000000 {
+			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+			reg = <0x33000000 0x2000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+		};
+
+		gpmi: nand-controller@33002000{
+			compatible = "fsl,imx7d-gpmi-nand";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+			reg-names = "gpmi-nand", "bch";
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "bch";
+			clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
+				<&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+			clock-names = "gpmi_io", "gpmi_bch_apb";
+			dmas = <&dma_apbh 0>;
+			dma-names = "rx-tx";
+			status = "disabled";
+			assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
+			assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
index 1e8619ccf5..abe0a2e450 100644
--- a/arch/arm/dts/imx8mm-evk.dts
+++ b/arch/arm/dts/imx8mm-evk.dts
@@ -7,56 +7,5 @@
 /dts-v1/;
 
 #include <arm64/freescale/imx8mm-evk.dts>
-
-/ {
-	chosen {
-		environment-sd {
-			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
-			status = "disabled";
-		};
-		environment-emmc {
-			compatible = "barebox,environment";
-			device-path = &usdhc3, "partname:barebox-environment";
-			status = "disabled";
-		};
-	};
-};
-
-&fec1 {
-	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
-};
-
-&usdhc2 {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	partition@0 {
-		label = "barebox";
-		reg = <0x0 0xe0000>;
-	};
-
-	partition@e0000 {
-		label = "barebox-environment";
-		reg = <0xe0000 0x20000>;
-	};
-};
-
-&usdhc3 {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	partition@0 {
-		label = "barebox";
-		reg = <0x0 0xe0000>;
-	};
-
-	partition@e0000 {
-		label = "barebox-environment";
-		reg = <0xe0000 0x20000>;
-	};
-};
-
-&ocotp {
-	barebox,provide-mac-address = <&fec1 0x640>;
-};
+#include "imx8mm.dtsi"
+#include "imx8mm-evk.dtsi"
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
new file mode 100644
index 0000000000..a657faa6bc
--- /dev/null
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+/ {
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &env_sd2;
+			status = "disabled";
+		};
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_sd3;
+			status = "disabled";
+		};
+	};
+};
+
+&{flexspi/flash@0} {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0xe0000>;
+		};
+
+		partition@e0000 {
+			label = "barebox-environment";
+			reg = <0xe0000 0x20000>;
+		};
+	};
+
+};
+
+&reg_usdhc2_vmmc {
+	off-on-delay-us = <20000>;
+};
+
+&usdhc2 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	env_sd2: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&usdhc3 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	env_sd3: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec1 0x640>;
+};
diff --git a/arch/arm/dts/imx8mm-evkb.dts b/arch/arm/dts/imx8mm-evkb.dts
new file mode 100644
index 0000000000..b7d3be7a84
--- /dev/null
+++ b/arch/arm/dts/imx8mm-evkb.dts
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de>
+ */
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mm-evk.dts>
+#include "imx8mm.dtsi"
+#include "imx8mm-evk.dtsi"
+
+/ {
+	model = "FSL i.MX8MM EVKB";
+	compatible = "fsl,imx8mm-evkb", "fsl,imx8mm";
+};
+
+&i2c1 {
+	/delete-node/ pmic@4b;
+
+	pmic@25 {
+		compatible = "nxp,pca9450a";
+		reg = <0x25>;
+		pinctrl-0 = <&pinctrl_pmic>;
+		pinctrl-names = "default";
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		regulators {
+			buck1_reg: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+				nxp,dvs-run-voltage = <820000>;
+				nxp,dvs-standby-voltage = <800000>;
+			};
+
+			buck2_reg: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck3_reg: BUCK3 {
+				regulator-name = "BUCK3";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: BUCK4 {
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: BUCK5 {
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/imx8mm-innocomm-wb15-evk.dts b/arch/arm/dts/imx8mm-innocomm-wb15-evk.dts
new file mode 100644
index 0000000000..ac7e5a1cb1
--- /dev/null
+++ b/arch/arm/dts/imx8mm-innocomm-wb15-evk.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mm-innocomm-wb15-evk.dts>
+
+/ {
+	chosen {
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_sd1;
+			status = "disabled";
+		};
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &env_sd2;
+			status = "disabled";
+		};
+	};
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec1 0x640>;
+};
+
+&usdhc1 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x0 0x0 0x100000>;
+		};
+
+		env_sd1: partition@100000 {
+			label = "barebox-environment";
+			reg = <0x0 0x100000 0x0 0x100000>;
+		};
+	};
+};
+
+&usdhc2 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x0 0x0 0x100000>;
+		};
+
+		env_sd2: partition@100000 {
+			label = "barebox-environment";
+			reg = <0x0 0x100000 0x0 0x100000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
new file mode 100644
index 0000000000..0a6183f092
--- /dev/null
+++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mm-phyboard-polis-rdk.dts>
+
+/ {
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &env_sd2;
+			status = "disabled";
+		};
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_emmc;
+			status = "disabled";
+		};
+	};
+
+	aliases {
+		state = &state_emmc;
+	};
+
+	state_emmc: state {
+		compatible = "barebox,state";
+		magic = <0xabff4b1f>;
+		backend-type = "raw";
+		backend = <&usdhc3>;
+		backend-storage-type="direct";
+		/*
+		 * barebox-state partition size: 1 MiB
+		 * nr. of redundant copies:      4
+		 * ==> max. stride size: 1 MiB / 4 = 256 KiB = 262144 Byte
+		 *
+		 * stride size:     262144 Byte
+		 * raw-header:     -    16 Byte
+		 * direct-storage: -     8 Byte
+		 *                 ------------
+		 * max state size:  262120 Byte
+		 *                  ===========
+		 */
+		backend-stridesize = <0x40000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		bootstate {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			system0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@0 {
+					reg = <0x0 0x4>;
+					type = "uint32";
+					default = <2>;
+				};
+
+				priority@4 {
+					reg = <0x4 0x4>;
+					type= "uint32";
+					default = <21>;
+				};
+			};
+
+			system1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@8 {
+					reg = <0x8 0x4>;
+					type = "uint32";
+					default = <2>;
+				};
+
+				priority@c {
+					reg = <0xc 0x4>;
+					type= "uint32";
+					default = <20>;
+				};
+			};
+
+			last_chosen@10 {
+				reg = <0x10 0x4>;
+				type = "uint32";
+			};
+		};
+	};
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec1 0x640>;
+};
+
+&usdhc2 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x0 0x0 0x100000>;
+		};
+
+		env_sd2: partition@100000 {
+			label = "dt-barebox-environment";
+			reg = <0x0 0x100000 0x0 0x100000>;
+		};
+	};
+};
+
+&usdhc3 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x0 0x0 0x100000>;
+		};
+
+		env_emmc: partition@100000 {
+			label = "dt-barebox-environment";
+			reg = <0x0 0x100000 0x0 0x100000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx8mm-prt8mm.dts b/arch/arm/dts/imx8mm-prt8mm.dts
new file mode 100644
index 0000000000..abd758f285
--- /dev/null
+++ b/arch/arm/dts/imx8mm-prt8mm.dts
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Protonic Holland
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mm.dtsi>
+#include "imx8mm.dtsi"
+
+/ {
+	model = "Protonic PRT8MM";
+	compatible = "prt,prt8mm", "fsl,imx8mm";
+
+	chosen {
+		stdout-path = &uart4;
+
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &part_env_sd;
+			status = "disabled";
+		};
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &part_env_emmc;
+			status = "disabled";
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usbotg1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1>;
+	dr_mode = "host";
+	power-active-high;
+	over-current-active-low;
+	status = "okay";
+};
+
+&usdhc2 {
+	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
+	assigned-clock-rates = <100000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	part_env_sd: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&usdhc3 {
+	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+	assigned-clock-rates = <400000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	no-sdio;
+	no-sd;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	part_env_emmc: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400000c3
+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400000c3
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400000c3
+			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400000c3
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400000c3
+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400000c3
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x040
+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x040
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x0d4
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
+		>;
+	};
+
+	pinctrl_usbotg1: usbotg1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR		0x000
+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x000
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
new file mode 100644
index 0000000000..01f74c1074
--- /dev/null
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/features/imx8m.h>
+
+/ {
+	aliases {
+		gpr.reboot_mode = &reboot_mode_gpr;
+		pwm0 = &pwm1;
+		pwm1 = &pwm2;
+		pwm2 = &pwm3;
+		pwm3 = &pwm4;
+	};
+
+	chosen {
+		barebox,bootsource-mmc0 = &usdhc1;
+		barebox,bootsource-mmc1 = &usdhc2;
+		barebox,bootsource-mmc2 = &usdhc3;
+	};
+};
+
+feat: &ocotp {
+	#feature-cells = <1>;
+	barebox,feature-controller;
+};
+
+&src {
+	compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon", "simple-mfd";
+
+	reboot_mode_gpr: reboot-mode {
+		compatible = "barebox,syscon-reboot-mode";
+		offset = <0x94>, <0x98>; /* SRC_GPR{9,10} */
+		mask = <0xffffffff>, <0x40000000>;
+		mode-normal = <0>, <0>;
+		mode-serial = <0x00000010>, <0x40000000>;
+	};
+};
+
+&A53_1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_CPU_DUAL>;
+};
+
+&A53_2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&A53_3 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&gpc {
+	barebox,feature-gates = <&feat 0>;
+};
+
+&vpu_g1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_g2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_blk_ctrl {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpumix {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_h1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts
new file mode 100644
index 0000000000..6ebb4d15e4
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-evk.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mn-ddr4-evk.dts>
+#include "imx8mn-evk.dtsi"
diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts
new file mode 100644
index 0000000000..eb6e1312f4
--- /dev/null
+++ b/arch/arm/dts/imx8mn-evk.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mn-evk.dts>
+#include "imx8mn-evk.dtsi"
diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi
new file mode 100644
index 0000000000..c23075216e
--- /dev/null
+++ b/arch/arm/dts/imx8mn-evk.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include "imx8mn.dtsi"
+
+/ {
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &env_sd2;
+			status = "disabled";
+		};
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_sd3;
+			status = "disabled";
+		};
+	};
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0xe0000>;
+		};
+
+		partition@e0000 {
+			label = "barebox-environment";
+			reg = <0xe0000 0x20000>;
+		};
+	};
+
+};
+
+&usdhc2 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	env_sd2: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&usdhc3 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	env_sd3: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec1 0x640>;
+};
+
+&iomuxc {
+	pinctrl_flexspi0: flexspi0grp {
+		fsl,pins = <
+		MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x1c4
+		MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x84
+		MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x84
+		MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x84
+		MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x84
+		MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x84
+		>;
+	};
+};
+
+&flexspi {
+	pinctrl-0 = <&pinctrl_flexspi0>;
+};
+
+&flash0 {
+	spi-max-frequency = <80000000>;
+};
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
new file mode 100644
index 0000000000..9aa787ea25
--- /dev/null
+++ b/arch/arm/dts/imx8mn.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/features/imx8m.h>
+
+/ {
+	aliases {
+		pwm0 = &pwm1;
+		pwm1 = &pwm2;
+		pwm2 = &pwm3;
+		pwm3 = &pwm4;
+	};
+
+	chosen {
+		barebox,bootsource-mmc0 = &usdhc1;
+		barebox,bootsource-mmc1 = &usdhc2;
+		barebox,bootsource-mmc2 = &usdhc3;
+	};
+};
+
+feat: &ocotp {
+	#feature-cells = <1>;
+	barebox,feature-controller;
+};
+
+&A53_1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_CPU_DUAL>;
+};
+
+&A53_2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&A53_3 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&gpc {
+	barebox,feature-gates = <&feat 0>;
+};
+
+&gpu {
+	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&pgc_gpumix {
+	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
diff --git a/arch/arm/dts/imx8mp-congatec-qmx8p.dtsi b/arch/arm/dts/imx8mp-congatec-qmx8p.dtsi
new file mode 100644
index 0000000000..b2e8fa968a
--- /dev/null
+++ b/arch/arm/dts/imx8mp-congatec-qmx8p.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-FileCopyrightText: 2019 NXP
+// SPDX-FileCopyrightText: 2022 congatec GmbH
+// SPDX-FileCopyrightText: 2023 Pengutronix
+
+&w25q64fw { /* FlexSPI NOR Flash */
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "boot";
+		reg = <0x0000000 0x400000>;
+	};
+
+	partition@400000 {
+		label = "failsafe";
+		reg = <0x400000 0x3e0000>;
+	};
+
+	partition@7e0000 {
+		label = "reserved";
+		reg = <0x7e0000 0x20000>;
+		read-only;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-congatec-qmx8p.kernel.dtsi b/arch/arm/dts/imx8mp-congatec-qmx8p.kernel.dtsi
new file mode 100644
index 0000000000..57010bd6f5
--- /dev/null
+++ b/arch/arm/dts/imx8mp-congatec-qmx8p.kernel.dtsi
@@ -0,0 +1,1040 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-FileCopyrightText: 2019 NXP
+// SPDX-FileCopyrightText: 2022 congatec GmbH
+// SPDX-FileCopyrightText: 2023 Pengutronix, Johannes Zink <j.zink@pengutronix.de>
+
+#include <arm64/freescale/imx8mp.dtsi>
+#include "imx8mp.dtsi"
+#include <dt-bindings/usb/pd.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	model = "conga-QMX8-Plus";
+	compatible = "congatec,qmx8p", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		rtc0 = &rtc_ext;     /* external I2C RTC M4162 */
+		rtc1 = &snvs_rtc;    /* internal in SoC */
+	};
+
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+		#clock-cells= <0>;
+		clock-frequency = <100000000>;
+	};
+
+	reg_usb1_host_vbus: regulator-usb1-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1_vbus>;
+		gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
+		regulator-name = "usb1_host_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+	};
+
+	reg_usb2_host_vbus: regulator-usb2-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb2_vbus>;
+		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+		regulator-name = "usb2_host_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+	};
+
+	/* reset line for SD1 (Qseven SD Card) interface */
+	reg_usdhc1_vmmc: regulator-usdhc1 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc1_vmmc>;
+		gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+		regulator-name = "3v3-sd1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		startup-delay-us = <100>;
+		off-on-delay-us = <12000>;
+	};
+
+	/* reset line for SD2 (on-SoM µSD) interface */
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		regulator-name = "3v3-sd2";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		startup-delay-us = <100>;
+		off-on-delay-us = <12000>;
+	};
+
+	/* reset line for SD3 (on-SoM eMMC) interface */
+	reg_usdhc3_vmmc: regulator-usdhc3 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc3_vmmc>;
+		gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+		regulator-name = "3v3-sd3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		startup-delay-us = <100>;
+		off-on-delay-us = <12000>;
+	};
+
+	reg_lfp_vdd: regulator-lfp-vdd {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_display_vdd_en>;
+		gpio = <&gpio4 1 GPIO_ACTIVE_HIGH>; // LFP0_VDD_EN
+		regulator-name = "Display_Panel_Vdd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_backlight_enable: regulator-backlight {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds0_backlight>;
+		gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+		regulator-name = "backlight";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+	};
+
+	lvds0_backlight: lvds0-backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 0 100000 0>;
+		power-supply = <&reg_backlight_enable>;
+		brightness-levels = <0 100>;
+		num-interpolated-steps = <100>;
+		default-brightness-level = <80>;
+	};
+
+	fan0: pwm-fan {
+		compatible = "pwm-fan";
+		pwms = <&pwm4 4 100000 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_interrupt_fan_in>;
+		#cooling-cells = <2>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+		status = "disabled";
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+};
+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+};
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+};
+
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs0>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_gbe0_rst>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* on-SoM PHY */
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <1000>;
+			reset-deassert-us = <1000>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+		};
+	};
+};
+
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	w25q64fw: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pca9450: pmic@25 {
+		compatible = "nxp,pca9450c";
+		reg = <0x25>;
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio4>; /* PMIC_nINT */
+		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck3: BUCK3 {
+				regulator-name = "BUCK3";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5 {
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c3 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+/* i2c-5: RTC */
+&i2c5 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c5>;
+	pinctrl-1 = <&pinctrl_i2c5_gpio>;
+	scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	rtc_ext: rtc@68 {
+		compatible = "microcrystal,rv4162";
+		reg = <0x68>;
+	};
+};
+
+/* i2c-6: I2C splitter */
+&i2c6 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c6>;
+	pinctrl-1 = <&pinctrl_i2c6_gpio>;
+	scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	mux@70 {
+		compatible = "nxp,pca9548";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* MIPI-CSI 1 */
+		imux0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		/* MIPI-CSI 2 */
+		imux1: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		/* Qseven LVDS_DID */
+		imux2: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		/* Qseven LVDS_BLC */
+		imux3: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		/* Ports 4 .. 7 not used */
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	fsl,max-link-speed = <2>;
+};
+
+&pcie_phy {
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	clocks = <&pcie0_refclk>;
+	clock-names= "ref";
+};
+
+&uart1 { /* UART0 connector on Qseven */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	uart-has-rtscts;
+};
+
+&uart2 {
+	/* on-SoM UART connector */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usb3_phy0 { /* on-SoM hub */
+	fsl,phy-tx-vref-tune = <8>;		// note: downstream
+	fsl,phy-tx-preemp-amp-tune = <3>;	// note: downstream
+	vbus-supply = <&reg_usb1_host_vbus>;
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 { /* Qseven USB_P1 */
+	dr_mode = "otg";
+	usb-role-switch;
+	role-switch-default-mode = "host";
+
+	connector {
+		compatible = "gpio-usb-b-connector", "usb-b-connector";
+		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb_overcurrent>;
+	};
+};
+
+&usb3_phy1 {
+	vbus-supply = <&reg_usb2_host_vbus>;
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 { /* Qseven USB_P0 */
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* Qseven SD Card interface */
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+	cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc1_vmmc>;
+	bus-width = <4>;
+};
+
+/* on-SoM µSD Card slot */
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+/* on-SoM eMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	vmmc-supply = <&reg_usdhc3_vmmc>;
+	bus-width = <8>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&gpio1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gbe0_phy_reg>;
+};
+
+&gpio4 {
+	stby_en-hog {
+		gpio-hog;
+		gpios = <11 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "CB_STBY_EN";
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 =
+		<&pinctrl_hog>,
+		<&pinctrl_android_buttons>,
+		<&pinctrl_pm>,
+		<&pinctrl_q7_suspend>,
+		<&pinctrl_q7_wdt>;
+
+	pinctrl_hog: hog-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09		0x01c0 /* PM_WAKE#   (X19:32) */
+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x01c0 /* SMB_ALERT# (X19:20) */
+			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31		0x01c0 /* I2S_RST# */
+		>;
+	};
+
+	pinctrl_display_vdd_en: lvds-vdd-enable-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x0100 /* LFP_VDD_EN */
+		>;
+	};
+
+	pinctrl_hdmi: hdmi-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000019
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019
+		>;
+	};
+
+	/* On module Android buttons (X7) */
+	pinctrl_android_buttons: androidbutton-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07		0x01c0 /* X7-2: Btn Vol Up */
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x01c0 /* X7-3: Btn Home */
+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x01c0 /* X7-4: Btn Search */
+			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x01c0 /* X7-5: Btn Back */
+			MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08		0x01c0 /* X7-6: Btn Menu */
+			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x01c0 /* X7-7: Btn Vol Down */
+		>;
+	};
+
+	/* Qseven PM signals */
+	pinctrl_pm: pm-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x01c0 /* Q7-21: Sleep Btn */
+			MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10		0x01c0 /* Q7-22: Lid Btn */
+			MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06		0x01c0 /* Q7-27: Bat Low */
+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x01c0 /* Q7-69: Thrm */
+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x01c0 /* Q7-71: Thrm Trip (X19:19) */
+		>;
+	};
+
+	/* Qseven WDT */
+	pinctrl_q7_wdt: q7-wdt-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04		0x01c0 /* Q7-70: WDT Trig */
+			MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13		0x0100 /* Q7-72: WDT Out */
+		>;
+	};
+
+	/* Qseven suspend signals */
+	pinctrl_q7_suspend: q7-suspend-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11		0x0100 /* Q7-18: SUS_S3# (enable signal from PMIC) */
+			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01		0x0100 /* Q7-19: SUS_STAT | GP_OUT0*/
+		>;
+	};
+
+	/* USB overcurrent */
+	pinctrl_usb_overcurrent: usb-overcurrent-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC		0x01c0
+			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0x01c0 /* USB1 OC as GPIO */
+		>;
+	};
+
+	pinctrl_pwm1: pwm1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x116
+		>;
+	};
+
+	pinctrl_pwm2: pwm2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0x116
+		>;
+	};
+
+	pinctrl_pwm4: pwm4-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT		0x116
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82
+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82
+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82
+		>;
+	};
+
+	pinctrl_ecspi1_cs: ecspi1cs-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x01c0
+		>;
+	};
+
+	pinctrl_ecspi2: ecspi2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82
+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82
+		>;
+	};
+
+	pinctrl_ecspi2_cs0: ecspi2cs0-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x01c0
+		>;
+	};
+
+	pinctrl_ecspi2_cs1: ecspi2cs1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x01c0
+		>;
+	};
+
+	pinctrl_eqos: eqos-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+
+			/* PTP capture INT */
+			MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN			0x1c0
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX			0x150
+			MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX			0x150
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART3_TXD__CAN2_RX			0x150
+			MX8MP_IOMUXC_UART3_RXD__CAN2_TX			0x150
+		>;
+	};
+
+	pinctrl_flexspi0: flexspi0-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c0
+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
+		>;
+	};
+
+	pinctrl_i2c1: i2c1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001c3
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c2: i2c2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3: i2c3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_i2c5: i2c5-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL			0x400001c3
+			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_i2c6: i2c6-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL		0x400001c3
+			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2grp-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001c3
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3grp-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x400001c3
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c5_gpio: i2c5grp-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03		0x400001c3
+			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c6_gpio: i2c6grp-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x400001c3
+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x400001c3
+		>;
+	};
+
+	pinctrl_pcie: pcie-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B		0x160  /* #OE of on-SoM PCIe CLK generator */
+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x41   /* WAKE */
+			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12		0x0100 /* reset */
+		>;
+	};
+
+	pinctrl_pmic: pmicirq-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05		0x41
+		>;
+	};
+
+	pinctrl_sai5: sai5-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK	0xd6
+			MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK	0xd6
+			MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC	0xd6
+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00	0xd6
+			MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00	0xd6
+		>;
+	};
+
+	pinctrl_uart1: uart1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x49
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x49
+			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
+			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x49
+		>;
+	};
+
+	pinctrl_uart2: uart2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
+		>;
+	};
+
+	pinctrl_uart4: uart4-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
+		>;
+	};
+
+	pinctrl_usb1: usb1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x140	/* USB1 ID */
+		>;
+	};
+
+	/* Qseven SD Card interface */
+	pinctrl_usdhc1: usdhc1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
+			MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
+			MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
+			MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_gpio: usdhc1-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x1c4 /* Q7-43: SD CD */
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x1c4 /* Q7-46: SD WP */
+		>;
+	};
+
+	pinctrl_usdhc1_vmmc: usdhc1-vmmc-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x41	/* reset */
+		>;
+	};
+
+	/* on-SoM µSD Card slot */
+	pinctrl_usdhc2: usdhc2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 		0x1c4
+		>;
+	};
+
+	pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41
+		>;
+	};
+
+	/* on-SoM eMMC */
+	pinctrl_usdhc3: usdhc3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
+		>;
+	};
+
+	pinctrl_usdhc3_vmmc: usdhc3-vmmc-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16		0x41
+		>;
+	};
+
+	pinctrl_wdog: wdog-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
+		>;
+	};
+
+	pinctrl_gpt1_capture1: gpt1-capture1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1		0x01C0
+		>;
+	};
+
+	pinctrl_interrupt_fan_in: interrupt-fan-in-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00		0x01C0
+		>;
+	};
+
+	pinctrl_usb1_vbus: usb1-vbus-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17		0x0100 /* USB1_PWR */
+		>;
+	};
+
+	pinctrl_usb2_vbus: usb2-vbus-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16		0x0100 /* USB0S_PWR */
+		>;
+	};
+
+	pinctrl_gbe0_phy_reg: gbe0-phy-reg-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x01C0 /* GBE0_PWR_EN# */
+		>;
+	};
+
+	pinctrl_gbe0_rst: gbe0-rst-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x01C0 /* GBE0_RST# */
+		>;
+	};
+
+	pinctrl_lvds0_backlight: lvds0-backlight-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x0100 /* BL_EN */
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-debix-model-a-upstream.dts b/arch/arm/dts/imx8mp-debix-model-a-upstream.dts
new file mode 100644
index 0000000000..48014748c5
--- /dev/null
+++ b/arch/arm/dts/imx8mp-debix-model-a-upstream.dts
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Ideas on Board Oy
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/usb/pd.h>
+
+#include <arm64/freescale/imx8mp.dtsi>
+
+/ {
+	model = "Polyhex Debix Model A i.MX8MPlus board";
+	compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_led>;
+
+		led-0 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-connection-type = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 { /* RTL8211E */
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <20>;
+			reset-deassert-us = <200000>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic@25 {
+		compatible = "nxp,pca9450c";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
+			};
+
+			buck4: BUCK4{
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5{
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		interrupt-parent = <&gpio2>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_rtc_int>;
+	};
+};
+
+&i2c6 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c6>;
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart2 {
+	/* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+/* SD Card */
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN			0x1f
+			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT			0x1f
+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18				0x19
+		>;
+	};
+
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC				0x3
+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO				0x3
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0				0x91
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1				0x91
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2				0x91
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3				0x91
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC				0x91
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL			0x91
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0				0x1f
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1				0x1f
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2				0x1f
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3				0x1f
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL			0x1f
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC				0x1f
+			MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT			0x1f
+			MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN			0x1f
+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19				0x19
+		>;
+	};
+
+	pinctrl_gpio_led: gpioledgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16				0x19
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c3
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c3
+		>;
+	};
+
+	pinctrl_i2c6: i2c6grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL				0x400001c3
+			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA					0x400001c3
+		>;
+	};
+
+	pinctrl_pmic: pmicirqgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03				0x41
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19				0x41
+		>;
+	};
+
+	pinctrl_rtc_int: rtcintgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11				0x140
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX				0x14f
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX				0x14f
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX				0x49
+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX				0x49
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX				0x49
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX				0x49
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d4
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d6
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12				0x1c4
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts
new file mode 100644
index 0000000000..a58b40ec86
--- /dev/null
+++ b/arch/arm/dts/imx8mp-debix-model-a.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "imx8mp-debix-model-a-upstream.dts"
+#include "imx8mp.dtsi"
+
+/ {
+	/*
+	* Switch the ethernet aliases compared to usual i.MX8MP ordering
+	* as the EQOS interface is on the main board, the FEC interface
+	* is located on the extension board.
+	*/
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &fec;
+	};
+
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &env_sd;
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_emmc;
+			status = "disabled";
+		};
+	};
+};
+
+&usdhc2 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x0 0x0 0x100000>;
+		};
+
+		env_sd: partition@100000 {
+			label = "barebox-environment";
+			reg = <0x0 0x100000 0x0 0x100000>;
+		};
+	};
+};
+
+&usdhc3 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x0 0x0 0x100000>;
+		};
+
+		env_emmc: partition@100000 {
+			label = "barebox-environment";
+			reg = <0x0 0x100000 0x0 0x100000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts b/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts
new file mode 100644
index 0000000000..59334ce30c
--- /dev/null
+++ b/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts
@@ -0,0 +1,472 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de>
+ */
+
+/dts-v1/;
+
+#include "imx8mp-debix-som-a-upstream.dtsi"
+
+/ {
+	model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
+	compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
+		     "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &fec;
+	};
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "BB_VDD3V3";
+		/* Required timings for ethernet phy's */
+		startup-delay-us = <50000>;
+		off-on-delay-us = <110000>;
+		gpio = <&expander0 10 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "BB_VDD5V";
+		gpio = <&expander0 9 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	regulator-som-vdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-name = "SOM_VDD1V8_SW";
+		gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	regulator-som-vdd3v3 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "SOM_VDD3V3_SW";
+		gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	regulator-vbus-usb20 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "USB20_5V";
+		gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+		vin-supply = <&reg_baseboard_vdd5v0>;
+	};
+
+	regulator-vbus-usb30 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "USB30_5V";
+		gpio = <&expander1 12 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+		vin-supply = <&reg_baseboard_vdd5v0>;
+	};
+
+	reg_vdd5v0: regulator-vdd5v0 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "VDD_5V";
+		gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	nvmem-cells = <&ethmac1>;
+	nvmem-cell-names = "mac-address";
+	phy-supply = <&reg_baseboard_vdd3v3>;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <20000>;
+			reset-deassert-us = <150000>;
+			eee-broken-1000t;
+			realtek,clkout-disable;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	nvmem-cells = <&ethmac2>;
+	nvmem-cell-names = "mac-address";
+	phy-supply = <&reg_baseboard_vdd3v3>;
+	phy-handle = <&ethphy1>;
+	phy-mode = "rgmii-id";
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <20000>;
+			reset-deassert-us = <150000>;
+			eee-broken-1000t;
+			realtek,clkout-disable;
+		};
+	};
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_vdd5v0>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_vdd5v0>;
+	status = "okay";
+};
+
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&i2c4 {
+	expander0: gpio@20 {
+		compatible = "nxp,pca9535";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <0x02>;
+	};
+
+	expander1: gpio@23 {
+		compatible = "nxp,pca9535";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <0x02>;
+
+		/*
+		 * Since USB1 is bound to peripheral mode we need to ensure
+		 * that VBUS is turned off.
+		 */
+		usb30-otg-hog {
+			gpio-hog;
+			gpios = <13 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "USB30_OTG_EN";
+		};
+	};
+
+	rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_rtc>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+		#clock-cells = <0>;
+	};
+
+	eeprom@52 {
+		compatible = "atmel,24c02";
+		reg = <0x52>;
+		pagesize = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* MACs stored in ASCII */
+		ethmac1: mac-address@0 {
+			reg = <0x0 0xc>;
+		};
+
+		ethmac2: mac-address@c {
+			reg = <0xc 0xc>;
+		};
+	};
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+/* Debug */
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	/* 2.x hub on port 1 */
+	usb_hub_2_x: hub@1 {
+		compatible = "usb5e3,610";
+		reg = <1>;
+		reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
+		vdd-supply = <&reg_vdd5v0>;
+		peer-hub = <&usb_hub_3_x>;
+	};
+
+	/* 3.x hub on port 2 */
+	usb_hub_3_x: hub@2 {
+		compatible = "usb5e3,620";
+		reg = <2>;
+		reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
+		vdd-supply = <&reg_vdd5v0>;
+		peer-hub = <&usb_hub_2_x>;
+	};
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+/* µSD Card */
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+	assigned-clock-rates = <400000000>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	disable-wp;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+
+			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN			0x1f
+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18				0x19
+		>;
+	};
+
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
+			MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN    0x1f
+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x19
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX			0x154
+			MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX			0x154
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX			0x154
+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX			0x154
+		>;
+	};
+
+	pinctrl_flexspi0: flexspi0grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_rtc: rtcgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x140
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x14f
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x14f
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x49
+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x49
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-debix-som-a-bmb-08.dts b/arch/arm/dts/imx8mp-debix-som-a-bmb-08.dts
new file mode 100644
index 0000000000..88ad897f34
--- /dev/null
+++ b/arch/arm/dts/imx8mp-debix-som-a-bmb-08.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "imx8mp-debix-som-a-bmb-08-upstream.dts"
+#include "imx8mp.dtsi"
+
+/ {
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &env_sd;
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_emmc;
+			status = "disabled";
+		};
+	};
+};
+
+/* Disable peer hub to avoid warnings */
+&usb_hub_2_x {
+	status = "disabled";
+};
+
+&usdhc2 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x0 0x0 0x100000>;
+		};
+
+		env_sd: partition@100000 {
+			label = "barebox-environment";
+			reg = <0x0 0x100000 0x0 0x100000>;
+		};
+	};
+};
+
+&usdhc3 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x0 0x0 0x100000>;
+		};
+
+		env_emmc: partition@100000 {
+			label = "barebox-environment";
+			reg = <0x0 0x100000 0x0 0x100000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi b/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi
new file mode 100644
index 0000000000..9e0d19a2a7
--- /dev/null
+++ b/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de>
+ */
+
+#include <arm64/freescale/imx8mp.dtsi>
+
+/ {
+	model = "Polyhex i.MX8MPlus Debix SOM A";
+	compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp";
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic@25 {
+		compatible = "nxp,pca9450c";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
+			};
+
+			buck4: BUCK4 {
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5 {
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	adc@48 {
+		 compatible = "ti,ads1115";
+		 reg = <0x48>;
+		 #address-cells = <1>;
+		 #size-cells = <0>;
+
+		 channel@4 {
+			 reg = <4>;
+			 ti,gain = <1>;
+			 ti,datarate = <7>;
+		 };
+
+		 channel@5 {
+			 reg = <5>;
+			 ti,gain = <1>;
+			 ti,datarate = <7>;
+		 };
+
+		 channel@6 {
+			 reg = <6>;
+			 ti,gain = <1>;
+			 ti,datarate = <7>;
+		 };
+
+		 channel@7 {
+			 reg = <7>;
+			 ti,gain = <1>;
+			 ti,datarate = <7>;
+		 };
+	 };
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index 3264ade4b8..0376743068 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -13,12 +13,12 @@
 	chosen {
 		environment-sd {
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 			status = "disabled";
 		};
 		environment-emmc {
 			compatible = "barebox,environment";
-			device-path = &usdhc3, "partname:barebox-environment";
+			device-path = &env_sd3;
 			status = "disabled";
 		};
 	};
@@ -30,11 +30,53 @@
 	};
 };
 
+/delete-node/ &{/memory@40000000};
+
 &ethphy1 {
 	reset-assert-us = <15000>;
 	reset-deassert-us = <100000>;
 };
 
+&{flexspi/flash@0} {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0xe0000>;
+		};
+
+		partition@e0000 {
+			label = "barebox-environment";
+			reg = <0xe0000 0x20000>;
+		};
+	};
+
+};
+
+&reg_usdhc2_vmmc {
+	off-on-delay-us = <20000>;
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	status = "okay";
+};
+
 &usdhc2 {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -44,7 +86,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
@@ -59,12 +101,8 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd3: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
 };
-
-&ocotp {
-	barebox,provide-mac-address = <&fec 0x640>;
-};
diff --git a/arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts b/arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts
new file mode 100644
index 0000000000..eec42954dc
--- /dev/null
+++ b/arch/arm/dts/imx8mp-karo-qsxp-ml81-qsbase4.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8mp-karo-qsxp-ml81.dtsi"
+
+/ {
+	model = "Ka-Ro electronics QSXP-ML81-QSBASE4 (NXP i.MX8MP) Board";
+	compatible = "karo,imx8mp-qsxp-ml81-qsbase4", "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
+};
+
+&eqos {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_eqos>;
+	pinctrl-1 = <&pinctrl_eqos_sleep>;
+	phy-connection-type = "rgmii-id";
+	phy-handle = <&ethphy1>;
+	phy-supply = <&ldo5_reg>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <7>;
+			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <100>;
+			reset-deassert-us = <250000>;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x140					/* PHY reset */
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x142
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x142
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x40000016
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x016
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x016
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x016
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x016
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x016
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x110				/* MODE0 */
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x150				/* MODE1 */
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x150				/* MODE2 */
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x150				/* MODE3 */
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x156		/* PHYAD2 */
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x000			/* CLK125_EN */
+			MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x110		/* LED_MODE */
+		>;
+	};
+
+	pinctrl_eqos_sleep: eqos-sleep-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x120
+			MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x120
+			MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x120
+			MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x120
+			MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x120
+			MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x120
+			MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x120
+			MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x120
+			MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x120
+			MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x120
+			MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x120
+			MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x120
+			MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x120
+			MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x120
+			MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x120
+			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x120
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-karo-qsxp-ml81-upstream.dtsi b/arch/arm/dts/imx8mp-karo-qsxp-ml81-upstream.dtsi
new file mode 100644
index 0000000000..4115fcf2f5
--- /dev/null
+++ b/arch/arm/dts/imx8mp-karo-qsxp-ml81-upstream.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8mp-karo.dtsi"
+
+/ {
+	model = "Ka-Ro electronics QSXP-ML81 (NXP i.MX8MP) module";
+	compatible = "karo,imx8mp-qsxp-ml81", "fsl,imx8mp";
+
+	reg_3v3_etn: regulator-3v3-etn {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3-etn";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&ldo5_reg>;
+	};
+};
+
+&usb_dwc3_0 {
+	dr_mode = "peripheral";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&ldo5_reg {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-boot-on;
+	regulator-always-on;
+};
+
+&iomuxc {
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x140
+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x140
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x140
+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-karo-qsxp-ml81.dtsi b/arch/arm/dts/imx8mp-karo-qsxp-ml81.dtsi
new file mode 100644
index 0000000000..e47623a1a5
--- /dev/null
+++ b/arch/arm/dts/imx8mp-karo-qsxp-ml81.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8mp-karo-qsxp-ml81-upstream.dtsi"
+
+/ {
+	chosen {
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_emmc;
+			status = "disabled";
+		};
+	};
+
+	aliases {
+		state = &state_emmc;
+	};
+
+	state_emmc: state {
+		compatible = "barebox,state";
+		magic = <0xabff4b1f>;
+		backend-type = "raw";
+		backend = <&usdhc3>;
+		backend-storage-type="direct";
+		/*
+		 * barebox-state partition size: 1 MiB
+		 * nr. of redundant copies:      4
+		 * ==> max. stride size: 1 MiB / 4 = 256 KiB = 262144 Byte
+		 *
+		 * stride size:     262144 Byte
+		 * raw-header:     -    16 Byte
+		 * direct-storage: -     8 Byte
+		 *                 ------------
+		 * max state size:  262120 Byte
+		 *                  ===========
+		 */
+		backend-stridesize = <0x40000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		bootstate {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			system0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@0 {
+					reg = <0x0 0x4>;
+					type = "uint32";
+					default = <2>;
+				};
+
+				priority@4 {
+					reg = <0x4 0x4>;
+					type= "uint32";
+					default = <21>;
+				};
+			};
+
+			system1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@8 {
+					reg = <0x8 0x4>;
+					type = "uint32";
+					default = <2>;
+				};
+
+				priority@c {
+					reg = <0xc 0x4>;
+					type= "uint32";
+					default = <20>;
+				};
+			};
+
+			last_chosen@10 {
+				reg = <0x10 0x4>;
+				type = "uint32";
+			};
+		};
+	};
+};
+
+&usdhc2 {
+	status = "disabled";
+};
+
+&usdhc3 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x0 0x0 0x100000>;
+		};
+
+		env_emmc: partition@100000 {
+			label = "dt-barebox-environment";
+			reg = <0x0 0x100000 0x0 0x100000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx8mp-karo.dtsi b/arch/arm/dts/imx8mp-karo.dtsi
new file mode 100644
index 0000000000..d034f14533
--- /dev/null
+++ b/arch/arm/dts/imx8mp-karo.dtsi
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+#include <arm64/freescale/imx8mp.dtsi>
+#include "imx8mp.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&reg_vdd_arm>;
+};
+
+&A53_1 {
+	cpu-supply = <&reg_vdd_arm>;
+};
+
+&A53_2 {
+	cpu-supply = <&reg_vdd_arm>;
+};
+
+&A53_3 {
+	cpu-supply = <&reg_vdd_arm>;
+};
+
+&i2c1 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	clock-frequency = <400000>;
+	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pmic@25 {
+		reg = <0x25>;
+		compatible = "nxp,pca9450c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+		status = "okay";
+
+		regulators {
+			reg_vdd_soc: BUCK1 {
+				regulator-name = "vdd-soc";
+				regulator-min-microvolt = <805000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			reg_vdd_arm: BUCK2 {
+				regulator-name = "vdd-core";
+				regulator-min-microvolt = <805000>;
+				regulator-max-microvolt = <950000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
+			};
+
+			reg_vdd_3v3: BUCK4 {
+				regulator-name = "3v3";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_nvcc_nand: BUCK5 {
+				regulator-name = "nvcc-nand";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_nvcc_dram: BUCK6 {
+				regulator-name = "nvcc-dram";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_snvs_1v8: LDO1 {
+				regulator-name = "snvs-1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-always-on;
+			};
+
+			reg_vdda_1v8: LDO3 {
+				regulator-name = "vdda-1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo5_reg: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_rtscts>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
+	dma-names = "rx", "tx";
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_usdhc2_cd>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_vdd_3v3>;
+	vqmmc-supply = <&reg_vdd_3v3>;
+	voltage-ranges = <3300 3300>;
+	no-1-8-v;
+	fsl,wp-controller;
+};
+
+&usdhc3 { /* eMMC */
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	no-sd;
+	no-sdio;
+	vmmc-supply = <&reg_vdd_3v3>;
+	vqmmc-supply = <&reg_nvcc_nand>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c2
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001c2
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c2
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c2
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2-gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001c2
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001c2
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c2
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3-gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c2
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4_gpio: i2c4-gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x400001c2
+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x400001c2
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x1c0
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x140
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x140
+		>;
+	};
+
+	pinctrl_uart1_rtscts: uart1-rtsctsgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS		0x140
+			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS		0x140
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x140
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x140
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x140
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x140
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_cd: usdhc2-cdgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-koenigbauer-alphajet.dts b/arch/arm/dts/imx8mp-koenigbauer-alphajet.dts
new file mode 100644
index 0000000000..5f8c83f2a2
--- /dev/null
+++ b/arch/arm/dts/imx8mp-koenigbauer-alphajet.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-FileCopyrightText: 2023 Pengutronix, Johannes Zink <j.zink@pengutronix.de>
+
+#include "imx8mp-koenigbauer-alphajet.kernel.dts"
+#include "imx8mp-congatec-qmx8p.dtsi"
+
+/ {
+	aliases {
+		state = &state_emmc;
+	};
+
+	chosen {
+		stdout-path = &uart1; /* baseboard UART0, connector J12 */
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_emmc;
+		};
+	};
+
+	state_emmc: state {
+		compatible = "barebox,state";
+		magic = <0xabff4b1f>;
+		backend-type = "raw";
+		backend = <&backend_state_emmc>;
+		backend-storage-type="direct";
+		backend-stridesize = <0x40>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		bootstate {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			system0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@0 {
+					reg = <0x0 0x4>;
+					type = "uint32";
+					default = <2>;
+				};
+
+				priority@4 {
+					reg = <0x4 0x4>;
+					type= "uint32";
+					default = <21>;
+				};
+			};
+
+			system1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@8 {
+					reg = <0x8 0x4>;
+					type = "uint32";
+					default = <2>;
+				};
+
+				priority@c {
+					reg = <0xC 0x4>;
+					type= "uint32";
+					default = <20>;
+				};
+			};
+
+			last_chosen@10 {
+				reg = <0x10 0x4>;
+				type = "uint32";
+			};
+
+		};
+
+	};
+};
+
+&usdhc3 { /* on-SoM eMMC */
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	env_emmc: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+
+	backend_state_emmc: partition@100000 {
+		label = "state";
+		reg = <0x100000 0x20000>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-koenigbauer-alphajet.kernel.dts b/arch/arm/dts/imx8mp-koenigbauer-alphajet.kernel.dts
new file mode 100644
index 0000000000..3f958ddf78
--- /dev/null
+++ b/arch/arm/dts/imx8mp-koenigbauer-alphajet.kernel.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-FileCopyrightText: 2023 Pengutronix
+
+/dts-v1/;
+
+#include "imx8mp-congatec-qmx8p.kernel.dtsi"
+
+/ {
+	model = "Koenig+Bauer Alphajet";
+	compatible = "koenigbauer,alphajet", "congatec,qmxp8p", "fsl,imx8mp";
+
+	display {
+		compatible = "innolux,g101ice-l01";
+		backlight = <&lvds0_backlight>;
+		power-supply = <&reg_lfp_vdd>;
+
+		port {
+			panel_in_lvds0: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+	};
+};
+
+&eqos { /* baseboard connects to on-SoM PHY */
+	status = "okay";
+};
+
+&gpu2d {
+	status = "okay";
+};
+
+&gpu3d {
+	status = "okay";
+};
+
+&lcdif2 {
+	/* pin IMX8MP_VIDEO_PLL1 to provide bitclock needed by LVDS panel */
+	assigned-clock-rates = <0>, <995400000>;
+	status = "okay";
+};
+
+&lvds0_backlight {
+	status = "okay";
+};
+
+&lvds_bridge {
+	status = "okay";
+
+	ports {
+		port@1 {
+			ldb_lvds_ch0: endpoint {
+				remote-endpoint = <&panel_in_lvds0>;
+			};
+		};
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pwm2 { /* PWM Backlight */
+	status = "okay";
+};
+
+&uart1 { /* Baseboard UART0 */
+	/delete-property/ uart-has-rtscts; /* not connected on baseboard */
+	status = "okay";
+};
+
+&usb_dwc3_0 { /* Baseboard J13 – Top Connector */
+	/* FIXME: overcurrent pin is handled via TUSB8041 (which one?) */
+	status = "okay";
+};
+
+&usdhc1 { /* Baseboard J8 - µSD Card slot */
+	status = "okay";
+	/delete-property/ cd-gpios; /* no CD is tied to GND on baseboard */
+	/delete-property/ wp-gpios; /* no WP is tied to GND on baseboard */
+	broken-cd;                  /* do not wait for CD interrupt */
+};
+
+&usdhc2 { /* on-SoM µSD Card slot is not used */
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx8mp-skov.dts b/arch/arm/dts/imx8mp-skov.dts
new file mode 100644
index 0000000000..254e68feca
--- /dev/null
+++ b/arch/arm/dts/imx8mp-skov.dts
@@ -0,0 +1,620 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mp.dtsi>
+#include "imx8mp.dtsi"
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Skov i.MX8MP";
+	compatible = "skov,imx8mp", "fsl,imx8mp";
+
+	chosen {
+		stdout-path = &uart2;
+
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &usdhc2, "partname:barebox-environment";
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &usdhc3, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &lan1;
+		ethernet2 = &lan2;
+		state = &state;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_led>;
+
+		led-0 {
+			label = "D1";
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_STATUS;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led-1 {
+			label = "D2";
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led-2 {
+			label = "D3";
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* Address will be determined by the bootloader */
+		ramoops {
+			compatible = "ramoops";
+		};
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	state: state {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		magic = <0x1c5b3f49>;
+		compatible = "barebox,state";
+		backend-type = "raw";
+		backend = <&usdhc3>;
+                /*
+                 * barebox-state partition size: 1 MiB
+                 * nr. of redundant copies:      4
+                 * ==> max. stride size: 1 MiB / 4 = 256 KiB = 262144 Byte
+                 *
+                 * stride size:     262144 Byte
+                 * raw-header:     -    16 Byte
+                 * direct-storage: -     8 Byte
+                 *                 ------------
+                 * max state size:  262120 Byte
+                 *                  ===========
+                 */
+		backend-stridesize = <0x40000>;
+
+		bootstate {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			system0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@0 {
+					reg = <0x0 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+				priority@4 {
+					reg = <0x4 0x4>;
+					type = "uint32";
+					default = <30>;
+				};
+			};
+
+			system1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@8 {
+					reg = <0x8 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+				priority@C {
+					reg = <0xC 0x4>;
+					type = "uint32";
+					default = <20>;
+				};
+			};
+
+			last_chosen@10 {
+				reg = <0x10 0x4>;
+				type = "uint32";
+			};
+		};
+
+		display {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			xres@14 {
+				reg = <0x14 0x4>;
+				type = "uint32";
+				default = <0>;
+			};
+
+			yres@18 {
+				reg = <0x18 0x4>;
+				type = "uint32";
+				default = <0>;
+			};
+
+			brightness@1C {
+				reg = <0x1C 0x1>;
+				type = "uint8";
+				default = <8>;
+			};
+
+			external@1D {
+				reg = <0x1D 0x1>;
+				type = "uint8";
+				default = <0>;
+			};
+		};
+
+		ethaddr {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			eth2@1e {
+				reg = <0x1E 0x6>;
+				type = "mac";
+				default = [00 11 22 33 44 55];
+			};
+		};
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-connection-type = "rgmii";
+	status = "okay";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic@25 {
+		compatible = "nxp,pca9450c";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+		reset-source-priority = <500>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
+			};
+
+			buck4: BUCK4 {
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5 {
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	switch@5f {
+		compatible = "microchip,ksz9893";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_switch>;
+		reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+		reg = <0x5f>;
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			lan1: port@0 {
+				reg = <0>;
+				phy-mode = "internal";
+				label = "lan1";
+				nvmem-cells = <&eth_mac1>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			lan2: port@1 {
+				reg = <1>;
+				phy-mode = "internal";
+				label = "lan2";
+				nvmem-cells = <&eth_mac2>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "cpu";
+				ethernet = <&eqos>;
+				/* 2ns rgmii-rxid is implemented on PCB.
+				 * Switch should add only rgmii-txid.
+				 */
+				phy-mode = "rgmii-txid";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart2 {
+	/* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+/* SD Card */
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			/* varaint id */
+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08				0x100
+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09				0x100
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10				0x100
+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11				0x100
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12				0x100
+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13				0x100
+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14				0x100
+			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15				0x100
+		>;
+	};
+
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+		>;
+	};
+
+	pinctrl_gpio_led: gpioledgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x19
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06				0x19
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07				0x19
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c3
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c3
+		>;
+	};
+
+	pinctrl_switch: switchgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01				0x41
+		>;
+	};
+
+	pinctrl_pmic: pmicirqgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03				0x41
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19				0x41
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX				0x14f
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX				0x14f
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d4
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d6
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12				0x1c4
+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20					0x1c4
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
new file mode 100644
index 0000000000..bf23e40489
--- /dev/null
+++ b/arch/arm/dts/imx8mp-tqma8mpql-mba8mpxl.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
+ */
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts>
+#include "imx8mp.dtsi"
+
+/ {
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &env_sd2;
+			status = "disabled";
+		};
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_sd3;
+			status = "disabled";
+		};
+	};
+};
+
+/delete-node/ &{/memory@40000000};
+
+&usdhc2 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	env_sd2: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&usdhc3 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	env_sd3: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-var-dart-dt8mcustomboard.dts b/arch/arm/dts/imx8mp-var-dart-dt8mcustomboard.dts
new file mode 100644
index 0000000000..ab4c5790cf
--- /dev/null
+++ b/arch/arm/dts/imx8mp-var-dart-dt8mcustomboard.dts
@@ -0,0 +1,680 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2020-2021 Variscite Ltd.
+ * Copyright 2023 VAHLE Automation GmbH
+ */
+
+#include "imx8mp-var-dart.dtsi"
+
+/ {
+	model = "Variscite DART-MX8M-PLUS on DT8MCustomBoard 2.x";
+
+	chosen {
+		stdout-path = &uart1;
+
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &env_sd;
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &env_emmc;
+			status = "disabled";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		back {
+			label = "Back";
+			linux,code = <KEY_BACK>;
+			gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		up {
+			label = "Up";
+			linux,code = <KEY_UP>;
+			gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		home {
+			label = "Home";
+			linux,code = <KEY_HOME>;
+			gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		down {
+			label = "Down";
+			linux,code = <KEY_DOWN>;
+			gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		gp-led1 {
+			label = "led1";
+			gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		gp-led2 {
+			label = "led2";
+			gpios = <&pca6408_2 6 GPIO_ACTIVE_HIGH>;
+		};
+
+		gp-led3 {
+			label = "led3";
+			gpios = <&pca6408_2 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		gp-led4 {
+			label = "eMMC";
+			gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc2";
+		};
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		startup-delay-us = <100>;
+		off-on-delay-us = <12000>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 1000000 0>;
+
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <80>;
+	};
+
+	can0_osc: can0_osc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <40000000>;
+	};
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&eqos {
+	mdio {
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			at803x,eee-disabled;
+			eee-broken-1000t;
+			reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <20000>;
+			vddio-supply = <&vddio1>;
+
+			vddio1: vddio-regulator {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+};
+
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "disabled";
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	typec@3d {
+		compatible = "nxp,ptn5150";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_extcon>;
+		reg = <0x3d>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+		irq-is-id-quirk;
+
+		port {
+			typec_dr_sw: endpoint {
+				remote-endpoint = <&usb3_drd_sw>;
+			};
+		};
+	};
+
+	/* DS1337 RTC module */
+	rtc@68 {
+		compatible = "dallas,ds1337";
+		reg = <0x68>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_rtc>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+		wakeup-source;
+	};
+
+	/* Capacitive touch controller */
+	ft5x06_ts: ft5x06_ts@38 {
+		compatible = "edt,edt-ft5206";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_captouch>;
+		reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+		wakeup-source;
+	};
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pca6408_1: gpio@20 {
+		compatible = "nxp,pcal6408";
+		standard-regs-fallback;
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pca6408>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+	};
+
+	pca6408_2: gpio@21 {
+		compatible = "nxp,pcal6408";
+		standard-regs-fallback;
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	status = "okay";
+};
+
+&pcie {
+	reset-gpio = <&pca6408_2 3 GPIO_ACTIVE_LOW>;
+	ext_osc = <1>;
+	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+		 <&clk IMX8MP_CLK_PCIE_AUX>,
+		 <&clk IMX8MP_CLK_HSIO_AXI>,
+		 <&clk IMX8MP_CLK_PCIE_ROOT>;
+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+			  <&clk IMX8MP_CLK_PCIE_AUX>;
+	assigned-clock-rates = <500000000>, <10000000>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
+				 <&clk IMX8MP_SYS_PLL2_50M>;
+	l1ss-disabled;
+	status = "okay";
+};
+
+&pcie_phy {
+	ext_osc = <1>;
+	status = "okay";
+};
+
+/* Console */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+/* Header */
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+/* Header */
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	fsl,phy-tx-vref-tune = <0xe>;
+	fsl,phy-tx-preemp-amp-tune = <3>;
+	fsl,phy-tx-vboost-level = <5>;
+	fsl,phy-comp-dis-tune = <7>;
+	fsl,pcs-tx-deemph-3p5db = <0x21>;
+	fsl,phy-pcs-tx-swing-full = <0x7f>;
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	role-switch-default-mode = "none";
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+
+	port {
+		usb3_drd_sw: endpoint {
+			remote-endpoint = <&typec_dr_sw>;
+		};
+	};
+};
+
+&usb3_phy1 {
+	fsl,phy-tx-preemp-amp-tune = <3>;
+	fsl,phy-tx-vref-tune = <0xb>;
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+};
+
+&usdhc2 {
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+
+	partition@0 {
+		compatible = "fixed-partitions";
+		label = "barebox";
+		reg = <0x00000000 0x00000000 0x000e0000>;
+	};
+
+	env_sd: partition@e0000 {
+		compatible = "fixed-partitions";
+		label = "barebox-environment";
+		reg = <0x00000000 0x000e0000 0x00020000>;
+	};
+};
+
+&usdhc3 {
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	env_emmc: partition@e0000 {
+		label = "barebox-environment";
+		reg = <0x00000000 0x000e0000 0x00020000>;
+	};
+};
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	cs-gpios = <&gpio5  9 GPIO_ACTIVE_LOW>,
+		   <&gpio1 12 GPIO_ACTIVE_LOW>,
+		   <&gpio2 10 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	/* Resistive touch controller */
+	ads7846@0 {
+		compatible = "ti,ads7846";
+		reg = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_restouch>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+		spi-max-frequency = <1500000>;
+		pendown-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+		ti,x-min = /bits/ 16 <125>;
+		ti,x-max = /bits/ 16 <4008>;
+		ti,y-min = /bits/ 16 <282>;
+		ti,y-max = /bits/ 16 <3864>;
+		ti,x-plate-ohms = /bits/ 16 <180>;
+		ti,pressure-max = /bits/ 16 <255>;
+		ti,debounce-max = /bits/ 16 <10>;
+		ti,debounce-tol = /bits/ 16 <3>;
+		ti,debounce-rep = /bits/ 16 <1>;
+		ti,settle-delay-usec = /bits/ 16 <150>;
+		ti,keep-vref-on;
+		wakeup-source;
+	};
+
+	can0: can@1 {
+		compatible = "microchip,mcp251xfd";
+		reg = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_can>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+		clocks = <&can0_osc>;
+		spi-max-frequency = <20000000>;
+	};
+
+	spidev@2 {
+		compatible = "var,spidev";
+		reg = <2>;
+		spi-max-frequency = <12000000>;
+	};
+};
+
+&ldo4 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x400001c2
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA			0x400001c2
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD				0x40000010
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC				0x40000010
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT				0x116
+		>;
+	};
+
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0				0x90
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1				0x90
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2				0x90
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3				0x90
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC				0x90
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL			0x90
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0				0x00
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1				0x00
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2				0x00
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3				0x00
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL			0x00
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC				0x00
+		>;
+	};
+
+	pinctrl_flexspi0: flexspi0grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK				0x1c2
+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B			0x82
+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00			0x82
+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01			0x82
+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02			0x82
+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03			0x82
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16				0x1c2
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17				0x1c2
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18				0x1c2
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19				0x1c2
+		>;
+	};
+
+	pinctrl_i2c4_gpio: i2c4gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20				0x1c2
+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21				0x1c2
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX				0x40
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX				0x40
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX				0x40
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX				0x40
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX				0x40
+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX				0x40
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX				0x140
+			MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX				0x140
+			MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS				0x140
+			MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS				0x140
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2grp-gpio {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 				0x1c4
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19				0x40
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d0
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT				0xc0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 			0xc0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d6
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 			0xc0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK				0x12
+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI				0x12
+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO				0x12
+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09				0x12
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12				0x12
+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10				0x12
+		>;
+	};
+
+	pinctrl_captouch: captouchgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14				0x16
+		>;
+	};
+
+
+	pinctrl_restouch: restouchgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07				0xc0
+		>;
+	};
+
+	pinctrl_extcon: extcongrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10				0x10
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_RXC__CAN1_TX					0x154
+			MX8MP_IOMUXC_SAI2_TXC__CAN1_RX					0x154
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX					0x154
+			MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX					0x154
+		>;
+	};
+
+	pinctrl_can: cangrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06				0x1c6
+			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04				0x16
+		>;
+	};
+
+	pinctrl_pca6408: pca6408grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x1c6
+		>;
+	};
+
+	pinctrl_gpio_leds: ledgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18				0xc6
+		>;
+	};
+
+	pinctrl_rtc: rtcgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 				0x1c0
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-var-dart.dtsi b/arch/arm/dts/imx8mp-var-dart.dtsi
new file mode 100644
index 0000000000..75c31b07f1
--- /dev/null
+++ b/arch/arm/dts/imx8mp-var-dart.dtsi
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2020-2021 Variscite Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include <arm64/freescale/imx8mp.dtsi>
+#include "imx8mp.dtsi"
+
+/ {
+	compatible = "variscite,imx8mp-var-dart", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &fec;
+	};
+
+	reg_eqos_phy: regulator-eqos-phy {
+		compatible = "regulator-fixed";
+		regulator-name = "eqos-phy";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-enable-ramp-delay = <20000>;
+		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	reg_audio: regulator-audio-vdd {
+		compatible = "regulator-fixed";
+		regulator-name = "wm8904_supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,eee-disabled;
+			eee-broken-1000t;
+			reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <20000>;
+			vddio-supply = <&vddio0>;
+
+			vddio0: vddio-regulator {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pca9450@25 {
+		reg = <0x25>;
+		compatible = "nxp,pca9450c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
+			};
+
+			buck4: BUCK4 {
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5 {
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+/* WIFI */
+&usdhc1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
+	bus-width = <4>;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+
+	brcmf: bcrmf@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20					0x10
+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11				0x150
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14				0x1c2
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15				0x1c2
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03				0x1c0
+		>;
+	};
+
+	pinctrl_sai3: sai3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC			0xd6
+			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK			0xd6
+			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00			0xd6
+			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00			0xd6
+			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK			0xd6
+			MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC			0xd6
+			MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK			0xd6
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK				0x190
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD				0x1d0
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0				0x1d0
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1				0x1d0
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2				0x1d0
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3				0x1d0
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK				0x194
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD				0x1d4
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0				0x1d4
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1				0x1d4
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2				0x1d4
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3				0x1d4
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK				0x196
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD				0x1d6
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0				0x1d6
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1				0x1d6
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2				0x1d6
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3				0x1d6
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6
+		>;
+	};
+
+	pinctrl_wifi: wifigrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07				0xc0 /* WIFI_EN  */
+			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08				0xc0 /* WIFI_PWR */
+		>;
+	};
+
+	pinctrl_bt: btgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06				0xc0 /* BT_EN  */
+			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09				0xc0 /* BT_BUF */
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index b251ebeada..4d1f1bf588 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -1,9 +1,112 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 
+#include <dt-bindings/features/imx8m.h>
+
 / {
 	remoteproc_cm7: remoteproc-cm7 {
 		compatible = "fsl,imx8mp-cm7";
 		clocks = <&clk IMX8MP_CLK_M7_CORE>;
 		syscon = <&src>;
 	};
+
+	aliases {
+		pwm0 = &pwm1;
+		pwm1 = &pwm2;
+		pwm2 = &pwm3;
+		pwm3 = &pwm4;
+	};
+
+	chosen {
+		barebox,bootsource-mmc0 = &usdhc1;
+		barebox,bootsource-mmc1 = &usdhc2;
+		barebox,bootsource-mmc2 = &usdhc3;
+	};
+};
+
+/*
+ * The DSP reserved memory will collide with the Barebox malloc area for some
+ * DRAM sizes, even though the DSP itself is disabled in most configurations.
+ */
+/delete-node/ &dsp_reserved;
+&dsp {
+	barebox,feature-gates = <&feat IMX8M_FEAT_DSP>;
+	/delete-property/ memory-region;
+	status = "disabled";
+};
+
+&edacmc {
+	compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a";
+};
+
+feat: &ocotp {
+	#feature-cells = <1>;
+	barebox,feature-controller;
+};
+
+&pgc_gpu2d {
+	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&pgc_gpu3d {
+	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&pgc_gpumix {
+	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&mipi_dsi {
+	barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>;
+};
+
+&lcdif1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>;
+};
+
+&gpu3d {
+	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&gpu2d {
+	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&pgc_vpumix {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_vc8000e {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_g1 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_g2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpumix_blk_ctrl {
+	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_mlmix {
+	barebox,feature-gates = <&feat IMX8M_FEAT_NPU>;
+};
+
+&lcdif2 {
+	barebox,feature-gates = <&feat IMX8M_FEAT_LVDS>;
+};
+
+&lvds_bridge {
+	barebox,feature-gates = <&feat IMX8M_FEAT_LVDS>;
 };
diff --git a/arch/arm/dts/imx8mq-ddrc.dtsi b/arch/arm/dts/imx8mq-ddrc.dtsi
index 1df39151a1..6961477eef 100644
--- a/arch/arm/dts/imx8mq-ddrc.dtsi
+++ b/arch/arm/dts/imx8mq-ddrc.dtsi
@@ -8,3 +8,7 @@
 	/delete-node/ memory@40000000;
 };
 
+&ddrc {
+	status = "okay";
+};
+
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 8ef2c984ac..2e753aeb0f 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -14,12 +14,12 @@
 	chosen {
 		environment-emmc {
 			compatible = "barebox,environment";
-			device-path = &usdhc1, "partname:barebox-environment";
+			device-path = &env_sd1;
 			status = "disabled";
 		};
 		environment-sd {
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 			status = "disabled";
 		};
 	};
@@ -34,7 +34,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd1: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
@@ -49,7 +49,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts
index 5a65324b3c..b048faa2b1 100644
--- a/arch/arm/dts/imx8mq-mnt-reform2.dts
+++ b/arch/arm/dts/imx8mq-mnt-reform2.dts
@@ -6,109 +6,31 @@
 
 /dts-v1/;
 
-#include <arm64/freescale/imx8mq.dtsi>
+#include <arm64/freescale/imx8mq-mnt-reform2.dts>
 #include "imx8mq.dtsi"
 #include "imx8mq-ddrc.dtsi"
 
 / {
-	model = "MNT Reform2";
-	compatible = "mntre,reform2", "fsl,imx8mq";
-
 	chosen {
-		stdout-path = &uart1;
-
 		environment-emmc {
 			compatible = "barebox,environment";
-			device-path = &usdhc1, "partname:barebox-environment";
+			device-path = &env_sd1;
 			status = "disabled";
 		};
 
 		environment-sd {
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 			status = "disabled";
 		};
 	};
-
-	pcie1_refclk: pcie1-refclk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-	};
-};
-
-&fec1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec1>;
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethphy0>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@4 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <4>;
-			interrupts = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
-			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
-		};
-	};
 };
 
 &ocotp {
 	barebox,provide-mac-address = <&fec1 0x640>;
 };
 
-&pcie1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pcie1>;
-	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
-		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	status = "okay";
-};
-
-&usb3_phy0 {
-	status = "okay";
-};
-
-&usb3_phy1 {
-	status = "okay";
-};
-
-&usb_dwc3_0 {
-	status = "okay";
-	dr_mode = "host";
-};
-
-&usb_dwc3_1 {
-	status = "okay";
-	dr_mode = "host";
-};
-
 &usdhc1 {
-	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
-	assigned-clock-rates = <400000000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	bus-width = <8>;
-	no-mmc-hs400;
-	non-removable;
-	no-sd;
-	no-sdio;
-	status = "okay";
-
 	#address-cells = <1>;
 	#size-cells = <1>;
 
@@ -117,21 +39,13 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd1: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
 };
 
 &usdhc2 {
-	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
-	assigned-clock-rates = <200000000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	bus-width = <4>;
-	no-1-8-v;
-	status = "okay";
-
 	#address-cells = <1>;
 	#size-cells = <1>;
 
@@ -140,84 +54,8 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
 };
-
-&wdog1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_wdog>;
-	fsl,ext-reset-output;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_fec1: fec1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
-			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
-			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
-			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
-			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
-			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
-			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
-			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0xd1
-			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
-			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0xd1
-			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x1
-			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x1
-		>;
-	};
-
-	pinctrl_pcie1: pcie1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
-		>;
-	};
-
-	pinctrl_uart1: uart1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x45
-			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x45
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
-			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
-			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
-			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
-			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
-			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
-			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
-			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
-			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
-			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
-			MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x41
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x03
-			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
-			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
-			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
-			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
-			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc
-		>;
-	};
-
-	pinctrl_wdog: wdog1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
-		>;
-	};
-};
diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi
index 896993a0e2..d45c243027 100644
--- a/arch/arm/dts/imx8mq-zii-ultra.dtsi
+++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi
@@ -10,12 +10,12 @@
 	chosen {
 		environment-emmc {
 			compatible = "barebox,environment";
-			device-path = &usdhc1, "partname:barebox-environment";
+			device-path = &env_sd1;
 			status = "disabled";
 		};
 		environment-sd {
 			compatible = "barebox,environment";
-			device-path = &usdhc2, "partname:barebox-environment";
+			device-path = &env_sd2;
 			status = "disabled";
 		};
 	};
@@ -64,31 +64,27 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&uart2 {
-	rave-sp {
-		watchdog {
-			nvmem-cells = <&boot_source>;
-			nvmem-cell-names = "boot-source";
-		};
+&{uart2/mcu/watchdog} {
+	nvmem-cells = <&boot_source>;
+	nvmem-cell-names = "boot-source";
+};
 
-		eeprom@a4 {
-			lru_part_number: lru-part-number@21 {
-				reg = <0x21 15>;
-				read-only;
-			};
+&{uart2/mcu/eeprom@a4} {
+	lru_part_number: lru-part-number@21 {
+		reg = <0x21 15>;
+		read-only;
+	};
 
-			boot_source: boot-source@83 {
-				reg = <0x83 1>;
-			};
+	boot_source: boot-source@83 {
+		reg = <0x83 1>;
+	};
 
-			mac_address_0: mac-address@180 {
-				reg = <0x180 6>;
-			};
+	mac_address_0: mac-address@180 {
+		reg = <0x180 6>;
+	};
 
-			mac_address_1: mac-address@190 {
-				reg = <0x190 6>;
-			};
-		};
+	mac_address_1: mac-address@190 {
+		reg = <0x190 6>;
 	};
 };
 
@@ -101,7 +97,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd1: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
@@ -116,7 +112,7 @@
 		reg = <0x0 0xe0000>;
 	};
 
-	partition@e0000 {
+	env_sd2: partition@e0000 {
 		label = "barebox-environment";
 		reg = <0xe0000 0x20000>;
 	};
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index e56cdfe130..7cdbafcffe 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -5,6 +5,11 @@
  */
 
 / {
+	chosen {
+		barebox,bootsource-mmc0 = &usdhc1;
+		barebox,bootsource-mmc1 = &usdhc2;
+	};
+
 	remoteproc_cm4: remoteproc-cm4 {
 		compatible = "fsl,imx8mq-cm4";
 		clocks = <&clk IMX8MQ_CLK_M4_CORE>;
diff --git a/arch/arm/dts/imx93-tqma9352-mba93xxca.dts b/arch/arm/dts/imx93-tqma9352-mba93xxca.dts
new file mode 100644
index 0000000000..b77f8b9f9a
--- /dev/null
+++ b/arch/arm/dts/imx93-tqma9352-mba93xxca.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+
+#include <arm64/freescale/imx93-tqma9352-mba93xxca.dts>
+#include "imx93.dtsi"
+#include "imx93-tqma93xx.dtsi"
diff --git a/arch/arm/dts/imx93-tqma9352-mba93xxla.dts b/arch/arm/dts/imx93-tqma9352-mba93xxla.dts
new file mode 100644
index 0000000000..d1d68a55e1
--- /dev/null
+++ b/arch/arm/dts/imx93-tqma9352-mba93xxla.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+
+#include <arm64/freescale/imx93-tqma9352-mba93xxla.dts>
+#include "imx93.dtsi"
+#include "imx93-tqma93xx.dtsi"
diff --git a/arch/arm/dts/imx93-tqma93xx.dtsi b/arch/arm/dts/imx93-tqma93xx.dtsi
new file mode 100644
index 0000000000..40425e39a7
--- /dev/null
+++ b/arch/arm/dts/imx93-tqma93xx.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+
+/{
+	chosen {
+		environment-spi-nor {
+			compatible = "barebox,environment";
+			device-path = &environment_spi_nor;
+		};
+	};
+};
+
+&lpi2c1 {
+	pca9451a: pmic@25 {
+		compatible = "nxp,pca9451a";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pca9451>;
+	};
+};
+
+&usbotg1 {
+	status = "okay";
+};
+
+&usbotg2 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&{flexspi1/flash@0} {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x400000>;
+		};
+
+		environment_spi_nor: partition@400000 {
+			label = "barebox-environment";
+			reg = <0x400000 0x100000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
new file mode 100644
index 0000000000..b931586d74
--- /dev/null
+++ b/arch/arm/dts/imx93.dtsi
@@ -0,0 +1,88 @@
+/{
+	chosen {
+		barebox,bootsource-mmc0 = &usdhc1;
+		barebox,bootsource-mmc1 = &usdhc2;
+		barebox,bootsource-mmc2 = &usdhc3;
+	};
+
+	soc@0 {
+		usbphynop1: usbphynop1 {
+			compatible = "usb-nop-xceiv";
+			clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+			clock-names = "main_clk";
+		};
+
+		usbotg1: usb@4c100000 {
+			compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+			reg = <0x4c100000 0x200>;
+			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
+				 <&clk IMX93_CLK_HSIO_32K_GATE>;
+			clock-names = "usb_ctrl_root_clk", "usb_wakeup_clk";
+			assigned-clocks = <&clk IMX93_CLK_HSIO>;
+			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+			assigned-clock-rates = <133000000>;
+			fsl,usbphy = <&usbphynop1>;
+			fsl,usbmisc = <&usbmisc1 0>;
+			status = "disabled";
+		};
+
+		usbmisc1: usbmisc@4c100200 {
+			compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+			#index-cells = <1>;
+			reg = <0x4c100200 0x200>;
+		};
+
+		usbphynop2: usbphynop2 {
+			compatible = "usb-nop-xceiv";
+			clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+			clock-names = "main_clk";
+		};
+
+		usbotg2: usb@4c200000 {
+			compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+			reg = <0x4c200000 0x200>;
+			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
+				 <&clk IMX93_CLK_HSIO_32K_GATE>;
+			clock-names = "usb_ctrl_root_clk", "usb_wakeup_clk";
+			assigned-clocks = <&clk IMX93_CLK_HSIO>;
+			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+			assigned-clock-rates = <133000000>;
+			fsl,usbphy = <&usbphynop2>;
+			fsl,usbmisc = <&usbmisc2 0>;
+			status = "disabled";
+		};
+
+		usbmisc2: usbmisc@4c200200 {
+			compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+			#index-cells = <1>;
+			reg = <0x4c200200 0x200>;
+		};
+
+		ddrc: memory-controller@4e300000 {
+			compatible = "fsl,imx93-ddrc";
+			reg = <0x4e300000 0x400000>;
+		};
+	};
+};
+
+&fec {
+	nvmem-cells = <&eth_mac1>;
+	nvmem-cell-names = "mac-address";
+};
+
+&eqos {
+	nvmem-cells = <&eth_mac2>;
+	nvmem-cell-names = "mac-address";
+};
+
+&ocotp {
+	eth_mac1: mac-address@4ec {
+		reg = <0x4ec 6>;
+	};
+
+	eth_mac2: mac-address@4f2 {
+		reg = <0x4f2 6>;
+	};
+};
diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts
new file mode 100644
index 0000000000..b4606ff129
--- /dev/null
+++ b/arch/arm/dts/k3-am625-beagleplay.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+
+#include <arm64/ti/k3-am625-beagleplay.dts>
+
+/ {
+	chosen {
+		stdout-path = &main_uart0;
+	};
+};
+
+&sd_pins_default {
+	pinctrl-single,pins = <
+		AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
+		AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
+		AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
+		AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
+		AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
+		AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
+		/*
+		 * The upstream dts configures this as MMC1_SDCD.GPIO1_48 and
+		 * uses main_gpio1 48 as card detect GPIO. With this the
+		 * MMC driver doesn't doesn't detect the card. Upstream
+		 * dts has the ti,fails-without-test-cd property which
+		 * purpose seems to be to work around this issue. This
+		 * doesn't work either in barebox. For now configure the
+		 * pin as native SDHCI card detect.
+		 */
+		AM62X_IOPAD(0x0240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
+	>;
+};
diff --git a/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts
index 1be03a7ac0..7374c23c2b 100644
--- a/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts
+++ b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts
@@ -3,7 +3,7 @@
  *   Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  */
 
-#include "arm/kirkwood-guruplug-server-plus.dts"
+#include "arm/marvell/kirkwood-guruplug-server-plus.dts"
 
 &{/gpio-leds/health-r} {
 	barebox,default-trigger = "heartbeat";
diff --git a/arch/arm/dts/kirkwood-openblocks_a6-bb.dts b/arch/arm/dts/kirkwood-openblocks_a6-bb.dts
index b13ab2ab93..748a57f924 100644
--- a/arch/arm/dts/kirkwood-openblocks_a6-bb.dts
+++ b/arch/arm/dts/kirkwood-openblocks_a6-bb.dts
@@ -2,7 +2,7 @@
  * Barebox specific DT overlay for OpenBlocks A6 board
  */
 
-#include "arm/kirkwood-openblocks_a6.dts"
+#include "arm/marvell/kirkwood-openblocks_a6.dts"
 
 &{/gpio-leds/led-green} {
 	barebox,default-trigger = "heartbeat";
diff --git a/arch/arm/dts/kirkwood-topkick-bb.dts b/arch/arm/dts/kirkwood-topkick-bb.dts
index c70d654c52..d99eba0274 100644
--- a/arch/arm/dts/kirkwood-topkick-bb.dts
+++ b/arch/arm/dts/kirkwood-topkick-bb.dts
@@ -3,7 +3,7 @@
  *   Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  */
 
-#include "arm/kirkwood-topkick.dts"
+#include "arm/marvell/kirkwood-topkick.dts"
 
 &{/gpio-leds/system} {
 	barebox,default-trigger = "heartbeat";
diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts
index daa75b831f..35aba4f5a6 100644
--- a/arch/arm/dts/rk3188-radxarock.dts
+++ b/arch/arm/dts/rk3188-radxarock.dts
@@ -12,7 +12,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arm/rk3188-radxarock.dts>
+#include <arm/rockchip/rk3188-radxarock.dts>
 
 / {
 	chosen {
@@ -20,8 +20,7 @@
 
 		environment {
 			compatible = "barebox,environment";
-			device-path = &mmc0, "partname:barebox-environment";
-			status = "okay";
+			device-path = &env_mmc0;
 		};
 	};
 };
@@ -34,7 +33,8 @@
 		label = "barebox";
 		reg = <0x0 0x80000>;
 	};
-	partition@80000 {
+
+	env_mmc0: partition@80000 {
 		label = "barebox-environment";
 		reg = <0x80000 0x80000>;
 	};
diff --git a/arch/arm/dts/rk3288-phycore-som.dts b/arch/arm/dts/rk3288-phycore-som.dts
index 67073b2d83..2e4fe44479 100644
--- a/arch/arm/dts/rk3288-phycore-som.dts
+++ b/arch/arm/dts/rk3288-phycore-som.dts
@@ -14,7 +14,7 @@
 
 /dts-v1/;
 
-#include <arm/rk3288.dtsi>
+#include <arm/rockchip/rk3288.dtsi>
 
 / {
 	model = "phycore-rk3288";
@@ -49,13 +49,13 @@
 
 		environment-emmc {
 			compatible = "barebox,environment";
-			device-path = &emmc, "partname:barebox-environment";
+			device-path = &env_emmc;
 			status = "disabled";
 		};
 
 		environment-sdmmc {
 			compatible = "barebox,environment";
-			device-path = &sdmmc, "partname:barebox-environment";
+			device-path = &env_sdmmc;
 			status = "disabled";
 		};
 	};
@@ -100,7 +100,7 @@
 		reg = <0x20000 0x80000>;
 	};
 
-	partition@a0000 {
+	env_emmc: partition@a0000 {
 		label = "barebox-environment";
 		reg = <0xa0000 0x20000>;
 	};
@@ -131,7 +131,7 @@
 		reg = <0x20000 0x80000>;
 	};
 
-	partition@a0000 {
+	env_sdmmc: partition@a0000 {
 		label = "barebox-environment";
 		reg = <0xa0000 0x20000>;
 	};
diff --git a/arch/arm/dts/rk3566-cm3-io.dts b/arch/arm/dts/rk3566-cm3-io.dts
new file mode 100644
index 0000000000..39cef5e797
--- /dev/null
+++ b/arch/arm/dts/rk3566-cm3-io.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/rockchip/rk3566-radxa-cm3-io.dts>
+#include "rk356x.dtsi"
+
+/ {
+	chosen: chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &environment_sd;
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &environment_emmc;
+			status = "disabled";
+		};
+	};
+};
+
+&sdhci {
+	no-sd;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_emmc: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
+
+&sdmmc0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_sd: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts
new file mode 100644
index 0000000000..0036ef31f1
--- /dev/null
+++ b/arch/arm/dts/rk3566-quartz64-a.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/rockchip/rk3566-quartz64-a.dts>
+#include "rk356x.dtsi"
+
+/ {
+	memory@a00000 {
+		device_type = "memory";
+		reg = <0x0 0x00a00000 0x0 0x7f600000>;
+	};
+};
diff --git a/arch/arm/dts/rk3568-bpi-r2-pro.dts b/arch/arm/dts/rk3568-bpi-r2-pro.dts
new file mode 100644
index 0000000000..58a2bc442f
--- /dev/null
+++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ *
+ */
+
+/dts-v1/;
+#include "arm64/rockchip/rk3568-bpi-r2-pro.dts"
+/ {
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &environment_sd;
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &environment_emmc;
+			status = "disabled";
+		};
+	};
+
+	memory@a00000 {
+		device_type = "memory";
+		reg = <0x0 0x00a00000 0x0 0x7f600000>;
+	};
+};
+
+&sdhci {
+	no-sd;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_emmc: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
+
+&sdmmc0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_sd: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+};
diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
new file mode 100644
index 0000000000..82186ff86e
--- /dev/null
+++ b/arch/arm/dts/rk3568-evb1-v10.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <arm64/rockchip/rk3568-evb1-v10.dts>
+#include "rk356x.dtsi"
+
+/ {
+	chosen: chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &environment_sd;
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &environment_emmc;
+			status = "disabled";
+		};
+	};
+
+	memory@a00000 {
+		device_type = "memory";
+		reg = <0x0 0x00a00000 0x0 0x7f600000>;
+	};
+};
+
+&sdhci {
+	no-sd;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_emmc: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
+
+&sdmmc0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_sd: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts
new file mode 100644
index 0000000000..25a0c05737
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/rockchip/rk3568-rock-3a.dts>
+#include "rk356x.dtsi"
+
+/ {
+	chosen: chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &environment_sd;
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &environment_emmc;
+			status = "disabled";
+		};
+	};
+
+	memory@a00000 {
+		device_type = "memory";
+		reg = <0x0 0x00a00000 0x0 0x7f600000>;
+	};
+};
+
+&sdhci {
+	no-sd;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_emmc: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
+
+&sdmmc0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_sd: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
new file mode 100644
index 0000000000..923e18e7cc
--- /dev/null
+++ b/arch/arm/dts/rk356x.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/ {
+	chosen {
+		barebox,bootsource-mmc0 = &sdhci;
+		barebox,bootsource-mmc1 = &sdmmc0;
+		barebox,bootsource-mmc2 = &sdmmc1;
+	};
+
+	dmc: memory-controller {
+		compatible = "rockchip,rk3568-dmc";
+		rockchip,pmu = <&pmugrf>;
+	};
+
+	otp: nvmem@fe38c000 {
+		compatible = "rockchip,rk3568-otp";
+		reg = <0x0 0xfe38c000 0x0 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpu_id: id@a {
+			reg = <0x0a 0x10>;
+		};
+	};
+
+	rng: rng@fe388000 {
+		compatible = "rockchip,rk3568-rng", "rockchip,cryptov2-rng";
+		reg = <0x0 0xfe388000 0x0 0x2000>;
+		clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+		clock-names = "trng_clk", "trng_hclk";
+		resets = <&cru SRST_TRNG_NS>;
+	};
+};
diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts
new file mode 100644
index 0000000000..ddff76028e
--- /dev/null
+++ b/arch/arm/dts/rk3588-rock-5b.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/rockchip/rk3588-rock-5b.dts>
+#include "rk3588.dtsi"
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		mmc1 = &sdmmc;
+	};
+
+	chosen: chosen {
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &environment_emmc;
+			status = "disabled";
+		};
+
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &environment_sd;
+			status = "disabled";
+		};
+	};
+};
+
+&sdhci {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_emmc: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
+
+&sdmmc {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		environment_sd: partition@408000 {
+			label = "barebox-environment";
+			reg = <0x0 0x408000 0x0 0x8000>;
+		};
+	};
+};
+
+&pcie3x4 {
+	/* Does not work in barebox (missing phy driver) */
+	status = "disabled";
+};
+
+&pcie30phy {
+	status = "disabled";
+};
+
+&pcie2x1l2 {
+	/*
+	 * Originally in upstream dts this is:
+	 * ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+	 *          <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
+	 *          <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
+	 *
+	 * Overwriting this shouldn't be necessary, but without it PCI doesn't
+	 * work. We have some deficiency in the PCI driver that causes this.
+	 */
+	ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+		 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
+		 <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
+};
+
+&pcie2x1l0 {
+	/* Does not work in barebox */
+	status = "disabled";
+};
+
+&usb_host0_ehci {
+	/* Does not work in barebox (missing phy driver) */
+	status = "disabled";
+};
+
+&usb_host1_ehci {
+	/* Does not work in barebox (missing phy driver) */
+	status = "disabled";
+};
diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
new file mode 100644
index 0000000000..0aef30eaff
--- /dev/null
+++ b/arch/arm/dts/rk3588.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/phy/phy.h>
+#include "rk3588s.dtsi"
+
+/ {
+};
diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
new file mode 100644
index 0000000000..6572588ad6
--- /dev/null
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -0,0 +1,12 @@
+/ {
+	dmc: memory-controller {
+		compatible = "rockchip,rk3588-dmc";
+		rockchip,pmu = <&pmu1grf>;
+	};
+};
+
+&scmi_clk {
+	assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
+			  <&scmi_clk SCMI_CLK_CPUB23>;
+	assigned-clock-rates = <816000000>, <816000000>;
+};
diff --git a/arch/arm/dts/rockchip-pinconf.dtsi b/arch/arm/dts/rockchip-pinconf.dtsi
new file mode 100644
index 0000000000..5c645437b5
--- /dev/null
+++ b/arch/arm/dts/rockchip-pinconf.dtsi
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+&pinctrl {
+	/omit-if-no-ref/
+	pcfg_pull_up: pcfg-pull-up {
+		bias-pull-up;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down: pcfg-pull-down {
+		bias-pull-down;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none: pcfg-pull-none {
+		bias-disable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+		bias-disable;
+		drive-strength = <0>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+		bias-disable;
+		drive-strength = <1>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+		bias-disable;
+		drive-strength = <2>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+		bias-disable;
+		drive-strength = <3>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
+		bias-disable;
+		drive-strength = <4>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
+		bias-disable;
+		drive-strength = <5>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
+		bias-disable;
+		drive-strength = <6>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
+		bias-disable;
+		drive-strength = <7>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
+		bias-disable;
+		drive-strength = <8>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
+		bias-disable;
+		drive-strength = <9>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
+		bias-disable;
+		drive-strength = <10>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
+		bias-disable;
+		drive-strength = <11>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
+		bias-disable;
+		drive-strength = <12>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
+		bias-disable;
+		drive-strength = <13>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
+		bias-disable;
+		drive-strength = <14>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
+		bias-disable;
+		drive-strength = <15>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+		bias-pull-up;
+		drive-strength = <0>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+		bias-pull-up;
+		drive-strength = <1>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+		bias-pull-up;
+		drive-strength = <2>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
+		bias-pull-up;
+		drive-strength = <3>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
+		bias-pull-up;
+		drive-strength = <4>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
+		bias-pull-up;
+		drive-strength = <5>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
+		bias-pull-up;
+		drive-strength = <6>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
+		bias-pull-up;
+		drive-strength = <7>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
+		bias-pull-up;
+		drive-strength = <8>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
+		bias-pull-up;
+		drive-strength = <9>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
+		bias-pull-up;
+		drive-strength = <10>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
+		bias-pull-up;
+		drive-strength = <11>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
+		bias-pull-up;
+		drive-strength = <12>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
+		bias-pull-up;
+		drive-strength = <13>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
+		bias-pull-up;
+		drive-strength = <14>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
+		bias-pull-up;
+		drive-strength = <15>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
+		bias-pull-down;
+		drive-strength = <0>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
+		bias-pull-down;
+		drive-strength = <1>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
+		bias-pull-down;
+		drive-strength = <3>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
+		bias-pull-down;
+		drive-strength = <4>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
+		bias-pull-down;
+		drive-strength = <5>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
+		bias-pull-down;
+		drive-strength = <6>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
+		bias-pull-down;
+		drive-strength = <7>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
+		bias-pull-down;
+		drive-strength = <8>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
+		bias-pull-down;
+		drive-strength = <9>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
+		bias-pull-down;
+		drive-strength = <10>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
+		bias-pull-down;
+		drive-strength = <11>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
+		bias-pull-down;
+		drive-strength = <12>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
+		bias-pull-down;
+		drive-strength = <13>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
+		bias-pull-down;
+		drive-strength = <14>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
+		bias-pull-down;
+		drive-strength = <15>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_smt: pcfg-pull-up-smt {
+		bias-pull-up;
+		input-schmitt-enable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_smt: pcfg-pull-down-smt {
+		bias-pull-down;
+		input-schmitt-enable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_smt: pcfg-pull-none-smt {
+		bias-disable;
+		input-schmitt-enable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
+		bias-disable;
+		drive-strength = <0>;
+		input-schmitt-enable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_output_high: pcfg-output-high {
+		output-high;
+	};
+
+	/omit-if-no-ref/
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+};
diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi
new file mode 100644
index 0000000000..658292792f
--- /dev/null
+++ b/arch/arm/dts/sama5d3.dtsi
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/ {
+	aliases {
+		mmc0 = &mmc0;
+		mmc1 = &mmc1;
+	};
+};
+
+/* Will be automatically read back from HW */
+/delete-node/ &{/memory@20000000};
diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi
new file mode 100644
index 0000000000..d7dbba667d
--- /dev/null
+++ b/arch/arm/dts/sama5d4.dtsi
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/ {
+	aliases {
+		mmc0 = &mmc0;
+		mmc1 = &mmc1;
+	};
+};
+
+/delete-node/ &{/memory@20000000};
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 7789c9d3b5..56dbf0b97d 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -4,6 +4,10 @@
 	};
 };
 
+&mmc {
+	reset-names = "reset";
+};
+
 &watchdog0 {
 	resets = <&rst L4WD0_RESET>;
 };
diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts
index 6071dbfb49..fbfdc9a882 100644
--- a/arch/arm/dts/socfpga_arria10_achilles.dts
+++ b/arch/arm/dts/socfpga_arria10_achilles.dts
@@ -15,7 +15,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 /dts-v1/;
-#include <arm/socfpga_arria10.dtsi>
+#include <arm/intel/socfpga/socfpga_arria10.dtsi>
 
 / {
 	model = "Reflex SOCFPGA Arria 10 Achilles";
@@ -108,19 +108,19 @@
 	};
 };
 
-&{/soc/clkmgr@ffd04000/clocks/osc1} {
+&osc1 {
 	clock-frequency = <25000000>;
 };
 
-&{/soc/clkmgr@ffd04000/clocks/cb_intosc_hs_div2_clk} {
+&cb_intosc_hs_div2_clk {
 	clock-frequency = <0>;
 };
 
-&{/soc/clkmgr@ffd04000/clocks/cb_intosc_ls_clk} {
+&cb_intosc_ls_clk {
 	clock-frequency = <60000000>;
 };
 
-&{/soc/clkmgr@ffd04000/clocks/f2s_free_clk} {
+&f2s_free_clk {
 	clock-frequency = <200000000>;
 };
 
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/dts/socfpga_arria10_mercury_aa1.dts
new file mode 100644
index 0000000000..84d4534cc6
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include <arm/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi>
+
+/ {
+	aliases {
+		mmc0 = &mmc;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+
+		environment {
+			compatible = "barebox,environment";
+			device-path = &environment_mmc;
+		};
+	};
+};
+
+// provide reset-names until fixed in the upstream dts. Binding prescribes this property.
+&mmc {
+	reset-names = "reset";
+};
+
+// This clock is unused, but fixed-clocks need to have a clock-frequency set
+&cb_intosc_hs_div2_clk {
+	clock-frequency = <0>;
+};
+
+&cb_intosc_ls_clk {
+	clock-frequency = <60000000>;
+};
+
+&f2s_free_clk {
+	clock-frequency = <200000000>;
+};
+
+&mmc {
+	bus-width = <8>;
+	non-removable;
+	disable-wp;
+	no-sd;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#size-cells = <1>;
+		#address-cells = <1>;
+
+		// This must be marked as an "A2" partition in the partition table
+		barebox1_xload: partition@100000 {
+			label = "barebox1-xload";
+			reg = <0x100000 0x40000>;
+		};
+
+		barebox2_xload: partition@140000 {
+			label = "barebox2-xload";
+			reg = <0x140000 0x40000>;
+		};
+
+		barebox1: partition@200000 {
+			label = "barebox1";
+			reg = <0x200000 0x100000>;
+		};
+
+		barebox2: partition@300000 {
+			label = "barebox2";
+			reg = <0x300000 0x100000>;
+		};
+
+		environment_mmc: partition@400000 {
+			label = "environment";
+			reg = <0x400000 0x8000>;
+		};
+
+		// This is actually the second partition on the mmc. It has no filesystem.
+		bitstream1: partition@700000 {
+			label = "bitstream1";
+			reg = <0x700000 0x2000000>;
+		};
+
+		bitstream2: partition@2700000 {
+			label = "bitstream2";
+			reg = <0x2700000 0x2000000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
index 427f150fb4..479c81476d 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -15,13 +15,10 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <arm/socfpga_cyclone5_de0_nano_soc.dts>
+#include <arm/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts>
 #include "socfpga.dtsi"
 
 / {
-	model = "Terasic DE0-Nano-SoC/Atlas-SoC Kit";
-	compatible = "terasic,de0-nano-soc","altr,socfpga-cyclone5", "altr,socfpga";
-
 	chosen {
 		stdout-path = &uart0;
 
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
new file mode 100644
index 0000000000..4a47773a78
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * socfpga_cyclone5_de10_nano.dts - Device Tree File for Terasic DE10-Nano
+ * Copyright (C) 2021 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
+ */
+
+#include <arm/intel/socfpga/socfpga_cyclone5.dtsi>
+#include "socfpga.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Terasic DE10-Nano";
+	compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "earlyprintk";
+		stdout-path = &uart0;
+
+		environment {
+			compatible = "barebox,environment";
+			device-path = &mmc, "partname:1";
+			file-path = "barebox.env";
+		};
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	aliases {
+		ethernet0 = &gmac1;
+	};
+
+	regulator_3_3v: 3-3-v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		hps_hkey0 {
+			label = "HPS_KEY";
+			gpios = <&portb 25 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_0>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		hps0 {
+			label = "hps_led0";
+			gpios = <&portb 24 0>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	txd0-skew-ps = <0>; /* -420ps */
+	txd1-skew-ps = <0>; /* -420ps */
+	txd2-skew-ps = <0>; /* -420ps */
+	txd3-skew-ps = <0>; /* -420ps */
+	rxd0-skew-ps = <420>; /* 0ps */
+	rxd1-skew-ps = <420>; /* 0ps */
+	rxd2-skew-ps = <420>; /* 0ps */
+	rxd3-skew-ps = <420>; /* 0ps */
+	txen-skew-ps = <0>; /* -420ps */
+	txc-skew-ps = <1860>; /* 960ps */
+	rxdv-skew-ps = <420>; /* 0ps */
+	rxc-skew-ps = <1680>; /* 780ps */
+
+	max-frame-size = <3800>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	adxl345: adxl345@53 {
+		compatible = "adi,adxl345";
+		reg = <0x53>;
+
+		interrupt-parent = <&portc>;
+		interrupts = <3 2>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&mmc0 {
+	vmmc-supply = <&regulator_3_3v>;
+	vqmmc-supply = <&regulator_3_3v>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index f0a6ae98ed..ef1f9af9cf 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -15,7 +15,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <arm/socfpga_cyclone5_socdk.dts>
+#include <arm/intel/socfpga/socfpga_cyclone5_socdk.dts>
 #include "socfpga.dtsi"
 
 / {
@@ -31,22 +31,6 @@
 	};
 };
 
-&qspi {
-	status = "okay";
-
-	flash: flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "n25q00";
-		reg = <0>;
-		spi-max-frequency = <108000000>;
-		m25p,fast-read;
-		cdns,page-size = <256>;
-		cdns,block-size = <16>;
-		cdns,read-delay = <4>;
-		cdns,tshsl-ns = <50>;
-		cdns,tsd2d-ns = <50>;
-		cdns,tchsh-ns = <4>;
-		cdns,tslch-ns = <4>;
-	};
+&flash0 {
+	compatible = "n25q00";
 };
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts
index 23e07c964c..0c377477f3 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -15,13 +15,10 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <arm/socfpga_cyclone5_sockit.dts>
+#include <arm/intel/socfpga/socfpga_cyclone5_sockit.dts>
 #include "socfpga.dtsi"
 
 / {
-	model = "Terasic SoCkit";
-	compatible = "terasic,sockit", "altr,socfpga";
-
 	chosen {
 		stdout-path = &uart0;
 
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index e731b55a6c..627a306b8a 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -15,7 +15,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <arm/socfpga_cyclone5_socrates.dts>
+#include <arm/intel/socfpga/socfpga_cyclone5_socrates.dts>
 #include "socfpga.dtsi"
 
 / {
@@ -34,52 +34,39 @@
 	};
 };
 
-&qspi {
-	status = "okay";
+&flash {
+	compatible = "n25q00";
+	cdns,page-size = <256>;
+	cdns,block-size = <16>;
+	cdns,read-delay = <4>;
 
-	flash: flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "n25q00";
-		reg = <0>;
-		spi-max-frequency = <100000000>;
-		m25p,fast-read;
-		cdns,page-size = <256>;
-		cdns,block-size = <16>;
-		cdns,read-delay = <4>;
-		cdns,tshsl-ns = <50>;
-		cdns,tsd2d-ns = <50>;
-		cdns,tchsh-ns = <4>;
-		cdns,tslch-ns = <4>;
-
-		partition@0 {
-			label = "prebootloader0";
-			reg = <0x00000 0x10000>;
-		};
+	partition@0 {
+		label = "prebootloader0";
+		reg = <0x00000 0x10000>;
+	};
 
-		partition@1 {
-			label = "prebootloader1";
-			reg = <0x10000 0x10000>;
-		};
+	partition@1 {
+		label = "prebootloader1";
+		reg = <0x10000 0x10000>;
+	};
 
-		partition@2 {
-			label = "prebootloader2";
-			reg = <0x20000 0x10000>;
-		};
+	partition@2 {
+		label = "prebootloader2";
+		reg = <0x20000 0x10000>;
+	};
 
-		partition@3 {
-			label = "prebootloader3";
-			reg = <0x30000 0x10000>;
-		};
+	partition@3 {
+		label = "prebootloader3";
+		reg = <0x30000 0x10000>;
+	};
 
-		partition@4 {
-			label = "barebox";
-			reg = <0x40000 0x80000>;
-		};
+	partition@4 {
+		label = "barebox";
+		reg = <0x40000 0x80000>;
+	};
 
-		partition@5 {
-			label = "data";
-			reg = <0xc0000 0x1f40000>;
-		};
+	partition@5 {
+		label = "data";
+		reg = <0xc0000 0x1f40000>;
 	};
 };
diff --git a/arch/arm/dts/state-example.dtsi b/arch/arm/dts/state-example.dtsi
index 490ee7840b..4572168336 100644
--- a/arch/arm/dts/state-example.dtsi
+++ b/arch/arm/dts/state-example.dtsi
@@ -89,28 +89,29 @@
 
 };
 
-&ecspi3 {
-	flash@0 {
-		backend_state_nor: partition@120000 {
-		};
-	};
+backend_state_nor: &{ecspi3/flash@0/partitions/partition@120000} {
 };
 
-&gpmi {
-	backend_state_nand: partition@500000 {
+/* Reduce barebox partition size from 16M to 15M */
+&{gpmi/partitions/partition@0} {
+	reg = <0x0 0xf00000>;
+};
+
+&{gpmi/partitions} {
+	backend_state_nand: partition@f00000 {
+		label = "barebox-state";
+		reg = <0xf00000 0x100000>;
 	};
 };
 
-&i2c1 {
-	eeprom@50 {
-		partitions {
-			compatible = "fixed-partitions";
-			#size-cells = <1>;
-			#address-cells = <1>;
-			backend_state_eeprom: state@400 {
-				reg = <0x400 0x400>;
-				label = "state-eeprom";
-			};
+&som_eeprom { /* On I2C1 */
+	partitions {
+		compatible = "fixed-partitions";
+		#size-cells = <1>;
+		#address-cells = <1>;
+		backend_state_eeprom: state@400 {
+			reg = <0x400 0x400>;
+			label = "state-eeprom";
 		};
 	};
 };
@@ -125,4 +126,4 @@
 			label = "state-sd";
 		};
 	};
-};
\ No newline at end of file
+};
diff --git a/arch/arm/dts/stm32mp1-scmi-smc.dtsi b/arch/arm/dts/stm32mp1-scmi-smc.dtsi
new file mode 100644
index 0000000000..590df657e9
--- /dev/null
+++ b/arch/arm/dts/stm32mp1-scmi-smc.dtsi
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+
+/ {
+	firmware {
+		scmi: scmi {
+			compatible = "arm,scmi-smc";
+			shmem = <&scmi0_shm>;
+			arm,smc-id = <0x82002000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			scmi_reset: protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
+		};
+	};
+
+	soc {
+		sram@2ffff000 {
+			compatible = "mmio-sram";
+			reg = <0x2ffff000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x2ffff000 0x1000>;
+
+			scmi0_shm: scmi_shm@0 {
+				compatible = "arm,scmi-shmem";
+				reg = <0 0x80>;
+			};
+
+			scmi1_shm: scmi_shm@200 {
+				compatible = "arm,scmi-shmem";
+				reg = <0x200 0x80>;
+			};
+		};
+	};
+};
+
+/delete-node/ &clk_hse;
+/delete-node/ &clk_hsi;
+/delete-node/ &clk_lse;
+/delete-node/ &clk_lsi;
+/delete-node/ &clk_csi;
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
new file mode 100644
index 0000000000..89a7ffcb81
--- /dev/null
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/ {
+	aliases {
+		mmc0 = &sdmmc1;
+	};
+};
+
+&{/soc} {
+	memory-controller@5a003000 {
+		compatible = "st,stm32mp13-ddr";
+		reg = <0x5a003000 0x1000>;
+	};
+};
+
+&iwdg2 {
+	barebox,restart-warm-bootrom;
+};
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
new file mode 100644
index 0000000000..5f0f52d005
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+
+#include <arm/st/stm32mp135f-dk.dts>
+#include "stm32mp131.dtsi"
+
+/ {
+	model = "STM32MP135F-DK";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+
+		environment {
+			compatible = "barebox,environment";
+			device-path = &sdmmc1, "partname:barebox-environment";
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32mp151-prtt1a.dts b/arch/arm/dts/stm32mp151-prtt1a.dts
new file mode 100644
index 0000000000..0f3c50f3e9
--- /dev/null
+++ b/arch/arm/dts/stm32mp151-prtt1a.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+// SPDX-FileCopyrightText: 2021 David Jander, Protonic Holland
+// SPDX-FileCopyrightText: 2021 Oleksij Rempel, Pengutronix
+/dts-v1/;
+
+#include "stm32mp151-prtt1l.dtsi"
+#include "stm32mp151-prtt1l-net.dtsi"
+
+/ {
+	model = "Protonic PRTT1A";
+	compatible = "prt,prtt1a", "st,stm32mp151";
+
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &sdmmc1, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32mp151-prtt1c.dts b/arch/arm/dts/stm32mp151-prtt1c.dts
new file mode 100644
index 0000000000..4eaf6712a5
--- /dev/null
+++ b/arch/arm/dts/stm32mp151-prtt1c.dts
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+// SPDX-FileCopyrightText: 2021 David Jander, Protonic Holland
+// SPDX-FileCopyrightText: 2021 Oleksij Rempel, Pengutronix
+/dts-v1/;
+
+#include "stm32mp151-prtt1l.dtsi"
+
+/ {
+	model = "Protonic PRTT1C";
+	compatible = "prt,prtt1c", "st,stm32mp151";
+
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &sdmmc1, "partname:barebox-environment";
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &sdmmc2, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+
+	aliases {
+		mdio-gpio0 = &mdio0;
+	};
+
+	clock_ksz9031: clock-ksz9031 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	mdio0: mdio {
+		compatible = "virtual,mdio-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
+			 &gpioa 2 GPIO_ACTIVE_HIGH>;
+
+		t1l0_phy: ethernet-phy@6 {
+			compatible = "ethernet-phy-id2000.0181";
+			reg = <6>;
+			interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
+		};
+
+		t1l1_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-id2000.0181";
+			reg = <7>;
+			interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
+		};
+
+		t1l2_phy: ethernet-phy@10 {
+			compatible = "ethernet-phy-id2000.0181";
+			reg = <10>;
+			interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
+		};
+
+		rj45_phy: ethernet-phy@2 {
+			reg = <2>;
+			interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <1000>;
+
+			clocks = <&clock_ksz9031>;
+		};
+	};
+
+	spi-gpio-0 {
+		compatible = "spi-gpio";
+		gpio-sck = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+		gpio-mosi = <&gpiob 5 GPIO_ACTIVE_HIGH>;
+		gpio-miso = <&gpioa 6 GPIO_ACTIVE_HIGH>;
+		cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
+		num-chipselects = <1>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch@0 {
+			compatible = "nxp,sja1105q";
+			reg = <0>;
+			spi-max-frequency = <4000000>;
+			spi-rx-delay-us = <1>;
+			spi-tx-delay-us = <1>;
+			spi-cpha;
+
+			reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					label = "t1l0";
+					phy-mode = "rmii";
+					phy-handle = <&t1l0_phy>;
+				};
+
+				port@1 {
+					reg = <1>;
+					label = "t1l1";
+					phy-mode = "rmii";
+					phy-handle = <&t1l1_phy>;
+				};
+
+				port@2 {
+					reg = <2>;
+					phy-mode = "rmii";
+					label = "t1l2";
+					phy-handle = <&t1l2_phy>;
+				};
+
+				port@3 {
+					reg = <3>;
+					label = "rj45";
+					phy-handle = <&rj45_phy>;
+					phy-mode = "rgmii-id";
+				};
+
+				port@4 {
+					reg = <4>;
+					label = "cpu";
+					ethernet = <&ethernet0>;
+					phy-mode = "rmii";
+
+					fixed-link {
+						speed = <100>;
+						full-duplex;
+					};
+				};
+			};
+		};
+	};
+
+
+};
+
+&ethernet0 {
+	pinctrl-0 = <&ethernet0_rmii_pins_a>;
+	pinctrl-names = "default";
+	phy-mode = "rmii";
+	status = "okay";
+
+	fixed-link {
+		speed = <100>;
+		full-duplex;
+	};
+};
+
+&sdmmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+	disable-wp;
+	disable-cd;
+	no-removable;
+	no-sd;
+	no-sdio;
+	no-1-8-v;
+	st,neg-edge;
+	bus-width = <8>;
+	vmmc-supply = <&v3v3>;
+	vqmmc-supply = <&v3v3>;
+	status = "okay";
+};
+
+&ethernet0_rmii_pins_a {
+	pins1 {
+		pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
+			 <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
+			 <STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */
+	};
+	pins2 {
+		pinmux = <STM32_PINMUX('C', 4, AF11)>,  /* ETH1_RMII_RXD0 */
+			 <STM32_PINMUX('C', 5, AF11)>,  /* ETH1_RMII_RXD1 */
+			 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK input */
+			 <STM32_PINMUX('A', 7, AF11)>;  /* ETH1_RMII_CRS_DV */
+	};
+};
+
+&sdmmc2_b4_pins_a {
+	pins1 {
+		pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+			 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+			 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+			 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+			 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+	};
+};
+
+&sdmmc2_d47_pins_a {
+	pins {
+		pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+			 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+			 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+			 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+	};
+};
diff --git a/arch/arm/dts/stm32mp151-prtt1l-net.dtsi b/arch/arm/dts/stm32mp151-prtt1l-net.dtsi
new file mode 100644
index 0000000000..04f4d64aaa
--- /dev/null
+++ b/arch/arm/dts/stm32mp151-prtt1l-net.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+// SPDX-FileCopyrightText: 2021 David Jander, Protonic Holland
+// SPDX-FileCopyrightText: 2021 Oleksij Rempel, Pengutronix
+
+&ethernet0 {
+	pinctrl-0 = <&ethernet0_rmii_pins_a>;
+	pinctrl-names = "default";
+	phy-mode = "rmii";
+	phy-reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&ethernet0_rmii_pins_a {
+	pins1 {
+		pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
+			 <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
+			 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
+			 <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */
+			 <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */
+	};
+	pins2 {
+		pinmux = <STM32_PINMUX('C', 4, AF11)>,  /* ETH1_RMII_RXD0 */
+			 <STM32_PINMUX('C', 5, AF11)>,  /* ETH1_RMII_RXD1 */
+			 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK input */
+			 <STM32_PINMUX('A', 7, AF11)>;  /* ETH1_RMII_CRS_DV */
+	};
+};
diff --git a/arch/arm/dts/stm32mp151-prtt1l.dtsi b/arch/arm/dts/stm32mp151-prtt1l.dtsi
new file mode 100644
index 0000000000..fffa64841b
--- /dev/null
+++ b/arch/arm/dts/stm32mp151-prtt1l.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+// SPDX-FileCopyrightText: 2021 David Jander, Protonic Holland
+// SPDX-FileCopyrightText: 2021 Oleksij Rempel, Pengutronix
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <arm/st/stm32mp151.dtsi>
+#include <arm/st/stm32mp15-pinctrl.dtsi>
+#include <arm/st/stm32mp15xxad-pinctrl.dtsi>
+
+#include "stm32mp151.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &uart4;
+		ethernet0 = &ethernet0;
+	};
+
+	v3v3: fixed-regulator-v3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "v3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	led {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "debug:red";
+			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+		};
+
+		led-1 {
+			label = "debug:green";
+			gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&usbh_ehci {
+	phys = <&usbphyc_port0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&usbotg_hs {
+	dr_mode = "host";
+	pinctrl-0 = <&usbotg_hs_pins_a>;
+	pinctrl-names = "default";
+	phys = <&usbphyc_port1 0>;
+	phy-names = "usb2-phy";
+	status = "okay";
+	g-tx-fifo-size = <128 128 128 16>;
+};
+
+&usbphyc {
+	status = "okay";
+};
+
+&usbphyc_port1 {
+	phy-supply = <&v3v3>;
+};
+
+&sdmmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_b4_pins_a>;
+	st,neg-edge;
+	bus-width = <4>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-ddr50;
+	vmmc-supply = <&v3v3>;
+	vqmmc-supply = <&v3v3>;
+	status = "okay";
+};
+
+&sdmmc1_b4_pins_a {
+	pins1 {
+		bias-pull-up;
+	};
+	pins2 {
+		bias-pull-up;
+	};
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_pins_a>;
+	status = "okay";
+};
+
+&uart4_pins_a {
+	pins1 {
+		pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
+		bias-disable;
+		drive-push-pull;
+		slew-rate = <0>;
+	};
+	pins2 {
+		pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+		bias-pull-up;
+	};
+};
diff --git a/arch/arm/dts/stm32mp151-prtt1s.dts b/arch/arm/dts/stm32mp151-prtt1s.dts
new file mode 100644
index 0000000000..f9093d01ac
--- /dev/null
+++ b/arch/arm/dts/stm32mp151-prtt1s.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+// SPDX-FileCopyrightText: 2021 David Jander, Protonic Holland
+// SPDX-FileCopyrightText: 2021 Oleksij Rempel, Pengutronix
+/dts-v1/;
+
+#include "stm32mp151-prtt1l.dtsi"
+#include "stm32mp151-prtt1l-net.dtsi"
+
+/ {
+	model = "Protonic PRTT1S";
+	compatible = "prt,prtt1s", "st,stm32mp151";
+
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &sdmmc1, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index f1fd888fa1..d3e924dc00 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -1,18 +1,6 @@
 
 / {
 	aliases {
-		gpio0 = &gpioa;
-		gpio1 = &gpiob;
-		gpio2 = &gpioc;
-		gpio3 = &gpiod;
-		gpio4 = &gpioe;
-		gpio5 = &gpiof;
-		gpio6 = &gpiog;
-		gpio7 = &gpioh;
-		gpio8 = &gpioi;
-		gpio9 = &gpioj;
-		gpio10 = &gpiok;
-		gpio25 = &gpioz;
 		mmc0 = &sdmmc1;
 		mmc1 = &sdmmc2;
 		mmc2 = &sdmmc3;
@@ -43,31 +31,24 @@
 		compatible = "st,stm32mp1-ddr";
 		reg = <0x5a003000 0x1000>;
 	};
-
-	tamp@5c00a000 {
-		compatible = "simple-bus", "syscon", "simple-mfd";
-		reg = <0x5c00a000 0x400>;
-
-		reboot_mode_tamp: reboot-mode {
-			compatible = "syscon-reboot-mode";
-			offset = <0x150>; /* reg20 */
-			mask = <0xff>;
-			mode-normal = <0>;
-			mode-loader = <0xBB>;
-			mode-recovery = <0xBC>;
-		};
-	};
 };
 
 &bsec {
 	barebox,provide-mac-address = <&ethernet0 0x39>;
 };
 
-&vrefbuf {
-	regulator-name = "vref";
+&iwdg2 {
+	barebox,restart-warm-bootrom;
 };
 
-&usbphyc {
-	vdda1v1-supply = <&reg11>;
-	vdda1v8-supply = <&reg18>;
+&tamp {
+	reboot_mode_tamp: reboot-mode {
+		compatible = "syscon-reboot-mode";
+		offset = <0x150>; /* reg20 */
+		mask = <0xffff>;
+		mode-normal = <0>;
+		mode-loader = <0xBB>;
+		mode-recovery = <0xBC>;
+		barebox,mode-serial = <0xFF>;
+	};
 };
diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dts
new file mode 100644
index 0000000000..7092b3af9f
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-dk1-scmi.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+
+#include <arm/st/stm32mp157a-dk1-scmi.dts>
+#include "stm32mp15xx-dkx.dtsi"
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 7a907cc314..d3395b0d95 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -4,5 +4,5 @@
  * Author: Alexandre Torgue <alexandre.torgue@st.com>.
  */
 
-#include <arm/stm32mp157a-dk1.dts>
+#include <arm/st/stm32mp157a-dk1.dts>
 #include "stm32mp15xx-dkx.dtsi"
diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dts
new file mode 100644
index 0000000000..7f01531986
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-dk2-scmi.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+
+#include <arm/st/stm32mp157c-dk2-scmi.dts>
+#include "stm32mp15xx-dkx.dtsi"
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index 98525abd71..e3840153ac 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -4,5 +4,5 @@
  * Author: Alexandre Torgue <alexandre.torgue@st.com>.
  */
 
-#include <arm/stm32mp157c-dk2.dts>
+#include <arm/st/stm32mp157c-dk2.dts>
 #include "stm32mp15xx-dkx.dtsi"
diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dts
new file mode 100644
index 0000000000..7cd279da4c
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ev1-scmi.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+
+#include <arm/st/stm32mp157c-ev1-scmi.dts>
+#include "stm32mp151.dtsi"
+
+/ {
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &sdmmc1, "partname:barebox-environment";
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &sdmmc2, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 742eca7a33..f1ca0cf997 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
 
-#include <arm/stm32mp157c-ev1.dts>
+#include <arm/st/stm32mp157c-ev1.dts>
 #include "stm32mp151.dtsi"
 
 / {
diff --git a/arch/arm/dts/stm32mp157c-lxa-mc1-scmi.dts b/arch/arm/dts/stm32mp157c-lxa-mc1-scmi.dts
new file mode 100644
index 0000000000..a7674cf0b3
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-lxa-mc1-scmi.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+#include "stm32mp157c-lxa-mc1.dts"
+#include "stm32mp1-scmi-smc.dtsi"
+
+/ {
+	model = "Linux Automation MC-1 SCMI board";
+	compatible = "lxa,stm32mp157c-mc1-scmi", "lxa,stm32mp157c-mc1",
+			   "oct,stm32mp15xx-osd32", "st,stm32mp157";
+
+};
+
+&cpu0 {
+	clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cpu1 {
+	clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&dsi {
+	clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+};
+
+&gpioz {
+	clocks = <&scmi_clk CK_SCMI_GPIOZ>;
+};
+
+&hash1 {
+	clocks = <&scmi_clk CK_SCMI_HASH1>;
+	resets = <&scmi_reset RST_SCMI_HASH1>;
+};
+
+&i2c4 {
+	clocks = <&scmi_clk CK_SCMI_I2C4>;
+	resets = <&scmi_reset RST_SCMI_I2C4>;
+};
+
+&iwdg2 {
+	clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
+};
+
+&mdma1 {
+	resets = <&scmi_reset RST_SCMI_MDMA>;
+};
+
+&rcc {
+	compatible = "st,stm32mp1-rcc-secure", "syscon";
+	clock-names = "hse", "hsi", "csi", "lse", "lsi";
+	clocks = <&scmi_clk CK_SCMI_HSE>,
+		 <&scmi_clk CK_SCMI_HSI>,
+		 <&scmi_clk CK_SCMI_CSI>,
+		 <&scmi_clk CK_SCMI_LSE>,
+		 <&scmi_clk CK_SCMI_LSI>;
+};
+
+&rng1 {
+	clocks = <&scmi_clk CK_SCMI_RNG1>;
+	resets = <&scmi_reset RST_SCMI_RNG1>;
+};
+
+&rtc {
+	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
+};
diff --git a/arch/arm/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/dts/stm32mp157c-lxa-mc1.dts
index f89c085280..1220a77c1b 100644
--- a/arch/arm/dts/stm32mp157c-lxa-mc1.dts
+++ b/arch/arm/dts/stm32mp157c-lxa-mc1.dts
@@ -3,7 +3,7 @@
  * Copyright (C) 2020 Ahmad Fatoum, Pengutronix
  */
 
-#include <arm/stm32mp157c-lxa-mc1.dts>
+#include <arm/st/stm32mp157c-lxa-mc1.dts>
 #include "stm32mp151.dtsi"
 
 / {
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi
deleted file mode 100644
index 1e5bd8bccb..0000000000
--- a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi
+++ /dev/null
@@ -1,294 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>.
- */
-
-/dts-v1/;
-
-#include <arm/stm32mp157.dtsi>
-#include <arm/stm32mp15xc.dtsi>
-#include <arm/stm32mp15-pinctrl.dtsi>
-#include <arm/stm32mp15xxac-pinctrl.dtsi>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
-	model = "Seeed Studio Odyssey-STM32MP157C SOM";
-	compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
-
-	memory@c0000000 {
-		device_type = "memory";
-		reg = <0xc0000000 0x20000000>;
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		mcuram2: mcuram2@10000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x10000000 0x40000>;
-			no-map;
-		};
-
-		vdev0vring0: vdev0vring0@10040000 {
-			compatible = "shared-dma-pool";
-			reg = <0x10040000 0x1000>;
-			no-map;
-		};
-
-		vdev0vring1: vdev0vring1@10041000 {
-			compatible = "shared-dma-pool";
-			reg = <0x10041000 0x1000>;
-			no-map;
-		};
-
-		vdev0buffer: vdev0buffer@10042000 {
-			compatible = "shared-dma-pool";
-			reg = <0x10042000 0x4000>;
-			no-map;
-		};
-
-		mcuram: mcuram@30000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x30000000 0x40000>;
-			no-map;
-		};
-
-		retram: retram@38000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x38000000 0x10000>;
-			no-map;
-		};
-
-		gpu_reserved: gpu@d4000000 {
-			reg = <0xd4000000 0x4000000>;
-			no-map;
-		};
-	};
-
-	led {
-		compatible = "gpio-leds";
-		led-blue {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_HEARTBEAT;
-			gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-		};
-	};
-};
-
-&gpu {
-	contiguous-area = <&gpu_reserved>;
-	status = "okay";
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins_a>;
-	i2c-scl-rising-time-ns = <185>;
-	i2c-scl-falling-time-ns = <20>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-
-	pmic: stpmic@33 {
-		compatible = "st,stpmic1";
-		reg = <0x33>;
-		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-
-		regulators {
-			compatible = "st,stpmic1-regulators";
-			ldo1-supply = <&v3v3>;
-			ldo3-supply = <&vdd_ddr>;
-			ldo6-supply = <&v3v3>;
-			pwr_sw1-supply = <&bst_out>;
-			pwr_sw2-supply = <&bst_out>;
-
-			vddcore: buck1 {
-				regulator-name = "vddcore";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd_ddr: buck2 {
-				regulator-name = "vdd_ddr";
-				regulator-min-microvolt = <1350000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd: buck3 {
-				regulator-name = "vdd";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-				st,mask-reset;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			v3v3: buck4 {
-				regulator-name = "v3v3";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-				regulator-over-current-protection;
-				regulator-initial-mode = <0>;
-			};
-
-			v1v8_audio: ldo1 {
-				regulator-name = "v1v8_audio";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-always-on;
-				interrupts = <IT_CURLIM_LDO1 0>;
-			};
-
-			v3v3_hdmi: ldo2 {
-				regulator-name = "v3v3_hdmi";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-				interrupts = <IT_CURLIM_LDO2 0>;
-			};
-
-			vtt_ddr: ldo3 {
-				regulator-name = "vtt_ddr";
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <750000>;
-				regulator-always-on;
-				regulator-over-current-protection;
-			};
-
-			vdd_usb: ldo4 {
-				regulator-name = "vdd_usb";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				interrupts = <IT_CURLIM_LDO4 0>;
-			};
-
-			vdda: ldo5 {
-				regulator-name = "vdda";
-				regulator-min-microvolt = <2900000>;
-				regulator-max-microvolt = <2900000>;
-				interrupts = <IT_CURLIM_LDO5 0>;
-				regulator-boot-on;
-			};
-
-			v1v2_hdmi: ldo6 {
-				regulator-name = "v1v2_hdmi";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-always-on;
-				interrupts = <IT_CURLIM_LDO6 0>;
-			};
-
-			vref_ddr: vref_ddr {
-				regulator-name = "vref_ddr";
-				regulator-always-on;
-				regulator-over-current-protection;
-			};
-
-			 bst_out: boost {
-				regulator-name = "bst_out";
-				interrupts = <IT_OCP_BOOST 0>;
-			 };
-
-			vbus_otg: pwr_sw1 {
-				regulator-name = "vbus_otg";
-				interrupts = <IT_OCP_OTG 0>;
-			 };
-
-			 vbus_sw: pwr_sw2 {
-				regulator-name = "vbus_sw";
-				interrupts = <IT_OCP_SWOUT 0>;
-				regulator-active-discharge;
-			 };
-		};
-
-		onkey {
-			compatible = "st,stpmic1-onkey";
-			interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
-			interrupt-names = "onkey-falling", "onkey-rising";
-			power-off-time-sec = <10>;
-		};
-
-		watchdog {
-			compatible = "st,stpmic1-wdt";
-			status = "disabled";
-		};
-	};
-};
-
-&ipcc {
-	status = "okay";
-};
-
-&iwdg2 {
-	timeout-sec = <32>;
-	status = "okay";
-};
-
-&m4_rproc {
-	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
-			<&vdev0vring1>, <&vdev0buffer>;
-	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
-	mbox-names = "vq0", "vq1", "shutdown";
-	interrupt-parent = <&exti>;
-	interrupts = <68 1>;
-	status = "okay";
-};
-
-&rng1 {
-	status = "okay";
-};
-
-&rtc {
-	status = "okay";
-};
-
-&sdmmc2_d47_pins_a {
-	pins {
-		pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
-			 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
-			 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
-			 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
-	};
-};
-
-&sdmmc2_d47_sleep_pins_a {
-	pins {
-		pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
-			 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
-			 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
-			 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
-	};
-};
-
-&sdmmc2 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
-	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
-	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	st,neg-edge;
-	bus-width = <8>;
-	vmmc-supply = <&v3v3>;
-	vqmmc-supply = <&v3v3>;
-	mmc-ddr-3_3v;
-	status = "okay";
-};
-
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts
index 0e395bdec9..9c9fd34ccd 100644
--- a/arch/arm/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/dts/stm32mp157c-odyssey.dts
@@ -3,7 +3,7 @@
  * Copyright (C) 2020 Ahmad Fatoum, Pengutronix
  */
 
-#include "stm32mp157c-odyssey.dtsi"
+#include <arm/st/stm32mp157c-odyssey.dts>
 #include "stm32mp151.dtsi"
 
 / {
@@ -21,7 +21,3 @@
 		};
 	};
 };
-
-&phy0 {
-	reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>;
-};
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dtsi b/arch/arm/dts/stm32mp157c-odyssey.dtsi
deleted file mode 100644
index 85a4f313ae..0000000000
--- a/arch/arm/dts/stm32mp157c-odyssey.dtsi
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>.
- */
-
-/dts-v1/;
-
-#include "stm32mp157c-odyssey-som.dtsi"
-
-/ {
-	model = "Seeed Studio Odyssey-STM32MP157C Board";
-	compatible = "seeed,stm32mp157c-odyssey",
-		     "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
-
-	aliases {
-		ethernet0 = &ethernet0;
-		serial0 = &uart4;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&ethernet0 {
-	status = "okay";
-	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
-	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
-	pinctrl-names = "default", "sleep";
-	phy-mode = "rgmii-id";
-	max-speed = <1000>;
-	phy-handle = <&phy0>;
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-		phy0: ethernet-phy@7 { /* KSZ9031RN */
-			reg = <7>;
-		};
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&i2c1_pins_a>;
-	pinctrl-1 = <&i2c1_sleep_pins_a>;
-	i2c-scl-rising-time-ns = <100>;
-	i2c-scl-falling-time-ns = <7>;
-	status = "okay";
-	/delete-property/dmas;
-	/delete-property/dma-names;
-};
-
-&sdmmc1 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc1_b4_pins_a>;
-	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
-	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
-	cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-	disable-wp;
-	st,neg-edge;
-	bus-width = <4>;
-	vmmc-supply = <&v3v3>;
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_a>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts
new file mode 100644
index 0000000000..6ad978f453
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
+ * Author: Dom VOVARD <dom.vovard@linrt.com>.
+ */
+
+/dts-v1/;
+
+#include <arm/st/stm32mp157c-phycore-stm32mp1-3.dts>
+#include "stm32mp151.dtsi"
+
+/ {
+	model = "PHYTEC phyCORE-STM32MP1-3 SoM";
+	compatible = "phytec,phycore-stm32mp1-3", "st,stm32mp157";
+
+	chosen {
+		environment-sd {
+			compatible = "barebox,environment";
+			device-path = &sdmmc1, "partname:barebox-environment";
+			status = "disabled";
+		};
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &sdmmc2, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+};
+
+&ethernet0_rgmii_pins_d {
+	/*
+	 * Kernel uses ETH_RGMII_CLK125 instead of ETH_RGMII_GTX_CLK. Drop this
+	 * once it is fixed upstream.
+	 */
+	pins1 {
+		pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+			 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+			 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+			 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+			 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+			 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+			 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+	};
+};
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts
index 027c2e5905..186985545b 100644
--- a/arch/arm/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -1,4 +1,4 @@
-#include <arm/tegra124-jetson-tk1.dts>
+#include <arm/nvidia/tegra124-jetson-tk1.dts>
 #include "tegra124.dtsi"
 
 / {
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index ce618db78c..abfa5f47ba 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -2,41 +2,41 @@
 
 / {
 	aliases {
-		mmc0 = "/sdhci@700b0000/";
-		mmc1 = "/sdhci@700b0200/";
-		mmc2 = "/sdhci@700b0400/";
-		mmc3 = "/sdhci@700b0600/";
+		mmc0 = &{/mmc@700b0000};
+		mmc1 = &{/mmc@700b0200};
+		mmc2 = &{/mmc@700b0400};
+		mmc3 = &{/mmc@700b0600};
 	};
+};
 
-	pcie-controller@01003000 {
-		phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
-		phy-names = "pcie";
-	};
+&{/pcie@1003000} {
+	phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
+	phy-names = "pcie";
+};
 
-	padctl@7009f000 {
-		pinctrl-0 = <&padctl_default>;
-		pinctrl-names = "default";
-		#phy-cells = <1>;
+&padctl {
+	pinctrl-0 = <&padctl_default>;
+	pinctrl-names = "default";
+	#phy-cells = <1>;
 
-		padctl_default: pinmux {
-			usb3 {
-				nvidia,lanes = "pcie-0", "pcie-1";
-				nvidia,function = "usb3";
-				nvidia,iddq = <0>;
-			};
+	padctl_default: pinmux {
+		usb3 {
+			nvidia,lanes = "pcie-0", "pcie-1";
+			nvidia,function = "usb3";
+			nvidia,iddq = <0>;
+		};
 
-			pcie {
-				nvidia,lanes = "pcie-2", "pcie-3",
-				               "pcie-4";
-				nvidia,function = "pcie";
-				nvidia,iddq = <0>;
-			};
+		pcie {
+			nvidia,lanes = "pcie-2", "pcie-3",
+				       "pcie-4";
+			nvidia,function = "pcie";
+			nvidia,iddq = <0>;
+		};
 
-			sata {
-				nvidia,lanes = "sata-0";
-				nvidia,function = "sata";
-				nvidia,iddq = <0>;
-			};
+		sata {
+			nvidia,lanes = "sata-0";
+			nvidia,function = "sata";
+			nvidia,iddq = <0>;
 		};
 	};
 };
diff --git a/arch/arm/dts/tegra20-colibri-iris.dts b/arch/arm/dts/tegra20-colibri-iris.dts
index da5ef7a7e7..e8bd8feb31 100644
--- a/arch/arm/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/dts/tegra20-colibri-iris.dts
@@ -9,72 +9,70 @@
 	chosen {
 		stdout-path = &uarta;
 	};
+};
 
-	host1x@50000000 {
-		hdmi@54280000 {
-			status = "okay";
-		};
-	};
-
-	pinmux@70000014 {
-		state_default: pinmux {
-			hdint {
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-
-			i2cddc {
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-
-			sdio4 {
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-
-			uarta {
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
+&{/host1x@50000000/hdmi@54280000} {
+	status = "okay";
+};
 
-			uartd {
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-		};
+&pinmux {
+	hdint {
+		nvidia,tristate = <TEGRA_PIN_DISABLE>;
 	};
 
-	serial@70006000 {
-		status = "okay";
+	i2cddc {
+		nvidia,tristate = <TEGRA_PIN_DISABLE>;
 	};
 
-	serial@70006300 {
-		status = "okay";
+	sdio4 {
+		nvidia,tristate = <TEGRA_PIN_DISABLE>;
 	};
 
-	i2c_ddc: i2c@7000c400 {
-		status = "okay";
+	uarta {
+		nvidia,tristate = <TEGRA_PIN_DISABLE>;
 	};
 
-	usb@c5000000 {
-		status = "okay";
+	uartd {
+		nvidia,tristate = <TEGRA_PIN_DISABLE>;
 	};
+};
 
-	usb-phy@c5000000 {
-		status = "okay";
-	};
+&uarta {
+	status = "okay";
+};
 
-	usb@c5008000 {
-		status = "okay";
-	};
+&uartd {
+	status = "okay";
+};
 
-	usb-phy@c5008000 {
-		status = "okay";
-	};
+i2c_ddc: &i2c2 {
+	status = "okay";
+};
 
-	sdhci@c8000600 {
-		status = "okay";
-		bus-width = <4>;
-		vmmc-supply = <&vcc_sd_reg>;
-		vqmmc-supply = <&vcc_sd_reg>;
-	};
+&{/usb@c5000000} {
+	status = "okay";
+};
+
+&phy1 {
+	status = "okay";
+};
+
+&{/usb@c5008000} {
+	status = "okay";
+};
+
+&phy3 {
+	status = "okay";
+};
 
+&{/mmc@c8000600} {
+	status = "okay";
+	bus-width = <4>;
+	vmmc-supply = <&vcc_sd_reg>;
+	vqmmc-supply = <&vcc_sd_reg>;
+};
+
+/ {
 	regulator_usb_host_vbus {
 		compatible = "regulator-fixed";
 		regulator-name = "usb_host_vbus";
diff --git a/arch/arm/dts/tegra20-colibri.dtsi b/arch/arm/dts/tegra20-colibri.dtsi
index 4f6dc9daf2..a9c2ad8bab 100644
--- a/arch/arm/dts/tegra20-colibri.dtsi
+++ b/arch/arm/dts/tegra20-colibri.dtsi
@@ -1,2 +1,2 @@
-#include <arm/tegra20-colibri.dtsi>
+#include <arm/nvidia/tegra20-colibri.dtsi>
 #include "tegra20.dtsi"
diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts
index f3a3759ebd..a9019d1959 100644
--- a/arch/arm/dts/tegra20-paz00.dts
+++ b/arch/arm/dts/tegra20-paz00.dts
@@ -1,2 +1,2 @@
-#include <arm/tegra20-paz00.dts>
+#include <arm/nvidia/tegra20-paz00.dts>
 #include "tegra20.dtsi"
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 995eee4a6e..02425874f6 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -1,8 +1,8 @@
 / {
 	aliases {
-		mmc0 = "/sdhci@c8000000/";
-		mmc1 = "/sdhci@c8000200/";
-		mmc2 = "/sdhci@c8000400/";
-		mmc3 = "/sdhci@c8000600/";
+		mmc0 = &{/mmc@c8000000};
+		mmc1 = &{/mmc@c8000200};
+		mmc2 = &{/mmc@c8000400};
+		mmc3 = &{/mmc@c8000600};
 	};
 };
diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index 7a9ced6cef..d6aa0e4d13 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-#include <arm/tegra30.dtsi>
+#include <arm/nvidia/tegra30.dtsi>
 #include "tegra30.dtsi"
 
 / {
@@ -8,8 +8,8 @@
 	compatible = "nvidia,beaver", "nvidia,tegra30";
 
 	aliases {
-		rtc0 = "/i2c@7000d000/tps65911@2d";
-		rtc1 = "/rtc@7000e000";
+		rtc0 = &pmic;
+		rtc1 = &{/rtc@7000e000};
 		serial0 = &uarta;
 	};
 
@@ -21,766 +21,764 @@
 			device-path = &emmc, "partname:boot1";
 		};
 	};
+};
+
+&{/pcie@3000} {
+	status = "okay";
+	pex-clk-supply = <&sys_3v3_pexs_reg>;
+	vdd-supply = <&ldo1_reg>;
+	avdd-supply = <&ldo2_reg>;
 
-	pcie-controller@00003000 {
+	pci@1,0 {
 		status = "okay";
-		pex-clk-supply = <&sys_3v3_pexs_reg>;
-		vdd-supply = <&ldo1_reg>;
-		avdd-supply = <&ldo2_reg>;
+		nvidia,num-lanes = <2>;
+	};
 
-		pci@1,0 {
-			status = "okay";
-			nvidia,num-lanes = <2>;
-		};
+	pci@2,0 {
+		nvidia,num-lanes = <2>;
+	};
 
-		pci@2,0 {
-			nvidia,num-lanes = <2>;
-		};
+	pci@3,0 {
+		status = "okay";
+		nvidia,num-lanes = <2>;
+	};
+};
+
+&{/host1x@50000000/hdmi@54280000} {
+	status = "okay";
+
+	vdd-supply = <&sys_3v3_reg>;
+	pll-supply = <&vio_reg>;
+
+	nvidia,hpd-gpio =
+		<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+	nvidia,ddc-i2c-bus = <&hdmiddc>;
+};
+
+&pinmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&state_default>;
 
-		pci@3,0 {
-			status = "okay";
-			nvidia,num-lanes = <2>;
+	state_default: pinmux {
+		sdmmc1_clk_pz0 {
+			nvidia,pins = "sdmmc1_clk_pz0";
+			nvidia,function = "sdmmc1";
+			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		sdmmc1_cmd_pz1 {
+			nvidia,pins =	"sdmmc1_cmd_pz1",
+					"sdmmc1_dat0_py7",
+					"sdmmc1_dat1_py6",
+					"sdmmc1_dat2_py5",
+					"sdmmc1_dat3_py4";
+			nvidia,function = "sdmmc1";
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		sdmmc3_clk_pa6 {
+			nvidia,pins = "sdmmc3_clk_pa6";
+			nvidia,function = "sdmmc3";
+			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		sdmmc3_cmd_pa7 {
+			nvidia,pins =	"sdmmc3_cmd_pa7",
+					"sdmmc3_dat0_pb7",
+					"sdmmc3_dat1_pb6",
+					"sdmmc3_dat2_pb5",
+					"sdmmc3_dat3_pb4";
+			nvidia,function = "sdmmc3";
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		sdmmc3_gpio {
+			nvidia,pins =	"sdmmc3_dat4_pd1",
+					"sdmmc3_dat5_pd0";
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		sdmmc4_rst {
+			nvidia,pins =	"sdmmc4_rst_n_pcc3";
+			nvidia,function = "sdmmc4";
+			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		sdmmc4_clk_pcc4 {
+			nvidia,pins =	"sdmmc4_clk_pcc4";
+			nvidia,function = "sdmmc4";
+			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		sdmmc4_dat0_paa0 {
+			nvidia,pins =	"sdmmc4_cmd_pt7",
+					"sdmmc4_dat0_paa0",
+					"sdmmc4_dat1_paa1",
+					"sdmmc4_dat2_paa2",
+					"sdmmc4_dat3_paa3",
+					"sdmmc4_dat4_paa4",
+					"sdmmc4_dat5_paa5",
+					"sdmmc4_dat6_paa6",
+					"sdmmc4_dat7_paa7";
+			nvidia,function = "sdmmc4";
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		crt {
+			nvidia,pins =	"crt_hsync_pv6",
+					"crt_vsync_pv7";
+			nvidia,function = "crt";
+			nvidia,tristate = <TEGRA_PIN_ENABLE>;
+		};
+		dap {
+			nvidia,pins =	"clk1_req_pee2",
+					"clk2_req_pcc5";
+			nvidia,function = "dap";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		dev3 {
+			nvidia,pins =	"clk3_req_pee1";
+			nvidia,function = "dev3";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		dap1 {
+			nvidia,pins =	"dap1_fs_pn0", "dap1_dout_pn2",
+					"dap1_din_pn1", "dap1_sclk_pn3";
+			nvidia,function = "i2s0";
+			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		dap2_fs_pa2 {
+			nvidia,pins =	"dap2_fs_pa2",
+					"dap2_sclk_pa3",
+					"dap2_din_pa4",
+					"dap2_dout_pa5";
+			nvidia,function = "i2s1";
+			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		dap3 {
+			nvidia,pins =	"dap3_fs_pp0", "dap3_dout_pp2",
+					"dap3_din_pp1", "dap3_sclk_pp3";
+			nvidia,function = "i2s2";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		dap4 {
+			nvidia,pins =	"dap4_fs_pp4", "dap4_dout_pp6",
+					"dap4_din_pp5", "dap4_sclk_pp7";
+			nvidia,function = "i2s3";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		pex_in {
+			nvidia,pins =	"pex_l0_prsnt_n_pdd0",
+					"pex_l0_clkreq_n_pdd2",
+					"pex_l2_prsnt_n_pdd7",
+					"pex_l2_clkreq_n_pcc7",
+					"pex_wake_n_pdd3";
+			nvidia,function = "pcie";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		pex_out {
+			nvidia,pins =	"pex_l0_rst_n_pdd1",
+					"pex_l1_rst_n_pdd5",
+					"pex_l2_rst_n_pcc6";
+			nvidia,function = "pcie";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		pex_l1_prsnt_n_pdd4 {
+			nvidia,pins =	"pex_l1_prsnt_n_pdd4",
+					"pex_l1_clkreq_n_pdd6";
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+		};
+		sdio1 {
+			nvidia,pins = "drive_sdio1";
+			nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+			nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+			nvidia,pull-down-strength = <46>;
+			nvidia,pull-up-strength = <42>;
+			nvidia,slew-rate-rising = <1>;
+			nvidia,slew-rate-falling = <1>;
+		};
+		sdio3 {
+			nvidia,pins = "drive_sdio3";
+			nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+			nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+			nvidia,pull-down-strength = <46>;
+			nvidia,pull-up-strength = <42>;
+			nvidia,slew-rate-rising = <1>;
+			nvidia,slew-rate-falling = <1>;
+		};
+		gpv {
+			nvidia,pins = "drive_gpv";
+			nvidia,pull-up-strength = <16>;
+		};
+		uarta {
+			nvidia,pins =	"ulpi_data0_po1",
+					"ulpi_data1_po2",
+					"ulpi_data2_po3",
+					"ulpi_data3_po4",
+					"ulpi_data4_po5",
+					"ulpi_data5_po6",
+					"ulpi_data6_po7",
+					"ulpi_data7_po0";
+			nvidia,function = "uarta";
+			nvidia,tristate = <0>;
+		};
+		pu {
+			nvidia,pins =	"pu0", "pu1", "pu2", "pu3",
+					"pu4", "pu5", "pu6";
+			nvidia,function = "rsvd4";
+			nvidia,tristate = <TEGRA_PIN_ENABLE>;
+		};
+		uartb {
+			nvidia,pins =	"uart2_txd_pc2",
+					"uart2_rxd_pc3",
+					"uart2_cts_n_pj5",
+					"uart2_rts_n_pj6";
+			nvidia,function = "uartb";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		uartc {
+			nvidia,pins =	"uart3_txd_pw6",
+					"uart3_rxd_pw7",
+					"uart3_cts_n_pa1",
+					"uart3_rts_n_pc0";
+			nvidia,function = "uartc";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		uartd {
+			nvidia,pins =	"ulpi_clk_py0", "ulpi_dir_py1",
+					"ulpi_nxt_py2", "ulpi_stp_py3";
+			nvidia,function = "uartd";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		i2c1 {
+			nvidia,pins =	"gen1_i2c_scl_pc4",
+					"gen1_i2c_sda_pc5";
+			nvidia,function = "i2c1";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+		};
+		i2c2 {
+			nvidia,pins =	"gen2_i2c_scl_pt5",
+					"gen2_i2c_sda_pt6";
+			nvidia,function = "i2c2";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+		};
+		i2c3 {
+			nvidia,pins =	"cam_i2c_scl_pbb1",
+					"cam_i2c_sda_pbb2";
+			nvidia,function = "i2c3";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+		};
+		i2c4 {
+			nvidia,pins =	"ddc_scl_pv4",
+					"ddc_sda_pv5";
+			nvidia,function = "i2c4";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+		};
+		i2cpwr {
+			nvidia,pins =	"pwr_i2c_scl_pz6",
+					"pwr_i2c_sda_pz7";
+			nvidia,function = "i2cpwr";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+		};
+		spi1 {
+			nvidia,pins =	"spi1_mosi_px4",
+					"spi1_sck_px5",
+					"spi1_cs0_n_px6",
+					"spi1_miso_px7";
+			nvidia,function = "spi1";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		spi2_up {
+			nvidia,pins =	"spi2_cs1_n_pw2";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+		};
+		spi4 {
+			nvidia,pins =	"gmi_a16_pj7", "gmi_a17_pb0",
+					"gmi_a18_pb1", "gmi_a19_pk7";
+			nvidia,function = "spi4";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		spdif {
+			nvidia,pins =	"spdif_out_pk5", "spdif_in_pk6";
+			nvidia,function = "spdif";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		hdmi_int {
+			nvidia,pins =	"hdmi_int_pn7";
+			nvidia,function = "hdmi";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		hdmi_cec {
+			nvidia,pins =	"hdmi_cec_pee3";
+			nvidia,function = "cec";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		ddr {
+			nvidia,pins =	"vi_d10_pt2", "vi_vsync_pd6",
+					"vi_hsync_pd7";
+			nvidia,function = "ddr";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+		};
+		ddr_up {
+			nvidia,pins =	"vi_d11_pt3";
+			nvidia,function = "ddr";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		vi {
+			nvidia,pins =	"vi_d4_pl2", "vi_mclk_pt1",
+					"vi_d6_pl4";
+			nvidia,function = "vi";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		owr {
+			nvidia,pins =	"pv2", "pu0", "owr";
+			nvidia,function = "owr";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		lcd {
+			nvidia,pins =	"lcd_pwr1_pc1", "lcd_pwr2_pc6",
+					"lcd_sdin_pz2", "lcd_sdout_pn5",
+					"lcd_wr_n_pz3", "lcd_cs0_n_pn4",
+					"lcd_dc0_pn6", "lcd_sck_pz4",
+					"lcd_pwr0_pb2", "lcd_pclk_pb3",
+					"lcd_de_pj1", "lcd_hsync_pj3",
+					"lcd_vsync_pj4", "lcd_d0_pe0",
+					"lcd_d1_pe1", "lcd_d2_pe2",
+					"lcd_d3_pe3", "lcd_d4_pe4",
+					"lcd_d5_pe5", "lcd_d6_pe6",
+					"lcd_d7_pe7", "lcd_d8_pf0",
+					"lcd_d9_pf1", "lcd_d10_pf2",
+					"lcd_d11_pf3", "lcd_d12_pf4",
+					"lcd_d13_pf5", "lcd_d14_pf6",
+					"lcd_d15_pf7", "lcd_d16_pm0",
+					"lcd_d17_pm1", "lcd_d18_pm2",
+					"lcd_d19_pm3", "lcd_d20_pm4",
+					"lcd_d21_pm5", "lcd_d22_pm6",
+					"lcd_d23_pm7", "lcd_cs1_n_pw0",
+					"lcd_m1_pw1", "lcd_dc1_pd2";
+			nvidia,function = "displaya";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		kbc {
+			nvidia,pins =	"kb_row0_pr0", "kb_row1_pr1",
+					"kb_row2_pr2", "kb_row3_pr3",
+					"kb_row4_pr4", "kb_row5_pr5",
+					"kb_row6_pr6", "kb_row7_pr7",
+					"kb_row9_ps1", "kb_row8_ps0",
+					"kb_row10_ps2", "kb_row11_ps3",
+					"kb_row12_ps4", "kb_row13_ps5",
+					"kb_row14_ps6", "kb_row15_ps7",
+					"kb_col0_pq0", "kb_col1_pq1",
+					"kb_col2_pq2", "kb_col3_pq3",
+					"kb_col4_pq4", "kb_col5_pq5",
+					"kb_col6_pq6", "kb_col7_pq7";
+			nvidia,function = "kbc";
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		gpio_vi {
+			nvidia,pins =	"vi_d1_pd5", "vi_d2_pl0",
+					"vi_d3_pl1", "vi_d5_pl3",
+					"vi_d7_pl5", "vi_d8_pl6",
+					"vi_d9_pl7";
+			nvidia,function = "sdmmc2";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		gpio_pbb0 {
+			nvidia,pins =	"pbb0", "pbb7", "pcc1", "pcc2";
+			nvidia,function = "i2s4";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		gpio_pbb3 {
+			nvidia,pins =	"pbb3";
+			nvidia,function = "vgp3";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		gpio_pbb4 {
+			nvidia,pins =	"pbb4";
+			nvidia,function = "vgp4";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		gpio_pbb5 {
+			nvidia,pins =	"pbb5";
+			nvidia,function = "vgp5";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		gpio_pbb6 {
+			nvidia,pins =	"pbb6";
+			nvidia,function = "vgp6";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+		};
+		gpio_pu1 {
+			nvidia,pins =	"pu1", "pu2";
+			nvidia,function = "rsvd1";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		gpio_pv0 {
+			nvidia,pins =	"pv0", "gmi_cs2_n_pk3";
+			nvidia,function = "rsvd1";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+		};
+		gpio_pv3 {
+			nvidia,pins =	"pv3";
+			nvidia,function = "clk_12m_out";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		gpio_gmi {
+			nvidia,pins =	"spi2_sck_px2", "gmi_wp_n_pc7";
+			nvidia,function = "gmi";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		gpio_gmi_ad {
+			nvidia,pins =	"gmi_ad10_ph2", "gmi_ad14_ph6";
+			nvidia,function = "nand";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		gpio_gmi_ad_up {
+			nvidia,pins =	"gmi_ad12_ph4";
+			nvidia,function = "nand";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+		};
+		gpio_gmi_iordy_up {
+			nvidia,pins =	"gmi_iordy_pi5";
+			nvidia,function = "rsvd1";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+		};
+		pwm0 {
+			nvidia,pins =	"gmi_ad8_ph0", "pu3";
+			nvidia,function = "pwm0";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		pwm1 {
+			nvidia,pins =	"pu4";
+			nvidia,function = "pwm1";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		pwm2 {
+			nvidia,pins =	"pu5";
+			nvidia,function = "pwm2";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		pwm3 {
+			nvidia,pins =	"pu6";
+			nvidia,function = "pwm3";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		extperiph1 {
+			nvidia,pins =	"clk1_out_pw4";
+			nvidia,function = "extperiph1";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		extperiph2 {
+			nvidia,pins =	"clk2_out_pw5";
+			nvidia,function = "extperiph2";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		extperiph3 {
+			nvidia,pins =	"clk3_out_pee0";
+			nvidia,function = "extperiph3";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		jtag {
+			nvidia,pins =	"jtag_rtck_pu7";
+			nvidia,function = "rtck";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		blink {
+			nvidia,pins =	"clk_32k_out_pa0";
+			nvidia,function = "blink";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		sysclk {
+			nvidia,pins =	"sys_clk_req_pz5";
+			nvidia,function = "sysclk";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+		};
+		cam_mclk {
+			nvidia,pins =	"cam_mclk_pcc0";
+			nvidia,function = "vi_alt3";
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+		};
+		vi_pclk {
+			nvidia,pins =	"vi_pclk_pt0";
+			nvidia,function = "rsvd1";
+			nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+		};
+		unused {
+			nvidia,pins =	"gmi_adv_n_pk0", "gmi_clk_pk1",
+					"gmi_cs3_n_pk4", "gmi_ad0_pg0",
+					"gmi_ad1_pg1", "gmi_ad2_pg2",
+					"gmi_ad3_pg3", "gmi_ad4_pg4",
+					"gmi_ad5_pg5", "gmi_ad6_pg6",
+					"gmi_ad7_pg7", "gmi_ad9_ph1",
+					"gmi_ad11_ph3", "gmi_wr_n_pi0",
+					"gmi_oe_n_pi1", "gmi_dqs_pi2";
+			nvidia,function = "nand";
+			nvidia,tristate = <TEGRA_PIN_ENABLE>;
+		};
+		unused_pu {
+			nvidia,pins =	"gmi_wait_pi7", "gmi_cs7_n_pi6",
+					"gmi_ad13_ph5";
+			nvidia,function = "nand";
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			nvidia,tristate = <TEGRA_PIN_ENABLE>;
 		};
 	};
+};
 
-	host1x@50000000 {
-		hdmi@54280000 {
-			status = "okay";
+&uarta {
+	status = "okay";
+};
 
-			vdd-supply = <&sys_3v3_reg>;
-			pll-supply = <&vio_reg>;
+&{/i2c@7000c000} {
+	status = "okay";
+	clock-frequency = <100000>;
+};
 
-			nvidia,hpd-gpio =
-				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
-			nvidia,ddc-i2c-bus = <&hdmiddc>;
-		};
+&{/i2c@7000c400} {
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+&{/i2c@7000c500} {
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+hdmiddc: &{/i2c@7000c700} {
+	status = "okay" ;
+	clock-frequency = <100000>;
+};
+
+&{/i2c@7000d000} {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	rt5640: rt5640@1c {
+		compatible = "realtek,rt5640";
+		reg = <0x1c>;
+		interrupt-parent = <&gpio>;
+		interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+		realtek,ldo1-en-gpios =
+			<&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
 	};
 
-	pinmux@70000868 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&state_default>;
+	pmic: tps65911@2d {
+		compatible = "ti,tps65911";
+		reg = <0x2d>;
 
-		state_default: pinmux {
-			sdmmc1_clk_pz0 {
-				nvidia,pins = "sdmmc1_clk_pz0";
-				nvidia,function = "sdmmc1";
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			sdmmc1_cmd_pz1 {
-				nvidia,pins =	"sdmmc1_cmd_pz1",
-						"sdmmc1_dat0_py7",
-						"sdmmc1_dat1_py6",
-						"sdmmc1_dat2_py5",
-						"sdmmc1_dat3_py4";
-				nvidia,function = "sdmmc1";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			sdmmc3_clk_pa6 {
-				nvidia,pins = "sdmmc3_clk_pa6";
-				nvidia,function = "sdmmc3";
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			sdmmc3_cmd_pa7 {
-				nvidia,pins =	"sdmmc3_cmd_pa7",
-						"sdmmc3_dat0_pb7",
-						"sdmmc3_dat1_pb6",
-						"sdmmc3_dat2_pb5",
-						"sdmmc3_dat3_pb4";
-				nvidia,function = "sdmmc3";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			sdmmc3_gpio {
-				nvidia,pins =	"sdmmc3_dat4_pd1",
-						"sdmmc3_dat5_pd0";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			sdmmc4_rst {
-				nvidia,pins =	"sdmmc4_rst_n_pcc3";
-				nvidia,function = "sdmmc4";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			sdmmc4_clk_pcc4 {
-				nvidia,pins =	"sdmmc4_clk_pcc4";
-				nvidia,function = "sdmmc4";
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			sdmmc4_dat0_paa0 {
-				nvidia,pins =	"sdmmc4_cmd_pt7",
-						"sdmmc4_dat0_paa0",
-						"sdmmc4_dat1_paa1",
-						"sdmmc4_dat2_paa2",
-						"sdmmc4_dat3_paa3",
-						"sdmmc4_dat4_paa4",
-						"sdmmc4_dat5_paa5",
-						"sdmmc4_dat6_paa6",
-						"sdmmc4_dat7_paa7";
-				nvidia,function = "sdmmc4";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			crt {
-				nvidia,pins =	"crt_hsync_pv6",
-						"crt_vsync_pv7";
-				nvidia,function = "crt";
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
-			};
-			dap {
-				nvidia,pins =	"clk1_req_pee2",
-						"clk2_req_pcc5";
-				nvidia,function = "dap";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			dev3 {
-				nvidia,pins =	"clk3_req_pee1";
-				nvidia,function = "dev3";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			dap1 {
-				nvidia,pins =	"dap1_fs_pn0", "dap1_dout_pn2",
-						"dap1_din_pn1", "dap1_sclk_pn3";
-				nvidia,function = "i2s0";
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			dap2_fs_pa2 {
-				nvidia,pins =	"dap2_fs_pa2",
-						"dap2_sclk_pa3",
-						"dap2_din_pa4",
-						"dap2_dout_pa5";
-				nvidia,function = "i2s1";
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			dap3 {
-				nvidia,pins =	"dap3_fs_pp0", "dap3_dout_pp2",
-						"dap3_din_pp1", "dap3_sclk_pp3";
-				nvidia,function = "i2s2";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			dap4 {
-				nvidia,pins =	"dap4_fs_pp4", "dap4_dout_pp6",
-						"dap4_din_pp5", "dap4_sclk_pp7";
-				nvidia,function = "i2s3";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			pex_in {
-				nvidia,pins =	"pex_l0_prsnt_n_pdd0",
-						"pex_l0_clkreq_n_pdd2",
-						"pex_l2_prsnt_n_pdd7",
-						"pex_l2_clkreq_n_pcc7",
-						"pex_wake_n_pdd3";
-				nvidia,function = "pcie";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			pex_out {
-				nvidia,pins =	"pex_l0_rst_n_pdd1",
-						"pex_l1_rst_n_pdd5",
-						"pex_l2_rst_n_pcc6";
-				nvidia,function = "pcie";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			pex_l1_prsnt_n_pdd4 {
-				nvidia,pins =	"pex_l1_prsnt_n_pdd4",
-						"pex_l1_clkreq_n_pdd6";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-			};
-			sdio1 {
-				nvidia,pins = "drive_sdio1";
-				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
-				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-				nvidia,pull-down-strength = <46>;
-				nvidia,pull-up-strength = <42>;
-				nvidia,slew-rate-rising = <1>;
-				nvidia,slew-rate-falling = <1>;
-			};
-			sdio3 {
-				nvidia,pins = "drive_sdio3";
-				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
-				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-				nvidia,pull-down-strength = <46>;
-				nvidia,pull-up-strength = <42>;
-				nvidia,slew-rate-rising = <1>;
-				nvidia,slew-rate-falling = <1>;
-			};
-			gpv {
-				nvidia,pins = "drive_gpv";
-				nvidia,pull-up-strength = <16>;
-			};
-			uarta {
-				nvidia,pins =	"ulpi_data0_po1",
-						"ulpi_data1_po2",
-						"ulpi_data2_po3",
-						"ulpi_data3_po4",
-						"ulpi_data4_po5",
-						"ulpi_data5_po6",
-						"ulpi_data6_po7",
-						"ulpi_data7_po0";
-				nvidia,function = "uarta";
-				nvidia,tristate = <0>;
-			};
-			pu {
-				nvidia,pins =	"pu0", "pu1", "pu2", "pu3",
-						"pu4", "pu5", "pu6";
-				nvidia,function = "rsvd4";
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
-			};
-			uartb {
-				nvidia,pins =	"uart2_txd_pc2",
-						"uart2_rxd_pc3",
-						"uart2_cts_n_pj5",
-						"uart2_rts_n_pj6";
-				nvidia,function = "uartb";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			uartc {
-				nvidia,pins =	"uart3_txd_pw6",
-						"uart3_rxd_pw7",
-						"uart3_cts_n_pa1",
-						"uart3_rts_n_pc0";
-				nvidia,function = "uartc";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			uartd {
-				nvidia,pins =	"ulpi_clk_py0", "ulpi_dir_py1",
-						"ulpi_nxt_py2", "ulpi_stp_py3";
-				nvidia,function = "uartd";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			i2c1 {
-				nvidia,pins =	"gen1_i2c_scl_pc4",
-						"gen1_i2c_sda_pc5";
-				nvidia,function = "i2c1";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-			};
-			i2c2 {
-				nvidia,pins =	"gen2_i2c_scl_pt5",
-						"gen2_i2c_sda_pt6";
-				nvidia,function = "i2c2";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-			};
-			i2c3 {
-				nvidia,pins =	"cam_i2c_scl_pbb1",
-						"cam_i2c_sda_pbb2";
-				nvidia,function = "i2c3";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-			};
-			i2c4 {
-				nvidia,pins =	"ddc_scl_pv4",
-						"ddc_sda_pv5";
-				nvidia,function = "i2c4";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-			};
-			i2cpwr {
-				nvidia,pins =	"pwr_i2c_scl_pz6",
-						"pwr_i2c_sda_pz7";
-				nvidia,function = "i2cpwr";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-			};
-			spi1 {
-				nvidia,pins =	"spi1_mosi_px4",
-						"spi1_sck_px5",
-						"spi1_cs0_n_px6",
-						"spi1_miso_px7";
-				nvidia,function = "spi1";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			spi2_up {
-				nvidia,pins =	"spi2_cs1_n_pw2";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-			};
-			spi4 {
-				nvidia,pins =	"gmi_a16_pj7", "gmi_a17_pb0",
-						"gmi_a18_pb1", "gmi_a19_pk7";
-				nvidia,function = "spi4";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			spdif {
-				nvidia,pins =	"spdif_out_pk5", "spdif_in_pk6";
-				nvidia,function = "spdif";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			hdmi_int {
-				nvidia,pins =	"hdmi_int_pn7";
-				nvidia,function = "hdmi";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			hdmi_cec {
-				nvidia,pins =	"hdmi_cec_pee3";
-				nvidia,function = "cec";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			ddr {
-				nvidia,pins =	"vi_d10_pt2", "vi_vsync_pd6",
-						"vi_hsync_pd7";
-				nvidia,function = "ddr";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
-			};
-			ddr_up {
-				nvidia,pins =	"vi_d11_pt3";
-				nvidia,function = "ddr";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			vi {
-				nvidia,pins =	"vi_d4_pl2", "vi_mclk_pt1",
-						"vi_d6_pl4";
-				nvidia,function = "vi";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			owr {
-				nvidia,pins =	"pv2", "pu0", "owr";
-				nvidia,function = "owr";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			lcd {
-				nvidia,pins =	"lcd_pwr1_pc1", "lcd_pwr2_pc6",
-						"lcd_sdin_pz2", "lcd_sdout_pn5",
-						"lcd_wr_n_pz3", "lcd_cs0_n_pn4",
-						"lcd_dc0_pn6", "lcd_sck_pz4",
-						"lcd_pwr0_pb2", "lcd_pclk_pb3",
-						"lcd_de_pj1", "lcd_hsync_pj3",
-						"lcd_vsync_pj4", "lcd_d0_pe0",
-						"lcd_d1_pe1", "lcd_d2_pe2",
-						"lcd_d3_pe3", "lcd_d4_pe4",
-						"lcd_d5_pe5", "lcd_d6_pe6",
-						"lcd_d7_pe7", "lcd_d8_pf0",
-						"lcd_d9_pf1", "lcd_d10_pf2",
-						"lcd_d11_pf3", "lcd_d12_pf4",
-						"lcd_d13_pf5", "lcd_d14_pf6",
-						"lcd_d15_pf7", "lcd_d16_pm0",
-						"lcd_d17_pm1", "lcd_d18_pm2",
-						"lcd_d19_pm3", "lcd_d20_pm4",
-						"lcd_d21_pm5", "lcd_d22_pm6",
-						"lcd_d23_pm7", "lcd_cs1_n_pw0",
-						"lcd_m1_pw1", "lcd_dc1_pd2";
-				nvidia,function = "displaya";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			kbc {
-				nvidia,pins =	"kb_row0_pr0", "kb_row1_pr1",
-						"kb_row2_pr2", "kb_row3_pr3",
-						"kb_row4_pr4", "kb_row5_pr5",
-						"kb_row6_pr6", "kb_row7_pr7",
-						"kb_row9_ps1", "kb_row8_ps0",
-						"kb_row10_ps2", "kb_row11_ps3",
-						"kb_row12_ps4", "kb_row13_ps5",
-						"kb_row14_ps6", "kb_row15_ps7",
-						"kb_col0_pq0", "kb_col1_pq1",
-						"kb_col2_pq2", "kb_col3_pq3",
-						"kb_col4_pq4", "kb_col5_pq5",
-						"kb_col6_pq6", "kb_col7_pq7";
-				nvidia,function = "kbc";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			gpio_vi {
-				nvidia,pins =	"vi_d1_pd5", "vi_d2_pl0",
-						"vi_d3_pl1", "vi_d5_pl3",
-						"vi_d7_pl5", "vi_d8_pl6",
-						"vi_d9_pl7";
-				nvidia,function = "sdmmc2";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			gpio_pbb0 {
-				nvidia,pins =	"pbb0", "pbb7", "pcc1", "pcc2";
-				nvidia,function = "i2s4";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			gpio_pbb3 {
-				nvidia,pins =	"pbb3";
-				nvidia,function = "vgp3";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			gpio_pbb4 {
-				nvidia,pins =	"pbb4";
-				nvidia,function = "vgp4";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			gpio_pbb5 {
-				nvidia,pins =	"pbb5";
-				nvidia,function = "vgp5";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			gpio_pbb6 {
-				nvidia,pins =	"pbb6";
-				nvidia,function = "vgp6";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-			gpio_pu1 {
-				nvidia,pins =	"pu1", "pu2";
-				nvidia,function = "rsvd1";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			gpio_pv0 {
-				nvidia,pins =	"pv0", "gmi_cs2_n_pk3";
-				nvidia,function = "rsvd1";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-			};
-			gpio_pv3 {
-				nvidia,pins =	"pv3";
-				nvidia,function = "clk_12m_out";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			gpio_gmi {
-				nvidia,pins =	"spi2_sck_px2", "gmi_wp_n_pc7";
-				nvidia,function = "gmi";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			gpio_gmi_ad {
-				nvidia,pins =	"gmi_ad10_ph2", "gmi_ad14_ph6";
-				nvidia,function = "nand";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			gpio_gmi_ad_up {
-				nvidia,pins =	"gmi_ad12_ph4";
-				nvidia,function = "nand";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-			};
-			gpio_gmi_iordy_up {
-				nvidia,pins =	"gmi_iordy_pi5";
-				nvidia,function = "rsvd1";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-			};
-			pwm0 {
-				nvidia,pins =	"gmi_ad8_ph0", "pu3";
-				nvidia,function = "pwm0";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			pwm1 {
-				nvidia,pins =	"pu4";
-				nvidia,function = "pwm1";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			pwm2 {
-				nvidia,pins =	"pu5";
-				nvidia,function = "pwm2";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			pwm3 {
-				nvidia,pins =	"pu6";
-				nvidia,function = "pwm3";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			extperiph1 {
-				nvidia,pins =	"clk1_out_pw4";
-				nvidia,function = "extperiph1";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			extperiph2 {
-				nvidia,pins =	"clk2_out_pw5";
-				nvidia,function = "extperiph2";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			extperiph3 {
-				nvidia,pins =	"clk3_out_pee0";
-				nvidia,function = "extperiph3";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			jtag {
-				nvidia,pins =	"jtag_rtck_pu7";
-				nvidia,function = "rtck";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			blink {
-				nvidia,pins =	"clk_32k_out_pa0";
-				nvidia,function = "blink";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			sysclk {
-				nvidia,pins =	"sys_clk_req_pz5";
-				nvidia,function = "sysclk";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-			};
-			cam_mclk {
-				nvidia,pins =	"cam_mclk_pcc0";
-				nvidia,function = "vi_alt3";
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+
+		ti,system-power-controller;
+
+		#gpio-cells = <2>;
+		gpio-controller;
+
+		vcc1-supply = <&vdd_5v_in_reg>;
+		vcc2-supply = <&vdd_5v_in_reg>;
+		vcc3-supply = <&vio_reg>;
+		vcc4-supply = <&vdd_5v_in_reg>;
+		vcc5-supply = <&vdd_5v_in_reg>;
+		vcc6-supply = <&vdd2_reg>;
+		vcc7-supply = <&vdd_5v_in_reg>;
+		vccio-supply = <&vdd_5v_in_reg>;
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vdd1_reg: vdd1 {
+				regulator-name = "vddio_ddr_1v2";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
 			};
-			vi_pclk {
-				nvidia,pins =	"vi_pclk_pt0";
-				nvidia,function = "rsvd1";
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
-				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+
+			vdd2_reg: vdd2 {
+				regulator-name = "vdd_1v5_gen";
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
 			};
-			unused {
-				nvidia,pins =	"gmi_adv_n_pk0", "gmi_clk_pk1",
-						"gmi_cs3_n_pk4", "gmi_ad0_pg0",
-						"gmi_ad1_pg1", "gmi_ad2_pg2",
-						"gmi_ad3_pg3", "gmi_ad4_pg4",
-						"gmi_ad5_pg5", "gmi_ad6_pg6",
-						"gmi_ad7_pg7", "gmi_ad9_ph1",
-						"gmi_ad11_ph3", "gmi_wr_n_pi0",
-						"gmi_oe_n_pi1", "gmi_dqs_pi2";
-				nvidia,function = "nand";
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+
+			vddctrl_reg: vddctrl {
+				regulator-name = "vdd_cpu,vdd_sys";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
 			};
-			unused_pu {
-				nvidia,pins =	"gmi_wait_pi7", "gmi_cs7_n_pi6",
-						"gmi_ad13_ph5";
-				nvidia,function = "nand";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+
+			vio_reg: vio {
+				regulator-name = "vdd_1v8_gen";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
 			};
-		};
-	};
 
-	serial@70006000 {
-		status = "okay";
-	};
+			ldo1_reg: ldo1 {
+				regulator-name = "vdd_pexa,vdd_pexb";
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+			};
 
-	i2c@7000c000 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
+			ldo2_reg: ldo2 {
+				regulator-name = "vdd_sata,avdd_plle";
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+			};
 
-	i2c@7000c400 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
+			/* LDO3 is not connected to anything */
 
-	i2c@7000c500 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
+			ldo4_reg: ldo4 {
+				regulator-name = "vdd_rtc";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
 
-	hdmiddc: i2c@7000c700 {
-		status = "okay";
-		clock-frequency = <100000>;
-	};
+			ldo5_reg: ldo5 {
+				regulator-name = "vddio_sdmmc,avdd_vdac";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
 
-	i2c@7000d000 {
-		status = "okay";
-		clock-frequency = <100000>;
-
-		rt5640: rt5640@1c {
-			compatible = "realtek,rt5640";
-			reg = <0x1c>;
-			interrupt-parent = <&gpio>;
-			interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
-			realtek,ldo1-en-gpios =
-				<&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
-		};
-
-		pmic: tps65911@2d {
-			compatible = "ti,tps65911";
-			reg = <0x2d>;
-
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			#interrupt-cells = <2>;
-			interrupt-controller;
-
-			ti,system-power-controller;
-
-			#gpio-cells = <2>;
-			gpio-controller;
-
-			vcc1-supply = <&vdd_5v_in_reg>;
-			vcc2-supply = <&vdd_5v_in_reg>;
-			vcc3-supply = <&vio_reg>;
-			vcc4-supply = <&vdd_5v_in_reg>;
-			vcc5-supply = <&vdd_5v_in_reg>;
-			vcc6-supply = <&vdd2_reg>;
-			vcc7-supply = <&vdd_5v_in_reg>;
-			vccio-supply = <&vdd_5v_in_reg>;
-
-			regulators {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				vdd1_reg: vdd1 {
-					regulator-name = "vddio_ddr_1v2";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-always-on;
-				};
-
-				vdd2_reg: vdd2 {
-					regulator-name = "vdd_1v5_gen";
-					regulator-min-microvolt = <1500000>;
-					regulator-max-microvolt = <1500000>;
-					regulator-always-on;
-				};
-
-				vddctrl_reg: vddctrl {
-					regulator-name = "vdd_cpu,vdd_sys";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-					regulator-always-on;
-				};
-
-				vio_reg: vio {
-					regulator-name = "vdd_1v8_gen";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-				};
-
-				ldo1_reg: ldo1 {
-					regulator-name = "vdd_pexa,vdd_pexb";
-					regulator-min-microvolt = <1050000>;
-					regulator-max-microvolt = <1050000>;
-				};
-
-				ldo2_reg: ldo2 {
-					regulator-name = "vdd_sata,avdd_plle";
-					regulator-min-microvolt = <1050000>;
-					regulator-max-microvolt = <1050000>;
-				};
-
-				/* LDO3 is not connected to anything */
-
-				ldo4_reg: ldo4 {
-					regulator-name = "vdd_rtc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-always-on;
-				};
-
-				ldo5_reg: ldo5 {
-					regulator-name = "vddio_sdmmc,avdd_vdac";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-always-on;
-				};
-
-				ldo6_reg: ldo6 {
-					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-				};
-
-				ldo7_reg: ldo7 {
-					regulator-name = "vdd_pllm,x,u,a_p_c_s";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-always-on;
-				};
-
-				ldo8_reg: ldo8 {
-					regulator-name = "vdd_ddr_hs";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-					regulator-always-on;
-				};
+			ldo6_reg: ldo6 {
+				regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
 			};
-		};
 
-		tps62361@60 {
-			compatible = "ti,tps62361";
-			reg = <0x60>;
+			ldo7_reg: ldo7 {
+				regulator-name = "vdd_pllm,x,u,a_p_c_s";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
 
-			regulator-name = "tps62361-vout";
-			regulator-min-microvolt = <500000>;
-			regulator-max-microvolt = <1500000>;
-			regulator-boot-on;
-			regulator-always-on;
-			ti,vsel0-state-high;
-			ti,vsel1-state-high;
+			ldo8_reg: ldo8 {
+				regulator-name = "vdd_ddr_hs";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
 		};
 	};
 
-	spi@7000da00 {
-		status = "okay";
-		spi-max-frequency = <25000000>;
-		spi-flash@1 {
-			compatible = "winbond,w25q32";
-			reg = <1>;
-			spi-max-frequency = <20000000>;
-		};
+	tps62361@60 {
+		compatible = "ti,tps62361";
+		reg = <0x60>;
+
+		regulator-name = "tps62361-vout";
+		regulator-min-microvolt = <500000>;
+		regulator-max-microvolt = <1500000>;
+		regulator-boot-on;
+		regulator-always-on;
+		ti,vsel0-state-high;
+		ti,vsel1-state-high;
 	};
+};
 
-	pmc@7000e400 {
-		status = "okay";
-		nvidia,invert-interrupt;
-		nvidia,suspend-mode = <1>;
-		nvidia,cpu-pwr-good-time = <2000>;
-		nvidia,cpu-pwr-off-time = <200>;
-		nvidia,core-pwr-good-time = <3845 3845>;
-		nvidia,core-pwr-off-time = <0>;
-		nvidia,core-power-req-active-high;
-		nvidia,sys-clock-req-active-high;
+&{/spi@7000da00} {
+	status = "okay";
+	spi-max-frequency = <25000000>;
+	spi-flash@1 {
+		compatible = "winbond,w25q32";
+		reg = <1>;
+		spi-max-frequency = <20000000>;
 	};
+};
 
-	ahub@70080000 {
-		i2s@70080400 {
-			status = "okay";
-		};
-	};
+&tegra_pmc {
+	status = "okay";
+	nvidia,invert-interrupt;
+	nvidia,suspend-mode = <1>;
+	nvidia,cpu-pwr-good-time = <2000>;
+	nvidia,cpu-pwr-off-time = <200>;
+	nvidia,core-pwr-good-time = <3845 3845>;
+	nvidia,core-pwr-off-time = <0>;
+	nvidia,core-power-req-active-high;
+	nvidia,sys-clock-req-active-high;
+};
 
-	sdhci@78000000 {
-		status = "okay";
-		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
-		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
-		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
-		bus-width = <4>;
-	};
+&tegra_i2s1 {
+	status = "okay";
+};
 
-	emmc: sdhci@78000600 {
-		status = "okay";
-		bus-width = <8>;
-		non-removable;
-	};
+&{/mmc@78000000} {
+	status = "okay";
+	cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+	power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
+	bus-width = <4>;
+};
 
-	usb@7d004000 {
-		status = "okay";
-	};
+emmc: &{/mmc@78000600} {
+	status = "okay";
+	bus-width = <8>;
+	non-removable;
+};
 
-	phy2: usb-phy@7d004000 {
-		vbus-supply = <&sys_3v3_reg>;
-		status = "okay";
-	};
+&{/usb@7d004000} {
+	status = "okay";
+};
 
-	usb@7d008000 {
-		status = "okay";
-	};
+&phy2 {
+	vbus-supply = <&sys_3v3_reg>;
+	status = "okay";
+};
 
-	usb-phy@7d008000 {
-		vbus-supply = <&usb3_vbus_reg>;
-		status = "okay";
-	};
+&{/usb@7d008000} {
+	status = "okay";
+};
 
+&phy3 {
+	vbus-supply = <&usb3_vbus_reg>;
+	status = "okay";
+};
+
+/ {
 	clocks {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index 90bd08ba63..2724714f60 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -1,8 +1,8 @@
 / {
 	aliases {
-		mmc0 = "/sdhci@78000000/";
-		mmc1 = "/sdhci@78000200/";
-		mmc2 = "/sdhci@78000400/";
-		mmc3 = "/sdhci@78000600/";
+		mmc0 = &{/mmc@78000000};
+		mmc1 = &{/mmc@78000200};
+		mmc2 = &{/mmc@78000400};
+		mmc3 = &{/mmc@78000600};
 	};
 };
diff --git a/arch/arm/dts/tny_a9260.dts b/arch/arm/dts/tny_a9260.dts
new file mode 100644
index 0000000000..2c4df66f7a
--- /dev/null
+++ b/arch/arm/dts/tny_a9260.dts
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arm/microchip/tny_a9260.dts>
+#include "at91sam9260.dtsi"
+#include "calao_nand.dtsi"
diff --git a/arch/arm/dts/tny_a9g20.dts b/arch/arm/dts/tny_a9g20.dts
new file mode 100644
index 0000000000..654a988c44
--- /dev/null
+++ b/arch/arm/dts/tny_a9g20.dts
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arm/microchip/tny_a9g20.dts>
+#include "at91sam9g20.dtsi"
+#include "calao_nand.dtsi"
diff --git a/arch/arm/dts/usb_a9260.dts b/arch/arm/dts/usb_a9260.dts
new file mode 100644
index 0000000000..9eb2db3ff8
--- /dev/null
+++ b/arch/arm/dts/usb_a9260.dts
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arm/microchip/usb_a9260.dts>
+#include "at91sam9260.dtsi"
+#include "calao_nand.dtsi"
diff --git a/arch/arm/dts/usb_a9g20.dts b/arch/arm/dts/usb_a9g20.dts
new file mode 100644
index 0000000000..a8ed22b7c4
--- /dev/null
+++ b/arch/arm/dts/usb_a9g20.dts
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arm/microchip/usb_a9g20.dts>
+#include "at91sam9g20.dtsi"
+#include "calao_nand.dtsi"
diff --git a/arch/arm/dts/versatile-pb.dts b/arch/arm/dts/versatile-pb.dts
index d374f54291..d81b7d2715 100644
--- a/arch/arm/dts/versatile-pb.dts
+++ b/arch/arm/dts/versatile-pb.dts
@@ -1,10 +1,36 @@
-#include <arm/versatile-ab.dts>
+#include <arm/arm/versatile-ab.dts>
 
 / {
 	model = "ARM Versatile PB";
 	compatible = "arm,versatile-pb";
+
+	chosen {
+		environment-nor {
+			compatible = "barebox,environment";
+			device-path = &env_nor;
+		};
+	};
 };
 
 &{/memory} {
 	reg = <0x0 0x04000000>;
 };
+
+&{/flash@34000000} {
+	partitions {
+		compatible = "fixed-partitions";
+
+		#address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+			label = "barebox";
+			reg = <0x0 0x400000>;
+		};
+
+                env_nor: partition@400000 {
+			label = "bareboxenv";
+			reg = <0x400000 0x400000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/vexpress-v2p-ca15.dts b/arch/arm/dts/vexpress-v2p-ca15.dts
index 78d0025909..acf4e023d5 100644
--- a/arch/arm/dts/vexpress-v2p-ca15.dts
+++ b/arch/arm/dts/vexpress-v2p-ca15.dts
@@ -1,4 +1,4 @@
-#include <arm/vexpress-v2p-ca15_a7.dts>
+#include <arm/arm/vexpress-v2p-ca15_a7.dts>
 
 / {
 	barebox_environment {
@@ -28,3 +28,11 @@
 		};
 	};
 };
+
+&{/leds} {
+	status = "disabled";
+};
+
+&{/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/compact-flash@1a0000/} {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/vexpress-v2p-ca9.dts b/arch/arm/dts/vexpress-v2p-ca9.dts
index 8be04b174b..d1484ff4b0 100644
--- a/arch/arm/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/dts/vexpress-v2p-ca9.dts
@@ -1,4 +1,4 @@
-#include <arm/vexpress-v2p-ca9.dts>
+#include <arm/arm/vexpress-v2p-ca9.dts>
 
 / {
 	barebox_environment {
@@ -69,7 +69,7 @@
 	};
 };
 
-&{/bus@4000000/motherboard/flash@0,00000000} {
+&{/bus@40000000/motherboard-bus@40000000/flash@0,00000000} {
 	partitions {
 		compatible = "fixed-partitions";
 		#address-cells = <1>;
@@ -91,3 +91,15 @@
 		};
 	};
 };
+
+&{/timer@1e000600} {
+	status = "disabled";
+};
+
+&{/bus@40000000/motherboard-bus@40000000/leds/} {
+	status = "disabled";
+};
+
+&{/bus@40000000/motherboard-bus@40000000/iofpga@7,00000000/compact-flash@1a000/} {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/vf610-ddrmc.dtsi b/arch/arm/dts/vf610-ddrmc.dtsi
index 772131ec28..44d933b3e9 100644
--- a/arch/arm/dts/vf610-ddrmc.dtsi
+++ b/arch/arm/dts/vf610-ddrmc.dtsi
@@ -1,10 +1,12 @@
 /*
  * Include file to switch board DTS form using hardcoded memory node
- * to dynamic memory size detection based on DDR controller settings
+ * (if specified) to dynamic memory size detection based on DDR
+ * controller settings
  */
 
 / {
 	/delete-node/ memory;
+	/delete-node/ memory@80000000;
 };
 
 &aips1 {
diff --git a/arch/arm/dts/vf610-twr.dts b/arch/arm/dts/vf610-twr.dts
index ac2774979e..14d9e74274 100644
--- a/arch/arm/dts/vf610-twr.dts
+++ b/arch/arm/dts/vf610-twr.dts
@@ -7,7 +7,7 @@
  * (at your option) any later version.
  */
 
-#include <arm/vf610-twr.dts>
+#include <arm/nxp/vf/vf610-twr.dts>
 #include "vf610.dtsi"
 #include "vf610-ddrmc.dtsi"
 
diff --git a/arch/arm/dts/vf610-zii-cfu1.dts b/arch/arm/dts/vf610-zii-cfu1.dts
index 9226930612..fd06147c8e 100644
--- a/arch/arm/dts/vf610-zii-cfu1.dts
+++ b/arch/arm/dts/vf610-zii-cfu1.dts
@@ -4,7 +4,7 @@
  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
  */
 
-#include <arm/vf610-zii-cfu1.dts>
+#include <arm/nxp/vf/vf610-zii-cfu1.dts>
 
 #include "vf610-zii-dev.dtsi"
 
@@ -18,12 +18,6 @@
 		switch-eeprom = &switch0;
 		fiber-eeprom0 = &fiber_eeprom0;
 	};
-
-	gpio-leds {
-		led-status {
-			linux,default-trigger = "heartbeat";
-		};
-	};
 };
 
 &{/gpio-leds/led-status} {
diff --git a/arch/arm/dts/vf610-zii-dev-rev-b.dts b/arch/arm/dts/vf610-zii-dev-rev-b.dts
index 2949042bc3..ec71b1e43a 100644
--- a/arch/arm/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/dts/vf610-zii-dev-rev-b.dts
@@ -4,11 +4,11 @@
  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
  */
 
-#include <arm/vf610-zii-dev-rev-b.dts>
+#include <arm/nxp/vf/vf610-zii-dev-rev-b.dts>
 
 #include "vf610-zii-dev.dtsi"
 
-&{/spi0/flash@0} {
+&{/spi-0/flash@0} {
 	#address-cells = <1>;
 	#size-cells = <0>;
 
diff --git a/arch/arm/dts/vf610-zii-dev-rev-c.dts b/arch/arm/dts/vf610-zii-dev-rev-c.dts
index c1b3bc86dc..d61b291509 100644
--- a/arch/arm/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/dts/vf610-zii-dev-rev-c.dts
@@ -4,7 +4,7 @@
  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
  */
 
-#include <arm/vf610-zii-dev-rev-c.dts>
+#include <arm/nxp/vf/vf610-zii-dev-rev-c.dts>
 
 #include "vf610-zii-dev.dtsi"
 
diff --git a/arch/arm/dts/vf610-zii-scu4-aib.dts b/arch/arm/dts/vf610-zii-scu4-aib.dts
index 43a13e243d..a6f585ae37 100644
--- a/arch/arm/dts/vf610-zii-scu4-aib.dts
+++ b/arch/arm/dts/vf610-zii-scu4-aib.dts
@@ -2,7 +2,7 @@
 //
 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
 
-#include <arm/vf610-zii-scu4-aib.dts>
+#include <arm/nxp/vf/vf610-zii-scu4-aib.dts>
 
 #include "vf610-zii-dev.dtsi"
 
diff --git a/arch/arm/dts/vf610-zii-spb4.dtsi b/arch/arm/dts/vf610-zii-spb4.dtsi
index f618ca45ee..b8e80be0e9 100644
--- a/arch/arm/dts/vf610-zii-spb4.dtsi
+++ b/arch/arm/dts/vf610-zii-spb4.dtsi
@@ -14,7 +14,7 @@
  */
 
 /dts-v1/;
-#include <arm/vf610.dtsi>
+#include <arm/nxp/vf/vf610.dtsi>
 
 / {
 	model = "ZII VF610 SPB4 Board";
diff --git a/arch/arm/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/dts/vf610-zii-ssmb-dtu.dts
index 6ffb7aa62d..7952b09e84 100644
--- a/arch/arm/dts/vf610-zii-ssmb-dtu.dts
+++ b/arch/arm/dts/vf610-zii-ssmb-dtu.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 
-#include <arm/vf610-zii-ssmb-dtu.dts>
+#include <arm/nxp/vf/vf610-zii-ssmb-dtu.dts>
 
 #include "vf610-zii-dev.dtsi"
 
diff --git a/arch/arm/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/dts/vf610-zii-ssmb-spu3.dts
index 5b2460cafa..d6c436b204 100644
--- a/arch/arm/dts/vf610-zii-ssmb-spu3.dts
+++ b/arch/arm/dts/vf610-zii-ssmb-spu3.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 
-#include <arm/vf610-zii-ssmb-spu3.dts>
+#include <arm/nxp/vf/vf610-zii-ssmb-spu3.dts>
 
 #include "vf610-zii-dev.dtsi"
 
diff --git a/arch/arm/dts/vf610.dtsi b/arch/arm/dts/vf610.dtsi
index 3060031b8a..d1297e952c 100644
--- a/arch/arm/dts/vf610.dtsi
+++ b/arch/arm/dts/vf610.dtsi
@@ -9,4 +9,4 @@
 		mmc0 = &esdhc0;
 		mmc1 = &esdhc1;
 	};
-};	
+};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 3791f743a4..f7a0d70bab 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -8,7 +8,7 @@
 		clocks = <&clkc 10>, <&clkc 43>;
 		clock-names = "ref_clk", "pclk";
 		status = "disabled";
-		
+
 		#address-cells = <1>;
 		#size-cells = <0>;
 	};
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index a6b1da854b..465758ebf6 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -1,4 +1,4 @@
-#include <arm/zynq-zed.dts>
+#include <arm/xilinx/zynq-zed.dts>
 #include "zynq-7000.dtsi"
 
 / {
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
new file mode 100644
index 0000000000..8f5410d5e6
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <arm64/xilinx/zynqmp-zcu102-revA.dts>
+
+/ {
+	chosen {
+		environment {
+			compatible = "barebox,environment";
+			device-path = &sdhci1, "partname:0";
+			file-path = "barebox.env";
+		};
+	};
+};
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
new file mode 100644
index 0000000000..3f772f465a
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <arm64/xilinx/zynqmp-zcu102-revB.dts>
+
+/ {
+	chosen {
+		environment {
+			compatible = "barebox,environment";
+			device-path = &sdhci1, "partname:0";
+			file-path = "barebox.env";
+		};
+	};
+};
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 8c467ee970..95b60a6b1d 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -8,3 +8,13 @@
  */
 
 #include <arm64/xilinx/zynqmp-zcu104-revA.dts>
+
+/ {
+	chosen {
+		environment {
+			compatible = "barebox,environment";
+			device-path = &sdhci1, "partname:0";
+			file-path = "barebox.env";
+		};
+	};
+};
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
new file mode 100644
index 0000000000..7c50588268
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU106
+ *
+ * Copyright (C) 2021, WolfVision GmbH
+ * Author: Michael Riesch <michael.riesch@wolfvision.net>
+ *
+ * Based on the dts for the Xilinx ZynqMP ZCU104.
+ */
+
+#include <arm64/xilinx/zynqmp-zcu106-revA.dts>
+
+/ {
+	chosen {
+		environment {
+			compatible = "barebox,environment";
+			device-path = &sdhci1, "partname:0";
+			file-path = "barebox.env";
+		};
+	};
+};
diff --git a/arch/arm/include/asm/arch-check.h b/arch/arm/include/asm/arch-check.h
new file mode 100644
index 0000000000..2cf1b624a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-check.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ARM_ASM_ARCH_CHECK_H__
+#define __ARM_ASM_ARCH_CHECK_H__
+
+#ifndef __LINUX_ARM_ARCH__
+#error No boards/CPUs selected in Kconfig
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/armlinux.h b/arch/arm/include/asm/armlinux.h
index 6af98968fa..8d8e05105b 100644
--- a/arch/arm/include/asm/armlinux.h
+++ b/arch/arm/include/asm/armlinux.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ARCH_ARMLINUX_H
 #define __ARCH_ARMLINUX_H
 
diff --git a/arch/arm/include/asm/asm-offsets.h b/arch/arm/include/asm/asm-offsets.h
index 2f84e83996..33db5a47e5 100644
--- a/arch/arm/include/asm/asm-offsets.h
+++ b/arch/arm/include/asm/asm-offsets.h
@@ -1 +1,3 @@
-#include <generated/asm-offsets.h>
\ No newline at end of file
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <generated/asm-offsets.h>
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 95c6768de8..5db0f692ee 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -111,3 +111,233 @@
 	.align	3;				\
 	.long	9999b,9001f;			\
 	.previous
+
+
+/*
+ * Select code when configured for BE.
+ */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define CPU_BE(code...) code
+#else
+#define CPU_BE(code...)
+#endif
+
+/*
+ * Select code when configured for LE.
+ */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define CPU_LE(code...)
+#else
+#define CPU_LE(code...) code
+#endif
+
+#ifdef CONFIG_CPU_64
+/*
+ * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
+ * <symbol> is within the range +/- 4 GB of the PC.
+ */
+	/*
+	 * @dst: destination register (64 bit wide)
+	 * @sym: name of the symbol
+	 */
+	.macro	adr_l, dst, sym
+	adrp	\dst, \sym
+	add	\dst, \dst, :lo12:\sym
+	.endm
+
+	/*
+	 * @dst: destination register (32 or 64 bit wide)
+	 * @sym: name of the symbol
+	 * @tmp: optional 64-bit scratch register to be used if <dst> is a
+	 *       32-bit wide register, in which case it cannot be used to hold
+	 *       the address
+	 */
+	.macro	ldr_l, dst, sym, tmp=
+	.ifb	\tmp
+	adrp	\dst, \sym
+	ldr	\dst, [\dst, :lo12:\sym]
+	.else
+	adrp	\tmp, \sym
+	ldr	\dst, [\tmp, :lo12:\sym]
+	.endif
+	.endm
+
+	/*
+	 * @src: source register (32 or 64 bit wide)
+	 * @sym: name of the symbol
+	 * @tmp: mandatory 64-bit scratch register to calculate the address
+	 *       while <src> needs to be preserved.
+	 */
+	.macro	str_l, src, sym, tmp
+	adrp	\tmp, \sym
+	str	\src, [\tmp, :lo12:\sym]
+	.endm
+
+#else
+
+	.macro		__adldst_l, op, reg, sym, tmp, c
+	.if		__LINUX_ARM_ARCH__ < 7
+	ldr\c		\tmp, .La\@
+	.subsection	1
+	.align		2
+.La\@:	.long		\sym - .Lpc\@
+	.previous
+	.else
+	.ifnb		\c
+ THUMB(	ittt		\c			)
+	.endif
+	movw\c		\tmp, #:lower16:\sym - .Lpc\@
+	movt\c		\tmp, #:upper16:\sym - .Lpc\@
+	.endif
+
+#ifndef CONFIG_THUMB2_BAREBOX
+	.set		.Lpc\@, . + 8			// PC bias
+	.ifc		\op, add
+	add\c		\reg, \tmp, pc
+	.else
+	\op\c		\reg, [pc, \tmp]
+	.endif
+#else
+.Lb\@:	add\c		\tmp, \tmp, pc
+	/*
+	 * In Thumb-2 builds, the PC bias depends on whether we are currently
+	 * emitting into a .arm or a .thumb section. The size of the add opcode
+	 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when
+	 * emitting in ARM mode, so let's use this to account for the bias.
+	 */
+	.set		.Lpc\@, . + (. - .Lb\@)
+
+	.ifnc		\op, add
+	\op\c		\reg, [\tmp]
+	.endif
+#endif
+	.endm
+
+	/*
+	 * mov_l - move a constant value or [relocated] address into a register
+	 */
+	.macro		mov_l, dst:req, imm:req, cond
+	.if		__LINUX_ARM_ARCH__ < 7
+	ldr\cond	\dst, =\imm
+	.else
+	movw\cond	\dst, #:lower16:\imm
+	movt\cond	\dst, #:upper16:\imm
+	.endif
+	.endm
+
+	/*
+	 * adr_l - adr pseudo-op with unlimited range
+	 *
+	 * @dst: destination register
+	 * @sym: name of the symbol
+	 * @cond: conditional opcode suffix
+	 */
+	.macro		adr_l, dst:req, sym:req, cond
+	__adldst_l	add, \dst, \sym, \dst, \cond
+	.endm
+
+	/*
+	 * ldr_l - ldr <literal> pseudo-op with unlimited range
+	 *
+	 * @dst: destination register
+	 * @sym: name of the symbol
+	 * @cond: conditional opcode suffix
+	 */
+	.macro		ldr_l, dst:req, sym:req, cond
+	__adldst_l	ldr, \dst, \sym, \dst, \cond
+	.endm
+
+	/*
+	 * str_l - str <literal> pseudo-op with unlimited range
+	 *
+	 * @src: source register
+	 * @sym: name of the symbol
+	 * @tmp: mandatory scratch register
+	 * @cond: conditional opcode suffix
+	 */
+	.macro		str_l, src:req, sym:req, tmp:req, cond
+	__adldst_l	str, \src, \sym, \tmp, \cond
+	.endm
+
+	.macro		__ldst_va, op, reg, tmp, sym, cond, offset
+#if __LINUX_ARM_ARCH__ >= 7 || \
+    (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
+	mov_l		\tmp, \sym, \cond
+#else
+	/*
+	 * Avoid a literal load, by emitting a sequence of ADD/LDR instructions
+	 * with the appropriate relocations. The combined sequence has a range
+	 * of -/+ 256 MiB, which should be sufficient for the core kernel and
+	 * for modules loaded into the module region.
+	 */
+	.globl		\sym
+	.reloc		.L0_\@, R_ARM_ALU_PC_G0_NC, \sym
+	.reloc		.L1_\@, R_ARM_ALU_PC_G1_NC, \sym
+	.reloc		.L2_\@, R_ARM_LDR_PC_G2, \sym
+.L0_\@: sub\cond	\tmp, pc, #8 - \offset
+.L1_\@: sub\cond	\tmp, \tmp, #4 - \offset
+.L2_\@:
+#endif
+	\op\cond	\reg, [\tmp, #\offset]
+	.endm
+
+	/*
+	 * ldr_va - load a 32-bit word from the virtual address of \sym
+	 */
+	.macro		ldr_va, rd:req, sym:req, cond, tmp, offset=0
+	.ifnb		\tmp
+	__ldst_va	ldr, \rd, \tmp, \sym, \cond, \offset
+	.else
+	__ldst_va	ldr, \rd, \rd, \sym, \cond, \offset
+	.endif
+	.endm
+
+	/*
+	 * str_va - store a 32-bit word to the virtual address of \sym
+	 */
+	.macro		str_va, rn:req, sym:req, tmp:req, cond
+	__ldst_va	str, \rn, \tmp, \sym, \cond, 0
+	.endm
+
+	/*
+	 * ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym'
+	 *		  into register 'rd', which may be the stack pointer,
+	 *		  using 't1' and 't2' as general temp registers. These
+	 *		  are permitted to overlap with 'rd' if != sp
+	 */
+	.macro		ldr_this_cpu, rd:req, sym:req, t1:req, t2:req
+	ldr_va		\rd, \sym, tmp=\t1
+	.endm
+
+	/*
+	 * rev_l - byte-swap a 32-bit value
+	 *
+	 * @val: source/destination register
+	 * @tmp: scratch register
+	 */
+	.macro		rev_l, val:req, tmp:req
+	.if		__LINUX_ARM_ARCH__ < 6
+	eor		\tmp, \val, \val, ror #16
+	bic		\tmp, \tmp, #0x00ff0000
+	mov		\val, \val, ror #8
+	eor		\val, \val, \tmp, lsr #8
+	.else
+	rev		\val, \val
+	.endif
+	.endm
+
+	/*
+	 * bl_r - branch and link to register
+	 *
+	 * @dst: target to branch to
+	 * @c: conditional opcode suffix
+	 */
+	.macro		bl_r, dst:req, c
+	.if		__LINUX_ARM_ARCH__ < 6
+	mov\c		lr, pc
+	mov\c		pc, \dst
+	.else
+	blx\c		\dst
+	.endif
+	.endm
+#endif
diff --git a/arch/arm/include/asm/assembler64.h b/arch/arm/include/asm/assembler64.h
index 26182aa5f6..615b257671 100644
--- a/arch/arm/include/asm/assembler64.h
+++ b/arch/arm/include/asm/assembler64.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARCH_ASSEMBLY_H
 #define __ASM_ARCH_ASSEMBLY_H
 
@@ -18,4 +20,4 @@
 	b.eq	\el1_label
 .endm
 
-#endif /* __ASM_ARCH_ASSEMBLY_H */
\ No newline at end of file
+#endif /* __ASM_ARCH_ASSEMBLY_H */
diff --git a/arch/arm/include/asm/atf_common.h b/arch/arm/include/asm/atf_common.h
new file mode 100644
index 0000000000..ab99cd3ac1
--- /dev/null
+++ b/arch/arm/include/asm/atf_common.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * This is from the ARM TF Project,
+ * Repository: https://github.com/ARM-software/arm-trusted-firmware.git
+ * File: include/common/bl_common.h
+ * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
+ * reserved.
+ * Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd
+ */
+
+#ifndef __BL_COMMON_H__
+#define __BL_COMMON_H__
+
+#define ATF_PARAM_EP		0x01
+#define ATF_PARAM_IMAGE_BINARY	0x02
+#define ATF_PARAM_BL31		0x03
+#define ATF_PARAM_BL_PARAMS	0x05
+
+#define ATF_VERSION_1	0x01
+#define ATF_VERSION_2	0x02
+
+#define ATF_BL31_IMAGE_ID	0x03
+#define ATF_BL32_IMAGE_ID	0x04
+#define ATF_BL33_IMAGE_ID	0x05
+
+#define ATF_EP_SECURE	0x0
+#define ATF_EP_NON_SECURE	0x1
+
+#define MODE_RW_SHIFT	0x4
+#define MODE_RW_MASK	0x1
+#define MODE_RW_64	0x0
+#define MODE_RW_32	0x1
+
+#define MODE_EL_SHIFT	0x2
+#define MODE_EL_MASK	0x3
+#define MODE_EL3	0x3
+#define MODE_EL2	0x2
+#define MODE_EL1	0x1
+#define MODE_EL0	0x0
+
+#define MODE_SP_SHIFT	0x0
+#define MODE_SP_MASK	0x1
+#define MODE_SP_EL0	0x0
+#define MODE_SP_ELX	0x1
+
+#define SPSR_DAIF_SHIFT	6
+#define SPSR_DAIF_MASK	0x0f
+
+#define SPSR_64(el, sp, daif)		\
+	(MODE_RW_64 << MODE_RW_SHIFT |	\
+	 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT |	\
+	 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT |	\
+	 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
+
+#define SPSR_FIQ             (1 << 6)
+#define SPSR_IRQ             (1 << 7)
+#define SPSR_SERROR          (1 << 8)
+#define SPSR_DEBUG           (1 << 9)
+#define SPSR_EXCEPTION_MASK  (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
+
+#define DAIF_FIQ_BIT (1<<0)
+#define DAIF_IRQ_BIT (1<<1)
+#define DAIF_ABT_BIT (1<<2)
+#define DAIF_DBG_BIT (1<<3)
+#define DISABLE_ALL_EXECPTIONS	\
+	(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
+
+#ifndef __ASSEMBLY__
+
+/*******************************************************************************
+ * Structure used for telling the next BL how much of a particular type of
+ * memory is available for its use and how much is already used.
+ ******************************************************************************/
+struct aapcs64_params {
+	unsigned long arg0;
+	unsigned long arg1;
+	unsigned long arg2;
+	unsigned long arg3;
+	unsigned long arg4;
+	unsigned long arg5;
+	unsigned long arg6;
+	unsigned long arg7;
+};
+
+/***************************************************************************
+ * This structure provides version information and the size of the
+ * structure, attributes for the structure it represents
+ ***************************************************************************/
+struct param_header {
+	uint8_t type;		/* type of the structure */
+	uint8_t version;    /* version of this structure */
+	uint16_t size;      /* size of this structure in bytes */
+	uint32_t attr;      /* attributes: unused bits SBZ */
+};
+
+/*****************************************************************************
+ * This structure represents the superset of information needed while
+ * switching exception levels. The only two mechanisms to do so are
+ * ERET & SMC. Security state is indicated using bit zero of header
+ * attribute
+ * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
+ * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
+ * processing SMC to jump to BL31.
+ *****************************************************************************/
+struct entry_point_info {
+	struct param_header h;
+	uintptr_t pc;
+	uint32_t spsr;
+	struct aapcs64_params args;
+};
+
+/*****************************************************************************
+ * Image info binary provides information from the image loader that
+ * can be used by the firmware to manage available trusted RAM.
+ * More advanced firmware image formats can provide additional
+ * information that enables optimization or greater flexibility in the
+ * common firmware code
+ *****************************************************************************/
+struct atf_image_info {
+	struct param_header h;
+	uintptr_t image_base;   /* physical address of base of image */
+	uint32_t image_size;    /* bytes read from image file */
+};
+
+/*****************************************************************************
+ * The image descriptor struct definition.
+ *****************************************************************************/
+struct image_desc {
+	/* Contains unique image id for the image. */
+	unsigned int image_id;
+	/*
+	 * This member contains Image state information.
+	 * Refer IMAGE_STATE_XXX defined above.
+	 */
+	unsigned int state;
+	uint32_t copied_size;	/* image size copied in blocks */
+	struct atf_image_info atf_image_info;
+	struct entry_point_info ep_info;
+};
+
+/*******************************************************************************
+ * This structure represents the superset of information that can be passed to
+ * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
+ * populated only if BL2 detects its presence. A pointer to a structure of this
+ * type should be passed in X0 to BL31's cold boot entrypoint.
+ *
+ * Use of this structure and the X0 parameter is not mandatory: the BL31
+ * platform code can use other mechanisms to provide the necessary information
+ * about BL32 and BL33 to the common and SPD code.
+ *
+ * BL31 image information is mandatory if this structure is used. If either of
+ * the optional BL32 and BL33 image information is not provided, this is
+ * indicated by the respective image_info pointers being zero.
+ ******************************************************************************/
+struct bl31_params {
+	struct param_header h;
+	struct atf_image_info *bl31_image_info;
+	struct entry_point_info *bl32_ep_info;
+	struct atf_image_info *bl32_image_info;
+	struct entry_point_info *bl33_ep_info;
+	struct atf_image_info *bl33_image_info;
+};
+
+void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
+		uintptr_t bl33_entry, uintptr_t fdt_addr);
+
+/* BL image node in the BL image execution sequence */
+struct bl_params_node {
+	unsigned int image_id;
+	struct atf_image_info *image_info;
+	struct entry_point_info *ep_info;
+	struct bl_params_node *next_params_info;
+};
+
+/*
+ * BL image head node in the BL image execution sequence
+ * It is also used to pass information to next BL image.
+ */
+struct bl_params {
+	struct param_header h;
+	struct bl_params_node *head;
+};
+
+struct bl2_to_bl31_params_mem_v2 {
+	struct bl_params bl_params;
+	struct bl_params_node bl31_params_node;
+	struct bl_params_node bl32_params_node;
+	struct bl_params_node bl33_params_node;
+	struct atf_image_info bl31_image_info;
+	struct atf_image_info bl32_image_info;
+	struct atf_image_info bl33_image_info;
+	struct entry_point_info bl31_ep_info;
+	struct entry_point_info bl32_ep_info;
+	struct entry_point_info bl33_ep_info;
+};
+
+struct bl2_to_bl31_params_mem_v2 *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
+					uintptr_t bl33_entry, uintptr_t fdt_addr);
+void bl31_entry_v2(uintptr_t bl31_entry, struct bl_params *params, void *fdt_addr);
+
+#endif /*__ASSEMBLY__ */
+
+#endif /* __BL_COMMON_H__ */
diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h
index 8409a77d2e..135d0585b1 100644
--- a/arch/arm/include/asm/barebox-arm-head.h
+++ b/arch/arm/include/asm/barebox-arm-head.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_HEAD_H
 #define __ASM_ARM_HEAD_H
 
@@ -16,13 +18,10 @@ void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2);
 #define ARM_HEAD_SPARE_OFS	0x30
 #define ARM_HEAD_SPARE_MARKER	0x55555555
 
-#ifdef CONFIG_HAVE_MACH_ARM_HEAD
-#include <mach/barebox-arm-head.h>
-#else
+#ifdef CONFIG_CPU_32
 static inline void __barebox_arm_head(void)
 {
 	__asm__ __volatile__ (
-#ifdef CONFIG_CPU_32
 #ifdef CONFIG_THUMB2_BAREBOX
 		".arm\n"
 		"adr r9, 1f + 1\n"
@@ -43,33 +42,17 @@ static inline void __barebox_arm_head(void)
 		"1: b 1b\n"
 		"1: b 1b\n"
 #endif
-#else
-		"b 2f\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-#endif
 		".asciz \"barebox\"\n"
-#ifdef CONFIG_CPU_32
 		".word _text\n"				/* text base. If copied there,
 							 * barebox can skip relocation
 							 */
-#else
-		".word 0xffffffff\n"
-#endif
 		".word _barebox_image_size\n"		/* image size to copy */
 		".rept 8\n"
 		".word 0x55555555\n"
 		".endr\n"
 		"2:\n"
 #ifdef CONFIG_PBL_BREAK
-#ifdef CONFIG_CPU_V8
-		"brk #17\n"
-#else
 		"bkpt #17\n"
-#endif
 		"nop\n"
 #else
 		"nop\n"
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 348a55e804..7a7e5a2403 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -15,77 +15,33 @@
 #include <linux/sizes.h>
 #include <asm-generic/memory_layout.h>
 #include <linux/kernel.h>
+#include <linux/pagemap.h>
 #include <linux/types.h>
 #include <linux/compiler.h>
 #include <asm/barebox-arm-head.h>
+#include <asm/common.h>
 #include <asm/sections.h>
+#include <asm/reloc.h>
+#include <linux/stringify.h>
+#include <boarddata.h>
 
-/*
- * We have a 4GiB address space split into 1MiB sections, with each
- * section header taking 4 bytes
- */
-#define ARM_TTB_SIZE	(SZ_4G / SZ_1M * sizeof(u32))
+#define ARM_EARLY_PAGETABLE_SIZE	SZ_64K
 
-unsigned long get_runtime_offset(void);
-
-/* global_variable_offset() - Access global variables when not running at link address
- *
- * Get the offset of global variables when not running at the address we are
- * linked at.
- */
-static inline unsigned long global_variable_offset(void)
-{
-#ifdef CONFIG_CPU_V8
-	unsigned long text;
-
-	__asm__ __volatile__(
-		"adr    %0, _text\n"
-		: "=r" (text)
-		:
-		: "memory");
-	return text - (unsigned long)_text;
-#else
-	return get_runtime_offset();
-#endif
-}
-
-void setup_c(void);
-void pbl_barebox_break(void);
-void relocate_to_current_adr(void);
-void relocate_to_adr(unsigned long target);
 void __noreturn barebox_arm_entry(unsigned long membase, unsigned long memsize, void *boarddata);
 
-struct barebox_arm_boarddata {
-#define BAREBOX_ARM_BOARDDATA_MAGIC	0xabe742c3
-	u32 magic;
-	u32 machine; /* machine number to pass to barebox. This may or may
-		      * not be a ARM machine number registered on arm.linux.org.uk.
-		      * It must only be unique across barebox. Please use a number
-		      * that do not potientially clashes with registered machines,
-		      * i.e. use a number > 0x10000.
-		      */
-};
-
-/*
- * Create a boarddata struct at given address. Suitable to be passed
- * as boarddata to barebox_arm_entry(). The machine can be retrieved
- * later with barebox_arm_machine().
- */
-static inline void boarddata_create(void *adr, u32 machine)
-{
-	struct barebox_arm_boarddata *bd = adr;
-
-	bd->magic = BAREBOX_ARM_BOARDDATA_MAGIC;
-	bd->machine = machine;
-}
+#define barebox_arm_boarddata		barebox_boarddata
+#define BAREBOX_ARM_BOARDDATA_MAGIC	BAREBOX_BOARDDATA_MAGIC
 
 u32 barebox_arm_machine(void);
 
 unsigned long arm_mem_ramoops_get(void);
+unsigned long arm_mem_membase_get(void);
 unsigned long arm_mem_endmem_get(void);
 
 struct barebox_arm_boarddata *barebox_arm_get_boarddata(void);
 
+#define barebox_arm_get_boarddata barebox_get_boarddata
+
 #if defined(CONFIG_RELOCATABLE) && defined(CONFIG_ARM_EXCEPTIONS)
 void arm_fixup_vectors(void);
 #else
@@ -96,46 +52,52 @@ static inline void arm_fixup_vectors(void)
 
 void *barebox_arm_boot_dtb(void);
 
-static inline unsigned long arm_mem_stack_top(unsigned long membase,
-					      unsigned long endmem)
+static inline unsigned long arm_mem_optee(unsigned long endmem)
+{
+	return endmem - OPTEE_SIZE;
+}
+
+static inline unsigned long arm_mem_scratch(unsigned long endmem)
 {
-	if (IS_ENABLED(CONFIG_BOOTM_OPTEE) || IS_ENABLED(CONFIG_PBL_OPTEE))
-		endmem -= OPTEE_SIZE;
+	return arm_mem_optee(endmem) - SZ_32K;
+}
 
-	return endmem - SZ_64K;
+static inline unsigned long arm_mem_stack(unsigned long endmem)
+{
+	return arm_mem_scratch(endmem) - STACK_SIZE;
 }
 
-static inline unsigned long arm_mem_stack(unsigned long membase,
-					  unsigned long endmem)
+static inline unsigned long arm_mem_guard_page(unsigned long endmem)
 {
-	return arm_mem_stack_top(membase, endmem) - STACK_SIZE;
+	endmem = arm_mem_stack(endmem);
+
+	if (!IS_ENABLED(CONFIG_STACK_GUARD_PAGE))
+		return endmem;
+
+	return ALIGN_DOWN(endmem, PAGE_SIZE) - PAGE_SIZE;
 }
 
-static inline unsigned long arm_mem_ttb(unsigned long membase,
-					unsigned long endmem)
+static inline unsigned long arm_mem_ttb(unsigned long endmem)
 {
-	endmem = arm_mem_stack(membase, endmem);
-	endmem = ALIGN_DOWN(endmem, ARM_TTB_SIZE) - ARM_TTB_SIZE;
+	endmem = arm_mem_guard_page(endmem);
+	endmem = ALIGN_DOWN(endmem, ARM_EARLY_PAGETABLE_SIZE) - ARM_EARLY_PAGETABLE_SIZE;
 
 	return endmem;
 }
 
-static inline unsigned long arm_mem_early_malloc(unsigned long membase,
-						 unsigned long endmem)
+static inline unsigned long arm_mem_early_malloc(unsigned long endmem)
 {
-	return arm_mem_ttb(membase, endmem) - SZ_128K;
+	return arm_mem_ttb(endmem) - SZ_128K;
 }
 
-static inline unsigned long arm_mem_early_malloc_end(unsigned long membase,
-						     unsigned long endmem)
+static inline unsigned long arm_mem_early_malloc_end(unsigned long endmem)
 {
-	return arm_mem_ttb(membase, endmem);
+	return arm_mem_ttb(endmem);
 }
 
-static inline unsigned long arm_mem_ramoops(unsigned long membase,
-					    unsigned long endmem)
+static inline unsigned long arm_mem_ramoops(unsigned long endmem)
 {
-	endmem = arm_mem_ttb(membase, endmem);
+	endmem = arm_mem_ttb(endmem);
 #ifdef CONFIG_FS_PSTORE_RAMOOPS
 	endmem -= CONFIG_FS_PSTORE_RAMOOPS_SIZE;
 	endmem = ALIGN_DOWN(endmem, SZ_4K);
@@ -144,11 +106,26 @@ static inline unsigned long arm_mem_ramoops(unsigned long membase,
 	return endmem;
 }
 
+static inline unsigned long arm_mem_stack_top(unsigned long endmem)
+{
+	return arm_mem_stack(endmem) + STACK_SIZE;
+}
+
+static inline const void *arm_mem_scratch_get(void)
+{
+	return (const void *)arm_mem_scratch(arm_mem_endmem_get());
+}
+
+static inline unsigned long arm_mem_guard_page_get(void)
+{
+	return arm_mem_guard_page(arm_mem_endmem_get());
+}
+
 static inline unsigned long arm_mem_barebox_image(unsigned long membase,
 						  unsigned long endmem,
 						  unsigned long size)
 {
-	endmem = arm_mem_ramoops(membase, endmem);
+	endmem = arm_mem_ramoops(endmem);
 
 	if (IS_ENABLED(CONFIG_RELOCATABLE)) {
 		return ALIGN_DOWN(endmem - size, SZ_1M);
@@ -160,19 +137,75 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase,
 	}
 }
 
+/*
+ * Unlike ENTRY_FUNCTION, this can be used to setup stack for a C entry
+ * point on both ARM32 and ARM64. ENTRY_FUNCTION on ARM64 can only be used
+ * if preceding boot stage has initialized the stack pointer.
+ *
+ * Stack top of 0 means stack is already set up. In that case, the follow-up
+ * code block will not be inlined and may spill to stack right away.
+ */
+#ifdef CONFIG_CPU_64
+
+void __barebox_arm64_head(ulong x0, ulong x1, ulong x2);
+
+#define ENTRY_FUNCTION_WITHSTACK_HEAD(name, stack_top, head, arg0, arg1, arg2)	\
+	void name(ulong r0, ulong r1, ulong r2);			\
+									\
+	static void __##name(ulong, ulong, ulong);			\
+									\
+	void __section(.text_head_entry_##name)	name			\
+				(ulong r0, ulong r1, ulong r2)		\
+		{							\
+			static __section(.pbl_board_stack_top_##name)	\
+				const ulong __stack_top = (stack_top);	\
+			__keep_symbolref(head);				\
+			__keep_symbolref(__stack_top);			\
+			__##name(r0, r1, r2);				\
+		}							\
+		static void noinline __##name				\
+			(ulong arg0, ulong arg1, ulong arg2)
+
+#define ENTRY_FUNCTION_WITHSTACK(name, stack_top, arg0, arg1, arg2)	\
+	ENTRY_FUNCTION_WITHSTACK_HEAD(name, stack_top,			\
+			      __barebox_arm64_head, arg0, arg1, arg2)
+
 #define ENTRY_FUNCTION(name, arg0, arg1, arg2)				\
-	void name (uint32_t r0, uint32_t r1, uint32_t r2);		\
+	ENTRY_FUNCTION_WITHSTACK(name, 0, arg0, arg1, arg2)
+
+#else
+#define ENTRY_FUNCTION_WITHSTACK_HEAD(name, stack_top, head, arg0, arg1, arg2)	\
+	static void ____##name(ulong, ulong, ulong);			\
+	__ENTRY_FUNCTION_HEAD(name, head, arg0, arg1, arg2)		\
+	{								\
+		if (stack_top)						\
+			arm_setup_stack(stack_top);			\
+		____##name(arg0, arg1, arg2);				\
+	}								\
+	static void noinline ____##name					\
+		(ulong arg0, ulong arg1, ulong arg2)
+
+#define __ENTRY_FUNCTION_HEAD(name, head, arg0, arg1, arg2)		\
+	void name(ulong r0, ulong r1, ulong r2);			\
 									\
-	static void __##name(uint32_t, uint32_t, uint32_t);		\
+	static void __##name(ulong, ulong, ulong);			\
 									\
-	void NAKED __section(.text_head_entry_##name)	name		\
-				(uint32_t r0, uint32_t r1, uint32_t r2)	\
+	void __naked __section(.text_head_entry_##name)	name		\
+				(ulong r0, ulong r1, ulong r2)		\
 		{							\
-			__barebox_arm_head();				\
+			head();				\
 			__##name(r0, r1, r2);				\
 		}							\
-		static void NAKED noinline __##name			\
-			(uint32_t arg0, uint32_t arg1, uint32_t arg2)
+	static void __naked noinline __##name				\
+		(ulong arg0, ulong arg1, ulong arg2)
+
+#define ENTRY_FUNCTION(name, arg0, arg1, arg2)		\
+	__ENTRY_FUNCTION_HEAD(name, __barebox_arm_head, arg0, arg1, arg2)
+
+#define ENTRY_FUNCTION_WITHSTACK(name, stack_top, arg0, arg1, arg2)	\
+	ENTRY_FUNCTION_WITHSTACK_HEAD(name, stack_top, \
+			      __barebox_arm_head, arg0, arg1, arg2)
+#endif
 
 /*
  * When using compressed images in conjunction with relocatable images
diff --git a/arch/arm/include/asm/barebox.lds.h b/arch/arm/include/asm/barebox.lds.h
new file mode 100644
index 0000000000..a5c74381d8
--- /dev/null
+++ b/arch/arm/include/asm/barebox.lds.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#if defined CONFIG_ARCH_EP93XX
+#include <mach/ep93xx/barebox.lds.h>
+#endif
+
+#ifdef CONFIG_CPU_32
+#define BAREBOX_OUTPUT_FORMAT	"elf32-littlearm", "elf32-littlearm", "elf32-littlearm"
+#define BAREBOX_OUTPUT_ARCH	"arm"
+#else
+#define BAREBOX_OUTPUT_FORMAT	"elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64"
+#define BAREBOX_OUTPUT_ARCH	"aarch64"
+#endif
+
+#ifdef CONFIG_CPU_32
+#define BAREBOX_RELOCATION_TYPE	rel
+#else
+#define BAREBOX_RELOCATION_TYPE	rela
+#endif
+
+#define BAREBOX_RELOCATION_TABLE					\
+	.rel_dyn_start : { *(.__rel_dyn_start) }			\
+	.BAREBOX_RELOCATION_TYPE.dyn : { *(.BAREBOX_RELOCATION_TYPE*) }	\
+	.rel_dyn_end : { *(.__rel_dyn_end) }				\
+	.__dynsym_start :  { *(.__dynsym_start) }			\
+	.dynsym : { *(.dynsym) }					\
+	.__dynsym_end : { *(.__dynsym_end) }
+
+
+#include <asm-generic/barebox.lds.h>
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index d8a4d9b667..2d0d300da2 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 /*
  * Copyright 1995, Russell King.
  * Various bits and pieces copyrights include:
diff --git a/arch/arm/include/asm/bitsperlong.h b/arch/arm/include/asm/bitsperlong.h
index 6dc0bb0c13..bf000a04cc 100644
--- a/arch/arm/include/asm/bitsperlong.h
+++ b/arch/arm/include/asm/bitsperlong.h
@@ -1 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <asm-generic/bitsperlong.h>
diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h
index c3489f1e1f..751dc0e530 100644
--- a/arch/arm/include/asm/byteorder.h
+++ b/arch/arm/include/asm/byteorder.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 /*
  *  linux/include/asm-arm/byteorder.h
  *
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index bf3a1a0ed2..261c30129a 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_CACHE_H
 #define __ASM_CACHE_H
 
@@ -16,11 +18,12 @@ static inline void icache_invalidate(void)
 #endif
 }
 
-int arm_set_cache_functions(void);
-
 void arm_early_mmu_cache_flush(void);
 void arm_early_mmu_cache_invalidate(void);
 
+#define sync_caches_for_execution sync_caches_for_execution
 void sync_caches_for_execution(void);
 
+#include <asm-generic/cache.h>
+
 #endif
diff --git a/arch/arm/include/asm/common.h b/arch/arm/include/asm/common.h
index d03ee6273f..9832a6a4d2 100644
--- a/arch/arm/include/asm/common.h
+++ b/arch/arm/include/asm/common.h
@@ -1,6 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_COMMON_H
 #define __ASM_ARM_COMMON_H
 
+#include <linux/compiler.h>
+
 static inline unsigned long get_pc(void)
 {
 	unsigned long pc;
@@ -46,8 +50,23 @@ static inline unsigned long get_sp(void)
 	return sp;
 }
 
+extern void __compiletime_error(
+	"arm_setup_stack() called outside of naked function. On ARM64, "
+	"stack should be setup in non-inline assembly before branching to C entry point."
+) __unsafe_setup_stack(void);
+
+/*
+ * Sets up new stack growing down from top within a naked C function.
+ * The first stack word will be top - sizeof(word).
+ *
+ * Avoid interleaving with C code as much as possible and jump
+ * ASAP to a noinline function.
+ */
 static inline void arm_setup_stack(unsigned long top)
 {
+	if (IS_ENABLED(CONFIG_CPU_64))
+		__unsafe_setup_stack();
+
 	__asm__ __volatile__("mov sp, %0"
 			     :
 			     : "r"(top));
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index f39939bd44..c3fc057650 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -1,9 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_CPUTYPE_H
 #define __ASM_ARM_CPUTYPE_H
 
 #include <linux/stringify.h>
 #include <linux/kernel.h>
 
+#ifdef CONFIG_CPU_64v8
+
+#define CPUID_ID	midr_el1
+#define CPUID_CACHETYPE	ctr_el0
+#define CPUID_MPIDR	mpidr_el1
+
+#define read_cpuid(reg)							\
+	({								\
+		unsigned int __val;					\
+		asm("mrs	%0, " __stringify(reg)			\
+		    : "=r" (__val)					\
+		    :							\
+		    : "cc");						\
+		__val;							\
+	})
+#else
+
 #define CPUID_ID	0
 #define CPUID_CACHETYPE	1
 #define CPUID_TCM	2
@@ -25,8 +44,6 @@
 #define CPUID_EXT_ISAR4	"c2, 4"
 #define CPUID_EXT_ISAR5	"c2, 5"
 
-extern unsigned int processor_id;
-
 #define read_cpuid(reg)							\
 	({								\
 		unsigned int __val;					\
@@ -45,6 +62,9 @@ extern unsigned int processor_id;
 		    : "cc");						\
 		__val;							\
 	})
+#endif
+
+extern unsigned int processor_id;
 
 /*
  * The CPU ID never changes at run time, so we might as well tell the
diff --git a/arch/arm/include/asm/debug_ll.h b/arch/arm/include/asm/debug_ll.h
new file mode 100644
index 0000000000..98a7d0d839
--- /dev/null
+++ b/arch/arm/include/asm/debug_ll.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_DEBUG_LL_H__
+#define __ASM_DEBUG_LL_H__
+
+#ifdef CONFIG_DEBUG_IMX_UART
+#include <mach/imx/debug_ll.h>
+#endif
+
+#ifdef CONFIG_DEBUG_ROCKCHIP_UART
+#include <mach/rockchip/debug_ll.h>
+#endif
+
+#ifdef CONFIG_DEBUG_OMAP_UART
+#include <mach/omap/debug_ll.h>
+#endif
+
+#ifdef CONFIG_DEBUG_ZYNQMP_UART
+#include <mach/zynqmp/debug_ll.h>
+#endif
+
+#ifdef CONFIG_DEBUG_STM32MP_UART
+#include <mach/stm32mp/debug_ll.h>
+#endif
+
+#ifdef CONFIG_DEBUG_VEXPRESS_UART
+#include <mach/vexpress/debug_ll.h>
+#endif
+
+#ifdef CONFIG_DEBUG_BCM283X_UART
+#include <mach/bcm283x/debug_ll.h>
+#endif
+
+#ifdef CONFIG_DEBUG_QEMU_ARM64_VIRT
+#define DEBUG_LL_UART_ADDR		0x9000000
+#include <debug_ll/pl011.h>
+#elif defined CONFIG_ARCH_MVEBU
+#include <mach/mvebu/debug_ll.h>
+#elif defined CONFIG_ARCH_DAVINCI
+#include <mach/davinci/debug_ll.h>
+#elif defined CONFIG_ARCH_ZYNQ
+#include <mach/zynq/debug_ll.h>
+#elif defined CONFIG_ARCH_VERSATILE
+#include <mach/versatile/debug_ll.h>
+#elif defined CONFIG_ARCH_LAYERSCAPE
+#include <mach/layerscape/debug_ll.h>
+#elif defined CONFIG_ARCH_TEGRA
+#include <mach/tegra/debug_ll.h>
+#elif defined CONFIG_ARCH_UEMD
+#include <mach/uemd/debug_ll.h>
+#elif defined CONFIG_ARCH_SOCFPGA
+#include <mach/socfpga/debug_ll.h>
+#elif defined CONFIG_ARCH_PXA
+#include <mach/pxa/debug_ll.h>
+#elif defined CONFIG_ARCH_NOMADIK
+#include <mach/nomadik/debug_ll.h>
+#elif defined CONFIG_ARCH_MXS
+#include <mach/mxs/debug_ll.h>
+#elif defined CONFIG_ARCH_EP93XX
+#include <mach/ep93xx/debug_ll.h>
+#elif defined CONFIG_ARCH_DIGIC
+#include <mach/digic/debug_ll.h>
+#elif defined CONFIG_ARCH_CLPS711X
+#include <mach/clps711x/debug_ll.h>
+#elif defined CONFIG_ARCH_AT91
+#include <mach/at91/debug_ll.h>
+#elif defined CONFIG_ARCH_K3
+#include <mach/k3/debug_ll.h>
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 226b1c1464..0774a11c5a 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -3,13 +3,10 @@
 
 #include <common.h>
 
-#define dma_alloc dma_alloc
-static inline void *dma_alloc(size_t size)
-{
-	return xmemalign(64, ALIGN(size, 64));
-}
+#define DMA_ALIGNMENT	64
 
 #ifndef CONFIG_MMU
+#define dma_alloc_coherent dma_alloc_coherent
 static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
 {
 	void *ret = xmemalign(4096, size);
@@ -21,24 +18,28 @@ static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
 	return ret;
 }
 
+#define dma_alloc_writecombine dma_alloc_writecombine
 static inline void *dma_alloc_writecombine(size_t size, dma_addr_t *dma_handle)
 {
 	return dma_alloc_coherent(size, dma_handle);
 }
 
+#define dma_free_coherent dma_free_coherent
 static inline void dma_free_coherent(void *mem, dma_addr_t dma_handle,
 				     size_t size)
 {
 	free(mem);
 }
 
-static inline void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
-					   enum dma_data_direction dir)
+#define arch_sync_dma_for_cpu arch_sync_dma_for_cpu
+static inline void arch_sync_dma_for_cpu(void *vaddr, size_t size,
+					 enum dma_data_direction dir)
 {
 }
 
-static inline void dma_sync_single_for_device(dma_addr_t address, size_t size,
-					      enum dma_data_direction dir)
+#define arch_sync_dma_for_device arch_sync_dma_for_device
+static inline void arch_sync_dma_for_device(void *vaddr, size_t size,
+					    enum dma_data_direction dir)
 {
 }
 #endif
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 3def567699..4043e6fd5b 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASMARM_ELF_H
 #define __ASMARM_ELF_H
 
@@ -20,6 +22,7 @@ typedef struct user_fp elf_fpregset_t;
 #endif
 
 #define EM_ARM	40
+#define EM_AARCH64	183
 #define EF_ARM_APCS26 0x08
 #define EF_ARM_SOFT_FLOAT 0x200
 #define EF_ARM_EABI_MASK 0xFF000000
@@ -42,7 +45,11 @@ typedef struct user_fp elf_fpregset_t;
 #else
 #define ELF_DATA	ELFDATA2LSB
 #endif
+#ifdef CONFIG_CPU_64
+#define ELF_ARCH	EM_AARCH64
+#else
 #define ELF_ARCH	EM_ARM
+#endif
 
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index f83f528141..d7e4c3cbf0 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __GIC_H__
 #define __GIC_H__
 
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index 8a58390a19..7911628ba7 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
 #define __ASM_ARM_HARDWARE_ARM_TIMER_H
 
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index b442a37b9c..486b142950 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_IO_H
 #define __ASM_ARM_IO_H
 
@@ -8,7 +10,6 @@
 #define memset_io memset_io
 
 #include <asm-generic/io.h>
-#include <asm-generic/bitio.h>
 
 /*
  * String version of IO memory access ops:
@@ -17,14 +18,4 @@ extern void memcpy_fromio(void *, const volatile void __iomem *, size_t);
 extern void memcpy_toio(volatile void __iomem *, const void *, size_t);
 extern void memset_io(volatile void __iomem *, int, size_t);
 
-static inline void *phys_to_virt(unsigned long phys)
-{
-	return (void *)phys;
-}
-
-static inline unsigned long virt_to_phys(volatile void *mem)
-{
-	return (unsigned long)mem;
-}
-
 #endif	/* __ASM_ARM_IO_H */
diff --git a/arch/arm/include/asm/linkage.h b/arch/arm/include/asm/linkage.h
index 5a25632b1b..728ebe6f6f 100644
--- a/arch/arm/include/asm/linkage.h
+++ b/arch/arm/include/asm/linkage.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_LINKAGE_H
 #define __ASM_LINKAGE_H
 
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
new file mode 100644
index 0000000000..f16aeb88db
--- /dev/null
+++ b/arch/arm/include/asm/mach-types.h
@@ -0,0 +1,868 @@
+/*
+ * Machine type definitions for legacy platforms.
+ */
+
+#ifndef __ASM_ARM_MACH_TYPE_H
+#define __ASM_ARM_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_LUBBOCK              89
+#define MACH_TYPE_VERSATILE_PB         387
+#define MACH_TYPE_CSB337               399
+#define MACH_TYPE_MAINSTONE            406
+#define MACH_TYPE_NOMADIK              420
+#define MACH_TYPE_EDB9312              451
+#define MACH_TYPE_EDB9301              462
+#define MACH_TYPE_EDB9315              463
+#define MACH_TYPE_SCB9328              508
+#define MACH_TYPE_EDB9302              538
+#define MACH_TYPE_EDB9307              607
+#define MACH_TYPE_AT91RM9200EK         705
+#define MACH_TYPE_PCM027               732
+#define MACH_TYPE_EDB9315A             772
+#define MACH_TYPE_AT91SAM9261EK        848
+#define MACH_TYPE_AT91SAM9260EK        1099
+#define MACH_TYPE_EDB9302A             1127
+#define MACH_TYPE_EDB9307A             1128
+#define MACH_TYPE_PM9261               1187
+#define MACH_TYPE_AT91SAM9263EK        1202
+#define MACH_TYPE_ZYLONITE             1233
+#define MACH_TYPE_MIOA701              1257
+#define MACH_TYPE_PM9263               1475
+#define MACH_TYPE_OMAP3EVM             1535
+#define MACH_TYPE_OMAP3_BEAGLE         1546
+#define MACH_TYPE_AT91SAM9G20EK        1624
+#define MACH_TYPE_USB_A9260            1709
+#define MACH_TYPE_USB_A9263            1710
+#define MACH_TYPE_QIL_A9260            1711
+#define MACH_TYPE_PICOCOM1             1751
+#define MACH_TYPE_AT91SAM9M10G45EK     1830
+#define MACH_TYPE_USB_A9G20            1841
+#define MACH_TYPE_QIL_A9G20            1844
+#define MACH_TYPE_CHUMBY               1937
+#define MACH_TYPE_TNY_A9260            2058
+#define MACH_TYPE_TNY_A9G20            2059
+#define MACH_TYPE_MX51_BABBAGE         2125
+#define MACH_TYPE_TNY_A9263            2140
+#define MACH_TYPE_AT91SAM9G10EK        2159
+#define MACH_TYPE_TX25                 2177
+#define MACH_TYPE_MX23EVK              2629
+#define MACH_TYPE_PM9G45               2672
+#define MACH_TYPE_OMAP4_PANDA          2791
+#define MACH_TYPE_PCAAL1               2843
+#define MACH_TYPE_ARMADA_XP_DB         3036
+#define MACH_TYPE_TX28                 3043
+#define MACH_TYPE_BCM2708              3138
+#define MACH_TYPE_MX53_LOCO            3273
+#define MACH_TYPE_TX53                 3279
+#define MACH_TYPE_CCMX53               3346
+#define MACH_TYPE_CCWMX53              3348
+#define MACH_TYPE_VMX53                3359
+#define MACH_TYPE_PCM049               3364
+#define MACH_TYPE_DSS11                3787
+#define MACH_TYPE_BEAGLEBONE           3808
+#define MACH_TYPE_PCAAXL2              3912
+#define MACH_TYPE_MX6Q_SABRESD         3980
+#define MACH_TYPE_TQMA53               4004
+#define MACH_TYPE_IMX233_OLINUXINO     4105
+#define MACH_TYPE_CFA10036             4142
+#define MACH_TYPE_PCM051               4144
+#define MACH_TYPE_HABA_KNX_LITE        4310
+#define MACH_TYPE_VAR_SOM_MX6          4419
+#define MACH_TYPE_PCAAXS1              4526
+#define MACH_TYPE_PFLA03               4575
+
+#ifdef CONFIG_ARCH_LUBBOCK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LUBBOCK
+# endif
+# define machine_is_lubbock()	(machine_arch_type == MACH_TYPE_LUBBOCK)
+#else
+# define machine_is_lubbock()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_VERSATILE_PB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VERSATILE_PB
+# endif
+# define machine_is_versatile_pb()	(machine_arch_type == MACH_TYPE_VERSATILE_PB)
+#else
+# define machine_is_versatile_pb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB337
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB337
+# endif
+# define machine_is_csb337()	(machine_arch_type == MACH_TYPE_CSB337)
+#else
+# define machine_is_csb337()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAINSTONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAINSTONE
+# endif
+# define machine_is_mainstone()	(machine_arch_type == MACH_TYPE_MAINSTONE)
+#else
+# define machine_is_mainstone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOMADIK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOMADIK
+# endif
+# define machine_is_nomadik()	(machine_arch_type == MACH_TYPE_NOMADIK)
+#else
+# define machine_is_nomadik()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9312
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9312
+# endif
+# define machine_is_edb9312()	(machine_arch_type == MACH_TYPE_EDB9312)
+#else
+# define machine_is_edb9312()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9301
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9301
+# endif
+# define machine_is_edb9301()	(machine_arch_type == MACH_TYPE_EDB9301)
+#else
+# define machine_is_edb9301()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9315
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9315
+# endif
+# define machine_is_edb9315()	(machine_arch_type == MACH_TYPE_EDB9315)
+#else
+# define machine_is_edb9315()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCB9328
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCB9328
+# endif
+# define machine_is_scb9328()	(machine_arch_type == MACH_TYPE_SCB9328)
+#else
+# define machine_is_scb9328()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9302
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9302
+# endif
+# define machine_is_edb9302()	(machine_arch_type == MACH_TYPE_EDB9302)
+#else
+# define machine_is_edb9302()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9307
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9307
+# endif
+# define machine_is_edb9307()	(machine_arch_type == MACH_TYPE_EDB9307)
+#else
+# define machine_is_edb9307()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91RM9200EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91RM9200EK
+# endif
+# define machine_is_at91rm9200ek()	(machine_arch_type == MACH_TYPE_AT91RM9200EK)
+#else
+# define machine_is_at91rm9200ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM027
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM027
+# endif
+# define machine_is_pcm027()	(machine_arch_type == MACH_TYPE_PCM027)
+#else
+# define machine_is_pcm027()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9315A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9315A
+# endif
+# define machine_is_edb9315a()	(machine_arch_type == MACH_TYPE_EDB9315A)
+#else
+# define machine_is_edb9315a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9261EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9261EK
+# endif
+# define machine_is_at91sam9261ek()	(machine_arch_type == MACH_TYPE_AT91SAM9261EK)
+#else
+# define machine_is_at91sam9261ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9260EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9260EK
+# endif
+# define machine_is_at91sam9260ek()	(machine_arch_type == MACH_TYPE_AT91SAM9260EK)
+#else
+# define machine_is_at91sam9260ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9302A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9302A
+# endif
+# define machine_is_edb9302a()	(machine_arch_type == MACH_TYPE_EDB9302A)
+#else
+# define machine_is_edb9302a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9307A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9307A
+# endif
+# define machine_is_edb9307a()	(machine_arch_type == MACH_TYPE_EDB9307A)
+#else
+# define machine_is_edb9307a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PM9261
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PM9261
+# endif
+# define machine_is_pm9261()	(machine_arch_type == MACH_TYPE_PM9261)
+#else
+# define machine_is_pm9261()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9263EK
+# endif
+# define machine_is_at91sam9263ek()	(machine_arch_type == MACH_TYPE_AT91SAM9263EK)
+#else
+# define machine_is_at91sam9263ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZYLONITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZYLONITE
+# endif
+# define machine_is_zylonite()	(machine_arch_type == MACH_TYPE_ZYLONITE)
+#else
+# define machine_is_zylonite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MIOA701
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MIOA701
+# endif
+# define machine_is_mioa701()	(machine_arch_type == MACH_TYPE_MIOA701)
+#else
+# define machine_is_mioa701()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PM9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PM9263
+# endif
+# define machine_is_pm9263()	(machine_arch_type == MACH_TYPE_PM9263)
+#else
+# define machine_is_pm9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3EVM
+# endif
+# define machine_is_omap3evm()	(machine_arch_type == MACH_TYPE_OMAP3EVM)
+#else
+# define machine_is_omap3evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_BEAGLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_BEAGLE
+# endif
+# define machine_is_omap3_beagle()	(machine_arch_type == MACH_TYPE_OMAP3_BEAGLE)
+#else
+# define machine_is_omap3_beagle()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G20EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9G20EK
+# endif
+# define machine_is_at91sam9g20ek()	(machine_arch_type == MACH_TYPE_AT91SAM9G20EK)
+#else
+# define machine_is_at91sam9g20ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_USB_A9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_USB_A9260
+# endif
+# define machine_is_usb_a9260()	(machine_arch_type == MACH_TYPE_USB_A9260)
+#else
+# define machine_is_usb_a9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_USB_A9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_USB_A9263
+# endif
+# define machine_is_usb_a9263()	(machine_arch_type == MACH_TYPE_USB_A9263)
+#else
+# define machine_is_usb_a9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QIL_A9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QIL_A9260
+# endif
+# define machine_is_qil_a9260()	(machine_arch_type == MACH_TYPE_QIL_A9260)
+#else
+# define machine_is_qil_a9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PICOCOM1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PICOCOM1
+# endif
+# define machine_is_picocom1()	(machine_arch_type == MACH_TYPE_PICOCOM1)
+#else
+# define machine_is_picocom1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9M10G45EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9M10G45EK
+# endif
+# define machine_is_at91sam9m10g45ek()	(machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK)
+#else
+# define machine_is_at91sam9m10g45ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_USB_A9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_USB_A9G20
+# endif
+# define machine_is_usb_a9g20()	(machine_arch_type == MACH_TYPE_USB_A9G20)
+#else
+# define machine_is_usb_a9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QIL_A9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QIL_A9G20
+# endif
+# define machine_is_qil_a9g20()	(machine_arch_type == MACH_TYPE_QIL_A9G20)
+#else
+# define machine_is_qil_a9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHUMBY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHUMBY
+# endif
+# define machine_is_chumby()	(machine_arch_type == MACH_TYPE_CHUMBY)
+#else
+# define machine_is_chumby()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TNY_A9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TNY_A9260
+# endif
+# define machine_is_tny_a9260()	(machine_arch_type == MACH_TYPE_TNY_A9260)
+#else
+# define machine_is_tny_a9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TNY_A9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TNY_A9G20
+# endif
+# define machine_is_tny_a9g20()	(machine_arch_type == MACH_TYPE_TNY_A9G20)
+#else
+# define machine_is_tny_a9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_BABBAGE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_BABBAGE
+# endif
+# define machine_is_mx51_babbage()	(machine_arch_type == MACH_TYPE_MX51_BABBAGE)
+#else
+# define machine_is_mx51_babbage()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TNY_A9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TNY_A9263
+# endif
+# define machine_is_tny_a9263()	(machine_arch_type == MACH_TYPE_TNY_A9263)
+#else
+# define machine_is_tny_a9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G10EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9G10EK
+# endif
+# define machine_is_at91sam9g10ek()	(machine_arch_type == MACH_TYPE_AT91SAM9G10EK)
+#else
+# define machine_is_at91sam9g10ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TX25
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TX25
+# endif
+# define machine_is_tx25()	(machine_arch_type == MACH_TYPE_TX25)
+#else
+# define machine_is_tx25()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX23EVK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX23EVK
+# endif
+# define machine_is_mx23evk()	(machine_arch_type == MACH_TYPE_MX23EVK)
+#else
+# define machine_is_mx23evk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PM9G45
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PM9G45
+# endif
+# define machine_is_pm9g45()	(machine_arch_type == MACH_TYPE_PM9G45)
+#else
+# define machine_is_pm9g45()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP4_PANDA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP4_PANDA
+# endif
+# define machine_is_omap4_panda()	(machine_arch_type == MACH_TYPE_OMAP4_PANDA)
+#else
+# define machine_is_omap4_panda()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCAAL1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCAAL1
+# endif
+# define machine_is_pcaal1()	(machine_arch_type == MACH_TYPE_PCAAL1)
+#else
+# define machine_is_pcaal1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADA_XP_DB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMADA_XP_DB
+# endif
+# define machine_is_armada_xp_db()	(machine_arch_type == MACH_TYPE_ARMADA_XP_DB)
+#else
+# define machine_is_armada_xp_db()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TX28
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TX28
+# endif
+# define machine_is_tx28()	(machine_arch_type == MACH_TYPE_TX28)
+#else
+# define machine_is_tx28()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCM2708
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCM2708
+# endif
+# define machine_is_bcm2708()	(machine_arch_type == MACH_TYPE_BCM2708)
+#else
+# define machine_is_bcm2708()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX53_LOCO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX53_LOCO
+# endif
+# define machine_is_mx53_loco()	(machine_arch_type == MACH_TYPE_MX53_LOCO)
+#else
+# define machine_is_mx53_loco()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TX53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TX53
+# endif
+# define machine_is_tx53()	(machine_arch_type == MACH_TYPE_TX53)
+#else
+# define machine_is_tx53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CCMX53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CCMX53
+# endif
+# define machine_is_ccmx53()	(machine_arch_type == MACH_TYPE_CCMX53)
+#else
+# define machine_is_ccmx53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CCWMX53
+# endif
+# define machine_is_ccwmx53()	(machine_arch_type == MACH_TYPE_CCWMX53)
+#else
+# define machine_is_ccwmx53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VMX53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VMX53
+# endif
+# define machine_is_vmx53()	(machine_arch_type == MACH_TYPE_VMX53)
+#else
+# define machine_is_vmx53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM049
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM049
+# endif
+# define machine_is_pcm049()	(machine_arch_type == MACH_TYPE_PCM049)
+#else
+# define machine_is_pcm049()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DSS11
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DSS11
+# endif
+# define machine_is_dss11()	(machine_arch_type == MACH_TYPE_DSS11)
+#else
+# define machine_is_dss11()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BEAGLEBONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BEAGLEBONE
+# endif
+# define machine_is_beaglebone()	(machine_arch_type == MACH_TYPE_BEAGLEBONE)
+#else
+# define machine_is_beaglebone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCAAXL2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCAAXL2
+# endif
+# define machine_is_pcaaxl2()	(machine_arch_type == MACH_TYPE_PCAAXL2)
+#else
+# define machine_is_pcaaxl2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX6Q_SABRESD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX6Q_SABRESD
+# endif
+# define machine_is_mx6q_sabresd()	(machine_arch_type == MACH_TYPE_MX6Q_SABRESD)
+#else
+# define machine_is_mx6q_sabresd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TQMA53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TQMA53
+# endif
+# define machine_is_tqma53()	(machine_arch_type == MACH_TYPE_TQMA53)
+#else
+# define machine_is_tqma53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IMX233_OLINUXINO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IMX233_OLINUXINO
+# endif
+# define machine_is_imx233_olinuxino()	(machine_arch_type == MACH_TYPE_IMX233_OLINUXINO)
+#else
+# define machine_is_imx233_olinuxino()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CFA10036
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CFA10036
+# endif
+# define machine_is_cfa10036()	(machine_arch_type == MACH_TYPE_CFA10036)
+#else
+# define machine_is_cfa10036()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM051
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM051
+# endif
+# define machine_is_pcm051()	(machine_arch_type == MACH_TYPE_PCM051)
+#else
+# define machine_is_pcm051()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HABA_KNX_LITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HABA_KNX_LITE
+# endif
+# define machine_is_haba_knx_lite()	(machine_arch_type == MACH_TYPE_HABA_KNX_LITE)
+#else
+# define machine_is_haba_knx_lite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VAR_SOM_MX6
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VAR_SOM_MX6
+# endif
+# define machine_is_var_som_mx6()	(machine_arch_type == MACH_TYPE_VAR_SOM_MX6)
+#else
+# define machine_is_var_som_mx6()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCAAXS1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCAAXS1
+# endif
+# define machine_is_pcaaxs1()	(machine_arch_type == MACH_TYPE_PCAAXS1)
+#else
+# define machine_is_pcaaxs1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PFLA03
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PFLA03
+# endif
+# define machine_is_pfla03()	(machine_arch_type == MACH_TYPE_PFLA03)
+#else
+# define machine_is_pfla03()	(0)
+#endif
+
+/*
+ * These have not yet been registered
+ */
+
+#ifndef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 52114d0c4e..765b089beb 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -1,19 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_MEMORY_H
 #define __ASM_ARM_MEMORY_H
 
+#include <linux/sizes.h>
+
+#ifndef __ASSEMBLY__
 #include <memory.h>
 
 #include <linux/const.h>
-/*
- * Allow for constants defined here to be used from assembly code
- * by prepending the UL suffix only with actual C code compilation.
- */
-#define UL(x) _AC(x, UL)
 
-static inline void arm_add_mem_device(const char* name, resource_size_t start,
-				    resource_size_t size)
+static inline int arm_add_mem_device(const char* name, resource_size_t start,
+				     resource_size_t size)
 {
-	barebox_add_memory_bank(name, start, size);
+	return barebox_add_memory_bank(name, start, size);
 }
 
+#endif
+
+
+/*
+ * Alignment of barebox PBL segments (e.g. .text, .data).
+ *
+ *  4  B granule:  Same flat rwx mapping for everything
+ *  4 KB granule:  16 level 3 entries, with contiguous bit
+ * 16 KB granule:   4 level 3 entries, without contiguous bit
+ * 64 KB granule:   1 level 3 entry
+ */
+#ifdef CONFIG_EFI_PAYLOAD
+#define PBL_SEGMENT_ALIGN		SZ_64K
+#else
+#define PBL_SEGMENT_ALIGN		4
+#endif
+
 #endif	/* __ASM_ARM_MEMORY_H */
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 417808bfcc..ebf1e096c6 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_MMU_H
 #define __ASM_MMU_H
 
@@ -21,7 +23,7 @@ static inline void setup_dma_coherent(unsigned long offset)
 #ifdef CONFIG_MMU
 #define ARCH_HAS_REMAP
 #define MAP_ARCH_DEFAULT MAP_CACHED
-int arch_remap_range(void *_start, size_t size, unsigned flags);
+int arch_remap_range(void *virt_addr, phys_addr_t phys_addr, size_t size, unsigned flags);
 void *map_io_sections(unsigned long physaddr, void *start, size_t size);
 #else
 #define MAP_ARCH_DEFAULT MAP_UNCACHED
@@ -48,14 +50,21 @@ struct outer_cache_fns {
 	void (*disable)(void);
 };
 
+#ifdef __PBL__
+/* Existing platforms with non-architected outer cache initialize it
+ * outside PBL and new ones will likely only have architected caches,
+ * so we provide a dummy here
+ */
+static __maybe_unused struct outer_cache_fns outer_cache;
+#else
 extern struct outer_cache_fns outer_cache;
+#endif
 
 void __dma_clean_range(unsigned long, unsigned long);
 void __dma_flush_range(unsigned long, unsigned long);
 void __dma_inv_range(unsigned long, unsigned long);
 
-void mmu_early_enable(unsigned long membase, unsigned long memsize,
-		      unsigned long ttb);
+void mmu_early_enable(unsigned long membase, unsigned long memsize);
 void mmu_early_disable(void);
 
 #endif /* __ASM_MMU_H */
diff --git a/arch/arm/include/asm/mmuinfo.h b/arch/arm/include/asm/mmuinfo.h
new file mode 100644
index 0000000000..3005c388b9
--- /dev/null
+++ b/arch/arm/include/asm/mmuinfo.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ARM_ASM_MMUINFO_H__
+#define __ARM_ASM_MMUINFO_H__
+
+int mmuinfo_v7(void *addr);
+int mmuinfo_v8(void *addr);
+
+#endif
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index 3ce39bf82b..a4473ff8b6 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef _ASM_ARM_MODULE_H
 #define _ASM_ARM_MODULE_H
 
diff --git a/arch/arm/include/asm/neon.h b/arch/arm/include/asm/neon.h
new file mode 100644
index 0000000000..476462e83e
--- /dev/null
+++ b/arch/arm/include/asm/neon.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ARM_ASM_NEON_H__
+#define __ARM_ASM_NEON_H__
+
+#define kernel_neon_begin()	((void)0)
+#define kernel_neon_end()	((void)0)
+
+#endif
diff --git a/arch/arm/include/asm/opcodes-sec.h b/arch/arm/include/asm/opcodes-sec.h
new file mode 100644
index 0000000000..b6f4b35024
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-sec.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+
+#ifndef __ASM_ARM_OPCODES_SEC_H
+#define __ASM_ARM_OPCODES_SEC_H
+
+#include <asm/opcodes.h>
+
+#define __SMC(imm4) __inst_arm_thumb32(					\
+	0xE1600070 | (((imm4) & 0xF) << 0),				\
+	0xF7F08000 | (((imm4) & 0xF) << 16)				\
+)
+
+#endif /* __ASM_ARM_OPCODES_SEC_H */
diff --git a/arch/arm/include/asm/optee.h b/arch/arm/include/asm/optee.h
new file mode 100644
index 0000000000..f8eb7b4a8b
--- /dev/null
+++ b/arch/arm/include/asm/optee.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ARM_OPTEE_H__
+#define __ARM_OPTEE_H__
+
+#include <linux/types.h>
+
+struct device_node;
+
+struct of_optee_fixup_data {
+	const char *method;
+	size_t shm_size;
+};
+
+int of_optee_fixup(struct device_node *root, void *fixup_data);
+
+#endif /* __ARM_OPTEE_H__ */
+
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index d7419cabe7..7c834f1101 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -2,6 +2,8 @@
 #ifndef __ASM_PCI_H
 #define __ASM_PCI_H
 
-#define pcibios_assign_all_busses()	1
+#include <efi/efi-mode.h>
+
+#define pcibios_assign_all_busses()	(!efi_is_payload())
 
 #endif
diff --git a/arch/arm/include/asm/pgtable64.h b/arch/arm/include/asm/pgtable64.h
index dbec61753b..b88ffe6be5 100644
--- a/arch/arm/include/asm/pgtable64.h
+++ b/arch/arm/include/asm/pgtable64.h
@@ -4,12 +4,11 @@
 #ifndef __ASM_PGTABLE64_H
 #define __ASM_PGTABLE64_H
 
-#define UL(x)		_AC(x, UL)
-
 #define UNUSED_DESC                0x6EbAAD0BBADbA6E0
 
 #define VA_START                   0x0
 #define BITS_PER_VA                48
+#define BITS_PER_PA                40 // Use 40 Physical address bits
 
 /* Granule size of 4KB is being used */
 #define GRANULE_SIZE_SHIFT         12
diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h
index 22cae6230c..feaed42471 100644
--- a/arch/arm/include/asm/posix_types.h
+++ b/arch/arm/include/asm/posix_types.h
@@ -1 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <asm-generic/posix_types.h>
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 3c1d046eb9..b342eb85f5 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -6,6 +6,8 @@
 #ifndef __ARM_PSCI_H__
 #define __ARM_PSCI_H__
 
+struct device_node;
+
 #define ARM_PSCI_VER(major, minor)	(((major) << 16) | (minor))
 #define ARM_PSCI_VER_1_0		ARM_PSCI_VER(1,0)
 #define ARM_PSCI_VER_0_2		ARM_PSCI_VER(0,2)
@@ -144,6 +146,7 @@ static inline int psci_printf(const char *fmt, ...)
 
 int psci_get_cpu_id(void);
 
-int of_psci_fixup(struct device_node *root, unsigned long psci_version);
+int of_psci_fixup(struct device_node *root, unsigned long psci_version,
+		  const char *method);
 
 #endif /* __ARM_PSCI_H__ */
diff --git a/arch/arm/include/asm/reloc.h b/arch/arm/include/asm/reloc.h
new file mode 100644
index 0000000000..95b4ef0af8
--- /dev/null
+++ b/arch/arm/include/asm/reloc.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _ASM_RELOC_H_
+#define _ASM_RELOC_H_
+
+#include <asm/sections.h>
+
+unsigned long get_runtime_offset(void);
+
+/* global_variable_offset() - Access global variables when not running at link address
+ *
+ * Get the offset of global variables when not running at the address we are
+ * linked at.
+ */
+static inline __prereloc unsigned long global_variable_offset(void)
+{
+#ifdef CONFIG_CPU_V8
+	unsigned long text;
+
+	__asm__ __volatile__(
+		"adr    %0, _text\n"
+		: "=r" (text)
+		:
+		: "memory");
+	return text - (unsigned long)_text;
+#else
+	return get_runtime_offset();
+#endif
+}
+#define global_variable_offset() global_variable_offset()
+
+void relocate_to_current_adr(void);
+void relocate_to_adr(unsigned long target);
+void relocate_to_adr_full(unsigned long target);
+
+void pbl_barebox_break(void);
+
+void setup_c(void);
+
+#include <asm-generic/reloc.h>
+
+#endif
diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h
index 8ab01f2b71..15b1a6482a 100644
--- a/arch/arm/include/asm/sections.h
+++ b/arch/arm/include/asm/sections.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_SECTIONS_H
 #define __ASM_SECTIONS_H
 
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index e0c2623723..fd10c47c6a 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_SECURE_H
 #define __ASM_ARM_SECURE_H
 
diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h
index b478dadb3a..9e1606c4ae 100644
--- a/arch/arm/include/asm/semihosting.h
+++ b/arch/arm/include/asm/semihosting.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_SEMIHOSTING_H
 #define __ASM_ARM_SEMIHOSTING_H
 
diff --git a/arch/arm/include/asm/stacktrace.h b/arch/arm/include/asm/stacktrace.h
index 602e79ced4..bbcd2a5f8e 100644
--- a/arch/arm/include/asm/stacktrace.h
+++ b/arch/arm/include/asm/stacktrace.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_STACKTRACE_H
 #define __ASM_STACKTRACE_H
 
diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h
index cd79f63402..2322b846b2 100644
--- a/arch/arm/include/asm/string.h
+++ b/arch/arm/include/asm/string.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_STRING_H
 #define __ASM_ARM_STRING_H
 
diff --git a/arch/arm/include/asm/swab.h b/arch/arm/include/asm/swab.h
index 3795437831..8dbde9b307 100644
--- a/arch/arm/include/asm/swab.h
+++ b/arch/arm/include/asm/swab.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 /*
  *  arch/arm/include/asm/byteorder.h
  *
diff --git a/arch/arm/include/asm/syscounter.h b/arch/arm/include/asm/syscounter.h
index a644cfaad6..16d52269e3 100644
--- a/arch/arm/include/asm/syscounter.h
+++ b/arch/arm/include/asm/syscounter.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef _ASM_SYSCNT_H_
 #define _ASM_SYSCNT_H_
 
@@ -21,4 +23,4 @@ static inline u32 syscnt_get_cntfrq(void __iomem *syscnt)
 	return readl(syscnt + SYSCNT_CNTFID(0));
 }
 
-#endif
\ No newline at end of file
+#endif
diff --git a/arch/arm/include/asm/sysreg.h b/arch/arm/include/asm/sysreg.h
new file mode 100644
index 0000000000..7d567e08d8
--- /dev/null
+++ b/arch/arm/include/asm/sysreg.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Macros for accessing system registers with older binutils.
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas@arm.com>
+ */
+
+#ifndef __ASM_SYSREG_H
+#define __ASM_SYSREG_H
+
+#include <asm/system.h>
+#include <linux/stringify.h>
+
+/*
+ * Unlike read_cpuid, calls to read_sysreg are never expected to be
+ * optimized away or replaced with synthetic values.
+ */
+#define read_sysreg(r) ({					\
+	u64 __val;						\
+	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
+	__val;							\
+})
+
+/*
+ * The "Z" constraint normally means a zero immediate, but when combined with
+ * the "%x0" template means XZR.
+ */
+#define write_sysreg(v, r) do {					\
+	u64 __val = (u64)(v);					\
+	asm volatile("msr " __stringify(r) ", %x0"		\
+		     : : "rZ" (__val));				\
+} while (0)
+
+/*
+ * For registers without architectural names, or simply unsupported by
+ * GAS.
+ */
+#define read_sysreg_s(r) ({						\
+	u64 __val;							\
+	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
+	__val;								\
+})
+
+#define write_sysreg_s(v, r) do {					\
+	u64 __val = (u64)(v);						\
+	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
+} while (0)
+
+/*
+ * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
+ * set mask are set. Other bits are left as-is.
+ */
+#define sysreg_clear_set(sysreg, clear, set) do {			\
+	u64 __scs_val = read_sysreg(sysreg);				\
+	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
+	if (__scs_new != __scs_val)					\
+		write_sysreg(__scs_new, sysreg);			\
+} while (0)
+
+#define sysreg_clear_set_s(sysreg, clear, set) do {			\
+	u64 __scs_val = read_sysreg_s(sysreg);				\
+	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
+	if (__scs_new != __scs_val)					\
+		write_sysreg_s(__scs_new, sysreg);			\
+} while (0)
+
+#define read_sysreg_par() ({						\
+	u64 par;							\
+	asm("dmb sy");							\
+	par = read_sysreg(par_el1);					\
+	asm("dmb sy");							\
+	par;								\
+})
+
+#endif	/* __ASM_SYSREG_H */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index a0180f2df8..bf3b7b02e2 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_SYSTEM_H
 #define __ASM_ARM_SYSTEM_H
 
@@ -23,12 +25,8 @@
 
 #if __LINUX_ARM_ARCH__ >= 7
 #define isb() __asm__ __volatile__ ("isb" : : : "memory")
-#ifdef CONFIG_CPU_64v8
 #define dsb() __asm__ __volatile__ ("dsb sy" : : : "memory")
-#else
-#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
-#endif
-#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+#define dmb() __asm__ __volatile__ ("dmb sy" : : : "memory")
 #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
                                     : : "r" (0) : "memory")
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index 1e3dfc845c..5a84fde75b 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_SYSTEM_INFO_H
 #define __ASM_ARM_SYSTEM_INFO_H
 
@@ -42,6 +44,12 @@
 #define CPU_IS_CORTEX_A15	0x410fc0f0
 #define CPU_IS_CORTEX_A15_MASK	0xff0ffff0
 
+#define CPU_IS_CORTEX_A53	0x410fd030
+#define CPU_IS_CORTEX_A53_MASK	0xff0ffff0
+
+#define CPU_IS_CORTEX_A72	0x410fd080
+#define CPU_IS_CORTEX_A72_MASK	0xff0ffff0
+
 #define CPU_IS_PXA250		0x69052100
 #define CPU_IS_PXA250_MASK	0xfffff7f0
 
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index 22b9642655..4adc815bf3 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef __ASM_ARM_TYPES_H
 #define __ASM_ARM_TYPES_H
 
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
index 44593a8949..b63d39da7f 100644
--- a/arch/arm/include/asm/unaligned.h
+++ b/arch/arm/include/asm/unaligned.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #ifndef _ASM_ARM_UNALIGNED_H
 #define _ASM_ARM_UNALIGNED_H
 
diff --git a/arch/arm/include/asm/unwind.h b/arch/arm/include/asm/unwind.h
index 319527ec9b..37aba2aa4c 100644
--- a/arch/arm/include/asm/unwind.h
+++ b/arch/arm/include/asm/unwind.h
@@ -16,14 +16,15 @@ enum unwind_reason_code {
 };
 
 struct unwind_idx {
-	unsigned long addr;
+	unsigned long addr_offset;
 	unsigned long insn;
 };
 
 struct unwind_table {
 	struct list_head list;
-	struct unwind_idx *start;
-	struct unwind_idx *stop;
+	const struct unwind_idx *start;
+	const struct unwind_idx *origin;
+	const struct unwind_idx *stop;
 	unsigned long begin_addr;
 	unsigned long end_addr;
 };
diff --git a/arch/arm/include/asm/word-at-a-time.h b/arch/arm/include/asm/word-at-a-time.h
new file mode 100644
index 0000000000..a2b20be13d
--- /dev/null
+++ b/arch/arm/include/asm/word-at-a-time.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 ARM Ltd.
+ */
+#ifndef __ASM_WORD_AT_A_TIME_H
+#define __ASM_WORD_AT_A_TIME_H
+
+#if !defined(__AARCH64EB__) && !defined(__ARMEB__)
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+
+struct word_at_a_time {
+	const unsigned long one_bits, high_bits;
+};
+
+#define WORD_AT_A_TIME_CONSTANTS { REPEAT_BYTE(0x01), REPEAT_BYTE(0x80) }
+
+static inline unsigned long has_zero(unsigned long a, unsigned long *bits,
+				     const struct word_at_a_time *c)
+{
+	unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits;
+	*bits = mask;
+	return mask;
+}
+
+#define prep_zero_mask(a, bits, c) (bits)
+
+static inline unsigned long create_zero_mask(unsigned long bits)
+{
+	bits = (bits - 1) & ~bits;
+	return bits >> 7;
+}
+
+static inline unsigned long find_zero(unsigned long mask)
+{
+	unsigned long ret;
+
+#if __LINUX_ARM_ARCH__ >= 8
+	ret = fls64(mask) >> 3;
+#elif __LINUX_ARM_ARCH__ >= 5
+	/* We have clz available. */
+	ret = fls(mask) >> 3;
+#else
+	/* (000000 0000ff 00ffff ffffff) -> ( 1 1 2 3 ) */
+	ret = (0x0ff0001 + mask) >> 23;
+	/* Fix the 1 for 00 case */
+	ret &= mask;
+#endif
+
+	return ret;
+}
+
+#define zero_bytemask(mask) (mask)
+
+#else	/* __AARCH64EB__ || __ARMEB__ */
+#include <asm-generic/word-at-a-time.h>
+#endif
+
+#endif /* __ASM_WORD_AT_A_TIME_H */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
deleted file mode 100644
index 33db7350f8..0000000000
--- a/arch/arm/lib/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-$(CONFIG_BOOTM)	+= bootm.o
-obj-$(CONFIG_CMD_BOOTU)	+= bootu.o
diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S
index 0a0fb8b5ac..ec7296f0fb 100644
--- a/arch/arm/lib/pbl.lds.S
+++ b/arch/arm/lib/pbl.lds.S
@@ -2,8 +2,28 @@
 /* SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */
 
 #include <linux/sizes.h>
-#include <asm-generic/barebox.lds.h>
+#include <asm/barebox.lds.h>
+#include <asm/memory.h>
 #include <asm-generic/memory_layout.h>
+#include <asm-generic/pointer.h>
+#include <asm/memory.h>
+
+/*
+ * The size of the PE/COFF section that covers the barebox image, which
+ * runs from _stext to _edata, must be a round multiple of the PE/COFF
+ * FileAlignment, which we set to its minimum value of 0x200. '_stext'
+ * itself must be 4 KB aligned, because that's what the adrp instructions
+ * expects, so padding out _edata to a 0x200 aligned boundary should be
+ * sufficient.
+ */
+PECOFF_FILE_ALIGNMENT = 0x200;
+
+#ifdef CONFIG_EFI_STUB
+#define PECOFF_EDATA_PADDING   \
+       .pecoff_edata_padding : { BYTE(0); . = ALIGN(PECOFF_FILE_ALIGNMENT); }
+#else
+#define PECOFF_EDATA_PADDING
+#endif
 
 #ifdef CONFIG_PBL_RELOCATABLE
 #define BASE	0x0
@@ -11,13 +31,15 @@
 #define BASE	(TEXT_BASE - SZ_2M)
 #endif
 
-#ifdef CONFIG_CPU_32
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
+#ifdef CONFIG_HABV4_QSPI
+#define HAB_CSF_LEN	0x4000
 #else
-OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
-OUTPUT_ARCH(aarch64)
+#define HAB_CSF_LEN	0x2000
 #endif
+
+OUTPUT_FORMAT(BAREBOX_OUTPUT_FORMAT)
+OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH)
+
 SECTIONS
 {
 	. = BASE;
@@ -31,6 +53,7 @@ SECTIONS
 	.text      :
 	{
 		_stext = .;
+		*(.text_head_prologue*)
 		*(.text_head_entry*)
 		__bare_init_start = .;
 		*(.text_bare_init*)
@@ -47,9 +70,20 @@ SECTIONS
 	. = ALIGN(4);
 	.rodata : { *(.rodata*) }
 
+	. = ALIGN(ASM_SZPTR);
+	__pbl_board_stack_top = .;
+	.rodata.pbl_board_stack_top : {
+		*(.pbl_board_stack_top_*)
+		/* Dummy for when BootROM sets up usable stack */
+		ASM_LD_PTR(0x00000000)
+	}
+	ASSERT(. - __pbl_board_stack_top <= 2 * ASM_SZPTR, "Only One PBL per Image allowed")
+
 	.barebox_imd : { BAREBOX_IMD }
 
+	. = ALIGN(PBL_SEGMENT_ALIGN);
 	_etext = .;			/* End of text and rodata section */
+	_sdata = .;
 
 	. = ALIGN(4);
 	.data : { *(.data*) }
@@ -61,17 +95,7 @@ SECTIONS
 	}
 	__shasum_end = .;
 
-	.rel_dyn_start : { *(.__rel_dyn_start) }
-#ifdef CONFIG_CPU_32
-	.rel.dyn : { *(.rel*) }
-#else
-	.rela.dyn : { *(.rela*) }
-#endif
-	.rel_dyn_end : { *(.__rel_dyn_end) }
-
-	.__dynsym_start :  { *(.__dynsym_start) }
-	.dynsym : { *(.dynsym) }
-	.__dynsym_end : { *(.__dynsym_end) }
+	BAREBOX_RELOCATION_TABLE
 
 	pbl_code_size =  . - BASE;
 
@@ -88,7 +112,7 @@ SECTIONS
 	__csf_start = .;
 	.hab_csf : {
 		BYTE(0x5a);
-		. += + 0x1fff;
+		. += + HAB_CSF_LEN - 1;
 	} = 0x5a
 	__csf_end = .;
 #endif /* CONFIG_CPU_64 && CONFIG_HABV4 */
@@ -98,7 +122,23 @@ SECTIONS
 	.piggydata : {
 		*(.piggydata)
 	}
-	__piggydata_end = .;
+
+	. = ALIGN(4);
+	__pblext_start = .;
+	.pblext : {
+		*(.pblext.*)
+	}
+	__pblext_end = .;
+
+	PECOFF_EDATA_PADDING
+
+	__pecoff_data_rawsize = ABSOLUTE(. - _etext);
+
+	/* .bss is dwarfed by piggydata size, so we just handle .bss
+	 * as normal PE data
+	 */
+
+	__pecoff_data_size = ABSOLUTE(. - _etext);
 
 	.image_end : { KEEP(*(.__image_end)) }
 
diff --git a/arch/arm/lib32/.gitignore b/arch/arm/lib32/.gitignore
index d1165788c9..03987a7009 100644
--- a/arch/arm/lib32/.gitignore
+++ b/arch/arm/lib32/.gitignore
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 barebox.lds
diff --git a/arch/arm/lib32/Makefile b/arch/arm/lib32/Makefile
index ec6a3aea67..d54fb7644c 100644
--- a/arch/arm/lib32/Makefile
+++ b/arch/arm/lib32/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-$(CONFIG_ARM_LINUX)	+= armlinux.o
 obj-$(CONFIG_CMD_BOOTZ)	+= bootz.o
 obj-$(CONFIG_BOOTM)     += bootm.o
@@ -29,6 +31,8 @@ extra-y += barebox.lds
 pbl-y	+= lib1funcs.o
 pbl-y	+= ashldi3.o
 pbl-y	+= div0.o
+pbl-$(CONFIG_CPU_32v7)	+= arm_architected_timer.o
+CFLAGS_arm_architected_timer.o := -march=armv7-a
 
 obj-pbl-y	+= setjmp.o
 
diff --git a/arch/arm/lib32/arm_architected_timer.c b/arch/arm/lib32/arm_architected_timer.c
new file mode 100644
index 0000000000..54eca13f8b
--- /dev/null
+++ b/arch/arm/lib32/arm_architected_timer.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <asm/system.h>
+#include <clock.h>
+#include <common.h>
+
+/* Unlike the ARMv8, the timer is not generic to ARM32 */
+void arm_architected_timer_udelay(unsigned long us)
+{
+	unsigned long long ticks, cntfrq = get_cntfrq();
+	unsigned long long start = get_cntpct();
+
+	ticks = DIV_ROUND_DOWN_ULL((us * cntfrq), 1000000);
+
+	while ((long)(start + ticks - get_cntpct()) > 0)
+		;
+}
diff --git a/arch/arm/lib32/armlinux.c b/arch/arm/lib32/armlinux.c
index 6cb7d4b5f3..eb30f4a952 100644
--- a/arch/arm/lib32/armlinux.c
+++ b/arch/arm/lib32/armlinux.c
@@ -18,6 +18,7 @@
 #include <memory.h>
 #include <of.h>
 #include <magicvar.h>
+#include <zero_page.h>
 
 #include <asm/byteorder.h>
 #include <asm/setup.h>
@@ -265,8 +266,12 @@ void start_linux(void *adr, int swap, unsigned long initrd_address,
 		pr_debug("booting kernel with devicetree\n");
 		params = oftree;
 	} else {
-		setup_tags(initrd_address, initrd_size, swap);
 		params = armlinux_get_bootparams();
+
+		if ((unsigned long)params < PAGE_SIZE)
+			zero_page_access();
+
+		setup_tags(initrd_address, initrd_size, swap);
 	}
 	architecture = armlinux_get_architecture();
 
diff --git a/arch/arm/lib32/barebox.lds.S b/arch/arm/lib32/barebox.lds.S
index 77a5c525c5..ec145569be 100644
--- a/arch/arm/lib32/barebox.lds.S
+++ b/arch/arm/lib32/barebox.lds.S
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 /* SPDX-FileCopyrightText: 2000-2004 Wolfgang Denk <wd@denx.de>, DENX Software Engineering */
 
-#include <asm-generic/barebox.lds.h>
+#include <asm/barebox.lds.h>
 #include <asm/secure.h>
 
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
+OUTPUT_FORMAT(BAREBOX_OUTPUT_FORMAT)
+OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH)
 ENTRY(start)
 SECTIONS
 {
@@ -71,13 +71,7 @@ SECTIONS
 
 	. = .;
 
-	.rel_dyn_start : { *(.__rel_dyn_start) }
-	.rel.dyn : { *(.rel*) }
-	.rel_dyn_end : { *(.__rel_dyn_end) }
-
-	.__dynsym_start :  { *(.__dynsym_start) }
-	.dynsym : { *(.dynsym) }
-	.__dynsym_end : { *(.__dynsym_end) }
+	BAREBOX_RELOCATION_TABLE
 
 	_edata = .;
 	.image_end : { *(.__image_end) }
diff --git a/arch/arm/lib32/bootm.c b/arch/arm/lib32/bootm.c
index 28a645a9d0..e814593dce 100644
--- a/arch/arm/lib32/bootm.c
+++ b/arch/arm/lib32/bootm.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <bootm.h>
 #include <boot.h>
 #include <common.h>
@@ -325,6 +327,10 @@ static int __do_bootm_linux(struct image_data *data, unsigned long free_mem,
 	if (data->dryrun)
 		return 0;
 
+	ret = of_overlay_load_firmware();
+	if (ret)
+		return ret;
+
 	if (data->tee_res)
 		tee = (void *)data->tee_res->start;
 	else
@@ -421,7 +427,7 @@ static int do_bootz_linux_fdt(int fd, struct image_data *data, void **outfdt)
 	if (IS_BUILTIN(CONFIG_OFTREE)) {
 		struct device_node *root;
 
-		root = of_unflatten_dtb(oftree);
+		root = of_unflatten_dtb(oftree, header->totalsize);
 		if (IS_ERR(root)) {
 			pr_err("unable to unflatten devicetree\n");
 			goto err_free;
diff --git a/arch/arm/lib32/bootu.c b/arch/arm/lib32/bootu.c
index 24c744da58..31c3c56cc5 100644
--- a/arch/arm/lib32/bootu.c
+++ b/arch/arm/lib32/bootu.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <command.h>
 #include <fs.h>
@@ -8,7 +10,7 @@
 
 static int do_bootu(int argc, char *argv[])
 {
-	int fd;
+	int fd, ret;
 	void *kernel = NULL;
 	void *oftree = NULL;
 
@@ -25,6 +27,9 @@ static int do_bootu(int argc, char *argv[])
 #ifdef CONFIG_OFTREE
 	oftree = of_get_fixed_tree(NULL);
 #endif
+	ret = of_overlay_load_firmware();
+	if (ret)
+		return ret;
 
 	start_linux(kernel, 0, 0, 0, oftree, ARM_STATE_SECURE, NULL);
 
diff --git a/arch/arm/lib32/bootz.c b/arch/arm/lib32/bootz.c
index a2a26ac2f9..7b3b32d418 100644
--- a/arch/arm/lib32/bootz.c
+++ b/arch/arm/lib32/bootz.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <command.h>
 #include <fs.h>
@@ -111,6 +113,9 @@ static int do_bootz(int argc, char *argv[])
 #ifdef CONFIG_OFTREE
 	oftree = of_get_fixed_tree(NULL);
 #endif
+	ret = of_overlay_load_firmware();
+	if (ret)
+		return ret;
 
 	start_linux(zimage, swap, 0, 0, oftree, ARM_STATE_SECURE, NULL);
 
diff --git a/arch/arm/lib32/io.c b/arch/arm/lib32/io.c
index abfd887aac..780b1083a6 100644
--- a/arch/arm/lib32/io.c
+++ b/arch/arm/lib32/io.c
@@ -1,47 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <module.h>
 #include <linux/types.h>
+#include <asm/unaligned.h>
 #include <io.h>
 
 /*
  * Copy data from IO memory space to "real" memory space.
- * This needs to be optimized.
  */
 void memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
 {
-	unsigned char *t = to;
-	while (count) {
+	while (count && !PTR_IS_ALIGNED(from, 4)) {
+		*(u8 *)to = __raw_readb(from);
+		from++;
+		to++;
 		count--;
-		*t = readb(from);
-		t++;
+	}
+
+	while (count >= 4) {
+		put_unaligned(__raw_readl(from), (u32 *)to);
+		from += 4;
+		to += 4;
+		count -= 4;
+	}
+
+	while (count) {
+		*(u8 *)to = __raw_readb(from);
 		from++;
+		to++;
+		count--;
 	}
 }
 
 /*
  * Copy data from "real" memory space to IO memory space.
- * This needs to be optimized.
  */
 void memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
 {
-	const unsigned char *f = from;
-	while (count) {
+	while (count && !IS_ALIGNED((unsigned long)to, 4)) {
+		__raw_writeb(*(u8 *)from, to);
+		from++;
+		to++;
 		count--;
-		writeb(*f, to);
-		f++;
+	}
+
+	while (count >= 4) {
+		__raw_writel(get_unaligned((u32 *)from), to);
+		from += 4;
+		to += 4;
+		count -= 4;
+	}
+
+	while (count) {
+		__raw_writeb(*(u8 *)from, to);
+		from++;
 		to++;
+		count--;
 	}
 }
 
 /*
  * "memset" on IO memory space.
- * This needs to be optimized.
  */
 void memset_io(volatile void __iomem *dst, int c, size_t count)
 {
-	while (count) {
+	u32 qc = (u8)c;
+
+	qc |= qc << 8;
+	qc |= qc << 16;
+
+	while (count && !PTR_IS_ALIGNED(dst, 4)) {
+		__raw_writeb(c, dst);
+		dst++;
 		count--;
-		writeb(c, dst);
+	}
+
+	while (count >= 4) {
+		__raw_writel(qc, dst);
+		dst += 4;
+		count -= 4;
+	}
+
+	while (count) {
+		__raw_writeb(c, dst);
 		dst++;
+		count--;
 	}
 }
 
diff --git a/arch/arm/lib32/module.c b/arch/arm/lib32/module.c
index 5073675180..7214e3c73c 100644
--- a/arch/arm/lib32/module.c
+++ b/arch/arm/lib32/module.c
@@ -38,7 +38,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 
 		sym = ((Elf32_Sym *)symsec->sh_addr) + offset;
 
-		if (rel->r_offset < 0 || rel->r_offset > dstsec->sh_size - sizeof(u32)) {
+		if (rel->r_offset > dstsec->sh_size - sizeof(u32)) {
 			printf("%s: out of bounds relocation, "
 				"section %u reloc %u offset %d size %d\n",
 				module->name, relindex, i, rel->r_offset,
diff --git a/arch/arm/lib32/optee-early.c b/arch/arm/lib32/optee-early.c
index 197325b8a0..735d829c99 100644
--- a/arch/arm/lib32/optee-early.c
+++ b/arch/arm/lib32/optee-early.c
@@ -9,6 +9,7 @@
 #include <asm/setjmp.h>
 #include <tee/optee.h>
 #include <debug_ll.h>
+#include <string.h>
 
 static jmp_buf tee_buf;
 
diff --git a/arch/arm/lib32/runtime-offset.S b/arch/arm/lib32/runtime-offset.S
index f86ca7865e..ac104de119 100644
--- a/arch/arm/lib32/runtime-offset.S
+++ b/arch/arm/lib32/runtime-offset.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
diff --git a/arch/arm/lib32/setjmp.S b/arch/arm/lib32/setjmp.S
index 626d915da1..cc6cafa4af 100644
--- a/arch/arm/lib32/setjmp.S
+++ b/arch/arm/lib32/setjmp.S
@@ -33,6 +33,7 @@ ENTRY(longjmp)
 1:
 	bx   lr
 ENDPROC(longjmp)
+.popsection
 
 .pushsection .text.initjmp, "ax"
 ENTRY(initjmp)
diff --git a/arch/arm/lib32/start-kernel-optee.S b/arch/arm/lib32/start-kernel-optee.S
index 92da4b63c9..261ab39ba7 100644
--- a/arch/arm/lib32/start-kernel-optee.S
+++ b/arch/arm/lib32/start-kernel-optee.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 
 ENTRY(start_kernel_optee)
diff --git a/arch/arm/lib32/unwind.c b/arch/arm/lib32/unwind.c
index 02fae3c253..c355bba1b7 100644
--- a/arch/arm/lib32/unwind.c
+++ b/arch/arm/lib32/unwind.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <asm/stacktrace.h>
@@ -26,7 +28,7 @@ EXPORT_SYMBOL(__aeabi_unwind_cpp_pr2);
 
 struct unwind_ctrl_block {
 	unsigned long vrs[16];		/* virtual register set */
-	unsigned long *insn;		/* pointer to the current instructions word */
+	const unsigned long *insn;	/* pointer to the current instructions word */
 	int entries;			/* number of entries left to interpret */
 	int byte;			/* current byte number in the instructions word */
 };
@@ -40,8 +42,9 @@ enum regs {
 
 #define THREAD_SIZE               8192
 
-extern struct unwind_idx __start_unwind_idx[];
-extern struct unwind_idx __stop_unwind_idx[];
+extern const struct unwind_idx __start_unwind_idx[];
+static const struct unwind_idx *__origin_unwind_idx;
+extern const struct unwind_idx __stop_unwind_idx[];
 
 /* Convert a prel31 symbol to an absolute address */
 #define prel31_to_addr(ptr)				\
@@ -62,51 +65,106 @@ static void dump_backtrace_entry(unsigned long where, unsigned long from,
 				 unsigned long frame)
 {
 #ifdef CONFIG_KALLSYMS
-	pr_warning("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
+	eprintf("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
 #else
-	pr_warning("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
+	eprintf("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
 #endif
 }
 
 /*
- * Binary search in the unwind index. The entries entries are
+ * Binary search in the unwind index. The entries are
  * guaranteed to be sorted in ascending order by the linker.
+ *
+ * start = first entry
+ * origin = first entry with positive offset (or stop if there is no such entry)
+ * stop - 1 = last entry
  */
-static struct unwind_idx *search_index(unsigned long addr,
-				       struct unwind_idx *first,
-				       struct unwind_idx *last)
+static const struct unwind_idx *search_index(unsigned long addr,
+					const struct unwind_idx *start,
+					const struct unwind_idx *origin,
+					const struct unwind_idx *stop)
 {
-	pr_debug("%s(%08lx, %p, %p)\n", __func__, addr, first, last);
+	unsigned long addr_prel31;
+
+	pr_debug("%s(%08lx, %p, %p, %p)\n",
+			__func__, addr, start, origin, stop);
+
+	/*
+	 * only search in the section with the matching sign. This way the
+	 * prel31 numbers can be compared as unsigned longs.
+	 */
+	if (addr < (unsigned long)start)
+		/* negative offsets: [start; origin) */
+		stop = origin;
+	else
+		/* positive offsets: [origin; stop) */
+		start = origin;
+
+	/* prel31 for address relavive to start */
+	addr_prel31 = (addr - (unsigned long)start) & 0x7fffffff;
+
+	while (start < stop - 1) {
+		const struct unwind_idx *mid = start + ((stop - start) >> 1);
+
+		/*
+		 * As addr_prel31 is relative to start an offset is needed to
+		 * make it relative to mid.
+		 */
+		if (addr_prel31 - ((unsigned long)mid - (unsigned long)start) <
+				mid->addr_offset)
+			stop = mid;
+		else {
+			/* keep addr_prel31 relative to start */
+			addr_prel31 -= ((unsigned long)mid -
+					(unsigned long)start);
+			start = mid;
+		}
+	}
 
-	if (addr < first->addr) {
-		pr_warning("unwind: Unknown symbol address %08lx\n", addr);
+	if (likely(start->addr_offset <= addr_prel31))
+		return start;
+	else {
+		eprintf("unwind: Unknown symbol address %08lx\n", addr);
 		return NULL;
-	} else if (addr >= last->addr)
-		return last;
+	}
+}
 
-	while (first < last - 1) {
-		struct unwind_idx *mid = first + ((last - first + 1) >> 1);
+static const struct unwind_idx *unwind_find_origin(
+		const struct unwind_idx *start, const struct unwind_idx *stop)
+{
+	pr_debug("%s(%p, %p)\n", __func__, start, stop);
+	while (start < stop - 1) {
+		const struct unwind_idx *mid = start + ((stop - start) >> 1);
 
-		if (addr < mid->addr)
-			last = mid;
+		if (mid->addr_offset >= 0x40000000)
+			/* negative offset */
+			start = mid;
 		else
-			first = mid;
+			/* positive offset */
+			stop = mid;
 	}
 
-	return first;
-}
+	pr_debug("%s -> %p\n", __func__, stop);
+	return stop;
+ }
 
-static struct unwind_idx *unwind_find_idx(unsigned long addr)
+static const struct unwind_idx *unwind_find_idx(unsigned long addr)
 {
-	struct unwind_idx *idx = NULL;
+	const struct unwind_idx *idx = NULL;
 
 	pr_debug("%s(%08lx)\n", __func__, addr);
 
-	if (is_kernel_text(addr))
+	if (is_kernel_text(addr)) {
+		if (unlikely(!__origin_unwind_idx))
+			__origin_unwind_idx =
+				unwind_find_origin(__start_unwind_idx,
+						__stop_unwind_idx);
+
 		/* main unwind table */
 		idx = search_index(addr, __start_unwind_idx,
-				   __stop_unwind_idx - 1);
-	else {
+					__origin_unwind_idx,
+					__stop_unwind_idx);
+	} else {
 		/* module unwinding not supported */
 	}
 
@@ -119,7 +177,7 @@ static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl)
 	unsigned long ret;
 
 	if (ctrl->entries <= 0) {
-		pr_warning("unwind: Corrupt unwind table\n");
+		eprintf("unwind: Corrupt unwind table\n");
 		return 0;
 	}
 
@@ -156,7 +214,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 		insn = (insn << 8) | unwind_get_byte(ctrl);
 		mask = insn & 0x0fff;
 		if (mask == 0) {
-			pr_warning("unwind: 'Refuse to unwind' instruction %04lx\n",
+			eprintf("unwind: 'Refuse to unwind' instruction %04lx\n",
 				   insn);
 			return -URC_FAILURE;
 		}
@@ -195,7 +253,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 		int reg = 0;
 
 		if (mask == 0 || mask & 0xf0) {
-			pr_warning("unwind: Spare encoding %04lx\n",
+			eprintf("unwind: Spare encoding %04lx\n",
 			       (insn << 8) | mask);
 			return -URC_FAILURE;
 		}
@@ -213,7 +271,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 
 		ctrl->vrs[SP] += 0x204 + (uleb128 << 2);
 	} else {
-		pr_warning("unwind: Unhandled instruction %02lx\n", insn);
+		eprintf("unwind: Unhandled instruction %02lx\n", insn);
 		return -URC_FAILURE;
 	}
 
@@ -230,7 +288,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 int unwind_frame(struct stackframe *frame)
 {
 	unsigned long high, low;
-	struct unwind_idx *idx;
+	const struct unwind_idx *idx;
 	struct unwind_ctrl_block ctrl;
 
 	/* only go to a higher address on the stack */
@@ -245,7 +303,7 @@ int unwind_frame(struct stackframe *frame)
 
 	idx = unwind_find_idx(frame->pc);
 	if (!idx) {
-		pr_warning("unwind: Index not found %08lx\n", frame->pc);
+		eprintf("unwind: Index not found %08lx\n", frame->pc);
 		return -URC_FAILURE;
 	}
 
@@ -264,7 +322,7 @@ int unwind_frame(struct stackframe *frame)
 		/* only personality routine 0 supported in the index */
 		ctrl.insn = &idx->insn;
 	else {
-		pr_warning("unwind: Unsupported personality routine %08lx in the index at %p\n",
+		eprintf("unwind: Unsupported personality routine %08lx in the index at %p\n",
 			   idx->insn, idx);
 		return -URC_FAILURE;
 	}
@@ -277,7 +335,7 @@ int unwind_frame(struct stackframe *frame)
 		ctrl.byte = 1;
 		ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16);
 	} else {
-		pr_warning("unwind: Unsupported personality routine %08lx at %p\n",
+		eprintf("unwind: Unsupported personality routine %08lx at %p\n",
 			   *ctrl.insn, ctrl.insn);
 		return -URC_FAILURE;
 	}
@@ -340,15 +398,3 @@ void dump_stack(void)
 {
 	unwind_backtrace(NULL);
 }
-
-static int unwind_init(void)
-{
-	struct unwind_idx *idx;
-
-	/* Convert the symbol addresses to absolute values */
-	for (idx = __start_unwind_idx; idx < __stop_unwind_idx; idx++)
-		idx->addr = prel31_to_addr(&idx->addr);
-
-	return 0;
-}
-core_initcall(unwind_init);
diff --git a/arch/arm/lib64/.gitignore b/arch/arm/lib64/.gitignore
index d1165788c9..03987a7009 100644
--- a/arch/arm/lib64/.gitignore
+++ b/arch/arm/lib64/.gitignore
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 barebox.lds
diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile
index 69cb3d8ea1..e86a2e5a2f 100644
--- a/arch/arm/lib64/Makefile
+++ b/arch/arm/lib64/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += stacktrace.o
 obj-$(CONFIG_ARM_LINUX)	+= armlinux.o
 obj-y	+= div0.o
@@ -6,5 +8,5 @@ obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS)	+= memset.o string.o
 extra-y += barebox.lds
 obj-pbl-y   += runtime-offset.o
 obj-pbl-y   += setjmp.o
-
+obj-y += io.o
 pbl-y	+= div0.o pbl.o
diff --git a/arch/arm/lib64/armlinux.c b/arch/arm/lib64/armlinux.c
index 0ba4d30b8e..3b108b21cb 100644
--- a/arch/arm/lib64/armlinux.c
+++ b/arch/arm/lib64/armlinux.c
@@ -5,17 +5,26 @@
 #include <memory.h>
 #include <init.h>
 #include <bootm.h>
+#include <efi/efi-mode.h>
 
 static int do_bootm_linux(struct image_data *data)
 {
 	void (*fn)(unsigned long dtb, unsigned long x1, unsigned long x2,
 		       unsigned long x3);
 	phys_addr_t devicetree;
+	int ret;
 
 	fn = booti_load_image(data, &devicetree);
 	if (IS_ERR(fn))
 		return PTR_ERR(fn);
 
+	if (data->dryrun)
+		return 0;
+
+	ret = of_overlay_load_firmware();
+	if (ret)
+		return ret;
+
 	shutdown_barebox();
 
 	fn(devicetree, 0, 0, 0);
@@ -29,6 +38,12 @@ static struct image_handler aarch64_linux_handler = {
         .filetype = filetype_arm64_linux_image,
 };
 
+static struct image_handler aarch64_linux_efi_handler = {
+        .name = "ARM aarch64 Linux/EFI image",
+        .bootm = do_bootm_linux,
+        .filetype = filetype_arm64_efi_linux_image,
+};
+
 static struct image_handler aarch64_fit_handler = {
 	.name = "FIT image",
 	.bootm = do_bootm_linux,
@@ -47,7 +62,7 @@ static int do_bootm_barebox(struct image_data *data)
 	if (ret)
 		goto out;
 
-	barebox = start;
+	barebox = PAGE_ALIGN(start);
 
 	ret = bootm_load_os(data, barebox);
 	if (ret)
@@ -75,6 +90,10 @@ static struct image_handler aarch64_barebox_handler = {
 
 static int aarch64_register_image_handler(void)
 {
+	if (efi_is_payload())
+		return 0;
+
+	register_image_handler(&aarch64_linux_efi_handler);
 	register_image_handler(&aarch64_linux_handler);
 	register_image_handler(&aarch64_barebox_handler);
 
diff --git a/arch/arm/lib64/barebox.lds.S b/arch/arm/lib64/barebox.lds.S
index 2ebaabef0f..de777ddb54 100644
--- a/arch/arm/lib64/barebox.lds.S
+++ b/arch/arm/lib64/barebox.lds.S
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 /* SPDX-FileCopyrightText: 2000-2004 Wolfgang Denk <wd@denx.de>, DENX Software Engineering */
 
-#include <asm-generic/barebox.lds.h>
+#include <asm/barebox.lds.h>
 
-OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
-OUTPUT_ARCH(aarch64)
+OUTPUT_FORMAT(BAREBOX_OUTPUT_FORMAT)
+OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH)
 ENTRY(start)
 SECTIONS
 {
@@ -49,13 +49,7 @@ SECTIONS
 
 	.barebox_imd : { BAREBOX_IMD }
 
-	.rel_dyn_start : { *(.__rel_dyn_start) }
-	.rela.dyn : { *(.rela*) }
-	.rel_dyn_end : { *(.__rel_dyn_end) }
-
-	.__dynsym_start :  { *(.__dynsym_start) }
-	.dynsym : { *(.dynsym) }
-	.__dynsym_end : { *(.__dynsym_end) }
+	BAREBOX_RELOCATION_TABLE
 
 	_edata = .;
 
diff --git a/arch/arm/lib64/io.c b/arch/arm/lib64/io.c
new file mode 100644
index 0000000000..fdf2117cc8
--- /dev/null
+++ b/arch/arm/lib64/io.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Based on arch/arm/kernel/io.c
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ */
+
+#include <linux/export.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <io.h>
+
+/*
+ * Copy data from IO memory space to "real" memory space.
+ */
+void memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
+{
+	while (count && !IS_ALIGNED((unsigned long)from, 8)) {
+		*(u8 *)to = __raw_readb(from);
+		from++;
+		to++;
+		count--;
+	}
+
+	while (count >= 8) {
+		*(u64 *)to = __raw_readq(from);
+		from += 8;
+		to += 8;
+		count -= 8;
+	}
+
+	while (count) {
+		*(u8 *)to = __raw_readb(from);
+		from++;
+		to++;
+		count--;
+	}
+}
+EXPORT_SYMBOL(memcpy_fromio);
+
+/*
+ * Copy data from "real" memory space to IO memory space.
+ */
+void memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
+{
+	while (count && !IS_ALIGNED((unsigned long)to, 8)) {
+		__raw_writeb(*(u8 *)from, to);
+		from++;
+		to++;
+		count--;
+	}
+
+	while (count >= 8) {
+		__raw_writeq(*(u64 *)from, to);
+		from += 8;
+		to += 8;
+		count -= 8;
+	}
+
+	while (count) {
+		__raw_writeb(*(u8 *)from, to);
+		from++;
+		to++;
+		count--;
+	}
+}
+EXPORT_SYMBOL(memcpy_toio);
+
+/*
+ * "memset" on IO memory space.
+ */
+void memset_io(volatile void __iomem *dst, int c, size_t count)
+{
+	u64 qc = (u8)c;
+
+	qc |= qc << 8;
+	qc |= qc << 16;
+	qc |= qc << 32;
+
+	while (count && !IS_ALIGNED((unsigned long)dst, 8)) {
+		__raw_writeb(c, dst);
+		dst++;
+		count--;
+	}
+
+	while (count >= 8) {
+		__raw_writeq(qc, dst);
+		dst += 8;
+		count -= 8;
+	}
+
+	while (count) {
+		__raw_writeb(c, dst);
+		dst++;
+		count--;
+	}
+}
+EXPORT_SYMBOL(memset_io);
diff --git a/arch/arm/lib64/pbl.c b/arch/arm/lib64/pbl.c
index 0cef08e4d2..78eab33f8d 100644
--- a/arch/arm/lib64/pbl.c
+++ b/arch/arm/lib64/pbl.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <asm/system.h>
 #include <clock.h>
 #include <common.h>
diff --git a/arch/arm/lib64/runtime-offset.S b/arch/arm/lib64/runtime-offset.S
index e2ff5d2103..b10c104b4d 100644
--- a/arch/arm/lib64/runtime-offset.S
+++ b/arch/arm/lib64/runtime-offset.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
@@ -9,10 +11,12 @@
  */
 ENTRY(get_runtime_offset)
 	adr x0, _text
-	ldr x1, linkadr
+	ldr_l x1, linkadr
 	subs x0, x0, x1
 	ret
+ENDPROC(get_runtime_offset)
 
+.section ".data.runtime_offset","a"
 .align 3
 linkadr:
 /*
@@ -22,4 +26,3 @@ linkadr:
  * use _text here since that is 0x0 and is correct without relocation.
  */
 .quad _text
-ENDPROC(get_runtime_offset)
diff --git a/arch/arm/lib64/stacktrace.c b/arch/arm/lib64/stacktrace.c
index db5691a609..76aec734e1 100644
--- a/arch/arm/lib64/stacktrace.c
+++ b/arch/arm/lib64/stacktrace.c
@@ -40,9 +40,9 @@ int unwind_frame(struct stackframe *frame)
 static void dump_backtrace_entry(unsigned long where, unsigned long from)
 {
 #ifdef CONFIG_KALLSYMS
-	printf("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
+	eprintf("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
 #else
-	printf("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
+	eprintf("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
 #endif
 }
 
@@ -60,7 +60,7 @@ void unwind_backtrace(struct pt_regs *regs)
 		frame.pc = (unsigned long)unwind_backtrace;
 	}
 
-	printf("Call trace:\n");
+	eprintf("Call trace:\n");
 	while (1) {
 		unsigned long where = frame.pc;
 		int ret;
diff --git a/arch/arm/lib64/string.c b/arch/arm/lib64/string.c
index a2cf09e58e..938790e1a9 100644
--- a/arch/arm/lib64/string.c
+++ b/arch/arm/lib64/string.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <asm/system.h>
 #include <string.h>
@@ -5,7 +7,7 @@
 void *__arch_memset(void *dst, int c, __kernel_size_t size);
 void *__arch_memcpy(void * dest, const void *src, size_t count);
 
-static void *_memset(void *dst, int c, __kernel_size_t size)
+static __prereloc void *_memset(void *dst, int c, __kernel_size_t size)
 {
 	if (likely(get_cr() & CR_M))
 		return __arch_memset(dst, c, size);
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 28a82c1a93..0e89916c9c 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_AT91
 
 config HAVE_AT91_UTMI
@@ -18,6 +20,10 @@ config MACH_AT91SAM9263EK_DT
 	  Enabled for at91sam9263ek - evaluation kit.
 	  But only if we need the device tree (bootstrap do not use DT)
 
+config HAVE_AT91_LEGACY_CLK
+	def_bool !COMMON_CLK_OF_PROVIDER
+	select HAVE_LEGACY_CLK
+
 config HAVE_AT91_SMD
 	bool
 
@@ -40,14 +46,14 @@ config HAVE_AT91_I2S_MUX_CLK
 config HAVE_AT91_SAM9X60_PLL
 	bool
 
+config HAVE_AT91_SDRAMC
+	bool
+
 config HAVE_AT91_DDRAMC
 	bool
 
 config AT91_MCI_PBL
-	bool
-	depends on MCI_ATMEL_PBL
-	depends on MCI_ATMEL_SDHCI_PBL
-	default y
+	def_bool MCI_ATMEL_PBL || MCI_ATMEL_SDHCI_PBL
 
 # Select if board uses the common at91sam926x_board_init
 config AT91SAM926X_BOARD_INIT
@@ -71,10 +77,17 @@ config SOC_AT91SAM9
 	select HAVE_AT91_UTMI
 	select PINCTRL_AT91
 
+config SOC_SAM_V7
+	select CPU_V7
+	bool
+
 config SOC_SAMA5
 	bool
 	select HAVE_AT91SAM9_RST
-	select CPU_V7
+	select SOC_SAM_V7
+
+config SOC_SAMA5_MULTI
+	def_bool SOC_SAMA5 && AT91_MULTI_BOARDS
 
 config SOC_SAMA5D2
 	bool
@@ -90,7 +103,6 @@ config SOC_SAMA5D2
 	select HAVE_AT91_I2S_MUX_CLK
 	select PINCTRL_AT91PIO4
 	select HAS_MACB
-	select HAVE_MACH_ARM_HEAD
 	select HAVE_AT91_DDRAMC
 
 config SOC_SAMA5D3
@@ -103,7 +115,7 @@ config SOC_SAMA5D3
 	select HAVE_AT91_UTMI
 	select PINCTRL_AT91
 	select HAS_MACB
-	select HAVE_MACH_ARM_HEAD
+	select HAVE_AT91_DDRAMC
 
 config SOC_SAMA5D4
 	bool
@@ -116,7 +128,7 @@ config SOC_SAMA5D4
 	select HAVE_AT91_UTMI
 	select PINCTRL_AT91
 	select HAS_MACB
-	select HAVE_MACH_ARM_HEAD
+	select HAVE_AT91_DDRAMC
 
 config SOC_SAM9X60
 	bool
@@ -126,6 +138,15 @@ config SOC_SAM9X60
 	select HAVE_AT91_SAM9X60_PLL
 	select PINCTRL_AT91
 
+config SOC_SAMA7G5
+	bool
+	select HAVE_AT91_GENERATED_CLK
+	select HAVE_AT91_SAM9X60_PLL
+	select HAVE_AT91_UTMI
+	select SOC_SAM_V7
+	help
+	  Select this if you are using one of Microchip's SAMA7G5 family SoC.
+
 config ARCH_TEXT_BASE
 	hex
 	default 0x73f00000 if SOC_AT91SAM9G45
@@ -157,7 +178,6 @@ config SOC_AT91SAM9260
 	select SOC_AT91SAM9
 	select HAS_MACB
 	select PINCTRL_AT91
-	select HAVE_MACH_ARM_HEAD
 	help
 	  Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
 	  or AT91SAM9G20 SoC.
@@ -167,7 +187,6 @@ config SOC_AT91SAM9261
 	select SOC_AT91SAM9
 	select PINCTRL_AT91
 	select HAVE_AT91_LOAD_BAREBOX_SRAM
-	select HAVE_MACH_ARM_HEAD
 	help
 	  Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
 
@@ -176,7 +195,6 @@ config SOC_AT91SAM9263
 	select SOC_AT91SAM9
 	select HAS_MACB
 	select HAVE_AT91_LOAD_BAREBOX_SRAM
-	select HAVE_MACH_ARM_HEAD
 	select PINCTRL_AT91
 
 config SOC_AT91SAM9G45
@@ -184,7 +202,6 @@ config SOC_AT91SAM9G45
 	select SOC_AT91SAM9
 	select HAS_MACB
 	select PINCTRL_AT91
-	select HAVE_MACH_ARM_HEAD
 	help
 	  Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
 	  This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -207,7 +224,6 @@ config SOC_AT91SAM9N12
 	bool
 	select SOC_AT91SAM9
 	select PINCTRL_AT91
-	select HAVE_MACH_ARM_HEAD
 	help
 	  Select this if you are using Atmel's AT91SAM9N12 SoC.
 
@@ -537,11 +553,6 @@ config MACH_SAMA5D3XEK
 	help
 	  Select this if you are using Atmel's SAMA5D3X-EK Evaluation Kit.
 
-config MACH_SAMA5D3_XPLAINED
-	bool "Atmel SAMA5D3_XPLAINED Evaluation Kit"
-	help
-	  Select this if you are using Atmel's SAMA5D3_XPLAINED Evaluation Kit.
-
 endchoice
 
 endif
@@ -573,19 +584,26 @@ endif
 
 config AT91_MULTI_BOARDS
 	bool "Allow multiple boards to be selected"
-	select HAVE_PBL_MULTI_IMAGES
 	select ARM_USE_COMPRESSED_DTB
 
 if AT91_MULTI_BOARDS
 
+config MACH_CALAO
+	bool "CALAO DT-enabled boards (TNY/USB-A9260/A9G20)"
+	select SOC_AT91SAM9260
+	select OFDEVICE
+	select COMMON_CLK_OF_PROVIDER
+	select HAVE_AT91_SDRAMC
+	help
+	  Select this if you are using a device tree enabled board
+	  from Calao Systems: TNY-A9260, TNY-A9G20, USB-A9260 or USB-A9G20.
+
 config MACH_SKOV_ARM9CPU
 	bool "SKOV ARM9 CPU"
 	select SOC_AT91SAM9263
 	select OFDEVICE
 	select COMMON_CLK_OF_PROVIDER
-	select HAVE_AT91_USB_CLK
-	select HAVE_AT91_BOOTSTRAP
-	select AT91SAM926X_BOARD_INIT
+	select MCI_ATMEL_PBL
 	help
 	  Say y here if you are using SKOV's ARM9 CPU board
 
@@ -616,6 +634,25 @@ config MACH_MICROCHIP_KSZ9477_EVB
 	help
 	  Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
 
+config MACH_MICROCHIP_SAMA5D3_EDS
+	bool "Microchip SAMA5D3 Ethernet Development System"
+	select SOC_SAMA5D3
+	select OFDEVICE
+	select MCI_ATMEL_PBL
+	select COMMON_CLK_OF_PROVIDER
+	help
+	  Select this if you are using Microchip's SAMA5D3 Ethernet Development
+	  System.
+
+config MACH_SAMA5D3_XPLAINED
+	bool "Atmel SAMA5D3_XPLAINED Evaluation Kit"
+	select SOC_SAMA5D3
+	select OFDEVICE
+	select MCI_ATMEL_PBL
+	select COMMON_CLK_OF_PROVIDER
+	help
+	  Select this if you are using Atmel's SAMA5D3_XPLAINED Evaluation Kit.
+
 config MACH_SAMA5D27_SOM1
 	bool "Microchip SAMA5D27 SoM-1 Evaluation Kit"
 	select SOC_SAMA5D2
@@ -634,6 +671,14 @@ config MACH_SAMA5D27_GIANTBOARD
 	help
 	  Select this if you are using the Groboards sama5d27 Giantboard
 
+config MACH_SAMA5D4_WIFX
+	bool "Wifx L1 LoRaWAN base station"
+	select SOC_SAMA5D4
+	select OFDEVICE
+	select COMMON_CLK_OF_PROVIDER
+	help
+	  Select this if you are using the SAMA5D4-based Wifx L1.
+
 endif
 
 comment "AT91 Board Options"
@@ -659,12 +704,6 @@ config AT91_HAVE_2MMC
 	  with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
 	  onwards.
 
-config AT91_HAVE_SRAM_128M
-	bool "Have 128 of ram"
-	depends on MACH_USB_A9G20 || MACH_USB_A9263 || MACH_QIL_A9260 || MACH_QIL_A9G20
-	help
-	  Select this if you board have 128 MiB of Ram (as USB_A9G20 C11)
-
 choice
 	prompt "LCD type"
 	depends on MACH_AT91SAM9M10G45EK
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c895af7a2f..7d7f27749f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,10 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += setup.o aic.o
-lwl-y += at91_pmc_ll.o ddramc_ll.o matrix.o
+lwl-y += at91_pmc_ll.o ddramc_ll.o at91sam9_sdramc_ll.o matrix.o
 lwl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
 
-ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
-obj-y += clock.o
-endif
+obj-$(CONFIG_HAVE_AT91_LEGACY_CLK) += clock.o
 
 obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o
 
@@ -14,20 +14,24 @@ obj-$(CONFIG_BOOTM) += bootm-barebox.o
 obj-y += at91sam9_reset.o
 obj-y += at91sam9g45_reset.o
 obj-pbl-$(CONFIG_HAVE_AT91_DDRAMC) += ddramc.o
+obj-pbl-$(CONFIG_HAVE_AT91_SDRAMC) += sdramc.o
 pbl-$(CONFIG_AT91_MCI_PBL) +=  xload-mmc.o
+pbl-$(CONFIG_AT91_MCI_PBL) +=  at91sam9_xload_mmc.o
 
 obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o
 obj-$(CONFIG_HAVE_AT91SAM9_RST) += at91sam9_rst.o
 
 # CPU-specific support
 obj-$(CONFIG_SOC_AT91RM9200)	+= at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
-obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o
 obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o
 obj-$(CONFIG_SOC_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o
-ifeq ($(CONFIG_OFDEVICE),)
+ifeq ($(CONFIG_AT91_MULTI_BOARDS),)
+obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o
 obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o
 obj-$(CONFIG_SOC_SAMA5D3)	+= sama5d3.o sama5d3_devices.o
+obj-$(CONFIG_SOC_SAMA5D4)	+= sama5d4.o sama5d4_devices.o
 endif
+lwl-$(CONFIG_SOC_AT91SAM9263)	+= sam9263_ll.o
 lwl-$(CONFIG_SOC_SAMA5D2)	+= sama5d2_ll.o
 obj-$(CONFIG_SOC_SAMA5D2)	+= sama5d2.o
 lwl-$(CONFIG_SOC_SAMA5D3)	+= sama5d3_ll.o
@@ -35,4 +39,4 @@ obj-$(CONFIG_SOC_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o
 obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o
 obj-$(CONFIG_SOC_AT91SAM9X5)	+= at91sam9x5.o at91sam9x5_devices.o
 obj-$(CONFIG_SOC_AT91SAM9N12)	+= at91sam9n12.o at91sam9n12_devices.o
-obj-$(CONFIG_SOC_SAMA5D4)	+= sama5d4.o sama5d4_devices.o
+obj-$(CONFIG_SOC_SAMA5_MULTI)	+= sama5_bootsource.o
diff --git a/arch/arm/mach-at91/aic.c b/arch/arm/mach-at91/aic.c
index b40f1d214b..b57fe57361 100644
--- a/arch/arm/mach-at91/aic.c
+++ b/arch/arm/mach-at91/aic.c
@@ -6,7 +6,7 @@
  * this software without specific prior written permission.
  */
 
-#include <mach/aic.h>
+#include <mach/at91/aic.h>
 #include <io.h>
 
 #define SFR_AICREDIR	0x54
diff --git a/arch/arm/mach-at91/at91_pmc_ll.c b/arch/arm/mach-at91/at91_pmc_ll.c
index e561f20755..0101623c8e 100644
--- a/arch/arm/mach-at91/at91_pmc_ll.c
+++ b/arch/arm/mach-at91/at91_pmc_ll.c
@@ -10,10 +10,10 @@
 #define pr_fmt(fmt) "at91pmc: " fmt
 
 #include <common.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_pmc_ll.h>
-#include <mach/early_udelay.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91_pmc_ll.h>
+#include <mach/at91/early_udelay.h>
 
 #define SFR_UTMICKTRIM	0x30	/* UTMI Clock Trimming Register */
 #define AT91_UTMICKTRIM_FREQ	0x03
@@ -157,6 +157,17 @@ void at91_pmc_cfg_plla(void __iomem *pmc_base, u32 pmc_pllar,
 		;
 }
 
+void at91_pmc_cfg_pllb(void __iomem *pmc_base, u32 pmc_pllbr,
+		       unsigned int __always_unused flags)
+{
+	/* Always disable PLL before configuring it */
+	at91_pmc_write(AT91_CKGR_PLLBR, 0);
+	at91_pmc_write(AT91_CKGR_PLLBR, pmc_pllbr);
+
+	while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB))
+		;
+}
+
 void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags)
 {
 	u32 tmp;
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index ba680eb81f..a45bf7cdd3 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -1,8 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <gpio.h>
 #include <init.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
 
 #include "clock.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index b509926d82..8717aefc77 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -7,11 +7,11 @@
 #include <common.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <mach/hardware.h>
-#include <mach/at91rm9200.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
-#include <mach/at91rm9200_mc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91rm9200.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/at91rm9200_mc.h>
 #include <i2c/i2c-gpio.h>
 #include <linux/sizes.h>
 
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index ccbefbbc33..c8394d3d74 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -6,8 +6,8 @@
 #include <init.h>
 #include <clock.h>
 #include <restart.h>
-#include <mach/hardware.h>
-#include <mach/at91rm9200_st.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91rm9200_st.h>
 #include <io.h>
 
 static void __iomem *st = IOMEM(AT91RM9200_BASE_ST);
@@ -35,6 +35,7 @@ static struct clocksource cs = {
 	.mask	= CLOCKSOURCE_MASK(20),
 	.read	= at91rm9200_clocksource_read,
 	.shift	= 10,
+	.priority = 80,
 };
 
 static int clocksource_init (void)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index fdd8ea014e..623c01605f 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -1,11 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <gpio.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_rstc.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 5ebe21c88a..435535a917 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -8,14 +8,14 @@
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9260_matrix.h>
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91_rtt.h>
-#include <mach/iomux.h>
-#include <mach/cpu.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91sam9260_matrix.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91_rtt.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/cpu.h>
 #include <i2c/i2c-gpio.h>
 
 #include "generic.h"
@@ -342,7 +342,7 @@ resource_size_t __init at91_configure_usart5(unsigned pins)
 /* Consider only one slot : slot 0 */
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 {
-	struct device_d *dev;
+	struct device *dev;
 
 	if (!data)
 		return;
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 0465ed9524..df35b7239c 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -1,11 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <gpio.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_rstc.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index dfde848aa3..20446a7077 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -8,14 +8,14 @@
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9261_matrix.h>
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91_rtt.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
-#include <mach/cpu.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91sam9261_matrix.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91_rtt.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/cpu.h>
 #include <i2c/i2c-gpio.h>
 
 #include "generic.h"
@@ -309,7 +309,7 @@ resource_size_t __init at91_configure_usart2(unsigned pins)
 /* Consider only one slot : slot 0 */
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 {
-	struct device_d *dev;
+	struct device *dev;
 
 	if (!data)
 		return;
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index dc5dddfb64..2241e568d4 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -1,11 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <gpio.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/board.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_rstc.h>
 
 #include "clock.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 0adf1ff0cb..1813eee746 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -8,13 +8,13 @@
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9263_matrix.h>
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91_rtt.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91sam9263_matrix.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91_rtt.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
 #include <i2c/i2c-gpio.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9_reset.S b/arch/arm/mach-at91/at91sam9_reset.S
index e50b5e13d5..37d0c8fc5d 100644
--- a/arch/arm/mach-at91/at91sam9_reset.S
+++ b/arch/arm/mach-at91/at91sam9_reset.S
@@ -10,8 +10,8 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/at91_rstc.h>
 
 			.arm
 
diff --git a/arch/arm/mach-at91/at91sam9_rst.c b/arch/arm/mach-at91/at91sam9_rst.c
index a61a26936f..d2c008e343 100644
--- a/arch/arm/mach-at91/at91sam9_rst.c
+++ b/arch/arm/mach-at91/at91sam9_rst.c
@@ -9,7 +9,8 @@
 #include <restart.h>
 #include <linux/bitfield.h>
 #include <linux/clk.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/at91_rstc.h>
+#include <mach/at91/at91sam9260.h>
 #include <reset_source.h>
 
 struct at91sam9x_rst {
@@ -25,7 +26,7 @@ static int reasons[] = {
 	RESET_EXT, /* USER     NRST pin detected low */
 };
 
-static void at91sam9x_set_reset_reason(struct device_d *dev,
+static void at91sam9x_set_reset_reason(struct device *dev,
 				       void __iomem *base)
 {
 	enum reset_src_type type = RESET_UKWN;
@@ -56,7 +57,17 @@ static void __noreturn at91sam9x_restart_soc(struct restart_handler *rst)
 	hang();
 }
 
-static int at91sam9x_rst_probe(struct device_d *dev)
+void __noreturn at91sam9_reset(void __iomem *sdram, void __iomem *rstc_cr);
+
+static void __noreturn at91sam9260_restart_soc(struct restart_handler *rst)
+{
+	struct at91sam9x_rst *priv = container_of(rst, struct at91sam9x_rst, restart);
+
+	at91sam9_reset(IOMEM(AT91SAM9260_BASE_SDRAMC),
+		       IOMEM(priv->base + AT91_RSTC_CR));
+}
+
+static int at91sam9x_rst_probe(struct device *dev)
 {
 	struct at91sam9x_rst *priv;
 	struct resource *iores;
@@ -83,18 +94,20 @@ static int at91sam9x_rst_probe(struct device_d *dev)
 	at91sam9x_set_reset_reason(dev, priv->base);
 
 	priv->restart.name = "at91sam9x-rst";
-	priv->restart.restart = at91sam9x_restart_soc;
+	priv->restart.restart = device_get_match_data(dev);
 
 	return restart_handler_register(&priv->restart);
 }
 
 static const __maybe_unused struct of_device_id at91sam9x_rst_dt_ids[] = {
-	{ .compatible = "atmel,at91sam9g45-rstc", },
-	{ .compatible = "atmel,sama5d3-rstc", },
+	{ .compatible = "atmel,at91sam9260-rstc", at91sam9260_restart_soc },
+	{ .compatible = "atmel,at91sam9g45-rstc", at91sam9x_restart_soc },
+	{ .compatible = "atmel,sama5d3-rstc", at91sam9x_restart_soc },
 	{ /* sentinel */ },
 };
+MODULE_DEVICE_TABLE(of, at91sam9x_rst_dt_ids);
 
-static struct driver_d at91sam9x_rst_driver = {
+static struct driver at91sam9x_rst_driver = {
 	.name		= "at91sam9x-rst",
 	.of_compatible	= DRV_OF_COMPAT(at91sam9x_rst_dt_ids),
 	.probe		= at91sam9x_rst_probe,
diff --git a/arch/arm/mach-at91/at91sam9_sdramc_ll.c b/arch/arm/mach-at91/at91sam9_sdramc_ll.c
new file mode 100644
index 0000000000..5305c94248
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9_sdramc_ll.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#include <mach/at91/at91sam9_sdramc.h>
+#include <mach/at91/early_udelay.h>
+
+static inline void sdramc_wr(const struct at91sam9_sdramc_config *config,
+			     unsigned int offset,
+			     const unsigned int value)
+{
+	writel(value, config->sdramc + offset);
+}
+
+int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
+			       unsigned int sdram_address)
+{
+	unsigned int i;
+
+	/* Step#1 SDRAM feature must be in the configuration register */
+	sdramc_wr(config, AT91_SDRAMC_CR, config->cr);
+
+	/* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */
+
+	/* Step#3 The SDRAM memory type must be set in the Memory Device Register */
+	sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr);
+
+	/* Step#4 The minimum pause of 200 us is provided to precede any single toggle */
+	early_udelay(200);
+
+	/* Step#5 A NOP command is issued to the SDRAM devices */
+	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NOP);
+	writel(0x00000000, sdram_address);
+
+	/* Step#6 An All Banks Precharge command is issued to the SDRAM devices  */
+	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
+	writel(0x00000000, sdram_address);
+
+	/* Pause cycles */
+	early_udelay(2000);
+
+	/* Step#7 Eight auto-refresh cycles are provided */
+	for (i = 0; i < 8; i++) {
+		sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
+		writel(0x00000001 + i, sdram_address + 4 + 4 * i);
+	}
+
+	/* Pause cycles */
+	early_udelay(200);
+
+	/* Step#8 A Mode Register set (MRS) cycle is issued to program (TCSR, PASR, DS) */
+	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
+	writel(0xcafedede, sdram_address + 0x24);
+
+	/*  Pause cycles */
+	early_udelay(200);
+
+	/* Step#9 For mobile SDRAM initialization, an Extended Mode Register set ... */
+
+	/* Step#10 The application must go into Normal Mode, setting Mode to 0
+	 * and perform a write access at any location in the SDRAM.
+	 */
+	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);	// Set mode
+	writel(0x00000000, sdram_address);				// Perform mode
+
+	/* Step#11 Write the refresh rate into the count field in the Refresh Register. */
+	sdramc_wr(config, AT91_SDRAMC_TR, config->tr);
+
+	return 0;
+}
diff --git a/arch/arm/mach-at91/at91sam9_xload_mmc.c b/arch/arm/mach-at91/at91sam9_xload_mmc.c
new file mode 100644
index 0000000000..26f268ae91
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9_xload_mmc.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-FileCopyrightText: 2022 Sam Ravnborg */
+
+#include <debug_ll.h>
+#include <common.h>
+#include <pbl/bio.h>
+
+#include <linux/sizes.h>
+#include <asm/cache.h>
+
+#include <mach/at91/at91_pmc_ll.h>
+#include <mach/at91/at91sam9263.h>
+#include <mach/at91/at91sam926x.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/xload.h>
+#include <mach/at91/gpio.h>
+
+typedef void (*func)(int zero, int arch, void *params);
+
+/*
+ * Load barebox.bin and start executing the first byte in the barebox image.
+ * barebox.bin is loaded to AT91_CHIPSELECT_1.
+ *
+ * To be able to load barebox.bin do a minimal init of the pheriferals
+ * used by MCI.
+ * This functions runs in PBL code and uses the PBL variant of the
+ * atmel_mci driver.
+ */
+void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock,
+					  bool slot_b)
+{
+	void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOA);
+	void *buf = (void *)AT91_CHIPSELECT_1;
+	void __iomem *base;
+	struct pbl_bio bio;
+	int ret;
+
+	at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_PIOA);
+
+	if (mmc_id == 0) {
+		base = IOMEM(AT91SAM9263_BASE_MCI0);
+
+		/* CLK */
+		at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA12), AT91_MUX_PERIPH_A, 0);
+
+		if (!slot_b) {
+			/* CMD */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA1), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+			/* DAT0 to DAT3 */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA0), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA3), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA4), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA5), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+		} else {
+			/* CMD */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA16), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+			/* DAT0 to DAT3 */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA17), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA18), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA19), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA20), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+		}
+
+		at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC),  AT91SAM9263_ID_MCI0);
+	} else {
+		base = IOMEM(AT91SAM9263_BASE_MCI1);
+
+		/* CLK */
+		at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA6), AT91_MUX_PERIPH_A, 0);
+
+		if (!slot_b) {
+			/* CMD */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA7), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+			/* DAT0 to DAT3 */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA8), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA9), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA10), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA11), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+		} else {
+			/* CMD */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA21), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+			/* DAT0 to DAT3 */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA22), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA23), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA24), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA25), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+		}
+
+		at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC),  AT91SAM9263_ID_MCI1);
+	}
+
+	ret = at91_mci_bio_init(&bio, base, clock, (int)slot_b);
+	if (ret) {
+		pr_err("atmci_start_image: bio init faild: %d\n", ret);
+		goto out_panic;
+	}
+
+	/* at91sam9x do not support high capacity */
+	at91_mci_bio_set_highcapacity(false);
+
+	ret = pbl_fat_load(&bio, "barebox.bin", buf, SZ_16M);
+	if (ret < 0) {
+		pr_err("pbl_fat_load: error %d\n", ret);
+		goto out_panic;
+	}
+
+	sync_caches_for_execution();
+
+	((func)buf)(0, 0, NULL);
+
+out_panic:
+	panic("FAT chainloading failed\n");
+}
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index affc624b1d..0d8d399fc5 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -1,12 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <gpio.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/cpu.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_rstc.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index d55ab4f9ea..e74ba8e917 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -8,13 +8,13 @@
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9g45_matrix.h>
-#include <mach/at91_ddrsdrc.h>
-#include <mach/at91_rtt.h>
-#include <mach/board.h>
-#include <mach/iomux.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91sam9g45_matrix.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/at91_rtt.h>
+#include <mach/at91/board.h>
+#include <mach/at91/iomux.h>
 #include <i2c/i2c-gpio.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 67517bf591..4189c4bfd7 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -11,8 +11,8 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/at91_ddrsdrc.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/at91_rstc.h>
 
 			.arm
 
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 850d34604a..e6f4495fc1 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -1,12 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <gpio.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/cpu.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_rstc.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c
index ef432f8758..626b267954 100644
--- a/arch/arm/mach-at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/at91sam9n12_devices.c
@@ -8,13 +8,13 @@
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9n12_matrix.h>
-#include <mach/at91_ddrsdrc.h>
-#include <mach/iomux.h>
-#include <mach/cpu.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91sam9n12_matrix.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/cpu.h>
 #include <i2c/i2c-gpio.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 8266b512c9..0b0fbc6ff3 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -1,9 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/at91sam9x5.h>
-#include <mach/board.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/at91sam9x5.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_rstc.h>
 
 static void at91sam9x5_restart(struct restart_handler *rst)
 {
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index a2c9f3085c..c5dea4e3d7 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -7,13 +7,13 @@
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9x5_matrix.h>
-#include <mach/at91_ddrsdrc.h>
-#include <mach/iomux.h>
-#include <mach/cpu.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91sam9x5_matrix.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/cpu.h>
 #include <i2c/i2c-gpio.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/boot_test_cmd.c b/arch/arm/mach-at91/boot_test_cmd.c
index 7bb40f2e40..9a5c0e3e4e 100644
--- a/arch/arm/mach-at91/boot_test_cmd.c
+++ b/arch/arm/mach-at91/boot_test_cmd.c
@@ -57,7 +57,7 @@ static int do_at91_boot_test(int argc, char *argv[])
 
 	fd = open(sram, O_WRONLY);
 	if (fd < 0) {
-		printf("could not open %s: %s\n", sram, errno_str());
+		printf("could not open %s: %m\n", sram);
 		ret = fd;
 		goto err;
 	}
diff --git a/arch/arm/mach-at91/bootm-barebox.c b/arch/arm/mach-at91/bootm-barebox.c
index 1dccdb86a9..5540b8fad3 100644
--- a/arch/arm/mach-at91/bootm-barebox.c
+++ b/arch/arm/mach-at91/bootm-barebox.c
@@ -1,11 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define pr_fmt(fmt) "at91-bootm-barebox: " fmt
 
 #include <bootm.h>
 #include <common.h>
 #include <init.h>
 #include <memory.h>
-#include <mach/cpu.h>
-#include <mach/sama5_bootsource.h>
+#include <mach/at91/sama5_bootsource.h>
+
+unsigned long at91_bootsource;
+EXPORT_SYMBOL(at91_bootsource);
 
 static int do_bootm_at91_barebox_image(struct image_data *data)
 {
@@ -38,7 +42,7 @@ static struct image_handler image_handler_at91_barebox_image = {
 
 static int at91_register_barebox_image_handler(void)
 {
-	if (!of_machine_is_compatible("atmel,sama5d2"))
+	if (!of_machine_is_compatible("atmel,sama5"))
 	    return 0;
 
 	return register_image_handler(&image_handler_at91_barebox_image);
diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c
index 0b1567cd23..fbf5fa78a1 100644
--- a/arch/arm/mach-at91/bootstrap.c
+++ b/arch/arm/mach-at91/bootstrap.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <bootstrap.h>
-#include <mach/bootstrap.h>
+#include <mach/at91/bootstrap.h>
 #include <linux/sizes.h>
 #include <malloc.h>
 #include <restart.h>
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 8fe0115765..a3071189bb 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -13,10 +13,10 @@
 #include <linux/clk.h>
 #include <init.h>
 
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/cpu.h>
+#include <mach/at91/board.h>
 
 #include "clock.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/ddramc.c b/arch/arm/mach-at91/ddramc.c
index 0aece5345f..4d0637b487 100644
--- a/arch/arm/mach-at91/ddramc.c
+++ b/arch/arm/mach-at91/ddramc.c
@@ -5,11 +5,11 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/ddramc.h>
-#include <mach/hardware.h>
+#include <mach/at91/ddramc.h>
+#include <mach/at91/hardware.h>
 #include <asm/barebox-arm.h>
-#include <mach/at91_ddrsdrc.h>
-#include <mach/sama5_bootsource.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/sama5_bootsource.h>
 #include <asm/memory.h>
 #include <pbl.h>
 #include <io.h>
@@ -33,8 +33,15 @@ void __noreturn sama5d3_barebox_entry(unsigned int r4, void *boarddata)
 	barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(),
 			  boarddata);
 }
+void __noreturn sama5d4_barebox_entry(unsigned int r4, void *boarddata)
+{
+	__sama5d4_stashed_bootrom_r4 = r4;
 
-static int sama5_ddr_probe(struct device_d *dev)
+	barebox_arm_entry(SAMA5_DDRCS, at91sama5d4_get_ddram_size(),
+			  boarddata);
+}
+
+static int sama5_ddr_probe(struct device *dev)
 {
 	struct resource *iores;
 	void __iomem *base;
@@ -44,17 +51,16 @@ static int sama5_ddr_probe(struct device_d *dev)
 		return PTR_ERR(iores);
 	base = IOMEM(iores->start);
 
-	arm_add_mem_device("ram0", SAMA5_DDRCS, sama5_ramsize(base));
-
-	return 0;
+	return arm_add_mem_device("ram0", SAMA5_DDRCS, sama5_ramsize(base));
 }
 
 static struct of_device_id sama5_ddr_dt_ids[] = {
 	{ .compatible = "atmel,sama5d3-ddramc" },
 	{ /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, sama5_ddr_dt_ids);
 
-static struct driver_d sama5_ddr_driver = {
+static struct driver sama5_ddr_driver = {
 	.name   = "sama5-ddramc",
 	.probe  = sama5_ddr_probe,
 	.of_compatible = sama5_ddr_dt_ids,
diff --git a/arch/arm/mach-at91/ddramc_ll.c b/arch/arm/mach-at91/ddramc_ll.c
index 77d03720cc..001d3d7a22 100644
--- a/arch/arm/mach-at91/ddramc_ll.c
+++ b/arch/arm/mach-at91/ddramc_ll.c
@@ -6,9 +6,9 @@
 
 #include <linux/kconfig.h>
 #include <asm/system.h>
-#include <mach/at91_ddrsdrc.h>
-#include <mach/ddramc.h>
-#include <mach/early_udelay.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/ddramc.h>
+#include <mach/at91/early_udelay.h>
 
 void at91_ddram_initialize(void __iomem *base_address,
 			   void __iomem *ram_address,
diff --git a/arch/arm/mach-at91/early_udelay.c b/arch/arm/mach-at91/early_udelay.c
index 632e797beb..c1a22d901a 100644
--- a/arch/arm/mach-at91/early_udelay.c
+++ b/arch/arm/mach-at91/early_udelay.c
@@ -3,11 +3,11 @@
  * Copyright (c) 2012, Atmel Corporation
  */
 
-#include <mach/hardware.h>
+#include <mach/at91/hardware.h>
 #include <asm/io.h>
-#include <mach/at91_pmc_ll.h>
-#include <mach/at91_pit.h>
-#include <mach/early_udelay.h>
+#include <mach/at91/at91_pmc_ll.h>
+#include <mach/at91/at91_pit.h>
+#include <mach/at91/early_udelay.h>
 
 static unsigned int master_clock;
 static void __iomem *pmc, *pit;
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index cdc1b7598a..4ea9779d34 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -13,25 +13,25 @@ static inline int __init at91_clock_init(void) { return 0; }
 extern int __init at91_clock_init(void);
 #endif
 
-static inline struct device_d *at91_add_rm9200_gpio(int id, resource_size_t start)
+static inline struct device *at91_add_rm9200_gpio(int id, resource_size_t start)
 {
 	return add_generic_device("at91rm9200-gpio", id, NULL, start, 512,
 				  IORESOURCE_MEM, NULL);
 }
 
-static inline struct device_d *at91_add_sam9x5_gpio(int id, resource_size_t start)
+static inline struct device *at91_add_sam9x5_gpio(int id, resource_size_t start)
 {
 	return add_generic_device("at91sam9x5-gpio", id, NULL, start, 512,
 				  IORESOURCE_MEM, NULL);
 }
 
-static inline struct device_d *at91_add_pit(resource_size_t start)
+static inline struct device *at91_add_pit(resource_size_t start)
 {
 	return add_generic_device("at91-pit", DEVICE_ID_SINGLE, NULL, start, 16,
 				  IORESOURCE_MEM, NULL);
 }
 
-static inline struct device_d *at91_add_sam9_smc(int id, resource_size_t start,
+static inline struct device *at91_add_sam9_smc(int id, resource_size_t start,
 						 resource_size_t size)
 {
 	return add_generic_device("at91sam9-smc", id, NULL, start, size,
diff --git a/arch/arm/mach-at91/include/mach/aic.h b/arch/arm/mach-at91/include/mach/aic.h
deleted file mode 100644
index c1f026b60c..0000000000
--- a/arch/arm/mach-at91/include/mach/aic.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: BSD-1-Clause */
-#ifndef __AT91_AIC_H_
-#define __AT91_AIC_H_
-
-#include <linux/compiler.h>
-
-void at91_aic_redir(void __iomem *sfr, u32 key);
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
deleted file mode 100644
index f79175c5e9..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */
-/* SPDX-FileCopyrightText: SAN People */
-
-/*
- * arch/arm/mach-at91/include/mach/at91_dbgu.h
- *
- * Debug Unit (DBGU) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E and SAMA5D3 datasheet revision B.
- */
-
-#ifndef AT91_DBGU_H
-#define AT91_DBGU_H
-
-#define AT91_DBGU_CR		(0x00)	/* Control Register */
-#define 	AT91_DBGU_RSTRX		(1 << 2)		/* Reset Receiver */
-#define 	AT91_DBGU_RSTTX		(1 << 3)		/* Reset Transmitter */
-#define 	AT91_DBGU_RXEN		(1 << 4)		/* Receiver Enable */
-#define 	AT91_DBGU_RXDIS		(1 << 5)		/* Receiver Disable */
-#define 	AT91_DBGU_TXEN		(1 << 6)		/* Transmitter Enable */
-#define 	AT91_DBGU_TXDIS		(1 << 7)		/* Transmitter Disable */
-#define 	AT91_DBGU_RSTSTA	(1 << 8)		/* Reset Status Bits */
-#define AT91_DBGU_MR		(0x04)	/* Mode Register */
-#define		AT91_DBGU_NBSTOP_1BIT		(0 << 12) /* 1 stop bit */
-#define		AT91_DBGU_NBSTOP_1_5BIT	(1 << 12) /* 1.5 stop bits */
-#define		AT91_DBGU_NBSTOP_2BIT		(2 << 12) /* 2 stop bits */
-
-#define		AT91_DBGU_CHRL_5BIT	(0 << 6) /* 5 bit character length */
-#define		AT91_DBGU_CHRL_6BIT	(1 << 6) /* 6 bit character length */
-#define		AT91_DBGU_CHRL_7BIT	(2 << 6) /* 7 bit character length */
-#define		AT91_DBGU_CHRL_8BIT	(3 << 6) /* 8 bit character length */
-
-#define 	AT91_DBGU_PAR_EVEN	(0 << 9)		/* Even Parity */
-#define 	AT91_DBGU_PAR_ODD	(1 << 9)		/* Odd Parity */
-#define 	AT91_DBGU_PAR_SPACE	(2 << 9)		/* Space: Force Parity to 0 */
-#define 	AT91_DBGU_PAR_MARK	(3 << 9)		/* Mark: Force Parity to 1 */
-#define 	AT91_DBGU_PAR_NONE	(4 << 9)		/* No Parity */
-
-#define 	AT91_DBGU_CHMODE_NORMAL	(0 << 14) /* Normal mode */
-#define 	AT91_DBGU_CHMODE_AUTO		(1 << 14) /* Automatic Echo */
-#define 	AT91_DBGU_CHMODE_LOCAL		(2 << 14) /* Local Loopback */
-#define 	AT91_DBGU_CHMODE_REMOTE	(3 << 14) /* Remote Loopback */
-#define AT91_DBGU_IER		(0x08)	/* Interrupt Enable Register */
-#define		AT91_DBGU_TXRDY		(1 << 1)		/* Transmitter Ready */
-#define		AT91_DBGU_TXEMPTY	(1 << 9)		/* Transmitter Empty */
-#define AT91_DBGU_IDR		(0x0c)	/* Interrupt Disable Register */
-#define AT91_DBGU_IMR		(0x10)	/* Interrupt Mask Register */
-#define AT91_DBGU_SR		(0x14)	/* Status Register */
-#define AT91_DBGU_RHR		(0x18)	/* Receiver Holding Register */
-#define AT91_DBGU_THR		(0x1c)	/* Transmitter Holding Register */
-#define AT91_DBGU_BRGR		(0x20)	/* Baud Rate Generator Register */
-
-#define AT91_DBGU_CIDR		(0x40)	/* Chip ID Register */
-#define AT91_DBGU_EXID		(0x44)	/* Chip ID Extension Register */
-#define AT91_DBGU_FNR		(0x48)	/* Force NTRST Register [SAM9 only] */
-#define		AT91_DBGU_FNTRST	(1 << 0)		/* Force NTRST */
-
-
-/*
- * Some AT91 parts that don't have full DEBUG units still support the ID
- * and extensions register.
- */
-#define		AT91_CIDR_VERSION	(0x1f << 0)		/* Version of the Device */
-#define		AT91_CIDR_EPROC		(7    << 5)		/* Embedded Processor */
-#define		AT91_CIDR_NVPSIZ	(0xf  << 8)		/* Nonvolatile Program Memory Size */
-#define		AT91_CIDR_NVPSIZ2	(0xf  << 12)		/* Second Nonvolatile Program Memory Size */
-#define		AT91_CIDR_SRAMSIZ	(0xf  << 16)		/* Internal SRAM Size */
-#define			AT91_CIDR_SRAMSIZ_1K	(1 << 16)
-#define			AT91_CIDR_SRAMSIZ_2K	(2 << 16)
-#define			AT91_CIDR_SRAMSIZ_112K	(4 << 16)
-#define			AT91_CIDR_SRAMSIZ_4K	(5 << 16)
-#define			AT91_CIDR_SRAMSIZ_80K	(6 << 16)
-#define			AT91_CIDR_SRAMSIZ_160K	(7 << 16)
-#define			AT91_CIDR_SRAMSIZ_8K	(8 << 16)
-#define			AT91_CIDR_SRAMSIZ_16K	(9 << 16)
-#define			AT91_CIDR_SRAMSIZ_32K	(10 << 16)
-#define			AT91_CIDR_SRAMSIZ_64K	(11 << 16)
-#define			AT91_CIDR_SRAMSIZ_128K	(12 << 16)
-#define			AT91_CIDR_SRAMSIZ_256K	(13 << 16)
-#define			AT91_CIDR_SRAMSIZ_96K	(14 << 16)
-#define			AT91_CIDR_SRAMSIZ_512K	(15 << 16)
-#define		AT91_CIDR_ARCH		(0xff << 20)		/* Architecture Identifier */
-#define		AT91_CIDR_NVPTYP	(7    << 28)		/* Nonvolatile Program Memory Type */
-#define		AT91_CIDR_EXT		(1    << 31)		/* Extension Flag */
-
-#ifndef __ASSEMBLY__
-
-#include <asm/io.h>
-static inline void at91_dbgu_setup_ll(void __iomem *dbgu_base,
-				      unsigned mck,
-				      unsigned baudrate)
-{
-	u32 brgr = mck / (baudrate * 16);
-
-	if ((mck / (baudrate * 16)) % 10 >= 5)
-		brgr++;
-
-	writel(~0, dbgu_base + AT91_DBGU_IDR);
-
-	writel(AT91_DBGU_RSTRX
-	       | AT91_DBGU_RSTTX
-	       | AT91_DBGU_RXDIS
-	       | AT91_DBGU_TXDIS,
-	       dbgu_base + AT91_DBGU_CR);
-
-	writel(brgr, dbgu_base + AT91_DBGU_BRGR);
-
-	writel(AT91_DBGU_PAR_NONE
-	       | AT91_DBGU_CHMODE_NORMAL
-	       | AT91_DBGU_CHRL_8BIT
-	       | AT91_DBGU_NBSTOP_1BIT,
-	       dbgu_base + AT91_DBGU_MR);
-
-	writel(AT91_DBGU_RXEN | AT91_DBGU_TXEN, dbgu_base + AT91_DBGU_CR);
-}
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
deleted file mode 100644
index 7d70fe4cb4..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
+++ /dev/null
@@ -1,373 +0,0 @@
-/* SPDX-License-Identifier: BSD-1-Clause */
-/*
- * Copyright (c) 2006, Atmel Corporation
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- */
-#ifndef __AT91_DDRSDRC_H__
-#define __AT91_DDRSDRC_H__
-
-/**** Register offset in AT91S_HDDRSDRC2 structure ***/
-#define AT91_HDDRSDRC2_MR		0x00	/* Mode Register */
-#define AT91_HDDRSDRC2_RTR		0x04	/* Refresh Timer Register */
-#define AT91_HDDRSDRC2_CR		0x08	/* Configuration Register */
-#define AT91_HDDRSDRC2_T0PR		0x0C	/* Timing Parameter 0 Register */
-#define AT91_HDDRSDRC2_T1PR		0x10	/* Timing Parameter 1 Register */
-#define AT91_HDDRSDRC2_T2PR		0x14	/* Timing Parameter 2 Register */
-#define AT91_HDDRSDRC2_T3PR		0x18	/* Timing Parameter 3 Register */
-#define AT91_HDDRSDRC2_LPR		0x1C	/* Low-power Register */
-#define AT91_HDDRSDRC2_MDR		0x20	/* Memory Device Register */
-#define AT91_HDDRSDRC2_DLL		0x24	/* DLL Information Register */
-#define AT91_HDDRSDRC2_HS		0x2C	/* High Speed Register */
-
-/* below items defined for sama5d3x */
-#define	AT91_MPDDRC_LPDDR2_HS		0x24	/* MPDDRC LPDDR2 High Speed Register */
-#define	AT91_MPDDRC_LPDDR2_LPR		0x28	/* MPDDRC LPDDR2 Low-power Register */
-#define	AT91_MPDDRC_LPDDR2_CAL_MR4	0x2C	/* MPDDRC LPDDR2 Calibration and MR4 Register */
-#define	AT91_MPDDRC_LPDDR2_TIM_CAL	0x30	/* MPDDRC LPDDR2 Timing Calibration Register */
-#define	AT91_MPDDRC_IO_CALIBR		0x34	/* MPDDRC IO Calibration */
-#define	AT91_MPDDRC_OCMS		0x38	/* MPDDRC OCMS Register */
-#define	AT91_MPDDRC_OCMS_KEY1		0x3C	/* MPDDRC OCMS KEY1 Register */
-#define	AT91_MPDDRC_OCMS_KEY2		0x40	/* MPDDRC OCMS KEY2 Register */
-/* 0x54 ~ 0x70 Reserved */
-#define	AT91_MPDDRC_DLL_MOR		0x74	/* MPDDRC DLL Master Offset Register */
-#define	AT91_MPDDRC_DLL_SOR		0x78	/* MPDDRC DLL Slave Offset Register */
-#define	AT91_MPDDRC_DLL_MSR		0x7C	/* MPDDRC DLL Master Status Register */
-#define	AT91_MPDDRC_DLL_S0SR		0x80	/* MPDDRC DLL Slave 0 Status Register */
-#define	AT91_MPDDRC_DLL_S1SR		0x84	/* MPDDRC DLL Slave 1 Status Register */
-
-#define AT91_MPDDRC_RD_DATA_PATH	0x5C	/* MPDDRC Read Data Path */
-
-/* 0x94 ~ 0xE0 Reserved */
-#define AT91_HDDRSDRC2_WPCR		0xE4	/* Write Protect Mode Register */
-#define AT91_HDDRSDRC2_WPSR		0xE8	/* Write Protect Status Register */
-
-/* -------- HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register --------*/
-#define AT91_DDRC2_MODE	(0x7UL << 0)
-#define 	AT91_DDRC2_MODE_NORMAL_CMD		(0x0UL)
-#define 	AT91_DDRC2_MODE_NOP_CMD			(0x1UL)
-#define 	AT91_DDRC2_MODE_PRCGALL_CMD		(0x2UL)
-#define 	AT91_DDRC2_MODE_LMR_CMD			(0x3UL)
-#define 	AT91_DDRC2_MODE_RFSH_CMD		(0x4UL)
-#define 	AT91_DDRC2_MODE_EXT_LMR_CMD		(0x5UL)
-#define 	AT91_DDRC2_MODE_DEEP_CMD		(0x6UL)
-#define		AT91_DDRC2_MODE_LPDDR2_CMD		(0x7UL)
-#define AT91_DDRC2_MRS(value)	(value << 8)
-
-/* -------- HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register -------- */
-#define AT91_DDRC2_COUNT	(0xFFFUL << 0)
-#define AT91_DDRC2_ADJ_REF	(0x1UL << 16)
-#define 	AT91_DDRC2_DISABLE_ADJ_REF	(0x0UL << 16)
-#define 	AT91_DDRC2_ENABLE_ADJ_REF	(0x1UL << 16)
-
-/* -------- HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register --------*/
-#define AT91_DDRC2_NC		(0x3UL <<  0)
-#define 	AT91_DDRC2_NC_DDR9_SDR8	(0x0UL)
-#define 	AT91_DDRC2_NC_DDR10_SDR9	(0x1UL)
-#define 	AT91_DDRC2_NC_DDR11_SDR10	(0x2UL)
-#define 	AT91_DDRC2_NC_DDR12_SDR11	(0x3UL)
-#define AT91_DDRC2_NR		(0x3UL << 2)
-#define 	AT91_DDRC2_NR_11		(0x0UL << 2)
-#define 	AT91_DDRC2_NR_12		(0x1UL << 2)
-#define 	AT91_DDRC2_NR_13		(0x2UL << 2)
-#define 	AT91_DDRC2_NR_14		(0x3UL << 2)
-#define AT91_DDRC2_CAS		(0x7UL << 4)
-#define 	AT91_DDRC2_CAS_2		(0x2UL << 4)
-#define 	AT91_DDRC2_CAS_3		(0x3UL << 4)
-#define 	AT91_DDRC2_CAS_4		(0x4UL << 4)
-#define 	AT91_DDRC2_CAS_5		(0x5UL << 4)
-#define 	AT91_DDRC2_CAS_6		(0x6UL << 4)
-#define AT91_DDRC2_RESET_DLL	(0x1UL << 7)
-#define 	AT91_DDRC2_DISABLE_RESET_DLL	(0x0UL << 7)
-#define 	AT91_DDRC2_ENABLE_RESET_DLL	(0x1UL << 7)
-#define AT91_DDRC2_DIC_DS	(0x1UL << 8)
-#define		AT91_DDRC2_NORMAL_STRENGTH_RZQ6	(0x0UL << 8)
-#define		AT91_DDRC2_WEAK_STRENGTH_RZQ7		(0x1UL << 8)
-#define AT91_DDRC2_DLL	(0x1UL << 9)
-#define 	AT91_DDRC2_ENABLE_DLL		(0x0UL << 9)
-#define 	AT91_DDRC2_DISABLE_DLL		(0x1UL << 9)
-#define AT91_DDRC2_ZQ		(0x03 << 10)
-#define		AT91_DDRC2_ZQ_INIT		(0x0 << 10)
-#define		AT91_DDRC2_ZQ_LONG		(0x1 << 10)
-#define		AT91_DDRC2_ZQ_SHORT		(0x2 << 10)
-#define		AT91_DDRC2_ZQ_RESET		(0x3 << 10)
-#define AT91_DDRC2_OCD		(0x7UL << 12)
-#define 	AT91_DDRC2_OCD_EXIT		(0x0UL << 12)
-#define 	AT91_DDRC2_OCD_DEFAULT		(0x7UL << 12)
-#define AT91_DDRC2_EBISHARE	(0x1UL << 16)
-#define AT91_DDRC2_DQMS	(0x1UL << 16)
-#define		AT91_DDRC2_DQMS_NOT_SHARED	(0x0UL << 16)
-#define		AT91_DDRC2_DQMS_SHARED		(0x1UL << 16)
-#define AT91_DDRC2_ENRDM	(0x1UL << 17)
-#define 	AT91_DDRC2_ENRDM_DISABLE	(0x0UL << 17)
-#define 	AT91_DDRC2_ENRDM_ENABLE	(0x1UL << 17)
-#define AT91_DDRC2_ACTBST	(0x1UL << 18)
-#define AT91_DDRC2_NB_BANKS	(0x1UL << 20)
-#define 	AT91_DDRC2_NB_BANKS_4		(0x0UL << 20)
-#define 	AT91_DDRC2_NB_BANKS_8		(0x1UL << 20)
-#define AT91_DDRC2_NDQS	(0x1UL << 21)	/* Not DQS(sama5d3x only) */
-#define 	AT91_DDRC2_NDQS_ENABLED	(0x0UL << 21)
-#define 	AT91_DDRC2_NDQS_DISABLED	(0x1UL << 21)
-#define AT91_DDRC2_DECOD	(0x1UL << 22)
-#define 	AT91_DDRC2_DECOD_SEQUENTIAL	(0x0UL << 22)
-#define 	AT91_DDRC2_DECOD_INTERLEAVED	(0x1UL << 22)
-#define AT91_DDRC2_UNAL		(0x1UL << 23)	/* Support Unaligned Access(sama5d3x only) */
-#define 	AT91_DDRC2_UNAL_UNSUPPORTED		(0x0UL << 23)
-#define 	AT91_DDRC2_UNAL_SUPPORTED		(0x1UL << 23)
-
-/* -------- HDDRSDRC2_T0PR : (HDDRSDRC2 Offset: 0xc) Timing0 Register --------*/
-#define AT91_DDRC2_TRAS	(0xFUL <<  0)
-#define		AT91_DDRC2_TRAS_(x)		(x & 0x0f)
-#define	AT91_DDRC2_TRCD	(0xFUL <<  4)
-#define		AT91_DDRC2_TRCD_(x)		((x & 0x0f) << 4)
-#define	AT91_DDRC2_TWR		(0xFUL << 8)
-#define		AT91_DDRC2_TWR_(x)		((x & 0x0f) << 8)
-#define	AT91_DDRC2_TRC		(0xFUL << 12)
-#define		AT91_DDRC2_TRC_(x)		((x & 0x0f) << 12)
-#define	AT91_DDRC2_TRP		(0xFUL << 16)
-#define		AT91_DDRC2_TRP_(x)		((x & 0x0f) << 16)
-#define	AT91_DDRC2_TRRD	(0xFUL << 20)
-#define		AT91_DDRC2_TRRD_(x)		((x & 0x0f) << 20)
-#define	AT91_DDRC2_TWTR	(0xFUL << 24)
-#define		AT91_DDRC2_TWTR_(x)		((x & 0x0f) << 24)
-#define	AT91_DDRC2_TMRD	(0xFUL << 28)
-#define		AT91_DDRC2_TMRD_(x)		((x & 0x0f) << 28)
-
-/* -------- HDDRSDRC2_T1PR : (HDDRSDRC2 Offset: 0x10) Timing1 Register -------- */
-#define	AT91_DDRC2_TRFC	(0x7FUL <<  0)
-#define		AT91_DDRC2_TRFC_(x)		(x & 0x7f)
-#define	AT91_DDRC2_TXSNR	(0xFFUL << 8)
-#define		AT91_DDRC2_TXSNR_(x)		((x & 0xff) << 8)
-#define AT91_DDRC2_TXSRD	(0xFFUL << 16)
-#define		AT91_DDRC2_TXSRD_(x)		((x & 0xff) << 16)
-#define	AT91_DDRC2_TXP		(0xFUL << 24)
-#define		AT91_DDRC2_TXP_(x)		((x & 0x0f) << 24)
-
-/* -------- HDDRSDRC2_T2PR : (HDDRSDRC2 Offset: 0x14) Timing2 Register --------*/
-#define	AT91_DDRC2_TXARD	(0xFUL << 0)
-#define		AT91_DDRC2_TXARD_(x)		(x & 0x0f)
-#define	AT91_DDRC2_TXARDS	(0xFUL << 4)
-#define		AT91_DDRC2_TXARDS_(x)		((x & 0x0f) << 4)
-#define	AT91_DDRC2_TRPA	(0xFUL << 8)
-#define		AT91_DDRC2_TRPA_(x)		((x & 0x0f) << 8)
-#define	AT91_DDRC2_TRT		(0xFUL << 12)
-#define		AT91_DDRC2_TRTP_(x)		((x & 0x0f) << 12)
-#define	AT91_DDRC2_TFA		(0xFUL << 16)
-#define		AT91_DDRC2_TFAW_(x)		((x & 0x0f) << 16)
-
-/* -------- HDDRSDRC2_LPR : (HDDRSDRC2 Offset: 0x1c) --------*/
-#define AT91_DDRC2_LPCB	(0x3UL << 0)
-#define 	AT91_DDRC2_LPCB_DISABLED	(0x0UL)
-#define 	AT91_DDRC2_LPCB_SELFREFRESH	(0x1UL)
-#define 	AT91_DDRC2_LPCB_POWERDOWN	(0x2UL)
-#define 	AT91_DDRC2_LPCB_DEEP_PWD	(0x3UL)
-#define AT91_DDRC2_CLK_FR	(0x1UL << 2)
-#define AT91_DDRC2_PASR	(0x7UL << 4)
-#define		AT91_DDRC2_PASR_(x)		((x & 0x7) << 4)
-#define AT91_DDRC2_DS		(0x7UL << 8)
-#define		AT91_DDRC2_DS_(x)		((x & 0x7) << 8)
-#define AT91_DDRC2_TIMEOUT	(0x3UL << 12)
-#define 	AT91_DDRC2_TIMEOUT_0		(0x0UL << 12)
-#define 	AT91_DDRC2_TIMEOUT_64		(0x1UL << 12)
-#define 	AT91_DDRC2_TIMEOUT_128		(0x2UL << 12)
-#define 	AT91_DDRC2_TIMEOUT_Reserved	(0x3UL << 12)
-#define AT91_DDRC2_ADPE	(0x1UL << 16)
-#define 	AT91_DDRC2_ADPE_FAST		(0x0UL << 16)
-#define 	AT91_DDRC2_ADPE_SLOW		(0x1UL << 16)
-#define AT91_DDRC2_UPD_MR	(0x3UL << 20)
-#define		AT91_DDRC2_UPD_MR_NO_UPDATE		(0x0UL << 20)
-#define		AT91_DDRC2_UPD_MR_SHARED_BUS		(0x1UL << 20)
-#define		AT91_DDRC2_UPD_MR_NO_SHARED_BUS	(0x2UL << 20)
-#define AT91_DDRC2_SELF_DONE	(0x1UL << 25)
-
-/* -------- HDDRSDRC2_MDR : (HDDRSDRC2 Offset: 0x20) Memory Device Register -------- */
-#define AT91_DDRC2_MD		(0x7UL << 0)
-#define 	AT91_DDRC2_MD_SDR_SDRAM	(0x0UL)
-#define 	AT91_DDRC2_MD_LP_SDR_SDRAM	(0x1UL)
-#define 	AT91_DDRC2_MD_DDR_SDRAM	(0x2UL)
-#define 	AT91_DDRC2_MD_LP_DDR_SDRAM	(0x3UL)
-#define 	AT91_DDRC2_MD_DDR3_SDRAM	(0x4UL)
-#define 	AT91_DDRC2_MD_LPDDR3_SDRAM	(0x5UL)
-#define 	AT91_DDRC2_MD_DDR2_SDRAM	(0x6UL)
-#define		AT91_DDRC2_MD_LPDDR2_SDRAM	(0x7UL)
-#define AT91_DDRC2_DBW		(0x1UL << 4)
-#define 	AT91_DDRC2_DBW_32_BITS		(0x0UL << 4)
-#define 	AT91_DDRC2_DBW_16_BITS		(0x1UL << 4)
-
-/* -------- HDDRSDRC2_DLL : (HDDRSDRC2 Offset: 0x24) DLL Information Register --------*/
-#define AT91_DDRC2_MDINC	(0x1UL << 0)
-#define AT91_DDRC2_MDDEC	(0x1UL << 1)
-#define AT91_DDRC2_MDOVF	(0x1UL << 2)
-#define AT91_DDRC2_MDVAL	(0xFFUL << 8)
-
-/* ------- MPDDRC_LPDDR2_LPR (offset: 0x28) */
-#define AT91_LPDDRC2_BK_MASK_PASR(value)	(value << 0)
-#define AT91_LPDDRC2_SEG_MASK(value)		(value << 8)
-#define AT91_LPDDRC2_DS(value)			(value << 24)
-
-/* -------- HDDRSDRC2_HS : (HDDRSDRC2 Offset: 0x2c) High Speed Register --------*/
-#define AT91_DDRC2_NO_ANT	(0x1UL << 2)
-
-/* -------- MPDDRC_LPDDR2_CAL_MR4: (MPDDRC Offset: 0x2c) Calibration and MR4 Register --------*/
-#define AT91_DDRC2_COUNT_CAL_MASK	(0xFFFFUL)
-#define AT91_DDRC2_COUNT_CAL(value)	(((value) & AT91_DDRC2_COUNT_CAL_MASK) << 0)
-#define AT91_DDRC2_MR4R(value)		(((value) & 0xFFFFUL) << 16)
-
-/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) */
-#define AT91_DDRC2_ZQCS(value)	(value << 0)
-
-/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) IO Calibration --------*/
-#define AT91_MPDDRC_RDIV	(0x7UL << 0)
-#define 	AT91_MPDDRC_RDIV_LPDDR2_RZQ_34		(0x1UL << 0)
-#define 	AT91_MPDDRC_RDIV_LPDDR2_RZQ_48		(0x3UL << 0)
-#define 	AT91_MPDDRC_RDIV_LPDDR2_RZQ_60		(0x4UL << 0)
-#define 	AT91_MPDDRC_RDIV_LPDDR2_RZQ_120	(0x7UL << 0)
-
-#define 	AT91_MPDDRC_RDIV_DDR2_RZQ_33_3		(0x2UL << 0)
-#define 	AT91_MPDDRC_RDIV_DDR2_RZQ_50		(0x4UL << 0)
-#define		AT91_MPDDRC_RDIV_DDR2_RZQ_66_7		(0x6UL << 0)
-#define 	AT91_MPDDRC_RDIV_DDR2_RZQ_100		(0x7UL << 0)
-
-#define		AT91_MPDDRC_RDIV_LPDDR3_RZQ_38		(0x02UL << 0)
-#define		AT91_MPDDRC_RDIV_LPDDR3_RZQ_46		(0x03UL << 0)
-#define		AT91_MPDDRC_RDIV_LPDDR3_RZQ_57		(0x04UL << 0)
-#define		AT91_MPDDRC_RDIV_LPDDR3_RZQ_77		(0x06UL << 0)
-#define		AT91_MPDDRC_RDIV_LPDDR3_RZQ_115	(0x07UL << 0)
-
-#define	AT91_MPDDRC_ENABLE_CALIB	(0x01 << 4)
-#define		AT91_MPDDRC_DISABLE_CALIB		(0x00 << 4)
-#define		AT91_MPDDRC_EN_CALIB		(0x01 << 4)
-
-#define	AT91_MPDDRC_TZQIO	(0x7FUL << 8)
-#define	AT91_MPDDRC_TZQIO_(x)		((x) << 8)
-#define		AT91_MPDDRC_TZQIO_0	(0x0UL << 8)
-#define		AT91_MPDDRC_TZQIO_1	(0x1UL << 8)
-#define		AT91_MPDDRC_TZQIO_3	(0x3UL << 8)
-#define		AT91_MPDDRC_TZQIO_4	(0x4UL << 8)
-#define		AT91_MPDDRC_TZQIO_5	(0x5UL << 8)
-#define		AT91_MPDDRC_TZQIO_31	(0x1FUL << 8)
-
-#define	AT91_MPDDRC_CALCODEP	(0xFUL << 16)
-#define		AT91_MPDDRC_CALCODEP_(x)	((x) << 16)
-
-#define	AT91_MPDDRC_CALCODEN	(0xFUL << 20)
-#define		AT91_MPDDRC_CALCODEN_(x)	((x) << 20)
-
-/* ---- MPDDRC_RD_DATA_PATH : (MPDDRC Offset: 0x5c) MPDDRC Read Data Path */
-#define AT91_MPDDRC_SHIFT_SAMPLING	(0x03 << 0)
-#define		AT91_MPDDRC_RD_DATA_PATH_NO_SHIFT	(0x00 << 0)
-#define		AT91_MPDDRC_RD_DATA_PATH_ONE_CYCLES	(0x01 << 0)
-#define		AT91_MPDDRC_RD_DATA_PATH_TWO_CYCLES	(0x02 << 0)
-#define		AT91_MPDDRC_RD_DATA_PATH_THREE_CYCLES	(0x03 << 0)
-
-/* -------- MPDDRC_DLL_MOR : (MPDDRC Offset: 0x74) DLL Master Offset Register --------*/
-#define AT91_MPDDRC_MOFF(value)	(value << 0)
-#define 	AT91_MPDDRC_MOFF_1	(0x1UL << 0)
-#define 	AT91_MPDDRC_MOFF_7	(0x7UL << 0)
-#define AT91_MPDDRC_CLK90OFF(value)		(value << 8)
-#define 	AT91_MPDDRC_CLK90OFF_1		(0x1UL << 8)
-#define 	AT91_MPDDRC_CLK90OFF_31	(0x1FUL << 8)
-#define AT91_MPDDRC_SELOFF	(0x1UL << 16)
-#define 	AT91_MPDDRC_SELOFF_DISABLED	(0x0UL << 16)
-#define 	AT91_MPDDRC_SELOFF_ENABLED	(0x1UL << 16)
-#define AT91_MPDDRC_KEY	(0xC5UL << 24)
-
-/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x78) DLL Slave Offset Register --------*/
-#define AT91_MPDDRC_S0OFF_1	(0x1UL << 0)
-#define AT91_MPDDRC_S1OFF_1	(0x1UL << 8)
-#define AT91_MPDDRC_S2OFF_1	(0x1UL << 16)
-#define AT91_MPDDRC_S3OFF_1	(0x1UL << 24)
-
-#define AT91_MPDDRC_S0OFF(value)	(value << 0)
-#define AT91_MPDDRC_S1OFF(value)	(value << 8)
-#define AT91_MPDDRC_S2OFF(value)	(value << 16)
-#define AT91_MPDDRC_S3OFF(value)	(value << 24)
-
-/* -------- HDDRSDRC2_WPCR : (HDDRSDRC2 Offset: 0xe4) Write Protect Control Register --------*/
-#define AT91_DDRC2_WPEN	(0x1UL << 0)
-#define AT91_DDRC2_WPKEY	(0xFFFFFFUL << 8)
-
-/* -------- HDDRSDRC2_WPSR : (HDDRSDRC2 Offset: 0xe8) Write Protect Status Register --------*/
-#define AT91_DDRC2_WPVS	(0x1UL << 0)
-#define AT91_DDRC2_WPSRC	(0xFFFFUL << 8)
-
-#ifndef __ASSEMBLY__
-#include <common.h>
-#include <io.h>
-#include <mach/hardware.h>
-
-static inline u32 at91_get_ddram_size(void __iomem *base, bool is_nb)
-{
-	u32 cr;
-	u32 mdr;
-	u32 size;
-	bool is_sdram;
-
-	cr = readl(base + AT91_HDDRSDRC2_CR);
-	mdr = readl(base + AT91_HDDRSDRC2_MDR);
-
-	/* will always be false for sama5d2, sama5d3 or sama5d4 */
-	is_sdram = (mdr & AT91_DDRC2_MD) <= AT91_DDRC2_MD_LP_SDR_SDRAM;
-
-	/* Formula:
-	 * size = bank << (col + row + 1);
-	 * if (bandwidth == 32 bits)
-	 *	size <<= 1;
-	 */
-	size = 1;
-	/* COL */
-	size += (cr & AT91_DDRC2_NC) + 8;
-	if (!is_sdram)
-		size ++;
-	/* ROW */
-	size += ((cr & AT91_DDRC2_NR) >> 2) + 11;
-	/* BANK */
-	if (is_nb)
-		size = ((cr & AT91_DDRC2_NB_BANKS) ? 8 : 4) << size;
-	else
-		size = 4 << size;
-
-	/* bandwidth */
-	if (!(mdr & AT91_DDRC2_DBW))
-		size <<= 1;
-
-	return size;
-}
-
-static inline u32 at91sam9g45_get_ddram_size(int bank)
-{
-	switch (bank) {
-	case 0:
-		return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0), false);
-	case 1:
-		return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1), false);
-	default:
-		return 0;
-	}
-}
-
-static inline u32 at91sam9x5_get_ddram_size(void)
-{
-	return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true);
-}
-
-static inline u32 at91sam9n12_get_ddram_size(void)
-{
-	return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true);
-}
-
-static inline u32 at91sama5d3_get_ddram_size(void)
-{
-	return at91_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC), true);
-}
-
-static inline u32 at91sama5d4_get_ddram_size(void)
-{
-	return at91_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC), true);
-}
-
-
-#endif /* __ASSEMBLY__ */
-
-#endif	/* #ifndef __AT91_DDRSDRC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
deleted file mode 100644
index 61cff83c73..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */
-/* SPDX-FileCopyrightText: SAN People */
-/* SPDX-FileCopyrightText: 2015 Atmel */
-/* SPDX-FileCopyrightText: 2015 Ludovic Desroches <ludovic.desroches@atmel.com> */
-
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
- *
- * Parallel I/O Controller (PIO) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- */
-
-#ifndef AT91_PIO_H
-#define AT91_PIO_H
-
-#include <linux/bitops.h>
-
-#define PIO_PER		0x00	/* Enable Register */
-#define PIO_PDR		0x04	/* Disable Register */
-#define PIO_PSR		0x08	/* Status Register */
-#define PIO_OER		0x10	/* Output Enable Register */
-#define PIO_ODR		0x14	/* Output Disable Register */
-#define PIO_OSR		0x18	/* Output Status Register */
-#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
-#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
-#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
-#define PIO_SODR	0x30	/* Set Output Data Register */
-#define PIO_CODR	0x34	/* Clear Output Data Register */
-#define PIO_ODSR	0x38	/* Output Data Status Register */
-#define PIO_PDSR	0x3c	/* Pin Data Status Register */
-#define PIO_IER		0x40	/* Interrupt Enable Register */
-#define PIO_IDR		0x44	/* Interrupt Disable Register */
-#define PIO_IMR		0x48	/* Interrupt Mask Register */
-#define PIO_ISR		0x4c	/* Interrupt Status Register */
-#define PIO_MDER	0x50	/* Multi-driver Enable Register */
-#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
-#define PIO_MDSR	0x58	/* Multi-driver Status Register */
-#define PIO_PUDR	0x60	/* Pull-up Disable Register */
-#define PIO_PUER	0x64	/* Pull-up Enable Register */
-#define PIO_PUSR	0x68	/* Pull-up Status Register */
-#define PIO_ASR		0x70	/* Peripheral A Select Register */
-#define PIO_ABCDSR1	0x70	/* Peripheral ABCD Select Register 1 [some sam9 only] */
-#define PIO_BSR		0x74	/* Peripheral B Select Register */
-#define PIO_ABCDSR2	0x74	/* Peripheral ABCD Select Register 2 [some sam9 only] */
-#define PIO_ABSR	0x78	/* AB Status Register */
-#define PIO_IFSCDR	0x80	/* Input Filter Slow Clock Disable Register */
-#define PIO_IFSCER	0x84	/* Input Filter Slow Clock Enable Register */
-#define PIO_IFSCSR	0x88	/* Input Filter Slow Clock Status Register */
-#define PIO_SCDR	0x8c	/* Slow Clock Divider Debouncing Register */
-#define		PIO_SCDR_DIV	(0x3fff <<  0)		/* Slow Clock Divider Mask */
-#define PIO_PPDDR	0x90	/* Pad Pull-down Disable Register */
-#define PIO_PPDER	0x94	/* Pad Pull-down Enable Register */
-#define PIO_PPDSR	0x98	/* Pad Pull-down Status Register */
-#define PIO_OWER	0xa0	/* Output Write Enable Register */
-#define PIO_OWDR	0xa4	/* Output Write Disable Register */
-#define PIO_OWSR	0xa8	/* Output Write Status Register */
-#define PIO_AIMER	0xb0	/* Additional Interrupt Modes Enable Register */
-#define PIO_AIMDR	0xb4	/* Additional Interrupt Modes Disable Register */
-#define PIO_AIMMR	0xb8	/* Additional Interrupt Modes Mask Register */
-#define PIO_ESR		0xc0	/* Edge Select Register */
-#define PIO_LSR		0xc4	/* Level Select Register */
-#define PIO_ELSR	0xc8	/* Edge/Level Status Register */
-#define PIO_FELLSR	0xd0	/* Falling Edge/Low Level Select Register */
-#define PIO_REHLSR	0xd4	/* Rising Edge/ High Level Select Register */
-#define PIO_FRLHSR	0xd8	/* Fall/Rise - Low/High Status Register */
-#define PIO_SCHMITT	0x100	/* Schmitt Trigger Register */
-
-#define ABCDSR_PERIPH_A	0x0
-#define ABCDSR_PERIPH_B	0x1
-#define ABCDSR_PERIPH_C	0x2
-#define ABCDSR_PERIPH_D	0x3
-
-#define PIO4_MSKR	0x0000	/* Mask Register */
-#define PIO4_CFGR	0x0004	/* Configuration Register */
-#define		PIO4_CFGR_FUNC_MASK		GENMASK(2, 0)
-#define		PIO4_DIR_MASK			BIT(8)
-#define		PIO4_PUEN_MASK			BIT(9)
-#define		PIO4_PDEN_MASK			BIT(10)
-#define		PIO4_IFEN_MASK			BIT(12)
-#define		PIO4_IFSCEN_MASK		BIT(13)
-#define		PIO4_OPD_MASK			BIT(14)
-#define		PIO4_SCHMITT_MASK		BIT(15)
-#define		PIO4_DRVSTR_MASK		GENMASK(17, 16)
-#define		PIO4_DRVSTR_OFFSET		16
-#define		PIO4_CFGR_EVTSEL_MASK		GENMASK(26, 24)
-#define		PIO4_CFGR_EVTSEL_FALLING	(0 << 24)
-#define		PIO4_CFGR_EVTSEL_RISING		(1 << 24)
-#define		PIO4_CFGR_EVTSEL_BOTH		(2 << 24)
-#define		PIO4_CFGR_EVTSEL_LOW		(3 << 24)
-#define		PIO4_CFGR_EVTSEL_HIGH		(4 << 24)
-#define	PIO4_PDSR	0x0008	/* Data Status Register */
-#define	PIO4_LOCKSR	0x000C	/* Lock Status Register */
-#define	PIO4_SODR	0x0010	/* Set Output Data Register */
-#define	PIO4_CODR	0x0014	/* Clear Output Data Register */
-#define	PIO4_ODSR	0x0018	/* Output Data Status Register */
-#define	PIO4_IER	0x0020	/* Interrupt Enable Register */
-#define	PIO4_IDR	0x0024	/* Interrupt Disable Register */
-#define	PIO4_IMR	0x0028	/* Interrupt Mask Register */
-#define	PIO4_ISR	0x002C	/* Interrupt Status Register */
-#define	PIO4_IOFR	0x003C	/* I/O Freeze Configuration Register */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
deleted file mode 100644
index 4cdeeb4871..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_pit.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2007 Andrew Victor */
-/* SPDX-FileCopyrightText: 2007 Atmel Corporation */
-
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h]
- *
- * Periodic Interval Timer (PIT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- */
-
-#ifndef AT91_PIT_H
-#define AT91_PIT_H
-
-#define AT91_PIT_MR		0x00			/* Mode Register */
-#define		AT91_PIT_PITIEN		(1 << 25)		/* Timer Interrupt Enable */
-#define		AT91_PIT_PITEN		(1 << 24)		/* Timer Enabled */
-#define		AT91_PIT_PIV		(0xfffff)		/* Periodic Interval Value */
-
-#define AT91_PIT_SR		0x04			/* Status Register */
-#define		AT91_PIT_PITS		(1 << 0)		/* Timer Status */
-
-#define AT91_PIT_PIVR		0x08			/* Periodic Interval Value Register */
-#define AT91_PIT_PIIR		0x0c			/* Periodic Interval Image Register */
-#define		AT91_PIT_PICNT		(0xfff << 20)		/* Interval Counter */
-#define		AT91_PIT_CPIV		(0xfffff)		/* Inverval Value */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
deleted file mode 100644
index 2860ea4854..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */
-/* SPDX-FileCopyrightText: SAN People */
-
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
- *
- * Power Management Controller (PMC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- */
-
-#ifndef AT91_PMC_H
-#define AT91_PMC_H
-
-#define	AT91_PMC_SCER		0x00			/* System Clock Enable Register */
-#define	AT91_PMC_SCDR		0x04			/* System Clock Disable Register */
-
-#define	AT91_PMC_SCSR		0x08			/* System Clock Status Register */
-#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
-#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
-#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define		AT91CAP9_PMC_DDR	(1 <<  2)		/* DDR Clock [CAP9 revC & some SAM9 only] */
-#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
-#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
-#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
-#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
-#define		AT91_PMC_PCK4		(1 << 12)		/* Programmable Clock 4 [AT572D940HF only] */
-#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
-#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
-
-#define	AT91_PMC_PCER		0x10			/* Peripheral Clock Enable Register */
-#define	AT91_PMC_PCDR		0x14			/* Peripheral Clock Disable Register */
-#define	AT91_PMC_PCSR		0x18			/* Peripheral Clock Status Register */
-
-#define	AT91_CKGR_UCKR		0x1C			/* UTMI Clock Register [some SAM9] */
-#define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
-#define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
-#define			AT91_PMC_UPLLCOUNT_DEFAULT	(0x1UL << 20)
-#define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
-#define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI BIAS Start-up Time */
-
-#define	AT91_CKGR_MOR		0x20			/* Main Oscillator Register [not on SAM9RL] */
-#define		AT91_PMC_MOSCEN		(1    <<  0)		/* Main Oscillator Enable */
-#define		AT91_PMC_OSCBYPASS	(1    <<  1)		/* Oscillator Bypass */
-#define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
-#define		AT91_PMC_OSCOUNT	(0xff <<  8)		/* Main Oscillator Start-up Time */
-#define			AT91_PMC_OSCOUNT_(x) ((x) << 8)
-#define		AT91_PMC_KEY_MASK	(0xff << 16)		/* MOR Writing Key */
-#define			AT91_PMC_KEY		(0x37 << 16)
-#define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
-#define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */
-
-#define	AT91_CKGR_MCFR		0x24			/* Main Clock Frequency Register */
-#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
-#define		AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Frequency Measure Ready */
-#define		AT91_PMC_RCMEAS         (1      << 20)          /* RC Oscillator Frequency Measure (write-only) */
-#define		AT91_PMC_CCSS           (1      << 24)          /* Counter Clock Source Selection */
-#define			AT91_PMC_CCSS_RC_OSC    (0      << 24)          /* MAINF counter clock is the RC oscillator. */
-#define			AT91_PMC_CCSS_XTAL_OSC  (1      << 24)          /* MAINF counter clock is the crystal oscillator. */
-#define	AT91_CKGR_PLLAR		0x28			/* PLL A Register */
-#define	AT91_CKGR_PLLBR		0x2c			/* PLL B Register */
-#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
-#define			AT91_PMC_DIV_BYPASS	(1 << 0)		/* Divider bypass */
-#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
-#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
-#define			AT91_PMC_OUT_0		(0 << 14)
-#define			AT91_PMC_OUT_1		(1 << 14)
-#define			AT91_PMC_OUT_2		(2 << 14)
-#define			AT91_PMC_OUT_3		(3 << 14)
-#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
-#define			AT91_PMC_MUL_(n)		(((n) << 16) & AT91_PMC_MUL)
-#define		AT91_PMC3_MUL		(0x7f << 18)		/* PLL Multiplier [SAMA5 only]*/
-#define			AT91_PMC3_MUL_(n)		(((n) << 18) & AT91_PMC3_MUL)
-#define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
-#define			AT91_PMC_USBDIV_1		(0 << 28)
-#define			AT91_PMC_USBDIV_2		(1 << 28)
-#define			AT91_PMC_USBDIV_4		(2 << 28)
-#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
-#define		AT91_PMC_PLLA_WR_ERRATA	(1     << 29)		/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
-
-#define	AT91_PMC_MCKR		0x30			/* Master Clock Register */
-#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
-#define			AT91_PMC_CSS_SLOW		(0 << 0)
-#define			AT91_PMC_CSS_MAIN		(1 << 0)
-#define			AT91_PMC_CSS_PLLA		(2 << 0)
-#define			AT91_PMC_CSS_PLLB		(3 << 0)
-#define			AT91_PMC_CSS_UPLL		(3 << 0)	/* [some SAM9 only] */
-#define		PMC_PRES_OFFSET		2
-#define		AT91_PMC_PRES		(7 <<  PMC_PRES_OFFSET)		/* Master Clock Prescaler */
-#define			AT91_PMC_PRES_1			(0 << PMC_PRES_OFFSET)
-#define			AT91_PMC_PRES_2			(1 << PMC_PRES_OFFSET)
-#define			AT91_PMC_PRES_4			(2 << PMC_PRES_OFFSET)
-#define			AT91_PMC_PRES_8			(3 << PMC_PRES_OFFSET)
-#define			AT91_PMC_PRES_16		(4 << PMC_PRES_OFFSET)
-#define			AT91_PMC_PRES_32		(5 << PMC_PRES_OFFSET)
-#define			AT91_PMC_PRES_64		(6 << PMC_PRES_OFFSET)
-#define		PMC_ALT_PRES_OFFSET	4
-#define		AT91_PMC_ALT_PRES	(7 <<  PMC_ALT_PRES_OFFSET)		/* Master Clock Prescaler [alternate location] */
-#define			AT91_PMC_ALT_PRES_1		(0 << PMC_ALT_PRES_OFFSET)
-#define			AT91_PMC_ALT_PRES_2		(1 << PMC_ALT_PRES_OFFSET)
-#define			AT91_PMC_ALT_PRES_4		(2 << PMC_ALT_PRES_OFFSET)
-#define			AT91_PMC_ALT_PRES_8		(3 << PMC_ALT_PRES_OFFSET)
-#define			AT91_PMC_ALT_PRES_16		(4 << PMC_ALT_PRES_OFFSET)
-#define			AT91_PMC_ALT_PRES_32		(5 << PMC_ALT_PRES_OFFSET)
-#define			AT91_PMC_ALT_PRES_64		(6 << PMC_ALT_PRES_OFFSET)
-#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
-#define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
-#define			AT91RM9200_PMC_MDIV_2		(1 << 8)
-#define			AT91RM9200_PMC_MDIV_3		(2 << 8)
-#define			AT91RM9200_PMC_MDIV_4		(3 << 8)
-#define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9 only] */
-#define			AT91SAM9_PMC_MDIV_2		(1 << 8)
-#define			AT91SAM9_PMC_MDIV_4		(2 << 8)
-#define			AT91SAM9_PMC_MDIV_6		(3 << 8)	/* [some SAM9 only] */
-#define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
-#define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
-#define			AT91_PMC_PDIV_1			(0 << 12)
-#define			AT91_PMC_PDIV_2			(1 << 12)
-#define		AT91_PMC_PLLADIV2	(1 << 12)		/* PLLA divisor by 2 [some SAM9 only] */
-#define			AT91_PMC_PLLADIV2_OFF		(0 << 12)
-#define			AT91_PMC_PLLADIV2_ON		(1 << 12)
-#define		AT91_PMC_H32MXDIV	(1 << 24)		/* AHB 32-bit Matrix Divisor [some SAMA5 only] */
-
-#define	AT91_PMC_USB		0x38			/* USB Clock Register [some SAM9 only] */
-#define		AT91_PMC_USBS		(0x1 <<  0)		/* USB OHCI Input clock selection */
-#define			AT91_PMC_USBS_PLLA		(0 << 0)
-#define			AT91_PMC_USBS_UPLL		(1 << 0)
-#define		AT91_PMC_OHCIUSBDIV	(0xF <<  8)		/* Divider for USB OHCI Clock */
-
-#define	AT91_PMC_SMD		0x3c			/* Soft Modem Clock Register [some SAM9 only] */
-#define		AT91_PMC_SMDS		(0x1  <<  0)		/* SMD input clock selection */
-#define		AT91_PMC_SMD_DIV	(0x1f <<  8)		/* SMD input clock divider */
-#define		AT91_PMC_SMDDIV(n)	(((n) <<  8) & AT91_PMC_SMD_DIV)
-
-#define	AT91_PMC_PCKR(n)	(0x40 + ((n) * 4))	/* Programmable Clock 0-N Registers */
-#define		AT91_PMC_ALT_PCKR_CSS	(0x7 <<  0)		/* Programmable Clock Source Selection [alternate length] */
-#define			AT91_PMC_CSS_MASTER		(4 << 0)	/* [some SAM9 only] */
-#define		AT91_PMC_CSSMCK		(0x1 <<  8)		/* CSS or Master Clock Selection */
-#define			AT91_PMC_CSSMCK_CSS		(0 << 8)
-#define			AT91_PMC_CSSMCK_MCK		(1 << 8)
-
-#define	AT91_PMC_IER		0x60			/* Interrupt Enable Register */
-#define		AT91_PMC_MOSCXTS	(1 << 0)		/* Oscillator Startup Time */
-#define	AT91_PMC_IDR		0x64			/* Interrupt Disable Register */
-#define	AT91_PMC_SR		0x68			/* Status Register */
-#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
-#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
-#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
-#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
-#define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock [some SAM9] */
-#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
-#define		AT91_PMC_MOSCSELS	(1 << 16)		/* Main Oscillator Selection [some SAM9] */
-#define		AT91_PMC_MOSCRCS	(1 << 17)		/* Main On-Chip RC [some SAM9] */
-#define		AT91_PMC_CFDEV		(1 << 18)		/* Clock Failure Detector Event [some SAM9] */
-#define		AT91_PMC_GCKRDY		(1 << 24)
-#define	AT91_PMC_IMR		0x6c			/* Interrupt Mask Register */
-#define	AT91_PMC_PLLICPR	0x80			/* PLL Charge Pump Current Register */
-#define		AT91_PMC_ICPPLLA	(0xf <<  0)
-#define			AT91_PMC_ICPPLLA_0		(0 <<  0)
-#define			AT91_PMC_ICPPLLA_1		(1 <<  0)
-#define		AT91_PMC_REALLOCK	(0x1 <<  7)
-#define		AT91_PMC_IPLLA		(0xf <<  8)
-#define			AT91_PMC_IPLLA_0		(0 <<  8)
-#define			AT91_PMC_IPLLA_1		(1 <<  8)
-#define			AT91_PMC_IPLLA_2		(2 <<  8)
-#define			AT91_PMC_IPLLA_3		(3 <<  8)
-
-
-#define AT91_PMC_PROT		0xe4			/* Write Protect Mode Register [some SAM9] */
-#define		AT91_PMC_WPEN		(0x1  <<  0)		/* Write Protect Enable */
-#define		AT91_PMC_WPKEY		(0xffffff << 8)		/* Write Protect Key */
-#define		AT91_PMC_PROTKEY	(0x504d43 << 8)		/* Activation Code */
-
-#define AT91_PMC_WPSR		0xe8			/* Write Protect Status Register [some SAM9] */
-#define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
-#define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
-
-#define AT91_PMC_VER		0xfc			/* PMC Module Version [AT91CAP9 only] */
-
-#define AT91_PMC_PCR		0x10c			/* Peripheral Control Register [some SAM9] */
-#define		AT91_PMC_PCR_PID	(0x3f  <<  0)		/* Peripheral ID */
-#define		AT91_PMC_GCKCSS	(0x7 << 8)
-#define			AT91_PMC_GCKCSS_SLOW_CLK	(0x0 << 8)
-#define			AT91_PMC_GCKCSS_MAIN_CLK	(0x1 << 8)
-#define			AT91_PMC_GCKCSS_PLLA_CLK	(0x2 << 8)
-#define			AT91_PMC_GCKCSS_UPLL_CLK	(0x3 << 8)
-#define			AT91_PMC_GCKCSS_MCK_CLK		(0x4 << 8)
-#define			AT91_PMC_GCKCSS_AUDIO_CLK	(0x5 << 8)
-#define		AT91_PMC_PCR_CMD	(0x1  <<  12)		/* Command */
-#define		AT91_PMC_PCR_DIV_MASK	(0x3  <<  16)
-#define		AT91_PMC_PCR_DIV(n)	((n) <<  16)	/* Divisor value */
-#define			AT91_PMC_PCR_DIV0	0x0		/* Peripheral clock is MCK */
-#define			AT91_PMC_PCR_DIV2	0x1		/* Peripheral clock is MCK/2 */
-#define			AT91_PMC_PCR_DIV4	0x2		/* Peripheral clock is MCK/4 */
-#define			AT91_PMC_PCR_DIV8	0x3		/* Peripheral clock is MCK/8 */
-#define		AT91_PMC_GCKDIV		(0xff << 20)
-#define			AT91_PMC_GCKDIV_MSK		0xff
-#define			AT91_PMC_GCKDIV_OFFSET		20
-#define			AT91_PMC_GCKDIV_(x)		(((x) & AT91_PMC_GCKDIV_MSK) << AT91_PMC_GCKDIV_OFFSET)
-#define		AT91_PMC_PCR_EN		(0x1  <<  28)		/* Enable */
-#define		AT91_PMC_GCK_EN		(0x1  <<  29)
-
-#define	AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 */
-#define	AT91_PMC_PCDR1		0x104			/* Peripheral Clock Disable Register 1 */
-#define	AT91_PMC_PCSR1		0x108			/* Peripheral Clock Status Register 1 */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
deleted file mode 100644
index 85896a01d5..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: BSD-1-Clause
-/*
- * Copyright (c) 2006, Atmel Corporation
- */
-
-#ifndef AT91_PMC_LL_H
-#define AT91_PMC_LL_H
-
-#include <errno.h>
-#include <asm/io.h>
-#include <mach/at91_pmc.h>
-
-#define AT91_PMC_LL_FLAG_SAM9X5_PMC	(1 << 0)
-#define AT91_PMC_LL_FLAG_MEASURE_XTAL	(1 << 1)
-#define AT91_PMC_LL_FLAG_DISABLE_RC	(1 << 2)
-#define AT91_PMC_LL_FLAG_H32MXDIV	(1 << 3)
-#define AT91_PMC_LL_FLAG_PMC_UTMI	(1 << 4)
-#define AT91_PMC_LL_FLAG_GCSR		(1 << 5)
-#define AT91_PMC_LL_FLAG_MCK_BYPASS	(1 << 6)
-
-#define AT91_PMC_LL_AT91RM9200	(0)
-#define AT91_PMC_LL_AT91SAM9260	(0)
-#define AT91_PMC_LL_AT91SAM9261	(0)
-#define AT91_PMC_LL_AT91SAM9263	(0)
-#define AT91_PMC_LL_AT91SAM9G45	(AT91_PMC_LL_FLAG_PMC_UTMI)
-#define AT91_PMC_LL_AT91SAM9X5	(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
-				 AT91_PMC_LL_FLAG_DISABLE_RC | \
-				 AT91_PMC_LL_FLAG_PMC_UTMI)
-#define AT91_PMC_LL_AT91SAM9N12	(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
-				 AT91_PMC_LL_FLAG_DISABLE_RC)
-#define AT91_PMC_LL_SAMA5D2	(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
-				 AT91_PMC_LL_FLAG_MEASURE_XTAL | \
-				 AT91_PMC_LL_FLAG_PMC_UTMI)
-/* This assumes a crystal on both XIN and XOUT. If your board
- * instead has an extenal oscillator on XIN only,
- * AT91_PMC_LL_FLAG_MCK_BYPASS needs to be OR`ed in as well
- */
-#define AT91_PMC_LL_SAMA5D3	(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
-				 AT91_PMC_LL_FLAG_DISABLE_RC | \
-				 AT91_PMC_LL_FLAG_PMC_UTMI)
-#define AT91_PMC_LL_SAMA5D4	(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
-				 AT91_PMC_LL_FLAG_H32MXDIV | \
-				 AT91_PMC_LL_FLAG_PMC_UTMI)
-
-void at91_pmc_init(void __iomem *pmc_base, unsigned int flags);
-void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags);
-void at91_pmc_cfg_plla(void __iomem *pmc_base, u32 pmc_pllar, unsigned int flags);
-
-int at91_pmc_enable_generic_clock(void __iomem *pmc_base, void __iomem *sfr_base,
-				  unsigned int periph_id,
-				  unsigned int clk_source, unsigned int div,
-				  unsigned int flags);
-
-static inline void at91_pmc_init_pll(void __iomem *pmc_base, u32 pmc_pllicpr)
-{
-	writel(pmc_pllicpr, pmc_base + AT91_PMC_PLLICPR);
-}
-
-static inline void at91_pmc_enable_system_clock(void __iomem *pmc_base,
-						unsigned clock_id)
-{
-	writel(clock_id, pmc_base +  AT91_PMC_SCER);
-}
-
-static inline int at91_pmc_enable_periph_clock(void __iomem *pmc_base,
-					       unsigned periph_id)
-{
-	u32 mask = 0x01 << (periph_id % 32);
-
-	if ((periph_id / 32) == 1)
-		writel(mask, pmc_base + AT91_PMC_PCER1);
-	else if ((periph_id / 32) == 0)
-		writel(mask, pmc_base + AT91_PMC_PCER);
-	else
-		return -EINVAL;
-
-	return 0;
-}
-
-static inline int at91_pmc_sam9x5_enable_periph_clock(void __iomem *pmc_base,
-						      unsigned periph_id)
-{
-       u32 pcr = periph_id;
-
-       if (periph_id >= 0x80) /* 7 bits only */
-               return -EINVAL;
-
-       writel(pcr, pmc_base + AT91_PMC_PCR);
-       pcr |= readl(pmc_base + AT91_PMC_PCR) & AT91_PMC_PCR_DIV_MASK;
-       pcr |= AT91_PMC_PCR_CMD | AT91_PMC_PCR_EN;
-       writel(pcr, pmc_base + AT91_PMC_PCR);
-
-       return 0;
-}
-
-static inline bool at91_pmc_check_mck_h32mxdiv(void __iomem *pmc_base,
-					       unsigned flags)
-{
-	if (flags & AT91_PMC_LL_FLAG_H32MXDIV)
-		return readl(pmc_base + AT91_PMC_MCKR) & AT91_PMC_H32MXDIV;
-
-	return false;
-}
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
deleted file mode 100644
index 1dc665b877..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_rstc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2007 Andrew Victor */
-/* SPDX-FileCopyrightText: 2007 Atmel Corporation */
-
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
- *
- * Reset Controller (RSTC) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- */
-
-#ifndef AT91_RSTC_H
-#define AT91_RSTC_H
-
-#define AT91_RSTC_CR		(0x00)	/* Reset Controller Control Register */
-#define		AT91_RSTC_PROCRST	(1 << 0)		/* Processor Reset */
-#define		AT91_RSTC_PERRST	(1 << 2)		/* Peripheral Reset */
-#define		AT91_RSTC_EXTRST	(1 << 3)		/* External Reset */
-#define		AT91_RSTC_KEY		(0xa5 << 24)		/* KEY Password */
-
-#define AT91_RSTC_SR		(0x04)	/* Reset Controller Status Register */
-#define		AT91_RSTC_URSTS		(1 << 0)		/* User Reset Status */
-#define		AT91_RSTC_RSTTYP	(7 << 8)		/* Reset Type */
-#define			AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
-#define			AT91_RSTC_RSTTYP_WAKEUP		(1 << 8)
-#define			AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
-#define			AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
-#define			AT91_RSTC_RSTTYP_USER	(4 << 8)
-#define		AT91_RSTC_NRSTL		(1 << 16)		/* NRST Pin Level */
-#define		AT91_RSTC_SRCMP		(1 << 17)		/* Software Reset Command in Progress */
-
-#define AT91_RSTC_MR		(0x08)	/* Reset Controller Mode Register */
-#define		AT91_RSTC_URSTEN	(1 << 0)		/* User Reset Enable */
-#define		AT91_RSTC_URSTIEN	(1 << 4)		/* User Reset Interrupt Enable */
-#define		AT91_RSTC_ERSTL		(0xf << 8)		/* External Reset Length */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h
deleted file mode 100644
index b4197665dd..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_rtt.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2007 Andrew Victor */
-/* SPDX-FileCopyrightText: 2007 Atmel Corporation */
-
-/*
- * arch/arm/mach-at91/include/mach/at91_rtt.h
- *
- * Real-time Timer (RTT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- */
-
-#ifndef AT91_RTT_H
-#define AT91_RTT_H
-
-#include <io.h>
-
-#define AT91_RTT_MR		0x00			/* Real-time Mode Register */
-#define		AT91_RTT_RTPRES		(0xffff << 0)		/* Real-time Timer Prescaler Value */
-#define		AT91_RTT_ALMIEN		(1 << 16)		/* Alarm Interrupt Enable */
-#define		AT91_RTT_RTTINCIEN	(1 << 17)		/* Real Time Timer Increment Interrupt Enable */
-#define		AT91_RTT_RTTRST		(1 << 18)		/* Real Time Timer Restart */
-
-#define AT91_RTT_AR		0x04			/* Real-time Alarm Register */
-#define		AT91_RTT_ALMV		(0xffffffff)		/* Alarm Value */
-
-#define AT91_RTT_VR		0x08			/* Real-time Value Register */
-#define		AT91_RTT_CRTV		(0xffffffff)		/* Current Real-time Value */
-
-#define AT91_RTT_SR		0x0c			/* Real-time Status Register */
-#define		AT91_RTT_ALMS		(1 << 0)		/* Real-time Alarm Status */
-#define		AT91_RTT_RTTINC		(1 << 1)		/* Real-time Timer Increment */
-
-
-/*
- * As the RTT is powered by the backup power so if the interrupt
- * is still on when the kernel start, the kernel will end up with
- * dead lock interrupt that it can not clear. Because the interrupt line is
- * shared with the basic timer (PIT) on AT91_ID_SYS.
- */
-static inline void at91_rtt_irq_fixup(void *base)
-{
-	void __iomem *reg = base + AT91_RTT_MR;
-	u32 mr = readl(reg);
-
-	writel(mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN), reg);
-}
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
deleted file mode 100644
index 04924742a5..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
- *
- * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Watchdog Timer (WDT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_WDT_H
-#define AT91_WDT_H
-
-#define AT91_WDT_CR		0x00			/* Watchdog Control Register */
-#define		AT91_WDT_WDRSTT		(1    << 0)		/* Restart */
-#define		AT91_WDT_KEY		(0xa5 << 24)		/* KEY Password */
-
-#define AT91_WDT_MR		 0x04			/* Watchdog Mode Register */
-#define		AT91_WDT_WDV		(0xfff << 0)		/* Counter Value */
-#define		AT91_WDT_WDFIEN		(1     << 12)		/* Fault Interrupt Enable */
-#define		AT91_WDT_WDRSTEN	(1     << 13)		/* Reset Processor */
-#define		AT91_WDT_WDRPROC	(1     << 14)		/* Timer Restart */
-#define		AT91_WDT_WDDIS		(1     << 15)		/* Watchdog Disable */
-#define		AT91_WDT_WDD		(0xfff << 16)		/* Delta Value */
-#define		AT91_WDT_WDDBGHLT	(1     << 28)		/* Debug Halt */
-#define		AT91_WDT_WDIDLEHLT	(1     << 29)		/* Idle Halt */
-
-#define AT91_WDT_SR		0x08			/* Watchdog Status Register */
-#define		AT91_WDT_WDUNF		(1 << 0)		/* Watchdog Underflow */
-#define		AT91_WDT_WDERR		(1 << 1)		/* Watchdog Error */
-
-#ifndef __ASSEMBLY__
-// SPDX-License-Identifier: BSD-1-Clause
-/*
- * Copyright (c) 2006, Atmel Corporation
- */
-
-#include <asm/io.h>
-
-static inline void at91_wdt_disable(void __iomem *wdt_base)
-{
-	u32 reg = readl(wdt_base + AT91_WDT_MR);
-	reg |= AT91_WDT_WDDIS;
-	writel(reg, wdt_base + AT91_WDT_MR);
-}
-
-#endif /* __ASSEMBLY__ */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
deleted file mode 100644
index 4d6c8939ef..0000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */
-/* SPDX-FileCopyrightText: SAN People */
-
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91rm9200.h]
- *
- * Common definitions.
- * Based on AT91RM9200 datasheet revision E.
- */
-
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91RM9200_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91RM9200_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91RM9200_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91RM9200_ID_PIOD	5	/* Parallel IO Controller D */
-#define AT91RM9200_ID_US0	6	/* USART 0 */
-#define AT91RM9200_ID_US1	7	/* USART 1 */
-#define AT91RM9200_ID_US2	8	/* USART 2 */
-#define AT91RM9200_ID_US3	9	/* USART 3 */
-#define AT91RM9200_ID_MCI	10	/* Multimedia Card Interface */
-#define AT91RM9200_ID_UDP	11	/* USB Device Port */
-#define AT91RM9200_ID_TWI	12	/* Two-Wire Interface */
-#define AT91RM9200_ID_SPI	13	/* Serial Peripheral Interface */
-#define AT91RM9200_ID_SSC0	14	/* Serial Synchronous Controller 0 */
-#define AT91RM9200_ID_SSC1	15	/* Serial Synchronous Controller 1 */
-#define AT91RM9200_ID_SSC2	16	/* Serial Synchronous Controller 2 */
-#define AT91RM9200_ID_TC0	17	/* Timer Counter 0 */
-#define AT91RM9200_ID_TC1	18	/* Timer Counter 1 */
-#define AT91RM9200_ID_TC2	19	/* Timer Counter 2 */
-#define AT91RM9200_ID_TC3	20	/* Timer Counter 3 */
-#define AT91RM9200_ID_TC4	21	/* Timer Counter 4 */
-#define AT91RM9200_ID_TC5	22	/* Timer Counter 5 */
-#define AT91RM9200_ID_UHP	23	/* USB Host port */
-#define AT91RM9200_ID_EMAC	24	/* Ethernet MAC */
-#define AT91RM9200_ID_IRQ0	25	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91RM9200_ID_IRQ1	26	/* Advanced Interrupt Controller (IRQ1) */
-#define AT91RM9200_ID_IRQ2	27	/* Advanced Interrupt Controller (IRQ2) */
-#define AT91RM9200_ID_IRQ3	28	/* Advanced Interrupt Controller (IRQ3) */
-#define AT91RM9200_ID_IRQ4	29	/* Advanced Interrupt Controller (IRQ4) */
-#define AT91RM9200_ID_IRQ5	30	/* Advanced Interrupt Controller (IRQ5) */
-#define AT91RM9200_ID_IRQ6	31	/* Advanced Interrupt Controller (IRQ6) */
-
-
-/*
- * Peripheral physical base addresses.
- */
-#define AT91RM9200_BASE_TCB0	0xfffa0000
-#define AT91RM9200_BASE_TC0	0xfffa0000
-#define AT91RM9200_BASE_TC1	0xfffa0040
-#define AT91RM9200_BASE_TC2	0xfffa0080
-#define AT91RM9200_BASE_TCB1	0xfffa4000
-#define AT91RM9200_BASE_TC3	0xfffa4000
-#define AT91RM9200_BASE_TC4	0xfffa4040
-#define AT91RM9200_BASE_TC5	0xfffa4080
-#define AT91RM9200_BASE_UDP	0xfffb0000
-#define AT91RM9200_BASE_MCI	0xfffb4000
-#define AT91RM9200_BASE_TWI	0xfffb8000
-#define AT91RM9200_BASE_EMAC	0xfffbc000
-#define AT91RM9200_BASE_US0	0xfffc0000
-#define AT91RM9200_BASE_US1	0xfffc4000
-#define AT91RM9200_BASE_US2	0xfffc8000
-#define AT91RM9200_BASE_US3	0xfffcc000
-#define AT91RM9200_BASE_SSC0	0xfffd0000
-#define AT91RM9200_BASE_SSC1	0xfffd4000
-#define AT91RM9200_BASE_SSC2	0xfffd8000
-#define AT91RM9200_BASE_SPI	0xfffe0000
-
-/*
- * System Peripherals
- */
-#define AT91RM9200_BASE_DBGU	AT91_BASE_DBGU0	/* Debug Unit */
-#define AT91RM9200_BASE_PIOA	0xfffff400	/* PIO Controller A */
-#define AT91RM9200_BASE_PIOB	0xfffff600	/* PIO Controller B */
-#define AT91RM9200_BASE_PIOC	0xfffff800	/* PIO Controller C */
-#define AT91RM9200_BASE_PIOD	0xfffffa00	/* PIO Controller D */
-#define AT91RM9200_BASE_PMC	0xfffffc00
-#define AT91RM9200_BASE_ST	0xfffffd00	/* System Timer */
-#define AT91RM9200_BASE_RTC	0xfffffe00	/* Real-Time Clock */
-#define AT91RM9200_BASE_MC	0xffffff00	/* Memory Controllers */
-
-/*
- * Internal Memory.
- */
-#define AT91RM9200_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91RM9200_ROM_SIZE	SZ_128K		/* Internal ROM size (128Kb) */
-
-#define AT91RM9200_SRAM_BASE	0x00200000	/* Internal SRAM base address */
-#define AT91RM9200_SRAM_SIZE	SZ_16K		/* Internal SRAM size (16Kb) */
-
-#define AT91RM9200_UHP_BASE	0x00300000	/* USB Host controller */
-
-#define AT91_VA_BASE_EMAC	AT91RM9200_BASE_EMAC
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
deleted file mode 100644
index 5de0349433..0000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */
-/* SPDX-FileCopyrightText: SAN People */
-
-/*
- * [origin: arch/arm/mach-at91/include/mach/at91rm9200_emac.h]
- *
- * Ethernet MAC registers.
- * Based on AT91RM9200 datasheet revision E.
- */
-
-#ifndef AT91RM9200_EMAC_H
-#define AT91RM9200_EMAC_H
-
-#define	AT91_EMAC_CTL		0x00	/* Control Register */
-#define		AT91_EMAC_LB		(1 <<  0)	/* Loopback */
-#define		AT91_EMAC_LBL		(1 <<  1)	/* Loopback Local */
-#define		AT91_EMAC_RE		(1 <<  2)	/* Receive Enable */
-#define		AT91_EMAC_TE		(1 <<  3)	/* Transmit Enable */
-#define		AT91_EMAC_MPE		(1 <<  4)	/* Management Port Enable */
-#define		AT91_EMAC_CSR		(1 <<  5)	/* Clear Statistics Registers */
-#define		AT91_EMAC_INCSTAT	(1 <<  6)	/* Increment Statistics Registers */
-#define		AT91_EMAC_WES		(1 <<  7)	/* Write Enable for Statistics Registers */
-#define		AT91_EMAC_BP		(1 <<  8)	/* Back Pressure */
-
-#define	AT91_EMAC_CFG		0x04	/* Configuration Register */
-#define		AT91_EMAC_SPD		(1 <<  0)	/* Speed */
-#define		AT91_EMAC_FD		(1 <<  1)	/* Full Duplex */
-#define		AT91_EMAC_BR		(1 <<  2)	/* Bit Rate */
-#define		AT91_EMAC_CAF		(1 <<  4)	/* Copy All Frames */
-#define		AT91_EMAC_NBC		(1 <<  5)	/* No Broadcast */
-#define		AT91_EMAC_MTI		(1 <<  6)	/* Multicast Hash Enable */
-#define		AT91_EMAC_UNI		(1 <<  7)	/* Unicast Hash Enable */
-#define		AT91_EMAC_BIG		(1 <<  8)	/* Receive 1522 Bytes */
-#define		AT91_EMAC_EAE		(1 <<  9)	/* External Address Match Enable */
-#define		AT91_EMAC_CLK		(3 << 10)	/* MDC Clock Divisor */
-#define		AT91_EMAC_CLK_DIV8		(0 << 10)
-#define		AT91_EMAC_CLK_DIV16		(1 << 10)
-#define		AT91_EMAC_CLK_DIV32		(2 << 10)
-#define		AT91_EMAC_CLK_DIV64		(3 << 10)
-#define		AT91_EMAC_RTY		(1 << 12)	/* Retry Test */
-#define		AT91_EMAC_RMII		(1 << 13)	/* Reduce MII (RMII) */
-
-#define	AT91_EMAC_SR		0x08	/* Status Register */
-#define		AT91_EMAC_SR_LINK	(1 <<  0)	/* Link */
-#define		AT91_EMAC_SR_MDIO	(1 <<  1)	/* MDIO pin */
-#define		AT91_EMAC_SR_IDLE	(1 <<  2)	/* PHY idle */
-
-#define	AT91_EMAC_TAR		0x0c	/* Transmit Address Register */
-
-#define	AT91_EMAC_TCR		0x10	/* Transmit Control Register */
-#define		AT91_EMAC_LEN		(0x7ff << 0)	/* Transmit Frame Length */
-#define		AT91_EMAC_NCRC		(1     << 15)	/* No CRC */
-
-#define	AT91_EMAC_TSR		0x14	/* Transmit Status Register */
-#define		AT91_EMAC_TSR_OVR	(1 <<  0)	/* Transmit Buffer Overrun */
-#define		AT91_EMAC_TSR_COL	(1 <<  1)	/* Collision Occurred */
-#define		AT91_EMAC_TSR_RLE	(1 <<  2)	/* Retry Limit Exceeded */
-#define		AT91_EMAC_TSR_IDLE	(1 <<  3)	/* Transmitter Idle */
-#define		AT91_EMAC_TSR_BNQ	(1 <<  4)	/* Transmit Buffer not Queued */
-#define		AT91_EMAC_TSR_COMP	(1 <<  5)	/* Transmit Complete */
-#define		AT91_EMAC_TSR_UND	(1 <<  6)	/* Transmit Underrun */
-
-#define	AT91_EMAC_RBQP		0x18	/* Receive Buffer Queue Pointer */
-
-#define	AT91_EMAC_RSR		0x20	/* Receive Status Register */
-#define		AT91_EMAC_RSR_BNA	(1 <<  0)	/* Buffer Not Available */
-#define		AT91_EMAC_RSR_REC	(1 <<  1)	/* Frame Received */
-#define		AT91_EMAC_RSR_OVR	(1 <<  2)	/* RX Overrun */
-
-#define	AT91_EMAC_ISR		0x24	/* Interrupt Status Register */
-#define		AT91_EMAC_DONE		(1 <<  0)	/* Management Done */
-#define		AT91_EMAC_RCOM		(1 <<  1)	/* Receive Complete */
-#define		AT91_EMAC_RBNA		(1 <<  2)	/* Receive Buffer Not Available */
-#define		AT91_EMAC_TOVR		(1 <<  3)	/* Transmit Buffer Overrun */
-#define		AT91_EMAC_TUND		(1 <<  4)	/* Transmit Buffer Underrun */
-#define		AT91_EMAC_RTRY		(1 <<  5)	/* Retry Limit */
-#define		AT91_EMAC_TBRE		(1 <<  6)	/* Transmit Buffer Register Empty */
-#define		AT91_EMAC_TCOM		(1 <<  7)	/* Transmit Complete */
-#define		AT91_EMAC_TIDLE		(1 <<  8)	/* Transmit Idle */
-#define		AT91_EMAC_LINK		(1 <<  9)	/* Link */
-#define		AT91_EMAC_ROVR		(1 << 10)	/* RX Overrun */
-#define		AT91_EMAC_ABT		(1 << 11)	/* Abort */
-
-#define	AT91_EMAC_IER		0x28	/* Interrupt Enable Register */
-#define	AT91_EMAC_IDR		0x2c	/* Interrupt Disable Register */
-#define	AT91_EMAC_IMR		0x30	/* Interrupt Mask Register */
-
-#define	AT91_EMAC_MAN		0x34	/* PHY Maintenance Register */
-#define		AT91_EMAC_DATA		(0xffff << 0)	/* MDIO Data */
-#define		AT91_EMAC_REGA		(0x1f	<< 18)	/* MDIO Register */
-#define		AT91_EMAC_PHYA		(0x1f	<< 23)	/* MDIO PHY Address */
-#define		AT91_EMAC_RW		(3	<< 28)	/* Read/Write operation */
-#define			AT91_EMAC_RW_W		(1 << 28)
-#define			AT91_EMAC_RW_R		(2 << 28)
-#define		AT91_EMAC_MAN_802_3	0x40020000	/* IEEE 802.3 value */
-
-/*
- * Statistics Registers.
- */
-#define AT91_EMAC_FRA		0x40	/* Frames Transmitted OK */
-#define AT91_EMAC_SCOL		0x44	/* Single Collision Frame */
-#define AT91_EMAC_MCOL		0x48	/* Multiple Collision Frame */
-#define AT91_EMAC_OK		0x4c	/* Frames Received OK */
-#define AT91_EMAC_SEQE		0x50	/* Frame Check Sequence Error */
-#define AT91_EMAC_ALE		0x54	/* Alignmemt Error */
-#define AT91_EMAC_DTE		0x58	/* Deffered Transmission Frame */
-#define AT91_EMAC_LCOL		0x5c	/* Late Collision */
-#define AT91_EMAC_ECOL		0x60	/* Excessive Collision */
-#define AT91_EMAC_TUE		0x64	/* Transmit Underrun Error */
-#define AT91_EMAC_CSE		0x68	/* Carrier Sense Error */
-#define AT91_EMAC_DRFC		0x6c	/* Discard RX Frame */
-#define AT91_EMAC_ROV		0x70	/* Receive Overrun */
-#define AT91_EMAC_CDE		0x74	/* Code Error */
-#define AT91_EMAC_ELR		0x78	/* Excessive Length Error */
-#define AT91_EMAC_RJB		0x7c	/* Receive Jabber */
-#define AT91_EMAC_USF		0x80	/* Undersize Frame */
-#define AT91_EMAC_SQEE		0x84	/* SQE Test Error */
-
-/*
- * Address Registers.
- */
-#define AT91_EMAC_HSL		0x90	/* Hash Address Low [31:0] */
-#define AT91_EMAC_HSH		0x94	/* Hash Address High [63:32] */
-#define AT91_EMAC_SA1L		0x98	/* Specific Address 1 Low, bytes 0-3 */
-#define AT91_EMAC_SA1H		0x9c	/* Specific Address 1 High, bytes 4-5 */
-#define AT91_EMAC_SA2L		0xa0	/* Specific Address 2 Low, bytes 0-3 */
-#define AT91_EMAC_SA2H		0xa4	/* Specific Address 2 High, bytes 4-5 */
-#define AT91_EMAC_SA3L		0xa8	/* Specific Address 3 Low, bytes 0-3 */
-#define AT91_EMAC_SA3H		0xac	/* Specific Address 3 High, bytes 4-5 */
-#define AT91_EMAC_SA4L		0xb0	/* Specific Address 4 Low, bytes 0-3 */
-#define AT91_EMAC_SA4H		0xb4	/* Specific Address 4 High, bytes 4-5 */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
deleted file mode 100644
index 41ee1caba7..0000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */
-/* SPDX-FileCopyrightText: SAN People */
-
-/*
- * arch/arm/mach-at91/include/mach/at91rm9200_mc.h
- *
- * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- */
-
-#ifndef AT91RM9200_MC_H
-#define AT91RM9200_MC_H
-
-/* Memory Controller */
-#define AT91RM9200_MC_RCR		(0x00)	/* MC Remap Control Register */
-#define		AT91RM9200_MC_RCB		(1 <<  0)		/* Remap Command Bit */
-
-#define AT91RM9200_MC_ASR		(0x04)	/* MC Abort Status Register */
-#define		AT91RM9200_MC_UNADD		(1 <<  0)		/* Undefined Address Abort Status */
-#define		AT91RM9200_MC_MISADD		(1 <<  1)		/* Misaligned Address Abort Status */
-#define		AT91RM9200_MC_ABTSZ		(3 <<  8)		/* Abort Size Status */
-#define			AT91RM9200_MC_ABTSZ_BYTE		(0 << 8)
-#define			AT91RM9200_MC_ABTSZ_HALFWORD		(1 << 8)
-#define			AT91RM9200_MC_ABTSZ_WORD		(2 << 8)
-#define		AT91RM9200_MC_ABTTYP		(3 << 10)		/* Abort Type Status */
-#define			AT91RM9200_MC_ABTTYP_DATAREAD		(0 << 10)
-#define			AT91RM9200_MC_ABTTYP_DATAWRITE	(1 << 10)
-#define			AT91RM9200_MC_ABTTYP_FETCH		(2 << 10)
-#define		AT91RM9200_MC_MST0		(1 << 16)		/* ARM920T Abort Source */
-#define		AT91RM9200_MC_MST1		(1 << 17)		/* PDC Abort Source */
-#define		AT91RM9200_MC_MST2		(1 << 18)		/* UHP Abort Source */
-#define		AT91RM9200_MC_MST3		(1 << 19)		/* EMAC Abort Source */
-#define		AT91RM9200_MC_SVMST0		(1 << 24)		/* Saved ARM920T Abort Source */
-#define		AT91RM9200_MC_SVMST1		(1 << 25)		/* Saved PDC Abort Source */
-#define		AT91RM9200_MC_SVMST2		(1 << 26)		/* Saved UHP Abort Source */
-#define		AT91RM9200_MC_SVMST3		(1 << 27)		/* Saved EMAC Abort Source */
-
-#define AT91RM9200_MC_AASR		(0x08)	/* MC Abort Address Status Register */
-
-#define AT91RM9200_MC_MPR		(0x0c)	/* MC Master Priority Register */
-#define		AT91RM9200_MPR_MSTP0		(7 <<  0)		/* ARM920T Priority */
-#define		AT91RM9200_MPR_MSTP1		(7 <<  4)		/* PDC Priority */
-#define		AT91RM9200_MPR_MSTP2		(7 <<  8)		/* UHP Priority */
-#define		AT91RM9200_MPR_MSTP3		(7 << 12)		/* EMAC Priority */
-
-/* External Bus Interface (EBI) registers */
-#define AT91RM9200_EBI_CSA		(0x60)	/* Chip Select Assignment Register */
-#define		AT91RM9200_EBI_CS0A		(1 << 0)		/* Chip Select 0 Assignment */
-#define			AT91RM9200_EBI_CS0A_SMC		(0 << 0)
-#define			AT91RM9200_EBI_CS0A_BFC		(1 << 0)
-#define		AT91RM9200_EBI_CS1A		(1 << 1)		/* Chip Select 1 Assignment */
-#define			AT91RM9200_EBI_CS1A_SMC		(0 << 1)
-#define			AT91RM9200_EBI_CS1A_SDRAMC		(1 << 1)
-#define		AT91RM9200_EBI_CS3A		(1 << 3)		/* Chip Select 2 Assignment */
-#define			AT91RM9200_EBI_CS3A_SMC		(0 << 3)
-#define			AT91RM9200_EBI_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91RM9200_EBI_CS4A		(1 << 4)		/* Chip Select 3 Assignment */
-#define			AT91RM9200_EBI_CS4A_SMC		(0 << 4)
-#define			AT91RM9200_EBI_CS4A_SMC_COMPACTFLASH	(1 << 4)
-#define AT91RM9200_EBI_CFGR		(0x64)	/* Configuration Register */
-#define		AT91RM9200_EBI_DBPUC		(1 << 0)		/* Data Bus Pull-Up Configuration */
-
-/* Static Memory Controller (SMC) registers */
-#define	AT91RM9200_SMC_CSR(n)		(0x70 + ((n) * 4))/* SMC Chip Select Register */
-#define		AT91RM9200_SMC_NWS		(0x7f <<  0)		/* Number of Wait States */
-#define			AT91RM9200_SMC_NWS_(x)	((x) << 0)
-#define		AT91RM9200_SMC_WSEN		(1    <<  7)		/* Wait State Enable */
-#define		AT91RM9200_SMC_TDF		(0xf  <<  8)		/* Data Float Time */
-#define			AT91RM9200_SMC_TDF_(x)	((x) << 8)
-#define		AT91RM9200_SMC_BAT		(1    << 12)		/* Byte Access Type */
-#define		AT91RM9200_SMC_DBW		(3    << 13)		/* Data Bus Width */
-#define			AT91RM9200_SMC_DBW_16		(1 << 13)
-#define			AT91RM9200_SMC_DBW_8		(2 << 13)
-#define		AT91RM9200_SMC_DPR		(1 << 15)		/* Data Read Protocol */
-#define		AT91RM9200_SMC_ACSS		(3 << 16)		/* Address to Chip Select Setup */
-#define			AT91RM9200_SMC_ACSS_STD	(0 << 16)
-#define			AT91RM9200_SMC_ACSS_1		(1 << 16)
-#define			AT91RM9200_SMC_ACSS_2		(2 << 16)
-#define			AT91RM9200_SMC_ACSS_3		(3 << 16)
-#define		AT91RM9200_SMC_RWSETUP	(7 << 24)		/* Read & Write Signal Time Setup */
-#define			AT91RM9200_SMC_RWSETUP_(x)	((x) << 24)
-#define		AT91RM9200_SMC_RWHOLD		(7 << 28)		/* Read & Write Signal Hold Time */
-#define			AT91RM9200_SMC_RWHOLD_(x)	((x) << 28)
-
-/* SDRAM Controller registers */
-#define AT91RM9200_SDRAMC_MR		(0x90)	/* Mode Register */
-#define		AT91RM9200_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
-#define			AT91RM9200_SDRAMC_MODE_NORMAL		(0 << 0)
-#define			AT91RM9200_SDRAMC_MODE_NOP		(1 << 0)
-#define			AT91RM9200_SDRAMC_MODE_PRECHARGE	(2 << 0)
-#define			AT91RM9200_SDRAMC_MODE_LMR		(3 << 0)
-#define			AT91RM9200_SDRAMC_MODE_REFRESH	(4 << 0)
-#define		AT91RM9200_SDRAMC_DBW		(1   << 4)		/* Data Bus Width */
-#define			AT91RM9200_SDRAMC_DBW_32	(0 << 4)
-#define			AT91RM9200_SDRAMC_DBW_16	(1 << 4)
-
-#define AT91RM9200_SDRAMC_TR		(0x94)	/* Refresh Timer Register */
-#define		AT91RM9200_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Count */
-
-#define AT91RM9200_SDRAMC_CR		(0x98)	/* Configuration Register */
-#define		AT91RM9200_SDRAMC_NC		(3   <<  0)		/* Number of Column Bits */
-#define			AT91RM9200_SDRAMC_NC_8	(0 << 0)
-#define			AT91RM9200_SDRAMC_NC_9	(1 << 0)
-#define			AT91RM9200_SDRAMC_NC_10	(2 << 0)
-#define			AT91RM9200_SDRAMC_NC_11	(3 << 0)
-#define		AT91RM9200_SDRAMC_NR		(3   <<  2)		/* Number of Row Bits */
-#define			AT91RM9200_SDRAMC_NR_11	(0 << 2)
-#define			AT91RM9200_SDRAMC_NR_12	(1 << 2)
-#define			AT91RM9200_SDRAMC_NR_13	(2 << 2)
-#define		AT91RM9200_SDRAMC_NB		(1   <<  4)		/* Number of Banks */
-#define			AT91RM9200_SDRAMC_NB_2	(0 << 4)
-#define			AT91RM9200_SDRAMC_NB_4	(1 << 4)
-#define		AT91RM9200_SDRAMC_CAS		(3   <<  5)		/* CAS Latency */
-#define			AT91RM9200_SDRAMC_CAS_2	(2 << 5)
-#define		AT91RM9200_SDRAMC_TWR		(0xf <<  7)		/* Write Recovery Delay */
-#define		AT91RM9200_SDRAMC_TRC		(0xf << 11)		/* Row Cycle Delay */
-#define		AT91RM9200_SDRAMC_TRP		(0xf << 15)		/* Row Precharge Delay */
-#define		AT91RM9200_SDRAMC_TRCD	(0xf << 19)		/* Row to Column Delay */
-#define		AT91RM9200_SDRAMC_TRAS	(0xf << 23)		/* Active to Precharge Delay */
-#define		AT91RM9200_SDRAMC_TXSR	(0xf << 27)		/* Exit Self Refresh to Active Delay */
-
-#define AT91RM9200_SDRAMC_SRR		(0x9c)	/* Self Refresh Register */
-#define AT91RM9200_SDRAMC_LPR		(0xa0)	/* Low Power Register */
-#define AT91RM9200_SDRAMC_IER		(0xa4)	/* Interrupt Enable Register */
-#define AT91RM9200_SDRAMC_IDR		(0xa8)	/* Interrupt Disable Register */
-#define AT91RM9200_SDRAMC_IMR		(0xac)	/* Interrupt Mask Register */
-#define AT91RM9200_SDRAMC_ISR		(0xb0)	/* Interrupt Status Register */
-
-/* Burst Flash Controller register */
-#define AT91RM9200_BFC_MR		(0xc0)	/* Mode Register */
-#define		AT91RM9200_BFC_BFCOM		(3   <<  0)		/* Burst Flash Controller Operating Mode */
-#define			AT91RM9200_BFC_BFCOM_DISABLED	(0 << 0)
-#define			AT91RM9200_BFC_BFCOM_ASYNC	(1 << 0)
-#define			AT91RM9200_BFC_BFCOM_BURST	(2 << 0)
-#define		AT91RM9200_BFC_BFCC		(3   <<  2)		/* Burst Flash Controller Clock */
-#define			AT91RM9200_BFC_BFCC_MCK	(1 << 2)
-#define			AT91RM9200_BFC_BFCC_DIV2	(2 << 2)
-#define			AT91RM9200_BFC_BFCC_DIV4	(3 << 2)
-#define		AT91RM9200_BFC_AVL		(0xf <<  4)		/* Address Valid Latency */
-#define		AT91RM9200_BFC_PAGES		(7   <<  8)		/* Page Size */
-#define			AT91RM9200_BFC_PAGES_NO_PAGE	(0 << 8)
-#define			AT91RM9200_BFC_PAGES_16	(1 << 8)
-#define			AT91RM9200_BFC_PAGES_32	(2 << 8)
-#define			AT91RM9200_BFC_PAGES_64	(3 << 8)
-#define			AT91RM9200_BFC_PAGES_128	(4 << 8)
-#define			AT91RM9200_BFC_PAGES_256	(5 << 8)
-#define			AT91RM9200_BFC_PAGES_512	(6 << 8)
-#define			AT91RM9200_BFC_PAGES_1024	(7 << 8)
-#define		AT91RM9200_BFC_OEL		(3   << 12)		/* Output Enable Latency */
-#define		AT91RM9200_BFC_BAAEN		(1   << 16)		/* Burst Address Advance Enable */
-#define		AT91RM9200_BFC_BFOEH		(1   << 17)		/* Burst Flash Output Enable Handling */
-#define		AT91RM9200_BFC_MUXEN		(1   << 18)		/* Multiplexed Bus Enable */
-#define		AT91RM9200_BFC_RDYEN		(1   << 19)		/* Ready Enable Mode */
-
-#ifndef __ASSEMBLY__
-#include <io.h>
-#include <mach/at91rm9200.h>
-static inline u32 at91rm9200_get_sdram_size(void)
-{
-	u32 cr, mr;
-	u32 size;
-
-	cr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_CR);
-	mr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_MR);
-
-	/* Formula:
-	 * size = bank << (col + row + 1);
-	 * if (bandwidth == 32 bits)
-	 *	size <<= 1;
-	 */
-	size = 1;
-	/* COL */
-	size += (cr & AT91RM9200_SDRAMC_NC) + 8;
-	/* ROW */
-	size += ((cr & AT91RM9200_SDRAMC_NR) >> 2) + 11;
-	/* BANK */
-	size = ((cr & AT91RM9200_SDRAMC_NB) ? 4 : 2) << size;
-	/* bandwidth */
-	if (!(mr & AT91RM9200_SDRAMC_DBW))
-		size <<= 1;
-
-	return size;
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_st.h b/arch/arm/mach-at91/include/mach/at91rm9200_st.h
deleted file mode 100644
index 67bcfaa13b..0000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_st.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2005 Ivan Kokshaysky */
-/* SPDX-FileCopyrightText: SAN People */
-
-/*
- * arch/arm/mach-at91/include/mach/at91_st.h
- *
- * System Timer (ST) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- */
-
-#ifndef AT91RM9200_ST_H
-#define AT91RM9200_ST_H
-
-#define	AT91RM9200_ST_CR		(0x00)	/* Control Register */
-#define 	AT91RM9200_ST_WDRST		(1 << 0)		/* Watchdog Timer Restart */
-
-#define	AT91RM9200_ST_PIMR		(0x04)	/* Period Interval Mode Register */
-#define		AT91RM9200_ST_PIV		(0xffff <<  0)		/* Period Interval Value */
-
-#define	AT91RM9200_ST_WDMR		(0x08)	/* Watchdog Mode Register */
-#define		AT91RM9200_ST_WDV		(0xffff <<  0)		/* Watchdog Counter Value */
-#define		AT91RM9200_ST_RSTEN		(1	<< 16)		/* Reset Enable */
-#define		AT91RM9200_ST_EXTEN		(1	<< 17)		/* External Signal Assertion Enable */
-
-#define	AT91RM9200_ST_RTMR		(0x0c)	/* Real-time Mode Register */
-#define		AT91RM9200_ST_RTPRES		(0xffff <<  0)		/* Real-time Prescalar Value */
-
-#define	AT91RM9200_ST_SR		(0x10)	/* Status Register */
-#define		AT91RM9200_ST_PITS		(1 << 0)		/* Period Interval Timer Status */
-#define		AT91RM9200_ST_WDOVF		(1 << 1) 		/* Watchdog Overflow */
-#define		AT91RM9200_ST_RTTINC		(1 << 2) 		/* Real-time Timer Increment */
-#define		AT91RM9200_ST_ALMS		(1 << 3) 		/* Alarm Status */
-
-#define	AT91RM9200_ST_IER		(0x14)	/* Interrupt Enable Register */
-#define	AT91RM9200_ST_IDR		(0x18)	/* Interrupt Disable Register */
-#define	AT91RM9200_ST_IMR		(0x1c)	/* Interrupt Mask Register */
-
-#define	AT91RM9200_ST_RTAR		(0x20)	/* Real-time Alarm Register */
-#define		AT91RM9200_ST_ALMV		(0xfffff << 0)		/* Alarm Value */
-
-#define	AT91RM9200_ST_CRTR		(0x24)	/* Current Real-time Register */
-#define		AT91RM9200_ST_CRTV		(0xfffff << 0)		/* Current Real-Time Value */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
deleted file mode 100644
index 1375872ce2..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2006 Andrew Victor */
-
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h]
- *
- * Common definitions.
- * Based on AT91SAM9260 datasheet revision A (Preliminary).
- */
-
-#ifndef AT91SAM9260_H
-#define AT91SAM9260_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9260_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9260_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9260_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91SAM9260_ID_ADC	5	/* Analog-to-Digital Converter */
-#define AT91SAM9260_ID_US0	6	/* USART 0 */
-#define AT91SAM9260_ID_US1	7	/* USART 1 */
-#define AT91SAM9260_ID_US2	8	/* USART 2 */
-#define AT91SAM9260_ID_MCI	9	/* Multimedia Card Interface */
-#define AT91SAM9260_ID_UDP	10	/* USB Device Port */
-#define AT91SAM9260_ID_TWI	11	/* Two-Wire Interface */
-#define AT91SAM9260_ID_SPI0	12	/* Serial Peripheral Interface 0 */
-#define AT91SAM9260_ID_SPI1	13	/* Serial Peripheral Interface 1 */
-#define AT91SAM9260_ID_SSC	14	/* Serial Synchronous Controller */
-#define AT91SAM9260_ID_TC0	17	/* Timer Counter 0 */
-#define AT91SAM9260_ID_TC1	18	/* Timer Counter 1 */
-#define AT91SAM9260_ID_TC2	19	/* Timer Counter 2 */
-#define AT91SAM9260_ID_UHP	20	/* USB Host port */
-#define AT91SAM9260_ID_EMAC	21	/* Ethernet */
-#define AT91SAM9260_ID_ISI	22	/* Image Sensor Interface */
-#define AT91SAM9260_ID_US3	23	/* USART 3 */
-#define AT91SAM9260_ID_US4	24	/* USART 4 */
-#define AT91SAM9260_ID_US5	25	/* USART 5 */
-#define AT91SAM9260_ID_TC3	26	/* Timer Counter 3 */
-#define AT91SAM9260_ID_TC4	27	/* Timer Counter 4 */
-#define AT91SAM9260_ID_TC5	28	/* Timer Counter 5 */
-#define AT91SAM9260_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9260_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9260_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9260_BASE_TCB0		0xfffa0000
-#define AT91SAM9260_BASE_TC0		0xfffa0000
-#define AT91SAM9260_BASE_TC1		0xfffa0040
-#define AT91SAM9260_BASE_TC2		0xfffa0080
-#define AT91SAM9260_BASE_UDP		0xfffa4000
-#define AT91SAM9260_BASE_MCI		0xfffa8000
-#define AT91SAM9260_BASE_TWI		0xfffac000
-#define AT91SAM9260_BASE_US0		0xfffb0000
-#define AT91SAM9260_BASE_US1		0xfffb4000
-#define AT91SAM9260_BASE_US2		0xfffb8000
-#define AT91SAM9260_BASE_SSC		0xfffbc000
-#define AT91SAM9260_BASE_ISI		0xfffc0000
-#define AT91SAM9260_BASE_EMAC		0xfffc4000
-#define AT91SAM9260_BASE_SPI0		0xfffc8000
-#define AT91SAM9260_BASE_SPI1		0xfffcc000
-#define AT91SAM9260_BASE_US3		0xfffd0000
-#define AT91SAM9260_BASE_US4		0xfffd4000
-#define AT91SAM9260_BASE_US5		0xfffd8000
-#define AT91SAM9260_BASE_TCB1		0xfffdc000
-#define AT91SAM9260_BASE_TC3		0xfffdc000
-#define AT91SAM9260_BASE_TC4		0xfffdc040
-#define AT91SAM9260_BASE_TC5		0xfffdc080
-#define AT91SAM9260_BASE_ADC		0xfffe0000
-
-/*
- * System Peripherals
- */
-#define AT91SAM9260_BASE_ECC	0xffffe800
-#define AT91SAM9260_BASE_SDRAMC	0xffffea00
-#define AT91SAM9260_BASE_SMC	0xffffec00
-#define AT91SAM9260_BASE_MATRIX	0xffffee00
-#define AT91SAM9260_BASE_DBGU	AT91_BASE_DBGU0
-#define AT91SAM9260_BASE_PIOA	0xfffff400
-#define AT91SAM9260_BASE_PIOB	0xfffff600
-#define AT91SAM9260_BASE_PIOC	0xfffff800
-#define AT91SAM9260_BASE_RSTC	0xfffffd00
-#define AT91SAM9260_BASE_SHDWC	0xfffffd10
-#define AT91SAM9260_BASE_RTT	0xfffffd20
-#define AT91SAM9260_BASE_PIT	0xfffffd30
-#define AT91SAM9260_BASE_WDT	0xfffffd40
-#define AT91SAM9260_BASE_GPBR	0xfffffd50
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9260_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91SAM9260_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
-
-#define AT91SAM9260_SRAM0_BASE	0x00200000	/* Internal SRAM 0 base address */
-#define AT91SAM9260_SRAM0_SIZE	SZ_4K		/* Internal SRAM 0 size (4Kb) */
-#define AT91SAM9260_SRAM1_BASE	0x00300000	/* Internal SRAM 1 base address */
-#define AT91SAM9260_SRAM1_SIZE	SZ_4K		/* Internal SRAM 1 size (4Kb) */
-#define AT91SAM9260_SRAM_BASE	0x002FF000	/* Internal SRAM base address */
-#define AT91SAM9260_SRAM_SIZE	SZ_8K		/* Internal SRAM size (8Kb) */
-
-#define AT91SAM9260_UHP_BASE	0x00500000	/* USB Host controller */
-
-#define AT91SAM9XE_FLASH_BASE	0x00200000	/* Internal FLASH base address */
-#define AT91SAM9XE_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-
-#define AT91SAM9G20_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91SAM9G20_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
-
-#define AT91SAM9G20_SRAM0_BASE	0x00200000	/* Internal SRAM 0 base address */
-#define AT91SAM9G20_SRAM0_SIZE	SZ_16K		/* Internal SRAM 0 size (16Kb) */
-#define AT91SAM9G20_SRAM1_BASE	0x00300000	/* Internal SRAM 1 base address */
-#define AT91SAM9G20_SRAM1_SIZE	SZ_16K		/* Internal SRAM 1 size (16Kb) */
-#define AT91SAM9G20_SRAM_BASE	0x002FC000	/* Internal SRAM base address */
-#define AT91SAM9G20_SRAM_SIZE	SZ_32K		/* Internal SRAM size (32Kb) */
-
-#define AT91SAM9G20_UHP_BASE	0x00500000	/* USB Host controller */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
deleted file mode 100644
index fb5e76bb51..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2007 Atmel Corporation */
-
-/*
- * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9260 datasheet revision B.
- */
-
-#ifndef AT91SAM9260_MATRIX_H
-#define AT91SAM9260_MATRIX_H
-
-#define AT91SAM9260_MATRIX_MCFG0	(0x00)	/* Master Configuration Register 0 */
-#define AT91SAM9260_MATRIX_MCFG1	(0x04)	/* Master Configuration Register 1 */
-#define AT91SAM9260_MATRIX_MCFG2	(0x08)	/* Master Configuration Register 2 */
-#define AT91SAM9260_MATRIX_MCFG3	(0x0C)	/* Master Configuration Register 3 */
-#define AT91SAM9260_MATRIX_MCFG4	(0x10)	/* Master Configuration Register 4 */
-#define AT91SAM9260_MATRIX_MCFG5	(0x14)	/* Master Configuration Register 5 */
-#define		AT91SAM9260_MATRIX_ULBT		(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91SAM9260_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91SAM9260_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91SAM9260_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91SAM9260_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91SAM9260_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91SAM9260_MATRIX_SCFG0	(0x40)	/* Slave Configuration Register 0 */
-#define AT91SAM9260_MATRIX_SCFG1	(0x44)	/* Slave Configuration Register 1 */
-#define AT91SAM9260_MATRIX_SCFG2	(0x48)	/* Slave Configuration Register 2 */
-#define AT91SAM9260_MATRIX_SCFG3	(0x4C)	/* Slave Configuration Register 3 */
-#define AT91SAM9260_MATRIX_SCFG4	(0x50)	/* Slave Configuration Register 4 */
-#define		AT91SAM9260_MATRIX_SLOT_CYCLE		(0xff <<  0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91SAM9260_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91SAM9260_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91SAM9260_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91SAM9260_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91SAM9260_MATRIX_FIXED_DEFMSTR	(7    << 18)	/* Fixed Index of Default Master */
-#define		AT91SAM9260_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91SAM9260_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91SAM9260_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91SAM9260_MATRIX_PRAS0	(0x80)	/* Priority Register A for Slave 0 */
-#define AT91SAM9260_MATRIX_PRAS1	(0x88)	/* Priority Register A for Slave 1 */
-#define AT91SAM9260_MATRIX_PRAS2	(0x90)	/* Priority Register A for Slave 2 */
-#define AT91SAM9260_MATRIX_PRAS3	(0x98)	/* Priority Register A for Slave 3 */
-#define AT91SAM9260_MATRIX_PRAS4	(0xA0)	/* Priority Register A for Slave 4 */
-#define		AT91SAM9260_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91SAM9260_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91SAM9260_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91SAM9260_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91SAM9260_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91SAM9260_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-
-#define AT91SAM9260_MATRIX_MRCR	(0x100)	/* Master Remap Control Register */
-#define		AT91SAM9260_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91SAM9260_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-
-#define AT91SAM9260_MATRIX_EBICSA	(0x11C)	/* EBI Chip Select Assignment Register */
-#define		AT91SAM9260_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91SAM9260_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91SAM9260_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91SAM9260_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91SAM9260_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91SAM9260_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91SAM9260_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91SAM9260_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91SAM9260_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91SAM9260_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91SAM9260_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91SAM9260_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91SAM9260_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91SAM9260_MATRIX_VDDIOMSEL		(1 << 16)	/* Memory voltage selection */
-#define			AT91SAM9260_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define			AT91SAM9260_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
deleted file mode 100644
index fa42907473..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: SAN People */
-
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
- *
- * Common definitions.
- * Based on AT91SAM9261 datasheet revision E. (Preliminary)
- */
-
-#ifndef AT91SAM9261_H
-#define AT91SAM9261_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9261_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9261_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9261_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91SAM9261_ID_US0	6	/* USART 0 */
-#define AT91SAM9261_ID_US1	7	/* USART 1 */
-#define AT91SAM9261_ID_US2	8	/* USART 2 */
-#define AT91SAM9261_ID_MCI	9	/* Multimedia Card Interface */
-#define AT91SAM9261_ID_UDP	10	/* USB Device Port */
-#define AT91SAM9261_ID_TWI	11	/* Two-Wire Interface */
-#define AT91SAM9261_ID_SPI0	12	/* Serial Peripheral Interface 0 */
-#define AT91SAM9261_ID_SPI1	13	/* Serial Peripheral Interface 1 */
-#define AT91SAM9261_ID_SSC0	14	/* Serial Synchronous Controller 0 */
-#define AT91SAM9261_ID_SSC1	15	/* Serial Synchronous Controller 1 */
-#define AT91SAM9261_ID_SSC2	16	/* Serial Synchronous Controller 2 */
-#define AT91SAM9261_ID_TC0	17	/* Timer Counter 0 */
-#define AT91SAM9261_ID_TC1	18	/* Timer Counter 1 */
-#define AT91SAM9261_ID_TC2	19	/* Timer Counter 2 */
-#define AT91SAM9261_ID_UHP	20	/* USB Host port */
-#define AT91SAM9261_ID_LCDC	21	/* LDC Controller */
-#define AT91SAM9261_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9261_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9261_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9261_BASE_TCB0		0xfffa0000
-#define AT91SAM9261_BASE_TC0		0xfffa0000
-#define AT91SAM9261_BASE_TC1		0xfffa0040
-#define AT91SAM9261_BASE_TC2		0xfffa0080
-#define AT91SAM9261_BASE_UDP		0xfffa4000
-#define AT91SAM9261_BASE_MCI		0xfffa8000
-#define AT91SAM9261_BASE_TWI		0xfffac000
-#define AT91SAM9261_BASE_US0		0xfffb0000
-#define AT91SAM9261_BASE_US1		0xfffb4000
-#define AT91SAM9261_BASE_US2		0xfffb8000
-#define AT91SAM9261_BASE_SSC0		0xfffbc000
-#define AT91SAM9261_BASE_SSC1		0xfffc0000
-#define AT91SAM9261_BASE_SSC2		0xfffc4000
-#define AT91SAM9261_BASE_SPI0		0xfffc8000
-#define AT91SAM9261_BASE_SPI1		0xfffcc000
-
-
-/*
- * System Peripherals
- */
-#define AT91SAM9261_BASE_SMC	0xffffec00
-#define AT91SAM9261_BASE_MATRIX	0xffffee00
-#define AT91SAM9261_BASE_SDRAMC	0xffffea00
-#define AT91SAM9261_BASE_DBGU	AT91_BASE_DBGU0
-#define AT91SAM9261_BASE_PIOA	0xfffff400
-#define AT91SAM9261_BASE_PIOB	0xfffff600
-#define AT91SAM9261_BASE_PIOC	0xfffff800
-#define AT91SAM9261_BASE_RSTC	0xfffffd00
-#define AT91SAM9261_BASE_SHDWC	0xfffffd10
-#define AT91SAM9261_BASE_RTT	0xfffffd20
-#define AT91SAM9261_BASE_PIT	0xfffffd30
-#define AT91SAM9261_BASE_WDT	0xfffffd40
-#define AT91SAM9261_BASE_GPBR	0xfffffd50
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9261_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define AT91SAM9261_SRAM_SIZE	0x00028000	/* Internal SRAM size (160Kb) */
-
-#define AT91SAM9G10_SRAM_BASE	AT91SAM9261_SRAM_BASE	/* Internal SRAM base address */
-#define AT91SAM9G10_SRAM_SIZE	0x00004000	/* Internal SRAM size (16Kb) */
-
-#define AT91SAM9261_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91SAM9261_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
-
-#define AT91SAM9261_UHP_BASE	0x00500000	/* USB Host controller */
-#define AT91SAM9261_LCDC_BASE	0x00600000	/* LDC controller */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
deleted file mode 100644
index dda9cef945..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2007 Atmel Corporation */
-
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- */
-
-#ifndef AT91SAM9261_MATRIX_H
-#define AT91SAM9261_MATRIX_H
-
-#define AT91SAM9261_MATRIX_MCFG	(0x00)	/* Master Configuration Register */
-#define		AT91SAM9261_MATRIX_RCB0	(1 << 0)		/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91SAM9261_MATRIX_RCB1	(1 << 1)		/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-
-#define AT91SAM9261_MATRIX_SCFG0	(0x04)	/* Slave Configuration Register 0 */
-#define AT91SAM9261_MATRIX_SCFG1	(0x08)	/* Slave Configuration Register 1 */
-#define AT91SAM9261_MATRIX_SCFG2	(0x0C)	/* Slave Configuration Register 2 */
-#define AT91SAM9261_MATRIX_SCFG3	(0x10)	/* Slave Configuration Register 3 */
-#define AT91SAM9261_MATRIX_SCFG4	(0x14)	/* Slave Configuration Register 4 */
-#define		AT91SAM9261_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91SAM9261_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91SAM9261_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91SAM9261_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91SAM9261_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91SAM9261_MATRIX_FIXED_DEFMSTR	(7    << 18)	/* Fixed Index of Default Master */
-
-#define AT91SAM9261_MATRIX_TCR		(0x24)	/* TCM Configuration Register */
-#define		AT91SAM9261_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91SAM9261_MATRIX_ITCM_0		(0 << 0)
-#define			AT91SAM9261_MATRIX_ITCM_16		(5 << 0)
-#define			AT91SAM9261_MATRIX_ITCM_32		(6 << 0)
-#define			AT91SAM9261_MATRIX_ITCM_64		(7 << 0)
-#define		AT91SAM9261_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91SAM9261_MATRIX_DTCM_0		(0 << 4)
-#define			AT91SAM9261_MATRIX_DTCM_16		(5 << 4)
-#define			AT91SAM9261_MATRIX_DTCM_32		(6 << 4)
-#define			AT91SAM9261_MATRIX_DTCM_64		(7 << 4)
-
-#define AT91SAM9261_MATRIX_EBICSA	(0x30)	/* EBI Chip Select Assignment Register */
-#define		AT91SAM9261_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91SAM9261_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91SAM9261_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91SAM9261_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91SAM9261_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91SAM9261_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91SAM9261_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91SAM9261_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91SAM9261_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91SAM9261_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91SAM9261_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91SAM9261_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91SAM9261_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-
-#define AT91SAM9261_MATRIX_USBPUCR	(0x34)	/* USB Pad Pull-Up Control Register */
-#define		AT91SAM9261_MATRIX_USBPUCR_PUON	(1 << 30)	/* USB Device PAD Pull-up Enable */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
deleted file mode 100644
index 2ea9aadafa..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2007 Atmel Corporation */
-
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
- *
- * Common definitions.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- */
-
-#ifndef AT91SAM9263_H
-#define AT91SAM9263_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9263_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9263_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9263_ID_PIOCDE	4	/* Parallel IO Controller C, D and E */
-#define AT91SAM9263_ID_US0	7	/* USART 0 */
-#define AT91SAM9263_ID_US1	8	/* USART 1 */
-#define AT91SAM9263_ID_US2	9	/* USART 2 */
-#define AT91SAM9263_ID_MCI0	10	/* Multimedia Card Interface 0 */
-#define AT91SAM9263_ID_MCI1	11	/* Multimedia Card Interface 1 */
-#define AT91SAM9263_ID_CAN	12	/* CAN */
-#define AT91SAM9263_ID_TWI	13	/* Two-Wire Interface */
-#define AT91SAM9263_ID_SPI0	14	/* Serial Peripheral Interface 0 */
-#define AT91SAM9263_ID_SPI1	15	/* Serial Peripheral Interface 1 */
-#define AT91SAM9263_ID_SSC0	16	/* Serial Synchronous Controller 0 */
-#define AT91SAM9263_ID_SSC1	17	/* Serial Synchronous Controller 1 */
-#define AT91SAM9263_ID_AC97C	18	/* AC97 Controller */
-#define AT91SAM9263_ID_TCB	19	/* Timer Counter 0, 1 and 2 */
-#define AT91SAM9263_ID_PWMC	20	/* Pulse Width Modulation Controller */
-#define AT91SAM9263_ID_EMAC	21	/* Ethernet */
-#define AT91SAM9263_ID_2DGE	23	/* 2D Graphic Engine */
-#define AT91SAM9263_ID_UDP	24	/* USB Device Port */
-#define AT91SAM9263_ID_ISI	25	/* Image Sensor Interface */
-#define AT91SAM9263_ID_LCDC	26	/* LCD Controller */
-#define AT91SAM9263_ID_DMA	27	/* DMA Controller */
-#define AT91SAM9263_ID_UHP	29	/* USB Host port */
-#define AT91SAM9263_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9263_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9263_BASE_UDP		0xfff78000
-#define AT91SAM9263_BASE_TCB0		0xfff7c000
-#define AT91SAM9263_BASE_TC0		0xfff7c000
-#define AT91SAM9263_BASE_TC1		0xfff7c040
-#define AT91SAM9263_BASE_TC2		0xfff7c080
-#define AT91SAM9263_BASE_MCI0		0xfff80000
-#define AT91SAM9263_BASE_MCI1		0xfff84000
-#define AT91SAM9263_BASE_TWI		0xfff88000
-#define AT91SAM9263_BASE_US0		0xfff8c000
-#define AT91SAM9263_BASE_US1		0xfff90000
-#define AT91SAM9263_BASE_US2		0xfff94000
-#define AT91SAM9263_BASE_SSC0		0xfff98000
-#define AT91SAM9263_BASE_SSC1		0xfff9c000
-#define AT91SAM9263_BASE_AC97C		0xfffa0000
-#define AT91SAM9263_BASE_SPI0		0xfffa4000
-#define AT91SAM9263_BASE_SPI1		0xfffa8000
-#define AT91SAM9263_BASE_CAN		0xfffac000
-#define AT91SAM9263_BASE_PWMC		0xfffb8000
-#define AT91SAM9263_BASE_EMAC		0xfffbc000
-#define AT91SAM9263_BASE_ISI		0xfffc4000
-#define AT91SAM9263_BASE_2DGE		0xfffc8000
-
-
-/*
- * System Peripherals
- */
-#define AT91SAM9263_BASE_ECC0	0xffffe000
-#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
-#define AT91SAM9263_BASE_SMC0	0xffffe400
-#define AT91SAM9263_BASE_ECC1	0xffffe600
-#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
-#define AT91SAM9263_BASE_SMC1	0xffffea00
-#define AT91SAM9263_BASE_MATRIX	0xffffec00
-#define AT91SAM9263_BASE_DBGU	AT91_BASE_DBGU1
-#define AT91SAM9263_BASE_PIOA	0xfffff200
-#define AT91SAM9263_BASE_PIOB	0xfffff400
-#define AT91SAM9263_BASE_PIOC	0xfffff600
-#define AT91SAM9263_BASE_PIOD	0xfffff800
-#define AT91SAM9263_BASE_PIOE	0xfffffa00
-#define AT91SAM9263_BASE_RSTC	0xfffffd00
-#define AT91SAM9263_BASE_SHDWC	0xfffffd10
-#define AT91SAM9263_BASE_RTT0	0xfffffd20
-#define AT91SAM9263_BASE_PIT	0xfffffd30
-#define AT91SAM9263_BASE_WDT	0xfffffd40
-#define AT91SAM9263_BASE_RTT1	0xfffffd50
-#define AT91SAM9263_BASE_GPBR	0xfffffd60
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9263_SRAM0_BASE	0x00300000	/* Internal SRAM 0 base address */
-#define AT91SAM9263_SRAM0_SIZE	(80 * SZ_1K)	/* Internal SRAM 0 size (80Kb) */
-
-#define AT91SAM9263_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91SAM9263_ROM_SIZE	SZ_128K		/* Internal ROM size (128Kb) */
-
-#define AT91SAM9263_SRAM1_BASE	0x00500000	/* Internal SRAM 1 base address */
-#define AT91SAM9263_SRAM1_SIZE	SZ_16K		/* Internal SRAM 1 size (16Kb) */
-
-#define AT91SAM9263_LCDC_BASE	0x00700000	/* LCD Controller */
-#define AT91SAM9263_DMAC_BASE	0x00800000	/* DMA Controller */
-#define AT91SAM9263_UHP_BASE	0x00a00000	/* USB Host controller */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
deleted file mode 100644
index 2f10ce096e..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2006 Atmel Corporation */
-
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h]
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- */
-
-#ifndef AT91SAM9263_MATRIX_H
-#define AT91SAM9263_MATRIX_H
-
-#define AT91SAM9263_MATRIX_MCFG0	(0x00)	/* Master Configuration Register 0 */
-#define AT91SAM9263_MATRIX_MCFG1	(0x04)	/* Master Configuration Register 1 */
-#define AT91SAM9263_MATRIX_MCFG2	(0x08)	/* Master Configuration Register 2 */
-#define AT91SAM9263_MATRIX_MCFG3	(0x0C)	/* Master Configuration Register 3 */
-#define AT91SAM9263_MATRIX_MCFG4	(0x10)	/* Master Configuration Register 4 */
-#define AT91SAM9263_MATRIX_MCFG5	(0x14)	/* Master Configuration Register 5 */
-#define AT91SAM9263_MATRIX_MCFG6	(0x18)	/* Master Configuration Register 6 */
-#define AT91SAM9263_MATRIX_MCFG7	(0x1C)	/* Master Configuration Register 7 */
-#define AT91SAM9263_MATRIX_MCFG8	(0x20)	/* Master Configuration Register 8 */
-#define		AT91SAM9263_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91SAM9263_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91SAM9263_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91SAM9263_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91SAM9263_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91SAM9263_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91SAM9263_MATRIX_SCFG0	(0x40)	/* Slave Configuration Register 0 */
-#define AT91SAM9263_MATRIX_SCFG1	(0x44)	/* Slave Configuration Register 1 */
-#define AT91SAM9263_MATRIX_SCFG2	(0x48)	/* Slave Configuration Register 2 */
-#define AT91SAM9263_MATRIX_SCFG3	(0x4C)	/* Slave Configuration Register 3 */
-#define AT91SAM9263_MATRIX_SCFG4	(0x50)	/* Slave Configuration Register 4 */
-#define AT91SAM9263_MATRIX_SCFG5	(0x54)	/* Slave Configuration Register 5 */
-#define AT91SAM9263_MATRIX_SCFG6	(0x58)	/* Slave Configuration Register 6 */
-#define AT91SAM9263_MATRIX_SCFG7	(0x5C)	/* Slave Configuration Register 7 */
-#define		AT91SAM9263_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91SAM9263_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91SAM9263_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91SAM9263_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91SAM9263_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
-#define		AT91SAM9263_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91SAM9263_MATRIX_PRAS0	(0x80)	/* Priority Register A for Slave 0 */
-#define AT91SAM9263_MATRIX_PRBS0	(0x84)	/* Priority Register B for Slave 0 */
-#define AT91SAM9263_MATRIX_PRAS1	(0x88)	/* Priority Register A for Slave 1 */
-#define AT91SAM9263_MATRIX_PRBS1	(0x8C)	/* Priority Register B for Slave 1 */
-#define AT91SAM9263_MATRIX_PRAS2	(0x90)	/* Priority Register A for Slave 2 */
-#define AT91SAM9263_MATRIX_PRBS2	(0x94)	/* Priority Register B for Slave 2 */
-#define AT91SAM9263_MATRIX_PRAS3	(0x98)	/* Priority Register A for Slave 3 */
-#define AT91SAM9263_MATRIX_PRBS3	(0x9C)	/* Priority Register B for Slave 3 */
-#define AT91SAM9263_MATRIX_PRAS4	(0xA0)	/* Priority Register A for Slave 4 */
-#define AT91SAM9263_MATRIX_PRBS4	(0xA4)	/* Priority Register B for Slave 4 */
-#define AT91SAM9263_MATRIX_PRAS5	(0xA8)	/* Priority Register A for Slave 5 */
-#define AT91SAM9263_MATRIX_PRBS5	(0xAC)	/* Priority Register B for Slave 5 */
-#define AT91SAM9263_MATRIX_PRAS6	(0xB0)	/* Priority Register A for Slave 6 */
-#define AT91SAM9263_MATRIX_PRBS6	(0xB4)	/* Priority Register B for Slave 6 */
-#define AT91SAM9263_MATRIX_PRAS7	(0xB8)	/* Priority Register A for Slave 7 */
-#define AT91SAM9263_MATRIX_PRBS7	(0xBC)	/* Priority Register B for Slave 7 */
-#define		AT91SAM9263_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91SAM9263_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91SAM9263_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91SAM9263_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91SAM9263_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91SAM9263_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-#define		AT91SAM9263_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
-#define		AT91SAM9263_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
-#define		AT91SAM9263_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
-
-#define AT91SAM9263_MATRIX_MRCR	(0x100)	/* Master Remap Control Register */
-#define		AT91SAM9263_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91SAM9263_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91SAM9263_MATRIX_RCB2		(1 << 2)
-#define		AT91SAM9263_MATRIX_RCB3		(1 << 3)
-#define		AT91SAM9263_MATRIX_RCB4		(1 << 4)
-#define		AT91SAM9263_MATRIX_RCB5		(1 << 5)
-#define		AT91SAM9263_MATRIX_RCB6		(1 << 6)
-#define		AT91SAM9263_MATRIX_RCB7		(1 << 7)
-#define		AT91SAM9263_MATRIX_RCB8		(1 << 8)
-
-#define AT91SAM9263_MATRIX_TCMR	(0x114)	/* TCM Configuration Register */
-#define		AT91SAM9263_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91SAM9263_MATRIX_ITCM_0		(0 << 0)
-#define			AT91SAM9263_MATRIX_ITCM_16		(5 << 0)
-#define			AT91SAM9263_MATRIX_ITCM_32		(6 << 0)
-#define		AT91SAM9263_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91SAM9263_MATRIX_DTCM_0		(0 << 4)
-#define			AT91SAM9263_MATRIX_DTCM_16		(5 << 4)
-#define			AT91SAM9263_MATRIX_DTCM_32		(6 << 4)
-
-#define AT91SAM9263_MATRIX_EBI0CSA	(0x120)	/* EBI0 Chip Select Assignment Register */
-#define		AT91SAM9263_MATRIX_EBI0_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91SAM9263_MATRIX_EBI0_CS1A_SMC		(0 << 1)
-#define			AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC		(1 << 1)
-#define		AT91SAM9263_MATRIX_EBI0_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91SAM9263_MATRIX_EBI0_CS3A_SMC		(0 << 3)
-#define			AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91SAM9263_MATRIX_EBI0_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91SAM9263_MATRIX_EBI0_CS4A_SMC		(0 << 4)
-#define			AT91SAM9263_MATRIX_EBI0_CS4A_SMC_CF1		(1 << 4)
-#define		AT91SAM9263_MATRIX_EBI0_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91SAM9263_MATRIX_EBI0_CS5A_SMC		(0 << 5)
-#define			AT91SAM9263_MATRIX_EBI0_CS5A_SMC_CF2		(1 << 5)
-#define		AT91SAM9263_MATRIX_EBI0_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91SAM9263_MATRIX_EBI0_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V		(1 << 16)
-
-#define AT91SAM9263_MATRIX_EBI1CSA	(0x124)	/* EBI1 Chip Select Assignment Register */
-#define		AT91SAM9263_MATRIX_EBI1_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91SAM9263_MATRIX_EBI1_CS1A_SMC		(0 << 1)
-#define			AT91SAM9263_MATRIX_EBI1_CS1A_SDRAMC		(1 << 1)
-#define		AT91SAM9263_MATRIX_EBI1_CS2A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91SAM9263_MATRIX_EBI1_CS2A_SMC		(0 << 3)
-#define			AT91SAM9263_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91SAM9263_MATRIX_EBI1_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91SAM9263_MATRIX_EBI1_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_3_3V		(1 << 16)
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x.h b/arch/arm/mach-at91/include/mach/at91sam926x.h
deleted file mode 100644
index ab5cf515ef..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam926x.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __MACH_AT91SAM926X_H
-#define __MACH_AT91SAM926X_H
-
-#define AT91SAM926X_BASE_PMC	0xfffffc00
-#define AT91SAM926X_BASE_RSTC	0xfffffd00
-#define AT91SAM926X_BASE_WDT	0xfffffd40
-
-#endif /* __MACH_AT91SAM926X_H */
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
deleted file mode 100644
index 3dab64b71a..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ /dev/null
@@ -1,204 +0,0 @@
-#ifndef __AT91SAM926X_BOARD_INIT_H__
-#define __AT91SAM926X_BOARD_INIT_H__
-/*
- * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
- * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2
- */
-
-#include <common.h>
-#include <init.h>
-
-#include <mach/at91sam9_sdramc.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_rstc.h>
-#include <mach/at91_pio.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_wdt.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <mach/at91sam926x.h>
-
-struct at91sam926x_board_cfg {
-	/* SoC specific */
-	void __iomem *pio;
-	void __iomem *sdramc;
-	u32 ebi_pio_is_peripha;
-	void __iomem *matrix_csa;
-
-	/* board specific */
-	u32 wdt_mr;
-	u32 ebi_pio_pdr;
-	u32 ebi_pio_ppudr;
-	u32 ebi_csa;
-	u32 smc_cs;
-	u32 smc_mode;
-	u32 smc_cycle;
-	u32 smc_pulse;
-	u32 smc_setup;
-	u32 pmc_mor;
-	u32 pmc_pllar;
-	u32 pmc_mckr1;
-	u32 pmc_mckr2;
-	u32 sdrc_cr;
-	u32 sdrc_tr1;
-	u32 sdrc_mdr;
-	u32 sdrc_tr2;
-	u32 rstc_rmr;
-};
-
-
-static void __always_inline access_sdram(void)
-{
-	writel(0x00000000, AT91_CHIPSELECT_1);
-}
-
-static void __always_inline pmc_check_mckrdy(void)
-{
-	u32 r;
-
-	do {
-		r = readl(AT91SAM926X_BASE_PMC + AT91_PMC_SR);
-	} while (!(r & AT91_PMC_MCKRDY));
-}
-
-static int __always_inline running_in_sram(void)
-{
-	u32 addr = get_pc();
-
-	addr >>= 28;
-	return addr == 0;
-}
-
-static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg *cfg)
-{
-	u32 r;
-	int i;
-	int in_sram = running_in_sram();
-
-	/* SDRAMC Check if Refresh Timer Counter is already initialized */
-	r = readl(cfg->sdramc + AT91_SDRAMC_TR);
-	if (r && !in_sram)
-		return;
-
-	/* SDRAMC_MR : Normal Mode */
-	writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
-
-	/* SDRAMC_TR - Refresh Timer register */
-	writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR);
-
-	/* SDRAMC_CR - Configuration register*/
-	writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR);
-
-	/* Memory Device Type */
-	writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR);
-
-	/* SDRAMC_MR : Precharge All */
-	writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR);
-	access_sdram();
-
-	/* SDRAMC_MR : refresh */
-	writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR);
-
-	/* access SDRAM 8 times */
-	for (i = 0; i < 8; i++)
-		access_sdram();
-
-	/* SDRAMC_MR : Load Mode Register */
-	writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR);
-	access_sdram();
-
-	/* SDRAMC_MR : Normal Mode */
-	writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
-	access_sdram();
-
-	/* SDRAMC_TR : Refresh Timer Counter */
-	writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR);
-	access_sdram();
-}
-
-static void __always_inline at91sam926x_board_init(void __iomem *smcbase,
-						   struct at91sam926x_board_cfg *cfg)
-{
-	u32 r;
-	void __iomem *pmc = IOMEM(AT91SAM926X_BASE_PMC);
-
-	if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT))
-		return;
-
-	writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR);
-
-	/* configure PIOx as EBI0 D[16-31] */
-	at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr);
-	at91_mux_set_pullup(cfg->pio, cfg->ebi_pio_ppudr, true);
-	if (cfg->ebi_pio_is_peripha)
-		at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr);
-
-	writel(cfg->ebi_csa, cfg->matrix_csa);
-
-	/* flash */
-	writel(cfg->smc_mode, smcbase + cfg->smc_cs * 0x10 + AT91_SAM9_SMC_MODE);
-	writel(cfg->smc_cycle, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_CYCLE);
-	writel(cfg->smc_pulse, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_PULSE);
-	writel(cfg->smc_setup, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_SETUP);
-
-	/* PMC Check if the PLL is already initialized */
-	r = readl(pmc + AT91_PMC_MCKR);
-	if ((r & AT91_PMC_CSS) && !running_in_sram())
-		return;
-
-	/* Enable the Main Oscillator */
-	writel(cfg->pmc_mor, pmc + AT91_CKGR_MOR);
-	do {
-		r = readl(pmc + AT91_PMC_SR);
-	} while (!(r & AT91_PMC_MOSCS));
-
-	/* PLLAR: x MHz for PCK */
-	writel(cfg->pmc_pllar, pmc + AT91_CKGR_PLLAR);
-	do {
-		r = readl(pmc + AT91_PMC_SR);
-	} while (!(r & AT91_PMC_LOCKA));
-
-	/* PCK/x = MCK Master Clock from SLOW */
-	writel(cfg->pmc_mckr1, pmc + AT91_PMC_MCKR);
-	pmc_check_mckrdy();
-
-	/* PCK/x = MCK Master Clock from PLLA */
-	writel(cfg->pmc_mckr2, pmc + AT91_PMC_MCKR);
-	pmc_check_mckrdy();
-
-	/* Init SDRAM */
-	at91sam926x_sdramc_init(cfg);
-
-	/* User reset enable*/
-	writel(cfg->rstc_rmr, AT91SAM926X_BASE_RSTC + AT91_RSTC_MR);
-
-	/*
-	 * When boot from external boot
-	 * we need to enable mck and ohter clock
-	 * so enable all of them
-	 * We will shutdown what we don't need later
-	 */
-	writel(0xffffffff, pmc + AT91_PMC_PCER);
-}
-
-#include <mach/at91sam9260.h>
-static void __always_inline at91sam9260_board_init(struct at91sam926x_board_cfg *cfg)
-{
-	at91sam926x_board_init(IOMEM(AT91SAM9260_BASE_SMC), cfg);
-}
-
-#include <mach/at91sam9261.h>
-static void __always_inline at91sam9261_board_init(struct at91sam926x_board_cfg *cfg)
-{
-	at91sam926x_board_init(IOMEM(AT91SAM9261_BASE_SMC), cfg);
-}
-
-#include <mach/at91sam9263.h>
-static void __always_inline at91sam9263_board_init(struct at91sam926x_board_cfg *cfg)
-{
-	at91sam926x_board_init(IOMEM(AT91SAM9263_BASE_SMC0), cfg);
-}
-
-#endif /* __AT91SAM926X_BOARD_INIT_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
deleted file mode 100644
index 80effe2148..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */
-/* SPDX-FileCopyrightText: 2007 Andrew Victor */
-/* SPDX-FileCopyrightText: 2007 Atmel Corporation */
-
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
- *
- * SDRAM Controllers (SDRAMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- */
-
-#ifndef AT91SAM9_SDRAMC_H
-#define AT91SAM9_SDRAMC_H
-
-/* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR		0x00	/* SDRAM Controller Mode Register */
-#define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
-#define			AT91_SDRAMC_MODE_NORMAL		0
-#define			AT91_SDRAMC_MODE_NOP		1
-#define			AT91_SDRAMC_MODE_PRECHARGE	2
-#define			AT91_SDRAMC_MODE_LMR		3
-#define			AT91_SDRAMC_MODE_REFRESH	4
-#define			AT91_SDRAMC_MODE_EXT_LMR	5
-#define			AT91_SDRAMC_MODE_DEEP		6
-
-#define AT91_SDRAMC_TR		0x04	/* SDRAM Controller Refresh Timer Register */
-#define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
-
-#define AT91_SDRAMC_CR		0x08	/* SDRAM Controller Configuration Register */
-#define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
-#define			AT91_SDRAMC_NC_8	(0 << 0)
-#define			AT91_SDRAMC_NC_9	(1 << 0)
-#define			AT91_SDRAMC_NC_10	(2 << 0)
-#define			AT91_SDRAMC_NC_11	(3 << 0)
-#define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
-#define			AT91_SDRAMC_NR_11	(0 << 2)
-#define			AT91_SDRAMC_NR_12	(1 << 2)
-#define			AT91_SDRAMC_NR_13	(2 << 2)
-#define		AT91_SDRAMC_NB		(1 << 4)		/* Number of Banks */
-#define			AT91_SDRAMC_NB_2	(0 << 4)
-#define			AT91_SDRAMC_NB_4	(1 << 4)
-#define		AT91_SDRAMC_CAS		(3 << 5)		/* CAS Latency */
-#define			AT91_SDRAMC_CAS_1	(1 << 5)
-#define			AT91_SDRAMC_CAS_2	(2 << 5)
-#define			AT91_SDRAMC_CAS_3	(3 << 5)
-#define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
-#define			AT91_SDRAMC_DBW_32	(0 << 7)
-#define			AT91_SDRAMC_DBW_16	(1 << 7)
-#define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
-#define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
-#define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
-#define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
-#define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
-#define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_LPR		0x10	/* SDRAM Controller Low Power Register */
-#define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
-#define			AT91_SDRAMC_LPCB_DISABLE		0
-#define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
-#define			AT91_SDRAMC_LPCB_POWER_DOWN		2
-#define			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
-#define		AT91_SDRAMC_PASR		(7 << 4)	/* Partial Array Self Refresh */
-#define		AT91_SDRAMC_TCSR		(3 << 8)	/* Temperature Compensated Self Refresh */
-#define		AT91_SDRAMC_DS			(3 << 10)	/* Drive Strength */
-#define		AT91_SDRAMC_TIMEOUT		(3 << 12)	/* Time to define when Low Power Mode is enabled */
-#define			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	(0 << 12)
-#define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
-#define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
-
-#define AT91_SDRAMC_IER		0x14	/* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR		0x18	/* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR		0x1C	/* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR		0x20	/* SDRAM Controller Interrupt Status Register */
-#define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
-
-#define AT91_SDRAMC_MDR		0x24	/* SDRAM Memory Device Register */
-#define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
-#define			AT91_SDRAMC_MD_SDRAM		0
-#define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
-
-#ifndef __ASSEMBLY__
-#include <io.h>
-static inline u32 at91_get_sdram_size(void *base)
-{
-	u32 val;
-	u32 size;
-
-	val = readl(base + AT91_SDRAMC_CR);
-
-	/* Formula:
-	 * size = bank << (col + row + 1);
-	 * if (bandwidth == 32 bits)
-	 *	size <<= 1;
-	 */
-	size = 1;
-	/* COL */
-	size += (val & AT91_SDRAMC_NC) + 8;
-	/* ROW */
-	size += ((val & AT91_SDRAMC_NR) >> 2) + 11;
-	/* BANK */
-	size = ((val & AT91_SDRAMC_NB) ? 4 : 2) << size;
-	/* bandwidth */
-	if (!(val & AT91_SDRAMC_DBW))
-		size <<= 1;
-
-	return size;
-}
-
-
-static inline bool at91_is_low_power_sdram(void *base)
-{
-	return readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM;
-}
-
-#ifdef CONFIG_SOC_AT91SAM9260
-#include <mach/at91sam9260.h>
-static inline u32 at91sam9260_get_sdram_size(void)
-{
-	return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC));
-}
-
-static inline bool at91sam9260_is_low_power_sdram(void)
-{
-	return at91_is_low_power_sdram(IOMEM(AT91SAM9260_BASE_SDRAMC));
-}
-#else
-static inline u32 at91sam9260_get_sdram_size(void)
-{
-	return 0;
-}
-
-static inline bool at91sam9260_is_low_power_sdram(void)
-{
-	return false;
-}
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9261
-#include <mach/at91sam9261.h>
-static inline u32 at91sam9261_get_sdram_size(void)
-{
-	return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC));
-}
-
-static inline bool at91sam9261_is_low_power_sdram(void)
-{
-	return at91_is_low_power_sdram(IOMEM(AT91SAM9261_BASE_SDRAMC));
-}
-#else
-static inline u32 at91sam9261_get_sdram_size(void)
-{
-	return 0;
-}
-
-static inline bool at91sam9261_is_low_power_sdram(void)
-{
-	return false;
-}
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9263
-#include <mach/at91sam9263.h>
-static inline u32 at91sam9263_get_sdram_size(int bank)
-{
-	switch (bank) {
-	case 0:
-		return at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC0));
-	case 1:
-		return at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC1));
-	default:
-		return 0;
-	}
-}
-
-static inline bool at91sam9263_is_low_power_sdram(int bank)
-{
-	switch (bank) {
-	case 0:
-		return at91_is_low_power_sdram(IOMEM(AT91SAM9263_BASE_SDRAMC0));
-	case 1:
-		return at91_is_low_power_sdram(IOMEM(AT91SAM9263_BASE_SDRAMC1));
-	default:
-		return false;
-	}
-}
-#else
-static inline u32 at91sam9263_get_sdram_size(int bank)
-{
-	return 0;
-}
-
-static inline bool at91sam9263_is_low_power_sdram(void)
-{
-	return false;
-}
-#endif
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
deleted file mode 100644
index d23ea52bce..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2007 Andrew Victor */
-/* SPDX-FileCopyrightText: 2007 Atmel Corporation */
-
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
- *
- * Static Memory Controllers (SMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- */
-
-#ifndef AT91SAM9_SMC_H
-#define AT91SAM9_SMC_H
-
-#ifndef __ASSEMBLY__
-struct sam9_smc_config {
-	/* Setup register */
-	u8 ncs_read_setup;
-	u8 nrd_setup;
-	u8 ncs_write_setup;
-	u8 nwe_setup;
-
-	/* Pulse register */
-	u8 ncs_read_pulse;
-	u8 nrd_pulse;
-	u8 ncs_write_pulse;
-	u8 nwe_pulse;
-
-	/* Cycle register */
-	u16 read_cycle;
-	u16 write_cycle;
-
-	/* Mode register */
-	u32 mode;
-	u8 tdf_cycles:4;
-
-	/* Timings register */
-	u8 tclr;
-	u8 tadl;
-	u8 tar;
-	u8 ocms;
-	u8 trr;
-	u8 twb;
-	u8 rbnsel;
-	u8 nfsel;
-};
-
-extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
-extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
-extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
-extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
-
-extern void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config);
-#endif
-
-#define AT91_SMC_SETUP		0x00				/* Setup Register for CS n */
-#define		AT91_SMC_NWESETUP	(0x3f << 0)			/* NWE Setup Length */
-#define			AT91_SMC_NWESETUP_(x)	((x) << 0)
-#define		AT91_SMC_NCS_WRSETUP	(0x3f << 8)			/* NCS Setup Length in Write Access */
-#define			AT91_SMC_NCS_WRSETUP_(x)	((x) << 8)
-#define		AT91_SMC_NRDSETUP	(0x3f << 16)			/* NRD Setup Length */
-#define			AT91_SMC_NRDSETUP_(x)	((x) << 16)
-#define		AT91_SMC_NCS_RDSETUP	(0x3f << 24)			/* NCS Setup Length in Read Access */
-#define			AT91_SMC_NCS_RDSETUP_(x)	((x) << 24)
-
-#define AT91_SMC_PULSE		0x04				/* Pulse Register for CS n */
-#define		AT91_SMC_NWEPULSE	(0x7f <<  0)			/* NWE Pulse Length */
-#define			AT91_SMC_NWEPULSE_(x)	((x) << 0)
-#define		AT91_SMC_NCS_WRPULSE	(0x7f <<  8)			/* NCS Pulse Length in Write Access */
-#define			AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define		AT91_SMC_NRDPULSE	(0x7f << 16)			/* NRD Pulse Length */
-#define			AT91_SMC_NRDPULSE_(x)	((x) << 16)
-#define		AT91_SMC_NCS_RDPULSE	(0x7f << 24)			/* NCS Pulse Length in Read Access */
-#define			AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE		0x08				/* Cycle Register for CS n */
-#define		AT91_SMC_NWECYCLE	(0x1ff << 0 )			/* Total Write Cycle Length */
-#define			AT91_SMC_NWECYCLE_(x)	((x) << 0)
-#define		AT91_SMC_NRDCYCLE	(0x1ff << 16)			/* Total Read Cycle Length */
-#define			AT91_SMC_NRDCYCLE_(x)	((x) << 16)
-
-#define AT91_SAMA5_SMC_TIMINGS	0x0c				/* Timings register for CS n */
-#define		AT91_SMC_TCLR		(0x0f  <<  0)			/* CLE to REN Low Delay */
-#define			AT91_SMC_TCLR_(x)	((x) << 0)
-#define		AT91_SMC_TADL		(0x0f  <<  4)			/* ALE to Data Start */
-#define			AT91_SMC_TADL_(x)	((x) << 4)
-#define		AT91_SMC_TAR		(0x0f  <<  8)			/* ALE to REN Low Delay */
-#define			AT91_SMC_TAR_(x)	((x) << 8)
-#define		AT91_SMC_OCMS		(0x1   << 12)			/* Off Chip Memory Scrambling Enable */
-#define			AT91_SMC_OCMS_(x)	((x) << 12)
-#define		AT91_SMC_TRR		(0x0f  << 16)			/* Ready to REN Low Delay */
-#define			AT91_SMC_TRR_(x)        ((x) << 16)
-#define		AT91_SMC_TWB		(0x0f  << 24)			/* WEN High to REN to Busy */
-#define			AT91_SMC_TWB_(x)	((x) << 24)
-#define		AT91_SMC_RBNSEL		(0x07  << 28)			/* Ready/Busy Line Selection */
-#define			AT91_SMC_RBNSEL_(x)	((x) << 28)
-#define		AT91_SMC_NFSEL		(0x01  << 31)			/* Nand Flash Selection */
-#define			AT91_SMC_NFSEL_(x)	((x) << 31)
-
-#define AT91_SAM9_SMC_MODE 0xc
-#define AT91_SAMA5_SMC_MODE 0x10
-#define		AT91_SMC_READMODE	(1 <<  0)			/* Read Mode */
-#define		AT91_SMC_WRITEMODE	(1 <<  1)			/* Write Mode */
-#define		AT91_SMC_EXNWMODE	(3 <<  4)			/* NWAIT Mode */
-#define			AT91_SMC_EXNWMODE_DISABLE	(0 << 4)
-#define			AT91_SMC_EXNWMODE_FROZEN	(2 << 4)
-#define			AT91_SMC_EXNWMODE_READY		(3 << 4)
-#define		AT91_SMC_BAT		(1 <<  8)			/* Byte Access Type */
-#define			AT91_SMC_BAT_SELECT		(0 << 8)
-#define			AT91_SMC_BAT_WRITE		(1 << 8)
-#define		AT91_SMC_DBW		(3 << 12)			/* Data Bus Width */
-#define			AT91_SMC_DBW_8			(0 << 12)
-#define			AT91_SMC_DBW_16			(1 << 12)
-#define			AT91_SMC_DBW_32			(2 << 12)
-#define		AT91_SMC_TDF		(0xf << 16)			/* Data Float Time. */
-#define			AT91_SMC_TDF_(x)		((x) << 16)
-#define		AT91_SMC_TDFMODE	(1 << 20)			/* TDF Optimization - Enabled */
-#define		AT91_SMC_PMEN		(1 << 24)			/* Page Mode Enabled */
-#define		AT91_SMC_PS		(3 << 28)			/* Page Size */
-#define			AT91_SMC_PS_4			(0 << 28)
-#define			AT91_SMC_PS_8			(1 << 28)
-#define			AT91_SMC_PS_16			(2 << 28)
-#define			AT91_SMC_PS_32			(3 << 28)
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
deleted file mode 100644
index d7596930d2..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2008-2009 Atmel Corporation */
-
-/*
- * Chip-specific header file for the AT91SAM9G45 family
- *
- * Common definitions.
- * Based on AT91SAM9G45 preliminary datasheet.
- */
-
-#ifndef AT91SAM9G45_H
-#define AT91SAM9G45_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9G45_ID_PIOA	2	/* Parallel I/O Controller A */
-#define AT91SAM9G45_ID_PIOB	3	/* Parallel I/O Controller B */
-#define AT91SAM9G45_ID_PIOC	4	/* Parallel I/O Controller C */
-#define AT91SAM9G45_ID_PIODE	5	/* Parallel I/O Controller D and E */
-#define AT91SAM9G45_ID_TRNG	6	/* True Random Number Generator */
-#define AT91SAM9G45_ID_US0	7	/* USART 0 */
-#define AT91SAM9G45_ID_US1	8	/* USART 1 */
-#define AT91SAM9G45_ID_US2	9	/* USART 2 */
-#define AT91SAM9G45_ID_US3	10	/* USART 3 */
-#define AT91SAM9G45_ID_MCI0	11	/* High Speed Multimedia Card Interface 0 */
-#define AT91SAM9G45_ID_TWI0	12	/* Two-Wire Interface 0 */
-#define AT91SAM9G45_ID_TWI1	13	/* Two-Wire Interface 1 */
-#define AT91SAM9G45_ID_SPI0	14	/* Serial Peripheral Interface 0 */
-#define AT91SAM9G45_ID_SPI1	15	/* Serial Peripheral Interface 1 */
-#define AT91SAM9G45_ID_SSC0	16	/* Synchronous Serial Controller 0 */
-#define AT91SAM9G45_ID_SSC1	17	/* Synchronous Serial Controller 1 */
-#define AT91SAM9G45_ID_TCB	18	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9G45_ID_PWMC	19	/* Pulse Width Modulation Controller */
-#define AT91SAM9G45_ID_TSC	20	/* Touch Screen ADC Controller */
-#define AT91SAM9G45_ID_DMA	21	/* DMA Controller */
-#define AT91SAM9G45_ID_UHPHS	22	/* USB Host High Speed */
-#define AT91SAM9G45_ID_LCDC	23	/* LCD Controller */
-#define AT91SAM9G45_ID_AC97C	24	/* AC97 Controller */
-#define AT91SAM9G45_ID_EMAC	25	/* Ethernet MAC */
-#define AT91SAM9G45_ID_ISI	26	/* Image Sensor Interface */
-#define AT91SAM9G45_ID_UDPHS	27	/* USB Device High Speed */
-#define AT91SAM9G45_ID_AESTDESSHA 28	/* AES + T-DES + SHA */
-#define AT91SAM9G45_ID_MCI1	29	/* High Speed Multimedia Card Interface 1 */
-#define AT91SAM9G45_ID_VDEC	30	/* Video Decoder */
-#define AT91SAM9G45_ID_IRQ0	31	/* Advanced Interrupt Controller */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9G45_BASE_UDPHS		0xfff78000
-#define AT91SAM9G45_BASE_TCB0		0xfff7c000
-#define AT91SAM9G45_BASE_TC0		0xfff7c000
-#define AT91SAM9G45_BASE_TC1		0xfff7c040
-#define AT91SAM9G45_BASE_TC2		0xfff7c080
-#define AT91SAM9G45_BASE_MCI0		0xfff80000
-#define AT91SAM9G45_BASE_TWI0		0xfff84000
-#define AT91SAM9G45_BASE_TWI1		0xfff88000
-#define AT91SAM9G45_BASE_US0		0xfff8c000
-#define AT91SAM9G45_BASE_US1		0xfff90000
-#define AT91SAM9G45_BASE_US2		0xfff94000
-#define AT91SAM9G45_BASE_US3		0xfff98000
-#define AT91SAM9G45_BASE_SSC0		0xfff9c000
-#define AT91SAM9G45_BASE_SSC1		0xfffa0000
-#define AT91SAM9G45_BASE_SPI0		0xfffa4000
-#define AT91SAM9G45_BASE_SPI1		0xfffa8000
-#define AT91SAM9G45_BASE_AC97C		0xfffac000
-#define AT91SAM9G45_BASE_TSC		0xfffb0000
-#define AT91SAM9G45_BASE_ISI		0xfffb4000
-#define AT91SAM9G45_BASE_PWMC		0xfffb8000
-#define AT91SAM9G45_BASE_EMAC		0xfffbc000
-#define AT91SAM9G45_BASE_AES		0xfffc0000
-#define AT91SAM9G45_BASE_TDES		0xfffc4000
-#define AT91SAM9G45_BASE_SHA		0xfffc8000
-#define AT91SAM9G45_BASE_TRNG		0xfffcc000
-#define AT91SAM9G45_BASE_MCI1		0xfffd0000
-#define AT91SAM9G45_BASE_TCB1		0xfffd4000
-#define AT91SAM9G45_BASE_TC3		0xfffd4000
-#define AT91SAM9G45_BASE_TC4		0xfffd4040
-#define AT91SAM9G45_BASE_TC5		0xfffd4080
-
-/*
- * System Peripherals
- */
-#define AT91SAM9G45_BASE_ECC	0xffffe200
-#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
-#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
-#define AT91SAM9G45_BASE_DMA	0xffffec00
-#define AT91SAM9G45_BASE_SMC	0xffffe800
-#define AT91SAM9G45_BASE_MATRIX	0xffffea00
-#define AT91SAM9G45_BASE_DBGU	AT91_BASE_DBGU1
-#define AT91SAM9G45_BASE_PIOA	0xfffff200
-#define AT91SAM9G45_BASE_PIOB	0xfffff400
-#define AT91SAM9G45_BASE_PIOC	0xfffff600
-#define AT91SAM9G45_BASE_PIOD	0xfffff800
-#define AT91SAM9G45_BASE_PIOE	0xfffffa00
-#define AT91SAM9G45_BASE_RSTC	0xfffffd00
-#define AT91SAM9G45_BASE_SHDWC	0xfffffd10
-#define AT91SAM9G45_BASE_RTT	0xfffffd20
-#define AT91SAM9G45_BASE_PIT	0xfffffd30
-#define AT91SAM9G45_BASE_WDT	0xfffffd40
-#define AT91SAM9G45_BASE_RTC	0xfffffdb0
-#define AT91SAM9G45_BASE_GPBR	0xfffffd60
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9G45_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define AT91SAM9G45_SRAM_SIZE	SZ_64K		/* Internal SRAM size (64Kb) */
-
-#define AT91SAM9G45_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91SAM9G45_ROM_SIZE	SZ_64K		/* Internal ROM size (64Kb) */
-
-#define AT91SAM9G45_LCDC_BASE	0x00500000	/* LCD Controller */
-#define AT91SAM9G45_UDPHS_FIFO	0x00600000	/* USB Device HS controller */
-#define AT91SAM9G45_OHCI_BASE	0x00700000	/* USB Host controller (OHCI) */
-#define AT91SAM9G45_EHCI_BASE	0x00800000	/* USB Host controller (EHCI) */
-#define AT91SAM9G45_VDEC_BASE	0x00900000	/* Video Decoder Controller */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
deleted file mode 100644
index 239e11df3d..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2008-2009 Atmel Corporation */
-
-/*
- * Matrix-centric header file for the AT91SAM9G45 family
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9G45 preliminary datasheet.
- */
-
-#ifndef AT91SAM9G45_MATRIX_H
-#define AT91SAM9G45_MATRIX_H
-
-#define AT91SAM9G45_MATRIX_MCFG0	(0x00)	/* Master Configuration Register 0 */
-#define AT91SAM9G45_MATRIX_MCFG1	(0x04)	/* Master Configuration Register 1 */
-#define AT91SAM9G45_MATRIX_MCFG2	(0x08)	/* Master Configuration Register 2 */
-#define AT91SAM9G45_MATRIX_MCFG3	(0x0C)	/* Master Configuration Register 3 */
-#define AT91SAM9G45_MATRIX_MCFG4	(0x10)	/* Master Configuration Register 4 */
-#define AT91SAM9G45_MATRIX_MCFG5	(0x14)	/* Master Configuration Register 5 */
-#define AT91SAM9G45_MATRIX_MCFG6	(0x18)	/* Master Configuration Register 6 */
-#define AT91SAM9G45_MATRIX_MCFG7	(0x1C)	/* Master Configuration Register 7 */
-#define AT91SAM9G45_MATRIX_MCFG8	(0x20)	/* Master Configuration Register 8 */
-#define AT91SAM9G45_MATRIX_MCFG9	(0x24)	/* Master Configuration Register 9 */
-#define AT91SAM9G45_MATRIX_MCFG10	(0x28)	/* Master Configuration Register 10 */
-#define AT91SAM9G45_MATRIX_MCFG11	(0x2C)	/* Master Configuration Register 11 */
-#define		AT91SAM9G45_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91SAM9G45_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91SAM9G45_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91SAM9G45_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91SAM9G45_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91SAM9G45_MATRIX_ULBT_SIXTEEN	(4 << 0)
-#define			AT91SAM9G45_MATRIX_ULBT_THIRTYTWO	(5 << 0)
-#define			AT91SAM9G45_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
-#define			AT91SAM9G45_MATRIX_ULBT_128		(7 << 0)
-
-#define AT91SAM9G45_MATRIX_SCFG0	(0x40)	/* Slave Configuration Register 0 */
-#define AT91SAM9G45_MATRIX_SCFG1	(0x44)	/* Slave Configuration Register 1 */
-#define AT91SAM9G45_MATRIX_SCFG2	(0x48)	/* Slave Configuration Register 2 */
-#define AT91SAM9G45_MATRIX_SCFG3	(0x4C)	/* Slave Configuration Register 3 */
-#define AT91SAM9G45_MATRIX_SCFG4	(0x50)	/* Slave Configuration Register 4 */
-#define AT91SAM9G45_MATRIX_SCFG5	(0x54)	/* Slave Configuration Register 5 */
-#define AT91SAM9G45_MATRIX_SCFG6	(0x58)	/* Slave Configuration Register 6 */
-#define AT91SAM9G45_MATRIX_SCFG7	(0x5C)	/* Slave Configuration Register 7 */
-#define		AT91SAM9G45_MATRIX_SLOT_CYCLE		(0x1ff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91SAM9G45_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91SAM9G45_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91SAM9G45_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91SAM9G45_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91SAM9G45_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
-
-#define AT91SAM9G45_MATRIX_PRAS0	(0x80)	/* Priority Register A for Slave 0 */
-#define AT91SAM9G45_MATRIX_PRBS0	(0x84)	/* Priority Register B for Slave 0 */
-#define AT91SAM9G45_MATRIX_PRAS1	(0x88)	/* Priority Register A for Slave 1 */
-#define AT91SAM9G45_MATRIX_PRBS1	(0x8C)	/* Priority Register B for Slave 1 */
-#define AT91SAM9G45_MATRIX_PRAS2	(0x90)	/* Priority Register A for Slave 2 */
-#define AT91SAM9G45_MATRIX_PRBS2	(0x94)	/* Priority Register B for Slave 2 */
-#define AT91SAM9G45_MATRIX_PRAS3	(0x98)	/* Priority Register A for Slave 3 */
-#define AT91SAM9G45_MATRIX_PRBS3	(0x9C)	/* Priority Register B for Slave 3 */
-#define AT91SAM9G45_MATRIX_PRAS4	(0xA0)	/* Priority Register A for Slave 4 */
-#define AT91SAM9G45_MATRIX_PRBS4	(0xA4)	/* Priority Register B for Slave 4 */
-#define AT91SAM9G45_MATRIX_PRAS5	(0xA8)	/* Priority Register A for Slave 5 */
-#define AT91SAM9G45_MATRIX_PRBS5	(0xAC)	/* Priority Register B for Slave 5 */
-#define AT91SAM9G45_MATRIX_PRAS6	(0xB0)	/* Priority Register A for Slave 6 */
-#define AT91SAM9G45_MATRIX_PRBS6	(0xB4)	/* Priority Register B for Slave 6 */
-#define AT91SAM9G45_MATRIX_PRAS7	(0xB8)	/* Priority Register A for Slave 7 */
-#define AT91SAM9G45_MATRIX_PRBS7	(0xBC)	/* Priority Register B for Slave 7 */
-#define		AT91SAM9G45_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91SAM9G45_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91SAM9G45_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91SAM9G45_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91SAM9G45_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91SAM9G45_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-#define		AT91SAM9G45_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
-#define		AT91SAM9G45_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
-#define		AT91SAM9G45_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
-#define		AT91SAM9G45_MATRIX_M9PR		(3 << 4)	/* Master 9 Priority (in Register B) */
-#define		AT91SAM9G45_MATRIX_M10PR		(3 << 8)	/* Master 10 Priority (in Register B) */
-#define		AT91SAM9G45_MATRIX_M11PR		(3 << 12)	/* Master 11 Priority (in Register B) */
-
-#define AT91SAM9G45_MATRIX_MRCR	(0x100)	/* Master Remap Control Register */
-#define		AT91SAM9G45_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91SAM9G45_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91SAM9G45_MATRIX_RCB2		(1 << 2)
-#define		AT91SAM9G45_MATRIX_RCB3		(1 << 3)
-#define		AT91SAM9G45_MATRIX_RCB4		(1 << 4)
-#define		AT91SAM9G45_MATRIX_RCB5		(1 << 5)
-#define		AT91SAM9G45_MATRIX_RCB6		(1 << 6)
-#define		AT91SAM9G45_MATRIX_RCB7		(1 << 7)
-#define		AT91SAM9G45_MATRIX_RCB8		(1 << 8)
-#define		AT91SAM9G45_MATRIX_RCB9		(1 << 9)
-#define		AT91SAM9G45_MATRIX_RCB10		(1 << 10)
-#define		AT91SAM9G45_MATRIX_RCB11		(1 << 11)
-
-#define AT91SAM9G45_MATRIX_TCMR	(0x110)	/* TCM Configuration Register */
-#define		AT91SAM9G45_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91SAM9G45_MATRIX_ITCM_0		(0 << 0)
-#define			AT91SAM9G45_MATRIX_ITCM_32		(6 << 0)
-#define		AT91SAM9G45_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91SAM9G45_MATRIX_DTCM_0		(0 << 4)
-#define			AT91SAM9G45_MATRIX_DTCM_32		(6 << 4)
-#define			AT91SAM9G45_MATRIX_DTCM_64		(7 << 4)
-#define		AT91SAM9G45_MATRIX_TCM_NWS		(0x1 << 11)	/* Wait state TCM register */
-#define			AT91SAM9G45_MATRIX_TCM_NO_WS		(0x0 << 11)
-#define			AT91SAM9G45_MATRIX_TCM_ONE_WS		(0x1 << 11)
-
-#define AT91SAM9G45_MATRIX_VIDEO	(0x118)	/* Video Mode Configuration Register */
-#define		AT91C_VDEC_SEL			(0x1 <<  0) /* Video Mode Selection */
-#define			AT91C_VDEC_SEL_OFF		(0 << 0)
-#define			AT91C_VDEC_SEL_ON		(1 << 0)
-
-#define AT91SAM9G45_MATRIX_EBICSA	(0x128)	/* EBI Chip Select Assignment Register */
-#define		AT91SAM9G45_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91SAM9G45_MATRIX_EBI_CS1A_SMC		(0 << 1)
-#define			AT91SAM9G45_MATRIX_EBI_CS1A_SDRAMC		(1 << 1)
-#define		AT91SAM9G45_MATRIX_EBI_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91SAM9G45_MATRIX_EBI_CS3A_SMC		(0 << 3)
-#define			AT91SAM9G45_MATRIX_EBI_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91SAM9G45_MATRIX_EBI_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91SAM9G45_MATRIX_EBI_CS4A_SMC		(0 << 4)
-#define			AT91SAM9G45_MATRIX_EBI_CS4A_SMC_CF0		(1 << 4)
-#define		AT91SAM9G45_MATRIX_EBI_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91SAM9G45_MATRIX_EBI_CS5A_SMC		(0 << 5)
-#define			AT91SAM9G45_MATRIX_EBI_CS5A_SMC_CF1		(1 << 5)
-#define		AT91SAM9G45_MATRIX_EBI_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define			AT91SAM9G45_MATRIX_EBI_DBPU_ON			(0 << 8)
-#define			AT91SAM9G45_MATRIX_EBI_DBPU_OFF		(1 << 8)
-#define		AT91SAM9G45_MATRIX_EBI_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_3_3V		(1 << 16)
-#define		AT91SAM9G45_MATRIX_EBI_EBI_IOSR	(1 << 17)	/* EBI I/O slew rate selection */
-#define			AT91SAM9G45_MATRIX_EBI_EBI_IOSR_REDUCED	(0 << 17)
-#define			AT91SAM9G45_MATRIX_EBI_EBI_IOSR_NORMAL		(1 << 17)
-#define		AT91SAM9G45_MATRIX_EBI_DDR_IOSR	(1 << 18)	/* DDR2 dedicated port I/O slew rate selection */
-#define			AT91SAM9G45_MATRIX_EBI_DDR_IOSR_REDUCED	(0 << 18)
-#define			AT91SAM9G45_MATRIX_EBI_DDR_IOSR_NORMAL		(1 << 18)
-
-#define AT91SAM9G45_MATRIX_WPMR	(0x1E4)	/* Write Protect Mode Register */
-#define		AT91SAM9G45_MATRIX_WPMR_WPEN		(1 << 0)	/* Write Protect ENable */
-#define			AT91SAM9G45_MATRIX_WPMR_WP_WPDIS		(0 << 0)
-#define			AT91SAM9G45_MATRIX_WPMR_WP_WPEN		(1 << 0)
-#define		AT91SAM9G45_MATRIX_WPMR_WPKEY		(0xFFFFFF << 8)	/* Write Protect KEY */
-
-#define AT91SAM9G45_MATRIX_WPSR	(0x1E8)	/* Write Protect Status Register */
-#define		AT91SAM9G45_MATRIX_WPSR_WPVS		(1 << 0)	/* Write Protect Violation Status */
-#define			AT91SAM9G45_MATRIX_WPSR_NO_WPV		(0 << 0)
-#define			AT91SAM9G45_MATRIX_WPSR_WPV		(1 << 0)
-#define		AT91SAM9G45_MATRIX_WPSR_WPVSRC		(0xFFFF << 8)	/* Write Protect Violation Source */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
deleted file mode 100644
index b68a529b05..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2011 Atmel Corporation */
-
-/*
- * Chip-specific header file for the AT91SAM9N12 SoC
- *
- * Common definitions.
- * Based on AT91SAM9N12 preliminary datasheet
- */
-
-#ifndef __MACH_AT91SAM9N12_H_
-#define __MACH_AT91SAM9N12_H_
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9N12_ID_PIOAB	2	/* Parallel I/O Controller A and B */
-#define AT91SAM9N12_ID_PIOCD	3	/* Parallel I/O Controller C and D */
-/* Reserved			4	*/
-#define AT91SAM9N12_ID_USART0	5	/* USART 0 */
-#define AT91SAM9N12_ID_USART1	6	/* USART 1 */
-#define AT91SAM9N12_ID_USART2	7	/* USART 2 */
-#define AT91SAM9N12_ID_USART3	8	/* USART 3 */
-#define AT91SAM9N12_ID_TWI0	9	/* Two-Wire Interface 0 */
-#define AT91SAM9N12_ID_TWI1	10	/* Two-Wire Interface 1 */
-/* Reserved			11	*/
-#define AT91SAM9N12_ID_MCI	12	/* High Speed Multimedia Card Interface 0 */
-#define AT91SAM9N12_ID_SPI0	13	/* Serial Peripheral Interface 0 */
-#define AT91SAM9N12_ID_SPI1	14	/* Serial Peripheral Interface 1 */
-#define AT91SAM9N12_ID_UART0	15	/* UART 0 */
-#define AT91SAM9N12_ID_UART1	16	/* UART 1 */
-#define AT91SAM9N12_ID_TCB	17	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9N12_ID_PWM	18	/* Pulse Width Modulation Controller */
-#define AT91SAM9N12_ID_ADC	19	/* ADC Controller */
-#define AT91SAM9N12_ID_DMA	20	/* DMA Controller 0 */
-/* Reserved			21	*/
-#define AT91SAM9N12_ID_UHPFS	22	/* USB Host Full Speed */
-#define AT91SAM9N12_ID_UDPFS	23	/* USB Device Full Speed */
-/* Reserved			24	*/
-#define AT91SAM9N12_ID_LCDC	25	/* LCD Controller */
-/* Reserved			26	*/
-/* Reserved			27	*/
-#define AT91SAM9N12_ID_SSC	28	/* Synchronous Serial Controller */
-/* Reserved			29	*/
-#define AT91SAM9N12_ID_TRNG	30	/* True Random Number Generator */
-#define AT91SAM9N12_ID_IRQ0	31	/* Advanced Interrupt Controller */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9N12_BASE_SPI0		0xf0000000
-#define AT91SAM9N12_BASE_SPI1		0xf0004000
-#define AT91SAM9N12_BASE_MCI		0xf0008000
-#define AT91SAM9N12_BASE_SSC		0xf0010000
-#define AT91SAM9N12_BASE_TCB0		0xf8008000
-#define AT91SAM9N12_BASE_TC0		0xf8008000
-#define AT91SAM9N12_BASE_TC1		0xf8008040
-#define AT91SAM9N12_BASE_TC2		0xf8008080
-#define AT91SAM9N12_BASE_TCB1		0xf800c000
-#define AT91SAM9N12_BASE_TC3		0xf800c000
-#define AT91SAM9N12_BASE_TC4		0xf800c040
-#define AT91SAM9N12_BASE_TC5		0xf800c080
-#define AT91SAM9N12_BASE_TWI0		0xf8010000
-#define AT91SAM9N12_BASE_TWI1		0xf8014000
-#define AT91SAM9N12_BASE_USART0		0xf801c000
-#define AT91SAM9N12_BASE_USART1		0xf8020000
-#define AT91SAM9N12_BASE_USART2		0xf8024000
-#define AT91SAM9N12_BASE_USART3		0xf8028000
-#define AT91SAM9N12_BASE_PWMC		0xf8034000
-#define AT91SAM9N12_BASE_LCDC		0xf8038000
-#define AT91SAM9N12_BASE_UDPFS		0xf803c000
-#define AT91SAM9N12_BASE_UART0		0xf8040000
-#define AT91SAM9N12_BASE_UART1		0xf8044000
-#define AT91SAM9N12_BASE_TRNG		0xf8048000
-#define AT91SAM9N12_BASE_ADC		0xf804c000
-
-/*
- * System Peripherals
- */
-#define AT91SAM9N12_BASE_FUSE		0xffffdc00
-#define AT91SAM9N12_BASE_MATRIX		0xffffde00
-#define AT91SAM9N12_BASE_PMECC		0xffffe000
-#define AT91SAM9N12_BASE_PMERRLOC	0xffffe600
-#define AT91SAM9N12_BASE_DDRSDRC0	0xffffe800
-#define AT91SAM9N12_BASE_SMC		0xffffea00
-#define AT91SAM9N12_BASE_DMA		0xffffec00
-#define AT91SAM9N12_BASE_AIC		0xfffff000
-#define AT91SAM9N12_BASE_DBGU		0xfffff200
-#define AT91SAM9N12_BASE_PIOA		0xfffff400
-#define AT91SAM9N12_BASE_PIOB		0xfffff600
-#define AT91SAM9N12_BASE_PIOC		0xfffff800
-#define AT91SAM9N12_BASE_PIOD		0xfffffa00
-#define AT91SAM9N12_BASE_PMC		0xfffffc00
-#define AT91SAM9N12_BASE_RSTC		0xfffffe00
-#define AT91SAM9N12_BASE_SHDWC		0xfffffe10
-#define AT91SAM9N12_BASE_PIT		0xfffffe30
-#define AT91SAM9N12_BASE_WDT		0xfffffe40
-#define AT91SAM9N12_BASE_GPBR		0xfffffe60
-#define AT91SAM9N12_BASE_RTC		0xfffffeb0
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9N12_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define AT91SAM9N12_SRAM_SIZE	SZ_32K		/* Internal SRAM size (32Kb) */
-
-#define AT91SAM9N12_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91SAM9N12_ROM_SIZE	SZ_1M		/* Internal ROM size (1Mb) */
-
-#define AT91SAM9N12_SMD_BASE	0x00400000	/* SMD Controller */
-#define AT91SAM9N12_OHCI_BASE	0x00500000	/* USB Host controller (OHCI) */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
deleted file mode 100644
index 43f255808f..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2011 Atmel Corporation */
-
-/*
- * Matrix-Centric header file for the AT91SAM9N12 SoC
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9N12 preliminary datasheet.
- */
-
-#ifndef _AT91SAM9N12_MATRIX_H_
-#define _AT91SAM9N12_MATRIX_H_
-
-#define AT91SAM9N12_MATRIX_MCFG0	(0x00)	/* Master Configuration Register 0 */
-#define AT91SAM9N12_MATRIX_MCFG1	(0x04)	/* Master Configuration Register 1 */
-#define AT91SAM9N12_MATRIX_MCFG2	(0x08)	/* Master Configuration Register 2 */
-#define AT91SAM9N12_MATRIX_MCFG3	(0x0C)	/* Master Configuration Register 3 */
-#define AT91SAM9N12_MATRIX_MCFG4	(0x10)	/* Master Configuration Register 4 */
-#define AT91SAM9N12_MATRIX_MCFG5	(0x14)	/* Master Configuration Register 5 */
-#define		AT91SAM9N12_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91SAM9N12_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91SAM9N12_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91SAM9N12_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91SAM9N12_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91SAM9N12_MATRIX_ULBT_SIXTEEN	(4 << 0)
-#define			AT91SAM9N12_MATRIX_ULBT_THIRTYTWO	(5 << 0)
-#define			AT91SAM9N12_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
-#define			AT91SAM9N12_MATRIX_ULBT_128		(7 << 0)
-
-#define AT91SAM9N12_MATRIX_SCFG0	(0x40)	/* Slave Configuration Register 0 */
-#define AT91SAM9N12_MATRIX_SCFG1	(0x44)	/* Slave Configuration Register 1 */
-#define AT91SAM9N12_MATRIX_SCFG2	(0x48)	/* Slave Configuration Register 2 */
-#define AT91SAM9N12_MATRIX_SCFG3	(0x4C)	/* Slave Configuration Register 3 */
-#define AT91SAM9N12_MATRIX_SCFG4	(0x50)	/* Slave Configuration Register 4 */
-#define		AT91SAM9N12_MATRIX_SLOT_CYCLE		(0x1ff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91SAM9N12_MATRIX_DEFMSTR_TYPE	(3 << 16)	/* Default Master Type */
-#define			AT91SAM9N12_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91SAM9N12_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91SAM9N12_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91SAM9N12_MATRIX_FIXED_DEFMSTR	(0xf << 18)	/* Fixed Index of Default Master */
-
-#define AT91SAM9N12_MATRIX_PRAS0	(0x80)	/* Priority Register A for Slave 0 */
-#define AT91SAM9N12_MATRIX_PRAS1	(0x88)	/* Priority Register A for Slave 1 */
-#define AT91SAM9N12_MATRIX_PRAS2	(0x90)	/* Priority Register A for Slave 2 */
-#define AT91SAM9N12_MATRIX_PRAS3	(0x98)	/* Priority Register A for Slave 3 */
-#define AT91SAM9N12_MATRIX_PRAS4	(0xA0)	/* Priority Register A for Slave 4 */
-#define		AT91SAM9N12_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91SAM9N12_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91SAM9N12_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91SAM9N12_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91SAM9N12_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91SAM9N12_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-
-#define AT91SAM9N12_MATRIX_MRCR	(0x100)	/* Master Remap Control Register */
-#define		AT91SAM9N12_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91SAM9N12_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91SAM9N12_MATRIX_RCB2		(1 << 2)
-#define		AT91SAM9N12_MATRIX_RCB3		(1 << 3)
-#define		AT91SAM9N12_MATRIX_RCB4		(1 << 4)
-#define		AT91SAM9N12_MATRIX_RCB5		(1 << 5)
-
-#define AT91SAM9N12_MATRIX_EBICSA	(0x118)	/* EBI Chip Select Assignment Register */
-#define		AT91SAM9N12_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91SAM9N12_MATRIX_EBI_CS1A_SMC		(0 << 1)
-#define			AT91SAM9N12_MATRIX_EBI_CS1A_SDRAMC		(1 << 1)
-#define		AT91SAM9N12_MATRIX_EBI_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91SAM9N12_MATRIX_EBI_CS3A_SMC		(0 << 3)
-#define			AT91SAM9N12_MATRIX_EBI_CS3A_SMC_NANDFLASH	(1 << 3)
-#define		AT91SAM9N12_MATRIX_EBI_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define			AT91SAM9N12_MATRIX_EBI_DBPU_ON			(0 << 8)
-#define			AT91SAM9N12_MATRIX_EBI_DBPU_OFF		(1 << 8)
-#define		AT91SAM9N12_MATRIX_EBI_DBPDC		(1 << 9)	/* Data Bus Pull-up Configuration */
-#define			AT91SAM9N12_MATRIX_EBI_DBPD_ON			(0 << 9)
-#define			AT91SAM9N12_MATRIX_EBI_DBPD_OFF		(1 << 9)
-#define		AT91SAM9N12_MATRIX_EBI_DRIVE		(1 << 17)	/* EBI I/O Drive Configuration */
-#define			AT91SAM9N12_MATRIX_EBI_LOW_DRIVE		(0 << 17)
-#define			AT91SAM9N12_MATRIX_EBI_HIGH_DRIVE		(1 << 17)
-#define		AT91SAM9N12_MATRIX_NFD0_SELECT		(1 << 24)	/* NAND Flash Data Bus Selection */
-#define			AT91SAM9N12_MATRIX_NFD0_ON_D0			(0 << 24)
-#define			AT91SAM9N12_MATRIX_NFD0_ON_D16			(1 << 24)
-
-#define AT91SAM9N12_MATRIX_WPMR	(0x1E4)	/* Write Protect Mode Register */
-#define		AT91SAM9N12_MATRIX_WPMR_WPEN		(1 << 0)	/* Write Protect ENable */
-#define			AT91SAM9N12_MATRIX_WPMR_WP_WPDIS		(0 << 0)
-#define			AT91SAM9N12_MATRIX_WPMR_WP_WPEN		(1 << 0)
-#define		AT91SAM9N12_MATRIX_WPMR_WPKEY		(0xFFFFFF << 8)	/* Write Protect KEY */
-
-#define AT91SAM9N12_MATRIX_WPSR	(0x1E8)	/* Write Protect Status Register */
-#define		AT91SAM9N12_MATRIX_WPSR_WPVS		(1 << 0)	/* Write Protect Violation Status */
-#define			AT91SAM9N12_MATRIX_WPSR_NO_WPV		(0 << 0)
-#define			AT91SAM9N12_MATRIX_WPSR_WPV		(1 << 0)
-#define		AT91SAM9N12_MATRIX_WPSR_WPVSRC		(0xFFFF << 8)	/* Write Protect Violation Source */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
deleted file mode 100644
index 00bef3456a..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2009-2010 Atmel Corporation */
-
-/*
- * Chip-specific header file for the AT91SAM9x5 family
- *
- * Common definitions.
- * Based on AT91SAM9x5 preliminary datasheet.
- */
-
-#ifndef AT91SAM9X5_H
-#define AT91SAM9X5_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9X5_ID_PIOAB	2	/* Parallel I/O Controller A and B */
-#define AT91SAM9X5_ID_PIOCD	3	/* Parallel I/O Controller C and D */
-#define AT91SAM9X5_ID_SMD	4	/* SMD Soft Modem (SMD) */
-#define AT91SAM9X5_ID_USART0	5	/* USART 0 */
-#define AT91SAM9X5_ID_USART1	6	/* USART 1 */
-#define AT91SAM9X5_ID_USART2	7	/* USART 2 */
-#define AT91SAM9X5_ID_USART3	8	/* USART 3 */
-#define AT91SAM9X5_ID_TWI0	9	/* Two-Wire Interface 0 */
-#define AT91SAM9X5_ID_TWI1	10	/* Two-Wire Interface 1 */
-#define AT91SAM9X5_ID_TWI2	11	/* Two-Wire Interface 2 */
-#define AT91SAM9X5_ID_MCI0	12	/* High Speed Multimedia Card Interface 0 */
-#define AT91SAM9X5_ID_SPI0	13	/* Serial Peripheral Interface 0 */
-#define AT91SAM9X5_ID_SPI1	14	/* Serial Peripheral Interface 1 */
-#define AT91SAM9X5_ID_UART0	15	/* UART 0 */
-#define AT91SAM9X5_ID_UART1	16	/* UART 1 */
-#define AT91SAM9X5_ID_TCB	17	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9X5_ID_PWM	18	/* Pulse Width Modulation Controller */
-#define AT91SAM9X5_ID_ADC	19	/* ADC Controller */
-#define AT91SAM9X5_ID_DMA0	20	/* DMA Controller 0 */
-#define AT91SAM9X5_ID_DMA1	21	/* DMA Controller 1 */
-#define AT91SAM9X5_ID_UHPHS	22	/* USB Host High Speed */
-#define AT91SAM9X5_ID_UDPHS	23	/* USB Device High Speed */
-#define AT91SAM9X5_ID_EMAC0	24	/* Ethernet MAC0 */
-#define AT91SAM9X5_ID_LCDC	25	/* LCD Controller */
-#define AT91SAM9X5_ID_ISI	25	/* Image Sensor Interface */
-#define AT91SAM9X5_ID_MCI1	26	/* High Speed Multimedia Card Interface 1 */
-#define AT91SAM9X5_ID_EMAC1	27	/* Ethernet MAC1 */
-#define AT91SAM9X5_ID_SSC	28	/* Synchronous Serial Controller */
-#define AT91SAM9X5_ID_CAN0	29	/* CAN Controller 0 */
-#define AT91SAM9X5_ID_CAN1	30	/* CAN Controller 1 */
-#define AT91SAM9X5_ID_IRQ0	31	/* Advanced Interrupt Controller */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9X5_BASE_SPI0		0xf0000000
-#define AT91SAM9X5_BASE_SPI1		0xf0004000
-#define AT91SAM9X5_BASE_MCI0		0xf0008000
-#define AT91SAM9X5_BASE_MCI1		0xf000c000
-#define AT91SAM9X5_BASE_SSC		0xf0010000
-#define AT91SAM9X5_BASE_CAN0		0xf8000000
-#define AT91SAM9X5_BASE_CAN1		0xf8004000
-#define AT91SAM9X5_BASE_TCB0		0xf8008000
-#define AT91SAM9X5_BASE_TC0		0xf8008000
-#define AT91SAM9X5_BASE_TC1		0xf8008040
-#define AT91SAM9X5_BASE_TC2		0xf8008080
-#define AT91SAM9X5_BASE_TCB1		0xf800c000
-#define AT91SAM9X5_BASE_TC3		0xf800c000
-#define AT91SAM9X5_BASE_TC4		0xf800c040
-#define AT91SAM9X5_BASE_TC5		0xf800c080
-#define AT91SAM9X5_BASE_TWI0		0xf8010000
-#define AT91SAM9X5_BASE_TWI1		0xf8014000
-#define AT91SAM9X5_BASE_TWI2		0xf8018000
-#define AT91SAM9X5_BASE_USART0		0xf801c000
-#define AT91SAM9X5_BASE_USART1		0xf8020000
-#define AT91SAM9X5_BASE_USART2		0xf8024000
-#define AT91SAM9X5_BASE_USART3		0xf8028000
-#define AT91SAM9X5_BASE_EMAC0		0xf802c000
-#define AT91SAM9X5_BASE_EMAC1		0xf8030000
-#define AT91SAM9X5_BASE_PWMC		0xf8034000
-#define AT91SAM9X5_BASE_LCDC		0xf8038000
-#define AT91SAM9X5_BASE_UDPHS		0xf803c000
-#define AT91SAM9X5_BASE_UART0		0xf8040000
-#define AT91SAM9X5_BASE_UART1		0xf8044000
-#define AT91SAM9X5_BASE_ISI		0xf8048000
-#define AT91SAM9X5_BASE_ADC		0xf804c000
-
-/*
- * System Peripherals
- */
-#define AT91SAM9X5_BASE_MATRIX		0xffffde00
-#define AT91SAM9X5_BASE_PMECC		0xffffe000
-#define AT91SAM9X5_BASE_PMERRLOC	0xffffe600
-#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
-#define AT91SAM9X5_BASE_SMC		0xffffea00
-#define AT91SAM9X5_BASE_DMA0		0xffffec00
-#define AT91SAM9X5_BASE_DMA1		0xffffee00
-#define AT91SAM9X5_BASE_AIC		0xfffff000
-#define AT91SAM9X5_BASE_DBGU		0xfffff200
-#define AT91SAM9X5_BASE_PIOA		0xfffff400
-#define AT91SAM9X5_BASE_PIOB		0xfffff600
-#define AT91SAM9X5_BASE_PIOC		0xfffff800
-#define AT91SAM9X5_BASE_PIOD		0xfffffa00
-#define AT91SAM9X5_BASE_PMC		0xfffffc00
-#define AT91SAM9X5_BASE_RSTC		0xfffffe00
-#define AT91SAM9X5_BASE_SHDWC		0xfffffe10
-#define AT91SAM9X5_BASE_PIT		0xfffffe30
-#define AT91SAM9X5_BASE_WDT		0xfffffe40
-#define AT91SAM9X5_BASE_GPBR		0xfffffe60
-#define AT91SAM9X5_BASE_RTC		0xfffffeb0
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9X5_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define AT91SAM9X5_SRAM_SIZE	SZ_32K		/* Internal SRAM size (32Kb) */
-
-#define AT91SAM9X5_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91SAM9X5_ROM_SIZE	SZ_64K		/* Internal ROM size (64Kb) */
-
-#define AT91SAM9X5_SMD_BASE	0x00400000	/* SMD Controller */
-#define AT91SAM9X5_UDPHS_FIFO	0x00500000	/* USB Device HS controller */
-#define AT91SAM9X5_OHCI_BASE	0x00600000	/* USB Host controller (OHCI) */
-#define AT91SAM9X5_EHCI_BASE	0x00700000	/* USB Host controller (EHCI) */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
deleted file mode 100644
index 2ab211c012..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2009-2010 Atmel Corporation */
-
-/*
- * Matrix-centric header file for the AT91SAM9x5 family
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9x5 preliminary datasheet.
- */
-
-#ifndef AT91SAM9X5_MATRIX_H
-#define AT91SAM9X5_MATRIX_H
-
-#define AT91SAM9X5_MATRIX_MCFG0	(0x00)	/* Master Configuration Register 0 */
-#define AT91SAM9X5_MATRIX_MCFG1	(0x04)	/* Master Configuration Register 1 */
-#define AT91SAM9X5_MATRIX_MCFG2	(0x08)	/* Master Configuration Register 2 */
-#define AT91SAM9X5_MATRIX_MCFG3	(0x0C)	/* Master Configuration Register 3 */
-#define AT91SAM9X5_MATRIX_MCFG4	(0x10)	/* Master Configuration Register 4 */
-#define AT91SAM9X5_MATRIX_MCFG5	(0x14)	/* Master Configuration Register 5 */
-#define AT91SAM9X5_MATRIX_MCFG6	(0x18)	/* Master Configuration Register 6 */
-#define AT91SAM9X5_MATRIX_MCFG7	(0x1C)	/* Master Configuration Register 7 */
-#define AT91SAM9X5_MATRIX_MCFG8	(0x20)	/* Master Configuration Register 8 */
-#define AT91SAM9X5_MATRIX_MCFG9	(0x24)	/* Master Configuration Register 9 */
-#define AT91SAM9X5_MATRIX_MCFG10	(0x28)	/* Master Configuration Register 10 */
-#define AT91SAM9X5_MATRIX_MCFG11	(0x2C)	/* Master Configuration Register 11 */
-#define		AT91SAM9X5_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91SAM9X5_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91SAM9X5_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91SAM9X5_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91SAM9X5_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91SAM9X5_MATRIX_ULBT_SIXTEEN	(4 << 0)
-#define			AT91SAM9X5_MATRIX_ULBT_THIRTYTWO	(5 << 0)
-#define			AT91SAM9X5_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
-#define			AT91SAM9X5_MATRIX_ULBT_128		(7 << 0)
-
-#define AT91SAM9X5_MATRIX_SCFG0	(0x40)	/* Slave Configuration Register 0 */
-#define AT91SAM9X5_MATRIX_SCFG1	(0x44)	/* Slave Configuration Register 1 */
-#define AT91SAM9X5_MATRIX_SCFG2	(0x48)	/* Slave Configuration Register 2 */
-#define AT91SAM9X5_MATRIX_SCFG3	(0x4C)	/* Slave Configuration Register 3 */
-#define AT91SAM9X5_MATRIX_SCFG4	(0x50)	/* Slave Configuration Register 4 */
-#define AT91SAM9X5_MATRIX_SCFG5	(0x54)	/* Slave Configuration Register 5 */
-#define AT91SAM9X5_MATRIX_SCFG6	(0x58)	/* Slave Configuration Register 6 */
-#define AT91SAM9X5_MATRIX_SCFG7	(0x5C)	/* Slave Configuration Register 7 */
-#define AT91SAM9X5_MATRIX_SCFG8	(0x60)	/* Slave Configuration Register 8 */
-#define		AT91SAM9X5_MATRIX_SLOT_CYCLE		(0x1ff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91SAM9X5_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91SAM9X5_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91SAM9X5_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91SAM9X5_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91SAM9X5_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
-
-#define AT91SAM9X5_MATRIX_PRAS0	(0x80)	/* Priority Register A for Slave 0 */
-#define AT91SAM9X5_MATRIX_PRBS0	(0x84)	/* Priority Register B for Slave 0 */
-#define AT91SAM9X5_MATRIX_PRAS1	(0x88)	/* Priority Register A for Slave 1 */
-#define AT91SAM9X5_MATRIX_PRBS1	(0x8C)	/* Priority Register B for Slave 1 */
-#define AT91SAM9X5_MATRIX_PRAS2	(0x90)	/* Priority Register A for Slave 2 */
-#define AT91SAM9X5_MATRIX_PRBS2	(0x94)	/* Priority Register B for Slave 2 */
-#define AT91SAM9X5_MATRIX_PRAS3	(0x98)	/* Priority Register A for Slave 3 */
-#define AT91SAM9X5_MATRIX_PRBS3	(0x9C)	/* Priority Register B for Slave 3 */
-#define AT91SAM9X5_MATRIX_PRAS4	(0xA0)	/* Priority Register A for Slave 4 */
-#define AT91SAM9X5_MATRIX_PRBS4	(0xA4)	/* Priority Register B for Slave 4 */
-#define AT91SAM9X5_MATRIX_PRAS5	(0xA8)	/* Priority Register A for Slave 5 */
-#define AT91SAM9X5_MATRIX_PRBS5	(0xAC)	/* Priority Register B for Slave 5 */
-#define AT91SAM9X5_MATRIX_PRAS6	(0xB0)	/* Priority Register A for Slave 6 */
-#define AT91SAM9X5_MATRIX_PRBS6	(0xB4)	/* Priority Register B for Slave 6 */
-#define AT91SAM9X5_MATRIX_PRAS7	(0xB8)	/* Priority Register A for Slave 7 */
-#define AT91SAM9X5_MATRIX_PRBS7	(0xBC)	/* Priority Register B for Slave 7 */
-#define AT91SAM9X5_MATRIX_PRAS8	(0xC0)	/* Priority Register A for Slave 8 */
-#define AT91SAM9X5_MATRIX_PRBS8	(0xC4)	/* Priority Register B for Slave 8 */
-#define		AT91SAM9X5_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91SAM9X5_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91SAM9X5_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91SAM9X5_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91SAM9X5_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91SAM9X5_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-#define		AT91SAM9X5_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
-#define		AT91SAM9X5_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
-#define		AT91SAM9X5_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
-#define		AT91SAM9X5_MATRIX_M9PR		(3 << 4)	/* Master 9 Priority (in Register B) */
-#define		AT91SAM9X5_MATRIX_M10PR		(3 << 8)	/* Master 10 Priority (in Register B) */
-#define		AT91SAM9X5_MATRIX_M11PR		(3 << 12)	/* Master 11 Priority (in Register B) */
-
-#define AT91SAM9X5_MATRIX_MRCR	(0x100)	/* Master Remap Control Register */
-#define		AT91SAM9X5_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91SAM9X5_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91SAM9X5_MATRIX_RCB2		(1 << 2)
-#define		AT91SAM9X5_MATRIX_RCB3		(1 << 3)
-#define		AT91SAM9X5_MATRIX_RCB4		(1 << 4)
-#define		AT91SAM9X5_MATRIX_RCB5		(1 << 5)
-#define		AT91SAM9X5_MATRIX_RCB6		(1 << 6)
-#define		AT91SAM9X5_MATRIX_RCB7		(1 << 7)
-#define		AT91SAM9X5_MATRIX_RCB8		(1 << 8)
-#define		AT91SAM9X5_MATRIX_RCB9		(1 << 9)
-#define		AT91SAM9X5_MATRIX_RCB10		(1 << 10)
-#define		AT91SAM9X5_MATRIX_RCB11		(1 << 11)
-
-#define AT91SAM9X5_MATRIX_EBICSA	(0x120)	/* EBI Chip Select Assignment Register */
-#define		AT91SAM9X5_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91SAM9X5_MATRIX_EBI_CS1A_SMC		(0 << 1)
-#define			AT91SAM9X5_MATRIX_EBI_CS1A_SDRAMC		(1 << 1)
-#define		AT91SAM9X5_MATRIX_EBI_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91SAM9X5_MATRIX_EBI_CS3A_SMC		(0 << 3)
-#define			AT91SAM9X5_MATRIX_EBI_CS3A_SMC_NANDFLASH	(1 << 3)
-#define		AT91SAM9X5_MATRIX_EBI_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define			AT91SAM9X5_MATRIX_EBI_DBPU_ON			(0 << 8)
-#define			AT91SAM9X5_MATRIX_EBI_DBPU_OFF		(1 << 8)
-#define		AT91SAM9X5_MATRIX_EBI_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_3_3V		(1 << 16)
-#define		AT91SAM9X5_MATRIX_EBI_EBI_IOSR	(1 << 17)	/* EBI I/O slew rate selection */
-#define			AT91SAM9X5_MATRIX_EBI_EBI_IOSR_REDUCED	(0 << 17)
-#define			AT91SAM9X5_MATRIX_EBI_EBI_IOSR_NORMAL		(1 << 17)
-#define		AT91SAM9X5_MATRIX_EBI_DDR_IOSR	(1 << 18)	/* DDR2 dedicated port I/O slew rate selection */
-#define			AT91SAM9X5_MATRIX_EBI_DDR_IOSR_REDUCED	(0 << 18)
-#define			AT91SAM9X5_MATRIX_EBI_DDR_IOSR_NORMAL		(1 << 18)
-#define		AT91SAM9X5_MATRIX_NFD0_SELECT		(1 << 24)	/* NAND Flash Data Bus Selection */
-#define			AT91SAM9X5_MATRIX_NFD0_ON_D0			(0 << 24)
-#define			AT91SAM9X5_MATRIX_NFD0_ON_D16			(1 << 24)
-#define		AT91SAM9X5_MATRIX_DDR_MP_EN		(1 << 25)	/* DDR Multi-port Enable */
-#define			AT91SAM9X5_MATRIX_MP_OFF			(0 << 25)
-#define			AT91SAM9X5_MATRIX_MP_ON			(1 << 25)
-
-#define AT91SAM9X5_MATRIX_WPMR	(0x1E4)	/* Write Protect Mode Register */
-#define		AT91SAM9X5_MATRIX_WPMR_WPEN		(1 << 0)	/* Write Protect ENable */
-#define			AT91SAM9X5_MATRIX_WPMR_WP_WPDIS		(0 << 0)
-#define			AT91SAM9X5_MATRIX_WPMR_WP_WPEN		(1 << 0)
-#define		AT91SAM9X5_MATRIX_WPMR_WPKEY		(0xFFFFFF << 8)	/* Write Protect KEY */
-
-#define AT91SAM9X5_MATRIX_WPSR	(0x1E8)	/* Write Protect Status Register */
-#define		AT91SAM9X5_MATRIX_WPSR_WPVS		(1 << 0)	/* Write Protect Violation Status */
-#define			AT91SAM9X5_MATRIX_WPSR_NO_WPV		(0 << 0)
-#define			AT91SAM9X5_MATRIX_WPSR_WPV		(1 << 0)
-#define		AT91SAM9X5_MATRIX_WPSR_WPVSRC		(0xFFFF << 8)	/* Write Protect Violation Source */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h
deleted file mode 100644
index a44160431e..0000000000
--- a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h
+++ /dev/null
@@ -1,748 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2010 Atmel Corporation */
-
-/*
- * Header file for AT91 High end LCD Controller
- *
- * Data structure and register user interface
- */
-
-#ifndef __MACH_ATMEL_HLCD_H__
-#define __MACH_ATMEL_HLCD_H__
-
-/* Lcdc hardware registers */
-#define ATMEL_LCDC_LCDCFG0	0x0000
-#define LCDC_LCDCFG0_CLKPOL		(0x1 << 0)
-#define LCDC_LCDCFG0_CLKSEL		(0x1 << 2)
-#define LCDC_LCDCFG0_CLKPWMSEL		(0x1 << 3)
-#define LCDC_LCDCFG0_CGDISBASE		(0x1 << 8)
-#define LCDC_LCDCFG0_CGDISOVR1		(0x1 << 9)
-#define LCDC_LCDCFG0_CGDISOVR2		(0x1 << 10)
-#define LCDC_LCDCFG0_CGDISHEO		(0x1 << 11)
-#define LCDC_LCDCFG0_CGDISHCR		(0x1 << 12)
-#define LCDC_LCDCFG0_CGDISPP		(0x1 << 13)
-#define LCDC_LCDCFG0_CLKDIV_OFFSET	16
-#define LCDC_LCDCFG0_CLKDIV		(0xff << LCDC_LCDCFG0_CLKDIV_OFFSET)
-
-#define ATMEL_LCDC_LCDCFG1	0x0004
-#define LCDC_LCDCFG1_HSPW_OFFSET	0
-#define LCDC_LCDCFG1_HSPW		(0x3f << LCDC_LCDCFG1_HSPW_OFFSET)
-#define LCDC_LCDCFG1_VSPW_OFFSET	16
-#define LCDC_LCDCFG1_VSPW		(0x3f << LCDC_LCDCFG1_VSPW_OFFSET)
-
-#define ATMEL_LCDC_LCDCFG2	0x0008
-#define LCDC_LCDCFG2_VFPW_OFFSET	0
-#define LCDC_LCDCFG2_VFPW		(0x3f << LCDC_LCDCFG2_VFPW_OFFSET)
-#define LCDC_LCDCFG2_VBPW_OFFSET	16
-#define LCDC_LCDCFG2_VBPW		(0x3f << LCDC_LCDCFG2_VBPW_OFFSET)
-
-#define ATMEL_LCDC_LCDCFG3	0x000C
-#define LCDC_LCDCFG3_HFPW_OFFSET	0
-#define LCDC_LCDCFG3_HFPW		(0xff << LCDC_LCDCFG3_HFPW_OFFSET)
-#define LCDC2_LCDCFG3_HFPW		(0x1ff << LCDC_LCDCFG3_HFPW_OFFSET)
-#define LCDC_LCDCFG3_HBPW_OFFSET	16
-#define LCDC_LCDCFG3_HBPW		(0xff << LCDC_LCDCFG3_HBPW_OFFSET)
-#define LCDC2_LCDCFG3_HBPW		(0x1ff << LCDC_LCDCFG3_HBPW_OFFSET)
-
-#define ATMEL_LCDC_LCDCFG4	0x0010
-#define LCDC_LCDCFG4_PPL_OFFSET		0
-#define LCDC_LCDCFG4_PPL		(0x7ff << LCDC_LCDCFG4_PPL_OFFSET)
-#define LCDC_LCDCFG4_RPF_OFFSET		16
-#define LCDC_LCDCFG4_RPF		(0x7ff << LCDC_LCDCFG4_RPF_OFFSET)
-
-#define ATMEL_LCDC_LCDCFG5	0x0014
-#define LCDC_LCDCFG5_HSPOL		(0x1 << 0)
-#define LCDC_LCDCFG5_VSPOL		(0x1 << 1)
-#define LCDC_LCDCFG5_VSPDLYS		(0x1 << 2)
-#define LCDC_LCDCFG5_VSPDLYE		(0x1 << 3)
-#define LCDC_LCDCFG5_DISPPOL		(0x1 << 4)
-#define LCDC_LCDCFG5_SERIAL		(0x1 << 5)
-#define LCDC_LCDCFG5_DITHER		(0x1 << 6)
-#define LCDC_LCDCFG5_DISPDLY		(0x1 << 7)
-#define LCDC_LCDCFG5_MODE_OFFSET	8
-#define LCDC_LCDCFG5_MODE		(0x3 << LCDC_LCDCFG5_MODE_OFFSET)
-#define		LCDC_LCDCFG5_MODE_OUTPUT_12BPP		(0x0 << 8)
-#define		LCDC_LCDCFG5_MODE_OUTPUT_16BPP		(0x1 << 8)
-#define		LCDC_LCDCFG5_MODE_OUTPUT_18BPP		(0x2 << 8)
-#define		LCDC_LCDCFG5_MODE_OUTPUT_24BPP		(0x3 << 8)
-#define LCDC_LCDCFG5_PP			(0x1 << 10)
-#define LCDC_LCDCFG5_VSPSU		(0x1 << 12)
-#define LCDC_LCDCFG5_VSPHO		(0x1 << 13)
-#define LCDC_LCDCFG5_GUARDTIME_OFFSET	16
-#define LCDC_LCDCFG5_GUARDTIME		(0x1f << LCDC_LCDCFG5_GUARDTIME_OFFSET)
-
-#define ATMEL_LCDC_LCDCFG6	0x0018
-#define LCDC_LCDCFG6_PWMPS_OFFSET	0
-#define LCDC_LCDCFG6_PWMPS		(0x7 << LCDC_LCDCFG6_PWMPS_OFFSET)
-#define LCDC_LCDCFG6_PWMPOL		(0x1 << 4)
-#define LCDC_LCDCFG6_PWMCVAL_OFFSET	8
-#define LCDC_LCDCFG6_PWMCVAL		(0xff << LCDC_LCDCFG6_PWMCVAL_OFFSET)
-
-#define ATMEL_LCDC_LCDEN	0x0020
-#define LCDC_LCDEN_CLKEN		(0x1 << 0)
-#define LCDC_LCDEN_SYNCEN		(0x1 << 1)
-#define LCDC_LCDEN_DISPEN		(0x1 << 2)
-#define LCDC_LCDEN_PWMEN		(0x1 << 3)
-
-#define ATMEL_LCDC_LCDDIS	0x0024
-#define LCDC_LCDDIS_CLKDIS		(0x1 << 0)
-#define LCDC_LCDDIS_SYNCDIS		(0x1 << 1)
-#define LCDC_LCDDIS_DISPDIS		(0x1 << 2)
-#define LCDC_LCDDIS_PWMDIS		(0x1 << 3)
-#define LCDC_LCDDIS_CLKRST		(0x1 << 8)
-#define LCDC_LCDDIS_SYNCRST		(0x1 << 9)
-#define LCDC_LCDDIS_DISPRST		(0x1 << 10)
-#define LCDC_LCDDIS_PWMRST		(0x1 << 11)
-
-#define ATMEL_LCDC_LCDSR	0x0028
-#define LCDC_LCDSR_CLKSTS		(0x1 << 0)
-#define LCDC_LCDSR_LCDSTS		(0x1 << 1)
-#define LCDC_LCDSR_DISPSTS		(0x1 << 2)
-#define LCDC_LCDSR_PWMSTS		(0x1 << 3)
-#define LCDC_LCDSR_SIPSTS		(0x1 << 4)
-
-#define ATMEL_LCDC_LCDIER	0x002C
-#define LCDC_LCDIER_SOFIE		(0x1 << 0)
-#define LCDC_LCDIER_DISIE		(0x1 << 1)
-#define LCDC_LCDIER_DISPIE		(0x1 << 2)
-#define LCDC_LCDIER_FIFOERRIE		(0x1 << 4)
-#define LCDC_LCDIER_BASEIE		(0x1 << 8)
-#define LCDC_LCDIER_OVR1IE		(0x1 << 9)
-#define LCDC_LCDIER_OVR2IE		(0x1 << 10)
-#define LCDC_LCDIER_HEOIE		(0x1 << 11)
-#define LCDC_LCDIER_HCRIE		(0x1 << 12)
-#define LCDC_LCDIER_PPIE		(0x1 << 13)
-
-#define ATMEL_LCDC_LCDIDR	0x0030
-#define LCDC_LCDIDR_SOFID		(0x1 << 0)
-#define LCDC_LCDIDR_DISID		(0x1 << 1)
-#define LCDC_LCDIDR_DISPID		(0x1 << 2)
-#define LCDC_LCDIDR_FIFOERRID		(0x1 << 4)
-#define LCDC_LCDIDR_BASEID		(0x1 << 8)
-#define LCDC_LCDIDR_OVR1ID		(0x1 << 9)
-#define LCDC_LCDIDR_OVR2ID		(0x1 << 10)
-#define LCDC_LCDIDR_HEOID		(0x1 << 11)
-#define LCDC_LCDIDR_HCRID		(0x1 << 12)
-#define LCDC_LCDIDR_PPID		(0x1 << 13)
-
-#define ATMEL_LCDC_LCDIMR	0x0034
-#define LCDC_LCDIMR_SOFIM		(0x1 << 0)
-#define LCDC_LCDIMR_DISIM		(0x1 << 1)
-#define LCDC_LCDIMR_DISPIM		(0x1 << 2)
-#define LCDC_LCDIMR_FIFOERRIM		(0x1 << 4)
-#define LCDC_LCDIMR_BASEIM		(0x1 << 8)
-#define LCDC_LCDIMR_OVR1IM		(0x1 << 9)
-#define LCDC_LCDIMR_OVR2IM		(0x1 << 10)
-#define LCDC_LCDIMR_HEOIM		(0x1 << 11)
-#define LCDC_LCDIMR_HCRIM		(0x1 << 12)
-#define LCDC_LCDIMR_PPIM		(0x1 << 13)
-
-#define ATMEL_LCDC_LCDISR	0x0038
-#define LCDC_LCDISR_SOF			(0x1 << 0)
-#define LCDC_LCDISR_DIS			(0x1 << 1)
-#define LCDC_LCDISR_DISP		(0x1 << 2)
-#define LCDC_LCDISR_FIFOERR		(0x1 << 4)
-#define LCDC_LCDISR_BASE		(0x1 << 8)
-#define LCDC_LCDISR_OVR1		(0x1 << 9)
-#define LCDC_LCDISR_OVR2		(0x1 << 10)
-#define LCDC_LCDISR_HEO			(0x1 << 11)
-#define LCDC_LCDISR_HCR			(0x1 << 12)
-#define LCDC_LCDISR_PP			(0x1 << 13)
-
-#define ATMEL_LCDC_BASECHER	0x0040
-#define LCDC_BASECHER_CHEN		(0x1 << 0)
-#define LCDC_BASECHER_UPDATEEN		(0x1 << 1)
-#define LCDC_BASECHER_A2QEN		(0x1 << 2)
-
-#define ATMEL_LCDC_BASECHDR	0x0044
-#define LCDC_BASECHDR_CHDIS		(0x1 << 0)
-#define LCDC_BASECHDR_CHRST		(0x1 << 8)
-
-#define ATMEL_LCDC_BASECHSR	0x0048
-#define LCDC_BASECHSR_CHSR		(0x1 << 0)
-#define LCDC_BASECHSR_UPDATESR		(0x1 << 1)
-#define LCDC_BASECHSR_A2QSR		(0x1 << 2)
-
-#define ATMEL_LCDC_BASEIER	0x004C
-#define LCDC_BASEIER_DMA		(0x1 << 2)
-#define LCDC_BASEIER_DSCR		(0x1 << 3)
-#define LCDC_BASEIER_ADD		(0x1 << 4)
-#define LCDC_BASEIER_DONE		(0x1 << 5)
-#define LCDC_BASEIER_OVR		(0x1 << 6)
-
-#define ATMEL_LCDC_BASEIDR	0x0050
-#define LCDC_BASEIDR_DMA		(0x1 << 2)
-#define LCDC_BASEIDR_DSCR		(0x1 << 3)
-#define LCDC_BASEIDR_ADD		(0x1 << 4)
-#define LCDC_BASEIDR_DONE		(0x1 << 5)
-#define LCDC_BASEIDR_OVR		(0x1 << 6)
-
-#define ATMEL_LCDC_BASEIMR	0x0054
-#define LCDC_BASEIMR_DMA		(0x1 << 2)
-#define LCDC_BASEIMR_DSCR		(0x1 << 3)
-#define LCDC_BASEIMR_ADD		(0x1 << 4)
-#define LCDC_BASEIMR_DONE		(0x1 << 5)
-#define LCDC_BASEIMR_OVR		(0x1 << 6)
-
-#define ATMEL_LCDC_BASEISR	0x0058
-#define LCDC_BASEISR_DMA		(0x1 << 2)
-#define LCDC_BASEISR_DSCR		(0x1 << 3)
-#define LCDC_BASEISR_ADD		(0x1 << 4)
-#define LCDC_BASEISR_DONE		(0x1 << 5)
-#define LCDC_BASEISR_OVR		(0x1 << 6)
-
-#define ATMEL_LCDC_BASEHEAD	0x005C
-
-#define ATMEL_LCDC_BASEADDR	0x0060
-
-#define ATMEL_LCDC_BASECTRL	0x0064
-#define LCDC_BASECTRL_DFETCH		(0x1 << 0)
-#define LCDC_BASECTRL_LFETCH		(0x1 << 1)
-#define LCDC_BASECTRL_DMAIEN		(0x1 << 2)
-#define LCDC_BASECTRL_DSCRIEN		(0x1 << 3)
-#define LCDC_BASECTRL_ADDIEN		(0x1 << 4)
-#define LCDC_BASECTRL_DONEIEN		(0x1 << 5)
-
-#define ATMEL_LCDC_BASENEXT	0x0068
-
-#define ATMEL_LCDC_BASECFG0	0x006C
-#define LCDC_BASECFG0_SIF		(0x1 << 0)
-#define LCDC_BASECFG0_BLEN_OFFSET 4
-#define LCDC_BASECFG0_BLEN		(0x3 << LCDC_BASECFG0_BLEN_OFFSET)
-#define		LCDC_BASECFG0_BLEN_AHB_SINGLE		(0x0 << 4)
-#define		LCDC_BASECFG0_BLEN_AHB_INCR4		(0x1 << 4)
-#define		LCDC_BASECFG0_BLEN_AHB_INCR8		(0x2 << 4)
-#define		LCDC_BASECFG0_BLEN_AHB_INCR16		(0x3 << 4)
-#define LCDC_BASECFG0_DLBO		(0x1 << 8)
-
-#define ATMEL_LCDC_BASECFG1	0x0070
-#define LCDC_BASECFG1_CLUTEN		(0x1 << 0)
-#define LCDC_BASECFG1_RGBMODE_OFFSET	4
-#define LCDC_BASECFG1_RGBMODE		(0xf << LCDC_BASECFG1_RGBMODE_OFFSET)
-#define		LCDC_BASECFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
-#define		LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
-#define		LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
-#define		LCDC_BASECFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
-#define		LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
-#define		LCDC_BASECFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
-#define		LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
-#define		LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
-#define		LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
-#define		LCDC_BASECFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
-#define		LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
-#define		LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
-#define		LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
-#define		LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
-#define LCDC_BASECFG1_CLUTMODE_OFFSET	8
-#define LCDC_BASECFG1_CLUTMODE		(0x3 << LCDC_BASECFG1_CLUTMODE_OFFSET)
-#define		LCDC_BASECFG1_CLUTMODE_1BPP		(0x0 << 8)
-#define		LCDC_BASECFG1_CLUTMODE_2BPP		(0x1 << 8)
-#define		LCDC_BASECFG1_CLUTMODE_4BPP		(0x2 << 8)
-#define		LCDC_BASECFG1_CLUTMODE_8BPP		(0x3 << 8)
-
-#define ATMEL_LCDC_BASECFG2	0x0074
-
-#define ATMEL_LCDC_BASECFG3	0x0078
-#define LCDC_BASECFG3_BDEF_OFFSET	0
-#define LCDC_BASECFG3_BDEF		(0xff << LCDC_BASECFG3_BDEF_OFFSET)
-#define LCDC_BASECFG3_GDEF_OFFSET	8
-#define LCDC_BASECFG3_GDEF		(0xff << LCDC_BASECFG3_GDEF_OFFSET)
-#define LCDC_BASECFG3_RDEF_OFFSET	16
-#define LCDC_BASECFG3_RDEF		(0xff << LCDC_BASECFG3_RDEF_OFFSET)
-
-#define ATMEL_LCDC_BASECFG4	0x007C
-#define LCDC_BASECFG4_DMA		(0x1 << 8)
-#define LCDC_BASECFG4_REP		(0x1 << 9)
-#define LCDC_BASECFG4_DISCEN		(0x1 << 11)
-
-#define ATMEL_LCDC_BASECFG5	0x0080
-#define LCDC_BASECFG5_DISCXPOS_OFFSET	0
-#define LCDC_BASECFG5_DISCXPOS		(0x7ff << LCDC_BASECFG5_DISCXPOS_OFFSET)
-#define LCDC_BASECFG5_DISCYPOS_OFFSET	16
-#define LCDC_BASECFG5_DISCYPOS		(0x7ff << LCDC_BASECFG5_DISCYPOS_OFFSET)
-
-#define ATMEL_LCDC_BASECFG6	0x0084
-#define LCDC_BASECFG6_DISCXSIZE_OFFSET	0
-#define LCDC_BASECFG6_DISCXSIZE		(0x7ff << LCDC_BASECFG6_DISCXSIZE_OFFSET)
-#define LCDC_BASECFG6_DISCYSIZE_OFFSET	16
-#define LCDC_BASECFG6_DISCYSIZE		(0x7ff << LCDC_BASECFG6_DISCYSIZE_OFFSET)
-
-#define ATMEL_LCDC_HEOCHER	0x0280
-#define ATMEL_LCDC2_HEOCHER	0x0340
-#define LCDC_HEOCHER_CHEN		(0x1 << 0)
-#define LCDC_HEOCHER_UPDATEEN		(0x1 << 1)
-#define LCDC_HEOCHER_A2QEN		(0x1 << 2)
-
-#define ATMEL_LCDC_HEOCHDR	0x0284
-#define LCDC_HEOCHDR_CHDIS		(0x1 << 0)
-#define LCDC_HEOCHDR_CHRST		(0x1 << 8)
-
-#define ATMEL_LCDC_HEOCHSR	0x0288
-#define LCDC_HEOCHSR_CHSR		(0x1 << 0)
-#define LCDC_HEOCHSR_UPDATESR		(0x1 << 1)
-#define LCDC_HEOCHSR_A2QSR		(0x1 << 2)
-
-#define ATMEL_LCDC_HEOIER	0x028C
-#define LCDC_HEOIER_DMA			(0x1 << 2)
-#define LCDC_HEOIER_DSCR		(0x1 << 3)
-#define LCDC_HEOIER_ADD			(0x1 << 4)
-#define LCDC_HEOIER_DONE		(0x1 << 5)
-#define LCDC_HEOIER_OVR			(0x1 << 6)
-#define LCDC_HEOIER_UDMA		(0x1 << 10)
-#define LCDC_HEOIER_UDSCR		(0x1 << 11)
-#define LCDC_HEOIER_UADD		(0x1 << 12)
-#define LCDC_HEOIER_UDONE		(0x1 << 13)
-#define LCDC_HEOIER_UOVR		(0x1 << 14)
-#define LCDC_HEOIER_VDMA		(0x1 << 18)
-#define LCDC_HEOIER_VDSCR		(0x1 << 19)
-#define LCDC_HEOIER_VADD		(0x1 << 20)
-#define LCDC_HEOIER_VDONE		(0x1 << 21)
-#define LCDC_HEOIER_VOVR		(0x1 << 22)
-
-#define ATMEL_LCDC_HEOIDR	0x0290
-#define LCDC_HEOIDR_DMA			(0x1 << 2)
-#define LCDC_HEOIDR_DSCR		(0x1 << 3)
-#define LCDC_HEOIDR_ADD			(0x1 << 4)
-#define LCDC_HEOIDR_DONE		(0x1 << 5)
-#define LCDC_HEOIDR_OVR			(0x1 << 6)
-#define LCDC_HEOIDR_UDMA		(0x1 << 10)
-#define LCDC_HEOIDR_UDSCR		(0x1 << 11)
-#define LCDC_HEOIDR_UADD		(0x1 << 12)
-#define LCDC_HEOIDR_UDONE		(0x1 << 13)
-#define LCDC_HEOIDR_UOVR		(0x1 << 14)
-#define LCDC_HEOIDR_VDMA		(0x1 << 18)
-#define LCDC_HEOIDR_VDSCR		(0x1 << 19)
-#define LCDC_HEOIDR_VADD		(0x1 << 20)
-#define LCDC_HEOIDR_VDONE		(0x1 << 21)
-#define LCDC_HEOIDR_VOVR		(0x1 << 22)
-
-#define ATMEL_LCDC_HEOIMR	0x0294
-#define LCDC_HEOIMR_DMA			(0x1 << 2)
-#define LCDC_HEOIMR_DSCR		(0x1 << 3)
-#define LCDC_HEOIMR_ADD			(0x1 << 4)
-#define LCDC_HEOIMR_DONE		(0x1 << 5)
-#define LCDC_HEOIMR_OVR			(0x1 << 6)
-#define LCDC_HEOIMR_UDMA		(0x1 << 10)
-#define LCDC_HEOIMR_UDSCR		(0x1 << 11)
-#define LCDC_HEOIMR_UADD		(0x1 << 12)
-#define LCDC_HEOIMR_UDONE		(0x1 << 13)
-#define LCDC_HEOIMR_UOVR		(0x1 << 14)
-#define LCDC_HEOIMR_VDMA		(0x1 << 18)
-#define LCDC_HEOIMR_VDSCR		(0x1 << 19)
-#define LCDC_HEOIMR_VADD		(0x1 << 20)
-#define LCDC_HEOIMR_VDONE		(0x1 << 21)
-#define LCDC_HEOIMR_VOVR		(0x1 << 22)
-
-#define ATMEL_LCDC_HEOISR	0x0298
-#define LCDC_HEOISR_DMA			(0x1 << 2)
-#define LCDC_HEOISR_DSCR		(0x1 << 3)
-#define LCDC_HEOISR_ADD			(0x1 << 4)
-#define LCDC_HEOISR_DONE		(0x1 << 5)
-#define LCDC_HEOISR_OVR			(0x1 << 6)
-#define LCDC_HEOISR_UDMA		(0x1 << 10)
-#define LCDC_HEOISR_UDSCR		(0x1 << 11)
-#define LCDC_HEOISR_UADD		(0x1 << 12)
-#define LCDC_HEOISR_UDONE		(0x1 << 13)
-#define LCDC_HEOISR_UOVR		(0x1 << 14)
-#define LCDC_HEOISR_VDMA		(0x1 << 18)
-#define LCDC_HEOISR_VDSCR		(0x1 << 19)
-#define LCDC_HEOISR_VADD		(0x1 << 20)
-#define LCDC_HEOISR_VDONE		(0x1 << 21)
-#define LCDC_HEOISR_VOVR		(0x1 << 22)
-
-#define ATMEL_LCDC_HEOHEAD	0x029C
-
-#define ATMEL_LCDC_HEOADDR	0x02A0
-
-#define ATMEL_LCDC_HEOCTRL	0x02A4
-#define LCDC_HEOCTRL_DFETCH		(0x1 << 0)
-#define LCDC_HEOCTRL_LFETCH		(0x1 << 1)
-#define LCDC_HEOCTRL_DMAIEN		(0x1 << 2)
-#define LCDC_HEOCTRL_DSCRIEN		(0x1 << 3)
-#define LCDC_HEOCTRL_ADDIEN		(0x1 << 4)
-#define LCDC_HEOCTRL_DONEIEN		(0x1 << 5)
-
-#define ATMEL_LCDC_HEONEXT	0x02A8
-
-#define ATMEL_LCDC_HEOUHEAD	0x02AC
-
-#define ATMEL_LCDC_HEOUADDR	0x02B0
-
-#define ATMEL_LCDC_HEOUCTRL	0x02B4
-#define LCDC_HEOUCTRL_UDFETCH		(0x1 << 0)
-#define LCDC_HEOUCTRL_UDMAIEN		(0x1 << 2)
-#define LCDC_HEOUCTRL_UDSCRIEN		(0x1 << 3)
-#define LCDC_HEOUCTRL_UADDIEN		(0x1 << 4)
-#define LCDC_HEOUCTRL_UDONEIEN		(0x1 << 5)
-
-#define ATMEL_LCDC_HEOUNEXT	0x02B8
-
-#define ATMEL_LCDC_HEOVHEAD	0x02BC
-
-#define ATMEL_LCDC_HEOVADDR	0x02C0
-
-#define ATMEL_LCDC_HEOVCTRL	0x02C4
-#define LCDC_HEOVCTRL_VDFETCH		(0x1 << 0)
-#define LCDC_HEOVCTRL_VDMAIEN		(0x1 << 2)
-#define LCDC_HEOVCTRL_VDSCRIEN		(0x1 << 3)
-#define LCDC_HEOVCTRL_VADDIEN		(0x1 << 4)
-#define LCDC_HEOVCTRL_VDONEIEN		(0x1 << 5)
-
-#define ATMEL_LCDC_HEOVNEXT	0x02C8
-
-#define ATMEL_LCDC_HEOCFG0	0x02CC
-#define LCDC_HEOCFG0_BLEN_OFFSET	4
-#define LCDC_HEOCFG0_BLEN		(0x3 << LCDC_HEOCFG0_BLEN_OFFSET)
-#define		LCDC_HEOCFG0_BLEN_AHB_SINGLE		(0x0 << 4)
-#define		LCDC_HEOCFG0_BLEN_AHB_INCR4		(0x1 << 4)
-#define		LCDC_HEOCFG0_BLEN_AHB_INCR8		(0x2 << 4)
-#define		LCDC_HEOCFG0_BLEN_AHB_INCR16		(0x3 << 4)
-#define LCDC_HEOCFG0_BLENUV_OFFSET	6
-#define LCDC_HEOCFG0_BLENUV		(0x3 << LCDC_HEOCFG0_BLENUV_OFFSET)
-#define		LCDC_HEOCFG0_BLENUV_AHB_SINGLE		(0x0 << 6)
-#define		LCDC_HEOCFG0_BLENUV_AHB_INCR4		(0x1 << 6)
-#define		LCDC_HEOCFG0_BLENUV_AHB_INCR8		(0x2 << 6)
-#define		LCDC_HEOCFG0_BLENUV_AHB_INCR16		(0x3 << 6)
-#define LCDC_HEOCFG0_DLBO		(0x1 << 8)
-#define LCDC_HEOCFG0_ROTDIS		(0x1 << 12)
-#define LCDC_HEOCFG0_LOCKDIS		(0x1 << 13)
-
-#define ATMEL_LCDC_HEOCFG1	0x02D0
-#define LCDC_HEOCFG1_CLUTEN		(0x1 << 0)
-#define LCDC_HEOCFG1_YUVEN		(0x1 << 1)
-#define LCDC_HEOCFG1_RGBMODE_OFFSET	4
-#define LCDC_HEOCFG1_RGBMODE		(0xf << LCDC_HEOCFG1_RGBMODE_OFFSET)
-#define		LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
-#define		LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
-#define		LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
-#define		LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
-#define		LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
-#define LCDC_HEOCFG1_CLUTMODE_OFFSET	8
-#define LCDC_HEOCFG1_CLUTMODE		(0x3 << LCDC_HEOCFG1_CLUTMODE_OFFSET)
-#define		LCDC_HEOCFG1_CLUTMODE_1BPP		(0x0 << 8)
-#define		LCDC_HEOCFG1_CLUTMODE_2BPP		(0x1 << 8)
-#define		LCDC_HEOCFG1_CLUTMODE_4BPP		(0x2 << 8)
-#define		LCDC_HEOCFG1_CLUTMODE_8BPP		(0x3 << 8)
-#define LCDC_HEOCFG1_YUVMODE_OFFSET	12
-#define LCDC_HEOCFG1_YUVMODE		(0xf << LCDC_HEOCFG1_YUVMODE_OFFSET)
-#define		LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR	(0x0 << 12)
-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0	(0x1 << 12)
-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1	(0x2 << 12)
-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2	(0x3 << 12)
-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3	(0x4 << 12)
-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR	(0x5 << 12)
-#define		LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR	(0x6 << 12)
-#define		LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR	(0x7 << 12)
-#define		LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR	(0x8 << 12)
-#define LCDC_HEOCFG1_YUV422ROT		(0x1 << 16)
-#define LCDC_HEOCFG1_YUV422SWP		(0x1 << 17)
-
-#define ATMEL_LCDC_HEOCFG2	0x02D4
-#define LCDC_HEOCFG2_XOFFSET_OFFSET	0
-#define LCDC_HEOCFG2_XOFFSET		(0x7ff << LCDC_HEOCFG2_XOFFSET_OFFSET)
-#define LCDC_HEOCFG2_YOFFSET_OFFSET	16
-#define LCDC_HEOCFG2_YOFFSET		(0x7ff << LCDC_HEOCFG2_YOFFSET_OFFSET)
-
-#define ATMEL_LCDC_HEOCFG3	0x02D8
-#define LCDC_HEOCFG3_XSIZE_OFFSET	0
-#define LCDC_HEOCFG3_XSIZE		(0x7ff << LCDC_HEOCFG3_XSIZE_OFFSET)
-#define LCDC_HEOCFG3_YSIZE_OFFSET	16
-#define LCDC_HEOCFG3_YSIZE		(0x7ff << LCDC_HEOCFG3_YSIZE_OFFSET)
-
-#define ATMEL_LCDC_HEOCFG4	0x02DC
-#define LCDC_HEOCFG4_XMEM_SIZE_OFFSET	0
-#define LCDC_HEOCFG4_XMEM_SIZE		(0x7ff << LCDC_HEOCFG4_XMEM_SIZE_OFFSET)
-#define LCDC_HEOCFG4_YMEM_SIZE_OFFSET	16
-#define LCDC_HEOCFG4_YMEM_SIZE		(0x7ff << LCDC_HEOCFG4_YMEM_SIZE_OFFSET)
-
-#define ATMEL_LCDC_HEOCFG5	0x02E0
-
-#define ATMEL_LCDC_HEOCFG6	0x02E4
-
-#define ATMEL_LCDC_HEOCFG7	0x02E8
-
-#define ATMEL_LCDC_HEOCFG8	0x02EC
-
-#define ATMEL_LCDC_HEOCFG9	0x02F0
-#define LCDC_HEOCFG9_BDEF_OFFSET	0
-#define LCDC_HEOCFG9_BDEF		(0xff << LCDC_HEOCFG9_BDEF_OFFSET)
-#define LCDC_HEOCFG9_GDEF_OFFSET	8
-#define LCDC_HEOCFG9_GDEF		(0xff << LCDC_HEOCFG9_GDEF_OFFSET)
-#define LCDC_HEOCFG9_RDEF_OFFSET	16
-#define LCDC_HEOCFG9_RDEF		(0xff << LCDC_HEOCFG9_RDEF_OFFSET)
-
-#define ATMEL_LCDC_HEOCFG10	0x02F4
-#define LCDC_HEOCFG10_BKEY_OFFSET	0
-#define LCDC_HEOCFG10_BKEY		(0xff << LCDC_HEOCFG10_BKEY_OFFSET)
-#define LCDC_HEOCFG10_GKEY_OFFSET	8
-#define LCDC_HEOCFG10_GKEY		(0xff << LCDC_HEOCFG10_GKEY_OFFSET)
-#define LCDC_HEOCFG10_RKEY_OFFSET	16
-#define LCDC_HEOCFG10_RKEY		(0xff << LCDC_HEOCFG10_RKEY_OFFSET)
-
-#define ATMEL_LCDC_HEOCFG11	0x02F8
-#define LCDC_HEOCFG11_BMASK_OFFSET	0
-#define LCDC_HEOCFG11_BMASK		(0xff << LCDC_HEOCFG11_BMASK_OFFSET)
-#define LCDC_HEOCFG11_GMASK_OFFSET	8
-#define LCDC_HEOCFG11_GMASK		(0xff << LCDC_HEOCFG11_GMASK_OFFSET)
-#define LCDC_HEOCFG11_RMASK_OFFSET	16
-#define LCDC_HEOCFG11_RMASK		(0xff << LCDC_HEOCFG11_RMASK_OFFSET)
-
-#define ATMEL_LCDC_HEOCFG12	0x02FC
-#define LCDC_HEOCFG12_CRKEY		(0x1 << 0)
-#define LCDC_HEOCFG12_INV		(0x1 << 1)
-#define LCDC_HEOCFG12_ITER2BL		(0x1 << 2)
-#define LCDC_HEOCFG12_ITER		(0x1 << 3)
-#define LCDC_HEOCFG12_REVALPHA		(0x1 << 4)
-#define LCDC_HEOCFG12_GAEN		(0x1 << 5)
-#define LCDC_HEOCFG12_LAEN		(0x1 << 6)
-#define LCDC_HEOCFG12_OVR		(0x1 << 7)
-#define LCDC_HEOCFG12_DMA		(0x1 << 8)
-#define LCDC_HEOCFG12_REP		(0x1 << 9)
-#define LCDC_HEOCFG12_DSTKEY		(0x1 << 10)
-#define LCDC_HEOCFG12_VIDPRI		(0x1 << 12)
-#define LCDC_HEOCFG12_GA_OFFSET		16
-#define LCDC_HEOCFG12_GA		(0xff << LCDC_HEOCFG12_GA_OFFSET)
-
-#define ATMEL_LCDC_HEOCFG13	0x0300
-#define LCDC_HEOCFG13_XFACTOR_OFFSET	0
-#define LCDC_HEOCFG13_XFACTOR		(0x1fff << LCDC_HEOCFG13_XFACTOR_OFFSET)
-#define LCDC_HEOCFG13_YFACTOR_OFFSET	16
-#define LCDC_HEOCFG13_YFACTOR		(0x1fff << LCDC_HEOCFG13_YFACTOR_OFFSET)
-#define LCDC_HEOCFG13_SCALEN		(0x1 << 31)
-
-#define ATMEL_LCDC_HEOCFG14	0x0304
-#define LCDC_HEOCFG14_CSCRY_OFFSET	0
-#define LCDC_HEOCFG14_CSCRY		(0x3ff << LCDC_HEOCFG14_CSCRY_OFFSET)
-#define LCDC_HEOCFG14_CSCRU_OFFSET	10
-#define LCDC_HEOCFG14_CSCRU		(0x3ff << LCDC_HEOCFG14_CSCRU_OFFSET)
-#define LCDC_HEOCFG14_CSCRV_OFFSET	20
-#define LCDC_HEOCFG14_CSCRV		(0x3ff << LCDC_HEOCFG14_CSCRV_OFFSET)
-#define LCDC_HEOCFG14_CSCYOFF		(0x1 << 30)
-
-#define ATMEL_LCDC_HEOCFG15	0x0308
-#define LCDC_HEOCFG15_CSCGY_OFFSET	0
-#define LCDC_HEOCFG15_CSCGY		(0x3ff << LCDC_HEOCFG15_CSCGY_OFFSET)
-#define LCDC_HEOCFG15_CSCGU_OFFSET	10
-#define LCDC_HEOCFG15_CSCGU		(0x3ff << LCDC_HEOCFG15_CSCGU_OFFSET)
-#define LCDC_HEOCFG15_CSCGV_OFFSET	20
-#define LCDC_HEOCFG15_CSCGV		(0x3ff << LCDC_HEOCFG15_CSCGV_OFFSET)
-#define LCDC_HEOCFG15_CSCUOFF		(0x1 << 30)
-
-#define ATMEL_LCDC_HEOCFG16	0x030C
-#define LCDC_HEOCFG16_CSCBY_OFFSET	0
-#define LCDC_HEOCFG16_CSCBY		(0x3ff << LCDC_HEOCFG16_CSCBY_OFFSET)
-#define LCDC_HEOCFG16_CSCBU_OFFSET	10
-#define LCDC_HEOCFG16_CSCBU		(0x3ff << LCDC_HEOCFG16_CSCBU_OFFSET)
-#define LCDC_HEOCFG16_CSCBV_OFFSET	20
-#define LCDC_HEOCFG16_CSCBV		(0x3ff << LCDC_HEOCFG16_CSCBV_OFFSET)
-#define LCDC_HEOCFG16_CSCVOFF		(0x1 << 30)
-
-#define ATMEL_LCDC_HCRCHER	0x0340
-#define LCDC_HCRCHER_CHEN		(0x1 << 0)
-#define LCDC_HCRCHER_UPDATEEN		(0x1 << 1)
-#define LCDC_HCRCHER_A2QEN		(0x1 << 2)
-
-#define ATMEL_LCDC_HCRCHDR	0x0344
-#define LCDC_HCRCHDR_CHDIS		(0x1 << 0)
-#define LCDC_HCRCHDR_CHRST		(0x1 << 8)
-
-#define ATMEL_LCDC_HCRCHSR	0x0348
-#define LCDC_HCRCHSR_CHSR		(0x1 << 0)
-#define LCDC_HCRCHSR_UPDATESR		(0x1 << 1)
-#define LCDC_HCRCHSR_A2QSR		(0x1 << 2)
-
-#define ATMEL_LCDC_HCRIER	0x034C
-#define LCDC_HCRIER_DMA			(0x1 << 2)
-#define LCDC_HCRIER_DSCR		(0x1 << 3)
-#define LCDC_HCRIER_ADD			(0x1 << 4)
-#define LCDC_HCRIER_DONE		(0x1 << 5)
-#define LCDC_HCRIER_OVR			(0x1 << 6)
-
-#define ATMEL_LCDC_HCRIDR	0x0350
-#define LCDC_HCRIDR_DMA			(0x1 << 2)
-#define LCDC_HCRIDR_DSCR		(0x1 << 3)
-#define LCDC_HCRIDR_ADD			(0x1 << 4)
-#define LCDC_HCRIDR_DONE		(0x1 << 5)
-#define LCDC_HCRIDR_OVR			(0x1 << 6)
-
-#define ATMEL_LCDC_HCRIMR	0x0354
-#define LCDC_HCRIMR_DMA			(0x1 << 2)
-#define LCDC_HCRIMR_DSCR		(0x1 << 3)
-#define LCDC_HCRIMR_ADD			(0x1 << 4)
-#define LCDC_HCRIMR_DONE		(0x1 << 5)
-#define LCDC_HCRIMR_OVR			(0x1 << 6)
-
-#define ATMEL_LCDC_HCRISR	0x0358
-#define LCDC_HCRISR_DMA			(0x1 << 2)
-#define LCDC_HCRISR_DSCR		(0x1 << 3)
-#define LCDC_HCRISR_ADD			(0x1 << 4)
-#define LCDC_HCRISR_DONE		(0x1 << 5)
-#define LCDC_HCRISR_OVR			(0x1 << 6)
-
-#define ATMEL_LCDC_HCRHEAD	0x035C
-
-#define ATMEL_LCDC_HCRADDR	0x0360
-
-#define ATMEL_LCDC_HCRCTRL	0x0364
-#define LCDC_HCRCTRL_DFETCH		(0x1 << 0)
-#define LCDC_HCRCTRL_LFETCH		(0x1 << 1)
-#define LCDC_HCRCTRL_DMAIEN		(0x1 << 2)
-#define LCDC_HCRCTRL_DSCRIEN		(0x1 << 3)
-#define LCDC_HCRCTRL_ADDIEN		(0x1 << 4)
-#define LCDC_HCRCTRL_DONEIEN		(0x1 << 5)
-
-#define ATMEL_LCDC_HCRNEXT	0x0368
-
-#define ATMEL_LCDC_HCRCFG0	0x036C
-#define LCDC_HCRCFG0_BLEN_OFFSET	4
-#define LCDC_HCRCFG0_BLEN		(0x3 << LCDC_HCRCFG0_BLEN_OFFSET)
-#define		LCDC_HCRCFG0_BLEN_AHB_SINGLE		(0x0 << 4)
-#define		LCDC_HCRCFG0_BLEN_AHB_INCR4		(0x1 << 4)
-#define		LCDC_HCRCFG0_BLEN_AHB_INCR8		(0x2 << 4)
-#define		LCDC_HCRCFG0_BLEN_AHB_INCR16		(0x3 << 4)
-#define LCDC_HCRCFG0_DLBO		(0x1 << 8)
-
-#define ATMEL_LCDC_HCRCFG1	0x0370
-#define LCDC_HCRCFG1_CLUTEN		(0x1 << 0)
-#define LCDC_HCRCFG1_RGBMODE_OFFSET	4
-#define LCDC_HCRCFG1_RGBMODE		(0xf << LCDC_HCRCFG1_RGBMODE_OFFSET)
-#define		LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444	(0x0 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444	(0x1 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444	(0x2 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565	(0x3 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555	(0x4 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666	(0x5 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666	(0x7 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED	(0x8 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888	(0x9 << 4)
-#define		LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
-#define		LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888	(0xB << 4)
-#define		LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888	(0xC << 4)
-#define		LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888	(0xD << 4)
-#define LCDC_HCRCFG1_CLUTMODE_OFFSET	8
-#define LCDC_HCRCFG1_CLUTMODE		(0x3 << LCDC_HCRCFG1_CLUTMODE_OFFSET)
-#define		LCDC_HCRCFG1_CLUTMODE_1BPP		(0x0 << 8)
-#define		LCDC_HCRCFG1_CLUTMODE_2BPP		(0x1 << 8)
-#define		LCDC_HCRCFG1_CLUTMODE_4BPP		(0x2 << 8)
-#define		LCDC_HCRCFG1_CLUTMODE_8BPP		(0x3 << 8)
-
-#define ATMEL_LCDC_HCRCFG2	0x0374
-#define LCDC_HCRCFG2_XOFFSET_OFFSET	0
-#define LCDC_HCRCFG2_XOFFSET		(0x7ff << LCDC_HCRCFG2_XOFFSET_OFFSET)
-#define LCDC_HCRCFG2_YOFFSET_OFFSET	16
-#define LCDC_HCRCFG2_YOFFSET		(0x7ff << LCDC_HCRCFG2_YOFFSET_OFFSET)
-
-#define ATMEL_LCDC_HCRCFG3	0x0378
-#define LCDC_HCRCFG3_XSIZE_OFFSET	0
-#define LCDC_HCRCFG3_XSIZE		(0x7f << LCDC_HCRCFG3_XSIZE_OFFSET)
-#define LCDC_HCRCFG3_YSIZE_OFFSET	16
-#define LCDC_HCRCFG3_YSIZE		(0x7f << LCDC_HCRCFG3_YSIZE_OFFSET)
-
-#define ATMEL_LCDC_HCRCFG4	0x037C
-
-#define ATMEL_LCDC_HCRCFG6	0x0384
-#define LCDC_HCRCFG6_BDEF_OFFSET	0
-#define LCDC_HCRCFG6_BDEF		(0xff << LCDC_HCRCFG6_BDEF_OFFSET)
-#define LCDC_HCRCFG6_GDEF_OFFSET	8
-#define LCDC_HCRCFG6_GDEF		(0xff << LCDC_HCRCFG6_GDEF_OFFSET)
-#define LCDC_HCRCFG6_RDEF_OFFSET	16
-#define LCDC_HCRCFG6_RDEF		(0xff << LCDC_HCRCFG6_RDEF_OFFSET)
-
-#define ATMEL_LCDC_HCRCFG7	0x0388
-#define LCDC_HCRCFG7_BKEY_OFFSET	0
-#define LCDC_HCRCFG7_BKEY		(0xff << LCDC_HCRCFG7_BKEY_OFFSET)
-#define LCDC_HCRCFG7_GKEY_OFFSET	8
-#define LCDC_HCRCFG7_GKEY		(0xff << LCDC_HCRCFG7_GKEY_OFFSET)
-#define LCDC_HCRCFG7_RKEY_OFFSET	16
-#define LCDC_HCRCFG7_RKEY		(0xff << LCDC_HCRCFG7_RKEY_OFFSET)
-
-#define ATMEL_LCDC_HCRCFG8	0x038C
-#define LCDC_HCRCFG8_BMASK_OFFSET	0
-#define LCDC_HCRCFG8_BMASK		(0xff << LCDC_HCRCFG8_BMASK_OFFSET)
-#define LCDC_HCRCFG8_GMASK_OFFSET	8
-#define LCDC_HCRCFG8_GMASK		(0xff << LCDC_HCRCFG8_GMASK_OFFSET)
-#define LCDC_HCRCFG8_RMASK_OFFSET	16
-#define LCDC_HCRCFG8_RMASK		(0xff << LCDC_HCRCFG8_RMASK_OFFSET)
-
-#define ATMEL_LCDC_HCRCFG9	0x0390
-#define LCDC_HCRCFG9_CRKEY		(0x1 << 0)
-#define LCDC_HCRCFG9_INV		(0x1 << 1)
-#define LCDC_HCRCFG9_ITER2BL		(0x1 << 2)
-#define LCDC_HCRCFG9_ITER		(0x1 << 3)
-#define LCDC_HCRCFG9_REVALPHA		(0x1 << 4)
-#define LCDC_HCRCFG9_GAEN		(0x1 << 5)
-#define LCDC_HCRCFG9_LAEN		(0x1 << 6)
-#define LCDC_HCRCFG9_OVR		(0x1 << 7)
-#define LCDC_HCRCFG9_DMA		(0x1 << 8)
-#define LCDC_HCRCFG9_REP		(0x1 << 9)
-#define LCDC_HCRCFG9_DSTKEY		(0x1 << 10)
-#define LCDC_HCRCFG9_GA_OFFSET		16
-#define LCDC_HCRCFG9_GA_Msk		(0xff << LCDC_HCRCFG9_GA_OFFSET)
-
-#define ATMEL_LCDC_BASECLUT	0x400
-#define ATMEL_LCDC2_BASECLUT	0x600
-#define LCDC_BASECLUT_BCLUT_OFFSET	0
-#define LCDC_BASECLUT_BCLUT		(0xff << LCDC_BASECLUT_BCLUT_OFFSET)
-#define LCDC_BASECLUT_GCLUT_OFFSET	8
-#define LCDC_BASECLUT_GCLUT		(0xff << LCDC_BASECLUT_GCLUT_OFFSET)
-#define LCDC_BASECLUT_RCLUT_OFFSET	16
-#define LCDC_BASECLUT_RCLUT		(0xff << LCDC_BASECLUT_RCLUT_OFFSET)
-
-#define ATMEL_LCDC_OVR1CLUT	0x800
-#define ATMEL_LCDC2_OVR1CLUT	0xa00
-#define LCDC_OVR1CLUT_BCLUT_OFFSET	0
-#define LCDC_OVR1CLUT_BCLUT		(0xff << LCDC_OVR1CLUT_BCLUT_OFFSET)
-#define LCDC_OVR1CLUT_GCLUT_OFFSET	8
-#define LCDC_OVR1CLUT_GCLUT		(0xff << LCDC_OVR1CLUT_GCLUT_OFFSET)
-#define LCDC_OVR1CLUT_RCLUT_OFFSET	16
-#define LCDC_OVR1CLUT_RCLUT		(0xff << LCDC_OVR1CLUT_RCLUT_OFFSET)
-#define LCDC_OVR1CLUT_ACLUT_OFFSET	24
-#define LCDC_OVR1CLUT_ACLUT		(0xff << LCDC_OVR1CLUT_ACLUT_OFFSET)
-
-#define ATMEL_LCDC_OVR2CLUT	0xe00
-#define LCDC_OVR2CLUT_BCLUT_OFFSET	0
-#define LCDC_OVR2CLUT_BCLUT		(0xff << LCDC_OVR2CLUT_BCLUT_OFFSET)
-#define LCDC_OVR2CLUT_GCLUT_OFFSET	8
-#define LCDC_OVR2CLUT_GCLUT		(0xff << LCDC_OVR2CLUT_GCLUT_OFFSET)
-#define LCDC_OVR2CLUT_RCLUT_OFFSET	16
-#define LCDC_OVR2CLUT_RCLUT		(0xff << LCDC_OVR2CLUT_RCLUT_OFFSET)
-#define LCDC_OVR2CLUT_ACLUT_OFFSET	24
-#define LCDC_OVR2CLUT_ACLUT		(0xff << LCDC_OVR2CLUT_ACLUT_OFFSET)
-
-#define ATMEL_LCDC_HEOCLUT	0x1000
-#define ATMEL_LCDC2_HEOCLUT	0x1200
-#define LCDC_HEOCLUT_BCLUT_OFFSET	0
-#define LCDC_HEOCLUT_BCLUT		(0xff << LCDC_HEOCLUT_BCLUT_OFFSET)
-#define LCDC_HEOCLUT_GCLUT_OFFSET	8
-#define LCDC_HEOCLUT_GCLUT		(0xff << LCDC_HEOCLUT_GCLUT_OFFSET)
-#define LCDC_HEOCLUT_RCLUT_OFFSET	16
-#define LCDC_HEOCLUT_RCLUT		(0xff << LCDC_HEOCLUT_RCLUT_OFFSET)
-#define LCDC_HEOCLUT_ACLUT_OFFSET	24
-#define LCDC_HEOCLUT_ACLUT		(0xff << LCDC_HEOCLUT_ACLUT_OFFSET)
-
-#define ATMEL_LCDC_HCRCLUT	0x1400
-#define ATMEL_LCDC2_HCRCLUT	0x1600
-#define LCDC_HCRCLUT_BCLUT_OFFSET	0
-#define LCDC_HCRCLUT_BCLUT		(0xff << LCDC_HCRCLUT_BCLUT_OFFSET)
-#define LCDC_HCRCLUT_GCLUT_OFFSET	8
-#define LCDC_HCRCLUT_GCLUT		(0xff << LCDC_HCRCLUT_GCLUT_OFFSET)
-#define LCDC_HCRCLUT_RCLUT_OFFSET	16
-#define LCDC_HCRCLUT_RCLUT		(0xff << LCDC_HCRCLUT_RCLUT_OFFSET)
-#define LCDC_HCRCLUT_ACLUT_OFFSET	24
-#define LCDC_HCRCLUT_ACLUT		(0xff << LCDC_HCRCLUT_ACLUT_OFFSET)
-
-/* Base layer CLUT */
-#define ATMEL_HLCDC_LUT			0x0400
-
-
-#endif /* __MACH_ATMEL_HLCDC4_H__ */
diff --git a/arch/arm/mach-at91/include/mach/barebox-arm-head.h b/arch/arm/mach-at91/include/mach/barebox-arm-head.h
deleted file mode 100644
index e0e07500a2..0000000000
--- a/arch/arm/mach-at91/include/mach/barebox-arm-head.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef __MACH_ARM_HEAD_H
-#define __MACH_ARM_HEAD_H
-
-#ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM
-#define AT91_EXV6	".word _barebox_image_size\n"
-#else
-#define AT91_EXV6	".word _barebox_bare_init_size\n"
-#endif
-
-static inline void __barebox_arm_head(void)
-{
-	__asm__ __volatile__ (
-#ifdef CONFIG_THUMB2_BAREBOX
-#error Thumb2 is not supported
-#else
-		"b 2f\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		AT91_EXV6				/* image size to load by the bootrom */
-		"1: b 1b\n"
-		"1: b 1b\n"
-#endif
-		".asciz \"barebox\"\n"
-		".word _text\n"				/* text base. If copied there,
-							 * barebox can skip relocation
-							 */
-		".word _barebox_image_size\n"		/* image size to copy */
-		".rept 8\n"
-		".word 0x55555555\n"
-		".endr\n"
-		"2:\n"
-	);
-}
-
-static inline void barebox_arm_head(void)
-{
-	__barebox_arm_head();
-	__asm__ __volatile__ (
-		"b barebox_arm_reset_vector\n"
-	);
-}
-
-#endif /* __MACH_ARM_HEAD_H */
diff --git a/arch/arm/mach-at91/include/mach/barebox-arm.h b/arch/arm/mach-at91/include/mach/barebox-arm.h
deleted file mode 100644
index 4a65c6f8fa..0000000000
--- a/arch/arm/mach-at91/include/mach/barebox-arm.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef AT91_BAREBOX_ARM_H_
-#define AT91_BAREBOX_ARM_H_
-
-#include <asm/barebox-arm.h>
-
-#define SAMA5_ENTRY_FUNCTION(name, r4)						\
-	void name (u32 r0, u32 r1, u32 r2, u32 r3);				\
-										\
-	static void __##name(u32);						\
-										\
-	void NAKED __section(.text_head_entry_##name)	name			\
-				(u32 r0, u32 r1, u32 r2, u32 r3)		\
-		{								\
-			register u32 r4 asm("r4");				\
-			__barebox_arm_head();					\
-			__##name(r4);						\
-		}								\
-		static void NAKED noinline __##name				\
-			(u32 r4)
-#endif
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
deleted file mode 100644
index 754a6b7c5e..0000000000
--- a/arch/arm/mach-at91/include/mach/board.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2005 HP Labs */
-
-/* [origin Linux: arch/arm/mach-at91/include/mach/board.h] */
-
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-
-#include <mach/hardware.h>
-#include <linux/sizes.h>
-#include <net.h>
-#include <i2c/i2c.h>
-#include <spi/spi.h>
-#include <linux/mtd/mtd.h>
-#include <fb.h>
-#include <video/atmel_lcdc.h>
-#include <mach/atmel_hlcdc.h>
-#include <linux/phy.h>
-#include <platform_data/macb.h>
-
-void at91_set_main_clock(unsigned long rate);
-
-#define AT91_MAX_USBH_PORTS	3
-
- /* USB Host */
-struct at91_usbh_data {
-	u8		ports;		/* number of ports on root hub */
-	int		vbus_pin[AT91_MAX_USBH_PORTS];	/* port power-control pin */
-	u8	vbus_pin_active_low[AT91_MAX_USBH_PORTS];	/* vbus polarity */
-};
-extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
-extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
-
-void atmel_nand_load_image(void *dest, int size, int pagesize, int blocksize);
-
- /* USB Device */
-struct at91_udc_data {
-	int	vbus_pin;		/* high == host powering us */
-	u8	vbus_active_low;	/* vbus polarity */
-	u8	vbus_polled;		/* Use polling, not interrupt */
-	int	pullup_pin;		/* active == D+ pulled up */
-	u8	pullup_active_low;	/* true == pullup_pin is active low */
-};
-extern void __init at91_add_device_udc(struct at91_udc_data *data);
-
- /* NAND / SmartMedia */
-struct atmel_nand_data {
-	int		enable_pin;	/* chip enable */
-	int		det_pin;	/* card detect */
-	int		rdy_pin;	/* ready/busy */
-	u8		ale;		/* address line number connected to ALE */
-	u8		cle;		/* address line number connected to CLE */
-	u8		bus_width_16;	/* buswidth is 16 bit */
-	u8		ecc_mode;	/* NAND_ECC_* */
-	u8		ecc_strength;	/* number of bits to correct per ECC step */
-	u8		ecc_size_shift;	/* data bytes covered by a single ECC step.*/
-	u8		on_flash_bbt;	/* Use flash based bbt */
-	u8		has_pmecc;	/* Use PMECC */
-	u8		bus_on_d0;
-
-	u8		pmecc_corr_cap;
-	u16		pmecc_sector_size;
-	u32		pmecc_lookup_table_offset;
-};
-
-void at91_add_device_nand(struct atmel_nand_data *data);
-
- /* Ethernet (EMAC & MACB) */
-#define AT91SAM_ETX2_ETX3_ALTERNATIVE	(1 << 0)
-
-void at91_add_device_eth(int id, struct macb_platform_data *data);
-
-void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
-
-/* SDRAM */
-void at91_add_device_sdram(u32 size);
-
- /* Serial */
-#define ATMEL_UART_CTS	0x01
-#define ATMEL_UART_RTS	0x02
-#define ATMEL_UART_DSR	0x04
-#define ATMEL_UART_DTR	0x08
-#define ATMEL_UART_DCD	0x10
-#define ATMEL_UART_RI	0x20
-
-resource_size_t __init at91_configure_dbgu(void);
-resource_size_t __init at91_configure_usart0(unsigned pins);
-resource_size_t __init at91_configure_usart1(unsigned pins);
-resource_size_t __init at91_configure_usart2(unsigned pins);
-resource_size_t __init at91_configure_usart3(unsigned pins);
-resource_size_t __init at91_configure_usart4(unsigned pins);
-resource_size_t __init at91_configure_usart5(unsigned pins);
-resource_size_t __init at91_configure_usart6(unsigned pins);
-
-#if defined(CONFIG_DRIVER_SERIAL_ATMEL)
-static inline struct device_d * at91_register_uart(unsigned id, unsigned pins)
-{
-	resource_size_t start;
-	resource_size_t size = SZ_16K;
-
-	switch (id) {
-		case 0:		/* DBGU */
-			start = at91_configure_dbgu();
-			size = 512;
-			break;
-		case 1:
-			start = at91_configure_usart0(pins);
-			break;
-		case 2:
-			start = at91_configure_usart1(pins);
-			break;
-		case 3:
-			start = at91_configure_usart2(pins);
-			break;
-		case 4:
-			start = at91_configure_usart3(pins);
-			break;
-		case 5:
-			start = at91_configure_usart4(pins);
-			break;
-		case 6:
-			start = at91_configure_usart5(pins);
-			break;
-		default:
-			return NULL;
-	}
-
-	return add_generic_device("atmel_usart", id, NULL, start, size,
-			   IORESOURCE_MEM, NULL);
-}
-#else
-static inline struct device_d * at91_register_uart(unsigned id, unsigned pins)
-{
-	return NULL;
-}
-#endif
-
-#include <platform_data/atmel-mci.h>
-
-/* SPI Master platform data */
-struct at91_spi_platform_data {
-	int *chipselect;	/* array of gpio_pins */
-	int num_chipselect;	/* chipselect array entry count */
-};
-
-void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata);
-
-void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data);
-
-void at91sam_phy_reset(void __iomem *rstc_base);
-
-void at91sam9_reset(void __iomem *sdram, void __iomem *rstc_cr);
-void at91sam9g45_reset(void __iomem *sdram, void __iomem *rstc_cr);
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/bootstrap.h b/arch/arm/mach-at91/include/mach/bootstrap.h
deleted file mode 100644
index a3d19dd54a..0000000000
--- a/arch/arm/mach-at91/include/mach/bootstrap.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
- *
- * Under GPLv2
- */
-
-#ifndef __MACH_BOOTSTRAP_H__
-#define __MACH_BOOTSTRAP_H__
-
-#ifdef CONFIG_MTD_M25P80
-void * bootstrap_board_read_m25p80(void);
-#else
-static inline void * bootstrap_board_read_m25p80(void)
-{
-	return NULL;
-}
-#endif
-
-#ifdef CONFIG_MTD_DATAFLASH
-void * bootstrap_board_read_dataflash(void);
-#else
-static inline void * bootstrap_board_read_dataflash(void)
-{
-	return NULL;
-}
-#endif
-
-#endif /* __MACH_BOOTSTRAP_H__ */
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
deleted file mode 100644
index 37e516947b..0000000000
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2006 SAN People */
-/* SPDX-FileCopyrightText: 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */
-
-/* arch/arm/mach-at91/include/mach/cpu.h */
-
-#ifndef __MACH_CPU_H__
-#define __MACH_CPU_H__
-
-#define ARCH_ID_AT91RM9200	0x09290780
-#define ARCH_ID_AT91SAM9260	0x019803a0
-#define ARCH_ID_AT91SAM9261	0x019703a0
-#define ARCH_ID_AT91SAM9263	0x019607a0
-#define ARCH_ID_AT91SAM9G10	0x019903a0
-#define ARCH_ID_AT91SAM9G20	0x019905a0
-#define ARCH_ID_AT91SAM9RL64	0x019b03a0
-#define ARCH_ID_AT91SAM9G45	0x819b05a0
-#define ARCH_ID_AT91SAM9G45MRL	0x819b05a2	/* aka 9G45-ES2 & non ES lots */
-#define ARCH_ID_AT91SAM9G45ES	0x819b05a1	/* 9G45-ES (Engineering Sample) */
-#define ARCH_ID_AT91SAM9X5	0x819a05a0
-#define ARCH_ID_AT91SAM9N12	0x819a07a0
-#define ARCH_ID_SAMA5		0x8A5C07C0
-
-#define ARCH_ID_AT91SAM9XE128	0x329973a0
-#define ARCH_ID_AT91SAM9XE256	0x329a93a0
-#define ARCH_ID_AT91SAM9XE512	0x329aa3a0
-
-#define ARCH_ID_AT91M40800	0x14080044
-#define ARCH_ID_AT91R40807	0x44080746
-#define ARCH_ID_AT91M40807	0x14080745
-#define ARCH_ID_AT91R40008	0x44000840
-
-#define ARCH_EXID_AT91SAM9M11	0x00000001
-#define ARCH_EXID_AT91SAM9M10	0x00000002
-#define ARCH_EXID_AT91SAM9G46	0x00000003
-#define ARCH_EXID_AT91SAM9G45	0x00000004
-
-#define ARCH_EXID_AT91SAM9G15	0x00000000
-#define ARCH_EXID_AT91SAM9G35	0x00000001
-#define ARCH_EXID_AT91SAM9X35	0x00000002
-#define ARCH_EXID_AT91SAM9G25	0x00000003
-#define ARCH_EXID_AT91SAM9X25	0x00000004
-
-#define ARCH_EXID_AT91SAM9N12	0x00000006
-#define ARCH_EXID_AT91SAM9CN11	0x00000009
-#define ARCH_EXID_AT91SAM9CN12	0x00000005
-
-#define ARCH_EXID_SAMA5D21CU		0x0000005a
-#define ARCH_EXID_SAMA5D225C_D1M	0x00000053
-#define ARCH_EXID_SAMA5D22CU		0x00000059
-#define ARCH_EXID_SAMA5D22CN		0x00000069
-#define ARCH_EXID_SAMA5D23CU		0x00000058
-#define ARCH_EXID_SAMA5D24CX		0x00000004
-#define ARCH_EXID_SAMA5D24CU		0x00000014
-#define ARCH_EXID_SAMA5D26CU		0x00000012
-#define ARCH_EXID_SAMA5D27C_D1G 	0x00000033
-#define ARCH_EXID_SAMA5D27C_D5M 	0x00000032
-#define ARCH_EXID_SAMA5D27CU		0x00000011
-#define ARCH_EXID_SAMA5D27CN		0x00000021
-#define ARCH_EXID_SAMA5D28C_D1G 	0x00000013
-#define ARCH_EXID_SAMA5D28CU		0x00000010
-#define ARCH_EXID_SAMA5D28CN		0x00000020
-
-#define ARCH_EXID_SAMA5D3	0x00004300
-#define ARCH_EXID_SAMA5D31	0x00444300
-#define ARCH_EXID_SAMA5D33	0x00414300
-#define ARCH_EXID_SAMA5D34	0x00414301
-#define ARCH_EXID_SAMA5D35	0x00584300
-#define ARCH_EXID_SAMA5D36	0x00004301
-
-#define ARCH_EXID_SAMA5D4	0x00000007
-#define ARCH_EXID_SAMA5D41	0x00000001
-#define ARCH_EXID_SAMA5D42	0x00000002
-#define ARCH_EXID_SAMA5D43	0x00000003
-#define ARCH_EXID_SAMA5D44	0x00000004
-
-#define ARCH_FAMILY_AT91X92	0x09200000
-#define ARCH_FAMILY_AT91SAM9	0x01900000
-#define ARCH_FAMILY_AT91SAM9XE	0x02900000
-
-/* RM9200 type */
-#define ARCH_REVISON_9200_BGA	(0 << 0)
-#define ARCH_REVISON_9200_PQFP	(1 << 0)
-
-#ifndef __ASSEMBLY__
-enum at91_soc_type {
-	/* 920T */
-	AT91_SOC_RM9200,
-
-	/* SAM92xx */
-	AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
-
-	/* SAM9Gxx */
-	AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
-
-	/* SAM9RL */
-	AT91_SOC_SAM9RL,
-
-	/* SAM9X5 */
-	AT91_SOC_SAM9X5,
-
-	/* SAM9N12 */
-	AT91_SOC_SAM9N12,
-
-	/* SAMA5D2 */
-	AT91_SOC_SAMA5D2,
-
-	/* SAMA5D3 */
-	AT91_SOC_SAMA5D3,
-
-	/* SAMA5D4 */
-	AT91_SOC_SAMA5D4,
-
-	/* Unknown type */
-	AT91_SOC_NONE
-};
-
-enum at91_soc_subtype {
-	/* RM9200 */
-	AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
-
-	/* SAM9260 */
-	AT91_SOC_SAM9XE,
-
-	/* SAM9G45 */
-	AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
-
-	/* SAM9X5 */
-	AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
-	AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
-
-	/* SAM9N12 */
-	AT91_SOC_SAM9CN11, AT91_SOC_SAM9CN12,
-
-	/* SAMA5D2 */
-	AT91_SOC_SAMA5D21CU,
-	AT91_SOC_SAMA5D225C_D1M, AT91_SOC_SAMA5D22CU, AT91_SOC_SAMA5D22CN,
-	AT91_SOC_SAMA5D23CU, AT91_SOC_SAMA5D24CX, AT91_SOC_SAMA5D24CU,
-	AT91_SOC_SAMA5D26CU, AT91_SOC_SAMA5D27C_D1G, AT91_SOC_SAMA5D27C_D5M,
-	AT91_SOC_SAMA5D27CU, AT91_SOC_SAMA5D27CN, AT91_SOC_SAMA5D28C_D1G,
-	AT91_SOC_SAMA5D28CU, AT91_SOC_SAMA5D28CN,
-
-	/* SAMA5D3 */
-	AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
-	AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
-
-	/* SAMA5D4 */
-	AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
-	AT91_SOC_SAMA5D44,
-
-	/* Unknown subtype */
-	AT91_SOC_SUBTYPE_NONE
-};
-
-struct at91_socinfo {
-	unsigned int type, subtype;
-	unsigned int cidr, exid;
-};
-
-extern struct at91_socinfo at91_soc_initdata;
-const char *at91_get_soc_type(struct at91_socinfo *c);
-const char *at91_get_soc_subtype(struct at91_socinfo *c);
-extern unsigned long at91_bootsource;
-
-static inline int at91_soc_is_detected(void)
-{
-	return at91_soc_initdata.type != AT91_SOC_NONE;
-}
-
-#ifdef CONFIG_SOC_AT91RM9200
-#define cpu_is_at91rm9200()	(at91_soc_initdata.type == AT91_SOC_RM9200)
-#define cpu_is_at91rm9200_bga()	(at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
-#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
-#else
-#define cpu_is_at91rm9200()	(0)
-#define cpu_is_at91rm9200_bga()	(0)
-#define cpu_is_at91rm9200_pqfp() (0)
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9260
-#define cpu_is_at91sam9xe()	(at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
-#define cpu_is_at91sam9260()	(at91_soc_initdata.type == AT91_SOC_SAM9260)
-#define cpu_is_at91sam9g20()	(at91_soc_initdata.type == AT91_SOC_SAM9G20)
-#else
-#define cpu_is_at91sam9xe()	(0)
-#define cpu_is_at91sam9260()	(0)
-#define cpu_is_at91sam9g20()	(0)
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9261
-#define cpu_is_at91sam9261()	(at91_soc_initdata.type == AT91_SOC_SAM9261)
-#define cpu_is_at91sam9g10()	(at91_soc_initdata.type == AT91_SOC_SAM9G10)
-#else
-#define cpu_is_at91sam9261()	(0)
-#define cpu_is_at91sam9g10()	(0)
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9263
-#define cpu_is_at91sam9263()	(at91_soc_initdata.type == AT91_SOC_SAM9263)
-#else
-#define cpu_is_at91sam9263()	(0)
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9RL
-#define cpu_is_at91sam9rl()	(at91_soc_initdata.type == AT91_SOC_SAM9RL)
-#else
-#define cpu_is_at91sam9rl()	(0)
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9G45
-#define cpu_is_at91sam9g45()	(at91_soc_initdata.type == AT91_SOC_SAM9G45)
-#define cpu_is_at91sam9g45es()	(at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
-#define cpu_is_at91sam9m10()	(at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
-#define cpu_is_at91sam9g46()	(at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
-#define cpu_is_at91sam9m11()	(at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
-#else
-#define cpu_is_at91sam9g45()	(0)
-#define cpu_is_at91sam9g45es()	(0)
-#define cpu_is_at91sam9m10()	(0)
-#define cpu_is_at91sam9g46()	(0)
-#define cpu_is_at91sam9m11()	(0)
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9X5
-#define cpu_is_at91sam9x5()	(at91_soc_initdata.type == AT91_SOC_SAM9X5)
-#define cpu_is_at91sam9g15()	(at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
-#define cpu_is_at91sam9g35()	(at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
-#define cpu_is_at91sam9x35()	(at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
-#define cpu_is_at91sam9g25()	(at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
-#define cpu_is_at91sam9x25()	(at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
-#else
-#define cpu_is_at91sam9x5()	(0)
-#define cpu_is_at91sam9g15()	(0)
-#define cpu_is_at91sam9g35()	(0)
-#define cpu_is_at91sam9x35()	(0)
-#define cpu_is_at91sam9g25()	(0)
-#define cpu_is_at91sam9x25()	(0)
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9N12
-#define cpu_is_at91sam9n12()	(at91_soc_initdata.type == AT91_SOC_SAM9N12)
-#else
-#define cpu_is_at91sam9n12()	(0)
-#endif
-
-#ifdef CONFIG_SOC_SAMA5D2
-#define cpu_is_sama5d2()	(at91_soc_initdata.type == AT91_SOC_SAMA5D2)
-#define cpu_is_sama5d21()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D21CU)
-#define cpu_is_sama5d22()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D225C_D1M \
-				|| at91_soc_initdata.subtype == AT91_SOC_SAMA5D225C_D1M \
-				|| at91_soc_initdata.subtype == AT91_SOC_SAMA5D22CU \
-				|| at91_soc_initdata.subtype == AT91_SOC_SAMA5D22CN)
-#define cpu_is_sama5d23()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D23CU)
-#define cpu_is_sama5d24()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D24CX \
-				|| at91_soc_initdata.subtype == AT91_SOC_SAMA5D24CU)
-#define cpu_is_sama5d26()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D26CU)
-#define cpu_is_sama5d27()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D27C_D1G \
-				|| at91_soc_initdata.subtype == AT91_SOC_SAMA5D27C_D5M \
-				|| at91_soc_initdata.subtype == AT91_SOC_SAMA5D27CU \
-				|| at91_soc_initdata.subtype == AT91_SOC_SAMA5D27CN)
-#define cpu_is_sama5d28()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D28C_D1G \
-				|| at91_soc_initdata.subtype == AT91_SOC_SAMA5D28CU \
-				|| at91_soc_initdata.subtype == AT91_SOC_SAMA5D28CN)
-#else
-#define cpu_is_sama5d2()	(0)
-#define cpu_is_sama5d21()	(0)
-#define cpu_is_sama5d22()	(0)
-#define cpu_is_sama5d23()	(0)
-#define cpu_is_sama5d24()	(0)
-#define cpu_is_sama5d26()	(0)
-#define cpu_is_sama5d27()	(0)
-#define cpu_is_sama5d28()	(0)
-#endif
-
-#ifdef CONFIG_SOC_SAMA5D3
-#define cpu_is_sama5d3()	(at91_soc_initdata.type == AT91_SOC_SAMA5D3)
-#define cpu_is_sama5d31()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D31)
-#define cpu_is_sama5d33()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D33)
-#define cpu_is_sama5d34()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D34)
-#define cpu_is_sama5d35()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D35)
-#define cpu_is_sama5d36()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D36)
-#else
-#define cpu_is_sama5d3()	(0)
-#define cpu_is_sama5d31()	(0)
-#define cpu_is_sama5d33()	(0)
-#define cpu_is_sama5d34()	(0)
-#define cpu_is_sama5d35()	(0)
-#define cpu_is_sama5d36()	(0)
-#endif
-
-#ifdef CONFIG_SOC_SAMA5D4
-#define cpu_is_sama5d4()	(at91_soc_initdata.type == AT91_SOC_SAMA5D4)
-#define cpu_is_sama5d41()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D41)
-#define cpu_is_sama5d42()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D42)
-#define cpu_is_sama5d43()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D43)
-#define cpu_is_sama5d44()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D44)
-#else
-#define cpu_is_sama5d4()	(0)
-#define cpu_is_sama5d41()	(0)
-#define cpu_is_sama5d42()	(0)
-#define cpu_is_sama5d43()	(0)
-#define cpu_is_sama5d44()	(0)
-#endif
-
-/*
- * Since this is ARM, we will never run on any AVR32 CPU. But these
- * definitions may reduce clutter in common drivers.
- */
-#define cpu_is_at32ap7000()	(0)
-#endif /* __ASSEMBLY__ */
-
-#endif /* __MACH_CPU_H__ */
diff --git a/arch/arm/mach-at91/include/mach/ddramc.h b/arch/arm/mach-at91/include/mach/ddramc.h
deleted file mode 100644
index 7daef17636..0000000000
--- a/arch/arm/mach-at91/include/mach/ddramc.h
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: BSD-1-Clause
-/*
- * Copyright (c) 2006, Atmel Corporation
- */
-#ifndef __DDRAMC_H__
-#define __DDRAMC_H__
-
-/* Note: reserved bits must always be zeroed */
-struct at91_ddramc_register {
-	unsigned long mdr;
-	unsigned long cr;
-	unsigned long rtr;
-	unsigned long t0pr;
-	unsigned long t1pr;
-	unsigned long t2pr;
-	unsigned long lpr;
-	unsigned long lpddr2_lpr;
-	unsigned long tim_calr;
-	unsigned long cal_mr4r;
-};
-
-void at91_ddram_initialize(void __iomem *base_address,
-			   void __iomem *ram_address,
-			   const struct at91_ddramc_register *ddramc_config);
-
-void at91_lpddr2_sdram_initialize(void __iomem *base_address,
-				  void __iomem *ram_address,
-				  const struct at91_ddramc_register *ddramc_config);
-
-
-void at91_lpddr1_sdram_initialize(void __iomem *base_address,
-				  void __iomem *ram_address,
-				  const struct at91_ddramc_register *ddramc_config);
-
-void __noreturn sama5d2_barebox_entry(unsigned int r4, void *boarddata);
-void __noreturn sama5d3_barebox_entry(unsigned int r4, void *boarddata);
-
-#endif /* #ifndef __DDRAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h b/arch/arm/mach-at91/include/mach/debug_ll.h
deleted file mode 100644
index b3cbdbc26f..0000000000
--- a/arch/arm/mach-at91/include/mach/debug_ll.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2012
- * Jean-Christophe PLAGNIOL-VILLARD <planioj@jcrosoft.com>
- *
- * Under GPLv2
- */
-
-#ifndef __MACH_DEBUG_LL_H__
-#define __MACH_DEBUG_LL_H__
-
-#include <asm/io.h>
-#include <mach/gpio.h>
-#include <mach/hardware.h>
-#include <mach/at91_dbgu.h>
-
-#define ATMEL_US_CSR		0x0014
-#define ATMEL_US_THR		0x001c
-#define ATMEL_US_TXRDY		(1 << 1)
-#define ATMEL_US_TXEMPTY	(1 << 9)
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- *
- * This does not append a newline
- */
-static inline void at91_dbgu_putc(void __iomem *base, int c)
-{
-	while (!(readl(base + ATMEL_US_CSR) & ATMEL_US_TXRDY))
-		barrier();
-	writel(c, base + ATMEL_US_THR);
-
-	while (!(readl(base + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
-		barrier();
-}
-
-static inline void PUTC_LL(char c)
-{
-	at91_dbgu_putc(IOMEM(CONFIG_DEBUG_AT91_UART_BASE), c);
-}
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/early_udelay.h b/arch/arm/mach-at91/include/mach/early_udelay.h
deleted file mode 100644
index 1c1b0123fe..0000000000
--- a/arch/arm/mach-at91/include/mach/early_udelay.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __EARLY_UDELAY_H__
-#define __EARLY_UDELAY_H__
-
-#include <linux/compiler.h>
-
-/* requires PIT to be initialized, but not the clocksource framework */
-void early_udelay(unsigned int usec);
-void early_udelay_init(void __iomem *pmc_base,
-		       void __iomem *pit_base,
-		       unsigned int clock,
-		       unsigned int master_clock_rate,
-		       unsigned int flags);
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
deleted file mode 100644
index ddd6971e37..0000000000
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2 only
- */
-
-#ifndef __AT91_GPIO_H__
-#define __AT91_GPIO_H__
-
-#include <dt-bindings/gpio/gpio.h>
-#include <asm/io.h>
-#include <mach/at91_pio.h>
-
-#define MAX_NB_GPIO_PER_BANK	32
-
-enum at91_mux {
-	AT91_MUX_GPIO = 0,
-	AT91_MUX_PERIPH_A = 1,
-	AT91_MUX_PERIPH_B = 2,
-	AT91_MUX_PERIPH_C = 3,
-	AT91_MUX_PERIPH_D = 4,
-	AT91_MUX_PERIPH_E = 5,
-	AT91_MUX_PERIPH_F = 6,
-	AT91_MUX_PERIPH_G = 7,
-};
-
-static inline unsigned pin_to_bank(unsigned pin)
-{
-	return pin / MAX_NB_GPIO_PER_BANK;
-}
-
-static inline unsigned pin_to_bank_offset(unsigned pin)
-{
-	return pin % MAX_NB_GPIO_PER_BANK;
-}
-
-static inline unsigned pin_to_mask(unsigned pin)
-{
-	return 1 << pin_to_bank_offset(pin);
-}
-
-static inline void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
-{
-	writel(mask, pio + PIO_IDR);
-}
-
-static inline void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
-{
-	writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
-}
-
-static inline void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
-{
-	writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
-}
-
-static inline void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
-{
-	writel(mask, pio + PIO_ASR);
-}
-
-static inline void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
-{
-	writel(mask, pio + PIO_BSR);
-}
-
-static inline void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
-{
-	writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
-	writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2);
-}
-
-static inline void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
-{
-	writel(readl(pio + PIO_ABCDSR1) |  mask, pio + PIO_ABCDSR1);
-	writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2);
-}
-
-static inline void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
-{
-	writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
-	writel(readl(pio + PIO_ABCDSR2) |  mask, pio + PIO_ABCDSR2);
-}
-
-static inline void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
-{
-	writel(readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
-	writel(readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-}
-
-static inline void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
-{
-	writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
-}
-
-static inline void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
-{
-	if (is_on)
-		writel(mask, pio + PIO_IFSCDR);
-	at91_mux_set_deglitch(pio, mask, is_on);
-}
-
-static inline void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
-				bool is_on, u32 div)
-{
-	if (is_on) {
-		writel(mask, pio + PIO_IFSCER);
-		writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
-		writel(mask, pio + PIO_IFER);
-	} else {
-		writel(mask, pio + PIO_IFDR);
-	}
-}
-
-static inline void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
-{
-	writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
-}
-
-static inline void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
-{
-	writel(readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
-}
-
-static inline void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
-{
-	writel(mask, pio + PIO_PDR);
-}
-
-static inline void at91_mux_gpio_enable(void __iomem *pio, unsigned mask)
-{
-	writel(mask, pio + PIO_PER);
-}
-
-static inline void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input)
-{
-	writel(mask, pio + (input ? PIO_ODR : PIO_OER));
-}
-
-static inline void at91_mux_gpio_set(void __iomem *pio, unsigned mask,
-int value)
-{
-	writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
-}
-
-static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
-{
-	u32 pdsr;
-
-	pdsr = readl(pio + PIO_PDSR);
-	return (pdsr & mask) != 0;
-}
-
-static inline void at91_mux_pio3_pin(void __iomem *pio, unsigned mask,
-				     enum at91_mux mux, int gpio_state)
-{
-	at91_mux_disable_interrupt(pio, mask);
-
-	switch(mux) {
-	case AT91_MUX_GPIO:
-		at91_mux_gpio_enable(pio, mask);
-		break;
-	case AT91_MUX_PERIPH_A:
-		at91_mux_pio3_set_A_periph(pio, mask);
-		break;
-	case AT91_MUX_PERIPH_B:
-		at91_mux_pio3_set_B_periph(pio, mask);
-		break;
-	case AT91_MUX_PERIPH_C:
-		at91_mux_pio3_set_C_periph(pio, mask);
-		break;
-	case AT91_MUX_PERIPH_D:
-		at91_mux_pio3_set_D_periph(pio, mask);
-		break;
-	default:
-		/* ignore everything else */
-		break;
-	}
-	if (mux != AT91_MUX_GPIO)
-		at91_mux_gpio_disable(pio, mask);
-
-	at91_mux_set_pullup(pio, mask, gpio_state & GPIO_PULL_UP);
-	at91_mux_pio3_set_pulldown(pio, mask, gpio_state & GPIO_PULL_DOWN);
-}
-
-/* helpers for PIO4 pinctrl (>= sama5d2) */
-
-static inline void at91_mux_pio4_set_periph(void __iomem *pio, unsigned mask, u32 func)
-{
-	writel(mask, pio + PIO4_MSKR);
-	writel(func, pio + PIO4_CFGR);
-}
-
-static inline void at91_mux_pio4_set_A_periph(void __iomem *pio, unsigned mask)
-{
-	at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_A);
-}
-
-static inline void at91_mux_pio4_set_B_periph(void __iomem *pio, unsigned mask)
-{
-	at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_B);
-}
-
-static inline void at91_mux_pio4_set_C_periph(void __iomem *pio, unsigned mask)
-{
-	at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_C);
-}
-
-static inline void at91_mux_pio4_set_D_periph(void __iomem *pio, unsigned mask)
-{
-	at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_D);
-}
-
-static inline void at91_mux_pio4_set_E_periph(void __iomem *pio, unsigned mask)
-{
-	at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_E);
-}
-
-static inline void at91_mux_pio4_set_F_periph(void __iomem *pio, unsigned mask)
-{
-	at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_F);
-}
-
-static inline void at91_mux_pio4_set_G_periph(void __iomem *pio, unsigned mask)
-{
-	at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_G);
-}
-
-static inline void at91_mux_pio4_set_func(void __iomem *pio,
-					  unsigned pin_mask,
-					  unsigned cfgr_and_mask,
-					  unsigned cfgr_or_mask)
-{
-	u32 reg;
-	writel(pin_mask, pio + PIO4_MSKR);
-	reg = readl(pio + PIO4_CFGR);
-	reg &= cfgr_and_mask;
-	reg |= cfgr_or_mask;
-	writel(reg, pio + PIO4_CFGR);
-}
-
-static inline void at91_mux_pio4_set_bistate(void __iomem *pio,
-					     unsigned pin_mask,
-					     unsigned func_mask,
-					     bool is_on)
-{
-	at91_mux_pio4_set_func(pio, pin_mask, ~func_mask,
-			       is_on ? func_mask : 0);
-}
-
-static inline void at91_mux_pio4_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
-{
-	at91_mux_pio4_set_bistate(pio, mask, PIO4_IFEN_MASK, is_on);
-}
-
-static inline void at91_mux_pio4_set_debounce(void __iomem *pio, unsigned mask,
-					      bool is_on, u32 div)
-{
-	at91_mux_pio4_set_bistate(pio, mask, PIO4_IFEN_MASK, is_on);
-	at91_mux_pio4_set_bistate(pio, mask, PIO4_IFSCEN_MASK, is_on);
-}
-
-static inline void at91_mux_pio4_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
-{
-	at91_mux_pio4_set_bistate(pio, mask, PIO4_PDEN_MASK, is_on);
-}
-
-static inline void at91_mux_pio4_disable_schmitt_trig(void __iomem *pio, unsigned mask)
-{
-	at91_mux_pio4_set_bistate(pio, mask, PIO4_SCHMITT_MASK, false);
-}
-
-static inline void at91_mux_gpio4_enable(void __iomem *pio, unsigned mask)
-{
-	at91_mux_pio4_set_func(pio, mask, ~PIO4_CFGR_FUNC_MASK, AT91_MUX_GPIO);
-}
-
-static inline void at91_mux_gpio4_input(void __iomem *pio, unsigned mask, bool input)
-{
-	u32 cfgr;
-
-	writel(mask, pio + PIO4_MSKR);
-
-	cfgr = readl(pio + PIO4_CFGR);
-	if (input)
-		cfgr &= ~PIO4_DIR_MASK;
-	else
-		cfgr |= PIO4_DIR_MASK;
-	writel(cfgr, pio + PIO4_CFGR);
-}
-
-static inline void at91_mux_gpio4_set(void __iomem *pio, unsigned mask,
-				      int value)
-{
-	writel(mask, pio + (value ? PIO4_SODR : PIO4_CODR));
-}
-
-static inline int at91_mux_gpio4_get(void __iomem *pio, unsigned mask)
-{
-	u32 pdsr;
-
-	pdsr = readl(pio + PIO4_PDSR);
-	return (pdsr & mask) != 0;
-}
-
-#endif /* __AT91_GPIO_H__ */
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
deleted file mode 100644
index 0d08a99fe4..0000000000
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2003 SAN People */
-/* SPDX-FileCopyrightText: 2003 ATMEL */
-
-/* [origin: Linux kernel include/asm-arm/arch-at91/hardware.h] */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* DBGU base */
-/* rm9200, 9260/9g20, 9261/9g10, 9rl */
-#define AT91_BASE_DBGU0	0xfffff200
-/* 9263, 9g45 */
-#define AT91_BASE_DBGU1	0xffffee00
-/* sama5d4 */
-#define AT91_BASE_DBGU2	0xfc069000
-
-#include <mach/at91rm9200.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9n12.h>
-#include <mach/at91sam9x5.h>
-#include <mach/sama5d2.h>
-#include <mach/sama5d3.h>
-#include <mach/sama5d4.h>
-
-/* External Memory Map */
-#define AT91_CHIPSELECT_0	0x10000000
-#define AT91_CHIPSELECT_1	0x20000000
-#define AT91_CHIPSELECT_2	0x30000000
-#define AT91_CHIPSELECT_3	0x40000000
-#define AT91_CHIPSELECT_4	0x50000000
-#define AT91_CHIPSELECT_5	0x60000000
-#define AT91_CHIPSELECT_6	0x70000000
-#define AT91_CHIPSELECT_7	0x80000000
-
-#define SAMA5_CHIPSELECT_0	0x10000000
-#define SAMA5_DDRCS		0x20000000
-#define SAMA5_CHIPSELECT_1	0x40000000
-#define SAMA5_CHIPSELECT_2	0x50000000
-#define SAMA5_CHIPSELECT_3	0x60000000
-
-/* Clocks */
-#define AT91_SLOW_CLOCK		32768		/* slow clock */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/iomux.h b/arch/arm/mach-at91/include/mach/iomux.h
deleted file mode 100644
index bdd34bed94..0000000000
--- a/arch/arm/mach-at91/include/mach/iomux.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2005 HP Labs */
-
-/* [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] */
-
-#ifndef __ASM_ARCH_AT91_GPIO_H
-#define __ASM_ARCH_AT91_GPIO_H
-
-#include <io.h>
-#include <asm-generic/errno.h>
-#include <mach/at91_pio.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-
-#define	AT91_PIN_PA0	(0x00 + 0)
-#define	AT91_PIN_PA1	(0x00 + 1)
-#define	AT91_PIN_PA2	(0x00 + 2)
-#define	AT91_PIN_PA3	(0x00 + 3)
-#define	AT91_PIN_PA4	(0x00 + 4)
-#define	AT91_PIN_PA5	(0x00 + 5)
-#define	AT91_PIN_PA6	(0x00 + 6)
-#define	AT91_PIN_PA7	(0x00 + 7)
-#define	AT91_PIN_PA8	(0x00 + 8)
-#define	AT91_PIN_PA9	(0x00 + 9)
-#define	AT91_PIN_PA10	(0x00 + 10)
-#define	AT91_PIN_PA11	(0x00 + 11)
-#define	AT91_PIN_PA12	(0x00 + 12)
-#define	AT91_PIN_PA13	(0x00 + 13)
-#define	AT91_PIN_PA14	(0x00 + 14)
-#define	AT91_PIN_PA15	(0x00 + 15)
-#define	AT91_PIN_PA16	(0x00 + 16)
-#define	AT91_PIN_PA17	(0x00 + 17)
-#define	AT91_PIN_PA18	(0x00 + 18)
-#define	AT91_PIN_PA19	(0x00 + 19)
-#define	AT91_PIN_PA20	(0x00 + 20)
-#define	AT91_PIN_PA21	(0x00 + 21)
-#define	AT91_PIN_PA22	(0x00 + 22)
-#define	AT91_PIN_PA23	(0x00 + 23)
-#define	AT91_PIN_PA24	(0x00 + 24)
-#define	AT91_PIN_PA25	(0x00 + 25)
-#define	AT91_PIN_PA26	(0x00 + 26)
-#define	AT91_PIN_PA27	(0x00 + 27)
-#define	AT91_PIN_PA28	(0x00 + 28)
-#define	AT91_PIN_PA29	(0x00 + 29)
-#define	AT91_PIN_PA30	(0x00 + 30)
-#define	AT91_PIN_PA31	(0x00 + 31)
-
-#define	AT91_PIN_PB0	(0x20 + 0)
-#define	AT91_PIN_PB1	(0x20 + 1)
-#define	AT91_PIN_PB2	(0x20 + 2)
-#define	AT91_PIN_PB3	(0x20 + 3)
-#define	AT91_PIN_PB4	(0x20 + 4)
-#define	AT91_PIN_PB5	(0x20 + 5)
-#define	AT91_PIN_PB6	(0x20 + 6)
-#define	AT91_PIN_PB7	(0x20 + 7)
-#define	AT91_PIN_PB8	(0x20 + 8)
-#define	AT91_PIN_PB9	(0x20 + 9)
-#define	AT91_PIN_PB10	(0x20 + 10)
-#define	AT91_PIN_PB11	(0x20 + 11)
-#define	AT91_PIN_PB12	(0x20 + 12)
-#define	AT91_PIN_PB13	(0x20 + 13)
-#define	AT91_PIN_PB14	(0x20 + 14)
-#define	AT91_PIN_PB15	(0x20 + 15)
-#define	AT91_PIN_PB16	(0x20 + 16)
-#define	AT91_PIN_PB17	(0x20 + 17)
-#define	AT91_PIN_PB18	(0x20 + 18)
-#define	AT91_PIN_PB19	(0x20 + 19)
-#define	AT91_PIN_PB20	(0x20 + 20)
-#define	AT91_PIN_PB21	(0x20 + 21)
-#define	AT91_PIN_PB22	(0x20 + 22)
-#define	AT91_PIN_PB23	(0x20 + 23)
-#define	AT91_PIN_PB24	(0x20 + 24)
-#define	AT91_PIN_PB25	(0x20 + 25)
-#define	AT91_PIN_PB26	(0x20 + 26)
-#define	AT91_PIN_PB27	(0x20 + 27)
-#define	AT91_PIN_PB28	(0x20 + 28)
-#define	AT91_PIN_PB29	(0x20 + 29)
-#define	AT91_PIN_PB30	(0x20 + 30)
-#define	AT91_PIN_PB31	(0x20 + 31)
-
-#define	AT91_PIN_PC0	(0x40 + 0)
-#define	AT91_PIN_PC1	(0x40 + 1)
-#define	AT91_PIN_PC2	(0x40 + 2)
-#define	AT91_PIN_PC3	(0x40 + 3)
-#define	AT91_PIN_PC4	(0x40 + 4)
-#define	AT91_PIN_PC5	(0x40 + 5)
-#define	AT91_PIN_PC6	(0x40 + 6)
-#define	AT91_PIN_PC7	(0x40 + 7)
-#define	AT91_PIN_PC8	(0x40 + 8)
-#define	AT91_PIN_PC9	(0x40 + 9)
-#define	AT91_PIN_PC10	(0x40 + 10)
-#define	AT91_PIN_PC11	(0x40 + 11)
-#define	AT91_PIN_PC12	(0x40 + 12)
-#define	AT91_PIN_PC13	(0x40 + 13)
-#define	AT91_PIN_PC14	(0x40 + 14)
-#define	AT91_PIN_PC15	(0x40 + 15)
-#define	AT91_PIN_PC16	(0x40 + 16)
-#define	AT91_PIN_PC17	(0x40 + 17)
-#define	AT91_PIN_PC18	(0x40 + 18)
-#define	AT91_PIN_PC19	(0x40 + 19)
-#define	AT91_PIN_PC20	(0x40 + 20)
-#define	AT91_PIN_PC21	(0x40 + 21)
-#define	AT91_PIN_PC22	(0x40 + 22)
-#define	AT91_PIN_PC23	(0x40 + 23)
-#define	AT91_PIN_PC24	(0x40 + 24)
-#define	AT91_PIN_PC25	(0x40 + 25)
-#define	AT91_PIN_PC26	(0x40 + 26)
-#define	AT91_PIN_PC27	(0x40 + 27)
-#define	AT91_PIN_PC28	(0x40 + 28)
-#define	AT91_PIN_PC29	(0x40 + 29)
-#define	AT91_PIN_PC30	(0x40 + 30)
-#define	AT91_PIN_PC31	(0x40 + 31)
-
-#define	AT91_PIN_PD0	(0x60 + 0)
-#define	AT91_PIN_PD1	(0x60 + 1)
-#define	AT91_PIN_PD2	(0x60 + 2)
-#define	AT91_PIN_PD3	(0x60 + 3)
-#define	AT91_PIN_PD4	(0x60 + 4)
-#define	AT91_PIN_PD5	(0x60 + 5)
-#define	AT91_PIN_PD6	(0x60 + 6)
-#define	AT91_PIN_PD7	(0x60 + 7)
-#define	AT91_PIN_PD8	(0x60 + 8)
-#define	AT91_PIN_PD9	(0x60 + 9)
-#define	AT91_PIN_PD10	(0x60 + 10)
-#define	AT91_PIN_PD11	(0x60 + 11)
-#define	AT91_PIN_PD12	(0x60 + 12)
-#define	AT91_PIN_PD13	(0x60 + 13)
-#define	AT91_PIN_PD14	(0x60 + 14)
-#define	AT91_PIN_PD15	(0x60 + 15)
-#define	AT91_PIN_PD16	(0x60 + 16)
-#define	AT91_PIN_PD17	(0x60 + 17)
-#define	AT91_PIN_PD18	(0x60 + 18)
-#define	AT91_PIN_PD19	(0x60 + 19)
-#define	AT91_PIN_PD20	(0x60 + 20)
-#define	AT91_PIN_PD21	(0x60 + 21)
-#define	AT91_PIN_PD22	(0x60 + 22)
-#define	AT91_PIN_PD23	(0x60 + 23)
-#define	AT91_PIN_PD24	(0x60 + 24)
-#define	AT91_PIN_PD25	(0x60 + 25)
-#define	AT91_PIN_PD26	(0x60 + 26)
-#define	AT91_PIN_PD27	(0x60 + 27)
-#define	AT91_PIN_PD28	(0x60 + 28)
-#define	AT91_PIN_PD29	(0x60 + 29)
-#define	AT91_PIN_PD30	(0x60 + 30)
-#define	AT91_PIN_PD31	(0x60 + 31)
-
-#define	AT91_PIN_PE0	(0x80 + 0)
-#define	AT91_PIN_PE1	(0x80 + 1)
-#define	AT91_PIN_PE2	(0x80 + 2)
-#define	AT91_PIN_PE3	(0x80 + 3)
-#define	AT91_PIN_PE4	(0x80 + 4)
-#define	AT91_PIN_PE5	(0x80 + 5)
-#define	AT91_PIN_PE6	(0x80 + 6)
-#define	AT91_PIN_PE7	(0x80 + 7)
-#define	AT91_PIN_PE8	(0x80 + 8)
-#define	AT91_PIN_PE9	(0x80 + 9)
-#define	AT91_PIN_PE10	(0x80 + 10)
-#define	AT91_PIN_PE11	(0x80 + 11)
-#define	AT91_PIN_PE12	(0x80 + 12)
-#define	AT91_PIN_PE13	(0x80 + 13)
-#define	AT91_PIN_PE14	(0x80 + 14)
-#define	AT91_PIN_PE15	(0x80 + 15)
-#define	AT91_PIN_PE16	(0x80 + 16)
-#define	AT91_PIN_PE17	(0x80 + 17)
-#define	AT91_PIN_PE18	(0x80 + 18)
-#define	AT91_PIN_PE19	(0x80 + 19)
-#define	AT91_PIN_PE20	(0x80 + 20)
-#define	AT91_PIN_PE21	(0x80 + 21)
-#define	AT91_PIN_PE22	(0x80 + 22)
-#define	AT91_PIN_PE23	(0x80 + 23)
-#define	AT91_PIN_PE24	(0x80 + 24)
-#define	AT91_PIN_PE25	(0x80 + 25)
-#define	AT91_PIN_PE26	(0x80 + 26)
-#define	AT91_PIN_PE27	(0x80 + 27)
-#define	AT91_PIN_PE28	(0x80 + 28)
-#define	AT91_PIN_PE29	(0x80 + 29)
-#define	AT91_PIN_PE30	(0x80 + 30)
-#define	AT91_PIN_PE31	(0x80 + 31)
-
-/*
- * mux the pin
- */
-int at91_mux_pin(unsigned pin, enum at91_mux mux, int use_pullup);
-
-/*
- * mux the pin to the "GPIO" peripheral role.
- */
-static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
-{
-	return at91_mux_pin(pin, AT91_MUX_GPIO, use_pullup);
-}
-
-/*
- * mux the pin to the "A" internal peripheral role.
- */
-static inline int at91_set_A_periph(unsigned pin, int use_pullup)
-{
-	return at91_mux_pin(pin, AT91_MUX_PERIPH_A, use_pullup);
-}
-
-/*
- * mux the pin to the "B" internal peripheral role.
- */
-static inline int at91_set_B_periph(unsigned pin, int use_pullup)
-{
-	return at91_mux_pin(pin, AT91_MUX_PERIPH_B, use_pullup);
-}
-
-/*
- * mux the pin to the "C" internal peripheral role.
- */
-static inline int at91_set_C_periph(unsigned pin, int use_pullup)
-{
-	return at91_mux_pin(pin, AT91_MUX_PERIPH_C, use_pullup);
-}
-
-/*
- * mux the pin to the "C" internal peripheral role.
- */
-static inline int at91_set_D_periph(unsigned pin, int use_pullup)
-{
-	return at91_mux_pin(pin, AT91_MUX_PERIPH_D, use_pullup);
-}
-
-/*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
- * configure it for an input.
- */
-int at91_set_gpio_input(unsigned pin, int use_pullup);
-
-/*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
- * and configure it for an output.
- */
-int at91_set_gpio_output(unsigned pin, int value);
-
-/*
- * enable/disable the glitch filter; mostly used with IRQ handling.
- */
-int at91_set_deglitch(unsigned pin, int is_on);
-
-/*
- * enable/disable the multi-driver; This is only valid for output and
- * allows the output pin to run as an open collector output.
- */
-int at91_set_multi_drive(unsigned pin, int is_on);
-
-extern int at91_set_debounce(unsigned pin, int is_on, int div);
-extern int at91_set_pulldown(unsigned pin, int is_on);
-extern int at91_disable_schmitt_trig(unsigned pin);
-
-#endif /* __ASM_ARCH_AT91SAM9_GPIO_H */
diff --git a/arch/arm/mach-at91/include/mach/matrix.h b/arch/arm/mach-at91/include/mach/matrix.h
deleted file mode 100644
index 5dbfcfe414..0000000000
--- a/arch/arm/mach-at91/include/mach/matrix.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: BSD-1-Clause */
-/*
- * Copyright (c) 2013, Atmel Corporation
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- */
-#ifndef __MATRIX_H__
-#define __MATRIX_H__
-
-#include <linux/compiler.h>
-
-void at91_matrix_write_protect_enable(void __iomem *matrix_base);
-void at91_matrix_write_protect_disable(void __iomem *matrix_base);
-void at91_matrix_configure_slave_security(void __iomem *matrix_base,
-					  unsigned int slave,
-					  unsigned int srtop_setting,
-					  unsigned int srsplit_setting,
-					  unsigned int ssr_setting);
-
-#endif /* #ifndef __MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/sama5_bootsource.h b/arch/arm/mach-at91/include/mach/sama5_bootsource.h
deleted file mode 100644
index 931e1f29c8..0000000000
--- a/arch/arm/mach-at91/include/mach/sama5_bootsource.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef AT91_SAMA5_BOOTSOURCE_H_
-#define AT91_SAMA5_BOOTSOURCE_H_
-
-#include <errno.h>
-#include <bootsource.h>
-#include <linux/bitops.h>
-#include <linux/bitfield.h>
-#include <mach/hardware.h>
-
-/* Boot modes stored by BootROM in r4 */
-#define SAMA5_BOOTSOURCE_SPI	0
-#define SAMA5_BOOTSOURCE_MCI	1
-#define SAMA5_BOOTSOURCE_SMC	2
-#define SAMA5_BOOTSOURCE_TWI	3
-#define SAMA5_BOOTSOURCE_QSPI	4
-#define SAMA5_BOOTSOURCE_SAM_BA	7
-
-#define SAMA5_BOOTSOURCE		GENMASK(3, 0)
-#define SAMA5_BOOTSOURCE_INSTANCE	GENMASK(7, 4)
-
-static inline int sama5_bootsource(u32 reg)
-{
-	u32 dev = FIELD_GET(SAMA5_BOOTSOURCE, reg);
-
-	switch(dev) {
-	case SAMA5_BOOTSOURCE_MCI:
-		return BOOTSOURCE_MMC;
-	case SAMA5_BOOTSOURCE_SPI:
-		return BOOTSOURCE_SPI_NOR;
-	case SAMA5_BOOTSOURCE_QSPI:
-		return BOOTSOURCE_SPI;
-	case SAMA5_BOOTSOURCE_SMC:
-		return BOOTSOURCE_NAND;
-	case SAMA5_BOOTSOURCE_SAM_BA:
-		return BOOTSOURCE_SERIAL;
-	}
-	return BOOTSOURCE_UNKNOWN;
-}
-
-static inline int sama5_bootsource_instance(u32 reg)
-{
-	return FIELD_GET(SAMA5_BOOTSOURCE_INSTANCE, reg);
-}
-
-#define __sama5d2_stashed_bootrom_r4 \
-	(*(volatile u32 *)(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE - 0x4))
-
-#define __sama5d3_stashed_bootrom_r4 \
-	(*(volatile u32 *)(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 0x4))
-
-static inline void __noreturn sama5_boot_xload(void __noreturn (*bb)(void), u32 r4)
-{
-	asm volatile("mov r4, %0" : : "r"(r4) : );
-	asm volatile("bx  %0"     : : "r"(bb) : );
-	__builtin_unreachable();
-}
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h b/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h
deleted file mode 100644
index 6a75ac71fc..0000000000
--- a/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: BSD-1-Clause
- *
- * Copyright (C) 2014, Atmel Corporation
- *
- * SAMA5D27 System-in-Package DDRAMC configuration
- */
-
-#include <mach/at91_ddrsdrc.h>
-#include <mach/ddramc.h>
-#include <mach/sama5d2_ll.h>
-
-static inline void sama5d2_d1g_ddrconf(void) /* DDR2 1Gbit SDRAM */
-{
-	const struct at91_ddramc_register conf = {
-		.mdr = AT91_DDRC2_DBW_16_BITS | AT91_DDRC2_MD_DDR2_SDRAM,
-
-		.cr = AT91_DDRC2_NC_DDR10_SDR9 | AT91_DDRC2_NR_13 |
-			AT91_DDRC2_CAS_3 | AT91_DDRC2_DISABLE_RESET_DLL |
-			AT91_DDRC2_WEAK_STRENGTH_RZQ7 | AT91_DDRC2_ENABLE_DLL |
-			AT91_DDRC2_NB_BANKS_8 | AT91_DDRC2_NDQS_ENABLED |
-			AT91_DDRC2_DECOD_INTERLEAVED | AT91_DDRC2_UNAL_SUPPORTED,
-
-		.rtr = 0x511,
-
-		.t0pr = AT91_DDRC2_TRAS_(7) | AT91_DDRC2_TRCD_(3) |
-			AT91_DDRC2_TWR_(3) | AT91_DDRC2_TRC_(9) |
-			AT91_DDRC2_TRP_(3) | AT91_DDRC2_TRRD_(2) |
-			AT91_DDRC2_TWTR_(2) | AT91_DDRC2_TMRD_(2),
-
-		.t1pr = AT91_DDRC2_TRFC_(22) | AT91_DDRC2_TXSNR_(23) |
-			AT91_DDRC2_TXSRD_(200) | AT91_DDRC2_TXP_(2),
-
-		.t2pr = AT91_DDRC2_TXARD_(2) | AT91_DDRC2_TXARDS_(8) |
-			AT91_DDRC2_TRPA_(4) | AT91_DDRC2_TRTP_(2) |
-			AT91_DDRC2_TFAW_(8),
-	};
-
-	sama5d2_ddr2_init(&conf);
-}
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
deleted file mode 100644
index 90b566ffc4..0000000000
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ /dev/null
@@ -1,320 +0,0 @@
-// SPDX-License-Identifier: BSD-1-Clause
-/*
- * Chip-specific header file for the SAMA5D2 family
- *
- * Copyright (c) 2015, Atmel Corporation
- * Copyright (c) 2019 Ahmad Fatoum, Pengutronix
- *
- * Common definitions.
- * Based on SAMA5D2 datasheet:
- * http://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-Sheet-DS60001476C.pdf
- *
- */
-
-#ifndef SAMA5D2_H
-#define SAMA5D2_H
-
-#include <asm/io.h>
-#include <linux/sizes.h>
-#include <linux/bitops.h>
-#include <linux/bitfield.h>
-
-/*
- * Peripheral identifiers/interrupts. (Table 18-9)
- */
-#define	SAMA5D2_ID_FIQ		0	/* FIQ Interrupt ID */
-/* 1 */
-#define	SAMA5D2_ID_ARM		2	/* Performance Monitor Unit */
-#define	SAMA5D2_ID_PIT		3	/* Periodic Interval Timer Interrupt */
-#define	SAMA5D2_ID_WDT		4	/* Watchdog Timer Interrupt */
-#define	SAMA5D2_ID_GMAC		5	/* Ethernet MAC */
-#define	SAMA5D2_ID_XDMAC0	6	/* DMA Controller 0 */
-#define	SAMA5D2_ID_XDMAC1	7	/* DMA Controller 1 */
-#define	SAMA5D2_ID_ICM		8	/* Integrity Check Monitor */
-#define	SAMA5D2_ID_AES		9	/* Advanced Encryption Standard */
-#define	SAMA5D2_ID_AESB		10	/* AES bridge */
-#define	SAMA5D2_ID_TDES		11	/* Triple Data Encryption Standard */
-#define	SAMA5D2_ID_SHA		12	/* SHA Signature */
-#define	SAMA5D2_ID_MPDDRC	13	/* MPDDR Controller */
-#define	SAMA5D2_ID_MATRIX1	14	/* H32MX, 32-bit AHB Matrix */
-#define	SAMA5D2_ID_MATRIX0	15	/* H64MX, 64-bit AHB Matrix */
-#define	SAMA5D2_ID_SECUMOD	16	/* Secure Module */
-#define	SAMA5D2_ID_HSMC		17	/* Multi-bit ECC interrupt */
-#define	SAMA5D2_ID_PIOA		18	/* Parallel I/O Controller A */
-#define	SAMA5D2_ID_FLEXCOM0	19	/* FLEXCOM0 */
-#define	SAMA5D2_ID_FLEXCOM1	20	/* FLEXCOM1 */
-#define	SAMA5D2_ID_FLEXCOM2	21	/* FLEXCOM2 */
-#define	SAMA5D2_ID_FLEXCOM3	22	/* FLEXCOM3 */
-#define	SAMA5D2_ID_FLEXCOM4	23	/* FLEXCOM4 */
-#define	SAMA5D2_ID_UART0	24	/* UART0 */
-#define	SAMA5D2_ID_UART1	25	/* UART1 */
-#define	SAMA5D2_ID_UART2	26	/* UART2 */
-#define	SAMA5D2_ID_UART3	27	/* UART3 */
-#define	SAMA5D2_ID_UART4	28	/* UART4 */
-#define	SAMA5D2_ID_TWI0		29	/* Two-wire Interface 0 */
-#define	SAMA5D2_ID_TWI1		30	/* Two-wire Interface 1 */
-#define	SAMA5D2_ID_SDMMC0	31	/* Secure Data Memory Card Controller 0 */
-#define	SAMA5D2_ID_SDMMC1	32	/* Secure Data Memory Card Controller 1 */
-#define	SAMA5D2_ID_SPI0		33	/* Serial Peripheral Interface 0 */
-#define	SAMA5D2_ID_SPI1		34	/* Serial Peripheral Interface 1 */
-#define	SAMA5D2_ID_TC0		35	/* Timer Counter 0 (ch.0,1,2) */
-#define	SAMA5D2_ID_TC1		36	/* Timer Counter 1 (ch.3,4,5) */
-/* 37 */
-#define	SAMA5D2_ID_PWM		38	/* Pulse Width Modulation Controller0 (ch. 0,1,2,3) */
-/* 39 */
-#define	SAMA5D2_ID_ADC		40	/* Touch Screen ADC Controller */
-#define	SAMA5D2_ID_UHPHS	41	/* USB Host High Speed */
-#define	SAMA5D2_ID_UDPHS	42	/* USB Device High Speed */
-#define	SAMA5D2_ID_SSC0		43	/* Serial Synchronous Controller 0 */
-#define	SAMA5D2_ID_SSC1		44	/* Serial Synchronous Controller 1 */
-#define	SAMA5D2_ID_LCDC		45	/* LCD Controller */
-#define	SAMA5D2_ID_ISI		46	/* Image Sensor Interface */
-#define	SAMA5D2_ID_TRNG		47	/* True Random Number Generator */
-#define	SAMA5D2_ID_PDMIC	48	/* Pulse Density Modulation Interface Controller */
-#define	SAMA5D2_ID_IRQ		49	/* IRQ Interrupt ID */
-#define	SAMA5D2_ID_SFC		50	/* Fuse Controller */
-#define	SAMA5D2_ID_SECURAM	51	/* Secure RAM */
-#define	SAMA5D2_ID_QSPI0	52	/* QSPI0 */
-#define	SAMA5D2_ID_QSPI1	53	/* QSPI1 */
-#define	SAMA5D2_ID_I2SC0	54	/* Inter-IC Sound Controller 0 */
-#define	SAMA5D2_ID_I2SC1	55	/* Inter-IC Sound Controller 1 */
-#define	SAMA5D2_ID_CAN0_INT0	56	/* MCAN 0 Interrupt0 */
-#define	SAMA5D2_ID_CAN1_INT0	57	/* MCAN 1 Interrupt0 */
-#define	SAMA5D2_ID_PTC		58	/* Peripheral Touch Controller */
-#define	SAMA5D2_ID_CLASSD	59	/* Audio Class D Amplifier */
-#define	SAMA5D2_ID_SFR		60	/* Special Function Register */
-#define	SAMA5D2_ID_SAIC		61	/* Secured Advanced Interrupt Controller */
-#define	SAMA5D2_ID_AIC		62	/* Advanced Interrupt Controller */
-#define	SAMA5D2_ID_L2CC		63	/* L2 Cache Controller */
-#define	SAMA5D2_ID_CAN0_INT1	64	/* MCAN 0 Interrupt1 */
-#define	SAMA5D2_ID_CAN1_INT1	65	/* MCAN 1 Interrupt1 */
-#define	SAMA5D2_ID_GMAC_Q1	66	/* GMAC Queue 1 Interrupt */
-#define	SAMA5D2_ID_GMAC_Q2	67	/* GMAC Queue 2 Interrupt */
-#define	SAMA5D2_ID_PIOB		68	/* Parallel I/O Controller B */
-#define	SAMA5D2_ID_PIOC		69	/* Parallel I/O Controller C */
-#define	SAMA5D2_ID_PIOD		70	/* Parallel I/O Controller D */
-#define	SAMA5D2_ID_SDMMC0_TIMER	71	/* Secure Data Memory Card Controller 0 */
-#define	SAMA5D2_ID_SDMMC1_TIMER	72	/* Secure Data Memory Card Controller 1 */
-/* 73 */
-#define	SAMA5D2_ID_SYS		74	/* System Controller Interrupt */
-#define	SAMA5D2_ID_ACC		75	/* Analog Comparator */
-#define	SAMA5D2_ID_RXLP		76	/* UART Low-Power */
-#define	SAMA5D2_ID_SFRBU	77	/* Special Function Register BackUp */
-#define	SAMA5D2_ID_CHIPID	78	/* Chip ID */
-
-/*
- * User Peripheral physical base addresses.
- */
-
-#define	SAMA5D2_BASE_LCDC	IOMEM(0xf0000000)
-#define	SAMA5D2_BASE_XDMAC1	IOMEM(0xf0004000)
-#define	SAMA5D2_BASE_HXISI	IOMEM(0xf0008000)
-#define	SAMA5D2_BASE_MPDDRC	IOMEM(0xf000c000)
-#define	SAMA5D2_BASE_XDMAC0	IOMEM(0xf0010000)
-#define	SAMA5D2_BASE_PMC	IOMEM(0xf0014000)
-#define	SAMA5D2_BASE_MATRIX64	IOMEM(0xf0018000)	/* MATRIX0 */
-#define	SAMA5D2_BASE_AESB	IOMEM(0xf001c000)
-#define	SAMA5D2_BASE_QSPI0	IOMEM(0xf0020000)
-#define	SAMA5D2_BASE_QSPI1	IOMEM(0xf0024000)
-#define	SAMA5D2_BASE_SHA	IOMEM(0xf0028000)
-#define	SAMA5D2_BASE_AES	IOMEM(0xf002c000)
-
-#define	SAMA5D2_BASE_SPI0	IOMEM(0xf8000000)
-#define	SAMA5D2_BASE_SSC0	IOMEM(0xf8004000)
-#define	SAMA5D2_BASE_GMAC	IOMEM(0xf8008000)
-#define	SAMA5D2_BASE_TC0	IOMEM(0xf800c000)
-#define	SAMA5D2_BASE_TC1	IOMEM(0xf8010000)
-#define	SAMA5D2_BASE_HSMC	IOMEM(0xf8014000)
-#define	SAMA5D2_BASE_PDMIC	IOMEM(0xf8018000)
-#define	SAMA5D2_BASE_UART0	IOMEM(0xf801c000)
-#define	SAMA5D2_BASE_UART1	IOMEM(0xf8020000)
-#define	SAMA5D2_BASE_UART2	IOMEM(0xf8024000)
-#define	SAMA5D2_BASE_TWI0	IOMEM(0xf8028000)
-#define	SAMA5D2_BASE_PWMC	IOMEM(0xf802c000)
-#define	SAMA5D2_BASE_SFR	IOMEM(0xf8030000)
-#define	SAMA5D2_BASE_FLEXCOM0	IOMEM(0xf8034000)
-#define	SAMA5D2_BASE_FLEXCOM1	IOMEM(0xf8038000)
-#define	SAMA5D2_BASE_SAIC	IOMEM(0xf803c000)
-#define	SAMA5D2_BASE_ICM	IOMEM(0xf8040000)
-#define	SAMA5D2_BASE_SECURAM	IOMEM(0xf8044000)
-#define	SAMA5D2_BASE_SYSC	IOMEM(0xf8048000)
-#define	SAMA5D2_BASE_ACC	IOMEM(0xf804a000)
-#define	SAMA5D2_BASE_SFC	IOMEM(0xf804c000)
-#define	SAMA5D2_BASE_I2SC0	IOMEM(0xf8050000)
-#define	SAMA5D2_BASE_CAN0	IOMEM(0xf8054000)
-
-#define	SAMA5D2_BASE_SPI1	IOMEM(0xfc000000)
-#define	SAMA5D2_BASE_SSC1	IOMEM(0xfc004000)
-#define	SAMA5D2_BASE_UART3	IOMEM(0xfc008000)
-#define	SAMA5D2_BASE_UART4	IOMEM(0xfc00c000)
-#define	SAMA5D2_BASE_FLEXCOM2	IOMEM(0xfc010000)
-#define	SAMA5D2_BASE_FLEXCOM3	IOMEM(0xfc014000)
-#define	SAMA5D2_BASE_FLEXCOM4	IOMEM(0xfc018000)
-#define	SAMA5D2_BASE_TRNG	IOMEM(0xfc01c000)
-#define	SAMA5D2_BASE_AIC	IOMEM(0xfc020000)
-#define	SAMA5D2_BASE_TWI1	IOMEM(0xfc028000)
-#define	SAMA5D2_BASE_UDPHS	IOMEM(0xfc02c000)
-#define	SAMA5D2_BASE_ADC	IOMEM(0xfc030000)
-
-#define	SAMA5D2_BASE_PIOA	IOMEM(0xfc038000)
-#define	SAMA5D2_BASE_MATRIX32	IOMEM(0xfc03c000)	/* MATRIX1 */
-#define	SAMA5D2_BASE_SECUMOD	IOMEM(0xfc040000)
-#define	SAMA5D2_BASE_TDES	IOMEM(0xfc044000)
-#define	SAMA5D2_BASE_CLASSD	IOMEM(0xfc048000)
-#define	SAMA5D2_BASE_I2SC1	IOMEM(0xfc04c000)
-#define	SAMA5D2_BASE_CAN1	IOMEM(0xfc050000)
-#define	SAMA5D2_BASE_SFRBU	IOMEM(0xfc05c000)
-#define	SAMA5D2_BASE_CHIPID	IOMEM(0xfc069000)
-
-/*
- * Address Memory Space
- */
-#define	SAMA5D2_BASE_INTERNAL_MEM	IOMEM(0x00000000)
-#define	SAMA5D2_BASE_CS0		IOMEM(0x10000000)
-#define	SAMA5D2_BASE_DDRCS		IOMEM(0x20000000)
-#define	SAMA5D2_BASE_DDRCS_AES		IOMEM(0x40000000)
-#define	SAMA5D2_BASE_CS1		IOMEM(0x60000000)
-#define	SAMA5D2_BASE_CS2		IOMEM(0x70000000)
-#define	SAMA5D2_BASE_CS3		IOMEM(0x80000000)
-#define	SAMA5D2_BASE_QSPI0_AES_MEM	IOMEM(0x90000000)
-#define	SAMA5D2_BASE_QSPI1_AES_MEM	IOMEM(0x98000000)
-#define	SAMA5D2_BASE_SDHC0		IOMEM(0xa0000000)
-#define	SAMA5D2_BASE_SDHC1		IOMEM(0xb0000000)
-#define	SAMA5D2_BASE_NFC_CMD_REG	IOMEM(0xc0000000)
-#define	SAMA5D2_BASE_QSPI0_MEM		IOMEM(0xd0000000)
-#define	SAMA5D2_BASE_QSPI1_MEM		IOMEM(0xd8000000)
-#define	SAMA5D2_BASE_PERIPH		IOMEM(0xf0000000)
-
-/*
- * Internal Memories
- */
-#define	SAMA5D2_BASE_ROM		IOMEM(0x00000000)	/* ROM */
-#define	SAMA5D2_BASE_ECC_ROM		IOMEM(0x00060000)	/* ECC ROM */
-#define	SAMA5D2_BASE_NFC_SRAM		0x00100000		/* NFC SRAM */
-#define	SAMA5D2_BASE_SRAM0		0x00200000		/* SRAM0 */
-#define	SAMA5D2_BASE_SRAM1		0x00220000		/* SRAM1 */
-#define	SAMA5D2_BASE_UDPHS_SRAM		0x00300000		/* UDPHS RAM */
-#define	SAMA5D2_BASE_UHP_OHCI		IOMEM(0x00400000)	/* UHP OHCI */
-#define	SAMA5D2_BASE_UHP_EHCI		IOMEM(0x00500000)	/* UHP EHCI */
-#define	SAMA5D2_BASE_AXI_MATRIX		IOMEM(0x00600000)	/* AXI Maxtrix */
-#define	SAMA5D2_BASE_DAP		IOMEM(0x00700000)	/* DAP */
-#define	SAMA5D2_BASE_PTC		IOMEM(0x00800000)	/* PTC */
-#define	SAMA5D2_BASE_L2CC		IOMEM(0x00A00000)	/* L2CC */
-
-/*
- * Other misc defines
- */
-#define	SAMA5D2_BASE_PMECC	(SAMA5D2_BASE_HSMC + 0x70)
-#define	SAMA5D2_BASE_PMERRLOC	(SAMA5D2_BASE_HSMC + 0x500)
-
-#define	SAMA5D2_PMECC		(SAMA5D2_BASE_PMECC - SAMA5D2_BASE_SYS)
-#define	SAMA5D2_PMERRLOC	(SAMA5D2_BASE_PMERRLOC - SAMA5D2_BASE_SYS)
-
-#define	SAMA5D2_BASE_PIOB	(SAMA5D2_BASE_PIOA + 0x40)
-#define	SAMA5D2_BASE_PIOC	(SAMA5D2_BASE_PIOB + 0x40)
-#define	SAMA5D2_BASE_PIOD	(SAMA5D2_BASE_PIOC + 0x40)
-
-/* SYSC spawns */
-#define	SAMA5D2_BASE_RSTC	SAMA5D2_BASE_SYSC
-#define	SAMA5D2_BASE_SHDC	(SAMA5D2_BASE_SYSC + 0x10)
-#define	SAMA5D2_BASE_PITC	(SAMA5D2_BASE_SYSC + 0x30)
-#define	SAMA5D2_BASE_WDT	(SAMA5D2_BASE_SYSC + 0x40)
-#define	SAMA5D2_BASE_SCKCR	(SAMA5D2_BASE_SYSC + 0x50)
-#define	SAMA5D2_BASE_RTCC	(SAMA5D2_BASE_SYSC + 0xb0)
-
-#define SAMA5D2_BASE_SMC	(SAMA5D2_BASE_HSMC + 0x700)
-
-#define	SAMA5D2_NUM_PIO		4
-#define	SAMA5D2_NUM_TWI		2
-
-/* AICREDIR Unlock Key */
-#define	SAMA5D2_AICREDIR_KEY		0xB6D81C4D
-
-/*
- * Matrix Slaves ID
- */
-/* MATRIX0(H64MX) Matrix Slaves */
-/* Bridge from H64MX to AXIMX (Internal ROM, Cryto Library, PKCC RAM) */
-#define	SAMA5D2_H64MX_SLAVE_BRIDGE_TO_AXIMX	0
-#define	SAMA5D2_H64MX_SLAVE_PERI_BRIDGE		1	/* H64MX Peripheral Bridge */
-#define	SAMA5D2_H64MX_SLAVE_DDR2_PORT_0		2	/* DDR2 Port0-AESOTF */
-#define	SAMA5D2_H64MX_SLAVE_DDR2_PORT_1		3	/* DDR2 Port1 */
-#define	SAMA5D2_H64MX_SLAVE_DDR2_PORT_2		4	/* DDR2 Port2 */
-#define	SAMA5D2_H64MX_SLAVE_DDR2_PORT_3		5	/* DDR2 Port3 */
-#define	SAMA5D2_H64MX_SLAVE_DDR2_PORT_4		6	/* DDR2 Port4 */
-#define	SAMA5D2_H64MX_SLAVE_DDR2_PORT_5		7	/* DDR2 Port5 */
-#define	SAMA5D2_H64MX_SLAVE_DDR2_PORT_6		8	/* DDR2 Port6 */
-#define	SAMA5D2_H64MX_SLAVE_DDR2_PORT_7		9	/* DDR2 Port7 */
-#define	SAMA5D2_H64MX_SLAVE_INTERNAL_SRAM	10	/* Internal SRAM 128K */
-#define	SAMA5D2_H64MX_SLAVE_CACHE_L2		11	/* Internal SRAM 128K (Cache L2) */
-#define	SAMA5D2_H64MX_SLAVE_QSPI0		12	/* QSPI0 */
-#define	SAMA5D2_H64MX_SLAVE_QSPI1		13	/* QSPI1 */
-#define	SAMA5D2_H64MX_SLAVE_AESB		14	/* AESB */
-
-/* MATRIX1(H32MX) Matrix Slaves */
-#define	SAMA5D2_H32MX_BRIDGE_TO_H64MX		0	/* Bridge from H32MX to H64MX */
-#define	SAMA5D2_H32MX_PERI_BRIDGE_0		1	/* H32MX Peripheral Bridge 0 */
-#define	SAMA5D2_H32MX_PERI_BRIDGE_1		2	/* H32MX Peripheral Bridge 1 */
-#define	SAMA5D2_H32MX_EXTERNAL_EBI		3	/* External Bus Interface */
-#define	SAMA5D2_H32MX_NFC_CMD_REG		3	/* NFC command Register */
-#define	SAMA5D2_H32MX_NFC_SRAM			4	/* NFC SRAM */
-#define	SAMA5D2_H32MX_USB			5
-
-#define	SAMA5D2_SRAM_BASE			SAMA5D2_BASE_SRAM0
-#define	SAMA5D2_SRAM_SIZE			(128 * SZ_1K)
-
-static inline void __iomem *sama5d2_pio_map_bank(int bank, unsigned *id)
-{
-	switch(bank + 'A') {
-	case 'A':
-		*id = SAMA5D2_ID_PIOA;
-		return SAMA5D2_BASE_PIOA;
-	case 'B':
-		*id = SAMA5D2_ID_PIOB;
-		return SAMA5D2_BASE_PIOB;
-	case 'C':
-		*id = SAMA5D2_ID_PIOC;
-		return SAMA5D2_BASE_PIOC;
-	case 'D':
-		*id = SAMA5D2_ID_PIOD;
-		return SAMA5D2_BASE_PIOD;
-	}
-
-	return NULL;
-}
-
-#define SAMA5D2_BUREG_INDEX	GENMASK(1, 0)
-#define SAMA5D2_BUREG_VALID	BIT(2)
-
-#define SAMA5D2_SFC_DR(x)	(SAMA5D2_BASE_SFC + 0x20 + 4 * (x))
-
-#define SAMA5D2_BOOTCFG_QSPI_0		GENMASK(1, 0)
-#define SAMA5D2_BOOTCFG_QSPI_1		GENMASK(3, 2)
-#define SAMA5D2_BOOTCFG_SPI_0		GENMASK(5, 4)
-#define SAMA5D2_BOOTCFG_SPI_1		GENMASK(7, 6)
-#define SAMA5D2_BOOTCFG_NFC		GENMASK(9, 8)
-#define SAMA5D2_BOOTCFG_SDMMC_0		BIT(10)
-#define SAMA5D2_BOOTCFG_SDMMC_1		BIT(11)
-#define SAMA5D2_BOOTCFG_UART		GENMASK(15, 12)
-#define SAMA5D2_BOOTCFG_JTAG		GENMASK(17, 16)
-#define SAMA5D2_BOOTCFG_EXT_MEM_BOOT_EN	BIT(18)
-#define SAMA5D2_BOOTCFG_QSPI_XIP	BIT(21)
-#define SAMA5D2_DISABLE_BSC_CR		BIT(22)
-#define SAMA5D2_DISABLE_MONITOR		BIT(24)
-#define SAMA5D2_SECURE_MODE		BIT(29)
-
-static inline u32 sama5d2_bootcfg(void)
-{
-	u32 __iomem *bureg = SAMA5D2_BASE_SECURAM + 0x1400;
-	u32 bsc_cr = readl(SAMA5D2_BASE_SYSC + 0x54);
-	u32 __iomem *bootcfg;
-
-	if (bsc_cr & SAMA5D2_BUREG_VALID)
-		bootcfg = &bureg[FIELD_GET(SAMA5D2_BUREG_INDEX, bsc_cr)];
-	else
-		bootcfg = SAMA5D2_SFC_DR(512 / 32);
-
-	return readl(bootcfg);
-}
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d2_ll.h b/arch/arm/mach-at91/include/mach/sama5d2_ll.h
deleted file mode 100644
index 244b1a7065..0000000000
--- a/arch/arm/mach-at91/include/mach/sama5d2_ll.h
+++ /dev/null
@@ -1,139 +0,0 @@
-#ifndef __MACH_SAMA5D2_LL__
-#define __MACH_SAMA5D2_LL__
-
-#include <mach/sama5d2.h>
-#include <mach/at91_pmc_ll.h>
-#include <mach/iomux.h>
-#include <mach/debug_ll.h>
-#include <mach/early_udelay.h>
-#include <mach/ddramc.h>
-
-#include <common.h>
-
-void sama5d2_lowlevel_init(void);
-
-static inline void sama5d2_pmc_enable_periph_clock(int clk)
-{
-	at91_pmc_sam9x5_enable_periph_clock(SAMA5D2_BASE_PMC, clk);
-}
-
-/* requires relocation */
-static inline void sama5d2_udelay_init(unsigned int msc)
-{
-	early_udelay_init(SAMA5D2_BASE_PMC, SAMA5D2_BASE_PITC,
-			  SAMA5D2_ID_PIT, msc, AT91_PMC_LL_SAMA5D2);
-}
-
-
-void sama5d2_ddr2_init(const struct at91_ddramc_register *ddramc_reg_config);
-
-static inline int sama5d2_pmc_enable_generic_clock(unsigned int periph_id,
-						   unsigned int clk_source,
-						   unsigned int div)
-{
-	return at91_pmc_enable_generic_clock(SAMA5D2_BASE_PMC,
-					     SAMA5D2_BASE_SFR,
-					     periph_id, clk_source, div,
-					     AT91_PMC_LL_SAMA5D2);
-}
-
-static inline int sama5d2_dbgu_setup_ll(unsigned dbgu_id,
-					unsigned pin, unsigned periph,
-					unsigned mck)
-{
-	unsigned mask, bank, pio_id;
-	void __iomem *dbgu_base, *pio_base;
-
-	mask = pin_to_mask(pin);
-	bank = pin_to_bank(pin);
-
-	switch (dbgu_id) {
-	case SAMA5D2_ID_UART0:
-		dbgu_base = SAMA5D2_BASE_UART0;
-		break;
-	case SAMA5D2_ID_UART1:
-		dbgu_base = SAMA5D2_BASE_UART1;
-		break;
-	case SAMA5D2_ID_UART2:
-		dbgu_base = SAMA5D2_BASE_UART2;
-		break;
-	case SAMA5D2_ID_UART3:
-		dbgu_base = SAMA5D2_BASE_UART3;
-		break;
-	case SAMA5D2_ID_UART4:
-		dbgu_base = SAMA5D2_BASE_UART4;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	pio_base = sama5d2_pio_map_bank(bank, &pio_id);
-	if (!pio_base)
-		return -EINVAL;
-
-	sama5d2_pmc_enable_periph_clock(pio_id);
-
-	at91_mux_pio4_set_periph(pio_base, mask, periph);
-
-	sama5d2_pmc_enable_periph_clock(dbgu_id);
-
-	at91_dbgu_setup_ll(dbgu_base, mck / 2, CONFIG_BAUDRATE);
-
-	return 0;
-}
-
-struct sama5d2_uart_pinmux {
-	void __iomem *base;
-	u8 id, dtxd, periph;
-};
-
-#define SAMA5D2_UART(idx, pio, periph) (struct sama5d2_uart_pinmux) {  \
-	SAMA5D2_BASE_UART##idx, SAMA5D2_ID_UART##idx, \
-	AT91_PIN_##pio, AT91_MUX_PERIPH_##periph }
-
-static inline void __iomem *sama5d2_resetup_uart_console(unsigned mck)
-{
-	struct sama5d2_uart_pinmux pinmux;
-
-	/* Table 48-2 I/O Lines and 16.4.4 Boot Configuration Word */
-
-	switch (FIELD_GET(SAMA5D2_BOOTCFG_UART, sama5d2_bootcfg())) {
-	case 0: /* UART_1_IOSET_1 */
-		pinmux = SAMA5D2_UART(1, PD3,  A);
-		break;
-	case 1: /* UART_0_IOSET_1 */
-		pinmux = SAMA5D2_UART(0, PB27, C);
-		break;
-	case 2: /* UART_1_IOSET_2 */
-		pinmux = SAMA5D2_UART(1, PC8,  E);
-		break;
-	case 3: /* UART_2_IOSET_1 */
-		pinmux = SAMA5D2_UART(2, PD5,  B);
-		break;
-	case 4: /* UART_2_IOSET_2 */
-		pinmux = SAMA5D2_UART(2, PD24, A);
-		break;
-	case 5: /* UART_2_IOSET_3 */
-		pinmux = SAMA5D2_UART(2, PD20, C);
-		break;
-	case 6: /* UART_3_IOSET_1 */
-		pinmux = SAMA5D2_UART(3, PC13, D);
-		break;
-	case 7: /* UART_3_IOSET_2 */
-		pinmux = SAMA5D2_UART(3, PD0,  C);
-		break;
-	case 8: /* UART_3_IOSET_3 */
-		pinmux = SAMA5D2_UART(3, PB12, C);
-		break;
-	case 9: /* UART_4_IOSET_1 */
-		pinmux = SAMA5D2_UART(4, PB4,  A);
-		break;
-	default:
-		return NULL;
-	}
-
-	sama5d2_dbgu_setup_ll(pinmux.id, pinmux.dtxd, pinmux.periph, mck);
-	return pinmux.base;
-}
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h b/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h
deleted file mode 100644
index 6f829282c6..0000000000
--- a/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: BSD-1-Clause
- *
- * Copyright (C) 2014, Atmel Corporation
- *
- * SAMA5D27 System-in-Package DDRAMC configuration
- */
-
-#include <mach/at91_ddrsdrc.h>
-#include <mach/ddramc.h>
-#include <mach/sama5d3_ll.h>
-
-static inline void sama5d3_xplained_ddrconf(void)
-{
-	const struct at91_ddramc_register conf = {
-		.mdr = AT91_DDRC2_DBW_32_BITS | AT91_DDRC2_MD_DDR2_SDRAM,
-
-		.cr = AT91_DDRC2_NC_DDR10_SDR9
-			| AT91_DDRC2_NR_13
-			| AT91_DDRC2_CAS_3
-			| AT91_DDRC2_DISABLE_RESET_DLL
-			| AT91_DDRC2_ENABLE_DLL
-			| AT91_DDRC2_ENRDM_ENABLE
-			| AT91_DDRC2_NB_BANKS_8
-			| AT91_DDRC2_NDQS_DISABLED
-			| AT91_DDRC2_DECOD_INTERLEAVED
-			| AT91_DDRC2_UNAL_SUPPORTED,
-
-		/*
-		 * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
-		 * With a 133 MHz frequency, the refresh timer count register must to be
-		 * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
-		 * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
-		 */
-		.rtr = 0x40F,     /* Refresh timer: 7.812us */
-
-		/* One clock cycle @ 133 MHz = 7.5 ns */
-		.t0pr = AT91_DDRC2_TRAS_(6)	/* 6 * 7.5 = 45 ns */
-			| AT91_DDRC2_TRCD_(2)	/* 2 * 7.5 = 22.5 ns */
-			| AT91_DDRC2_TWR_(2)	/* 2 * 7.5 = 15   ns */
-			| AT91_DDRC2_TRC_(8)	/* 8 * 7.5 = 75   ns */
-			| AT91_DDRC2_TRP_(2)	/* 2 * 7.5 = 15   ns */
-			| AT91_DDRC2_TRRD_(2)	/* 2 * 7.5 = 15   ns */
-			| AT91_DDRC2_TWTR_(2)	/* 2 clock cycles min */
-			| AT91_DDRC2_TMRD_(2),	/* 2 clock cycles */
-
-		.t1pr = AT91_DDRC2_TXP_(2)		/* 2 clock cycles */
-			| AT91_DDRC2_TXSRD_(200)	/* 200 clock cycles */
-			| AT91_DDRC2_TXSNR_(19)	/* 19 * 7.5 = 142.5 ns */
-			| AT91_DDRC2_TRFC_(17),	/* 17 * 7.5 = 127.5 ns */
-
-		.t2pr = AT91_DDRC2_TFAW_(6)	/* 6 * 7.5 = 45 ns */
-			| AT91_DDRC2_TRTP_(2)		/* 2 clock cycles min */
-			| AT91_DDRC2_TRPA_(2)		/* 2 * 7.5 = 15 ns */
-			| AT91_DDRC2_TXARDS_(8)	/* = TXARD */
-			| AT91_DDRC2_TXARD_(8),	/* MR12 = 1 */
-	};
-	u32 reg;
-
-	/* enable ddr2 clock */
-	sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_MPDDRC);
-	at91_pmc_enable_system_clock(IOMEM(SAMA5D3_BASE_PMC), AT91CAP9_PMC_DDR);
-
-
-	/* Init the special register for sama5d3x */
-	/* MPDDRC DLL Slave Offset Register: DDR2 configuration */
-	reg = AT91_MPDDRC_S0OFF_1
-		| AT91_MPDDRC_S2OFF_1
-		| AT91_MPDDRC_S3OFF_1;
-	writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_DLL_SOR);
-
-	/* MPDDRC DLL Master Offset Register */
-	/* write master + clk90 offset */
-	reg = AT91_MPDDRC_MOFF_7
-		| AT91_MPDDRC_CLK90OFF_31
-		| AT91_MPDDRC_SELOFF_ENABLED | AT91_MPDDRC_KEY;
-	writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_DLL_MOR);
-
-	/* MPDDRC I/O Calibration Register */
-	/* DDR2 RZQ = 50 Ohm */
-	/* TZQIO = 4 */
-	reg = AT91_MPDDRC_RDIV_DDR2_RZQ_50
-		| AT91_MPDDRC_TZQIO_4;
-	writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_IO_CALIBR);
-
-	/* DDRAM2 Controller initialize */
-	at91_ddram_initialize(IOMEM(SAMA5D3_BASE_MPDDRC), IOMEM(SAMA5_DDRCS),
-			      &conf);
-}
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
deleted file mode 100644
index cd2102c20e..0000000000
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Chip-specific header file for the SAMA5D3 family
- *
- *  Copyright (C) 2009-2012 Atmel Corporation.
- *
- * Common definitions.
- * Based on SAMA5D3 datasheet.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef SAMA5D3_H
-#define SAMA5D3_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define SAMA5D3_ID_DBGU		 2	/* debug Unit (usually no special interrupt line) */
-#define SAMA5D3_ID_PIT		 3	/* Periodic Interval Timer Interrupt */
-#define SAMA5D3_ID_WDT		 4	/* Watchdog timer Interrupt */
-#define SAMA5D3_ID_HSMC5	 5	/* Static Memory Controller */
-#define SAMA5D3_ID_PIOA		 6	/* Parallel I/O Controller A */
-#define SAMA5D3_ID_PIOB		 7	/* Parallel I/O Controller B */
-#define SAMA5D3_ID_PIOC		 8	/* Parallel I/O Controller C */
-#define SAMA5D3_ID_PIOD		 9	/* Parallel I/O Controller D */
-#define SAMA5D3_ID_PIOE		10	/* Parallel I/O Controller E */
-#define SAMA5D3_ID_SMD		11	/* SMD Soft Modem */
-#define SAMA5D3_ID_USART0	12	/* USART0 */
-#define SAMA5D3_ID_USART1	13	/* USART1 */
-#define SAMA5D3_ID_USART2	14	/* USART2 */
-#define SAMA5D3_ID_USART3	15	/* USART3 */
-#define SAMA5D3_ID_UART0	16	/* UART0 */
-#define SAMA5D3_ID_UART1	17	/* UART1 */
-#define SAMA5D3_ID_TWI0		18	/* Two-Wire Interface 0 */
-#define SAMA5D3_ID_TWI1		19	/* Two-Wire Interface 1 */
-#define SAMA5D3_ID_TWI2		20	/* Two-Wire Interface 2 */
-#define SAMA5D3_ID_HSMCI0	21	/* High Speed Multimedia Card Interface 0 */
-#define SAMA5D3_ID_HSMCI1	22	/* High Speed Multimedia Card Interface 1 */
-#define SAMA5D3_ID_HSMCI2	23	/* High Speed Multimedia Card Interface 2 */
-#define SAMA5D3_ID_SPI0		24	/* Serial Peripheral Interface 0 */
-#define SAMA5D3_ID_SPI1		25	/* Serial Peripheral Interface 1 */
-#define SAMA5D3_ID_TC0		26	/* Timer Counter 0 (ch. 0, 1, 2) */
-#define SAMA5D3_ID_TC1		27	/* Timer Counter 1 (ch. 3, 4, 5) */
-#define SAMA5D3_ID_PWM		28	/* Pulse Width Modulation Controller */
-#define SAMA5D3_ID_ADC		29	/* Touch Screen ADC Controller */
-#define SAMA5D3_ID_DMA0		30	/* DMA Controller 0 */
-#define SAMA5D3_ID_DMA1		31	/* DMA Controller 1 */
-#define SAMA5D3_ID_UHPHS	32	/* USB Host High Speed */
-#define SAMA5D3_ID_UDPHS	33	/* USB Device High Speed */
-#define SAMA5D3_ID_GMAC		34	/* Gigabit Ethernet MAC */
-#define SAMA5D3_ID_EMAC		35	/* Ethernet MAC */
-#define SAMA5D3_ID_LCDC		36	/* LCD Controller */
-#define SAMA5D3_ID_ISI		37	/* Image Sensor Interface */
-#define SAMA5D3_ID_SSC0		38	/* Synchronous Serial Controller 0 */
-#define SAMA5D3_ID_SSC1		39	/* Synchronous Serial Controller 1 */
-#define SAMA5D3_ID_CAN0		40	/* CAN controller 0 */
-#define SAMA5D3_ID_CAN1		41	/* CAN controller 1 */
-#define SAMA5D3_ID_SHA		42	/* Secure Hash Algorithm */
-#define SAMA5D3_ID_AES		43	/* Advanced Encryption Standard */
-#define SAMA5D3_ID_TDES		44	/* Triple Data Encryption Standard */
-#define SAMA5D3_ID_TRNG		45	/* True Random Number Generator */
-#define SAMA5D3_ID_ARM		46	/* Performance Monitor Unit */
-#define SAMA5D3_ID_AIC		47	/* Advanced Interrupt Controller */
-#define SAMA5D3_ID_FUSE		48	/* Fuse Controller */
-#define SAMA5D3_ID_MPDDRC	49	/* MPDDR controller */
-
-/*
- * User Peripheral physical base addresses.
- */
-
-#define SAMA5D3_BASE_HSMCI0	0xf0000000 /* (MMCI) Base Address */
-#define SAMA5D3_BASE_SPI0	0xf0004000
-#define SAMA5D3_BASE_TC0	0xf0010000 /* (TC0) Base Address */
-#define SAMA5D3_BASE_TC1	0xf0010040 /* (TC1) Base Address */
-#define	SAMA5D3_BASE_USART0	0xf001c000
-#define	SAMA5D3_BASE_USART1	0xf0020000
-#define SAMA5D3_BASE_GMAC	0xf0028000 /* (GMAC) Base Address */
-#define SAMA5D3_BASE_LCDC	0xf0030000 /* (HLCDC5) Base Address */
-#define SAMA5D3_BASE_HSMCI1	0xf8000000
-#define SAMA5D3_BASE_HSMCI2	0xf8004000
-#define SAMA5D3_BASE_SPI1	0xf8008000
-#define SAMA5D3_BASE_EMAC	0xf802c000 /* (EMAC) Base Address */
-#define SAMA5D3_BASE_UDPHS	0xf8030000
-
-#define SAMA5D3_BASE_PIOA	0xfffff200
-#define SAMA5D3_BASE_PIOB	0xfffff400
-#define SAMA5D3_BASE_PIOC	0xfffff600
-#define SAMA5D3_BASE_PIOD	0xfffff800
-#define SAMA5D3_BASE_PIOE	0xfffffa00
-#define SAMA5D3_BASE_MPDDRC	0xffffea00
-#define	SAMA5D3_BASE_HSMC	0xffffc000
-#define SAMA5D3_BASE_RSTC	0xfffffe00
-#define SAMA5D3_BASE_PIT	0xfffffe30
-#define SAMA5D3_BASE_WDT	0xfffffe40
-#define SAMA5D3_BASE_PMC	0xfffffc00
-#define SAMA5D3_BASE_PMECC	0xffffc070
-#define SAMA5D3_BASE_PMERRLOC	0xffffc500
-
-/*
- * Internal Memory.
- */
-#define SAMA5D3_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define SAMA5D3_SRAM_SIZE	(128 * SZ_1K)	/* Internal SRAM size (128Kb) */
-
-#define SAMA5D3_ROM_BASE	0x00100000
-#define SAMA5D3_ROM_SIZE	SZ_1M
-
-#define SAMA5D3_UDPHS_FIFO	0x00500000
-#define SAMA5D3_OHCI_BASE	0x00600000	/* USB Host controller (OHCI) */
-#define SAMA5D3_EHCI_BASE	0x00700000	/* USB Host controller (EHCI) */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d3_ll.h b/arch/arm/mach-at91/include/mach/sama5d3_ll.h
deleted file mode 100644
index b5b6b5d820..0000000000
--- a/arch/arm/mach-at91/include/mach/sama5d3_ll.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef __SAMA5D3_LL_H__
-#define __SAMA5D3_LL_H__
-
-#include <mach/at91_pmc_ll.h>
-#include <mach/debug_ll.h>
-#include <mach/early_udelay.h>
-
-void sama5d3_lowlevel_init(void);
-
-static inline void sama5d3_pmc_enable_periph_clock(int clk)
-{
-	at91_pmc_enable_periph_clock(IOMEM(SAMA5D3_BASE_PMC), clk);
-}
-
-/* requires relocation */
-static inline void sama5d3_udelay_init(unsigned int msc)
-{
-	early_udelay_init(IOMEM(SAMA5D3_BASE_PMC), IOMEM(SAMA5D3_BASE_PIT),
-			  SAMA5D3_ID_PIT, msc, AT91_PMC_LL_SAMA5D3);
-}
-
-#endif /* __SAMA5D3_LL_H__ */
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
deleted file mode 100644
index 6d621e0111..0000000000
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Chip-specific header file for the SAMA5D4 family
- *
- * Copyright (C) 2014 Atmel Corporation,
- *		      Bo Shen <voice.shen@atmel.com>
- *
- * Common definitions.
- * Based on SAMA5D4 datasheet.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef SAMA5D4_H
-#define SAMA5D4_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define SAMA5D4_ID_PIT		 3
-#define SAMA5D4_ID_WDT		 4
-#define SAMA5D4_ID_PIOD		 5
-#define SAMA5D4_ID_USART0	 6
-#define SAMA5D4_ID_USART1	 7
-#define SAMA5D4_ID_DMA0		 8
-#define SAMA5D4_ID_ICM		 9
-#define SAMA5D4_ID_PKCC		10
-#define SAMA5D4_ID_SCI		11
-#define SAMA5D4_ID_AES		12
-#define SAMA5D4_ID_AESB		13
-#define SAMA5D4_ID_TDES		14
-#define SAMA5D4_ID_SHA		15
-#define SAMA5D4_ID_MPDDRC	16
-#define SAMA5D4_ID_MATRIX1	17
-#define SAMA5D4_ID_MATRIX0	18
-#define SAMA5D4_ID_VDEC		19
-#define SAMA5D4_ID_SECUMOD	20
-#define SAMA5D4_ID_MSADCC	21
-#define SAMA5D4_ID_HSMC		22
-#define SAMA5D4_ID_PIOA		23
-#define SAMA5D4_ID_PIOB		24
-#define SAMA5D4_ID_PIOC		25
-#define SAMA5D4_ID_PIOE		26
-#define SAMA5D4_ID_UART0	27
-#define SAMA5D4_ID_UART1	28
-#define SAMA5D4_ID_USART2	29
-#define SAMA5D4_ID_USART3	30
-#define SAMA5D4_ID_USART4	31
-#define SAMA5D4_ID_TWI0		32
-#define SAMA5D4_ID_TWI1		33
-#define SAMA5D4_ID_TWI2		34
-#define SAMA5D4_ID_HSMCI0	35
-#define SAMA5D4_ID_HSMCI1	36
-#define SAMA5D4_ID_SPI0		37
-#define SAMA5D4_ID_SPI1		38
-#define SAMA5D4_ID_SPI2		39
-#define SAMA5D4_ID_TC0		40
-#define SAMA5D4_ID_TC1		41
-#define SAMA5D4_ID_TC2		42
-#define SAMA5D4_ID_PWM		43
-#define SAMA5D4_ID_ADC		44
-#define SAMA5D4_ID_DBGU		45
-#define SAMA5D4_ID_UHPHS	46
-#define SAMA5D4_ID_UDPHS	47
-#define SAMA5D4_ID_SSC0		48
-#define SAMA5D4_ID_SSC1		49
-#define SAMA5D4_ID_DMA1		50
-#define SAMA5D4_ID_LCDC		51
-#define SAMA5D4_ID_ISI		52
-#define SAMA5D4_ID_TRNG		53
-#define SAMA5D4_ID_GMAC0	54
-#define SAMA5D4_ID_IRQ		56
-#define SAMA5D4_ID_IRQ		56
-#define SAMA5D4_ID_SFC		57
-#define SAMA5D4_ID_SECURAM	59
-#define SAMA5D4_ID_CTB		60
-#define SAMA5D4_ID_SMD		61
-#define SAMA5D4_ID_TWI3		62
-#define SAMA5D4_ID_CATB		63
-#define SAMA5D4_ID_SFR		64
-#define SAMA5D4_ID_AIC		65
-#define SAMA5D4_ID_SAIC		66
-#define SAMA5D4_ID_L2CC		67
-
-/*
- * User Peripheral physical base addresses.
- */
-
-#define SAMA5D4_BASE_LCDC	0xf0000000 /* (HLCDC5) Base Address */
-#define SAMA5D4_BASE_MPDDRC	0xf0010000 /* (MPDDRC) Base Address */
-#define SAMA5D4_BASE_PMC	0xf0018000 /* (PMC) Base Address */
-#define SAMA5D4_BASE_HSMCI0	0xf8000000 /* (MMCI0) Base Address */
-#define SAMA5D4_BASE_UART0	0xf8004000 /* (UART0) Base Address */
-#define SAMA5D4_BASE_SPI0	0xf8010000 /* (SPI0) Base Address */
-#define SAMA5D4_BASE_TC0	0xf801c000 /* (TC0) Base Address */
-#define SAMA5D4_BASE_GMAC0	0xf8020000 /* (GMAC0) Base Address */
-#define SAMA5D4_BASE_USART0	0xf802c000 /* (USART0) Base Address */
-#define SAMA5D4_BASE_USART1	0xf8030000 /* (USART1) Base Address */
-#define SAMA5D4_BASE_HSMCI1	0xfc000000 /* (HSMCI1) Base Address */
-#define SAMA5D4_BASE_UART1	0xfc004000 /* (UART1) Base Address */
-#define SAMA5D4_BASE_USART2	0xfc008000 /* (USART2) Base Address */
-#define SAMA5D4_BASE_USART3	0xfc00c000 /* (USART3) Base Address */
-#define SAMA5D4_BASE_USART4	0xfc010000 /* (USART4) Base Address */
-#define SAMA5D4_BASE_SPI1	0xfc018000 /* (SPI1) Base Address */
-#define SAMA5D4_BASE_GMAC1	0xfc028000 /* (GMAC1) Base Address */
-#define SAMA5D4_BASE_HSMC	0xfc05c000 /* (HSMC) Base Address */
-#define SAMA5D4_BASE_PMECC	0xfc05c070 /* (PMECC) Base Address */
-#define SAMA5D4_BASE_PMERRLOC	0xfc05c500 /* (PMERRLOC) Base Address */
-#define SAMA5D4_BASE_PIOD	0xfc068000 /* (PIOD) Base Address */
-#define SAMA5D4_BASE_RSTC	0xfc068600
-#define SAMA5D4_BASE_PIT	0xfc068630 /* (PIT) Base Address */
-#define SAMA5D4_BASE_DBGU	0xfc069000 /* (DBGU) Base Address */
-#define SAMA5D4_BASE_PIOA	0xfc06a000 /* (PIOA) Base Address */
-#define SAMA5D4_BASE_PIOB	0xfc06b000 /* (PIOB) Base Address */
-#define SAMA5D4_BASE_PIOC	0xfc06c000 /* (PIOC) Base Address */
-#define SAMA5D4_BASE_PIOE	0xfc06d000 /* (PIOE) Base Address */
-#define SAMA5D4_BASE_AIC	0xfc06e000 /* (AIC) Base Address */
-
-#define SAMA5D4_CHIPSELECT_3	0x80000000
-
-/*
- * Internal Memory.
- */
-#define SAMA5D4_SRAM_BASE	0x00200000	/* Internal SRAM base address */
-#define SAMA5D4_SRAM_SIZE	(128 * SZ_1K)	/* Internal SRAM size */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/tz_matrix.h b/arch/arm/mach-at91/include/mach/tz_matrix.h
deleted file mode 100644
index 85589bfa65..0000000000
--- a/arch/arm/mach-at91/include/mach/tz_matrix.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: BSD-1-Clause */
-/*
- * Copyright (c) 2013, Atmel Corporation
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- */
-#ifndef __TZ_MATRIX_H__
-#define __TZ_MATRIX_H__
-
-#define MATRIX_MCFG(n)	(0x0000 + (n) * 4)/* Master Configuration Register */
-#define MATRIX_SCFG(n)	(0x0040 + (n) * 4)/* Slave Configuration Register */
-#define MATRIX_PRAS(n)	(0x0080 + (n) * 8)/* Priority Register A for Slave */
-#define MATRIX_PRBS(n)	(0x0084 + (n) * 8)/* Priority Register B for Slave */
-
-#define MATRIX_MRCR	0x0100	/* Master Remap Control Register */
-#define MATRIX_MEIER	0x0150	/* Master Error Interrupt Enable Register */
-#define MATRIX_MEIDR	0x0154	/* Master Error Interrupt Disable Register */
-#define MATRIX_MEIMR	0x0158	/* Master Error Interrupt Mask Register */
-#define MATRIX_MESR	0x015c	/* Master Error Statue Register */
-
-/* Master n Error Address Register */
-#define MATRIX_MEAR(n)	(0x0160 + (n) * 4)
-
-#define MATRIX_WPMR	0x01E4		/* Write Protect Mode Register */
-#define MATRIX_WPSR	0x01E8		/* Write Protect Status Register */
-
-/* Security Slave n Register */
-#define MATRIX_SSR(n)	(0x0200 + (n) * 4)
-/* Security Area Split Slave n Register */
-#define MATRIX_SASSR(n)	(0x0240 + (n) * 4)
-/* Security Region Top Slave n Register */
-#define MATRIX_SRTSR(n)	(0x0280 + (n) * 4)
-
-/* Security Peripheral Select n Register */
-#define MATRIX_SPSELR(n)	(0x02c0	+ (n) * 4)
-
-/**************************************************************************/
-/* Write Protect Mode Register (MATRIX_WPMR) */
-#define MATRIX_WPMR_WPEN	(1 << 0)	/* Write Protect Enable */
-#define		MATRIX_WPMR_WPEN_DISABLE	(0 << 0)
-#define		MATRIX_WPMR_WPEN_ENABLE		(1 << 0)
-#define	MATRIX_WPMR_WPKEY	(PASSWD << 8) /* Write Protect KEY */
-#define		MATRIX_WPMR_WPKEY_PASSWD	(0x4D4154 << 8)
-
-/* Security Slave Registers (MATRIX_SSRx) */
-#define MATRIX_LANSECH(n, bit)	((bit) << n)
-#define		MATRIX_LANSECH_S(n)	(0x00 << n)
-#define		MATRIX_LANSECH_NS(n)	(0x01 << n)
-#define MATRIX_RDNSECH(n, bit)	((bit) << (n + 8))
-#define		MATRIX_RDNSECH_S(n)	(0x00 << (n + 8))
-#define		MATRIX_RDNSECH_NS(n)	(0x01 << (n + 8))
-#define MATRIX_WRNSECH(n, bit)	((bit) << (n + 16))
-#define		MATRIX_WRNSECH_S(n)	(0x00 << (n + 16))
-#define		MATRIX_WRNSECH_NS(n)	(0x01 << (n + 16))
-
-/* Security Areas Split Slave Registers (MATRIX_SASSRx) */
-#define MATRIX_SASPLIT(n, value)	((value) << (4 * n))
-#define		MATRIX_SASPLIT_VALUE_4K		0x00
-#define		MATRIX_SASPLIT_VALUE_8K		0x01
-#define		MATRIX_SASPLIT_VALUE_16K	0x02
-#define		MATRIX_SASPLIT_VALUE_32K	0x03
-#define		MATRIX_SASPLIT_VALUE_64K	0x04
-#define		MATRIX_SASPLIT_VALUE_128K	0x05
-#define		MATRIX_SASPLIT_VALUE_256K	0x06
-#define		MATRIX_SASPLIT_VALUE_512K	0x07
-#define		MATRIX_SASPLIT_VALUE_1M		0x08
-#define		MATRIX_SASPLIT_VALUE_2M		0x09
-#define		MATRIX_SASPLIT_VALUE_4M		0x0a
-#define		MATRIX_SASPLIT_VALUE_8M		0x0b
-#define		MATRIX_SASPLIT_VALUE_16M	0x0c
-#define		MATRIX_SASPLIT_VALUE_32M	0x0d
-#define		MATRIX_SASPLIT_VALUE_64M	0x0e
-#define		MATRIX_SASPLIT_VALUE_128M	0x0f
-
-/* Security Region Top Slave Registers (MATRIX_SRTSRx) */
-#define MATRIX_SRTOP(n, value)		((value) << (4 * n))
-#define		MATRIX_SRTOP_VALUE_4K		0x00
-#define		MATRIX_SRTOP_VALUE_8K		0x01
-#define		MATRIX_SRTOP_VALUE_16K		0x02
-#define		MATRIX_SRTOP_VALUE_32K		0x03
-#define		MATRIX_SRTOP_VALUE_64K		0x04
-#define		MATRIX_SRTOP_VALUE_128K		0x05
-#define		MATRIX_SRTOP_VALUE_256K		0x06
-#define		MATRIX_SRTOP_VALUE_512K		0x07
-#define		MATRIX_SRTOP_VALUE_1M		0x08
-#define		MATRIX_SRTOP_VALUE_2M		0x09
-#define		MATRIX_SRTOP_VALUE_4M		0x0a
-#define		MATRIX_SRTOP_VALUE_8M		0x0b
-#define		MATRIX_SRTOP_VALUE_16M		0x0c
-#define		MATRIX_SRTOP_VALUE_32M		0x0d
-#define		MATRIX_SRTOP_VALUE_64M		0x0e
-#define		MATRIX_SRTOP_VALUE_128M		0x0f
-
-#endif /* #ifndef __TZ_MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h
deleted file mode 100644
index bbc70af210..0000000000
--- a/arch/arm/mach-at91/include/mach/xload.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __MACH_XLOAD_H
-#define __MACH_XLOAD_H
-
-#include <linux/compiler.h>
-#include <pbl.h>
-
-void __noreturn sama5d2_sdhci_start_image(u32 r4);
-void __noreturn sama5d3_atmci_start_image(u32 r4, unsigned int clock,
-					  unsigned int slot);
-
-int at91_sdhci_bio_init(struct pbl_bio *bio, void __iomem *base);
-int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
-		      unsigned int clock, unsigned int slot);
-
-#endif /* __MACH_XLOAD_H */
diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c
index b2e7345ec1..39ac3648f4 100644
--- a/arch/arm/mach-at91/matrix.c
+++ b/arch/arm/mach-at91/matrix.c
@@ -7,8 +7,8 @@
  */
 
 #include <io.h>
-#include <mach/tz_matrix.h>
-#include <mach/matrix.h>
+#include <mach/at91/tz_matrix.h>
+#include <mach/at91/matrix.h>
 
 static inline void matrix_write(void __iomem *base,
 				unsigned int offset,
diff --git a/arch/arm/mach-at91/sam9263_ll.c b/arch/arm/mach-at91/sam9263_ll.c
new file mode 100644
index 0000000000..a60d3c7a25
--- /dev/null
+++ b/arch/arm/mach-at91/sam9263_ll.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
+// SPDX-FileCopyrightText: 2017, Microchip Corporation
+
+#include <mach/at91/at91sam9263_matrix.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/at91_rstc.h>
+#include <mach/at91/at91_wdt.h>
+#include <mach/at91/sam92_ll.h>
+
+static void sam9263_pmc_init(u32 plla, u32 pllb)
+{
+	unsigned flags = AT91_PMC_LL_AT91SAM9263;
+	u32 mckr_settings;
+
+	at91_pmc_init(IOMEM(AT91SAM926X_BASE_PMC), flags);
+
+	/* Setting PLL A and divider A */
+	at91_pmc_cfg_plla(IOMEM(AT91SAM926X_BASE_PMC), plla, flags);
+
+	/* Selection of Master Clock and Processor Clock */
+	mckr_settings = AT91_PMC_PRES_1 | AT91SAM9_PMC_MDIV_2 | AT91_PMC_PDIV_1;
+
+	/* PCK = PLLA = 2 * MCK */
+	at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
+			 AT91_PMC_CSS_SLOW | mckr_settings, flags);
+
+	/* Switch MCK on PLLA output */
+	at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
+			 AT91_PMC_CSS_PLLA | mckr_settings, flags);
+
+	if (pllb)
+		at91_pmc_cfg_pllb(IOMEM(AT91SAM926X_BASE_PMC), pllb, flags);
+}
+
+static inline void matrix_wr(unsigned int offset, const unsigned int value)
+{
+	writel(value, IOMEM(AT91SAM9263_BASE_MATRIX + offset));
+}
+
+static void sam9263_matrix_init(void)
+{
+	/* Bus Matrix Master Configuration Register */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG0, AT91SAM9263_MATRIX_ULBT_SIXTEEN);	/* OHCI */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG1, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* ISI */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG2, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* 2D */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG3, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* DMAC */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG4, AT91SAM9263_MATRIX_ULBT_FOUR);	/* MACB */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG5, AT91SAM9263_MATRIX_ULBT_SIXTEEN);	/* LCDC */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG6, AT91SAM9263_MATRIX_ULBT_SINGLE);	/* PDC */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG7, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* DBUS */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG8, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* IBUS */
+
+	/* Bus Matrix Slave Configuration Registers */
+
+	/* ROM */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG0,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+	/* RAM80K */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG1,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+	/* RAM16K */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG2,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(16));
+
+	/* PERIPHERALS */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG3,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
+
+	/* EBI0 */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG4,
+		  AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+	/* EBI1 */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG5,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(64));
+
+	/* APB */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG6,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
+
+	/* ROM */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS0,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(0)
+		  | AT91SAM9263_MATRIX_M2PR_(2)
+		  | AT91SAM9263_MATRIX_M3PR_(1)
+		  | AT91SAM9263_MATRIX_M4PR_(0)
+		  | AT91SAM9263_MATRIX_M5PR_(3)
+		  | AT91SAM9263_MATRIX_M6PR_(2)
+		  | AT91SAM9263_MATRIX_M7PR_(3));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS0, AT91SAM9263_MATRIX_M8PR_(0));
+
+	/* RAM80K */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS1,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(2)
+		  | AT91SAM9263_MATRIX_M2PR_(1)
+		  | AT91SAM9263_MATRIX_M3PR_(3)
+		  | AT91SAM9263_MATRIX_M4PR_(0)
+		  | AT91SAM9263_MATRIX_M5PR_(0)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(0));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS1, AT91SAM9263_MATRIX_M8PR_(2));
+
+       /* RAM16K */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS2,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(0)
+		  | AT91SAM9263_MATRIX_M2PR_(2)
+		  | AT91SAM9263_MATRIX_M3PR_(1)
+		  | AT91SAM9263_MATRIX_M4PR_(0)
+		  | AT91SAM9263_MATRIX_M5PR_(3)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(2));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS2, AT91SAM9263_MATRIX_M8PR_(0));
+
+	/* PERIPHERALS */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS3,
+		  AT91SAM9263_MATRIX_M0PR_(0)
+		  | AT91SAM9263_MATRIX_M1PR_(1)
+		  | AT91SAM9263_MATRIX_M2PR_(0)
+		  | AT91SAM9263_MATRIX_M3PR_(2)
+		  | AT91SAM9263_MATRIX_M4PR_(1)
+		  | AT91SAM9263_MATRIX_M5PR_(0)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(2));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS3, AT91SAM9263_MATRIX_M8PR_(3));
+
+	/* EBI0 */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS4,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(3)
+		  | AT91SAM9263_MATRIX_M2PR_(0)
+		  | AT91SAM9263_MATRIX_M3PR_(2)
+		  | AT91SAM9263_MATRIX_M4PR_(3)
+		  | AT91SAM9263_MATRIX_M5PR_(0)
+		  | AT91SAM9263_MATRIX_M6PR_(0)
+		  | AT91SAM9263_MATRIX_M7PR_(1));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS4, AT91SAM9263_MATRIX_M8PR_(2));
+
+	/* EBI1 */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS5,
+		  AT91SAM9263_MATRIX_M0PR_(0)
+		  | AT91SAM9263_MATRIX_M1PR_(1)
+		  | AT91SAM9263_MATRIX_M2PR_(0)
+		  | AT91SAM9263_MATRIX_M3PR_(0)
+		  | AT91SAM9263_MATRIX_M4PR_(3)
+		  | AT91SAM9263_MATRIX_M5PR_(2)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(2));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS5, AT91SAM9263_MATRIX_M8PR_(1));
+
+	/* APB */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS6,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(0)
+		  | AT91SAM9263_MATRIX_M2PR_(2)
+		  | AT91SAM9263_MATRIX_M3PR_(1)
+		  | AT91SAM9263_MATRIX_M4PR_(0)
+		  | AT91SAM9263_MATRIX_M5PR_(0)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(3));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS6, AT91SAM9263_MATRIX_M8PR_(2));
+}
+
+static void sam9263_rstc_init(void)
+{
+	writel(AT91_RSTC_KEY | AT91_RSTC_URSTEN, IOMEM(AT91SAM926X_BASE_RSTC + AT91_RSTC_MR));
+}
+
+void sam9263_lowlevel_init(u32 plla, u32 pllb)
+{
+	at91_wdt_disable(IOMEM(AT91SAM9263_BASE_WDT));
+	sam9263_pmc_init(plla, pllb);
+	sam9263_matrix_init();
+	sam9263_rstc_init();
+}
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 66261a95ee..ef58a0153a 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -6,11 +6,11 @@
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/hardware.h>
-#include <mach/cpu.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/cpu.h>
 #include <linux/err.h>
 
-#include <mach/at91sam9_smc.h>
+#include <mach/at91/at91sam9_smc.h>
 
 #define AT91_SAM9_SMC_CS_STRIDE		0x10
 #define AT91_SAMA5_SMC_CS_STRIDE	0x14
@@ -168,7 +168,7 @@ void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config)
         sam9_smc_cs_write_timings(AT91_SMC_CS(id, cs), config);
 }
 
-static int at91sam9_smc_probe(struct device_d *dev)
+static int at91sam9_smc_probe(struct device *dev)
 {
 	struct resource *iores;
 	int id = dev->id;
@@ -190,9 +190,9 @@ static int at91sam9_smc_probe(struct device_d *dev)
 	return 0;
 }
 
-static struct driver_d at91sam9_smc_driver = {
+static struct driver at91sam9_smc_driver = {
 	.name = "at91sam9-smc",
 	.probe = at91sam9_smc_probe,
 };
 
-coredevice_platform_driver(at91sam9_smc_driver);
+postcore_platform_driver(at91sam9_smc_driver);
diff --git a/arch/arm/mach-at91/sama5_bootsource.c b/arch/arm/mach-at91/sama5_bootsource.c
new file mode 100644
index 0000000000..4ede256e8f
--- /dev/null
+++ b/arch/arm/mach-at91/sama5_bootsource.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <mach/at91/sama5_bootsource.h>
+#include <linux/export.h>
+#include <bootsource.h>
+#include <init.h>
+#include <of.h>
+
+/*
+ * sama5_bootsource_init - initialize bootsource
+ *
+ * BootROM will populate r4 when loading first stage bootloader
+ * with information about boot source. The entry points for
+ * multi-image capable SAMA5 boards will pass this information
+ * along. If you use a bootloader before barebox, you need to
+ * ensure that r4 is initialized for $bootsource to be correct
+ * in barebox. Example implementing it for AT91Bootstrap:
+ * https://github.com/linux4sam/at91bootstrap/pull/159
+ */
+static int sama5_bootsource_init(void)
+{
+	if (!of_machine_is_compatible("atmel,sama5"))
+		return 0;
+
+	at91_bootsource = __sama5d2_stashed_bootrom_r4;
+
+	if (at91_bootsource)
+		bootsource_set_raw(sama5_bootsource(at91_bootsource),
+				   sama5_bootsource_instance(at91_bootsource));
+
+	return 0;
+}
+postcore_initcall(sama5_bootsource_init);
diff --git a/arch/arm/mach-at91/sama5d2.c b/arch/arm/mach-at91/sama5d2.c
index a4aa8a2339..f629d1df33 100644
--- a/arch/arm/mach-at91/sama5d2.c
+++ b/arch/arm/mach-at91/sama5d2.c
@@ -3,12 +3,11 @@
 #include <common.h>
 #include <of.h>
 #include <init.h>
-#include <mach/aic.h>
-#include <mach/sama5d2.h>
+#include <mach/at91/aic.h>
+#include <mach/at91/sama5d2.h>
 #include <asm/cache-l2x0.h>
-#include <mach/sama5_bootsource.h>
 #include <asm/mmu.h>
-#include <mach/cpu.h>
+#include <mach/at91/cpu.h>
 
 #define SFR_CAN		0x48
 #define SFR_L2CC_HRAMC	0x58
@@ -54,17 +53,3 @@ static int sama5d2_init(void)
 	return 0;
 }
 postmmu_initcall(sama5d2_init);
-
-static int sama5d2_bootsource_init(void)
-{
-	if (!of_machine_is_compatible("atmel,sama5d2"))
-		return 0;
-
-	at91_bootsource = __sama5d2_stashed_bootrom_r4;
-
-	bootsource_set(sama5_bootsource(at91_bootsource));
-	bootsource_set_instance(sama5_bootsource_instance(at91_bootsource));
-
-	return 0;
-}
-postcore_initcall(sama5d2_bootsource_init);
diff --git a/arch/arm/mach-at91/sama5d2_ll.c b/arch/arm/mach-at91/sama5d2_ll.c
index 3366a50e8f..c0adf220a2 100644
--- a/arch/arm/mach-at91/sama5d2_ll.c
+++ b/arch/arm/mach-at91/sama5d2_ll.c
@@ -6,13 +6,13 @@
  * from this software without specific prior written permission.
  */
 
-#include <mach/sama5d2_ll.h>
-#include <mach/at91_ddrsdrc.h>
-#include <mach/ddramc.h>
-#include <mach/early_udelay.h>
-#include <mach/tz_matrix.h>
-#include <mach/matrix.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/sama5d2_ll.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/ddramc.h>
+#include <mach/at91/early_udelay.h>
+#include <mach/at91/tz_matrix.h>
+#include <mach/at91/matrix.h>
+#include <mach/at91/at91_rstc.h>
 #include <asm/barebox-arm.h>
 
 #define sama5d2_pmc_write(off, val) writel(val, SAMA5D2_BASE_PMC + off)
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index b1e7b2c565..447ac711b4 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -1,12 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <gpio.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/cpu.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_rstc.h>
 #include <linux/clk.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/sama5d3_devices.c b/arch/arm/mach-at91/sama5d3_devices.c
index 75f588deff..f6d5617e5f 100644
--- a/arch/arm/mach-at91/sama5d3_devices.c
+++ b/arch/arm/mach-at91/sama5d3_devices.c
@@ -8,13 +8,13 @@
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9x5_matrix.h>
-#include <mach/at91_ddrsdrc.h>
-#include <mach/iomux.h>
-#include <mach/cpu.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91sam9x5_matrix.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/cpu.h>
 #include <i2c/i2c-gpio.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/sama5d3_ll.c b/arch/arm/mach-at91/sama5d3_ll.c
index 4650593699..65eea93723 100644
--- a/arch/arm/mach-at91/sama5d3_ll.c
+++ b/arch/arm/mach-at91/sama5d3_ll.c
@@ -1,9 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
 // SPDX-FileCopyrightText: 2017, Microchip Corporation
 
-#include <mach/at91_wdt.h>
-#include <mach/barebox-arm.h>
-#include <mach/sama5d3_ll.h>
+#include <mach/at91/at91_wdt.h>
+#include <mach/at91/barebox-arm.h>
+#include <mach/at91/sama5d3_ll.h>
 
 void sama5d3_lowlevel_init(void)
 {
diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c
index 62e466fe51..8417dedbd1 100644
--- a/arch/arm/mach-at91/sama5d4.c
+++ b/arch/arm/mach-at91/sama5d4.c
@@ -11,11 +11,11 @@
 #include <gpio.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
-#include <mach/at91_rstc.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/cpu.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_rstc.h>
 #include <linux/clk.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/sama5d4_devices.c b/arch/arm/mach-at91/sama5d4_devices.c
index 6af1d3a4de..e438bd0d10 100644
--- a/arch/arm/mach-at91/sama5d4_devices.c
+++ b/arch/arm/mach-at91/sama5d4_devices.c
@@ -8,13 +8,13 @@
 #include <linux/sizes.h>
 #include <gpio.h>
 #include <asm/armlinux.h>
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91sam9x5_matrix.h>
-#include <mach/at91_ddrsdrc.h>
-#include <mach/iomux.h>
-#include <mach/cpu.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/board.h>
+#include <mach/at91/at91_pmc.h>
+#include <mach/at91/at91sam9x5_matrix.h>
+#include <mach/at91/at91_ddrsdrc.h>
+#include <mach/at91/iomux.h>
+#include <mach/at91/cpu.h>
 #include <i2c/i2c-gpio.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/sdramc.c b/arch/arm/mach-at91/sdramc.c
new file mode 100644
index 0000000000..655f24ecd9
--- /dev/null
+++ b/arch/arm/mach-at91/sdramc.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Ahmad Fatoum <a.fatoum@pengutronix.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/at91/hardware.h>
+#include <asm/barebox-arm.h>
+#include <mach/at91/at91sam9_sdramc.h>
+#include <asm/memory.h>
+#include <pbl.h>
+#include <io.h>
+
+void __noreturn at91sam9260_barebox_entry(void *boarddata)
+{
+	barebox_arm_entry(AT91_CHIPSELECT_1,
+			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
+			  boarddata);
+}
+
+static int at91_sdramc_probe(struct device *dev)
+{
+	struct resource *iores;
+	void __iomem *base;
+
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
+	base = IOMEM(iores->start);
+
+	return arm_add_mem_device("ram0", AT91_CHIPSELECT_1,
+				  at91_get_sdram_size(base));
+}
+
+static struct of_device_id at91_sdramc_dt_ids[] = {
+	{ .compatible = "atmel,at91sam9260-sdramc" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, at91_sdramc_dt_ids);
+
+static struct driver at91_sdramc_driver = {
+	.name   = "at91sam9260-sdramc",
+	.probe  = at91_sdramc_probe,
+	.of_compatible = at91_sdramc_dt_ids,
+};
+mem_platform_driver(at91_sdramc_driver);
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 47247dc97c..708c946192 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -11,11 +11,11 @@
 #include <restart.h>
 #include <linux/clk.h>
 
-#include <mach/hardware.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91_rstc.h>
-#include <mach/board.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/cpu.h>
+#include <mach/at91/at91_dbgu.h>
+#include <mach/at91/at91_rstc.h>
+#include <mach/at91/board.h>
 
 #include "generic.h"
 
@@ -371,7 +371,7 @@ postcore_initcall(at91_detect);
 
 static int at91_soc_device(void)
 {
-	struct device_d *dev;
+	struct device *dev;
 
 	dev = add_generic_device_res("soc", DEVICE_ID_SINGLE, NULL, 0, NULL);
 	dev_add_param_fixed(dev, "name", (char*)at91_get_soc_type(&at91_soc_initdata));
@@ -403,6 +403,3 @@ void at91sam_phy_reset(void __iomem *rstc_base)
 	/* Restore NRST value */
 	writel(AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN, rstc_base + AT91_RSTC_MR);
 }
-
-unsigned long at91_bootsource;
-EXPORT_SYMBOL(at91_bootsource);
diff --git a/arch/arm/mach-at91/xload-mmc.c b/arch/arm/mach-at91/xload-mmc.c
index 1b641f3a47..9c03d2119c 100644
--- a/arch/arm/mach-at91/xload-mmc.c
+++ b/arch/arm/mach-at91/xload-mmc.c
@@ -1,13 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <mach/xload.h>
-#include <mach/sama5_bootsource.h>
-#include <mach/hardware.h>
-#include <mach/sama5d2_ll.h>
-#include <mach/sama5d3_ll.h>
-#include <mach/gpio.h>
+#include <mach/at91/xload.h>
+#include <mach/at91/sama5_bootsource.h>
+#include <mach/at91/hardware.h>
+#include <mach/at91/sama5d2_ll.h>
+#include <mach/at91/sama5d3_ll.h>
+#include <mach/at91/gpio.h>
 #include <linux/sizes.h>
 #include <asm/cache.h>
-#include <pbl.h>
+#include <pbl/bio.h>
 
 static void at91_fat_start_image(struct pbl_bio *bio,
 				 void *buf, unsigned int len,
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 9d6a7b2ec2..f7434d2f5c 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_BCM283X
 
 config ARCH_TEXT_BASE
@@ -6,30 +8,49 @@ config ARCH_TEXT_BASE
 
 config MACH_RPI_COMMON
 	bool
+	select ARM_USE_COMPRESSED_DTB
+
+config MACH_RPI_AARCH_32_64
+	select MACH_RPI_COMMON
+	select CPU_V7 if 32BIT
+	select ARM_SECURE_MONITOR if 32BIT
+	select CPU_V8 if 64BIT
+	select BOARD_ARM_GENERIC_DT if 64BIT
+	bool
+	help
+	  Select this from CPUs that support both AArch32 and AArch64
+	  execution modes. barebox can be compiled for only one of
+	  these states, depending on the value of
+	  CONFIG_32BIT/CONFIG_64BIT.
 
 menu "select Broadcom BCM283X boards to be built"
 
 config MACH_RPI
 	bool "RaspberryPi (BCM2835/ARM1176JZF-S)"
+	depends on 32BIT
 	select CPU_V6
 	select MACH_RPI_COMMON
 
 config MACH_RPI2
 	bool "RaspberryPi 2 (BCM2836/CORTEX-A7)"
+	depends on 32BIT
 	select CPU_V7
 	select MACH_RPI_COMMON
 
 config MACH_RPI3
 	bool "RaspberryPi 3 (BCM2837/CORTEX-A53)"
-	select CPU_V7
+	select MACH_RPI_AARCH_32_64
 	select MACH_RPI_COMMON
-	select ARM_SECURE_MONITOR
 
 config MACH_RPI_CM3
 	bool "RaspberryPi Compute Module 3 (BCM2837/CORTEX-A53)"
-	select CPU_V7
+	select MACH_RPI_AARCH_32_64
+	select MACH_RPI_COMMON
+
+config MACH_RPI4
+	bool "RaspberryPi 4 (BCM2711/CORTEX-A72)"
+	select MACH_RPI_AARCH_32_64
 	select MACH_RPI_COMMON
-	select ARM_SECURE_MONITOR
 
 endmenu
 
diff --git a/arch/arm/mach-bcm283x/Makefile b/arch/arm/mach-bcm283x/Makefile
index 940f98cbce..53343cec8c 100644
--- a/arch/arm/mach-bcm283x/Makefile
+++ b/arch/arm/mach-bcm283x/Makefile
@@ -1 +1,3 @@
-obj-y += core.o mbox.o
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-pbl-y += mbox.o core.o
diff --git a/arch/arm/mach-bcm283x/core.c b/arch/arm/mach-bcm283x/core.c
index f2528cf1f1..1091ad0b56 100644
--- a/arch/arm/mach-bcm283x/core.c
+++ b/arch/arm/mach-bcm283x/core.c
@@ -1,40 +1,29 @@
-/*
- * Author: Carlo Caione <carlo@carlocaione.org>
- *
- * Based on mach-nomadik
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
-#include <common.h>
-#include <init.h>
+#include <linux/types.h>
+#include <mach/bcm283x/core.h>
+#include <asm/system_info.h>
 
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-
-#include <io.h>
-#include <asm/armlinux.h>
-#include <linux/sizes.h>
+void __iomem *bcm2835_get_mmio_base_by_cpuid(void)
+{
+	static u32 cpuid;
 
-#include <mach/platform.h>
-#include <mach/core.h>
-#include <linux/amba/bus.h>
+	if (!cpuid) {
+		cpuid = read_cpuid_id();
+		pr_debug("ARM CPUID: %08x\n", cpuid);
+	}
 
-void bcm2835_add_device_sdram(u32 size)
-{
-	if (!size)
-		size = get_ram_size((ulong *) BCM2835_SDRAM_BASE, SZ_128M);
+	/* We know ARM1167, Cortex A-7, A-53 and A-72 CPUID mask is identical */
+	switch(cpuid & CPU_IS_ARM1176_MASK) {
+	case CPU_IS_ARM1176:	/* bcm2835 */
+		return IOMEM(0x20000000);
+	case CPU_IS_CORTEX_A7:	/* bcm2836 */
+	case CPU_IS_CORTEX_A53:	/* bcm2837 */
+		return IOMEM(0x3f000000);
+	case CPU_IS_CORTEX_A72:	/* bcm2711 */
+		return IOMEM(0xfe000000);
+	}
 
-	arm_add_mem_device("ram0", BCM2835_SDRAM_BASE, size);
+	pr_err("Couldn't determine rpi by CPUID %08x\n", cpuid);
+	return NULL;
 }
diff --git a/arch/arm/mach-bcm283x/include/mach/core.h b/arch/arm/mach-bcm283x/include/mach/core.h
deleted file mode 100644
index a1c47f9154..0000000000
--- a/arch/arm/mach-bcm283x/include/mach/core.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2009 Carlo Caione <carlo@carlocaione.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __BCM2835_CORE_H__
-#define __BCM2835_CORE_H__
-
-#include <mach/platform.h>
-
-void bcm2835_add_device_sdram(u32 size);
-
-static void inline bcm2835_register_fb(void)
-{
-	add_generic_device("bcm2835_fb", 0, NULL, 0, 0, 0, NULL);
-}
-
-#endif
diff --git a/arch/arm/mach-bcm283x/include/mach/debug_ll.h b/arch/arm/mach-bcm283x/include/mach/debug_ll.h
deleted file mode 100644
index 4bfa5abc7c..0000000000
--- a/arch/arm/mach-bcm283x/include/mach/debug_ll.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_BCM2835_DEBUG_LL_H__
-#define __MACH_BCM2835_DEBUG_LL_H__
-
-#include <mach/platform.h>
-
-#ifdef CONFIG_DEBUG_RPI1_UART
-
-static inline void debug_ll_init(void)
-{
-	/* Configured by ROM */
-}
-
-#define DEBUG_LL_UART_ADDR BCM2835_PL011_BASE
-#include <debug_ll/pl011.h>
-
-#elif defined CONFIG_DEBUG_RPI2_3_UART
-
-static inline void debug_ll_init(void)
-{
-	/* Configured by ROM */
-}
-
-#define DEBUG_LL_UART_ADDR BCM2836_PL011_BASE
-#include <debug_ll/pl011.h>
-
-#elif defined CONFIG_DEBUG_RPI3_MINI_UART
-
-static inline uint8_t debug_ll_read_reg(int reg)
-{
-	return readb(BCM2836_MINIUART_BASE + (reg << 2));
-}
-
-static inline void debug_ll_write_reg(int reg, uint8_t val)
-{
-	writeb(val, BCM2836_MINIUART_BASE + (reg << 2));
-}
-
-#define BCM2836_AUX_CLOCK_ENB		0x3f215004 /* BCM2835 AUX Clock enable register */
-#define BCM2836_AUX_CLOCK_EN_UART	BIT(0) /* Bit 0 enables the Miniuart */
-
-#include <debug_ll/ns16550.h>
-
-static inline void debug_ll_init(void)
-{
-	uint16_t divisor;
-
-	writeb(BCM2836_AUX_CLOCK_EN_UART, BCM2836_AUX_CLOCK_ENB);
-
-	divisor = debug_ll_ns16550_calc_divisor(250000000 * 2);
-	debug_ll_ns16550_init(divisor);
-}
-
-#endif
-
-#endif /* __MACH_BCM2835_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
deleted file mode 100644
index f10f5bc148..0000000000
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * based on U-Boot code
- *
- * (C) Copyright 2012 Stephen Warren
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BCM2835_MBOX_H
-#define _BCM2835_MBOX_H
-
-#include <common.h>
-
-#include <mach/platform.h>
-
-/*
- * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
- * and the ARM CPU. The ARM CPU is often thought of as the main CPU.
- * However, the VideoCore actually controls the initial SoC boot, and hides
- * much of the hardware behind a protocol. This protocol is transported
- * using the SoC's mailbox hardware module.
- *
- * The mailbox hardware supports passing 32-bit values back and forth.
- * Presumably by software convention of the firmware, the bottom 4 bits of the
- * value are used to indicate a logical channel, and the upper 28 bits are the
- * actual payload. Various channels exist using these simple raw messages. See
- * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an
- * example, the messages on the power management channel are a bitmask of
- * devices whose power should be enabled.
- *
- * The property mailbox channel passes messages that contain the (16-byte
- * aligned) ARM physical address of a memory buffer. This buffer is passed to
- * the VC for processing, is modified in-place by the VC, and the address then
- * passed back to the ARM CPU as the response mailbox message to indicate
- * request completion. The buffers have a generic and extensible format; each
- * buffer contains a standard header, a list of "tags", and a terminating zero
- * entry. Each tag contains an ID indicating its type, and length fields for
- * generic parsing. With some limitations, an arbitrary set of tags may be
- * combined together into a single message buffer. This file defines structs
- * representing the header and many individual tag layouts and IDs.
- */
-
-/* Raw mailbox HW */
-#define ARM_0_MAIL0	0x00
-#define ARM_0_MAIL1	0x20
-
-#define MAIL0_RD	(ARM_0_MAIL0 + 0x00)
-#define MAIL0_POL	(ARM_0_MAIL0 + 0x10)
-#define MAIL0_STA	(ARM_0_MAIL0 + 0x18)
-#define MAIL0_CNF	(ARM_0_MAIL0 + 0x1C)
-#define MAIL1_WRT	(ARM_0_MAIL1 + 0x00)
-#define MAIL1_STA	(ARM_0_MAIL1 + 0x18)
-
-#define BCM2835_MBOX_STATUS_WR_FULL	0x80000000
-#define BCM2835_MBOX_STATUS_RD_EMPTY	0x40000000
-
-/* Lower 4-bits are channel ID */
-#define BCM2835_CHAN_MASK		0xf
-#define BCM2835_MBOX_PACK(chan, data)	(((data) & (~BCM2835_CHAN_MASK)) | \
-					 (chan & BCM2835_CHAN_MASK))
-#define BCM2835_MBOX_UNPACK_CHAN(val)	((val) & BCM2835_CHAN_MASK)
-#define BCM2835_MBOX_UNPACK_DATA(val)	((val) & (~BCM2835_CHAN_MASK))
-
-/* Property mailbox buffer structures */
-
-#define BCM2835_MBOX_PROP_CHAN		8
-
-/* All message buffers must start with this header */
-struct bcm2835_mbox_hdr {
-	u32 buf_size;
-	u32 code;
-};
-
-#define BCM2835_MBOX_REQ_CODE		0
-#define BCM2835_MBOX_RESP_CODE_SUCCESS	0x80000000
-
-#define BCM2835_MBOX_STACK_ALIGN(type, name) \
-	STACK_ALIGN_ARRAY(type, name, 1, BCM2835_CACHELINE_SIZE)
-
-#define BCM2835_MBOX_INIT_HDR(_m_) { \
-		memset((_m_), 0, sizeof(*(_m_))); \
-		(_m_)->hdr.buf_size = sizeof(*(_m_)); \
-		(_m_)->hdr.code = 0; \
-		(_m_)->end_tag = 0; \
-	}
-
-/*
- * A message buffer contains a list of tags. Each tag must also start with
- * a standardized header.
- */
-struct bcm2835_mbox_tag_hdr {
-	u32 tag;
-	u32 val_buf_size;
-	u32 val_len;
-};
-
-#define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \
-		(_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
-		(_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
-		(_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \
-	}
-
-#define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \
-		(_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
-		(_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
-		(_t_)->tag_hdr.val_len = 0; \
-	}
-
-/* When responding, the VC sets this bit in val_len to indicate a response */
-#define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE	0x80000000
-
-/*
- * Below we define the ID and struct for many possible tags. This header only
- * defines individual tag structs, not entire message structs, since in
- * general an arbitrary set of tags may be combined into a single message.
- * Clients of the mbox API are expected to define their own overall message
- * structures by combining the header, a set of tags, and a terminating
- * entry. For example,
- *
- * struct msg {
- *     struct bcm2835_mbox_hdr hdr;
- *     struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
- *     ... perhaps other tags here ...
- *     u32 end_tag;
- * };
- */
-
-#define BCM2835_MBOX_TAG_GET_BOARD_REV	0x00010002
-#define BCM2835_MBOX_TAG_GET_GPIO_STATE 0x00030041
-#define BCM2835_MBOX_TAG_SET_GPIO_STATE 0x00038041
-#define BCM2835_MBOX_TAG_GET_GPIO_CONFIG 0x00030043
-#define BCM2835_MBOX_TAG_SET_GPIO_CONFIG 0x00038043
-
-/*
- * ids
- * 	https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
- * cpu info
- * 	https://en.wikipedia.org/wiki/Raspberry_Pi#Processor
- *
- */
-#define BCM2835_BOARD_REV_B_I2C0_2	0x2
-#define BCM2835_BOARD_REV_B_I2C0_3	0x3
-#define BCM2835_BOARD_REV_B_I2C1_4	0x4
-#define BCM2835_BOARD_REV_B_I2C1_5	0x5
-#define BCM2835_BOARD_REV_B_I2C1_6	0x6
-#define BCM2835_BOARD_REV_A_7		0x7
-#define BCM2835_BOARD_REV_A_8		0x8
-#define BCM2835_BOARD_REV_A_9		0x9
-#define BCM2835_BOARD_REV_B_REV2_d	0xd
-#define BCM2835_BOARD_REV_B_REV2_e	0xe
-#define BCM2835_BOARD_REV_B_REV2_f	0xf
-#define BCM2835_BOARD_REV_B_PLUS_10	0x10
-#define BCM2835_BOARD_REV_CM_11		0x11
-#define BCM2835_BOARD_REV_A_PLUS_12	0x12
-#define BCM2835_BOARD_REV_B_PLUS_13	0x13
-#define BCM2835_BOARD_REV_CM_14		0x14
-#define BCM2835_BOARD_REV_A_PLUS_15	0x15
-
-
-#define BCM2835_BOARD_REV_A   		0x00
-#define BCM2835_BOARD_REV_B   		0x01
-#define BCM2835_BOARD_REV_A_PLUS   	0x02
-#define BCM2835_BOARD_REV_B_PLUS   	0x03
-#define BCM2836_BOARD_REV_2_B   	0x04
-#define BCM283x_BOARD_REV_Alpha   	0x05
-#define BCM2835_BOARD_REV_CM1   	0x06
-#define BCM2837_BOARD_REV_3_B   	0x08
-#define BCM2835_BOARD_REV_ZERO   	0x09
-#define BCM2837_BOARD_REV_CM3   	0x0a
-#define BCM2835_BOARD_REV_ZERO_W   	0x0c
-#define BCM2837B0_BOARD_REV_3B_PLUS   	0x0d
-#define BCM2837B0_BOARD_REV_3A_PLUS   	0x0e
-#define BCM2837B0_BOARD_REV_CM3_PLUS	0x10
-
-struct bcm2835_mbox_tag_get_board_rev {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u32 rev;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS	0x00010003
-
-struct bcm2835_mbox_tag_get_mac_address {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u8 mac[6];
-			u8 pad[2];
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_ARM_MEMORY		0x00010005
-
-struct bcm2835_mbox_tag_get_arm_mem {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u32 mem_base;
-			u32 mem_size;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_POWER_DEVID_SDHCI		0
-#define BCM2835_MBOX_POWER_DEVID_UART0		1
-#define BCM2835_MBOX_POWER_DEVID_UART1		2
-#define BCM2835_MBOX_POWER_DEVID_USB_HCD	3
-#define BCM2835_MBOX_POWER_DEVID_I2C0		4
-#define BCM2835_MBOX_POWER_DEVID_I2C1		5
-#define BCM2835_MBOX_POWER_DEVID_I2C2		6
-#define BCM2835_MBOX_POWER_DEVID_SPI		7
-#define BCM2835_MBOX_POWER_DEVID_CCP2TX		8
-
-#define BCM2835_MBOX_POWER_STATE_RESP_ON	(1 << 0)
-/* Device doesn't exist */
-#define BCM2835_MBOX_POWER_STATE_RESP_NODEV	(1 << 1)
-
-#define BCM2835_MBOX_TAG_GET_POWER_STATE	0x00020001
-
-struct bcm2835_mbox_tag_get_power_state {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 device_id;
-		} req;
-		struct {
-			u32 device_id;
-			u32 state;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_SET_POWER_STATE	0x00028001
-
-#define BCM2835_MBOX_SET_POWER_STATE_REQ_OFF	(0 << 0)
-#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON	(1 << 0)
-#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT	(1 << 1)
-
-struct bcm2835_mbox_tag_set_power_state {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 device_id;
-			u32 state;
-		} req;
-		struct {
-			u32 device_id;
-			u32 state;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_CLOCK_RATE	0x00030002
-
-#define BCM2835_MBOX_CLOCK_ID_EMMC	1
-#define BCM2835_MBOX_CLOCK_ID_UART	2
-#define BCM2835_MBOX_CLOCK_ID_ARM	3
-#define BCM2835_MBOX_CLOCK_ID_CORE	4
-#define BCM2835_MBOX_CLOCK_ID_V3D	5
-#define BCM2835_MBOX_CLOCK_ID_H264	6
-#define BCM2835_MBOX_CLOCK_ID_ISP	7
-#define BCM2835_MBOX_CLOCK_ID_SDRAM	8
-#define BCM2835_MBOX_CLOCK_ID_PIXEL	9
-#define BCM2835_MBOX_CLOCK_ID_PWM	10
-
-struct bcm2835_mbox_tag_get_clock_rate {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 clock_id;
-		} req;
-		struct {
-			u32 clock_id;
-			u32 rate_hz;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_ALLOCATE_BUFFER	0x00040001
-
-struct bcm2835_mbox_tag_allocate_buffer {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 alignment;
-		} req;
-		struct {
-			u32 fb_address;
-			u32 fb_size;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_RELEASE_BUFFER		0x00048001
-
-struct bcm2835_mbox_tag_release_buffer {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_BLANK_SCREEN		0x00040002
-
-struct bcm2835_mbox_tag_blank_screen {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			/* bit 0 means on, other bits reserved */
-			u32 state;
-		} req;
-		struct {
-			u32 state;
-		} resp;
-	} body;
-};
-
-/* Physical means output signal */
-#define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H	0x00040003
-#define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H	0x00044003
-#define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H	0x00048003
-
-struct bcm2835_mbox_tag_physical_w_h {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 width;
-			u32 height;
-		} req;
-		struct {
-			u32 width;
-			u32 height;
-		} resp;
-	} body;
-};
-
-/* Virtual means display buffer */
-#define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H	0x00040004
-#define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H	0x00044004
-#define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H	0x00048004
-
-struct bcm2835_mbox_tag_virtual_w_h {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 width;
-			u32 height;
-		} req;
-		struct {
-			u32 width;
-			u32 height;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_DEPTH		0x00040005
-#define BCM2835_MBOX_TAG_TEST_DEPTH		0x00044005
-#define BCM2835_MBOX_TAG_SET_DEPTH		0x00048005
-
-struct bcm2835_mbox_tag_depth {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 bpp;
-		} req;
-		struct {
-			u32 bpp;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_PIXEL_ORDER	0x00040006
-#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER	0x00044005
-#define BCM2835_MBOX_TAG_SET_PIXEL_ORDER	0x00048006
-
-#define BCM2835_MBOX_PIXEL_ORDER_BGR		0
-#define BCM2835_MBOX_PIXEL_ORDER_RGB		1
-
-struct bcm2835_mbox_tag_pixel_order {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 order;
-		} req;
-		struct {
-			u32 order;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_ALPHA_MODE		0x00040007
-#define BCM2835_MBOX_TAG_TEST_ALPHA_MODE	0x00044007
-#define BCM2835_MBOX_TAG_SET_ALPHA_MODE		0x00048007
-
-#define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE	0
-#define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT	1
-#define BCM2835_MBOX_ALPHA_MODE_IGNORED		2
-
-struct bcm2835_mbox_tag_alpha_mode {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 alpha;
-		} req;
-		struct {
-			u32 alpha;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_PITCH		0x00040008
-
-struct bcm2835_mbox_tag_pitch {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u32 pitch;
-		} resp;
-	} body;
-};
-
-/* Offset of display window within buffer */
-#define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET	0x00040009
-#define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET	0x00044009
-#define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET	0x00048009
-
-struct bcm2835_mbox_tag_virtual_offset {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 x;
-			u32 y;
-		} req;
-		struct {
-			u32 x;
-			u32 y;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_OVERSCAN		0x0004000a
-#define BCM2835_MBOX_TAG_TEST_OVERSCAN		0x0004400a
-#define BCM2835_MBOX_TAG_SET_OVERSCAN		0x0004800a
-
-struct bcm2835_mbox_tag_overscan {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 top;
-			u32 bottom;
-			u32 left;
-			u32 right;
-		} req;
-		struct {
-			u32 top;
-			u32 bottom;
-			u32 left;
-			u32 right;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_PALETTE		0x0004000b
-
-struct bcm2835_mbox_tag_get_palette {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u32 data[1024];
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_TEST_PALETTE		0x0004400b
-
-struct bcm2835_mbox_tag_test_palette {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 offset;
-			u32 num_entries;
-			u32 data[256];
-		} req;
-		struct {
-			u32 is_invalid;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_SET_PALETTE		0x0004800b
-
-struct bcm2835_mbox_tag_set_palette {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 offset;
-			u32 num_entries;
-			u32 data[256];
-		} req;
-		struct {
-			u32 is_invalid;
-		} resp;
-	} body;
-};
-
-/*
- * Pass a complete property-style buffer to the VC, and wait until it has
- * been processed.
- *
- * This function expects a pointer to the mbox_hdr structure in an attempt
- * to ensure some degree of type safety. However, some number of tags and
- * a termination value are expected to immediately follow the header in
- * memory, as required by the property protocol.
- *
- * Returns 0 for success, any other value for error.
- */
-int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);
-
-#endif
diff --git a/arch/arm/mach-bcm283x/include/mach/platform.h b/arch/arm/mach-bcm283x/include/mach/platform.h
deleted file mode 100644
index 310f2463f2..0000000000
--- a/arch/arm/mach-bcm283x/include/mach/platform.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Extract from arch/arm/mach-bcm2708/include/mach/platform.h
- *
- * Copyright (C) 2010 Broadcom
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BCM2835_PLATFORM_H
-#define _BCM2835_PLATFORM_H
-
-/*
- *  SDRAM
- */
-#define BCM2835_SDRAM_BASE	0x00000000
-
-/*
- * Definitions and addresses for the ARM CONTROL logic
- * This file is manually generated.
- */
-
-#define BCM2835_CACHELINE_SIZE	64
-
-#define BCM2835_PL011_BASE 0x20201000
-#define BCM2836_PL011_BASE 0x3f201000
-#define BCM2835_MINIUART_BASE 0x20215040
-#define BCM2836_MINIUART_BASE 0x3f215040
-
-#endif
-
-/* END */
diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c
index 9839683d03..32d646f4ad 100644
--- a/arch/arm/mach-bcm283x/mbox.c
+++ b/arch/arm/mach-bcm283x/mbox.c
@@ -13,13 +13,21 @@
 #include <dma.h>
 #include <init.h>
 #include <io.h>
+#include <of_address.h>
+#include <pbl.h>
 
-#include <mach/mbox.h>
+#include <mach/bcm283x/mbox.h>
+#include <mach/bcm283x/core.h>
 
 #define TIMEOUT (MSECOND * 1000)
 
 static void __iomem *mbox_base;
 
+#ifdef __PBL__
+#define is_timeout_non_interruptible(start, timeout) ((void)start, 0)
+#define get_time_ns() 0
+#endif
+
 static int bcm2835_mbox_call_raw(u32 chan, struct bcm2835_mbox_hdr *buffer,
 					u32 *recv)
 {
@@ -58,7 +66,7 @@ static int bcm2835_mbox_call_raw(u32 chan, struct bcm2835_mbox_hdr *buffer,
 	/* Send the request */
 	val = BCM2835_MBOX_PACK(chan, send);
 	pr_debug("mbox: TX raw: 0x%08x\n", val);
-	dma_sync_single_for_device((unsigned long)send, buffer->buf_size,
+	dma_sync_single_for_device(NULL, (unsigned long)send, buffer->buf_size,
 				   DMA_BIDIRECTIONAL);
 	writel(val, mbox_base + MAIL1_WRT);
 
@@ -76,7 +84,7 @@ static int bcm2835_mbox_call_raw(u32 chan, struct bcm2835_mbox_hdr *buffer,
 	/* Read the response */
 	val = readl(mbox_base + MAIL0_RD);
 	pr_debug("mbox: RX raw: 0x%08x\n", val);
-	dma_sync_single_for_cpu((unsigned long)send, buffer->buf_size,
+	dma_sync_single_for_cpu(NULL, (unsigned long)send, buffer->buf_size,
 				DMA_BIDIRECTIONAL);
 
 	/* Validate the response */
@@ -108,6 +116,22 @@ static void dump_buf(struct bcm2835_mbox_hdr *buffer)
 }
 #endif
 
+static void __iomem *bcm2835_mbox_probe(void)
+{
+	struct device_node *mbox_node;
+
+	if (IN_PBL)
+		return bcm2835_get_mmio_base_by_cpuid() + 0xb880;
+
+	mbox_node = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-mbox");
+	if (!mbox_node) {
+		pr_err("Missing mbox node\n");
+		return NULL;
+	}
+
+	return of_iomap(mbox_node, 0);
+}
+
 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
 {
 	int ret;
@@ -115,13 +139,19 @@ int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
 	struct bcm2835_mbox_tag_hdr *tag;
 	int tag_index;
 
+	if (!mbox_base) {
+		mbox_base = bcm2835_mbox_probe();
+		if (!mbox_base)
+			return -ENOENT;
+	}
+
 	pr_debug("mbox: TX buffer\n");
 	dump_buf(buffer);
 
 	ret = bcm2835_mbox_call_raw(chan, buffer, &rbuffer);
 	if (ret)
 		return ret;
-	if (rbuffer != (u32)buffer) {
+	if (rbuffer != (uintptr_t)buffer) {
 		pr_err("mbox: Response buffer mismatch\n");
 		return -EIO;
 	}
@@ -150,33 +180,3 @@ int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
 
 	return 0;
 }
-
-static int bcm2835_mbox_probe(struct device_d *dev)
-{
-	struct resource *iores;
-
-	iores = dev_request_mem_resource(dev, 0);
-	if (IS_ERR(iores)) {
-		dev_err(dev, "could not get memory region\n");
-		return PTR_ERR(iores);
-	}
-	mbox_base = IOMEM(iores->start);
-
-	return 0;
-}
-
-static __maybe_unused struct of_device_id bcm2835_mbox_dt_ids[] = {
-	{
-		.compatible = "brcm,bcm2835-mbox",
-	}, {
-		/* sentinel */
-	},
-};
-
-static struct driver_d bcm2835_mbox_driver = {
-	.name		= "bcm2835_mbox",
-	.of_compatible	= DRV_OF_COMPAT(bcm2835_mbox_dt_ids),
-	.probe		= bcm2835_mbox_probe,
-};
-
-core_platform_driver(bcm2835_mbox_driver);
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index c00514e86d..6cf6bc37a2 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_CLPS711X
 
 choice
@@ -14,7 +16,6 @@ menu "CLPS711X specific settings"
 
 config CLPS711X_RAISE_CPUFREQ
 	bool "Raise CPU frequency to 90 MHz"
-	depends on MACH_CLEP7212
 	help
 	  Raise CPU frequency to 90 MHz. This operation can be performed
 	  only for devices which allow to operate at 90 MHz.
@@ -22,12 +23,4 @@ config CLPS711X_RAISE_CPUFREQ
 
 endmenu
 
-config ARCH_TEXT_BASE
-	hex
-	default 0xc0740000 if MACH_CLEP7212
-
-config BAREBOX_MAX_IMAGE_SIZE
-	hex
-	default 0x00080000 if MACH_CLEP7212
-
 endif
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 45525343d7..871c5f7e9c 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -1,2 +1,4 @@
-obj-y += clock.o devices.o reset.o
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += clock.o common.o
 lwl-y += lowlevel.o
diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c
index 2c5137c582..4cb0f2bbfa 100644
--- a/arch/arm/mach-clps711x/clock.c
+++ b/arch/arm/mach-clps711x/clock.c
@@ -1,11 +1,5 @@
-/*
- * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru>
 
 #include <common.h>
 #include <init.h>
@@ -15,19 +9,21 @@
 #include <linux/sizes.h>
 #include <dt-bindings/clock/clps711x-clock.h>
 
-#include <mach/clps711x.h>
+#include <mach/clps711x/clps711x.h>
 
 #define CLPS711X_OSC_FREQ	3686400
 #define CLPS711X_EXT_FREQ	13000000
 
 static struct clk *clks[CLPS711X_CLK_MAX];
+static struct clk_onecell_data clk_data;
 
-static struct clk_div_table tdiv_tbl[] = {
+static const struct clk_div_table tdiv_tbl[] = {
 	{ .val = 0, .div = 256, },
 	{ .val = 1, .div = 1, },
+	{ }
 };
 
-static __init int clps711x_clk_init(void)
+static int clps711x_clk_probe(struct device *dev)
 {
 	unsigned int f_cpu, f_bus, f_uart, f_timer_ref, pll;
 	u32 tmp;
@@ -50,7 +46,7 @@ static __init int clps711x_clk_init(void)
 			f_bus = 36864000 / 2;
 	}
 
-	f_uart = f_bus / 10;
+	f_uart = DIV_ROUND_CLOSEST(f_bus, 10);
 
 	if (tmp & SYSFLG2_CKMODE) {
 		tmp = readw(SYSCON2);
@@ -72,23 +68,26 @@ static __init int clps711x_clk_init(void)
 	clks[CLPS711X_CLK_UART] = clk_fixed("uart", f_uart);
 	clks[CLPS711X_CLK_TIMERREF] = clk_fixed("timer_ref", f_timer_ref);
 	clks[CLPS711X_CLK_TIMER1] = clk_divider_table("timer1", "timer_ref", 0,
-		IOMEM(SYSCON1), 5, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl));
+		IOMEM(SYSCON1), 5, 1, tdiv_tbl, 0);
 	clks[CLPS711X_CLK_TIMER2] = clk_divider_table("timer2", "timer_ref", 0,
-		IOMEM(SYSCON1), 7, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl));
+		IOMEM(SYSCON1), 7, 1, tdiv_tbl, 0);
 
-	clkdev_add_physbase(clks[CLPS711X_CLK_UART], UARTDR1, NULL);
-	clkdev_add_physbase(clks[CLPS711X_CLK_UART], UARTDR2, NULL);
-	clkdev_add_physbase(clks[CLPS711X_CLK_TIMER2], TC2D, NULL);
+	clk_data.clks = clks;
+	clk_data.clk_num = CLPS711X_CLK_MAX;
+	of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, &clk_data);
 
 	return 0;
 }
-postcore_initcall(clps711x_clk_init);
 
-static __init int clps711x_core_init(void)
-{
-	add_generic_device("clps711x-cs", DEVICE_ID_SINGLE, NULL,
-			   TC2D, SZ_2, IORESOURCE_MEM, NULL);
+static const struct of_device_id __maybe_unused clps711x_clk_dt_ids[] = {
+	{ .compatible = "cirrus,ep7209-clk", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, clps711x_clk_dt_ids);
 
-	return 0;
-}
-coredevice_initcall(clps711x_core_init);
+static struct driver clps711x_clk_driver = {
+	.probe = clps711x_clk_probe,
+	.name = "clps711x-clk",
+	.of_compatible = DRV_OF_COMPAT(clps711x_clk_dt_ids),
+};
+postcore_platform_driver(clps711x_clk_driver);
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
new file mode 100644
index 0000000000..60db39ad11
--- /dev/null
+++ b/arch/arm/mach-clps711x/common.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru>
+
+#include <common.h>
+#include <driver.h>
+#include <restart.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <mach/clps711x/clps711x.h>
+
+#define CLPS711X_MAP_ADDR	0x90000000
+
+static u32 remap_size = 0;
+
+static void __noreturn clps711x_restart(struct restart_handler *rst)
+{
+	shutdown_barebox();
+
+	asm("mov pc, #0");
+
+	hang();
+}
+
+static __init int is_clps711x_compatible(void)
+{
+	return of_machine_is_compatible("cirrus,ep7209");
+}
+
+static __init int clps711x_init(void)
+{
+	char *serial;
+
+	if (!is_clps711x_compatible())
+		return 0;
+
+	restart_handler_register_fn("vector", clps711x_restart);
+
+	serial = basprintf("%08x%08x", 0, readl(UNIQID));
+
+	barebox_set_serial_number(serial);
+
+	free(serial);
+
+	return 0;
+}
+postcore_initcall(clps711x_init);
+
+static int __init clps711x_bus_map(void)
+{
+	if (is_clps711x_compatible() && remap_size)
+		map_io_sections(0, (void *)CLPS711X_MAP_ADDR, remap_size);
+
+	return 0;
+}
+postmmu_initcall(clps711x_bus_map);
+
+/* Scan for devices that start at zero address and maps them
+ * to a different unused address.
+ * To start the kernel, a fixup is used that rewrites the address
+ * of the patched device to its original state.
+ */
+
+static void clps711x_bus_patch(struct device_node *node,
+			       u32 compare, u32 change)
+{
+	const __be32 *ranges;
+	int rsize;
+
+	ranges = of_get_property(node, "ranges", &rsize);
+
+	if (ranges) {
+		int banks = rsize / (sizeof(u32) * 4);
+		__be32 *fixed, *fixedptr;
+
+		fixed = xmalloc(rsize);
+		fixedptr = fixed;
+
+		while (banks--) {
+			u32 bank, cell, addr, size;
+
+			bank = be32_to_cpu(*ranges++);
+			cell = be32_to_cpu(*ranges++);
+			addr = be32_to_cpu(*ranges++);
+			size = be32_to_cpu(*ranges++);
+
+			if (addr == compare) {
+				addr = change;
+				remap_size = size;
+			}
+
+			*fixedptr++ = cpu_to_be32(bank);
+			*fixedptr++ = cpu_to_be32(cell);
+			*fixedptr++ = cpu_to_be32(addr);
+			*fixedptr++ = cpu_to_be32(size);
+		}
+
+		of_set_property(node, "ranges", fixed, rsize, 0);
+
+		free(fixed);
+	}
+}
+
+static int clps711x_bus_fixup(struct device_node *root, void *context)
+{
+	struct device_node *node = context;
+
+	if (remap_size)
+		clps711x_bus_patch(node, CLPS711X_MAP_ADDR, 0);
+
+	return 0;
+}
+
+static int clps711x_bus_probe(struct device *dev)
+{
+	u32 mcfg;
+
+	/* Setup bus timings */
+	if (!of_property_read_u32(dev->of_node,
+				  "barebox,ep7209-memcfg1", &mcfg))
+		writel(mcfg, MEMCFG1);
+	if (!of_property_read_u32(dev->of_node,
+				  "barebox,ep7209-memcfg2", &mcfg))
+		writel(mcfg, MEMCFG2);
+
+	clps711x_bus_patch(dev->of_node, 0, CLPS711X_MAP_ADDR);
+
+	of_platform_populate(dev->of_node, NULL, dev);
+
+	of_register_fixup(clps711x_bus_fixup, dev->of_node);
+
+	return 0;
+}
+
+static const struct of_device_id __maybe_unused clps711x_bus_dt_ids[] = {
+	{ .compatible = "cirrus,ep7209-bus", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, clps711x_bus_dt_ids);
+
+static struct driver clps711x_bus_driver = {
+	.name = "clps711x-bus",
+	.probe = clps711x_bus_probe,
+	.of_compatible = DRV_OF_COMPAT(clps711x_bus_dt_ids),
+};
+
+static int __init clps711x_bus_init(void)
+{
+	return platform_driver_register(&clps711x_bus_driver);
+}
+core_initcall(clps711x_bus_init);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
deleted file mode 100644
index 8eacc70018..0000000000
--- a/arch/arm/mach-clps711x/devices.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
-
-#include <common.h>
-#include <init.h>
-#include <linux/sizes.h>
-
-#include <asm/io.h>
-#include <asm/memory.h>
-
-#include <mach/clps711x.h>
-#include <mach/devices.h>
-
-static int clps711x_mem_init(void)
-{
-	ulong memsize = get_ram_size((ulong *)SDRAM0_BASE, SZ_64M);
-
-	arm_add_mem_device("ram0", SDRAM0_BASE, memsize);
-
-	return 0;
-}
-mem_initcall(clps711x_mem_init);
-
-inline static void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
-{
-	u32 tmp = readl(addr);
-
-	tmp &= ~(0xff << (bank * 8));
-	tmp |= val << (bank * 8);
-
-	writel(tmp, addr);
-}
-
-void clps711x_setup_memcfg(int bank, u32 val)
-{
-	switch (bank) {
-	case 0 ... 3:
-		_clps711x_setup_memcfg(bank, MEMCFG1, val);
-		break;
-	case 4 ... 5:
-		_clps711x_setup_memcfg(bank - 4, MEMCFG2, val);
-		break;
-	}
-}
-
-static struct resource uart0_resources[] = {
-	DEFINE_RES_MEM(UARTDR1, SZ_128),
-};
-
-static struct resource uart1_resources[] = {
-	DEFINE_RES_MEM(UARTDR2, SZ_128),
-};
-
-void clps711x_add_uart(unsigned int id)
-{
-	switch (id) {
-	case 0:
-		add_generic_device_res("clps711x-uart", 0, uart0_resources,
-				       ARRAY_SIZE(uart0_resources), NULL);
-		break;
-	case 1:
-		add_generic_device_res("clps711x-uart", 1, uart1_resources,
-				       ARRAY_SIZE(uart1_resources), NULL);
-		break;
-	}
-}
-
-static struct resource gpio0_resources[] = {
-	DEFINE_RES_MEM(PADR, SZ_1),
-	DEFINE_RES_MEM(PADDR, SZ_1),
-};
-
-static struct resource gpio1_resources[] = {
-	DEFINE_RES_MEM(PBDR, SZ_1),
-	DEFINE_RES_MEM(PBDDR, SZ_1),
-};
-
-static struct resource gpio2_resources[] = {
-	DEFINE_RES_MEM(PCDR, SZ_1),
-	DEFINE_RES_MEM(PCDDR, SZ_1),
-};
-
-static struct resource gpio3_resources[] = {
-	DEFINE_RES_MEM(PDDR, SZ_1),
-	DEFINE_RES_MEM(PDDDR, SZ_1),
-};
-
-static struct resource gpio4_resources[] = {
-	DEFINE_RES_MEM(PEDR, SZ_1),
-	DEFINE_RES_MEM(PEDDR, SZ_1),
-};
-
-static __init int clps711x_gpio_init(void)
-{
-	add_generic_device_res("clps711x-gpio", 0, gpio0_resources,
-			       ARRAY_SIZE(gpio0_resources), NULL);
-	add_generic_device_res("clps711x-gpio", 1, gpio1_resources,
-			       ARRAY_SIZE(gpio1_resources), NULL);
-	add_generic_device_res("clps711x-gpio", 2, gpio2_resources,
-			       ARRAY_SIZE(gpio2_resources), NULL);
-	add_generic_device_res("clps711x-gpio", 3, gpio3_resources,
-			       ARRAY_SIZE(gpio3_resources), NULL);
-	add_generic_device_res("clps711x-gpio", 4, gpio4_resources,
-			       ARRAY_SIZE(gpio4_resources), NULL);
-
-	return 0;
-}
-coredevice_initcall(clps711x_gpio_init);
-
-static __init int clps711x_syscon_init(void)
-{
-	/* SYSCON1, SYSFLG1 */
-	add_generic_device("syscon", 1, NULL, SYSCON1, SZ_128,
-			   IORESOURCE_MEM, NULL);
-	/* SYSCON2, SYSFLG2 */
-	add_generic_device("syscon", 2, NULL, SYSCON2, SZ_128,
-			   IORESOURCE_MEM, NULL);
-
-	return 0;
-}
-postcore_initcall(clps711x_syscon_init);
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
deleted file mode 100644
index 957b2b8477..0000000000
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- *  Hardware definitions for Cirrus Logic CLPS711X
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __MACH_CLPS711X_H
-#define __MACH_CLPS711X_H
-
-#define CS0_BASE		(0x00000000)
-#define CS1_BASE		(0x10000000)
-#define CS2_BASE		(0x20000000)
-#define CS3_BASE		(0x30000000)
-#define CS4_BASE		(0x40000000)
-#define CS5_BASE		(0x50000000)
-#define CS6_BASE		(0x60000000)
-#define CS7_BASE		(0x70000000)
-#define REGS_BASE		(0x80000000)
-#define SDRAM0_BASE		(0xc0000000)
-#define SDRAM1_BASE		(0xd0000000)
-
-#define PADR			(REGS_BASE + 0x0000)
-#define PBDR			(REGS_BASE + 0x0001)
-#define PCDR			(REGS_BASE + 0x0002)
-#define PDDR			(REGS_BASE + 0x0003)
-#define PADDR			(REGS_BASE + 0x0040)
-#define PBDDR			(REGS_BASE + 0x0041)
-#define PCDDR			(REGS_BASE + 0x0042)
-#define PDDDR			(REGS_BASE + 0x0043)
-#define PEDR			(REGS_BASE + 0x0083)
-#define PEDDR			(REGS_BASE + 0x00c3)
-#define SYSCON1			(REGS_BASE + 0x0100)
-#define SYSFLG1			(REGS_BASE + 0x0140)
-#define MEMCFG1			(REGS_BASE + 0x0180)
-#define MEMCFG2			(REGS_BASE + 0x01c0)
-#define DRFPR			(REGS_BASE + 0x0200)
-#define INTSR1			(REGS_BASE + 0x0240)
-#define INTMR1			(REGS_BASE + 0x0280)
-#define LCDCON			(REGS_BASE + 0x02c0)
-#define TC1D			(REGS_BASE + 0x0300)
-#define TC2D			(REGS_BASE + 0x0340)
-#define RTCDR			(REGS_BASE + 0x0380)
-#define RTCMR			(REGS_BASE + 0x03c0)
-#define PMPCON			(REGS_BASE + 0x0400)
-#define CODR			(REGS_BASE + 0x0440)
-#define UARTDR1			(REGS_BASE + 0x0480)
-#define UBRLCR1			(REGS_BASE + 0x04c0)
-#define SYNCIO			(REGS_BASE + 0x0500)
-#define PALLSW			(REGS_BASE + 0x0540)
-#define PALMSW			(REGS_BASE + 0x0580)
-#define STFCLR			(REGS_BASE + 0x05c0)
-#define BLEOI			(REGS_BASE + 0x0600)
-#define MCEOI			(REGS_BASE + 0x0640)
-#define TEOI			(REGS_BASE + 0x0680)
-#define TC1EOI			(REGS_BASE + 0x06c0)
-#define TC2EOI			(REGS_BASE + 0x0700)
-#define RTCEOI			(REGS_BASE + 0x0740)
-#define UMSEOI			(REGS_BASE + 0x0780)
-#define COEOI			(REGS_BASE + 0x07c0)
-#define HALT			(REGS_BASE + 0x0800)
-#define STDBY			(REGS_BASE + 0x0840)
-
-#define FBADDR			(REGS_BASE + 0x1000)
-#define SYSCON2			(REGS_BASE + 0x1100)
-#define SYSFLG2			(REGS_BASE + 0x1140)
-#define INTSR2			(REGS_BASE + 0x1240)
-#define INTMR2			(REGS_BASE + 0x1280)
-#define UARTDR2			(REGS_BASE + 0x1480)
-#define UBRLCR2			(REGS_BASE + 0x14c0)
-#define SS2DR			(REGS_BASE + 0x1500)
-#define SRXEOF			(REGS_BASE + 0x1600)
-#define SS2POP			(REGS_BASE + 0x16c0)
-#define KBDEOI			(REGS_BASE + 0x1700)
-
-#define DAIR			(REGS_BASE + 0x2000)
-#define DAIDR0			(REGS_BASE + 0x2040)
-#define DAIDR1			(REGS_BASE + 0x2080)
-#define DAIDR2			(REGS_BASE + 0x20c0)
-#define DAISR			(REGS_BASE + 0x2100)
-#define SYSCON3			(REGS_BASE + 0x2200)
-#define INTSR3			(REGS_BASE + 0x2240)
-#define INTMR3			(REGS_BASE + 0x2280)
-#define LEDFLSH			(REGS_BASE + 0x22c0)
-#define SDCONF			(REGS_BASE + 0x2300)
-#define SDRFPR			(REGS_BASE + 0x2340)
-#define UNIQID			(REGS_BASE + 0x2440)
-#define DAI64FS			(REGS_BASE + 0x2600)
-#define PLLW			(REGS_BASE + 0x2610)
-#define PLLR			(REGS_BASE + 0xa5a8)
-#define RANDID0			(REGS_BASE + 0x2700)
-#define RANDID1			(REGS_BASE + 0x2704)
-#define RANDID2			(REGS_BASE + 0x2708)
-#define RANDID3			(REGS_BASE + 0x270c)
-
-#define SYSCON1_KBDSCAN(x)	((x) & 15)
-#define SYSCON1_KBDSCANMASK	(15)
-#define SYSCON1_TC1M		(1 << 4)
-#define SYSCON1_TC1S		(1 << 5)
-#define SYSCON1_TC2M		(1 << 6)
-#define SYSCON1_TC2S		(1 << 7)
-#define SYSCON1_BZTOG		(1 << 9)
-#define SYSCON1_BZMOD		(1 << 10)
-#define SYSCON1_DBGEN		(1 << 11)
-#define SYSCON1_LCDEN		(1 << 12)
-#define SYSCON1_CDENTX		(1 << 13)
-#define SYSCON1_CDENRX		(1 << 14)
-#define SYSCON1_SIREN		(1 << 15)
-#define SYSCON1_ADCKSEL(x)	(((x) & 3) << 16)
-#define SYSCON1_ADCKSEL_MASK	(3 << 16)
-#define SYSCON1_EXCKEN		(1 << 18)
-#define SYSCON1_WAKEDIS		(1 << 19)
-#define SYSCON1_IRTXM		(1 << 20)
-
-#define SYSFLG1_MCDR		(1 << 0)
-#define SYSFLG1_DCDET		(1 << 1)
-#define SYSFLG1_WUDR		(1 << 2)
-#define SYSFLG1_WUON		(1 << 3)
-#define SYSFLG1_CTS		(1 << 8)
-#define SYSFLG1_DSR		(1 << 9)
-#define SYSFLG1_DCD		(1 << 10)
-#define SYSFLG1_NBFLG		(1 << 12)
-#define SYSFLG1_RSTFLG		(1 << 13)
-#define SYSFLG1_PFFLG		(1 << 14)
-#define SYSFLG1_CLDFLG		(1 << 15)
-#define SYSFLG1_CRXFE		(1 << 24)
-#define SYSFLG1_CTXFF		(1 << 25)
-#define SYSFLG1_SSIBUSY		(1 << 26)
-#define SYSFLG1_ID		(1 << 29)
-#define SYSFLG1_VERID(x)	(((x) >> 30) & 3)
-#define SYSFLG1_VERID_MASK	(3 << 30)
-
-#define SYSFLG2_SSRXOF		(1 << 0)
-#define SYSFLG2_RESVAL		(1 << 1)
-#define SYSFLG2_RESFRM		(1 << 2)
-#define SYSFLG2_SS2RXFE		(1 << 3)
-#define SYSFLG2_SS2TXFF		(1 << 4)
-#define SYSFLG2_SS2TXUF		(1 << 5)
-#define SYSFLG2_CKMODE		(1 << 6)
-
-#define LCDCON_GSEN		(1 << 30)
-#define LCDCON_GSMD		(1 << 31)
-
-#define SYSCON2_SERSEL		(1 << 0)
-#define SYSCON2_KBD6		(1 << 1)
-#define SYSCON2_DRAMZ		(1 << 2)
-#define SYSCON2_KBWEN		(1 << 3)
-#define SYSCON2_SS2TXEN		(1 << 4)
-#define SYSCON2_PCCARD1		(1 << 5)
-#define SYSCON2_PCCARD2		(1 << 6)
-#define SYSCON2_SS2RXEN		(1 << 7)
-#define SYSCON2_SS2MAEN		(1 << 9)
-#define SYSCON2_OSTB		(1 << 12)
-#define SYSCON2_CLKENSL		(1 << 13)
-#define SYSCON2_BUZFREQ		(1 << 14)
-
-#define SYNCIO_FRMLEN(x)	(((x) & 0x1f) << 8)
-#define SYNCIO_SMCKEN		(1 << 13)
-#define SYNCIO_TXFRMEN		(1 << 14)
-
-#define DAIR_RESERVED		(0x0404)
-#define DAIR_DAIEN		(1 << 16)
-#define DAIR_ECS		(1 << 17)
-#define DAIR_LCTM		(1 << 19)
-#define DAIR_LCRM		(1 << 20)
-#define DAIR_RCTM		(1 << 21)
-#define DAIR_RCRM		(1 << 22)
-#define DAIR_LBM		(1 << 23)
-
-#define DAIDR2_FIFOEN		(1 << 15)
-#define DAIDR2_FIFOLEFT		(0x0d << 16)
-#define DAIDR2_FIFORIGHT	(0x11 << 16)
-
-#define DAISR_RCTS		(1 << 0)
-#define DAISR_RCRS		(1 << 1)
-#define DAISR_LCTS		(1 << 2)
-#define DAISR_LCRS		(1 << 3)
-#define DAISR_RCTU		(1 << 4)
-#define DAISR_RCRO		(1 << 5)
-#define DAISR_LCTU		(1 << 6)
-#define DAISR_LCRO		(1 << 7)
-#define DAISR_RCNF		(1 << 8)
-#define DAISR_RCNE		(1 << 9)
-#define DAISR_LCNF		(1 << 10)
-#define DAISR_LCNE		(1 << 11)
-#define DAISR_FIFO		(1 << 12)
-
-#define DAI64FS_I2SF64		(1 << 0)
-#define DAI64FS_AUDIOCLKEN	(1 << 1)
-#define DAI64FS_AUDIOCLKSRC	(1 << 2)
-#define DAI64FS_MCLK256EN	(1 << 3)
-#define DAI64FS_LOOPBACK	(1 << 5)
-#define DAI64FS_AUDIV_MASK	(0x7f)
-#define DAI64FS_AUDIV(x)	(((x) & DAI64FS_AUDIV_MASK) << 8)
-
-#define SYSCON3_ADCCON		(1 << 0)
-#define SYSCON3_CLKCTL0		(1 << 1)
-#define SYSCON3_CLKCTL1		(1 << 2)
-#define SYSCON3_DAISEL		(1 << 3)
-#define SYSCON3_ADCCKNSEN	(1 << 4)
-#define SYSCON3_VERSN(x)	(((x) >> 5) & 7)
-#define SYSCON3_VERSN_MASK	(7 << 5)
-#define SYSCON3_FASTWAKE	(1 << 8)
-#define SYSCON3_DAIEN		(1 << 9)
-#define SYSCON3_128FS		SYSCON3_DAIEN
-#define SYSCON3_ENPD67		(1 << 10)
-
-#define SDCONF_ACTIVE		(1 << 10)
-#define SDCONF_CLKCTL		(1 << 9)
-#define SDCONF_WIDTH_4		(0 << 7)
-#define SDCONF_WIDTH_8		(1 << 7)
-#define SDCONF_WIDTH_16		(2 << 7)
-#define SDCONF_WIDTH_32		(3 << 7)
-#define SDCONF_SIZE_16		(0 << 5)
-#define SDCONF_SIZE_64		(1 << 5)
-#define SDCONF_SIZE_128		(2 << 5)
-#define SDCONF_SIZE_256		(3 << 5)
-#define SDCONF_CASLAT_2		(2)
-#define SDCONF_CASLAT_3		(3)
-
-#define MEMCFG_BUS_WIDTH_32	(1)
-#define MEMCFG_BUS_WIDTH_16	(0)
-#define MEMCFG_BUS_WIDTH_8	(3)
-
-#define MEMCFG_SQAEN		(1 << 6)
-#define MEMCFG_CLKENB		(1 << 7)
-
-#define MEMCFG_WAITSTATE_8_3	(0 << 2)
-#define MEMCFG_WAITSTATE_7_3	(1 << 2)
-#define MEMCFG_WAITSTATE_6_3	(2 << 2)
-#define MEMCFG_WAITSTATE_5_3	(3 << 2)
-#define MEMCFG_WAITSTATE_4_2	(4 << 2)
-#define MEMCFG_WAITSTATE_3_2	(5 << 2)
-#define MEMCFG_WAITSTATE_2_2	(6 << 2)
-#define MEMCFG_WAITSTATE_1_2	(7 << 2)
-#define MEMCFG_WAITSTATE_8_1	(8 << 2)
-#define MEMCFG_WAITSTATE_7_1	(9 << 2)
-#define MEMCFG_WAITSTATE_6_1	(10 << 2)
-#define MEMCFG_WAITSTATE_5_1	(11 << 2)
-#define MEMCFG_WAITSTATE_4_0	(12 << 2)
-#define MEMCFG_WAITSTATE_3_0	(13 << 2)
-#define MEMCFG_WAITSTATE_2_0	(14 << 2)
-#define MEMCFG_WAITSTATE_1_0	(15 << 2)
-
-void clps711x_barebox_entry(u32, void *);
-
-#endif
diff --git a/arch/arm/mach-clps711x/include/mach/devices.h b/arch/arm/mach-clps711x/include/mach/devices.h
deleted file mode 100644
index 18a251a1d9..0000000000
--- a/arch/arm/mach-clps711x/include/mach/devices.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_DEVICES_H
-#define __MACH_DEVICES_H
-
-void clps711x_setup_memcfg(int bank, u32 val);
-void clps711x_add_uart(unsigned int id);
-
-#endif
diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
index 35b8b35e87..2ede50538a 100644
--- a/arch/arm/mach-clps711x/lowlevel.c
+++ b/arch/arm/mach-clps711x/lowlevel.c
@@ -1,25 +1,31 @@
-/*
- * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru>
 
+#include <asm/io.h>
+#include <asm/barebox-arm.h>
 #include <common.h>
-#include <init.h>
+#include <debug_ll.h>
 #include <linux/sizes.h>
+#include <mach/clps711x/clps711x.h>
 
-#include <asm/io.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
+#define DEBUG_LL_BAUDRATE	(57600)
+
+static inline void setup_uart(const u32 bus_speed)
+{
+	u32 baud_base = DIV_ROUND_CLOSEST(bus_speed, 10);
+	u32 baud_divisor =
+		DIV_ROUND_CLOSEST(baud_base, DEBUG_LL_BAUDRATE * 16) - 1;
+
+	writel(baud_divisor | UBRLCR_FIFOEN | UBRLCR_WRDLEN8, UBRLCR1);
+	writel(0, STFCLR);
+	writel(SYSCON_UARTEN, SYSCON1);
 
-#include <mach/clps711x.h>
+	putc_ll('>');
+}
 
-void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data)
+void clps711x_start(void *fdt)
 {
-	u32 cpu, bus;
+	u32 bus, pll;
 
 	/* Check if we running from external 13 MHz clock */
 	if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) {
@@ -27,24 +33,17 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data)
 		writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
 		asm("nop");
 
-		/* Check valid multiplier, default to 74 MHz */
-		if ((pllmult < 20) || (pllmult > 50))
-			pllmult = 40;
-
-		/* Setup PLL */
-		writel(pllmult << 24, PLLW);
-		asm("nop");
+		if (IS_ENABLED(CONFIG_CLPS711X_RAISE_CPUFREQ)) {
+			/* Setup PLL to 92160000 Hz */
+			writel(50 << 24, PLLW);
+			asm("nop");
+		}
 
-		/* Check for old CPUs without PLL */
-		if ((readl(PLLR) >> 24) != pllmult)
-			cpu = 73728000;
+		pll = readl(PLLR) >> 24;
+		if (pll)
+			bus = (pll * 3686400) / 4;
 		else
-			cpu = pllmult * 3686400;
-
-		if (cpu >= 36864000)
-			bus = cpu / 2;
-		else
-			bus = 36864000 / 2;
+			bus = 73728000 / 4;
 	} else {
 		bus = 13000000;
 		/* Setup bus wait state scaling factor to 1  */
@@ -52,6 +51,13 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data)
 		asm("nop");
 	}
 
+
+	/* Disable UART, IrDa, LCD */
+	writel(0, SYSCON1);
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart(bus);
+
 	/* CLKEN select, SDRAM width=32 */
 	writel(SYSCON2_CLKENSL, SYSCON2);
 
@@ -62,12 +68,10 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data)
 	/* Setup Refresh Rate (64ms 8K Blocks) */
 	writel((64 * bus) / (8192 * 1000), SDRFPR);
 
-	/* Disable UART, IrDa, LCD */
-	writel(0, SYSCON1);
 	/* Disable PWM */
 	writew(0, PMPCON);
 	/* Disable LED flasher */
 	writew(0, LEDFLSH);
 
-	barebox_arm_entry(SDRAM0_BASE, SZ_8M, data);
+	barebox_arm_entry(SDRAM0_BASE, SZ_8M, fdt);
 }
diff --git a/arch/arm/mach-clps711x/reset.c b/arch/arm/mach-clps711x/reset.c
deleted file mode 100644
index 90ddb8f5d2..0000000000
--- a/arch/arm/mach-clps711x/reset.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
-
-#include <common.h>
-#include <init.h>
-#include <restart.h>
-
-static void __noreturn clps711x_restart_soc(struct restart_handler *rst)
-{
-	shutdown_barebox();
-
-	asm("mov pc, #0");
-
-	hang();
-}
-
-static int restart_register_feature(void)
-{
-	restart_handler_register_fn("vector", clps711x_restart_soc);
-
-	return 0;
-}
-coredevice_initcall(restart_register_feature);
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index c6d4fce603..a87b6256ce 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_DAVINCI
 
 config ARCH_TEXT_BASE
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index b96d4146f6..f7865a941b 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += time.o
diff --git a/arch/arm/mach-davinci/include/mach/debug_ll.h b/arch/arm/mach-davinci/include/mach/debug_ll.h
deleted file mode 100644
index 60a8d2a5f1..0000000000
--- a/arch/arm/mach-davinci/include/mach/debug_ll.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> */
-
-/** @file
- *  This File contains declaration for early output support
- */
-#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
-#define __INCLUDE_ARCH_DEBUG_LL_H__
-
-#include <asm/io.h>
-#include <mach/serial.h>
-
-#define DEBUG_LL_UART_ADDR	DAVINCI_UART0_BASE
-#define DEBUG_LL_UART_RSHFT	2
-
-#define rbr		(0 << DEBUG_LL_UART_RSHFT)
-#define lsr		(5 << DEBUG_LL_UART_RSHFT)
-#define LSR_THRE	0x20	/* Xmit holding register empty */
-
-static inline void PUTC_LL(char ch)
-{
-	while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE))
-		;
-
-	__raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
-}
-
-#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
deleted file mode 100644
index 8ab824800e..0000000000
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* SPDX-FileCopyrightText: 2007 Deep Root Systems, LLC. */
-
-/*
- * Hardware definitions common to all DaVinci family processors
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/memory.h>
-
-/*
- * Before you add anything to this file:
- *
- * This header is for defines common to ALL DaVinci family chips.
- * Anything that is chip specific should go in <chipname>.h,
- * and the chip/board init code should then explicitly include
- * <chipname>.h
- */
-/*
- * I/O mapping
- */
-#define IO_PHYS				UL(0x01c00000)
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
deleted file mode 100644
index 03e8ef43dd..0000000000
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* SPDX-FileCopyrightText: 2007 MontaVista Software, Inc. */
-
-/*
- * DaVinci serial device definitions
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-#include <mach/hardware.h>
-
-#define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
-#define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
-#define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
-
-#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
deleted file mode 100644
index 6456205859..0000000000
--- a/arch/arm/mach-davinci/include/mach/time.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* SPDX-FileCopyrightText: 2007 MontaVista Software, Inc. */
-
-/*
- * Local header file for DaVinci time code.
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- */
-#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
-#define __ARCH_ARM_MACH_DAVINCI_TIME_H
-
-#include <mach/hardware.h>
-
-#define DAVINCI_TIMER0_BASE		(IO_PHYS + 0x21400)
-#define DAVINCI_TIMER1_BASE		(IO_PHYS + 0x21800)
-#define DAVINCI_WDOG_BASE		(IO_PHYS + 0x21C00)
-
-#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 52b3ac3e68..5456820009 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -13,7 +13,7 @@
 #include <restart.h>
 #include <clock.h>
 
-#include <mach/time.h>
+#include <mach/davinci/time.h>
 
 /* Timer register offsets */
 #define PID12			0x0
@@ -96,6 +96,7 @@ static uint64_t davinci_cs_read(void)
 static struct clocksource davinci_cs = {
 	.read	= davinci_cs_read,
 	.mask	= CLOCKSOURCE_MASK(32),
+	.priority = 80,
 };
 
 static int timer32_config(struct timer_s *t)
diff --git a/arch/arm/mach-digic/Kconfig b/arch/arm/mach-digic/Kconfig
index d25c3b3f51..25b9a0da2f 100644
--- a/arch/arm/mach-digic/Kconfig
+++ b/arch/arm/mach-digic/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_DIGIC
 
 choice
diff --git a/arch/arm/mach-digic/Makefile b/arch/arm/mach-digic/Makefile
index 16a218658a..1c2b374603 100644
--- a/arch/arm/mach-digic/Makefile
+++ b/arch/arm/mach-digic/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj- := __dummy__.o
diff --git a/arch/arm/mach-digic/include/mach/debug_ll.h b/arch/arm/mach-digic/include/mach/debug_ll.h
deleted file mode 100644
index 3b17100dae..0000000000
--- a/arch/arm/mach-digic/include/mach/debug_ll.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2013, 2014 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_DEBUG_LL_H__
-#define __MACH_DEBUG_LL_H__
-
-#include <io.h>
-#include <mach/digic4.h>
-#include <mach/uart.h>
-
-#define DEBUG_LL_UART         DIGIC4_UART
-
-/* Serial interface registers */
-#define DEBUG_LL_UART_TX         (DEBUG_LL_UART + DIGIC_UART_TX)
-#define DEBUG_LL_UART_ST         (DEBUG_LL_UART + DIGIC_UART_ST)
-
-static inline void PUTC_LL(char ch)
-{
-	while (!(readl(DEBUG_LL_UART_ST) & DIGIC_UART_ST_TX_RDY))
-		; /* noop */
-
-	writel(0x06, DEBUG_LL_UART_ST);
-	writel(ch, DEBUG_LL_UART_TX);
-}
-
-#endif /* __MACH_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-digic/include/mach/digic4.h b/arch/arm/mach-digic/include/mach/digic4.h
deleted file mode 100644
index 54a897f828..0000000000
--- a/arch/arm/mach-digic/include/mach/digic4.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __DIGIC4_H__
-#define __DIGIC4_H__
-
-#define DIGIC4_UART	0xc0800000
-
-#endif /* __DIGIC4_H__ */
diff --git a/arch/arm/mach-digic/include/mach/uart.h b/arch/arm/mach-digic/include/mach/uart.h
deleted file mode 100644
index 481c3c62c7..0000000000
--- a/arch/arm/mach-digic/include/mach/uart.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __DIGIC_UART_H__
-#define __DIGIC_UART_H__
-
-/* Serial interface registers offsets */
-#define DIGIC_UART_TX	0x0
-#define DIGIC_UART_RX	0x4
-#define DIGIC_UART_ST	0x14
-# define DIGIC_UART_ST_RX_RDY	1
-# define DIGIC_UART_ST_TX_RDY	2
-
-#endif /* __DIGIC_UART_H__ */
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index f805a8fd52..e39f1d8a9b 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_EP93XX
 
 config EP93XX_SDCE0_PHYS_OFFSET
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index fc0cb1afcd..80dbe7c42b 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += clocksource.o gpio.o header.o
 
 lwl-y += lowlevel_init.o led.o
diff --git a/arch/arm/mach-ep93xx/clocksource.c b/arch/arm/mach-ep93xx/clocksource.c
index 1f3ff7f8f2..53aae437b3 100644
--- a/arch/arm/mach-ep93xx/clocksource.c
+++ b/arch/arm/mach-ep93xx/clocksource.c
@@ -18,7 +18,7 @@
 #include <clock.h>
 #include <io.h>
 #include <restart.h>
-#include <mach/ep93xx-regs.h>
+#include <mach/ep93xx/ep93xx-regs.h>
 
 #define TIMER_CLKSEL		(1 << 3)
 #define TIMER_MODE		(1 << 6)
@@ -37,6 +37,7 @@ static struct clocksource cs = {
 	.read	= ep93xx_clocksource_read,
 	.mask	= CLOCKSOURCE_MASK(32),
 	.shift	= 10,
+	.priority = 80,
 };
 
 static int clocksource_init(void)
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 20477f83e6..f30798fd4b 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -19,7 +19,7 @@
 #include <init.h>
 #include <io.h>
 #include <gpio.h>
-#include <mach/ep93xx-regs.h>
+#include <mach/ep93xx/ep93xx-regs.h>
 
 #define EP93XX_GPIO_NUM_PORTS	8
 #define EP93XX_GPIO_NUM_GPIOS	(EP93XX_GPIO_NUM_PORTS * 8)
diff --git a/arch/arm/mach-ep93xx/header.c b/arch/arm/mach-ep93xx/header.c
index a9dde2d8b0..0d7e68c34b 100644
--- a/arch/arm/mach-ep93xx/header.c
+++ b/arch/arm/mach-ep93xx/header.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <linux/compiler.h>
 #include <asm/barebox-arm-head.h>
diff --git a/arch/arm/mach-ep93xx/include/mach/barebox.lds.h b/arch/arm/mach-ep93xx/include/mach/barebox.lds.h
deleted file mode 100644
index 74c4662a57..0000000000
--- a/arch/arm/mach-ep93xx/include/mach/barebox.lds.h
+++ /dev/null
@@ -1,9 +0,0 @@
-
-/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
-
-#define PRE_IMAGE				\
-	.pre_image : {				\
-		KEEP(*(.flash_header_start*))	\
-		. = 0x1000;			\
-		LONG(0x53555243) /* 'CRUS' */	\
-	}
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
deleted file mode 100644
index f1d3076045..0000000000
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/* -----------------------------------------------------------------------------
- * Cirrus Logic EP93xx register definitions.
- *
- * Copyright (C) 2009
- * Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * Copyright (C) 2006
- * Dominic Rath <Dominic.Rath@gmx.de>
- *
- * Copyright (C) 2004, 2005
- * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
- *
- * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
- *
- * Copyright (C) 2004 Ray Lehtiniemi
- * Copyright (C) 2003 Cirrus Logic, Inc
- * Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.	 See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
-
-#define EP93XX_AHB_BASE			0x80000000
-#define EP93XX_APB_BASE			0x80800000
-
-/* -----------------------------------------------------------------------------
- * 0x80000000 - 0x8000FFFF: DMA
- */
-#define DMA_OFFSET			0x000000
-#define DMA_BASE			(EP93XX_AHB_BASE | DMA_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct dma_channel {
-	uint32_t control;
-	uint32_t interrupt;
-	uint32_t ppalloc;
-	uint32_t status;
-	uint32_t reserved0;
-	uint32_t remain;
-	uint32_t reserved1[2];
-	uint32_t maxcnt0;
-	uint32_t base0;
-	uint32_t current0;
-	uint32_t reserved2;
-	uint32_t maxcnt1;
-	uint32_t base1;
-	uint32_t current1;
-	uint32_t reserved3;
-};
-
-struct dma_regs {
-	struct dma_channel m2p_channel_0;
-	struct dma_channel m2p_channel_1;
-	struct dma_channel m2p_channel_2;
-	struct dma_channel m2p_channel_3;
-	struct dma_channel m2m_channel_0;
-	struct dma_channel m2m_channel_1;
-	struct dma_channel reserved0[2];
-	struct dma_channel m2p_channel_5;
-	struct dma_channel m2p_channel_4;
-	struct dma_channel m2p_channel_7;
-	struct dma_channel m2p_channel_6;
-	struct dma_channel m2p_channel_9;
-	struct dma_channel m2p_channel_8;
-	uint32_t channel_arbitration;
-	uint32_t reserved[15];
-	uint32_t global_interrupt;
-};
-#endif
-
-/* -----------------------------------------------------------------------------
- * 0x80010000 - 0x8001FFFF: Ethernet MAC
- */
-#define MAC_OFFSET			0x010000
-#define MAC_BASE			(EP93XX_AHB_BASE | MAC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct mac_queue {
-	uint32_t badd;
-	union { /* deal with half-word aligned registers */
-		uint32_t blen;
-		union {
-			uint16_t filler;
-			uint16_t curlen;
-		};
-	};
-	uint32_t curadd;
-};
-
-struct mac_regs {
-	uint32_t rxctl;
-	uint32_t txctl;
-	uint32_t testctl;
-	uint32_t reserved0;
-	uint32_t miicmd;
-	uint32_t miidata;
-	uint32_t miists;
-	uint32_t reserved1;
-	uint32_t selfctl;
-	uint32_t inten;
-	uint32_t intstsp;
-	uint32_t intstsc;
-	uint32_t reserved2[2];
-	uint32_t diagad;
-	uint32_t diagdata;
-	uint32_t gt;
-	uint32_t fct;
-	uint32_t fcf;
-	uint32_t afp;
-	union {
-		struct {
-			uint32_t indad;
-			uint32_t indad_upper;
-		};
-		uint32_t hashtbl;
-	};
-	uint32_t reserved3[2];
-	uint32_t giintsts;
-	uint32_t giintmsk;
-	uint32_t giintrosts;
-	uint32_t giintfrc;
-	uint32_t txcollcnt;
-	uint32_t rxmissnct;
-	uint32_t rxruntcnt;
-	uint32_t reserved4;
-	uint32_t bmctl;
-	uint32_t bmsts;
-	uint32_t rxbca;
-	uint32_t reserved5;
-	struct mac_queue rxdq;
-	uint32_t rxdqenq;
-	struct mac_queue rxstsq;
-	uint32_t rxstsqenq;
-	struct mac_queue txdq;
-	uint32_t txdqenq;
-	struct mac_queue txstsq;
-	uint32_t reserved6;
-	uint32_t rxbufthrshld;
-	uint32_t txbufthrshld;
-	uint32_t rxststhrshld;
-	uint32_t txststhrshld;
-	uint32_t rxdthrshld;
-	uint32_t txdthrshld;
-	uint32_t maxfrmlen;
-	uint32_t maxhdrlen;
-};
-#endif
-
-#define SELFCTL_RWP		(1 << 7)
-#define SELFCTL_GPO0		(1 << 5)
-#define SELFCTL_PUWE		(1 << 4)
-#define SELFCTL_PDWE		(1 << 3)
-#define SELFCTL_MIIL		(1 << 2)
-#define SELFCTL_RESET		(1 << 0)
-
-#define INTSTS_RWI		(1 << 30)
-#define INTSTS_RXMI		(1 << 29)
-#define INTSTS_RXBI		(1 << 28)
-#define INTSTS_RXSQI		(1 << 27)
-#define INTSTS_TXLEI		(1 << 26)
-#define INTSTS_ECIE		(1 << 25)
-#define INTSTS_TXUHI		(1 << 24)
-#define INTSTS_MOI		(1 << 18)
-#define INTSTS_TXCOI		(1 << 17)
-#define INTSTS_RXROI		(1 << 16)
-#define INTSTS_MIII		(1 << 12)
-#define INTSTS_PHYI		(1 << 11)
-#define INTSTS_TI		(1 << 10)
-#define INTSTS_AHBE		(1 << 8)
-#define INTSTS_OTHER		(1 << 4)
-#define INTSTS_TXSQ		(1 << 3)
-#define INTSTS_RXSQ		(1 << 2)
-
-#define BMCTL_MT		(1 << 13)
-#define BMCTL_TT		(1 << 12)
-#define BMCTL_UNH		(1 << 11)
-#define BMCTL_TXCHR		(1 << 10)
-#define BMCTL_TXDIS		(1 << 9)
-#define BMCTL_TXEN		(1 << 8)
-#define BMCTL_EH2		(1 << 6)
-#define BMCTL_EH1		(1 << 5)
-#define BMCTL_EEOB		(1 << 4)
-#define BMCTL_RXCHR		(1 << 2)
-#define BMCTL_RXDIS		(1 << 1)
-#define BMCTL_RXEN		(1 << 0)
-
-#define BMSTS_TXACT		(1 << 7)
-#define BMSTS_TP		(1 << 4)
-#define BMSTS_RXACT		(1 << 3)
-#define BMSTS_QID_MASK		0x07
-#define BMSTS_QID_RXDATA	0x00
-#define BMSTS_QID_TXDATA	0x01
-#define BMSTS_QID_RXSTS		0x02
-#define BMSTS_QID_TXSTS		0x03
-#define BMSTS_QID_RXDESC	0x04
-#define BMSTS_QID_TXDESC	0x05
-
-#define AFP_MASK		0x07
-#define AFP_IAPRIMARY		0x00
-#define AFP_IASECONDARY1	0x01
-#define AFP_IASECONDARY2	0x02
-#define AFP_IASECONDARY3	0x03
-#define AFP_TX			0x06
-#define AFP_HASH		0x07
-
-#define RXCTL_PAUSEA		(1 << 20)
-#define RXCTL_RXFCE1		(1 << 19)
-#define RXCTL_RXFCE0		(1 << 18)
-#define RXCTL_BCRC		(1 << 17)
-#define RXCTL_SRXON		(1 << 16)
-#define RXCTL_RCRCA		(1 << 13)
-#define RXCTL_RA		(1 << 12)
-#define RXCTL_PA		(1 << 11)
-#define RXCTL_BA		(1 << 10)
-#define RXCTL_MA		(1 << 9)
-#define RXCTL_IAHA		(1 << 8)
-#define RXCTL_IA3		(1 << 3)
-#define RXCTL_IA2		(1 << 2)
-#define RXCTL_IA1		(1 << 1)
-#define RXCTL_IA0		(1 << 0)
-
-#define TXCTL_DEFDIS		(1 << 7)
-#define TXCTL_MBE		(1 << 6)
-#define TXCTL_ICRC		(1 << 5)
-#define TXCTL_TPD		(1 << 4)
-#define TXCTL_OCOLL		(1 << 3)
-#define TXCTL_SP		(1 << 2)
-#define TXCTL_PB		(1 << 1)
-#define TXCTL_STXON		(1 << 0)
-
-#define MIICMD_REGAD_MASK	(0x001F)
-#define MIICMD_PHYAD_MASK	(0x03E0)
-#define MIICMD_OPCODE_MASK	(0xC000)
-#define MIICMD_PHYAD_8950	(0x0000)
-#define MIICMD_OPCODE_READ	(0x8000)
-#define MIICMD_OPCODE_WRITE	(0x4000)
-
-#define MIISTS_BUSY		(1 << 0)
-
-/* -----------------------------------------------------------------------------
- * 0x80020000 - 0x8002FFFF: USB OHCI
- */
-#define USB_OFFSET			0x020000
-#define USB_BASE			(EP93XX_AHB_BASE | USB_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x80030000 - 0x8003FFFF: Raster engine
- */
-#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
-#define RASTER_OFFSET			0x030000
-#define RASTER_BASE			(EP93XX_AHB_BASE | RASTER_OFFSET)
-#endif
-
-/* -----------------------------------------------------------------------------
- * 0x80040000 - 0x8004FFFF: Graphics accelerator
- */
-#if defined(CONFIG_EP9315)
-#define GFX_OFFSET			0x040000
-#define GFX_BASE			(EP93XX_AHB_BASE | GFX_OFFSET)
-#endif
-
-/* -----------------------------------------------------------------------------
- * 0x80050000 - 0x8005FFFF: Reserved
- */
-
-/* -----------------------------------------------------------------------------
- * 0x80060000 - 0x8006FFFF: SDRAM controller
- */
-#define SDRAM_OFFSET			0x060000
-#define SDRAM_BASE			(EP93XX_AHB_BASE | SDRAM_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct sdram_regs {
-	uint32_t reserved;
-	uint32_t glconfig;
-	uint32_t refrshtimr;
-	uint32_t bootsts;
-	uint32_t devcfg0;
-	uint32_t devcfg1;
-	uint32_t devcfg2;
-	uint32_t devcfg3;
-};
-#endif
-
-#define SDRAM_DEVCFG_EXTBUSWIDTH	(1 << 2)
-#define SDRAM_DEVCFG_BANKCOUNT		(1 << 3)
-#define SDRAM_DEVCFG_SROMLL		(1 << 5)
-#define SDRAM_DEVCFG_CASLAT_2		0x00010000
-#define SDRAM_DEVCFG_RASTOCAS_2		0x00200000
-
-#define GLCONFIG_INIT			(1 << 0)
-#define GLCONFIG_MRS			(1 << 1)
-#define GLCONFIG_SMEMBUSY		(1 << 5)
-#define GLCONFIG_LCR			(1 << 6)
-#define GLCONFIG_REARBEN		(1 << 7)
-#define GLCONFIG_CLKSHUTDOWN		(1 << 30)
-#define GLCONFIG_CKE			(1 << 31)
-
-/* -----------------------------------------------------------------------------
- * 0x80070000 - 0x8007FFFF: Reserved
- */
-
-/* -----------------------------------------------------------------------------
- * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
- */
-#define SMC_OFFSET			0x080000
-#define SMC_BASE			(EP93XX_AHB_BASE | SMC_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct smc_regs {
-	uint32_t bcr0;
-	uint32_t bcr1;
-	uint32_t bcr2;
-	uint32_t bcr3;
-	uint32_t reserved0[2];
-	uint32_t bcr6;
-	uint32_t bcr7;
-#if defined(CONFIG_EP9315)
-	uint32_t pcattribute;
-	uint32_t pccommon;
-	uint32_t pcio;
-	uint32_t reserved1[5];
-	uint32_t pcmciactrl;
-#endif
-};
-#endif
-
-#define SMC_BCR_IDCY_SHIFT	0
-#define SMC_BCR_WST1_SHIFT	5
-#define SMC_BCR_BLE		(1 << 10)
-#define SMC_BCR_WST2_SHIFT	11
-#define SMC_BCR_MW_SHIFT	28
-
-/* -----------------------------------------------------------------------------
- * 0x80090000 - 0x8009FFFF: Boot ROM
- */
-
-/* -----------------------------------------------------------------------------
- * 0x800A0000 - 0x800AFFFF: IDE interface
- */
-
-/* -----------------------------------------------------------------------------
- * 0x800B0000 - 0x800BFFFF: VIC1
- */
-
-/* -----------------------------------------------------------------------------
- * 0x800C0000 - 0x800CFFFF: VIC2
- */
-
-/* -----------------------------------------------------------------------------
- * 0x800D0000 - 0x800FFFFF: Reserved
- */
-
-/* -----------------------------------------------------------------------------
- * 0x80800000 - 0x8080FFFF: Reserved
- */
-
-/* -----------------------------------------------------------------------------
- * 0x80810000 - 0x8081FFFF: Timers
- */
-#define TIMER_OFFSET		0x010000
-#define TIMER_BASE		(EP93XX_APB_BASE | TIMER_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct timer {
-	uint32_t load;
-	uint32_t value;
-	uint32_t control;
-	uint32_t clear;
-};
-
-struct timer4 {
-	uint32_t value_low;
-	uint32_t value_high;
-};
-
-struct timer_regs {
-	struct timer timer1;
-	uint32_t reserved0[4];
-	struct timer timer2;
-	uint32_t reserved1[12];
-	struct timer4 timer4;
-	uint32_t reserved2[6];
-	struct timer timer3;
-};
-#endif
-
-/* -----------------------------------------------------------------------------
- * 0x80820000 - 0x8082FFFF: I2S
- */
-#define I2S_OFFSET		0x020000
-#define I2S_BASE		(EP93XX_APB_BASE | I2S_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x80830000 - 0x8083FFFF: Security
- */
-#define SECURITY_OFFSET		0x030000
-#define SECURITY_BASE		(EP93XX_APB_BASE | SECURITY_OFFSET)
-
-#define EXTENSIONID		(SECURITY_BASE + 0x2714)
-
-/* -----------------------------------------------------------------------------
- * 0x80840000 - 0x8084FFFF: GPIO
- */
-#define GPIO_OFFSET		0x040000
-#define GPIO_BASE		(EP93XX_APB_BASE | GPIO_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct gpio_int {
-	uint32_t inttype1;
-	uint32_t inttype2;
-	uint32_t eoi;
-	uint32_t inten;
-	uint32_t intsts;
-	uint32_t rawintsts;
-	uint32_t db;
-};
-
-struct gpio_regs {
-	uint32_t padr;
-	uint32_t pbdr;
-	uint32_t pcdr;
-	uint32_t pddr;
-	uint32_t paddr;
-	uint32_t pbddr;
-	uint32_t pcddr;
-	uint32_t pdddr;
-	uint32_t pedr;
-	uint32_t peddr;
-	uint32_t reserved0[2];
-	uint32_t pfdr;
-	uint32_t pfddr;
-	uint32_t pgdr;
-	uint32_t pgddr;
-	uint32_t phdr;
-	uint32_t phddr;
-	uint32_t reserved1;
-	uint32_t finttype1;
-	uint32_t finttype2;
-	uint32_t reserved2;
-	struct gpio_int pfint;
-	uint32_t reserved3[10];
-	struct gpio_int paint;
-	struct gpio_int pbint;
-	uint32_t eedrive;
-};
-#endif
-
-/* -----------------------------------------------------------------------------
- * 0x80850000 - 0x8087FFFF: Reserved
- */
-
-/* -----------------------------------------------------------------------------
- * 0x80880000 - 0x8088FFFF: AAC
- */
-#define AAC_OFFSET		0x080000
-#define AAC_BASE		(EP93XX_APB_BASE | AAC_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x80890000 - 0x8089FFFF: Reserved
- */
-
-/* -----------------------------------------------------------------------------
- * 0x808A0000 - 0x808AFFFF: SPI
- */
-#define SPI_OFFSET		0x0A0000
-#define SPI_BASE		(EP93XX_APB_BASE | SPI_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x808B0000 - 0x808BFFFF: IrDA
- */
-#define IRDA_OFFSET		0x0B0000
-#define IRDA_BASE		(EP93XX_APB_BASE | IRDA_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x808C0000 - 0x808CFFFF: UART1
- */
-#define UART1_OFFSET		0x0C0000
-#define UART1_BASE		(EP93XX_APB_BASE | UART1_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x808D0000 - 0x808DFFFF: UART2
- */
-#define UART2_OFFSET		0x0D0000
-#define UART2_BASE		(EP93XX_APB_BASE | UART2_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x808E0000 - 0x808EFFFF: UART3
- */
-#define UART3_OFFSET		0x0E0000
-#define UART3_BASE		(EP93XX_APB_BASE | UART3_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x808F0000 - 0x808FFFFF: Key Matrix
- */
-#define KEY_OFFSET		0x0F0000
-#define KEY_BASE		(EP93XX_APB_BASE | KEY_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x80900000 - 0x8090FFFF: Touchscreen
- */
-#define TOUCH_OFFSET		0x900000
-#define TOUCH_BASE		(EP93XX_APB_BASE | TOUCH_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
- */
-#define PWM_OFFSET		0x910000
-#define PWM_BASE		(EP93XX_APB_BASE | PWM_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x80920000 - 0x8092FFFF: Real time clock
- */
-#define RTC_OFFSET		0x920000
-#define RTC_BASE		(EP93XX_APB_BASE | RTC_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x80930000 - 0x8093FFFF: Syscon
- */
-#define SYSCON_OFFSET		0x930000
-#define SYSCON_BASE		(EP93XX_APB_BASE | SYSCON_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct syscon_regs {
-	uint32_t pwrsts;
-	uint32_t pwrcnt;
-	uint32_t halt;
-	uint32_t stby;
-	uint32_t reserved0[2];
-	uint32_t teoi;
-	uint32_t stfclr;
-	uint32_t clkset1;
-	uint32_t clkset2;
-	uint32_t reserved1[6];
-	uint32_t scratch0;
-	uint32_t scratch1;
-	uint32_t reserved2[2];
-	uint32_t apbwait;
-	uint32_t bustmstrarb;
-	uint32_t bootmodeclr;
-	uint32_t reserved3[9];
-	uint32_t devicecfg;
-	uint32_t vidclkdiv;
-	uint32_t mirclkdiv;
-	uint32_t i2sclkdiv;
-	uint32_t keytchclkdiv;
-	uint32_t chipid;
-	uint32_t reserved4;
-	uint32_t syscfg;
-	uint32_t reserved5[8];
-	uint32_t sysswlock;
-};
-#else
-#define SYSCON_SCRATCH0		(SYSCON_BASE + 0x0040)
-#endif
-
-#define SYSCON_PWRCNT_UART_BAUD			(1 << 29)
-
-#define SYSCON_CLKSET_PLL_X2IPD_SHIFT		0
-#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT		5
-#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT		11
-#define SYSCON_CLKSET_PLL_PS_SHIFT		16
-#define SYSCON_CLKSET1_PCLK_DIV_SHIFT		18
-#define SYSCON_CLKSET1_HCLK_DIV_SHIFT		20
-#define SYSCON_CLKSET1_NBYP1			(1 << 23)
-#define SYSCON_CLKSET1_FCLK_DIV_SHIFT		25
-
-#define SYSCON_CLKSET2_PLL2_EN			(1 << 18)
-#define SYSCON_CLKSET2_NBYP2			(1 << 19)
-#define SYSCON_CLKSET2_USB_DIV_SHIFT		28
-
-#define SYSCON_CHIPID_REV_MASK			0xF0000000
-#define SYSCON_DEVICECFG_SWRST			(1 << 31)
-
-/* -----------------------------------------------------------------------------
- * 0x80930000 - 0x8093FFFF: Watchdog Timer
- */
-#define WATCHDOG_OFFSET		0x940000
-#define WATCHDOG_BASE		(EP93XX_APB_BASE | WATCHDOG_OFFSET)
-
-/* -----------------------------------------------------------------------------
- * 0x80950000 - 0x9000FFFF: Reserved
- */
-
diff --git a/arch/arm/mach-ep93xx/led.c b/arch/arm/mach-ep93xx/led.c
index cbd035b64c..b2909fc070 100644
--- a/arch/arm/mach-ep93xx/led.c
+++ b/arch/arm/mach-ep93xx/led.c
@@ -15,7 +15,7 @@
 
 #include <common.h>
 #include <io.h>
-#include <mach/ep93xx-regs.h>
+#include <mach/ep93xx/ep93xx-regs.h>
 
 #include "led.h"
 
diff --git a/arch/arm/mach-ep93xx/lowlevel_init.S b/arch/arm/mach-ep93xx/lowlevel_init.S
index 8b0ce3792a..5cc24a1cc0 100644
--- a/arch/arm/mach-ep93xx/lowlevel_init.S
+++ b/arch/arm/mach-ep93xx/lowlevel_init.S
@@ -18,7 +18,7 @@
  */
 
 #include <linux/sizes.h>
-#include <mach/ep93xx-regs.h>
+#include <mach/ep93xx/ep93xx-regs.h>
 #include <asm/barebox-arm-head.h>
 
 .globl barebox_arm_reset_vector
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5f5b762ce5..6125813773 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,41 +1,6 @@
-if ARCH_IMX
+# SPDX-License-Identifier: GPL-2.0-only
 
-config ARCH_TEXT_BASE
-	hex
-	default 0x83f00000 if MACH_EUKREA_CPUIMX25
-	default 0xa0000000 if MACH_EUKREA_CPUIMX27
-	default 0x87f00000 if MACH_EUKREA_CPUIMX35
-	default 0x97f00000 if MACH_EUKREA_CPUIMX51SD
-	default 0xc0000000 if MACH_IMX21ADS
-	default 0xa0000000 if MACH_IMX27ADS
-	default 0x83f00000 if MACH_FREESCALE_MX25_3STACK && FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
-	default 0x87f00000 if MACH_FREESCALE_MX25_3STACK && FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
-	default 0x87f00000 if MACH_FREESCALE_MX35_3STACK
-	default 0xa7f00000 if MACH_PCA100
-	default 0xa0000000 if MACH_PCM038
-	default 0x87f00000 if MACH_PCM037
-	default 0x87f00000 if MACH_PCM043
-	default 0xa7e00000 if MACH_NESO
-	default 0x97f00000 if MACH_FREESCALE_MX51_PDK
-	default 0x7ff00000 if MACH_FREESCALE_MX53_LOCO
-	default 0x7ff00000 if MACH_FREESCALE_MX53_SMD
-	default 0x7ff00000 if MACH_FREESCALE_MX53_VMX53
-	default 0x87f00000 if MACH_GUF_CUPID
-	default 0x93d00000 if MACH_TX25
-	default 0x7ff00000 if MACH_TQMA53
-	default 0x4fc00000 if MACH_SABRELITE
-	default 0x8fe00000 if MACH_TX53
-	default 0x97f00000 if MACH_EFIKA_MX_SMARTBOOK
-	default 0x17800000 if MACH_SABRESD
-	default 0x4fc00000 if MACH_REALQ7
-	default 0x4fc00000 if MACH_GK802
-	default 0x87f00000 if MACH_KINDLE3
-	default 0x2fc00000 if MACH_TQMA6X
-	default 0x4fc00000 if MACH_DFI_FS700_M60
-	default 0x4fc00000 if MACH_UDOO
-	default 0x4fc00000 if MACH_VARISCITE_MX6
-	default 0x4fc00000 if MACH_PHYTEC_SOM_IMX6
-	default 0x9fc00000 if MACH_WARP7
+if ARCH_IMX
 
 config ARCH_IMX_IMXIMAGE
 	bool
@@ -62,10 +27,25 @@ config BAREBOX_UPDATE_IMX_EXTERNAL_NAND
 	depends on MTD_WRITE
 	default y
 
+config USB_GADGET_DRIVER_ARC_PBL
+	bool
+
 config RESET_IMX_SRC
 	def_bool y
 	depends on ARCH_IMX6 || ARCH_IMX50 || ARCH_IMX51 || ARCH_IMX53
 
+config ARCH_IMX_ATF
+	def_bool y
+	depends on ARCH_IMX8M || ARCH_IMX9
+
+config ARCH_IMX_ROMAPI
+	def_bool y
+	depends on ARCH_IMX8M || ARCH_IMX9
+
+config ARCH_IMX_SCRATCHMEM
+	def_bool y
+	depends on ARCH_IMX8M || ARCH_IMX9
+
 #
 # PMIC configuration found on i.MX51 Babbadge board
 #
@@ -75,7 +55,7 @@ config MACH_FREESCALE_MX51_PDK_POWER
 	select DRIVER_SPI_IMX
 	select MFD_MC13XXX
 
-comment "Freescale i.MX System-on-Chip"
+menu "i.MX boards"
 
 config ARCH_IMX1
 	bool
@@ -175,17 +155,23 @@ config ARCH_IMX8M
 	select CPU_V8
 	select PINCTRL_IMX_IOMUX_V3
 	select OFTREE
-	select SYS_SUPPORTS_64BIT_KERNEL
 	select COMMON_CLK_OF_PROVIDER
 	select ARCH_HAS_FEC_IMX
 	select HW_HAS_PCI
 	select IMX8M_DRAM
 	select PBL_VERIFY_PIGGY if HABV4
+	select ARM_USE_COMPRESSED_DTB
+	select SOC_BUS
+	imply FSL_CAAM_RNG_PBL_INIT if HAVE_OPTEE
 
 config ARCH_IMX8MM
 	select ARCH_IMX8M
 	bool
 
+config ARCH_IMX8MN
+	select ARCH_IMX8M
+	bool
+
 config ARCH_IMX8MP
 	select ARCH_IMX8M
 	bool
@@ -194,6 +180,20 @@ config ARCH_IMX8MQ
 	select ARCH_IMX8M
 	bool
 
+config ARCH_IMX9
+	select AHAB
+	bool
+
+config ARCH_IMX93
+	bool
+	select ARCH_IMX9
+	select CPU_V8
+	select PINCTRL_IMX_IOMUX_V3
+	select OFTREE
+	select COMMON_CLK_OF_PROVIDER
+	select ARM_USE_COMPRESSED_DTB
+	select ARCH_HAS_FEC_IMX
+
 config ARCH_VF610
 	bool
 	select ARCH_HAS_L2X0
@@ -208,12 +208,12 @@ config ARCH_VF610
 	select IMX_OCOTP	# Needed for clock adjustement
 	select CLOCKSOURCE_ARM_GLOBAL_TIMER
 
-config IMX_MULTI_BOARDS
-	bool "Allow multiple boards to be selected"
-	select HAVE_PBL_MULTI_IMAGES
-	select RELOCATABLE
+config MACH_ZII_COMMON
+	bool
 
-if IMX_MULTI_BOARDS
+if 32BIT
+
+comment "i.MX1 boards"
 
 config MACH_SCB9328
 	bool "Synertronixx scb9328"
@@ -222,6 +222,8 @@ config MACH_SCB9328
 	help
 	  Say Y here if you are using the Synertronixx scb9328 board
 
+comment "i.MX25 boards"
+
 config MACH_TX25
 	bool "Ka-Ro TX25"
 	select ARCH_IMX25
@@ -229,6 +231,8 @@ config MACH_TX25
 	help
 	  Say Y here if you are using the Ka-Ro tx25 board
 
+comment "i.MX27 boards"
+
 config MACH_PCA100
 	bool "phyCard-i.MX27"
 	select ARCH_IMX27
@@ -248,6 +252,8 @@ config MACH_PCM038
 	  Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
 	  with a Freescale i.MX27 Processor
 
+comment "i.MX50 boards"
+
 config MACH_KINDLE_MX50
 	bool "i.MX50 based Amazon Kindle 4 and 5"
 	select ARCH_IMX50
@@ -264,6 +270,8 @@ config MACH_KINDLE_MX50
 	  Kindle Model No. D01100 (Kindle Wi-Fi), D01200 (Kindle Touch) or
 	  EY21 (Kindle Paperwhite).
 
+comment "i.MX51 boards"
+
 config MACH_CCMX51
 	bool "ConnectCore i.MX51"
 	select ARCH_IMX51
@@ -271,7 +279,6 @@ config MACH_CCMX51
 	select SPI
 	select DRIVER_SPI_IMX
 	select MFD_MC13XXX
-	select RELOCATABLE
 	help
 	  Say Y here if you are using Digi ConnectCore (W)i-i.MX51
 	  equipped with a Freescale i.MX51 Processor
@@ -285,17 +292,13 @@ config MACH_EFIKA_MX_SMARTBOOK
 	help
 	  Choose this to compile barebox for the Efika MX Smartbook
 
-config MACH_EMBEDSKY_E9
-	bool "Embedsky E9 Mini-PC"
-	select ARCH_IMX6
-	help
-	  Choose this to compile barebox for the Embedsky E9 Mini PC
-
 config MACH_FREESCALE_MX51_PDK
 	bool "Freescale i.MX51 PDK"
 	select ARCH_IMX51
 	select MACH_FREESCALE_MX51_PDK_POWER
 
+comment "i.MX53 boards"
+
 config MACH_CCMX53
 	bool "Digi ConnectCore i.MX53"
 	select ARCH_IMX53
@@ -315,6 +318,12 @@ config MACH_GUF_VINCELL
 	bool "Garz-Fricke Vincell"
 	select ARCH_IMX53
 
+config MACH_TX53
+	bool "Ka-Ro TX53"
+	select ARCH_IMX53
+	help
+	  Say Y here if you are using the Ka-Ro tx53 board
+
 config MACH_TQMA53
 	bool "TQ i.MX53 TQMa53"
 	select ARCH_IMX53
@@ -326,60 +335,63 @@ config MACH_FREESCALE_MX53_VMX53
 	  Say Y here if you are using the Voipac Technologies X53-DMM-668
 	  module equipped with a Freescale i.MX53 Processor
 
-config MACH_TX53
-	bool "Ka-Ro TX53"
-	select ARCH_IMX53
-	help
-	  Say Y here if you are using the Ka-Ro tx53 board
+config MACH_ZII_RDU1
+	bool "ZII i.MX51 RDU1"
+	select ARCH_IMX51
+	select MACH_FREESCALE_MX51_PDK_POWER
+	select CRC8
+	select MACH_ZII_COMMON
+	select ARM_USE_COMPRESSED_DTB
 
-config MACH_PHYTEC_SOM_IMX6
-        bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6"
-        select ARCH_IMX6
-	select ARCH_IMX6UL
-	select I2C
-	select I2C_IMX
+comment "i.MX6 boards"
 
-config MACH_PROTONIC_IMX6
-	bool "Protonic-Holland i.MX6 based boards"
+config MACH_ADVANTECH_ROM_742X
+	bool "Advantech ROM 742X"
 	select ARCH_IMX6
-	select ARCH_IMX6UL
 	select ARM_USE_COMPRESSED_DTB
 
-config MACH_KONTRON_SAMX6I
-        bool "Kontron sAMX6i"
-        select ARCH_IMX6
-
-config MACH_DFI_FS700_M60
-	bool "DFI i.MX6 FS700 M60 Q7 Board"
+config MACH_NITROGEN6
+	bool "BoundaryDevices Nitrogen6 boards"
 	select ARCH_IMX6
 
-config MACH_GUF_SANTARO
-	bool "Garz+Fricke Santaro Board"
+config MACH_CM_FX6
+	bool "CM FX6"
 	select ARCH_IMX6
-	select I2C
-	select I2C_IMX
+	select MCI_IMX_ESDHC_PBL
 
 config MACH_REALQ7
 	bool "DataModul i.MX6Q Real Qseven Board"
 	select ARCH_IMX6
 
-config MACH_GK802
-	bool "Zealz GK802 Mini PC"
+config MACH_DFI_FS700_M60
+	bool "DFI i.MX6 FS700 M60 Q7 Board"
 	select ARCH_IMX6
 
+config MACH_DIGI_CCIMX6ULSBCPRO
+	bool "Digi Internal CC-IMX6UL SBC Pro"
+	select ARCH_IMX6
+	select ARCH_IMX6UL
+	select ARM_USE_COMPRESSED_DTB
+
 config MACH_ELTEC_HIPERCAM
 	bool "ELTEC HiPerCam"
 	select ARCH_IMX6
 
-config MACH_TQMA6X
-	bool "TQ tqma6x on mba6x"
+config MACH_EMBEDSKY_E9
+	bool "Embedsky E9 Mini-PC"
 	select ARCH_IMX6
+	help
+	  Choose this to compile barebox for the Embedsky E9 Mini PC
 
-config MACH_TX6X
-	bool "Karo TX6x"
+config MACH_EMBEST_MARSBOARD
+	bool "Embest MarSboard"
 	select ARCH_IMX6
-	select I2C
-	select I2C_IMX
+	select ARM_USE_COMPRESSED_DTB
+
+config MACH_EMBEST_RIOTBOARD
+	bool "Embest RIoTboard"
+	select ARCH_IMX6
+	imply AT803X_PHY
 
 config MACH_SABRELITE
 	bool "Freescale i.MX6 Sabre Lite"
@@ -395,45 +407,16 @@ config MACH_FREESCALE_IMX6SX_SABRESDB
 	select I2C
 	select I2C_IMX
 
-config MACH_NITROGEN6
-	bool "BoundaryDevices Nitrogen6 boards"
-	select ARCH_IMX6
-
-config MACH_SOLIDRUN_MICROSOM
-	bool "SolidRun MicroSOM based devices"
-	select ARCH_IMX6
-
-config MACH_TECHNEXION_PICO_HOBBIT
-	bool "Technexion Pico Hobbit"
-	select ARCH_IMX6
-	select ARCH_IMX6UL
-	select ARM_USE_COMPRESSED_DTB
-
-config MACH_TECHNEXION_WANDBOARD
-	bool "Technexion Wandboard"
-	select ARCH_IMX6
-	select ARM_USE_COMPRESSED_DTB
-	select MCI_IMX_ESDHC_PBL
-
-config MACH_EMBEST_MARSBOARD
-	bool "Embest MarSboard"
-	select ARCH_IMX6
-	select ARM_USE_COMPRESSED_DTB
-
-config MACH_EMBEST_RIOTBOARD
-	bool "Embest RIoTboard"
-	select ARCH_IMX6
-
 config MACH_UDOO
 	bool "Freescale i.MX6 UDOO Board"
 	select ARCH_IMX6
 
 config MACH_UDOO_NEO
-	bool "i.MX6 UDOO Neo Board (full variant)"
+	bool "Freescale i.MX6 UDOO Neo Board (full variant)"
 	select ARCH_IMX6SX
 
-config MACH_VARISCITE_MX6
-	bool "Variscite i.MX6 Quad SOM"
+config MACH_GUF_SANTARO
+	bool "Garz+Fricke Santaro Board"
 	select ARCH_IMX6
 	select I2C
 	select I2C_IMX
@@ -444,40 +427,96 @@ config MACH_GW_VENTANA
 	select I2C
 	select I2C_IMX
 
-config MACH_CM_FX6
-	bool "CM FX6"
+config MACH_GRINN_LITEBOARD
+	bool "Grinn liteboard"
+	select ARCH_IMX6UL
+
+config MACH_TX6X
+	bool "Karo TX6x"
 	select ARCH_IMX6
-	select MCI_IMX_ESDHC_PBL
+	select I2C
+	select I2C_IMX
 
-config MACH_ADVANTECH_ROM_742X
-	bool "Advantech ROM 742X"
+config MACH_KONTRON_SAMX6I
+        bool "Kontron sAMX6i"
+        select ARCH_IMX6
+
+config MACH_NOVENA
+	bool "Kosagi Novena board"
 	select ARCH_IMX6
 	select ARM_USE_COMPRESSED_DTB
+	select DDR_SPD
+	select I2C_IMX_EARLY
+	select MCI_IMX_ESDHC_PBL
+	select USB_GADGET_DRIVER_ARC_PBL
 
-config MACH_WARP7
-	bool "NXP i.MX7: element 14 WaRP7 Board"
-	select ARCH_IMX7
+config MACH_NXP_IMX6ULL_EVK
+	bool "NXP i.MX6ull EVK Board"
+	select ARCH_IMX6UL
 
-config MACH_AC_SXB
-	bool "Atlas Copco: SXB board"
-	select ARCH_IMX7
+config MACH_PHYTEC_SOM_IMX6
+        bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6"
+        select ARCH_IMX6
+	select ARCH_IMX6UL
+	select I2C
+	select I2C_IMX
+
+config MACH_PROTONIC_IMX6
+	bool "Protonic-Holland i.MX6 based boards"
+	select ARCH_IMX6
+	select ARCH_IMX6UL
+	select ARM_USE_COMPRESSED_DTB
+	select IMX_OCOTP
+
+config MACH_SKOV_IMX6
+	bool "Skov IMX6"
+	select ARCH_IMX6
+	select ARM_USE_COMPRESSED_DTB
 	select MCI_IMX_ESDHC_PBL
+	select DSA
+	select DRIVER_NET_KSZ8873
+
+config MACH_SOLIDRUN_MICROSOM
+	bool "SolidRun MicroSOM based devices"
+	select ARCH_IMX6
+
+config MACH_TECHNEXION_PICO_HOBBIT
+	bool "Technexion Pico Hobbit"
+	select ARCH_IMX6
+	select ARCH_IMX6UL
 	select ARM_USE_COMPRESSED_DTB
 
-config MACH_VF610_TWR
-	bool "Freescale VF610 Tower Board"
-	select ARCH_VF610
+config MACH_TECHNEXION_WANDBOARD
+	bool "Technexion Wandboard"
+	select ARCH_IMX6
+	select ARM_USE_COMPRESSED_DTB
+	select MCI_IMX_ESDHC_PBL
 
-config MACH_ZII_COMMON
-	bool
+config MACH_TQMA6X
+	bool "TQ tqma6x on mba6x"
+	select ARCH_IMX6
 
-config MACH_ZII_RDU1
-	bool "ZII i.MX51 RDU1"
-	select ARCH_IMX51
-	select MACH_FREESCALE_MX51_PDK_POWER
-	select CRC8
-	select MACH_ZII_COMMON
+config MACH_TQMA6UL
+	bool "TQ tqma6ul on mba6ulx"
+	select ARCH_IMX6UL
 	select ARM_USE_COMPRESSED_DTB
+	select BOARD_TQ
+	select I2C_IMX_EARLY
+
+config MACH_VARISCITE_MX6
+	bool "Variscite i.MX6 Quad SOM"
+	select ARCH_IMX6
+	select I2C
+	select I2C_IMX
+
+config MACH_WEBASTO_CCBV2
+	bool "Webasto Common Communication Board V2"
+	select ARCH_IMX6UL
+	select ARM_USE_COMPRESSED_DTB
+
+config MACH_GK802
+	bool "Zealz GK802 Mini PC"
+	select ARCH_IMX6
 
 config MACH_ZII_RDU2
 	bool "ZII i.MX6Q(+) RDU2"
@@ -486,30 +525,21 @@ config MACH_ZII_RDU2
 	select MACH_ZII_COMMON
 	select ARM_USE_COMPRESSED_DTB
 
-config MACH_ZII_IMX8MQ_DEV
-	bool "ZII i.MX8MQ based devices"
-	select ARCH_IMX8MQ
-	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
-	select FIRMWARE_IMX8MQ_ATF
-	select ARM_SMCCC
-	select MCI_IMX_ESDHC_PBL
-	select MACH_ZII_COMMON
-	select ARM_USE_COMPRESSED_DTB
+comment "i.MX7 boards"
 
-config MACH_ZII_VF610_DEV
-	bool "ZII VF610 Dev Family"
-	select ARCH_VF610
-	select CLKDEV_LOOKUP
-	select MACH_ZII_COMMON
+config MACH_MEERKAT96
+	bool "96Boards: i.MX7 Meerkat96"
+	select ARCH_IMX7
 	select ARM_USE_COMPRESSED_DTB
 
-config MACH_ZII_IMX7D_DEV
-	bool "ZII i.MX7D based devices"
+config MACH_AC_SXB
+	bool "Atlas Copco: SXB board"
 	select ARCH_IMX7
+	select MCI_IMX_ESDHC_PBL
 	select ARM_USE_COMPRESSED_DTB
 
-config MACH_PHYTEC_PHYCORE_IMX7
-	bool "Phytec phyCORE i.MX7"
+config MACH_WARP7
+	bool "NXP i.MX7: element 14 WaRP7 Board"
 	select ARCH_IMX7
 
 config MACH_FREESCALE_MX7_SABRESD
@@ -524,14 +554,90 @@ config MACH_FREESCALE_MX7_SABRESD
 
 	  https://goo.gl/6EKGdk
 
+config MACH_PHYTEC_PHYCORE_IMX7
+	bool "Phytec phyCORE i.MX7"
+	select ARCH_IMX7
+
+config MACH_VARISCITE_SOM_MX7
+	bool "Variscite VAR-SOM-MX7"
+	select ARCH_IMX7
+	select ARM_USE_COMPRESSED_DTB
+	help
+	  Support for boards that use a Variscite SOM-MX7, like:
+	  - Gossen Metrawatt e143_01
+
+config MACH_ZII_IMX7D_DEV
+	bool "ZII i.MX7D based devices"
+	select ARCH_IMX7
+	select ARM_USE_COMPRESSED_DTB
+
 config MACH_KAMSTRUP_MX7_CONCENTRATOR
 	bool "Kamstrup i.MX7 Concentrator"
 	select ARCH_IMX7
 	select ARM_USE_COMPRESSED_DTB
 
-config MACH_NXP_IMX6ULL_EVK
-	bool "NXP i.MX6ull EVK Board"
-	select ARCH_IMX6UL
+comment "VF610 boards"
+
+config MACH_VF610_TWR
+	bool "Freescale VF610 Tower Board"
+	select ARCH_VF610
+
+config MACH_ZII_VF610_DEV
+	bool "ZII VF610 Dev Family"
+	select ARCH_VF610
+	select MACH_ZII_COMMON
+	select ARM_USE_COMPRESSED_DTB
+
+endif
+
+if 64BIT
+
+comment "i.MX8M boards"
+
+config MACH_CONGATEC_QMX8P_SOM
+	bool
+	select ARCH_IMX8MP
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MP_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
+	select I2C_IMX_EARLY
+
+config MACH_KOENIGBAUER_ALPHAJET
+	bool "Koenig+Bauer AlphaJet"
+	select MACH_CONGATEC_QMX8P_SOM
+
+config MACH_INNOCOMM_WB15
+	bool "InnoComm WB15 (i.MX8MM) EVK"
+	select ARCH_IMX8MM
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MM_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
+	select I2C_IMX_EARLY
+	select USB_GADGET_DRIVER_ARC_PBL
+	imply AT803X_PHY
+
+config MACH_KARO_QSXP_ML81
+	bool "Karo QSXP ML81 (i.MX8MP) SOM on QSBASE4 Board"
+	select ARCH_IMX8MP
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MP_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
+	select I2C_IMX_EARLY
+
+config MACH_MNT_REFORM
+	bool "MNT Reform"
+	select ARCH_IMX8MQ
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MQ_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select I2C_IMX_EARLY
 
 config MACH_NXP_IMX8MM_EVK
 	bool "NXP i.MX8MM EVK Board"
@@ -544,6 +650,17 @@ config MACH_NXP_IMX8MM_EVK
 	select I2C_IMX_EARLY
 	select USB_GADGET_DRIVER_ARC_PBL
 
+config MACH_NXP_IMX8MN_EVK
+	bool "NXP i.MX8MN EVK Board"
+	select ARCH_IMX8MN
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX_DDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MN_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
+	select I2C_IMX_EARLY
+
 config MACH_NXP_IMX8MP_EVK
 	bool "NXP i.MX8MP EVK Board"
 	select ARCH_IMX8MP
@@ -553,7 +670,6 @@ config MACH_NXP_IMX8MP_EVK
 	select MCI_IMX_ESDHC_PBL
 	select IMX8M_DRAM
 	select I2C_IMX_EARLY
-	select USB_GADGET_DRIVER_ARC_PBL
 
 config MACH_NXP_IMX8MQ_EVK
 	bool "NXP i.MX8MQ EVK Board"
@@ -563,6 +679,19 @@ config MACH_NXP_IMX8MQ_EVK
 	select ARM_SMCCC
 	select MCI_IMX_ESDHC_PBL
 
+config MACH_PHYTEC_SOM_IMX8MM
+	bool "Phytec i.MX8MM SOM"
+	select ARCH_IMX8MM
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MM_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
+	select I2C_IMX_EARLY
+	select USB_GADGET_DRIVER_ARC_PBL
+	select BOARD_PHYTEC_SOM_IMX8M_DETECTION
+	imply AT803X_PHY
+
 config MACH_PHYTEC_SOM_IMX8MQ
 	bool "Phytec i.MX8M SOM"
 	select ARCH_IMX8MQ
@@ -571,254 +700,85 @@ config MACH_PHYTEC_SOM_IMX8MQ
 	select ARM_SMCCC
 	select MCI_IMX_ESDHC_PBL
 
-config MACH_GRINN_LITEBOARD
-	bool "Grinn liteboard"
-	select ARCH_IMX6UL
-
-config MACH_DIGI_CCIMX6ULSBCPRO
-	bool "Digi Internal CC-IMX6UL SBC Pro"
-	select ARCH_IMX6
-	select ARCH_IMX6UL
-	select ARM_USE_COMPRESSED_DTB
-
-config MACH_WEBASTO_CCBV2
-	bool "Webasto Common Communication Board V2"
-	select ARCH_IMX6UL
-	select ARM_USE_COMPRESSED_DTB
-
-config MACH_MNT_REFORM
-	bool "MNT Reform"
-	select ARCH_IMX8MQ
+config MACH_POLYHEX_DEBIX
+	bool "Polyhex DEBIX i.MX8MP Boards"
+	select ARCH_IMX8MP
 	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
-	select FIRMWARE_IMX8MQ_ATF
+	select FIRMWARE_IMX8MP_ATF
 	select ARM_SMCCC
 	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
 	select I2C_IMX_EARLY
-
-config MACH_SKOV_IMX6
-	bool "Skov IMX6"
-	select ARCH_IMX6
-	select ARM_USE_COMPRESSED_DTB
-	select MCI_IMX_ESDHC_PBL
-
-endif
-
-# ----------------------------------------------------------
-
-choice
-	prompt "Select Board"
-	depends on !IMX_MULTI_BOARDS
-
-# ----------------------------------------------------------
-
-comment "i.MX21 Boards"
-
-config MACH_IMX21ADS
-	bool "Freescale i.MX21ADS"
-	select ARCH_IMX21
-	select HAS_CS8900
-	help
-	  Say Y here if you are using the Freescale i.MX21ads board equipped
-	  with a Freescale i.MX21 Processor
-
-# ----------------------------------------------------------
-
-comment "i.MX25 Boards"
-
-config MACH_EUKREA_CPUIMX25
-	bool "Eukrea CPUIMX25"
-	select ARCH_IMX25
-	help
-	  Say Y here if you are using the Eukrea Electromatique's CPUIMX25
-	  equipped with a Freescale i.MX25 Processor
-
-config MACH_FREESCALE_MX25_3STACK
-	bool "Freescale MX25 3stack"
-	select ARCH_IMX25
-	select I2C
-	select MFD_MC34704
 	help
-	  Say Y here if you are using the Freescale MX25 3stack board equipped
-	  with a Freescale i.MX25 Processor
-
-# ----------------------------------------------------------
-
-comment "i.MX27 Boards"
-
-config MACH_EUKREA_CPUIMX27
-	bool "EUKREA CPUIMX27"
-	select ARCH_IMX27
-	help
-	  Say Y here if you are using Eukrea's CPUIMX27 equipped
-	  with a Freescale i.MX27 Processor
-
-config MACH_IMX27ADS
-	bool "Freescale i.MX27ADS"
-	select ARCH_IMX27
-	help
-	  Say Y here if you are using the Freescale i.MX27ads board equipped
-	  with a Freescale i.MX27 Processor
-
-config MACH_NESO
-	bool "Garz+Fricke Neso"
-	select ARCH_IMX27
-	help
-	  Say Y here if you are using the Garz+Fricke Neso board equipped
-	  with a Freescale i.MX27 Processor
+	  Support for DEBIX Model-A/B and SOM A + SOM A I/O board
 
-# ----------------------------------------------------------
+config MACH_PROTONIC_IMX8M
+	bool "Protonic-Holland i.MX8Mx based boards"
+	select ARCH_IMX8MM
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MM_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
+	select USB_GADGET_DRIVER_ARC_PBL
 
-comment "i.MX31 Boards"
+config MACH_SKOV_IMX8MP
+	bool "Skov i.MX8MP based boards"
+	select ARCH_IMX8MP
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MP_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
+	select I2C_IMX_EARLY
 
-config MACH_PCM037
-	bool "phyCORE-i.MX31"
-	select ARCH_IMX31
-	select USB_ULPI if USB
-	select ARCH_HAS_L2X0
-	help
-	  Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped
-	  with a Freescale i.MX31 Processor
+config MACH_TQ_MBA8MPXL
+	bool "TQ i.MX8MP Dual/Quad on MBa8MPxL Board"
+	select ARCH_IMX8MP
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MP_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
+	select I2C_IMX_EARLY
 
-# ----------------------------------------------------------
+config MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP
+	bool "Variscite DT8MCustomBoard with DART-MX8M-PLUS"
+	select ARCH_IMX8MP
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MP_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select IMX8M_DRAM
+	select I2C_IMX_EARLY
 
-comment "i.MX35 Boards"
+config MACH_ZII_IMX8MQ_DEV
+	bool "ZII i.MX8MQ based devices"
+	select ARCH_IMX8MQ
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+	select FIRMWARE_IMX8MQ_ATF
+	select ARM_SMCCC
+	select MCI_IMX_ESDHC_PBL
+	select MACH_ZII_COMMON
 
-config MACH_EUKREA_CPUIMX35
-	bool "EUKREA CPUIMX35"
-	select ARCH_IMX35
-	select ARCH_HAS_L2X0
-	help
-	  Say Y here if you are using Eukrea's CPUIMX35 equipped
-	  with a Freescale i.MX35 Processor
+comment "i.MX93 boards"
 
-config MACH_FREESCALE_MX35_3STACK
-	bool "Freescale MX35 3stack"
-	select ARCH_IMX35
+config MACH_TQMA93XX
+	bool "TQ i.MX93 on TQMA93XX Board"
+	select ARCH_IMX93
+	select IMX9_DRAM
+	select BOARD_TQ
 	select I2C
-	select I2C_IMX
-	select MFD_MC13XXX
-	select MFD_MC9SDZ60
-	help
-	  Say Y here if you are using the Freescale MX35 3stack board equipped
-	  with a Freescale i.MX35 Processor
-
-config MACH_PCM043
-	bool "phyCORE-i.MX35"
-	select ARCH_IMX35
-	select ARCH_HAS_L2X0
-	help
-	  Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
-	  with a Freescale i.MX35 Processor
-
-config MACH_GUF_CUPID
-	bool "Garz+Fricke Cupid"
-	select ARCH_IMX35
-	select ARCH_HAS_L2X0
-	help
-	  Say Y here if you are using the Garz+Fricke Neso board equipped
-	  with a Freescale i.MX35 Processor
-
-config MACH_KINDLE3
-	bool "Amazon Kindle3"
-	select ARCH_IMX35
-	select ARCH_HAS_L2X0
-	help
-	  Say Y here if you are using the Amazon Model No. D00901 Kindle
-
-# ----------------------------------------------------------
-
-comment "i.MX51 Boards"
-
-config MACH_EUKREA_CPUIMX51SD
-	bool "EUKREA CPUIMX51"
-	select ARCH_IMX51
-	help
-	  Say Y here if you are using Eukrea's CPUIMX51 equipped
-	  with a Freescale i.MX51 Processor
-
-# ----------------------------------------------------------
-
-comment "i.MX53 Boards"
-
-config MACH_FREESCALE_MX53_SMD
-	bool "Freescale i.MX53 SMD"
-	select ARCH_IMX53
-
-endchoice
-
-# ----------------------------------------------------------
-
-menu "Board specific settings"
-
-if MACH_PCM037
-
-choice
-	prompt "SDRAM Bank0"
-config PCM037_SDRAM_BANK0_128MB
-	bool "128MB"
-config PCM037_SDRAM_BANK0_256MB
-	bool "256MB"
-endchoice
-
-choice
-	prompt "SDRAM Bank1"
-config PCM037_SDRAM_BANK1_NONE
-	bool "none"
-config PCM037_SDRAM_BANK1_128MB
-	bool "128MB"
-config PCM037_SDRAM_BANK1_256MB
-	bool "256MB"
-endchoice
-
-endif
-
-if MACH_EUKREA_CPUIMX27
-
-choice
-	prompt "SDRAM Size"
-config EUKREA_CPUIMX27_SDRAM_128MB
-	bool "128 MB"
-config EUKREA_CPUIMX27_SDRAM_256MB
-	bool "256 MB"
-endchoice
-
-choice
-	prompt "NOR Flash Size"
-config EUKREA_CPUIMX27_NOR_32MB
-	bool "<= 32 MB"
-config EUKREA_CPUIMX27_NOR_64MB
-	bool "> 32 MB"
-endchoice
-
-choice
-	prompt "Quad UART Port"
-	depends on DRIVER_SERIAL_NS16550
-config EUKREA_CPUIMX27_QUART1
-	bool "Q1"
-config EUKREA_CPUIMX27_QUART2
-	bool "Q2"
-config EUKREA_CPUIMX27_QUART3
-	bool "Q3"
-config EUKREA_CPUIMX27_QUART4
-	bool "Q4"
-endchoice
-
-endif
-
-if MACH_FREESCALE_MX25_3STACK
-
-choice
-	prompt "SDRAM Type"
-config FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
-	bool "64 MB (DDR2)"
-config FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
-	bool "128 MB (mDDR)"
-endchoice
+	select I2C_IMX_LPI2C
+	select FIRMWARE_IMX93_ATF
+	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
 
 endif
 
 endmenu
 
+# ----------------------------------------------------------
+
 menu "i.MX specific settings"
 
 config IMX_IIM
@@ -848,18 +808,32 @@ config IMX_IIM_FUSE_BLOW
 	  enable it:
 	    imx_iim0.permanent_write_enable=1
 
+config IMX_SAVE_BOOTROM_LOG
+	bool
+	default CMD_BOOTROM
+
 config HAB
 	bool
 
+config AHAB
+	bool
+	select HAB
+
 config HABV4
 	tristate "HABv4 support"
 	select HAB
 	select NVMEM
 	select IMX_OCOTP
-	depends on ARCH_IMX6 || ARCH_IMX8MQ
+	depends on ARCH_IMX6 || ARCH_IMX8M
 	depends on OFDEVICE
 	help
-	  High Assurance Boot, as found on i.MX28/i.MX6/i.MX8MQ.
+	  High Assurance Boot, as found on i.MX28/i.MX6/i.MX8M.
+
+config HABV4_QSPI
+	depends on HABV4
+	bool "HABv4 QPSI support"
+	help
+	  Enable this option to build signed QSPI/FlexSPI images.
 
 config HAB_CERTS_ENV
 	depends on HAB
@@ -932,11 +906,13 @@ if HABV4
 config HABV4_IMAGE_SIGNED
 	bool "build signed images"
 	help
-	  enable the creation of a signed image, if the habv4-imx6-gencsf.h
-	  included in the flash-header and the NXP cst Tool is available
+	  enable the creation of a signed image, if the habv4-imx*-gencsf.h
+	  file appropriate for the SoC is included in the flash-header and
+	  the NXP cst Tool is available
 
 config HABV4_IMAGE_SIGNED_USB
 	bool "build signed USB images"
+	depends on ARCH_IMX6
 	help
 	  enable the creation of a usb signed image, if the habv4-imx6-gencsf.h
 	  included in the flash-header and the NXP cst Tool is available
@@ -944,8 +920,9 @@ config HABV4_IMAGE_SIGNED_USB
 config HABV4_IMAGE_SIGNED_ENCRYPTED
 	bool "build signed encrypted images"
 	help
-	  enable the creation of the encrypted image, if the habv4-imx6-gencsf.h
-	  included in the flash-header and the NXP cst Tool is available
+	  enable the creation of the encrypted image, if the habv4-imx*-gencsf.h
+	  file appropriate for the SoC is included in the flash-header and
+	  the NXP cst Tool is available
 
 endif
 
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d94c846a13..a2d9702bf4 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-$(CONFIG_ARCH_IMX1)  += imx1.o
 obj-$(CONFIG_ARCH_IMX25) += imx25.o
 obj-$(CONFIG_ARCH_IMX21) += imx21.o
@@ -16,14 +18,23 @@ lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
 obj-$(CONFIG_ARCH_IMX7) += imx7.o
 obj-$(CONFIG_ARCH_VF610) += vf610.o
 obj-pbl-$(CONFIG_ARCH_IMX8M) += imx8m.o
-lwl-$(CONFIG_ARCH_IMX8M) += atf.o
+obj-pbl-$(CONFIG_ARCH_IMX_SCRATCHMEM) += scratch.o
+obj-$(CONFIG_ARCH_IMX9) += imx9.o
+lwl-$(CONFIG_ARCH_IMX_ATF) += atf.o
+obj-pbl-$(CONFIG_ARCH_IMX8M) += tzasc.o
+obj-pbl-$(CONFIG_ARCH_IMX_ROMAPI) += romapi.o
 obj-$(CONFIG_IMX_IIM)	+= iim.o
 obj-$(CONFIG_NAND_IMX) += nand.o
 lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
 obj-y += devices.o imx.o
-obj-pbl-y += esdctl.o boot.o
+obj-$(CONFIG_CMD_BOOTROM) += bootrom-cmd.o
+obj-pbl-y += esdctl.o boot.o imx.o
 obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
 obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o
+pbl-$(CONFIG_USB_GADGET_DRIVER_ARC_PBL) += imx-udc.o
 obj-$(CONFIG_RESET_IMX_SRC) += src.o
 lwl-y += cpu_init.o
 pbl-y += xload-spi.o xload-common.o xload-imx-nand.o xload-gpmi-nand.o
+pbl-y += xload-qspi.o
+obj-pbl-$(CONFIG_ARCH_IMX9) += ele.o
+obj-pbl-$(CONFIG_ARCH_IMX9) += imx93-trdc.o
diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c
index 03857e6b9b..8b80460268 100644
--- a/arch/arm/mach-imx/atf.c
+++ b/arch/arm/mach-imx/atf.c
@@ -1,5 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <asm/sections.h>
 #include <common.h>
-#include <mach/atf.h>
+#include <firmware.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/romapi.h>
+#include <mach/imx/esdctl.h>
+#include <asm-generic/memory_layout.h>
+#include <asm/barebox-arm.h>
+#include <mach/imx/imx8m-regs.h>
+#include <mach/imx/imx9-regs.h>
+#include <soc/fsl/fsl_udc.h>
+#include <soc/fsl/caam.h>
+#include <tee/optee.h>
+#include <mach/imx/ele.h>
 
 /**
  * imx8m_atf_load_bl31 - Load ATF BL31 blob and transfer control to it
@@ -11,28 +27,29 @@
  * This function:
  *
  *     1. Copies built-in BL31 blob to an address i.MX8M's BL31
- *        expects to be placed
+ *        expects to be placed (TF-A v2.8+ is position-independent)
  *
  *     2. Sets up temporary stack pointer for EL2, which is execution
  *        level that BL31 will drop us off at after it completes its
  *        initialization routine
  *
  *     3. Transfers control to BL31
- *
- * NOTE: This function expects NXP's implementation of ATF that can be
- * found at:
- *     https://source.codeaurora.org/external/imx/imx-atf
- *
- * any other implementation may or may not work
- *
  */
 
-static void imx8m_atf_load_bl31(const void *fw, size_t fw_size, void *atf_dest)
+static __noreturn void imx8m_atf_start_bl31(const void *fw, size_t fw_size, void *atf_dest)
 {
 	void __noreturn (*bl31)(void) = atf_dest;
+	int ret;
 
-	if (WARN_ON(fw_size > MX8M_ATF_BL31_SIZE_LIMIT))
-		return;
+	BUG_ON(fw_size > MX8M_ATF_BL31_SIZE_LIMIT);
+
+	if (IS_ENABLED(CONFIG_FSL_CAAM_RNG_PBL_INIT)) {
+		ret = imx_early_caam_init(MX8M_CAAM_BASE_ADDR);
+		if (ret)
+			pr_debug("CAAM early init failed: %d\n", ret);
+		else
+			pr_debug("CAAM early init successful\n");
+	}
 
 	memcpy(bl31, fw, fw_size);
 
@@ -40,19 +57,385 @@ static void imx8m_atf_load_bl31(const void *fw, size_t fw_size, void *atf_dest)
 		     "r" (atf_dest - 16) :
 		     "cc");
 	bl31();
+	__builtin_unreachable();
+}
+
+void imx8mm_load_bl33(void *bl33)
+{
+	enum bootsource src;
+	int instance;
+
+	imx8mm_get_boot_source(&src, &instance);
+	switch (src) {
+	case BOOTSOURCE_MMC:
+		imx8m_esdhc_load_image(instance, bl33);
+		break;
+	case BOOTSOURCE_SERIAL:
+		if (!IS_ENABLED(CONFIG_USB_GADGET_DRIVER_ARC_PBL)) {
+			printf("Serial bootmode not supported\n");
+			break;
+		}
+
+		/*
+		 * Traditionally imx-usb-loader sends the PBL twice. The first
+		 * PBL is loaded to OCRAM and executed. Then the full barebox
+		 * image including the PBL is sent again and received here. We
+		 * might change that in the future in imx-usb-loader so that the
+		 * PBL is sent only once and we only receive the rest of the
+		 * image here. To prepare that step we check if we get a full
+		 * barebox image or piggydata only. When it's piggydata only move
+		 * it to the place where it would be if it would have been a
+		 * full image.
+		 */
+		imx8mm_barebox_load_usb(bl33);
+
+		if (!strcmp("barebox", bl33 + 0x20)) {
+			/* Found the barebox marker, so this is a PBL + piggydata */
+			pr_debug("received PBL + piggydata\n");
+		} else {
+			/* no barebox marker, so this is piggydata only */
+			pr_debug("received piggydata\n");
+			memmove(bl33 + barebox_pbl_size, bl33,
+				barebox_image_size - barebox_pbl_size);
+		}
+
+		break;
+	case BOOTSOURCE_SPI:
+		imx8mm_qspi_load_image(instance, bl33);
+		break;
+	default:
+		printf("Unsupported bootsource BOOTSOURCE_%d\n", src);
+		hang();
+	}
+
+	/*
+	 * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
+	 * in EL2. Copy the image there, but replace the PBL part of
+	 * that image with ourselves. On a high assurance boot only the
+	 * currently running code is validated and contains the checksum
+	 * for the piggy data, so we need to ensure that we are running
+	 * the same code in DRAM.
+	 */
+	memcpy(bl33, __image_start, barebox_pbl_size);
+}
+
+static void imx_adjust_optee_memory(void **bl32, void **bl32_image, size_t *bl32_size)
+{
+	struct optee_header *hdr = *bl32_image;
+	u64 membase;
+
+	if (optee_verify_header(hdr))
+		return;
+
+	imx_scratch_save_optee_hdr(hdr);
+
+	membase = (u64)hdr->init_load_addr_hi << 32;
+	membase |= hdr->init_load_addr_lo;
+
+	*bl32 = (void *)membase;
+	*bl32_size -= sizeof(*hdr);
+	*bl32_image += sizeof(*hdr);
+}
+
+__noreturn void imx8mm_load_and_start_image_via_tfa(void)
+{
+	__imx8mm_load_and_start_image_via_tfa((void *)MX8M_ATF_BL33_BASE_ADDR);
+}
+
+__noreturn void __imx8mm_load_and_start_image_via_tfa(void *bl33)
+{
+	const void *bl31;
+	size_t bl31_size;
+	unsigned long endmem = MX8M_DDR_CSD1_BASE_ADDR + imx8m_barebox_earlymem_size(32);
+
+	imx_set_cpu_type(IMX_CPU_IMX8MM);
+	imx8mm_init_scratch_space();
+	imx8m_save_bootrom_log();
+	imx8mm_load_bl33(bl33);
+
+	if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MM_OPTEE)) {
+		void *bl32 = (void *)arm_mem_optee(endmem);
+		size_t bl32_size;
+		void *bl32_image;
+
+		imx8m_tzc380_init();
+		get_builtin_firmware_ext(imx8mm_bl32_bin,
+				bl33, &bl32_image,
+				&bl32_size);
+
+		imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size);
+
+		memcpy(bl32, bl32_image, bl32_size);
+
+		get_builtin_firmware(imx8mm_bl31_bin_optee, &bl31, &bl31_size);
+	} else {
+		get_builtin_firmware(imx8mm_bl31_bin, &bl31, &bl31_size);
+	}
+
+	imx8m_atf_start_bl31(bl31, bl31_size, (void *)MX8MM_ATF_BL31_BASE_ADDR);
+}
+
+void imx8mp_load_bl33(void *bl33)
+{
+	enum bootsource src;
+	int instance;
+
+	imx8mp_get_boot_source(&src, &instance);
+	switch (src) {
+	case BOOTSOURCE_MMC:
+		imx8mp_esdhc_load_image(instance, bl33);
+		break;
+	case BOOTSOURCE_SERIAL:
+		imx8mp_romapi_load_image(bl33);
+		break;
+	case BOOTSOURCE_SPI:
+		imx8mp_qspi_load_image(instance, bl33);
+		break;
+	default:
+		printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
+		hang();
+	}
+
+
+	/*
+	 * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
+	 * in EL2. Copy the image there, but replace the PBL part of
+	 * that image with ourselves. On a high assurance boot only the
+	 * currently running code is validated and contains the checksum
+	 * for the piggy data, so we need to ensure that we are running
+	 * the same code in DRAM.
+	 */
+	memcpy(bl33, __image_start, barebox_pbl_size);
+}
+
+__noreturn void imx8mp_load_and_start_image_via_tfa(void)
+{
+	__imx8mp_load_and_start_image_via_tfa((void *)MX8M_ATF_BL33_BASE_ADDR);
+}
+
+__noreturn void __imx8mp_load_and_start_image_via_tfa(void *bl33)
+{
+	const void *bl31;
+	size_t bl31_size;
+	unsigned long endmem = MX8M_DDR_CSD1_BASE_ADDR + imx8m_barebox_earlymem_size(32);
+
+	imx_set_cpu_type(IMX_CPU_IMX8MP);
+	imx8mp_init_scratch_space();
+	imx8m_save_bootrom_log();
+	imx8mp_load_bl33(bl33);
+
+	if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MP_OPTEE)) {
+		void *bl32 = (void *)arm_mem_optee(endmem);
+		size_t bl32_size;
+		void *bl32_image;
+
+		imx8m_tzc380_init();
+		get_builtin_firmware_ext(imx8mp_bl32_bin,
+				bl33, &bl32_image,
+				&bl32_size);
+
+		imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size);
+
+		memcpy(bl32, bl32_image, bl32_size);
+
+		get_builtin_firmware(imx8mp_bl31_bin_optee, &bl31, &bl31_size);
+	} else {
+		get_builtin_firmware(imx8mp_bl31_bin, &bl31, &bl31_size);
+	}
+
+	imx8m_atf_start_bl31(bl31, bl31_size, (void *)MX8MP_ATF_BL31_BASE_ADDR);
+}
+
+
+void imx8mn_load_bl33(void *bl33)
+{
+	enum bootsource src;
+	int instance;
+
+	imx8mn_get_boot_source(&src, &instance);
+	switch (src) {
+	case BOOTSOURCE_MMC:
+		imx8mn_esdhc_load_image(instance, bl33);
+		break;
+	case BOOTSOURCE_SERIAL:
+		imx8mn_romapi_load_image(bl33);
+		break;
+	case BOOTSOURCE_SPI:
+		imx8mn_qspi_load_image(instance, bl33);
+		break;
+	default:
+		printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
+		hang();
+	}
+
+
+	/*
+	 * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
+	 * in EL2. Copy the image there, but replace the PBL part of
+	 * that image with ourselves. On a high assurance boot only the
+	 * currently running code is validated and contains the checksum
+	 * for the piggy data, so we need to ensure that we are running
+	 * the same code in DRAM.
+	 */
+	memcpy(bl33, __image_start, barebox_pbl_size);
+}
+
+__noreturn void imx8mn_load_and_start_image_via_tfa(void)
+{
+	__imx8mn_load_and_start_image_via_tfa((void *)MX8M_ATF_BL33_BASE_ADDR);
+}
+
+__noreturn void __imx8mn_load_and_start_image_via_tfa(void *bl33)
+{
+	const void *bl31;
+	size_t bl31_size;
+	unsigned long endmem = MX8M_DDR_CSD1_BASE_ADDR + imx8m_barebox_earlymem_size(16);
+
+	imx_set_cpu_type(IMX_CPU_IMX8MN);
+	imx8mn_init_scratch_space();
+	imx8m_save_bootrom_log();
+	imx8mn_load_bl33(bl33);
+
+	if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MN_OPTEE)) {
+		void *bl32 = (void *)arm_mem_optee(endmem);
+		size_t bl32_size;
+		void *bl32_image;
+
+		imx8m_tzc380_init();
+		get_builtin_firmware_ext(imx8mn_bl32_bin,
+				bl33, &bl32_image,
+				&bl32_size);
+
+		imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size);
+
+		memcpy(bl32, bl32_image, bl32_size);
+
+		get_builtin_firmware(imx8mn_bl31_bin_optee, &bl31, &bl31_size);
+	} else {
+		get_builtin_firmware(imx8mn_bl31_bin, &bl31, &bl31_size);
+	}
+
+	imx8m_atf_start_bl31(bl31, bl31_size, (void *)MX8MN_ATF_BL31_BASE_ADDR);
+}
+
+void imx8mq_load_bl33(void *bl33)
+{
+	enum bootsource src;
+	int instance;
+
+	imx8mq_get_boot_source(&src, &instance);
+	switch (src) {
+	case BOOTSOURCE_MMC:
+		imx8m_esdhc_load_image(instance, bl33);
+		break;
+	default:
+		printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
+		hang();
+	}
+
+
+	/*
+	 * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
+	 * in EL2. Copy the image there, but replace the PBL part of
+	 * that image with ourselves. On a high assurance boot only the
+	 * currently running code is validated and contains the checksum
+	 * for the piggy data, so we need to ensure that we are running
+	 * the same code in DRAM.
+	 */
+	memcpy(bl33, __image_start, barebox_pbl_size);
 }
 
-void imx8mm_atf_load_bl31(const void *fw, size_t fw_size)
+__noreturn void imx8mq_load_and_start_image_via_tfa(void)
 {
-	imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MM_ATF_BL31_BASE_ADDR);
+	__imx8mq_load_and_start_image_via_tfa((void *)MX8M_ATF_BL33_BASE_ADDR);
 }
 
-void imx8mp_atf_load_bl31(const void *fw, size_t fw_size)
+__noreturn void __imx8mq_load_and_start_image_via_tfa(void *bl33)
 {
-	imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MP_ATF_BL31_BASE_ADDR);
+	const void *bl31;
+	size_t bl31_size;
+	unsigned long endmem = MX8M_DDR_CSD1_BASE_ADDR + imx8m_barebox_earlymem_size(32);
+
+	imx_set_cpu_type(IMX_CPU_IMX8MQ);
+	imx8mq_init_scratch_space();
+	imx8m_save_bootrom_log();
+	imx8mq_load_bl33(bl33);
+
+	if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_OPTEE)) {
+		void *bl32 = (void *)arm_mem_optee(endmem);
+		size_t bl32_size;
+		void *bl32_image;
+
+		imx8m_tzc380_init();
+		get_builtin_firmware_ext(imx8mq_bl32_bin,
+				bl33, &bl32_image,
+				&bl32_size);
+
+		imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size);
+
+		memcpy(bl32, bl32_image, bl32_size);
+
+		get_builtin_firmware(imx8mq_bl31_bin_optee, &bl31, &bl31_size);
+	} else {
+		get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size);
+	}
+
+	imx8m_atf_start_bl31(bl31, bl31_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR);
 }
 
-void imx8mq_atf_load_bl31(const void *fw, size_t fw_size)
+void __noreturn imx93_load_and_start_image_via_tfa(void)
 {
-	imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR);
+	unsigned long atf_dest = MX93_ATF_BL31_BASE_ADDR;
+	void __noreturn (*bl31)(void) = (void *)atf_dest;
+	const void *tfa;
+	size_t tfa_size;
+	void *bl33 = (void *)MX93_ATF_BL33_BASE_ADDR;
+	unsigned long endmem = MX9_DDR_CSD1_BASE_ADDR + imx9_ddrc_sdram_size();
+
+	imx_set_cpu_type(IMX_CPU_IMX93);
+	imx93_init_scratch_space(true);
+
+	/*
+	 * On completion the TF-A will jump to MX93_ATF_BL33_BASE_ADDR
+	 * in EL2. Copy the image there, but replace the PBL part of
+	 * that image with ourselves. On a high assurance boot only the
+	 * currently running code is validated and contains the checksum
+	 * for the piggy data, so we need to ensure that we are running
+	 * the same code in DRAM.
+	 *
+	 * The second purpose of this memcpy is for USB booting. When booting
+	 * from USB the image comes in as a stream, so the PBL is transferred
+	 * only once. As we jump into the PBL again in SDRAM we need to copy
+	 * it there. The USB protocol transfers data in chunks of 1024 bytes,
+	 * so align the copy size up to the next 1KiB boundary.
+	 */
+	memcpy((void *)MX93_ATF_BL33_BASE_ADDR, __image_start, ALIGN(barebox_pbl_size, 1024));
+
+	if (IS_ENABLED(CONFIG_FIRMWARE_IMX93_OPTEE)) {
+		void *bl32 = (void *)arm_mem_optee(endmem);
+		size_t bl32_size;
+		void *bl32_image;
+
+		imx93_ele_load_fw(bl33);
+
+		get_builtin_firmware_ext(imx93_bl32_bin,
+				bl33, &bl32_image,
+				&bl32_size);
+
+		imx_adjust_optee_memory(&bl32, &bl32_image, &bl32_size);
+
+		memcpy(bl32, bl32_image, bl32_size);
+
+		get_builtin_firmware(imx93_bl31_bin_optee, &tfa, &tfa_size);
+	} else {
+		get_builtin_firmware(imx93_bl31_bin, &tfa, &tfa_size);
+	}
+
+	memcpy(bl31, tfa, tfa_size);
+
+	asm volatile("msr sp_el2, %0" : :
+		     "r" (MX93_ATF_BL33_BASE_ADDR - 16) :
+		     "cc");
+	bl31();
+	__builtin_unreachable();
 }
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index e9b5a49443..3fea22d05f 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -1,15 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
 #include <bootsource.h>
@@ -19,21 +8,23 @@
 #include <magicvar.h>
 
 #include <io.h>
-#include <mach/generic.h>
-#include <mach/imx25-regs.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx51-regs.h>
-#include <mach/imx53-regs.h>
-#include <mach/imx6-regs.h>
-#include <mach/imx7-regs.h>
-#include <mach/imx8mm-regs.h>
-#include <mach/imx8mp-regs.h>
-#include <mach/imx8mq-regs.h>
-#include <mach/vf610-regs.h>
-#include <mach/imx8mq.h>
-#include <mach/imx6.h>
-
+#include <mach/imx/clock-imx6.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx25-regs.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/imx35-regs.h>
+#include <mach/imx/imx51-regs.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx7-regs.h>
+#include <mach/imx/imx8mm-regs.h>
+#include <mach/imx/imx8mp-regs.h>
+#include <mach/imx/imx8mq-regs.h>
+#include <mach/imx/vf610-regs.h>
+#include <mach/imx/imx8mq.h>
+#include <mach/imx/imx6.h>
+
+#include <soc/fsl/fsl_udc.h>
 
 static void
 imx_boot_save_loc(void (*get_boot_source)(enum bootsource *, int *))
@@ -43,8 +34,7 @@ imx_boot_save_loc(void (*get_boot_source)(enum bootsource *, int *))
 
 	get_boot_source(&src, &instance);
 
-	bootsource_set(src);
-	bootsource_set_instance(instance);
+	bootsource_set(src, instance);
 }
 
 
@@ -212,7 +202,8 @@ void imx51_boot_save_loc(void)
 }
 
 #define IMX53_SRC_SBMR	0x4
-#define SRC_SBMR_BMOD	GENMASK(25, 24)
+#define IMX53_SRC_SBMR_BMOD	GENMASK(25, 24)
+#define IMX8MP_SRC_SBMR_BMOD	GENMASK(27, 24)
 #define IMX53_BMOD_SERIAL	0b11
 
 #define __BOOT_CFG(n, m, l)	GENMASK((m) + ((n) - 1) * 8, \
@@ -244,7 +235,17 @@ __MAKE_BOOT_CFG_BITS(4)
 
 static unsigned int imx53_get_bmod(uint32_t r)
 {
-	return FIELD_GET(SRC_SBMR_BMOD, r);
+	return FIELD_GET(IMX53_SRC_SBMR_BMOD, r);
+}
+
+static unsigned int imx8mp_get_bmod(uint32_t r)
+{
+	return FIELD_GET(IMX8MP_SRC_SBMR_BMOD, r);
+}
+
+static unsigned int imx8mm_get_bcfg(uint32_t r)
+{
+	return FIELD_GET(BOOT_CFG2(6, 4), r);
 }
 
 static int imx53_bootsource_internal(uint32_t r)
@@ -294,6 +295,8 @@ void imx53_get_boot_source(enum bootsource *src, int *instance)
 	default:
 		if (imx53_bootsource_nand(cfg1))
 			*src = BOOTSOURCE_NAND;
+		else
+			*src = BOOTSOURCE_UNKNOWN;
 		break;
 	}
 
@@ -316,8 +319,7 @@ void imx53_boot_save_loc(void)
 
 	imx53_get_boot_source(&src, &instance);
 
-	bootsource_set(src);
-	bootsource_set_instance(instance);
+	bootsource_set(src, instance);
 }
 
 #define IMX6_SRC_SBMR1	0x04
@@ -326,6 +328,9 @@ void imx53_boot_save_loc(void)
 #define IMX6_SRC_GPR10	0x44
 #define IMX6_BMOD_SERIAL	0b01
 #define IMX6_BMOD_RESERVED	0b11
+#define IMX8MM_BCFG_FSPI	0b100
+#define IMX8MP_BMOD_FUSES	0b0000
+#define IMX8MP_BMOD_SERIAL	0b0001
 #define IMX6_BMOD_FUSES		0b00
 #define BT_FUSE_SEL		BIT(4)
 #define GPR10_BOOT_FROM_GPR9	BIT(28)
@@ -347,6 +352,23 @@ static bool imx6_bootsource_serial(uint32_t sbmr2)
 		!(sbmr2 & BT_FUSE_SEL));
 }
 
+static bool imx8mp_bootsource_serial(uint32_t sbmr2)
+{
+	return imx8mp_get_bmod(sbmr2) == IMX8MP_BMOD_SERIAL ||
+		/*
+		 * If boot from fuses is selected and fuses are not
+		 * programmed by setting BT_FUSE_SEL, ROM code will
+		 * fallback to serial mode
+		 */
+		(imx8mp_get_bmod(sbmr2) == IMX8MP_BMOD_FUSES &&
+		 !(sbmr2 & BT_FUSE_SEL));
+}
+
+static bool imx8mm_bootsource_qspi(uint32_t sbmr1)
+{
+	return imx8mm_get_bcfg(sbmr1) == IMX8MM_BCFG_FSPI;
+}
+
 static bool imx6_bootsource_serial_forced(uint32_t bootmode)
 {
 	if (cpu_mx6_is_mx6ul() || cpu_mx6_is_mx6ull())
@@ -408,6 +430,11 @@ static u32 imx6_get_src_boot_mode(void __iomem *src_base)
 	return readl(src_base + IMX6_SRC_SBMR1);
 }
 
+static inline bool imx6_usboh3_clk_active(void)
+{
+	return (readl(MXC_CCM_CCGR6) & 0x3) == 0x3;
+}
+
 void imx6_get_boot_source(enum bootsource *src, int *instance)
 {
 	void __iomem *src_base = IOMEM(MX6_SRC_BASE_ADDR);
@@ -421,6 +448,26 @@ void imx6_get_boot_source(enum bootsource *src, int *instance)
 
 	bootsrc = imx53_bootsource_internal(bootmode);
 
+	/*
+	 * imx6_bootsource_serial() can't detect cases where the boot ROM
+	 * decided to use the serial downloader as a fall back (primary
+	 * boot source failed).
+	 *
+	 * Infer that the boot ROM used the USB serial downloader by
+	 * checking whether both the UDC and the clock enabling access
+	 * to its MMIO region are currently active...
+	 * This assumes:
+	 * - On fresh boots, PBL doesn't itself start a stopped UDC
+	 * - In barebox proper, boot source is saved before the UDC driver
+	 *   may enable the UDC
+	 */
+
+	if (imx6_usboh3_clk_active() &&
+	    is_chipidea_udc_running(IOMEM(MX6_OTG_BASE_ADDR))) {
+		*src = BOOTSOURCE_SERIAL;
+		return;
+	}
+
 	if (imx6_bootsource_serial(sbmr2) ||
 	    imx6_bootsource_serial_forced(bootsrc)) {
 		*src = BOOTSOURCE_SERIAL;
@@ -448,6 +495,8 @@ void imx6_get_boot_source(enum bootsource *src, int *instance)
 	default:
 		if (imx53_bootsource_nand(bootmode))
 			*src = BOOTSOURCE_NAND;
+		else
+			*src = BOOTSOURCE_UNKNOWN;
 		break;
 	}
 }
@@ -479,11 +528,6 @@ static void __imx7_get_boot_source(enum bootsource *src, int *instance,
 {
 	const struct imx_boot_sw_info *info;
 
-	if (imx6_bootsource_serial(sbmr2)) {
-		*src = BOOTSOURCE_SERIAL;
-		return;
-	}
-
 	info = (const void *)(unsigned long)
 		readl(boot_sw_info_pointer_addr);
 
@@ -502,14 +546,17 @@ static void __imx7_get_boot_source(enum bootsource *src, int *instance,
 		break;
 	case 4:
 		*src = BOOTSOURCE_SPI; /* Really: qspi */
+		*instance = info->boot_device_instance;
 		break;
 	case 5:
 		*src = BOOTSOURCE_NOR;
 		break;
-	case 15:
+	case 14: /* observed on i.MX8MP for USB "serial" booting */
+	case 15: /* observed on i.MX8MM for USB "serial" booting */
 		*src = BOOTSOURCE_SERIAL;
 		break;
 	default:
+		*src = BOOTSOURCE_UNKNOWN;
 		break;
 	}
 }
@@ -519,6 +566,11 @@ void imx7_get_boot_source(enum bootsource *src, int *instance)
 	void __iomem *src_base = IOMEM(MX7_SRC_BASE_ADDR);
 	uint32_t sbmr2 = readl(src_base + 0x70);
 
+	if (imx6_bootsource_serial(sbmr2)) {
+		*src = BOOTSOURCE_SERIAL;
+		return;
+	}
+
 	__imx7_get_boot_source(src, instance, IMX7_BOOT_SW_INFO_POINTER_ADDR,
 			       sbmr2);
 }
@@ -613,6 +665,8 @@ void vf610_get_boot_source(enum bootsource *src, int *instance)
 	default:
 		if (imx53_bootsource_nand(sbmr1))
 			*src = BOOTSOURCE_NAND;
+		else
+			*src = BOOTSOURCE_UNKNOWN;
 		break;
 	}
 }
@@ -632,6 +686,11 @@ void imx8mq_get_boot_source(enum bootsource *src, int *instance)
 		IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0 :
 		IMX8M_BOOT_SW_INFO_POINTER_ADDR_B0;
 
+	if (imx6_bootsource_serial(sbmr2)) {
+		*src = BOOTSOURCE_SERIAL;
+		return;
+	}
+
 	__imx7_get_boot_source(src, instance, addr, sbmr2);
 }
 
@@ -644,11 +703,26 @@ void imx8mm_get_boot_source(enum bootsource *src, int *instance)
 {
 	unsigned long addr;
 	void __iomem *src_base = IOMEM(MX8MM_SRC_BASE_ADDR);
+	uint32_t sbmr1 = readl(src_base + 0x58);
 	uint32_t sbmr2 = readl(src_base + 0x70);
 
+	if (imx6_bootsource_serial(sbmr2)) {
+		*src = BOOTSOURCE_SERIAL;
+		return;
+	}
+
 	addr = IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0;
 
 	__imx7_get_boot_source(src, instance, addr, sbmr2);
+
+	if (*src != BOOTSOURCE_UNKNOWN)
+		return;
+
+	if (imx8mm_bootsource_qspi(sbmr1)) {
+		*src = BOOTSOURCE_SPI; /* Really: qspi */
+		*instance = 0;
+		return;
+	}
 }
 
 void imx8mm_boot_save_loc(void)
@@ -662,6 +736,11 @@ void imx8mp_get_boot_source(enum bootsource *src, int *instance)
 	void __iomem *src_base = IOMEM(MX8MP_SRC_BASE_ADDR);
 	uint32_t sbmr2 = readl(src_base + 0x70);
 
+	if (imx8mp_bootsource_serial(sbmr2)) {
+		*src = BOOTSOURCE_SERIAL;
+		return;
+	}
+
 	addr = IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0;
 
 	__imx7_get_boot_source(src, instance, addr, sbmr2);
@@ -671,3 +750,9 @@ void imx8mp_boot_save_loc(void)
 {
 	imx_boot_save_loc(imx8mp_get_boot_source);
 }
+
+void imx8mn_get_boot_source(enum bootsource *src, int *instance)
+	__alias(imx8mp_get_boot_source);
+
+void imx8mn_boot_save_loc(void)
+	__alias(imx8mp_boot_save_loc);
diff --git a/arch/arm/mach-imx/bootrom-cmd.c b/arch/arm/mach-imx/bootrom-cmd.c
new file mode 100644
index 0000000000..08e393b01a
--- /dev/null
+++ b/arch/arm/mach-imx/bootrom-cmd.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <command.h>
+#include <errno.h>
+#include <getopt.h>
+#include <printk.h>
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <mach/imx/imx8m-regs.h>
+#include <mach/imx/romapi.h>
+
+/* i.MX7 and later ID field is swapped compared to i.MX6 */
+#define ROM_EVENT_FORMAT_V0_RES	GENMASK(31, 24)
+#define ROM_EVENT_FORMAT_V0_ID	GENMASK(23, 0)
+#define ROM_EVENT_FORMAT_V1_ID	GENMASK(31, 24)
+#define		ROM_EVENT_FORMAT_V1_ID_TYPE	GENMASK(31, 28)
+#define		ROM_EVENT_FORMAT_V1_ID_IDX	GENMASK(27, 24)
+#define ROM_EVENT_FORMAT_V1_RES	GENMASK(23, 0)
+
+static const char *lookup(const char *table[], size_t table_size, size_t idx)
+{
+	const char *str = NULL;
+
+	if (idx < table_size)
+		str = table[idx];
+
+	return str ?: "unknown";
+}
+
+#define LOOKUP(table, idx) lookup(table, ARRAY_SIZE(table), idx)
+
+static const char *boot_mode_0x1y[] = {
+	"Fuse", "Serial Download", "Internal Download", "Test Mode"
+};
+
+static const char *secure_config_0x2y[] = {
+	"FAB", "Field Return", "Open", "Closed"
+};
+
+static const char *boot_image_0x5y[] = {
+	"primary", "secondary"
+};
+
+static const char *boot_device_0x6y[] = {
+	"RAW NAND", "SD or EMMC", NULL, NULL, "ECSPI NOR", NULL, NULL, "QSPI NOR"
+};
+
+/* Parse the ROM event ID defintion version 1 log, see AN12853 */
+static int imx8m_bootrom_decode_log(const u32 *rom_log)
+{
+	int i;
+
+	if (!rom_log)
+		return -ENODATA;
+
+	for (i = 0; i < 128; i++) {
+		u8 event_id = FIELD_GET(ROM_EVENT_FORMAT_V1_ID, rom_log[i]);
+		u8 event_id_idx = FIELD_GET(ROM_EVENT_FORMAT_V1_ID_IDX, rom_log[i]);
+		const char *arg = NULL;
+
+		printf("[%02x] ", event_id);
+		switch (event_id) {
+		case 0x0:
+			printf("End of list\n");
+			return 0;
+		case 0x01:
+			printf("ROM event version 0x%02x\n", rom_log[i] & 0xFF);
+			continue;
+
+		case 0x10 ... 0x13:
+			printf("Boot mode is Boot from %s\n",
+			       LOOKUP(boot_mode_0x1y, event_id_idx));
+			continue;
+
+		case 0x20 ... 0x23:
+			printf("Secure config is %s\n",
+			       LOOKUP(secure_config_0x2y, event_id_idx));
+			continue;
+
+		case 0x30 ... 0x31:
+		case 0xe0:
+			printf("Internal use\n");
+			continue;
+
+		case 0x40 ... 0x41:
+			printf("FUSE_SEL_VALUE Fuse is %sblown\n",
+			       event_id_idx ? "" : "not ");
+			continue;
+
+		case 0x50 ... 0x51:
+			printf("Boot from the %s boot image\n",
+			       LOOKUP(boot_image_0x5y, event_id_idx));
+			continue;
+
+		case 0x74:
+			arg = "SPI NAND";
+			fallthrough;
+		case 0x60 ... 0x67:
+			printf("Primary boot from %s device\n",
+			       arg ?: LOOKUP(boot_device_0x6y, event_id_idx));
+			continue;
+
+		case 0x71:
+			printf("Recovery boot from ECSPI NOR device\n");
+			continue;
+		case 0x72:
+			printf("No Recovery boot device\n");
+			continue;
+		case 0x73:
+			printf("Manufacture boot from SD or EMMC\n");
+			continue;
+
+		case 0x80:
+			printf("Start to perform the device initialization: @%u ticks\n",
+			       rom_log[++i]);
+			continue;
+		case 0x81:
+			printf("The boot device initialization completes: @%u ticks\n",
+			       rom_log[++i]);
+			continue;
+		case 0x82:
+			printf("Start to execute boot device driver pre-config @%u ticks\n",
+			       rom_log[++i]);
+			continue;
+		case 0x83:
+			printf("Boot device driver pre-config completes\n");
+			continue;
+		case 0x8E:
+			printf("Boot device driver pre-config fails\n");
+			continue;
+		case 0x8f:
+			printf("boot device initialization fails: @%u ticks\n",
+			       rom_log[++i]);
+			continue;
+
+		case 0x90:
+			printf("Start to read data from boot device: @ offset %08x\n",
+			       rom_log[++i]);
+			continue;
+		case 0x91:
+			printf("Reading data from boot device completes: @%u ticks\n",
+			       rom_log[++i]);
+			continue;
+		case 0x9f:
+			printf("Reading data from boot device fails: @%u ticks\n",
+			       rom_log[++i]);
+			continue;
+
+		case 0xa0:
+			printf("Image authentication result: %s(0x%08x) @%u ticks\n",
+			       (rom_log[i+1] & 0xFF) == 0xF0 ? "PASS " : "",
+			       rom_log[i+1], rom_log[i+2]);
+			i += 2;
+			continue;
+		case 0xa1:
+			printf("IVT header is not valid\n");
+			continue;
+
+		case 0xc0:
+			printf("Jump to the boot image soon: @ offset 0x%08x @ %u ticks\n",
+			       rom_log[i+1], rom_log[i+2]);
+			i += 2;
+			continue;
+
+		case 0xd0:
+			printf("Enters serial download processing\n");
+			continue;
+
+		case 0xf0:
+			printf("Enters ROM exception handler\n");
+			continue;
+		default:
+			printf("Unknown\n");
+			continue;
+		}
+	}
+
+	return -EILSEQ;
+}
+
+static int do_bootrom(int argc, char *argv[])
+{
+	union {
+		const u32 *ptr;
+		ulong addr;
+	} rom_log = { NULL };
+	bool log = false;
+	int ret, opt;
+
+	while((opt = getopt(argc, argv, "la:")) > 0) {
+		switch(opt) {
+		case 'a':
+			ret = kstrtoul(optarg, 0, &rom_log.addr);
+			if (ret)
+				return ret;
+		case 'l':
+			log = true;
+			break;
+		default:
+			return COMMAND_ERROR_USAGE;
+		}
+	}
+
+	if (!rom_log.addr)
+		rom_log.ptr = imx8m_get_bootrom_log();
+
+	if (log)
+		return imx8m_bootrom_decode_log(rom_log.ptr);
+
+	return COMMAND_ERROR_USAGE;
+}
+
+BAREBOX_CMD_HELP_START(bootrom)
+BAREBOX_CMD_HELP_TEXT("List information about the specified files or directories.")
+BAREBOX_CMD_HELP_TEXT("")
+BAREBOX_CMD_HELP_TEXT("Options:")
+BAREBOX_CMD_HELP_OPT ("-l",  "list event log")
+BAREBOX_CMD_HELP_OPT ("-a ADDR",  "event log address (default PBL scratch space)")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(bootrom)
+	.cmd            = do_bootrom,
+	BAREBOX_CMD_DESC("Interact with BootROM on i.MX8M")
+	BAREBOX_CMD_OPTS("[-la]")
+	BAREBOX_CMD_HELP(cmd_bootrom_help)
+	BAREBOX_CMD_GROUP(CMD_GRP_INFO)
+BAREBOX_CMD_END
diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index 9d86353e22..c5a47d9b91 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -1,27 +1,17 @@
-/*
- * Copyright (C) 2014 Lucas Stach, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix
 
 #include <common.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/errata.h>
 #include <linux/types.h>
 #include <linux/bitops.h>
-#include <mach/generic.h>
-#include <mach/imx7-regs.h>
-#include <mach/imx8mq-regs.h>
-#include <mach/imx8m-ccm-regs.h>
-#include <common.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx7-regs.h>
+#include <mach/imx/imx8mq-regs.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/imx9-regs.h>
+#include <mach/imx/trdc.h>
 #include <io.h>
 #include <asm/syscounter.h>
 #include <asm/system.h>
@@ -61,6 +51,7 @@ void imx6ul_cpu_lowlevel_init(void)
 
 void imx7_cpu_lowlevel_init(void)
 {
+	cortex_a7_lowlevel_init();
 	arm_cpu_lowlevel_init();
 	imx_cpu_timer_init(IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR));
 }
@@ -86,13 +77,54 @@ void imx8mm_cpu_lowlevel_init(void)
 	imx8m_cpu_lowlevel_init();
 }
 
+void imx8mn_cpu_lowlevel_init(void)
+	__alias(imx8mm_cpu_lowlevel_init);
+
 void imx8mp_cpu_lowlevel_init(void)
+	__alias(imx8mm_cpu_lowlevel_init);
+
+void imx8mq_cpu_lowlevel_init(void)
 {
 	imx8m_cpu_lowlevel_init();
 }
 
-void imx8mq_cpu_lowlevel_init(void)
+#define CCM_AUTHEN_TZ_NS	BIT(9)
+
+#define OSCPLLa_AUTHEN(n)		(0x5030  + (n) * 0x40) /* 0..18 */
+#define CLOCK_ROOT_AUTHEN(n)		(0x30  + (n) * 0x80) /* 0..94 */
+#define LPCGa_AUTHEN(n)			(0x8030 + (n) * 0x40) /* 0..126 */
+#define GPR_SHARED0_AUTHEN(n)		(0x4810 + (n) * 0x10) /* 0..3 */
+#define SET 4
+
+#define SRC_SP_ISO_CTRL			0x10c
+
+void imx93_cpu_lowlevel_init(void)
 {
-	imx8m_cpu_lowlevel_init();
+	void __iomem *ccm = IOMEM(MX9_CCM_BASE_ADDR);
+	void __iomem *src = IOMEM(MX9_SRC_BASE_ADDR);
+	int i;
+
+	arm_cpu_lowlevel_init();
+
+	if (current_el() != 3)
+		return;
+
+	imx9_trdc_init();
+
+	imx_cpu_timer_init(IOMEM(MX9_SYSCNT_CTRL_BASE_ADDR));
+
+	for (i = 0; i <= 18; i++)
+		writel(CCM_AUTHEN_TZ_NS, ccm + OSCPLLa_AUTHEN(i) + SET);
+	for (i = 0; i <= 94; i++)
+		writel(CCM_AUTHEN_TZ_NS, ccm + CLOCK_ROOT_AUTHEN(i) + SET);
+	for (i = 0; i <= 126 ; i++)
+		writel(CCM_AUTHEN_TZ_NS, ccm + LPCGa_AUTHEN(i) + SET);
+	for (i = 0; i <= 3 ; i++)
+		writel(CCM_AUTHEN_TZ_NS, ccm + GPR_SHARED0_AUTHEN(i) + SET);
+
+	/* clear isolation for usbphy, dsi, csi*/
+	writel(0x0, src + SRC_SP_ISO_CTRL);
+
 }
+
 #endif
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index a0609e282a..7572738d0e 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -1,94 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <driver.h>
-#include <mach/devices.h>
+#include <mach/imx/devices.h>
 
-static inline struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata)
+static inline struct device *imx_add_device(char *name, int id, void *base, int size, void *pdata)
 {
 	return add_generic_device(name, id, NULL, (resource_size_t)base, size,
 				  IORESOURCE_MEM, pdata);
 }
 
-struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata)
+struct device *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata)
 {
 	return imx_add_device("imx27-fec", -1, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata)
+struct device *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata)
 {
 	return imx_add_device("imx6-fec", -1, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_spi_imx27(void *base, int id, struct spi_imx_master *pdata)
+struct device *imx_add_spi_imx27(void *base, int id, struct spi_imx_master *pdata)
 {
 	return imx_add_device("imx27-spi", id, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_spi_imx35(void *base, int id, struct spi_imx_master *pdata)
+struct device *imx_add_spi_imx35(void *base, int id, struct spi_imx_master *pdata)
 {
 	return imx_add_device("imx35-spi", id, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_spi_imx51(void *base, int id, struct spi_imx_master *pdata)
+struct device *imx_add_spi_imx51(void *base, int id, struct spi_imx_master *pdata)
 {
 	return imx_add_device("imx51-spi", id, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata)
+struct device *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata)
 {
 	return imx_add_device("i2c-fsl", id, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_uart_imx1(void *base, int id)
+struct device *imx_add_uart_imx1(void *base, int id)
 {
 	return imx_add_device("imx1-uart", id, base, 0x1000, NULL);
 }
 
-struct device_d *imx_add_uart_imx21(void *base, int id)
+struct device *imx_add_uart_imx21(void *base, int id)
 {
 	return imx_add_device("imx21-uart", id, base, 0x1000, NULL);
 }
 
-struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata)
+struct device *imx_add_nand(void *base, struct imx_nand_platform_data *pdata)
 {
 	return imx_add_device("imx_nand", -1, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata)
+struct device *imx_add_fb(void *base, struct imx_fb_platform_data *pdata)
 {
 	return imx_add_device("imxfb", -1, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata)
+struct device *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata)
 {
 	return imx_add_device("imx-ipu-fb", -1, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_mmc(void *base, int id, void *pdata)
+struct device *imx_add_mmc(void *base, int id, void *pdata)
 {
 	return imx_add_device("imx-mmc", id, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_esdhc_imx25(void *base, int id, struct esdhc_platform_data *pdata)
+struct device *imx_add_esdhc_imx25(void *base, int id, struct esdhc_platform_data *pdata)
 {
 	return imx_add_device("imx25-esdhc", id, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_esdhc_imx5(void *base, int id, struct esdhc_platform_data *pdata)
+struct device *imx_add_esdhc_imx5(void *base, int id, struct esdhc_platform_data *pdata)
 {
 	return imx_add_device("imx5-esdhc", id, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_kpp(void *base, struct matrix_keymap_data *pdata)
+struct device *imx_add_kpp(void *base, struct matrix_keymap_data *pdata)
 {
        return imx_add_device("imx-kpp", -1, base, 0x1000, pdata);
 }
 
-struct device_d *imx_add_pata(void *base)
+struct device *imx_add_pata(void *base)
 {
 	return imx_add_device("imx-pata", -1, base, 0x1000, NULL);
 }
 
-struct device_d *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata)
+struct device *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata)
 {
 	return imx_add_device("imx-usb", id, base, 0x200, pdata);
 }
diff --git a/arch/arm/mach-imx/ele.c b/arch/arm/mach-imx/ele.c
new file mode 100644
index 0000000000..48e8749b31
--- /dev/null
+++ b/arch/arm/mach-imx/ele.c
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020-2022 NXP
+ */
+#define pr_fmt(fmt) "ele: " fmt
+
+#include <common.h>
+#include <io.h>
+#include <mach/imx/ele.h>
+#include <mach/imx/imx9-regs.h>
+#include <linux/iopoll.h>
+#include <firmware.h>
+#include <linux/bitfield.h>
+
+#define MU_SR_TE0_MASK		BIT(0)
+#define MU_SR_RF0_MASK		BIT(0)
+#define MU_TR_COUNT		8
+#define MU_RR_COUNT		4
+
+struct mu_type {
+	u32 ver;
+	u32 par;
+	u32 cr;
+	u32 sr;
+	u32 reserved0[60];
+	u32 fcr;
+	u32 fsr;
+	u32 reserved1[2];
+	u32 gier;
+	u32 gcr;
+	u32 gsr;
+	u32 reserved2;
+	u32 tcr;
+	u32 tsr;
+	u32 rcr;
+	u32 rsr;
+	u32 reserved3[52];
+	u32 tr[16];
+	u32 reserved4[16];
+	u32 rr[16];
+	u32 reserved5[14];
+	u32 mu_attr;
+};
+
+static int mu_hal_sendmsg(void __iomem *base, u32 reg_index, u32 msg)
+{
+	struct mu_type *mu_base = base;
+	u32 mask = MU_SR_TE0_MASK << reg_index;
+	u32 val;
+	int ret;
+
+	/* Wait TX register to be empty. */
+	ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000);
+	if (ret < 0) {
+		pr_debug("%s timeout\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	writel(msg, &mu_base->tr[reg_index]);
+
+	return 0;
+}
+
+static int mu_hal_receivemsg(void __iomem *base, u32 reg_index, u32 *msg)
+{
+	struct mu_type *mu_base = base;
+	u32 mask = MU_SR_RF0_MASK << reg_index;
+	u32 val;
+	int ret;
+
+	/* Wait RX register to be full. */
+	ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000000);
+	if (ret < 0)
+		return -ETIMEDOUT;
+
+	*msg = readl(&mu_base->rr[reg_index]);
+
+	return 0;
+}
+
+static int mu_read(void __iomem *base, struct ele_msg *msg)
+{
+	int ret, i;
+
+	/* Read first word */
+	ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
+	if (ret)
+		return ret;
+
+	/* Read remaining words */
+	for (i = 1; i < msg->size; i++) {
+		ret = mu_hal_receivemsg(base, i % MU_RR_COUNT, &msg->data[i - 1]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int mu_write(void __iomem *base, struct ele_msg *msg)
+{
+	int ret, i;
+
+	/* Write first word */
+	ret = mu_hal_sendmsg(base, 0, *((u32 *)msg));
+	if (ret)
+		return ret;
+
+	/* Write remaining words */
+	for (i = 1; i < msg->size; i++) {
+		ret = mu_hal_sendmsg(base, i % MU_TR_COUNT, msg->data[i - 1]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int imx9_s3mua_call(struct ele_msg *msg)
+{
+	void __iomem *s3mua = IOMEM(MX9_S3MUA_BASE_ADDR);
+	u32 result;
+	int ret;
+
+	ret = mu_write(s3mua, msg);
+	if (ret)
+		return ret;
+
+	ret = mu_read(s3mua, msg);
+	if (ret)
+		return ret;
+
+	result = msg->data[0];
+	if ((result & 0xff) == 0xd6)
+		return 0;
+
+	return -EIO;
+}
+
+int ele_call(struct ele_msg *msg)
+{
+	return imx9_s3mua_call(msg);
+}
+
+int ele_get_info(struct ele_get_info_data *info)
+{
+        struct ele_msg msg = {
+		.version = ELE_VERSION,
+		.tag = ELE_CMD_TAG,
+		.size = 4,
+		.command = ELE_GET_INFO_REQ,
+		.data = {
+			upper_32_bits((unsigned long)info),
+			lower_32_bits((unsigned long)info),
+			sizeof(struct ele_get_info_data),
+		},
+	};
+	int ret;
+
+	ret = ele_call(&msg);
+	if (ret)
+		pr_err("Could not get ELE info: ret %d, response 0x%x\n",
+			ret, msg.data[0]);
+
+	return ret;
+}
+
+static int ele_get_start_trng(void)
+{
+	struct ele_msg msg = {
+		.version = ELE_VERSION,
+		.tag = ELE_CMD_TAG,
+		.size = 1,
+		.command = ELE_START_RNG,
+	};
+	int ret;
+
+	ret = ele_call(&msg);
+	if (ret)
+		pr_err("Could not start TRNG, response 0x%x\n", msg.data[0]);
+
+	return ret;
+}
+
+int imx93_ele_load_fw(void *bl33)
+{
+	struct ele_get_info_data info = {};
+	struct ele_msg msg = {
+		.version = ELE_VERSION,
+		.tag = ELE_CMD_TAG,
+		.size = 4,
+		.command = ELE_FW_AUTH_REQ,
+	};
+	void *firmware;
+	int size, ret;
+	int rev = 0;
+
+	ele_get_info(&info);
+
+	rev = FIELD_GET(ELE_INFO_SOC_REV, info.soc);
+
+	switch (rev) {
+	case 0xa0:
+		get_builtin_firmware_ext(mx93a0_ahab_container_img, bl33, &firmware, &size);
+		break;
+	case 0xa1:
+		get_builtin_firmware_ext(mx93a1_ahab_container_img, bl33, &firmware, &size);
+		break;
+	default:
+		pr_err("Unknown unhandled SoC revision %2x\n", rev);
+		return -EINVAL;
+	}
+
+	/* Address of the container header */
+	msg.data[0] = lower_32_bits((unsigned long)firmware);
+	/* Actual address of the container header */
+	msg.data[2] = lower_32_bits((unsigned long)firmware);
+
+	ret = ele_call(&msg);
+	if (ret)
+		pr_err("Could not start ELE firmware: ret %d, response 0x%x\n",
+			ret, msg.data[0]);
+
+	if (rev >= 0xa1)
+		ele_get_start_trng();
+
+	return 0;
+}
+
+/*
+ * ele_read_common_fuse - read a fuse
+ * @fuse_id: The fuse to read (in 32bit word number)
+ * fuse_word: The value read from the fuse
+ * @response: on return contains the response from ELE
+ *
+ * This reads the shadow value of the fuse @fuse_id.
+ *
+ * Return: 0 when the ELE call succeeds, negative error code otherwise
+ */
+int ele_read_common_fuse(u16 fuse_id, u32 *fuse_word, u32 *response)
+{
+	struct ele_msg msg;
+	int ret;
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_READ_FUSE_REQ;
+	msg.data[0] = fuse_id;
+
+	ret = imx9_s3mua_call(&msg);
+
+	if (response)
+		*response = msg.data[0];
+
+	*fuse_word = msg.data[1];
+
+	return ret;
+}
+
+/*
+ * ele_read_shadow_fuse - read a fuse
+ * @fuse_id: The fuse to read (in 32bit word number)
+ * fuse_word: The value read from the fuse
+ * @response: on return contains the response from ELE
+ *
+ * This reads the shadow value of the fuse @fuse_id.
+ *
+ * Return: 0 when the ELE call succeeds, negative error code otherwise
+ */
+int ele_read_shadow_fuse(u16 fuse_id, u32 *fuse_word, u32 *response)
+{
+	struct ele_msg msg;
+	int ret;
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_READ_SHADOW_REQ;
+	msg.data[0] = fuse_id;
+
+	ret = imx9_s3mua_call(&msg);
+
+	if (response)
+		*response = msg.data[0];
+
+	*fuse_word = msg.data[1];
+
+	return ret;
+}
+
+/*
+ * ele_write_fuse - write a fuse
+ * @fuse_id: The fuse to write to (in 32bit word number)
+ * @fuse_val: The value to write to the fuse
+ * @lock: lock fuse after writing
+ * @response: on return contains the response from ELE
+ *
+ * This writes the 32bit given in @fuse_val to the fuses at @fuse_id. This is
+ * a permanent change, be careful.
+ *
+ * Return: 0 when the ELE call succeeds, negative error code otherwise
+ */
+int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
+{
+	struct ele_msg msg;
+	int ret;
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 3;
+	msg.command = ELE_WRITE_FUSE_REQ;
+	msg.data[0] = (32 << 16) | (fuse_id << 5);
+
+	if (lock)
+		msg.data[0] |= (1 << 31);
+
+	msg.data[1] = fuse_val;
+
+	ret = imx9_s3mua_call(&msg);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+/*
+ * ele_write_shadow_fuse - write a fuse
+ * @fuse_id: The fuse to write to
+ * @fuse_val: The value to write to the fuse
+ * @lock: lock fuse after writing
+ * @response: on return contains the response from ELE
+ *
+ * This writes the 32bit given in @fuse_val to the fuses at @fuse_id. This is
+ * a permanent change, be careful.
+ *
+ * Return: 0 when the ELE call succeeds, negative error code otherwise
+ */
+int ele_write_shadow_fuse(u16 fuse_id, u32 fuse_val, u32 *response)
+{
+	struct ele_msg msg;
+	int ret;
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 3;
+	msg.command = ELE_WRITE_SHADOW_REQ;
+	msg.data[0] = fuse_id;
+
+	msg.data[1] = fuse_val;
+
+	ret = imx9_s3mua_call(&msg);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+/*
+ * ele_forward_lifecycle - forward lifecycle
+ * @lc: The lifecycle value to forward to
+ * @response: on return contains the response from ELE
+ *
+ * This changes the chip's lifecycle value. Mainly useful to forward to
+ * from ELE_LIFECYCLE_OEM_OPEN to ELE_LIFECYCLE_OEM_CLOSED. When doing
+ * this the SoC will only boot authenticated images. Make sure the correct
+ * SRK has been fused beforehand, otherwise you brick your board.
+ *
+ * Return: 0 when the ELE call succeeds, negative error code otherwise
+ */
+int ele_forward_lifecycle(enum ele_lifecycle lc, u32 *response)
+{
+	struct ele_msg msg;
+	int ret;
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_FWD_LIFECYCLE_UP_REQ;
+	msg.data[0] = lc;
+
+	ret = imx9_s3mua_call(&msg);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+/*
+ * ele_authenticate_container - authenticate a container image
+ * @addr: the address of the container
+ * @response: on return contains the response from ELE
+ *
+ * This authenticates a container with the ELE. On return the result
+ * of the authentication will be encoded in @response
+ *
+ * Return: 0 when the ELE call succeeds, negative error code otherwise
+ */
+int ele_authenticate_container(unsigned long addr, u32 *response)
+{
+	struct ele_msg msg;
+	int ret;
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 3;
+	msg.command = ELE_OEM_CNTN_AUTH_REQ;
+	msg.data[0] = upper_32_bits(addr);
+	msg.data[1] = lower_32_bits(addr);
+
+	ret = imx9_s3mua_call(&msg);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+/*
+ * ele_release_container - release a container image
+ * @response: on return contains the response from ELE
+ *
+ * This releases a container image. Must be called when done with an
+ * image previously authenticated with ele_authenticate_container()
+ *
+ * Return: 0 when the ELE call succeeds, negative error code otherwise
+ */
+int ele_release_container(u32 *response)
+{
+	struct ele_msg msg;
+	int ret;
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_RELEASE_CONTAINER_REQ;
+
+	ret = imx9_s3mua_call(&msg);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response)
+{
+	struct ele_msg msg;
+	int ret;
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_RELEASE_RDC_REQ;
+
+	switch (xrdc) {
+	case 0:
+		msg.data[0] = (0x74 << 8) | core_id;
+		break;
+	case 1:
+		msg.data[0] = (0x78 << 8) | core_id;
+		break;
+	case 2:
+		msg.data[0] = (0x82 << 8) | core_id;
+		break;
+	case 3:
+		msg.data[0] = (0x86 << 8) | core_id;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = ele_call(&msg);
+	if (ret)
+		pr_err("%s: ret %d, core id %u, response 0x%x\n",
+			__func__, ret, core_id, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+struct ele_str {
+	u8 id;
+	const char *str;
+};
+
+static struct ele_str ele_ind[] = {
+	{ .id = ELE_ROM_PING_FAILURE_IND, .str = "ELE_ROM_PING_FAILURE" },
+	{ .id = ELE_FW_PING_FAILURE_IND, .str = "ELE_FW_PING_FAILURE" },
+	{ .id = ELE_BAD_SIGNATURE_FAILURE_IND, .str = "ELE_BAD_SIGNATURE_FAILURE" },
+	{ .id = ELE_BAD_HASH_FAILURE_IND, .str = "ELE_BAD_HASH_FAILURE" },
+	{ .id = ELE_INVALID_LIFECYCLE_IND, .str = "ELE_INVALID_LIFECYCLE" },
+	{ .id = ELE_PERMISSION_DENIED_FAILURE_IND, .str = "ELE_PERMISSION_DENIED_FAILURE" },
+	{ .id = ELE_INVALID_MESSAGE_FAILURE_IND, .str = "ELE_INVALID_MESSAGE_FAILURE" },
+	{ .id = ELE_BAD_VALUE_FAILURE_IND, .str = "ELE_BAD_VALUE_FAILURE" },
+	{ .id = ELE_BAD_FUSE_ID_FAILURE_IND, .str = "ELE_BAD_FUSE_ID_FAILURE" },
+	{ .id = ELE_BAD_CONTAINER_FAILURE_IND, .str = "ELE_BAD_CONTAINER_FAILURE" },
+	{ .id = ELE_BAD_VERSION_FAILURE_IND, .str = "ELE_BAD_VERSION_FAILURE" },
+	{ .id = ELE_INVALID_KEY_FAILURE_IND, .str = "ELE_INVALID_KEY_FAILURE" },
+	{ .id = ELE_BAD_KEY_HASH_FAILURE_IND, .str = "ELE_BAD_KEY_HASH_FAILURE" },
+	{ .id = ELE_NO_VALID_CONTAINER_FAILURE_IND, .str = "ELE_NO_VALID_CONTAINER_FAILURE" },
+	{ .id = ELE_BAD_CERTIFICATE_FAILURE_IND, .str = "ELE_BAD_CERTIFICATE_FAILURE" },
+	{ .id = ELE_BAD_UID_FAILURE_IND, .str = "ELE_BAD_UID_FAILURE" },
+	{ .id = ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND, .str = "ELE_BAD_MONOTONIC_COUNTER_FAILURE" },
+	{ .id = ELE_MUST_SIGNED_FAILURE_IND, .str = "ELE_MUST_SIGNED_FAILURE" },
+	{ .id = ELE_NO_AUTHENTICATION_FAILURE_IND, .str = "ELE_NO_AUTHENTICATION_FAILURE" },
+	{ .id = ELE_BAD_SRK_SET_FAILURE_IND, .str = "ELE_BAD_SRK_SET_FAILURE" },
+	{ .id = ELE_UNALIGNED_PAYLOAD_FAILURE_IND, .str = "ELE_UNALIGNED_PAYLOAD_FAILURE" },
+	{ .id = ELE_WRONG_SIZE_FAILURE_IND, .str = "ELE_WRONG_SIZE_FAILURE" },
+	{ .id = ELE_ENCRYPTION_FAILURE_IND, .str = "ELE_ENCRYPTION_FAILURE" },
+	{ .id = ELE_DECRYPTION_FAILURE_IND, .str = "ELE_DECRYPTION_FAILURE" },
+	{ .id = ELE_OTP_PROGFAIL_FAILURE_IND, .str = "ELE_OTP_PROGFAIL_FAILURE" },
+	{ .id = ELE_OTP_LOCKED_FAILURE_IND, .str = "ELE_OTP_LOCKED_FAILURE" },
+	{ .id = ELE_OTP_INVALID_IDX_FAILURE_IND, .str = "ELE_OTP_INVALID_IDX_FAILURE" },
+	{ .id = ELE_TIME_OUT_FAILURE_IND, .str = "ELE_TIME_OUT_FAILURE" },
+	{ .id = ELE_BAD_PAYLOAD_FAILURE_IND, .str = "ELE_BAD_PAYLOAD_FAILURE" },
+	{ .id = ELE_WRONG_ADDRESS_FAILURE_IND, .str = "ELE_WRONG_ADDRESS_FAILURE" },
+	{ .id = ELE_DMA_FAILURE_IND, .str = "ELE_DMA_FAILURE" },
+	{ .id = ELE_DISABLED_FEATURE_FAILURE_IND, .str = "ELE_DISABLED_FEATURE_FAILURE" },
+	{ .id = ELE_MUST_ATTEST_FAILURE_IND, .str = "ELE_MUST_ATTEST_FAILURE" },
+	{ .id = ELE_RNG_NOT_STARTED_FAILURE_IND, .str = "ELE_RNG_NOT_STARTED_FAILURE" },
+	{ .id = ELE_CRC_ERROR_IND, .str = "ELE_CRC_ERROR" },
+	{ .id = ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND, .str = "ELE_AUTH_SKIPPED_OR_FAILED_FAILURE" },
+	{ .id = ELE_INCONSISTENT_PAR_FAILURE_IND, .str = "ELE_INCONSISTENT_PAR_FAILURE" },
+	{ .id = ELE_RNG_INST_FAILURE_FAILURE_IND, .str = "ELE_RNG_INST_FAILURE_FAILURE" },
+	{ .id = ELE_LOCKED_REG_FAILURE_IND, .str = "ELE_LOCKED_REG_FAILURE" },
+	{ .id = ELE_BAD_ID_FAILURE_IND, .str = "ELE_BAD_ID_FAILURE" },
+	{ .id = ELE_INVALID_OPERATION_FAILURE_IND, .str = "ELE_INVALID_OPERATION_FAILURE" },
+	{ .id = ELE_NON_SECURE_STATE_FAILURE_IND, .str = "ELE_NON_SECURE_STATE_FAILURE" },
+	{ .id = ELE_MSG_TRUNCATED_IND, .str = "ELE_MSG_TRUNCATED" },
+	{ .id = ELE_BAD_IMAGE_NUM_FAILURE_IND, .str = "ELE_BAD_IMAGE_NUM_FAILURE" },
+	{ .id = ELE_BAD_IMAGE_ADDR_FAILURE_IND, .str = "ELE_BAD_IMAGE_ADDR_FAILURE" },
+	{ .id = ELE_BAD_IMAGE_PARAM_FAILURE_IND, .str = "ELE_BAD_IMAGE_PARAM_FAILURE" },
+	{ .id = ELE_BAD_IMAGE_TYPE_FAILURE_IND, .str = "ELE_BAD_IMAGE_TYPE_FAILURE" },
+	{ .id = ELE_CORRUPTED_SRK_FAILURE_IND, .str = "ELE_CORRUPTED_SRK_FAILURE" },
+	{ .id = ELE_OUT_OF_MEMORY_IND, .str = "ELE_OUT_OF_MEMORY" },
+	{ .id = ELE_CSTM_FAILURE_IND, .str = "ELE_CSTM_FAILURE" },
+	{ .id = ELE_OLD_VERSION_FAILURE_IND, .str = "ELE_OLD_VERSION_FAILURE" },
+	{ .id = ELE_WRONG_BOOT_MODE_FAILURE_IND, .str = "ELE_WRONG_BOOT_MODE_FAILURE" },
+	{ .id = ELE_APC_ALREADY_ENABLED_FAILURE_IND, .str = "ELE_APC_ALREADY_ENABLED_FAILURE" },
+	{ .id = ELE_RTC_ALREADY_ENABLED_FAILURE_IND, .str = "ELE_RTC_ALREADY_ENABLED_FAILURE" },
+	{ .id = ELE_ABORT_IND, .str = "ELE_ABORT" },
+};
+
+static struct ele_str ele_ipc[] = {
+	{ .id = ELE_IPC_MU_RTD, .str = "MU RTD" },
+	{ .id = ELE_IPC_MU_APD, .str = "MU APD" },
+};
+
+static struct ele_str ele_command[] = {
+	{ .id = ELE_PING_REQ, .str = "ELE_PING" },
+	{ .id = ELE_FW_AUTH_REQ, .str = "ELE_FW_AUTH" },
+	{ .id = ELE_RESTART_RST_TIMER_REQ, .str = "ELE_RESTART_RST_TIMER" },
+	{ .id = ELE_DUMP_DEBUG_BUFFER_REQ, .str = "ELE_DUMP_DEBUG_BUFFER" },
+	{ .id = ELE_OEM_CNTN_AUTH_REQ, .str = "ELE_OEM_CNTN_AUTH" },
+	{ .id = ELE_VERIFY_IMAGE_REQ, .str = "ELE_VERIFY_IMAGE" },
+	{ .id = ELE_RELEASE_CONTAINER_REQ, .str = "ELE_RELEASE_CONTAINER" },
+	{ .id = ELE_WRITE_SECURE_FUSE_REQ, .str = "ELE_WRITE_SECURE_FUSE" },
+	{ .id = ELE_FWD_LIFECYCLE_UP_REQ, .str = "ELE_FWD_LIFECYCLE_UP" },
+	{ .id = ELE_READ_FUSE_REQ, .str = "ELE_READ_FUSE" },
+	{ .id = ELE_GET_FW_VERSION_REQ, .str = "ELE_GET_FW_VERSION" },
+	{ .id = ELE_RET_LIFECYCLE_UP_REQ, .str = "ELE_RET_LIFECYCLE_UP" },
+	{ .id = ELE_GET_EVENTS_REQ, .str = "ELE_GET_EVENTS" },
+	{ .id = ELE_ENABLE_PATCH_REQ, .str = "ELE_ENABLE_PATCH" },
+	{ .id = ELE_RELEASE_RDC_REQ, .str = "ELE_RELEASE_RDC" },
+	{ .id = ELE_GET_FW_STATUS_REQ, .str = "ELE_GET_FW_STATUS" },
+	{ .id = ELE_ENABLE_OTFAD_REQ, .str = "ELE_ENABLE_OTFAD" },
+	{ .id = ELE_RESET_REQ, .str = "ELE_RESET" },
+	{ .id = ELE_UPDATE_OTP_CLKDIV_REQ, .str = "ELE_UPDATE_OTP_CLKDIV" },
+	{ .id = ELE_POWER_DOWN_REQ, .str = "ELE_POWER_DOWN" },
+	{ .id = ELE_ENABLE_APC_REQ, .str = "ELE_ENABLE_APC" },
+	{ .id = ELE_ENABLE_RTC_REQ, .str = "ELE_ENABLE_RTC" },
+	{ .id = ELE_DEEP_POWER_DOWN_REQ, .str = "ELE_DEEP_POWER_DOWN" },
+	{ .id = ELE_STOP_RST_TIMER_REQ, .str = "ELE_STOP_RST_TIMER" },
+	{ .id = ELE_WRITE_FUSE_REQ, .str = "ELE_WRITE_FUSE" },
+	{ .id = ELE_RELEASE_CAAM_REQ, .str = "ELE_RELEASE_CAAM" },
+	{ .id = ELE_RESET_A35_CTX_REQ, .str = "ELE_RESET_A35_CTX" },
+	{ .id = ELE_MOVE_TO_UNSECURED_REQ, .str = "ELE_MOVE_TO_UNSECURED" },
+	{ .id = ELE_GET_INFO_REQ, .str = "ELE_GET_INFO" },
+	{ .id = ELE_ATTEST_REQ, .str = "ELE_ATTEST" },
+	{ .id = ELE_RELEASE_PATCH_REQ, .str = "ELE_RELEASE_PATCH" },
+	{ .id = ELE_OTP_SEQ_SWITH_REQ, .str = "ELE_OTP_SEQ_SWITH" },
+};
+
+static struct ele_str ele_status[] = {
+	{ .id = ELE_SUCCESS_IND, .str = "ELE_SUCCESS" },
+	{ .id = ELE_FAILURE_IND, .str = "ELE_FAILURE" },
+};
+
+static const struct ele_str *get_idx(struct ele_str *str, int size, int id)
+{
+	u32 i;
+
+	for (i = 0; i < size; i++) {
+		if (str[i].id == id)
+			return &str[i];
+	}
+
+	return NULL;
+}
+
+#define ELE_EVENT_IPC		GENMASK(31, 24)
+#define ELE_EVENT_COMMAND	GENMASK(23, 16)
+#define ELE_EVENT_IND		GENMASK(15, 8)
+#define ELE_EVENT_STATUS	GENMASK(7, 0)
+
+static void display_event(u32 event)
+{
+	int ipc = FIELD_GET(ELE_EVENT_IPC, event);
+	int command = FIELD_GET(ELE_EVENT_COMMAND, event);
+	int ind = FIELD_GET(ELE_EVENT_IND, event);
+	int status = FIELD_GET(ELE_EVENT_STATUS, event);
+	const struct ele_str *ipc_str = get_idx(ARRAY_AND_SIZE(ele_ipc), ipc);
+	const struct ele_str *command_str = get_idx(ARRAY_AND_SIZE(ele_command), command);
+	const struct ele_str *ind_str = get_idx(ARRAY_AND_SIZE(ele_ind), ind);
+	const struct ele_str *status_str = get_idx(ARRAY_AND_SIZE(ele_status), status);
+
+	pr_info("Event 0x%08x:\n", event);
+	pr_info("  IPC = %s (0x%02x)\n", ipc_str ? ipc_str->str : "INVALID", ipc);
+	pr_info("  CMD = %s (0x%02x)\n", command_str ? command_str->str : "INVALID", command);
+	pr_info("  IND = %s (0x%02x)\n", ind_str ? ind_str->str : "INVALID", ind);
+	pr_info("  STA = %s (0x%02x)\n", status_str ? status_str->str : "INVALID", status);
+}
+
+#define AHAB_MAX_EVENTS 8
+
+static int ahab_get_events(u32 *events)
+{
+	struct ele_msg msg;
+	int ret, i = 0;
+	u32 n_events;
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_GET_EVENTS_REQ;
+
+	ret = imx9_s3mua_call(&msg);
+	if (ret) {
+		pr_err("%s: ret %d, response 0x%x\n", __func__, ret, msg.data[0]);
+
+		return ret;
+	}
+
+	n_events = msg.data[1] & 0xffff;
+
+	if (n_events > AHAB_MAX_EVENTS)
+		n_events = AHAB_MAX_EVENTS;
+
+	for (; i < n_events; i++)
+		events[i] = msg.data[i + 2];
+
+	return n_events;
+}
+
+unsigned int imx93_ahab_read_lifecycle(void)
+{
+	return readl(MX9_OCOTP_BASE_ADDR + 0x41c) & 0x3ff;
+}
+
+static const char *ele_life_cycle(u32 lc)
+{
+	switch (lc) {
+	case ELE_LIFECYCLE_BLANK: return "BLANK";
+	case ELE_LIFECYCLE_FAB: return "FAB";
+	case ELE_LIFECYCLE_NXP_PROVISIONED: return "NXP Provisioned";
+	case ELE_LIFECYCLE_OEM_OPEN: return "OEM Open";
+	case ELE_LIFECYCLE_OEM_CLOSED: return "OEM closed";
+	case ELE_LIFECYCLE_FIELD_RETURN_OEM: return "Field Return OEM";
+	case ELE_LIFECYCLE_FIELD_RETURN_NXP: return "Field Return NXP";
+	case ELE_LIFECYCLE_OEM_LOCKED: return "OEM Locked";
+	case ELE_LIFECYCLE_BRICKED: return "BRICKED";
+	default: return "Unknown";
+	}
+}
+
+int ele_print_events(void)
+{
+	unsigned int lc;
+	u32 events[AHAB_MAX_EVENTS];
+	int i, ret;
+
+	lc = imx93_ahab_read_lifecycle();
+	pr_info("Current lifecycle: %s\n", ele_life_cycle(lc));
+
+	ret = ahab_get_events(events);
+	if (ret < 0)
+		return ret;
+
+	if (!ret) {
+		pr_info("No Events Found!\n");
+		return 0;
+	}
+
+	for (i = 0; i < ret; i++)
+		display_event(events[i]);
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/esdctl-v4.c b/arch/arm/mach-imx/esdctl-v4.c
index d9f6e919a1..26f476f0f5 100644
--- a/arch/arm/mach-imx/esdctl-v4.c
+++ b/arch/arm/mach-imx/esdctl-v4.c
@@ -1,22 +1,12 @@
-/*
- * esdctl-v4.c - i.MX sdram controller functions for i.MX53
- *
- * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+
+/* esdctl-v4.c - i.MX sdram controller functions for i.MX53 */
 
 #include <common.h>
 #include <io.h>
-#include <mach/esdctl-v4.h>
-#include <mach/imx53-regs.h>
+#include <mach/imx/esdctl-v4.h>
+#include <mach/imx/imx53-regs.h>
 #include <asm/system.h>
 
 void imx_esdctlv4_do_write_leveling(void)
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 135a16d111..701ca0ac1f 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -1,17 +1,7 @@
-/*
- * esdctl.c - i.MX sdram controller functions
- *
- * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+
+/* esdctl.c - i.MX sdram controller functions */
 
 #include <common.h>
 #include <io.h>
@@ -23,26 +13,29 @@
 #include <linux/bitfield.h>
 #include <asm/barebox-arm.h>
 #include <asm/memory.h>
-#include <mach/esdctl.h>
-#include <mach/esdctl-v4.h>
-#include <mach/imx6-mmdc.h>
-#include <mach/imx1-regs.h>
-#include <mach/imx21-regs.h>
-#include <mach/imx25-regs.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx31-regs.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx51-regs.h>
-#include <mach/imx53-regs.h>
-#include <mach/imx6-regs.h>
-#include <mach/vf610-ddrmc.h>
-#include <mach/imx8m-regs.h>
-#include <mach/imx7-regs.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/esdctl-v4.h>
+#include <mach/imx/imx6-mmdc.h>
+#include <mach/imx/imx1-regs.h>
+#include <mach/imx/imx21-regs.h>
+#include <mach/imx/imx25-regs.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/imx31-regs.h>
+#include <mach/imx/imx35-regs.h>
+#include <mach/imx/imx51-regs.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/vf610-ddrmc.h>
+#include <mach/imx/imx8m-regs.h>
+#include <mach/imx/imx7-regs.h>
+#include <mach/imx/imx9-regs.h>
+#include <mach/imx/scratch.h>
+#include <tee/optee.h>
 
 struct imx_esdctl_data {
 	unsigned long base0;
 	unsigned long base1;
-	void (*add_mem)(void *esdctlbase, struct imx_esdctl_data *);
+	int (*add_mem)(void *esdctlbase, struct imx_esdctl_data *);
 };
 
 static int imx_esdctl_disabled;
@@ -192,9 +185,11 @@ static inline u64 __imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs)
 	return memory_sdram_size(cols, rows, banks, width);
 }
 
-static void add_mem(unsigned long base0, unsigned long size0,
+static int add_mem(unsigned long base0, unsigned long size0,
 		unsigned long base1, unsigned long size1)
 {
+	int ret0 = 0, ret1 = 0;
+
 	debug("%s: cs0 base: 0x%08lx cs0 size: 0x%08lx\n", __func__, base0, size0);
 	debug("%s: cs1 base: 0x%08lx cs1 size: 0x%08lx\n", __func__, base1, size1);
 
@@ -202,16 +197,16 @@ static void add_mem(unsigned long base0, unsigned long size0,
 		/*
 		 * concatenate both chip selects to a single bank
 		 */
-		arm_add_mem_device("ram0", base0, size0 + size1);
-
-		return;
+		return arm_add_mem_device("ram0", base0, size0 + size1);
 	}
 
 	if (size0)
-		arm_add_mem_device("ram0", base0, size0);
+		ret0 = arm_add_mem_device("ram0", base0, size0);
 
 	if (size1)
-		arm_add_mem_device(size0 ? "ram1" : "ram0", base1, size1);
+		ret1 = arm_add_mem_device(size0 ? "ram1" : "ram0", base1, size1);
+
+	return ret0 ? ret0 : ret1;
 }
 
 /*
@@ -234,35 +229,35 @@ static inline void imx_esdctl_v2_disable_default(void __iomem *esdctlbase)
 	}
 }
 
-static void imx_esdctl_v1_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v1_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
 {
-	add_mem(data->base0, imx_v1_sdram_size(esdctlbase, 0),
+	return add_mem(data->base0, imx_v1_sdram_size(esdctlbase, 0),
 			data->base1, imx_v1_sdram_size(esdctlbase, 1));
 }
 
-static void imx_esdctl_v2_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v2_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
 {
-	add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0),
+	return add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0),
 			data->base1, imx_v2_sdram_size(esdctlbase, 1));
 }
 
-static void imx_esdctl_v2_bug_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v2_bug_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
 {
 	imx_esdctl_v2_disable_default(esdctlbase);
 
-	add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0),
+	return add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0),
 			data->base1, imx_v2_sdram_size(esdctlbase, 1));
 }
 
-static void imx_esdctl_v3_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v3_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
 {
-	add_mem(data->base0, imx_v3_sdram_size(esdctlbase, 0),
+	return add_mem(data->base0, imx_v3_sdram_size(esdctlbase, 0),
 			data->base1, imx_v3_sdram_size(esdctlbase, 1));
 }
 
-static void imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
 {
-	add_mem(data->base0, imx_v4_sdram_size(esdctlbase, 0),
+	return add_mem(data->base0, imx_v4_sdram_size(esdctlbase, 0),
 			data->base1, imx_v4_sdram_size(esdctlbase, 1));
 }
 
@@ -291,9 +286,9 @@ static inline resource_size_t imx6_mmdc_sdram_size(void __iomem *mmdcbase)
 	return size;
 }
 
-static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static int imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 {
-	arm_add_mem_device("ram0", data->base0,
+	return arm_add_mem_device("ram0", data->base0,
 			   imx6_mmdc_sdram_size(mmdcbase));
 }
 
@@ -313,9 +308,9 @@ static inline resource_size_t vf610_ddrmc_sdram_size(void __iomem *ddrmc)
 	return memory_sdram_size(cols, rows, banks, width);
 }
 
-static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 {
-	arm_add_mem_device("ram0", data->base0,
+	return arm_add_mem_device("ram0", data->base0,
 			   vf610_ddrmc_sdram_size(mmdcbase));
 }
 
@@ -325,9 +320,11 @@ static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 #define DDRC_ADDRMAP0_CS_BIT0			GENMASK(4, 0)
 
 #define DDRC_MSTR				0x0000
+#define DDRC_MSTR_DDR4				BIT(4)
 #define DDRC_MSTR_LPDDR4			BIT(5)
 #define DDRC_MSTR_DATA_BUS_WIDTH		GENMASK(13, 12)
 #define DDRC_MSTR_ACTIVE_RANKS			GENMASK(27, 24)
+#define DDRC_MSTR_DEVICE_CONFIG		GENMASK(31, 30)
 
 #define DDRC_ADDRMAP0_CS_BIT1			GENMASK(12,  8)
 
@@ -354,24 +351,31 @@ static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 #define DDRC_ADDRMAP7_ROW_B17			GENMASK(11,  8)
 #define DDRC_ADDRMAP7_ROW_B16			GENMASK( 3,  0)
 
+#define DDRC_ADDRMAP8_BG_B1			GENMASK(13,  8)
+#define DDRC_ADDRMAP8_BG_B0			GENMASK(4,  0)
+
+#define DDRC_ADDRMAP_LENGTH			9
+
 static unsigned int
 imx_ddrc_count_bits(unsigned int bits, const u8 config[],
 		     unsigned int config_num)
 {
 	unsigned int i;
-	for (i = 0; i < config_num && config[i] == 0b1111; i++)
-		bits--;
+
+	for (i = 0; i < config_num; i++) {
+		if (config[i] == 0b1111)
+			bits--;
+	}
 
 	return bits;
 }
 
 static resource_size_t
-imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
+imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[DDRC_ADDRMAP_LENGTH],
 		    u8 col_max, const u8 col_b[], unsigned int col_b_num,
 		    u8 row_max, const u8 row_b[], unsigned int row_b_num,
-		    bool reduced_adress_space)
+		    bool reduced_adress_space, unsigned int mstr)
 {
-	const u32 mstr = readl(ddrc + DDRC_MSTR);
 	unsigned int banks, ranks, columns, rows, active_ranks, width;
 	resource_size_t size;
 
@@ -392,15 +396,22 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
 		BUG();
 	}
 
+	/*
+	 * mstr is ignored for some SoCs/RAM types and may yield wrong
+	 * results when used for calculation. Callers of this function
+	 * are expected to fix it up as necessary.
+	 * Bus width in bytes, 0 means half byte or 4-bit mode
+	 */
+	width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1;
+
 	switch (FIELD_GET(DDRC_MSTR_DATA_BUS_WIDTH, mstr)) {
 	case 0b00:	/* Full DQ bus  */
-		width = 4;
 		break;
-	case 0b01:      /* Half DQ bus  */
-		width = 2;
+	case 0b01:	/* Half DQ bus  */
+		width >>= 1;
 		break;
 	case 0b10:	/* Quarter DQ bus  */
-		width = 1;
+		width >>= 2;
 		break;
 	default:
 		BUG();
@@ -417,17 +428,43 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
 	if (FIELD_GET(DDRC_ADDRMAP1_BANK_B2, addrmap[1]) != 0b11111)
 		banks++;
 
+	if (mstr & DDRC_MSTR_DDR4) {
+		/* FIXME: DDR register spreasheet claims this to be
+		 * 6-bit and 63 meaning bank group address bit 0 is 0,
+		 * but reference manual claims 5-bit without 'neutral' value
+		 * See MX8M_Mini_DDR4_RPA_v17, MX8M_Nano_DDR4_RPA_v8
+		 */
+		if (FIELD_GET(DDRC_ADDRMAP8_BG_B0, addrmap[8]) != 0b11111)
+			banks++;
+		if (FIELD_GET(DDRC_ADDRMAP8_BG_B1, addrmap[8]) != 0b111111)
+			banks++;
+	}
+
 	columns = imx_ddrc_count_bits(col_max, col_b, col_b_num);
 	rows    = imx_ddrc_count_bits(row_max, row_b, row_b_num);
 
-	size = memory_sdram_size(columns, rows, 1 << banks, width) << ranks;
+	/*
+	 * Special case when bus width is 0 or x4 mode,
+	 * calculate the mem size and then divide the size by 2.
+	 */
+	if (width)
+		size = memory_sdram_size(columns, rows, 1 << banks, width);
+	else
+		size = memory_sdram_size(columns, rows, 1 << banks, 1) >> 1;
+	size <<= ranks;
 
 	return reduced_adress_space ? size * 3 / 4 : size;
 }
 
-static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
+static void imx_ddrc_set_mstr_device_config(u32 *mstr, unsigned bits)
 {
-	const u32 addrmap[] = {
+	*mstr &= ~DDRC_MSTR_DEVICE_CONFIG;
+	*mstr |= FIELD_PREP(DDRC_MSTR_DEVICE_CONFIG, fls(bits / 8));
+}
+
+static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc, unsigned buswidth)
+{
+	const u32 addrmap[DDRC_ADDRMAP_LENGTH] = {
 		readl(ddrc + DDRC_ADDRMAP(0)),
 		readl(ddrc + DDRC_ADDRMAP(1)),
 		readl(ddrc + DDRC_ADDRMAP(2)),
@@ -435,7 +472,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
 		readl(ddrc + DDRC_ADDRMAP(4)),
 		readl(ddrc + DDRC_ADDRMAP(5)),
 		readl(ddrc + DDRC_ADDRMAP(6)),
-		readl(ddrc + DDRC_ADDRMAP(7))
+		readl(ddrc + DDRC_ADDRMAP(7)),
+		readl(ddrc + DDRC_ADDRMAP(8))
 	};
 	const u8 col_b[] = {
 		/*
@@ -453,15 +491,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
 		FIELD_GET(DDRC_ADDRMAP2_COL_B4,  addrmap[2]),
 	};
 	const u8 row_b[] = {
-		/*
-		 * FIXME: RM mentions the following fields as being
-		 * present, but looking at the code generated by DDR
-		 * tool it doesn't look like those registers are
-		 * really implemented/used.
-		 *
-		 * FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]),
-		 * FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]),
-		 */
+		FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]),
+		FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]),
 		FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]),
 		FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]),
 		FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]),
@@ -470,22 +501,105 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
 	};
 	const bool reduced_adress_space =
 		FIELD_GET(DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB, addrmap[6]);
+	u32 mstr = readl(ddrc + DDRC_MSTR);
+
+	/* Device config is ignored and taken as 32-bit for LPDDR4 */
+	if (mstr & DDRC_MSTR_LPDDR4)
+		imx_ddrc_set_mstr_device_config(&mstr, buswidth);
 
 	return imx_ddrc_sdram_size(ddrc, addrmap,
 				   12, ARRAY_AND_SIZE(col_b),
-				   16, ARRAY_AND_SIZE(row_b),
-				   reduced_adress_space);
+				   18, ARRAY_AND_SIZE(row_b),
+				   reduced_adress_space, mstr);
+}
+
+static int _imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data,
+			       unsigned int buswidth)
+{
+	resource_size_t size = imx8m_ddrc_sdram_size(mmdcbase, buswidth);
+	resource_size_t size0, size1;
+	int ret;
+
+	/*
+	 * Split the available memory into multiple banks if the device does
+	 * have more RAM than 3G. At the moment this is necessary to prevent
+	 * memory_bank_first_find_space() from finding free space near the end
+	 * of the 4G barrier which is the case in a 6G/8G setup. This is
+	 * important for larger barebox-pbl binaries (e.g. debug enabled) and
+	 * the barebox chainloading mechanism since the pbl init the MMU to 4G.
+	 * In this case a MMU exception will be thrown if the barebox-pbl is
+	 * placed near the 4G barrier.
+	 */
+	size0 = min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size);
+	size1 = size - size0;
+
+	ret = arm_add_mem_device("ram0", data->base0, size0);
+	if (ret || size1 == 0)
+		return ret;
+
+#ifdef CONFIG_64BIT
+	/*
+	 * Albeit this hook is called on 64bit machines only, the driver serves
+	 * 32bit machines as well. Guard the code to avoid compiler warnings.
+	 */
+	ret = arm_add_mem_device("ram1", SZ_4G, size1);
+#endif
+
+	return ret;
+}
+
+static int imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
+	return _imx8m_ddrc_add_mem(mmdcbase, data, 32);
+}
+
+static int imx8mn_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
+	return _imx8m_ddrc_add_mem(mmdcbase, data, 16);
+}
+
+#define IMX9_DDRC_CS_CONFIG(n)	(0x80 + (n) * 4)
+#define IMX9_DDRC_CS_ROW_BITS	GENMASK(10, 8)
+#define IMX9_DDRC_CS_COL_BITS	GENMASK(2, 0)
+#define IMX9_DDRC_CS_EN		BIT(31)
+
+resource_size_t imx9_ddrc_sdram_size(void)
+{
+	void __iomem *mmdcbase = IOMEM(MX9_DDR_CTL_BASE);
+	int width = 2;
+	int banks = 8;
+	resource_size_t mem = 0;
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		int rows, cols;
+		u32 cs, col_bits;
+
+		cs = readl(mmdcbase + IMX9_DDRC_CS_CONFIG(i));
+		if (!(cs & IMX9_DDRC_CS_EN))
+			continue;
+
+		rows = FIELD_GET(IMX9_DDRC_CS_ROW_BITS, cs) + 12;
+		col_bits = FIELD_GET(IMX9_DDRC_CS_COL_BITS, cs);
+		if (col_bits == 7)
+			cols = 7;
+		else
+			cols = col_bits + 8;
+
+		mem += memory_sdram_size(cols, rows, banks, width);
+	}
+
+	return mem;
 }
 
-static void imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static int imx9_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 {
-	arm_add_mem_device("ram0", data->base0,
-			   imx8m_ddrc_sdram_size(mmdcbase));
+	return arm_add_mem_device("ram0", data->base0, imx9_ddrc_sdram_size());
 }
 
 static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc)
 {
-	const u32 addrmap[] = {
+	const u32 addrmap[DDRC_ADDRMAP_LENGTH] = {
 		readl(ddrc + DDRC_ADDRMAP(0)),
 		readl(ddrc + DDRC_ADDRMAP(1)),
 		readl(ddrc + DDRC_ADDRMAP(2)),
@@ -512,20 +626,24 @@ static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc)
 	};
 	const bool reduced_adress_space =
 		FIELD_GET(DDRC_ADDRMAP6_LPDDR3_6GB_12GB, addrmap[6]);
+	u32 mstr = readl(ddrc + DDRC_MSTR);
+
+	/* Device config is unused on i.MX7, so rewrite it as 32-bit wide */
+	imx_ddrc_set_mstr_device_config(&mstr, 32);
 
 	return imx_ddrc_sdram_size(ddrc, addrmap,
 				   11, ARRAY_AND_SIZE(col_b),
 				   15, ARRAY_AND_SIZE(row_b),
-				   reduced_adress_space);
+				   reduced_adress_space, mstr);
 }
 
-static void imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static int imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 {
-	arm_add_mem_device("ram0", data->base0,
+	return arm_add_mem_device("ram0", data->base0,
 			   imx7d_ddrc_sdram_size(mmdcbase));
 }
 
-static int imx_esdctl_probe(struct device_d *dev)
+static int imx_esdctl_probe(struct device *dev)
 {
 	struct resource *iores;
 	struct imx_esdctl_data *data;
@@ -544,9 +662,7 @@ static int imx_esdctl_probe(struct device_d *dev)
 	if (imx_esdctl_disabled)
 		return 0;
 
-	data->add_mem(base, data);
-
-	return 0;
+	return data->add_mem(base, data);
 }
 
 static __maybe_unused struct imx_esdctl_data imx1_data = {
@@ -611,11 +727,21 @@ static __maybe_unused struct imx_esdctl_data vf610_data = {
 	.add_mem = vf610_ddrmc_add_mem,
 };
 
-static __maybe_unused struct imx_esdctl_data imx8mq_data = {
+static __maybe_unused struct imx_esdctl_data imx8m_data = {
 	.base0 = MX8M_DDR_CSD1_BASE_ADDR,
 	.add_mem = imx8m_ddrc_add_mem,
 };
 
+static __maybe_unused struct imx_esdctl_data imx8mn_data = {
+	.base0 = MX8M_DDR_CSD1_BASE_ADDR,
+	.add_mem = imx8mn_ddrc_add_mem,
+};
+
+static __maybe_unused struct imx_esdctl_data imx9_data = {
+	.base0 = MX9_DDR_CSD1_BASE_ADDR,
+	.add_mem = imx9_ddrc_add_mem,
+};
+
 static __maybe_unused struct imx_esdctl_data imx7d_data = {
 	.base0 = MX7_DDR_BASE_ADDR,
 	.add_mem = imx7d_ddrc_add_mem,
@@ -686,11 +812,14 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
 		.compatible = "fsl,vf610-ddrmc",
 		.data = &vf610_data
 	}, {
-		.compatible = "fsl,imx8mm-ddrc",
-		.data = &imx8mq_data
+		.compatible = "fsl,imx8m-ddrc",
+		.data = &imx8m_data
+	}, {
+		.compatible = "fsl,imx8mn-ddrc",
+		.data = &imx8mn_data
 	}, {
-		.compatible = "fsl,imx8mq-ddrc",
-		.data = &imx8mq_data
+		.compatible = "fsl,imx93-ddrc",
+		.data = &imx9_data
 	}, {
 		.compatible = "fsl,imx7d-ddrc",
 		.data = &imx7d_data
@@ -698,14 +827,14 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
 		/* sentinel */
 	}
 };
+MODULE_DEVICE_TABLE(of, imx_esdctl_dt_ids);
 
-static struct driver_d imx_esdctl_driver = {
+static struct driver imx_esdctl_driver = {
 	.name   = "imx-esdctl",
 	.probe  = imx_esdctl_probe,
 	.id_table = imx_esdctl_ids,
 	.of_compatible = DRV_OF_COMPAT(imx_esdctl_dt_ids),
 };
-
 mem_platform_driver(imx_esdctl_driver);
 
 /*
@@ -864,11 +993,11 @@ void __noreturn vf610_barebox_entry(void *boarddata)
 			  boarddata);
 }
 
-static void __noreturn imx8m_barebox_entry(void *boarddata)
+resource_size_t imx8m_barebox_earlymem_size(unsigned buswidth)
 {
 	resource_size_t size;
 
-	size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR));
+	size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR), buswidth);
 	/*
 	 * We artificially limit detected memory size to force malloc
 	 * pool placement to be within 4GiB address space, so as to
@@ -878,23 +1007,35 @@ static void __noreturn imx8m_barebox_entry(void *boarddata)
 	 * pool placement. The rest of the system should be able to
 	 * detect and utilize full amount of memory.
 	 */
-	size = min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size);
-	barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR, size, boarddata);
+	return min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size);
+}
+
+static void __noreturn imx8m_barebox_entry(void *boarddata, unsigned buswidth)
+{
+	imx8m_init_scratch_space(buswidth, false);
+	optee_set_membase(imx_scratch_get_optee_hdr());
+	barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR,
+			  imx8m_barebox_earlymem_size(buswidth), boarddata);
 }
 
 void __noreturn imx8mm_barebox_entry(void *boarddata)
 {
-	imx8m_barebox_entry(boarddata);
+	imx8m_barebox_entry(boarddata, 32);
+}
+
+void __noreturn imx8mn_barebox_entry(void *boarddata)
+{
+	imx8m_barebox_entry(boarddata, 16);
 }
 
 void __noreturn imx8mp_barebox_entry(void *boarddata)
 {
-	imx8m_barebox_entry(boarddata);
+	imx8m_barebox_entry(boarddata, 32);
 }
 
 void __noreturn imx8mq_barebox_entry(void *boarddata)
 {
-	imx8m_barebox_entry(boarddata);
+	imx8m_barebox_entry(boarddata, 32);
 }
 
 void __noreturn imx7d_barebox_entry(void *boarddata)
@@ -904,4 +1045,11 @@ void __noreturn imx7d_barebox_entry(void *boarddata)
 			  boarddata);
 }
 
+void __noreturn imx93_barebox_entry(void *boarddata)
+{
+	imx93_init_scratch_space(false);
+	optee_set_membase(imx_scratch_get_optee_hdr());
 
+	barebox_arm_entry(MX9_DDR_CSD1_BASE_ADDR,
+			  imx9_ddrc_sdram_size(), boarddata);
+}
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index 893bfdb77f..79cedbd68a 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -1,15 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
 #include <init.h>
@@ -20,14 +9,14 @@
 #include <asm/sections.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
-#include <mach/imx-nand.h>
-#include <mach/esdctl.h>
-#include <mach/generic.h>
-#include <mach/imx21-regs.h>
-#include <mach/imx25-regs.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx31-regs.h>
-#include <mach/imx35-regs.h>
+#include <mach/imx/imx-nand.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx21-regs.h>
+#include <mach/imx/imx25-regs.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/imx31-regs.h>
+#include <mach/imx/imx35-regs.h>
 
 #define BARE_INIT_FUNCTION(name)  \
 	__section(.text_bare_init_##name) \
diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c
index b60c5de7e1..f4581396b1 100644
--- a/arch/arm/mach-imx/iim.c
+++ b/arch/arm/mach-imx/iim.c
@@ -1,19 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2010 Baruch Siach <baruch@tkos.co.il>, Orex Computed Radiography
+
 /*
  * iim.c - i.MX IIM fusebox driver
  *
  * Provide an interface for programming and sensing the information that are
  * stored in on-chip fuse elements. This functionality is part of the IC
  * Identification Module (IIM), which is present on some i.MX CPUs.
- *
- * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
- * 	Orex Computed Radiography
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
  */
 
 #include <common.h>
@@ -26,15 +19,16 @@
 #include <malloc.h>
 #include <of.h>
 #include <io.h>
-#include <regmap.h>
+#include <linux/regmap.h>
 #include <regulator.h>
 #include <linux/err.h>
+#include <machine_id.h>
 
-#include <mach/iim.h>
-#include <mach/imx51-regs.h>
-#include <mach/imx53-regs.h>
-#include <mach/clock-imx51_53.h>
-#include <mach/imx25-fusemap.h>
+#include <mach/imx/iim.h>
+#include <mach/imx/imx51-regs.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/clock-imx51_53.h>
+#include <mach/imx/imx25-fusemap.h>
 
 #define DRIVERNAME	"imx_iim"
 #define IIM_NUM_BANKS	8
@@ -50,7 +44,7 @@ struct iim_bank {
 };
 
 struct iim_priv {
-	struct device_d dev;
+	struct device dev;
 	void __iomem *base;
 	void __iomem *bankbase;
 	struct iim_bank *bank[IIM_NUM_BANKS];
@@ -298,7 +292,7 @@ err_out:
 	return ret;
 }
 
-static ssize_t imx_iim_reg_write(void *ctx, unsigned int reg, unsigned int val)
+static int imx_iim_reg_write(void *ctx, unsigned int reg, unsigned int val)
 {
 	struct iim_bank *bank = ctx;
 
@@ -411,11 +405,11 @@ static void imx_iim_add_mac_param(struct iim_priv *iim, int macnum, int bank, in
  */
 #define MAC_ADDRESS_PROPLEN	(3 * sizeof(__be32))
 
-static void imx_iim_init_dt(struct device_d *dev, struct iim_priv *iim)
+static void imx_iim_init_dt(struct device *dev, struct iim_priv *iim)
 {
 	char mac[6];
 	const __be32 *prop;
-	struct device_node *node = dev->device_node;
+	struct device_node *node = dev->of_node;
 	int len, ret, macnum = 0;
 
 	if (!node)
@@ -449,12 +443,12 @@ static void imx_iim_init_dt(struct device_d *dev, struct iim_priv *iim)
 	}
 }
 #else
-static inline void imx_iim_init_dt(struct device_d *dev, struct iim_priv *iim)
+static inline void imx_iim_init_dt(struct device *dev, struct iim_priv *iim)
 {
 }
 #endif
 
-static int imx_iim_probe(struct device_d *dev)
+static int imx_iim_probe(struct device *dev)
 {
 	struct resource *iores;
 	struct iim_priv *iim;
@@ -511,6 +505,25 @@ static int imx_iim_probe(struct device_d *dev)
 	dev_add_param_bool(&iim->dev, "explicit_sense_enable",
 			NULL, NULL, &iim->sense_enable, NULL);
 
+	/* Maybe this is too strict? This might also work on i.MX31 and i.MX35 */
+	if (IS_ENABLED(CONFIG_MACHINE_ID) &&
+	    of_device_is_compatible(dev->of_node, "fsl,imx25-iim")) {
+		char uid[8];
+
+		for (i = 0; i < 8; ++i) {
+			unsigned int value;
+
+			ret = imx_iim_read_field(IMX25_IIM_UID(i), &value);
+			if (ret)
+				break;
+
+			uid[i] = value;
+		}
+
+		if (!ret)
+			machine_id_set_hashable(uid, 8);
+	}
+
 	return 0;
 }
 
@@ -579,8 +592,9 @@ static __maybe_unused struct of_device_id imx_iim_dt_ids[] = {
 		/* sentinel */
 	}
 };
+MODULE_DEVICE_TABLE(of, imx_iim_dt_ids);
 
-static struct driver_d imx_iim_driver = {
+static struct driver imx_iim_driver = {
 	.name	= DRIVERNAME,
 	.probe	= imx_iim_probe,
 	.of_compatible = DRV_OF_COMPAT(imx_iim_dt_ids),
diff --git a/arch/arm/mach-imx/imx-bbu-external-nand.c b/arch/arm/mach-imx/imx-bbu-external-nand.c
index 8aa4f152a1..7523008cdb 100644
--- a/arch/arm/mach-imx/imx-bbu-external-nand.c
+++ b/arch/arm/mach-imx/imx-bbu-external-nand.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+
 /*
  * imx-bbu-external-nand.c - i.MX specific update functions for external
  *			     nand boot
- *
- * Copyright (c) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <common.h>
@@ -25,8 +17,8 @@
 #include <linux/mtd/mtd-abi.h>
 #include <linux/stat.h>
 #include <ioctl.h>
-#include <mach/bbu.h>
-#include <mach/imx-nand.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/imx-nand.h>
 #include <asm/barebox-arm-head.h>
 
 static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_data *data)
@@ -37,9 +29,9 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
 	int size_available, size_need;
 	int ret;
 	uint32_t num_bb = 0, bbt = 0;
-	loff_t offset = 0;
+	loff_t nand_offset = 0, image_offset = 0;
 	int block = 0, len, now, blocksize;
-	void *image = data->image;
+	void *image = NULL;
 
 	ret = stat(data->devicefile, &s);
 	if (ret)
@@ -55,6 +47,12 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
 	if (ret)
 		goto out;
 
+	image = memdup(data->image, data->len);
+	if (!image) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
 	blocksize = meminfo.erasesize;
 
 	size_need = data->len;
@@ -63,27 +61,27 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
 	 * Collect bad blocks and construct BBT
 	 */
 	while (size_need > 0) {
-		ret = ioctl(fd, MEMGETBADBLOCK, &offset);
+		ret = ioctl(fd, MEMGETBADBLOCK, &nand_offset);
 		if (ret < 0)
 			goto out;
 
 		if (ret) {
-			if (!offset) {
+			if (!nand_offset) {
 				printf("1st block is bad. This is not supported\n");
 				ret = -EINVAL;
 				goto out;
 			}
 
-			debug("bad block at 0x%08llx\n", offset);
+			debug("bad block at 0x%08llx\n", nand_offset);
 			num_bb++;
 			bbt |= (1 << block);
-			offset += blocksize;
+			nand_offset += blocksize;
 			block++;
 			continue;
 		}
 		size_need -= blocksize;
 		size_available -= blocksize;
-		offset += blocksize;
+		nand_offset += blocksize;
 		block++;
 
 		if (size_available < 0) {
@@ -126,7 +124,7 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
 	}
 
 	len = data->len;
-	offset = 0;
+	nand_offset = 0;
 
 	/* last chance before erasing the flash */
 	ret = bbu_confirm(data);
@@ -139,13 +137,13 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
 	while (len > 0) {
 		now = min(len, blocksize);
 
-		ret = ioctl(fd, MEMGETBADBLOCK, &offset);
+		ret = ioctl(fd, MEMGETBADBLOCK, &nand_offset);
 		if (ret < 0)
 			goto out;
 
 		if (ret) {
-			offset += blocksize;
-			if (lseek(fd, offset, SEEK_SET) != offset) {
+			nand_offset += blocksize;
+			if (lseek(fd, nand_offset, SEEK_SET) != nand_offset) {
 				ret = -errno;
 				goto out;
 			}
@@ -153,25 +151,26 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
 			continue;
 		}
 
-		debug("writing %d bytes at 0x%08llx\n", now, offset);
+		debug("writing %d bytes at 0x%08llx\n", now, nand_offset);
 
-		ret = erase(fd, blocksize, offset);
+		ret = erase(fd, blocksize, nand_offset);
 		if (ret)
 			goto out;
 
-		ret = write(fd, image, now);
+		ret = write(fd, image + image_offset, now);
 		if (ret < 0)
 			goto out;
 
 		len -= now;
-		image += now;
-		offset += now;
+		image_offset += now;
+		nand_offset += now;
 	}
 
 	ret = 0;
 
 out:
 	close(fd);
+	free(image);
 
 	return ret;
 }
diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c
index c6d427a46c..8cdaab5c16 100644
--- a/arch/arm/mach-imx/imx-bbu-internal.c
+++ b/arch/arm/mach-imx/imx-bbu-internal.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+
 /*
  * imx-bbu-internal.c - i.MX specific update functions for internal boot
- *
- * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <common.h>
@@ -25,17 +17,17 @@
 #include <linux/stat.h>
 #include <ioctl.h>
 #include <environment.h>
-#include <mach/bbu.h>
-#include <mach/generic.h>
+#include <mach/imx/bbu.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx-header.h>
 #include <libfile.h>
 
-#define IMX_INTERNAL_FLAG_ERASE		BIT(30)
-
 struct imx_internal_bbu_handler {
 	struct bbu_handler handler;
 	int (*write_device)(struct imx_internal_bbu_handler *,
 			    struct bbu_data *);
 	unsigned long flash_header_offset;
+	unsigned long filetype_offset;
 	size_t device_size;
 	enum filetype expected_type;
 };
@@ -43,7 +35,7 @@ struct imx_internal_bbu_handler {
 static bool
 imx_bbu_erase_required(struct imx_internal_bbu_handler *imx_handler)
 {
-	return imx_handler->handler.flags & IMX_INTERNAL_FLAG_ERASE;
+	return imx_handler->handler.flags & IMX_BBU_FLAG_ERASE;
 }
 
 static int imx_bbu_protect(int fd, struct imx_internal_bbu_handler *imx_handler,
@@ -171,8 +163,8 @@ static int imx_bbu_check_prereq(struct imx_internal_bbu_handler *imx_handler,
 		if (expected_type == filetype_unknown)
 			break;
 
-		blob = data->image + imx_handler->flash_header_offset;
-		len  = data->len   - imx_handler->flash_header_offset;
+		blob = data->image + imx_handler->filetype_offset;
+		len  = data->len   - imx_handler->filetype_offset;
 		type = file_detect_type(blob, len);
 
 		if (type != expected_type) {
@@ -392,15 +384,27 @@ static unsigned long imx_bbu_flash_header_offset_mmc(void)
 		return SZ_32K + SZ_1K;
 
 	/*
-	 * i.MX8MP moved the header by 32K to accomodate for GPT partition
+	 * i.MX8MN/P moved the header by 32K to accomodate for GPT partition
 	 * tables, but the IVT is right at the beginning of the image.
 	 */
-	if (cpu_is_mx8mp())
+	if (cpu_is_mx8mn() || cpu_is_mx8mp())
 		return SZ_32K;
 
 	return SZ_1K;
 }
 
+static unsigned long imx_bbu_flash_header_offset_mmcboot(unsigned long *flags)
+{
+	/*
+	 * i.MX8MN/P places IVT directly at start of eMMC boot partition. IVT
+	 * in eMMC user partition and SD is at 32K offset.
+	 */
+	if (cpu_is_mx8mn() || cpu_is_mx8mp())
+		*flags |= IMX_BBU_FLAG_PARTITION_STARTS_AT_HEADER;
+
+	return imx_bbu_flash_header_offset_mmc();
+}
+
 static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data)
 {
 	struct imx_internal_bbu_handler *imx_handler =
@@ -418,54 +422,12 @@ static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data)
 static int imx_bbu_internal_mmcboot_update(struct bbu_handler *handler,
 					   struct bbu_data *data)
 {
-	struct bbu_data _data = *data;
 	int ret;
-	char *bootpartvar;
-	const char *bootpart;
-	char *devicefile;
-	const char *devname = devpath_to_name(data->devicefile);
-
-	ret = device_detect_by_name(devname);
-	if (ret) {
-		pr_err("Couldn't detect device '%s'\n", devname);
-		return ret;
-	}
-
-	ret = asprintf(&bootpartvar, "%s.boot", devname);
-	if (ret < 0)
-		return ret;
-
-	bootpart = getenv(bootpartvar);
-	if (!bootpart) {
-		pr_err("Couldn't read the value of '%s'\n", bootpartvar);
-		ret = -ENOENT;
-		goto free_bootpartvar;
-	}
-
-	if (!strcmp(bootpart, "boot0")) {
-		bootpart = "boot1";
-	} else {
-		bootpart = "boot0";
-	}
-
-	ret = asprintf(&devicefile, "/dev/%s.%s", devname, bootpart);
-	if (ret < 0)
-		goto free_bootpartvar;
 
-	_data.devicefile = devicefile;
+	ret = bbu_mmcboot_handler(handler, data, imx_bbu_update);
 
-	ret = imx_bbu_update(handler, &_data);
-	if (ret)
-		goto free_devicefile;
-
-	/* on success switch boot source */
-	ret = setenv(bootpartvar, bootpart);
-
-free_devicefile:
-	free(devicefile);
-
-free_bootpartvar:
-	free(bootpartvar);
+	if (ret == -ENOENT)
+		pr_err("Couldn't read the value of .boot parameter\n");
 
 	return ret;
 }
@@ -510,6 +472,7 @@ imx_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
 	imx_handler = __init_handler(name, devicefile, flags |
 				     IMX_BBU_FLAG_KEEP_HEAD);
 	imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc();
+	imx_handler->filetype_offset = imx_handler->flash_header_offset;
 
 	return __register_handler(imx_handler);
 }
@@ -522,8 +485,9 @@ imx_bbu_internal_spi_i2c_register_handler(const char *name,
 	struct imx_internal_bbu_handler *imx_handler;
 
 	imx_handler = __init_handler(name, devicefile, flags |
-				     IMX_INTERNAL_FLAG_ERASE);
+				     IMX_BBU_FLAG_ERASE);
 	imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc();
+	imx_handler->filetype_offset = imx_handler->flash_header_offset;
 
 	return __register_handler(imx_handler);
 }
@@ -569,6 +533,7 @@ int imx53_bbu_internal_nand_register_handler(const char *name,
 
 	imx_handler = __init_handler(name, "/dev/nand0", flags);
 	imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc();
+	imx_handler->filetype_offset = imx_handler->flash_header_offset;
 
 	imx_handler->device_size = partition_size;
 	imx_handler->write_device = imx_bbu_internal_v2_write_nand_dbbt;
@@ -614,9 +579,13 @@ static int imx_bbu_internal_mmcboot_register_handler(const char *name,
 						     unsigned long flags)
 {
 	struct imx_internal_bbu_handler *imx_handler;
+	unsigned long flash_header_offset;
+
+	flash_header_offset = imx_bbu_flash_header_offset_mmcboot(&flags);
 
 	imx_handler = __init_handler(name, devicefile, flags);
-	imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc();
+	imx_handler->flash_header_offset = flash_header_offset;
+	imx_handler->filetype_offset = flash_header_offset;
 
 	imx_handler->handler.handler = imx_bbu_internal_mmcboot_update;
 
@@ -681,9 +650,40 @@ int imx_bbu_external_nor_register_handler(const char *name,
 	struct imx_internal_bbu_handler *imx_handler;
 
 	imx_handler = __init_handler(name, devicefile, flags |
-				     IMX_INTERNAL_FLAG_ERASE);
+				     IMX_BBU_FLAG_ERASE);
 
 	imx_handler->expected_type = filetype_unknown;
 
 	return __register_handler(imx_handler);
 }
+
+static unsigned long imx_bbu_filetype_offset_flexspi(void)
+{
+	unsigned int sd_flash_header_gap = SZ_32K;
+
+	if (cpu_is_mx8mm())
+		return sd_flash_header_gap;
+
+	return sd_flash_header_gap + SZ_1K;
+}
+
+static int
+imx_bbu_internal_flexspi_nor_register_handler(const char *name,
+					      const char *devicefile,
+					      unsigned long flags)
+{
+	struct imx_internal_bbu_handler *imx_handler;
+
+	flags |= IMX_BBU_FLAG_ERASE | IMX_BBU_FLAG_PARTITION_STARTS_AT_HEADER;
+	imx_handler = __init_handler(name, devicefile, flags);
+	imx_handler->flash_header_offset = SZ_32K;
+	imx_handler->expected_type = filetype_nxp_fspi_image;
+	imx_handler->filetype_offset = imx_bbu_filetype_offset_flexspi();
+
+	return __register_handler(imx_handler);
+}
+
+int imx8m_bbu_internal_flexspi_nor_register_handler(const char *name,
+						    const char *devicefile,
+						    unsigned long flags)
+	__alias(imx_bbu_internal_flexspi_nor_register_handler);
diff --git a/arch/arm/mach-imx/imx-udc.c b/arch/arm/mach-imx/imx-udc.c
new file mode 100644
index 0000000000..a5364decb1
--- /dev/null
+++ b/arch/arm/mach-imx/imx-udc.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <linux/usb/ch9.h>
+#include <soc/fsl/fsl_udc.h>
+#include <mach/imx/imx8mm-regs.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx7-regs.h>
+
+static void fsl_queue_td(struct usb_dr_device *dr, struct ep_td_struct *dtd,
+			 int ep_is_in)
+{
+	int ep_index = 0;
+	int i = ep_index * 2 + ep_is_in;
+	u32 bitmask;
+	volatile struct ep_queue_head *dQH =
+		(void *)(unsigned long)readl(&dr->endpointlistaddr);
+	unsigned long td_dma = (unsigned long)dtd;
+
+	dQH = &dQH[i];
+
+	bitmask = ep_is_in ? (1 << (ep_index + 16)) : (1 << (ep_index));
+
+	dQH->next_dtd_ptr = cpu_to_le32(td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
+
+	dQH->size_ioc_int_sts &= cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
+			| EP_QUEUE_HEAD_STATUS_HALT));
+
+	writel(bitmask, &dr->endpointprime);
+}
+
+static struct ep_td_struct dtd_data __attribute__((aligned(64)));
+static struct ep_td_struct dtd_status __attribute__((aligned(64)));
+
+static int fsl_ep_queue(struct usb_dr_device *dr, struct ep_td_struct *dtd,
+			void *buf, int len)
+{
+	u32 swap_temp;
+
+	memset(dtd, 0, sizeof(*dtd));
+
+	/* Clear reserved field */
+	swap_temp = cpu_to_le32(dtd->size_ioc_sts);
+	swap_temp &= ~DTD_RESERVED_FIELDS;
+	dtd->size_ioc_sts = cpu_to_le32(swap_temp);
+
+	swap_temp = (unsigned long)buf;
+	dtd->buff_ptr0 = cpu_to_le32(swap_temp);
+	dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000);
+	dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000);
+	dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000);
+	dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000);
+
+	/* Fill in the transfer size; set active bit */
+	swap_temp = ((len << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE) | DTD_IOC;
+
+	writel(cpu_to_le32(swap_temp), &dtd->size_ioc_sts);
+
+	dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE);
+
+	fsl_queue_td(dr, dtd, len ? 0 : 1);
+
+	return 0;
+}
+
+enum state {
+	state_init = 0,
+	state_expect_command,
+	state_transfer_data,
+	state_complete,
+};
+
+#define MAX_TRANSFER_SIZE 2048
+
+static enum state state;
+static uint8_t databuf[MAX_TRANSFER_SIZE] __attribute__((aligned(64)));
+static int actual;
+static int to_transfer;
+static void *image;
+
+static void tripwire_handler(struct usb_dr_device *dr, u8 ep_num)
+{
+	uint32_t val;
+	struct ep_queue_head *qh;
+	struct ep_queue_head *dQH = (void *)(unsigned long)readl(&dr->endpointlistaddr);
+	struct usb_ctrlrequest *ctrl;
+
+	qh = &dQH[ep_num * 2];
+
+	val = readl(&dr->endptsetupstat);
+	val |= 1 << ep_num;
+	writel(val, &dr->endptsetupstat);
+
+	do {
+		val = readl(&dr->usbcmd);
+		val |= USB_CMD_SUTW;
+		writel(val, &dr->usbcmd);
+
+		ctrl = (void *)qh->setup_buffer;
+		if ((ctrl->wValue & 0xff) == 1)
+			state = state_expect_command;
+
+	} while (!(readl(&dr->usbcmd) & USB_CMD_SUTW));
+
+	val = readl(&dr->usbcmd);
+	val &= ~USB_CMD_SUTW;
+	writel(val, &dr->usbcmd);
+
+	fsl_ep_queue(dr, &dtd_data, databuf, MAX_TRANSFER_SIZE);
+}
+
+static void dtd_complete_irq(struct usb_dr_device *dr)
+{
+	struct ep_td_struct *dtd = &dtd_data;
+	u32 bit_pos;
+	int len;
+
+	/* Clear the bits in the register */
+	bit_pos = readl(&dr->endptcomplete);
+	writel(bit_pos, &dr->endptcomplete);
+
+	if (!(bit_pos & 1))
+		return;
+
+	len = MAX_TRANSFER_SIZE -
+		(le32_to_cpu(dtd->size_ioc_sts) >> DTD_LENGTH_BIT_POS);
+
+	if (state == state_expect_command) {
+		state = state_transfer_data;
+		to_transfer = databuf[8] << 24 |
+				databuf[9] << 16 |
+				databuf[10] << 8 |
+				databuf[11];
+	} else {
+		memcpy(image + actual, &databuf[1], len - 1);
+		actual += len - 1;
+		to_transfer -= len - 1;
+
+		if (to_transfer <= 0)
+			state = state_complete;
+	}
+
+	fsl_ep_queue(dr, &dtd_status, NULL, 0);
+}
+
+static int usb_irq(struct usb_dr_device *dr)
+{
+	uint32_t irq_src = readl(&dr->usbsts);
+
+	irq_src &= ~0x80;
+
+	if (!irq_src)
+		return -EAGAIN;
+
+	/* Clear notification bits */
+	writel(irq_src, &dr->usbsts);
+
+	/* USB Interrupt */
+	if (irq_src & USB_STS_INT) {
+		/* Setup package, we only support ep0 as control ep */
+		if (readl(&dr->endptsetupstat) & EP_SETUP_STATUS_EP0)
+			tripwire_handler(dr, 0);
+
+		/* completion of dtd */
+		if (readl(&dr->endptcomplete))
+			dtd_complete_irq(dr);
+	}
+
+	if (state == state_complete)
+		return 0;
+	else
+		return -EAGAIN;
+}
+
+int imx_barebox_load_usb(void __iomem *dr, void *dest)
+{
+	int ret;
+
+	image = dest;
+
+	while (1) {
+		ret = usb_irq(dr);
+		if (!ret)
+			break;
+	}
+
+	return 0;
+}
+
+int imx_barebox_start_usb(void __iomem *dr, void *dest)
+{
+	void __noreturn (*bb)(void);
+	int ret;
+
+	ret = imx_barebox_load_usb(dr, dest);
+	if (ret)
+		return ret;
+
+	printf("Downloading complete, start barebox\n");
+	bb = dest;
+	bb();
+}
+
+int imx6_barebox_load_usb(void *dest)
+{
+	return imx_barebox_load_usb(IOMEM(MX6_OTG_BASE_ADDR), dest);
+}
+
+int imx6_barebox_start_usb(void *dest)
+{
+	return imx_barebox_start_usb(IOMEM(MX6_OTG_BASE_ADDR), dest);
+}
+
+int imx7_barebox_load_usb(void *dest)
+{
+	return imx_barebox_load_usb(IOMEM(MX7_OTG1_BASE_ADDR), dest);
+}
+
+int imx7_barebox_start_usb(void *dest)
+{
+	return imx_barebox_start_usb(IOMEM(MX7_OTG1_BASE_ADDR), dest);
+}
+
+int imx8mm_barebox_load_usb(void *dest)
+{
+	return imx_barebox_load_usb(IOMEM(MX8MM_USB1_BASE_ADDR), dest);
+}
+
+int imx8mm_barebox_start_usb(void *dest)
+{
+	return imx_barebox_start_usb(IOMEM(MX8MM_USB1_BASE_ADDR), dest);
+}
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index bd7e9ac423..f3491c6df7 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -1,23 +1,12 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
 #include <of.h>
 #include <init.h>
 #include <io.h>
-#include <mach/revision.h>
-#include <mach/generic.h>
-#include <mach/reset-reason.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/reset-reason.h>
 
 static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN;
 
@@ -82,8 +71,12 @@ static int imx_soc_from_dt(void)
 		return IMX_CPU_IMX8MQ;
 	if (of_machine_is_compatible("fsl,imx8mm"))
 		return IMX_CPU_IMX8MM;
+	if (of_machine_is_compatible("fsl,imx8mn"))
+		return IMX_CPU_IMX8MN;
 	if (of_machine_is_compatible("fsl,imx8mp"))
 		return IMX_CPU_IMX8MP;
+	if (of_machine_is_compatible("fsl,imx93"))
+		return IMX_CPU_IMX93;
 	if (of_machine_is_compatible("fsl,vf610"))
 		return IMX_CPU_VF610;
 
@@ -102,6 +95,10 @@ static int imx_init(void)
 			return 0;
 	}
 
+	/*
+	 * Don't add new SoCs to this list, instead use the new
+	 * soc framework (see soc-imx8m.c).
+	 */
 	if (cpu_is_mx1())
 		ret = imx1_init();
 	else if (cpu_is_mx21())
@@ -125,11 +122,15 @@ static int imx_init(void)
 	else if (cpu_is_mx7())
 		ret = imx7_init();
 	else if (cpu_is_mx8mm())
-		ret = imx8mm_init();
+		ret = 0;
+	else if (cpu_is_mx8mn())
+		ret = 0;
 	else if (cpu_is_mx8mp())
-		ret = imx8mp_init();
+		ret = 0;
 	else if (cpu_is_mx8mq())
-		ret = imx8mq_init();
+		ret = 0;
+	else if (cpu_is_mx93())
+		ret = imx93_init();
 	else if (cpu_is_vf610())
 		ret = vf610_init();
 	else
diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index 6a09b276c8..817095da82 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -1,23 +1,12 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/imx1-regs.h>
-#include <mach/weim.h>
-#include <mach/iomux-v1.h>
-#include <mach/generic.h>
+#include <mach/imx/imx1-regs.h>
+#include <mach/imx/weim.h>
+#include <mach/imx/iomux-v1.h>
+#include <mach/imx/generic.h>
 #include <reset_source.h>
 
 #define MX1_RSR MX1_SCM_BASE_ADDR
@@ -50,7 +39,7 @@ void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
 	writel(lower, MX1_EIM_BASE_ADDR + 4 + cs * 8);
 }
 
-#include <mach/esdctl.h>
+#include <mach/imx/esdctl.h>
 
 int imx1_init(void)
 {
diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index 7a19ed3986..4271fb92d7 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -1,23 +1,12 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/imx21-regs.h>
-#include <mach/weim.h>
-#include <mach/iomux-v1.h>
-#include <mach/generic.h>
+#include <mach/imx/imx21-regs.h>
+#include <mach/imx/weim.h>
+#include <mach/imx/iomux-v1.h>
+#include <mach/imx/generic.h>
 
 void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
 {
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index d27680e428..2f6d6f0523 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -1,23 +1,12 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
 #include <init.h>
-#include <mach/imx25-regs.h>
-#include <mach/iim.h>
+#include <mach/imx/imx25-regs.h>
+#include <mach/imx/iim.h>
 #include <io.h>
-#include <mach/weim.h>
-#include <mach/generic.h>
+#include <mach/imx/weim.h>
+#include <mach/imx/generic.h>
 #include <linux/sizes.h>
 
 #define MX25_BOOTROM_HAB_MAGIC		0x3c95cac6
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index d4949babeb..4dcc2e028e 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -1,23 +1,12 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
-#include <mach/imx27-regs.h>
-#include <mach/weim.h>
-#include <mach/iomux-v1.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/weim.h>
+#include <mach/imx/iomux-v1.h>
 #include <linux/sizes.h>
-#include <mach/revision.h>
-#include <mach/generic.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/generic.h>
 #include <init.h>
 #include <io.h>
 
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index 137c77a923..20ca9299f1 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -1,23 +1,12 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
 #include <init.h>
 #include <linux/sizes.h>
 #include <io.h>
-#include <mach/imx31-regs.h>
-#include <mach/weim.h>
-#include <mach/generic.h>
+#include <mach/imx/imx31-regs.h>
+#include <mach/imx/weim.h>
+#include <mach/imx/generic.h>
 
 void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
 		unsigned additional)
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index d37bdfda7b..29b77b42c2 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -1,25 +1,14 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
 #include <linux/sizes.h>
 #include <init.h>
 #include <io.h>
-#include <mach/weim.h>
-#include <mach/imx35-regs.h>
-#include <mach/iim.h>
-#include <mach/revision.h>
-#include <mach/generic.h>
+#include <mach/imx/weim.h>
+#include <mach/imx/imx35-regs.h>
+#include <mach/imx/iim.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/generic.h>
 
 void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
 		unsigned additional)
diff --git a/arch/arm/mach-imx/imx5.c b/arch/arm/mach-imx/imx5.c
index dd6c079fe3..10a3ae7bca 100644
--- a/arch/arm/mach-imx/imx5.c
+++ b/arch/arm/mach-imx/imx5.c
@@ -1,8 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <io.h>
 #include <linux/sizes.h>
-#include <mach/imx5.h>
-#include <mach/clock-imx51_53.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/clock-imx51_53.h>
 
 void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn)
 {
diff --git a/arch/arm/mach-imx/imx50.c b/arch/arm/mach-imx/imx50.c
index b76e3794e3..de82ce2ae7 100644
--- a/arch/arm/mach-imx/imx50.c
+++ b/arch/arm/mach-imx/imx50.c
@@ -1,28 +1,17 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <init.h>
 #include <common.h>
 #include <io.h>
 #include <notifier.h>
 #include <linux/sizes.h>
-#include <mach/imx5.h>
-#include <mach/imx50-regs.h>
-#include <mach/revision.h>
-#include <mach/clock-imx51_53.h>
-#include <mach/generic.h>
-#include <mach/reset-reason.h>
-#include <mach/usb.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/imx50-regs.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/clock-imx51_53.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/reset-reason.h>
+#include <mach/imx/usb.h>
 
 #define SI_REV 0x48
 
@@ -32,6 +21,8 @@ static int imx50_silicon_revision(void)
 	u32 rev;
 	u32 mx50_silicon_revision;
 
+	OPTIMIZER_HIDE_VAR(rom);
+
 	rev = readl(rom + SI_REV);
 	switch (rev) {
 	case 0x10:
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 7404254bee..69b892b01a 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -1,28 +1,17 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <init.h>
 #include <common.h>
 #include <linux/sizes.h>
 #include <environment.h>
 #include <io.h>
-#include <mach/imx5.h>
-#include <mach/imx51-regs.h>
-#include <mach/revision.h>
-#include <mach/clock-imx51_53.h>
-#include <mach/generic.h>
-#include <mach/reset-reason.h>
-#include <mach/usb.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/imx51-regs.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/clock-imx51_53.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/reset-reason.h>
+#include <mach/imx/usb.h>
 
 #define IIM_SREV 0x24
 
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index f8e34a39da..e7eb3ea796 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -1,28 +1,17 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <init.h>
 #include <common.h>
 #include <io.h>
 #include <notifier.h>
 #include <linux/sizes.h>
-#include <mach/imx5.h>
-#include <mach/imx53-regs.h>
-#include <mach/revision.h>
-#include <mach/clock-imx51_53.h>
-#include <mach/generic.h>
-#include <mach/reset-reason.h>
-#include <mach/usb.h>
+#include <mach/imx/imx5.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/clock-imx51_53.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/reset-reason.h>
+#include <mach/imx/usb.h>
 
 #define SI_REV 0x48
 
@@ -32,6 +21,8 @@ static int imx53_silicon_revision(void)
 	u32 rev;
 	u32 mx53_silicon_revision;
 
+	OPTIMIZER_HIDE_VAR(rom);
+
 	rev = readl(rom + SI_REV);
 	switch (rev) {
 	case 0x10:
diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
index 8f661e3dfe..134a41bad5 100644
--- a/arch/arm/mach-imx/imx6-mmdc.c
+++ b/arch/arm/mach-imx/imx6-mmdc.c
@@ -1,33 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de
+
 /*
  * i.MX6 DDR controller calibration functions
  * Based on Freescale code
- *
- * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
  */
 #include <common.h>
 #include <io.h>
-#include <mach/imx6-mmdc.h>
-#include <mach/imx6-regs.h>
-#include <mach/imx6.h>
+#include <mach/imx/imx6-mmdc.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx6.h>
+
+static bool wlcalib_failed(void __iomem *ips)
+{
+	/*
+	 * The i.MX 6 reference manual specifies that an MMDC flags reports
+	 * write calibration errors in the MPWLGCR register's HW_WL_ERR field.
+	 *
+	 * ERR050070 specifies that this doesn't work and we should check
+	 * the MPWLHWERR register instead which reports which write leveling
+	 * steps succeeded or failed on a per-byte basis.
+	 *
+	 * Check each byte to see which steps succeeded. If no steps succeeded
+	 * then declare the calibration a failure.
+	*/
+
+	int i;
+
+	for (i = 0; i < 4; ++i) {
+		if (readb(ips + MPWLHWERR + i) == 0)
+			return true;
+	}
+
+	return false;
+}
 
 int mmdc_do_write_level_calibration(void)
 {
+	u32 ldectrl[4];
 	u32 esdmisc_val, zq_val;
 	int errorcount = 0;
 	u32 val;
 	u32 ddr_mr1 = 0x4;
 
+	/* Store current calibration data in case of failure */
+	ldectrl[0] = readl(P0_IPS + MPWLDECTRL0);
+	ldectrl[1] = readl(P0_IPS + MPWLDECTRL1);
+	ldectrl[2] = readl(P1_IPS + MPWLDECTRL0);
+	ldectrl[3] = readl(P1_IPS + MPWLDECTRL1);
+
 	/* disable DDR logic power down timer */
 	val = readl((P0_IPS + MDPDC));
 	val &= 0xffff00ff;
@@ -66,9 +87,13 @@ int mmdc_do_write_level_calibration(void)
 	/* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */
 	while (readl(P0_IPS + MPWLGCR) & 0x00000001);
 
-	/* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */
-	if ((readl(P0_IPS + MPWLGCR) & 0x00000F00) ||
-			(readl(P1_IPS + MPWLGCR) & 0x00000F00)) {
+	/* check for any errors on both PHYs */
+	if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS)) {
+		pr_debug("Calibration failed, rolling back calibration data\n");
+		writel(ldectrl[0], P0_IPS + MPWLDECTRL0);
+		writel(ldectrl[1], P0_IPS + MPWLDECTRL1);
+		writel(ldectrl[2], P1_IPS + MPWLDECTRL0);
+		writel(ldectrl[3], P1_IPS + MPWLDECTRL1);
 		errorcount++;
 	}
 
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 6a9ea23c71..b0d3d8ef2f 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -1,15 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <abort.h>
 #include <init.h>
@@ -17,15 +6,15 @@
 #include <io.h>
 #include <linux/sizes.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
-#include <mach/clock-imx6.h>
-#include <mach/imx6.h>
-#include <mach/generic.h>
-#include <mach/revision.h>
-#include <mach/reset-reason.h>
-#include <mach/imx6-anadig.h>
-#include <mach/imx6-regs.h>
-#include <mach/imx6-fusemap.h>
-#include <mach/usb.h>
+#include <mach/imx/clock-imx6.h>
+#include <mach/imx/imx6.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/reset-reason.h>
+#include <mach/imx/imx6-anadig.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx6-fusemap.h>
+#include <mach/imx/usb.h>
 #include <asm/mmu.h>
 #include <asm/cache-l2x0.h>
 #include <mfd/pfuze.h>
@@ -42,76 +31,44 @@
 #define MX6_OCOTP_CFG0			0x410
 #define MX6_OCOTP_CFG1			0x420
 
-static void imx6_init_lowlevel(void)
+static void imx6_configure_aips(void __iomem *aips)
 {
-	void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
-	void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
-	bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
-	bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
-	uint32_t val_480;
-	uint32_t val_528;
-	uint32_t periph_sel_1;
-	uint32_t periph_sel_2;
-	uint32_t reg;
-
-	if ((readl(MXC_CCM_CCGR6) & 0x3))
-		imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR));
-
 	/*
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
 	 * not forced to user-mode.
 	 */
-	writel(0x77777777, aips1);
-	writel(0x77777777, aips1 + 0x4);
-	writel(0, aips1 + 0x40);
-	writel(0, aips1 + 0x44);
-	writel(0, aips1 + 0x48);
-	writel(0, aips1 + 0x4c);
-	writel(0, aips1 + 0x50);
-
-	writel(0x77777777, aips2);
-	writel(0x77777777, aips2 + 0x4);
-	writel(0, aips2 + 0x40);
-	writel(0, aips2 + 0x44);
-	writel(0, aips2 + 0x48);
-	writel(0, aips2 + 0x4c);
-	writel(0, aips2 + 0x50);
-
-	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
-	 * to make sure PFD is working right, otherwise, PFDs may
-	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
-	 * workaround in ROM code, as bus clock need it.
-	 * Don't reset PLL2 PFD0 / PLL2 PFD2 if is's used by periph_clk.
-	 */
-	if (is_imx6q || is_imx6d) {
-		val_480 = BM_ANADIG_PFD_480_PFD3_CLKGATE |
-			   BM_ANADIG_PFD_480_PFD2_CLKGATE |
-			   BM_ANADIG_PFD_480_PFD1_CLKGATE |
-			   BM_ANADIG_PFD_480_PFD0_CLKGATE;
+	writel(0x77777777, aips);
+	writel(0x77777777, aips + 0x4);
 
-		val_528 = BM_ANADIG_PFD_528_PFD3_CLKGATE |
-			   BM_ANADIG_PFD_528_PFD1_CLKGATE;
-
-		reg = readl(MXC_CCM_CBCMR);
-		periph_sel_1 = (reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
-			>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
-
-		periph_sel_2 = (reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
-			>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET;
-
-		if ((periph_sel_1 != 0x2) && (periph_sel_2 != 0x2))
-			val_528 |= BM_ANADIG_PFD_528_PFD0_CLKGATE;
+	/*
+	 * Set all OPACRx to be non-bufferable, not require
+	 * supervisor privilege level for access,allow for
+	 * write access and untrusted master access.
+	 */
+	writel(0, aips + 0x40);
+	writel(0, aips + 0x44);
+	writel(0, aips + 0x48);
+	writel(0, aips + 0x4c);
+	writel(0, aips + 0x50);
+}
 
-		if ((periph_sel_1 != 0x1) && (periph_sel_2 != 0x1)
-		    && (periph_sel_1 != 0x3) && (periph_sel_2 != 0x3))
-			val_528 |= BM_ANADIG_PFD_528_PFD2_CLKGATE;
+static void imx6_init_lowlevel(void)
+{
+	bool is_imx6ull = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6ULL;
+	bool is_imx6sx = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6SX;
 
-		writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
-		writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
+	/*
+	 * Before reset the controller imx6_boot_save_loc() must be called to
+	 * detect serial-downloader fall back boots. For further information
+	 * check the comment in imx6_get_boot_source().
+	 */
+	if ((readl(MXC_CCM_CCGR6) & 0x3))
+		imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR));
 
-		writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
-		writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
-	}
+	imx6_configure_aips(IOMEM(MX6_AIPS1_ON_BASE_ADDR));
+	imx6_configure_aips(IOMEM(MX6_AIPS2_ON_BASE_ADDR));
+	if (is_imx6ull || is_imx6sx)
+		imx6_configure_aips(IOMEM(MX6_AIPS3_ON_BASE_ADDR));
 }
 
 static bool imx6_has_ipu(void)
@@ -216,10 +173,10 @@ int imx6_init(void)
 	void __iomem *src = IOMEM(MX6_SRC_BASE_ADDR);
 	u64 mx6_uid;
 
-	imx6_init_lowlevel();
-
 	imx6_boot_save_loc();
 
+	imx6_init_lowlevel();
+
 	mx6_silicon_revision = imx6_cpu_revision();
 	mx6_uid = imx6_uid();
 
@@ -369,7 +326,7 @@ static int imx6_fixup_cpus(struct device_node *root, void *context)
 	unsigned long scu_phys_base;
 	unsigned int max_core_index;
 
-	cpus_node = of_find_node_by_name(root, "cpus");
+	cpus_node = of_find_node_by_name_address(root, "cpus");
 	if (!cpus_node)
 		return 0;
 
diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c
index d875bf44f1..fbbed423c0 100644
--- a/arch/arm/mach-imx/imx7.c
+++ b/arch/arm/mach-imx/imx7.c
@@ -1,26 +1,16 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <init.h>
 #include <common.h>
 #include <io.h>
+#include <pm_domain.h>
 #include <linux/sizes.h>
 #include <asm/psci.h>
-#include <mach/imx7.h>
-#include <mach/generic.h>
-#include <mach/revision.h>
-#include <mach/reset-reason.h>
-#include <mach/imx7-regs.h>
+#include <mach/imx/imx7.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/reset-reason.h>
+#include <mach/imx/imx7-regs.h>
 
 void imx7_init_lowlevel(void)
 {
@@ -172,5 +162,7 @@ int imx7_init(void)
 	imx_set_silicon_revision(cputypestr, imx7_cpu_revision());
 	imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);
 
+	genpd_activate();
+
 	return 0;
 }
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 350d203539..52e42ee9ef 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -1,37 +1,20 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <init.h>
 #include <common.h>
+#include <linux/sizes.h>
 #include <io.h>
 #include <asm/syscounter.h>
 #include <asm/system.h>
-#include <mach/generic.h>
-#include <mach/revision.h>
-#include <mach/imx8mq.h>
-#include <mach/imx8m-ccm-regs.h>
-#include <mach/reset-reason.h>
-#include <mach/ocotp.h>
-#include <mach/imx8mp-regs.h>
-#include <mach/imx8mq-regs.h>
-#include <mach/imx8m-ccm-regs.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8m-ccm-regs.h>
 #include <soc/imx8m/clk-early.h>
 
+#include <linux/bitfield.h>
 #include <linux/iopoll.h>
-#include <linux/arm-smccc.h>
 
-#define FSL_SIP_BUILDINFO			0xC2000003
-#define FSL_SIP_BUILDINFO_GET_COMMITHASH	0x00
+#define IMX_SIP_BUILDINFO			0xC2000003
+#define IMX_SIP_BUILDINFO_GET_COMMITHASH	0x00
 
 void imx8m_clock_set_target_val(int clock_id, u32 val)
 {
@@ -56,102 +39,6 @@ void imx8m_ccgr_clock_disable(int index)
 	       ccm + IMX8M_CCM_CCGRn_CLR(index));
 }
 
-u64 imx8m_uid(void)
-{
-	return imx_ocotp_read_uid(IOMEM(MX8M_OCOTP_BASE_ADDR));
-}
-
-static int imx8m_init(const char *cputypestr)
-{
-	void __iomem *src = IOMEM(MX8M_SRC_BASE_ADDR);
-	struct arm_smccc_res res;
-
-	/*
-	 * Reset reasons seem to be identical to that of i.MX7
-	 */
-	imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);
-	pr_info("%s unique ID: %llx\n", cputypestr, imx8m_uid());
-
-	if (IS_ENABLED(CONFIG_ARM_SMCCC) &&
-	    IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) {
-		arm_smccc_smc(FSL_SIP_BUILDINFO,
-			      FSL_SIP_BUILDINFO_GET_COMMITHASH,
-			      0, 0, 0, 0, 0, 0, &res);
-		pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0);
-	}
-
-	return 0;
-}
-
-int imx8mm_init(void)
-{
-	void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR);
-	uint32_t type = FIELD_GET(DIGPROG_MAJOR,
-				  readl(anatop + MX8MM_ANATOP_DIGPROG));
-	const char *cputypestr;
-
-	imx8mm_boot_save_loc();
-
-	switch (type) {
-	case IMX8M_CPUTYPE_IMX8MM:
-		cputypestr = "i.MX8MM";
-		break;
-	default:
-		cputypestr = "unknown i.MX8M";
-		break;
-	};
-
-	imx_set_silicon_revision(cputypestr, imx8mm_cpu_revision());
-
-	return imx8m_init(cputypestr);
-}
-
-int imx8mp_init(void)
-{
-	void __iomem *anatop = IOMEM(MX8MP_ANATOP_BASE_ADDR);
-	uint32_t type = FIELD_GET(DIGPROG_MAJOR,
-				  readl(anatop + MX8MP_ANATOP_DIGPROG));
-	const char *cputypestr;
-
-	imx8mp_boot_save_loc();
-
-	switch (type) {
-	case IMX8M_CPUTYPE_IMX8MP:
-		cputypestr = "i.MX8MP";
-		break;
-	default:
-		cputypestr = "unknown i.MX8M";
-		break;
-	};
-
-	imx_set_silicon_revision(cputypestr, imx8mp_cpu_revision());
-
-	return imx8m_init(cputypestr);
-}
-
-int imx8mq_init(void)
-{
-	void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR);
-	uint32_t type = FIELD_GET(DIGPROG_MAJOR,
-				  readl(anatop + MX8MQ_ANATOP_DIGPROG));
-	const char *cputypestr;
-
-	imx8mq_boot_save_loc();
-
-	switch (type) {
-	case IMX8M_CPUTYPE_IMX8MQ:
-		cputypestr = "i.MX8MQ";
-		break;
-	default:
-		cputypestr = "unknown i.MX8M";
-		break;
-	};
-
-	imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision());
-
-	return imx8m_init(cputypestr);
-}
-
 #define INTPLL_DIV20_CLKE_MASK                  BIT(27)
 #define INTPLL_DIV10_CLKE_MASK                  BIT(25)
 #define INTPLL_DIV8_CLKE_MASK                   BIT(23)
@@ -169,7 +56,7 @@ int imx8mq_init(void)
 #define IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL	0x104
 #define IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL	0x114
 
-void imx8mm_early_clock_init(void)
+static void __imx8m_early_clock_init(unsigned long pll3_freq) /* and later */
 {
 	void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR);
 	void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
@@ -212,9 +99,9 @@ void imx8mm_early_clock_init(void)
 				   IMX8M_CCM_TARGET_ROOTn_MUX(3));
 	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC);
 
-	/* Configure SYS_PLL3 to 750MHz */
+	/* Configure SYS_PLL3 */
 	clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL,
-				    750000000UL, 25000000UL);
+				    pll3_freq, 25000000UL);
 
 	clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT),
 			IMX8M_CCM_TARGET_ROOTn_MUX(7),
@@ -237,6 +124,22 @@ void imx8mm_early_clock_init(void)
 			FIELD_PREP(CCM_TARGET_ROOT0_DIV, 0));
 }
 
+void imx8mm_early_clock_init(void)
+{
+	__imx8m_early_clock_init(750000000UL);
+}
+
+void imx8mn_early_clock_init(void)
+{
+	__imx8m_early_clock_init(600000000UL);
+}
+
+void imx8mp_early_clock_init(void)
+{
+	__imx8m_early_clock_init(750000000UL);
+}
+
+
 #define KEEP_ALIVE			0x18
 #define VER_L				0x1c
 #define VER_H				0x20
diff --git a/arch/arm/mach-imx/imx9.c b/arch/arm/mach-imx/imx9.c
new file mode 100644
index 0000000000..220951fd19
--- /dev/null
+++ b/arch/arm/mach-imx/imx9.c
@@ -0,0 +1,189 @@
+#define pr_fmt(fmt)     "imx9: " fmt
+
+#include <init.h>
+#include <common.h>
+#include <linux/clk.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/ele.h>
+#include <linux/bitfield.h>
+#include <mach/imx/imx9-regs.h>
+#include <tee/optee.h>
+#include <asm-generic/memory_layout.h>
+#include <asm/optee.h>
+#include <mach/imx/scratch.h>
+
+#define SPEED_GRADING_MASK GENMASK(11, 6)
+#define MARKETING_GRADING_MASK     GENMASK(5, 4)
+
+static u32 imx9_read_shadow_fuse(int fuse)
+{
+	void *ocotp = IOMEM(MX9_OCOTP_BASE_ADDR);
+
+	return readl(ocotp + 0x8000 + (fuse << 2));
+}
+
+static u32 imx9_cpu_speed_grade_hz(void)
+{
+	u32 speed, max_speed;
+	u32 val;
+
+	val = imx9_read_shadow_fuse(19);
+
+	val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xf;
+
+	speed = 2300000000 - val * 100000000;
+
+	if (cpu_is_mx93())
+		max_speed = 1700000000;
+
+	/* In case the fuse of speed grade not programmed */
+	if (speed > max_speed)
+		speed = max_speed;
+
+	return speed;
+}
+
+static void imx93_set_arm_clock(void)
+{
+	struct clk *pll = clk_lookup("arm_pll");
+	struct clk *sel = clk_lookup("a55_sel");
+	struct clk *alt = clk_lookup("a55_alt");
+	u32 speed;
+
+	if (IS_ERR(pll) || IS_ERR(sel) || IS_ERR(alt)) {
+		pr_err("Failed to get clocks\n");
+		return;
+	}
+
+	speed = imx9_cpu_speed_grade_hz();
+	if (!speed)
+		return;
+
+	pr_debug("Setting CPU clock to %dMHz\n", speed / 1000000);
+
+	clk_set_parent(sel, alt);
+	clk_set_rate(pll, speed);
+	clk_set_parent(sel, pll);
+}
+
+static const bool imx93_have_npu(void)
+{
+	u32 val = imx9_read_shadow_fuse(19);
+
+	if (val & BIT(13))
+		return false;
+	else
+		return true;
+}
+
+static const int imx93_ncores(void)
+{
+	u32 val = imx9_read_shadow_fuse(19);
+
+	if (val & BIT(15))
+		return 1;
+	else
+		return 2;
+}
+
+static const int imx93_is_9x9(void)
+{
+	u32 val = imx9_read_shadow_fuse(20);
+	u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+
+	if ((val & pack_9x9_fused) == pack_9x9_fused)
+		return true;
+	else
+		return false;
+}
+
+#define TEMP_COMMERCIAL         0
+#define TEMP_EXTCOMMERCIAL      1
+#define TEMP_INDUSTRIAL         2
+#define TEMP_AUTOMOTIVE         3
+
+static void imx93_cpu_temp_grade(int *minc, int *maxc, char *code)
+{
+	u32 val = imx9_read_shadow_fuse(19);
+	int min, max;
+	char c;
+
+	switch (FIELD_GET(MARKETING_GRADING_MASK, val)) {
+	case TEMP_AUTOMOTIVE:
+		min = -40;
+		max = 125;
+		c = 'A';
+		break;
+	case TEMP_INDUSTRIAL:
+		min = -40;
+		max = 105;
+		c = 'C';
+		break;
+	case TEMP_EXTCOMMERCIAL:
+		if (cpu_is_mx93()) {
+			/* imx93 only has extended industrial*/
+			min = -40;
+			max = 125;
+			c = 'X';
+		} else {
+			min = -20;
+			max = 105;
+			c = '-';
+		}
+		break;
+	case TEMP_COMMERCIAL:
+		min = 0;
+		max = 95;
+		c = 'D';
+		break;
+	}
+
+	if (minc)
+		*minc = min;
+	if (maxc)
+		*maxc = max;
+	if (code)
+		*code = c;
+}
+
+static void imx93_type(void)
+{
+	int subfamily, min, max;
+	char code;
+
+	if (imx93_is_9x9()) {
+		if (imx93_have_npu())
+			subfamily = 2;
+		else
+			subfamily = 1;
+	} else {
+		if (imx93_have_npu())
+			subfamily = 5;
+		else
+			subfamily = 3;
+	}
+
+	imx93_cpu_temp_grade(&min, &max, &code);
+
+	pr_info("Detected IMX93%d%d%c (%d - %dC)\n", subfamily, imx93_ncores(), code, min, max);
+}
+
+int imx93_init(void)
+{
+	imx93_type();
+	imx93_set_arm_clock();
+	imx93_bootsource();
+
+	if (IS_ENABLED(CONFIG_PBL_OPTEE)) {
+		static struct of_optee_fixup_data optee_fixup_data = {
+			.shm_size = OPTEE_SHM_SIZE,
+			.method = "smc",
+		};
+
+		optee_set_membase(imx_scratch_get_optee_hdr());
+		of_optee_fixup(of_get_root_node(), &optee_fixup_data);
+		of_register_fixup(of_optee_fixup, &optee_fixup_data);
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/imx93-trdc.c b/arch/arm/mach-imx/imx93-trdc.c
new file mode 100644
index 0000000000..e5ef5bc081
--- /dev/null
+++ b/arch/arm/mach-imx/imx93-trdc.c
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+#define pr_fmt(fmt) "trdc: " fmt
+
+#include <common.h>
+#include <io.h>
+#include <mach/imx/ele.h>
+#include <mach/imx/trdc.h>
+#include <mach/imx/imx9-regs.h>
+
+#define DID_NUM 16
+#define MBC_MAX_NUM 4
+#define MRC_MAX_NUM 2
+#define MBC_NUM(HWCFG) ((HWCFG >> 16) & 0xF)
+#define MRC_NUM(HWCFG) ((HWCFG >> 24) & 0x1F)
+
+struct mbc_mem_dom {
+	u32 mem_glbcfg[4];
+	u32 nse_blk_index;
+	u32 nse_blk_set;
+	u32 nse_blk_clr;
+	u32 nsr_blk_clr_all;
+	u32 memn_glbac[8];
+	/* The upper only existed in the beginning of each MBC */
+	u32 mem0_blk_cfg_w[64];
+	u32 mem0_blk_nse_w[16];
+	u32 mem1_blk_cfg_w[8];
+	u32 mem1_blk_nse_w[2];
+	u32 mem2_blk_cfg_w[8];
+	u32 mem2_blk_nse_w[2];
+	u32 mem3_blk_cfg_w[8];
+	u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+	u32 reserved[2];
+};
+
+struct mrc_rgn_dom {
+	u32 mrc_glbcfg[4];
+	u32 nse_rgn_indirect;
+	u32 nse_rgn_set;
+	u32 nse_rgn_clr;
+	u32 nse_rgn_clr_all;
+	u32 memn_glbac[8];
+	/* The upper only existed in the beginning of each MRC */
+	u32 rgn_desc_words[16][2]; /* 16  regions at max, 2 words per region */
+	u32 rgn_nse;
+	u32 reserved2[15];
+};
+
+struct mda_inst {
+	u32 mda_w[8];
+};
+
+struct trdc_mgr {
+	u32 trdc_cr;
+	u32 res0[59];
+	u32 trdc_hwcfg0;
+	u32 trdc_hwcfg1;
+	u32 res1[450];
+	struct mda_inst mda[8];
+	u32 res2[15808];
+};
+
+struct trdc_mbc {
+	struct mbc_mem_dom mem_dom[DID_NUM];
+};
+
+struct trdc_mrc {
+	struct mrc_rgn_dom mrc_dom[DID_NUM];
+};
+
+static void *trdc_get_mbc_base(ulong trdc_reg, u32 mbc_x)
+{
+	struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+	u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
+
+	if (mbc_x >= mbc_num)
+		return 0;
+
+	return (void *)trdc_reg + 0x10000 + 0x2000 * mbc_x;
+}
+
+static void *trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x)
+{
+	struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+	u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
+	u32 mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0);
+
+	if (mrc_x >= mrc_num)
+		return 0;
+
+	return (void *)trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x;
+}
+
+static int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id,
+			 u32 glbac_val)
+{
+	struct trdc_mbc *mbc_base = trdc_get_mbc_base(trdc_reg, mbc_x);
+	struct mbc_mem_dom *mbc_dom;
+
+	if (mbc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	/* only first dom has the glbac */
+	mbc_dom = &mbc_base->mem_dom[0];
+
+	writel(glbac_val, &mbc_dom->memn_glbac[glbac_id]);
+
+	return 0;
+}
+
+static int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x,
+			u32 blk_x, bool sec_access, u32 glbac_id)
+{
+	struct trdc_mbc *mbc_base = trdc_get_mbc_base(trdc_reg, mbc_x);
+	struct mbc_mem_dom *mbc_dom;
+	u32 *cfg_w, *nse_w;
+	u32 index, offset, val;
+
+	if (mbc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	mbc_dom = &mbc_base->mem_dom[dom_x];
+
+	switch (mem_x) {
+	case 0:
+		cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
+		nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32];
+		break;
+	case 1:
+		cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
+		nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32];
+		break;
+	case 2:
+		cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
+		nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32];
+		break;
+	case 3:
+		cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
+		nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32];
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	index = blk_x % 8;
+	offset = index * 4;
+
+	val = readl((void __iomem *)cfg_w);
+
+	val &= ~(0xFU << offset);
+
+	/* MBC0-3
+	 *  Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+	 *  So select MBC0_MEMN_GLBAC0
+	 */
+	if (sec_access) {
+		val |= ((0x0 | (glbac_id & 0x7)) << offset);
+		writel(val, (void __iomem *)cfg_w);
+	} else {
+		val |= ((0x8 | (glbac_id & 0x7)) << offset); /* nse bit set */
+		writel(val, (void __iomem *)cfg_w);
+	}
+
+	return 0;
+}
+
+static int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32 glbac_val)
+{
+	struct trdc_mrc *mrc_base = trdc_get_mrc_base(trdc_reg, mrc_x);
+	struct mrc_rgn_dom *mrc_dom;
+
+	if (mrc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	/* only first dom has the glbac */
+	mrc_dom = &mrc_base->mrc_dom[0];
+
+	pr_vdebug("mrc_dom 0x%lx\n", (ulong)mrc_dom);
+
+	writel(glbac_val, &mrc_dom->memn_glbac[glbac_id]);
+
+	return 0;
+}
+
+static int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start,
+			   u32 addr_end, bool sec_access, u32 glbac_id)
+{
+	struct trdc_mrc *mrc_base = trdc_get_mrc_base(trdc_reg, mrc_x);
+	struct mrc_rgn_dom *mrc_dom;
+	u32 *desc_w;
+	u32 start, end;
+	u32 i, free = 8;
+	bool vld, hit = false;
+
+	if (mrc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	mrc_dom = &mrc_base->mrc_dom[dom_x];
+
+	addr_start &= ~0x3fff;
+	addr_end &= ~0x3fff;
+
+	for (i = 0; i < 8; i++) {
+		desc_w = &mrc_dom->rgn_desc_words[i][0];
+
+		start = readl((void __iomem *)desc_w) & (~0x3fff);
+		end = readl((void __iomem *)(desc_w + 1));
+		vld = end & 0x1;
+		end = end & (~0x3fff);
+
+		if (start == 0 && end == 0 && !vld && free >= 8)
+			free = i;
+
+		/* Check all the region descriptors, even overlap */
+		if (addr_start >= end || addr_end <= start || !vld)
+			continue;
+
+		/* MRC0,1
+		 *  Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+		 *  So select MRCx_MEMN_GLBAC0
+		 */
+		if (sec_access) {
+			writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
+			writel(end | 0x1, (void __iomem *)(desc_w + 1));
+		} else {
+			writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
+			writel(end | 0x1 | 0x10, (void __iomem *)(desc_w + 1));
+		}
+
+		if (addr_start >= start && addr_end <= end)
+			hit = true;
+	}
+
+	if (!hit) {
+		if (free >= 8)
+			return -EFAULT;
+
+		desc_w = &mrc_dom->rgn_desc_words[free][0];
+
+		if (sec_access) {
+			writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
+			writel(addr_end | 0x1, (void __iomem *)(desc_w + 1));
+		} else {
+			writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
+			writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1));
+		}
+	}
+
+	return 0;
+}
+
+static bool trdc_mrc_enabled(ulong trdc_base)
+{
+	return (!!(readl((void __iomem *)trdc_base) & 0x8000));
+}
+
+#define CORE_ID_A55	0x2
+
+void imx9_trdc_init(void)
+{
+	unsigned long base = MX9_TRDC_NICMIX_BASE_ADDR;
+	int ret = 0, i;
+
+	ret |= ele_release_rdc(CORE_ID_A55, 0, NULL);
+	ret |= ele_release_rdc(CORE_ID_A55, 2, NULL);
+	ret |= ele_release_rdc(CORE_ID_A55, 1, NULL);
+	ret |= ele_release_rdc(CORE_ID_A55, 3, NULL);
+
+	if (ret)
+		return;
+
+	/* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
+	trdc_mbc_set_control(base, 3, 0, 0x7700);
+
+	for (i = 0; i < 40; i++)
+		trdc_mbc_blk_config(base, 3, 3, 0, i, true, 0);
+
+	for (i = 0; i < 40; i++)
+		trdc_mbc_blk_config(base, 3, 3, 1, i, true, 0);
+
+	for (i = 0; i < 40; i++)
+		trdc_mbc_blk_config(base, 3, 0, 0, i, true, 0);
+
+	for (i = 0; i < 40; i++)
+		trdc_mbc_blk_config(base, 3, 0, 1, i, true, 0);
+
+	/* TRDC mega */
+	if (!trdc_mrc_enabled(base))
+		return;
+
+	/* DDR */
+	trdc_mrc_set_control(base, 0, 0, 0x7777);
+	/* S400*/
+	trdc_mrc_region_config(base, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* MTR */
+	trdc_mrc_region_config(base, 0, 1, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* M33 */
+	trdc_mrc_region_config(base, 0, 2, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* A55*/
+	trdc_mrc_region_config(base, 0, 3, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* For USDHC1 to DDR, USDHC1 is default force to non-secure */
+	trdc_mrc_region_config(base, 0, 5, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* For USDHC2 to DDR, USDHC2 is default force to non-secure */
+	trdc_mrc_region_config(base, 0, 6, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* eDMA */
+	trdc_mrc_region_config(base, 0, 7, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* CoreSight, TestPort */
+	trdc_mrc_region_config(base, 0, 8, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* DAP */
+	trdc_mrc_region_config(base, 0, 9, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* SoC masters */
+	trdc_mrc_region_config(base, 0, 10, 0x80000000, 0xFFFFFFFF, false, 0);
+	/* USB */
+	trdc_mrc_region_config(base, 0, 11, 0x80000000, 0xFFFFFFFF, false, 0);
+}
diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h
deleted file mode 100644
index c21ffaeb56..0000000000
--- a/arch/arm/mach-imx/include/mach/atf.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __IMX_ATF_H__
-#define __IMX_ATF_H__
-
-#include <linux/sizes.h>
-#include <asm/system.h>
-
-#define MX8M_ATF_BL31_SIZE_LIMIT	SZ_64K
-
-#define MX8MM_ATF_BL31_BASE_ADDR	0x00920000
-#define MX8MP_ATF_BL31_BASE_ADDR	0x00960000
-#define MX8MQ_ATF_BL31_BASE_ADDR	0x00910000
-#define MX8M_ATF_BL33_BASE_ADDR		0x40200000
-#define MX8MM_ATF_BL33_BASE_ADDR	MX8M_ATF_BL33_BASE_ADDR
-#define MX8MQ_ATF_BL33_BASE_ADDR	MX8M_ATF_BL33_BASE_ADDR
-
-void imx8mm_atf_load_bl31(const void *fw, size_t fw_size);
-void imx8mp_atf_load_bl31(const void *fw, size_t fw_size);
-void imx8mq_atf_load_bl31(const void *fw, size_t fw_size);
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h
deleted file mode 100644
index f2e326f475..0000000000
--- a/arch/arm/mach-imx/include/mach/bbu.h
+++ /dev/null
@@ -1,210 +0,0 @@
-#ifndef __MACH_BBU_H
-#define __MACH_BBU_H
-
-#include <bbu.h>
-#include <errno.h>
-
-struct imx_dcd_entry;
-struct imx_dcd_v2_entry;
-
-/*
- * The ROM code reads images from a certain offset of the boot device
- * (usually 0x400), whereas the update images start from offset 0x0.
- * Set this flag to skip the offset on both the update image and the
- * device so that the initial boot device portion is preserved. This
- * is useful if a partition table or other data is in this area.
- */
-#define IMX_BBU_FLAG_KEEP_HEAD	BIT(16)
-
-/*
- * Set this flag when the partition the update image is written to
- * actually starts at the offset where the i.MX flash header is expected
- * (usually 0x400). This means for the update code that it has to skip
- * the first 0x400 bytes of the image.
- */
-#define IMX_BBU_FLAG_PARTITION_STARTS_AT_HEADER	(1 << 17)
-
-/*
- * The upper 16 bit of the flags passes to the below functions are reserved
- * for i.MX specific flags
- */
-#define IMX_BBU_FLAG_MASK	0xffff0000
-
-#ifdef CONFIG_BAREBOX_UPDATE
-
-int imx51_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-
-int imx51_bbu_internal_spi_i2c_register_handler(const char *name,
-		const char *devicefile, unsigned long flags);
-
-int imx53_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-
-int imx53_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-
-int imx53_bbu_internal_nand_register_handler(const char *name,
-		unsigned long flags, int partition_size);
-
-int imx6_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-
-int imx6_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-
-int imx51_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-
-int vf610_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile,
-						unsigned long flags);
-
-int imx7_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile,
-						unsigned long flags);
-
-int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-
-int vf610_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-
-int vf610_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
-						unsigned long flags);
-
-int imx7_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
-					       unsigned long flags);
-
-int imx8m_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-					    unsigned long flags);
-int imx8m_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile,
-						unsigned long flags);
-
-int imx_bbu_external_nor_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-
-#else
-
-static inline int imx51_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-		unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx51_bbu_internal_spi_i2c_register_handler(const char *name,
-		const char *devicefile, unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx53_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-		unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx53_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
-		unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx53_bbu_internal_nand_register_handler(const char *name,
-		unsigned long flags, int partition_size)
-{
-	return -ENOSYS;
-}
-
-static inline int imx6_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-		unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx6_bbu_internal_mmcboot_register_handler(const char *name,
-							     const char *devicefile,
-							     unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx51_bbu_internal_mmcboot_register_handler(const char *name,
-							      const char *devicefile,
-							      unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-
-static inline int vf610_bbu_internal_mmcboot_register_handler(const char *name,
-							      const char *devicefile,
-							      unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx7_bbu_internal_mmcboot_register_handler(const char *name,
-							     const char *devicefile,
-							     unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
-		unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int vf610_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-					    unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx8m_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
-							  unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx8m_bbu_internal_mmcboot_register_handler(const char *name,
-							      const char *devicefile,
-							      unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int imx_bbu_external_nor_register_handler(const char *name, const char *devicefile,
-		unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int
-vf610_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
-					    unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-static inline int
-imx7_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
-					   unsigned long flags)
-{
-	return -ENOSYS;
-}
-
-#endif
-
-#if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND)
-int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile,
-		unsigned long flags);
-#else
-static inline int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile,
-		unsigned long flags)
-{
-	return -ENOSYS;
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/ccm.h b/arch/arm/mach-imx/include/mach/ccm.h
deleted file mode 100644
index 32254a85b4..0000000000
--- a/arch/arm/mach-imx/include/mach/ccm.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __IMX_CCM_H__
-
-/* 0 <= n <= 190 */
-#define CCM_CCGRn_SET(n)	(0x4004 + 16 * (n))
-#define CCM_CCGRn_CLR(n)	(0x4008 + 16 * (n))
-
-/* 0 <= n <= 120 */
-#define CCM_TARGET_ROOTn(n)	(0x8000 + 128 * (n))
-
-#define CCM_TARGET_ROOTn_MUX(x)		((x) << 24)
-#define CCM_TARGET_ROOTn_ENABLE		BIT(28)
-
-
-#define CCM_CCGR_SETTINGn(n, s)  ((s) << ((n) * 4))
-#define CCM_CCGR_SETTINGn_NOT_NEEDED(n)		CCM_CCGR_SETTINGn(n, 0b00)
-#define CCM_CCGR_SETTINGn_NEEDED_RUN(n)		CCM_CCGR_SETTINGn(n, 0b01)
-#define CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n)	CCM_CCGR_SETTINGn(n, 0b10)
-#define CCM_CCGR_SETTINGn_NEEDED(n)		CCM_CCGR_SETTINGn(n, 0b11)
-
-#endif
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/clock-imx51_53.h b/arch/arm/mach-imx/include/mach/clock-imx51_53.h
deleted file mode 100644
index 06ea2e2a3c..0000000000
--- a/arch/arm/mach-imx/include/mach/clock-imx51_53.h
+++ /dev/null
@@ -1,591 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-/* PLL Register Offsets */
-#define MX5_PLL_DP_CTL			0x00
-#define MX5_PLL_DP_CONFIG		0x04
-#define MX5_PLL_DP_OP			0x08
-#define MX5_PLL_DP_MFD			0x0C
-#define MX5_PLL_DP_MFN			0x10
-#define MX5_PLL_DP_MFNMINUS		0x14
-#define MX5_PLL_DP_MFNPLUS		0x18
-#define MX5_PLL_DP_HFS_OP		0x1C
-#define MX5_PLL_DP_HFS_MFD		0x20
-#define MX5_PLL_DP_HFS_MFN		0x24
-#define MX5_PLL_DP_MFN_TOGC		0x28
-#define MX5_PLL_DP_DESTAT		0x2c
-
-/* PLL Register Bit definitions */
-#define MX5_PLL_DP_CTL_MUL_CTRL		0x2000
-#define MX5_PLL_DP_CTL_DPDCK0_2_EN	0x1000
-#define MX5_PLL_DP_CTL_DPDCK0_2_OFFSET	12
-#define MX5_PLL_DP_CTL_ADE		0x800
-#define MX5_PLL_DP_CTL_REF_CLK_DIV	0x400
-#define MX5_PLL_DP_CTL_REF_CLK_SEL_MASK	(3 << 8)
-#define MX5_PLL_DP_CTL_REF_CLK_SEL_OFFSET	8
-#define MX5_PLL_DP_CTL_HFSM		0x80
-#define MX5_PLL_DP_CTL_PRE		0x40
-#define MX5_PLL_DP_CTL_UPEN		0x20
-#define MX5_PLL_DP_CTL_RST		0x10
-#define MX5_PLL_DP_CTL_RCP		0x8
-#define MX5_PLL_DP_CTL_PLM		0x4
-#define MX5_PLL_DP_CTL_BRM0		0x2
-#define MX5_PLL_DP_CTL_LRF		0x1
-
-#define MX5_PLL_DP_CONFIG_BIST		0x8
-#define MX5_PLL_DP_CONFIG_SJC_CE	0x4
-#define MX5_PLL_DP_CONFIG_AREN		0x2
-#define MX5_PLL_DP_CONFIG_LDREQ		0x1
-
-#define MX5_PLL_DP_OP_MFI_OFFSET	4
-#define MX5_PLL_DP_OP_MFI_MASK		(0xF << 4)
-#define MX5_PLL_DP_OP_PDF_OFFSET	0
-#define MX5_PLL_DP_OP_PDF_MASK		0xF
-
-#define MX5_PLL_DP_MFD_OFFSET		0
-#define MX5_PLL_DP_MFD_MASK		0x07FFFFFF
-
-#define MX5_PLL_DP_MFN_OFFSET		0x0
-#define MX5_PLL_DP_MFN_MASK		0x07FFFFFF
-
-#define MX5_PLL_DP_MFN_TOGC_TOG_DIS	(1 << 17)
-#define MX5_PLL_DP_MFN_TOGC_TOG_EN	(1 << 16)
-#define MX5_PLL_DP_MFN_TOGC_CNT_OFFSET	0x0
-#define MX5_PLL_DP_MFN_TOGC_CNT_MASK	0xFFFF
-
-#define MX5_PLL_DxP_DESTAT_TOG_SEL	(1 << 31)
-#define MX5_PLL_DP_DESTAT_MFN		0x07FFFFFF
-
-/* Register addresses of CCM */
-#define MX5_CCM_CCR		0x00
-#define MX5_CCM_CCDR		0x04
-#define MX5_CCM_CSR		0x08
-#define MX5_CCM_CCSR		0x0C
-#define MX5_CCM_CACRR		0x10
-#define MX5_CCM_CBCDR		0x14
-#define MX5_CCM_CBCMR		0x18
-#define MX5_CCM_CSCMR1		0x1C
-#define MX5_CCM_CSCMR2		0x20
-#define MX5_CCM_CSCDR1		0x24
-#define MX5_CCM_CS1CDR		0x28
-#define MX5_CCM_CS2CDR		0x2C
-#define MX5_CCM_CDCDR		0x30
-#define MX5_CCM_CHSCDR		0x34
-#define MX5_CCM_CSCDR2		0x38
-#define MX5_CCM_CSCDR3		0x3C
-#define MX5_CCM_CSCDR4		0x40
-#define MX5_CCM_CWDR		0x44
-#define MX5_CCM_CDHIPR		0x48
-#define MX5_CCM_CDCR		0x4C
-#define MX5_CCM_CTOR		0x50
-#define MX5_CCM_CLPCR		0x54
-#define MX5_CCM_CISR		0x58
-#define MX5_CCM_CIMR		0x5C
-#define MX5_CCM_CCOSR		0x60
-#define MX5_CCM_CGPR		0x64
-#define MX5_CCM_CCGR0		0x68
-#define MX5_CCM_CCGR1		0x6C
-#define MX5_CCM_CCGR2		0x70
-#define MX5_CCM_CCGR3		0x74
-#define MX5_CCM_CCGR4		0x78
-#define MX5_CCM_CCGR5		0x7C
-#define MX5_CCM_CCGR6		0x80
-#define MX50_CCM_CCGR7		0x84
-#define MX53_CCM_CCGR7		0x84
-#define MX51_CCM_CMEOR		0x84
-
-/* Define the bits in register CCR */
-#define MX5_CCM_CCR_COSC_EN		(1 << 12)
-#define MX5_CCM_CCR_FPM_MULT_MASK	(1 << 11)
-#define MX5_CCM_CCR_CAMP2_EN		(1 << 10)
-#define MX5_CCM_CCR_CAMP1_EN		(1 << 9)
-#define MX5_CCM_CCR_FPM_EN		(1 << 8)
-#define MX5_CCM_CCR_OSCNT_OFFSET	(0)
-#define MX5_CCM_CCR_OSCNT_MASK	(0xFF)
-
-/* Define the bits in register CCDR */
-#define MX5_CCM_CCDR_HSC_HS_MASK	(0x1 << 18)
-#define MX5_CCM_CCDR_IPU_HS_MASK	(0x1 << 17)
-#define MX5_CCM_CCDR_EMI_HS_MASK	(0x1 << 16)
-
-/* Define the bits in register CSR */
-#define MX5_CCM_CSR_COSR_READY	(1 << 5)
-#define MX5_CCM_CSR_LVS_VALUE	(1 << 4)
-#define MX5_CCM_CSR_CAMP2_READY	(1 << 3)
-#define MX5_CCM_CSR_CAMP1_READY	(1 << 2)
-#define MX5_CCM_CSR_FPM_READY	(1 << 1)
-#define MX5_CCM_CSR_REF_EN_B	(1 << 0)
-
-/* Define the bits in register CCSR */
-#define MX5_CCM_CCSR_LP_APM_SEL		(0x1 << 9)
-#define MX5_CCM_CCSR_STEP_SEL_OFFSET	(7)
-#define MX5_CCM_CCSR_STEP_SEL_MASK	(0x3 << 7)
-#define MX5_CCM_CCSR_STEP_SEL_LP_APM	   0
-#define MX5_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
-#define MX5_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
-#define MX5_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
-#define MX5_CCM_CCSR_PLL2_PODF_OFFSET	(5)
-#define MX5_CCM_CCSR_PLL2_PODF_MASK	(0x3 << 5)
-#define MX5_CCM_CCSR_PLL3_PODF_OFFSET	(3)
-#define MX5_CCM_CCSR_PLL3_PODF_MASK	(0x3 << 3)
-#define MX5_CCM_CCSR_PLL1_SW_CLK_SEL	(1 << 2) /* 0: pll1_main_clk,
-						    1: step_clk */
-#define MX5_CCM_CCSR_PLL2_SW_CLK_SEL	(1 << 1)
-#define MX5_CCM_CCSR_PLL3_SW_CLK_SEL	(1 << 0)
-
-/* Define the bits in register CACRR */
-#define MX5_CCM_CACRR_ARM_PODF_OFFSET	(0)
-#define MX5_CCM_CACRR_ARM_PODF_MASK	(0x7)
-
-/* Define the bits in register CBCDR */
-#define MX5_CCM_CBCDR_RESET_VALUE		(0x19239145)
-#define MX5_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
-#define MX5_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
-#define MX5_CCM_CBCDR_DDR_HF_SEL_OFFSET		(30)
-#define MX5_CCM_CBCDR_DDR_HF_SEL		(0x1 << 30)
-#define MX5_CCM_CBCDR_DDR_PODF_OFFSET		(27)
-#define MX5_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
-#define MX5_CCM_CBCDR_EMI_PODF_OFFSET		(22)
-#define MX5_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
-#define MX5_CCM_CBCDR_AXI_B_PODF_OFFSET		(19)
-#define MX5_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
-#define MX5_CCM_CBCDR_AXI_A_PODF_OFFSET		(16)
-#define MX5_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
-#define MX5_CCM_CBCDR_NFC_PODF_OFFSET		(13)
-#define MX5_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
-#define MX5_CCM_CBCDR_AHB_PODF_OFFSET		(10)
-#define MX5_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
-#define MX5_CCM_CBCDR_IPG_PODF_OFFSET		(8)
-#define MX5_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
-#define MX5_CCM_CBCDR_PERCLK_PRED1_OFFSET	(6)
-#define MX5_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
-#define MX5_CCM_CBCDR_PERCLK_PRED2_OFFSET	(3)
-#define MX5_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
-#define MX5_CCM_CBCDR_PERCLK_PODF_OFFSET	(0)
-#define MX5_CCM_CBCDR_PERCLK_PODF_MASK		(0x7)
-
-/* Define the bits in register CBCMR */
-#define MX5_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET	(14)
-#define MX5_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK	(0x3 << 14)
-#define MX5_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET	(12)
-#define MX5_CCM_CBCMR_PERIPH_CLK_SEL_MASK	(0x3 << 12)
-#define MX5_CCM_CBCMR_DDR_CLK_SEL_OFFSET	(10)
-#define MX5_CCM_CBCMR_DDR_CLK_SEL_MASK		(0x3 << 10)
-#define MX5_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET	(8)
-#define MX5_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK	(0x3 << 8)
-#define MX5_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET	(6)
-#define MX5_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK	(0x3 << 6)
-#define MX5_CCM_CBCMR_GPU_CLK_SEL_OFFSET	(4)
-#define MX5_CCM_CBCMR_GPU_CLK_SEL_MASK		(0x3 << 4)
-#define MX5_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET	(14)
-#define MX5_CCM_CBCMR_GPU2D_CLK_SEL_MASK	(0x3 << 14)
-#define MX5_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL	(0x1 << 1)
-#define MX5_CCM_CBCMR_PERCLK_IPG_CLK_SEL	(0x1 << 0)
-
-/* Define the bits in register CSCMR1 */
-#define MX5_CCM_CSCMR1_RESET_VALUE			(0xa6a2a020)
-#define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		(30)
-#define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
-#define MX5_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		(28)
-#define MX5_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
-#define MX5_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		(26)
-#define MX5_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
-#define MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET		(24)
-#define MX5_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
-#define MX5_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		(22)
-#define MX5_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
-#define MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	(20)
-#define MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
-#define MX5_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
-#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL	(0x1 << 19)
-#define MX5_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
-#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	(16)
-#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
-#define MX5_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET	(16)
-#define MX5_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK		(0x3 << 16)
-#define MX5_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		(14)
-#define MX5_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
-#define MX5_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		(12)
-#define MX5_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
-#define MX5_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
-#define MX5_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
-#define MX5_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		(8)
-#define MX5_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
-#define MX5_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
-#define MX5_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
-#define MX5_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		(4)
-#define MX5_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
-#define MX5_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		(2)
-#define MX5_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
-#define MX5_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
-#define MX5_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		(0x1)
-
-/* Define the bits in register CSCMR2 */
-#define MX5_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)		(26+n*3)
-#define MX5_CCM_CSCMR2_DI_CLK_SEL_MASK(n)		(0x7 << (26+n*3))
-#define MX5_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET		(24)
-#define MX5_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK		(0x3 << 24)
-#define MX5_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET		(22)
-#define MX5_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK		(0x3 << 22)
-#define MX5_CCM_CSCMR2_ESC_CLK_SEL_OFFSET		(20)
-#define MX5_CCM_CSCMR2_ESC_CLK_SEL_MASK			(0x3 << 20)
-#define MX5_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET		(18)
-#define MX5_CCM_CSCMR2_HSC2_CLK_SEL_MASK		(0x3 << 18)
-#define MX5_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET		(16)
-#define MX5_CCM_CSCMR2_HSC1_CLK_SEL_MASK		(0x3 << 16)
-#define MX5_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET		(14)
-#define MX5_CCM_CSCMR2_HSI2C_CLK_SEL_MASK		(0x3 << 14)
-#define MX5_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET		(12)
-#define MX5_CCM_CSCMR2_FIRI_CLK_SEL_MASK		(0x3 << 12)
-#define MX5_CCM_CSCMR2_SIM_CLK_SEL_OFFSET		(10)
-#define MX5_CCM_CSCMR2_SIM_CLK_SEL_MASK			(0x3 << 10)
-#define MX5_CCM_CSCMR2_SLIMBUS_COM			(0x1 << 9)
-#define MX5_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET		(6)
-#define MX5_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK		(0x7 << 6)
-#define MX5_CCM_CSCMR2_SPDIF1_COM			(1 << 5)
-#define MX5_CCM_CSCMR2_SPDIF0_COM			(1 << 4)
-#define MX5_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET		(2)
-#define MX5_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK		(0x3 << 2)
-#define MX5_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET		(0)
-#define MX5_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK		(0x3)
-
-/* Define the bits in register CSCDR1 */
-#define MX5_CCM_CSCDR1_RESET_VALUE			(0x00c30318)
-#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	(22)
-#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
-#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	(19)
-#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
-#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET	(22)
-#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK	(0x7 << 22)
-#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET	(19)
-#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK	(0x7 << 19)
-#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	(16)
-#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
-#define MX5_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		(14)
-#define MX5_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
-#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	(11)
-#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
-#define MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		(8)
-#define MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
-#define MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		(6)
-#define MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
-#define MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET		(3)
-#define MX5_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
-#define MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET		(0)
-#define MX5_CCM_CSCDR1_UART_CLK_PODF_MASK		(0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET		(22)
-#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK		(0x7 << 22)
-#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET		(16)
-#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK		(0x3F << 16)
-#define MX5_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		(6)
-#define MX5_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
-#define MX5_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		(0)
-#define MX5_CCM_CS1CDR_SSI1_CLK_PODF_MASK		(0x3F)
-
-#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET		(22)
-#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK		(0x7 << 22)
-#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET		(16)
-#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK		(0x3F << 16)
-#define MX5_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		(6)
-#define MX5_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
-#define MX5_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		(0)
-#define MX5_CCM_CS2CDR_SSI2_CLK_PODF_MASK		(0x3F)
-
-/* Define the bits in register CDCDR */
-#define MX5_CCM_CDCDR_TVE_CLK_PRED_OFFSET		(28)
-#define MX5_CCM_CDCDR_TVE_CLK_PRED_MASK			(0x7 << 28)
-#define MX5_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET		(25)
-#define MX5_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
-#define MX5_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET		(19)
-#define MX5_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x3F << 19)
-#define MX5_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET		(16)
-#define MX5_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 16)
-#define MX5_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		(9)
-#define MX5_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x3F << 9)
-#define MX5_CCM_CDCDR_DI_CLK_PRED_OFFSET		(6)
-#define MX5_CCM_CDCDR_DI_CLK_PRED_MASK			(0x7 << 6)
-#define MX5_CCM_CDCDR_USB_PHY_PRED_OFFSET		(3)
-#define MX5_CCM_CDCDR_USB_PHY_PRED_MASK			(0x7 << 3)
-#define MX5_CCM_CDCDR_USB_PHY_PODF_OFFSET		(0)
-#define MX5_CCM_CDCDR_USB_PHY_PODF_MASK			(0x7)
-
-/* Define the bits in register CHSCCDR */
-#define MX5_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET		(12)
-#define MX5_CCM_CHSCCDR_ESC_CLK_PRED_MASK		(0x7 << 12)
-#define MX5_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET		(6)
-#define MX5_CCM_CHSCCDR_ESC_CLK_PODF_MASK		(0x3F << 6)
-#define MX5_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET		(3)
-#define MX5_CCM_CHSCCDR_HSC2_CLK_PODF_MASK		(0x7 << 3)
-#define MX5_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET		(0)
-#define MX5_CCM_CHSCCDR_HSC1_CLK_PODF_MASK		(0x7)
-
-/* Define the bits in register CSCDR2 */
-#define MX5_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		(25)
-#define MX5_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
-#define MX5_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		(19)
-#define MX5_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
-#define MX5_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		(16)
-#define MX5_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
-#define MX5_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		(9)
-#define MX5_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
-#define MX5_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		(6)
-#define MX5_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
-#define MX5_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		(0)
-#define MX5_CCM_CSCDR2_SLIMBUS_PODF_MASK		(0x3F)
-
-/* Define the bits in register CSCDR3 */
-#define MX5_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET		(16)
-#define MX5_CCM_CSCDR3_HSI2C_CLK_PRED_MASK		(0x7 << 16)
-#define MX5_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET		(9)
-#define MX5_CCM_CSCDR3_HSI2C_CLK_PODF_MASK		(0x3F << 9)
-#define MX5_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET		(6)
-#define MX5_CCM_CSCDR3_FIRI_CLK_PRED_MASK		(0x7 << 6)
-#define MX5_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET		(0)
-#define MX5_CCM_CSCDR3_FIRI_CLK_PODF_MASK		(0x3F)
-
-/* Define the bits in register CSCDR4 */
-#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET	(16)
-#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK		(0x7 << 16)
-#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET	(9)
-#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK		(0x3F << 9)
-#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET	(6)
-#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK		(0x7 << 6)
-#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET	(0)
-#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK		(0x3F)
-
-/* Define the bits in register CDHIPR */
-#define MX5_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
-#define MX5_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY		(1 << 8)
-#define MX5_CCM_CDHIPR_DDR_PODF_BUSY			(1 << 7)
-#define MX5_CCM_CDHIPR_EMI_CLK_SEL_BUSY			(1 << 6)
-#define MX5_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
-#define MX5_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY	(1 << 4)
-#define MX5_CCM_CDHIPR_AHB_PODF_BUSY			(1 << 3)
-#define MX5_CCM_CDHIPR_EMI_PODF_BUSY			(1 << 2)
-#define MX5_CCM_CDHIPR_AXI_B_PODF_BUSY			(1 << 1)
-#define MX5_CCM_CDHIPR_AXI_A_PODF_BUSY			(1 << 0)
-
-/* Define the bits in register CDCR */
-#define MX5_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER		(0x1 << 2)
-#define MX5_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET	(0)
-#define MX5_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK		(0x3)
-
-/* Define the bits in register CLPCR */
-#define MX5_CCM_CLPCR_BYPASS_HSC_LPM_HS		(0x1 << 23)
-#define MX5_CCM_CLPCR_BYPASS_SCC_LPM_HS		(0x1 << 22)
-#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS		(0x1 << 21)
-#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS		(0x1 << 25)
-#define MX5_CCM_CLPCR_BYPASS_SDMA_LPM_HS	(0x1 << 20)
-#define MX5_CCM_CLPCR_BYPASS_EMI_LPM_HS		(0x1 << 19)
-#define MX5_CCM_CLPCR_BYPASS_IPU_LPM_HS		(0x1 << 18)
-#define MX5_CCM_CLPCR_BYPASS_RTIC_LPM_HS	(0x1 << 17)
-#define MX5_CCM_CLPCR_BYPASS_RNGC_LPM_HS	(0x1 << 16)
-#define MX5_CCM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
-#define MX5_CCM_CLPCR_STBY_COUNT_OFFSET		(9)
-#define MX5_CCM_CLPCR_STBY_COUNT_MASK		(0x3 << 9)
-#define MX5_CCM_CLPCR_VSTBY			(0x1 << 8)
-#define MX5_CCM_CLPCR_DIS_REF_OSC		(0x1 << 7)
-#define MX5_CCM_CLPCR_SBYOS			(0x1 << 6)
-#define MX5_CCM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
-#define MX5_CCM_CLPCR_LPSR_CLK_SEL_OFFSET	(3)
-#define MX5_CCM_CLPCR_LPSR_CLK_SEL_MASK		(0x3 << 3)
-#define MX5_CCM_CLPCR_LPM_OFFSET		(0)
-#define MX5_CCM_CLPCR_LPM_MASK			(0x3)
-
-/* Define the bits in register CISR */
-#define MX5_CCM_CISR_ARM_PODF_LOADED			(0x1 << 25)
-#define MX5_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
-#define MX5_CCM_CISR_AHB_PODF_LOADED			(0x1 << 20)
-#define MX5_CCM_CISR_EMI_PODF_LOADED			(0x1 << 19)
-#define MX5_CCM_CISR_AXI_B_PODF_LOADED			(0x1 << 18)
-#define MX5_CCM_CISR_AXI_A_PODF_LOADED			(0x1 << 17)
-#define MX5_CCM_CISR_DIVIDER_LOADED			(0x1 << 16)
-#define MX5_CCM_CISR_COSC_READY				(0x1 << 6)
-#define MX5_CCM_CISR_CKIH2_READY			(0x1 << 5)
-#define MX5_CCM_CISR_CKIH_READY				(0x1 << 4)
-#define MX5_CCM_CISR_FPM_READY				(0x1 << 3)
-#define MX5_CCM_CISR_LRF_PLL3				(0x1 << 2)
-#define MX5_CCM_CISR_LRF_PLL2				(0x1 << 1)
-#define MX5_CCM_CISR_LRF_PLL1				(0x1)
-
-/* Define the bits in register CIMR */
-#define MX5_CCM_CIMR_MASK_ARM_PODF_LOADED		(0x1 << 25)
-#define MX5_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
-#define MX5_CCM_CIMR_MASK_EMI_PODF_LOADED		(0x1 << 20)
-#define MX5_CCM_CIMR_MASK_AXI_C_PODF_LOADED		(0x1 << 19)
-#define MX5_CCM_CIMR_MASK_AXI_B_PODF_LOADED		(0x1 << 18)
-#define MX5_CCM_CIMR_MASK_AXI_A_PODF_LOADED		(0x1 << 17)
-#define MX5_CCM_CIMR_MASK_DIVIDER_LOADED		(0x1 << 16)
-#define MX5_CCM_CIMR_MASK_COSC_READY			(0x1 << 5)
-#define MX5_CCM_CIMR_MASK_CKIH_READY			(0x1 << 4)
-#define MX5_CCM_CIMR_MASK_FPM_READY			(0x1 << 3)
-#define MX5_CCM_CIMR_MASK_LRF_PLL3			(0x1 << 2)
-#define MX5_CCM_CIMR_MASK_LRF_PLL2			(0x1 << 1)
-#define MX5_CCM_CIMR_MASK_LRF_PLL1			(0x1)
-
-/* Define the bits in register CCOSR */
-#define MX5_CCM_CCOSR_CKO2_EN_OFFSET			(0x1 << 24)
-#define MX5_CCM_CCOSR_CKO2_DIV_OFFSET			(21)
-#define MX5_CCM_CCOSR_CKO2_DIV_MASK			(0x7 << 21)
-#define MX5_CCM_CCOSR_CKO2_SEL_OFFSET			(16)
-#define MX5_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
-#define MX5_CCM_CCOSR_CKOL_EN				(0x1 << 7)
-#define MX5_CCM_CCOSR_CKOL_DIV_OFFSET			(4)
-#define MX5_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
-#define MX5_CCM_CCOSR_CKOL_SEL_OFFSET			(0)
-#define MX5_CCM_CCOSR_CKOL_SEL_MASK			(0xF)
-
-/* Define the bits in registers CGPR */
-#define MX5_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(0x1 << 4)
-#define MX5_CCM_CGPR_FPM_SEL				(0x1 << 3)
-#define MX5_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET		(0)
-#define MX5_CCM_CGPR_VL_L2BIST_CLKDIV_MASK		(0x7)
-
-/* Define the bits in registers CCGRx */
-#define MX5_CCM_CCGRx_CG_MASK				0x3
-#define MX5_CCM_CCGRx_MOD_OFF				0x0
-#define MX5_CCM_CCGRx_MOD_ON				0x3
-#define MX5_CCM_CCGRx_MOD_IDLE				0x1
-
-#define MX5_CCM_CCGRx_CG15_MASK				(0x3 << 30)
-#define MX5_CCM_CCGRx_CG14_MASK				(0x3 << 28)
-#define MX5_CCM_CCGRx_CG13_MASK				(0x3 << 26)
-#define MX5_CCM_CCGRx_CG12_MASK				(0x3 << 24)
-#define MX5_CCM_CCGRx_CG11_MASK				(0x3 << 22)
-#define MX5_CCM_CCGRx_CG10_MASK				(0x3 << 20)
-#define MX5_CCM_CCGRx_CG9_MASK				(0x3 << 18)
-#define MX5_CCM_CCGRx_CG8_MASK				(0x3 << 16)
-#define MX5_CCM_CCGRx_CG5_MASK				(0x3 << 10)
-#define MX5_CCM_CCGRx_CG4_MASK				(0x3 << 8)
-#define MX5_CCM_CCGRx_CG3_MASK				(0x3 << 6)
-#define MX5_CCM_CCGRx_CG2_MASK				(0x3 << 4)
-#define MX5_CCM_CCGRx_CG1_MASK				(0x3 << 2)
-#define MX5_CCM_CCGRx_CG0_MASK				(0x3 << 0)
-
-#define MX5_CCM_CCGRx_CG15_OFFSET			30
-#define MX5_CCM_CCGRx_CG14_OFFSET			28
-#define MX5_CCM_CCGRx_CG13_OFFSET			26
-#define MX5_CCM_CCGRx_CG12_OFFSET			24
-#define MX5_CCM_CCGRx_CG11_OFFSET			22
-#define MX5_CCM_CCGRx_CG10_OFFSET			20
-#define MX5_CCM_CCGRx_CG9_OFFSET			18
-#define MX5_CCM_CCGRx_CG8_OFFSET			16
-#define MX5_CCM_CCGRx_CG7_OFFSET			14
-#define MX5_CCM_CCGRx_CG6_OFFSET			12
-#define MX5_CCM_CCGRx_CG5_OFFSET			10
-#define MX5_CCM_CCGRx_CG4_OFFSET			8
-#define MX5_CCM_CCGRx_CG3_OFFSET			6
-#define MX5_CCM_CCGRx_CG2_OFFSET			4
-#define MX5_CCM_CCGRx_CG1_OFFSET			2
-#define MX5_CCM_CCGRx_CG0_OFFSET			0
-
-#define MX5_DPTC_LP_BASE	(MX51_GPC_BASE + 0x80)
-#define MX5_DPTC_GP_BASE	(MX51_GPC_BASE + 0x100)
-#define MX5_DVFS_CORE_BASE	(MX51_GPC_BASE + 0x180)
-#define MX5_DPTC_PER_BASE	(MX51_GPC_BASE + 0x1C0)
-#define MX5_PGC_IPU_BASE	(MX51_GPC_BASE + 0x220)
-#define MX5_PGC_VPU_BASE	(MX51_GPC_BASE + 0x240)
-#define MX5_PGC_GPU_BASE	(MX51_GPC_BASE + 0x260)
-#define MX5_SRPG_NEON_BASE	(MX51_GPC_BASE + 0x280)
-#define MX5_SRPG_ARM_BASE	(MX51_GPC_BASE + 0x2A0)
-#define MX5_SRPG_EMPGC0_BASE	(MX51_GPC_BASE + 0x2C0)
-#define MX5_SRPG_EMPGC1_BASE	(MX51_GPC_BASE + 0x2D0)
-#define MX5_SRPG_MEGAMIX_BASE	(MX51_GPC_BASE + 0x2E0)
-#define MX5_SRPG_EMI_BASE	(MX51_GPC_BASE + 0x300)
-
-/* CORTEXA8 platform */
-#define MX5_CORTEXA8_PLAT_PVID		(MX51_CORTEXA8_BASE + 0x0)
-#define MX5_CORTEXA8_PLAT_GPC		(MX51_CORTEXA8_BASE + 0x4)
-#define MX5_CORTEXA8_PLAT_PIC		(MX51_CORTEXA8_BASE + 0x8)
-#define MX5_CORTEXA8_PLAT_LPC		(MX51_CORTEXA8_BASE + 0xC)
-#define MX5_CORTEXA8_PLAT_NEON_LPC	(MX51_CORTEXA8_BASE + 0x10)
-#define MX5_CORTEXA8_PLAT_ICGC		(MX51_CORTEXA8_BASE + 0x14)
-#define MX5_CORTEXA8_PLAT_AMC		(MX51_CORTEXA8_BASE + 0x18)
-#define MX5_CORTEXA8_PLAT_NMC		(MX51_CORTEXA8_BASE + 0x20)
-#define MX5_CORTEXA8_PLAT_NMS		(MX51_CORTEXA8_BASE + 0x24)
-
-/* DVFS CORE */
-#define MX5_DVFSTHRS		(MX5_DVFS_CORE_BASE + 0x00)
-#define MX5_DVFSCOUN		(MX5_DVFS_CORE_BASE + 0x04)
-#define MX5_DVFSSIG1		(MX5_DVFS_CORE_BASE + 0x08)
-#define MX5_DVFSSIG0		(MX5_DVFS_CORE_BASE + 0x0C)
-#define MX5_DVFSGPC0		(MX5_DVFS_CORE_BASE + 0x10)
-#define MX5_DVFSGPC1		(MX5_DVFS_CORE_BASE + 0x14)
-#define MX5_DVFSGPBT		(MX5_DVFS_CORE_BASE + 0x18)
-#define MX5_DVFSEMAC		(MX5_DVFS_CORE_BASE + 0x1C)
-#define MX5_DVFSCNTR		(MX5_DVFS_CORE_BASE + 0x20)
-#define MX5_DVFSLTR0_0		(MX5_DVFS_CORE_BASE + 0x24)
-#define MX5_DVFSLTR0_1		(MX5_DVFS_CORE_BASE + 0x28)
-#define MX5_DVFSLTR1_0		(MX5_DVFS_CORE_BASE + 0x2C)
-#define MX5_DVFSLTR1_1		(MX5_DVFS_CORE_BASE + 0x30)
-#define MX5_DVFSPT0 		(MX5_DVFS_CORE_BASE + 0x34)
-#define MX5_DVFSPT1 		(MX5_DVFS_CORE_BASE + 0x38)
-#define MX5_DVFSPT2 		(MX5_DVFS_CORE_BASE + 0x3C)
-#define MX5_DVFSPT3 		(MX5_DVFS_CORE_BASE + 0x40)
-
-/* GPC */
-#define MX5_GPC_CNTR		(MX51_GPC_BASE + 0x0)
-#define MX5_GPC_PGR		(MX51_GPC_BASE + 0x4)
-#define MX5_GPC_VCR		(MX51_GPC_BASE + 0x8)
-#define MX5_GPC_ALL_PU		(MX51_GPC_BASE + 0xC)
-#define MX5_GPC_NEON		(MX51_GPC_BASE + 0x10)
-#define MX5_GPC_PGR_ARMPG_OFFSET	8
-#define MX5_GPC_PGR_ARMPG_MASK		(3 << 8)
-
-/* PGC */
-#define MX5_PGC_IPU_PGCR	(MX5_PGC_IPU_BASE + 0x0)
-#define MX5_PGC_IPU_PGSR	(MX5_PGC_IPU_BASE + 0xC)
-#define MX5_PGC_VPU_PGCR	(MX5_PGC_VPU_BASE + 0x0)
-#define MX5_PGC_VPU_PGSR	(MX5_PGC_VPU_BASE + 0xC)
-#define MX5_PGC_GPU_PGCR	(MX5_PGC_GPU_BASE + 0x0)
-#define MX5_PGC_GPU_PGSR	(MX5_PGC_GPU_BASE + 0xC)
-
-#define MX5_PGCR_PCR		1
-#define MX5_SRPGCR_PCR		1
-#define MX5_EMPGCR_PCR		1
-#define MX5_PGSR_PSR		1
-
-
-#define MX5_CORTEXA8_PLAT_LPC_DSM	(1 << 0)
-#define MX5_CORTEXA8_PLAT_LPC_DBG_DSM	(1 << 1)
-
-/* SRPG */
-#define MX5_SRPG_NEON_SRPGCR	(MX5_SRPG_NEON_BASE + 0x0)
-#define MX5_SRPG_NEON_PUPSCR	(MX5_SRPG_NEON_BASE + 0x4)
-#define MX5_SRPG_NEON_PDNSCR	(MX5_SRPG_NEON_BASE + 0x8)
-
-#define MX5_SRPG_ARM_SRPGCR	(MX5_SRPG_ARM_BASE + 0x0)
-#define MX5_SRPG_ARM_PUPSCR	(MX5_SRPG_ARM_BASE + 0x4)
-#define MX5_SRPG_ARM_PDNSCR	(MX5_SRPG_ARM_BASE + 0x8)
-
-#define MX5_SRPG_EMPGC0_SRPGCR	(MX5_SRPG_EMPGC0_BASE + 0x0)
-#define MX5_SRPG_EMPGC0_PUPSCR	(MX5_SRPG_EMPGC0_BASE + 0x4)
-#define MX5_SRPG_EMPGC0_PDNSCR	(MX5_SRPG_EMPGC0_BASE + 0x8)
-
-#define MX5_SRPG_EMPGC1_SRPGCR	(MX5_SRPG_EMPGC1_BASE + 0x0)
-#define MX5_SRPG_EMPGC1_PUPSCR	(MX5_SRPG_EMPGC1_BASE + 0x4)
-#define MX5_SRPG_EMPGC1_PDNSCR	(MX5_SRPG_EMPGC1_BASE + 0x8)
-
-#define MX5_SRPG_MEGAMIX_SRPGCR		(MX5_SRPG_MEGAMIX_BASE + 0x0)
-#define MX5_SRPG_MEGAMIX_PUPSCR		(MX5_SRPG_MEGAMIX_BASE + 0x4)
-#define MX5_SRPG_MEGAMIX_PDNSCR		(MX5_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MX5_SRPGC_EMI_SRPGCR	(MX5_SRPGC_EMI_BASE + 0x0)
-#define MX5_SRPGC_EMI_PUPSCR	(MX5_SRPGC_EMI_BASE + 0x4)
-#define MX5_SRPGC_EMI_PDNSCR	(MX5_SRPGC_EMI_BASE + 0x8)
-
-#endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-imx/include/mach/clock-imx6.h b/arch/arm/mach-imx/include/mach/clock-imx6.h
deleted file mode 100644
index 69fbedd51e..0000000000
--- a/arch/arm/mach-imx/include/mach/clock-imx6.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2010-2011 Freescale Semiconductor, Inc. */
-
-#ifndef __ARCH_ARM_MACH_MX6_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX6_CRM_REGS_H__
-
-#define MXC_CCM_BASE   MX6_CCM_BASE_ADDR
-
-/* Register addresses of CCM*/
-#define MXC_CCM_CCR		(MXC_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR		(MXC_CCM_BASE + 0x04)
-#define MXC_CCM_CSR		(MXC_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR		(MXC_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR		(MXC_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR		(MXC_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR		(MXC_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1		(MXC_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2		(MXC_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1		(MXC_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR		(MXC_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR		(MXC_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR		(MXC_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR		(MXC_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2		(MXC_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3		(MXC_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4		(MXC_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR		(MXC_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR		(MXC_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR		(MXC_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR		(MXC_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR		(MXC_CCM_BASE + 0x54)
-#define MXC_CCM_CISR		(MXC_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR		(MXC_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR		(MXC_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR		(MXC_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0		(MXC_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1		(MXC_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2		(MXC_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3		(MXC_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4		(MXC_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5		(MXC_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6		(MXC_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7		(MXC_CCM_BASE + 0x80)
-#define MXC_CCM_CMEOR		(MXC_CCM_BASE + 0x88)
-
-/* Define the bits in register CCR */
-#define MXC_CCM_CCR_RBC_EN				(1 << 27)
-#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK 		(0x3F << 21)
-#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 		(21)
-#define MXC_CCM_CCR_WB_COUNT_MASK 			(0x7)
-#define MXC_CCM_CCR_WB_COUNT_OFFSET			(1 << 16)
-#define MXC_CCM_CCR_COSC_EN				(1 << 12)
-#define MXC_CCM_CCR_OSCNT_MASK				(0xFF)
-#define MXC_CCM_CCR_OSCNT_OFFSET			(0)
-
-/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
-#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
-
-/* Define the bits in register CSR */
-#define MXC_CCM_CSR_COSC_READY				(1 << 5)
-#define MXC_CCM_CSR_REF_EN_B				(1 << 0)
-
-/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS			(1 << 15)
-#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS			(1 << 14)
-#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS			(1 << 13)
-#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS			(1 << 12)
-#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS			(1 << 11)
-#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS			(1 << 10)
-#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS			(1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL				(1 << 8)
-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL			(1 << 2)
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL			(1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL			(1 << 0)
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET			(0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK			(0x7)
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK		(0x7 << 27)
-#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET		(27)
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL			(1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL			(1 << 25)
-#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK		(0x7 << 19)
-#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET		(19)
-#define MXC_CCM_CBCDR_AXI_PODF_MASK			(0x7 << 16)
-#define MXC_CCM_CBCDR_AXI_PODF_OFFSET			(16)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK			(0x7 << 10)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET			(10)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK			(0x3 << 8)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET			(8)
-#define MXC_CCM_CBCDR_AXI_ALT_SEL			(1 << 7)
-#define MXC_CCM_CBCDR_AXI_SEL				(1 << 6)
-#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK		(0x7 << 3)
-#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET		(3)
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK		(0x7 << 0)
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET		(0)
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK		(0x7 << 29)
-#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		(29)
-#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
-#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		(26)
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		(23)
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	(21)
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL		(1 << 20)
-#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK		(0x3 << 18)
-#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET		(18)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK		(0x3 << 16)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET		(16)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		(14)
-#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK		(0x3 << 12)
-#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET		(12)
-#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL			(1 << 11)
-#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL			(1 << 10)
-#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK		(0x3 << 8)
-#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	(8)
-#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
-#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		(4)
-#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL			(1 << 1)
-#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL			(1 << 0)
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK		(0x3 << 29)
-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET		(29)
-#define MXC_CCM_CSCMR1_ACLK_EMI_MASK			(0x3 << 27)
-#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET			(27)
-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK		(0x7 << 23)
-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET	(23)
-#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK		(0x7 << 20)
-#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET		(20)
-#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL			(1 << 19)
-#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL			(1 << 18)
-#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL			(1 << 17)
-#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL			(1 << 16)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK		(0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET		(14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		(12)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 10)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		(10)
-#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			(0x3F)
-
-/* Define the bits in register CSCMR2 */
-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK		(0x3 << 19)
-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		(19)
-#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
-#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3F << 2)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		(2)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK		(0x7 << 25)
-#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET		(25)
-#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK			(0x7 << 22)
-#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET		(22)
-#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK			(0x7 << 19)
-#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET		(19)
-#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK			(0x7 << 16)
-#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET		(16)
-#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK			(0x7 << 11)
-#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET		(11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		(8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		(6)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		(0x3F)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		(0)
-
-/* Define the bits in register CS1CDR */
-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET		(25)
-#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK		(0x3F << 16)
-#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET		(16)
-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK		(0x3 << 9)
-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET		(9)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		(6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK		(0x3F)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		(0)
-
-/* Define the bits in register CS2CDR */
-#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK		(0x3F << 21)
-#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET		(21)
-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		(18)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		(16)
-#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
-#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		(12)
-#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK		(0x7 << 9)
-#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET		(9)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		(6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK		(0x3F)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		(0)
-
-/* Define the bits in register CDCDR */
-#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK			(0x7 << 29)
-#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET		(29)
-#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL			(1 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET		(25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x7 << 19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET		(19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK		(0x3 << 20)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET		(20)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 12)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET		(12)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x7 << 9)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		(9)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK		(0x3 << 7)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET		(7)
-
-/* Define the bits in register CHSCCDR */
-#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
-#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET	(15)
-#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK		(0x7 << 12)
-#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET		(12)
-#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK		(0x7 << 9)
-#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET		(9)
-#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
-#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET	(6)
-#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK		(0x7 << 3)
-#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET		(3)
-#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
-#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET		(0)
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
-#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		(19)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	(15)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK		(0x7 << 12)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET		(12)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK		(0x7 << 9)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET		(9)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET	(6)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK		(0x7 << 3)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET		(3)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK		(0x7)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET		(0)
-
-/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK		(0x7 << 16)
-#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET		(16)
-#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK		(0x3 << 14)
-#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET		(14)
-#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK		(0x7 << 11)
-#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET		(11)
-#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK		(0x3 << 9)
-#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET		(9)
-
-/* Define the bits in register CDHIPR */
-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
-#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY		(1 << 4)
-#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY		(1 << 3)
-#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY		(1 << 2)
-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY			(1 << 1)
-#define MXC_CCM_CDHIPR_AXI_PODF_BUSY			(1)
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_MASK_L2CC_IDLE			(1 << 27)
-#define MXC_CCM_CLPCR_MASK_SCU_IDLE			(1 << 26)
-#define MXC_CCM_CLPCR_MASK_CORE3_WFI			(1 << 25)
-#define MXC_CCM_CLPCR_MASK_CORE2_WFI			(1 << 24)
-#define MXC_CCM_CLPCR_MASK_CORE1_WFI			(1 << 23)
-#define MXC_CCM_CLPCR_MASK_CORE0_WFI			(1 << 22)
-#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS		(1 << 21)
-#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS		(1 << 19)
-#define MXC_CCM_CLPCR_WB_CORE_AT_LPM			(1 << 17)
-#define MXC_CCM_CLPCR_WB_PER_AT_LPM			(1 << 17)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN			(1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK			(0x3 << 9)
-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET			(9)
-#define MXC_CCM_CLPCR_VSTBY				(1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC			(1 << 7)
-#define MXC_CCM_CLPCR_SBYOS				(1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM		(1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK			(0x3 << 3)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET		(3)
-#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY		(1 << 2)
-#define MXC_CCM_CLPCR_LPM_MASK				(0x3)
-#define MXC_CCM_CLPCR_LPM_OFFSET			(0)
-
-/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED			(1 << 26)
-#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED		(1 << 23)
-#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED		(1 << 22)
-#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED		(1 << 21)
-#define MXC_CCM_CISR_AHB_PODF_LOADED			(1 << 20)
-#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED		(1 << 19)
-#define MXC_CCM_CISR_AXI_PODF_LOADED			(1 << 17)
-#define MXC_CCM_CISR_COSC_READY				(1 << 6)
-#define MXC_CCM_CISR_LRF_PLL				(1)
-
-/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(1 << 26)
-#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED		(1 << 23)
-#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED		(1 << 22)
-#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED		(1 << 21)
-#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED		(1 << 20)
-#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED	(1 << 22)
-#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED		(1 << 17)
-#define MXC_CCM_CIMR_MASK_COSC_READY			(1 << 6)
-#define MXC_CCM_CIMR_MASK_LRF_PLL			(1)
-
-/* Define the bits in register CCOSR */
-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET			(1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK			(0x7 << 21)
-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET			(21)
-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET			(16)
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
-#define MXC_CCM_CCOSR_CKOL_EN				(0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET			(4)
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK			(0xF)
-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET			(0)
-
-/* Define the bits in registers CGPR */
-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(1 << 4)
-#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS			(1 << 2)
-#define MXC_CCM_CGPR_PMIC_DELAY_SCALER			(1)
-
-#endif				/* __ARCH_ARM_MACH_MX6_CRM_REGS_H__ */
diff --git a/arch/arm/mach-imx/include/mach/clock-vf610.h b/arch/arm/mach-imx/include/mach/clock-vf610.h
deleted file mode 100644
index 0fa70a4385..0000000000
--- a/arch/arm/mach-imx/include/mach/clock-vf610.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MACH_CLOCK_VF610_H__
-#define __MACH_CLOCK_VF610_H__
-
-#define VF610_CCM_CCR				(VF610_CCM_BASE_ADDR + 0x00)
-#define VF610_CCM_CSR				(VF610_CCM_BASE_ADDR + 0x04)
-#define VF610_CCM_CCSR				(VF610_CCM_BASE_ADDR + 0x08)
-#define VF610_CCM_CACRR				(VF610_CCM_BASE_ADDR + 0x0c)
-#define VF610_CCM_CSCMR1			(VF610_CCM_BASE_ADDR + 0x10)
-#define VF610_CCM_CSCDR1			(VF610_CCM_BASE_ADDR + 0x14)
-#define VF610_CCM_CSCDR2			(VF610_CCM_BASE_ADDR + 0x18)
-#define VF610_CCM_CSCDR3			(VF610_CCM_BASE_ADDR + 0x1c)
-#define VF610_CCM_CSCMR2			(VF610_CCM_BASE_ADDR + 0x20)
-#define VF610_CCM_CTOR				(VF610_CCM_BASE_ADDR + 0x28)
-#define VF610_CCM_CLPCR				(VF610_CCM_BASE_ADDR + 0x80)
-#define VF610_CCM_CMEOR5			(VF610_CCM_BASE_ADDR + 0x84)
-#define VF610_CCM_CPPDSR			(VF610_CCM_BASE_ADDR + 0x88)
-#define VF610_CCM_CCOWR				(VF610_CCM_BASE_ADDR + 0x8c)
-#define VF610_CCM_CCPGR0			(VF610_CCM_BASE_ADDR + 0x90)
-#define VF610_CCM_CCPGR1			(VF610_CCM_BASE_ADDR + 0x94)
-#define VF610_CCM_CCPGR2			(VF610_CCM_BASE_ADDR + 0x98)
-#define VF610_CCM_CCPGR3			(VF610_CCM_BASE_ADDR + 0x9c)
-
-#define VF610_CCM_CCGRx_CGn(n)	((n) * 2)
-
-#define VF610_ANADIG_PLL1_CTRL			(VF610_ANADIG_BASE_ADDR + 0x270)
-#define VF610_ANADIG_PLL1_NUM			(VF610_ANADIG_BASE_ADDR + 0x290)
-#define VF610_ANADIG_PLL1_DENOM			(VF610_ANADIG_BASE_ADDR + 0x2A0)
-#define VF610_ANADIG_PLL2_CTRL			(VF610_ANADIG_BASE_ADDR + 0x30)
-#define VF610_ANADIG_PLL2_NUM			(VF610_ANADIG_BASE_ADDR + 0x50)
-#define VF610_ANADIG_PLL3_CTRL			(VF610_ANADIG_BASE_ADDR + 0x10)
-#define VF610_ANADIG_PLL4_CTRL			(VF610_ANADIG_BASE_ADDR + 0x70)
-#define VF610_ANADIG_PLL5_CTRL			(VF610_ANADIG_BASE_ADDR + 0xe0)
-#define VF610_ANADIG_PLL6_CTRL			(VF610_ANADIG_BASE_ADDR + 0xa0)
-#define VF610_ANADIG_PLL7_CTRL			(VF610_ANADIG_BASE_ADDR + 0x20)
-#define VF610_ANADIG_ANA_MISC1			(VF610_ANADIG_BASE_ADDR + 0x160)
-#define VF610_ANADIG_LOCK			(VF610_ANADIG_BASE_ADDR + 0x2C0)
-
-#define CCM_CCR_FIRC_EN				(1 << 16)
-#define CCM_CCR_OSCNT_MASK			0xff
-#define CCM_CCR_OSCNT(v)			((v) & 0xff)
-
-#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET	19
-#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK		(0x7 << 19)
-#define CCM_CCSR_PLL2_PFD_CLK_SEL(v)		(((v) & 0x7) << 19)
-
-#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET	16
-#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK		(0x7 << 16)
-#define CCM_CCSR_PLL1_PFD_CLK_SEL(v)		(((v) & 0x7) << 16)
-
-#define CCM_CCSR_PLL2_PFD4_EN			(1 << 15)
-#define CCM_CCSR_PLL2_PFD3_EN			(1 << 14)
-#define CCM_CCSR_PLL2_PFD2_EN			(1 << 13)
-#define CCM_CCSR_PLL2_PFD1_EN			(1 << 12)
-#define CCM_CCSR_PLL1_PFD4_EN			(1 << 11)
-#define CCM_CCSR_PLL1_PFD3_EN			(1 << 10)
-#define CCM_CCSR_PLL1_PFD2_EN			(1 << 9)
-#define CCM_CCSR_PLL1_PFD1_EN			(1 << 8)
-
-#define CCM_CCSR_DDRC_CLK_SEL(v)		((v) << 6)
-#define CCM_CCSR_FAST_CLK_SEL(v)		((v) << 5)
-
-#define CCM_CCSR_SYS_CLK_SEL_OFFSET		0
-#define CCM_CCSR_SYS_CLK_SEL_MASK		0x7
-#define CCM_CCSR_SYS_CLK_SEL(v)			((v) & 0x7)
-
-#define CCM_CACRR_IPG_CLK_DIV_OFFSET		11
-#define CCM_CACRR_IPG_CLK_DIV_MASK		(0x3 << 11)
-#define CCM_CACRR_IPG_CLK_DIV(v)		(((v) & 0x3) << 11)
-#define CCM_CACRR_BUS_CLK_DIV_OFFSET		3
-#define CCM_CACRR_BUS_CLK_DIV_MASK		(0x7 << 3)
-#define CCM_CACRR_BUS_CLK_DIV(v)		(((v) & 0x7) << 3)
-#define CCM_CACRR_ARM_CLK_DIV_OFFSET		0
-#define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
-#define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
-
-#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET		22
-#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK		(0x3 << 22)
-#define CCM_CSCMR1_QSPI0_CLK_SEL(v)		(((v) & 0x3) << 22)
-#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET	18
-#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK		(0x3 << 18)
-#define CCM_CSCMR1_ESDHC1_CLK_SEL(v)		(((v) & 0x3) << 18)
-#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET		12
-#define CCM_CSCMR1_NFC_CLK_SEL_MASK		(0x3 << 12)
-#define CCM_CSCMR1_NFC_CLK_SEL(v)		(((v) & 0x3) << 12)
-
-#define CCM_CSCDR1_RMII_CLK_EN			(1 << 24)
-
-#define CCM_CSCDR2_NFC_EN			(1 << 9)
-#define CCM_CSCDR2_NFC_FRAC_DIV_EN		(1 << 13)
-#define CCM_CSCDR2_NFC_CLK_INV			(1 << 14)
-#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET		4
-#define CCM_CSCDR2_NFC_FRAC_DIV_MASK		(0xf << 4)
-#define CCM_CSCDR2_NFC_FRAC_DIV(v)		(((v) & 0xf) << 4)
-
-#define CCM_CSCDR2_ESDHC1_EN			(1 << 29)
-#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET	20
-#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
-#define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
-
-#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET		13
-#define CCM_CSCDR3_NFC_PRE_DIV_MASK		(0x7 << 13)
-#define CCM_CSCDR3_NFC_PRE_DIV(v)		(((v) & 0x7) << 13)
-#define CCM_CSCDR3_QSPI0_EN			(1 << 4)
-#define CCM_CSCDR3_QSPI0_DIV(v)			((v) << 3)
-#define CCM_CSCDR3_QSPI0_X2_DIV(v)		((v) << 2)
-#define CCM_CSCDR3_QSPI0_X4_DIV(v)		((v) & 0x3)
-
-#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET		4
-#define CCM_CSCMR2_RMII_CLK_SEL_MASK		(0x3 << 4)
-#define CCM_CSCMR2_RMII_CLK_SEL(v)		(((v) & 0x3) << 4)
-
-#define CCM_REG_CTRL_MASK			0xffffffff
-#define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
-#define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
-#define CCM_CCGR0_DSPI0_CTRL_MASK		(0x3 << 24)
-#define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
-#define CCM_CCGR1_USBC0_CTRL_MASK		(0x3 << 8)
-#define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
-#define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
-#define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
-#define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)
-#define CCM_CCGR2_PORTA_CTRL_MASK		(0x3 << 18)
-#define CCM_CCGR2_PORTB_CTRL_MASK		(0x3 << 20)
-#define CCM_CCGR2_PORTC_CTRL_MASK		(0x3 << 22)
-#define CCM_CCGR2_PORTD_CTRL_MASK		(0x3 << 24)
-#define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
-#define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
-#define CCM_CCGR3_SCSC_CTRL_MASK		(0x3 << 4)
-#define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
-#define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
-#define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
-#define CCM_CCGR4_I2C0_CTRL_MASK		(0x3 << 12)
-#define CCM_CCGR4_I2C1_CTRL_MASK		(0x3 << 14)
-#define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
-#define CCM_CCGR6_DSPI2_CTRL_MASK		(0x3 << 24)
-#define CCM_CCGR6_DSPI3_CTRL_MASK		(0x3 << 26)
-#define CCM_CCGR6_DDRMC_CTRL_MASK		(0x3 << 28)
-#define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
-#define CCM_CCGR7_USBC1_CTRL_MASK		(0x3 << 8)
-#define CCM_CCGR9_FEC0_CTRL_MASK		0x3
-#define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
-#define CCM_CCGR10_NFC_CTRL_MASK		0x3
-#define CCM_CCGR10_I2C2_CTRL_MASK		(0x3 << 12)
-#define CCM_CCGR10_I2C3_CTRL_MASK		(0x3 << 14)
-
-#define ANADIG_PLL7_CTRL_BYPASS			(1 << 16)
-#define ANADIG_PLL7_CTRL_ENABLE			(1 << 13)
-#define ANADIG_PLL7_CTRL_POWERDOWN		(1 << 12)
-#define ANADIG_PLL7_CTRL_DIV_SELECT		(1 << 1)
-#define ANADIG_PLL5_CTRL_BYPASS			(1 << 16)
-#define ANADIG_PLL5_CTRL_ENABLE			(1 << 13)
-#define ANADIG_PLL5_CTRL_POWERDOWN		(1 << 12)
-#define ANADIG_PLL5_CTRL_DIV_SELECT		1
-#define ANADIG_PLL3_CTRL_BYPASS			(1 << 16)
-#define ANADIG_PLL3_CTRL_ENABLE			(1 << 13)
-#define ANADIG_PLL3_CTRL_POWERDOWN		(1 << 12)
-#define ANADIG_PLL3_CTRL_DIV_SELECT		(1 << 1)
-#define ANADIG_PLL2_CTRL_ENABLE			(1 << 13)
-#define ANADIG_PLL2_CTRL_POWERDOWN		(1 << 12)
-#define ANADIG_PLL2_CTRL_DIV_SELECT		1
-#define ANADIG_PLL1_CTRL_ENABLE			(1 << 13)
-#define ANADIG_PLL1_CTRL_POWERDOWN		(1 << 12)
-#define ANADIG_PLL1_CTRL_DIV_SELECT		1
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h
deleted file mode 100644
index 304a7c885c..0000000000
--- a/arch/arm/mach-imx/include/mach/clock.h
+++ /dev/null
@@ -1 +0,0 @@
-/* nothing, but some drivers need this include */
diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
deleted file mode 100644
index a4c57c5d5a..0000000000
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ /dev/null
@@ -1,165 +0,0 @@
-#ifndef __MACH_DEBUG_LL_H__
-#define __MACH_DEBUG_LL_H__
-
-#include <io.h>
-#include <config.h>
-#include <common.h>
-#include <mach/imx1-regs.h>
-#include <mach/imx21-regs.h>
-#include <mach/imx25-regs.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx31-regs.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx50-regs.h>
-#include <mach/imx51-regs.h>
-#include <mach/imx53-regs.h>
-#include <mach/imx6-regs.h>
-#include <mach/imx7-regs.h>
-#include <mach/imx8m-regs.h>
-#include <mach/vf610-regs.h>
-
-#include <serial/imx-uart.h>
-#include <serial/lpuart.h>
-
-#ifdef CONFIG_DEBUG_LL
-
-#define __IMX_UART_BASE(soc, num) soc##_UART##num##_BASE_ADDR
-#define IMX_UART_BASE(soc, num) __IMX_UART_BASE(soc, num)
-
-#ifdef CONFIG_DEBUG_IMX1_UART
-#define IMX_DEBUG_SOC MX1
-#elif defined CONFIG_DEBUG_IMX21_UART
-#define IMX_DEBUG_SOC MX21
-#elif defined CONFIG_DEBUG_IMX25_UART
-#define IMX_DEBUG_SOC MX25
-#elif defined CONFIG_DEBUG_IMX27_UART
-#define IMX_DEBUG_SOC MX27
-#elif defined CONFIG_DEBUG_IMX31_UART
-#define IMX_DEBUG_SOC MX31
-#elif defined CONFIG_DEBUG_IMX35_UART
-#define IMX_DEBUG_SOC MX35
-#elif defined CONFIG_DEBUG_IMX50_UART
-#define IMX_DEBUG_SOC MX50
-#elif defined CONFIG_DEBUG_IMX51_UART
-#define IMX_DEBUG_SOC MX51
-#elif defined CONFIG_DEBUG_IMX53_UART
-#define IMX_DEBUG_SOC MX53
-#elif defined CONFIG_DEBUG_IMX6Q_UART
-#define IMX_DEBUG_SOC MX6
-#elif defined CONFIG_DEBUG_IMX7D_UART
-#define IMX_DEBUG_SOC MX7
-#elif defined CONFIG_DEBUG_IMX8M_UART
-#define IMX_DEBUG_SOC MX8M
-#elif defined CONFIG_DEBUG_VF610_UART
-#define IMX_DEBUG_SOC VF610
-#else
-#error "unknown i.MX debug uart soc type"
-#endif
-
-static inline void imx50_uart_setup_ll(void)
-{
-	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
-
-	imx50_uart_setup(base);
-}
-
-static inline void imx51_uart_setup_ll(void)
-{
-	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
-
-	imx51_uart_setup(base);
-}
-
-static inline void imx53_uart_setup_ll(void)
-{
-	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
-
-	imx53_uart_setup(base);
-}
-
-static inline void imx6_uart_setup_ll(void)
-{
-	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
-
-	imx6_uart_setup(base);
-}
-
-static inline void imx7_uart_setup_ll(void)
-{
-	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
-
-	imx7_uart_setup(base);
-}
-
-static inline void vf610_uart_setup_ll(void)
-{
-	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
-
-	lpuart_setup(base, 66000000);
-}
-
-static inline void imx8m_uart_setup_ll(void)
-{
-	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
-					 CONFIG_DEBUG_IMX_UART_PORT));
-	imx8m_uart_setup(base);
-}
-
-static inline void PUTC_LL(int c)
-{
-	void __iomem *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
-						 CONFIG_DEBUG_IMX_UART_PORT));
-
-	if (!base)
-		return;
-
-	if (IS_ENABLED(CONFIG_DEBUG_VF610_UART))
-		lpuart_putc(base, c);
-	else
-		imx_uart_putc(base, c);
-}
-
-#else
-
-static inline void imx50_uart_setup_ll(void) {}
-static inline void imx51_uart_setup_ll(void) {}
-static inline void imx53_uart_setup_ll(void) {}
-static inline void imx6_uart_setup_ll(void)  {}
-static inline void imx7_uart_setup_ll(void)  {}
-static inline void vf610_uart_setup_ll(void) {}
-static inline void imx8m_uart_setup_ll(void) {}
-
-#endif /* CONFIG_DEBUG_LL */
-
-static inline void imx_ungate_all_peripherals(void __iomem *ccmbase)
-{
-	int i;
-	for (i = 0x68; i <= 0x80; i += 4)
-		writel(0xffffffff, ccmbase + i);
-}
-
-static inline void imx6_ungate_all_peripherals(void)
-{
-	imx_ungate_all_peripherals(IOMEM(MX6_CCM_BASE_ADDR));
-}
-
-static inline void imx51_ungate_all_peripherals(void)
-{
-	imx_ungate_all_peripherals(IOMEM(MX51_CCM_BASE_ADDR));
-}
-
-static inline void imx53_ungate_all_peripherals(void)
-{
-	imx_ungate_all_peripherals(IOMEM(MX53_CCM_BASE_ADDR));
-}
-
-static inline void vf610_ungate_all_peripherals(void)
-{
-	void __iomem *ccmbase = IOMEM(VF610_CCM_BASE_ADDR);
-	int i;
-
-	for (i = 0x40; i <= 0x6c; i += 4)
-		writel(0xffffffff, ccmbase + i);
-}
-
-#endif /* __MACH_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-imx/include/mach/devices-imx1.h b/arch/arm/mach-imx/include/mach/devices-imx1.h
deleted file mode 100644
index e4185bc281..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx1.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <mach/devices.h>
-#include <mach/imx1-regs.h>
-
-static inline struct device_d *imx1_add_uart0(void)
-{
-	return imx_add_uart_imx1((void *)MX1_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx1_add_uart1(void)
-{
-	return imx_add_uart_imx1((void *)MX1_UART2_BASE_ADDR, 1);
-}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx21.h b/arch/arm/mach-imx/include/mach/devices-imx21.h
deleted file mode 100644
index 5b2dfd7505..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx21.h
+++ /dev/null
@@ -1,34 +0,0 @@
-
-#include <mach/devices.h>
-#include <mach/imx21-regs.h>
-
-static inline struct device_d *imx21_add_uart0(void)
-{
-	return imx_add_uart_imx21((void *)MX21_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx21_add_uart1(void)
-{
-	return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 1);
-}
-
-static inline struct device_d *imx21_add_uart2(void)
-{
-	return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 2);
-}
-
-static inline struct device_d *imx21_add_uart3(void)
-{
-	return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 3);
-}
-
-static inline struct device_d *imx21_add_nand(struct imx_nand_platform_data *pdata)
-{
-	return imx_add_nand((void *)0xDF003000, pdata);
-}
-
-static inline struct device_d *imx21_add_fb(struct imx_fb_platform_data *pdata)
-{
-	return imx_add_fb((void *)0x10021000, pdata);
-}
-
diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h
deleted file mode 100644
index 7779a02be1..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx25.h
+++ /dev/null
@@ -1,83 +0,0 @@
-
-#include <mach/devices.h>
-#include <mach/imx25-regs.h>
-
-static inline struct device_d *imx25_add_i2c0(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX25_I2C1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx25_add_i2c1(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX25_I2C2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx25_add_i2c2(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX25_I2C3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx25_add_spi0(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX25_CSPI1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx25_add_spi1(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX25_CSPI2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx25_add_spi2(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX25_CSPI3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx25_add_uart0(void)
-{
-	return imx_add_uart_imx21((void *)MX25_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx25_add_uart1(void)
-{
-	return imx_add_uart_imx21((void *)MX25_UART2_BASE_ADDR, 1);
-}
-
-static inline struct device_d *imx25_add_uart2(void)
-{
-	return imx_add_uart_imx21((void *)MX25_UART3_BASE_ADDR, 2);
-}
-
-static inline struct device_d *imx25_add_uart3(void)
-{
-	return imx_add_uart_imx21((void *)MX25_UART4_BASE_ADDR, 3);
-}
-
-static inline struct device_d *imx25_add_uart4(void)
-{
-	return imx_add_uart_imx21((void *)MX25_UART5_BASE_ADDR, 4);
-}
-
-static inline struct device_d *imx25_add_nand(struct imx_nand_platform_data *pdata)
-{
-	return imx_add_nand((void *)MX25_NFC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx25_add_fb(struct imx_fb_platform_data *pdata)
-{
-	return imx_add_fb((void *)MX25_LCDC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx25_add_fec(struct fec_platform_data *pdata)
-{
-	return imx_add_fec_imx27((void *)MX25_FEC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx25_add_mmc0(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx25((void *)MX25_ESDHC1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx25_add_mmc1(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx25((void *)MX25_ESDHC2_BASE_ADDR, 1, pdata);
-}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h
deleted file mode 100644
index da2289b191..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx27.h
+++ /dev/null
@@ -1,88 +0,0 @@
-
-#include <mach/devices.h>
-#include <mach/imx27-regs.h>
-
-static inline struct device_d *imx27_add_spi0(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx27((void *)MX27_CSPI1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx27_add_spi1(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx27((void *)MX27_CSPI2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx27_add_i2c0(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX27_I2C1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx27_add_i2c1(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX27_I2C2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx27_add_uart0(void)
-{
-	return imx_add_uart_imx21((void *)MX27_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx27_add_uart1(void)
-{
-	return imx_add_uart_imx21((void *)MX27_UART2_BASE_ADDR, 1);
-}
-
-static inline struct device_d *imx27_add_uart2(void)
-{
-	return imx_add_uart_imx21((void *)MX27_UART3_BASE_ADDR, 2);
-}
-
-static inline struct device_d *imx27_add_uart3(void)
-{
-	return imx_add_uart_imx21((void *)MX27_UART4_BASE_ADDR, 3);
-}
-
-static inline struct device_d *imx27_add_nand(struct imx_nand_platform_data *pdata)
-{
-	return imx_add_nand((void *)MX27_NFC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx27_add_fb(struct imx_fb_platform_data *pdata)
-{
-	return imx_add_fb((void *)MX27_LCDC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx27_add_fec(struct fec_platform_data *pdata)
-{
-	return imx_add_fec_imx27((void *)MX27_FEC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx27_add_mmc0(void *pdata)
-{
-	return imx_add_mmc((void *)MX27_SDHC1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx27_add_mmc1(void *pdata)
-{
-	return imx_add_mmc((void *)MX27_SDHC2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx27_add_mmc2(void *pdata)
-{
-	return imx_add_mmc((void *)MX27_SDHC3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx27_add_usbotg(void *pdata)
-{
-	return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx27_add_usbh1(void *pdata)
-{
-	return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR + 0x200, 1, pdata);
-}
-
-static inline struct device_d *imx27_add_usbh2(void *pdata)
-{
-	return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR + 0x400, 2, pdata);
-}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h
deleted file mode 100644
index 51125d1bca..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx31.h
+++ /dev/null
@@ -1,93 +0,0 @@
-
-#include <mach/imx31-regs.h>
-#include <mach/devices.h>
-
-static inline struct device_d *imx31_add_i2c0(void *pdata)
-{
-	return imx_add_i2c((void *)MX31_I2C1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx31_add_i2c1(void *pdata)
-{
-	return imx_add_i2c((void *)MX31_I2C2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx31_add_i2c2(void *pdata)
-{
-	return imx_add_i2c((void *)MX31_I2C3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX31_CSPI1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx31_add_spi1(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX31_CSPI2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx31_add_spi2(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX31_CSPI3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx31_add_uart0(void)
-{
-	return imx_add_uart_imx21((void *)MX31_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx31_add_uart1(void)
-{
-	return imx_add_uart_imx21((void *)MX31_UART2_BASE_ADDR, 1);
-}
-
-static inline struct device_d *imx31_add_uart2(void)
-{
-	return imx_add_uart_imx21((void *)MX31_UART3_BASE_ADDR, 2);
-}
-
-static inline struct device_d *imx31_add_uart3(void)
-{
-	return imx_add_uart_imx21((void *)MX31_UART4_BASE_ADDR, 3);
-}
-
-static inline struct device_d *imx31_add_uart4(void)
-{
-	return imx_add_uart_imx21((void *)MX31_UART5_BASE_ADDR, 4);
-}
-
-static inline struct device_d *imx31_add_nand(struct imx_nand_platform_data *pdata)
-{
-	return imx_add_nand((void *)MX31_NFC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pdata)
-{
-	return imx_add_ipufb((void *)MX31_IPU_CTRL_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx31_add_mmc0(void *pdata)
-{
-	return imx_add_mmc((void *)MX31_SDHC1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx31_add_mmc1(void *pdata)
-{
-	return imx_add_mmc((void *)MX31_SDHC2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx31_add_usbotg(void *pdata)
-{
-	return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx31_add_usbh1(void *pdata)
-{
-	return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR + 0x200, 1, pdata);
-}
-
-static inline struct device_d *imx31_add_usbh2(void *pdata)
-{
-	return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR + 0x400, 2, pdata);
-}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h
deleted file mode 100644
index 922bb589c6..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx35.h
+++ /dev/null
@@ -1,73 +0,0 @@
-
-#include <mach/devices.h>
-#include <mach/imx35-regs.h>
-
-static inline struct device_d *imx35_add_i2c0(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX35_I2C1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx35_add_i2c1(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX35_I2C2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx35_add_i2c2(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX35_I2C3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx35_add_spi0(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX35_CSPI1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx35_add_spi(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX35_CSPI2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx35_add_uart0(void)
-{
-	return imx_add_uart_imx21((void *)MX35_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx35_add_uart1(void)
-{
-	return imx_add_uart_imx21((void *)MX35_UART2_BASE_ADDR, 1);
-}
-
-static inline struct device_d *imx35_add_uart2(void)
-{
-	return imx_add_uart_imx21((void *)MX35_UART3_BASE_ADDR, 2);
-}
-
-static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata)
-{
-	return imx_add_nand((void *)MX35_NFC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx35_add_fb(struct imx_ipu_fb_platform_data *pdata)
-{
-	return imx_add_ipufb((void *)MX35_IPU_CTRL_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata)
-{
-	return imx_add_fec_imx27((void *)MX35_FEC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx35_add_mmc0(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx25((void *)MX35_ESDHC1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx35_add_mmc1(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx25((void *)MX35_ESDHC2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx35_add_mmc2(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx25((void *)MX35_ESDHC3_BASE_ADDR, 2, pdata);
-}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx50.h b/arch/arm/mach-imx/include/mach/devices-imx50.h
deleted file mode 100644
index 7e5141a107..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx50.h
+++ /dev/null
@@ -1,83 +0,0 @@
-
-#include <mach/devices.h>
-#include <mach/imx50-regs.h>
-
-static inline struct device_d *imx50_add_spi0(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX50_ECSPI1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx50_add_spi1(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX50_ECSPI2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx50_add_cspi(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX50_CSPI_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx50_add_i2c0(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX50_I2C1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx50_add_i2c1(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX50_I2C2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx50_add_i2c2(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX50_I2C3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx50_add_uart0(void)
-{
-	return imx_add_uart_imx21((void *)MX50_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx50_add_uart1(void)
-{
-	return imx_add_uart_imx21((void *)MX50_UART2_BASE_ADDR, 1);
-}
-
-static inline struct device_d *imx50_add_uart2(void)
-{
-	return imx_add_uart_imx21((void *)MX50_UART3_BASE_ADDR, 2);
-}
-
-static inline struct device_d *imx50_add_uart3(void)
-{
-	return imx_add_uart_imx21((void *)MX50_UART4_BASE_ADDR, 3);
-}
-
-static inline struct device_d *imx50_add_fec(struct fec_platform_data *pdata)
-{
-	return imx_add_fec_imx27((void *)MX50_FEC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx50_add_mmc0(struct esdhc_platform_data *pdata)
-{
-	return imx5_add_esdhc((void *)MX50_ESDHC1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx50_add_mmc1(struct esdhc_platform_data *pdata)
-{
-	return imx5_add_esdhc((void *)MX50_ESDHC2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx50_add_mmc2(struct esdhc_platform_data *pdata)
-{
-	return imx5_add_esdhc((void *)MX50_ESDHC3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx50_add_mmc3(struct esdhc_platform_data *pdata)
-{
-	return imx5_add_esdhc((void *)MX50_ESDHC4_BASE_ADDR, 3, pdata);
-}
-
-static inline struct device_d *imx50_add_kpp(struct matrix_keymap_data *pdata)
-{
-	return imx_add_kpp((void *)MX50_KPP_BASE_ADDR, pdata);
-}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h
deleted file mode 100644
index 5a968a3000..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx51.h
+++ /dev/null
@@ -1,116 +0,0 @@
-
-#include <linux/sizes.h>
-#include <mach/devices.h>
-#include <mach/imx51-regs.h>
-
-static inline struct device_d *imx51_add_spi0(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX51_ECSPI1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx51_add_spi1(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX51_ECSPI2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx51_add_cspi(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX51_CSPI_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx51_add_i2c0(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX51_I2C1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx51_add_i2c1(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX51_I2C2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx51_add_uart0(void)
-{
-	return imx_add_uart_imx21((void *)MX51_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx51_add_uart1(void)
-{
-	return imx_add_uart_imx21((void *)MX51_UART2_BASE_ADDR, 1);
-}
-
-static inline struct device_d *imx51_add_uart2(void)
-{
-	return imx_add_uart_imx21((void *)MX51_UART3_BASE_ADDR, 2);
-}
-
-static inline struct device_d *imx51_add_fec(struct fec_platform_data *pdata)
-{
-	return imx_add_fec_imx27((void *)MX51_MXC_FEC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx51_add_mmc0(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx5((void *)MX51_MMC_SDHC1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx51_add_mmc1(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx5((void *)MX51_MMC_SDHC2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx51_add_mmc2(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx5((void *)MX51_MMC_SDHC3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx51_add_nand(struct imx_nand_platform_data *pdata)
-{
-	struct resource res[] = {
-		{
-			.start = MX51_NFC_BASE_ADDR,
-			.end = MX51_NFC_BASE_ADDR + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = MX51_NFC_AXI_BASE_ADDR,
-			.end = MX51_NFC_AXI_BASE_ADDR + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-	};
-	struct device_d *dev = xzalloc(sizeof(*dev));
-
-	dev->resource = xzalloc(sizeof(struct resource) * ARRAY_SIZE(res));
-	memcpy(dev->resource, res, sizeof(struct resource) * ARRAY_SIZE(res));
-	dev->num_resources = ARRAY_SIZE(res);
-	dev_set_name(dev, "imx_nand");
-	dev->id = DEVICE_ID_DYNAMIC;
-	dev->platform_data = pdata;
-
-	platform_device_register(dev);
-
-	return dev;
-}
-
-static inline struct device_d *imx51_add_kpp(struct matrix_keymap_data *pdata)
-{
-	return imx_add_kpp((void *)MX51_KPP_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx51_add_pata(void)
-{
-	return imx_add_pata((void *)MX51_ATA_BASE_ADDR);
-}
-
-static inline struct device_d *imx51_add_usbotg(void *pdata)
-{
-	return imx_add_usb((void *)MX51_OTG_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx51_add_usbh1(void *pdata)
-{
-	return imx_add_usb((void *)MX51_OTG_BASE_ADDR + 0x200, 1, pdata);
-}
-
-static inline struct device_d *imx51_add_usbh2(void *pdata)
-{
-	return imx_add_usb((void *)MX51_OTG_BASE_ADDR + 0x400, 2, pdata);
-}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx53.h b/arch/arm/mach-imx/include/mach/devices-imx53.h
deleted file mode 100644
index e5c257a40b..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx53.h
+++ /dev/null
@@ -1,115 +0,0 @@
-
-#include <mach/devices.h>
-#include <mach/imx53-regs.h>
-
-static inline struct device_d *imx53_add_cspi(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx35((void *)MX53_CSPI_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx53_add_spi0(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX53_ECSPI1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx53_add_spi1(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX53_ECSPI2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx53_add_i2c0(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX53_I2C1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx53_add_i2c1(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX53_I2C2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx53_add_i2c2(struct i2c_platform_data *pdata)
-{
-       return imx_add_i2c((void *)MX53_I2C3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx53_add_uart0(void)
-{
-	return imx_add_uart_imx21((void *)MX53_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx53_add_uart1(void)
-{
-	return imx_add_uart_imx21((void *)MX53_UART2_BASE_ADDR, 1);
-}
-
-static inline struct device_d *imx53_add_uart2(void)
-{
-	return imx_add_uart_imx21((void *)MX53_UART3_BASE_ADDR, 2);
-}
-
-static inline struct device_d *imx53_add_uart3(void)
-{
-	return imx_add_uart_imx21((void *)MX53_UART4_BASE_ADDR, 3);
-}
-
-static inline struct device_d *imx53_add_fec(struct fec_platform_data *pdata)
-{
-	return imx_add_fec_imx27((void *)MX53_FEC_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx53_add_mmc0(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx5((void *)MX53_ESDHC1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx53_add_mmc1(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx5((void *)MX53_ESDHC2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx53_add_mmc2(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx5((void *)MX53_ESDHC3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx53_add_mmc3(struct esdhc_platform_data *pdata)
-{
-	return imx_add_esdhc_imx5((void *)MX53_ESDHC4_BASE_ADDR, 3, pdata);
-}
-
-static inline struct device_d *imx53_add_nand(struct imx_nand_platform_data *pdata)
-{
-	struct resource res[] = {
-		{
-			.start = MX53_NFC_BASE_ADDR,
-			.end = MX53_NFC_BASE_ADDR + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = MX53_NFC_AXI_BASE_ADDR,
-			.end = MX53_NFC_AXI_BASE_ADDR + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-	};
-	struct device_d *dev = xzalloc(sizeof(*dev));
-
-	dev->resource = xzalloc(sizeof(struct resource) * ARRAY_SIZE(res));
-	memcpy(dev->resource, res, sizeof(struct resource) * ARRAY_SIZE(res));
-	dev->num_resources = ARRAY_SIZE(res);
-	dev_set_name(dev, "imx_nand");
-	dev->id = DEVICE_ID_DYNAMIC;
-	dev->platform_data = pdata;
-
-	platform_device_register(dev);
-
-	return dev;
-}
-
-static inline struct device_d *imx53_add_kpp(struct matrix_keymap_data *pdata)
-{
-	return imx_add_kpp((void *)MX53_KPP_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx53_add_sata(void)
-{
-	return add_generic_device("imx53-sata", 0, NULL, MX53_SATA_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
-}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h
deleted file mode 100644
index 9471f57909..0000000000
--- a/arch/arm/mach-imx/include/mach/devices-imx6.h
+++ /dev/null
@@ -1,98 +0,0 @@
-#include <mach/devices.h>
-#include <mach/imx6-regs.h>
-
-static inline struct device_d *imx6_add_uart0(void)
-{
-	return imx_add_uart_imx21((void *)MX6_UART1_BASE_ADDR, 0);
-}
-
-static inline struct device_d *imx6_add_uart1(void)
-{
-	return imx_add_uart_imx21((void *)MX6_UART2_BASE_ADDR, 1);
-}
-
-static inline struct device_d *imx6_add_uart2(void)
-{
-	return imx_add_uart_imx21((void *)MX6_UART3_BASE_ADDR, 2);
-}
-
-static inline struct device_d *imx6_add_uart3(void)
-{
-	return imx_add_uart_imx21((void *)MX6_UART4_BASE_ADDR, 3);
-}
-
-static inline struct device_d *imx6_add_fec(struct fec_platform_data *pdata)
-{
-	return imx_add_fec_imx6((void *)MX6_ENET_BASE_ADDR, pdata);
-}
-
-static inline struct device_d *imx6_add_spi0(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX6_ECSPI1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx6_add_spi1(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX6_ECSPI2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx6_add_spi2(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX6_ECSPI3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx6_add_spi3(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX6_ECSPI4_BASE_ADDR, 3, pdata);
-}
-
-static inline struct device_d *imx6_add_spi4(struct spi_imx_master *pdata)
-{
-	return imx_add_spi_imx51((void *)MX6_ECSPI5_BASE_ADDR, 4, pdata);
-}
-
-static inline struct device_d *imx6_add_i2c0(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX6_I2C1_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx6_add_i2c1(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX6_I2C2_BASE_ADDR, 1, pdata);
-}
-
-static inline struct device_d *imx6_add_i2c2(struct i2c_platform_data *pdata)
-{
-	return imx_add_i2c((void *)MX6_I2C3_BASE_ADDR, 2, pdata);
-}
-
-static inline struct device_d *imx6_add_sata(void)
-{
-	return add_generic_device("imx6-sata", 0, NULL, MX6_SATA_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
-}
-
-static inline struct device_d *imx6_add_usbotg(void *pdata)
-{
-	add_generic_device("imx-usb-phy", 0, NULL, MX6_USBPHY1_BASE_ADDR, 0x1000,
-			IORESOURCE_MEM, NULL);
-
-	return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR, 0, pdata);
-}
-
-static inline struct device_d *imx6_add_usbh1(void *pdata)
-{
-	add_generic_device("imx-usb-phy", 1, NULL, MX6_USBPHY2_BASE_ADDR, 0x1000,
-			IORESOURCE_MEM, NULL);
-
-	return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR + 0x200, 1, pdata);
-}
-
-static inline struct device_d *imx6_add_usbh2(void *pdata)
-{
-	return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR + 0x400, 2, pdata);
-}
-
-static inline struct device_d *imx6_add_usbh3(void *pdata)
-{
-	return imx_add_usb((void *)MX6_USBOH3_USB_BASE_ADDR + 0x600, 2, pdata);
-}
diff --git a/arch/arm/mach-imx/include/mach/devices.h b/arch/arm/mach-imx/include/mach/devices.h
deleted file mode 100644
index 4754b92a6f..0000000000
--- a/arch/arm/mach-imx/include/mach/devices.h
+++ /dev/null
@@ -1,28 +0,0 @@
-
-#include <platform_data/eth-fec.h>
-#include <input/matrix_keypad.h>
-#include <i2c/i2c.h>
-#include <mach/spi.h>
-#include <mach/imx-nand.h>
-#include <mach/imxfb.h>
-#include <mach/imx-ipu-fb.h>
-#include <platform_data/mmc-esdhc-imx.h>
-#include <usb/chipidea-imx.h>
-
-struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata);
-struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata);
-struct device_d *imx_add_spi_imx27(void *base, int id, struct spi_imx_master *pdata);
-struct device_d *imx_add_spi_imx35(void *base, int id, struct spi_imx_master *pdata);
-struct device_d *imx_add_spi_imx51(void *base, int id, struct spi_imx_master *pdata);
-struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata);
-struct device_d *imx_add_uart_imx1(void *base, int id);
-struct device_d *imx_add_uart_imx21(void *base, int id);
-struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata);
-struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata);
-struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata);
-struct device_d *imx_add_mmc(void *base, int id, void *pdata);
-struct device_d *imx_add_esdhc_imx25(void *base, int id, struct esdhc_platform_data *pdata);
-struct device_d *imx_add_esdhc_imx5(void *base, int id, struct esdhc_platform_data *pdata);
-struct device_d *imx_add_kpp(void *base, struct matrix_keymap_data *pdata);
-struct device_d *imx_add_pata(void *base);
-struct device_d *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata);
diff --git a/arch/arm/mach-imx/include/mach/esdctl-v4.h b/arch/arm/mach-imx/include/mach/esdctl-v4.h
deleted file mode 100644
index 2e6741e0d5..0000000000
--- a/arch/arm/mach-imx/include/mach/esdctl-v4.h
+++ /dev/null
@@ -1,520 +0,0 @@
-#ifndef __MACH_ESDCTL_V4_H
-#define __MACH_ESDCTL_V4_H
-
-#define ESDCTL_V4_ESDCTL0		0x00
-#define ESDCTL_V4_ESDPDC		0x04
-#define ESDCTL_V4_ESDOTC		0x08
-#define ESDCTL_V4_ESDCFG0		0x0c
-#define ESDCTL_V4_ESDCFG1		0x10
-#define ESDCTL_V4_ESDCFG2		0x14
-#define ESDCTL_V4_ESDMISC		0x18
-#define ESDCTL_V4_ESDSCR		0x1c
-#define ESDCTL_V4_ESDREF		0x20
-#define ESDCTL_V4_ESDWCC		0x24
-#define ESDCTL_V4_ESDRCC		0x28
-#define ESDCTL_V4_ESDRWD		0x2c
-#define ESDCTL_V4_ESDOR			0x30
-#define ESDCTL_V4_ESDMRR		0x34
-#define ESDCTL_V4_ESDCFG3_LP		0x38
-#define ESDCTL_V4_ESDMR4		0x3c
-#define ESDCTL_V4_ZQHWCTRL		0x40
-#define ESDCTL_V4_ZQSWCTRL		0x44
-#define ESDCTL_V4_WLGCR			0x48
-#define ESDCTL_V4_WLDECTRL0		0x4c
-#define ESDCTL_V4_WLDECTRL1		0x50
-#define ESDCTL_V4_WLDLST		0x54
-#define ESDCTL_V4_ODTCTRL		0x58
-#define ESDCTL_V4_RDDQBY0DL		0x5c
-#define ESDCTL_V4_RDDQBY1DL		0x60
-#define ESDCTL_V4_RDDQBY2DL		0x64
-#define ESDCTL_V4_RDDQBY3DL		0x68
-#define ESDCTL_V4_WRDQBY0DL		0x6c
-#define ESDCTL_V4_WRDQBY1DL		0x70
-#define ESDCTL_V4_WRDQBY2DL		0x74
-#define ESDCTL_V4_WRDQBY3DL		0x78
-#define ESDCTL_V4_DGCTRL0		0x7c
-#define ESDCTL_V4_DGCTRL1		0x80
-#define ESDCTL_V4_DGDLST		0x84
-#define ESDCTL_V4_RDDLCTL		0x88
-#define ESDCTL_V4_RDDLST		0x8c
-#define ESDCTL_V4_WRDLCTL		0x90
-#define ESDCTL_V4_WRDLST		0x94
-#define ESDCTL_V4_SDCTRL		0x98
-#define ESDCTL_V4_ZQLP2CTL		0x9c
-#define ESDCTL_V4_RDDLHWCTL		0xa0
-#define ESDCTL_V4_WRDLHWCTL		0xa4
-#define ESDCTL_V4_RDDLHWST0		0xa8
-#define ESDCTL_V4_RDDLHWST1		0xac
-#define ESDCTL_V4_WRDLHWST0		0xb0
-#define ESDCTL_V4_WRDLHWST1		0xb4
-#define ESDCTL_V4_WLHWERR		0xb8
-#define ESDCTL_V4_DGHWST0		0xbc
-#define ESDCTL_V4_DGHWST1		0xc0
-#define ESDCTL_V4_DGHWST2		0xc4
-#define ESDCTL_V4_DGHWST3		0xc8
-#define ESDCTL_V4_PDCMPR1		0xcc
-#define ESDCTL_V4_PDCMPR2		0xd0
-#define ESDCTL_V4_SWDADR		0xd4
-#define ESDCTL_V4_SWDRDR0		0xd8
-#define ESDCTL_V4_SWDRDR1		0xdc
-#define ESDCTL_V4_SWDRDR2		0xe0
-#define ESDCTL_V4_SWDRDR3		0xe4
-#define ESDCTL_V4_SWDRDR4		0xe8
-#define ESDCTL_V4_SWDRDR5		0xec
-#define ESDCTL_V4_SWDRDR6		0xf0
-#define ESDCTL_V4_SWDRDR7		0xf4
-#define ESDCTL_V4_MUR			0xf8
-#define ESDCTL_V4_WRCADL		0xfc
-
-#define ESDCTL_V4_ESDCTLx_SDE0				0x80000000
-#define ESDCTL_V4_ESDCTLx_SDE1				0x40000000
-
-#define ESDCTL_V4_ESDCTLx_ROW_MASK			0x07000000
-#define ESDCTL_V4_ESDCTLx_ROW_11			0x00000000
-#define ESDCTL_V4_ESDCTLx_ROW_12			0x01000000
-#define ESDCTL_V4_ESDCTLx_ROW_13			0x02000000
-#define ESDCTL_V4_ESDCTLx_ROW_14			0x03000000
-#define ESDCTL_V4_ESDCTLx_ROW_15			0x04000000
-#define ESDCTL_V4_ESDCTLx_ROW_16			0x05000000
-
-#define ESDCTL_V4_ESDCTLx_COL_MASK			0x00700000
-#define ESDCTL_V4_ESDCTLx_COL_9				0x00000000
-#define ESDCTL_V4_ESDCTLx_COL_10			0x00100000
-#define ESDCTL_V4_ESDCTLx_COL_11			0x00200000
-#define ESDCTL_V4_ESDCTLx_COL_8				0x00300000
-#define ESDCTL_V4_ESDCTLx_COL_12			0x00400000
-
-#define ESDCTL_V4_ESDCTLx_BL_MASK			0x00080000
-#define ESDCTL_V4_ESDCTLx_BL_4_RES			0x00000000
-#define ESDCTL_V4_ESDCTLx_BL_8_8			0x00080000
-
-#define ESDCTL_V4_ESDCTLx_DSIZ_MASK			0x00010000
-#define ESDCTL_V4_ESDCTLx_DSIZ_16B_LOW			0x00000000
-#define ESDCTL_V4_ESDCTLx_DSIZ_32B			0x00010000
-
-#define ESDCTL_V4_ESDMISC_CS0_RDY			0x80000000
-#define ESDCTL_V4_ESDMISC_CS1_RDY			0x40000000
-#define ESDCTL_V4_ESDMISC_ONE_CS			0x00100000
-#define ESDCTL_V4_ESDMISC_ADDR_MIRROR			0x00080000
-#define ESDCTL_V4_ESDMISC_LHD				0x00040000
-#define ESDCTL_V4_ESDMISC_WALAT_SHIFT			16
-#define ESDCTL_V4_ESDMISC_WALAT_MASK			(0x3 << ESDCTL_V4_ESDMISC_WALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_WALAT_0			(0x0 << ESDCTL_V4_ESDMISC_WALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_WALAT_1			(0x1 << ESDCTL_V4_ESDMISC_WALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_WALAT_2			(0x2 << ESDCTL_V4_ESDMISC_WALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_WALAT_3			(0x3 << ESDCTL_V4_ESDMISC_WALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_BI_ON				0x00001000
-#define ESDCTL_V4_ESDMISC_MIF3_MODE_MASK		0x00000600
-#define ESDCTL_V4_ESDMISC_MIF3_MODE_DIS			0x00000000
-#define ESDCTL_V4_ESDMISC_MIF3_MODE_EF			0x00000200
-#define ESDCTL_V4_ESDMISC_MIF3_MODE_EFA			0x00000400
-#define ESDCTL_V4_ESDMISC_MIF3_MODE_EFAM		0x00000600
-#define ESDCTL_V4_ESDMISC_RALAT_SHIFT			6
-#define ESDCTL_V4_ESDMISC_RALAT_MASK			(0x7 << ESDCTL_V4_ESDMISC_RALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_RALAT_0			(0x0 << ESDCTL_V4_ESDMISC_RALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_RALAT_1			(0x1 << ESDCTL_V4_ESDMISC_RALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_RALAT_2			(0x2 << ESDCTL_V4_ESDMISC_RALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_RALAT_3			(0x3 << ESDCTL_V4_ESDMISC_RALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_RALAT_4			(0x4 << ESDCTL_V4_ESDMISC_RALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_RALAT_5			(0x5 << ESDCTL_V4_ESDMISC_RALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_RALAT_6			(0x6 << ESDCTL_V4_ESDMISC_RALAT_SHIFT)
-#define ESDCTL_V4_ESDMISC_RALAT_7			(0x7 << ESDCTL_V4_ESDMISC_RALAT_SHIFT)
-
-#define ESDCTL_V4_ESDMISC_DDR_MASK			0x00000818
-#define ESDCTL_V4_ESDMISC_DDR_DDR3			0x00000000
-#define ESDCTL_V4_ESDMISC_DDR_LPDDR2_S4			0x00000008
-#define ESDCTL_V4_ESDMISC_DDR_LPDDR2_S2			0x00000808
-#define ESDCTL_V4_ESDMISC_DDR_DDR2			0x00000010
-
-#define ESDCTL_V4_ESDMISC_BANKS_MASK			0x00000020
-#define ESDCTL_V4_ESDMISC_BANKS_4			0x00000020
-#define ESDCTL_V4_ESDMISC_BANKS_8			0x00000000
-
-#define ESDCTL_V4_ESDMISC_RST				0x00000002
-
-
-#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET3_SHIFT	24
-#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET2_SHIFT	16
-#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT	8
-#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT	0
-#define ESDCTL_V4_ESDRDDLCTL_RD_DL_ABS_OFFSET_MASK	0xff
-
-#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET3_SHIFT	24
-#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET2_SHIFT	16
-#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET1_SHIFT	8
-#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET0_SHIFT	0
-#define ESDCTL_V4_ESDRDDLCTL_WR_DL_ABS_OFFSET_MASK	0xff
-
-
-#define ESDCTL_V4_ESDDGCTRL0_RST_RD_FIFO		0x80000000
-#define ESDCTL_V4_ESDDGCTRL0_DG_CMP_CYC			0x40000000
-#define ESDCTL_V4_ESDDGCTRL0_DG_DIS			0x20000000
-#define ESDCTL_V4_ESDDGCTRL0_HW_DG_EN			0x10000000
-#define ESDCTL_V4_ESDDGCTRL0_DG_HC_DEL1_MASK		0x0f000000
-#define ESDCTL_V4_ESDDGCTRL0_DG_HC_DEL1_SHIFT		24
-#define ESDCTL_V4_ESDDGCTRL0_DG_EXT_UP			0x00800000
-#define ESDCTL_V4_ESDDGCTRL0_DG_DL_ABS_OFFSET1_MASK	0x007f0000
-#define ESDCTL_V4_ESDDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT	16
-#define ESDCTL_V4_ESDDGCTRL0_HW_DG_ERR			0x00001000
-#define ESDCTL_V4_ESDDGCTRL0_DG_HC_DEL0_MASK		0x00000f00
-#define ESDCTL_V4_ESDDGCTRL0_DG_HC_DEL0_SHIFT		8
-#define ESDCTL_V4_ESDDGCTRL0_DG_DL_ABS_OFFSET0_MASK	0x0000007f
-#define ESDCTL_V4_ESDDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT	0
-
-#define ESDCTL_V4_ESDDGCTRL1_DG_HC_DEL3_MASK		0x0f000000
-#define ESDCTL_V4_ESDDGCTRL1_DG_HC_DEL3_SHIFT		24
-#define ESDCTL_V4_ESDDGCTRL1_DG_DL_ABS_OFFSET3_MASK	0x007f0000
-#define ESDCTL_V4_ESDDGCTRL1_DG_DL_ABS_OFFSET3_SHIFT	16
-#define ESDCTL_V4_ESDDGCTRL1_DG_HC_DEL2_MASK		0x00000f00
-#define ESDCTL_V4_ESDDGCTRL1_DG_HC_DEL2_SHIFT		8
-#define ESDCTL_V4_ESDDGCTRL1_DG_DL_ABS_OFFSET2_MASK	0x0000007f
-#define ESDCTL_V4_ESDDGCTRL1_DG_DL_ABS_OFFSET2_SHIFT	0
-
-
-#define ESDCTL_V4_ESDCFG0_tRFC_SHIFT			24
-#define ESDCTL_V4_ESDCFG0_tRFC_MASK			(0xff << ESDCTL_V4_ESDCFG0_tRFC_SHIFT)
-#define ESDCTL_V4_ESDCFG0_tXS_SHIFT			16
-#define ESDCTL_V4_ESDCFG0_tXS_MASK			(0xff << ESDCTL_V4_ESDCFG0_tXS_SHIFT)
-#define ESDCTL_V4_ESDCFG0_tXP_SHIFT			13
-#define ESDCTL_V4_ESDCFG0_tXP_MASK			(0x7 << ESDCTL_V4_ESDCFG0_tXP_SHIFT)
-#define ESDCTL_V4_ESDCFG0_tXPDLL_SHIFT			9
-#define ESDCTL_V4_ESDCFG0_tXPDLL_MASK			(0xf << ESDCTL_V4_ESDCFG0_tXPDLL_SHIFT)
-#define ESDCTL_V4_ESDCFG0_tFAW_SHIFT			4
-#define ESDCTL_V4_ESDCFG0_tFAW_MASK			(0x1f << ESDCTL_V4_ESDCFG0_tFAW_SHIFT)
-#define ESDCTL_V4_ESDCFG0_tCL_SHIFT			0
-#define ESDCTL_V4_ESDCFG0_tCL_MASK			(0xf << ESDCTL_V4_ESDCFG0_tCL_SHIFT)
-
-#define ESDCTL_V4_ESDCFG1_tRCD_SHIFT			29
-#define ESDCTL_V4_ESDCFG1_tRCD_MASK			(0x7 << ESDCTL_V4_ESDCFG1_tRCD_SHIFT)
-#define ESDCTL_V4_ESDCFG1_tRP_SHIFT			26
-#define ESDCTL_V4_ESDCFG1_tRP_MASK			(0x7 << ESDCTL_V4_ESDCFG1_tRP_SHIFT)
-#define ESDCTL_V4_ESDCFG1_tRC_SHIFT			21
-#define ESDCTL_V4_ESDCFG1_tRC_MASK			(0x1f << ESDCTL_V4_ESDCFG1_tRC_SHIFT)
-#define ESDCTL_V4_ESDCFG1_tRAS_SHIFT			16
-#define ESDCTL_V4_ESDCFG1_tRAS_MASK			(0x1f << ESDCTL_V4_ESDCFG1_tRAS_SHIFT)
-#define ESDCTL_V4_ESDCFG1_tRPA_SHIFT			15
-#define ESDCTL_V4_ESDCFG1_tRPA_MASK			(0x1 << ESDCTL_V4_ESDCFG1_tRPA_SHIFT)
-#define ESDCTL_V4_ESDCFG1_tWR_SHIFT			9
-#define ESDCTL_V4_ESDCFG1_tWR_MASK			(0x7 << ESDCTL_V4_ESDCFG1_tWR_SHIFT)
-#define ESDCTL_V4_ESDCFG1_tMRD_SHIFT			5
-#define ESDCTL_V4_ESDCFG1_tMRD_MASK			(0xf << ESDCTL_V4_ESDCFG1_tMRD_SHIFT)
-#define ESDCTL_V4_ESDCFG1_tCWL_SHIFT			0
-#define ESDCTL_V4_ESDCFG1_tCWL_MASK			(0x7 << ESDCTL_V4_ESDCFG1_tCWL_SHIFT)
-
-#define ESDCTL_V4_ESDCFG2_tDLLK_SHIFT			16
-#define ESDCTL_V4_ESDCFG2_tDLLK_MASK			(0x1ff << ESDCTL_V4_ESDCFG2_tDLLK_SHIFT)
-#define ESDCTL_V4_ESDCFG2_tRTP_SHIFT			6
-#define ESDCTL_V4_ESDCFG2_tRTP_MASK			(0x7 << ESDCTL_V4_ESDCFG2_tRTP_SHIFT)
-#define ESDCTL_V4_ESDCFG2_tWTR_SHIFT			3
-#define ESDCTL_V4_ESDCFG2_tWTR_MASK			(0x7 << ESDCTL_V4_ESDCFG2_tWTR_SHIFT)
-#define ESDCTL_V4_ESDCFG2_tRRD_SHIFT			0
-#define ESDCTL_V4_ESDCFG2_tRRD_MASK			(0x7 << ESDCTL_V4_ESDCFG2_tRRD_SHIFT)
-
-#define ESDCTL_V4_ESDRWD_tDAI_SHIFT			16
-#define ESDCTL_V4_ESDRWD_tDAI_MASK			(0x1fff << ESDCTL_V4_ESDRWD_tDAI_SHIFT)
-#define ESDCTL_V4_ESDRWD_RTW_SAME_SHIFT			12
-#define ESDCTL_V4_ESDRWD_RTW_SAME_MASK			(0x7 << ESDCTL_V4_ESDRWD_RTW_SAME_SHIFT)
-#define ESDCTL_V4_ESDRWD_WTR_DIFF_SHIFT			9
-#define ESDCTL_V4_ESDRWD_WTR_DIFF_MASK			(0x7 << ESDCTL_V4_ESDRWD_WTR_DIFF_SHIFT)
-#define ESDCTL_V4_ESDRWD_WTW_DIFF_SHIFT			6
-#define ESDCTL_V4_ESDRWD_WTW_DIFF_MASK			(0x7 << ESDCTL_V4_ESDRWD_WTW_DIFF_SHIFT)
-#define ESDCTL_V4_ESDRWD_RTW_DIFF_SHIFT			3
-#define ESDCTL_V4_ESDRWD_RTW_DIFF_MASK			(0x7 << ESDCTL_V4_ESDRWD_RTW_DIFF_SHIFT)
-#define ESDCTL_V4_ESDRWD_RTR_DIFF_SHIFT			0
-#define ESDCTL_V4_ESDRWD_RTR_DIFF_MASK			(0x7 << ESDCTL_V4_ESDRWD_RTR_DIFF_SHIFT)
-
-#define ESDCTL_V4_ESDOR_tXPR_SHIFT			16
-#define ESDCTL_V4_ESDOR_tXPR_MASK			(0xff << ESDCTL_V4_ESDOR_tXPR_SHIFT)
-#define ESDCTL_V4_ESDOR_SDE_to_RST_SHIFT		8
-#define ESDCTL_V4_ESDOR_SDE_to_RST_MASK			(0x3f << ESDCTL_V4_ESDOR_SDE_to_RST_SHIFT)
-#define ESDCTL_V4_ESDOR_RST_to_CKE_SHIFT		0
-#define ESDCTL_V4_ESDOR_RST_to_CKE_MASK			(0x3f << ESDCTL_V4_ESDOR_RST_to_CKE_SHIFT)
-
-#define ESDCTL_V4_ESDOTC_tAOFPD_SHIFT			27
-#define ESDCTL_V4_ESDOTC_tAOFPD_MASK			(0x7 << ESDCTL_V4_ESDOTC_tAOFPD_SHIFT)
-#define ESDCTL_V4_ESDOTC_tAONPD_SHIFT			24
-#define ESDCTL_V4_ESDOTC_tAONPD_MASK			(0x7 << ESDCTL_V4_ESDOTC_tAONPD_SHIFT)
-#define ESDCTL_V4_ESDOTC_tANPD_SHIFT			20
-#define ESDCTL_V4_ESDOTC_tANPD_MASK			(0xf << ESDCTL_V4_ESDOTC_tANPD_SHIFT)
-#define ESDCTL_V4_ESDOTC_tAXPD_SHIFT			16
-#define ESDCTL_V4_ESDOTC_tAXPD_MASK			(0xf << ESDCTL_V4_ESDOTC_tAXPD_SHIFT)
-#define ESDCTL_V4_ESDOTC_tODTLon_SHIFT			12
-#define ESDCTL_V4_ESDOTC_tODTLon_MASK			(0x7 << ESDCTL_V4_ESDOTC_tODTLon_SHIFT)
-#define ESDCTL_V4_ESDOTC_tODT_idle_off_SHIFT		4
-#define ESDCTL_V4_ESDOTC_tODT_idle_off_MASK		(0x1f << ESDCTL_V4_ESDOTC_tODT_idle_off_SHIFT)
-
-#define ESDCTL_V4_ESDPDC_PRCT1_SHIFT			28
-#define ESDCTL_V4_ESDPDC_PRCT1_MASK			(0x7 << ESDCTL_V4_ESDPDC_PRCT1_SHIFT)
-#define ESDCTL_V4_ESDPDC_PRCT0_SHIFT			24
-#define ESDCTL_V4_ESDPDC_PRCT0_MASK			(0x7 << ESDCTL_V4_ESDPDC_PRCT0_SHIFT)
-#define ESDCTL_V4_ESDPDC_tCKE_SHIFT			16
-#define ESDCTL_V4_ESDPDC_tCKE_MASK			(0x7 << ESDCTL_V4_ESDPDC_tCKE_SHIFT)
-#define ESDCTL_V4_ESDPDC_PWDT1_SHIFT			12
-#define ESDCTL_V4_ESDPDC_PWDT1_MASK			(0xf << ESDCTL_V4_ESDPDC_PWDT1_SHIFT)
-#define ESDCTL_V4_ESDPDC_PWDT0_SHIFT			8
-#define ESDCTL_V4_ESDPDC_PWDT0_MASK			(0xf << ESDCTL_V4_ESDPDC_PWDT0_SHIFT)
-#define ESDCTL_V4_ESDPDC_SLOW_PD			0x00000080
-#define ESDCTL_V4_ESDPDC_BOTH_CS_PD			0x00000040
-#define ESDCTL_V4_ESDPDC_tCKSRX_SHIFT			3
-#define ESDCTL_V4_ESDPDC_tCKSRX_MASK			(0x7 << ESDCTL_V4_ESDPDC_tCKSRX_SHIFT)
-#define ESDCTL_V4_ESDPDC_tCKSRE_SHIFT			0
-#define ESDCTL_V4_ESDPDC_tCKSRE_MASK			(0x7 << ESDCTL_V4_ESDPDC_tCKSRE_SHIFT)
-
-#define ESDCTL_V4_ESDPDC_PRCT_DISABLE			0x0
-#define ESDCTL_V4_ESDPDC_PRCT_2				0x1
-#define ESDCTL_V4_ESDPDC_PRCT_4				0x2
-#define ESDCTL_V4_ESDPDC_PRCT_8				0x3
-#define ESDCTL_V4_ESDPDC_PRCT_16			0x4
-#define ESDCTL_V4_ESDPDC_PRCT_32			0x5
-#define ESDCTL_V4_ESDPDC_PRCT_64			0x6
-#define ESDCTL_V4_ESDPDC_PRCT_128			0x7
-
-#define ESDCTL_V4_ESDPDC_PWDT_DISABLE			0x0
-#define ESDCTL_V4_ESDPDC_PWDT_16			0x1
-#define ESDCTL_V4_ESDPDC_PWDT_32			0x2
-#define ESDCTL_V4_ESDPDC_PWDT_64			0x3
-#define ESDCTL_V4_ESDPDC_PWDT_128			0x4
-#define ESDCTL_V4_ESDPDC_PWDT_256			0x5
-#define ESDCTL_V4_ESDPDC_PWDT_512			0x6
-#define ESDCTL_V4_ESDPDC_PWDT_1024			0x7
-#define ESDCTL_V4_ESDPDC_PWDT_2048			0x8
-#define ESDCTL_V4_ESDPDC_PWDT_4096			0x9
-#define ESDCTL_V4_ESDPDC_PWDT_8192			0xa
-#define ESDCTL_V4_ESDPDC_PWDT_16384			0xb
-#define ESDCTL_V4_ESDPDC_PWDT_32768			0xc
-
-#define ESDCTL_V4_ESDREF_REF_CNT_SHIFT			16
-#define ESDCTL_V4_ESDREF_REF_CNT_MASK			(0xffff << ESDCTL_V4_ESDREF_REF_CNT_SHIFT)
-#define ESDCTL_V4_ESDREF_REF_SEL_MASK			0x0000c000
-#define ESDCTL_V4_ESDREF_REF_SEL_64K			0x00000000
-#define ESDCTL_V4_ESDREF_REF_SEL_32K			0x00001000
-#define ESDCTL_V4_ESDREF_REF_SEL_REFCNT			0x00002000
-#define ESDCTL_V4_ESDREF_REFR_SHIFT			11
-#define ESDCTL_V4_ESDREF_REFR_MASK			(0x7 << ESDCTL_V4_ESDREF_REFR_SHIFT)
-#define ESDCTL_V4_ESDREF_START_REF			0x00000001
-
-#define ESDCTL_V4_ESDZQHWC_ZQ_PARA_EN			0x04000000
-#define ESDCTL_V4_ESDZQHWC_TZQ_CS_SHIFT			23
-#define ESDCTL_V4_ESDZQHWC_TZQ_CS_MASK			(0x7 << ESDCTL_V4_ESDZQHWC_TZQ_CS_SHIFT)
-#define ESDCTL_V4_ESDZQHWC_TZQ_OPER_SHIFT		20
-#define ESDCTL_V4_ESDZQHWC_TZQ_OPER_MASK		(0x7 << ESDCTL_V4_ESDZQHWC_TZQ_OPER_SHIFT)
-#define ESDCTL_V4_ESDZQHWC_TZQ_INIT_SHIFT		17
-#define ESDCTL_V4_ESDZQHWC_TZQ_INIT_MASK		(0x7 << ESDCTL_V4_ESDZQHWC_TZQ_INIT_SHIFT)
-#define ESDCTL_V4_ESDZQHWC_ZQ_HW_FOR			0x00010000
-#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PD_RES_SHIFT		11
-#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PD_RES_MASK		(0x1f << ESDCTL_V4_ESDZQHWC_ZQ_HW_PD_RES_SHIFT)
-#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PU_RES_SHIFT		6
-#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PU_RES_MASK		(0x1f << ESDCTL_V4_ESDZQHWC_ZQ_HW_PU_RES_SHIFT)
-#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PER_SHIFT		2
-#define ESDCTL_V4_ESDZQHWC_ZQ_HW_PER_MASK		(0xf << ESDCTL_V4_ESDZQHWC_ZQ_HW_PER_SHIFT)
-#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT		0
-#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_MASK			(0x3 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT)
-
-#define ESDCTL_V4_ESDZQHWC_32CYC			0x0
-#define ESDCTL_V4_ESDZQHWC_64CYC			0x1
-#define ESDCTL_V4_ESDZQHWC_128CYC			0x2
-#define ESDCTL_V4_ESDZQHWC_256CYC			0x3
-#define ESDCTL_V4_ESDZQHWC_512CYC			0x4
-#define ESDCTL_V4_ESDZQHWC_1024CYC			0x5
-
-#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_NO_CAL		(0x0 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT)
-#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_BOTH_EXIT		(0x1 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT)
-#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_EXTERNAL_PER		(0x2 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT)
-#define ESDCTL_V4_ESDZQHWC_ZQ_MODE_BOTH_PER		(0x3 << ESDCTL_V4_ESDZQHWC_ZQ_MODE_SHIFT)
-
-#define ESDCTL_V4_ESDODTC_ODT3_INT_RES_SHIFT		16
-#define ESDCTL_V4_ESDODTC_ODT3_INT_RES_MASK		(0x7 << ESDCTL_V4_ESDODTC_ODT3_INT_RES_SHIFT)
-#define ESDCTL_V4_ESDODTC_ODT2_INT_RES_SHIFT		12
-#define ESDCTL_V4_ESDODTC_ODT2_INT_RES_MASK		(0x7 << ESDCTL_V4_ESDODTC_ODT2_INT_RES_SHIFT)
-#define ESDCTL_V4_ESDODTC_ODT1_INT_RES_SHIFT		8
-#define ESDCTL_V4_ESDODTC_ODT1_INT_RES_MASK		(0x7 << ESDCTL_V4_ESDODTC_ODT1_INT_RES_SHIFT)
-#define ESDCTL_V4_ESDODTC_ODT0_INT_RES_SHIFT		4
-#define ESDCTL_V4_ESDODTC_ODT0_INT_RES_MASK		(0x7 << ESDCTL_V4_ESDODTC_ODT0_INT_RES_SHIFT)
-#define ESDCTL_V4_ESDODTC_ODT_RD_ACT_EN			0x00000008
-#define ESDCTL_V4_ESDODTC_ODT_RD_PAS_EN			0x00000004
-#define ESDCTL_V4_ESDODTC_ODT_WR_ACT_EN			0x00000002
-#define ESDCTL_V4_ESDODTC_ODT_WR_PAS_EN			0x00000001
-
-#define ESDCTL_V4_ESDODTC_RTT_DISABLE			0x0
-#define ESDCTL_V4_ESDODTC_RTT_60			0x1
-#define ESDCTL_V4_ESDODTC_RTT_120			0x2
-#define ESDCTL_V4_ESDODTC_RTT_40			0x3
-#define ESDCTL_V4_ESDODTC_RTT_20			0x4
-#define ESDCTL_V4_ESDODTC_RTT_30			0x5
-
-#define ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT			16
-#define ESDCTL_V4_ESDSCR_CMD_ADDR_MASK			(0xffff << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_ESDSCR_CON_REQ			0x00008000
-#define ESDCTL_V4_ESDSCR_CON_ACK			0x00004000
-#define ESDCTL_V4_ESDSCR_MRR_DATA_VALID			0x00000400
-#define ESDCTL_V4_ESDSCR_WL_EN				0x00000200
-#define ESDCTL_V4_ESDSCR_DLL_RST1			0x00000100
-#define ESDCTL_V4_ESDSCR_DLL_RST0			0x00000080
-#define ESDCTL_V4_ESDSCR_CMD_SHIFT			4
-#define ESDCTL_V4_ESDSCR_CMD_MASK			(0x7 << ESDCTL_V4_ESDSCR_CMD_SHIFT)
-#define ESDCTL_V4_ESDSCR_CMD_NOP			(0x0 << ESDCTL_V4_ESDSCR_CMD_SHIFT)
-#define ESDCTL_V4_ESDSCR_CMD_PRE_ALL			(0x1 << ESDCTL_V4_ESDSCR_CMD_SHIFT)
-#define ESDCTL_V4_ESDSCR_CMD_AREFRESH			(0x2 << ESDCTL_V4_ESDSCR_CMD_SHIFT)
-#define ESDCTL_V4_ESDSCR_CMD_LMR			(0x3 << ESDCTL_V4_ESDSCR_CMD_SHIFT)
-#define ESDCTL_V4_ESDSCR_CMD_ZQCALIB_OLD		(0x4 << ESDCTL_V4_ESDSCR_CMD_SHIFT)
-#define ESDCTL_V4_ESDSCR_CMD_PRE_ALL_OPEN		(0x5 << ESDCTL_V4_ESDSCR_CMD_SHIFT)
-#define ESDCTL_V4_ESDSCR_CMD_MRR			(0x6 << ESDCTL_V4_ESDSCR_CMD_SHIFT)
-#define ESDCTL_V4_ESDSCR_CMD_CS				0x00000008
-#define ESDCTL_V4_ESDSCR_CMD_CS0			0x00000000
-#define ESDCTL_V4_ESDSCR_CMD_CS1			0x00000008
-#define ESDCTL_V4_ESDSCR_CMD_BA_SHIFT			0
-#define ESDCTL_V4_ESDSCR_CMD_BA_MASK			(0x7 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT)
-
-#define ESDCTL_V4_PDCMPR2_PHY_CA_DL_SHIFT		24
-#define ESDCTL_V4_PDCMPR2_PHY_CA_DL_MASK		(0x7f << ESDCTL_V4_PDCMPR2_PHY_CA_DL_SHIFT)
-#define ESDCTL_V4_PDCMPR2_CA_DL_ABS_SHIFT		16
-#define ESDCTL_V4_PDCMPR2_CA_DL_ABS_MASK		(0x7f << ESDCTL_V4_PDCMPR2_CA_DL_ABS_SHIFT)
-#define ESDCTL_V4_PDCMPR2_RLPAT				0x4
-#define ESDCTL_V4_PDCMPR2_RLPAT_0			0x0
-#define ESDCTL_V4_PDCMPR2_RLPAT_1			0x4
-#define ESDCTL_V4_PDCMPR2_MPR_FULL_CMP			0x2
-#define ESDCTL_V4_PDCMPR2_MPR_CMP			0x1
-
-#define ESDCTL_V4_WLGCR_WL_HW_ERR3			(1 << 11)
-#define ESDCTL_V4_WLGCR_WL_HW_ERR2			(1 << 10)
-#define ESDCTL_V4_WLGCR_WL_HW_ERR1			(1 << 9)
-#define ESDCTL_V4_WLGCR_WL_HW_ERR0			(1 << 8)
-#define ESDCTL_V4_WLGCR_WL_SW_ERR3			(1 << 7)
-#define ESDCTL_V4_WLGCR_WL_SW_ERR2			(1 << 6)
-#define ESDCTL_V4_WLGCR_WL_SW_ERR1			(1 << 5)
-#define ESDCTL_V4_WLGCR_WL_SW_ERR0			(1 << 4)
-#define ESDCTL_V4_WLGCR_SW_WL_CNT_EN			(1 << 2)
-#define ESDCTL_V4_WLGCR_SW_WL_EN			(1 << 1)
-#define ESDCTL_V4_WLGCR_HW_WL_EN			(1 << 1)
-
-#define ESDCTL_V4_RDDLHWCTL_HW_RDL_CMP_CYC		(1 << 5)
-#define ESDCTL_V4_RDDLHWCTL_HW_RDL_EN			(1 << 4)
-#define ESDCTL_V4_RDDLHWCTL_HW_RDL_ERR3			(1 << 3)
-#define ESDCTL_V4_RDDLHWCTL_HW_RDL_ERR2			(1 << 2)
-#define ESDCTL_V4_RDDLHWCTL_HW_RDL_ERR1			(1 << 1)
-#define ESDCTL_V4_RDDLHWCTL_HW_RDL_ERR0			(1 << 0)
-
-#define ESDCTL_V4_WRDLHWCTL_HW_WDL_CMP_CYC		(1 << 5)
-#define ESDCTL_V4_WRDLHWCTL_HW_WDL_EN			(1 << 4)
-#define ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR3			(1 << 3)
-#define ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR2			(1 << 2)
-#define ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR1			(1 << 1)
-#define ESDCTL_V4_WRDLHWCTL_HW_WDL_ERR0			(1 << 0)
-
-#define ESDCTL_V4_DDR3_REG_MR0				(0x0 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT)
-#define ESDCTL_V4_DDR3_REG_MR1				(0x1 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT)
-#define ESDCTL_V4_DDR3_REG_MR2				(0x2 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT)
-#define ESDCTL_V4_DDR3_REG_MR3				(0x3 << ESDCTL_V4_ESDSCR_CMD_BA_SHIFT)
-
-#define ESDCTL_V4_DDR3_MR0_PPD				(0x1000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_PPD_SLOW			(0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_PPD_FAST			(0x1000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_SHIFT			(9 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_MASK			(0x7 << ESDCTL_V4_DDR3_MR0_WR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_16			(0x0 << ESDCTL_V4_DDR3_MR0_WR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_5				(0x1 << ESDCTL_V4_DDR3_MR0_WR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_6				(0x2 << ESDCTL_V4_DDR3_MR0_WR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_7				(0x3 << ESDCTL_V4_DDR3_MR0_WR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_8				(0x4 << ESDCTL_V4_DDR3_MR0_WR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_10			(0x5 << ESDCTL_V4_DDR3_MR0_WR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_12			(0x6 << ESDCTL_V4_DDR3_MR0_WR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_WR_14			(0x7 << ESDCTL_V4_DDR3_MR0_WR_SHIFT)
-#define ESDCTL_V4_DDR3_DLL_RESET			(0x0100 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_TM				(0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_TM_NORMAL			(0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_TM_TEST				(0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_SHIFT			(2 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_MASK			(0x74 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_5				(0x10 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_6				(0x20 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_7				(0x30 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_8				(0x40 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_9				(0x50 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_10			(0x60 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_11			(0x70 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_12			(0x04 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_13			(0x14 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_14			(0x24 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_15			(0x34 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_CL_16			(0x44 << ESDCTL_V4_DDR3_MR0_CL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_RBT				(0x0008 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_RBT_NIBBLE			(0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_RBT_INTERL			(0x0008 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_BL_SHIFT			(0 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_BL_MASK			(0x3 << ESDCTL_V4_DDR3_MR0_BL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_BL_FIXED8			(0x0 << ESDCTL_V4_DDR3_MR0_BL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_BL_DYNAMIC			(0x1 << ESDCTL_V4_DDR3_MR0_BL_SHIFT)
-#define ESDCTL_V4_DDR3_MR0_BL_FIXED4			(0x2 << ESDCTL_V4_DDR3_MR0_BL_SHIFT)
-
-#define ESDCTL_V4_DDR3_MR1_QOFF				(0x1000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_TDQS				(0x0800 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_WL				(0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_AL_SHIFT			(3 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_AL_MASK			(0x3 << ESDCTL_V4_DDR3_MR1_AL_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_AL_DISABLE			(0x0 << ESDCTL_V4_DDR3_MR1_AL_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_AL_CL1			(0x1 << ESDCTL_V4_DDR3_MR1_AL_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_AL_CL2			(0x2 << ESDCTL_V4_DDR3_MR1_AL_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_DLL_DISABLE			(0x0001 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_RTTN_MASK			(0x0244 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_RTTN_DIS			(0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ4			(0x0004 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ2			(0x0040 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ6			(0x0044 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ12			(0x0200 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_RTTN_RZQ8			(0x0204 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_ODIC_MASK			(0x0022 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_ODIC_RZQ6			(0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR1_ODIC_RZQ7			(0x0002 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-
-#define ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT			(9 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_RTTWR_MASK			(0x3 << ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_RTTWR_OFF			(0x0 << ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_RTTWR_RZQ4			(0x1 << ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_RTTWR_RZQ2			(0x2 << ESDCTL_V4_DDR3_MR2_RTTWR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_SRT				(0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_SRT_NORMAL			(0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_SRT_EXTENDED			(0x0080 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_ASR_ENABLE			(0x0040 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_SHIFT			(3 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_MASK			(0x7 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_5			(0x0 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_6			(0x1 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_7			(0x2 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_8			(0x3 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_9			(0x4 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_10			(0x5 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_11			(0x6 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_CWL_12			(0x7 << ESDCTL_V4_DDR3_MR2_CWL_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_SHIFT			(0 + ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_MASK			(0x7 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_1_1			(0x0 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_1_2L			(0x1 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_1_4L			(0x2 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_1_8L			(0x3 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_3_4L			(0x4 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_1_2H			(0x5 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_1_4H			(0x6 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT)
-#define ESDCTL_V4_DDR3_MR2_PASR_1_8H			(0x7 << ESDCTL_V4_DDR3_MR2_PASR_SHIFT)
-
-#define ESDCTL_V4_DDR3_MR3_MPR_DISABLE			(0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR3_MPR_ENABLE			(0x0004 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR3_MPR_PATTERN			(0x0000 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR3_MPR_RFU1			(0x0001 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR3_MPR_RFU2			(0x0002 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-#define ESDCTL_V4_DDR3_MR3_MPR_RFU3			(0x0003 << ESDCTL_V4_ESDSCR_CMD_ADDR_SHIFT)
-
-#ifndef __ASSEMBLY__
-
-void imx_esdctlv4_do_write_leveling(void);
-void imx_esdctlv4_do_dqs_gating(void);
-void imx_esdctlv4_do_zq_calibration(void);
-void imx_esdctlv4_start_ddr3_sdram(int cs);
-void imx_esdctlv4_do_read_delay_line_calibration(void);
-void imx_esdctlv4_do_write_delay_line_calibration(void);
-void imx_esdctlv4_set_tRFC_timing(void);
-void imx_esdctlv4_detect_sdrams(void);
-void imx_esdctlv4_init(void);
-
-#endif
-
-#endif /* __MACH_ESDCTL_V4_H */
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
deleted file mode 100644
index e6bbc3145a..0000000000
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ /dev/null
@@ -1,150 +0,0 @@
-#ifndef __MACH_ESDCTL_V2_H
-#define __MACH_ESDCTL_V2_H
-
-/* SDRAM Controller registers */
-#define IMX_ESDCTL0 0x00 /* Enhanced SDRAM Control Register 0       */
-#define IMX_ESDCFG0 0x04 /* Enhanced SDRAM Configuration Register 0 */
-#define IMX_ESDCTL1 0x08 /* Enhanced SDRAM Control Register 1       */
-#define IMX_ESDCFG1 0x0C /* Enhanced SDRAM Configuration Register 1 */
-#define IMX_ESDMISC 0x10 /* Enhanced SDRAM Miscellanious Register   */
-
-#define ESDCTL0_SDE				(1 << 31)
-#define ESDCTL0_SMODE_NORMAL			(0 << 28)
-#define ESDCTL0_SMODE_PRECHARGE			(1 << 28)
-#define ESDCTL0_SMODE_AUTO_REFRESH		(2 << 28)
-#define ESDCTL0_SMODE_LOAD_MODE			(3 << 28)
-#define ESDCTL0_SMODE_MANUAL_SELF_REFRESH	(4 << 28)
-#define ESDCTL0_SP				(1 << 27)
-#define ESDCTL0_ROW11				(0 << 24)
-#define ESDCTL0_ROW12				(1 << 24)
-#define ESDCTL0_ROW13				(2 << 24)
-#define ESDCTL0_ROW14				(3 << 24)
-#define ESDCTL0_ROW15				(4 << 24)
-#define ESDCTL0_ROW_MASK			(7 << 24)
-#define ESDCTL0_COL8				(0 << 20)
-#define ESDCTL0_COL9				(1 << 20)
-#define ESDCTL0_COL10				(2 << 20)
-#define ESDCTL0_COL_MASK			(3 << 20)
-#define ESDCTL0_DSIZ_31_16			(0 << 16)
-#define ESDCTL0_DSIZ_15_0			(1 << 16)
-#define ESDCTL0_DSIZ_31_0			(2 << 16)
-#define ESDCTL0_DSIZ_MASK			(3 << 16)
-#define ESDCTL0_REF1				(1 << 13)
-#define ESDCTL0_REF2				(2 << 13)
-#define ESDCTL0_REF4				(3 << 13)
-#define ESDCTL0_REF8				(4 << 13)
-#define ESDCTL0_REF16				(5 << 13)
-#define ESDCTL0_PWDT_DISABLED			(0 << 10)
-#define ESDCTL0_PWDT_PRECHARGE_PWDN		(1 << 10)
-#define ESDCTL0_PWDT_PWDN_64			(2 << 10)
-#define ESDCTL0_PWDT_PWDN_128			(3 << 10)
-#define ESDCTL0_FP				(1 << 8)
-#define ESDCTL0_BL				(1 << 7)
-
-#define ESDMISC_RST			0x00000002
-#define ESDMISC_MDDR_EN			0x00000004
-#define ESDMISC_MDDR_DIS		0x00000000
-#define ESDMISC_MDDR_DL_RST		0x00000008
-#define ESDMISC_MDDR_MDIS		0x00000010
-#define ESDMISC_LHD			0x00000020
-#define ESDMISC_SDRAMRDY		0x80000000
-#define ESDMISC_DDR2_8_BANK		BIT(6)
-
-#define	ESDCFGx_tXP_MASK 		0x00600000
-#define ESDCFGx_tXP_1			0x00000000
-#define ESDCFGx_tXP_2			0x00200000
-#define ESDCFGx_tXP_3			0x00400000
-#define ESDCFGx_tXP_4			0x00600000
-
-#define ESDCFGx_tWTR_MASK		0x00100000
-#define ESDCFGx_tWTR_1			0x00000000
-#define ESDCFGx_tWTR_2			0x00100000
-
-#define ESDCFGx_tRP_MASK		0x000c0000
-#define ESDCFGx_tRP_1			0x00000000
-#define ESDCFGx_tRP_2			0x00040000
-#define ESDCFGx_tRP_3			0x00080000
-#define ESDCFGx_tRP_4			0x000c0000
-
-
-#define ESDCFGx_tMRD_MASK		0x00030000
-#define ESDCFGx_tMRD_1			0x00000000
-#define ESDCFGx_tMRD_2			0x00010000
-#define ESDCFGx_tMRD_3			0x00020000
-#define ESDCFGx_tMRD_4			0x00030000
-
-
-#define ESDCFGx_tWR_MASK		0x00008000
-#define ESDCFGx_tWR_1_2			0x00000000
-#define ESDCFGx_tWR_2_3			0x00008000
-
-#define ESDCFGx_tRAS_MASK		0x00007000
-#define ESDCFGx_tRAS_1			0x00000000
-#define ESDCFGx_tRAS_2			0x00001000
-#define ESDCFGx_tRAS_3			0x00002000
-#define ESDCFGx_tRAS_4			0x00003000
-#define ESDCFGx_tRAS_5			0x00004000
-#define ESDCFGx_tRAS_6			0x00005000
-#define ESDCFGx_tRAS_7			0x00006000
-#define ESDCFGx_tRAS_8			0x00007000
-
-
-#define ESDCFGx_tRRD_MASK		0x00000c00
-#define ESDCFGx_tRRD_1			0x00000000
-#define ESDCFGx_tRRD_2			0x00000400
-#define ESDCFGx_tRRD_3			0x00000800
-#define ESDCFGx_tRRD_4			0x00000c00
-
-
-#define ESDCFGx_tCAS_MASK		0x00000300
-#define ESDCFGx_tCAS_2			0x00000200
-#define ESDCFGx_tCAS_3			0x00000300
-
-#define ESDCFGx_tRCD_MASK		0x00000070
-#define ESDCFGx_tRCD_1			0x00000000
-#define ESDCFGx_tRCD_2			0x00000010
-#define ESDCFGx_tRCD_3			0x00000020
-#define ESDCFGx_tRCD_4			0x00000030
-#define ESDCFGx_tRCD_5			0x00000040
-#define ESDCFGx_tRCD_6			0x00000050
-#define ESDCFGx_tRCD_7			0x00000060
-#define ESDCFGx_tRCD_8			0x00000070
-
-#define ESDCFGx_tRC_MASK		0x0000000f
-#define ESDCFGx_tRC_20			0x00000000
-#define ESDCFGx_tRC_2			0x00000001
-#define ESDCFGx_tRC_3			0x00000002
-#define ESDCFGx_tRC_4			0x00000003
-#define ESDCFGx_tRC_5			0x00000004
-#define ESDCFGx_tRC_6			0x00000005
-#define ESDCFGx_tRC_7			0x00000006
-#define ESDCFGx_tRC_8			0x00000007
-#define ESDCFGx_tRC_9			0x00000008
-#define ESDCFGx_tRC_10			0x00000009
-#define ESDCFGx_tRC_11			0x0000000a
-#define ESDCFGx_tRC_12			0x0000000b
-#define ESDCFGx_tRC_13			0x0000000c
-#define ESDCFGx_tRC_14			0x0000000d
-//#define ESDCFGx_tRC_14		0x0000000e	// 15 seems to not exist
-#define ESDCFGx_tRC_16			0x0000000f
-
-#ifndef __ASSEMBLY__
-void __noreturn imx1_barebox_entry(void *boarddata);
-void __noreturn imx25_barebox_entry(void *boarddata);
-void __noreturn imx27_barebox_entry(void *boarddata);
-void __noreturn imx31_barebox_entry(void *boarddata);
-void __noreturn imx35_barebox_entry(void *boarddata);
-void __noreturn imx51_barebox_entry(void *boarddata);
-void __noreturn imx53_barebox_entry(void *boarddata);
-void __noreturn imx6q_barebox_entry(void *boarddata);
-void __noreturn imx6ul_barebox_entry(void *boarddata);
-void __noreturn vf610_barebox_entry(void *boarddata);
-void __noreturn imx8mm_barebox_entry(void *boarddata);
-void __noreturn imx8mp_barebox_entry(void *boarddata);
-void __noreturn imx8mq_barebox_entry(void *boarddata);
-void __noreturn imx7d_barebox_entry(void *boarddata);
-#define imx6sx_barebox_entry(boarddata) imx6ul_barebox_entry(boarddata)
-void imx_esdctl_disable(void);
-#endif
-
-#endif /* __MACH_ESDCTL_V2_H */
diff --git a/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg
deleted file mode 100644
index e98f055eea..0000000000
--- a/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2016 NXP Semiconductors
- *
- * SPDX-License-Identifier:	GPL-2.0
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- *
- * Taken from upstream U-Boot git://git.denx.de/u-boot.git, commit
- * 1a8150d4b16fbafa6f1d207ddb85eda7dc399e2d
- */
-
-#include <mach/imx7-ddr-regs.h>
-
-wm 32 0x30340004 0x4F400005
-
-wm 32 0x30391000 0x00000002
-
-wm 32 MX7_DDRC_MSTR 0x01040001
-wm 32 MX7_DDRC_DFIUPD0 0x80400003
-wm 32 MX7_DDRC_DFIUPD1 0x00100020
-wm 32 MX7_DDRC_DFIUPD2 0x80100004
-wm 32 MX7_DDRC_RFSHTMG 0x00400046
-wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001
-wm 32 MX7_DDRC_INIT0 0x00020083
-wm 32 MX7_DDRC_INIT1 0x00690000
-wm 32 MX7_DDRC_INIT3 0x09300004
-wm 32 MX7_DDRC_INIT4 0x04080000
-wm 32 MX7_DDRC_INIT5 0x00100004
-wm 32 MX7_DDRC_RANKCTL 0x0000033f
-wm 32 MX7_DDRC_DRAMTMG0 0x09081109
-wm 32 MX7_DDRC_DRAMTMG1 0x0007020d
-wm 32 MX7_DDRC_DRAMTMG2 0x03040407
-wm 32 MX7_DDRC_DRAMTMG3 0x00002006
-wm 32 MX7_DDRC_DRAMTMG4 0x04020205
-wm 32 MX7_DDRC_DRAMTMG5 0x03030202
-wm 32 MX7_DDRC_DRAMTMG8 0x00000803
-wm 32 MX7_DDRC_ZQCTL0 0x00800020
-wm 32 MX7_DDRC_ZQCTL1 0x02000100
-wm 32 MX7_DDRC_DFITMG0 0x02098204
-wm 32 MX7_DDRC_DFITMG1 0x00030303
-wm 32 MX7_DDRC_ADDRMAP0 0x00000016
-wm 32 MX7_DDRC_ADDRMAP1 0x00171717
-wm 32 MX7_DDRC_ADDRMAP5 0x04040404
-wm 32 MX7_DDRC_ADDRMAP6 0x0f040404
-wm 32 MX7_DDRC_ODTCFG 0x06000604
-wm 32 MX7_DDRC_ODTMAP 0x00000001
-
-wm 32 0x30391000 0x00000000
-
-wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40
-wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100
-wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807
-wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e
-wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e
-wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808
-wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808
-wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010
-wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010
-
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306
-
-check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1
-
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
-
-wm 32 0x30384130 0x00000000
-wm 32 0x30340020 0x00000178
-wm 32 0x30384130 0x00000002
-
-wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f
-
-check 32 until_any_bit_set MX7_DDRC_STAT 0x1
diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg
deleted file mode 100644
index 8c411ddc7e..0000000000
--- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
-
- The following table contains DDR3 memory timing parameters derived
- form memory module (Samsung K4B4G1646E) datasheet:
-
-| CL         |                                  6 | @400Mhz          |
-| WRLAT      |                                  5 |                  |
-| t_RC       |                                 21 |                  |
-| t_RRD      |                                  4 | [5]              |
-| t_CCD      |                                  4 |                  |
-| t_FAW      |          16(1KB page)/20(2KB page) |                  |
-| t_RP       |                                  6 |                  |
-| t_WTR      |                                  4 | [6]              |
-| t_RAS(MIN) |                                 15 |                  |
-| t_MRD      |                                  4 |                  |
-| t_RTP      |                                  4 | [1]              |
-| t_MOD      |                                 12 | [7]              |
-| t_RAS(MAX) |                              28080 | [8]              |
-| t_CKESR    |                                  4 | [9]              |
-| t_CKE      |                                  3 | [10]             |
-| t_RCD      |                                  6 |                  |
-| t_DAL      |                                 12 | [11]             |
-| t_DDLK     |                                512 |                  |
-| t_RP(AB)   |                                  6 | n/a in datasheet |
-| t_REFI     |                               3120 |                  |
-| t_RFC      | 44 @ 1Gb, 64@2Gb, 104@4Gb, 140@8Gb |                  |
-| t_XP       |                                  3 | [4]              |
-| t_XPDLL    |                                 10 | [12]             |
-| t_XS       | 48 @ 1Gb, 68@2Gb, 108@4Gb, 148@8Gb | [2]              |
-| t_XSDLL    |                                512 |                  |
-| t_CKSRX    |                                  5 | [3]              |
-| t_CKSRE    |                                  5 | [3]              |
-| MR0        |                                    |                  |
-| MR1        |                                    |                  |
-| MR2        |                                    |                  |
-| MR3        |                                    |                  |
-| t_ZQoper   |                                256 |                  |
-| t_ZQinit   |                                512 |                  |
-| t_ZQCS     |                                 64 |                  |
-| ODTL_off   |                                  3 | [14]             |
-| t_WLMRD    |                                 40 |                  |
-| t_WLDQSEN  |                                 25 |                  |
-| t_WR       |                                  6 |                  |
-| t_ODTH8(R) |                                  6 | n/a in datasheet |
-| t_ODTH8(W) |                                  6 |                  |
-
-
-[1]  t_RTP      = max(4nCK, 7.5ns) = max(10ns, 7.5ns)@400Mhz = 4nCK
-[2]  t_XS       = max(5nCK, t_RFC + 10ns)
-[3]  t_CKSRX    = t_CKSRE = max(5nCK, 10ns) = max(12.5ns, 7.5ns)@400Mhz = 5nCK
-[4]  t_XP       = max(3nCK, 7.5ns) = max(7.5ns, 7.5ns)@400Mhz = 3nCK
-[5]  t_RRD      = max(4nCK, 10ns) = max(10ns, 10ns)@400Mhz = 4nCK
-[6]  t_WTR      = max(4nCK, 7.5ns) = 4nCK (see [1] for calculation)
-[7]  t_MOD      = max(12nCK, 15ns) = max(30ns, 15ns)@400Mhz = 12nCK
-[8]  t_RAS(MAX) = 9 * t_REFI = 9 * 7.8us = 28080nCK
-[9]  t_CKESR    = t_CKE(min) + 1tCK = 4nCK
-[10] t_CKE      = max(3nCK, 7.5ns) = 3nCK (see [4])
-[11] t_DAL      = t_WR + roundup(t_RP/t_CK(AVG)) = 6nCK + 6nCK = 12nCK
-[12] t_XPDLL    = max(10nCK, 24ns) = max(25ns, 25ns)@400Mhz = 10nCK
-[13] WRLAT      = AL + CWL = 0 (not supported by controller) + 5nCK = 5nCK
-[14] ODTL_off   = WRLAT - 2 = 3nCK
-
-*/
-
-wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3
-wm 32 DDRMC_CR02 0x00000005
-wm 32 DDRMC_CR10 0x00013880
-wm 32 DDRMC_CR11 0x00030d40
-wm 32 DDRMC_CR12 0x0000050c
-wm 32 DDRMC_CR13 0x15040400
-wm 32 DDRMC_CR14 0x1406040f
-wm 32 DDRMC_CR16 0x04040000
-wm 32 DDRMC_CR17 0x006db00c
-wm 32 DDRMC_CR18 0x00000403
-wm 32 DDRMC_CR20 0x01000000
-wm 32 DDRMC_CR21 0x00060001
-wm 32 DDRMC_CR22 0x000c0000
-wm 32 DDRMC_CR23 0x03000200
-wm 32 DDRMC_CR24 0x00000006
-wm 32 DDRMC_CR25 0x00010000
-wm 32 DDRMC_CR26 0x0c30002c
-wm 32 DDRMC_CR28 0x00000000
-wm 32 DDRMC_CR29 0x00000003
-wm 32 DDRMC_CR30 0x0000000a
-wm 32 DDRMC_CR31 0x00300200
-wm 32 DDRMC_CR33 0x00010000
-wm 32 DDRMC_CR34 0x00050500
-wm 32 DDRMC_CR38 0x00000000
-wm 32 DDRMC_CR39 0x04001002
-wm 32 DDRMC_CR41 0x00000001
-wm 32 DDRMC_CR48 0x00460420
-wm 32 DDRMC_CR66 0x01000200
-wm 32 DDRMC_CR67 0x00000040
-wm 32 DDRMC_CR69 0x00000200
-wm 32 DDRMC_CR70 0x00000040
-wm 32 DDRMC_CR72 0x00000000
-wm 32 DDRMC_CR73 0x0a010300
-wm 32 DDRMC_CR74 0x01014040
-wm 32 DDRMC_CR75 0x01010101
-wm 32 DDRMC_CR76 0x03030100
-wm 32 DDRMC_CR77 0x01000101
-wm 32 DDRMC_CR78 0x0700000c
-wm 32 DDRMC_CR79 0x00000000
-wm 32 DDRMC_CR82 0x10000000
-wm 32 DDRMC_CR87 0x01000000
-wm 32 DDRMC_CR88 0x00040000
-wm 32 DDRMC_CR89 0x00000002
-wm 32 DDRMC_CR91 0x00020000
-wm 32 DDRMC_CR96 0x00002819
-wm 32 DDRMC_CR117 0x00000000
-wm 32 DDRMC_CR118 0x01010000
-wm 32 DDRMC_CR120 0x02020000
-wm 32 DDRMC_CR121 0x00000202
-wm 32 DDRMC_CR122 0x01010064
-wm 32 DDRMC_CR123 0x00010101
-wm 32 DDRMC_CR124 0x00000064
-wm 32 DDRMC_CR126 0x00000800
-/*
- * Despite the RM insisting on setting RDLAT_ADJ to CASLAT_LIN - 1 in
- * two places: p 1459 (section 10.1.5.133 "Control Register 132
- * (DDRMC_CR132)") and p. 1587 (section 10.1.6.15.10 "Configure the
- * 'output enable' of I/O Control") changing it from current 6 to
- * recommended 5 results in non-working DDR.
- */
-wm 32 DDRMC_CR132 0x00000506
-wm 32 DDRMC_CR137 0x00020000
-wm 32 DDRMC_CR138 0x01000100
-wm 32 DDRMC_CR154 0x682c4000
-wm 32 DDRMC_CR155 0x00000009
-wm 32 DDRMC_CR158 0x00000006
-wm 32 DDRMC_CR161 0x00010606
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-phy-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-phy-default.imxcfg
deleted file mode 100644
index e9d5ab0ca2..0000000000
--- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-phy-default.imxcfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * VFxxx shared DDR PHY DCD code. Intended use is to share code
- * between all board that copy VF610 Tower Board DDR reference
- * layout/design
- *
- * Copyright (C) 2018 Zodiac Inflight Innovations
- */
-
-#define DDRMC_PHY_DQ_TIMING	0x00002613
-#define DDRMC_PHY_DQS_TIMING	0x00002615
-#define DDRMC_PHY_CTRL		0x00210000
-#define DDRMC_PHY_MASTER_CTRL	0x0001012a
-#define DDRMC_PHY_SLAVE_CTRL	0x00002000
-#define DDRMC_PHY_OFF		0x00000000
-#define DDRMC_PHY_PROC_PAD_ODT	0x00010101
-#define DDRMC_PHY50_DDR3_MODE_EN_SW_HALF_CYCLE 0x00001100
-
-
-wm 32 DDRMC_PHY00 DDRMC_PHY_DQ_TIMING
-wm 32 DDRMC_PHY16 DDRMC_PHY_DQ_TIMING
-wm 32 DDRMC_PHY32 DDRMC_PHY_DQ_TIMING
-
-wm 32 DDRMC_PHY01 DDRMC_PHY_DQS_TIMING
-wm 32 DDRMC_PHY17 DDRMC_PHY_DQS_TIMING
-
-wm 32 DDRMC_PHY02 DDRMC_PHY_CTRL
-wm 32 DDRMC_PHY18 DDRMC_PHY_CTRL
-wm 32 DDRMC_PHY34 DDRMC_PHY_CTRL
-
-wm 32 DDRMC_PHY03 DDRMC_PHY_MASTER_CTRL
-wm 32 DDRMC_PHY19 DDRMC_PHY_MASTER_CTRL
-wm 32 DDRMC_PHY35 DDRMC_PHY_MASTER_CTRL
-
-wm 32 DDRMC_PHY04 DDRMC_PHY_SLAVE_CTRL
-wm 32 DDRMC_PHY20 DDRMC_PHY_SLAVE_CTRL
-wm 32 DDRMC_PHY36 DDRMC_PHY_SLAVE_CTRL
-
-wm 32 DDRMC_PHY49 DDRMC_PHY_OFF
-wm 32 DDRMC_PHY50 DDRMC_PHY50_DDR3_MODE_EN_SW_HALF_CYCLE
-wm 32 DDRMC_PHY52 DDRMC_PHY_PROC_PAD_ODT
diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg
deleted file mode 100644
index 74d119b59e..0000000000
--- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Ungate all IP block clocks
- */
-wm 32 0x4006b040 0xffffffff
-wm 32 0x4006b044 0xffffffff
-wm 32 0x4006b048 0xffffffff
-wm 32 0x4006b04c 0xffffffff
-wm 32 0x4006b050 0xffffffff
-wm 32 0x4006b058 0xffffffff
-wm 32 0x4006b05c 0xffffffff
-wm 32 0x4006b060 0xffffffff
-wm 32 0x4006b064 0xffffffff
-wm 32 0x4006b068 0xffffffff
-wm 32 0x4006b06c 0xffffffff
-
-/*
- * We have to options to clock DDR controller:
- *
- *  - Use Core-A5 clock
- *  - Use PLL2 PFD2 clock
- *
-
- * Using first option without changing PLL settings doesn't seem to be
- * possible given that DDRMC requires minimum of 300Mhz and MaskROM
- * configures it to be clocked at 264Mhz. Changing PLL1 settings
- * proved to be challenging becuase MaskROM code executing this DCD
- * will also be fetching the rest of the bootloader via some
- * peripheral interface whose clock is derived from Cortex-A5 clock.
- *
- * As a result this DCD configuration code uses the second option of
- * clocking DDR wiht PLL2 PFD2 clock output
- *
- * Turn PLL2 on
- */
-wm 32 0x40050030 0x00002001 /* Fout = Fin * 22 */
-
-/*
- * Wait for PLLs to lock
- */
-check 32 until_any_bit_set 0x40050030 0x80000000
-
-/*
- * Switch DDRMC to be clocked with PLL2 PFD2 and enable PFD2 output
- */
-clear_bits 32 0x4006b008 0x00000040
-set_bits   32 0x4006b008 0x00002000
diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
deleted file mode 100644
index 742275b92f..0000000000
--- a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * VFxxx shared DDR IOMUX DCD code. Intended use is to share code
- * between all board that copy VF610 Tower Board DDR reference
- * layout/design
- *
- * Copyright (C) 2018 Zodiac Inflight Innovations
- */
-
-#define VF610_DDR_PAD_CTRL	0x00000180 /* 40 Ohm drive strength */
-#define VF610_DDR_PAD_CTRL_1	0x00010180 /* ditto + differential input */
-
-wm 32 VF610_PAD_DDR_A15__DDR_A_15	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A14__DDR_A_14	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A13__DDR_A_13	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A12__DDR_A_12	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A11__DDR_A_11	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A10__DDR_A_10	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A9__DDR_A_9		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A8__DDR_A_8		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A7__DDR_A_7		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A6__DDR_A_6		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A5__DDR_A_5		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A4__DDR_A_4		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A3__DDR_A_3		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A2__DDR_A_2		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A1__DDR_A_1		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_A0__DDR_A_0		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_BA2__DDR_BA_2	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_BA1__DDR_BA_1	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_BA0__DDR_BA_0	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_CAS__DDR_CAS_B	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_CKE__DDR_CKE_0	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_CLK__DDR_CLK_0	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_CS__DDR_CS_B_0	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D15__DDR_D_15	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D14__DDR_D_14	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D13__DDR_D_13	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D12__DDR_D_12	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D11__DDR_D_11	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D10__DDR_D_10	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D9__DDR_D_9		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D8__DDR_D_8		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D7__DDR_D_7		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D6__DDR_D_6		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D5__DDR_D_5		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D4__DDR_D_4		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D3__DDR_D_3		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D2__DDR_D_2		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D1__DDR_D_1		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D0__DDR_D_0		VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_DQM1__DDR_DQM_1	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_DQM0__DDR_DQM_0	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_DQS1__DDR_DQS_1	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_DQS0__DDR_DQS_0	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_RAS__DDR_RAS_B	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_WE__DDR_WE_B	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_ODT1__DDR_ODT_0	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_ODT0__DDR_ODT_1	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_RESETB		VF610_DDR_PAD_CTRL
-
-wm 32 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 VF610_DDR_PAD_CTRL
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
deleted file mode 100644
index f30133a05a..0000000000
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ /dev/null
@@ -1,272 +0,0 @@
-#ifndef __MACH_GENERIC_H
-#define __MACH_GENERIC_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <bootsource.h>
-#include <mach/imx_cpu_types.h>
-
-u64 imx_uid(void);
-
-void imx25_boot_save_loc(void);
-void imx35_boot_save_loc(void);
-void imx27_boot_save_loc(void);
-void imx51_boot_save_loc(void);
-void imx53_boot_save_loc(void);
-void imx6_boot_save_loc(void);
-void imx7_boot_save_loc(void);
-void vf610_boot_save_loc(void);
-void imx8mm_boot_save_loc(void);
-void imx8mp_boot_save_loc(void);
-void imx8mq_boot_save_loc(void);
-
-void imx25_get_boot_source(enum bootsource *src, int *instance);
-void imx27_get_boot_source(enum bootsource *src, int *instance);
-void imx35_get_boot_source(enum bootsource *src, int *instance);
-void imx51_get_boot_source(enum bootsource *src, int *instance);
-void imx53_get_boot_source(enum bootsource *src, int *instance);
-void imx6_get_boot_source(enum bootsource *src, int *instance);
-void imx7_get_boot_source(enum bootsource *src, int *instance);
-void vf610_get_boot_source(enum bootsource *src, int *instance);
-void imx8mm_get_boot_source(enum bootsource *src, int *instance);
-void imx8mp_get_boot_source(enum bootsource *src, int *instance);
-void imx8mq_get_boot_source(enum bootsource *src, int *instance);
-
-int imx1_init(void);
-int imx21_init(void);
-int imx25_init(void);
-int imx27_init(void);
-int imx31_init(void);
-int imx35_init(void);
-int imx50_init(void);
-int imx51_init(void);
-int imx53_init(void);
-int imx6_init(void);
-int imx7_init(void);
-int vf610_init(void);
-int imx8mm_init(void);
-int imx8mp_init(void);
-int imx8mq_init(void);
-
-int imx1_devices_init(void);
-int imx21_devices_init(void);
-int imx25_devices_init(void);
-int imx27_devices_init(void);
-int imx31_devices_init(void);
-int imx35_devices_init(void);
-int imx50_devices_init(void);
-int imx51_devices_init(void);
-int imx53_devices_init(void);
-int imx6_devices_init(void);
-
-void imx5_cpu_lowlevel_init(void);
-void imx6_cpu_lowlevel_init(void);
-void imx6ul_cpu_lowlevel_init(void);
-void imx7_cpu_lowlevel_init(void);
-void vf610_cpu_lowlevel_init(void);
-void imx8mq_cpu_lowlevel_init(void);
-void imx8mm_cpu_lowlevel_init(void);
-void imx8mp_cpu_lowlevel_init(void);
-
-/* There's a off-by-one betweem the gpio bank number and the gpiochip */
-/* range e.g. GPIO_1_5 is gpio 5 under linux */
-#define IMX_GPIO_NR(bank, nr)		(((bank) - 1) * 32 + (nr))
-
-extern unsigned int __imx_cpu_type;
-
-#ifdef CONFIG_ARCH_IMX1
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX1
-# endif
-# define cpu_is_mx1()		(imx_cpu_type == IMX_CPU_IMX1)
-#else
-# define cpu_is_mx1()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX21
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX21
-# endif
-# define cpu_is_mx21()		(imx_cpu_type == IMX_CPU_IMX21)
-#else
-# define cpu_is_mx21()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX25
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX25
-# endif
-# define cpu_is_mx25()		(imx_cpu_type == IMX_CPU_IMX25)
-#else
-# define cpu_is_mx25()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX27
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX27
-# endif
-# define cpu_is_mx27()		(imx_cpu_type == IMX_CPU_IMX27)
-#else
-# define cpu_is_mx27()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX31
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX31
-# endif
-# define cpu_is_mx31()		(imx_cpu_type == IMX_CPU_IMX31)
-#else
-# define cpu_is_mx31()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX35
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX35
-# endif
-# define cpu_is_mx35()		(imx_cpu_type == IMX_CPU_IMX35)
-#else
-# define cpu_is_mx35()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX50
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX50
-# endif
-# define cpu_is_mx50()		(imx_cpu_type == IMX_CPU_IMX50)
-#else
-# define cpu_is_mx50()		(0)
-#endif
-
-
-#ifdef CONFIG_ARCH_IMX51
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX51
-# endif
-# define cpu_is_mx51()		(imx_cpu_type == IMX_CPU_IMX51)
-#else
-# define cpu_is_mx51()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX53
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX53
-# endif
-# define cpu_is_mx53()		(imx_cpu_type == IMX_CPU_IMX53)
-#else
-# define cpu_is_mx53()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX6
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX6
-# endif
-# define cpu_is_mx6()		(imx_cpu_type == IMX_CPU_IMX6)
-#else
-# define cpu_is_mx6()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX7
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX7
-# endif
-# define cpu_is_mx7()		(imx_cpu_type == IMX_CPU_IMX7)
-#else
-# define cpu_is_mx7()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX8MM
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX8MM
-# endif
-# define cpu_is_mx8mm()	(imx_cpu_type == IMX_CPU_IMX8MM)
-#else
-# define cpu_is_mx8mm()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX8MP
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX8MP
-# endif
-# define cpu_is_mx8mp()	(imx_cpu_type == IMX_CPU_IMX8MP)
-#else
-# define cpu_is_mx8mp()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX8MQ
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_IMX8MQ
-# endif
-# define cpu_is_mx8mq()	(imx_cpu_type == IMX_CPU_IMX8MQ)
-#else
-# define cpu_is_mx8mq()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_VF610
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type IMX_CPU_VF610
-# endif
-# define cpu_is_vf610()		(imx_cpu_type == IMX_CPU_VF610)
-#else
-# define cpu_is_vf610()		(0)
-#endif
-
-#ifdef CONFIG_BOARD_ARM_GENERIC_DT
-# ifdef imx_cpu_type
-#  undef imx_cpu_type
-#  define imx_cpu_type __imx_cpu_type
-# else
-#  define imx_cpu_type 0
-# endif
-#endif
-
-#define cpu_is_mx23()	(0)
-#define cpu_is_mx28()	(0)
-
-#define cpu_is_mx8m()	(cpu_is_mx8mq() || cpu_is_mx8mm() || cpu_is_mx8mp())
-
-#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h b/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h
deleted file mode 100644
index 60f730f8ec..0000000000
--- a/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This snippet can be included from a i.MX flash header configuration
- * file for generating signed images. The necessary keys/certificates
- * are expected in these config variables:
- *
- * CONFIG_HABV3_SRK_PEM
- * CONFIG_HABV3_CSF_CRT_DER
- * CONFIG_HABV3_IMG_CRT_DER
- */
-super_root_key CONFIG_HABV3_SRK_PEM
-
-hab [Header]
-hab Version = 3.0
-hab Security Configuration = Production
-hab Hash Algorithm = SHA256
-hab Engine = RTIC
-hab Certificate Format = WTLS
-hab Signature Format = PKCS1
-hab UID = Generic
-hab Code = 0x00
-
-hab [Install SRK]
-hab File = "not-used"
-
-hab [Install CSFK]
-/* target key index in keystore 1 */
-hab File = CONFIG_HABV3_CSF_CRT_DER
-
-hab [Authenticate CSF]
-
-/* unlock the access to the DryIce registers */
-hab [Write Data]
-hab Width = 4
-hab Address Data = 0x53FFC03C 0xCA693569
-
-hab [Install Key]
-/* verification key index in key store (1...4) */
-/* in contrast to documentation 0 seems to be valid, too */
-hab Verification index = 1
-/* target key index in key store (1...4) */
-hab Target index = 2
-hab File = CONFIG_HABV3_IMG_CRT_DER
-
-hab [Authenticate Data]
-/* verification key index in key store (2...4) */
-hab Verification index = 2
-
-hab_blocks
diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h
deleted file mode 100644
index 668fb0646f..0000000000
--- a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This snippet can be included from a i.MX flash header configuration
- * file for generating signed images. The necessary keys/certificates
- * are expected in these config variables:
- *
- * CONFIG_HABV4_TABLE_BIN
- * CONFIG_HABV4_CSF_CRT_PEM
- * CONFIG_HABV4_IMG_CRT_PEM
- */
-
-#ifndef SETUP_HABV4_ENGINE
-#error "SETUP_HABV4_ENGINE undefined"
-#endif
-
-hab [Header]
-hab Version = 4.1
-hab Hash Algorithm = sha256
-hab Engine Configuration = 0
-hab Certificate Format = X509
-hab Signature Format = CMS
-hab Engine = SETUP_HABV4_ENGINE
-
-hab [Install SRK]
-hab File = CONFIG_HABV4_TABLE_BIN
-hab # SRK index within SRK-Table 0..3
-hab Source index = CONFIG_HABV4_SRK_INDEX
-
-hab [Install CSFK]
-/* target key index in keystore 1 */
-hab File = CONFIG_HABV4_CSF_CRT_PEM
-
-hab [Authenticate CSF]
-
-hab [Unlock]
-hab Engine = SETUP_HABV4_ENGINE
-#ifdef SETUP_HABV4_FEATURES
-hab Features = SETUP_HABV4_FEATURES
-#endif
-
-hab [Install Key]
-/* verification key index in key store (0, 2...4) */
-hab Verification index = 0
-/* target key index in key store (2...4) */
-hab Target index = 2
-hab File = CONFIG_HABV4_IMG_CRT_PEM
-
-hab [Authenticate Data]
-/* verification key index in key store (2...4) */
-hab Verification index = 2
-
-hab_blocks
-
-hab_encrypt [Install Secret Key]
-hab_encrypt Verification index = 0
-hab_encrypt Target index = 0
-hab_encrypt_key
-hab_encrypt_key_length 256
-hab_encrypt_blob_address
-
-hab_encrypt [Decrypt Data]
-hab_encrypt Verification index = 0
-hab_encrypt Mac Bytes = 16
-
-hab_encrypt_blocks
diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h
deleted file mode 100644
index ca741b2736..0000000000
--- a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h
+++ /dev/null
@@ -1,5 +0,0 @@
-
-#define SETUP_HABV4_ENGINE CAAM
-#define SETUP_HABV4_FEATURES  RNG, MID
-
-#include <mach/habv4-imx6-gencsf-template.h>
diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6ull-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx6ull-gencsf.h
deleted file mode 100644
index 6a558b880b..0000000000
--- a/arch/arm/mach-imx/include/mach/habv4-imx6ull-gencsf.h
+++ /dev/null
@@ -1,4 +0,0 @@
-
-#define SETUP_HABV4_ENGINE SW
-
-#include <mach/habv4-imx6-gencsf-template.h>
diff --git a/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h
deleted file mode 100644
index a3917cc74f..0000000000
--- a/arch/arm/mach-imx/include/mach/habv4-imx8-gencsf.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This snippet can be included from a i.MX flash header configuration
- * file for generating signed images. The necessary keys/certificates
- * are expected in these config variables:
- *
- * CONFIG_HABV4_TABLE_BIN
- * CONFIG_HABV4_CSF_CRT_PEM
- * CONFIG_HABV4_IMG_CRT_PEM
- */
-#if defined(CONFIG_HABV4) && defined(CONFIG_CPU_64)
-hab [Header]
-hab Version = 4.3
-hab Hash Algorithm = sha256
-hab Engine Configuration = 0
-hab Certificate Format = X509
-hab Signature Format = CMS
-hab Engine = CAAM
-
-hab [Install SRK]
-hab File = CONFIG_HABV4_TABLE_BIN
-hab # SRK index within SRK-Table 0..3
-hab Source index = CONFIG_HABV4_SRK_INDEX
-
-hab [Install CSFK]
-/* target key index in keystore 1 */
-hab File = CONFIG_HABV4_CSF_CRT_PEM
-
-hab [Authenticate CSF]
-
-hab [Unlock]
-hab Engine = CAAM
-hab Features = RNG, MID
-
-hab [Install Key]
-/* verification key index in key store (0, 2...4) */
-hab Verification index = 0
-/* target key index in key store (2...4) */
-hab Target index = 2
-hab File = CONFIG_HABV4_IMG_CRT_PEM
-
-hab [Authenticate Data]
-/* verification key index in key store (2...4) */
-hab Verification index = 2
-
-hab_blocks
-
-hab_encrypt [Install Secret Key]
-hab_encrypt Verification index = 0
-hab_encrypt Target index = 0
-hab_encrypt_key
-hab_encrypt_key_length 256
-hab_encrypt_blob_address
-
-hab_encrypt [Decrypt Data]
-hab_encrypt Verification index = 0
-hab_encrypt Mac Bytes = 16
-
-hab_encrypt_blocks
-#endif
diff --git a/arch/arm/mach-imx/include/mach/iim.h b/arch/arm/mach-imx/include/mach/iim.h
deleted file mode 100644
index 3199e4e790..0000000000
--- a/arch/arm/mach-imx/include/mach/iim.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */
-
-#ifndef __MACH_IMX_IIM_H
-#define __MACH_IMX_IIM_H
-
-#include <errno.h>
-#include <net.h>
-
-#define IIM_STAT	0x0000
-#define IIM_STATM	0x0004
-#define IIM_ERR		0x0008
-#define IIM_EMASK	0x000C
-#define IIM_FCTL	0x0010
-#define IIM_UA		0x0014
-#define IIM_LA		0x0018
-#define IIM_SDAT	0x001C
-#define IIM_PREV	0x0020
-#define IIM_SREV	0x0024
-#define IIM_PREG_P	0x0028
-#define IIM_SCS0	0x002C
-#define IIM_SCS1	0x0030
-#define IIM_SCS2	0x0034
-#define IIM_SCS3	0x0038
-
-#ifdef CONFIG_IMX_IIM
-int imx_iim_read(unsigned int bank, int offset, void *buf, int count);
-#else
-static inline int imx_iim_read(unsigned int bank, int offset, void *buf,
-		int count)
-{
-	return -EINVAL;
-}
-#endif /* CONFIG_IMX_IIM */
-
-static inline int imx51_iim_register_fec_ethaddr(void)
-{
-	int ret;
-	u8 buf[6];
-
-	ret = imx_iim_read(1, 9, buf, 6);
-	if (ret != 6)
-		return -EINVAL;
-
-	eth_register_ethaddr(0, buf);
-
-	return 0;
-}
-
-static inline int imx53_iim_register_fec_ethaddr(void)
-{
-	return imx51_iim_register_fec_ethaddr();
-}
-
-static inline int imx25_iim_register_fec_ethaddr(void)
-{
-	int ret;
-	u8 buf[6];
-
-	ret = imx_iim_read(0, 26, buf, 6);
-	if (ret != 6)
-		return -EINVAL;
-
-	eth_register_ethaddr(0, buf);
-
-	return 0;
-}
-
-#define IIM_BANK_MASK_WIDTH	3
-#define IIM_BANK_MASK_SHIFT	0
-#define IIM_BANK(n)		(((n) & ((1 << IIM_BANK_MASK_WIDTH) - 1)) << IIM_BANK_MASK_SHIFT)
-
-#define IIM_BYTE_MASK_WIDTH	5
-#define IIM_BYTE_MASK_SHIFT	IIM_BANK_MASK_WIDTH
-#define IIM_BYTE(n)		((((n) >> 2) & ((1 << IIM_BYTE_MASK_WIDTH) - 1)) << IIM_BYTE_MASK_SHIFT)
-
-#define IIM_BIT_MASK_WIDTH	3
-#define IIM_BIT_MASK_SHIFT	(IIM_BYTE_MASK_SHIFT + IIM_BYTE_MASK_WIDTH)
-#define IIM_BIT(n)		(((n) & ((1 << IIM_BIT_MASK_WIDTH) - 1)) << IIM_BIT_MASK_SHIFT)
-
-#define IIM_WIDTH_MASK_WIDTH	3
-#define IIM_WIDTH_MASK_SHIFT	(IIM_BIT_MASK_SHIFT + IIM_BIT_MASK_WIDTH)
-#define IIM_WIDTH(n)		((((n) - 1) & ((1 << IIM_WIDTH_MASK_WIDTH) - 1)) << IIM_WIDTH_MASK_SHIFT)
-
-int imx_iim_read_field(uint32_t field, unsigned *value);
-int imx_iim_write_field(uint32_t field, unsigned value);
-int imx_iim_permanent_write(int enable);
-
-#endif /* __MACH_IMX_IIM_H */
diff --git a/arch/arm/mach-imx/include/mach/imx-gpio.h b/arch/arm/mach-imx/include/mach/imx-gpio.h
deleted file mode 100644
index 64ac278d61..0000000000
--- a/arch/arm/mach-imx/include/mach/imx-gpio.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef __MACH_IMX_GPIO_H
-#define __MACH_IMX_GPIO_H
-
-#include <io.h>
-
-/*
- * i.MX lowlevel gpio functions. Only for use with lowlevel code. Use
- * regular gpio functions outside of lowlevel code!
- */
-
-static inline void imx_gpio_direction(void __iomem *gdir, void __iomem *dr,
-		int gpio, int out, int value)
-{
-	uint32_t val;
-
-	val = readl(gdir);
-	if (out)
-		val |= 1 << gpio;
-	else
-		val &= ~(1 << gpio);
-	writel(val, gdir);
-
-	if (!out)
-		return;
-
-	val = readl(dr);
-	if (value)
-		val |= 1 << gpio;
-	else
-		val &= ~(1 << gpio);
-
-	writel(val, dr);
-}
-
-static inline void imx1_gpio_direction_output(void __iomem *base, int gpio, int value)
-{
-	imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 1, value);
-}
-
-#define imx21_gpio_direction_output(base, gpio, value) imx1_gpio_direction_output(base, gpio,value)
-#define imx27_gpio_direction_output(base, gpio, value) imx1_gpio_direction_output(base, gpio,value)
-
-static inline void imx31_gpio_direction_output(void __iomem *base, int gpio, int value)
-{
-	imx_gpio_direction(base + 0x4, base + 0x0, gpio, 1, value);
-}
-
-#define imx25_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value)
-#define imx35_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value)
-#define imx51_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value)
-#define imx53_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value)
-#define imx6_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value)
-#define imx8m_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value)
-
-static inline void imx1_gpio_direction_input(void __iomem *base, int gpio, int value)
-{
-	imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 0, 0);
-}
-
-#define imx21_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio)
-#define imx27_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio)
-
-static inline void imx31_gpio_direction_input(void __iomem *base, int gpio)
-{
-	imx_gpio_direction(base + 0x4, base + 0x0, gpio, 0, 0);
-}
-
-#define imx25_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio)
-#define imx35_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio)
-#define imx51_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio)
-#define imx53_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio)
-#define imx6_gpio_direction_input(base, gpio) imx31_gpio_direction_input(base, gpio)
-#define imx8m_gpio_direction_input(base, gpio) imx31_gpio_direction_input(base, gpio)
-
-static inline int imx1_gpio_val(void __iomem *base, int gpio)
-{
-	return readl(base + 0x1c) & (1 << gpio) ? 1 : 0;
-}
-
-static inline int imx31_gpio_val(void __iomem *base, int gpio)
-{
-	return readl(base) & (1 << gpio) ? 1 : 0;
-}
-
-#define imx21_gpio_val(base, gpio) imx1_gpio_val(base, gpio)
-#define imx27_gpio_val(base, gpio) imx1_gpio_val(base, gpio)
-#define imx25_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
-#define imx35_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
-#define imx51_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
-#define imx53_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
-#define imx6_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
-#define imx8m_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
-
-#endif /* __MACH_IMX_GPIO_H */
diff --git a/arch/arm/mach-imx/include/mach/imx-header.h b/arch/arm/mach-imx/include/mach/imx-header.h
deleted file mode 100644
index f1e076dab9..0000000000
--- a/arch/arm/mach-imx/include/mach/imx-header.h
+++ /dev/null
@@ -1,150 +0,0 @@
-#ifndef __IMX_HEADER_H__
-#define __IMX_HEADER_H__
-
-#include <linux/types.h>
-
-#define HEADER_LEN 0x1000	/* length of the blank area + IVT + DCD */
-#define CSF_LEN 0x2000		/* length of the CSF (needed for HAB) */
-
-#define DEK_BLOB_HEADER 8	/* length of DEK blob header */
-#define DEK_BLOB_KEY 32		/* length of DEK blob AES-256 key */
-#define DEK_BLOB_MAC 16		/* length of DEK blob MAC */
-
-/* DEK blob length excluding DEK itself */
-#define DEK_BLOB_OVERHEAD (DEK_BLOB_HEADER + DEK_BLOB_KEY + DEK_BLOB_MAC)
-
-/*
- * ============================================================================
- * i.MX flash header v1 handling. Found on i.MX35 and i.MX51
- * ============================================================================
- */
-#define DCD_BARKER       0xb17219e9
-
-struct imx_flash_header {
-	uint32_t app_code_jump_vector;
-	uint32_t app_code_barker;
-	uint32_t app_code_csf;
-	uint32_t dcd_ptr_ptr;
-	uint32_t super_root_key;
-	uint32_t dcd;
-	uint32_t app_dest;
-	uint32_t dcd_barker;
-	uint32_t dcd_block_len;
-} __attribute__((packed));
-
-struct imx_boot_data {
-	uint32_t start;
-	uint32_t size;
-	uint32_t plugin;
-} __attribute__((packed));
-
-struct imx_dcd_rec_v1 {
-	uint32_t type;
-	uint32_t addr;
-	uint32_t val;
-} __attribute__((packed));
-
-#define TAG_IVT_HEADER	0xd1
-#define IVT_VERSION	0x40
-#define TAG_DCD_HEADER	0xd2
-#define DCD_VERSION	0x40
-#define TAG_UNLOCK	0xb2
-#define TAG_NOP		0xc0
-#define TAG_WRITE	0xcc
-#define TAG_CHECK	0xcf
-#define PARAMETER_FLAG_MASK	(1 << 3)
-#define PARAMETER_FLAG_SET	(1 << 4)
-
-#define PLUGIN_HDMI_IMAGE	0x0002
-
-/*
- * As per Table 6-22 "eMMC/SD BOOT layout", in Normal Boot layout HDMI
- * firmware image starts at LBA# 64 and ends at LBA# 271
- */
-#define PLUGIN_HDMI_SIZE	((271 - 64 + 1) * 512)
-
-struct imx_ivt_header {
-	uint8_t tag;
-	uint16_t length;
-	uint8_t version;
-} __attribute__((packed));
-
-struct imx_flash_header_v2 {
-	struct imx_ivt_header header;
-
-	uint32_t entry;
-	uint32_t reserved1;
-	uint32_t dcd_ptr;
-	uint32_t boot_data_ptr;
-	uint32_t self;
-	uint32_t csf;
-	uint32_t reserved2;
-
-	struct imx_boot_data boot_data;
-	struct imx_ivt_header dcd_header;
-} __attribute__((packed));
-
-static inline bool is_imx_flash_header_v2(const void *blob)
-{
-	const struct imx_flash_header_v2 *hdr = blob;
-
-	return  hdr->header.tag == TAG_IVT_HEADER &&
-		hdr->header.version >= IVT_VERSION;
-}
-
-struct config_data {
-	uint32_t image_load_addr;
-	uint32_t image_ivt_offset;
-	uint32_t image_size;
-	uint32_t max_load_size;
-	uint32_t load_size;
-	uint32_t pbl_code_size;
-	char *outfile;
-	char *srkfile;
-	int header_version;
-	off_t header_gap;
-	uint32_t first_opcode;
-	int cpu_type;
-	int (*check)(const struct config_data *data, uint32_t cmd,
-		     uint32_t addr, uint32_t mask);
-	int (*write_mem)(const struct config_data *data, uint32_t addr,
-			 uint32_t val, int width, int set_bits, int clear_bits);
-	int (*nop)(const struct config_data *data);
-	int csf_space;
-	char *csf;
-	int sign_image;
-	char *signed_hdmi_firmware_file;
-	int encrypt_image;
-	size_t dek_size;
-};
-
-#define MAX_RECORDS_DCD_V2 1024
-struct imx_dcd_v2_write_rec {
-	uint32_t addr;
-	uint32_t val;
-} __attribute__((packed));
-
-struct imx_dcd_v2_write {
-	uint8_t tag;
-	uint16_t length;
-	uint8_t param;
-	struct imx_dcd_v2_write_rec data[MAX_RECORDS_DCD_V2];
-} __attribute__((packed));
-
-struct imx_dcd_v2_check {
-	uint8_t tag;
-	uint16_t length;
-	uint8_t param;
-	uint32_t addr;
-	uint32_t mask;
-	uint32_t count;
-} __attribute__((packed));
-
-enum imx_dcd_v2_check_cond {
-	until_all_bits_clear = 0, /* until ((*address & mask) == 0) { ...} */
-	until_any_bit_clear = 1, /* until ((*address & mask) != mask) { ...} */
-	until_all_bits_set = 2, /* until ((*address & mask) == mask) { ...} */
-	until_any_bit_set = 3, /* until ((*address & mask) != 0) { ...} */
-} __attribute__((packed));
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h
deleted file mode 100644
index 651bf9a5c9..0000000000
--- a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* SPDX-FileCopyrightText: 2008 Guennadi Liakhovetski <lg@denx.de>, DENX Software Engineering */
-
-#ifndef __MACH_IMX_IPU_FB_H__
-#define __MACH_IMX_IPU_FB_H__
-
-#include <fb.h>
-
-/* Proprietary FB_SYNC_ flags */
-#define FB_SYNC_OE_ACT_HIGH	0x80000000
-#define FB_SYNC_CLK_INVERT	0x40000000
-#define FB_SYNC_DATA_INVERT	0x20000000
-#define FB_SYNC_CLK_IDLE_EN	0x10000000
-#define FB_SYNC_SHARP_MODE	0x08000000
-#define FB_SYNC_SWAP_RGB	0x04000000
-#define FB_SYNC_CLK_SEL_EN	0x02000000
-
-/*
- * Specify the way your display is connected. The IPU can arbitrarily
- * map the internal colors to the external data lines. We only support
- * the following mappings at the moment.
- */
-enum disp_data_mapping {
-	/* blue -> d[0..5], green -> d[6..11], red -> d[12..17] */
-	IPU_DISP_DATA_MAPPING_RGB666,
-	/* blue -> d[0..4], green -> d[5..10], red -> d[11..15] */
-	IPU_DISP_DATA_MAPPING_RGB565,
-	/* blue -> d[0..7], green -> d[8..15], red -> d[16..23] */
-	IPU_DISP_DATA_MAPPING_RGB888,
-};
-
-/*
- * struct mx3fb_platform_data - mx3fb platform data
- */
-struct imx_ipu_fb_platform_data {
-	struct fb_videomode	*mode;
-	unsigned char		bpp;
-	u_int			num_modes;
-	enum disp_data_mapping	disp_data_fmt;
-	void __iomem		*framebuffer;
-	unsigned long		framebuffer_size;
-	void __iomem		*framebuffer_ovl;
-	unsigned long		framebuffer_ovl_size;
-	/** hook to enable backlight and stuff */
-	void			(*enable)(int enable);
-	/*
-	 * Fractional pixelclock divider causes jitter which some displays
-	 * or LVDS transceivers can't handle. Disable it if necessary.
-	 */
-	int			disable_fractional_divider;
-};
-
-#endif /* __MACH_IMX_IPU_FB_H__ */
-
diff --git a/arch/arm/mach-imx/include/mach/imx-nand.h b/arch/arm/mach-imx/include/mach/imx-nand.h
deleted file mode 100644
index f34799a011..0000000000
--- a/arch/arm/mach-imx/include/mach/imx-nand.h
+++ /dev/null
@@ -1,137 +0,0 @@
-#ifndef __ASM_ARCH_NAND_H
-#define __ASM_ARCH_NAND_H
-
-#include <linux/mtd/mtd.h>
-
-void imx25_nand_load_image(void);
-void imx27_nand_load_image(void);
-void imx31_nand_load_image(void);
-void imx35_nand_load_image(void);
-
-void imx25_nand_relocate_to_sdram(void __noreturn (*fn)(void));
-void imx27_nand_relocate_to_sdram(void __noreturn (*fn)(void));
-void imx31_nand_relocate_to_sdram(void __noreturn (*fn)(void));
-void imx35_nand_relocate_to_sdram(void __noreturn (*fn)(void));
-
-void imx25_barebox_boot_nand_external(void);
-void imx27_barebox_boot_nand_external(void);
-void imx31_barebox_boot_nand_external(void);
-void imx35_barebox_boot_nand_external(void);
-void imx_nand_set_layout(int writesize, int datawidth);
-
-struct imx_nand_platform_data {
-	int width;
-	unsigned int hw_ecc:1;
-	unsigned int flash_bbt:1;
-};
-
-#define nfc_is_v21()		(cpu_is_mx25() || cpu_is_mx35())
-#define nfc_is_v1()		(cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
-#define nfc_is_v3_2()		(cpu_is_mx51() || cpu_is_mx53())
-#define nfc_is_v3()		nfc_is_v3_2()
-
-#define NFC_V1_ECC_STATUS_RESULT	0x0c
-#define NFC_V1_RSLTMAIN_AREA		0x0e
-#define NFC_V1_RSLTSPARE_AREA		0x10
-
-#define NFC_V2_ECC_STATUS_RESULT1	0x0c
-#define NFC_V2_ECC_STATUS_RESULT2	0x0e
-#define NFC_V2_SPAS			0x10
-
-#define NFC_V1_V2_BUF_SIZE		0x00
-#define NFC_V1_V2_BUF_ADDR		0x04
-#define NFC_V1_V2_FLASH_ADDR		0x06
-#define NFC_V1_V2_FLASH_CMD		0x08
-#define NFC_V1_V2_CONFIG		0x0a
-
-#define NFC_V1_V2_WRPROT		0x12
-#define NFC_V1_UNLOCKSTART_BLKADDR	0x14
-#define NFC_V1_UNLOCKEND_BLKADDR	0x16
-#define NFC_V21_UNLOCKSTART_BLKADDR	0x20
-#define NFC_V21_UNLOCKEND_BLKADDR	0x22
-#define NFC_V1_V2_NF_WRPRST		0x18
-#define NFC_V1_V2_CONFIG1		0x1a
-#define NFC_V1_V2_CONFIG2		0x1c
-
-#define NFC_V2_CONFIG1_ECC_MODE_4       (1 << 0)
-#define NFC_V1_V2_CONFIG1_SP_EN		(1 << 2)
-#define NFC_V1_V2_CONFIG1_ECC_EN	(1 << 3)
-#define NFC_V1_V2_CONFIG1_INT_MSK	(1 << 4)
-#define NFC_V1_V2_CONFIG1_BIG		(1 << 5)
-#define NFC_V1_V2_CONFIG1_RST		(1 << 6)
-#define NFC_V1_V2_CONFIG1_CE		(1 << 7)
-#define NFC_V1_V2_CONFIG1_ONE_CYCLE	(1 << 8)
-#define NFC_V2_CONFIG1_PPB(x)		(((x) & 0x3) << 9)
-#define NFC_V2_CONFIG1_FP_INT		(1 << 11)
-
-#define NFC_V1_V2_CONFIG2_INT		(1 << 15)
-
-#define NFC_V2_SPAS_SPARESIZE(spas)	((spas) >> 1)
-
-#define NFC_V3_FLASH_CMD		(host->regs_axi + 0x00)
-#define NFC_V3_FLASH_ADDR0		(host->regs_axi + 0x04)
-
-#define NFC_V3_CONFIG1			(host->regs_axi + 0x34)
-#define NFC_V3_CONFIG1_SP_EN		(1 << 0)
-#define NFC_V3_CONFIG1_RBA(x)		(((x) & 0x7 ) << 4)
-
-#define NFC_V3_ECC_STATUS_RESULT	(host->regs_axi + 0x38)
-
-#define NFC_V3_LAUNCH			(host->regs_axi + 0x40)
-
-#define NFC_V3_WRPROT			(host->regs_ip + 0x0)
-#define NFC_V3_WRPROT_LOCK_TIGHT	(1 << 0)
-#define NFC_V3_WRPROT_LOCK		(1 << 1)
-#define NFC_V3_WRPROT_UNLOCK		(1 << 2)
-#define NFC_V3_WRPROT_BLS_UNLOCK	(2 << 6)
-
-#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
-
-#define NFC_V3_CONFIG2			(host->regs_ip + 0x24)
-#define NFC_V3_CONFIG2_PS_512			(0 << 0)
-#define NFC_V3_CONFIG2_PS_2048			(1 << 0)
-#define NFC_V3_CONFIG2_PS_4096			(2 << 0)
-#define NFC_V3_CONFIG2_ONE_CYCLE		(1 << 2)
-#define NFC_V3_CONFIG2_ECC_EN			(1 << 3)
-#define NFC_V3_CONFIG2_2CMD_PHASES		(1 << 4)
-#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0		(1 << 5)
-#define NFC_V3_CONFIG2_ECC_MODE_8		(1 << 6)
-#define NFC_V3_MX51_CONFIG2_PPB(x)		(((x) & 0x3) << 7)
-#define NFC_V3_MX53_CONFIG2_PPB(x)		(((x) & 0x3) << 8)
-#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)	(((x) & 0x3) << 12)
-#define NFC_V3_CONFIG2_INT_MSK			(1 << 15)
-#define NFC_V3_CONFIG2_ST_CMD(x)		(((x) & 0xff) << 24)
-#define NFC_V3_CONFIG2_SPAS(x)			(((x) & 0xff) << 16)
-
-#define NFC_V3_CONFIG3				(host->regs_ip + 0x28)
-#define NFC_V3_CONFIG3_ADD_OP(x)		(((x) & 0x3) << 0)
-#define NFC_V3_CONFIG3_FW8			(1 << 3)
-#define NFC_V3_CONFIG3_SBB(x)			(((x) & 0x7) << 8)
-#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)	(((x) & 0x7) << 12)
-#define NFC_V3_CONFIG3_RBB_MODE			(1 << 15)
-#define NFC_V3_CONFIG3_NO_SDMA			(1 << 20)
-
-#define NFC_V3_IPC			(host->regs_ip + 0x2C)
-#define NFC_V3_IPC_CREQ			(1 << 0)
-#define NFC_V3_IPC_INT			(1 << 31)
-
-#define NFC_V3_DELAY_LINE		(host->regs_ip + 0x34)
-
-/*
- * Operation modes for the NFC. Valid for v1, v2 and v3
- * type controllers.
- */
-#define NFC_CMD				(1 << 0)
-#define NFC_ADDR			(1 << 1)
-#define NFC_INPUT			(1 << 2)
-#define NFC_OUTPUT			(1 << 3)
-#define NFC_ID				(1 << 4)
-#define NFC_STATUS			(1 << 5)
-
-/*
- * For external NAND boot this defines the magic value for the bad block table
- * This is found at offset ARM_HEAD_SPARE_OFS in the image on NAND.
- */
-#define IMX_NAND_BBT_MAGIC 0xbadb10c0
-
-#endif /* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/mach-imx/include/mach/imx-pll.h b/arch/arm/mach-imx/include/mach/imx-pll.h
deleted file mode 100644
index 0ccf41bcaa..0000000000
--- a/arch/arm/mach-imx/include/mach/imx-pll.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __INCLUDE_ASM_ARCH_IMX_PLL_H
-#define __INCLUDE_ASM_ARCH_IMX_PLL_H
-
-/*
- * This can be used for various PLLs found on
- * i.MX SoCs.
- *
- *                   mfi + mfn / (mfd + 1)
- * fpll = 2 * fref * ---------------------
- *                          pd + 1
- */
-#define IMX_PLL_PD(x)		(((x) & 0xf) << 26)
-#define IMX_PLL_MFD(x)		(((x) & 0x3ff) << 16)
-#define IMX_PLL_MFI(x)		(((x) & 0xf) << 10)
-#define IMX_PLL_MFN(x)		(((x) & 0x3ff) << 0)
-#define IMX_PLL_BRMO		(1 << 31)
-
-/* Assuming 24MHz input clock */
-#define MPCTL_PARAM_532 ((1 << 31) | \
-	IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
-#define MPCTL_PARAM_399 \
-	(IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
-#define PPCTL_PARAM_300 \
-	(IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
-
-#endif /* __INCLUDE_ASM_ARCH_IMX_PLL_H*/
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h
deleted file mode 100644
index 69e57e3cfd..0000000000
--- a/arch/arm/mach-imx/include/mach/imx1-regs.h
+++ /dev/null
@@ -1,86 +0,0 @@
-#ifndef _IMX1_REGS_H
-#define _IMX1_REGS_H
-
-#define MX1_IO_BASE_ADDR	0x00200000
-#define MX1_IO_SIZE		SZ_1M
-
-#define MX1_CSD0_BASE_ADDR	0x08000000
-#define MX1_CSD1_BASE_ADDR	0x0c000000
-
-#define MX1_CS0_PHYS		0x10000000
-#define MX1_CS0_SIZE		0x02000000
-
-#define MX1_CS1_PHYS		0x12000000
-#define MX1_CS1_SIZE		0x01000000
-
-#define MX1_CS2_PHYS		0x13000000
-#define MX1_CS2_SIZE		0x01000000
-
-#define MX1_CS3_PHYS		0x14000000
-#define MX1_CS3_SIZE		0x01000000
-
-#define MX1_CS4_PHYS		0x15000000
-#define MX1_CS4_SIZE		0x01000000
-
-#define MX1_CS5_PHYS		0x16000000
-#define MX1_CS5_SIZE		0x01000000
-
-/*
- *  Register BASEs, based on OFFSETs
- */
-#define MX1_AIPI1_BASE_ADDR		(0x00000 + MX1_IO_BASE_ADDR)
-#define MX1_WDT_BASE_ADDR		(0x01000 + MX1_IO_BASE_ADDR)
-#define MX1_TIM1_BASE_ADDR		(0x02000 + MX1_IO_BASE_ADDR)
-#define MX1_TIM2_BASE_ADDR		(0x03000 + MX1_IO_BASE_ADDR)
-#define MX1_RTC_BASE_ADDR		(0x04000 + MX1_IO_BASE_ADDR)
-#define MX1_LCDC_BASE_ADDR		(0x05000 + MX1_IO_BASE_ADDR)
-#define MX1_UART1_BASE_ADDR		(0x06000 + MX1_IO_BASE_ADDR)
-#define MX1_UART2_BASE_ADDR		(0x07000 + MX1_IO_BASE_ADDR)
-#define MX1_PWM_BASE_ADDR		(0x08000 + MX1_IO_BASE_ADDR)
-#define MX1_DMA_BASE_ADDR		(0x09000 + MX1_IO_BASE_ADDR)
-#define MX1_AIPI2_BASE_ADDR		(0x10000 + MX1_IO_BASE_ADDR)
-#define MX1_SIM_BASE_ADDR		(0x11000 + MX1_IO_BASE_ADDR)
-#define MX1_USBD_BASE_ADDR		(0x12000 + MX1_IO_BASE_ADDR)
-#define MX1_CSPI1_BASE_ADDR		(0x13000 + MX1_IO_BASE_ADDR)
-#define MX1_MMC_BASE_ADDR		(0x14000 + MX1_IO_BASE_ADDR)
-#define MX1_ASP_BASE_ADDR		(0x15000 + MX1_IO_BASE_ADDR)
-#define MX1_BTA_BASE_ADDR		(0x16000 + MX1_IO_BASE_ADDR)
-#define MX1_I2C_BASE_ADDR		(0x17000 + MX1_IO_BASE_ADDR)
-#define MX1_SSI_BASE_ADDR		(0x18000 + MX1_IO_BASE_ADDR)
-#define MX1_CSPI2_BASE_ADDR		(0x19000 + MX1_IO_BASE_ADDR)
-#define MX1_MSHC_BASE_ADDR		(0x1A000 + MX1_IO_BASE_ADDR)
-#define MX1_CCM_BASE_ADDR		(0x1B000 + MX1_IO_BASE_ADDR)
-#define MX1_SCM_BASE_ADDR		(0x1B800 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO_BASE_ADDR		(0x1C000 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO1_BASE_ADDR		(0x1C000 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO2_BASE_ADDR		(0x1C100 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO3_BASE_ADDR		(0x1C200 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO4_BASE_ADDR		(0x1C300 + MX1_IO_BASE_ADDR)
-#define MX1_EIM_BASE_ADDR		(0x20000 + MX1_IO_BASE_ADDR)
-#define MX1_SDRAMC_BASE_ADDR		(0x21000 + MX1_IO_BASE_ADDR)
-#define MX1_MMA_BASE_ADDR		(0x22000 + MX1_IO_BASE_ADDR)
-#define MX1_AVIC_BASE_ADDR		(0x23000 + MX1_IO_BASE_ADDR)
-#define MX1_CSI_BASE_ADDR		(0x24000 + MX1_IO_BASE_ADDR)
-
-/* SYSCTRL Registers (base MX1_SCM_BASE_ADDR) */
-#define MX1_SIDR   0x4 /* Silicon ID Register		    */
-#define MX1_FMCR   0x8 /* Function Multiplex Control Register */
-#define MX1_GPCR   0xC /* Function Multiplex Control Register */
-
-/* SDRAM controller registers (base MX1_SDRAMC_BASE_ADDR) */
-#define MX1_SDCTL0 0x0	/* SDRAM 0 Control Register */
-#define MX1_SDCTL1 0x4	/* SDRAM 1 Control Register */
-#define MX1_SDMISC 0x14	/* Miscellaneous Register */
-#define MX1_SDRST  0x18	/* SDRAM Reset Register */
-
-/* PLL registers (base MX1_CCM_BASE_ADDR) */
-#define MX1_CSCR   0x0	/* Clock Source Control Register */
-#define MX1_MPCTL0 0x4	/* MCU PLL Control Register 0 */
-#define MX1_MPCTL1 0x8	/* MCU PLL and System Clock Register 1 */
-#define MX1_SPCTL0 0xc	/* System PLL Control Register 0 */
-#define MX1_SPCTL1 0x10	/* System PLL Control Register 1 */
-#define MX1_PCDR   0x20	/* Peripheral Clock Divider Register */
-
-#define MX1_CSCR_MPLL_RESTART (1<<21)
-
-#endif /* _IMX1_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h
deleted file mode 100644
index 1fa463a256..0000000000
--- a/arch/arm/mach-imx/include/mach/imx21-regs.h
+++ /dev/null
@@ -1,135 +0,0 @@
-#ifndef _IMX21_REGS_H
-#define _IMX21_REGS_H
-
-#define MX21_AIPI_BASE_ADDR		0x10000000
-#define MX21_AIPI_SIZE			SZ_1M
-#define MX21_DMA_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x01000)
-#define MX21_WDOG_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x02000)
-#define MX21_GPT1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x03000)
-#define MX21_GPT2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x04000)
-#define MX21_GPT3_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x05000)
-#define MX21_PWM_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x06000)
-#define MX21_RTC_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x07000)
-#define MX21_KPP_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x08000)
-#define MX21_OWIRE_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x09000)
-#define MX21_UART1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0a000)
-#define MX21_UART2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0b000)
-#define MX21_UART3_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0c000)
-#define MX21_UART4_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0d000)
-#define MX21_CSPI1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0e000)
-#define MX21_CSPI2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0f000)
-#define MX21_SSI1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x10000)
-#define MX21_SSI2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x11000)
-#define MX21_I2C_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x12000)
-#define MX21_SDHC1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x13000)
-#define MX21_SDHC2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x14000)
-#define MX21_GPIO_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x15000)
-#define MX21_GPIO1_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x000)
-#define MX21_GPIO2_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x100)
-#define MX21_GPIO3_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x200)
-#define MX21_GPIO4_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x300)
-#define MX21_GPIO5_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x400)
-#define MX21_GPIO6_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x500)
-#define MX21_AUDMUX_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x16000)
-#define MX21_CSPI3_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x17000)
-#define MX21_LCDC_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x21000)
-#define MX21_SLCDC_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x22000)
-#define MX21_USBOTG_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x24000)
-#define MX21_EMMA_PP_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x26000)
-#define MX21_EMMA_PRP_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x26400)
-#define MX21_CCM_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x27000)
-#define MX21_SYSCTRL_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x27800)
-#define MX21_JAM_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x3e000)
-#define MX21_MAX_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX21_AVIC_BASE_ADDR		0x10040000
-
-#define MX21_SAHB1_BASE_ADDR		0x80000000
-#define MX21_SAHB1_SIZE			SZ_1M
-#define MX21_CSI_BASE_ADDR			(MX2x_SAHB1_BASE_ADDR + 0x0000)
-
-/* Memory regions and CS */
-#define MX21_SDRAM_BASE_ADDR		0xc0000000
-#define MX21_CSD1_BASE_ADDR		0xc4000000
-
-#define MX21_CS0_BASE_ADDR		0xc8000000
-#define MX21_CS1_BASE_ADDR		0xcc000000
-#define MX21_CS2_BASE_ADDR		0xd0000000
-#define MX21_CS3_BASE_ADDR		0xd1000000
-#define MX21_CS4_BASE_ADDR		0xd2000000
-#define MX21_PCMCIA_MEM_BASE_ADDR	0xd4000000
-#define MX21_CS5_BASE_ADDR		0xdd000000
-
-/* NAND, SDRAM, WEIM etc controllers */
-#define MX21_X_MEMC_BASE_ADDR		0xdf000000
-#define MX21_X_MEMC_SIZE		SZ_256K
-
-#define MX21_SDRAMC_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x0000)
-#define MX21_EIM_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x1000)
-#define MX21_PCMCIA_CTL_BASE_ADDR	(MX21_X_MEMC_BASE_ADDR + 0x2000)
-#define MX21_NFC_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x3000)
-
-#define MX21_IRAM_BASE_ADDR		0xffffe800	/* internal ram */
-#define MX21_IRAM_SIZE			0x00001800
-
-/* AIPI (base MX21_AIPI_BASE_ADDR) */
-#define MX21_AIPI1_PSR0	0x00
-#define MX21_AIPI1_PSR1	0x04
-#define MX21_AIPI2_PSR0	(0x20000 + 0x00)
-#define MX21_AIPI2_PSR1	(0x20000 + 0x04)
-
-/* System Control (base: MX21_SYSCTRL_BASE_ADDR) */
-#define MX21_SUID0	0x4	/* Silicon ID Register (12 bytes) */
-#define MX21_SUID1	0x8	/* Silicon ID Register (12 bytes) */
-#define MX21_CID	0xC	/* Silicon ID Register (12 bytes) */
-#define MX21_FMCR	0x14	/* Function Multeplexing Control Register */
-#define MX21_GPCR	0x18	/* Global Peripheral Control Register */
-#define MX21_WBCR	0x1C	/* Well Bias Control Register */
-#define MX21_DSCR(x)	0x1C + ((x) << 2)	/* Driving Strength Control Register 1 - 13 */
-
-#define MX21_GPCR_BOOT_SHIFT		16
-#define MX21_GPCR_BOOT_MASK		(0xf << GPCR_BOOT_SHIFT)
-#define MX21_GPCR_BOOT_UART_USB		0
-#define MX21_GPCR_BOOT_8BIT_NAND_2k	2
-#define MX21_GPCR_BOOT_16BIT_NAND_2k	3
-#define MX21_GPCR_BOOT_16BIT_NAND_512	4
-#define MX21_GPCR_BOOT_16BIT_CS0	5
-#define MX21_GPCR_BOOT_32BIT_CS0	6
-#define MX21_GPCR_BOOT_8BIT_NAND_512	7
-
-/* SDRAM Controller registers bitfields (base: MX21_X_MEMC_BASE_ADDR) */
-#define MX21_SDCTL0 0x00 /* SDRAM 0 Control Register */
-#define MX21_SDCTL1 0x04 /* SDRAM 0 Control Register */
-#define MX21_SDRST  0x18 /* SDRAM Reset Register */
-#define MX21_SDMISC 0x14 /* SDRAM Miscellaneous Register */
-
-/* PLL registers (base: MX21_CCM_BASE_ADDR) */
-#define MX21_CSCR		0x00 /* Clock Source Control Register       */
-#define MX21_MPCTL0		0x04 /* MCU PLL Control Register 0          */
-#define MX21_MPCTL1		0x08 /* MCU PLL Control Register 1          */
-#define MX21_SPCTL0		0x0c /* System PLL Control Register 0       */
-#define MX21_SPCTL1		0x10 /* System PLL Control Register 1       */
-#define MX21_OSC26MCTL		0x14 /* Oscillator 26M Register             */
-#define MX21_PCDR0		0x18 /* Peripheral Clock Divider Register 0 */
-#define MX21_PCDR1		0x1c /* Peripheral Clock Divider Register 1 */
-#define MX21_PCCR0		0x20 /* Peripheral Clock Control Register 0 */
-#define MX21_PCCR1		0x24 /* Peripheral Clock Control Register 1 */
-#define MX21_CCSR		0x28 /* Clock Control Status Register       */
-
-#define MX21_CSCR_MPEN		(1 << 0)
-#define MX21_CSCR_SPEN		(1 << 1)
-#define MX21_CSCR_FPM_EN	(1 << 2)
-#define MX21_CSCR_OSC26M_DIS	(1 << 3)
-#define MX21_CSCR_OSC26M_DIV1P5	(1 << 4)
-#define MX21_CSCR_MCU_SEL	(1 << 16)
-#define MX21_CSCR_SP_SEL	(1 << 17)
-#define MX21_CSCR_SD_CNT(d)	(((d) & 0x3) << 24)
-#define MX21_CSCR_USB_DIV(d)	(((d) & 0x7) << 26)
-#define MX21_CSCR_PRESC(d)	(((d) & 0x7) << 29)
-
-#define MX21_MPCTL1_BRMO	(1 << 6)
-#define MX21_MPCTL1_LF		(1 << 15)
-
-#define MX21_CCSR_32K_SR	(1 << 15)
-
-#endif /* _IMX21_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx25-fusemap.h b/arch/arm/mach-imx/include/mach/imx25-fusemap.h
deleted file mode 100644
index 749b0d17b2..0000000000
--- a/arch/arm/mach-imx/include/mach/imx25-fusemap.h
+++ /dev/null
@@ -1,272 +0,0 @@
-#ifndef __MACH_IMX25_FUSEMAP_H
-#define __MACH_IMX25_FUSEMAP_H
-
-#include <mach/iim.h>
-
-/* Fuse bank write protect */
-#define IMX25_IIM_FBWP(bank)		(IIM_BANK(bank) | IIM_BYTE(0) | IIM_BIT(7))
-/* Fuse Bank Override Protect */
-#define IMX25_IIM_FBOP(bank)		(IIM_BANK(bank) | IIM_BYTE(0) | IIM_BIT(6))
-/* Fuse Bank Read Protect */
-#define IMX25_IIM_FBRP(bank)		(IIM_BANK(bank) | IIM_BYTE(0) | IIM_BIT(5))
-/* Tester fuses. Burnt on the tester at the end of the wafer sort, locks bank0, rows 001C-003C */
-#define IMX25_IIM_TESTER_LOCK		(IIM_BANK(0) | IIM_BYTE(0) | IIM_BIT(4))
-/* Fuse Banks Explicit Sense Protect */
-#define IMX25_IIM_FBESP(bank)		(IIM_BANK(bank) | IIM_BYTE(0) | IIM_BIT(3))
-/* Locking row 0068-007C, fusebank0 */
-#define IMX25_IIM_MAC_ADDR_LOCK		(IIM_BANK(0) | IIM_BYTE(0) | IIM_BIT(2))
-/* Locking rows 0008 0054-0064, fusebank0 */
-#define IMX25_IIM_TRIM_LOCK		(IIM_BANK(0) | IIM_BYTE(0) | IIM_BIT(1))
-/* Locking rows 0004, 000C-0018, 0040-0044, fusebank0 */
-#define IMX25_IIM_BOOT_LOCK		(IIM_BANK(0) | IIM_BYTE(0) | IIM_BIT(0))
-/* Disabling the Secure JTAG Controller module clock */
-#define IMX25_IIM_SJC_DISABLE		(IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(7))
-
-/* Controls the security mode of the JTAG debug interface */
-#define IMX25_IIM_JTAG_SMODE		(IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(5) | IIM_WIDTH(2))
-
-/* Disable SCC debug through SJC */
-#define IMX25_IIM_JTAG_SCC		(IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(4))
-
-/* JTAG HAB Enable Override (1 = HAB may not enable JTAG debug access */
-#define IMX25_IIM_JTAG_HEO		(IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(3))
-
-/* Secure JTAG Re-enable.
- * 0 Secure JTAG Bypass fuse is not overridden (secure JTAG bypass is allowed)
- * 1 Secure JTAG Bypass fuse is overridden (secure JTAG bypass is not allowed)
- */
-#define IMX25_IIM_SEC_JTAG_RE		(IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(1))
-
-/* JTAG Debug Security Bypass.
- * 0 JTAG Security bypass is not active
- * 1 JTAG Security bypass is active
- */
-#define IMX25_IIM_JTAG_BP		(IIM_BANK(0) | IIM_BYTE(4) | IIM_BIT(0))
-
-/*  High Temperature Detect Configuration. A field in DryIce Analog Configuration Register (DACR) */
-#define IMX25_IIM_HTDC			(IIM_BANK(0) | IIM_BYTE(8) | IIM_BIT(3) | IIM_WIDTH(3))
-
-/*  Low Temperature Detect Configuration. A field in DryIce Analog Configuration Register (DACR) */
-#define IMX25_IIM_LTDC			(IIM_BANK(0) | IIM_BYTE(8) | IIM_BIT(0) | IIM_WIDTH(3))
-
- /*  Choosing the specific eSDHC, CSPI or I2C controller for booting from. */
-#define IMX25_IIM_BT_SRC		(IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(6) | IIM_WIDTH(2))
-
-/* SLC/MLC NAND device. (Former BT_ECC_SEL fuse) Also used as a fast boot mode indication for eMMC 4.3 protocol.
- *	If the bootable device is NAND then
- *		0 SLC NAND device
- *		1 MLC NAND device
- *	If the bootable device is MMC then
- *		0 Do not use eMMC fast boot mode
- *		1 Use eMMC fast boot mode
- */
-#define IMX25_IIM_BT_MLC_SEL		(IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(5))
-
-/* Specifies the size of spare bytes for 4KB page size NAND Flash devices.
- *	If the bootable device is NAND then
- *		0 128 bytes spare (Samsung) (4-IIM_BIT ECC)
- *		1 218 bytes spare (Micron, Toshiba) (8-IIM_BIT ECC)
- *	If the bootable device is SD then
- *		0 ‘FAST_BOOT’ IIM_BIT 29 in ACMD41 argument is 0
- *		1 ‘FAST_BOOT’ IIM_BIT 29 in ACMD41 argument is 1
- */
-#define IMX25_IIM_BT_SPARE_SIZE		(IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(2))
-
- /* Bypassing a pullup on D+ line in case of LPB.
-  *	1 No pullup on D+ line.
-  */
-#define IMX25_IIM_BT_DPLUS_BYPASS	(IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(1))
-
-/* USB boot source selection. Has a corresponding GPIO pin.
- *	0 USB OTG Internal PHY (UTMI)
- *	1 USB OTG External PHY (ULPI)
- */
-#define IMX25_IIM_BT_USB_SRC		(IIM_BANK(0) | IIM_BYTE(0xc) | IIM_BIT(0))
-
-/* NAND Flash Page Size.
- *	If BT_MEM_CTL = NAND Flash, then
- *		00 512 bytes
- *		01 2K bytes
- *		10 4K bytes
- *		11 Reserved
- */
-#define IMX25_IIM_BT_PAGE_SIZE		(IIM_BANK(0) | IIM_BYTE(0x10) | IIM_BIT(5) | IIM_WIDTH(2))
-
-/* Selects whether EEPROM device is used for load of configuration DCD data
- *	0 Use EEPROM DCD
- *	1 Do not use EEPROM DCD
- */
-#define IMX25_IIM_BT_EEPROM_CFG		(IIM_BANK(0) | IIM_BYTE(0x10) | IIM_BIT(4))
-
-/*  GPIO Boot Select. Determines whether certain boot fuse values are controlled from GPIO pins or IIM.
- *	0 The fuse values are determined by GPIO pins
- *	1 The fuse values are determined by fuses
- */
-#define IMX25_IIM_GPIO_BT_SEL		(IIM_BANK(0) | IIM_BYTE(0x10) | IIM_BIT(3))
-
-/* Security Type.
- *	001 Engineering (allows any code to be flashed and executed, even if does not have a valid signature)
- *	100 Security Disabled (forinternal/testing use)
- *	Others Production (Security On)
- */
-#define IMX25_IIM_HAB_TYPE		(IIM_BANK(0) | IIM_BYTE(0x10) | IIM_BIT(0) | IIM_WIDTH(3))
-
-/* Boot Memory Type.
- *	If BT_MEM_CTL = WEIM, then
- *		00 NOR
- *		01 Reserved
- *		10 OneNand
- *		11 Reserved
- *	If BT_MEM_CTL = NAND Flash
- *		00 3 address cycles
- *		01 4 address cycles
- *		10 5 address cycles
- *		11 Reserved
- *	If BT_MEM_CTL = Expansion Card Device
- *		00 SD/MMC/MoviNAND HDD
- *		01 Reserved
- *		10 Serial ROM via I2C
- *		11 Serial ROM via SPI
- */
-#define IMX25_IIM_BT_MEM_TYPE		(IIM_BANK(0) | IIM_BYTE(0x14) | IIM_BIT(5) | IIM_WIDTH(2))
-
-/* Bus IIM_WIDTH and muxed/unmuxed interface. Has a corresponding GPIO pin.
- *	If BT_MEM_CTL=NAND then
- *		00 8 IIM_BIT bus,
- *		01 16 IIM_BIT bus
- *		1x Reserved
- *	If BT_MEM_CTL=WEIM then
- *		00 16 IIM_BIT addr/data muxed
- *		01 16 IIM_BIT addr/data unmuxed
- *		1x Reserved
- *	If BT_MEM_CTL=SPI then
- *		00 2-addr word SPI (16-IIM_BIT)
- *		01 3-addr word SPI (24-IIM_BIT)
- *		1x Reserved
- */
-#define IMX25_IIM_BT_BUS_WIDTH		(IIM_BANK(0) | IIM_BYTE(0x14) | IIM_BIT(3) | IIM_WIDTH(2))
-
-/* Boot Memory Control Type. (memory device)
- *	00 WEIM
- *	01 NAND Flash
- *	10 ATA HDD
- *	11 Expansion Device
- *	(SD/MMC, support high storage, EEPROMs. See BT_MEM_TYPE[1:0] settings for details.
- */
-#define IMX25_IIM_BT_MEM_CTL		(IIM_BANK(0) | IIM_BYTE(0x14) | IIM_BIT(1) | IIM_WIDTH(2))
-
-/* Direct External Memory Boot Disable.
- *	0 Direct boot from external memory is allowed
- *	1 Direct boot from external memory is not allowed
- */
-#define IMX25_IIM_DIR_BT_DIS		(IIM_BANK(0) | IIM_BYTE(0x14) | IIM_BIT(0))
-
-/* HAB Customer Code. Select customer code as input to HAB. */
-#define IMX25_IIM_HAB_CUS		(IIM_BANK(0) | IIM_BYTE(0x18) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* Silicon revision number. 0 Rev1.0 1 Rev1.1 */
-#define IMX25_IIM_SI_REV		(IIM_BANK(0) | IIM_BYTE(0x1c) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* 64-IIM_BIT Unique ID. 0 <= n <= 7 */
-#define IMX25_IIM_UID(n)		(IIM_BANK(0) | IIM_BYTE(0x20 + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* LPB ARM core frequency. Has a corresponding GPIO pin.
- *	000 133 MHz (Default)
- *	001 24MHz
- *	010 55.33 MHz
- *	011 66 MHz
- *	100 83 MHz
- *	101 166 MHz
- *	110 266 MHz
- *	111 Normal boot frequency
- */
-#define IMX25_IIM_BT_LPB_FREQ		(IIM_BANK(0) | IIM_BYTE(0x44) | IIM_BIT(5) | IIM_WIDTH(3))
-
-/* Choosing the specific UART controller for booting from. */
-#define IMX25_IIM_BT_UART_SRC		(IIM_BANK(0) | IIM_BYTE(0x44) | IIM_BIT(2) | IIM_WIDTH(3))
-
-/* Options for Low Power Boot mode.
- *	00 LPB disabled
- *	01 Generic PMIC and one GPIO input (Low battery)
- *	10 Generic PMIC and two GPIO inputs (Low battery and Charger detect)
- *	11 Atlas AP Power Management IC.
- */
-#define IMX25_IIM_BT_LPB		(IIM_BANK(0) | IIM_BYTE(0x44) | IIM_BIT(0) | IIM_WIDTH(2))
-
-/* Application Processor Boot Image Version. */
-#define IMX25_IIM_AP_BI_VER_15_8	(IIM_BANK(0) | IIM_BYTE(0x48) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* Application Processor Boot Image Version. */
-#define IMX25_IIM_AP_BI_VER_7_0		(IIM_BANK(0) | IIM_BYTE(0x4c) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* Most significant IIM_BYTE of 256-IIM_BIT hash value of AP super root key (SRK0_HASH) */
-#define IMX25_IIM_SRK0_HASH_0		(IIM_BANK(0) | IIM_BYTE(0x50) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* For SPC statistics during production. */
-#define IMX25_IIM_STORE_COUNT		(IIM_BANK(0) | IIM_BYTE(0x54) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* Use for adjustment the compensator delays on silicon and the system works as a whole at 1.0V and 1.2V (DVFS) */
-#define IMX25_IIM_DVFS_DELAY_ADJUST	(IIM_BANK(0) | IIM_BYTE(0x58) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* PTC version control number. */
-#define IMX25_IIM_PTC_VER		(IIM_BANK(0) | IIM_BYTE(0x5c) | IIM_BIT(5) | IIM_WIDTH(3))
-
-#define IMX25_IIM_GDPTCV_VALID		(IIM_BANK(0) | IIM_BYTE(0x5c) | IIM_BIT(4))
-
-/* GP domain DPTC/SPC Test Voltage. */
-#define IMX25_IIM_GDPTCV		(IIM_BANK(0) | IIM_BYTE(0x5c) | IIM_BIT(0) | IIM_WIDTH(4))
-
-/* Voltage Reference Configuration. A field in DryIce Analog Configuration Register (DACR) */
-#define IMX25_IIM_VRC			(IIM_BANK(0) | IIM_BYTE(0x60) | IIM_BIT(5) | IIM_WIDTH(3))
-
-#define IMX25_IIM_LDPTCV_VALID		(IIM_BANK(0) | IIM_BYTE(0x60) | IIM_BIT(4))
-
-/* LP domain DPTC Test Voltage. */
-#define IMX25_IIM_LDPTCV		(IIM_BANK(0) | IIM_BYTE(0x60) | IIM_BIT(0) | IIM_WIDTH(4))
-
-/* Well Bias Charge Pump Frequency Adjust. Adjusting the frequency of the internal free-running oscillator. */
-#define IMX25_IIM_CPFA			(IIM_BANK(0) | IIM_BYTE(0x64) | IIM_BIT(4))
-
-/* Well Bias Charge Pump Set Point Adjustment. */
-#define IMX25_IIM_CPSPA			(IIM_BANK(0) | IIM_BYTE(0x64) | IIM_BIT(0) | IIM_WIDTH(4))
-
-/* Ethernet MAC Address, 0 <= n <= 5 */
-#define IMX25_IIM_MAC_ADDR(n)		(IIM_BANK(1) | IIM_BYTE(0x68 + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* Locking row 0058, fusebank 1 */
-#define IMX25_IIM_USR5_LOCK		(IIM_BANK(1) | IIM_BYTE(0) | IIM_BIT(4))
-
-/* Lock for rows 0078–007C of fusebank 1 */
-#define IMX25_IIM_USR6_LOCK		(IIM_BANK(1) | IIM_BYTE(0) | IIM_BIT(2))
-
-/* Locking 0008-0020, fusebank1 */
-#define IMX25_IIM_SJC_RESP_LOCK		(IIM_BANK(1) | IIM_BYTE(0) | IIM_BIT(1))
-
-/* Locking SCC_KEY[255:0] */
-#define IMX25_IIM_SCC_LOCK		(IIM_BANK(1) | IIM_BYTE(0) | IIM_BIT(0))
-
-/* SCC Secret Key, 0 <= n <= 20 */
-#define IMX25_IIM_SCC_KEY(n)		(IIM_BANK(1) | IIM_BYTE(0x4 + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* Fuses available for software/customers */
-#define IMX25_IIM_USR5			(IIM_BANK(1) | IIM_BYTE(0x58) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* Response reference value for the secure JTAG controller, 0 <= n <= 7 */
-#define IMX25_IIM_SJC_RESP(n)		(IIM_BANK(1) | IIM_BYTE(0x5c + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* Fuses available for software/customers. 0 <= n <= 1 */
-#define IMX25_IIM_USR6(n)		(IIM_BANK(1) | IIM_BYTE(0x78 + 0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8))
-
-/* Lock for SRK_HASH[255:160] fuses in row 0x0050, fusebank0 and in rows 0x0004-0x002C, fusebank3 */
-#define IMX25_IIM_SRK0_LOCK96		(IIM_BANK(2) | IIM_BYTE(0) | IIM_BIT(1))
-
-/* Lock for SRK0_HASH[159:0] fuses in rows 0x0030-0x007C */
-#define IMX25_IIM_SRK0_LOCK160		(IIM_BANK(2) | IIM_BYTE(0) | IIM_BIT(0))
-
-/* AP Super Root Key hash, bits [247:0].
- * Most significant IIM_BYTE SRK_HASH[255:248] is in the fuse bank #0, 0050
- * 1 <= n <= 31
- */
-#define IMX25_IIM_SRK0_HASH_1_31(n)	(IIM_BANK(2) | IIM_BYTE(0x4 * (n)) | IIM_BIT(0) | IIM_WIDTH(8))
-
-#endif /* __MACH_IMX25_FUSEMAP_H */
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
deleted file mode 100644
index d63669e1e0..0000000000
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */
-
-#ifndef __ASM_ARCH_MX25_REGS_H
-#define __ASM_ARCH_MX25_REGS_H
-
-#define MX25_AIPS1_BASE_ADDR		0x43f00000
-#define MX25_AIPS1_SIZE			SZ_1M
-#define MX25_AIPS2_BASE_ADDR		0x53f00000
-#define MX25_AIPS2_SIZE			SZ_1M
-#define MX25_AVIC_BASE_ADDR		0x68000000
-#define MX25_AVIC_SIZE			SZ_1M
-
-#define MX25_I2C1_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x80000)
-#define MX25_I2C3_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x84000)
-#define MX25_CAN1_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x88000)
-#define MX25_CAN2_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x8c000)
-#define MX25_I2C2_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x98000)
-#define MX25_CSPI1_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0xa4000)
-#define MX25_IOMUXC_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0xac000)
-
-#define MX25_CCM_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0x80000)
-#define MX25_GPT4_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0x84000)
-#define MX25_GPT3_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0x88000)
-#define MX25_GPT2_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0x8c000)
-#define MX25_GPT1_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0x90000)
-#define MX25_GPIO4_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0x9c000)
-#define MX25_PWM2_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xa0000)
-#define MX25_GPIO3_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xa4000)
-#define MX25_PWM3_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xa8000)
-#define MX25_PWM4_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xc8000)
-#define MX25_GPIO1_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xcc000)
-#define MX25_GPIO2_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xd0000)
-#define MX25_WDOG_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xdc000)
-#define MX25_PWM1_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0xe0000)
-
-#define MX25_UART1_BASE_ADDR		0x43f90000
-#define MX25_UART2_BASE_ADDR		0x43f94000
-#define MX25_AUDMUX_BASE_ADDR		0x43fb0000
-#define MX25_UART3_BASE_ADDR		0x5000c000
-#define MX25_UART4_BASE_ADDR		0x50008000
-#define MX25_UART5_BASE_ADDR		0x5002c000
-
-#define MX25_CSPI3_BASE_ADDR		0x50004000
-#define MX25_CSPI2_BASE_ADDR		0x50010000
-#define MX25_FEC_BASE_ADDR		0x50038000
-#define MX25_SSI2_BASE_ADDR		0x50014000
-#define MX25_SSI1_BASE_ADDR		0x50034000
-#define MX25_NFC_BASE_ADDR		0xbb000000
-#define MX25_SCC_BASE_ADDR		0x53fac000
-#define MX25_IIM_BASE_ADDR		0x53ff0000
-#define MX25_DRYICE_BASE_ADDR		0x53ffc000
-#define MX25_ESDHC1_BASE_ADDR		0x53fb4000
-#define MX25_ESDHC2_BASE_ADDR		0x53fb8000
-#define MX25_LCDC_BASE_ADDR		0x53fbc000
-#define MX25_KPP_BASE_ADDR		0x43fa8000
-#define MX25_RNGB_BASE_ADDR		0x53fb0000
-#define MX25_SDMA_BASE_ADDR		0x53fd4000
-#define MX25_USB_BASE_ADDR		0x53ff4000
-#define MX25_USB_OTG_BASE_ADDR			(MX25_USB_BASE_ADDR + 0x0000)
-/*
- * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
- * for the host controller.  Early documentation drafts specified 0x400 and
- * Freescale internal sources confirm only the latter value to work.
- */
-#define MX25_USB_HS_BASE_ADDR			(MX25_USB_BASE_ADDR + 0x0400)
-#define MX25_CSI_BASE_ADDR		0x53ff8000
-
-#define MX25_IRAM_BASE_ADDR		0x78000000	/* internal ram */
-#define MX25_IRAM_SIZE			SZ_128K
-
-/*
- * Clock Controller Module (CCM)
- */
-#define MX25_CCM_MPCTL	0x00
-#define MX25_CCM_UPCTL	0x04
-#define MX25_CCM_CCTL	0x08
-#define MX25_CCM_CGCR0	0x0C
-#define MX25_CCM_CGCR1	0x10
-#define MX25_CCM_CGCR2	0x14
-#define MX25_CCM_PCDR0	0x18
-#define MX25_CCM_PCDR1	0x1C
-#define MX25_CCM_PCDR2	0x20
-#define MX25_CCM_PCDR3	0x24
-#define MX25_CCM_RCSR	0x28
-#define MX25_CCM_CRDR	0x2C
-#define MX25_CCM_DCVR0	0x30
-#define MX25_CCM_DCVR1	0x34
-#define MX25_CCM_DCVR2	0x38
-#define MX25_CCM_DCVR3	0x3c
-#define MX25_CCM_LTR0	0x40
-#define MX25_CCM_LTR1	0x44
-#define MX25_CCM_LTR2	0x48
-#define MX25_CCM_LTR3	0x4c
-
-#define MX25_PDR0_AUTO_MUX_DIV(x)	(((x) & 0x7) << 9)
-#define MX25_PDR0_CCM_PER_AHB(x)	(((x) & 0x7) << 12)
-#define MX25_PDR0_CON_MUX_DIV(x)	(((x) & 0xf) << 16)
-#define MX25_PDR0_HSP_PODF(x)		(((x) & 0x3) << 20)
-#define MX25_PDR0_AUTO_CON		(1 << 0)
-#define MX25_PDR0_PER_SEL		(1 << 26)
-
-#define MX25_CCM_RCSR_MEM_CTRL_SHIFT		30
-#define MX25_CCM_RCSR_MEM_TYPE_SHIFT		28
-
-/*
- * Adresses and ranges of the external chip select lines
- */
-#define MX25_CS0_BASE_ADDR	0xA0000000
-#define MX25_CS0_SIZE		SZ_128M
-#define MX25_CS1_BASE_ADDR	0xA8000000
-#define MX25_CS1_SIZE		SZ_128M
-#define MX25_CS2_BASE_ADDR	0xB0000000
-#define MX25_CS2_SIZE		SZ_32M
-#define MX25_CS3_BASE_ADDR	0xB2000000
-#define MX25_CS3_SIZE		SZ_32M
-#define MX25_CS4_BASE_ADDR	0xB4000000
-#define MX25_CS4_SIZE		SZ_32M
-#define MX25_CS5_BASE_ADDR	0xB6000000
-#define MX25_CS5_SIZE		SZ_32M
-
-#define MX25_CSD0_BASE_ADDR  0x80000000
-#define MX25_CSD1_BASE_ADDR  0x90000000
-
-#define MX25_ESDCTL_BASE_ADDR	0xb8001000
-#define MX25_WEIM_BASE_ADDR	0xb8002000
-
-#endif /* __ASM_ARCH_MX25_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
deleted file mode 100644
index c45befb57c..0000000000
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ /dev/null
@@ -1,164 +0,0 @@
-#ifndef _IMX27_REGS_H
-#define _IMX27_REGS_H
-
-#define MX27_AIPI_BASE_ADDR		0x10000000
-#define MX27_AIPI_SIZE			SZ_1M
-#define MX27_DMA_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x01000)
-#define MX27_WDOG_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x02000)
-#define MX27_GPT1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x03000)
-#define MX27_GPT2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x04000)
-#define MX27_GPT3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x05000)
-#define MX27_PWM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x06000)
-#define MX27_RTC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x07000)
-#define MX27_KPP_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x08000)
-#define MX27_OWIRE_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x09000)
-#define MX27_UART1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0a000)
-#define MX27_UART2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0b000)
-#define MX27_UART3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0c000)
-#define MX27_UART4_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0d000)
-#define MX27_CSPI1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0e000)
-#define MX27_CSPI2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0f000)
-#define MX27_SSI1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x10000)
-#define MX27_SSI2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x11000)
-#define MX27_I2C1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x12000)
-#define MX27_SDHC1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x13000)
-#define MX27_SDHC2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x14000)
-#define MX27_GPIO_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x15000)
-#define MX27_GPIO1_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x000)
-#define MX27_GPIO2_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x100)
-#define MX27_GPIO3_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x200)
-#define MX27_GPIO4_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x300)
-#define MX27_GPIO5_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x400)
-#define MX27_GPIO6_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x500)
-#define MX27_AUDMUX_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x16000)
-#define MX27_CSPI3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x17000)
-#define MX27_MSHC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x18000)
-#define MX27_GPT4_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x19000)
-#define MX27_GPT5_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1a000)
-#define MX27_UART5_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1b000)
-#define MX27_UART6_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1c000)
-#define MX27_I2C2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1d000)
-#define MX27_SDHC3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1e000)
-#define MX27_GPT6_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1f000)
-#define MX27_LCDC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x21000)
-#define MX27_SLCDC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x22000)
-#define MX27_VPU_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x23000)
-#define MX27_USB_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x24000)
-#define MX27_USB_OTG_BASE_ADDR			(MX27_USB_BASE_ADDR + 0x0000)
-#define MX27_USB_HS1_BASE_ADDR			(MX27_USB_BASE_ADDR + 0x0200)
-#define MX27_USB_HS2_BASE_ADDR			(MX27_USB_BASE_ADDR + 0x0400)
-#define MX27_SAHARA_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x25000)
-#define MX27_EMMAPP_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x26000)
-#define MX27_EMMAPRP_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x26400)
-#define MX27_CCM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x27000)
-#define MX27_SYSCTRL_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x27800)
-#define MX27_IIM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x28000)
-#define MX27_RTIC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x2a000)
-#define MX27_FEC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x2b000)
-#define MX27_SCC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x2c000)
-#define MX27_ETB_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3b000)
-#define MX27_ETB_RAM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3c000)
-#define MX27_JAM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3e000)
-#define MX27_MAX_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX27_AVIC_BASE_ADDR		0x10040000
-
-/* ROM patch */
-#define MX27_ROMP_BASE_ADDR		0x10041000
-
-#define MX27_SAHB1_BASE_ADDR		0x80000000
-#define MX27_SAHB1_SIZE			SZ_1M
-#define MX27_CSI_BASE_ADDR			(MX27_SAHB1_BASE_ADDR + 0x0000)
-#define MX27_ATA_BASE_ADDR			(MX27_SAHB1_BASE_ADDR + 0x1000)
-
-/* Memory regions and CS */
-#define MX27_CSD0_BASE_ADDR		0xa0000000
-#define MX27_CSD1_BASE_ADDR		0xb0000000
-
-#define MX27_CS0_BASE_ADDR		0xc0000000
-#define MX27_CS1_BASE_ADDR		0xc8000000
-#define MX27_CS2_BASE_ADDR		0xd0000000
-#define MX27_CS3_BASE_ADDR		0xd2000000
-#define MX27_CS4_BASE_ADDR		0xd4000000
-#define MX27_CS5_BASE_ADDR		0xd6000000
-
-/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
-#define MX27_X_MEMC_BASE_ADDR		0xd8000000
-#define MX27_X_MEMC_SIZE		SZ_1M
-#define MX27_NFC_BASE_ADDR		(MX27_X_MEMC_BASE_ADDR)
-#define MX27_ESDCTL_BASE_ADDR		(MX27_X_MEMC_BASE_ADDR + 0x1000)
-#define MX27_WEIM_BASE_ADDR		(MX27_X_MEMC_BASE_ADDR + 0x2000)
-#define MX27_M3IF_BASE_ADDR		(MX27_X_MEMC_BASE_ADDR + 0x3000)
-#define MX27_PCMCIA_CTL_BASE_ADDR	(MX27_X_MEMC_BASE_ADDR + 0x4000)
-
-#define MX27_WEIM_CSCRx_BASE_ADDR(cs)	(MX27_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX27_WEIM_CSCRxU(cs)		(MX27_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX27_WEIM_CSCRxL(cs)		(MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX27_WEIM_CSCRxA(cs)		(MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX27_PCMCIA_MEM_BASE_ADDR	0xdc000000
-
-/* IRAM */
-#define MX27_IRAM_BASE_ADDR		0xffff4c00	/* internal ram */
-#define MX27_IRAM_SIZE			0x0000b400
-
-/* PCMCIA (base: MX27_PCMCIA_CTL_BASE_ADDR) */
-#define MX27_PCMCIA_PIPR	0x00
-#define MX27_PCMCIA_PSCR	0x04
-#define MX27_PCMCIA_PER		0x08
-#define MX27_PCMCIA_PBR(x)	(0x0c + ((x) << 2))
-#define MX27_PCMCIA_POR(x)	(0x28 + ((x) << 2))
-#define MX27_PCMCIA_POFR(x)	(0x44 + ((x) << 2))
-#define MX27_PCMCIA_PGCR	0x60
-#define MX27_PCMCIA_PGSR	0x64
-
-/* AIPI (base: MX27_AIPI_BASE_ADDR) */
-#define MX27_AIPI1_PSR0	0x00
-#define MX27_AIPI1_PSR1	0x04
-#define MX27_AIPI2_PSR0	(0x20000 + 0x00)
-#define MX27_AIPI2_PSR1	(0x20000 + 0x04)
-
-/* System Control (base: MX27_SYSCTRL_BASE_ADDR) */
-#define MX27_CID	0x0	/* Chip ID Register */
-#define MX27_FMCR	0x14	/* Function Multeplexing Control Register */
-#define MX27_GPCR	0x18	/* Global Peripheral Control Register */
-#define MX27_WBCR	0x1C	/* Well Bias Control Register */
-#define MX27_DSCR(x)	(0x1C + ((x) << 2))	/* Driving Strength Control Register 1 - 13 */
-
-/* PLL registers (base: MX27_CCM_BASE_ADDR) */
-#define MX27_CSCR	0x00 /* Clock Source Control Register       */
-#define MX27_MPCTL0	0x04 /* MCU PLL Control Register 0          */
-#define MX27_MPCTL1	0x08 /* MCU PLL Control Register 1          */
-#define MX27_SPCTL0	0x0c /* System PLL Control Register 0       */
-#define MX27_SPCTL1	0x10 /* System PLL Control Register 1       */
-#define MX27_OSC26MCTL	0x14 /* Oscillator 26M Register             */
-#define MX27_PCDR0	0x18 /* Peripheral Clock Divider Register 0 */
-#define MX27_PCDR1	0x1c /* Peripheral Clock Divider Register 1 */
-#define MX27_PCCR0	0x20 /* Peripheral Clock Control Register 0 */
-#define MX27_PCCR1	0x24 /* Peripheral Clock Control Register 1 */
-#define MX27_CCSR	0x28 /* Clock Control Status Register       */
-
-#define MX27_CSCR_MPEN		(1 << 0)
-#define MX27_CSCR_SPEN		(1 << 1)
-#define MX27_CSCR_FPM_EN	(1 << 2)
-#define MX27_CSCR_OSC26M_DIS	(1 << 3)
-#define MX27_CSCR_OSC26M_DIV1P5	(1 << 4)
-#define MX27_CSCR_AHB_DIV(d)	(((d) & 0x3) << 8)
-#define MX27_CSCR_ARM_DIV(d)	(((d) & 0x3) << 12)
-#define MX27_CSCR_ARM_SRC_MPLL	(1 << 15)
-#define MX27_CSCR_MCU_SEL	(1 << 16)
-#define MX27_CSCR_SP_SEL	(1 << 17)
-#define MX27_CSCR_MPLL_RESTART	(1 << 18)
-#define MX27_CSCR_SPLL_RESTART	(1 << 19)
-#define MX27_CSCR_MSHC_SEL	(1 << 20)
-#define MX27_CSCR_H264_SEL	(1 << 21)
-#define MX27_CSCR_SSI1_SEL	(1 << 22)
-#define MX27_CSCR_SSI2_SEL	(1 << 23)
-#define MX27_CSCR_SD_CNT(d)	(((d) & 0x3) << 24)
-#define MX27_CSCR_USB_DIV(d)	(((d) & 0x7) << 28)
-#define MX27_CSCR_UPDATE_DIS	(1 << 31)
-
-#define MX27_MPCTL1_BRMO	(1 << 6)
-#define MX27_MPCTL1_LF		(1 << 15)
-
-#endif /* _IMX27_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h
deleted file mode 100644
index 56c518c120..0000000000
--- a/arch/arm/mach-imx/include/mach/imx31-regs.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */
-
-#ifndef __ASM_ARCH_MX31_REGS_H
-#define __ASM_ARCH_MX31_REGS_H
-
-#include <linux/sizes.h>
-
-#define MX31_IRAM_BASE_ADDR		0x1fffc000
-#define MX31_IRAM_SIZE			0x00004000
-
-#define MX31_AIPS1_BASE_ADDR		0x43f00000
-#define MX31_AIPS1_SIZE			SZ_1M
-#define MX31_MAX_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x04000)
-#define MX31_EVTMON_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x08000)
-#define MX31_CLKCTL_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x0c000)
-#define MX31_ETB_SLOT4_BASE_ADDR		(MX31_AIPS1_BASE_ADDR + 0x10000)
-#define MX31_ETB_SLOT5_BASE_ADDR		(MX31_AIPS1_BASE_ADDR + 0x14000)
-#define MX31_ECT_CTIO_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x18000)
-#define MX31_I2C1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x80000)
-#define MX31_I2C3_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x84000)
-#define MX31_USB_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x88000)
-#define MX31_USB_OTG_BASE_ADDR			(MX31_USB_BASE_ADDR + 0x0000)
-#define MX31_USB_HS1_BASE_ADDR			(MX31_USB_BASE_ADDR + 0x0200)
-#define MX31_USB_HS2_BASE_ADDR			(MX31_USB_BASE_ADDR + 0x0400)
-#define MX31_ATA_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x8c000)
-#define MX31_UART1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x90000)
-#define MX31_UART2_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x94000)
-#define MX31_I2C2_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x98000)
-#define MX31_OWIRE_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x9c000)
-#define MX31_SSI1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xa0000)
-#define MX31_CSPI1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xa4000)
-#define MX31_KPP_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xa8000)
-#define MX31_IOMUXC_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xac000)
-#define MX31_UART4_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xb0000)
-#define MX31_UART5_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xb4000)
-#define MX31_ECT_IP1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xb8000)
-#define MX31_ECT_IP2_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0xbc000)
-
-#define MX31_SPBA0_BASE_ADDR		0x50000000
-#define MX31_SPBA0_SIZE			SZ_1M
-#define MX31_SDHC1_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x04000)
-#define MX31_SDHC2_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x08000)
-#define MX31_UART3_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x0c000)
-#define MX31_CSPI2_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x10000)
-#define MX31_SSI2_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x14000)
-#define MX31_SIM1_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x18000)
-#define MX31_IIM_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x1c000)
-#define MX31_ATA_DMA_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x20000)
-#define MX31_MSHC1_BASE_ADDR			(MX31_SPBA0_BASE_ADDR + 0x24000)
-#define MX31_SPBA_CTRL_BASE_ADDR		(MX31_SPBA0_BASE_ADDR + 0x3c000)
-
-#define MX31_AIPS2_BASE_ADDR		0x53f00000
-#define MX31_AIPS2_SIZE			SZ_1M
-#define MX31_CCM_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x80000)
-#define MX31_CSPI3_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x84000)
-#define MX31_FIRI_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x8c000)
-#define MX31_GPT1_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x90000)
-#define MX31_EPIT1_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x94000)
-#define MX31_EPIT2_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0x98000)
-#define MX31_GPIO3_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xa4000)
-#define MX31_SCC_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xac000)
-#define MX31_SCM_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xae000)
-#define MX31_SMN_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xaf000)
-#define MX31_RNGA_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xb0000)
-#define MX31_IPU_CTRL_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xc0000)
-#define MX31_AUDMUX_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xc4000)
-#define MX31_MPEG4_ENC_BASE_ADDR		(MX31_AIPS2_BASE_ADDR + 0xc8000)
-#define MX31_GPIO1_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xcc000)
-#define MX31_GPIO2_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xd0000)
-#define MX31_SDMA_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xd4000)
-#define MX31_RTC_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xd8000)
-#define MX31_WDOG_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xdc000)
-#define MX31_PWM_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xe0000)
-#define MX31_RTIC_BASE_ADDR			(MX31_AIPS2_BASE_ADDR + 0xec000)
-
-#define MX31_ROMP_BASE_ADDR		0x60000000
-#define MX31_ROMP_SIZE			SZ_1M
-
-#define MX31_AVIC_BASE_ADDR		0x68000000
-#define MX31_AVIC_SIZE			SZ_1M
-
-#define MX31_IPU_MEM_BASE_ADDR		0x70000000
-#define MX31_CSD0_BASE_ADDR		0x80000000
-#define MX31_CSD1_BASE_ADDR		0x90000000
-
-#define MX31_CS0_BASE_ADDR		0xa0000000
-#define MX31_CS0_SIZE			SZ_128M
-
-#define MX31_CS1_BASE_ADDR		0xa8000000
-#define MX31_CS1_SIZE			SZ_128M
-
-#define MX31_CS2_BASE_ADDR		0xb0000000
-#define MX31_CS2_SIZE			SZ_32M
-
-#define MX31_CS3_BASE_ADDR		0xb2000000
-#define MX31_CS3_SIZE			SZ_32M
-
-#define MX31_CS4_BASE_ADDR		0xb4000000
-#define MX31_CS4_SIZE			SZ_32M
-
-#define MX31_CS5_BASE_ADDR		0xb6000000
-#define MX31_CS5_SIZE			SZ_32M
-
-#define MX31_X_MEMC_BASE_ADDR		0xb8000000
-#define MX31_X_MEMC_SIZE		SZ_64K
-#define MX31_NFC_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x0000)
-#define MX31_ESDCTL_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x1000)
-#define MX31_WEIM_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x2000)
-#define MX31_M3IF_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x3000)
-#define MX31_EMI_CTL_BASE_ADDR			(MX31_X_MEMC_BASE_ADDR + 0x4000)
-#define MX31_PCMCIA_CTL_BASE_ADDR		MX31_EMI_CTL_BASE_ADDR
-
-#define MX31_WEIM_CSCRx_BASE_ADDR(cs)	(MX31_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX31_WEIM_CSCRxU(cs)			(MX31_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX31_WEIM_CSCRxL(cs)			(MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX31_WEIM_CSCRxA(cs)			(MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX31_PCMCIA_MEM_BASE_ADDR	0xbc000000
-
-/*
- * Clock Controller Module (CCM)
- */
-#define MX31_CCM_CCMR	0x00
-#define MX31_CCM_PDR0	0x04
-#define MX31_CCM_PDR1	0x08
-#define MX31_CCM_RCSR	0x0c
-#define MX31_CCM_MPCTL	0x10
-#define MX31_CCM_UPCTL	0x14
-#define MX31_CCM_SPCTL	0x18
-#define MX31_CCM_COSR	0x1C
-
-#define MX31_CCMR_MDS	(1 << 7)
-#define MX31_CCMR_SBYCS	(1 << 4)
-#define MX31_CCMR_MPE	(1 << 3)
-#define MX31_CCMR_PRCS_MASK	(3 << 1)
-#define MX31_CCMR_FPM	(1 << 1)
-#define MX31_CCMR_CKIH	(2 << 1)
-
-#define MX31_RCSR_NFMS	(1 << 30)
-
-#define MX31_PDR0_CSI_PODF(x)	(((x) & 0x1ff) << 23)
-#define MX31_PDR0_PER_PODF(x)	(((x) & 0x1f) << 16)
-#define MX31_PDR0_HSP_PODF(x)	(((x) & 0x7) << 11)
-#define MX31_PDR0_NFC_PODF(x)	(((x) & 0x7) << 8)
-#define MX31_PDR0_IPG_PODF(x)	(((x) & 0x3) << 6)
-#define MX31_PDR0_MAX_PODF(x)	(((x) & 0x7) << 3)
-#define MX31_PDR0_MCU_PODF(x)	((x) & 0x7)
-
-#define MX31_IOMUXC_GPR	(MX31_IOMUXC_BASE_ADDR + 0x8)
-#define MX31_IOMUXC_SW_MUX_CTL(x)	(MX31_IOMUXC_BASE_ADDR + 0xc + (x) * 4)
-#define MX31_IOMUXC_SW_PAD_CTL(x)	(MX31_IOMUXC_BASE_ADDR + 0x154 + (x) * 4)
-
-/*
- * Signal Multiplexing (IOMUX)
- */
-
-/* bits in the SW_MUX_CTL registers */
-#define MX31_MUX_CTL_OUT_GPIO_DR	(0 << 4)
-#define MX31_MUX_CTL_OUT_FUNC		(1 << 4)
-#define MX31_MUX_CTL_OUT_ALT1		(2 << 4)
-#define MX31_MUX_CTL_OUT_ALT2		(3 << 4)
-#define MX31_MUX_CTL_OUT_ALT3		(4 << 4)
-#define MX31_MUX_CTL_OUT_ALT4		(5 << 4)
-#define MX31_MUX_CTL_OUT_ALT5		(6 << 4)
-#define MX31_MUX_CTL_OUT_ALT6		(7 << 4)
-#define MX31_MUX_CTL_IN_NONE		(0 << 0)
-#define MX31_MUX_CTL_IN_GPIO		(1 << 0)
-#define MX31_MUX_CTL_IN_FUNC		(2 << 0)
-#define MX31_MUX_CTL_IN_ALT1		(4 << 0)
-#define MX31_MUX_CTL_IN_ALT2		(8 << 0)
-
-#define MX31_MUX_CTL_FUNC	(MX31_MUX_CTL_OUT_FUNC | MX31_MUX_CTL_IN_FUNC)
-#define MX31_MUX_CTL_ALT1	(MX31_MUX_CTL_OUT_ALT1 | MX31_MUX_CTL_IN_ALT1)
-#define MX31_MUX_CTL_ALT2	(MX31_MUX_CTL_OUT_ALT2 | MX31_MUX_CTL_IN_ALT2)
-#define MX31_MUX_CTL_GPIO	(MX31_MUX_CTL_OUT_GPIO_DR | MX31_MUX_CTL_IN_GPIO)
-
-#endif /* __ASM_ARCH_MX31_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
deleted file mode 100644
index 4a4aa754aa..0000000000
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */
-
-#ifndef __ASM_ARCH_MX35_REGS_H
-#define __ASM_ARCH_MX35_REGS_H
-
-#include <linux/sizes.h>
-
-#define MX35_IRAM_BASE_ADDR		0x10000000	/* internal ram */
-#define MX35_IRAM_SIZE			SZ_128K
-
-#define MX35_L2CC_BASE_ADDR		0x30000000
-#define MX35_L2CC_SIZE			SZ_1M
-
-#define MX35_AIPS1_BASE_ADDR		0x43f00000
-#define MX35_AIPS1_SIZE			SZ_1M
-#define MX35_MAX_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x04000)
-#define MX35_EVTMON_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x08000)
-#define MX35_CLKCTL_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x0c000)
-#define MX35_ETB_SLOT4_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x10000)
-#define MX35_ETB_SLOT5_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x14000)
-#define MX35_ECT_CTIO_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x80000)
-#define MX35_I2C3_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x84000)
-#define MX35_UART1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x90000)
-#define MX35_UART2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x94000)
-#define MX35_I2C2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x98000)
-#define MX35_OWIRE_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x9c000)
-#define MX35_SSI1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xa0000)
-#define MX35_CSPI1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xa4000)
-#define MX35_KPP_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xa8000)
-#define MX35_IOMUXC_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xac000)
-#define MX35_ECT_IP1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xb8000)
-#define MX35_ECT_IP2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0xbc000)
-
-#define MX35_SPBA0_BASE_ADDR		0x50000000
-#define MX35_SPBA0_SIZE			SZ_1M
-#define MX35_UART3_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x0c000)
-#define MX35_CSPI2_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x10000)
-#define MX35_SSI2_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x14000)
-#define MX35_ATA_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x20000)
-#define MX35_MSHC1_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x24000)
-#define MX35_FEC_BASE_ADDR		0x50038000
-#define MX35_SPBA_CTRL_BASE_ADDR		(MX35_SPBA0_BASE_ADDR + 0x3c000)
-
-#define MX35_AIPS2_BASE_ADDR		0x53f00000
-#define MX35_AIPS2_SIZE			SZ_1M
-#define MX35_CCM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x80000)
-#define MX35_GPT1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x90000)
-#define MX35_EPIT1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x94000)
-#define MX35_EPIT2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0x98000)
-#define MX35_GPIO3_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xa4000)
-#define MX35_SCC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xac000)
-#define MX35_RNGA_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb0000)
-#define MX35_ESDHC1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb4000)
-#define MX35_ESDHC2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb8000)
-#define MX35_ESDHC3_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xbc000)
-#define MX35_IPU_CTRL_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xc0000)
-#define MX35_AUDMUX_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xc4000)
-#define MX35_GPIO1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xcc000)
-#define MX35_GPIO2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xd0000)
-#define MX35_SDMA_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xd4000)
-#define MX35_RTC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xd8000)
-#define MX35_WDOG_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xdc000)
-#define MX35_PWM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe0000)
-#define MX35_CAN1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe4000)
-#define MX35_CAN2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe8000)
-#define MX35_RTIC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xec000)
-#define MX35_IIM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xf0000)
-#define MX35_USB_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xf4000)
-#define MX35_USB_OTG_BASE_ADDR			(MX35_USB_BASE_ADDR + 0x0000)
-
-/*
- * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
- * HS.  When host support was implemented only a preliminary document was
- * available, which told 0x400.  This works fine.
- */
-#define MX35_USB_HS_BASE_ADDR			(MX35_USB_BASE_ADDR + 0x0400)
-
-#define MX35_ROMP_BASE_ADDR		0x60000000
-#define MX35_ROMP_SIZE			SZ_1M
-
-#define MX35_AVIC_BASE_ADDR		0x68000000
-#define MX35_AVIC_SIZE			SZ_1M
-
-/*
- * Memory regions and CS
- */
-#define MX35_IPU_MEM_BASE_ADDR		0x70000000
-#define MX35_CSD0_BASE_ADDR		0x80000000
-#define MX35_CSD1_BASE_ADDR		0x90000000
-
-#define MX35_CS0_BASE_ADDR		0xa0000000
-#define MX35_CS1_BASE_ADDR		0xa8000000
-#define MX35_CS2_BASE_ADDR		0xb0000000
-#define MX35_CS3_BASE_ADDR		0xb2000000
-
-#define MX35_CS4_BASE_ADDR		0xb4000000
-#define MX35_CS4_SIZE			SZ_32M
-
-#define MX35_CS5_BASE_ADDR		0xb6000000
-#define MX35_CS5_SIZE			SZ_32M
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define MX35_X_MEMC_BASE_ADDR		0xb8000000
-#define MX35_X_MEMC_SIZE		SZ_64K
-#define MX35_ESDCTL_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x1000)
-#define MX35_WEIM_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x2000)
-#define MX35_M3IF_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x3000)
-#define MX35_EMI_CTL_BASE_ADDR			(MX35_X_MEMC_BASE_ADDR + 0x4000)
-#define MX35_PCMCIA_CTL_BASE_ADDR		MX35_EMI_CTL_BASE_ADDR
-
-#define MX35_NFC_BASE_ADDR		0xbb000000
-#define MX35_PCMCIA_MEM_BASE_ADDR	0xbc000000
-
-/*
- * Clock Controller Module (CCM)
- */
-#define MX35_CCM_CCMR	0x00
-#define MX35_CCM_PDR0	0x04
-#define MX35_CCM_PDR1	0x08
-#define MX35_CCM_PDR2	0x0C
-#define MX35_CCM_PDR3	0x10
-#define MX35_CCM_PDR4	0x14
-#define MX35_CCM_RCSR	0x18
-#define MX35_CCM_MPCTL	0x1C
-#define MX35_CCM_PPCTL	0x20
-#define MX35_CCM_ACMR	0x24
-#define MX35_CCM_COSR	0x28
-#define MX35_CCM_CGR0	0x2C
-#define MX35_CCM_CGR1	0x30
-#define MX35_CCM_CGR2	0x34
-#define MX35_CCM_CGR3	0x38
-
-#define MX35_CCM_CGR0_CSPI1_SHIFT	10
-#define MX35_CCM_CGR0_CSPI2_SHIFT	12
-#define MX35_CCM_CGR0_EPIT1_SHIFT	20
-#define MX35_CCM_CGR0_EPIT2_SHIFT	22
-#define MX35_CCM_CGR0_ESDHC1_SHIFT	26
-#define MX35_CCM_CGR0_ESDHC2_SHIFT	28
-#define MX35_CCM_CGR0_ESDHC3_SHIFT	30
-#define MX35_CCM_CGR1_FEC_SHIFT	0
-#define MX35_CCM_CGR1_GPIO1_SHIFT	2
-#define MX35_CCM_CGR1_GPIO2_SHIFT	4
-#define MX35_CCM_CGR1_GPIO3_SHIFT	6
-#define MX35_CCM_CGR1_I2C1_SHIFT	10
-#define MX35_CCM_CGR1_I2C2_SHIFT	12
-#define MX35_CCM_CGR1_I2C3_SHIFT	14
-#define MX35_CCM_CGR1_IOMUX_SHIFT	16
-#define MX35_CCM_CGR1_KPP_SHIFT	20
-#define MX35_CCM_CGR2_UART1_SHIFT	16
-#define MX35_CCM_CGR2_UART2_SHIFT	18
-#define MX35_CCM_CGR2_UART3_SHIFT	20
-#define MX35_CCM_CGR2_USB_SHIFT	22
-#define MX35_CCM_CGR2_WDOG_SHIFT	24
-
-#define MX35_CCM_RCSR_MEM_CTRL_SHIFT		25
-#define MX35_CCM_RCSR_MEM_TYPE_SHIFT		23
-
-#define MX35_PDR0_AUTO_MUX_DIV(x)	(((x) & 0x7) << 9)
-#define MX35_PDR0_CCM_PER_AHB(x)	(((x) & 0x7) << 12)
-#define MX35_PDR0_CON_MUX_DIV(x)	(((x) & 0xf) << 16)
-#define MX35_PDR0_HSP_PODF(x)		(((x) & 0x3) << 20)
-#define MX35_PDR0_AUTO_CON		(1 << 0)
-#define MX35_PDR0_PER_SEL		(1 << 26)
-
-#endif /* __ASM_ARCH_MX35_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx5.h b/arch/arm/mach-imx/include/mach/imx5.h
deleted file mode 100644
index dd5cfe99cf..0000000000
--- a/arch/arm/mach-imx/include/mach/imx5.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __MACH_MX5_H
-#define __MACH_MX5_H
-
-void imx50_init_lowlevel(unsigned int cpufreq_mhz);
-void imx51_init_lowlevel(unsigned int cpufreq_mhz);
-void imx53_init_lowlevel(unsigned int cpufreq_mhz);
-void imx53_init_lowlevel_early(unsigned int cpufreq_mhz);
-void imx5_init_lowlevel(void);
-
-void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn);
-
-#define imx5_setup_pll_1000(base)	imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
-#define imx5_setup_pll_864(base)	imx5_setup_pll((base),  864, (( 8 << 4) + ((1 - 1) << 0)), (180 - 1), 180)
-#define imx5_setup_pll_800(base)	imx5_setup_pll((base),  800, (( 8 << 4) + ((1 - 1) << 0)), (3 - 1), 1)
-#define imx5_setup_pll_665(base)	imx5_setup_pll((base),  665, (( 6 << 4) + ((1 - 1) << 0)), (96 - 1), 89)
-#define imx5_setup_pll_600(base)	imx5_setup_pll((base),  600, (( 6 << 4) + ((1 - 1) << 0)), ( 4 - 1),  1)
-#define imx5_setup_pll_455(base)	imx5_setup_pll((base),  455, (( 9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
-#define imx5_setup_pll_400(base)	imx5_setup_pll((base),  400, (( 8 << 4) + ((2 - 1) << 0)), (3 - 1), 1)
-#define imx5_setup_pll_216(base)	imx5_setup_pll((base),  216, (( 6 << 4) + ((3 - 1) << 0)), (4 - 1), 3)
-
-void imx51_babbage_power_init(void);
-
-#endif /* __MACH_MX53_H */
diff --git a/arch/arm/mach-imx/include/mach/imx50-regs.h b/arch/arm/mach-imx/include/mach/imx50-regs.h
deleted file mode 100644
index 97ac8e2dad..0000000000
--- a/arch/arm/mach-imx/include/mach/imx50-regs.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef __MACH_IMX50_REGS_H
-#define __MACH_IMX50_REGS_H
-
-#include <linux/sizes.h>
-
-#define MX50_IROM_BASE_ADDR	0x0
-
-#define MX50_IRAM_BASE_ADDR     0xF8000000
-#define MX50_IRAM_SIZE          SZ_128K
-
-/*
- * SPBA global module enabled #0
- */
-#define MX50_SPBA0_BASE_ADDR		0x50000000
-#define MX50_SPBA0_SIZE		SZ_1M
-
-#define MX50_ESDHC1_BASE_ADDR	(MX50_SPBA0_BASE_ADDR + 0x00004000)
-#define MX50_ESDHC2_BASE_ADDR	(MX50_SPBA0_BASE_ADDR + 0x00008000)
-#define MX50_UART3_BASE_ADDR		(MX50_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX50_ECSPI1_BASE_ADDR		(MX50_SPBA0_BASE_ADDR + 0x00010000)
-#define MX50_SSI2_BASE_ADDR		(MX50_SPBA0_BASE_ADDR + 0x00014000)
-#define MX50_ESDHC3_BASE_ADDR	(MX50_SPBA0_BASE_ADDR + 0x00020000)
-#define MX50_ESDHC4_BASE_ADDR	(MX50_SPBA0_BASE_ADDR + 0x00024000)
-#define MX50_SPBA_CTRL_BASE_ADDR	(MX50_SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define MX50_AIPS1_BASE_ADDR	0x53F00000
-#define MX50_AIPS1_SIZE		SZ_512K
-
-#define MX50_OTG_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00080000)
-#define MX50_GPIO1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00084000)
-#define MX50_GPIO2_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00088000)
-#define MX50_GPIO3_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX50_GPIO4_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00090000)
-#define MX50_KPP_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00094000)
-#define MX50_WDOG1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00098000)
-#define MX50_GPT1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX50_SRTC_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX50_IOMUXC_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX50_EPIT1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX50_PWM1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX50_PWM2_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX50_UART1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX50_UART2_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000C0000)
-
-#define MX50_SRC_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX50_CCM_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX50_GPC_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000D8000)
-#define MX50_GPIO5_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000DC000)
-#define MX50_GPIO6_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000E0000)
-#define MX50_I2C3_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000EC000)
-#define MX50_UART4_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000F0000)
-
-/*
- * AIPS 2
- */
-#define MX50_AIPS2_BASE_ADDR		0x63F00000
-#define MX50_AIPS2_SIZE			SZ_512K
-
-#define MX50_PLL1_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00080000)
-#define MX50_PLL2_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00084000)
-#define MX50_PLL3_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00088000)
-#define MX50_UART5_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00090000)
-#define MX50_AHBMAX_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00094000)
-#define MX50_ARM_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX50_OWIRE_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX50_ECSPI2_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX50_SDMA_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX50_ROMCP_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX50_CSPI_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX50_I2C2_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX50_I2C1_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX50_SSI1_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX50_AUDMUX_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX50_WEIM_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX50_FEC_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000EC000)
-
-/*
- * Memory regions and CS
- */
-#define MX50_CSD0_BASE_ADDR		0x70000000
-#define MX50_CSD1_BASE_ADDR		0xB0000000
-#define MX50_CS0_BASE_ADDR		0xF0000000
-#define MX50_CS1_32MB_BASE_ADDR		0xF2000000
-#define MX50_CS1_64MB_BASE_ADDR		0xF4000000
-#define MX50_CS2_64MB_BASE_ADDR		0xF4000000
-#define MX50_CS2_96MB_BASE_ADDR		0xF6000000
-#define MX50_CS3_BASE_ADDR		0xF6000000
-
-#endif /* __MACH_IMX50_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h
deleted file mode 100644
index b6685ce065..0000000000
--- a/arch/arm/mach-imx/include/mach/imx51-regs.h
+++ /dev/null
@@ -1,112 +0,0 @@
-#ifndef __MACH_IMX51_REGS_H
-#define __MACH_IMX51_REGS_H
-
-/* WEIM registers */
-#define WEIM_CSxGCR1(n)	(((n) * 0x18) + 0x00)
-#define WEIM_CSxGCR2(n)	(((n) * 0x18) + 0x04)
-#define WEIM_CSxRCR1(n)	(((n) * 0x18) + 0x08)
-#define WEIM_CSxRCR2(n)	(((n) * 0x18) + 0x0c)
-#define WEIM_CSxWCR1(n)	(((n) * 0x18) + 0x10)
-#define WEIM_WCR	0x90
-#define WEIM_WIAR	0x94
-#define WEIM_EAR	0x98
-
-#define MX51_IROM_BASE_ADDR	0x0
-
-#define MX51_IPU_BASE_ADDR	0x40000000
-
-/*
- * AIPS 1
- */
-#define MX51_AIPS1_BASE_ADDR 	0x73F00000
-
-#define MX51_OTG_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00080000)
-#define MX51_GPIO1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00084000)
-#define MX51_GPIO2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00088000)
-#define MX51_GPIO3_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX51_GPIO4_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00090000)
-#define MX51_KPP_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00094000)
-#define MX51_WDOG_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00098000)
-#define MX51_WDOG2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX51_GPT1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX51_SRTC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX51_IOMUXC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX51_EPIT1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX51_EPIT2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX51_PWM1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX51_PWM2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX51_UART1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX51_UART2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX51_SRC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX51_CCM_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX51_GPC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D8000)
-
-/*
- * AIPS 2
- */
-#define MX51_AIPS2_BASE_ADDR		0x83F00000
-
-#define MX51_PLL1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00080000)
-#define MX51_PLL2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00084000)
-#define MX51_PLL3_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00088000)
-#define MX51_AHBMAX_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00094000)
-#define MX51_IIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00098000)
-#define MX51_CSU_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX51_ARM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX51_FIRI_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX51_ECSPI2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX51_SDMA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX51_SCC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX51_ROMCP_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX51_RTIC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX51_CSPI_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX51_I2C2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX51_I2C1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX51_SSI1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX51_AUDMUX_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX51_M4IF_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX51_ESDCTL_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX51_WEIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX51_NFC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX51_EMI_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX51_MIPI_HSC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX51_ATA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E0000)
-#define MX51_SIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX51_SSI3_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX51_MXC_FEC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX51_TVE_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX51_VPU_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX51_SAHARA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F8000)
-
-#define MX51_SPBA0_BASE_ADDR    0x70000000
-#define MX51_MMC_SDHC1_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00004000)
-#define MX51_MMC_SDHC2_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00008000)
-#define MX51_UART3_BASE_ADDR 		(MX51_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX51_ECSPI1_BASE_ADDR 		(MX51_SPBA0_BASE_ADDR + 0x00010000)
-#define MX51_SSI2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00014000)
-#define MX51_MMC_SDHC3_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00020000)
-#define MX51_MMC_SDHC4_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00024000)
-#define MX51_SPDIF_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00028000)
-#define MX51_ATA_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00030000)
-#define MX51_SLIM_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00034000)
-#define MX51_HSI2C_DMA_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00038000)
-#define MX51_SPBA_CTRL_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x0003C000)
-
-#define MX51_NFC_AXI_BASE_ADDR	0xcfff0000
-
-/*
- * Memory regions and CS
- */
-#define MX51_GPU_CTRL_BASE_ADDR	0x30000000
-#define MX51_IPU_CTRL_BASE_ADDR	0x40000000
-#define MX51_CSD0_BASE_ADDR		0x90000000
-#define MX51_CSD1_BASE_ADDR		0xA0000000
-#define MX51_CS0_BASE_ADDR		0xB0000000
-#define MX51_CS1_BASE_ADDR		0xB8000000
-#define MX51_CS2_BASE_ADDR		0xC0000000
-#define MX51_CS3_BASE_ADDR		0xC8000000
-#define MX51_CS4_BASE_ADDR		0xCC000000
-#define MX51_CS5_BASE_ADDR		0xCE000000
-
-#endif /* __MACH_IMX51_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx53-regs.h b/arch/arm/mach-imx/include/mach/imx53-regs.h
deleted file mode 100644
index d45c94370d..0000000000
--- a/arch/arm/mach-imx/include/mach/imx53-regs.h
+++ /dev/null
@@ -1,124 +0,0 @@
-#ifndef __MACH_IMX53_REGS_H
-#define __MACH_IMX53_REGS_H
-
-#include <linux/sizes.h>
-
-#define MX53_IROM_BASE_ADDR	0x0
-
-#define MX53_IRAM_BASE_ADDR	0xF8000000
-#define MX53_IRAM_SIZE		SZ_128K
-
-#define MX53_SATA_BASE_ADDR	0x10000000
-
-#define MX53_IPU_BASE_ADDR	0x18000000
-/*
- * SPBA global module enabled #0
- */
-#define MX53_SPBA0_BASE_ADDR		0x50000000
-#define MX53_SPBA0_SIZE		SZ_1M
-
-#define MX53_ESDHC1_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00004000)
-#define MX53_ESDHC2_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00008000)
-#define MX53_UART3_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX53_ECSPI1_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x00010000)
-#define MX53_SSI2_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x00014000)
-#define MX53_ESDHC3_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00020000)
-#define MX53_ESDHC4_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00024000)
-#define MX53_SPDIF_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x00028000)
-#define MX53_ASRC_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x0002C000)
-#define MX53_ATA_DMA_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00030000)
-#define MX53_SLIM_DMA_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00034000)
-#define MX53_HSI2C_DMA_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00038000)
-#define MX53_SPBA_CTRL_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define MX53_AIPS1_BASE_ADDR 	0x53F00000
-#define MX53_AIPS1_SIZE		SZ_1M
-
-#define MX53_OTG_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00080000)
-#define MX53_GPIO1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00084000)
-#define MX53_GPIO2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00088000)
-#define MX53_GPIO3_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX53_GPIO4_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00090000)
-#define MX53_KPP_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00094000)
-#define MX53_WDOG1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00098000)
-#define MX53_WDOG2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX53_GPT1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX53_SRTC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX53_IOMUXC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX53_EPIT1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX53_EPIT2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX53_PWM1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX53_PWM2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX53_UART1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX53_UART2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX53_SRC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX53_CCM_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX53_GPC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000D8000)
-#define MX53_GPIO5_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000DC000)
-#define MX53_GPIO6_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000E0000)
-#define MX53_GPIO7_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000E4000)
-#define MX53_ATA_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000E8000)
-#define MX53_I2C3_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000EC000)
-#define MX53_UART4_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000F0000)
-
-/*
- * AIPS 2
- */
-#define MX53_AIPS2_BASE_ADDR		0x63F00000
-#define MX53_AIPS2_SIZE			SZ_1M
-
-#define MX53_PLL1_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00080000)
-#define MX53_PLL2_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00084000)
-#define MX53_PLL3_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00088000)
-#define MX53_PLL4_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x0008C000)
-#define MX53_UART5_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00090000)
-#define MX53_AHBMAX_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00094000)
-#define MX53_IIM_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00098000)
-#define MX53_CSU_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX53_ARM_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX53_OWIRE_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX53_FIRI_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX53_ECSPI2_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX53_SDMA_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX53_SCC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX53_ROMCP_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX53_RTIC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX53_CSPI_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX53_I2C2_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX53_I2C1_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX53_SSI1_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX53_AUDMUX_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX53_RTC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D4000)
-#define MX53_M4IF_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX53_ESDCTL_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX53_WEIM_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX53_NFC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX53_EMI_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX53_MIPI_HSC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX53_MLB_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX53_SSI3_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX53_FEC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX53_TVE_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX53_VPU_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX53_SAHARA_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000F8000)
-#define MX53_PTP_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000FC000)
-
-#define MX53_NFC_AXI_BASE_ADDR	0xF7FF0000
-
-/*
- * Memory regions and CS
- */
-#define MX53_CSD0_BASE_ADDR		0x70000000
-#define MX53_CSD1_BASE_ADDR		0xB0000000
-#define MX53_CS0_BASE_ADDR		0xF0000000
-#define MX53_CS1_32MB_BASE_ADDR		0xF2000000
-#define MX53_CS1_64MB_BASE_ADDR		0xF4000000
-#define MX53_CS2_64MB_BASE_ADDR		0xF4000000
-#define MX53_CS2_96MB_BASE_ADDR		0xF6000000
-#define MX53_CS3_BASE_ADDR		0xF6000000
-
-#endif /* __MACH_IMX53_REGS_H */
-
diff --git a/arch/arm/mach-imx/include/mach/imx6-anadig.h b/arch/arm/mach-imx/include/mach/imx6-anadig.h
deleted file mode 100644
index 38f4ad7351..0000000000
--- a/arch/arm/mach-imx/include/mach/imx6-anadig.h
+++ /dev/null
@@ -1,705 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2008-2011 Freescale Semiconductor, Inc. */
-
-/* Freescale ANADIG Register Definitions */
-
-#ifndef __ARCH_ARM___ANADIG_H
-#define __ARCH_ARM___ANADIG_H
-
-#define HW_ANADIG_PLL_SYS	(0x00000000)
-#define HW_ANADIG_PLL_SYS_SET	(0x00000004)
-#define HW_ANADIG_PLL_SYS_CLR	(0x00000008)
-#define HW_ANADIG_PLL_SYS_TOG	(0x0000000c)
-
-#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
-#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
-#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
-#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
-#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
-#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC      14
-#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M  0x0
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR      0x3
-#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
-#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_SYS_DIV_SELECT      0
-#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
-#define BF_ANADIG_PLL_SYS_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
-
-#define HW_ANADIG_USB1_PLL_480_CTRL	(0x00000010)
-#define HW_ANADIG_USB1_PLL_480_CTRL_SET	(0x00000014)
-#define HW_ANADIG_USB1_PLL_480_CTRL_CLR	(0x00000018)
-#define HW_ANADIG_USB1_PLL_480_CTRL_TOG	(0x0000001c)
-
-#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
-#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC      14
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
-#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
-#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
-#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
-#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
-#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0      2
-#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
-#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)  (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT      0
-#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
-#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
-
-#define HW_ANADIG_USB2_PLL_480_CTRL	(0x00000020)
-#define HW_ANADIG_USB2_PLL_480_CTRL_SET	(0x00000024)
-#define HW_ANADIG_USB2_PLL_480_CTRL_CLR	(0x00000028)
-#define HW_ANADIG_USB2_PLL_480_CTRL_TOG	(0x0000002c)
-
-#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK 0x80000000
-#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
-#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC      14
-#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
-#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
-#define BM_ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
-#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP 0x00000400
-#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP 0x00000200
-#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF 0x00000100
-#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF 0x00000080
-#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
-#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0      2
-#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 0x0000001C
-#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v)  (((v) << 2) & BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT      0
-#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0x00000003
-#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
-
-#define HW_ANADIG_PLL_528	(0x00000030)
-#define HW_ANADIG_PLL_528_SET	(0x00000034)
-#define HW_ANADIG_PLL_528_CLR	(0x00000038)
-#define HW_ANADIG_PLL_528_TOG	(0x0000003c)
-
-#define BM_ANADIG_PLL_528_LOCK 0x80000000
-#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_528_BYPASS 0x00010000
-#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC      14
-#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M  0x0
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR      0x3
-#define BM_ANADIG_PLL_528_ENABLE 0x00002000
-#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
-#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
-
-#define HW_ANADIG_PLL_528_SS	(0x00000040)
-
-#define BP_ANADIG_PLL_528_SS_STOP      16
-#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
-#define BF_ANADIG_PLL_528_SS_STOP(v) (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
-#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
-#define BP_ANADIG_PLL_528_SS_STEP      0
-#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
-#define BF_ANADIG_PLL_528_SS_STEP(v)  (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
-
-#define HW_ANADIG_PLL_528_NUM	(0x00000050)
-
-#define BP_ANADIG_PLL_528_NUM_A      0
-#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_528_NUM_A(v)  (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
-
-#define HW_ANADIG_PLL_528_DENOM	(0x00000060)
-
-#define BP_ANADIG_PLL_528_DENOM_B      0
-#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_528_DENOM_B(v)  (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
-
-#define HW_ANADIG_PLL_AUDIO	(0x00000070)
-#define HW_ANADIG_PLL_AUDIO_SET	(0x00000074)
-#define HW_ANADIG_PLL_AUDIO_CLR	(0x00000078)
-#define HW_ANADIG_PLL_AUDIO_TOG	(0x0000007c)
-
-#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
-#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT      19
-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)  (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
-#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC      14
-#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M  0x0
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR      0x3
-#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
-#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_AUDIO_DIV_SELECT      0
-#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
-#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
-
-#define HW_ANADIG_PLL_AUDIO_NUM	(0x00000080)
-
-#define BP_ANADIG_PLL_AUDIO_NUM_A      0
-#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_NUM_A(v)  (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
-
-#define HW_ANADIG_PLL_AUDIO_DENOM	(0x00000090)
-
-#define BP_ANADIG_PLL_AUDIO_DENOM_B      0
-#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)  (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
-
-#define HW_ANADIG_PLL_VIDEO	(0x000000a0)
-#define HW_ANADIG_PLL_VIDEO_SET	(0x000000a4)
-#define HW_ANADIG_PLL_VIDEO_CLR	(0x000000a8)
-#define HW_ANADIG_PLL_VIDEO_TOG	(0x000000ac)
-
-#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
-#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT      19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)  (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
-#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC      14
-#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M  0x0
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR      0x3
-#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
-#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_VIDEO_DIV_SELECT      0
-#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
-#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
-
-#define HW_ANADIG_PLL_VIDEO_NUM	(0x000000b0)
-
-#define BP_ANADIG_PLL_VIDEO_NUM_A      0
-#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_VIDEO_NUM_A(v)  (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
-
-#define HW_ANADIG_PLL_VIDEO_DENOM	(0x000000c0)
-
-#define BP_ANADIG_PLL_VIDEO_DENOM_B      0
-#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)  (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
-
-#define HW_ANADIG_PLL_MLB	(0x000000d0)
-#define HW_ANADIG_PLL_MLB_SET	(0x000000d4)
-#define HW_ANADIG_PLL_MLB_CLR	(0x000000d8)
-#define HW_ANADIG_PLL_MLB_TOG	(0x000000dc)
-
-#define BM_ANADIG_PLL_MLB_LOCK 0x80000000
-#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_SEL      26
-#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL 0x1C000000
-#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_SEL(v)  (((v) << 26) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL)
-#define BP_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG      23
-#define BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG 0x03800000
-#define BF_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG(v)  (((v) << 23) & BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG)
-#define BP_ANADIG_PLL_MLB_VDDD_DELAY_CFG      20
-#define BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG 0x00700000
-#define BF_ANADIG_PLL_MLB_VDDD_DELAY_CFG(v)  (((v) << 20) & BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG)
-#define BP_ANADIG_PLL_MLB_VDDA_DELAY_CFG      17
-#define BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG 0x000E0000
-#define BF_ANADIG_PLL_MLB_VDDA_DELAY_CFG(v)  (((v) << 17) & BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG)
-#define BM_ANADIG_PLL_MLB_BYPASS 0x00010000
-#define BP_ANADIG_PLL_MLB_PHASE_SEL      12
-#define BM_ANADIG_PLL_MLB_PHASE_SEL 0x00003000
-#define BF_ANADIG_PLL_MLB_PHASE_SEL(v)  (((v) << 12) & BM_ANADIG_PLL_MLB_PHASE_SEL)
-#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_MLB_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_MLB_HALF_CP 0x00000200
-
-#define HW_ANADIG_PLL_ENET	(0x000000e0)
-#define HW_ANADIG_PLL_ENET_SET	(0x000000e4)
-#define HW_ANADIG_PLL_ENET_CLR	(0x000000e8)
-#define HW_ANADIG_PLL_ENET_TOG	(0x000000ec)
-
-#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
-#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
-#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
-#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
-#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC      14
-#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)  (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M  0x0
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR      0x3
-#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
-#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_ENET_DIV_SELECT      0
-#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
-#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
-
-#define HW_ANADIG_PFD_480	(0x000000f0)
-#define HW_ANADIG_PFD_480_SET	(0x000000f4)
-#define HW_ANADIG_PFD_480_CLR	(0x000000f8)
-#define HW_ANADIG_PFD_480_TOG	(0x000000fc)
-
-#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
-#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
-#define BP_ANADIG_PFD_480_PFD3_FRAC      24
-#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
-#define BF_ANADIG_PFD_480_PFD3_FRAC(v)  (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
-#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
-#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
-#define BP_ANADIG_PFD_480_PFD2_FRAC      16
-#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
-#define BF_ANADIG_PFD_480_PFD2_FRAC(v)  (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
-#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
-#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
-#define BP_ANADIG_PFD_480_PFD1_FRAC      8
-#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
-#define BF_ANADIG_PFD_480_PFD1_FRAC(v)  (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
-#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
-#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
-#define BP_ANADIG_PFD_480_PFD0_FRAC      0
-#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
-#define BF_ANADIG_PFD_480_PFD0_FRAC(v)  (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
-
-#define HW_ANADIG_PFD_528	(0x00000100)
-#define HW_ANADIG_PFD_528_SET	(0x00000104)
-#define HW_ANADIG_PFD_528_CLR	(0x00000108)
-#define HW_ANADIG_PFD_528_TOG	(0x0000010c)
-
-#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
-#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
-#define BP_ANADIG_PFD_528_PFD3_FRAC      24
-#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
-#define BF_ANADIG_PFD_528_PFD3_FRAC(v)  (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
-#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
-#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
-#define BP_ANADIG_PFD_528_PFD2_FRAC      16
-#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
-#define BF_ANADIG_PFD_528_PFD2_FRAC(v)  (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
-#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
-#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
-#define BP_ANADIG_PFD_528_PFD1_FRAC      8
-#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
-#define BF_ANADIG_PFD_528_PFD1_FRAC(v)  (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
-#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
-#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
-#define BP_ANADIG_PFD_528_PFD0_FRAC      0
-#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
-#define BF_ANADIG_PFD_528_PFD0_FRAC(v)  (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
-
-#define HW_ANADIG_REG_1P1	(0x00000110)
-#define HW_ANADIG_REG_1P1_SET	(0x00000114)
-#define HW_ANADIG_REG_1P1_CLR	(0x00000118)
-#define HW_ANADIG_REG_1P1_TOG	(0x0000011c)
-
-#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000
-#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000
-#define BP_ANADIG_REG_1P1_OUTPUT_TRG      8
-#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x00001F00
-#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v)  (((v) << 8) & BM_ANADIG_REG_1P1_OUTPUT_TRG)
-#define BP_ANADIG_REG_1P1_BO_OFFSET      4
-#define BM_ANADIG_REG_1P1_BO_OFFSET 0x00000070
-#define BF_ANADIG_REG_1P1_BO_OFFSET(v)  (((v) << 4) & BM_ANADIG_REG_1P1_BO_OFFSET)
-#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008
-#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004
-#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002
-#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001
-
-#define HW_ANADIG_REG_3P0	(0x00000120)
-#define HW_ANADIG_REG_3P0_SET	(0x00000124)
-#define HW_ANADIG_REG_3P0_CLR	(0x00000128)
-#define HW_ANADIG_REG_3P0_TOG	(0x0000012c)
-
-#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000
-#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000
-#define BP_ANADIG_REG_3P0_OUTPUT_TRG      8
-#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x00001F00
-#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v)  (((v) << 8) & BM_ANADIG_REG_3P0_OUTPUT_TRG)
-#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080
-#define BP_ANADIG_REG_3P0_BO_OFFSET      4
-#define BM_ANADIG_REG_3P0_BO_OFFSET 0x00000070
-#define BF_ANADIG_REG_3P0_BO_OFFSET(v)  (((v) << 4) & BM_ANADIG_REG_3P0_BO_OFFSET)
-#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004
-#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002
-#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001
-
-#define HW_ANADIG_REG_2P5	(0x00000130)
-#define HW_ANADIG_REG_2P5_SET	(0x00000134)
-#define HW_ANADIG_REG_2P5_CLR	(0x00000138)
-#define HW_ANADIG_REG_2P5_TOG	(0x0000013c)
-
-#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000
-#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000
-#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000
-#define BP_ANADIG_REG_2P5_OUTPUT_TRG      8
-#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x00001F00
-#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v)  (((v) << 8) & BM_ANADIG_REG_2P5_OUTPUT_TRG)
-#define BP_ANADIG_REG_2P5_BO_OFFSET      4
-#define BM_ANADIG_REG_2P5_BO_OFFSET 0x00000070
-#define BF_ANADIG_REG_2P5_BO_OFFSET(v)  (((v) << 4) & BM_ANADIG_REG_2P5_BO_OFFSET)
-#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008
-#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004
-#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002
-#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001
-
-#define HW_ANADIG_REG_CORE	(0x00000140)
-#define HW_ANADIG_REG_CORE_SET	(0x00000144)
-#define HW_ANADIG_REG_CORE_CLR	(0x00000148)
-#define HW_ANADIG_REG_CORE_TOG	(0x0000014c)
-
-#define BM_ANADIG_REG_CORE_REF_SHIFT 0x80000000
-#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
-#define BP_ANADIG_REG_CORE_RAMP_RATE      27
-#define BM_ANADIG_REG_CORE_RAMP_RATE 0x18000000
-#define BF_ANADIG_REG_CORE_RAMP_RATE(v)  (((v) << 27) & BM_ANADIG_REG_CORE_RAMP_RATE)
-#define BP_ANADIG_REG_CORE_REG2_ADJ      23
-#define BM_ANADIG_REG_CORE_REG2_ADJ 0x07800000
-#define BF_ANADIG_REG_CORE_REG2_ADJ(v)  (((v) << 23) & BM_ANADIG_REG_CORE_REG2_ADJ)
-#define BP_ANADIG_REG_CORE_REG2_TRG      18
-#define BM_ANADIG_REG_CORE_REG2_TRG 0x007C0000
-#define BF_ANADIG_REG_CORE_REG2_TRG(v)  (((v) << 18) & BM_ANADIG_REG_CORE_REG2_TRG)
-#define BP_ANADIG_REG_CORE_REG1_ADJ      14
-#define BM_ANADIG_REG_CORE_REG1_ADJ 0x0003C000
-#define BF_ANADIG_REG_CORE_REG1_ADJ(v)  (((v) << 14) & BM_ANADIG_REG_CORE_REG1_ADJ)
-#define BP_ANADIG_REG_CORE_REG1_TRG      9
-#define BM_ANADIG_REG_CORE_REG1_TRG 0x00003E00
-#define BF_ANADIG_REG_CORE_REG1_TRG(v)  (((v) << 9) & BM_ANADIG_REG_CORE_REG1_TRG)
-#define BP_ANADIG_REG_CORE_REG0_ADJ      5
-#define BM_ANADIG_REG_CORE_REG0_ADJ 0x000001E0
-#define BF_ANADIG_REG_CORE_REG0_ADJ(v)  (((v) << 5) & BM_ANADIG_REG_CORE_REG0_ADJ)
-#define BP_ANADIG_REG_CORE_REG0_TRG      0
-#define BM_ANADIG_REG_CORE_REG0_TRG 0x0000001F
-#define BF_ANADIG_REG_CORE_REG0_TRG(v)  (((v) << 0) & BM_ANADIG_REG_CORE_REG0_TRG)
-
-#define HW_ANADIG_ANA_MISC0	(0x00000150)
-#define HW_ANADIG_ANA_MISC0_SET	(0x00000154)
-#define HW_ANADIG_ANA_MISC0_CLR	(0x00000158)
-#define HW_ANADIG_ANA_MISC0_TOG	(0x0000015c)
-
-#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY      26
-#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000
-#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v)  (((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
-#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000
-#define BP_ANADIG_ANA_MISC0_ANAMUX      21
-#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000
-#define BF_ANADIG_ANA_MISC0_ANAMUX(v)  (((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX)
-#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000
-#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH      18
-#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000
-#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v)  (((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
-#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000
-#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000
-#define BP_ANADIG_ANA_MISC0_OSC_I      14
-#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000
-#define BF_ANADIG_ANA_MISC0_OSC_I(v)  (((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I)
-#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN 0x00002000
-#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000
-#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST      8
-#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300
-#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v)  (((v) << 8) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
-#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080
-#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ      4
-#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x00000070
-#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v)  (((v) << 4) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
-#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
-#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004
-#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002
-#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001
-
-#define HW_ANADIG_ANA_MISC1	(0x00000160)
-#define HW_ANADIG_ANA_MISC1_SET	(0x00000164)
-#define HW_ANADIG_ANA_MISC1_CLR	(0x00000168)
-#define HW_ANADIG_ANA_MISC1_TOG	(0x0000016c)
-
-#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO 0x80000000
-#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000
-#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000
-#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN 0x00002000
-#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000
-#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN 0x00000800
-#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400
-#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL      5
-#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0
-#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v)  (((v) << 5) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
-#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL      0
-#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F
-#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v)  (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
-
-#define HW_ANADIG_ANA_MISC2	(0x00000170)
-#define HW_ANADIG_ANA_MISC2_SET	(0x00000174)
-#define HW_ANADIG_ANA_MISC2_CLR	(0x00000178)
-#define HW_ANADIG_ANA_MISC2_TOG	(0x0000017c)
-
-#define BP_ANADIG_ANA_MISC2_CONTROL3      30
-#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000
-#define BF_ANADIG_ANA_MISC2_CONTROL3(v) (((v) << 30) & BM_ANADIG_ANA_MISC2_CONTROL3)
-#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME      28
-#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000
-#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v)  (((v) << 28) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
-#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME      26
-#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000
-#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v)  (((v) << 26) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
-#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME      24
-#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000
-#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v)  (((v) << 24) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
-#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000
-#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000
-#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO 0x00200000
-#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS 0x00080000
-#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET      16
-#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000
-#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v)  (((v) << 16) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
-#define BM_ANADIG_ANA_MISC2_CONTROL1 0x00008000
-#define BM_ANADIG_ANA_MISC2_REG1_OK 0x00004000
-#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO 0x00002000
-#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS 0x00000800
-#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET      8
-#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700
-#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v)  (((v) << 8) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
-#define BM_ANADIG_ANA_MISC2_CONTROL0 0x00000080
-#define BM_ANADIG_ANA_MISC2_REG0_OK 0x00000040
-#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO 0x00000020
-#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS 0x00000008
-#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET      0
-#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0x00000007
-#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v)  (((v) << 0) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
-
-#define HW_ANADIG_TEMPSENSE0	(0x00000180)
-#define HW_ANADIG_TEMPSENSE0_SET	(0x00000184)
-#define HW_ANADIG_TEMPSENSE0_CLR	(0x00000188)
-#define HW_ANADIG_TEMPSENSE0_TOG	(0x0000018c)
-
-#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE      20
-#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000
-#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) (((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
-#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE      8
-#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00
-#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v)  (((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
-#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040
-#define BP_ANADIG_TEMPSENSE0_VBGADJ      3
-#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038
-#define BF_ANADIG_TEMPSENSE0_VBGADJ(v)  (((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ)
-#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004
-#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002
-#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001
-
-#define HW_ANADIG_TEMPSENSE1	(0x00000190)
-#define HW_ANADIG_TEMPSENSE1_SET	(0x00000194)
-#define HW_ANADIG_TEMPSENSE1_CLR	(0x00000198)
-#define HW_ANADIG_TEMPSENSE1_TOG	(0x0000019c)
-
-#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ      0
-#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF
-#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v)  (((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
-
-#define HW_ANADIG_USB1_VBUS_DETECT	(0x000001a0)
-#define HW_ANADIG_USB1_VBUS_DETECT_SET	(0x000001a4)
-#define HW_ANADIG_USB1_VBUS_DETECT_CLR	(0x000001a8)
-#define HW_ANADIG_USB1_VBUS_DETECT_TOG	(0x000001ac)
-
-#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000
-#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000
-#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000
-#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000
-#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000
-#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000
-#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080
-#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040
-#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020
-#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010
-#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008
-#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH      0
-#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007
-#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v)  (((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH)
-
-#define HW_ANADIG_USB1_CHRG_DETECT	(0x000001b0)
-#define HW_ANADIG_USB1_CHRG_DETECT_SET	(0x000001b4)
-#define HW_ANADIG_USB1_CHRG_DETECT_CLR	(0x000001b8)
-#define HW_ANADIG_USB1_CHRG_DETECT_TOG	(0x000001bc)
-
-#define BM_ANADIG_USB1_CHRG_DETECT_BGR_BIAS 0x00800000
-#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000
-#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000
-#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000
-#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001
-
-#define HW_ANADIG_USB1_VBUS_DET_STAT	(0x000001c0)
-#define HW_ANADIG_USB1_VBUS_DET_STAT_SET	(0x000001c4)
-#define HW_ANADIG_USB1_VBUS_DET_STAT_CLR	(0x000001c8)
-#define HW_ANADIG_USB1_VBUS_DET_STAT_TOG	(0x000001cc)
-
-#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008
-#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004
-#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002
-#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001
-
-#define HW_ANADIG_USB1_CHRG_DET_STAT	(0x000001d0)
-#define HW_ANADIG_USB1_CHRG_DET_STAT_SET	(0x000001d4)
-#define HW_ANADIG_USB1_CHRG_DET_STAT_CLR	(0x000001d8)
-#define HW_ANADIG_USB1_CHRG_DET_STAT_TOG	(0x000001dc)
-
-#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008
-#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004
-#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
-#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001
-
-#define HW_ANADIG_USB1_LOOPBACK	(0x000001e0)
-#define HW_ANADIG_USB1_LOOPBACK_SET	(0x000001e4)
-#define HW_ANADIG_USB1_LOOPBACK_CLR	(0x000001e8)
-#define HW_ANADIG_USB1_LOOPBACK_TOG	(0x000001ec)
-
-#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100
-#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080
-#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040
-#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020
-#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010
-#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008
-#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004
-#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002
-#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001
-
-#define HW_ANADIG_USB1_MISC	(0x000001f0)
-#define HW_ANADIG_USB1_MISC_SET	(0x000001f4)
-#define HW_ANADIG_USB1_MISC_CLR	(0x000001f8)
-#define HW_ANADIG_USB1_MISC_TOG	(0x000001fc)
-
-#define BM_ANADIG_USB1_MISC_EN_CLK_UTMI 0x40000000
-#define BM_ANADIG_USB1_MISC_RX_VPIN_FS 0x20000000
-#define BM_ANADIG_USB1_MISC_RX_VMIN_FS 0x10000000
-#define BM_ANADIG_USB1_MISC_RX_RXD_FS 0x08000000
-#define BM_ANADIG_USB1_MISC_RX_SQUELCH 0x04000000
-#define BM_ANADIG_USB1_MISC_RX_DISCON_DET 0x02000000
-#define BM_ANADIG_USB1_MISC_RX_HS_DATA 0x01000000
-#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002
-#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001
-
-#define HW_ANADIG_USB2_VBUS_DETECT	(0x00000200)
-#define HW_ANADIG_USB2_VBUS_DETECT_SET	(0x00000204)
-#define HW_ANADIG_USB2_VBUS_DETECT_CLR	(0x00000208)
-#define HW_ANADIG_USB2_VBUS_DETECT_TOG	(0x0000020c)
-
-#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000
-#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000
-#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000
-#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000
-#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000
-#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000
-#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH      0
-#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007
-#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v)  (((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH)
-
-#define HW_ANADIG_USB2_CHRG_DETECT	(0x00000210)
-#define HW_ANADIG_USB2_CHRG_DETECT_SET	(0x00000214)
-#define HW_ANADIG_USB2_CHRG_DETECT_CLR	(0x00000218)
-#define HW_ANADIG_USB2_CHRG_DETECT_TOG	(0x0000021c)
-
-#define BM_ANADIG_USB2_CHRG_DETECT_BGR_BIAS 0x00800000
-#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
-#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
-#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000
-#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001
-
-#define HW_ANADIG_USB2_VBUS_DET_STAT	(0x00000220)
-#define HW_ANADIG_USB2_VBUS_DET_STAT_SET	(0x00000224)
-#define HW_ANADIG_USB2_VBUS_DET_STAT_CLR	(0x00000228)
-#define HW_ANADIG_USB2_VBUS_DET_STAT_TOG	(0x0000022c)
-
-#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008
-#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004
-#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002
-#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001
-
-#define HW_ANADIG_USB2_CHRG_DET_STAT	(0x00000230)
-#define HW_ANADIG_USB2_CHRG_DET_STAT_SET	(0x00000234)
-#define HW_ANADIG_USB2_CHRG_DET_STAT_CLR	(0x00000238)
-#define HW_ANADIG_USB2_CHRG_DET_STAT_TOG	(0x0000023c)
-
-#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008
-#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004
-#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
-#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001
-
-#define HW_ANADIG_USB2_LOOPBACK	(0x00000240)
-#define HW_ANADIG_USB2_LOOPBACK_SET	(0x00000244)
-#define HW_ANADIG_USB2_LOOPBACK_CLR	(0x00000248)
-#define HW_ANADIG_USB2_LOOPBACK_TOG	(0x0000024c)
-
-#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100
-#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080
-#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040
-#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020
-#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010
-#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008
-#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004
-#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002
-#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001
-
-#define HW_ANADIG_USB2_MISC	(0x00000250)
-#define HW_ANADIG_USB2_MISC_SET	(0x00000254)
-#define HW_ANADIG_USB2_MISC_CLR	(0x00000258)
-#define HW_ANADIG_USB2_MISC_TOG	(0x0000025c)
-
-#define BM_ANADIG_USB2_MISC_EN_CLK_UTMI 0x40000000
-#define BM_ANADIG_USB2_MISC_RX_VPIN_FS 0x20000000
-#define BM_ANADIG_USB2_MISC_RX_VMIN_FS 0x10000000
-#define BM_ANADIG_USB2_MISC_RX_RXD_FS 0x08000000
-#define BM_ANADIG_USB2_MISC_RX_SQUELCH 0x04000000
-#define BM_ANADIG_USB2_MISC_RX_DISCON_DET 0x02000000
-#define BM_ANADIG_USB2_MISC_RX_HS_DATA 0x01000000
-#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002
-#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001
-
-#define HW_ANADIG_DIGPROG	(0x00000260)
-
-#define BP_ANADIG_DIGPROG_MAJOR      8
-#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00
-#define BF_ANADIG_DIGPROG_MAJOR(v)  (((v) << 8) & BM_ANADIG_DIGPROG_MAJOR)
-#define BP_ANADIG_DIGPROG_MINOR      0
-#define BM_ANADIG_DIGPROG_MINOR 0x000000FF
-#define BF_ANADIG_DIGPROG_MINOR(v)  (((v) << 0) & BM_ANADIG_DIGPROG_MINOR)
-#endif /* __ARCH_ARM___ANADIG_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h
deleted file mode 100644
index f10902cec2..0000000000
--- a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2013 Boundary Devices Inc. */
-
-#define MX6_MMDC_P0_MDCTL		0x021b0000
-#define MX6_MMDC_P0_MDPDC		0x021b0004
-#define MX6_MMDC_P0_MDOTC		0x021b0008
-#define MX6_MMDC_P0_MDCFG0		0x021b000c
-#define MX6_MMDC_P0_MDCFG1		0x021b0010
-#define MX6_MMDC_P0_MDCFG2		0x021b0014
-#define MX6_MMDC_P0_MDMISC		0x021b0018
-#define MX6_MMDC_P0_MDSCR		0x021b001c
-#define MX6_MMDC_P0_MDREF		0x021b0020
-#define MX6_MMDC_P0_MDRWD		0x021b002c
-#define MX6_MMDC_P0_MDOR		0x021b0030
-#define MX6_MMDC_P0_MDASP		0x021b0040
-#define MX6_MMDC_P0_MAARCR		0x021b0400
-#define MX6_MMDC_P0_MAPSR		0x021b0404
-#define MX6_MMDC_P0_MPZQHWCTRL		0x021b0800
-#define MX6_MMDC_P0_MPWLDECTRL0		0x021b080c
-#define MX6_MMDC_P0_MPWLDECTRL1		0x021b0810
-#define MX6_MMDC_P0_MPODTCTRL		0x021b0818
-#define MX6_MMDC_P0_MPRDDQBY0DL		0x021b081c
-#define MX6_MMDC_P0_MPRDDQBY1DL		0x021b0820
-#define MX6_MMDC_P0_MPRDDQBY2DL		0x021b0824
-#define MX6_MMDC_P0_MPRDDQBY3DL		0x021b0828
-#define MX6_MMDC_P0_MPDGCTRL0		0x021b083c
-#define MX6_MMDC_P0_MPDGCTRL1		0x021b0840
-#define MX6_MMDC_P0_MPRDDLCTL		0x021b0848
-#define MX6_MMDC_P0_MPWRDLCTL		0x021b0850
-#define MX6_MMDC_P0_MPRDDLHWCTL		0x021b0860
-#define MX6_MMDC_P0_MPWRDLHWCTL		0x021b0864
-#define MX6_MMDC_P0_MPPDCMPR2		0x021b0890
-#define MX6_MMDC_P0_MPMUR0		0x021b08b8
-#define MX6_MMDC_P0_MPDCCR		0x021b08c0
-
-#define MX6_MMDC_P1_MDCTL		0x021b4000
-#define MX6_MMDC_P1_MDPDC		0x021b4004
-#define MX6_MMDC_P1_MDOTC		0x021b4008
-#define MX6_MMDC_P1_MDCFG0		0x021b400c
-#define MX6_MMDC_P1_MDCFG1		0x021b4010
-#define MX6_MMDC_P1_MDCFG2		0x021b4014
-#define MX6_MMDC_P1_MDMISC		0x021b4018
-#define MX6_MMDC_P1_MDSCR		0x021b401c
-#define MX6_MMDC_P1_MDREF		0x021b4020
-#define MX6_MMDC_P1_MDRWD		0x021b402c
-#define MX6_MMDC_P1_MDOR		0x021b4030
-#define MX6_MMDC_P1_MDASP		0x021b4040
-#define MX6_MMDC_P1_MAPSR		0x021b4404
-#define MX6_MMDC_P1_MPZQHWCTRL		0x021b4800
-#define MX6_MMDC_P1_MPWLDECTRL0		0x021b480c
-#define MX6_MMDC_P1_MPWLDECTRL1		0x021b4810
-#define MX6_MMDC_P1_MPODTCTRL		0x021b4818
-#define MX6_MMDC_P1_MPRDDQBY0DL		0x021b481c
-#define MX6_MMDC_P1_MPRDDQBY1DL		0x021b4820
-#define MX6_MMDC_P1_MPRDDQBY2DL		0x021b4824
-#define MX6_MMDC_P1_MPRDDQBY3DL		0x021b4828
-#define MX6_MMDC_P1_MPDGCTRL0		0x021b483c
-#define MX6_MMDC_P1_MPDGCTRL1		0x021b4840
-#define MX6_MMDC_P1_MPRDDLCTL		0x021b4848
-#define MX6_MMDC_P1_MPWRDLCTL		0x021b4850
-#define MX6_MMDC_P1_MPRDDLHWCTL		0x021b4860
-#define MX6_MMDC_P1_MPWRDLHWCTL		0x021b4864
-#define MX6_MMDC_P1_MPPDCMPR2		0x021b4890
-#define MX6_MMDC_P1_MPMUR0		0x021b48b8
-#define MX6_MMDC_P1_MPDCCR		0x021b48c0
diff --git a/arch/arm/mach-imx/include/mach/imx6-fusemap.h b/arch/arm/mach-imx/include/mach/imx6-fusemap.h
deleted file mode 100644
index e14044e98a..0000000000
--- a/arch/arm/mach-imx/include/mach/imx6-fusemap.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __MACH_IMX_IMX6_OCOTP_H
-#define __MACH_IMX_IMX6_OCOTP_H
-
-#include <mach/ocotp-fusemap.h>
-
-#define IMX6_OCOTP_SI_REV		(OCOTP_WORD(0x430) | OCOTP_BIT(16) | OCOTP_WIDTH(4))
-#define IMX6_OCOTP_SATA_RST_SRC		(OCOTP_WORD(0x430) | OCOTP_BIT(24) | OCOTP_WIDTH(1))
-#define IMX6_OCOTP_VPU_DISABLE		(OCOTP_WORD(0x440) | OCOTP_BIT(15) | OCOTP_WIDTH(1))
-#define IMX6_OCOTP_SPEED_GRADING	(OCOTP_WORD(0x440) | OCOTP_BIT(16) | OCOTP_WIDTH(2))
-#define IMX6_OCOTP_DDR3_CONFIG		(OCOTP_WORD(0x460) | OCOTP_BIT(8) | OCOTP_WIDTH(8))
-#define IMX6_OCOTP_HDCP			(OCOTP_WORD(0x460) | OCOTP_BIT(16) | OCOTP_WIDTH(1))
-#define IMX6_OCOTP_TZASC_ENABLE		(OCOTP_WORD(0x460) | OCOTP_BIT(28) | OCOTP_WIDTH(1))
-#define IMX6_OCOTP_SDMMC_HYS_EN		(OCOTP_WORD(0x460) | OCOTP_BIT(29) | OCOTP_WIDTH(1))
-#define IMX6_OCOTP_eMMC_RESET_EN	(OCOTP_WORD(0x460) | OCOTP_BIT(30) | OCOTP_WIDTH(1))
-#define IMX6_OCOTP_BT_LPB_POLARITY	(OCOTP_WORD(0x470) | OCOTP_BIT(20) | OCOTP_WIDTH(1))
-#define IMX6_OCOTP_LPB_BOOT		(OCOTP_WORD(0x470) | OCOTP_BIT(21) | OCOTP_WIDTH(2))
-#define IMX6_OCOTP_MMC_DLL_DLY		(OCOTP_WORD(0x470) | OCOTP_BIT(24) | OCOTP_WIDTH(7))
-#define IMX6_OCOTP_TEMPERATURE_GRADE	(OCOTP_WORD(0x480) | OCOTP_BIT(6) | OCOTP_WIDTH(2))
-#define IMX6_OCOTP_POWER_GATE_CORES	(OCOTP_WORD(0x4d0) | OCOTP_BIT(31) | OCOTP_WIDTH(1))
-#define IMX6DQ_OCOTP_TEST_PORT_DISABLE	(OCOTP_WORD(0x6e0) | OCOTP_BIT(1) | OCOTP_WIDTH(1))
-#define IMX6SDL_OCOTP_FIELD_RETURN	(OCOTP_WORD(0x6e0) | OCOTP_BIT(0) | OCOTP_WIDTH(1))
-
-#endif /* __MACH_IMX_IMX6_OCOTP_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
deleted file mode 100644
index 9385b342c2..0000000000
--- a/arch/arm/mach-imx/include/mach/imx6-mmdc.h
+++ /dev/null
@@ -1,331 +0,0 @@
-#ifndef __MACH_MMDC_H
-#define __MACH_MMDC_H
-
-#include <mach/imx6-regs.h>
-
-#define P0_IPS (void __iomem *)MX6_MMDC_P0_BASE_ADDR
-#define P1_IPS (void __iomem *)MX6_MMDC_P1_BASE_ADDR
-
-#define MDCTL		0x000
-#define MDPDC		0x004
-#define MDSCR		0x01c
-#define MDMISC		0x018
-#define MDREF		0x020
-#define MAPSR		0x404
-#define MPZQHWCTRL	0x800
-#define MPWLGCR		0x808
-#define MPWLDECTRL0	0x80c
-#define MPWLDECTRL1	0x810
-#define MPPDCMPR1	0x88c
-#define MPSWDAR		0x894
-#define MPRDDLCTL	0x848
-#define MPMUR		0x8b8
-#define MPDGCTRL0	0x83c
-#define MPDGCTRL1	0x840
-#define MPRDDLCTL	0x848
-#define MPWRDLCTL	0x850
-#define MPRDDLHWCTL	0x860
-#define MPWRDLHWCTL	0x864
-#define MPDGHWST0	0x87c
-#define MPDGHWST1	0x880
-#define MPDGHWST2	0x884
-#define MPDGHWST3	0x888
-
-#define MMDCx_MDCTL_SDE0	0x80000000
-#define MMDCx_MDCTL_SDE1	0x40000000
-
-#define MMDCx_MDCTL_DSIZ_16B	0x00000000
-#define MMDCx_MDCTL_DSIZ_32B	0x00010000
-#define MMDCx_MDCTL_DSIZ_64B	0x00020000
-
-#define MMDCx_MDMISC_DDR_4_BANKS	0x00000020
-
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0	((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5a8)
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1	((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5b0)
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2	((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x524)
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3	((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x51c)
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4	((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x518)
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5	((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x50c)
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6	((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5b8)
-#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7	((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5c0)
-
-
-int mmdc_do_write_level_calibration(void);
-int mmdc_do_dqs_calibration(void);
-void mmdc_print_calibration_results(void);
-
-/* MMDC P0/P1 Registers */
-struct mmdc_p_regs {
-	u32 mdctl;
-	u32 mdpdc;
-	u32 mdotc;
-	u32 mdcfg0;
-	u32 mdcfg1;
-	u32 mdcfg2;
-	u32 mdmisc;
-	u32 mdscr;
-	u32 mdref;
-	u32 res1[2];
-	u32 mdrwd;
-	u32 mdor;
-	u32 res2[3];
-	u32 mdasp;
-	u32 res3[240];
-	u32 mapsr;
-	u32 res4[254];
-	u32 mpzqhwctrl;
-	u32 res5[2];
-	u32 mpwldectrl0;
-	u32 mpwldectrl1;
-	u32 res6;
-	u32 mpodtctrl;
-	u32 mprddqby0dl;
-	u32 mprddqby1dl;
-	u32 mprddqby2dl;
-	u32 mprddqby3dl;
-	u32 res7[4];
-	u32 mpdgctrl0;
-	u32 mpdgctrl1;
-	u32 res8;
-	u32 mprddlctl;
-	u32 res9;
-	u32 mpwrdlctl;
-	u32 res10[25];
-	u32 mpmur0;
-};
-
-#define MX6SX_IOM_DDR_BASE	0x020e0200
-struct mx6sx_iomux_ddr_regs {
-	u32 res1[59];
-	u32 dram_dqm0;
-	u32 dram_dqm1;
-	u32 dram_dqm2;
-	u32 dram_dqm3;
-	u32 dram_ras;
-	u32 dram_cas;
-	u32 res2[2];
-	u32 dram_sdwe_b;
-	u32 dram_odt0;
-	u32 dram_odt1;
-	u32 dram_sdba0;
-	u32 dram_sdba1;
-	u32 dram_sdba2;
-	u32 dram_sdcke0;
-	u32 dram_sdcke1;
-	u32 dram_sdclk_0;
-	u32 dram_sdqs0;
-	u32 dram_sdqs1;
-	u32 dram_sdqs2;
-	u32 dram_sdqs3;
-	u32 dram_reset;
-};
-
-#define MX6SX_IOM_GRP_BASE	0x020e0500
-struct mx6sx_iomux_grp_regs {
-	u32 res1[61];
-	u32 grp_addds;
-	u32 grp_ddrmode_ctl;
-	u32 grp_ddrpke;
-	u32 grp_ddrpk;
-	u32 grp_ddrhys;
-	u32 grp_ddrmode;
-	u32 grp_b0ds;
-	u32 grp_b1ds;
-	u32 grp_ctlds;
-	u32 grp_ddr_type;
-	u32 grp_b2ds;
-	u32 grp_b3ds;
-};
-
-/*
- * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
- */
-#define MX6DQ_IOM_DDR_BASE      0x020e0500
-struct mx6dq_iomux_ddr_regs {
-	u32 res1[3];
-	u32 dram_sdqs5;
-	u32 dram_dqm5;
-	u32 dram_dqm4;
-	u32 dram_sdqs4;
-	u32 dram_sdqs3;
-	u32 dram_dqm3;
-	u32 dram_sdqs2;
-	u32 dram_dqm2;
-	u32 res2[16];
-	u32 dram_cas;
-	u32 res3[2];
-	u32 dram_ras;
-	u32 dram_reset;
-	u32 res4[2];
-	u32 dram_sdclk_0;
-	u32 dram_sdba2;
-	u32 dram_sdcke0;
-	u32 dram_sdclk_1;
-	u32 dram_sdcke1;
-	u32 dram_sdodt0;
-	u32 dram_sdodt1;
-	u32 res5;
-	u32 dram_sdqs0;
-	u32 dram_dqm0;
-	u32 dram_sdqs1;
-	u32 dram_dqm1;
-	u32 dram_sdqs6;
-	u32 dram_dqm6;
-	u32 dram_sdqs7;
-	u32 dram_dqm7;
-};
-
-#define MX6DQ_IOM_GRP_BASE      0x020e0700
-struct mx6dq_iomux_grp_regs {
-	u32 res1[18];
-	u32 grp_b7ds;
-	u32 grp_addds;
-	u32 grp_ddrmode_ctl;
-	u32 res2;
-	u32 grp_ddrpke;
-	u32 res3[6];
-	u32 grp_ddrmode;
-	u32 res4[3];
-	u32 grp_b0ds;
-	u32 grp_b1ds;
-	u32 grp_ctlds;
-	u32 res5;
-	u32 grp_b2ds;
-	u32 grp_ddr_type;
-	u32 grp_b3ds;
-	u32 grp_b4ds;
-	u32 grp_b5ds;
-	u32 grp_b6ds;
-};
-
-#define MX6SDL_IOM_DDR_BASE     0x020e0400
-struct mx6sdl_iomux_ddr_regs {
-	u32 res1[25];
-	u32 dram_cas;
-	u32 res2[2];
-	u32 dram_dqm0;
-	u32 dram_dqm1;
-	u32 dram_dqm2;
-	u32 dram_dqm3;
-	u32 dram_dqm4;
-	u32 dram_dqm5;
-	u32 dram_dqm6;
-	u32 dram_dqm7;
-	u32 dram_ras;
-	u32 dram_reset;
-	u32 res3[2];
-	u32 dram_sdba2;
-	u32 dram_sdcke0;
-	u32 dram_sdcke1;
-	u32 dram_sdclk_0;
-	u32 dram_sdclk_1;
-	u32 dram_sdodt0;
-	u32 dram_sdodt1;
-	u32 dram_sdqs0;
-	u32 dram_sdqs1;
-	u32 dram_sdqs2;
-	u32 dram_sdqs3;
-	u32 dram_sdqs4;
-	u32 dram_sdqs5;
-	u32 dram_sdqs6;
-	u32 dram_sdqs7;
-};
-
-#define MX6SDL_IOM_GRP_BASE     0x020e0700
-struct mx6sdl_iomux_grp_regs {
-	u32 res1[18];
-	u32 grp_b7ds;
-	u32 grp_addds;
-	u32 grp_ddrmode_ctl;
-	u32 grp_ddrpke;
-	u32 res2[2];
-	u32 grp_ddrmode;
-	u32 grp_b0ds;
-	u32 res3;
-	u32 grp_ctlds;
-	u32 grp_b1ds;
-	u32 grp_ddr_type;
-	u32 grp_b2ds;
-	u32 grp_b3ds;
-	u32 grp_b4ds;
-	u32 grp_b5ds;
-	u32 res4;
-	u32 grp_b6ds;
-};
-
-/* Device Information: Varies per DDR3 part number and speed grade */
-struct mx6_ddr3_cfg {
-	u16 mem_speed;	/* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
-	u8 density;	/* chip density (Gb) (1,2,4,8) */
-	u8 width;	/* bus width (bits) (4,8,16) */
-	u8 banks;	/* number of banks */
-	u8 rowaddr;	/* row address bits (11-16)*/
-	u8 coladdr;	/* col address bits (9-12) */
-	u8 pagesz;	/* page size (K) (1-2) */
-	u16 trcd;	/* tRCD=tRP=CL (ns*100) */
-	u16 trcmin;	/* tRC min (ns*100) */
-	u16 trasmin;	/* tRAS min (ns*100) */
-	u8 SRT;		/* self-refresh temperature: 0=normal, 1=extended */
-};
-
-/* System Information: Varies per board design, layout, and term choices */
-struct mx6_ddr_sysinfo {
-	u8 dsize;	/* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
-	u8 cs_density;	/* density per chip select (Gb) */
-	u8 ncs;		/* number chip selects used (1|2) */
-	char cs1_mirror;/* enable address mirror (0|1) */
-	char bi_on;	/* Bank interleaving enable */
-	u8 rtt_nom;	/* Rtt_Nom (DDR3_RTT_*) */
-	u8 rtt_wr;	/* Rtt_Wr (DDR3_RTT_*) */
-	u8 ralat;	/* Read Additional Latency (0-7) */
-	u8 walat;	/* Write Additional Latency (0-3) */
-	u8 mif3_mode;	/* Command prediction working mode */
-	u8 rst_to_cke;	/* Time from SDE enable to CKE rise */
-	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
-	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
-};
-
-/*
- * Board specific calibration:
- *   This includes write leveling calibration values as well as DQS gating
- *   and read/write delays. These values are board/layout/device specific.
- *   Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
- *   (DOC-96412) to determine these values over a range of boards and
- *   temperatures.
- */
-struct mx6_mmdc_calibration {
-	/* write leveling calibration */
-	u32 p0_mpwldectrl0;
-	u32 p0_mpwldectrl1;
-	u32 p1_mpwldectrl0;
-	u32 p1_mpwldectrl1;
-	/* read DQS gating */
-	u32 p0_mpdgctrl0;
-	u32 p0_mpdgctrl1;
-	u32 p1_mpdgctrl0;
-	u32 p1_mpdgctrl1;
-	/* read delay */
-	u32 p0_mprddlctl;
-	u32 p1_mprddlctl;
-	/* write delay */
-	u32 p0_mpwrdlctl;
-	u32 p1_mpwrdlctl;
-};
-
-/* configure iomux (pinctl/padctl) */
-void mx6dq_dram_iocfg(unsigned width,
-		      const struct mx6dq_iomux_ddr_regs *,
-		      const struct mx6dq_iomux_grp_regs *);
-void mx6sdl_dram_iocfg(unsigned width,
-		       const struct mx6sdl_iomux_ddr_regs *,
-		       const struct mx6sdl_iomux_grp_regs *);
-void mx6sx_dram_iocfg(unsigned width,
-		      const struct mx6sx_iomux_ddr_regs *,
-		      const struct mx6sx_iomux_grp_regs *);
-
-/* configure mx6 mmdc registers */
-void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
-		  const struct mx6_mmdc_calibration *,
-		  const struct mx6_ddr3_cfg *);
-
-#endif /* __MACH_MMDC_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
deleted file mode 100644
index 7350ffd16f..0000000000
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ /dev/null
@@ -1,125 +0,0 @@
-#ifndef __MACH_IMX6_REGS_H
-#define __MACH_IMX6_REGS_H
-
-#define MX6_GPMI_BASE_ADDR		0x00112000
-
-#define MX6_FAST1_BASE_ADDR		0x00c00000
-#define MX6_FAST2_BASE_ADDR		0x00b00000
-
-#define MX6_AIPS1_ARB_BASE_ADDR		0x02000000
-#define MX6_AIPS2_ARB_BASE_ADDR		0x02100000
-
-/* Defines for Blocks connected via AIPS (SkyBlue) */
-#define MX6_ATZ1_BASE_ADDR              MX6_AIPS1_ARB_BASE_ADDR
-#define MX6_ATZ2_BASE_ADDR              MX6_AIPS2_ARB_BASE_ADDR
-
-/* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */
-#define MX6_SPDIF_BASE_ADDR             (MX6_ATZ1_BASE_ADDR + 0x04000)
-#define MX6_ECSPI1_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x08000)
-#define MX6_ECSPI2_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x0C000)
-#define MX6_ECSPI3_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x10000)
-#define MX6_ECSPI4_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x14000)
-#define MX6_ECSPI5_BASE_ADDR            (MX6_ATZ1_BASE_ADDR + 0x18000)
-#define MX6_UART1_BASE_ADDR             (MX6_ATZ1_BASE_ADDR + 0x20000)
-#define MX6_ESAI1_BASE_ADDR             (MX6_ATZ1_BASE_ADDR + 0x24000)
-#define MX6_SSI1_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x28000)
-#define MX6_SSI2_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x2C000)
-#define MX6_SSI3_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x30000)
-#define MX6_ASRC_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x34000)
-#define MX6_SPBA_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x3C000)
-#define MX6_VPU_BASE_ADDR               (MX6_ATZ1_BASE_ADDR + 0x40000)
-
-#define MX6_IPU1_BASE_ADDR		0x02400000
-#define MX6_IPU2_BASE_ADDR		0x02800000
-
-/* ATZ#1- On Platform */
-#define MX6_AIPS1_ON_BASE_ADDR          (MX6_ATZ1_BASE_ADDR + 0x7C000)
-
-/* ATZ#1- Off Platform */
-#define MX6_AIPS1_OFF_BASE_ADDR         (MX6_ATZ1_BASE_ADDR + 0x80000)
-
-#define MX6_PWM1_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x0000)
-#define MX6_PWM2_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x4000)
-#define MX6_PWM3_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x8000)
-#define MX6_PWM4_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0xC000)
-#define MX6_CAN1_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x10000)
-#define MX6_CAN2_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x14000)
-#define MX6_GPT_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x18000)
-#define MX6_GPIO1_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x1C000)
-#define MX6_GPIO2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x20000)
-#define MX6_GPIO3_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x24000)
-#define MX6_GPIO4_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x28000)
-#define MX6_GPIO5_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x2C000)
-#define MX6_GPIO6_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x30000)
-#define MX6_GPIO7_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x34000)
-#define MX6_KPP_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x38000)
-#define MX6_WDOG1_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x3C000)
-#define MX6_WDOG2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x40000)
-#define MX6_CCM_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x44000)
-#define MX6_ANATOP_BASE_ADDR            (MX6_AIPS1_OFF_BASE_ADDR + 0x48000)
-#define MX6_USBPHY1_BASE_ADDR		(MX6_AIPS1_OFF_BASE_ADDR + 0x49000)
-#define MX6_USBPHY2_BASE_ADDR		(MX6_AIPS1_OFF_BASE_ADDR + 0x4a000)
-#define MX6_SNVS_BASE_ADDR              (MX6_AIPS1_OFF_BASE_ADDR + 0x4C000)
-#define MX6_EPIT1_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x50000)
-#define MX6_EPIT2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x54000)
-#define MX6_SRC_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x58000)
-#define MX6_GPC_BASE_ADDR               (MX6_AIPS1_OFF_BASE_ADDR + 0x5C000)
-#define MX6_IOMUXC_BASE_ADDR            (MX6_AIPS1_OFF_BASE_ADDR + 0x60000)
-#define MX6_DCIC1_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x64000)
-#define MX6_DCIC2_BASE_ADDR             (MX6_AIPS1_OFF_BASE_ADDR + 0x68000)
-#define MX6_DMA_REQ_PORT_HOST_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x6C000)
-
-/* ATZ#2- On Platform */
-#define MX6_AIPS2_ON_BASE_ADDR          (MX6_ATZ2_BASE_ADDR + 0x7C000)
-
-/* ATZ#2- Off Platform */
-#define MX6_AIPS2_OFF_BASE_ADDR         (MX6_ATZ2_BASE_ADDR + 0x80000)
-
-/* ATZ#2  - Global enable (0) */
-#define MX6_CAAM_BASE_ADDR              (MX6_ATZ2_BASE_ADDR)
-#define MX6_ARM_BASE_ADDR		(MX6_ATZ2_BASE_ADDR + 0x40000)
-
-#define MX6_USBOH3_PL301_BASE_ADDR      (MX6_AIPS2_OFF_BASE_ADDR + 0x0000)
-#define MX6_USBOH3_USB_BASE_ADDR        (MX6_AIPS2_OFF_BASE_ADDR + 0x4000)
-#define MX6_OTG_BASE_ADDR		MX6_USBOH3_USB_BASE_ADDR
-#define MX6_ENET_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x8000)
-#define MX6_MLB_BASE_ADDR               (MX6_AIPS2_OFF_BASE_ADDR + 0xC000)
-
-#define MX6_USDHC1_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x10000)
-#define MX6_USDHC2_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x14000)
-#define MX6_USDHC3_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x18000)
-#define MX6_USDHC4_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x1C000)
-#define MX6_I2C1_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x20000)
-#define MX6_I2C2_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x24000)
-#define MX6_I2C3_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x28000)
-#define MX6_ROMCP_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x2C000)
-#define MX6_MMDC_P0_BASE_ADDR           (MX6_AIPS2_OFF_BASE_ADDR + 0x30000)
-#define MX6_MMDC_P1_BASE_ADDR           (MX6_AIPS2_OFF_BASE_ADDR + 0x34000)
-#define MX6_WEIM_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x38000)
-#define MX6_OCOTP_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x3C000)
-#define MX6_CSU_BASE_ADDR               (MX6_AIPS2_OFF_BASE_ADDR + 0x40000)
-#define MX6_IP2APB_PERFMON1_BASE_ADDR   (MX6_AIPS2_OFF_BASE_ADDR + 0x44000)
-#define MX6_IP2APB_PERFMON2_BASE_ADDR   (MX6_AIPS2_OFF_BASE_ADDR + 0x48000)
-#define MX6_IP2APB_PERFMON3_BASE_ADDR   (MX6_AIPS2_OFF_BASE_ADDR + 0x4C000)
-#define MX6_IP2APB_TZASC1_BASE_ADDR     (MX6_AIPS2_OFF_BASE_ADDR + 0x50000)
-#define MX6_IP2APB_TZASC2_BASE_ADDR     (MX6_AIPS2_OFF_BASE_ADDR + 0x54000)
-#define MX6_AUDMUX_BASE_ADDR            (MX6_AIPS2_OFF_BASE_ADDR + 0x58000)
-#define MX6_MIPI_CSI2_BASE_ADDR         (MX6_AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define MX6_MIPI_DSI_BASE_ADDR          (MX6_AIPS2_OFF_BASE_ADDR + 0x60000)
-#define MX6_VDOA_BASE_ADDR              (MX6_AIPS2_OFF_BASE_ADDR + 0x64000)
-#define MX6ULL_WDOG3_BASE_ADDR          (MX6_AIPS2_OFF_BASE_ADDR + 0x64000)
-#define MX6_UART2_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x68000)
-#define MX6_UART3_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x6C000)
-#define MX6_UART4_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x70000)
-#define MX6_UART5_BASE_ADDR             (MX6_AIPS2_OFF_BASE_ADDR + 0x74000)
-#define MX6_IP2APB_USBPHY1_BASE_ADDR    (MX6_AIPS2_OFF_BASE_ADDR + 0x78000)
-#define MX6_IP2APB_USBPHY2_BASE_ADDR    (MX6_AIPS2_OFF_BASE_ADDR + 0x7C000)
-
-#define MX6_UART7_BASE_ADDR		0x02018000
-#define MX6_SATA_BASE_ADDR		0x02200000
-
-#define MX6_MMDC_PORT01_BASE_ADDR	0x10000000
-#define MX6_MMDC_PORT0_BASE_ADDR	0x80000000
-
-
-#endif /* __MACH_IMX6_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h
deleted file mode 100644
index b65cdaaf40..0000000000
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ /dev/null
@@ -1,135 +0,0 @@
-#ifndef __MACH_IMX6_H
-#define __MACH_IMX6_H
-
-#include <io.h>
-#include <mach/generic.h>
-#include <mach/imx6-regs.h>
-#include <mach/revision.h>
-
-#include <poweroff.h>
-
-void __noreturn imx6_pm_stby_poweroff(struct poweroff_handler *handler);
-
-#define IMX6_ANATOP_SI_REV 0x260
-#define IMX6SL_ANATOP_SI_REV 0x280
-
-#define IMX6_CPUTYPE_IMX6SL	0x160
-#define IMX6_CPUTYPE_IMX6S	0x161
-#define IMX6_CPUTYPE_IMX6DL	0x261
-#define IMX6_CPUTYPE_IMX6SX	0x462
-#define IMX6_CPUTYPE_IMX6D	0x263
-#define IMX6_CPUTYPE_IMX6DP	0x1263
-#define IMX6_CPUTYPE_IMX6Q	0x463
-#define IMX6_CPUTYPE_IMX6QP	0x1463
-#define IMX6_CPUTYPE_IMX6UL	0x164
-#define IMX6_CPUTYPE_IMX6ULL	0x165
-
-#define SCU_CONFIG              0x04
-
-static inline int scu_get_core_count(void)
-{
-#if __LINUX_ARM_ARCH__ <= 7
-	unsigned long base;
-	unsigned int ncores;
-
-	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
-
-	ncores = readl(base + SCU_CONFIG);
-	return (ncores & 0x03) + 1;
-#else
-	return 0;
-#endif
-}
-
-#define SI_REV_CPUTYPE(s)	(((s) >> 16) & 0xff)
-#define SI_REV_MAJOR(s)		(((s) >> 8) & 0xf)
-#define SI_REV_MINOR(s)		((s) & 0xf)
-
-static inline uint32_t __imx6_read_si_rev(void)
-{
-	uint32_t si_rev;
-	uint32_t cpu_type;
-
-	si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV);
-	cpu_type = SI_REV_CPUTYPE(si_rev);
-
-	if (cpu_type >= 0x61 && cpu_type <= 0x65)
-		return si_rev;
-
-	/* try non-MX6-standard SI_REV reg offset for MX6SL */
-	si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV);
-	cpu_type = SI_REV_CPUTYPE(si_rev);
-
-	if (si_rev == 0x60)
-		return si_rev;
-
-	return 0;
-}
-
-static inline int __imx6_cpu_type(void)
-{
-	uint32_t si_rev = __imx6_read_si_rev();
-	uint32_t cpu_type = SI_REV_CPUTYPE(si_rev);
-
-	/* intentionally skip scu_get_core_count() for MX6SL */
-	if (cpu_type == IMX6_CPUTYPE_IMX6SL)
-		return IMX6_CPUTYPE_IMX6SL;
-
-	cpu_type |= scu_get_core_count() << 8;
-
-	if ((cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) &&
-	    SI_REV_MAJOR(si_rev) >= 1)
-		cpu_type |= 0x1000;
-
-	return cpu_type;
-}
-
-int imx6_cpu_type(void);
-
-#define DEFINE_MX6_CPU_TYPE(str, type)					\
-	static inline int cpu_mx6_is_##str(void)			\
-	{								\
-		return __imx6_cpu_type() == type;			\
-	}								\
-									\
-	static inline int cpu_is_##str(void)				\
-	{								\
-		if (!cpu_is_mx6())					\
-			return 0;					\
-		return cpu_mx6_is_##str();				\
-	}
-
-/*
- * Below are defined:
- *
- * cpu_is_mx6s(), cpu_is_mx6dl(), cpu_is_mx6q(), cpu_is_mx6qp(), cpu_is_mx6d(),
- * cpu_is_mx6dp(), cpu_is_mx6sx(), cpu_is_mx6sl(), cpu_is_mx6ul(),
- * cpu_is_mx6ull()
- */
-DEFINE_MX6_CPU_TYPE(mx6s, IMX6_CPUTYPE_IMX6S);
-DEFINE_MX6_CPU_TYPE(mx6dl, IMX6_CPUTYPE_IMX6DL);
-DEFINE_MX6_CPU_TYPE(mx6q, IMX6_CPUTYPE_IMX6Q);
-DEFINE_MX6_CPU_TYPE(mx6qp, IMX6_CPUTYPE_IMX6QP);
-DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D);
-DEFINE_MX6_CPU_TYPE(mx6dp, IMX6_CPUTYPE_IMX6DP);
-DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX);
-DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL);
-DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL);
-DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL);
-
-static inline int __imx6_cpu_revision(void)
-{
-	uint32_t si_rev = __imx6_read_si_rev();
-	u8 major_part, minor_part;
-
-	major_part = (si_rev >> 8) & 0xf;
-	minor_part = si_rev & 0xf;
-
-	return ((major_part + 1) << 4) | minor_part;
-}
-
-int imx6_cpu_revision(void);
-
-u64 imx6_uid(void);
-
-#endif /* __MACH_IMX6_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h
deleted file mode 100644
index 9e5764276f..0000000000
--- a/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2013 Boundary Devices Inc. */
-
-#define MX6_IOM_DRAM_ADDR00	0x020e0424
-#define MX6_IOM_DRAM_ADDR01	0x020e0428
-#define MX6_IOM_DRAM_ADDR10	0x020e042c
-#define MX6_IOM_DRAM_ADDR11	0x020e0430
-#define MX6_IOM_DRAM_ADDR12	0x020e0434
-#define MX6_IOM_DRAM_ADDR13	0x020e0438
-#define MX6_IOM_DRAM_ADDR14	0x020e043c
-#define MX6_IOM_DRAM_ADDR15	0x020e0440
-#define MX6_IOM_DRAM_ADDR02	0x020e0444
-#define MX6_IOM_DRAM_ADDR03	0x020e0448
-#define MX6_IOM_DRAM_ADDR04	0x020e044c
-#define MX6_IOM_DRAM_ADDR05	0x020e0450
-#define MX6_IOM_DRAM_ADDR06	0x020e0454
-#define MX6_IOM_DRAM_ADDR07	0x020e0458
-#define MX6_IOM_DRAM_ADDR08	0x020e045c
-#define MX6_IOM_DRAM_ADDR09	0x020e0460
-
-#define MX6_IOM_DRAM_DQM0	0x020e0470
-#define MX6_IOM_DRAM_DQM1	0x020e0474
-#define MX6_IOM_DRAM_DQM2	0x020e0478
-#define MX6_IOM_DRAM_DQM3	0x020e047c
-#define MX6_IOM_DRAM_DQM4	0x020e0480
-#define MX6_IOM_DRAM_DQM5	0x020e0484
-#define MX6_IOM_DRAM_DQM6	0x020e0488
-#define MX6_IOM_DRAM_DQM7	0x020e048c
-
-#define MX6_IOM_DRAM_CAS	0x020e0464
-#define MX6_IOM_DRAM_RAS	0x020e0490
-#define MX6_IOM_DRAM_RESET	0x020e0494
-#define MX6_IOM_DRAM_SDBA0	0x020e0498
-#define MX6_IOM_DRAM_SDBA1	0x020e049c
-#define MX6_IOM_DRAM_SDCLK_0	0x020e04ac
-#define MX6_IOM_DRAM_SDCLK_1	0x020e04b0
-#define MX6_IOM_DRAM_SDBA2	0x020e04a0
-#define MX6_IOM_DRAM_SDCKE0	0x020e04a4
-#define MX6_IOM_DRAM_SDCKE1	0x020e04a8
-#define MX6_IOM_DRAM_SDODT0	0x020e04b4
-#define MX6_IOM_DRAM_SDODT1	0x020e04b8
-
-#define MX6_IOM_DRAM_SDQS0	0x020e04bc
-#define MX6_IOM_DRAM_SDQS1	0x020e04c0
-#define MX6_IOM_DRAM_SDQS2	0x020e04c4
-#define MX6_IOM_DRAM_SDQS3	0x020e04c8
-#define MX6_IOM_DRAM_SDQS4	0x020e04cc
-#define MX6_IOM_DRAM_SDQS5	0x020e04d0
-#define MX6_IOM_DRAM_SDQS6	0x020e04d4
-#define MX6_IOM_DRAM_SDQS7	0x020e04d8
-
-#define MX6_IOM_GRP_B0DS	0x020e0764
-#define MX6_IOM_GRP_B1DS	0x020e0770
-#define MX6_IOM_GRP_B2DS	0x020e0778
-#define MX6_IOM_GRP_B3DS	0x020e077c
-#define MX6_IOM_GRP_B4DS	0x020e0780
-#define MX6_IOM_GRP_B5DS	0x020e0784
-#define MX6_IOM_GRP_B6DS	0x020e078c
-#define MX6_IOM_GRP_B7DS	0x020e0748
-#define MX6_IOM_GRP_ADDDS	0x020e074c
-#define MX6_IOM_DDRMODE_CTL	0x020e0750
-#define MX6_IOM_GRP_DDRPKE	0x020e0754
-#define MX6_IOM_GRP_DDRHYS	0x020e075c
-#define MX6_IOM_GRP_DDRMODE	0x020e0760
-#define MX6_IOM_GRP_CTLDS	0x020e076c
-#define MX6_IOM_GRP_DDR_TYPE	0x020e0774
diff --git a/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h
deleted file mode 100644
index 3f20b95091..0000000000
--- a/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2013 Boundary Devices Inc. */
-
-#define MX6_IOM_DRAM_DQM0	0x020e05ac
-#define MX6_IOM_DRAM_DQM1	0x020e05b4
-#define MX6_IOM_DRAM_DQM2	0x020e0528
-#define MX6_IOM_DRAM_DQM3	0x020e0520
-#define MX6_IOM_DRAM_DQM4	0x020e0514
-#define MX6_IOM_DRAM_DQM5	0x020e0510
-#define MX6_IOM_DRAM_DQM6	0x020e05bc
-#define MX6_IOM_DRAM_DQM7	0x020e05c4
-
-#define MX6_IOM_DRAM_CAS	0x020e056c
-#define MX6_IOM_DRAM_RAS	0x020e0578
-#define MX6_IOM_DRAM_RESET	0x020e057c
-#define MX6_IOM_DRAM_SDCLK_0	0x020e0588
-#define MX6_IOM_DRAM_SDCLK_1	0x020e0594
-#define MX6_IOM_DRAM_SDBA2	0x020e058c
-#define MX6_IOM_DRAM_SDCKE0	0x020e0590
-#define MX6_IOM_DRAM_SDCKE1	0x020e0598
-#define MX6_IOM_DRAM_SDODT0	0x020e059c
-#define MX6_IOM_DRAM_SDODT1	0x020e05a0
-
-#define MX6_IOM_DRAM_SDQS0	0x020e05a8
-#define MX6_IOM_DRAM_SDQS1	0x020e05b0
-#define MX6_IOM_DRAM_SDQS2	0x020e0524
-#define MX6_IOM_DRAM_SDQS3	0x020e051c
-#define MX6_IOM_DRAM_SDQS4	0x020e0518
-#define MX6_IOM_DRAM_SDQS5	0x020e050c
-#define MX6_IOM_DRAM_SDQS6	0x020e05b8
-#define MX6_IOM_DRAM_SDQS7	0x020e05c0
-
-#define MX6_IOM_GRP_B0DS	0x020e0784
-#define MX6_IOM_GRP_B1DS	0x020e0788
-#define MX6_IOM_GRP_B2DS	0x020e0794
-#define MX6_IOM_GRP_B3DS	0x020e079c
-#define MX6_IOM_GRP_B4DS	0x020e07a0
-#define MX6_IOM_GRP_B5DS	0x020e07a4
-#define MX6_IOM_GRP_B6DS	0x020e07a8
-#define MX6_IOM_GRP_B7DS	0x020e0748
-#define MX6_IOM_GRP_ADDDS	0x020e074c
-#define MX6_IOM_DDRMODE_CTL	0x020e0750
-#define MX6_IOM_GRP_DDRPKE	0x020e0758
-#define MX6_IOM_GRP_DDRMODE	0x020e0774
-#define MX6_IOM_GRP_CTLDS	0x020e078c
-#define MX6_IOM_GRP_DDR_TYPE	0x020e0798
diff --git a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h
deleted file mode 100644
index 5c60794ca7..0000000000
--- a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef __MACH_IMX7_CCM_REGS_H__
-#define __MACH_IMX7_CCM_REGS_H__
-
-#define IMX7_CCM_CCGR_UART1		148
-#define IMX7_CCM_CCGR_UART2		149
-#define IMX7_CCM_CCGR_UART3		150
-
-#define IMX7_CLOCK_ROOT_INDEX(x)	(((x) - 0x8000) / 128)
-
-/*
- * Taken from "Table 5-11. Clock Root Table" from i.MX7 Dual Processor
- * Reference Manual
- */
-#define IMX7_UART1_CLK_ROOT		IMX7_CLOCK_ROOT_INDEX(0xaf80)
-#define IMX7_UART1_CLK_ROOT__OSC_24M IMX7_CCM_TARGET_ROOTn_MUX(0b000)
-
-#define IMX7_UART2_CLK_ROOT		IMX7_CLOCK_ROOT_INDEX(0xb000)
-#define IMX7_UART2_CLK_ROOT__OSC_24M IMX7_CCM_TARGET_ROOTn_MUX(0b000)
-
-#define IMX7_UART3_CLK_ROOT		IMX7_CLOCK_ROOT_INDEX(0xb080)
-#define IMX7_UART3_CLK_ROOT__OSC_24M IMX7_CCM_TARGET_ROOTn_MUX(0b000)
-
-/* 0 <= n <= 190 */
-#define IMX7_CCM_CCGRn_SET(n)	(0x4004 + 16 * (n))
-#define IMX7_CCM_CCGRn_CLR(n)	(0x4008 + 16 * (n))
-
-/* 0 <= n <= 120 */
-#define IMX7_CCM_TARGET_ROOTn(n)	(0x8000 + 128 * (n))
-
-#define IMX7_CCM_TARGET_ROOTn_MUX(x)		((x) << 24)
-#define IMX7_CCM_TARGET_ROOTn_ENABLE		BIT(28)
-
-
-#define IMX7_CCM_CCGR_SETTINGn(n, s)  ((s) << ((n) * 4))
-#define IMX7_CCM_CCGR_SETTINGn_NOT_NEEDED(n)		IMX7_CCM_CCGR_SETTINGn(n, 0b00)
-#define IMX7_CCM_CCGR_SETTINGn_NEEDED_RUN(n)		IMX7_CCM_CCGR_SETTINGn(n, 0b01)
-#define IMX7_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n)	IMX7_CCM_CCGR_SETTINGn(n, 0b10)
-#define IMX7_CCM_CCGR_SETTINGn_NEEDED(n)		IMX7_CCM_CCGR_SETTINGn(n, 0b11)
-
-static inline void imx7_early_setup_uart_clock(void)
-{
-	void __iomem *ccm   = IOMEM(MX7_CCM_BASE_ADDR);
-
-	writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0),
-	       ccm + IMX7_CCM_CCGRn_CLR(IMX7_CCM_CCGR_UART1));
-	writel(IMX7_CCM_TARGET_ROOTn_ENABLE | IMX7_UART1_CLK_ROOT__OSC_24M,
-	       ccm + IMX7_CCM_TARGET_ROOTn(IMX7_UART1_CLK_ROOT));
-	writel(IMX7_CCM_CCGR_SETTINGn_NEEDED(0),
-	       ccm + IMX7_CCM_CCGRn_SET(IMX7_CCM_CCGR_UART1));
-}
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h
deleted file mode 100644
index 3ff690608a..0000000000
--- a/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* SPDX-FileCopyrightText: 2017 Uwe Kleine-König <u.kleine-koenig@pengutronix.de>, Pengutronix */
-
-#define MX7_DDRC_MSTR			0x307a0000
-#define MX7_DDRC_STAT			0x307a0004
-#define MX7_DDRC_MRCTRL0		0x307a0010
-#define MX7_DDRC_MRCTRL1		0x307a0014
-#define MX7_DDRC_MRSTAT			0x307a0018
-#define MX7_DDRC_DERATEEN		0x307a0020
-#define MX7_DDRC_DERATEINT		0x307a0024
-#define MX7_DDRC_PWRCTL			0x307a0030
-#define MX7_DDRC_PWRTMG			0x307a0034
-#define MX7_DDRC_HWLPCTL		0x307a0038
-#define MX7_DDRC_RFSHCTL0		0x307a0050
-#define MX7_DDRC_RFSHCTL1		0x307a0054
-#define MX7_DDRC_RFSHCTL3		0x307a0060
-#define MX7_DDRC_RFSHTMG		0x307a0064
-#define MX7_DDRC_INIT0			0x307a00d0
-#define MX7_DDRC_INIT1			0x307a00d4
-#define MX7_DDRC_INIT2			0x307a00d8
-#define MX7_DDRC_INIT3			0x307a00dc
-#define MX7_DDRC_INIT4			0x307a00e0
-#define MX7_DDRC_INIT5			0x307a00e4
-#define MX7_DDRC_RANKCTL		0x307a00f4
-#define MX7_DDRC_DRAMTMG0		0x307a0100
-#define MX7_DDRC_DRAMTMG1		0x307a0104
-#define MX7_DDRC_DRAMTMG2		0x307a0108
-#define MX7_DDRC_DRAMTMG3		0x307a010c
-#define MX7_DDRC_DRAMTMG4		0x307a0110
-#define MX7_DDRC_DRAMTMG5		0x307a0114
-#define MX7_DDRC_DRAMTMG6		0x307a0118
-#define MX7_DDRC_DRAMTMG7		0x307a011c
-#define MX7_DDRC_DRAMTMG8		0x307a0120
-#define MX7_DDRC_ZQCTL0			0x307a0180
-#define MX7_DDRC_ZQCTL1			0x307a0184
-#define MX7_DDRC_ZQCTL2			0x307a0188
-#define MX7_DDRC_ZQSTAT			0x307a018c
-#define MX7_DDRC_DFITMG0		0x307a0190
-#define MX7_DDRC_DFITMG1		0x307a0194
-#define MX7_DDRC_DFILPCFG0		0x307a0198
-#define MX7_DDRC_DFIUPD0		0x307a01a0
-#define MX7_DDRC_DFIUPD1		0x307a01a4
-#define MX7_DDRC_DFIUPD2		0x307a01a8
-#define MX7_DDRC_DFIUPD3		0x307a01ac
-#define MX7_DDRC_DFIMISC		0x307a01b0
-#define MX7_DDRC_ADDRMAP0		0x307a0200
-#define MX7_DDRC_ADDRMAP1		0x307a0204
-#define MX7_DDRC_ADDRMAP2		0x307a0208
-#define MX7_DDRC_ADDRMAP3		0x307a020c
-#define MX7_DDRC_ADDRMAP4		0x307a0210
-#define MX7_DDRC_ADDRMAP5		0x307a0214
-#define MX7_DDRC_ADDRMAP6		0x307a0218
-#define MX7_DDRC_ODTCFG			0x307a0240
-#define MX7_DDRC_ODTMAP			0x307a0244
-#define MX7_DDRC_SCHED			0x307a0250
-#define MX7_DDRC_SCHED1			0x307a0254
-#define MX7_DDRC_PERFHPR1		0x307a025c
-#define MX7_DDRC_PERFLPR1		0x307a0264
-#define MX7_DDRC_PERFWR1		0x307a026c
-#define MX7_DDRC_PERFVPR1		0x307a0274
-#define MX7_DDRC_PERFVPW1		0x307a0278
-#define MX7_DDRC_DBG0			0x307a0300
-#define MX7_DDRC_DBG1			0x307a0304
-#define MX7_DDRC_DBGCAM			0x307a0308
-#define MX7_DDRC_DBGCMD			0x307a030c
-#define MX7_DDRC_DBGSTAT		0x307a0310
-#define MX7_DDRC_SWCTL			0x307a0320
-#define MX7_DDRC_SWSTAT			0x307a0324
-
-#define MX7_DDRC_MP_PSTAT		0x307a03fc
-#define MX7_DDRC_MP_PCCFG		0x307a0400
-#define MX7_DDRC_MP_PCFGR_0		0x307a0404
-#define MX7_DDRC_MP_PCFGW_0		0x307a0408
-#define MX7_DDRC_MP_PCFGIDMASKCH_00	0x307a0410
-#define MX7_DDRC_MP_PCFGIDVALUECH_00	0x307a0414
-#define MX7_DDRC_MP_PCFGIDMASKCH_10	0x307a0418
-#define MX7_DDRC_MP_PCFGIDVALUECH_10	0x307a041c
-#define MX7_DDRC_MP_PCFGIDMASKCH_20	0x307a0420
-#define MX7_DDRC_MP_PCFGIDVALUECH_20	0x307a0424
-#define MX7_DDRC_MP_PCFGIDMASKCH_30	0x307a0428
-#define MX7_DDRC_MP_PCFGIDVALUECH_30	0x307a042c
-#define MX7_DDRC_MP_PCFGIDMASKCH_40	0x307a0430
-#define MX7_DDRC_MP_PCFGIDVALUECH_40	0x307a0434
-#define MX7_DDRC_MP_PCFGIDMASKCH_50	0x307a0438
-#define MX7_DDRC_MP_PCFGIDVALUECH_50	0x307a043c
-#define MX7_DDRC_MP_PCFGIDMASKCH_60	0x307a0440
-#define MX7_DDRC_MP_PCFGIDVALUECH_60	0x307a0444
-#define MX7_DDRC_MP_PCFGIDMASKCH_70	0x307a0448
-#define MX7_DDRC_MP_PCFGIDVALUECH_70	0x307a044c
-#define MX7_DDRC_MP_PCFGIDMASKCH_80	0x307a0450
-#define MX7_DDRC_MP_PCFGIDVALUECH_80	0x307a0454
-#define MX7_DDRC_MP_PCFGIDMASKCH_90	0x307a0458
-#define MX7_DDRC_MP_PCFGIDVALUECH_90	0x307a045c
-#define MX7_DDRC_MP_PCFGIDMASKCH_100	0x307a0460
-#define MX7_DDRC_MP_PCFGIDVALUECH_100	0x307a0464
-#define MX7_DDRC_MP_PCFGIDMASKCH_110	0x307a0468
-#define MX7_DDRC_MP_PCFGIDVALUECH_110	0x307a046c
-#define MX7_DDRC_MP_PCFGIDMASKCH_120	0x307a0470
-#define MX7_DDRC_MP_PCFGIDVALUECH_120	0x307a0474
-#define MX7_DDRC_MP_PCFGIDMASKCH_130	0x307a0478
-#define MX7_DDRC_MP_PCFGIDVALUECH_130	0x307a047c
-#define MX7_DDRC_MP_PCFGIDMASKCH_140	0x307a0480
-#define MX7_DDRC_MP_PCFGIDVALUECH_140	0x307a0484
-#define MX7_DDRC_MP_PCFGIDMASKCH_150	0x307a0488
-#define MX7_DDRC_MP_PCFGIDVALUECH_150	0x307a048c
-#define MX7_DDRC_MP_PCTRL_0		0x307a0490
-#define MX7_DDRC_MP_PCFGQOS0_0		0x307a0494
-#define MX7_DDRC_MP_PCFGQOS1_0		0x307a0498
-#define MX7_DDRC_MP_PCFGWQOS0_0		0x307a049c
-#define MX7_DDRC_MP_PCFGWQOS1_0		0x307a04a0
-#define MX7_DDRC_MP_SARBASE0		0x307a0f04
-#define MX7_DDRC_MP_SARSIZE0		0x307a0f08
-#define MX7_DDRC_MP_SARBASE1		0x307a0f0c
-#define MX7_DDRC_MP_SARSIZE1		0x307a0f10
-#define MX7_DDRC_MP_SARBASE2		0x307a0f14
-#define MX7_DDRC_MP_SARSIZE2		0x307a0f18
-#define MX7_DDRC_MP_SARBASE3		0x307a0f1c
-#define MX7_DDRC_MP_SARSIZE3		0x307a0f20
-
-#define MX7_DDR_PHY_PHY_CON0		0x30790000
-#define MX7_DDR_PHY_PHY_CON1		0x30790004
-#define MX7_DDR_PHY_PHY_CON2		0x30790008
-#define MX7_DDR_PHY_PHY_CON3		0x3079000c
-#define MX7_DDR_PHY_PHY_CON4		0x30790010
-#define MX7_DDR_PHY_PHY_CON5		0x30790014
-#define MX7_DDR_PHY_LP_CON0		0x30790018
-#define MX7_DDR_PHY_RODT_CON0		0x3079001c
-#define MX7_DDR_PHY_OFFSET_RD_CON0	0x30790020
-#define MX7_DDR_PHY_OFFSET_WR_CON0	0x30790030
-#define MX7_DDR_PHY_GATE_CODE_CON0	0x30790040
-#define MX7_DDR_PHY_SHIFTC_CON0		0x3079004c
-#define MX7_DDR_PHY_CMD_SDLL_CON0	0x30790050
-#define MX7_DDR_PHY_LVL_CON0		0x3079006c
-#define MX7_DDR_PHY_LVL_CON3		0x30790078
-#define MX7_DDR_PHY_CMD_DESKEW_CON0	0x3079007c
-#define MX7_DDR_PHY_CMD_DESKEW_CON1	0x30790080
-#define MX7_DDR_PHY_CMD_DESKEW_CON2	0x30790084
-#define MX7_DDR_PHY_CMD_DESKEW_CON3	0x30790088
-#define MX7_DDR_PHY_CMD_DESKEW_CON4	0x30790094
-#define MX7_DDR_PHY_DRVDS_CON0		0x3079009c
-#define MX7_DDR_PHY_MDLL_CON0		0x307900b0
-#define MX7_DDR_PHY_MDLL_CON1		0x307900b4
-#define MX7_DDR_PHY_ZQ_CON0		0x307900c0
-#define MX7_DDR_PHY_ZQ_CON1		0x307900c4
-#define MX7_DDR_PHY_ZQ_CON2		0x307900c8
-#define MX7_DDR_PHY_RD_DESKEW_CON0	0x30790190
-#define MX7_DDR_PHY_RD_DESKEW_CON3	0x3079019c
-#define MX7_DDR_PHY_RD_DESKEW_CON6	0x307901a8
-#define MX7_DDR_PHY_RD_DESKEW_CON9	0x307901b4
-#define MX7_DDR_PHY_RD_DESKEW_CON12	0x307901c0
-#define MX7_DDR_PHY_RD_DESKEW_CON15	0x307901cc
-#define MX7_DDR_PHY_RD_DESKEW_CON18	0x307901d8
-#define MX7_DDR_PHY_RD_DESKEW_CON21	0x307901e4
-#define MX7_DDR_PHY_WR_DESKEW_CON0	0x307901f0
-#define MX7_DDR_PHY_WR_DESKEW_CON3	0x307901fc
-#define MX7_DDR_PHY_WR_DESKEW_CON6	0x30790208
-#define MX7_DDR_PHY_WR_DESKEW_CON9	0x30790214
-#define MX7_DDR_PHY_WR_DESKEW_CON12	0x30790220
-#define MX7_DDR_PHY_WR_DESKEW_CON15	0x3079022c
-#define MX7_DDR_PHY_WR_DESKEW_CON18	0x30790238
-#define MX7_DDR_PHY_WR_DESKEW_CON21	0x30790244
-#define MX7_DDR_PHY_DM_DESKEW_CON	0x30790250
-#define MX7_DDR_PHY_RDATA0		0x307903a0
-#define MX7_DDR_PHY_STAT0		0x307903ac
diff --git a/arch/arm/mach-imx/include/mach/imx7-regs.h b/arch/arm/mach-imx/include/mach/imx7-regs.h
deleted file mode 100644
index 21e2830b97..0000000000
--- a/arch/arm/mach-imx/include/mach/imx7-regs.h
+++ /dev/null
@@ -1,121 +0,0 @@
-#ifndef __MACH_IMX7_REGS_H
-#define __MACH_IMX7_REGS_H
-
-/* Defines for Blocks connected via AIPS */
-#define MX7_AIPS1_BASE_ADDR		0x30000000
-#define MX7_AIPS2_BASE_ADDR		0x30400000
-#define MX7_AIPS3_BASE_ADDR		0x30800000
-
-/* ATZ#1- On Platform */
-#define MX7_DAP_BASE_ADDR		(MX7_AIPS1_BASE_ADDR)
-#define MX7_AIPS1_CONFIG_BASE_ADDR	(MX7_AIPS1_BASE_ADDR + 0x1F0000)
-
-/* ATZ#1- Off Platform */
-#define MX7_GPIO1_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x200000)
-#define MX7_GPIO2_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x210000)
-#define MX7_GPIO3_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x220000)
-#define MX7_GPIO4_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x230000)
-#define MX7_GPIO5_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x240000)
-#define MX7_GPIO6_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x250000)
-#define MX7_GPIO7_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x260000)
-#define MX7_IOMUXC_LPSR_GPR_BASE_ADDR	(MX7_AIPS1_BASE_ADDR + 0x270000)
-#define MX7_WDOG1_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x280000)
-#define MX7_WDOG2_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x290000)
-#define MX7_WDOG3_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x2A0000)
-#define MX7_WDOG4_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x2B0000)
-#define MX7_IOMUXC_LPSR_BASE_ADDR	(MX7_AIPS1_BASE_ADDR + 0x2C0000)
-#define MX7_GPT1_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x2D0000)
-#define MX7_GPT2_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x2E0000)
-#define MX7_GPT3_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x2F0000)
-#define MX7_GPT4_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x300000)
-#define MX7_ROMCP_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x310000)
-#define MX7_KPP_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x320000)
-#define MX7_IOMUXC_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x330000)
-#define MX7_IOMUXC_GPR_BASE_ADDR	(MX7_AIPS1_BASE_ADDR + 0x340000)
-#define MX7_OCOTP_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x350000)
-#define MX7_ANATOP_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x360000)
-#define MX7_SNVS_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x370000)
-#define MX7_CCM_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x380000)
-#define MX7_SRC_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x390000)
-#define MX7_GPC_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x3A0000)
-#define MX7_SEMAPHORE1_BASE_ADDR	(MX7_AIPS1_BASE_ADDR + 0x3B0000)
-#define MX7_SEMAPHORE2_BASE_ADDR	(MX7_AIPS1_BASE_ADDR + 0x3C0000)
-#define MX7_RDC_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x3D0000)
-#define MX7_CSU_BASE_ADDR		(MX7_AIPS1_BASE_ADDR + 0x3E0000)
-
-/* ATZ#2- On Platform */
-#define MX7_AIPS2_CONFIG_BASE_ADDR	(MX7_AIPS2_BASE_ADDR + 0x1F0000)
-
-/* ATZ#2- Off Platform */
-#define MX7_ADC1_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x230000)
-#define MX7_ADC2_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x230000)
-#define MX7_ECSPI4_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x230000)
-#define MX7_FTM1_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x240000)
-#define MX7_FTM2_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x250000)
-#define MX7_PWM1_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x260000)
-#define MX7_PWM2_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x270000)
-#define MX7_PWM3_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x280000)
-#define MX7_PWM4_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x290000)
-#define MX7_SYSCNT_RD_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x2A0000)
-#define MX7_SYSCNT_CMP_BASE_ADDR	(MX7_AIPS2_BASE_ADDR + 0x2B0000)
-#define MX7_SYSCNT_CTRL_BASE_ADDR	(MX7_AIPS2_BASE_ADDR + 0x2C0000)
-#define MX7_PCIE_PHY_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x2D0000)
-#define MX7_EPDC_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x2F0000)
-#define MX7_PXP_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x300000)
-#define MX7_CSI_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x310000)
-#define MX7_LCDIF_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x330000)
-#define MX7_MIPI_CSI_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x350000)
-#define MX7_MIPI_DSI_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x360000)
-#define MX7_TZASC_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x380000)
-#define MX7_DDRPHY_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x390000)
-#define MX7_DDRC_BASE_ADDR		(MX7_AIPS2_BASE_ADDR + 0x3A0000)
-#define MX7_IP2APB_PERFMON1_BASE_ADDR	(MX7_AIPS2_BASE_ADDR + 0x3C0000)
-#define MX7_IP2APB_PERFMON2_BASE_ADDR	(MX7_AIPS2_BASE_ADDR + 0x3D0000)
-#define MX7_AXI_DEBUG_MON_BASE_ADDR	(MX7_AIPS2_BASE_ADDR + 0x3E0000)
-
-/* ATZ#3- On Platform */
-#define MX7_ECSPI1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x20000)
-#define MX7_ECSPI2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x30000)
-#define MX7_ECSPI3_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x40000)
-#define MX7_UART1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x60000)
-#define MX7_UART2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x90000)
-#define MX7_UART3_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x80000)
-#define MX7_SAI1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0xA0000)
-#define MX7_SAI2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0xB0000)
-#define MX7_SAI3_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0xC0000)
-#define MX7_SPBA_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x90000)
-#define MX7_CAAM_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x100000)
-#define MX7_AIPS3_CONFIG_BASE_ADDR	(MX7_AIPS3_BASE_ADDR + 0x1F0000)
-
-/* ATZ#3- Off Platform */
-#define MX7_CAN1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x200000)
-#define MX7_CAN2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x210000)
-#define MX7_I2C1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x220000)
-#define MX7_I2C2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x230000)
-#define MX7_I2C3_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x240000)
-#define MX7_I2C4_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x250000)
-#define MX7_UART4_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x260000)
-#define MX7_UART5_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x270000)
-#define MX7_UART6_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x280000)
-#define MX7_UART7_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x290000)
-#define MX7_MU_A_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x2A0000)
-#define MX7_MU_B_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x2B0000)
-#define MX7_SEM_HS_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x2C0000)
-#define MX7_USBOH2_PL301_BASE_ADDR	(MX7_AIPS3_BASE_ADDR + 0x2D0000)
-#define MX7_OTG1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x310000)
-#define MX7_OTG2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x320000)
-#define MX7_USBOH3_USB_BASE_ADDR	(MX7_AIPS3_BASE_ADDR + 0x330000)
-#define MX7_USDHC1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x340000)
-#define MX7_USDHC2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x350000)
-#define MX7_USDHC3_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x360000)
-#define MX7_SIM1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x390000)
-#define MX7_SIM2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x3A0000)
-#define MX7_QSPI_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x3B0000)
-#define MX7_WEIM_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x3C0000)
-#define MX7_SDMA_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x3D0000)
-#define MX7_ENET1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x3E0000)
-#define MX7_ENET2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x3F0000)
-
-#define MX7_DDR_BASE_ADDR		0x80000000
-
-#endif /* __MACH_IMX7_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx7.h b/arch/arm/mach-imx/include/mach/imx7.h
deleted file mode 100644
index 8518935468..0000000000
--- a/arch/arm/mach-imx/include/mach/imx7.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef __MACH_IMX7_H
-#define __MACH_IMX7_H
-
-#include <io.h>
-#include <mach/generic.h>
-#include <mach/imx7-regs.h>
-#include <mach/revision.h>
-
-void imx7_init_lowlevel(void);
-
-#define ANADIG_DIGPROG_IMX7	0x800
-
-#define IMX7_CPUTYPE_IMX7S	0x71
-#define IMX7_CPUTYPE_IMX7D	0x72
-
-static inline int __imx7_cpu_type(void)
-{
-	void __iomem *ocotp = IOMEM(MX7_OCOTP_BASE_ADDR);
-
-	if (readl(ocotp + 0x450) & 1)
-		return IMX7_CPUTYPE_IMX7S;
-	else
-		return IMX7_CPUTYPE_IMX7D;
-}
-
-static inline int imx7_cpu_type(void)
-{
-	if (!cpu_is_mx7())
-		return 0;
-
-	return __imx7_cpu_type();
-}
-
-static inline int imx7_cpu_revision(void)
-{
-	if (!cpu_is_mx7())
-		return IMX_CHIP_REV_UNKNOWN;
-
-	/* register value has the format of the IMX_CHIP_REV_* macros */
-	return readl(MX7_ANATOP_BASE_ADDR + ANADIG_DIGPROG_IMX7) & 0xff;
-}
-
-#define DEFINE_MX7_CPU_TYPE(str, type)					\
-	static inline int cpu_mx7_is_##str(void)			\
-	{								\
-		return __imx7_cpu_type() == type;			\
-	}								\
-									\
-	static inline int cpu_is_##str(void)				\
-	{								\
-		if (!cpu_is_mx7())					\
-			return 0;					\
-		return cpu_mx7_is_##str();				\
-	}
-
-DEFINE_MX7_CPU_TYPE(mx7s, IMX7_CPUTYPE_IMX7S);
-DEFINE_MX7_CPU_TYPE(mx7d, IMX7_CPUTYPE_IMX7D);
-
-#endif /* __MACH_IMX7_H */
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
deleted file mode 100644
index 743ed6cda0..0000000000
--- a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef __MACH_IMX8_CCM_REGS_H__
-#define __MACH_IMX8_CCM_REGS_H__
-
-#include <mach/imx8mq-regs.h>
-
-#define IMX8M_CCM_CCGR_DDR1	5
-#define IMX8M_CCM_CCGR_I2C1	23
-#define IMX8M_CCM_CCGR_I2C2	24
-#define IMX8M_CCM_CCGR_I2C3	25
-#define IMX8M_CCM_CCGR_I2C4	26
-#define IMX8M_CCM_CCGR_SCTR	57
-#define IMX8M_CCM_CCGR_UART1	73
-#define IMX8M_CCM_CCGR_UART2 	74
-#define IMX8M_CCM_CCGR_UART3	75
-#define IMX8M_CCM_CCGR_UART4	76
-#define IMX8M_CCM_CCGR_GIC	92
-
-/*
- * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad
- * Applications Processor Reference Manual
- */
-#define IMX8M_ARM_A53_CLK_ROOT		0
-#define IMX8M_DRAM_SEL_CFG		48
-#define IMX8M_DRAM_ALT_CLK_ROOT		64
-#define IMX8M_DRAM_APB_CLK_ROOT		65
-#define IMX8M_UART1_CLK_ROOT		94
-#define IMX8M_UART2_CLK_ROOT		95
-#define IMX8M_UART3_CLK_ROOT		96
-#define IMX8M_UART4_CLK_ROOT		97
-#define IMX8M_GIC_CLK_ROOT		100
-#define IMX8M_UART1_CLK_ROOT__25M_REF_CLK IMX8M_CCM_TARGET_ROOTn_MUX(0b000)
-
-/* 0 <= n <= 190 */
-#define IMX8M_CCM_CCGRn_SET(n)	(0x4004 + 16 * (n))
-#define IMX8M_CCM_CCGRn_CLR(n)	(0x4008 + 16 * (n))
-
-/* 0 <= n <= 120 */
-#define IMX8M_CCM_TARGET_ROOTn(n)	(0x8000 + 128 * (n))
-
-#define IMX8M_CCM_TARGET_ROOTn_POST_DIV(n)	((n) & 0x0000003f)
-#define IMX8M_CCM_TARGET_ROOTn_PRE_DIV(n)	(((n) << 16) & 0x00070000)
-#define IMX8M_CCM_TARGET_ROOTn_MUX(x)		((x) << 24)
-#define IMX8M_CCM_TARGET_ROOTn_ENABLE		BIT(28)
-
-#define IMX8M_CCM_CCGR_SETTINGn(n, s)  ((s) << ((n) * 4))
-#define IMX8M_CCM_CCGR_SETTINGn_NOT_NEEDED(n)		IMX8M_CCM_CCGR_SETTINGn(n, 0b00)
-#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN(n)		IMX8M_CCM_CCGR_SETTINGn(n, 0b01)
-#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n)	IMX8M_CCM_CCGR_SETTINGn(n, 0b10)
-#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n)		IMX8M_CCM_CCGR_SETTINGn(n, 0b11)
-
-void imx8m_early_setup_uart_clock(void);
-void imx8mm_early_clock_init(void);
-void imx8m_clock_set_target_val(int clock_id, u32 val);
-void imx8m_ccgr_clock_enable(int index);
-void imx8m_ccgr_clock_disable(int index);
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/imx8m-regs.h b/arch/arm/mach-imx/include/mach/imx8m-regs.h
deleted file mode 100644
index e5f466c291..0000000000
--- a/arch/arm/mach-imx/include/mach/imx8m-regs.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __MACH_IMX8M_REGS_H
-#define __MACH_IMX8M_REGS_H
-
-#define MX8M_GPIO1_BASE_ADDR		0X30200000
-#define MX8M_GPIO2_BASE_ADDR		0x30210000
-#define MX8M_GPIO3_BASE_ADDR		0x30220000
-#define MX8M_GPIO4_BASE_ADDR		0x30230000
-#define MX8M_GPIO5_BASE_ADDR		0x30240000
-#define MX8M_WDOG1_BASE_ADDR		0x30280000
-#define MX8M_WDOG2_BASE_ADDR		0x30290000
-#define MX8M_WDOG3_BASE_ADDR		0x302A0000
-#define MX8M_IOMUXC_BASE_ADDR		0x30330000
-#define MX8M_IOMUXC_GPR_BASE_ADDR	0x30340000
-#define MX8M_OCOTP_BASE_ADDR		0x30350000
-#define MX8M_ANATOP_BASE_ADDR		0x30360000
-#define MX8M_CCM_BASE_ADDR		0x30380000
-#define MX8M_SRC_BASE_ADDR		0x30390000
-#define MX8M_SRC_DDRC_RCR_ADDR		0x30391000
-#define MX8M_GPC_BASE_ADDR		0x303A0000
-#define MX8M_SYSCNT_CTRL_BASE_ADDR	0x306C0000
-#define MX8M_UART1_BASE_ADDR		0x30860000
-#define MX8M_UART3_BASE_ADDR		0x30880000
-#define MX8M_UART2_BASE_ADDR		0x30890000
-#define MX8M_I2C1_BASE_ADDR		0x30A20000
-#define MX8M_I2C2_BASE_ADDR		0x30A30000
-#define MX8M_I2C3_BASE_ADDR		0x30A40000
-#define MX8M_I2C4_BASE_ADDR		0x30A50000
-#define MX8M_UART4_BASE_ADDR		0x30A60000
-#define MX8M_USDHC1_BASE_ADDR		0x30B40000
-#define MX8M_USDHC2_BASE_ADDR		0x30B50000
-#define MX8M_DDRC_PHY_BASE_ADDR		0x3c000000
-#define MX8M_DDRC_DDR_SS_GPR0		(MX8M_DDRC_PHY_BASE_ADDR + 0x01000000)
-#define MX8M_DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
-#define MX8M_DDRC_CTL_BASE_ADDR		MX8M_DDRC_IPS_BASE_ADDR(0)
-#define MX8M_DDR_CSD1_BASE_ADDR		0x40000000
-
-#endif /* __MACH_IMX8M_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx8mm-regs.h b/arch/arm/mach-imx/include/mach/imx8mm-regs.h
deleted file mode 100644
index e10ca42d2d..0000000000
--- a/arch/arm/mach-imx/include/mach/imx8mm-regs.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef __MACH_IMX8MM_REGS_H
-#define __MACH_IMX8MM_REGS_H
-
-#include <mach/imx8m-regs.h>
-
-#define MX8MM_M4_BOOTROM_BASE_ADDR	0x007e0000
-
-#define MX8MM_GPIO1_BASE_ADDR		0x30200000
-#define MX8MM_GPIO2_BASE_ADDR		0x30210000
-#define MX8MM_GPIO3_BASE_ADDR		0x30220000
-#define MX8MM_GPIO4_BASE_ADDR		0x30230000
-#define MX8MM_GPIO5_BASE_ADDR		0x30240000
-#define MX8MM_WDOG1_BASE_ADDR		0x30280000
-#define MX8MM_WDOG2_BASE_ADDR		0x30290000
-#define MX8MM_WDOG3_BASE_ADDR		0x302a0000
-#define MX8MM_IOMUXC_BASE_ADDR		0x30330000
-#define MX8MM_IOMUXC_GPR_BASE_ADDR	0x30340000
-#define MX8MM_OCOTP_BASE_ADDR		0x30350000
-#define MX8MM_ANATOP_BASE_ADDR		0x30360000
-#define MX8MM_CCM_BASE_ADDR		0x30380000
-#define MX8MM_SRC_BASE_ADDR		0x30390000
-#define MX8MM_GPC_BASE_ADDR		0x303a0000
-#define MX8MM_SYSCNT_RD_BASE_ADDR	0x306a0000
-#define MX8MM_SYSCNT_CMP_BASE_ADDR	0x306b0000
-#define MX8MM_SYSCNT_CTRL_BASE_ADDR	0x306c0000
-#define MX8MM_I2C1_BASE_ADDR		0x30a20000
-#define MX8MM_I2C2_BASE_ADDR		0x30a30000
-#define MX8MM_I2C3_BASE_ADDR		0x30a40000
-#define MX8MM_I2C4_BASE_ADDR		0x30a50000
-#define MX8MM_USDHC1_BASE_ADDR		0x30b40000
-#define MX8MM_USDHC2_BASE_ADDR		0x30b50000
-#define MX8MM_USDHC3_BASE_ADDR		0x30b60000
-#define MX8MM_USB1_BASE_ADDR		0x32e40000
-#define MX8MM_USB2_BASE_ADDR		0x32e50000
-#define MX8MM_TZASC_BASE_ADDR		0x32f80000
-#define MX8MM_SRC_IPS_BASE_ADDR		0x30390000
-#define MX8MM_SRC_DDRC_RCR_ADDR		0x30391000
-#define MX8MM_SRC_DDRC2_RCR_ADDR	0x30391004
-#define MX8MM_DDRC_DDR_SS_GPR0		0x3d000000
-#define MX8MM_DDR_CSD1_BASE_ADDR	0x40000000
-
-#endif /* __MACH_IMX8MM_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx8mp-regs.h b/arch/arm/mach-imx/include/mach/imx8mp-regs.h
deleted file mode 100644
index ad53abbc9d..0000000000
--- a/arch/arm/mach-imx/include/mach/imx8mp-regs.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef __MACH_IMX8MP_REGS_H
-#define __MACH_IMX8MP_REGS_H
-
-#include <mach/imx8m-regs.h>
-
-#define MX8MP_M4_BOOTROM_BASE_ADDR	0x007e0000
-
-#define MX8MP_GPIO1_BASE_ADDR		0x30200000
-#define MX8MP_GPIO2_BASE_ADDR		0x30210000
-#define MX8MP_GPIO3_BASE_ADDR		0x30220000
-#define MX8MP_GPIO4_BASE_ADDR		0x30230000
-#define MX8MP_GPIO5_BASE_ADDR		0x30240000
-#define MX8MP_WDOG1_BASE_ADDR		0x30280000
-#define MX8MP_WDOG2_BASE_ADDR		0x30290000
-#define MX8MP_WDOG3_BASE_ADDR		0x302a0000
-#define MX8MP_IOMUXC_BASE_ADDR		0x30330000
-#define MX8MP_IOMUXC_GPR_BASE_ADDR	0x30340000
-#define MX8MP_OCOTP_BASE_ADDR		0x30350000
-#define MX8MP_ANATOP_BASE_ADDR		0x30360000
-#define MX8MP_CCM_BASE_ADDR		0x30380000
-#define MX8MP_SRC_BASE_ADDR		0x30390000
-#define MX8MP_GPC_BASE_ADDR		0x303a0000
-#define MX8MP_SYSCNT_RD_BASE_ADDR	0x306a0000
-#define MX8MP_SYSCNT_CMP_BASE_ADDR	0x306b0000
-#define MX8MP_SYSCNT_CTRL_BASE_ADDR	0x306c0000
-#define MX8MP_I2C1_BASE_ADDR		0x30a20000
-#define MX8MP_I2C2_BASE_ADDR		0x30a30000
-#define MX8MP_I2C3_BASE_ADDR		0x30a40000
-#define MX8MP_I2C4_BASE_ADDR		0x30a50000
-#define MX8MP_USDHC1_BASE_ADDR		0x30b40000
-#define MX8MP_USDHC2_BASE_ADDR		0x30b50000
-#define MX8MP_USDHC3_BASE_ADDR		0x30b60000
-#define MX8MP_USB1_BASE_ADDR		0x32e40000
-#define MX8MP_USB2_BASE_ADDR		0x32e50000
-#define MX8MP_TZASC_BASE_ADDR		0x32f80000
-#define MX8MP_SRC_IPS_BASE_ADDR		0x30390000
-#define MX8MP_SRC_DDRC_RCR_ADDR		0x30391000
-#define MX8MP_SRC_DDRC2_RCR_ADDR	0x30391004
-#define MX8MP_DDRC_DDR_SS_GPR0		0x3d000000
-#define MX8MP_DDR_CSD1_BASE_ADDR	0x40000000
-
-#endif /* __MACH_IMX8MP_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx8mq-regs.h b/arch/arm/mach-imx/include/mach/imx8mq-regs.h
deleted file mode 100644
index 50d02ba6a2..0000000000
--- a/arch/arm/mach-imx/include/mach/imx8mq-regs.h
+++ /dev/null
@@ -1,121 +0,0 @@
-#ifndef __MACH_IMX8MQ_REGS_H
-#define __MACH_IMX8MQ_REGS_H
-
-#include <mach/imx8m-regs.h>
-
-#define MX8MQ_M4_BOOTROM_BASE_ADDR	0x007E0000
-
-#define MX8MQ_SAI1_BASE_ADDR		0x30010000
-#define MX8MQ_SAI6_BASE_ADDR		0x30030000
-#define MX8MQ_SAI5_BASE_ADDR		0x30040000
-#define MX8MQ_SAI4_BASE_ADDR		0x30050000
-#define MX8MQ_SPBA2_BASE_ADDR		0x300F0000
-#define MX8MQ_AIPS1_BASE_ADDR		0x301F0000
-#define MX8MQ_GPIO1_BASE_ADDR		0X30200000
-#define MX8MQ_GPIO2_BASE_ADDR		0x30210000
-#define MX8MQ_GPIO3_BASE_ADDR		0x30220000
-#define MX8MQ_GPIO4_BASE_ADDR		0x30230000
-#define MX8MQ_GPIO5_BASE_ADDR		0x30240000
-#define MX8MQ_ANA_TSENSOR_BASE_ADDR	0x30260000
-#define MX8MQ_ANA_OSC_BASE_ADDR		0x30270000
-#define MX8MQ_WDOG1_BASE_ADDR		0x30280000
-#define MX8MQ_WDOG2_BASE_ADDR		0x30290000
-#define MX8MQ_WDOG3_BASE_ADDR		0x302A0000
-#define MX8MQ_SDMA2_BASE_ADDR		0x302C0000
-#define MX8MQ_GPT1_BASE_ADDR		0x302D0000
-#define MX8MQ_GPT2_BASE_ADDR		0x302E0000
-#define MX8MQ_GPT3_BASE_ADDR		0x302F0000
-#define MX8MQ_ROMCP_BASE_ADDR		0x30310000
-#define MX8MQ_LCDIF_BASE_ADDR		0x30320000
-#define MX8MQ_IOMUXC_BASE_ADDR		0x30330000
-#define MX8MQ_IOMUXC_GPR_BASE_ADDR	0x30340000
-#define MX8MQ_OCOTP_BASE_ADDR		0x30350000
-#define MX8MQ_ANATOP_BASE_ADDR		0x30360000
-#define MX8MQ_SNVS_HP_BASE_ADDR		0x30370000
-#define MX8MQ_CCM_BASE_ADDR		0x30380000
-#define MX8MQ_SRC_BASE_ADDR		0x30390000
-#define MX8MQ_GPC_BASE_ADDR		0x303A0000
-#define MX8MQ_SEMAPHORE1_BASE_ADDR	0x303B0000
-#define MX8MQ_SEMAPHORE2_BASE_ADDR	0x303C0000
-#define MX8MQ_RDC_BASE_ADDR		0x303D0000
-#define MX8MQ_CSU_BASE_ADDR		0x303E0000
-
-#define MX8MQ_AIPS2_BASE_ADDR		0x305F0000
-#define MX8MQ_PWM1_BASE_ADDR		0x30660000
-#define MX8MQ_PWM2_BASE_ADDR		0x30670000
-#define MX8MQ_PWM3_BASE_ADDR		0x30680000
-#define MX8MQ_PWM4_BASE_ADDR		0x30690000
-#define MX8MQ_SYSCNT_RD_BASE_ADDR	0x306A0000
-#define MX8MQ_SYSCNT_CMP_BASE_ADDR	0x306B0000
-#define MX8MQ_SYSCNT_CTRL_BASE_ADDR	0x306C0000
-#define MX8MQ_GPT6_BASE_ADDR		0x306E0000
-#define MX8MQ_GPT5_BASE_ADDR		0x306F0000
-#define MX8MQ_GPT4_BASE_ADDR		0x30700000
-#define MX8MQ_PERFMON1_BASE_ADDR	0x307C0000
-#define MX8MQ_PERFMON2_BASE_ADDR	0x307D0000
-#define MX8MQ_QOSC_BASE_ADDR		0x307F0000
-
-#define MX8MQ_SPDIF1_BASE_ADDR		0x30810000
-#define MX8MQ_ECSPI1_BASE_ADDR		0x30820000
-#define MX8MQ_ECSPI2_BASE_ADDR		0x30830000
-#define MX8MQ_ECSPI3_BASE_ADDR		0x30840000
-#define MX8MQ_SPDIF2_BASE_ADDR		0x308A0000
-#define MX8MQ_SAI2_BASE_ADDR		0x308B0000
-#define MX8MQ_SAI3_BASE_ADDR		0x308C0000
-#define MX8MQ_SPBA1_BASE_ADDR		0x308F0000
-#define MX8MQ_CAAM_BASE_ADDR		0x30900000
-#define MX8MQ_AIPS3_BASE_ADDR		0x309F0000
-#define MX8MQ_MIPI_PHY_BASE_ADDR	0x30A00000
-#define MX8MQ_MIPI_DSI_BASE_ADDR	0x30A10000
-#define MX8MQ_I2C1_BASE_ADDR		0x30A20000
-#define MX8MQ_I2C2_BASE_ADDR		0x30A30000
-#define MX8MQ_I2C3_BASE_ADDR		0x30A40000
-#define MX8MQ_I2C4_BASE_ADDR		0x30A50000
-#define MX8MQ_MIPI_CSI_BASE_ADDR	0x30A70000
-#define MX8MQ_MIPI_CSI_PHY1_BASE_ADDR	0x30A80000
-#define MX8MQ_CSI1_BASE_ADDR		0x30A90000
-#define MX8MQ_MU_A_BASE_ADDR		0x30AA0000
-#define MX8MQ_MU_B_BASE_ADDR		0x30AB0000
-#define MX8MQ_SEMAPHOR_HS_BASE_ADDR	0x30AC0000
-#define MX8MQ_USDHC1_BASE_ADDR		0x30B40000
-#define MX8MQ_USDHC2_BASE_ADDR		0x30B50000
-#define MX8MQ_MIPI_CS2_BASE_ADDR	0x30B60000
-#define MX8MQ_MIPI_CSI_PHY2_BASE_ADDR	0x30B70000
-#define MX8MQ_CSI2_BASE_ADDR		0x30B80000
-#define MX8MQ_QSPI0_BASE_ADDR		0x30BB0000
-#define MX8MQ_QSPI0_AMBA_BASE		0x08000000
-#define MX8MQ_SDMA1_BASE_ADDR		0x30BD0000
-#define MX8MQ_ENET1_BASE_ADDR		0x30BE0000
-
-#define MX8MQ_HDMI_CTRL_BASE_ADDR	0x32C00000
-#define MX8MQ_AIPS4_BASE_ADDR		0x32DF0000
-#define MX8MQ_DC1_BASE_ADDR		0x32E00000
-#define MX8MQ_DC2_BASE_ADDR		0x32E10000
-#define MX8MQ_DC3_BASE_ADDR		0x32E20000
-#define MX8MQ_HDMI_SEC_BASE_ADDR	0x32E40000
-#define MX8MQ_TZASC_BASE_ADDR		0x32F80000
-#define MX8MQ_MTR_BASE_ADDR		0x32FB0000
-#define MX8MQ_PLATFORM_CTRL_BASE_ADDR	0x32FE0000
-
-#define MX8MQ_MXS_APBH_BASE		0x33000000
-#define MX8MQ_MXS_GPMI_BASE		0x33002000
-#define MX8MQ_MXS_BCH_BASE		0x33004000
-
-#define MX8MQ_USB1_BASE_ADDR		0x38100000
-#define MX8MQ_USB2_BASE_ADDR		0x38200000
-#define MX8MQ_USB1_PHY_BASE_ADDR	0x381F0000
-#define MX8MQ_USB2_PHY_BASE_ADDR	0x382F0000
-
-#define MX8MQ_MXS_LCDIF_BASE		LCDIF_BASE_ADDR
-
-#define MX8MQ_SRC_IPS_BASE_ADDR		0x30390000
-#define MX8MQ_SRC_DDRC_RCR_ADDR		0x30391000
-#define MX8MQ_SRC_DDRC2_RCR_ADDR	0x30391004
-
-#define MX8MQ_DDRC_PHY_BASE_ADDR	0x3c000000
-#define MX8MQ_DDRC_DDR_SS_GPR0		(MX8MQ_DDRC_PHY_BASE_ADDR + 0x01000000)
-#define MX8MQ_DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
-#define MX8MQ_DDRC_CTL_BASE_ADDR	MX8MQ_DDRC_IPS_BASE_ADDR(0)
-#define MX8MQ_DDR_CSD1_BASE_ADDR	0x40000000
-
-#endif /* __MACH_IMX8MQ_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h
deleted file mode 100644
index 1494fd661f..0000000000
--- a/arch/arm/mach-imx/include/mach/imx8mq.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef __MACH_IMX8MQ_H
-#define __MACH_IMX8MQ_H
-
-#include <io.h>
-#include <mach/generic.h>
-#include <mach/imx8mq-regs.h>
-#include <mach/imx8mm-regs.h>
-#include <mach/imx8mp-regs.h>
-#include <mach/revision.h>
-#include <linux/bitfield.h>
-
-#define IMX8MQ_ROM_VERSION_A0	0x800
-#define IMX8MQ_ROM_VERSION_B0	0x83C
-#define IMX8MQ_OCOTP_VERSION_B1 0x40
-#define IMX8MQ_OCOTP_VERSION_B1_MAGIC	0xff0055aa
-
-#define MX8MQ_ANATOP_DIGPROG	0x6c
-#define MX8MM_ANATOP_DIGPROG	0x800
-#define MX8MP_ANATOP_DIGPROG	0x800
-
-#define DIGPROG_MAJOR	GENMASK(23, 8)
-#define DIGPROG_MINOR	GENMASK(7, 0)
-
-#define IMX8M_CPUTYPE_IMX8MQ	0x8240
-#define IMX8M_CPUTYPE_IMX8MM	0x8241
-#define IMX8M_CPUTYPE_IMX8MP	0x8243
-
-static inline int imx8mm_cpu_revision(void)
-{
-	void __iomem *anatop = IOMEM(MX8MM_ANATOP_BASE_ADDR);
-	uint32_t revision = FIELD_GET(DIGPROG_MINOR,
-				      readl(anatop + MX8MM_ANATOP_DIGPROG));
-	return revision;
-}
-
-static inline int imx8mp_cpu_revision(void)
-{
-	void __iomem *anatop = IOMEM(MX8MP_ANATOP_BASE_ADDR);
-	uint32_t revision = FIELD_GET(DIGPROG_MINOR,
-				      readl(anatop + MX8MP_ANATOP_DIGPROG));
-	return revision;
-}
-
-static inline int imx8mq_cpu_revision(void)
-{
-	void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
-	void __iomem *ocotp = IOMEM(MX8MQ_OCOTP_BASE_ADDR);
-	uint32_t revision = FIELD_GET(DIGPROG_MINOR,
-				      readl(anatop + MX8MQ_ANATOP_DIGPROG));
-	uint32_t rom_version;
-
-	if (revision != IMX_CHIP_REV_1_0)
-		return revision;
-	/*
-	 * For B1 chip we need to check OCOTP
-	 */
-	if (readl(ocotp + IMX8MQ_OCOTP_VERSION_B1) ==
-	    IMX8MQ_OCOTP_VERSION_B1_MAGIC)
-		return IMX_CHIP_REV_2_1;
-	/*
-	 * For B0 chip, the DIGPROG is not updated, still TO1.0.
-	 * we have to check ROM version further
-	 */
-	rom_version = readb(IOMEM(IMX8MQ_ROM_VERSION_A0));
-	if (rom_version != IMX_CHIP_REV_1_0) {
-		rom_version = readb(IOMEM(IMX8MQ_ROM_VERSION_B0));
-		if (rom_version >= IMX_CHIP_REV_2_0)
-			revision = IMX_CHIP_REV_2_0;
-	}
-
-	return revision;
-}
-
-u64 imx8m_uid(void);
-
-#endif /* __MACH_IMX8_H */
diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h
deleted file mode 100644
index 6d96f7c590..0000000000
--- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __MACH_IMX_CPU_TYPES_H
-#define __MACH_IMX_CPU_TYPES_H
-
-#define IMX_CPU_IMX1	1
-#define IMX_CPU_IMX21	21
-#define IMX_CPU_IMX25	25
-#define IMX_CPU_IMX27	27
-#define IMX_CPU_IMX31	31
-#define IMX_CPU_IMX35	35
-#define IMX_CPU_IMX50	50
-#define IMX_CPU_IMX51	51
-#define IMX_CPU_IMX53	53
-#define IMX_CPU_IMX6	6
-#define IMX_CPU_IMX7	7
-#define IMX_CPU_IMX8MQ	8
-#define IMX_CPU_IMX8MM  81
-#define IMX_CPU_IMX8MP  83
-#define IMX_CPU_VF610	610
-
-#endif /* __MACH_IMX_CPU_TYPES_H */
diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h
deleted file mode 100644
index 6df7a14dde..0000000000
--- a/arch/arm/mach-imx/include/mach/imxfb.h
+++ /dev/null
@@ -1,88 +0,0 @@
-#ifndef __MACH_IMXFB_H
-#define __MACH_IMXFB_H
-
-/*
- * This structure describes the machine which we are running on.
- */
-
-#include <fb.h>
-
-#define PCR_TFT		(1 << 31)
-#define PCR_COLOR	(1 << 30)
-#define PCR_PBSIZ_1	(0 << 28)
-#define PCR_PBSIZ_2	(1 << 28)
-#define PCR_PBSIZ_4	(2 << 28)
-#define PCR_PBSIZ_8	(3 << 28)
-#define PCR_BPIX_1	(0 << 25)
-#define PCR_BPIX_2	(1 << 25)
-#define PCR_BPIX_4	(2 << 25)
-#define PCR_BPIX_8	(3 << 25)
-#define PCR_BPIX_12	(4 << 25)
-#define PCR_BPIX_16	(5 << 25)
-#define PCR_BPIX_18	(6 << 25)
-#define PCR_PIXPOL	(1 << 24)
-#define PCR_FLMPOL	(1 << 23)
-#define PCR_LPPOL	(1 << 22)
-#define PCR_CLKPOL	(1 << 21)
-#define PCR_OEPOL	(1 << 20)
-#define PCR_SCLKIDLE	(1 << 19)
-#define PCR_END_SEL	(1 << 18)
-#define PCR_END_BYTE_SWAP (1 << 17)
-#define PCR_REV_VS	(1 << 16)
-#define PCR_ACD_SEL	(1 << 15)
-#define PCR_ACD(x)	(((x) & 0x7f) << 8)
-#define PCR_SCLK_SEL	(1 << 7)
-#define PCR_SHARP	(1 << 6)
-#define PCR_PCD(x)	((x) & 0x3f)
-
-#define PWMR_CLS(x)	(((x) & 0x1ff) << 16)
-#define PWMR_LDMSK	(1 << 15)
-#define PWMR_SCR1	(1 << 10)
-#define PWMR_SCR0	(1 << 9)
-#define PWMR_CC_EN	(1 << 8)
-#define PWMR_PW(x)	((x) & 0xff)
-
-#define LSCR1_PS_RISE_DELAY(x)    (((x) & 0x7f) << 26)
-#define LSCR1_CLS_RISE_DELAY(x)   (((x) & 0x3f) << 16)
-#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
-#define LSCR1_GRAY2(x)            (((x) & 0xf) << 4)
-#define LSCR1_GRAY1(x)            (((x) & 0xf))
-
-#define DMACR_BURST	(1 << 31)
-#define DMACR_HM(x)	(((x) & 0xf) << 16)
-#define DMACR_TM(x)	((x) & 0xf)
-
-/**
- * Define relevant framebuffer information
- */
-struct imx_fb_platform_data {
-	struct fb_videomode *mode;
-	u_int			num_modes;
-
-	u_int		cmap_greyscale:1,
-			cmap_inverse:1,
-			cmap_static:1,
-			unused:29;
-
-	u_int		pwmr;
-	u_int		lscr1;
-	u_int		dmacr;
-	u32 pcr;
-	unsigned char	bpp;
-
-	/** force a memory area to be used, else NULL for dynamic allocation */
-	void		*framebuffer;
-	/** force a memory area to be used, else NULL for dynamic allocation */
-	void		*framebuffer_ovl;
-	/** hook to enable backlight and stuff */
-	void		(*enable)(int enable);
-};
-
-void set_imx_fb_info(struct imx_fb_platform_data *);
-
-#endif /* __MACH_IMXFB_H */
-
-/**
- * @file
- * @brief i.MX related framebuffer declarations
- */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx1.h b/arch/arm/mach-imx/include/mach/iomux-mx1.h
deleted file mode 100644
index 51317d35d5..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx1.h
+++ /dev/null
@@ -1,135 +0,0 @@
-#ifndef __MACH_IOMUX_MX1_H
-#define __MACH_IOMUX_MX1_H
-
-#include <mach/iomux-v1.h>
-
-/*
- * FIXME: This list is not completed. The correct directions are
- * missing on some (many) pins
- */
-#define PA0_PF_A24           ( GPIO_PORTA | GPIO_PF | 0 )
-#define PA0_AIN_SPI2_CLK     ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
-#define PA0_AF_ETMTRACESYNC  ( GPIO_PORTA | GPIO_AF | 0 )
-#define PA1_AOUT_SPI2_RXD    ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
-#define PA1_PF_TIN           ( GPIO_PORTA | GPIO_PF | 1 )
-#define PA2_PF_PWM0          ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
-#define PA3_PF_CSI_MCLK      ( GPIO_PORTA | GPIO_PF | 3 )
-#define PA4_PF_CSI_D0        ( GPIO_PORTA | GPIO_PF | 4 )
-#define PA5_PF_CSI_D1        ( GPIO_PORTA | GPIO_PF | 5 )
-#define PA6_PF_CSI_D2        ( GPIO_PORTA | GPIO_PF | 6 )
-#define PA7_PF_CSI_D3        ( GPIO_PORTA | GPIO_PF | 7 )
-#define PA8_PF_CSI_D4        ( GPIO_PORTA | GPIO_PF | 8 )
-#define PA9_PF_CSI_D5        ( GPIO_PORTA | GPIO_PF | 9 )
-#define PA10_PF_CSI_D6       ( GPIO_PORTA | GPIO_PF | 10 )
-#define PA11_PF_CSI_D7       ( GPIO_PORTA | GPIO_PF | 11 )
-#define PA12_PF_CSI_VSYNC    ( GPIO_PORTA | GPIO_PF | 12 )
-#define PA13_PF_CSI_HSYNC    ( GPIO_PORTA | GPIO_PF | 13 )
-#define PA14_PF_CSI_PIXCLK   ( GPIO_PORTA | GPIO_PF | 14 )
-#define PA15_PF_I2C_SDA      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
-#define PA16_PF_I2C_SCL      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
-#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
-#define PA17_AIN_SPI2_SS     ( GPIO_PORTA | GPIO_AIN | 17 )
-#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
-#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
-#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
-#define PA21_PF_A0           ( GPIO_PORTA | GPIO_PF | 21 )
-#define PA22_PF_CS4          ( GPIO_PORTA | GPIO_PF | 22 )
-#define PA23_PF_CS5          ( GPIO_PORTA | GPIO_PF | 23 )
-#define PA24_PF_A16          ( GPIO_PORTA | GPIO_PF | 24 )
-#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
-#define PA25_PF_A17          ( GPIO_PORTA | GPIO_PF | 25 )
-#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
-#define PA26_PF_A18          ( GPIO_PORTA | GPIO_PF | 26 )
-#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
-#define PA27_PF_A19          ( GPIO_PORTA | GPIO_PF | 27 )
-#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
-#define PA28_PF_A20          ( GPIO_PORTA | GPIO_PF | 28 )
-#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
-#define PA29_PF_A21          ( GPIO_PORTA | GPIO_PF | 29 )
-#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
-#define PA30_PF_A22          ( GPIO_PORTA | GPIO_PF | 30 )
-#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
-#define PA31_PF_A23          ( GPIO_PORTA | GPIO_PF | 31 )
-#define PA31_AF_ETMTRACECLK  ( GPIO_PORTA | GPIO_AF | 31 )
-#define PB8_PF_SD_DAT0       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
-#define PB8_AF_MS_PIO        ( GPIO_PORTB | GPIO_AF | 8 )
-#define PB9_PF_SD_DAT1       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9 )
-#define PB9_AF_MS_PI1        ( GPIO_PORTB | GPIO_AF | 9 )
-#define PB10_PF_SD_DAT2      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10 )
-#define PB10_AF_MS_SCLKI     ( GPIO_PORTB | GPIO_AF | 10 )
-#define PB11_PF_SD_DAT3      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 11 )
-#define PB11_AF_MS_SDIO      ( GPIO_PORTB | GPIO_AF | 11 )
-#define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
-#define PB12_AF_MS_SCLK0     ( GPIO_PORTB | GPIO_AF | 12 )
-#define PB13_PF_SD_CMD       ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
-#define PB13_AF_MS_BS        ( GPIO_PORTB | GPIO_AF | 13 )
-#define PB14_AF_SSI_RXFS     ( GPIO_PORTB | GPIO_AF | 14 )
-#define PB15_AF_SSI_RXCLK    ( GPIO_PORTB | GPIO_AF | 15 )
-#define PB16_AF_SSI_RXDAT    ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
-#define PB17_AF_SSI_TXDAT    ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
-#define PB18_AF_SSI_TXFS     ( GPIO_PORTB | GPIO_AF | 18 )
-#define PB19_AF_SSI_TXCLK    ( GPIO_PORTB | GPIO_AF | 19 )
-#define PB20_PF_USBD_AFE     ( GPIO_PORTB | GPIO_PF | 20 )
-#define PB21_PF_USBD_OE      ( GPIO_PORTB | GPIO_PF | 21 )
-#define PB22_PFUSBD_RCV      ( GPIO_PORTB | GPIO_PF | 22 )
-#define PB23_PF_USBD_SUSPND  ( GPIO_PORTB | GPIO_PF | 23 )
-#define PB24_PF_USBD_VP      ( GPIO_PORTB | GPIO_PF | 24 )
-#define PB25_PF_USBD_VM      ( GPIO_PORTB | GPIO_PF | 25 )
-#define PB26_PF_USBD_VPO     ( GPIO_PORTB | GPIO_PF | 26 )
-#define PB27_PF_USBD_VMO     ( GPIO_PORTB | GPIO_PF | 27 )
-#define PB28_PF_UART2_CTS    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
-#define PB29_PF_UART2_RTS    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
-#define PB30_PF_UART2_TXD    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
-#define PB31_PF_UART2_RXD    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
-#define PC3_PF_SSI_RXFS      ( GPIO_PORTC | GPIO_PF | 3 )
-#define PC4_PF_SSI_RXCLK     ( GPIO_PORTC | GPIO_PF | 4 )
-#define PC5_PF_SSI_RXDAT     ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
-#define PC6_PF_SSI_TXDAT     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
-#define PC7_PF_SSI_TXFS      ( GPIO_PORTC | GPIO_PF | 7 )
-#define PC8_PF_SSI_TXCLK     ( GPIO_PORTC | GPIO_PF | 8 )
-#define PC9_PF_UART1_CTS     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
-#define PC10_PF_UART1_RTS    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
-#define PC11_PF_UART1_TXD    ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
-#define PC12_PF_UART1_RXD    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
-#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
-#define PC14_PF_SPI1_SCLK    ( GPIO_PORTC | GPIO_PF | 14 )
-#define PC15_PF_SPI1_SS      ( GPIO_PORTC | GPIO_PF | 15 )
-#define PC16_PF_SPI1_MISO    ( GPIO_PORTC | GPIO_PF | 16 )
-#define PC17_PF_SPI1_MOSI    ( GPIO_PORTC | GPIO_PF | 17 )
-#define PD6_PF_LSCLK         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
-#define PD7_PF_REV           ( GPIO_PORTD | GPIO_PF | 7 )
-#define PD7_AF_UART2_DTR     ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
-#define PD7_AIN_SPI2_SCLK    ( GPIO_PORTD | GPIO_AIN | 7 )
-#define PD8_PF_CLS           ( GPIO_PORTD | GPIO_PF | 8 )
-#define PD8_AF_UART2_DCD     ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
-#define PD8_AIN_SPI2_SS      ( GPIO_PORTD | GPIO_AIN | 8 )
-#define PD9_PF_PS            ( GPIO_PORTD | GPIO_PF | 9 )
-#define PD9_AF_UART2_RI      ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
-#define PD9_AOUT_SPI2_RXD    ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
-#define PD10_PF_SPL_SPR      ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
-#define PD10_AF_UART2_DSR    ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
-#define PD10_AIN_SPI2_TXD    ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
-#define PD11_PF_CONTRAST     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
-#define PD12_PF_ACD_OE       ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
-#define PD13_PF_LP_HSYNC     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
-#define PD14_PF_FLM_VSYNC    ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
-#define PD15_PF_LD0          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
-#define PD16_PF_LD1          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
-#define PD17_PF_LD2          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
-#define PD18_PF_LD3          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
-#define PD19_PF_LD4          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
-#define PD20_PF_LD5          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
-#define PD21_PF_LD6          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
-#define PD22_PF_LD7          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
-#define PD23_PF_LD8          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
-#define PD24_PF_LD9          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
-#define PD25_PF_LD10         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
-#define PD26_PF_LD11         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
-#define PD27_PF_LD12         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
-#define PD28_PF_LD13         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
-#define PD29_PF_LD14         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
-#define PD30_PF_LD15         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
-#define PD31_PF_TMR2OUT      ( GPIO_PORTD | GPIO_PF | 31 )
-#define PD31_BIN_SPI2_TXD    ( GPIO_PORTD | GPIO_BIN | 31 )
-
-#endif /* __MACH_IOMUX_MX1_H */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx21.h b/arch/arm/mach-imx/include/mach/iomux-mx21.h
deleted file mode 100644
index 308bfac99b..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx21.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2009 Holger Schurig <hs4233@mail.mn-solutions.de> */
-
-#ifndef __MACH_IOMUX_MX21_H__
-#define __MACH_IOMUX_MX21_H__
-
-#include <mach/iomux-v1.h>
-#include <mach/iomux-mx2x.h>
-
-/* Primary GPIO pin functions */
-
-#define PB22_PF_USBH1_BYP	(GPIO_PORTB | GPIO_PF | 22)
-#define PB25_PF_USBH1_ON	(GPIO_PORTB | GPIO_PF | 25)
-#define PC5_PF_USBOTG_SDA	(GPIO_PORTC | GPIO_PF | 5)
-#define PC6_PF_USBOTG_SCL	(GPIO_PORTC | GPIO_PF | 6)
-#define PC7_PF_USBOTG_ON	(GPIO_PORTC | GPIO_PF | 7)
-#define PC8_PF_USBOTG_FS	(GPIO_PORTC | GPIO_PF | 8)
-#define PC9_PF_USBOTG_OE	(GPIO_PORTC | GPIO_PF | 9)
-#define PC10_PF_USBOTG_TXDM	(GPIO_PORTC | GPIO_PF | 10)
-#define PC11_PF_USBOTG_TXDP	(GPIO_PORTC | GPIO_PF | 11)
-#define PC12_PF_USBOTG_RXDM	(GPIO_PORTC | GPIO_PF | 12)
-#define PC13_PF_USBOTG_RXDP	(GPIO_PORTC | GPIO_PF | 13)
-#define PC16_PF_SAP_FS		(GPIO_PORTC | GPIO_PF | 16)
-#define PC17_PF_SAP_RXD		(GPIO_PORTC | GPIO_PF | 17)
-#define PC18_PF_SAP_TXD		(GPIO_PORTC | GPIO_PF | 18)
-#define PC19_PF_SAP_CLK		(GPIO_PORTC | GPIO_PF | 19)
-#define PE0_PF_TEST_WB2		(GPIO_PORTE | GPIO_PF | 0)
-#define PE1_PF_TEST_WB1		(GPIO_PORTE | GPIO_PF | 1)
-#define PE2_PF_TEST_WB0		(GPIO_PORTE | GPIO_PF | 2)
-#define PF1_PF_NFCE		(GPIO_PORTF | GPIO_PF | 1)
-#define PF3_PF_NFCLE		(GPIO_PORTF | GPIO_PF | 3)
-#define PF7_PF_NFIO0		(GPIO_PORTF | GPIO_PF | 7)
-#define PF8_PF_NFIO1		(GPIO_PORTF | GPIO_PF | 8)
-#define PF9_PF_NFIO2		(GPIO_PORTF | GPIO_PF | 9)
-#define PF10_PF_NFIO3		(GPIO_PORTF | GPIO_PF | 10)
-#define PF11_PF_NFIO4		(GPIO_PORTF | GPIO_PF | 11)
-#define PF12_PF_NFIO5		(GPIO_PORTF | GPIO_PF | 12)
-#define PF13_PF_NFIO6		(GPIO_PORTF | GPIO_PF | 13)
-#define PF14_PF_NFIO7		(GPIO_PORTF | GPIO_PF | 14)
-#define PF16_PF_RES		(GPIO_PORTF | GPIO_PF | 16)
-
-/* Alternate GPIO pin functions */
-
-#define PA5_AF_BMI_CLK_CS	(GPIO_PORTA | GPIO_AF | 5)
-#define PA6_AF_BMI_D0		(GPIO_PORTA | GPIO_AF | 6)
-#define PA7_AF_BMI_D1		(GPIO_PORTA | GPIO_AF | 7)
-#define PA8_AF_BMI_D2		(GPIO_PORTA | GPIO_AF | 8)
-#define PA9_AF_BMI_D3		(GPIO_PORTA | GPIO_AF | 9)
-#define PA10_AF_BMI_D4		(GPIO_PORTA | GPIO_AF | 10)
-#define PA11_AF_BMI_D5		(GPIO_PORTA | GPIO_AF | 11)
-#define PA12_AF_BMI_D6		(GPIO_PORTA | GPIO_AF | 12)
-#define PA13_AF_BMI_D7		(GPIO_PORTA | GPIO_AF | 13)
-#define PA14_AF_BMI_D8		(GPIO_PORTA | GPIO_AF | 14)
-#define PA15_AF_BMI_D9		(GPIO_PORTA | GPIO_AF | 15)
-#define PA16_AF_BMI_D10		(GPIO_PORTA | GPIO_AF | 16)
-#define PA17_AF_BMI_D11		(GPIO_PORTA | GPIO_AF | 17)
-#define PA18_AF_BMI_D12		(GPIO_PORTA | GPIO_AF | 18)
-#define PA19_AF_BMI_D13		(GPIO_PORTA | GPIO_AF | 19)
-#define PA20_AF_BMI_D14		(GPIO_PORTA | GPIO_AF | 20)
-#define PA21_AF_BMI_D15		(GPIO_PORTA | GPIO_AF | 21)
-#define PA22_AF_BMI_READ_REQ	(GPIO_PORTA | GPIO_AF | 22)
-#define PA23_AF_BMI_WRITE	(GPIO_PORTA | GPIO_AF | 23)
-#define PA29_AF_BMI_RX_FULL	(GPIO_PORTA | GPIO_AF | 29)
-#define PA30_AF_BMI_READ	(GPIO_PORTA | GPIO_AF | 30)
-
-/* AIN GPIO pin functions */
-
-#define PC14_AIN_SYS_CLK	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
-#define PD21_AIN_USBH2_FS	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
-#define PD22_AIN_USBH2_OE	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
-#define PD23_AIN_USBH2_TXDM	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
-#define PD24_AIN_USBH2_TXDP	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
-#define PE8_AIN_IR_TXD		(GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
-#define PF0_AIN_PC_RST		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
-#define PF1_AIN_PC_CE1		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
-#define PF2_AIN_PC_CE2		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
-#define PF3_AIN_PC_POE		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
-#define PF4_AIN_PC_OE		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
-#define PF5_AIN_PC_RW		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
-
-/* BIN GPIO pin functions */
-
-#define PC14_BIN_SYS_CLK	(GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
-#define PD27_BIN_EXT_DMA_GRANT	(GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
-
-/* CIN GPIO pin functions */
-
-#define PB26_CIN_USBH1_RXDAT	(GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
-
-/* AOUT GPIO pin functions */
-
-#define PA29_AOUT_BMI_WAIT	(GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
-#define PD19_AOUT_USBH2_RXDM	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
-#define PD20_AOUT_USBH2_RXDP	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
-#define PD25_AOUT_EXT_DMAREQ	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
-#define PD26_AOUT_USBOTG_RXDAT	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
-#define PE9_AOUT_IR_RXD		(GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
-#define PF6_AOUT_PC_BVD2	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
-#define PF7_AOUT_PC_BVD1	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
-#define PF8_AOUT_PC_VS2		(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
-#define PF9_AOUT_PC_VS1		(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
-#define PF10_AOUT_PC_WP		(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
-#define PF11_AOUT_PC_READY	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
-#define PF12_AOUT_PC_WAIT	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
-#define PF13_AOUT_PC_CD2	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
-#define PF14_AOUT_PC_CD1	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
-
-#endif /* ifndef __MACH_IOMUX_MX21_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx25.h b/arch/arm/mach-imx/include/mach/iomux-mx25.h
deleted file mode 100644
index 58761b5e77..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx25.h
+++ /dev/null
@@ -1,529 +0,0 @@
-/*
- * arch/arm/plat-mxc/include/mach/iomux-mx25.h
- *
- * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
- *
- * based on arch/arm/mach-mx25/mx25_pins.h
- *    Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * and
- * arch/arm/plat-mxc/include/mach/iomux-mx35.h
- *    Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_IOMUX_MX25_H__
-#define __MACH_IOMUX_MX25_H__
-
-#include <mach/iomux-v3.h>
-
-/*
- * IOMUX/PAD Bit field definitions
- */
-
-#define MX25_PAD_A10__A10		IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A10__GPIO_4_0		IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A13__A13		IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A13__GPIO_4_1		IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A14__A14		IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A14__GPIO_2_0		IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A15__A15		IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A15__GPIO_2_1		IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A16__A16		IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A16__GPIO_2_2		IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A17__A17		IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A17__GPIO_2_3		IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A18__A18		IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__GPIO_2_4		IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__FEC_COL		IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A19__A19		IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__FEC_RX_ER		IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__GPIO_2_5		IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A20__A20		IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__GPIO_2_6		IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__FEC_RDATA2	IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A21__A21		IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__GPIO_2_7		IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__FEC_RDATA3	IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A22__A22		IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A22__GPIO_2_8		IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A23__A23		IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A23__GPIO_2_9		IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A24__A24		IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__GPIO_2_10		IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__FEC_RX_CLK	IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A25__A25		IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__GPIO_2_11		IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__FEC_CRS		IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_EB0__EB0		IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB0__AUD4_TXD		IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB0__GPIO_2_12		IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_EB1__EB1		IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB1__AUD4_RXD		IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB1__GPIO_2_13		IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_OE__OE			IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE__AUD4_TXC		IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE__GPIO_2_14		IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS0__CS0		IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS0__GPIO_4_2		IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS1__CS1		IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS1__GPIO_4_3		IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS4__CS4		IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__UART5_CTS		IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__GPIO_3_20		IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS5__CS5		IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__UART5_RTS		IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__GPIO_3_21		IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NF_CE0__NF_CE0		IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NF_CE0__GPIO_3_22	IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_ECB__ECB		IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_ECB__UART5_TXD_MUX	IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_ECB__GPIO_3_23		IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LBA__LBA		IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LBA__UART5_RXD_MUX	IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL)
-#define MX25_PAD_LBA__GPIO_3_24		IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_BCLK__BCLK		IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BCLK__GPIO_4_4		IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_RW__RW			IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RW__AUD4_TXFS		IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL)
-#define MX25_PAD_RW__GPIO_3_25		IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFWE_B__NFWE_B		IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWE_B__GPIO_3_26	IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFRE_B__NFRE_B		IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFRE_B__GPIO_3_27	IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFALE__NFALE		IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFALE__GPIO_3_28	IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFCLE__NFCLE		IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFCLE__GPIO_3_29	IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFWP_B__NFWP_B		IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWP_B__GPIO_3_30	IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFRB__NFRB		IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_NFRB__GPIO_3_31	IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D15__D15		IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__LD16		IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__GPIO_4_5		IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D14__D14		IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__LD17		IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__GPIO_4_6		IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D13__D13		IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__LD18		IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__GPIO_4_7		IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D12__D12		IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D12__GPIO_4_8		IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D11__D11		IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D11__GPIO_4_9		IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D10__D10		IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D10__GPIO_4_10		IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D10__USBOTG_OC		IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_D9__D9			IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D9__GPIO_4_11		IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D9__USBH2_PWR		IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
-
-#define MX25_PAD_D8__D8			IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D8__GPIO_4_12		IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D8__USBH2_OC		IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_D7__D7			IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D7__GPIO_4_13		IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D6__D6			IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D6__GPIO_4_14		IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D5__D5			IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D5__GPIO_4_15		IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D4__D4			IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D4__GPIO_4_16		IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D3__D3			IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D3__GPIO_4_17		IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D2__D2			IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D2__GPIO_4_18		IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D1__D1			IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D1__GPIO_4_19		IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D0__D0			IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D0__GPIO_4_20		IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD0__LD0		IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD0__CSI_D0		IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD0__GPIO_2_15		IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD0__USBH2_CLK		IOMUX_PAD(0x2c0,  0xc8, 0x06, 0, 0, 0xe0)
-
-#define MX25_PAD_LD1__LD1		IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD1__CSI_D1		IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD1__GPIO_2_16		IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD1__USBH2_DIR		IOMUX_PAD(0x2c4, 0x0cc, 0x06, 0, 0, 0xe0)
-
-#define MX25_PAD_LD2__LD2		IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD2__GPIO_2_17		IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD2__USBH2_STP		IOMUX_PAD(0x2c8, 0x0d0, 0x06, 0, 0, 0xe5)
-
-#define MX25_PAD_LD3__LD3		IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD3__GPIO_2_18		IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD3__USBH2_NXT		IOMUX_PAD(0x2cc, 0x0d4, 0x06, 0, 0, 0xe0)
-
-#define MX25_PAD_LD4__LD4		IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD4__GPIO_2_19		IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD4__USBH2_DATA0	IOMUX_PAD(0x2d0, 0x0d8, 0x06, 0, 0, 0xe5)
-
-#define MX25_PAD_LD5__LD5		IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD5__GPIO_1_19		IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD5__USBH2_DATA1	IOMUX_PAD(0x2d4, 0x0dc, 0x06, 0, 0, 0xe5)
-
-#define MX25_PAD_LD6__LD6		IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD6__GPIO_1_20		IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD6__USBH2_DATA2	IOMUX_PAD(0x2d8, 0x0e0, 0x06, 0, 0, 0xe5)
-
-#define MX25_PAD_LD7__LD7		IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD7__GPIO_1_21		IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD7__USBH2_DATA3	IOMUX_PAD(0x2dc, 0x0e4, 0x06, 0, 0, 0xe5)
-
-#define MX25_PAD_LD8__LD8		IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD8__FEC_TX_ERR	IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD9__LD9		IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD9__FEC_COL		IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD10__LD10		IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD10__FEC_RX_ER	IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD11__LD11		IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD11__FEC_RDATA2	IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD12__LD12		IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD12__FEC_RDATA3	IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD13__LD13		IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD13__FEC_TDATA2	IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD14__LD14		IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD14__FEC_TDATA3	IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD15__LD15		IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD15__FEC_RX_CLK	IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_HSYNC__HSYNC		IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_HSYNC__GPIO_1_22	IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_HSYNC__USBH2_DATA4	IOMUX_PAD(0x300, 0x108, 0x06, 0, 0, 0xe5)
-
-#define MX25_PAD_VSYNC__VSYNC		IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSYNC__GPIO_1_23	IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSYNC__USBH2_DATA5	IOMUX_PAD(0x304, 0x10c, 0x06, 0, 0, 0xe5)
-
-#define MX25_PAD_LSCLK__LSCLK		IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LSCLK__GPIO_1_24	IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LSCLK__USBH2_DATA6	IOMUX_PAD(0x308, 0x110, 0x06, 0, 0, 0xe5)
-
-#define MX25_PAD_OE_ACD__OE_ACD		IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE_ACD__GPIO_1_25	IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE_ACD__USBH2_DATA7	IOMUX_PAD(0x30c, 0x114, 0x06, 0, 0, 0xe5)
-
-#define MX25_PAD_CONTRAST__CONTRAST	IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__PWM4_PWMO	IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__FEC_CRS	IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_PWM__PWM		IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_PWM__GPIO_1_26		IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_PWM__USBH2_OC		IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_CSI_D2__CSI_D2		IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__UART5_RXD_MUX	IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__GPIO_1_27	IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D3__CSI_D3		IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D3__GPIO_1_28	IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D4__CSI_D4		IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__UART5_RTS	IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__GPIO_1_29	IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D5__CSI_D5		IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D5__GPIO_1_30	IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D6__CSI_D6		IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D6__GPIO_1_31	IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D7__CSI_D7		IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D7__GPIO_1_6	IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D8__CSI_D8		IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D8__GPIO_1_7	IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D9__CSI_D9		IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D9__GPIO_4_21	IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_MCLK__CSI_MCLK	IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_MCLK__GPIO_1_8	IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_VSYNC__CSI_VSYNC	IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_VSYNC__GPIO_1_9	IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_HSYNC__CSI_HSYNC	IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_HSYNC__GPIO_1_10	IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK	IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_PIXCLK__GPIO_1_11	IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_I2C1_CLK__I2C1_CLK	IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_CLK__GPIO_1_12	IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_I2C1_DAT__I2C1_DAT	IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_DAT__GPIO_1_13	IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI	IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MOSI__GPIO_1_14	IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_MISO__CSPI1_MISO	IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MISO__GPIO_1_15	IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_SS0__CSPI1_SS0	IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS0__GPIO_1_16	IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_SS1__CSPI1_SS1	IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS1__GPIO_1_17	IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK	IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SCLK__GPIO_1_18	IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_RDY__CSPI1_RDY	IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_CSPI1_RDY__GPIO_2_22	IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_RXD__UART1_RXD	IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN)
-#define MX25_PAD_UART1_RXD__GPIO_4_22	IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_TXD__UART1_TXD	IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART1_TXD__GPIO_4_23	IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_RTS__UART1_RTS	IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_UART1_RTS__CSI_D0	IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL)
-#define MX25_PAD_UART1_RTS__GPIO_4_24	IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_CTS__UART1_CTS	IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_UART1_CTS__CSI_D1	IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL)
-#define MX25_PAD_UART1_CTS__GPIO_4_25	IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RXD__GPIO_4_26	IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_TXD__GPIO_4_27	IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_RTS__UART2_RTS	IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__FEC_COL	IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__GPIO_4_28	IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_CTS__FEC_RX_ER	IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__UART2_CTS	IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__GPIO_4_29	IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_CMD__SD1_CMD	IOMUX_PAD(0x388, 0x190, 0x00, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CMD__FEC_RDATA2	IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CMD__GPIO_2_23	IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_CLK__SD1_CLK	IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CLK__FEC_RDATA3	IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CLK__GPIO_2_24	IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA0__SD1_DATA0	IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA0__GPIO_2_25	IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA1__SD1_DATA1	IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA1__AUD7_RXD	IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA1__GPIO_2_26	IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA2__SD1_DATA2	IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK	IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA2__GPIO_2_27	IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA3__SD1_DATA3	IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA3__FEC_CRS	IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA3__GPIO_2_28	IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define KPP_CTL_ROW	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define KPP_CTL_COL	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-#define MX25_PAD_KPP_ROW0__KPP_ROW0	IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW0__GPIO_2_29	IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_ROW1__KPP_ROW1	IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW1__GPIO_2_30	IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_ROW2__KPP_ROW2	IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW2__CSI_D0	IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW2__GPIO_2_31	IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_ROW3__KPP_ROW3	IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW3__CSI_LD1	IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW3__GPIO_3_0	IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL0__KPP_COL0	IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL0__AUD5_TXD	IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL0__GPIO_3_1	IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL1__KPP_COL1	IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL1__AUD5_RXD	IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL1__GPIO_3_2	IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL2__KPP_COL2	IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL2__UART4_RTS	IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL2__AUD5_TXC	IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL2__GPIO_3_3	IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL3__KPP_COL3	IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL3__UART4_CTS	IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL3__AUD5_TXFS	IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL3__GPIO_3_4	IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_MDC__FEC_MDC	IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__AUD4_TXD	IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__GPIO_3_5	IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_MDIO__FEC_MDIO	IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE)
-#define MX25_PAD_FEC_MDIO__AUD4_RXD	IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDIO__GPIO_3_6	IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TDATA0__FEC_TDATA0	IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA0__GPIO_3_7	IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TDATA1__FEC_TDATA1	IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__AUD4_TXFS	IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__GPIO_3_8	IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TX_EN__FEC_TX_EN	IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TX_EN__GPIO_3_9   	IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_RDATA0__FEC_RDATA0	IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA0__GPIO_3_10	IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_RDATA1__FEC_RDATA1	IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA1__GPIO_3_11	IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_RX_DV__FEC_RX_DV	IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RX_DV__CAN2_RX	IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_FEC_RX_DV__GPIO_3_12	IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK	IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
-#define MX25_PAD_FEC_TX_CLK__GPIO_3_13	IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_RTCK__RTCK		IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RTCK__OWIRE		IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RTCK__GPIO_3_14	IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_DE_B__DE_B		IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_DE_B__GPIO_2_20	IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_TDO__TDO		IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_GPIO_A__GPIO_A		IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_A__CAN1_TX	IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_GPIO_A__USBOTG_PWR	IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE)
-
-#define MX25_PAD_GPIO_B__GPIO_B		IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_B__CAN1_RX	IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K)
-#define MX25_PAD_GPIO_B__USBOTG_OC	IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_GPIO_C__GPIO_C		IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_C__CAN2_TX	IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
-
-#define MX25_PAD_GPIO_D__GPIO_D		IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_D__CAN2_RX	IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
-
-#define MX25_PAD_GPIO_E__GPIO_E		IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_GPIO_E__AUD7_TXD	IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_GPIO_F__GPIO_F		IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_GPIO_F__AUD7_TXC	IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK	IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EXT_ARMCLK__GPIO_3_15	IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16	IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_VSTBY_REQ__VSTBY_REQ	IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_REQ__AUD7_TXFS	IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_REQ__GPIO_3_17	IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_ACK__VSTBY_ACK	IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_ACK__GPIO_3_18	IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_POWER_FAIL__POWER_FAIL	IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_POWER_FAIL__AUD7_RXD	IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL)
-#define MX25_PAD_POWER_FAIL__GPIO_3_19	IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CLKO__CLKO		IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CLKO__GPIO_2_21	IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_BOOT_MODE0__BOOT_MODE0	IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE0__GPIO_4_30	IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE1__BOOT_MODE1	IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE1__GPIO_4_31	IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CTL_GRP_DVS_MISC	IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_FEC	IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_JTAG	IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_NFC	IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_CSI	IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_WEIM	IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_DDR	IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_CRM	IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_KPP	IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_SDHC1	IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_LCD	IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_UART	IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_NFC	IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_CSI	IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_CSPI1	IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DDRTYPE	IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_SDHC1	IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_LCD	IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-
-#endif /* __MACH_IOMUX_MX25_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h
deleted file mode 100644
index 5f8a3826f6..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx27.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2008 Sascha Hauer <kernel@pengutronix.de> */
-/* SPDX-FileCopyrightText: 2009 Holger Schurig <hs4233@mail.mn-solutions.de> */
-
-#ifndef __MACH_IOMUX_MX27_H__
-#define __MACH_IOMUX_MX27_H__
-
-#include <mach/iomux-v1.h>
-#include <mach/iomux-mx2x.h>
-
-/* Primary GPIO pin functions */
-
-#define PA0_PF_USBH2_CLK	(GPIO_PORTA | GPIO_PF | 0)
-#define PA1_PF_USBH2_DIR	(GPIO_PORTA | GPIO_PF | 1)
-#define PA2_PF_USBH2_DATA7	(GPIO_PORTA | GPIO_PF | 2)
-#define PA3_PF_USBH2_NXT	(GPIO_PORTA | GPIO_PF | 3)
-#define PA4_PF_USBH2_STP	(GPIO_PORTA | GPIO_PF | 4)
-#define PB22_PF_USBH1_SUSP	(GPIO_PORTB | GPIO_PF | 22)
-#define PB25_PF_USBH1_RCV	(GPIO_PORTB | GPIO_PF | 25)
-#define PC5_PF_I2C2_SDA		(GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
-#define PC6_PF_I2C2_SCL		(GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
-#define PC7_PF_USBOTG_DATA5	(GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
-#define PC8_PF_USBOTG_DATA6	(GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
-#define PC9_PF_USBOTG_DATA0	(GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
-#define PC10_PF_USBOTG_DATA2	(GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
-#define PC11_PF_USBOTG_DATA1	(GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
-#define PC12_PF_USBOTG_DATA4	(GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
-#define PC13_PF_USBOTG_DATA3	(GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
-#define PC16_PF_SSI4_FS		(GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
-#define PC17_PF_SSI4_RXD	(GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
-#define PC18_PF_SSI4_TXD	(GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
-#define PC19_PF_SSI4_CLK	(GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
-#define PD0_PF_SD3_CMD		(GPIO_PORTD | GPIO_PF | 0)
-#define PD1_PF_SD3_CLK		(GPIO_PORTD | GPIO_PF | 1)
-#define PD2_PF_ATA_DATA0	(GPIO_PORTD | GPIO_PF | 2)
-#define PD3_PF_ATA_DATA1	(GPIO_PORTD | GPIO_PF | 3)
-#define PD4_PF_ATA_DATA2	(GPIO_PORTD | GPIO_PF | 4)
-#define PD5_PF_ATA_DATA3	(GPIO_PORTD | GPIO_PF | 5)
-#define PD6_PF_ATA_DATA4	(GPIO_PORTD | GPIO_PF | 6)
-#define PD7_PF_ATA_DATA5	(GPIO_PORTD | GPIO_PF | 7)
-#define PD8_PF_ATA_DATA6	(GPIO_PORTD | GPIO_PF | 8)
-#define PD9_PF_ATA_DATA7	(GPIO_PORTD | GPIO_PF | 9)
-#define PD10_PF_ATA_DATA8	(GPIO_PORTD | GPIO_PF | 10)
-#define PD11_PF_ATA_DATA9	(GPIO_PORTD | GPIO_PF | 11)
-#define PD12_PF_ATA_DATA10	(GPIO_PORTD | GPIO_PF | 12)
-#define PD13_PF_ATA_DATA11	(GPIO_PORTD | GPIO_PF | 13)
-#define PD14_PF_ATA_DATA12	(GPIO_PORTD | GPIO_PF | 14)
-#define PD15_PF_ATA_DATA13	(GPIO_PORTD | GPIO_PF | 15)
-#define PD16_PF_ATA_DATA14	(GPIO_PORTD | GPIO_PF | 16)
-#define PE0_PF_USBOTG_NXT	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
-#define PE1_PF_USBOTG_STP	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
-#define PE2_PF_USBOTG_DIR	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
-#define PE24_PF_USBOTG_CLK	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
-#define PE25_PF_USBOTG_DATA7	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
-#define PF1_PF_NFCLE		(GPIO_PORTF | GPIO_PF | 1)
-#define PF3_PF_NFCE		(GPIO_PORTF | GPIO_PF | 3)
-#define PF7_PF_PC_POE		(GPIO_PORTF | GPIO_PF | 7)
-#define PF8_PF_PC_RW		(GPIO_PORTF | GPIO_PF | 8)
-#define PF9_PF_PC_IOIS16	(GPIO_PORTF | GPIO_PF | 9)
-#define PF10_PF_PC_RST		(GPIO_PORTF | GPIO_PF | 10)
-#define PF11_PF_PC_BVD2		(GPIO_PORTF | GPIO_PF | 11)
-#define PF12_PF_PC_BVD1		(GPIO_PORTF | GPIO_PF | 12)
-#define PF13_PF_PC_VS2		(GPIO_PORTF | GPIO_PF | 13)
-#define PF14_PF_PC_VS1		(GPIO_PORTF | GPIO_PF | 14)
-#define PF16_PF_PC_PWRON	(GPIO_PORTF | GPIO_PF | 16)
-#define PF17_PF_PC_READY	(GPIO_PORTF | GPIO_PF | 17)
-#define PF18_PF_PC_WAIT		(GPIO_PORTF | GPIO_PF | 18)
-#define PF19_PF_PC_CD2		(GPIO_PORTF | GPIO_PF | 19)
-#define PF20_PF_PC_CD1		(GPIO_PORTF | GPIO_PF | 20)
-#define PF23_PF_ATA_DATA15	(GPIO_PORTF | GPIO_PF | 23)
-
-/* Alternate GPIO pin functions */
-
-#define PB4_AF_MSHC_DATA0	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
-#define PB5_AF_MSHC_DATA1	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
-#define PB6_AF_MSHC_DATA2	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
-#define PB7_AF_MSHC_DATA4	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
-#define PB8_AF_MSHC_BS		(GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
-#define PB9_AF_MSHC_SCLK	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
-#define PB10_AF_UART6_TXD	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
-#define PB11_AF_UART6_RXD	(GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
-#define PB12_AF_UART6_CTS	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
-#define PB13_AF_UART6_RTS	(GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
-#define PB18_AF_UART5_TXD	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
-#define PB19_AF_UART5_RXD	(GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
-#define PB20_AF_UART5_CTS	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
-#define PB21_AF_UART5_RTS	(GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
-#define PC8_AF_FEC_MDIO		(GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
-#define PC24_AF_GPT5_TOUT	(GPIO_PORTC | GPIO_AF | 24)
-#define PC25_AF_GPT5_TIN	(GPIO_PORTC | GPIO_AF | 25)
-#define PC26_AF_GPT4_TOUT	(GPIO_PORTC | GPIO_AF | 26)
-#define PC27_AF_GPT4_TIN	(GPIO_PORTC | GPIO_AF | 27)
-#define PD1_AF_ETMTRACE_PKT15	(GPIO_PORTD | GPIO_AF | 1)
-#define PD6_AF_ETMTRACE_PKT14	(GPIO_PORTD | GPIO_AF | 6)
-#define PD7_AF_ETMTRACE_PKT13	(GPIO_PORTD | GPIO_AF | 7)
-#define PD9_AF_ETMTRACE_PKT12	(GPIO_PORTD | GPIO_AF | 9)
-#define PD2_AF_SD3_D0		(GPIO_PORTD | GPIO_AF | 2)
-#define PD3_AF_SD3_D1		(GPIO_PORTD | GPIO_AF | 3)
-#define PD4_AF_SD3_D2		(GPIO_PORTD | GPIO_AF | 4)
-#define PD5_AF_SD3_D3		(GPIO_PORTD | GPIO_AF | 5)
-#define PD8_AF_FEC_MDIO		(GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
-#define PD10_AF_ETMTRACE_PKT11	(GPIO_PORTD | GPIO_AF | 10)
-#define PD11_AF_ETMTRACE_PKT10	(GPIO_PORTD | GPIO_AF | 11)
-#define PD12_AF_ETMTRACE_PKT9	(GPIO_PORTD | GPIO_AF | 12)
-#define PD13_AF_ETMTRACE_PKT8	(GPIO_PORTD | GPIO_AF | 13)
-#define PD14_AF_ETMTRACE_PKT7	(GPIO_PORTD | GPIO_AF | 14)
-#define PD15_AF_ETMTRACE_PKT6	(GPIO_PORTD | GPIO_AF | 15)
-#define PD16_AF_ETMTRACE_PKT5	(GPIO_PORTD | GPIO_AF | 16)
-#define PF1_AF_ETMTRACE_PKT0	(GPIO_PORTF | GPIO_AF | 1)
-#define PF3_AF_ETMTRACE_PKT2	(GPIO_PORTF | GPIO_AF | 3)
-#define PF5_AF_ETMPIPESTAT11	(GPIO_PORTF | GPIO_AF | 5)
-#define PF7_AF_ATA_BUFFER_EN	(GPIO_PORTF | GPIO_AF | 7)
-#define PF8_AF_ATA_IORDY	(GPIO_PORTF | GPIO_AF | 8)
-#define PF9_AF_ATA_INTRQ	(GPIO_PORTF | GPIO_AF | 9)
-#define PF10_AF_ATA_RESET	(GPIO_PORTF | GPIO_AF | 10)
-#define PF11_AF_ATA_DMACK	(GPIO_PORTF | GPIO_AF | 11)
-#define PF12_AF_ATA_DMAREQ	(GPIO_PORTF | GPIO_AF | 12)
-#define PF13_AF_ATA_DA0		(GPIO_PORTF | GPIO_AF | 13)
-#define PF14_AF_ATA_DA1		(GPIO_PORTF | GPIO_AF | 14)
-#define PF15_AF_ETMTRACE_SYNC	(GPIO_PORTF | GPIO_AF | 15)
-#define PF16_AF_ATA_DA2		(GPIO_PORTF | GPIO_AF | 16)
-#define PF17_AF_ATA_CS0		(GPIO_PORTF | GPIO_AF | 17)
-#define PF18_AF_ATA_CS1		(GPIO_PORTF | GPIO_AF | 18)
-#define PF19_AF_ATA_DIOW	(GPIO_PORTF | GPIO_AF | 19)
-#define PF20_AF_ATA_DIOR	(GPIO_PORTF | GPIO_AF | 20)
-#define PF22_AF_ETMTRACE_CLK	(GPIO_PORTF | GPIO_AF | 22)
-#define PF23_AF_ETMTRACE_PKT4	(GPIO_PORTF | GPIO_AF | 23)
-
-/* AIN GPIO pin functions */
-
-#define PC14_AIN_SSI1_MCLK	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
-#define PC15_AIN_GPT6_TOUT	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
-#define PD0_AIN_FEC_TXD0	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
-#define PD1_AIN_FEC_TXD1	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
-#define PD2_AIN_FEC_TXD2	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
-#define PD3_AIN_FEC_TXD3	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
-#define PD9_AIN_FEC_MDC		(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
-#define PD16_AIN_FEC_TX_ER	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
-#define PD27_AIN_EXT_DMA_GRANT	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
-#define PF23_AIN_FEC_TX_EN	(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
-
-/* BIN GPIO pin functions */
-
-#define PC14_BIN_SSI2_MCLK	(GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
-
-/* CIN GPIO pin functions */
-
-#define PD2_CIN_SLCDC1_DAT0	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
-#define PD3_CIN_SLCDC1_DAT1	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
-#define PD4_CIN_SLCDC1_DAT2	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
-#define PD5_CIN_SLCDC1_DAT3	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
-#define PD6_CIN_SLCDC1_DAT4	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
-#define PD7_CIN_SLCDC1_DAT5	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
-#define PD8_CIN_SLCDC1_DAT6	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
-#define PD9_CIN_SLCDC1_DAT7	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
-#define PD10_CIN_SLCDC1_DAT8	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
-#define PD11_CIN_SLCDC1_DAT9	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
-#define PD12_CIN_SLCDC1_DAT10	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
-#define PD13_CIN_SLCDC1_DAT11	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
-#define PD14_CIN_SLCDC1_DAT12	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
-#define PD15_CIN_SLCDC1_DAT13	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
-#define PD16_CIN_SLCDC1_DAT14	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
-#define PD23_CIN_SLCDC1_DAT15	(GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
-#define PF27_CIN_EXT_DMA_GRANT	(GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
-/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
-
-/* AOUT GPIO pin functions */
-
-#define PC14_AOUT_GPT6_TIN	(GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
-#define PD4_AOUT_FEC_RX_ER	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
-#define PD5_AOUT_FEC_RXD1	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
-#define PD6_AOUT_FEC_RXD2	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
-#define PD7_AOUT_FEC_RXD3	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
-#define PD10_AOUT_FEC_CRS	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
-#define PD11_AOUT_FEC_TX_CLK	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
-#define PD12_AOUT_FEC_RXD0	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
-#define PD13_AOUT_FEC_RX_DV	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
-#define PD14_AOUT_FEC_RX_CLK	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
-#define PD15_AOUT_FEC_COL	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
-
-/* BOUT GPIO pin functions */
-
-#define PC17_BOUT_PC_IOIS16	(GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
-#define PC18_BOUT_PC_BVD2	(GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
-#define PC19_BOUT_PC_BVD1	(GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
-#define PC28_BOUT_PC_BVD2	(GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
-#define PC29_BOUT_PC_VS1	(GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
-#define PC30_BOUT_PC_READY	(GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
-#define PC31_BOUT_PC_WAIT	(GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
-
-#endif /* __MACH_IOMUX_MX27_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx2x.h b/arch/arm/mach-imx/include/mach/iomux-mx2x.h
deleted file mode 100644
index 64f07c0c33..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx2x.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2008 Sascha Hauer <kernel@pengutronix.de> */
-/* SPDX-FileCopyrightText: 2009 Holger Schurig <hs4233@mail.mn-solutions.de> */
-
-#ifndef __MACH_IOMUX_MX2x_H__
-#define __MACH_IOMUX_MX2x_H__
-
-/* Primary GPIO pin functions */
-
-#define PA5_PF_LSCLK		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
-#define PA6_PF_LD0		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
-#define PA7_PF_LD1		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
-#define PA8_PF_LD2		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
-#define PA9_PF_LD3		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
-#define PA10_PF_LD4		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
-#define PA11_PF_LD5		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
-#define PA12_PF_LD6		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
-#define PA13_PF_LD7		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
-#define PA14_PF_LD8		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
-#define PA15_PF_LD9		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
-#define PA16_PF_LD10		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
-#define PA17_PF_LD11		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
-#define PA18_PF_LD12		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
-#define PA19_PF_LD13		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
-#define PA20_PF_LD14		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
-#define PA21_PF_LD15		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
-#define PA22_PF_LD16		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
-#define PA23_PF_LD17		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
-#define PA24_PF_REV		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
-#define PA25_PF_CLS		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
-#define PA26_PF_PS		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
-#define PA27_PF_SPL_SPR		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
-#define PA28_PF_HSYNC		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
-#define PA29_PF_VSYNC		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
-#define PA30_PF_CONTRAST	(GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
-#define PA31_PF_OE_ACD		(GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
-#define PB4_PF_SD2_D0		(GPIO_PORTB | GPIO_PF | 4)
-#define PB5_PF_SD2_D1		(GPIO_PORTB | GPIO_PF | 5)
-#define PB6_PF_SD2_D2		(GPIO_PORTB | GPIO_PF | 6)
-#define PB7_PF_SD2_D3		(GPIO_PORTB | GPIO_PF | 7)
-#define PB8_PF_SD2_CMD		(GPIO_PORTB | GPIO_PF | 8)
-#define PB9_PF_SD2_CLK		(GPIO_PORTB | GPIO_PF | 9)
-#define PB10_PF_CSI_D0		(GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
-#define PB11_PF_CSI_D1		(GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
-#define PB12_PF_CSI_D2		(GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
-#define PB13_PF_CSI_D3		(GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
-#define PB14_PF_CSI_D4		(GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
-#define PB15_PF_CSI_MCLK	(GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
-#define PB16_PF_CSI_PIXCLK	(GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
-#define PB17_PF_CSI_D5		(GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
-#define PB18_PF_CSI_D6		(GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
-#define PB19_PF_CSI_D7		(GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
-#define PB20_PF_CSI_VSYNC	(GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
-#define PB21_PF_CSI_HSYNC	(GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
-#define PB23_PF_USB_PWR		(GPIO_PORTB | GPIO_PF | 23)
-#define PB24_PF_USB_OC		(GPIO_PORTB | GPIO_PF | 24)
-#define PB26_PF_USBH1_FS	(GPIO_PORTB | GPIO_PF | 26)
-#define PB27_PF_USBH1_OE	(GPIO_PORTB | GPIO_PF | 27)
-#define PB28_PF_USBH1_TXDM	(GPIO_PORTB | GPIO_PF | 28)
-#define PB29_PF_USBH1_TXDP	(GPIO_PORTB | GPIO_PF | 29)
-#define PB30_PF_USBH1_RXDM	(GPIO_PORTB | GPIO_PF | 30)
-#define PB31_PF_USBH1_RXDP	(GPIO_PORTB | GPIO_PF | 31)
-#define PC14_PF_TOUT		(GPIO_PORTC | GPIO_PF | 14)
-#define PC15_PF_TIN		(GPIO_PORTC | GPIO_PF | 15)
-#define PC20_PF_SSI1_FS		(GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
-#define PC21_PF_SSI1_RXD	(GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
-#define PC22_PF_SSI1_TXD	(GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
-#define PC23_PF_SSI1_CLK	(GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
-#define PC24_PF_SSI2_FS		(GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
-#define PC25_PF_SSI2_RXD	(GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
-#define PC26_PF_SSI2_TXD	(GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
-#define PC27_PF_SSI2_CLK	(GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
-#define PC28_PF_SSI3_FS		(GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
-#define PC29_PF_SSI3_RXD	(GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
-#define PC30_PF_SSI3_TXD	(GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
-#define PC31_PF_SSI3_CLK	(GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
-#define PD17_PF_I2C_DATA	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
-#define PD18_PF_I2C_CLK		(GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
-#define PD19_PF_CSPI2_SS2	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
-#define PD20_PF_CSPI2_SS1	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
-#define PD21_PF_CSPI2_SS0	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
-#define PD22_PF_CSPI2_SCLK	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
-#define PD23_PF_CSPI2_MISO	(GPIO_PORTD | GPIO_PF | GPIO_IN | 23)
-#define PD24_PF_CSPI2_MOSI	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
-#define PD25_PF_CSPI1_RDY	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
-#define PD26_PF_CSPI1_SS2	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
-#define PD27_PF_CSPI1_SS1	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
-#define PD28_PF_CSPI1_SS0	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
-#define PD29_PF_CSPI1_SCLK	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
-#define PD30_PF_CSPI1_MISO	(GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
-#define PD31_PF_CSPI1_MOSI	(GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
-#define PE3_PF_UART2_CTS	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
-#define PE4_PF_UART2_RTS	(GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
-#define PE5_PF_PWMO		(GPIO_PORTE | GPIO_PF | 5)
-#define PE6_PF_UART2_TXD	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
-#define PE7_PF_UART2_RXD	(GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
-#define PE8_PF_UART3_TXD	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
-#define PE9_PF_UART3_RXD	(GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
-#define PE10_PF_UART3_CTS	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
-#define PE11_PF_UART3_RTS	(GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
-#define PE12_PF_UART1_TXD	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
-#define PE13_PF_UART1_RXD	(GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
-#define PE14_PF_UART1_CTS	(GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
-#define PE15_PF_UART1_RTS	(GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
-#define PE16_PF_RTCK		(GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
-#define PE17_PF_RESET_OUT	(GPIO_PORTE | GPIO_PF | 17)
-#define PE18_PF_SD1_D0		(GPIO_PORTE | GPIO_PF | 18)
-#define PE19_PF_SD1_D1		(GPIO_PORTE | GPIO_PF | 19)
-#define PE20_PF_SD1_D2		(GPIO_PORTE | GPIO_PF | 20)
-#define PE21_PF_SD1_D3		(GPIO_PORTE | GPIO_PF | 21)
-#define PE22_PF_SD1_CMD		(GPIO_PORTE | GPIO_PF | 22)
-#define PE23_PF_SD1_CLK		(GPIO_PORTE | GPIO_PF | 23)
-#define PF0_PF_NRFB		(GPIO_PORTF | GPIO_PF | 0)
-#define PF2_PF_NFWP		(GPIO_PORTF | GPIO_PF | 2)
-#define PF4_PF_NFALE		(GPIO_PORTF | GPIO_PF | 4)
-#define PF5_PF_NFRE		(GPIO_PORTF | GPIO_PF | 5)
-#define PF6_PF_NFWE		(GPIO_PORTF | GPIO_PF | 6)
-#define PF15_PF_CLKO		(GPIO_PORTF | GPIO_PF | 15)
-#define PF21_PF_CS4		(GPIO_PORTF | GPIO_PF | 21)
-#define PF22_PF_CS5		(GPIO_PORTF | GPIO_PF | 22)
-
-/* Alternate GPIO pin functions */
-
-#define PB26_AF_UART4_RTS	(GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
-#define PB28_AF_UART4_TXD	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
-#define PB29_AF_UART4_CTS	(GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
-#define PB31_AF_UART4_RXD	(GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
-#define PC28_AF_SLCDC2_D0	(GPIO_PORTC | GPIO_AF | 28)
-#define PC29_AF_SLCDC2_RS	(GPIO_PORTC | GPIO_AF | 29)
-#define PC30_AF_SLCDC2_CS	(GPIO_PORTC | GPIO_AF | 30)
-#define PC31_AF_SLCDC2_CLK	(GPIO_PORTC | GPIO_AF | 31)
-#define PD19_AF_USBH2_DATA4	(GPIO_PORTD | GPIO_AF | 19)
-#define PD20_AF_USBH2_DATA3	(GPIO_PORTD | GPIO_AF | 20)
-#define PD21_AF_USBH2_DATA6	(GPIO_PORTD | GPIO_AF | 21)
-#define PD22_AF_USBH2_DATA0	(GPIO_PORTD | GPIO_AF | 22)
-#define PD23_AF_USBH2_DATA2	(GPIO_PORTD | GPIO_AF | 23)
-#define PD24_AF_USBH2_DATA1	(GPIO_PORTD | GPIO_AF | 24)
-#define PD26_AF_USBH2_DATA5	(GPIO_PORTD | GPIO_AF | 26)
-#define PE0_AF_KP_COL6		(GPIO_PORTE | GPIO_AF | 0)
-#define PE1_AF_KP_ROW6		(GPIO_PORTE | GPIO_AF | 1)
-#define PE2_AF_KP_ROW7		(GPIO_PORTE | GPIO_AF | 2)
-#define PE3_AF_KP_COL7		(GPIO_PORTE | GPIO_AF | 3)
-#define PE4_AF_KP_ROW7		(GPIO_PORTE | GPIO_AF | 4)
-#define PE6_AF_KP_COL6		(GPIO_PORTE | GPIO_AF | 6)
-#define PE7_AF_KP_ROW6		(GPIO_PORTE | GPIO_AF | 7)
-#define PE16_AF_OWIRE		(GPIO_PORTE | GPIO_AF | 16)
-#define PE18_AF_CSPI3_MISO	(GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
-#define PE21_AF_CSPI3_SS	(GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
-#define PE22_AF_CSPI3_MOSI	(GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
-#define PE23_AF_CSPI3_SCLK	(GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
-
-/* AIN GPIO pin functions */
-
-#define PA6_AIN_SLCDC1_DAT0	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
-#define PA7_AIN_SLCDC1_DAT1	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
-#define PA8_AIN_SLCDC1_DAT2	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
-#define PA0_AIN_SLCDC1_DAT3	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
-#define PA11_AIN_SLCDC1_DAT5	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
-#define PA13_AIN_SLCDC1_DAT7	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
-#define PA15_AIN_SLCDC1_DAT9	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
-#define PA17_AIN_SLCDC1_DAT11	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
-#define PA19_AIN_SLCDC1_DAT13	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
-#define PA21_AIN_SLCDC1_DAT15	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
-#define PA22_AIN_EXT_DMAGRANT	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
-#define PA24_AIN_SLCDC1_D0	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
-#define PA25_AIN_SLCDC1_RS	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
-#define PA26_AIN_SLCDC1_CS	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
-#define PA27_AIN_SLCDC1_CLK	(GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
-#define PB6_AIN_SLCDC1_D0	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
-#define PB7_AIN_SLCDC1_RS	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
-#define PB8_AIN_SLCDC1_CS	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
-#define PB9_AIN_SLCDC1_CLK	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
-#define PB25_AIN_SLCDC1_DAT0	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
-#define PB26_AIN_SLCDC1_DAT1	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
-#define PB27_AIN_SLCDC1_DAT2	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
-#define PB28_AIN_SLCDC1_DAT3	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
-#define PB29_AIN_SLCDC1_DAT4	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
-#define PB30_AIN_SLCDC1_DAT5	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
-#define PB31_AIN_SLCDC1_DAT6	(GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
-#define PC5_AIN_SLCDC1_DAT7	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
-#define PC6_AIN_SLCDC1_DAT8	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
-#define PC7_AIN_SLCDC1_DAT9	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
-#define PC8_AIN_SLCDC1_DAT10	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
-#define PC9_AIN_SLCDC1_DAT11	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
-#define PC10_AIN_SLCDC1_DAT12	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
-#define PC11_AIN_SLCDC1_DAT13	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
-#define PC12_AIN_SLCDC1_DAT14	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
-#define PC13_AIN_SLCDC1_DAT15	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
-#define PE5_AIN_PC_SPKOUT	(GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
-
-/* BIN GPIO pin functions */
-
-#define PE5_BIN_TOUT2		(GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
-
-/* CIN GPIO pin functions */
-
-#define PA14_CIN_SLCDC1_DAT0	(GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
-#define PA15_CIN_SLCDC1_DAT1	(GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
-#define PA16_CIN_SLCDC1_DAT2	(GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
-#define PA17_CIN_SLCDC1_DAT3	(GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
-#define PA18_CIN_SLCDC1_DAT4	(GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
-#define PA19_CIN_SLCDC1_DAT5	(GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
-#define PA20_CIN_SLCDC1_DAT6	(GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
-#define PA21_CIN_SLCDC1_DAT7	(GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
-#define PB30_CIN_UART4_CTS	(GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
-#define PE5_CIN_TOUT3		(GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
-
-/* AOUT GPIO pin functions */
-
-#define PB29_AOUT_UART4_RXD	(GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
-#define PB31_AOUT_UART4_RTS	(GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
-#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
-#define PC15_AOUT_WKGD		(GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
-#define PF21_AOUT_DTACK		(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
-
-#endif /* ifndef __MACH_IOMUX_MX2x_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx31.h b/arch/arm/mach-imx/include/mach/iomux-mx31.h
deleted file mode 100644
index d524125a85..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx31.h
+++ /dev/null
@@ -1,684 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2004-2006 Freescale Semiconductor, Inc. */
-/* SPDX-FileCopyrightText: 2008 Sascha Hauer <kernel@pengutronix.de> */
-
-#ifndef __MACH_IOMUX_MX3_H__
-#define __MACH_IOMUX_MX3_H__
-
-#include <linux/types.h>
-/*
- * various IOMUX output functions
- */
-
-#define	IOMUX_OCONFIG_GPIO (0 << 4)	/* used as GPIO */
-#define	IOMUX_OCONFIG_FUNC (1 << 4)	/* used as function */
-#define	IOMUX_OCONFIG_ALT1 (2 << 4)	/* used as alternate function 1 */
-#define	IOMUX_OCONFIG_ALT2 (3 << 4)	/* used as alternate function 2 */
-#define	IOMUX_OCONFIG_ALT3 (4 << 4)	/* used as alternate function 3 */
-#define	IOMUX_OCONFIG_ALT4 (5 << 4)	/* used as alternate function 4 */
-#define	IOMUX_OCONFIG_ALT5 (6 << 4)	/* used as alternate function 5 */
-#define	IOMUX_OCONFIG_ALT6 (7 << 4)	/* used as alternate function 6 */
-#define	IOMUX_ICONFIG_NONE  0		/* not configured for input */
-#define	IOMUX_ICONFIG_GPIO  1		/* used as GPIO */
-#define	IOMUX_ICONFIG_FUNC  2		/* used as function */
-#define	IOMUX_ICONFIG_ALT1  4		/* used as alternate function 1 */
-#define	IOMUX_ICONFIG_ALT2  8		/* used as alternate function 2 */
-
-#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
-#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
-#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
-#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
-
-/*
- * various IOMUX pad functions
- */
-enum iomux_pad_config {
-	PAD_CTL_NOLOOPBACK	= 0x0 << 9,
-	PAD_CTL_LOOPBACK	= 0x1 << 9,
-	PAD_CTL_PKE_NONE	= 0x0 << 8,
-	PAD_CTL_PKE_ENABLE	= 0x1 << 8,
-	PAD_CTL_PUE_KEEPER	= 0x0 << 7,
-	PAD_CTL_PUE_PUD		= 0x1 << 7,
-	PAD_CTL_100K_PD		= 0x0 << 5,
-	PAD_CTL_100K_PU		= 0x1 << 5,
-	PAD_CTL_47K_PU		= 0x2 << 5,
-	PAD_CTL_22K_PU		= 0x3 << 5,
-	PAD_CTL_HYS_CMOS	= 0x0 << 4,
-	PAD_CTL_HYS_SCHMITZ	= 0x1 << 4,
-	PAD_CTL_ODE_CMOS	= 0x0 << 3,
-	PAD_CTL_ODE_OpenDrain	= 0x1 << 3,
-	PAD_CTL_DRV_NORMAL	= 0x0 << 1,
-	PAD_CTL_DRV_HIGH	= 0x1 << 1,
-	PAD_CTL_DRV_MAX		= 0x2 << 1,
-	PAD_CTL_SRE_SLOW	= 0x0 << 0,
-	PAD_CTL_SRE_FAST	= 0x1 << 0
-};
-
-/*
- * various IOMUX general purpose functions
- */
-enum iomux_gp_func {
-	MUX_PGP_FIRI			= 1 << 0,
-	MUX_DDR_MODE			= 1 << 1,
-	MUX_PGP_CSPI_BB			= 1 << 2,
-	MUX_PGP_ATA_1			= 1 << 3,
-	MUX_PGP_ATA_2			= 1 << 4,
-	MUX_PGP_ATA_3			= 1 << 5,
-	MUX_PGP_ATA_4			= 1 << 6,
-	MUX_PGP_ATA_5			= 1 << 7,
-	MUX_PGP_ATA_6			= 1 << 8,
-	MUX_PGP_ATA_7			= 1 << 9,
-	MUX_PGP_ATA_8			= 1 << 10,
-	MUX_PGP_UH2			= 1 << 11,
-	MUX_SDCTL_CSD0_SEL		= 1 << 12,
-	MUX_SDCTL_CSD1_SEL		= 1 << 13,
-	MUX_CSPI1_UART3			= 1 << 14,
-	MUX_EXTDMAREQ2_MBX_SEL		= 1 << 15,
-	MUX_TAMPER_DETECT_EN		= 1 << 16,
-	MUX_PGP_USB_4WIRE		= 1 << 17,
-	MUX_PGP_USB_COMMON		= 1 << 18,
-	MUX_SDHC_MEMSTICK1		= 1 << 19,
-	MUX_SDHC_MEMSTICK2		= 1 << 20,
-	MUX_PGP_SPLL_BYP		= 1 << 21,
-	MUX_PGP_UPLL_BYP		= 1 << 22,
-	MUX_PGP_MSHC1_CLK_SEL		= 1 << 23,
-	MUX_PGP_MSHC2_CLK_SEL		= 1 << 24,
-	MUX_CSPI3_UART5_SEL		= 1 << 25,
-	MUX_PGP_ATA_9			= 1 << 26,
-	MUX_PGP_USB_SUSPEND		= 1 << 27,
-	MUX_PGP_USB_OTG_LOOPBACK	= 1 << 28,
-	MUX_PGP_USB_HS1_LOOPBACK	= 1 << 29,
-	MUX_PGP_USB_HS2_LOOPBACK	= 1 << 30,
-	MUX_CLKO_DDR_MODE		= 1 << 31,
-};
-
-/*
- * setups mutliple pins
- * convenient way to call the above function with tables
- */
-int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count);
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- */
-void imx_iomux_set_gpr(enum iomux_gp_func, bool en);
-
-/*
- * This function only configures the iomux hardware.
- * It is called by the setup functions and should not be called directly anymore.
- * It is here visible for backward compatibility
- */
-int imx_iomux_mode(unsigned int pin_mode);
-
-#define IOMUX_PADNUM_MASK	0x1ff
-#define IOMUX_GPIONUM_SHIFT	9
-#define IOMUX_GPIONUM_MASK	(0xff << IOMUX_GPIONUM_SHIFT)
-#define IOMUX_MODE_SHIFT	17
-#define IOMUX_MODE_MASK	(0xff << IOMUX_MODE_SHIFT)
-
-#define IOMUX_PIN(gpionum, padnum) \
-	(((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
-	 (padnum & IOMUX_PADNUM_MASK))
-
-#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
-
-#define IOMUX_TO_GPIO(iomux_pin) \
-	((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-
-enum iomux_pins {
-	MX31_PIN_TTM_PAD	= IOMUX_PIN(0xff,   0),
-	MX31_PIN_CSPI3_SPI_RDY	= IOMUX_PIN(0xff,   1),
-	MX31_PIN_CSPI3_SCLK	= IOMUX_PIN(0xff,   2),
-	MX31_PIN_CSPI3_MISO	= IOMUX_PIN(0xff,   3),
-	MX31_PIN_CSPI3_MOSI	= IOMUX_PIN(0xff,   4),
-	MX31_PIN_CLKSS		= IOMUX_PIN(0xff,   5),
-	MX31_PIN_CE_CONTROL	= IOMUX_PIN(0xff,   6),
-	MX31_PIN_ATA_RESET_B	= IOMUX_PIN(95,     7),
-	MX31_PIN_ATA_DMACK	= IOMUX_PIN(94,     8),
-	MX31_PIN_ATA_DIOW	= IOMUX_PIN(93,     9),
-	MX31_PIN_ATA_DIOR	= IOMUX_PIN(92,    10),
-	MX31_PIN_ATA_CS1	= IOMUX_PIN(91,    11),
-	MX31_PIN_ATA_CS0	= IOMUX_PIN(90,    12),
-	MX31_PIN_SD1_DATA3	= IOMUX_PIN(63,    13),
-	MX31_PIN_SD1_DATA2	= IOMUX_PIN(62,    14),
-	MX31_PIN_SD1_DATA1	= IOMUX_PIN(61,    15),
-	MX31_PIN_SD1_DATA0	= IOMUX_PIN(60,    16),
-	MX31_PIN_SD1_CLK	= IOMUX_PIN(59,    17),
-	MX31_PIN_SD1_CMD	= IOMUX_PIN(58,    18),
-	MX31_PIN_D3_SPL		= IOMUX_PIN(0xff,  19),
-	MX31_PIN_D3_CLS		= IOMUX_PIN(0xff,  20),
-	MX31_PIN_D3_REV		= IOMUX_PIN(0xff,  21),
-	MX31_PIN_CONTRAST	= IOMUX_PIN(0xff,  22),
-	MX31_PIN_VSYNC3		= IOMUX_PIN(0xff,  23),
-	MX31_PIN_READ		= IOMUX_PIN(0xff,  24),
-	MX31_PIN_WRITE		= IOMUX_PIN(0xff,  25),
-	MX31_PIN_PAR_RS		= IOMUX_PIN(0xff,  26),
-	MX31_PIN_SER_RS		= IOMUX_PIN(89,    27),
-	MX31_PIN_LCS1		= IOMUX_PIN(88,    28),
-	MX31_PIN_LCS0		= IOMUX_PIN(87,    29),
-	MX31_PIN_SD_D_CLK	= IOMUX_PIN(86,    30),
-	MX31_PIN_SD_D_IO	= IOMUX_PIN(85,    31),
-	MX31_PIN_SD_D_I		= IOMUX_PIN(84,    32),
-	MX31_PIN_DRDY0		= IOMUX_PIN(0xff,  33),
-	MX31_PIN_FPSHIFT	= IOMUX_PIN(0xff,  34),
-	MX31_PIN_HSYNC		= IOMUX_PIN(0xff,  35),
-	MX31_PIN_VSYNC0		= IOMUX_PIN(0xff,  36),
-	MX31_PIN_LD17		= IOMUX_PIN(0xff,  37),
-	MX31_PIN_LD16		= IOMUX_PIN(0xff,  38),
-	MX31_PIN_LD15		= IOMUX_PIN(0xff,  39),
-	MX31_PIN_LD14		= IOMUX_PIN(0xff,  40),
-	MX31_PIN_LD13		= IOMUX_PIN(0xff,  41),
-	MX31_PIN_LD12		= IOMUX_PIN(0xff,  42),
-	MX31_PIN_LD11		= IOMUX_PIN(0xff,  43),
-	MX31_PIN_LD10		= IOMUX_PIN(0xff,  44),
-	MX31_PIN_LD9		= IOMUX_PIN(0xff,  45),
-	MX31_PIN_LD8		= IOMUX_PIN(0xff,  46),
-	MX31_PIN_LD7		= IOMUX_PIN(0xff,  47),
-	MX31_PIN_LD6		= IOMUX_PIN(0xff,  48),
-	MX31_PIN_LD5		= IOMUX_PIN(0xff,  49),
-	MX31_PIN_LD4		= IOMUX_PIN(0xff,  50),
-	MX31_PIN_LD3		= IOMUX_PIN(0xff,  51),
-	MX31_PIN_LD2		= IOMUX_PIN(0xff,  52),
-	MX31_PIN_LD1		= IOMUX_PIN(0xff,  53),
-	MX31_PIN_LD0		= IOMUX_PIN(0xff,  54),
-	MX31_PIN_USBH2_DATA1	= IOMUX_PIN(0xff,  55),
-	MX31_PIN_USBH2_DATA0	= IOMUX_PIN(0xff,  56),
-	MX31_PIN_USBH2_NXT	= IOMUX_PIN(0xff,  57),
-	MX31_PIN_USBH2_STP	= IOMUX_PIN(0xff,  58),
-	MX31_PIN_USBH2_DIR	= IOMUX_PIN(0xff,  59),
-	MX31_PIN_USBH2_CLK	= IOMUX_PIN(0xff,  60),
-	MX31_PIN_USBOTG_DATA7	= IOMUX_PIN(0xff,  61),
-	MX31_PIN_USBOTG_DATA6	= IOMUX_PIN(0xff,  62),
-	MX31_PIN_USBOTG_DATA5	= IOMUX_PIN(0xff,  63),
-	MX31_PIN_USBOTG_DATA4	= IOMUX_PIN(0xff,  64),
-	MX31_PIN_USBOTG_DATA3	= IOMUX_PIN(0xff,  65),
-	MX31_PIN_USBOTG_DATA2	= IOMUX_PIN(0xff,  66),
-	MX31_PIN_USBOTG_DATA1	= IOMUX_PIN(0xff,  67),
-	MX31_PIN_USBOTG_DATA0	= IOMUX_PIN(0xff,  68),
-	MX31_PIN_USBOTG_NXT	= IOMUX_PIN(0xff,  69),
-	MX31_PIN_USBOTG_STP	= IOMUX_PIN(0xff,  70),
-	MX31_PIN_USBOTG_DIR	= IOMUX_PIN(0xff,  71),
-	MX31_PIN_USBOTG_CLK	= IOMUX_PIN(0xff,  72),
-	MX31_PIN_USB_BYP	= IOMUX_PIN(31,    73),
-	MX31_PIN_USB_OC		= IOMUX_PIN(30,    74),
-	MX31_PIN_USB_PWR	= IOMUX_PIN(29,    75),
-	MX31_PIN_SJC_MOD	= IOMUX_PIN(0xff,  76),
-	MX31_PIN_DE_B		= IOMUX_PIN(0xff,  77),
-	MX31_PIN_TRSTB		= IOMUX_PIN(0xff,  78),
-	MX31_PIN_TDO		= IOMUX_PIN(0xff,  79),
-	MX31_PIN_TDI		= IOMUX_PIN(0xff,  80),
-	MX31_PIN_TMS		= IOMUX_PIN(0xff,  81),
-	MX31_PIN_TCK		= IOMUX_PIN(0xff,  82),
-	MX31_PIN_RTCK		= IOMUX_PIN(0xff,  83),
-	MX31_PIN_KEY_COL7	= IOMUX_PIN(57,    84),
-	MX31_PIN_KEY_COL6	= IOMUX_PIN(56,    85),
-	MX31_PIN_KEY_COL5	= IOMUX_PIN(55,    86),
-	MX31_PIN_KEY_COL4	= IOMUX_PIN(54,    87),
-	MX31_PIN_KEY_COL3	= IOMUX_PIN(0xff,  88),
-	MX31_PIN_KEY_COL2	= IOMUX_PIN(0xff,  89),
-	MX31_PIN_KEY_COL1	= IOMUX_PIN(0xff,  90),
-	MX31_PIN_KEY_COL0	= IOMUX_PIN(0xff,  91),
-	MX31_PIN_KEY_ROW7	= IOMUX_PIN(53,    92),
-	MX31_PIN_KEY_ROW6	= IOMUX_PIN(52,    93),
-	MX31_PIN_KEY_ROW5	= IOMUX_PIN(51,    94),
-	MX31_PIN_KEY_ROW4	= IOMUX_PIN(50,    95),
-	MX31_PIN_KEY_ROW3	= IOMUX_PIN(0xff,  96),
-	MX31_PIN_KEY_ROW2	= IOMUX_PIN(0xff,  97),
-	MX31_PIN_KEY_ROW1	= IOMUX_PIN(0xff,  98),
-	MX31_PIN_KEY_ROW0	= IOMUX_PIN(0xff,  99),
-	MX31_PIN_BATT_LINE	= IOMUX_PIN(49,   100),
-	MX31_PIN_CTS2		= IOMUX_PIN(0xff, 101),
-	MX31_PIN_RTS2		= IOMUX_PIN(0xff, 102),
-	MX31_PIN_TXD2		= IOMUX_PIN(28,   103),
-	MX31_PIN_RXD2		= IOMUX_PIN(27,   104),
-	MX31_PIN_DTR_DCE2	= IOMUX_PIN(48,   105),
-	MX31_PIN_DCD_DTE1	= IOMUX_PIN(47,   106),
-	MX31_PIN_RI_DTE1	= IOMUX_PIN(46,   107),
-	MX31_PIN_DSR_DTE1	= IOMUX_PIN(45,   108),
-	MX31_PIN_DTR_DTE1	= IOMUX_PIN(44,   109),
-	MX31_PIN_DCD_DCE1	= IOMUX_PIN(43,   110),
-	MX31_PIN_RI_DCE1	= IOMUX_PIN(42,   111),
-	MX31_PIN_DSR_DCE1	= IOMUX_PIN(41,   112),
-	MX31_PIN_DTR_DCE1	= IOMUX_PIN(40,   113),
-	MX31_PIN_CTS1		= IOMUX_PIN(39,   114),
-	MX31_PIN_RTS1		= IOMUX_PIN(38,   115),
-	MX31_PIN_TXD1		= IOMUX_PIN(37,   116),
-	MX31_PIN_RXD1		= IOMUX_PIN(36,   117),
-	MX31_PIN_CSPI2_SPI_RDY	= IOMUX_PIN(0xff, 118),
-	MX31_PIN_CSPI2_SCLK	= IOMUX_PIN(0xff, 119),
-	MX31_PIN_CSPI2_SS2	= IOMUX_PIN(0xff, 120),
-	MX31_PIN_CSPI2_SS1	= IOMUX_PIN(0xff, 121),
-	MX31_PIN_CSPI2_SS0	= IOMUX_PIN(0xff, 122),
-	MX31_PIN_CSPI2_MISO	= IOMUX_PIN(0xff, 123),
-	MX31_PIN_CSPI2_MOSI	= IOMUX_PIN(0xff, 124),
-	MX31_PIN_CSPI1_SPI_RDY	= IOMUX_PIN(0xff, 125),
-	MX31_PIN_CSPI1_SCLK	= IOMUX_PIN(0xff, 126),
-	MX31_PIN_CSPI1_SS2	= IOMUX_PIN(0xff, 127),
-	MX31_PIN_CSPI1_SS1	= IOMUX_PIN(0xff, 128),
-	MX31_PIN_CSPI1_SS0	= IOMUX_PIN(0xff, 129),
-	MX31_PIN_CSPI1_MISO	= IOMUX_PIN(0xff, 130),
-	MX31_PIN_CSPI1_MOSI	= IOMUX_PIN(0xff, 131),
-	MX31_PIN_SFS6		= IOMUX_PIN(26,   132),
-	MX31_PIN_SCK6		= IOMUX_PIN(25,   133),
-	MX31_PIN_SRXD6		= IOMUX_PIN(24,   134),
-	MX31_PIN_STXD6		= IOMUX_PIN(23,   135),
-	MX31_PIN_SFS5		= IOMUX_PIN(0xff, 136),
-	MX31_PIN_SCK5		= IOMUX_PIN(0xff, 137),
-	MX31_PIN_SRXD5		= IOMUX_PIN(22,   138),
-	MX31_PIN_STXD5		= IOMUX_PIN(21,   139),
-	MX31_PIN_SFS4		= IOMUX_PIN(0xff, 140),
-	MX31_PIN_SCK4		= IOMUX_PIN(0xff, 141),
-	MX31_PIN_SRXD4		= IOMUX_PIN(20,   142),
-	MX31_PIN_STXD4		= IOMUX_PIN(19,   143),
-	MX31_PIN_SFS3		= IOMUX_PIN(0xff, 144),
-	MX31_PIN_SCK3		= IOMUX_PIN(0xff, 145),
-	MX31_PIN_SRXD3		= IOMUX_PIN(18,   146),
-	MX31_PIN_STXD3		= IOMUX_PIN(17,   147),
-	MX31_PIN_I2C_DAT	= IOMUX_PIN(0xff, 148),
-	MX31_PIN_I2C_CLK	= IOMUX_PIN(0xff, 149),
-	MX31_PIN_CSI_PIXCLK	= IOMUX_PIN(83,   150),
-	MX31_PIN_CSI_HSYNC	= IOMUX_PIN(82,   151),
-	MX31_PIN_CSI_VSYNC	= IOMUX_PIN(81,   152),
-	MX31_PIN_CSI_MCLK	= IOMUX_PIN(80,   153),
-	MX31_PIN_CSI_D15	= IOMUX_PIN(79,   154),
-	MX31_PIN_CSI_D14	= IOMUX_PIN(78,   155),
-	MX31_PIN_CSI_D13	= IOMUX_PIN(77,   156),
-	MX31_PIN_CSI_D12	= IOMUX_PIN(76,   157),
-	MX31_PIN_CSI_D11	= IOMUX_PIN(75,   158),
-	MX31_PIN_CSI_D10	= IOMUX_PIN(74,   159),
-	MX31_PIN_CSI_D9		= IOMUX_PIN(73,   160),
-	MX31_PIN_CSI_D8		= IOMUX_PIN(72,   161),
-	MX31_PIN_CSI_D7		= IOMUX_PIN(71,   162),
-	MX31_PIN_CSI_D6		= IOMUX_PIN(70,   163),
-	MX31_PIN_CSI_D5		= IOMUX_PIN(69,   164),
-	MX31_PIN_CSI_D4		= IOMUX_PIN(68,   165),
-	MX31_PIN_M_GRANT	= IOMUX_PIN(0xff, 166),
-	MX31_PIN_M_REQUEST	= IOMUX_PIN(0xff, 167),
-	MX31_PIN_PC_POE		= IOMUX_PIN(0xff, 168),
-	MX31_PIN_PC_RW_B	= IOMUX_PIN(0xff, 169),
-	MX31_PIN_IOIS16		= IOMUX_PIN(0xff, 170),
-	MX31_PIN_PC_RST		= IOMUX_PIN(0xff, 171),
-	MX31_PIN_PC_BVD2	= IOMUX_PIN(0xff, 172),
-	MX31_PIN_PC_BVD1	= IOMUX_PIN(0xff, 173),
-	MX31_PIN_PC_VS2		= IOMUX_PIN(0xff, 174),
-	MX31_PIN_PC_VS1		= IOMUX_PIN(0xff, 175),
-	MX31_PIN_PC_PWRON	= IOMUX_PIN(0xff, 176),
-	MX31_PIN_PC_READY	= IOMUX_PIN(0xff, 177),
-	MX31_PIN_PC_WAIT_B	= IOMUX_PIN(0xff, 178),
-	MX31_PIN_PC_CD2_B	= IOMUX_PIN(0xff, 179),
-	MX31_PIN_PC_CD1_B	= IOMUX_PIN(0xff, 180),
-	MX31_PIN_D0		= IOMUX_PIN(0xff, 181),
-	MX31_PIN_D1		= IOMUX_PIN(0xff, 182),
-	MX31_PIN_D2		= IOMUX_PIN(0xff, 183),
-	MX31_PIN_D3		= IOMUX_PIN(0xff, 184),
-	MX31_PIN_D4		= IOMUX_PIN(0xff, 185),
-	MX31_PIN_D5		= IOMUX_PIN(0xff, 186),
-	MX31_PIN_D6		= IOMUX_PIN(0xff, 187),
-	MX31_PIN_D7		= IOMUX_PIN(0xff, 188),
-	MX31_PIN_D8		= IOMUX_PIN(0xff, 189),
-	MX31_PIN_D9		= IOMUX_PIN(0xff, 190),
-	MX31_PIN_D10		= IOMUX_PIN(0xff, 191),
-	MX31_PIN_D11		= IOMUX_PIN(0xff, 192),
-	MX31_PIN_D12		= IOMUX_PIN(0xff, 193),
-	MX31_PIN_D13		= IOMUX_PIN(0xff, 194),
-	MX31_PIN_D14		= IOMUX_PIN(0xff, 195),
-	MX31_PIN_D15		= IOMUX_PIN(0xff, 196),
-	MX31_PIN_NFRB		= IOMUX_PIN(16,   197),
-	MX31_PIN_NFCE_B		= IOMUX_PIN(15,   198),
-	MX31_PIN_NFWP_B		= IOMUX_PIN(14,   199),
-	MX31_PIN_NFCLE		= IOMUX_PIN(13,   200),
-	MX31_PIN_NFALE		= IOMUX_PIN(12,   201),
-	MX31_PIN_NFRE_B		= IOMUX_PIN(11,   202),
-	MX31_PIN_NFWE_B		= IOMUX_PIN(10,   203),
-	MX31_PIN_SDQS3		= IOMUX_PIN(0xff, 204),
-	MX31_PIN_SDQS2		= IOMUX_PIN(0xff, 205),
-	MX31_PIN_SDQS1		= IOMUX_PIN(0xff, 206),
-	MX31_PIN_SDQS0		= IOMUX_PIN(0xff, 207),
-	MX31_PIN_SDCLK_B	= IOMUX_PIN(0xff, 208),
-	MX31_PIN_SDCLK		= IOMUX_PIN(0xff, 209),
-	MX31_PIN_SDCKE1		= IOMUX_PIN(0xff, 210),
-	MX31_PIN_SDCKE0		= IOMUX_PIN(0xff, 211),
-	MX31_PIN_SDWE		= IOMUX_PIN(0xff, 212),
-	MX31_PIN_CAS		= IOMUX_PIN(0xff, 213),
-	MX31_PIN_RAS		= IOMUX_PIN(0xff, 214),
-	MX31_PIN_RW		= IOMUX_PIN(0xff, 215),
-	MX31_PIN_BCLK		= IOMUX_PIN(0xff, 216),
-	MX31_PIN_LBA		= IOMUX_PIN(0xff, 217),
-	MX31_PIN_ECB		= IOMUX_PIN(0xff, 218),
-	MX31_PIN_CS5		= IOMUX_PIN(0xff, 219),
-	MX31_PIN_CS4		= IOMUX_PIN(0xff, 220),
-	MX31_PIN_CS3		= IOMUX_PIN(0xff, 221),
-	MX31_PIN_CS2		= IOMUX_PIN(0xff, 222),
-	MX31_PIN_CS1		= IOMUX_PIN(0xff, 223),
-	MX31_PIN_CS0		= IOMUX_PIN(0xff, 224),
-	MX31_PIN_OE		= IOMUX_PIN(0xff, 225),
-	MX31_PIN_EB1		= IOMUX_PIN(0xff, 226),
-	MX31_PIN_EB0		= IOMUX_PIN(0xff, 227),
-	MX31_PIN_DQM3		= IOMUX_PIN(0xff, 228),
-	MX31_PIN_DQM2		= IOMUX_PIN(0xff, 229),
-	MX31_PIN_DQM1		= IOMUX_PIN(0xff, 230),
-	MX31_PIN_DQM0		= IOMUX_PIN(0xff, 231),
-	MX31_PIN_SD31		= IOMUX_PIN(0xff, 232),
-	MX31_PIN_SD30		= IOMUX_PIN(0xff, 233),
-	MX31_PIN_SD29		= IOMUX_PIN(0xff, 234),
-	MX31_PIN_SD28		= IOMUX_PIN(0xff, 235),
-	MX31_PIN_SD27		= IOMUX_PIN(0xff, 236),
-	MX31_PIN_SD26		= IOMUX_PIN(0xff, 237),
-	MX31_PIN_SD25		= IOMUX_PIN(0xff, 238),
-	MX31_PIN_SD24		= IOMUX_PIN(0xff, 239),
-	MX31_PIN_SD23		= IOMUX_PIN(0xff, 240),
-	MX31_PIN_SD22		= IOMUX_PIN(0xff, 241),
-	MX31_PIN_SD21		= IOMUX_PIN(0xff, 242),
-	MX31_PIN_SD20		= IOMUX_PIN(0xff, 243),
-	MX31_PIN_SD19		= IOMUX_PIN(0xff, 244),
-	MX31_PIN_SD18		= IOMUX_PIN(0xff, 245),
-	MX31_PIN_SD17		= IOMUX_PIN(0xff, 246),
-	MX31_PIN_SD16		= IOMUX_PIN(0xff, 247),
-	MX31_PIN_SD15		= IOMUX_PIN(0xff, 248),
-	MX31_PIN_SD14		= IOMUX_PIN(0xff, 249),
-	MX31_PIN_SD13		= IOMUX_PIN(0xff, 250),
-	MX31_PIN_SD12		= IOMUX_PIN(0xff, 251),
-	MX31_PIN_SD11		= IOMUX_PIN(0xff, 252),
-	MX31_PIN_SD10		= IOMUX_PIN(0xff, 253),
-	MX31_PIN_SD9		= IOMUX_PIN(0xff, 254),
-	MX31_PIN_SD8		= IOMUX_PIN(0xff, 255),
-	MX31_PIN_SD7		= IOMUX_PIN(0xff, 256),
-	MX31_PIN_SD6		= IOMUX_PIN(0xff, 257),
-	MX31_PIN_SD5		= IOMUX_PIN(0xff, 258),
-	MX31_PIN_SD4		= IOMUX_PIN(0xff, 259),
-	MX31_PIN_SD3		= IOMUX_PIN(0xff, 260),
-	MX31_PIN_SD2		= IOMUX_PIN(0xff, 261),
-	MX31_PIN_SD1		= IOMUX_PIN(0xff, 262),
-	MX31_PIN_SD0		= IOMUX_PIN(0xff, 263),
-	MX31_PIN_SDBA0		= IOMUX_PIN(0xff, 264),
-	MX31_PIN_SDBA1		= IOMUX_PIN(0xff, 265),
-	MX31_PIN_A25		= IOMUX_PIN(0xff, 266),
-	MX31_PIN_A24		= IOMUX_PIN(0xff, 267),
-	MX31_PIN_A23		= IOMUX_PIN(0xff, 268),
-	MX31_PIN_A22		= IOMUX_PIN(0xff, 269),
-	MX31_PIN_A21		= IOMUX_PIN(0xff, 270),
-	MX31_PIN_A20		= IOMUX_PIN(0xff, 271),
-	MX31_PIN_A19		= IOMUX_PIN(0xff, 272),
-	MX31_PIN_A18		= IOMUX_PIN(0xff, 273),
-	MX31_PIN_A17		= IOMUX_PIN(0xff, 274),
-	MX31_PIN_A16		= IOMUX_PIN(0xff, 275),
-	MX31_PIN_A14		= IOMUX_PIN(0xff, 276),
-	MX31_PIN_A15		= IOMUX_PIN(0xff, 277),
-	MX31_PIN_A13		= IOMUX_PIN(0xff, 278),
-	MX31_PIN_A12		= IOMUX_PIN(0xff, 279),
-	MX31_PIN_A11		= IOMUX_PIN(0xff, 280),
-	MX31_PIN_MA10		= IOMUX_PIN(0xff, 281),
-	MX31_PIN_A10		= IOMUX_PIN(0xff, 282),
-	MX31_PIN_A9		= IOMUX_PIN(0xff, 283),
-	MX31_PIN_A8		= IOMUX_PIN(0xff, 284),
-	MX31_PIN_A7		= IOMUX_PIN(0xff, 285),
-	MX31_PIN_A6		= IOMUX_PIN(0xff, 286),
-	MX31_PIN_A5		= IOMUX_PIN(0xff, 287),
-	MX31_PIN_A4		= IOMUX_PIN(0xff, 288),
-	MX31_PIN_A3		= IOMUX_PIN(0xff, 289),
-	MX31_PIN_A2		= IOMUX_PIN(0xff, 290),
-	MX31_PIN_A1		= IOMUX_PIN(0xff, 291),
-	MX31_PIN_A0		= IOMUX_PIN(0xff, 292),
-	MX31_PIN_VPG1		= IOMUX_PIN(0xff, 293),
-	MX31_PIN_VPG0		= IOMUX_PIN(0xff, 294),
-	MX31_PIN_DVFS1		= IOMUX_PIN(0xff, 295),
-	MX31_PIN_DVFS0		= IOMUX_PIN(0xff, 296),
-	MX31_PIN_VSTBY		= IOMUX_PIN(0xff, 297),
-	MX31_PIN_POWER_FAIL	= IOMUX_PIN(0xff, 298),
-	MX31_PIN_CKIL		= IOMUX_PIN(0xff, 299),
-	MX31_PIN_BOOT_MODE4	= IOMUX_PIN(0xff, 300),
-	MX31_PIN_BOOT_MODE3	= IOMUX_PIN(0xff, 301),
-	MX31_PIN_BOOT_MODE2	= IOMUX_PIN(0xff, 302),
-	MX31_PIN_BOOT_MODE1	= IOMUX_PIN(0xff, 303),
-	MX31_PIN_BOOT_MODE0	= IOMUX_PIN(0xff, 304),
-	MX31_PIN_CLKO		= IOMUX_PIN(0xff, 305),
-	MX31_PIN_POR_B		= IOMUX_PIN(0xff, 306),
-	MX31_PIN_RESET_IN_B	= IOMUX_PIN(0xff, 307),
-	MX31_PIN_CKIH		= IOMUX_PIN(0xff, 308),
-	MX31_PIN_SIMPD0		= IOMUX_PIN(35,   309),
-	MX31_PIN_SRX0		= IOMUX_PIN(34,   310),
-	MX31_PIN_STX0		= IOMUX_PIN(33,   311),
-	MX31_PIN_SVEN0		= IOMUX_PIN(32,   312),
-	MX31_PIN_SRST0		= IOMUX_PIN(67,   313),
-	MX31_PIN_SCLK0		= IOMUX_PIN(66,   314),
-	MX31_PIN_GPIO3_1	= IOMUX_PIN(65,   315),
-	MX31_PIN_GPIO3_0	= IOMUX_PIN(64,   316),
-	MX31_PIN_GPIO1_6	= IOMUX_PIN( 6,   317),
-	MX31_PIN_GPIO1_5	= IOMUX_PIN( 5,   318),
-	MX31_PIN_GPIO1_4	= IOMUX_PIN( 4,   319),
-	MX31_PIN_GPIO1_3	= IOMUX_PIN( 3,   320),
-	MX31_PIN_GPIO1_2	= IOMUX_PIN( 2,   321),
-	MX31_PIN_GPIO1_1	= IOMUX_PIN( 1,   322),
-	MX31_PIN_GPIO1_0	= IOMUX_PIN( 0,   323),
-	MX31_PIN_PWMO		= IOMUX_PIN( 9,   324),
-	MX31_PIN_WATCHDOG_RST	= IOMUX_PIN(0xff, 325),
-	MX31_PIN_COMPARE	= IOMUX_PIN( 8,   326),
-	MX31_PIN_CAPTURE	= IOMUX_PIN( 7,   327),
-};
-
-#define PIN_MAX 327
-#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */
-
-/*
- * Convenience values for use with mxc_iomux_mode()
- *
- * Format here is MX31_PIN_(pin name)__(function)
- */
-#define MX31_PIN_CSPI3_MOSI__RXD3	IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI3_MISO__TXD3	IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI3_SCLK__RTS3	IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI3_SPI_RDY__CTS3	IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CTS1__CTS1		IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RTS1__RTS1		IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RTS1__SFS		IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_TXD1__TXD1		IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_TXD1__SCK		IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_RXD1__RXD1		IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RXD1__STXDA		IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_DCD_DCE1__DCD_DCE1	IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RI_DCE1__RI_DCE1	IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DSR_DCE1__DSR_DCE1	IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DTR_DCE1__DTR_DCE1	IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DTR_DCE1__SRXDA	IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_CTS2__CTS2		IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RTS2__RTS2		IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_TXD2__TXD2		IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RXD2__RXD2		IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DCD_DTE1__DCD_DTE2	IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_RI_DTE1__RI_DTE2	IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_DSR_DTE1__DSR_DTE2	IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_DTR_DTE1__DTR_DTE2	IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
-#define MX31_PIN_PC_RST__CTS5		IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_PC_VS2__RTS5		IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_PC_BVD2__TXD5		IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_PC_BVD1__RXD5		IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_CSPI1_MOSI__MOSI	IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_MISO__MISO	IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SCLK__SCLK	IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY	IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SS0__SS0		IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SS1__SS1		IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SS2__SS2		IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_MOSI__MOSI	IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_MOSI__SCL	IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI2_MISO__MISO	IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_MISO__SDA	IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI2_SCLK__SCLK	IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY	IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SS0__SS0		IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SS1__SS1		IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SS2__SS2		IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_MOSI__MOSI	IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_MISO__MISO	IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_SCLK__SCLK	IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY	IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_BATT_LINE__OWIRE	IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CS4__CS4		IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA3__SD1_DATA3	IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA2__SD1_DATA2	IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA1__SD1_DATA1	IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA0__SD1_DATA0	IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_CLK__SD1_CLK	IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_CMD__SD1_CMD	IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_ATA_CS0__GPIO3_26	IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_CS1__GPIO3_27	IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_PC_PWRON__SD2_DATA3	IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_VS1__SD2_DATA2	IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_READY__SD2_DATA1	IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_WAIT_B__SD2_DATA0	IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD2_B__SD2_CLK	IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD1_B__SD2_CMD	IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_ATA_DIOR__GPIO3_28	IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_DIOW__GPIO3_29	IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_LD0__LD0		IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD1__LD1		IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD2__LD2		IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD3__LD3		IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD4__LD4		IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD5__LD5		IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD6__LD6		IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD7__LD7		IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD8__LD8		IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD9__LD9		IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD10__LD10		IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD11__LD11		IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD12__LD12		IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD13__LD13		IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD14__LD14		IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD15__LD15		IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD16__LD16		IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD17__LD17		IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_VSYNC3__VSYNC3		IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_HSYNC__HSYNC		IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_FPSHIFT__FPSHIFT	IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DRDY0__DRDY0		IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_D3_REV__D3_REV		IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CONTRAST__CONTRAST	IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_D3_SPL__D3_SPL		IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_D3_CLS__D3_CLS		IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO1_1__GPIO          IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DCD_DTE1__I2C2_SDA	IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_RI_DTE1__I2C2_SCL	IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_CSPI2_SS2__I2C3_SDA	IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI2_SCLK__I2C3_SCL	IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSI_D4__CSI_D4		IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D5__CSI_D5		IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D6__CSI_D6		IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D7__CSI_D7		IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D8__CSI_D8		IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D9__CSI_D9		IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D10__CSI_D10	IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D11__CSI_D11	IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D12__CSI_D12	IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D13__CSI_D13	IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D14__CSI_D14	IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D15__CSI_D15	IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_HSYNC__CSI_HSYNC	IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_MCLK__CSI_MCLK	IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK	IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_VSYNC__CSI_VSYNC	IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO3_0__GPIO3_0	IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO3_1__GPIO3_1	IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_TXD2__GPIO1_28		IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSI_D4__GPIO3_4	IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSI_D5__GPIO3_5	IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0	IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1	IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2	IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3	IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4	IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5	IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6	IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7	IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_CLK__USBOTG_CLK		IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DIR__USBOTG_DIR		IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_NXT__USBOTG_NXT		IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_STP__USBOTG_STP		IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM		IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_MISO__USBH1_RXDP		IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SS0__USBH1_TXDM		IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SS1__USBH1_TXDP		IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SS2__USBH1_RCV		IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SCLK__USBH1_OEB		IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS	IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_SFS6__USBH1_SUSPEND	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_NFRE_B__GPIO1_11	IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_NFALE__GPIO1_12	IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_USBH2_DATA0__USBH2_DATA0	IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_DATA1__USBH2_DATA1	IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_STXD3__USBH2_DATA2	IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD3__USBH2_DATA3	IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK3__USBH2_DATA4	IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SFS3__USBH2_DATA5	IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_STXD6__USBH2_DATA6	IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD6__USBH2_DATA7	IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_CLK__USBH2_CLK		IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_DIR__USBH2_DIR		IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_NXT__USBH2_NXT		IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_STP__USBH2_STP		IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK6__GPIO1_25		IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_USB_OC__GPIO1_30	IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_I2C_DAT__I2C1_SDA	IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_I2C_CLK__I2C1_SCL	IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO1_0__GPIO1_0	IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SVEN0__GPIO2_0		IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_STX0__GPIO2_1		IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SRX0__GPIO2_2		IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SIMPD0__GPIO2_3	IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DTR_DCE1__GPIO2_8	IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DSR_DCE1__GPIO2_9	IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_RI_DCE1__GPIO2_10	IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DCD_DCE1__GPIO2_11	IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_STXD5__GPIO1_21	IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SRXD5__GPIO1_22	IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO1_3__GPIO1_3	IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSPI2_SS1__CSPI3_SS1	IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_RTS1__GPIO2_6		IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CTS1__GPIO2_7		IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_LCS0__GPIO3_23		IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_STXD4__STXD4		IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD4__SRXD4		IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK4__SCK4		IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SFS4__SFS4		IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_STXD5__STXD5		IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD5__SRXD5		IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK5__SCK5		IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SFS5__SFS5		IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW0_KEY_ROW0	IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW1_KEY_ROW1	IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW2_KEY_ROW2	IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW3_KEY_ROW3	IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW4_KEY_ROW4	IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW4_GPIO		IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_KEY_ROW5_KEY_ROW5	IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW6_KEY_ROW6	IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW7_KEY_ROW7	IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL0_KEY_COL0	IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL1_KEY_COL1	IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL2_KEY_COL2	IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL3_KEY_COL3	IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL4_KEY_COL4	IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL5_KEY_COL5	IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL6_KEY_COL6	IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL7_KEY_COL7	IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST	IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC)
-
-
-/*
- * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
- * cspi2_ss1, cspi1_ss0 cspi1_ss1
- */
-
-/*
- * This function configures the pad value for a IOMUX pin.
- */
-void imx_iomux_set_pad(enum iomux_pins, u32);
-
-#endif /* ifndef __MACH_IOMUX_MX3_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx35.h b/arch/arm/mach-imx/include/mach/iomux-mx35.h
deleted file mode 100644
index 18f9a11171..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx35.h
+++ /dev/null
@@ -1,1253 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2009 Jan Weitzel <armlinux@phytec.de>, Phytec Messtechnik GmbH */
-
-#ifndef __MACH_IOMUX_MX35_H__
-#define __MACH_IOMUX_MX35_H__
-
-#include <mach/iomux-v3.h>
-
-/*
- * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num> see also iomux-v3.h
- */
-
-/*									  PAD    MUX   ALT INPSE PATH */
-#define MX35_PAD_CAPTURE__GPT_CAPIN1				IOMUX_PAD(0x328, 0x004, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__GPT_CMPOUT2				IOMUX_PAD(0x328, 0x004, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__CSPI2_SS1				IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__EPIT1_EPITO				IOMUX_PAD(0x328, 0x004, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__CCM_CLK32K				IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__GPIO1_4				IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_COMPARE__GPT_CMPOUT1				IOMUX_PAD(0x32c, 0x008, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__GPT_CAPIN2				IOMUX_PAD(0x32c, 0x008, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__GPT_CMPOUT3				IOMUX_PAD(0x32c, 0x008, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__EPIT2_EPITO				IOMUX_PAD(0x32c, 0x008, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__GPIO1_5				IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__SDMA_EXTDMA_2				IOMUX_PAD(0x32c, 0x008, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_WDOG_RST__WDOG_WDOG_B				IOMUX_PAD(0x330, 0x00c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE			IOMUX_PAD(0x330, 0x00c, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_WDOG_RST__GPIO1_6				IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO1_0__GPIO1_0				IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY				IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_0__OWIRE_LINE				IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0				IOMUX_PAD(0x334, 0x010, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO1_1__GPIO1_1				IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__PWM_PWMO				IOMUX_PAD(0x338, 0x014, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__CSPI1_SS2				IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT			IOMUX_PAD(0x338, 0x014, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1				IOMUX_PAD(0x338, 0x014, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO2_0__GPIO2_0				IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK			IOMUX_PAD(0x33c, 0x018, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO3_0__GPIO3_0				IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK			IOMUX_PAD(0x340, 0x01c, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B			IOMUX_PAD(0x344, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_POR_B__CCM_POR_B				IOMUX_PAD(0x348, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CLKO__CCM_CLKO					IOMUX_PAD(0x34c, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CLKO__GPIO1_8					IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0			IOMUX_PAD(0x350, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1			IOMUX_PAD(0x354, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0			IOMUX_PAD(0x358, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1			IOMUX_PAD(0x35c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26		IOMUX_PAD(0x360, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_VSTBY__CCM_VSTBY				IOMUX_PAD(0x364, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_VSTBY__GPIO1_7					IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A0__EMI_EIM_DA_L_0				IOMUX_PAD(0x368, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A1__EMI_EIM_DA_L_1				IOMUX_PAD(0x36c, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A2__EMI_EIM_DA_L_2				IOMUX_PAD(0x370, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A3__EMI_EIM_DA_L_3				IOMUX_PAD(0x374, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A4__EMI_EIM_DA_L_4				IOMUX_PAD(0x378, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A5__EMI_EIM_DA_L_5				IOMUX_PAD(0x37c, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A6__EMI_EIM_DA_L_6				IOMUX_PAD(0x380, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A7__EMI_EIM_DA_L_7				IOMUX_PAD(0x384, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A8__EMI_EIM_DA_H_8				IOMUX_PAD(0x388, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A9__EMI_EIM_DA_H_9				IOMUX_PAD(0x38c, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A10__EMI_EIM_DA_H_10				IOMUX_PAD(0x390, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_MA10__EMI_MA10					IOMUX_PAD(0x394, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A11__EMI_EIM_DA_H_11				IOMUX_PAD(0x398, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A12__EMI_EIM_DA_H_12				IOMUX_PAD(0x39c, 0x05c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A13__EMI_EIM_DA_H_13				IOMUX_PAD(0x3a0, 0x060, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A14__EMI_EIM_DA_H2_14				IOMUX_PAD(0x3a4, 0x064, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A15__EMI_EIM_DA_H2_15				IOMUX_PAD(0x3a8, 0x068, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A16__EMI_EIM_A_16				IOMUX_PAD(0x3ac, 0x06c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A17__EMI_EIM_A_17				IOMUX_PAD(0x3b0, 0x070, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A18__EMI_EIM_A_18				IOMUX_PAD(0x3b4, 0x074, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A19__EMI_EIM_A_19				IOMUX_PAD(0x3b8, 0x078, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A20__EMI_EIM_A_20				IOMUX_PAD(0x3bc, 0x07c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A21__EMI_EIM_A_21				IOMUX_PAD(0x3c0, 0x080, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A22__EMI_EIM_A_22				IOMUX_PAD(0x3c4, 0x084, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A23__EMI_EIM_A_23				IOMUX_PAD(0x3c8, 0x088, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A24__EMI_EIM_A_24				IOMUX_PAD(0x3cc, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_A25__EMI_EIM_A_25				IOMUX_PAD(0x3d0, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDBA1__EMI_EIM_SDBA1				IOMUX_PAD(0x3d4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDBA0__EMI_EIM_SDBA0				IOMUX_PAD(0x3d8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD0__EMI_DRAM_D_0				IOMUX_PAD(0x3dc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1__EMI_DRAM_D_1				IOMUX_PAD(0x3e0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2__EMI_DRAM_D_2				IOMUX_PAD(0x3e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD3__EMI_DRAM_D_3				IOMUX_PAD(0x3e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD4__EMI_DRAM_D_4				IOMUX_PAD(0x3ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD5__EMI_DRAM_D_5				IOMUX_PAD(0x3f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD6__EMI_DRAM_D_6				IOMUX_PAD(0x3f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD7__EMI_DRAM_D_7				IOMUX_PAD(0x3f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD8__EMI_DRAM_D_8				IOMUX_PAD(0x3fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD9__EMI_DRAM_D_9				IOMUX_PAD(0x400, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD10__EMI_DRAM_D_10				IOMUX_PAD(0x404, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD11__EMI_DRAM_D_11				IOMUX_PAD(0x408, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD12__EMI_DRAM_D_12				IOMUX_PAD(0x40c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD13__EMI_DRAM_D_13				IOMUX_PAD(0x410, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD14__EMI_DRAM_D_14				IOMUX_PAD(0x414, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD15__EMI_DRAM_D_15				IOMUX_PAD(0x418, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD16__EMI_DRAM_D_16				IOMUX_PAD(0x41c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD17__EMI_DRAM_D_17				IOMUX_PAD(0x420, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD18__EMI_DRAM_D_18				IOMUX_PAD(0x424, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD19__EMI_DRAM_D_19				IOMUX_PAD(0x428, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD20__EMI_DRAM_D_20				IOMUX_PAD(0x42c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD21__EMI_DRAM_D_21				IOMUX_PAD(0x430, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD22__EMI_DRAM_D_22				IOMUX_PAD(0x434, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD23__EMI_DRAM_D_23				IOMUX_PAD(0x438, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD24__EMI_DRAM_D_24				IOMUX_PAD(0x43c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD25__EMI_DRAM_D_25				IOMUX_PAD(0x440, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD26__EMI_DRAM_D_26				IOMUX_PAD(0x444, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD27__EMI_DRAM_D_27				IOMUX_PAD(0x448, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD28__EMI_DRAM_D_28				IOMUX_PAD(0x44c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD29__EMI_DRAM_D_29				IOMUX_PAD(0x450, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD30__EMI_DRAM_D_30				IOMUX_PAD(0x454, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD31__EMI_DRAM_D_31				IOMUX_PAD(0x458, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM0__EMI_DRAM_DQM_0				IOMUX_PAD(0x45c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM1__EMI_DRAM_DQM_1				IOMUX_PAD(0x460, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM2__EMI_DRAM_DQM_2				IOMUX_PAD(0x464, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM3__EMI_DRAM_DQM_3				IOMUX_PAD(0x468, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_EB0__EMI_EIM_EB0_B				IOMUX_PAD(0x46c, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_EB1__EMI_EIM_EB1_B				IOMUX_PAD(0x470, 0x098, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_OE__EMI_EIM_OE					IOMUX_PAD(0x474, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS0__EMI_EIM_CS0				IOMUX_PAD(0x478, 0x0a0, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS1__EMI_EIM_CS1				IOMUX_PAD(0x47c, 0x0a4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS1__EMI_NANDF_CE3				IOMUX_PAD(0x47c, 0x0a4, 3, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS2__EMI_EIM_CS2				IOMUX_PAD(0x480, 0x0a8, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS3__EMI_EIM_CS3				IOMUX_PAD(0x484, 0x0ac, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS4__EMI_EIM_CS4				IOMUX_PAD(0x488, 0x0b0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS4__EMI_DTACK_B				IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS4__EMI_NANDF_CE1				IOMUX_PAD(0x488, 0x0b0, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS4__GPIO1_20					IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS5__EMI_EIM_CS5				IOMUX_PAD(0x48c, 0x0b4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS5__CSPI2_SS2					IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS5__CSPI1_SS2					IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL)
-#define MX35_PAD_CS5__EMI_NANDF_CE2				IOMUX_PAD(0x48c, 0x0b4, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CS5__GPIO1_21					IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_NF_CE0__EMI_NANDF_CE0				IOMUX_PAD(0x490, 0x0b8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NF_CE0__GPIO1_22				IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ECB__EMI_EIM_ECB				IOMUX_PAD(0x494, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LBA__EMI_EIM_LBA				IOMUX_PAD(0x498, 0x0bc, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_BCLK__EMI_EIM_BCLK				IOMUX_PAD(0x49c, 0x0c0, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RW__EMI_EIM_RW					IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RAS__EMI_DRAM_RAS				IOMUX_PAD(0x4a4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CAS__EMI_DRAM_CAS				IOMUX_PAD(0x4a8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDWE__EMI_DRAM_SDWE				IOMUX_PAD(0x4ac, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0			IOMUX_PAD(0x4b0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1			IOMUX_PAD(0x4b4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK				IOMUX_PAD(0x4b8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0				IOMUX_PAD(0x4bc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1				IOMUX_PAD(0x4c0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2				IOMUX_PAD(0x4c4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3				IOMUX_PAD(0x4c8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B				IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3			IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC			IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__GPIO2_18				IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0			IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B				IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR			IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK				IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__GPIO2_19				IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1			IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFALE__EMI_NANDF_ALE				IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__USB_TOP_USBH2_STP			IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__IPU_DISPB_CS0				IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__GPIO2_20				IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2			IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFCLE__EMI_NANDF_CLE				IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT			IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS			IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__GPIO2_21				IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3			IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B				IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7			IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__IPU_DISPB_WR				IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__GPIO2_22				IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL			IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFRB__EMI_NANDF_RB				IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFRB__IPU_DISPB_RD				IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_NFRB__GPIO2_23					IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK				IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D15__EMI_EIM_D_15				IOMUX_PAD(0x4e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D14__EMI_EIM_D_14				IOMUX_PAD(0x4e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D13__EMI_EIM_D_13				IOMUX_PAD(0x4ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D12__EMI_EIM_D_12				IOMUX_PAD(0x4f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D11__EMI_EIM_D_11				IOMUX_PAD(0x4f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D10__EMI_EIM_D_10				IOMUX_PAD(0x4f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D9__EMI_EIM_D_9				IOMUX_PAD(0x4fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D8__EMI_EIM_D_8				IOMUX_PAD(0x500, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D7__EMI_EIM_D_7				IOMUX_PAD(0x504, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D6__EMI_EIM_D_6				IOMUX_PAD(0x508, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D5__EMI_EIM_D_5				IOMUX_PAD(0x50c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D4__EMI_EIM_D_4				IOMUX_PAD(0x510, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3__EMI_EIM_D_3				IOMUX_PAD(0x514, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D2__EMI_EIM_D_2				IOMUX_PAD(0x518, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D1__EMI_EIM_D_1				IOMUX_PAD(0x51c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D0__EMI_EIM_D_0				IOMUX_PAD(0x520, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D8__IPU_CSI_D_8				IOMUX_PAD(0x524, 0x0e0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D8__KPP_COL_0				IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D8__GPIO1_20				IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13			IOMUX_PAD(0x524, 0x0e0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D9__IPU_CSI_D_9				IOMUX_PAD(0x528, 0x0e4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D9__KPP_COL_1				IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D9__GPIO1_21				IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14			IOMUX_PAD(0x528, 0x0e4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D10__IPU_CSI_D_10				IOMUX_PAD(0x52c, 0x0e8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D10__KPP_COL_2				IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D10__GPIO1_22				IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15			IOMUX_PAD(0x52c, 0x0e8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D11__IPU_CSI_D_11				IOMUX_PAD(0x530, 0x0ec, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D11__KPP_COL_3				IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D11__GPIO1_23				IOMUX_PAD(0x530, 0x0ec, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D12__IPU_CSI_D_12				IOMUX_PAD(0x534, 0x0f0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D12__KPP_ROW_0				IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D12__GPIO1_24				IOMUX_PAD(0x534, 0x0f0, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D13__IPU_CSI_D_13				IOMUX_PAD(0x538, 0x0f4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D13__KPP_ROW_1				IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D13__GPIO1_25				IOMUX_PAD(0x538, 0x0f4, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D14__IPU_CSI_D_14				IOMUX_PAD(0x53c, 0x0f8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D14__KPP_ROW_2				IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D14__GPIO1_26				IOMUX_PAD(0x53c, 0x0f8, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D15__IPU_CSI_D_15				IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D15__KPP_ROW_3				IOMUX_PAD(0x540, 0x0fc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D15__GPIO1_27				IOMUX_PAD(0x540, 0x0fc, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK				IOMUX_PAD(0x544, 0x100, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_MCLK__GPIO1_28				IOMUX_PAD(0x544, 0x100, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC			IOMUX_PAD(0x548, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_VSYNC__GPIO1_29				IOMUX_PAD(0x548, 0x104, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC			IOMUX_PAD(0x54c, 0x108, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_HSYNC__GPIO1_30				IOMUX_PAD(0x54c, 0x108, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK			IOMUX_PAD(0x550, 0x10c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_PIXCLK__GPIO1_31				IOMUX_PAD(0x550, 0x10c, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C1_CLK__I2C1_SCL				IOMUX_PAD(0x554, 0x110, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C1_CLK__GPIO2_24				IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK			IOMUX_PAD(0x554, 0x110, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C1_DAT__I2C1_SDA				IOMUX_PAD(0x558, 0x114, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C1_DAT__GPIO2_25				IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C2_CLK__I2C2_SCL				IOMUX_PAD(0x55c, 0x118, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__CAN1_TXCAN				IOMUX_PAD(0x55c, 0x118, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR			IOMUX_PAD(0x55c, 0x118, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__GPIO2_26				IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2		IOMUX_PAD(0x55c, 0x118, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C2_DAT__I2C2_SDA				IOMUX_PAD(0x560, 0x11c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__CAN1_RXCAN				IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC			IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__GPIO2_27				IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3		IOMUX_PAD(0x560, 0x11c, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD				IOMUX_PAD(0x564, 0x120, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXD4__GPIO2_28				IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0		IOMUX_PAD(0x564, 0x120, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD				IOMUX_PAD(0x568, 0x124, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD4__GPIO2_29				IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1		IOMUX_PAD(0x568, 0x124, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC				IOMUX_PAD(0x56c, 0x128, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SCK4__GPIO2_30					IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2			IOMUX_PAD(0x56c, 0x128, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS			IOMUX_PAD(0x570, 0x12c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS4__GPIO2_31				IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3		IOMUX_PAD(0x570, 0x12c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD				IOMUX_PAD(0x574, 0x130, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1			IOMUX_PAD(0x574, 0x130, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__CSPI2_MOSI				IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__GPIO1_0					IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4		IOMUX_PAD(0x574, 0x130, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD				IOMUX_PAD(0x578, 0x134, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1				IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__CSPI2_MISO				IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__GPIO1_1					IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5		IOMUX_PAD(0x578, 0x134, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC				IOMUX_PAD(0x57c, 0x138, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK			IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__CSPI2_SCLK				IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__GPIO1_2					IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6			IOMUX_PAD(0x57c, 0x138, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS			IOMUX_PAD(0x580, 0x13c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS5__CSPI2_RDY				IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS5__GPIO1_3				IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7		IOMUX_PAD(0x580, 0x13c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCKR__ESAI_SCKR				IOMUX_PAD(0x584, 0x140, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SCKR__GPIO1_4					IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL)
-#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10			IOMUX_PAD(0x584, 0x140, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FSR__ESAI_FSR					IOMUX_PAD(0x588, 0x144, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FSR__GPIO1_5					IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL)
-#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11			IOMUX_PAD(0x588, 0x144, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_HCKR__ESAI_HCKR				IOMUX_PAD(0x58c, 0x148, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS				IOMUX_PAD(0x58c, 0x148, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__CSPI2_SS0				IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__IPU_FLASH_STROBE				IOMUX_PAD(0x58c, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__GPIO1_6					IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12			IOMUX_PAD(0x58c, 0x148, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCKT__ESAI_SCKT				IOMUX_PAD(0x590, 0x14c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SCKT__GPIO1_7					IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL)
-#define MX35_PAD_SCKT__IPU_CSI_D_0				IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCKT__KPP_ROW_2				IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_FST__ESAI_FST					IOMUX_PAD(0x594, 0x150, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FST__GPIO1_8					IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL)
-#define MX35_PAD_FST__IPU_CSI_D_1				IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL)
-#define MX35_PAD_FST__KPP_ROW_3					IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_HCKT__ESAI_HCKT				IOMUX_PAD(0x598, 0x154, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC				IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__GPIO1_9					IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__IPU_CSI_D_2				IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__KPP_COL_3				IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0				IOMUX_PAD(0x59c, 0x158, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC			IOMUX_PAD(0x59c, 0x158, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__CSPI2_SS2				IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__CAN2_TXCAN				IOMUX_PAD(0x59c, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__UART2_DTR				IOMUX_PAD(0x59c, 0x158, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__GPIO1_10				IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0		IOMUX_PAD(0x59c, 0x158, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1				IOMUX_PAD(0x5a0, 0x15c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS			IOMUX_PAD(0x5a0, 0x15c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__CSPI2_SS3				IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__CAN2_RXCAN				IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__UART2_DSR				IOMUX_PAD(0x5a0, 0x15c, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__GPIO1_11				IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__IPU_CSI_D_3				IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__KPP_ROW_0				IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2				IOMUX_PAD(0x5a4, 0x160, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__I2C3_SCL				IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1				IOMUX_PAD(0x5a4, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__GPIO1_12				IOMUX_PAD(0x5a4, 0x160, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__IPU_CSI_D_4				IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__KPP_ROW_1				IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3				IOMUX_PAD(0x5a8, 0x164, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__I2C3_SDA				IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2				IOMUX_PAD(0x5a8, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__GPIO1_13				IOMUX_PAD(0x5a8, 0x164, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__IPU_CSI_D_5				IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__KPP_COL_0				IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX1__ESAI_TX1					IOMUX_PAD(0x5ac, 0x168, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__CCM_PMIC_RDY				IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX1__CSPI1_SS2					IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL)
-#define MX35_PAD_TX1__EMI_NANDF_CE3				IOMUX_PAD(0x5ac, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__UART2_RI					IOMUX_PAD(0x5ac, 0x168, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__GPIO1_14					IOMUX_PAD(0x5ac, 0x168, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__IPU_CSI_D_6				IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__KPP_COL_1					IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX0__ESAI_TX0					IOMUX_PAD(0x5b0, 0x16c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK			IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX0__CSPI1_SS3					IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__EMI_DTACK_B				IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX0__UART2_DCD					IOMUX_PAD(0x5b0, 0x16c, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__GPIO1_15					IOMUX_PAD(0x5b0, 0x16c, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__IPU_CSI_D_7				IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__KPP_COL_2					IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI				IOMUX_PAD(0x5b4, 0x170, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MOSI__GPIO1_16				IOMUX_PAD(0x5b4, 0x170, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2		IOMUX_PAD(0x5b4, 0x170, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_MISO__CSPI1_MISO				IOMUX_PAD(0x5b8, 0x174, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MISO__GPIO1_17				IOMUX_PAD(0x5b8, 0x174, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3		IOMUX_PAD(0x5b8, 0x174, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SS0__CSPI1_SS0				IOMUX_PAD(0x5bc, 0x178, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__OWIRE_LINE				IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__CSPI2_SS3				IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__GPIO1_18				IOMUX_PAD(0x5bc, 0x178, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4			IOMUX_PAD(0x5bc, 0x178, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SS1__CSPI1_SS1				IOMUX_PAD(0x5c0, 0x17c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__PWM_PWMO				IOMUX_PAD(0x5c0, 0x17c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__CCM_CLK32K				IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__GPIO1_19				IOMUX_PAD(0x5c0, 0x17c, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29			IOMUX_PAD(0x5c0, 0x17c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5			IOMUX_PAD(0x5c0, 0x17c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK				IOMUX_PAD(0x5c4, 0x180, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SCLK__GPIO3_4				IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30			IOMUX_PAD(0x5c4, 0x180, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1		IOMUX_PAD(0x5c4, 0x180, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY			IOMUX_PAD(0x5c8, 0x184, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5				IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31			IOMUX_PAD(0x5c8, 0x184, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2	IOMUX_PAD(0x5c8, 0x184, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RXD1__UART1_RXD_MUX				IOMUX_PAD(0x5cc, 0x188, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__CSPI2_MOSI				IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__KPP_COL_4				IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__GPIO3_6					IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16			IOMUX_PAD(0x5cc, 0x188, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TXD1__UART1_TXD_MUX				IOMUX_PAD(0x5d0, 0x18c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__CSPI2_MISO				IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__KPP_COL_5				IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__GPIO3_7					IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17			IOMUX_PAD(0x5d0, 0x18c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RTS1__UART1_RTS				IOMUX_PAD(0x5d4, 0x190, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__CSPI2_SCLK				IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__I2C3_SCL					IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__IPU_CSI_D_0				IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__KPP_COL_6				IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__GPIO3_8					IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__EMI_NANDF_CE1				IOMUX_PAD(0x5d4, 0x190, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18			IOMUX_PAD(0x5d4, 0x190, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CTS1__UART1_CTS				IOMUX_PAD(0x5d8, 0x194, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__CSPI2_RDY				IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__I2C3_SDA					IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__IPU_CSI_D_1				IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__KPP_COL_7				IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__GPIO3_9					IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__EMI_NANDF_CE2				IOMUX_PAD(0x5d8, 0x194, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19			IOMUX_PAD(0x5d8, 0x194, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RXD2__UART2_RXD_MUX				IOMUX_PAD(0x5dc, 0x198, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RXD2__KPP_ROW_4				IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD2__GPIO3_10					IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TXD2__UART2_TXD_MUX				IOMUX_PAD(0x5e0, 0x19c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK			IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL)
-#define MX35_PAD_TXD2__KPP_ROW_5				IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD2__GPIO3_11					IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RTS2__UART2_RTS				IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1				IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__CAN2_RXCAN				IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__IPU_CSI_D_2				IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__KPP_ROW_6				IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__GPIO3_12					IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC				IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__UART3_RXD_MUX				IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CTS2__UART2_CTS				IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1				IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__CAN2_TXCAN				IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__IPU_CSI_D_3				IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__KPP_ROW_7				IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__GPIO3_13					IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS				IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__UART3_TXD_MUX				IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_RTCK__ARM11P_TOP_RTCK				IOMUX_PAD(0x5ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TCK__SJC_TCK					IOMUX_PAD(0x5f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TMS__SJC_TMS					IOMUX_PAD(0x5f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TDI__SJC_TDI					IOMUX_PAD(0x5f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TDO__SJC_TDO					IOMUX_PAD(0x5fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TRSTB__SJC_TRSTB				IOMUX_PAD(0x600, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_DE_B__SJC_DE_B					IOMUX_PAD(0x604, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SJC_MOD__SJC_MOD				IOMUX_PAD(0x608, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR			IOMUX_PAD(0x60c, 0x1a8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR			IOMUX_PAD(0x60c, 0x1a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_PWR__GPIO3_14				IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC			IOMUX_PAD(0x610, 0x1ac, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC			IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_OC__GPIO3_15				IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD0__IPU_DISPB_DAT_0				IOMUX_PAD(0x614, 0x1b0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD0__GPIO2_0					IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0			IOMUX_PAD(0x614, 0x1b0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD1__IPU_DISPB_DAT_1				IOMUX_PAD(0x618, 0x1b4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD1__GPIO2_1					IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1			IOMUX_PAD(0x618, 0x1b4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD2__IPU_DISPB_DAT_2				IOMUX_PAD(0x61c, 0x1b8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD2__GPIO2_2					IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2			IOMUX_PAD(0x61c, 0x1b8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD3__IPU_DISPB_DAT_3				IOMUX_PAD(0x620, 0x1bc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD3__GPIO2_3					IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3			IOMUX_PAD(0x620, 0x1bc, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD4__IPU_DISPB_DAT_4				IOMUX_PAD(0x624, 0x1c0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD4__GPIO2_4					IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4			IOMUX_PAD(0x624, 0x1c0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD5__IPU_DISPB_DAT_5				IOMUX_PAD(0x628, 0x1c4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD5__GPIO2_5					IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5			IOMUX_PAD(0x628, 0x1c4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD6__IPU_DISPB_DAT_6				IOMUX_PAD(0x62c, 0x1c8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD6__GPIO2_6					IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6			IOMUX_PAD(0x62c, 0x1c8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD7__IPU_DISPB_DAT_7				IOMUX_PAD(0x630, 0x1cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD7__GPIO2_7					IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7			IOMUX_PAD(0x630, 0x1cc, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD8__IPU_DISPB_DAT_8				IOMUX_PAD(0x634, 0x1d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD8__GPIO2_8					IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8			IOMUX_PAD(0x634, 0x1d0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD9__IPU_DISPB_DAT_9				IOMUX_PAD(0x638, 0x1d4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD9__GPIO2_9					IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9			IOMUX_PAD(0x638, 0x1d4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD10__IPU_DISPB_DAT_10				IOMUX_PAD(0x63c, 0x1d8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD10__GPIO2_10					IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10			IOMUX_PAD(0x63c, 0x1d8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD11__IPU_DISPB_DAT_11				IOMUX_PAD(0x640, 0x1dc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD11__GPIO2_11					IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11			IOMUX_PAD(0x640, 0x1dc, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4			IOMUX_PAD(0x640, 0x1dc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD12__IPU_DISPB_DAT_12				IOMUX_PAD(0x644, 0x1e0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD12__GPIO2_12					IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12			IOMUX_PAD(0x644, 0x1e0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5			IOMUX_PAD(0x644, 0x1e0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD13__IPU_DISPB_DAT_13				IOMUX_PAD(0x648, 0x1e4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD13__GPIO2_13					IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13			IOMUX_PAD(0x648, 0x1e4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6			IOMUX_PAD(0x648, 0x1e4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD14__IPU_DISPB_DAT_14				IOMUX_PAD(0x64c, 0x1e8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD14__GPIO2_14					IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0		IOMUX_PAD(0x64c, 0x1e8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7			IOMUX_PAD(0x64c, 0x1e8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD15__IPU_DISPB_DAT_15				IOMUX_PAD(0x650, 0x1ec, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD15__GPIO2_15					IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1		IOMUX_PAD(0x650, 0x1ec, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8			IOMUX_PAD(0x650, 0x1ec, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD16__IPU_DISPB_DAT_16				IOMUX_PAD(0x654, 0x1f0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC			IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__GPIO2_16					IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2		IOMUX_PAD(0x654, 0x1f0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9			IOMUX_PAD(0x654, 0x1f0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD17__IPU_DISPB_DAT_17				IOMUX_PAD(0x658, 0x1f4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__IPU_DISPB_CS2				IOMUX_PAD(0x658, 0x1f4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__GPIO2_17					IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3		IOMUX_PAD(0x658, 0x1f4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10			IOMUX_PAD(0x658, 0x1f4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD18__IPU_DISPB_DAT_18				IOMUX_PAD(0x65c, 0x1f8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC			IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC			IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD18__ESDHC3_CMD				IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3			IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__GPIO3_24					IOMUX_PAD(0x65c, 0x1f8, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4		IOMUX_PAD(0x65c, 0x1f8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11			IOMUX_PAD(0x65c, 0x1f8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD19__IPU_DISPB_DAT_19				IOMUX_PAD(0x660, 0x1fc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__IPU_DISPB_BCLK				IOMUX_PAD(0x660, 0x1fc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__IPU_DISPB_CS1				IOMUX_PAD(0x660, 0x1fc, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__ESDHC3_CLK				IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR			IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__GPIO3_25					IOMUX_PAD(0x660, 0x1fc, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5		IOMUX_PAD(0x660, 0x1fc, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12			IOMUX_PAD(0x660, 0x1fc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD20__IPU_DISPB_DAT_20				IOMUX_PAD(0x664, 0x200, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__IPU_DISPB_CS0				IOMUX_PAD(0x664, 0x200, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__IPU_DISPB_SD_CLK				IOMUX_PAD(0x664, 0x200, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__ESDHC3_DAT0				IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__GPIO3_26					IOMUX_PAD(0x664, 0x200, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3		IOMUX_PAD(0x664, 0x200, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13			IOMUX_PAD(0x664, 0x200, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD21__IPU_DISPB_DAT_21				IOMUX_PAD(0x668, 0x204, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__IPU_DISPB_PAR_RS				IOMUX_PAD(0x668, 0x204, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__IPU_DISPB_SER_RS				IOMUX_PAD(0x668, 0x204, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__ESDHC3_DAT1				IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__USB_TOP_USBOTG_STP			IOMUX_PAD(0x668, 0x204, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__GPIO3_27					IOMUX_PAD(0x668, 0x204, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL		IOMUX_PAD(0x668, 0x204, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14			IOMUX_PAD(0x668, 0x204, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD22__IPU_DISPB_DAT_22				IOMUX_PAD(0x66c, 0x208, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__IPU_DISPB_WR				IOMUX_PAD(0x66c, 0x208, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__IPU_DISPB_SD_D_I				IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__ESDHC3_DAT2				IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT			IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__GPIO3_28					IOMUX_PAD(0x66c, 0x208, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR			IOMUX_PAD(0x66c, 0x208, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__ARM11P_TOP_TRCTL				IOMUX_PAD(0x66c, 0x208, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD23__IPU_DISPB_DAT_23				IOMUX_PAD(0x670, 0x20c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__IPU_DISPB_RD				IOMUX_PAD(0x670, 0x20c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO			IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD23__ESDHC3_DAT3				IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7			IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__GPIO3_29					IOMUX_PAD(0x670, 0x20c, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS			IOMUX_PAD(0x670, 0x20c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__ARM11P_TOP_TRCLK				IOMUX_PAD(0x670, 0x20c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC			IOMUX_PAD(0x674, 0x210, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO			IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__GPIO3_30				IOMUX_PAD(0x674, 0x210, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE		IOMUX_PAD(0x674, 0x210, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15			IOMUX_PAD(0x674, 0x210, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK			IOMUX_PAD(0x678, 0x214, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK			IOMUX_PAD(0x678, 0x214, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__GPIO3_31				IOMUX_PAD(0x678, 0x214, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0	IOMUX_PAD(0x678, 0x214, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16		IOMUX_PAD(0x678, 0x214, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY			IOMUX_PAD(0x67c, 0x218, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O			IOMUX_PAD(0x67c, 0x218, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__GPIO1_0				IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1		IOMUX_PAD(0x67c, 0x218, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17			IOMUX_PAD(0x67c, 0x218, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR			IOMUX_PAD(0x680, 0x21c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CONTRAST__GPIO1_1				IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL)
-#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2	IOMUX_PAD(0x680, 0x21c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18			IOMUX_PAD(0x680, 0x21c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC			IOMUX_PAD(0x684, 0x220, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1			IOMUX_PAD(0x684, 0x220, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__GPIO1_2				IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD			IOMUX_PAD(0x684, 0x220, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19			IOMUX_PAD(0x684, 0x220, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV			IOMUX_PAD(0x688, 0x224, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS			IOMUX_PAD(0x688, 0x224, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__GPIO1_3				IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB			IOMUX_PAD(0x688, 0x224, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20			IOMUX_PAD(0x688, 0x224, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS			IOMUX_PAD(0x68c, 0x228, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__IPU_DISPB_CS2				IOMUX_PAD(0x68c, 0x228, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__GPIO1_4				IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0		IOMUX_PAD(0x68c, 0x228, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21			IOMUX_PAD(0x68c, 0x228, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL			IOMUX_PAD(0x690, 0x22c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC			IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__GPIO1_5				IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1		IOMUX_PAD(0x690, 0x22c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22			IOMUX_PAD(0x690, 0x22c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_CMD__ESDHC1_CMD				IOMUX_PAD(0x694, 0x230, 0x10, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__MSHC_SCLK				IOMUX_PAD(0x694, 0x230, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC			IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4			IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__GPIO1_6				IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL			IOMUX_PAD(0x694, 0x230, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_CLK__ESDHC1_CLK				IOMUX_PAD(0x698, 0x234, 0x10, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__MSHC_BS				IOMUX_PAD(0x698, 0x234, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK			IOMUX_PAD(0x698, 0x234, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5			IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__GPIO1_7				IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK			IOMUX_PAD(0x698, 0x234, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0				IOMUX_PAD(0x69c, 0x238, 0x10, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__MSHC_DATA_0				IOMUX_PAD(0x69c, 0x238, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0			IOMUX_PAD(0x69c, 0x238, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6		IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__GPIO1_8				IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23			IOMUX_PAD(0x69c, 0x238, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1				IOMUX_PAD(0x6a0, 0x23c, 0x10, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__MSHC_DATA_1				IOMUX_PAD(0x6a0, 0x23c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS			IOMUX_PAD(0x6a0, 0x23c, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0		IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__GPIO1_9				IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24			IOMUX_PAD(0x6a0, 0x23c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2				IOMUX_PAD(0x6a4, 0x240, 0x10, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__MSHC_DATA_2				IOMUX_PAD(0x6a4, 0x240, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR			IOMUX_PAD(0x6a4, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1		IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__GPIO1_10				IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25			IOMUX_PAD(0x6a4, 0x240, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3				IOMUX_PAD(0x6a8, 0x244, 0x10, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__MSHC_DATA_3				IOMUX_PAD(0x6a8, 0x244, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD			IOMUX_PAD(0x6a8, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2		IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__GPIO1_11				IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26			IOMUX_PAD(0x6a8, 0x244, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_CMD__ESDHC2_CMD				IOMUX_PAD(0x6ac, 0x248, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__I2C3_SCL				IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__ESDHC1_DAT4				IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__IPU_CSI_D_2				IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4			IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__GPIO2_0				IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1			IOMUX_PAD(0x6ac, 0x248, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC			IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_CLK__ESDHC2_CLK				IOMUX_PAD(0x6b0, 0x24c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__I2C3_SDA				IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__ESDHC1_DAT5				IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__IPU_CSI_D_3				IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5			IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__GPIO2_1				IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1			IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2				IOMUX_PAD(0x6b0, 0x24c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0				IOMUX_PAD(0x6b4, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX			IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6				IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4				IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6		IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__GPIO2_2				IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK			IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1				IOMUX_PAD(0x6b8, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX			IOMUX_PAD(0x6b8, 0x254, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7				IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5				IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0		IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__GPIO2_3				IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2				IOMUX_PAD(0x6bc, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__UART3_RTS				IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__CAN1_RXCAN				IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6				IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1		IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__GPIO2_4				IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3				IOMUX_PAD(0x6c0, 0x25c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__UART3_CTS				IOMUX_PAD(0x6c0, 0x25c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__CAN1_TXCAN				IOMUX_PAD(0x6c0, 0x25c, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7				IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2		IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__GPIO2_5				IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_CS0__ATA_CS0				IOMUX_PAD(0x6c4, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__CSPI1_SS3				IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1				IOMUX_PAD(0x6c4, 0x260, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__GPIO2_6				IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__IPU_DIAGB_0				IOMUX_PAD(0x6c4, 0x260, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0		IOMUX_PAD(0x6c4, 0x260, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_CS1__ATA_CS1				IOMUX_PAD(0x6c8, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2				IOMUX_PAD(0x6c8, 0x264, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__CSPI2_SS0				IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__GPIO2_7				IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__IPU_DIAGB_1				IOMUX_PAD(0x6c8, 0x264, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1		IOMUX_PAD(0x6c8, 0x264, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DIOR__ATA_DIOR				IOMUX_PAD(0x6cc, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0				IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR			IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0			IOMUX_PAD(0x6cc, 0x268, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__CSPI2_SS1				IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__GPIO2_8				IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2				IOMUX_PAD(0x6cc, 0x268, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2		IOMUX_PAD(0x6cc, 0x268, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DIOW__ATA_DIOW				IOMUX_PAD(0x6d0, 0x26c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1				IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP			IOMUX_PAD(0x6d0, 0x26c, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1			IOMUX_PAD(0x6d0, 0x26c, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__CSPI2_MOSI				IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__GPIO2_9				IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3				IOMUX_PAD(0x6d0, 0x26c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3		IOMUX_PAD(0x6d0, 0x26c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DMACK__ATA_DMACK				IOMUX_PAD(0x6d4, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2				IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT			IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__CSPI2_MISO				IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__GPIO2_10				IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4				IOMUX_PAD(0x6d4, 0x270, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0		IOMUX_PAD(0x6d4, 0x270, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_RESET_B__ATA_RESET_B			IOMUX_PAD(0x6d8, 0x274, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3			IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0		IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O			IOMUX_PAD(0x6d8, 0x274, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__CSPI2_RDY				IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__GPIO2_11				IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5			IOMUX_PAD(0x6d8, 0x274, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1		IOMUX_PAD(0x6d8, 0x274, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_IORDY__ATA_IORDY				IOMUX_PAD(0x6dc, 0x278, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4				IOMUX_PAD(0x6dc, 0x278, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1		IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO			IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4				IOMUX_PAD(0x6dc, 0x278, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__GPIO2_12				IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6				IOMUX_PAD(0x6dc, 0x278, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2		IOMUX_PAD(0x6dc, 0x278, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA0__ATA_DATA_0				IOMUX_PAD(0x6e0, 0x27c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5				IOMUX_PAD(0x6e0, 0x27c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2		IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC			IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5				IOMUX_PAD(0x6e0, 0x27c, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__GPIO2_13				IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7				IOMUX_PAD(0x6e0, 0x27c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3		IOMUX_PAD(0x6e0, 0x27c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA1__ATA_DATA_1				IOMUX_PAD(0x6e4, 0x280, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6				IOMUX_PAD(0x6e4, 0x280, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3		IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK			IOMUX_PAD(0x6e4, 0x280, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6				IOMUX_PAD(0x6e4, 0x280, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__GPIO2_14				IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8				IOMUX_PAD(0x6e4, 0x280, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27			IOMUX_PAD(0x6e4, 0x280, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA2__ATA_DATA_2				IOMUX_PAD(0x6e8, 0x284, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7				IOMUX_PAD(0x6e8, 0x284, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4		IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS			IOMUX_PAD(0x6e8, 0x284, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7				IOMUX_PAD(0x6e8, 0x284, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__GPIO2_15				IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9				IOMUX_PAD(0x6e8, 0x284, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28			IOMUX_PAD(0x6e8, 0x284, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA3__ATA_DATA_3				IOMUX_PAD(0x6e8, 0x288, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ESDHC3_CLK				IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5		IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__CSPI2_SCLK				IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__GPIO2_16				IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10			IOMUX_PAD(0x6e8, 0x288, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29			IOMUX_PAD(0x6e8, 0x288, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA4__ATA_DATA_4				IOMUX_PAD(0x6f0, 0x28c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__ESDHC3_CMD				IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6		IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__GPIO2_17				IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11			IOMUX_PAD(0x6f0, 0x28c, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30			IOMUX_PAD(0x6f0, 0x28c, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA5__ATA_DATA_5				IOMUX_PAD(0x6f4, 0x290, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7		IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__GPIO2_18				IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12			IOMUX_PAD(0x6f4, 0x290, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31			IOMUX_PAD(0x6f4, 0x290, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA6__ATA_DATA_6				IOMUX_PAD(0x6f8, 0x294, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__CAN1_TXCAN				IOMUX_PAD(0x6f8, 0x294, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__UART1_DTR				IOMUX_PAD(0x6f8, 0x294, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD			IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__GPIO2_19				IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13			IOMUX_PAD(0x6f8, 0x294, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA7__ATA_DATA_7				IOMUX_PAD(0x6fc, 0x298, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__CAN1_RXCAN				IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__UART1_DSR				IOMUX_PAD(0x6fc, 0x298, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD			IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__GPIO2_20				IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14			IOMUX_PAD(0x6fc, 0x298, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA8__ATA_DATA_8				IOMUX_PAD(0x700, 0x29c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__UART3_RTS				IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__UART1_RI				IOMUX_PAD(0x700, 0x29c, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC			IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__GPIO2_21				IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15			IOMUX_PAD(0x700, 0x29c, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA9__ATA_DATA_9				IOMUX_PAD(0x704, 0x2a0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__UART3_CTS				IOMUX_PAD(0x704, 0x2a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__UART1_DCD				IOMUX_PAD(0x704, 0x2a0, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS			IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__GPIO2_22				IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16			IOMUX_PAD(0x704, 0x2a0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA10__ATA_DATA_10			IOMUX_PAD(0x708, 0x2a4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX			IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC			IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__GPIO2_23				IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17			IOMUX_PAD(0x708, 0x2a4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA11__ATA_DATA_11			IOMUX_PAD(0x70c, 0x2a8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX			IOMUX_PAD(0x70c, 0x2a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS			IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__GPIO2_24				IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18			IOMUX_PAD(0x70c, 0x2a8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA12__ATA_DATA_12			IOMUX_PAD(0x710, 0x2ac, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA12__I2C3_SCL				IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA12__GPIO2_25				IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19			IOMUX_PAD(0x710, 0x2ac, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA13__ATA_DATA_13			IOMUX_PAD(0x714, 0x2b0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA13__I2C3_SDA				IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA13__GPIO2_26				IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20			IOMUX_PAD(0x714, 0x2b0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA14__ATA_DATA_14			IOMUX_PAD(0x718, 0x2b4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0			IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__KPP_ROW_0				IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__GPIO2_27				IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21			IOMUX_PAD(0x718, 0x2b4, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA15__ATA_DATA_15			IOMUX_PAD(0x71c, 0x2b8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1			IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__KPP_ROW_1				IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__GPIO2_28				IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22			IOMUX_PAD(0x71c, 0x2b8, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_INTRQ__ATA_INTRQ				IOMUX_PAD(0x720, 0x2bc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2				IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__KPP_ROW_2				IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__GPIO2_29				IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23			IOMUX_PAD(0x720, 0x2bc, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN			IOMUX_PAD(0x724, 0x2c0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3			IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3				IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__GPIO2_30				IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24			IOMUX_PAD(0x724, 0x2c0, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DMARQ__ATA_DMARQ				IOMUX_PAD(0x728, 0x2c4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4				IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__KPP_COL_0				IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__GPIO2_31				IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25			IOMUX_PAD(0x728, 0x2c4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4			IOMUX_PAD(0x728, 0x2c4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DA0__ATA_DA_0				IOMUX_PAD(0x72c, 0x2c8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__IPU_CSI_D_5				IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__KPP_COL_1				IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__GPIO3_0				IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__IPU_DIAGB_26				IOMUX_PAD(0x72c, 0x2c8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5			IOMUX_PAD(0x72c, 0x2c8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DA1__ATA_DA_1				IOMUX_PAD(0x730, 0x2cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__IPU_CSI_D_6				IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__KPP_COL_2				IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__GPIO3_1				IOMUX_PAD(0x730, 0x2cc, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__IPU_DIAGB_27				IOMUX_PAD(0x730, 0x2cc, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6			IOMUX_PAD(0x730, 0x2cc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DA2__ATA_DA_2				IOMUX_PAD(0x734, 0x2d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__IPU_CSI_D_7				IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__KPP_COL_3				IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__GPIO3_2				IOMUX_PAD(0x734, 0x2d0, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__IPU_DIAGB_28				IOMUX_PAD(0x734, 0x2d0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7			IOMUX_PAD(0x734, 0x2d0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_MLB_CLK__MLB_MLBCLK				IOMUX_PAD(0x738, 0x2d4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_MLB_CLK__GPIO3_3				IOMUX_PAD(0x738, 0x2d4, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_MLB_DAT__MLB_MLBDAT				IOMUX_PAD(0x73c, 0x2d8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_MLB_DAT__GPIO3_4				IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_MLB_SIG__MLB_MLBSIG				IOMUX_PAD(0x740, 0x2dc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_MLB_SIG__GPIO3_5				IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK				IOMUX_PAD(0x744, 0x2e0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4			IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX			IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR			IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI				IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__GPIO3_6				IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC		IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0		IOMUX_PAD(0x744, 0x2e0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK				IOMUX_PAD(0x748, 0x2e4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5			IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX			IOMUX_PAD(0x748, 0x2e4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP			IOMUX_PAD(0x748, 0x2e4, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO				IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__GPIO3_7				IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I			IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1		IOMUX_PAD(0x748, 0x2e4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RX_DV__FEC_RX_DV				IOMUX_PAD(0x74c, 0x2e8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6				IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__UART3_RTS				IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT			IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK				IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__GPIO3_8				IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK			IOMUX_PAD(0x74c, 0x2e8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2		IOMUX_PAD(0x74c, 0x2e8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_COL__FEC_COL				IOMUX_PAD(0x750, 0x2ec, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__ESDHC1_DAT7				IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__UART3_CTS				IOMUX_PAD(0x750, 0x2ec, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0			IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__CSPI2_RDY				IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__GPIO3_9				IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS			IOMUX_PAD(0x750, 0x2ec, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3			IOMUX_PAD(0x750, 0x2ec, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0			IOMUX_PAD(0x754, 0x2f0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__PWM_PWMO				IOMUX_PAD(0x754, 0x2f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__UART3_DTR				IOMUX_PAD(0x754, 0x2f0, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1		IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__CSPI2_SS0				IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__GPIO3_10				IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1			IOMUX_PAD(0x754, 0x2f0, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4		IOMUX_PAD(0x754, 0x2f0, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0			IOMUX_PAD(0x758, 0x2f4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1			IOMUX_PAD(0x758, 0x2f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__UART3_DSR				IOMUX_PAD(0x758, 0x2f4, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2		IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__CSPI2_SS1				IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__GPIO3_11				IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0			IOMUX_PAD(0x758, 0x2f4, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5		IOMUX_PAD(0x758, 0x2f4, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TX_EN__FEC_TX_EN				IOMUX_PAD(0x75c, 0x2f8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1			IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__UART3_RI				IOMUX_PAD(0x75c, 0x2f8, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3		IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__GPIO3_12				IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS			IOMUX_PAD(0x75c, 0x2f8, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6		IOMUX_PAD(0x75c, 0x2f8, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_MDC__FEC_MDC				IOMUX_PAD(0x760, 0x2fc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__CAN2_TXCAN				IOMUX_PAD(0x760, 0x2fc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__UART3_DCD				IOMUX_PAD(0x760, 0x2fc, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4			IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__GPIO3_13				IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__IPU_DISPB_WR				IOMUX_PAD(0x760, 0x2fc, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7			IOMUX_PAD(0x760, 0x2fc, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_MDIO__FEC_MDIO				IOMUX_PAD(0x764, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__CAN2_RXCAN				IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5			IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__GPIO3_14				IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD				IOMUX_PAD(0x764, 0x300, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8			IOMUX_PAD(0x764, 0x300, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR				IOMUX_PAD(0x768, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE				IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK			IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6		IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__GPIO3_15				IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC			IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9		IOMUX_PAD(0x768, 0x304, 7, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR				IOMUX_PAD(0x76c, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0			IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7		IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__KPP_COL_4				IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__GPIO3_16				IOMUX_PAD(0x76c, 0x308, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO			IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_CRS__FEC_CRS				IOMUX_PAD(0x770, 0x30c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__IPU_CSI_D_1				IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR			IOMUX_PAD(0x770, 0x30c, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__KPP_COL_5				IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__GPIO3_17				IOMUX_PAD(0x770, 0x30c, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE			IOMUX_PAD(0x770, 0x30c, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1			IOMUX_PAD(0x774, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2			IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC			IOMUX_PAD(0x774, 0x310, 2, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC			IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__KPP_COL_6				IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__GPIO3_18				IOMUX_PAD(0x774, 0x310, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0			IOMUX_PAD(0x774, 0x310, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1			IOMUX_PAD(0x778, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3			IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS			IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__KPP_COL_7				IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__GPIO3_19				IOMUX_PAD(0x778, 0x314, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1			IOMUX_PAD(0x778, 0x314, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2			IOMUX_PAD(0x77c, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4			IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD			IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__KPP_ROW_4				IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__GPIO3_20				IOMUX_PAD(0x77c, 0x318, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2			IOMUX_PAD(0x780, 0x31c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5			IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD			IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__KPP_ROW_5				IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__GPIO3_21				IOMUX_PAD(0x780, 0x31c, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3			IOMUX_PAD(0x784, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6			IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC			IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__KPP_ROW_6				IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__GPIO3_22				IOMUX_PAD(0x784, 0x320, 6, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3			IOMUX_PAD(0x788, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7			IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS			IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__KPP_ROW_7				IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__GPIO3_23				IOMUX_PAD(0x788, 0x324, 5, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK			IOMUX_PAD(0x78c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX35_PAD_TEST_MODE__TCU_TEST_MODE			IOMUX_PAD(0x790, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
-
-
-#endif /* __MACH_IOMUX_MX35_H__ */
-
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx50.h b/arch/arm/mach-imx/include/mach/iomux-mx50.h
deleted file mode 100644
index aeb47092df..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx50.h
+++ /dev/null
@@ -1,929 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2013 Greg Ungerer <gerg@uclinux.org> */
-/* SPDX-FileCopyrightText: 2016 Alexander Kurz <akurz@blala.de> */
-
-/* based on linux imx50-pinfunc.h */
-
-#ifndef __MACH_IOMUX_MX50_H__
-#define __MACH_IOMUX_MX50_H__
-
-#include <mach/iomux-v3.h>
-
-/* These 2 defines are for pins that may not have a mux register, but could
- * have a pad setting register, and vice-versa. */
-#define __NA_   0x00
-
-#define MX50_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH)
-#define MX50_SDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
-			    PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
-#define MX50_I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_ODE | \
-			   PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
-#define MX50_SPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
-
-#define MX50_PAD_KEY_COL0__KPP_COL_0			IOMUX_PAD(0x2CC, 0x020, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL0__GPIO4_0			IOMUX_PAD(0x2CC, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE		IOMUX_PAD(0x2CC, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL0__CTI_TRIGIN7			IOMUX_PAD(0x2CC, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY		IOMUX_PAD(0x2CC, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW0__KPP_ROW_0			IOMUX_PAD(0x2D0, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW0__GPIO4_1			IOMUX_PAD(0x2D0, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE		IOMUX_PAD(0x2D0, 0x024, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7		IOMUX_PAD(0x2D0, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID		IOMUX_PAD(0x2D0, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL1__KPP_COL_1			IOMUX_PAD(0x2D4, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL1__GPIO4_2			IOMUX_PAD(0x2D4, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0		IOMUX_PAD(0x2D4, 0x028, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6		IOMUX_PAD(0x2D4, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE		IOMUX_PAD(0x2D4, 0x028, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW1__KPP_ROW_1			IOMUX_PAD(0x2D8, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW1__GPIO4_3			IOMUX_PAD(0x2D8, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1		IOMUX_PAD(0x2D8, 0x02C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7		IOMUX_PAD(0x2D8, 0x02C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR		IOMUX_PAD(0x2D8, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL2__KPP_COL_1			IOMUX_PAD(0x2DC, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL2__GPIO4_4			IOMUX_PAD(0x2DC, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2		IOMUX_PAD(0x2DC, 0x030, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6			IOMUX_PAD(0x2DC, 0x030, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK		IOMUX_PAD(0x2DC, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW2__KPP_ROW_2			IOMUX_PAD(0x2E0, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW2__GPIO4_5			IOMUX_PAD(0x2E0, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3		IOMUX_PAD(0x2E0, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7			IOMUX_PAD(0x2E0, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0		IOMUX_PAD(0x2E0, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL3__KPP_COL_2			IOMUX_PAD(0x2E4, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL3__GPIO4_6			IOMUX_PAD(0x2E4, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0		IOMUX_PAD(0x2E4, 0x038, 2, 0x7B4, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0		IOMUX_PAD(0x2E4, 0x038, 6, 0x7B8, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1		IOMUX_PAD(0x2E4, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW3__KPP_ROW_3			IOMUX_PAD(0x2E8, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW3__GPIO4_7			IOMUX_PAD(0x2E8, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS		IOMUX_PAD(0x2E8, 0x03C, 2, 0x7B0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1		IOMUX_PAD(0x2E8, 0x03C, 6, 0x7BC, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID		IOMUX_PAD(0x2E8, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__I2C1_SCL			IOMUX_PAD(0x2EC, 0x040, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__GPIO6_18			IOMUX_PAD(0x2EC, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX		IOMUX_PAD(0x2EC, 0x040, 2, 0x7CC, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C1_SDA__I2C1_SDA			IOMUX_PAD(0x2F0, 0x044, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C1_SDA__GPIO6_19			IOMUX_PAD(0x2F0, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX		IOMUX_PAD(0x2F0, 0x044, 2, 0x7CC, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__I2C2_SCL			IOMUX_PAD(0x2F4, 0x048, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__GPIO6_20			IOMUX_PAD(0x2F4, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__UART2_CTS			IOMUX_PAD(0x2F4, 0x048, 2, __NA_, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__I2C2_SDA			IOMUX_PAD(0x2F8, 0x04C, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__GPIO6_21			IOMUX_PAD(0x2F8, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__UART2_RTS			IOMUX_PAD(0x2F8, 0x04C, 2, 0x7C8, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__I2C3_SCL			IOMUX_PAD(0x2FC, 0x050, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__GPIO6_22			IOMUX_PAD(0x2FC, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__FEC_MDC			IOMUX_PAD(0x2FC, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY			IOMUX_PAD(0x2FC, 0x050, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__GPT_CAPIN1			IOMUX_PAD(0x2FC, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0	IOMUX_PAD(0x2FC, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC		IOMUX_PAD(0x2FC, 0x050, 7, 0x7E8, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__I2C3_SDA			IOMUX_PAD(0x300, 0x054, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__GPIO6_23			IOMUX_PAD(0x300, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__FEC_MDIO			IOMUX_PAD(0x300, 0x054, 2, 0x774, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT		IOMUX_PAD(0x300, 0x054, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB		IOMUX_PAD(0x300, 0x054, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__GPT_CAPIN2			IOMUX_PAD(0x300, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1	IOMUX_PAD(0x300, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR		IOMUX_PAD(0x300, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__PWM1_PWMO			IOMUX_PAD(0x304, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__GPIO6_24				IOMUX_PAD(0x304, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__USBOH1_USBOTG_OC			IOMUX_PAD(0x304, 0x058, 2, 0x7E8, 1, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__GPT_CMPOUT1			IOMUX_PAD(0x304, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2	IOMUX_PAD(0x304, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__SJC_FAIL				IOMUX_PAD(0x304, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__PWM2_PWMO			IOMUX_PAD(0x308, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__GPIO6_25				IOMUX_PAD(0x308, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR		IOMUX_PAD(0x308, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__GPT_CMPOUT2			IOMUX_PAD(0x308, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3	IOMUX_PAD(0x308, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__SRC_ANY_PU_RST			IOMUX_PAD(0x308, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__OWIRE_LINE			IOMUX_PAD(0x30C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__GPIO6_26			IOMUX_PAD(0x30C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__USBOH1_USBH1_OC			IOMUX_PAD(0x30C, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK		IOMUX_PAD(0x30C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__EPDC_PWRIRQ			IOMUX_PAD(0x30C, 0x060, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__GPT_CMPOUT3			IOMUX_PAD(0x30C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4	IOMUX_PAD(0x30C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__SJC_JTAG_ACT			IOMUX_PAD(0x30C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__EPIT1_EPITO			IOMUX_PAD(0x310, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__GPIO6_27			IOMUX_PAD(0x310, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__USBOH1_USBH1_PWR		IOMUX_PAD(0x310, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK		IOMUX_PAD(0x310, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__DPLLIP1_TOG_EN			IOMUX_PAD(0x310, 0x064, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__GPT_CLK_IN			IOMUX_PAD(0x310, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__PMU_IRQ_B			IOMUX_PAD(0x310, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__SJC_DE_B			IOMUX_PAD(0x310, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__WDOG1_WDOG_B			IOMUX_PAD(0x314, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__GPIO6_28				IOMUX_PAD(0x314, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB		IOMUX_PAD(0x314, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__CCM_XTAL32K			IOMUX_PAD(0x314, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__SJC_DONE				IOMUX_PAD(0x314, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS		IOMUX_PAD(0x318, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXFS__GPIO6_0			IOMUX_PAD(0x318, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1		IOMUX_PAD(0x318, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8		IOMUX_PAD(0x318, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC		IOMUX_PAD(0x31C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXC__GPIO6_1			IOMUX_PAD(0x31C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0		IOMUX_PAD(0x31C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9		IOMUX_PAD(0x31C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD		IOMUX_PAD(0x320, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXD__GPIO6_2			IOMUX_PAD(0x320, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXD__CSPI_RDY			IOMUX_PAD(0x320, 0x074, 4, 0x6E8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10		IOMUX_PAD(0x320, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD		IOMUX_PAD(0x324, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXD__GPIO6_3			IOMUX_PAD(0x324, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXD__CSPI_SS3			IOMUX_PAD(0x324, 0x078, 4, 0x6F4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11		IOMUX_PAD(0x324, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS		IOMUX_PAD(0x328, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__GPIO6_4			IOMUX_PAD(0x328, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX		IOMUX_PAD(0x328, 0x07C, 2, 0x7E4, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6			IOMUX_PAD(0x328, 0x07C, 3, 0x804, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__CSPI_SS2			IOMUX_PAD(0x328, 0x07C, 4, 0x6F0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__FEC_COL			IOMUX_PAD(0x328, 0x07C, 5, 0x770, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__FEC_MDC			IOMUX_PAD(0x328, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12		IOMUX_PAD(0x328, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC		IOMUX_PAD(0x32C, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__GPIO6_5			IOMUX_PAD(0x32C, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__UART5_RXD_MUX			IOMUX_PAD(0x32C, 0x080, 2, 0x7E4, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7			IOMUX_PAD(0x32C, 0x080, 3, 0x808, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__CSPI_SS1			IOMUX_PAD(0x32C, 0x080, 4, 0x6EC, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__FEC_RX_CLK			IOMUX_PAD(0x32C, 0x080, 5, 0x780, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__FEC_MDIO			IOMUX_PAD(0x32C, 0x080, 6, 0x774, 1, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13		IOMUX_PAD(0x32C, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_TXD__UART1_TXD_MUX		IOMUX_PAD(0x330, 0x084, 0, 0x7C4, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_TXD__GPIO6_6			IOMUX_PAD(0x330, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14		IOMUX_PAD(0x330, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_RXD__UART1_RXD_MUX		IOMUX_PAD(0x334, 0x088, 0, 0x7C4, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RXD__GPIO6_7			IOMUX_PAD(0x334, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15		IOMUX_PAD(0x334, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__UART1_CTS			IOMUX_PAD(0x338, 0x08C, 0, __NA_, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__GPIO6_8			IOMUX_PAD(0x338, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__UART5_TXD_MUX		IOMUX_PAD(0x338, 0x08C, 2, 0x7E4, 2, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__ESDHC4_DAT4			IOMUX_PAD(0x338, 0x08C, 4, 0x760, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__ESDHC4_CMD			IOMUX_PAD(0x338, 0x08C, 5, 0x74C, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8		IOMUX_PAD(0x338, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__UART1_RTS			IOMUX_PAD(0x33C, 0x090, 0, 0x7C0, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__GPIO6_9			IOMUX_PAD(0x33C, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__UART5_RXD_MUX		IOMUX_PAD(0x33C, 0x090, 2, 0x7E4, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__ESDHC4_DAT5			IOMUX_PAD(0x33C, 0x090, 4, 0x764, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__ESDHC4_CLK			IOMUX_PAD(0x33C, 0x090, 5, 0x748, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9		IOMUX_PAD(0x33C, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__UART2_TXD_MUX		IOMUX_PAD(0x340, 0x094, 0, 0x7CC, 2, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__GPIO6_10			IOMUX_PAD(0x340, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__ESDHC4_DAT6			IOMUX_PAD(0x340, 0x094, 4, 0x768, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__ESDHC4_DAT4			IOMUX_PAD(0x340, 0x094, 5, 0x760, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10		IOMUX_PAD(0x340, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__UART2_RXD_MUX		IOMUX_PAD(0x344, 0x098, 0, 0x7CC, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__GPIO6_11			IOMUX_PAD(0x344, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__ESDHC4_DAT7			IOMUX_PAD(0x344, 0x098, 4, 0x76C, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__ESDHC4_DAT5			IOMUX_PAD(0x344, 0x098, 5, 0x764, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11		IOMUX_PAD(0x344, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__UART2_CTS			IOMUX_PAD(0x348, 0x09C, 0, __NA_, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__GPIO6_12			IOMUX_PAD(0x348, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__ESDHC4_CMD			IOMUX_PAD(0x348, 0x09C, 4, 0x74C, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__ESDHC4_DAT6			IOMUX_PAD(0x348, 0x09C, 5, 0x768, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12		IOMUX_PAD(0x348, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__UART2_RTS			IOMUX_PAD(0x34C, 0x0A0, 0, 0x7C8, 2, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__GPIO6_13			IOMUX_PAD(0x34C, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__ESDHC4_CLK			IOMUX_PAD(0x34C, 0x0A0, 4, 0x748, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__ESDHC4_DAT7			IOMUX_PAD(0x34C, 0x0A0, 5, 0x76C, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13		IOMUX_PAD(0x34C, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__UART3_TXD_MUX		IOMUX_PAD(0x350, 0x0A4, 0, 0x7D4, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__GPIO6_14			IOMUX_PAD(0x350, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__ESDHC1_DAT4			IOMUX_PAD(0x350, 0x0A4, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__ESDHC4_DAT0			IOMUX_PAD(0x350, 0x0A4, 4, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__ESDHC2_WP			IOMUX_PAD(0x350, 0x0A4, 5, 0x744, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12		IOMUX_PAD(0x350, 0x0A4, 6, 0x81C, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14		IOMUX_PAD(0x350, 0x0A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__UART3_RXD_MUX		IOMUX_PAD(0x354, 0x0A8, 0, 0x7D4, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__GPIO6_15			IOMUX_PAD(0x354, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__ESDHC1_DAT5			IOMUX_PAD(0x354, 0x0A8, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__ESDHC4_DAT1			IOMUX_PAD(0x354, 0x0A8, 4, 0x754, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__ESDHC2_CD			IOMUX_PAD(0x354, 0x0A8, 5, 0x740, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13		IOMUX_PAD(0x354, 0x0A8, 6, 0x820, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15		IOMUX_PAD(0x354, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__UART4_TXD_MUX		IOMUX_PAD(0x358, 0x0AC, 0, 0x7DC, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__GPIO6_16			IOMUX_PAD(0x358, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__UART3_CTS			IOMUX_PAD(0x358, 0x0AC, 2, 0x7D0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__ESDHC1_DAT6			IOMUX_PAD(0x358, 0x0AC, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__ESDHC4_DAT2			IOMUX_PAD(0x358, 0x0AC, 4, 0x758, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__ESDHC2_LCTL			IOMUX_PAD(0x358, 0x0AC, 5, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14		IOMUX_PAD(0x358, 0x0AC, 6, 0x824, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__UART4_RXD_MUX		IOMUX_PAD(0x35C, 0x0B0, 0, 0x7DC, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__GPIO6_17			IOMUX_PAD(0x35C, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__UART3_RTS			IOMUX_PAD(0x35C, 0x0B0, 2, 0x7D0, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__ESDHC1_DAT7			IOMUX_PAD(0x35C, 0x0B0, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__ESDHC4_DAT3			IOMUX_PAD(0x35C, 0x0B0, 4, 0x75C, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__ESDHC1_LCTL			IOMUX_PAD(0x35C, 0x0B0, 5, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15		IOMUX_PAD(0x35C, 0x0B0, 6, 0x828, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_SCLK__CSPI_SCLK			IOMUX_PAD(0x360, 0x0B4, 0, __NA_, 0, MX50_SPI_PAD_CTRL)
-#define MX50_PAD_CSPI_SCLK__GPIO4_8			IOMUX_PAD(0x360, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_MOSI__CSPI_MOSI			IOMUX_PAD(0x364, 0x0B8, 0, __NA_, 0, MX50_SPI_PAD_CTRL)
-#define MX50_PAD_CSPI_MOSI__GPIO4_9			IOMUX_PAD(0x364, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_MISO__CSPI_MISO			IOMUX_PAD(0x368, 0x0BC, 0, __NA_, 0, MX50_SPI_PAD_CTRL)
-#define MX50_PAD_CSPI_MISO__GPIO4_10			IOMUX_PAD(0x368, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_SS0__CSPI_SS0			IOMUX_PAD(0x36C, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_SS0__GPIO4_11			IOMUX_PAD(0x36C, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK		IOMUX_PAD(0x370, 0x0C4, 0, __NA_, 0, MX50_SPI_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__GPIO4_12			IOMUX_PAD(0x370, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY			IOMUX_PAD(0x370, 0x0C4, 2, 0x6E8, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY		IOMUX_PAD(0x370, 0x0C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__UART3_RTS			IOMUX_PAD(0x370, 0x0C4, 4, 0x7D0, 2, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6		IOMUX_PAD(0x370, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8		IOMUX_PAD(0x370, 0x0C4, 7, 0x80C, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI		IOMUX_PAD(0x374, 0x0C8, 0, __NA_, 0, MX50_SPI_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__GPIO4_13			IOMUX_PAD(0x374, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1			IOMUX_PAD(0x374, 0x0C8, 2, 0x6EC, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1		IOMUX_PAD(0x374, 0x0C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__UART3_CTS			IOMUX_PAD(0x374, 0x0C8, 4, __NA_, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7		IOMUX_PAD(0x374, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9		IOMUX_PAD(0x374, 0x0C8, 7, 0x810, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO		IOMUX_PAD(0x378, 0x0CC, 0, __NA_, 0, MX50_SPI_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__GPIO4_14			IOMUX_PAD(0x378, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__CSPI_SS2			IOMUX_PAD(0x378, 0x0CC, 2, 0x6F0, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2		IOMUX_PAD(0x378, 0x0CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__UART4_RTS			IOMUX_PAD(0x378, 0x0CC, 4, 0x7D8, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8		IOMUX_PAD(0x378, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10		IOMUX_PAD(0x378, 0x0CC, 7, 0x814, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0			IOMUX_PAD(0x37C, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__GPIO4_15			IOMUX_PAD(0x37C, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__CSPI_SS3			IOMUX_PAD(0x37C, 0x0D0, 2, 0x6F4, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3			IOMUX_PAD(0x37C, 0x0D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__UART4_CTS			IOMUX_PAD(0x37C, 0x0D0, 4, __NA_, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9		IOMUX_PAD(0x37C, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11		IOMUX_PAD(0x37C, 0x0D0, 7, 0x818, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK		IOMUX_PAD(0x380, 0x0D4, 0, __NA_, 0, MX50_SPI_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__GPIO4_16			IOMUX_PAD(0x380, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN		IOMUX_PAD(0x380, 0x0D4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY		IOMUX_PAD(0x380, 0x0D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__UART5_RTS			IOMUX_PAD(0x380, 0x0D4, 4, 0x7E0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK		IOMUX_PAD(0x380, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4		IOMUX_PAD(0x380, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8		IOMUX_PAD(0x380, 0x0D4, 7, 0x80C, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI		IOMUX_PAD(0x384, 0x0D8, 0, __NA_, 0, MX50_SPI_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__GPIO4_17			IOMUX_PAD(0x384, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E		IOMUX_PAD(0x384, 0x0D8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1		IOMUX_PAD(0x384, 0x0D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__UART5_CTS			IOMUX_PAD(0x384, 0x0D8, 4, 0x7E0, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE		IOMUX_PAD(0x384, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5		IOMUX_PAD(0x384, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9		IOMUX_PAD(0x384, 0x0D8, 7, 0x810, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO		IOMUX_PAD(0x388, 0x0DC, 0, __NA_, 0, MX50_SPI_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__GPIO4_18			IOMUX_PAD(0x388, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS			IOMUX_PAD(0x388, 0x0DC, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2		IOMUX_PAD(0x388, 0x0DC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX		IOMUX_PAD(0x388, 0x0DC, 4, 0x7E4, 4, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC		IOMUX_PAD(0x388, 0x0DC, 5, 0x73C, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6		IOMUX_PAD(0x388, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10		IOMUX_PAD(0x388, 0x0DC, 7, 0x814, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0			IOMUX_PAD(0x38C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__GPIO4_19			IOMUX_PAD(0x38C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS			IOMUX_PAD(0x38C, 0x0E0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3			IOMUX_PAD(0x38C, 0x0E0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX		IOMUX_PAD(0x38C, 0x0E0, 4, 0x7E4, 5, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC		IOMUX_PAD(0x38C, 0x0E0, 5, 0x6F8, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7		IOMUX_PAD(0x38C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11		IOMUX_PAD(0x38C, 0x0E0, 7, 0x818, 1, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CLK__ESDHC1_CLK			IOMUX_PAD(0x390, 0x0E4, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD1_CLK__GPIO5_0			IOMUX_PAD(0x390, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CLK__CCM_CLKO			IOMUX_PAD(0x390, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CMD__ESDHC1_CMD			IOMUX_PAD(0x394, 0x0E8, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD1_CMD__GPIO5_1			IOMUX_PAD(0x394, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CMD__CCM_CLKO2			IOMUX_PAD(0x394, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D0__ESDHC1_DAT0			IOMUX_PAD(0x398, 0x0EC, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD1_D0__GPIO5_2			IOMUX_PAD(0x398, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D0__CCM_PLL1_BYP			IOMUX_PAD(0x398, 0x0EC, 7, 0x6DC, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D1__ESDHC1_DAT1			IOMUX_PAD(0x39C, 0x0F0, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD1_D1__GPIO5_3			IOMUX_PAD(0x39C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D1__CCM_PLL2_BYP			IOMUX_PAD(0x39C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D2__ESDHC1_DAT2			IOMUX_PAD(0x3A0, 0x0F4, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD1_D2__GPIO5_4			IOMUX_PAD(0x3A0, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D2__CCM_PLL3_BYP			IOMUX_PAD(0x3A0, 0x0F4, 7, 0x6E4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D3__ESDHC1_DAT3			IOMUX_PAD(0x3A4, 0x0F8, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD1_D3__GPIO5_5			IOMUX_PAD(0x3A4, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CLK__ESDHC2_CLK			IOMUX_PAD(0x3A8, 0x0FC, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_CLK__GPIO5_6			IOMUX_PAD(0x3A8, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CLK__MSHC_SCLK			IOMUX_PAD(0x3A8, 0x0FC, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CMD__ESDHC2_CMD			IOMUX_PAD(0x3AC, 0x100, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_CMD__GPIO5_7			IOMUX_PAD(0x3AC, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CMD__MSHC_BS			IOMUX_PAD(0x3AC, 0x100, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D0__ESDHC2_DAT0			IOMUX_PAD(0x3B0, 0x104, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_D0__GPIO5_8			IOMUX_PAD(0x3B0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D0__MSHC_DATA_0			IOMUX_PAD(0x3B0, 0x104, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D0__KPP_COL_4			IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D1__ESDHC2_DAT1			IOMUX_PAD(0x3B4, 0x108, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_D1__GPIO5_9			IOMUX_PAD(0x3B4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D1__MSHC_DATA_1			IOMUX_PAD(0x3B4, 0x108, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D1__KPP_ROW_4			IOMUX_PAD(0x3B4, 0x108, 3, 0x7A0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D2__ESDHC2_DAT2			IOMUX_PAD(0x3B8, 0x10C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_D2__GPIO5_10			IOMUX_PAD(0x3B8, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D2__MSHC_DATA_2			IOMUX_PAD(0x3B8, 0x10C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D2__KPP_COL_5			IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D3__ESDHC2_DAT3			IOMUX_PAD(0x3BC, 0x110, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_D3__GPIO5_11			IOMUX_PAD(0x3BC, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D3__MSHC_DATA_3			IOMUX_PAD(0x3BC, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D3__KPP_ROW_5			IOMUX_PAD(0x3BC, 0x110, 3, 0x7A4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__ESDHC2_DAT4			IOMUX_PAD(0x3C0, 0x114, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_D4__GPIO5_12			IOMUX_PAD(0x3C0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS		IOMUX_PAD(0x3C0, 0x114, 2, 0x6D0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__KPP_COL_6			IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__EIM_WEIM_D_0			IOMUX_PAD(0x3C0, 0x114, 4, 0x7EC, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0			IOMUX_PAD(0x3C0, 0x114, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__ESDHC2_DAT5			IOMUX_PAD(0x3C4, 0x118, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_D5__GPIO5_13			IOMUX_PAD(0x3C4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC		IOMUX_PAD(0x3C4, 0x118, 2, 0x6CC, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__KPP_ROW_6			IOMUX_PAD(0x3C4, 0x118, 3, 0x7A8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__EIM_WEIM_D_1			IOMUX_PAD(0x3C4, 0x118, 4, 0x7F0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1			IOMUX_PAD(0x3C4, 0x118, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__ESDHC2_DAT6			IOMUX_PAD(0x3C8, 0x11C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_D6__GPIO5_14			IOMUX_PAD(0x3C8, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD		IOMUX_PAD(0x3C8, 0x11C, 2, 0x6C4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__KPP_COL_7			IOMUX_PAD(0x3C8, 0x11C, 3, 0x79C, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__EIM_WEIM_D_2			IOMUX_PAD(0x3C8, 0x11C, 4, 0x7F4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2			IOMUX_PAD(0x3C8, 0x11C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__ESDHC2_DAT7			IOMUX_PAD(0x3CC, 0x120, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_D7__GPIO5_15			IOMUX_PAD(0x3CC, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS		IOMUX_PAD(0x3CC, 0x120, 2, 0x6D8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__KPP_ROW_7			IOMUX_PAD(0x3CC, 0x120, 3, 0x7AC, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__EIM_WEIM_D_3			IOMUX_PAD(0x3CC, 0x120, 4, 0x7F8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__CCM_STOP			IOMUX_PAD(0x3CC, 0x120, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__ESDHC2_WP			IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_WP__GPIO5_16			IOMUX_PAD(0x3D0, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD		IOMUX_PAD(0x3D0, 0x124, 2, 0x6C8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__EIM_WEIM_D_4			IOMUX_PAD(0x3D0, 0x124, 4, 0x7FC, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__CCM_WAIT			IOMUX_PAD(0x3D0, 0x124, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__ESDHC2_CD			IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD2_CD__GPIO5_17			IOMUX_PAD(0x3D4, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC		IOMUX_PAD(0x3D4, 0x128, 2, 0x6D4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__EIM_WEIM_D_5			IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__CCM_REF_EN_B			IOMUX_PAD(0x3D4, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D0__ELCDIF_DAT_0			IOMUX_PAD(0x40C, 0x12C, 0, 0x6FC, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D0__GPIO2_0			IOMUX_PAD(0x40C, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D0__FEC_TX_CLK			IOMUX_PAD(0x40C, 0x12C, 2, 0x78C, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D0__EIM_WEIM_A_16			IOMUX_PAD(0x40C, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0		IOMUX_PAD(0x40C, 0x12C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0		IOMUX_PAD(0x40C, 0x12C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D1__ELCDIF_DAT_1			IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D1__GPIO2_1			IOMUX_PAD(0x410, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D1__FEC_RX_ERR			IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D1__EIM_WEIM_A_17			IOMUX_PAD(0x410, 0x130, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1		IOMUX_PAD(0x410, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1		IOMUX_PAD(0x410, 0x130, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D2__ELCDIF_DAT_2			IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D2__GPIO2_2			IOMUX_PAD(0x414, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D2__FEC_RX_DV			IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D2__EIM_WEIM_A_18			IOMUX_PAD(0x414, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2		IOMUX_PAD(0x414, 0x134, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2		IOMUX_PAD(0x414, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__ELCDIF_DAT_3			IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__GPIO2_3			IOMUX_PAD(0x418, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__FEC_RDATA_1			IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__EIM_WEIM_A_19			IOMUX_PAD(0x418, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__FEC_COL			IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3		IOMUX_PAD(0x418, 0x138, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3		IOMUX_PAD(0x418, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D4__ELCDIF_DAT_4			IOMUX_PAD(0x41C, 0x13C, 0, 0x70C, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D4__GPIO2_4			IOMUX_PAD(0x41C, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D4__FEC_RDATA_0			IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D4__EIM_WEIM_A_20			IOMUX_PAD(0x41C, 0x13C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4		IOMUX_PAD(0x41C, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4		IOMUX_PAD(0x41C, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D5__ELCDIF_DAT_5			IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D5__GPIO2_5			IOMUX_PAD(0x420, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D5__FEC_TX_EN			IOMUX_PAD(0x420, 0x140, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D5__EIM_WEIM_A_21			IOMUX_PAD(0x420, 0x140, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5		IOMUX_PAD(0x420, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5		IOMUX_PAD(0x420, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__ELCDIF_DAT_6			IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__GPIO2_6			IOMUX_PAD(0x424, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__FEC_TDATA_1			IOMUX_PAD(0x424, 0x144, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__EIM_WEIM_A_22			IOMUX_PAD(0x424, 0x144, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__FEC_RX_CLK			IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6		IOMUX_PAD(0x424, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6		IOMUX_PAD(0x424, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D7__ELCDIF_DAT_7			IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D7__GPIO2_7			IOMUX_PAD(0x428, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D7__FEC_TDATA_0			IOMUX_PAD(0x428, 0x148, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D7__EIM_WEIM_A_23			IOMUX_PAD(0x428, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7		IOMUX_PAD(0x428, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7		IOMUX_PAD(0x428, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN			IOMUX_PAD(0x42C, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_WR__GPIO2_16			IOMUX_PAD(0x42C, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK			IOMUX_PAD(0x42C, 0x14C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_WR__EIM_WEIM_A_24			IOMUX_PAD(0x42C, 0x14C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8		IOMUX_PAD(0x42C, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_WR__USBPHY1_AVALID		IOMUX_PAD(0x42C, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RD__ELCDIF_RD_E			IOMUX_PAD(0x430, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RD__GPIO2_19			IOMUX_PAD(0x430, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RD__ELCDIF_ENABLE			IOMUX_PAD(0x430, 0x150, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RD__EIM_WEIM_A_25			IOMUX_PAD(0x430, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9		IOMUX_PAD(0x430, 0x150, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RD__USBPHY1_BVALID		IOMUX_PAD(0x430, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__ELCDIF_RS			IOMUX_PAD(0x434, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__GPIO2_17			IOMUX_PAD(0x434, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__ELCDIF_VSYNC			IOMUX_PAD(0x434, 0x154, 2, 0x73C, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__EIM_WEIM_A_26			IOMUX_PAD(0x434, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10		IOMUX_PAD(0x434, 0x154, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION		IOMUX_PAD(0x434, 0x154, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__ELCDIF_CS			IOMUX_PAD(0x438, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__GPIO2_21			IOMUX_PAD(0x438, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__ELCDIF_HSYNC			IOMUX_PAD(0x438, 0x158, 2, 0x6F8, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__EIM_WEIM_A_27			IOMUX_PAD(0x438, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3			IOMUX_PAD(0x438, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11		IOMUX_PAD(0x438, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__USBPHY1_IDDIG			IOMUX_PAD(0x438, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY			IOMUX_PAD(0x43C, 0x15C, 0, 0x6F8, 2, NO_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__GPIO2_18			IOMUX_PAD(0x43C, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3		IOMUX_PAD(0x43C, 0x15C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12		IOMUX_PAD(0x43C, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT	IOMUX_PAD(0x43C, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__ELCDIF_RESET		IOMUX_PAD(0x440, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__GPIO2_20			IOMUX_PAD(0x440, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3		IOMUX_PAD(0x440, 0x160, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13		IOMUX_PAD(0x440, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK		IOMUX_PAD(0x440, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_CMD__ESDHC3_CMD			IOMUX_PAD(0x444, 0x164, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_CMD__GPIO5_18			IOMUX_PAD(0x444, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN			IOMUX_PAD(0x444, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_CMD__SSP_CMD			IOMUX_PAD(0x444, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_CLK__ESDHC3_CLK			IOMUX_PAD(0x448, 0x168, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_CLK__GPIO5_19			IOMUX_PAD(0x448, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN			IOMUX_PAD(0x448, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_CLK__SSP_CLK			IOMUX_PAD(0x448, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D0__ESDHC3_DAT0			IOMUX_PAD(0x44C, 0x16C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_D0__GPIO5_20			IOMUX_PAD(0x44C, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D0__EIM_NANDF_D_4			IOMUX_PAD(0x44C, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D0__SSP_D0				IOMUX_PAD(0x44C, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D0__CCM_PLL1_BYP			IOMUX_PAD(0x44C, 0x16C, 7, 0x6DC, 1, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D1__ESDHC3_DAT1			IOMUX_PAD(0x450, 0x170, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_D1__GPIO5_21			IOMUX_PAD(0x450, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D1__EIM_NANDF_D_5			IOMUX_PAD(0x450, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D1__SSP_D1				IOMUX_PAD(0x450, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D1__CCM_PLL2_BYP			IOMUX_PAD(0x450, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D2__ESDHC3_DAT2			IOMUX_PAD(0x454, 0x174, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_D2__GPIO5_22			IOMUX_PAD(0x454, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D2__EIM_NANDF_D_6			IOMUX_PAD(0x454, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D2__SSP_D2				IOMUX_PAD(0x454, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D2__CCM_PLL3_BYP			IOMUX_PAD(0x454, 0x174, 7, 0x6E4, 1, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D3__ESDHC3_DAT3			IOMUX_PAD(0x458, 0x178, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_D3__GPIO5_23			IOMUX_PAD(0x458, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D3__EIM_NANDF_D_7			IOMUX_PAD(0x458, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D3__SSP_D3				IOMUX_PAD(0x458, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D4__ESDHC3_DAT4			IOMUX_PAD(0x45C, 0x17C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_D4__GPIO5_24			IOMUX_PAD(0x45C, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D4__EIM_NANDF_D_0			IOMUX_PAD(0x45C, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D4__SSP_D4				IOMUX_PAD(0x45C, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D5__ESDHC3_DAT5			IOMUX_PAD(0x460, 0x180, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_D5__GPIO5_25			IOMUX_PAD(0x460, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D5__EIM_NANDF_D_1			IOMUX_PAD(0x460, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D5__SSP_D5				IOMUX_PAD(0x460, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D6__ESDHC3_DAT6			IOMUX_PAD(0x464, 0x184, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_D6__GPIO5_26			IOMUX_PAD(0x464, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D6__EIM_NANDF_D_2			IOMUX_PAD(0x464, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D6__SSP_D6				IOMUX_PAD(0x464, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D7__ESDHC3_DAT7			IOMUX_PAD(0x468, 0x188, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_D7__GPIO5_27			IOMUX_PAD(0x468, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D7__EIM_NANDF_D_3			IOMUX_PAD(0x468, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D7__SSP_D7				IOMUX_PAD(0x468, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_WP__ESDHC3_WP			IOMUX_PAD(0x46C, 0x18C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_WP__GPIO5_28			IOMUX_PAD(0x46C, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN		IOMUX_PAD(0x46C, 0x18C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_WP__SSP_CD				IOMUX_PAD(0x46C, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_WP__ESDHC4_LCTL			IOMUX_PAD(0x46C, 0x18C, 4, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3			IOMUX_PAD(0x46C, 0x18C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__ELCDIF_DAT_8			IOMUX_PAD(0x470, 0x190, 0, 0x71C, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__GPIO2_8			IOMUX_PAD(0x470, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__EIM_NANDF_CLE			IOMUX_PAD(0x470, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__ESDHC1_LCTL			IOMUX_PAD(0x470, 0x190, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D8__ESDHC4_CMD			IOMUX_PAD(0x470, 0x190, 4, 0x74C, 2, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D8__KPP_COL_4			IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__FEC_TX_CLK			IOMUX_PAD(0x470, 0x190, 6, 0x78C, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0		IOMUX_PAD(0x470, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__ELCDIF_DAT_9			IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__GPIO2_9			IOMUX_PAD(0x474, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__EIM_NANDF_ALE			IOMUX_PAD(0x474, 0x194, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__ESDHC2_LCTL			IOMUX_PAD(0x474, 0x194, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D9__ESDHC4_CLK			IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D9__KPP_ROW_4			IOMUX_PAD(0x474, 0x194, 5, 0x7A0, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__FEC_RX_ER			IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1		IOMUX_PAD(0x474, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__ELCDIF_DAT_10		IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__GPIO2_10			IOMUX_PAD(0x478, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0		IOMUX_PAD(0x478, 0x198, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__ESDHC3_LCTL			IOMUX_PAD(0x478, 0x198, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D10__ESDHC4_DAT0			IOMUX_PAD(0x478, 0x198, 4, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D10__KPP_COL_5			IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__FEC_RX_DV			IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2		IOMUX_PAD(0x478, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__ELCDIF_DAT_11		IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__GPIO2_11			IOMUX_PAD(0x47C, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1		IOMUX_PAD(0x47C, 0x19C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__ESDHC4_DAT1			IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D11__KPP_ROW_5			IOMUX_PAD(0x47C, 0x19C, 5, 0x7A4, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__FEC_RDATA_1			IOMUX_PAD(0x47C, 0x19C, 6, 0x77C, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3		IOMUX_PAD(0x47C, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__ELCDIF_DAT_12		IOMUX_PAD(0x480, 0x1A0, 0, 0x72C, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__GPIO2_12			IOMUX_PAD(0x480, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2		IOMUX_PAD(0x480, 0x1A0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__ESDHC1_CD			IOMUX_PAD(0x480, 0x1A0, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D12__ESDHC4_DAT2			IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D12__KPP_COL_6			IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__FEC_RDATA_0			IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4		IOMUX_PAD(0x480, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__ELCDIF_DAT_13		IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__GPIO2_13			IOMUX_PAD(0x484, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3		IOMUX_PAD(0x484, 0x1A4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__ESDHC3_CD			IOMUX_PAD(0x484, 0x1A4, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D13__ESDHC4_DAT3			IOMUX_PAD(0x484, 0x1A4, 4, 0x75C, 1, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D13__KPP_ROW_6			IOMUX_PAD(0x484, 0x1A4, 5, 0x7A8, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__FEC_TX_EN			IOMUX_PAD(0x484, 0x1A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5		IOMUX_PAD(0x484, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__ELCDIF_DAT_14		IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__GPIO2_14			IOMUX_PAD(0x488, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__EIM_NANDF_READY0		IOMUX_PAD(0x488, 0x1A8, 2, 0x7B4, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__ESDHC1_WP			IOMUX_PAD(0x488, 0x1A8, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D14__ESDHC4_WP			IOMUX_PAD(0x488, 0x1A8, 4, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D14__KPP_COL_7			IOMUX_PAD(0x488, 0x1A8, 5, 0x79C, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__FEC_TDATA_1			IOMUX_PAD(0x488, 0x1A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6		IOMUX_PAD(0x488, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__ELCDIF_DAT_15		IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__GPIO2_15			IOMUX_PAD(0x48C, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__EIM_NANDF_DQS		IOMUX_PAD(0x48C, 0x1AC, 2, 0x7B0, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__ESDHC3_RST			IOMUX_PAD(0x48C, 0x1AC, 3, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D15__ESDHC4_CD			IOMUX_PAD(0x48C, 0x1AC, 4, __NA_, 0, MX50_SDHC_PAD_CTRL)
-#define MX50_PAD_DISP_D15__KPP_ROW_7			IOMUX_PAD(0x48C, 0x1AC, 5, 0x7AC, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__FEC_TDATA_0			IOMUX_PAD(0x48C, 0x1AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7		IOMUX_PAD(0x48C, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__EPDC_SDDO_0			IOMUX_PAD(0x54C, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__GPIO3_0			IOMUX_PAD(0x54C, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0			IOMUX_PAD(0x54C, 0x1B0, 2, 0x7EC, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__ELCDIF_RS			IOMUX_PAD(0x54C, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK			IOMUX_PAD(0x54C, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0	IOMUX_PAD(0x54C, 0x1B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0		IOMUX_PAD(0x54C, 0x1B0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__EPDC_SDDO_1			IOMUX_PAD(0x550, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__GPIO3_1			IOMUX_PAD(0x550, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1			IOMUX_PAD(0x550, 0x1B4, 2, 0x7F0, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__ELCDIF_CS			IOMUX_PAD(0x550, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE			IOMUX_PAD(0x550, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1	IOMUX_PAD(0x550, 0x1B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1		IOMUX_PAD(0x550, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__EPDC_SDDO_2			IOMUX_PAD(0x554, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__GPIO3_2			IOMUX_PAD(0x554, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2			IOMUX_PAD(0x554, 0x1B8, 2, 0x7F4, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN			IOMUX_PAD(0x554, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC			IOMUX_PAD(0x554, 0x1B8, 4, 0x73C, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2	IOMUX_PAD(0x554, 0x1B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2		IOMUX_PAD(0x554, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__EPDC_SDDO_3			IOMUX_PAD(0x558, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__GPIO3_3			IOMUX_PAD(0x558, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3			IOMUX_PAD(0x558, 0x1BC, 2, 0x7F8, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__ELCDIF_RD_E			IOMUX_PAD(0x558, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC			IOMUX_PAD(0x558, 0x1BC, 4, 0x6F8, 3, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3	IOMUX_PAD(0x558, 0x1BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3		IOMUX_PAD(0x558, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__EPDC_SDDO_4			IOMUX_PAD(0x55C, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__GPIO3_4			IOMUX_PAD(0x55C, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4			IOMUX_PAD(0x55C, 0x1C0, 2, 0x7FC, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4	IOMUX_PAD(0x55C, 0x1C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4		IOMUX_PAD(0x55C, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__EPDC_SDDO_5			IOMUX_PAD(0x560, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__GPIO3_5			IOMUX_PAD(0x560, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5			IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5	IOMUX_PAD(0x560, 0x1C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5		IOMUX_PAD(0x560, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__EPDC_SDDO_6			IOMUX_PAD(0x564, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__GPIO3_6			IOMUX_PAD(0x564, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6			IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6	IOMUX_PAD(0x564, 0x1C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6		IOMUX_PAD(0x564, 0x1C8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__EPDC_SDDO_7			IOMUX_PAD(0x568, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__GPIO3_7			IOMUX_PAD(0x568, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7			IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7	IOMUX_PAD(0x568, 0x1CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7		IOMUX_PAD(0x568, 0x1CC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__EPDC_SDDO_8			IOMUX_PAD(0x56C, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__GPIO3_8			IOMUX_PAD(0x56C, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8			IOMUX_PAD(0x56C, 0x1D0, 2, 0x80C, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24			IOMUX_PAD(0x56C, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS	IOMUX_PAD(0x56C, 0x1D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0		IOMUX_PAD(0x56C, 0x1D0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__EPDC_SDDO_9			IOMUX_PAD(0x570, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__GPIO3_9			IOMUX_PAD(0x570, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9			IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25			IOMUX_PAD(0x570, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL	IOMUX_PAD(0x570, 0x1D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1		IOMUX_PAD(0x570, 0x1D4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__EPDC_SDDO_10			IOMUX_PAD(0x574, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__GPIO3_10			IOMUX_PAD(0x574, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10		IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26		IOMUX_PAD(0x574, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0	IOMUX_PAD(0x574, 0x1D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2		IOMUX_PAD(0x574, 0x1D8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__EPDC_SDDO_11			IOMUX_PAD(0x578, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__GPIO3_11			IOMUX_PAD(0x578, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11		IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27		IOMUX_PAD(0x578, 0x1DC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1	IOMUX_PAD(0x578, 0x1DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3		IOMUX_PAD(0x578, 0x1DC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__EPDC_SDDO_12			IOMUX_PAD(0x57C, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__GPIO3_12			IOMUX_PAD(0x57C, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12		IOMUX_PAD(0x57C, 0x1E0, 2, 0x81C, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28		IOMUX_PAD(0x57C, 0x1E0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2	IOMUX_PAD(0x57C, 0x1E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4		IOMUX_PAD(0x57C, 0x1E0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__EPDC_SDDO_13			IOMUX_PAD(0x580, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__GPIO3_13			IOMUX_PAD(0x580, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13		IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29		IOMUX_PAD(0x580, 0x1E4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3	IOMUX_PAD(0x580, 0x1E4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5		IOMUX_PAD(0x580, 0x1E4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__EPDC_SDDO_14			IOMUX_PAD(0x584, 0x1E8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__GPIO3_14			IOMUX_PAD(0x584, 0x1E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14		IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30		IOMUX_PAD(0x584, 0x1E8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD		IOMUX_PAD(0x584, 0x1E8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4	IOMUX_PAD(0x584, 0x1E8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6		IOMUX_PAD(0x584, 0x1E8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__EPDC_SDDO_15			IOMUX_PAD(0x588, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__GPIO3_15			IOMUX_PAD(0x588, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15		IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31		IOMUX_PAD(0x588, 0x1EC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC		IOMUX_PAD(0x588, 0x1EC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5	IOMUX_PAD(0x588, 0x1EC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7		IOMUX_PAD(0x588, 0x1EC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK			IOMUX_PAD(0x58C, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__GPIO3_16			IOMUX_PAD(0x58C, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16		IOMUX_PAD(0x58C, 0x1F0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16		IOMUX_PAD(0x58C, 0x1F0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS		IOMUX_PAD(0x58C, 0x1F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0	IOMUX_PAD(0x58C, 0x1F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK		IOMUX_PAD(0x58C, 0x1F0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__EPCD_GDSP			IOMUX_PAD(0x590, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__GPIO3_17			IOMUX_PAD(0x590, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17		IOMUX_PAD(0x590, 0x1F4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17		IOMUX_PAD(0x590, 0x1F4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD		IOMUX_PAD(0x590, 0x1F4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1	IOMUX_PAD(0x590, 0x1F4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID		IOMUX_PAD(0x590, 0x1F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__EPCD_GDOE			IOMUX_PAD(0x594, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__GPIO3_18			IOMUX_PAD(0x594, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18		IOMUX_PAD(0x594, 0x1F8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18		IOMUX_PAD(0x594, 0x1F8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC		IOMUX_PAD(0x594, 0x1F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2	IOMUX_PAD(0x594, 0x1F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION		IOMUX_PAD(0x594, 0x1F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__EPCD_GDRL			IOMUX_PAD(0x598, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__GPIO3_19			IOMUX_PAD(0x598, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19		IOMUX_PAD(0x598, 0x1F8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19		IOMUX_PAD(0x598, 0x1FC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS		IOMUX_PAD(0x598, 0x1FC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3	IOMUX_PAD(0x598, 0x1FC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG		IOMUX_PAD(0x598, 0x1FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK			IOMUX_PAD(0x59C, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__GPIO3_20			IOMUX_PAD(0x59C, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20		IOMUX_PAD(0x59C, 0x200, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20		IOMUX_PAD(0x59C, 0x200, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD		IOMUX_PAD(0x59C, 0x200, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0	IOMUX_PAD(0x59C, 0x200, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT	IOMUX_PAD(0x59C, 0x200, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ			IOMUX_PAD(0x5A0, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__GPIO3_21			IOMUX_PAD(0x5A0, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21		IOMUX_PAD(0x5A0, 0x204, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21		IOMUX_PAD(0x5A0, 0x204, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC		IOMUX_PAD(0x5A0, 0x204, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1	IOMUX_PAD(0x5A0, 0x204, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY		IOMUX_PAD(0x5A0, 0x204, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__EPCD_SDOED			IOMUX_PAD(0x5A4, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__GPIO3_22			IOMUX_PAD(0x5A4, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22		IOMUX_PAD(0x5A4, 0x208, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22		IOMUX_PAD(0x5A4, 0x208, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS		IOMUX_PAD(0x5A4, 0x208, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2	IOMUX_PAD(0x5A4, 0x208, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID		IOMUX_PAD(0x5A4, 0x208, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__EPCD_SDOE			IOMUX_PAD(0x5A8, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__GPIO3_23			IOMUX_PAD(0x5A8, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23		IOMUX_PAD(0x5A8, 0x20C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23		IOMUX_PAD(0x5A8, 0x20C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD		IOMUX_PAD(0x5A8, 0x20C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3	IOMUX_PAD(0x5A8, 0x20C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE		IOMUX_PAD(0x5A8, 0x20C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__EPCD_SDLE			IOMUX_PAD(0x5AC, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__GPIO3_24			IOMUX_PAD(0x5AC, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24		IOMUX_PAD(0x5AC, 0x210, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8		IOMUX_PAD(0x5AC, 0x210, 3, 0x71C, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC		IOMUX_PAD(0x5AC, 0x210, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4	IOMUX_PAD(0x5AC, 0x210, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR		IOMUX_PAD(0x5AC, 0x210, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN		IOMUX_PAD(0x5B0, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__GPIO3_25			IOMUX_PAD(0x5B0, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25		IOMUX_PAD(0x5B0, 0x214, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9		IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS		IOMUX_PAD(0x5B0, 0x214, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR	IOMUX_PAD(0x5B0, 0x214, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK		IOMUX_PAD(0x5B0, 0x214, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR			IOMUX_PAD(0x5B4, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__GPIO3_26			IOMUX_PAD(0x5B4, 0x218, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26		IOMUX_PAD(0x5B4, 0x218, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10		IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD		IOMUX_PAD(0x5B4, 0x218, 4, 0x6C8, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB		IOMUX_PAD(0x5B4, 0x218, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0	IOMUX_PAD(0x5B4, 0x218, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM		IOMUX_PAD(0x5B8, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__GPIO3_27			IOMUX_PAD(0x5B8, 0x21C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27		IOMUX_PAD(0x5B8, 0x21C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11		IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC		IOMUX_PAD(0x5B8, 0x21C, 4, 0x6D4, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN	IOMUX_PAD(0x5B8, 0x21C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1	IOMUX_PAD(0x5B8, 0x21C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT		IOMUX_PAD(0x5BC, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28			IOMUX_PAD(0x5BC, 0x220, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28		IOMUX_PAD(0x5BC, 0x220, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12		IOMUX_PAD(0x5BC, 0x220, 3, 0x72C, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS		IOMUX_PAD(0x5BC, 0x220, 4, 0x6D8, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE		IOMUX_PAD(0x5BC, 0x220, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID	IOMUX_PAD(0x5BC, 0x220, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0		IOMUX_PAD(0x5C0, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29		IOMUX_PAD(0x5C0, 0x224, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29		IOMUX_PAD(0x5C0, 0x224, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13		IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD		IOMUX_PAD(0x5C0, 0x224, 4, 0x6C4, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE	IOMUX_PAD(0x5C0, 0x224, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID		IOMUX_PAD(0x5C0, 0x224, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1		IOMUX_PAD(0x5C4, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30		IOMUX_PAD(0x5C4, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30		IOMUX_PAD(0x5C4, 0x228, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14		IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC		IOMUX_PAD(0x5C4, 0x228, 4, 0x6CC, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD	IOMUX_PAD(0x5C4, 0x228, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST		IOMUX_PAD(0x5C4, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2		IOMUX_PAD(0x5C8, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31		IOMUX_PAD(0x5C8, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31		IOMUX_PAD(0x5C8, 0x22C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15		IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS	IOMUX_PAD(0x5C8, 0x22C, 4, 0x6D0, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0	IOMUX_PAD(0x5C8, 0x22C, 6, 0x7B8, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST		IOMUX_PAD(0x5C8, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3		IOMUX_PAD(0x5CC, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20		IOMUX_PAD(0x5CC, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2		IOMUX_PAD(0x5CC, 0x230, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1	IOMUX_PAD(0x5CC, 0x230, 6, 0x7BC, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK		IOMUX_PAD(0x5CC, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0		IOMUX_PAD(0x5D0, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM0__GPIO4_21			IOMUX_PAD(0x5D0, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3		IOMUX_PAD(0x5D0, 0x234, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK		IOMUX_PAD(0x5D0, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1		IOMUX_PAD(0x5D4, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM1__GPIO4_22			IOMUX_PAD(0x5D4, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3		IOMUX_PAD(0x5D4, 0x238, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0			IOMUX_PAD(0x5D8, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR0__GPIO4_23			IOMUX_PAD(0x5D8, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7		IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1			IOMUX_PAD(0x5DC, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR1__GPIO4_24			IOMUX_PAD(0x5DC, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6		IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0		IOMUX_PAD(0x5E0, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE0__GPIO4_25			IOMUX_PAD(0x5E0, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5		IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1		IOMUX_PAD(0x5E4, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE1__GPIO4_26			IOMUX_PAD(0x5E4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4		IOMUX_PAD(0x5E4, 0x248, 3, 0x70C, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2		IOMUX_PAD(0x5E8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE2__GPIO4_27			IOMUX_PAD(0x5E8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3		IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3		IOMUX_PAD(0x5EC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE3__GPIO4_28			IOMUX_PAD(0x5EC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2		IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4		IOMUX_PAD(0x5F0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE4__GPIO4_29			IOMUX_PAD(0x5F0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1		IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5		IOMUX_PAD(0x5F4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE5__GPIO4_30			IOMUX_PAD(0x5F4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0		IOMUX_PAD(0x5F4, 0x258, 3, 0x6FC, 1, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0			IOMUX_PAD(0x5F8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__GPIO1_0			IOMUX_PAD(0x5F8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__KPP_COL_4			IOMUX_PAD(0x5F8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__TPIU_TRACE_0			IOMUX_PAD(0x5F8, 0x25C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0			IOMUX_PAD(0x5F8, 0x25C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1			IOMUX_PAD(0x5FC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__GPIO1_1			IOMUX_PAD(0x5FC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__KPP_ROW_4			IOMUX_PAD(0x5FC, 0x260, 3, 0x7A0, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__TPIU_TRACE_1			IOMUX_PAD(0x5FC, 0x260, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1			IOMUX_PAD(0x5FC, 0x260, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2			IOMUX_PAD(0x600, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA2__GPIO1_2			IOMUX_PAD(0x600, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA2__KPP_COL_5			IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA2__TPIU_TRACE_2			IOMUX_PAD(0x600, 0x264, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2			IOMUX_PAD(0x600, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3			IOMUX_PAD(0x604, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__GPIO1_3			IOMUX_PAD(0x604, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__KPP_ROW_5			IOMUX_PAD(0x604, 0x268, 3, 0x7A4, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__TPIU_TRACE_3			IOMUX_PAD(0x604, 0x268, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3			IOMUX_PAD(0x604, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4			IOMUX_PAD(0x608, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA4__GPIO1_4			IOMUX_PAD(0x608, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA4__KPP_COL_6			IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA4__TPIU_TRACE_4			IOMUX_PAD(0x608, 0x26C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4			IOMUX_PAD(0x608, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5			IOMUX_PAD(0x60C, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__GPIO1_5			IOMUX_PAD(0x60C, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__KPP_ROW_6			IOMUX_PAD(0x60C, 0x270, 3, 0x7A8, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__TPIU_TRACE_5			IOMUX_PAD(0x60C, 0x270, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5			IOMUX_PAD(0x60C, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6			IOMUX_PAD(0x610, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA6__GPIO1_6			IOMUX_PAD(0x610, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA6__KPP_COL_7			IOMUX_PAD(0x610, 0x274, 3, 0x79C, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA6__TPIU_TRACE_6			IOMUX_PAD(0x610, 0x274, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6			IOMUX_PAD(0x610, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7			IOMUX_PAD(0x614, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__GPIO1_7			IOMUX_PAD(0x614, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__KPP_ROW_7			IOMUX_PAD(0x614, 0x278, 3, 0x7AC, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__TPIU_TRACE_7			IOMUX_PAD(0x614, 0x278, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7			IOMUX_PAD(0x614, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8			IOMUX_PAD(0x618, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA8__GPIO1_8			IOMUX_PAD(0x618, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE			IOMUX_PAD(0x618, 0x27C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA8__TPIU_TRACE_8			IOMUX_PAD(0x618, 0x27C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0			IOMUX_PAD(0x618, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9			IOMUX_PAD(0x61C, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA9__GPIO1_9			IOMUX_PAD(0x61C, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE			IOMUX_PAD(0x61C, 0x280, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA9__TPIU_TRACE_9			IOMUX_PAD(0x61C, 0x280, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1			IOMUX_PAD(0x61C, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10		IOMUX_PAD(0x620, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA10__GPIO1_10			IOMUX_PAD(0x620, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0		IOMUX_PAD(0x620, 0x284, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA10__TPIU_TRACE_10		IOMUX_PAD(0x620, 0x284, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2		IOMUX_PAD(0x620, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11		IOMUX_PAD(0x624, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA11__GPIO1_11			IOMUX_PAD(0x624, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1		IOMUX_PAD(0x624, 0x288, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA11__TPIU_TRACE_11		IOMUX_PAD(0x624, 0x288, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3		IOMUX_PAD(0x624, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12		IOMUX_PAD(0x628, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA12__GPIO1_12			IOMUX_PAD(0x628, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2		IOMUX_PAD(0x628, 0x28C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA12__EPDC_SDCE_6			IOMUX_PAD(0x628, 0x28C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA12__TPIU_TRACE_12		IOMUX_PAD(0x628, 0x28C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4		IOMUX_PAD(0x628, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13		IOMUX_PAD(0x62C, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA13__GPIO1_13			IOMUX_PAD(0x62C, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3		IOMUX_PAD(0x62C, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA13__EPDC_SDCE_7			IOMUX_PAD(0x62C, 0x290, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA13__TPIU_TRACE_13		IOMUX_PAD(0x62C, 0x290, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5		IOMUX_PAD(0x62C, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14		IOMUX_PAD(0x630, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__GPIO1_14			IOMUX_PAD(0x630, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0		IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__EPDC_SDCE_8			IOMUX_PAD(0x630, 0x294, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__TPIU_TRACE_14		IOMUX_PAD(0x630, 0x294, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6		IOMUX_PAD(0x630, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15		IOMUX_PAD(0x634, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA15__GPIO1_15			IOMUX_PAD(0x634, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS		IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA15__EPDC_SDCE_9			IOMUX_PAD(0x634, 0x298, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA15__TPIU_TRACE_15		IOMUX_PAD(0x634, 0x298, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7		IOMUX_PAD(0x634, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2			IOMUX_PAD(0x638, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__GPIO1_16			IOMUX_PAD(0x638, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27			IOMUX_PAD(0x638, 0x29C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__TPIU_TRCLK			IOMUX_PAD(0x638, 0x29C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0			IOMUX_PAD(0x638, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1			IOMUX_PAD(0x63C, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS1__GPIO1_17			IOMUX_PAD(0x63C, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS1__TPIU_TRCTL			IOMUX_PAD(0x63C, 0x2A0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1			IOMUX_PAD(0x63C, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0			IOMUX_PAD(0x640, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS0__GPIO1_18			IOMUX_PAD(0x640, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2			IOMUX_PAD(0x640, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0			IOMUX_PAD(0x644, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB0__GPIO1_19			IOMUX_PAD(0x644, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3			IOMUX_PAD(0x644, 0x2A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1			IOMUX_PAD(0x648, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB1__GPIO1_20			IOMUX_PAD(0x648, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4			IOMUX_PAD(0x648, 0x2AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT		IOMUX_PAD(0x64C, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_WAIT__GPIO1_21			IOMUX_PAD(0x64C, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B		IOMUX_PAD(0x64C, 0x2B0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5		IOMUX_PAD(0x64C, 0x2B0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK		IOMUX_PAD(0x650, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_BCLK__GPIO1_22			IOMUX_PAD(0x650, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6		IOMUX_PAD(0x650, 0x2B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY			IOMUX_PAD(0x654, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RDY__GPIO1_23			IOMUX_PAD(0x654, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7			IOMUX_PAD(0x654, 0x2B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_OE__EIM_WEIM_OE			IOMUX_PAD(0x658, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_OE__GPIO1_24			IOMUX_PAD(0x658, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_OE__INT_BOOT			IOMUX_PAD(0x658, 0x2BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RW__EIM_WEIM_RW			IOMUX_PAD(0x65C, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RW__GPIO1_25			IOMUX_PAD(0x65C, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RW__SYSTEM_RST			IOMUX_PAD(0x65C, 0x2C0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA			IOMUX_PAD(0x660, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_LBA__GPIO1_26			IOMUX_PAD(0x660, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_LBA__TESTER_ACK			IOMUX_PAD(0x660, 0x2C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE			IOMUX_PAD(0x664, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CRE__GPIO1_27			IOMUX_PAD(0x664, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
-
-#endif /* __MACH_IOMUX_MX50_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx51.h b/arch/arm/mach-imx/include/mach/iomux-mx51.h
deleted file mode 100644
index 2623e7a2e1..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx51.h
+++ /dev/null
@@ -1,827 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX51_H__
-#define __MACH_IOMUX_MX51_H__
-
-#include <mach/iomux-v3.h>
-#define __NA_	0x000
-
-
-/* Pad control groupings */
-#define MX51_UART_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
-				PAD_CTL_HYS | PAD_CTL_SRE_FAST)
-#define MX51_I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
-				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-				PAD_CTL_HYS)
-#define MX51_ESDHC_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
-				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-				PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-				PAD_CTL_HYS | PAD_CTL_PUE)
-#define MX51_ECSPI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_HYS | \
-				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
-				PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
-				PAD_CTL_SRE_FAST | PAD_CTL_DVS)
-#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
-
-#define MX51_PAD_CTRL_2		(PAD_CTL_PKE | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_3		(PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_CTRL_4		(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_5		(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
-
-/*
- * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
- * See also iomux-v3.h
- */
-
-/* Raw pin modes without pad control */
-/*							  PAD    MUX ALT INPSE PATH PADCTRL */
-
-/* The same pins as above but with the default pad control values applied */
-#define MX51_PAD_EIM_D16__AUD4_RXFS		IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__AUD5_TXD		IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__EIM_D16		IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__GPIO2_0		IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__I2C1_SDA		IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D16__UART2_CTS		IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D16__USBH2_DATA0		IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__AUD5_RXD		IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__EIM_D17		IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__GPIO2_1		IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART2_RXD		IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART3_CTS		IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__USBH2_DATA1		IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__AUD5_TXC		IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__EIM_D18		IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__GPIO2_2		IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART2_TXD		IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART3_RTS		IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__USBH2_DATA2		IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD4_RXC		IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD5_TXFS		IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__EIM_D19		IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__GPIO2_3		IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__I2C1_SCL		IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D19__UART2_RTS		IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D19__USBH2_DATA3		IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__AUD4_TXD		IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__EIM_D20		IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__GPIO2_4		IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB	IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__USBH2_DATA4		IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__AUD4_RXD		IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__EIM_D21		IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO2_5		IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB	IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__USBH2_DATA5		IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__AUD4_TXC		IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__EIM_D22		IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__GPIO2_6		IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__USBH2_DATA6		IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__AUD4_TXFS		IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__EIM_D23		IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__GPIO2_7		IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__SPDIF_OUT1		IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__USBH2_DATA7		IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__AUD6_RXFS		IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__EIM_D24		IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__GPIO2_8		IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__I2C2_SDA		IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D24__USBOTG_DATA0		IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__EIM_D25		IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__KEY_COL6		IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART2_CTS		IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD		IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__USBOTG_DATA1		IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__GPT_CMPOUT1		IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__EIM_D26		IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__KEY_COL7		IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART2_RTS		IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD		IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__USBOTG_DATA2		IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__GPT_CMPOUT2		IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__AUD6_RXC		IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__EIM_D27		IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__GPIO2_9		IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__I2C2_SCL		IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D27__USBOTG_DATA3		IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__AUD6_TXD		IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__EIM_D28		IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__KEY_ROW4		IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__USBOTG_DATA4		IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__AUD6_RXD		IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29		IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__KEY_ROW5		IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__USBOTG_DATA5		IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__AUD6_TXC		IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30		IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__KEY_ROW6		IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__USBOTG_DATA6		IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__AUD6_TXFS		IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31		IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__KEY_ROW7		IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__USBOTG_DATA7		IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__EIM_A16		IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__GPIO2_10		IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0		IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__EIM_A17		IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__GPIO2_11		IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1		IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__BOOT_LPB0		IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__EIM_A18		IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__GPIO2_12		IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__BOOT_LPB1		IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__EIM_A19		IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__GPIO2_13		IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__BOOT_UART_SRC0	IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__EIM_A20		IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__GPIO2_14		IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__BOOT_UART_SRC1	IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__EIM_A21		IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__GPIO2_15		IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__EIM_A22		IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__GPIO2_16		IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__BOOT_HPN_EN		IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__EIM_A23		IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__GPIO2_17		IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__EIM_A24		IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__GPIO2_18		IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__USBH2_CLK		IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__DISP1_PIN4		IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__EIM_A25		IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__GPIO2_19		IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__USBH2_DIR		IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__CSI1_DATA_EN		IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__DISP2_EXT_CLK		IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__EIM_A26		IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__GPIO2_20		IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__USBH2_STP		IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__CSI2_DATA_EN		IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__DISP1_PIN1		IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__EIM_A27		IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__GPIO2_21		IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__USBH2_NXT		IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0		IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1		IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__AUD5_RXFS		IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__CSI1_D2		IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__EIM_EB2		IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__FEC_MDIO		(IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \
-		MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-		PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
-#define MX51_PAD_EIM_EB2__GPIO2_22		IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__GPT_CMPOUT1		IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__AUD5_RXC		IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__CSI1_D3		IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__EIM_EB3		IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__FEC_RDATA1		IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPIO2_23		IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPT_CMPOUT2		IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__EIM_OE			IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__GPIO2_24		IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__EIM_CS0		IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__GPIO2_25		IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__EIM_CS1		IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__GPIO2_26		IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__AUD5_TXD		IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__CSI1_D4		IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__EIM_CS2		IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__FEC_RDATA2		IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__GPIO2_27		IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__USBOTG_STP		IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__AUD5_RXD		IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__CSI1_D5		IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__EIM_CS3		IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__FEC_RDATA3		IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__GPIO2_28		IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__USBOTG_NXT		IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__AUD5_TXC		IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__CSI1_D6		IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__EIM_CS4		IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__FEC_RX_ER		IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS4__GPIO2_29		IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__USBOTG_CLK		IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__AUD5_TXFS		IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__CSI1_D7		IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK		IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__EIM_CS5		IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__FEC_CRS		IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS5__GPIO2_30		IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__USBOTG_DIR		IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__EIM_DTACK		IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__GPIO2_31		IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__EIM_LBA		IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__GPIO3_1		IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__EIM_CRE		IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__GPIO3_2		IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1		IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__CCM_CLKO		IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__GPIO3_3		IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__NANDF_WE_B		IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__PATA_DIOW		IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__SD3_DATA0		IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__GPIO3_4		IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__NANDF_RE_B		IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__PATA_DIOR		IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__SD3_DATA1		IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__GPIO3_5		IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__NANDF_ALE		IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN	IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__GPIO3_6		IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__NANDF_CLE		IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__PATA_RESET_B	IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__GPIO3_7		IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__NANDF_WP_B		IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__PATA_DMACK		IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__SD3_DATA2		IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__ECSPI2_SS1		IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__GPIO3_8		IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__NANDF_RB0		IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__PATA_DMARQ		IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__SD3_DATA3		IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__CSPI_MOSI		IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__ECSPI2_RDY		IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPIO3_9		IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__NANDF_RB1		IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__PATA_IORDY		IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2		IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__SD4_CMD		IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__DISP2_WAIT		IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK		IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__FEC_COL		IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB2__GPIO3_10		IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__NANDF_RB2		IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3		IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_H3_DP		IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_NXT		IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__DISP1_WAIT		IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__ECSPI2_MISO		IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__FEC_RX_CLK		IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB3__GPIO3_11		IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__NANDF_RB3		IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_CLK		IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_H3_DM		IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__GPIO_NAND		IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__PATA_INTRQ		IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__GPIO3_16		IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__NANDF_CS0		IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__GPIO3_17		IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__NANDF_CS1		IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__CSPI_SCLK		IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__FEC_TX_ER		IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS2__GPIO3_18		IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__NANDF_CS2		IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__PATA_CS_0		IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__SD4_CLK		IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_CS2__USBH3_H1_DP		IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__FEC_MDC		IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS3__GPIO3_19		IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__NANDF_CS3		IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__PATA_CS_1		IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__SD4_DAT0		IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__USBH3_H1_DM		IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__FEC_TDATA1		IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS4__GPIO3_20		IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__NANDF_CS4		IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__PATA_DA_0		IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__SD4_DAT1		IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__USBH3_STP		IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__FEC_TDATA2		IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS5__GPIO3_21		IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__NANDF_CS5		IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__PATA_DA_1		IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__SD4_DAT2		IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__USBH3_DIR		IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__CSPI_SS3		IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__FEC_TDATA3		IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS6__GPIO3_22		IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__NANDF_CS6		IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__PATA_DA_2		IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__SD4_DAT3		IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__FEC_TX_EN		IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS7__GPIO3_23		IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__NANDF_CS7		IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__SD3_CLK		IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0	IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_RDY_INT__GPIO3_24	IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT	IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD		IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__ECSPI2_MOSI		IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__GPIO3_25		IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__NANDF_D15		IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__PATA_DATA15		IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__SD3_DAT7		IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__ECSPI2_SS3		IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__GPIO3_26		IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__NANDF_D14		IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__PATA_DATA14		IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__SD3_DAT6		IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__ECSPI2_SS2		IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__GPIO3_27		IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__NANDF_D13		IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__PATA_DATA13		IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__SD3_DAT5		IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__ECSPI2_SS1		IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__GPIO3_28		IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__NANDF_D12		IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__PATA_DATA12		IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__SD3_DAT4		IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__FEC_RX_DV		IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__GPIO3_29		IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__NANDF_D11		IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__PATA_DATA11		IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__SD3_DATA3		IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__GPIO3_30		IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__NANDF_D10		IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__PATA_DATA10		IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__SD3_DATA2		IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__FEC_RDATA0		IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_D9__GPIO3_31		IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__NANDF_D9		IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__PATA_DATA9		IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__SD3_DATA1		IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__FEC_TDATA0		IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_D8__GPIO4_0		IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__NANDF_D8		IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__PATA_DATA8		IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__SD3_DATA0		IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__GPIO4_1		IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__NANDF_D7		IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__PATA_DATA7		IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__USBH3_DATA0		IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__GPIO4_2		IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__NANDF_D6		IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__PATA_DATA6		IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__SD4_LCTL		IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__USBH3_DATA1		IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__GPIO4_3		IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__NANDF_D5		IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__PATA_DATA5		IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__SD4_WP		IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__USBH3_DATA2		IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__GPIO4_4		IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__NANDF_D4		IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__PATA_DATA4		IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__SD4_CD		IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__USBH3_DATA3		IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__GPIO4_5		IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__NANDF_D3		IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__PATA_DATA3		IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__SD4_DAT4		IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__USBH3_DATA4		IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__GPIO4_6		IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__NANDF_D2		IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__PATA_DATA2		IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__SD4_DAT5		IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__USBH3_DATA5		IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__GPIO4_7		IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__NANDF_D1		IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__PATA_DATA1		IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__SD4_DAT6		IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__USBH3_DATA6		IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__GPIO4_8		IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__NANDF_D0		IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__PATA_DATA0		IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__SD4_DAT7		IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__USBH3_DATA7		IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__CSI1_D8		IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__GPIO3_12		IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__CSI1_D9		IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__GPIO3_13		IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10		IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11		IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12		IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13		IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14		IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15		IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16		IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17		IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18		IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19		IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC		IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__GPIO3_14		IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC		IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__GPIO3_15		IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK		IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__CSI2_D12		IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__GPIO4_9		IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__CSI2_D13		IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__GPIO4_10		IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D14__CSI2_D14		IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D15__CSI2_D15		IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D16__CSI2_D16		IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D17__CSI2_D17		IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__CSI2_D18		IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__GPIO4_11		IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__CSI2_D19		IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__GPIO4_12		IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC		IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__GPIO4_13		IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC		IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__GPIO4_14		IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK	IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__GPIO4_15		IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__GPIO4_16		IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__I2C1_CLK		IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__GPIO4_17		IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__I2C1_DAT		IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD		IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__GPIO4_18		IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD		IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__GPIO4_19		IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__UART3_RXD		IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__AUD3_TXC		IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__GPIO4_20		IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS		IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__GPIO4_21		IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__UART3_TXD		IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__GPIO4_22		IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__I2C1_SDA		IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__AUD4_RXD		IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO	IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__GPIO4_23		IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__AUD4_TXC		IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0		IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__GPIO4_24		IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__AUD4_TXD		IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1		IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__GPIO4_25		IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__AUD4_TXFS		IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY		IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__GPIO4_26		IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__GPIO4_27		IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__I2C1_SCL		IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__GPIO4_28		IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__UART1_RXD		IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__GPIO4_29		IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__PWM2_PWMO		IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__UART1_TXD		IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__GPIO4_30		IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__UART1_RTS		IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__GPIO4_31		IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS		IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__FIRI_TXD		IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__GPIO1_20		IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__UART2_RXD		IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__FIRI_RXD		IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__GPIO1_21		IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD		IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__CSI1_D0		IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__GPIO1_22		IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART1_DTR		IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART3_RXD		IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__CSI1_D1		IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__GPIO1_23		IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART1_DSR		IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART3_TXD		IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__GPIO1_24		IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__OWIRE_LINE		IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__SPDIF_OUT		IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0		IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1		IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2		IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3		IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0		IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__PLL1_BYP		IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1		IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__PLL2_BYP		IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2		IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__PLL3_BYP		IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3		IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__I2C2_SCL		IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4		IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__SPDIF_OUT1		IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART1_RI		IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART3_RTS		IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__I2C2_SDA		IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5		IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART1_DCD		IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART3_CTS		IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__CSPI_SCLK		IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__GPIO1_25		IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__I2C2_SCL		IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK		IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__CSPI_MOSI		IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__GPIO1_26		IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__I2C2_SDA		IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR		IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__CSPI_RDY		IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO1_27		IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__UART3_RXD		IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP		IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__CSPI_MISO		IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__GPIO1_28		IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__UART3_TXD		IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT		IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__GPIO1_11		IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__UART2_CTS		IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__GPIO1_12		IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__UART2_RXD		IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__GPIO1_13		IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__UART2_TXD		IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__GPIO1_14		IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__UART2_RTS		IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__CSPI_SS0		IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__GPIO1_15		IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__CSPI_SS1		IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__GPIO1_16		IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__CSPI_SS3		IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__GPIO1_17		IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3	IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3	IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__GPIO1_18		IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__DI1_PIN11		IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__ECSPI1_SS2		IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__GPIO3_0		IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__DI1_PIN12		IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__GPIO3_1		IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__DI1_PIN13		IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__GPIO3_2		IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__DI1_D0_CS		IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__GPIO3_3		IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DI1_D1_CS		IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN14		IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN5		IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__GPIO3_4		IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1	IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN	IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5	IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6	IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO	IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6	IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17	IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7	IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK	IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7	IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK	IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16	IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8	IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS	IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS	IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__GPIO3_8		IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0		IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1		IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2		IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3		IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4		IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5		IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC	IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6		IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG	IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7		IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__BOOT_SRC0		IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8		IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__BOOT_SRC1		IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9		IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE	IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2	IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL	IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0	IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1	IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH	IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0	IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1	IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0	IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN11	IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN5	IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1	IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN12	IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN6	IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0	IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN13	IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN7	IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1	IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN14	IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN8	IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0	IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS	IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_DAT16	IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1	IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS	IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_DAT17	IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS	IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3		IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK	IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2		IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN15__DI1_PIN15		IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP1_SER_CLK		IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP2_WAIT		IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__CSI1_DATA_EN		IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DISP1_SER_DIO		IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__FEC_TX_ER		IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN		IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4		IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__FEC_CRS		IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2		IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__FEC_MDC		IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3		IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__FEC_MDIO		IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1	IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI2_PIN15		IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP1_SER_DIN		IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP2_PIN1		IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__FEC_RDATA2		IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0		IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__FEC_RDATA3		IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__KEY_COL6		IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__UART3_RXD		IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__USBH3_CLK		IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1		IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__FEC_RX_ER		IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__KEY_COL7		IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__UART3_TXD		IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__USBH3_DIR		IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2		IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3		IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4		IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5		IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__DISP2_DAT6		IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__FEC_TDATA1		IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT6__GPIO1_19		IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__KEY_ROW4		IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__USBH3_STP		IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__DISP2_DAT7		IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__FEC_TDATA2		IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT7__GPIO1_29		IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__KEY_ROW5		IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__USBH3_NXT		IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__DISP2_DAT8		IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__FEC_TDATA3		IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT8__GPIO1_30		IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__KEY_ROW6		IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__USBH3_DATA0	IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__AUD6_RXC		IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__DISP2_DAT9		IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__FEC_TX_EN		IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT9__GPIO1_31		IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__USBH3_DATA1	IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS	IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__FEC_COL		IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__KEY_ROW7		IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__USBH3_DATA2	IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__AUD6_TXD		IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK	IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__GPIO1_10		IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__USBH3_DATA3	IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__AUD6_RXD		IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__FEC_RX_DV		IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__USBH3_DATA4	IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__AUD6_TXC		IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK	IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT13__USBH3_DATA5	IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__AUD6_TXFS		IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__FEC_RDATA0	IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT14__USBH3_DATA6	IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__AUD6_RXFS		IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS	IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__FEC_TDATA0	IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT15__USBH3_DATA7	IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__AUD5_RXFS		IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__CSPI_MOSI		IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD		IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__AUD5_RXC		IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__CSPI_SCLK		IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK		IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD1_DATA0__AUD5_TXD		IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__CSPI_MISO		IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0		IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA0__EIM_DA0		IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1		IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2		IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3		IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__AUD5_RXD		IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1		IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4		IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5		IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6		IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7		IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__AUD5_TXC		IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2		IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10		IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11		IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA8__EIM_DA8		IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9		IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__AUD5_TXFS		IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__CSPI_SS1		IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3		IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__CSPI_SS2		IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__GPIO1_0		IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__SD1_CD		IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__CSPI_MISO		IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__GPIO1_1		IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__SD1_WP		IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12		IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13		IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14		IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15		IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__CSPI_MOSI		IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__I2C1_SCL		IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD		IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__CSPI_SCLK		IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__I2C1_SDA		IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK		IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD2_DATA0__CSPI_MISO		IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD1_DAT4		IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0		IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD1_DAT5		IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1		IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__USBH3_H2_DP		IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD1_DAT6		IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2		IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__USBH3_H2_DM		IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__CSPI_SS2		IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD1_DAT7		IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3		IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__CCM_OUT_2		IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__GPIO1_2		IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__I2C2_SCL		IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PLL1_BYP		IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PWM1_PWMO		IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPIO1_3		IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__I2C2_SDA		IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__CCM_CLKO2		IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPT_CLKIN		IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PLL2_BYP		IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PWM2_PWMO		IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B	IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK		IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__EIM_RDY		IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPIO1_4		IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B		IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPT_CAPIN1		IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__CSI2_MCLK		IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__DISP2_PIN16		IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__GPIO1_5		IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B		IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__CCM_CLKO		IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__DISP2_PIN17		IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPIO1_6		IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__REF_EN_B		IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPT_CAPIN2		IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__CCM_OUT_0		IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__GPIO1_7		IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SD2_WP		IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SPDIF_OUT1		IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__CSI2_DATA_EN		IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__GPIO1_8		IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__SD2_CD		IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__USBH3_PWR		IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__CCM_CLKO2		IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__CCM_OUT_1		IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_D1_CS		IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_SER_CS		IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__GPIO1_9		IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__SD2_LCTL		IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__USBH3_OC		IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__CCM_CLKO		IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
-
-#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx53.h b/arch/arm/mach-imx/include/mach/iomux-mx53.h
deleted file mode 100644
index 010fb6e5cc..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx53.h
+++ /dev/null
@@ -1,1204 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2010-2011 Freescale Semiconductor, Inc. */
-
-#ifndef __MACH_IOMUX_MX53_H__
-#define __MACH_IOMUX_MX53_H__
-
-#include <mach/iomux-v3.h>
-
-/* These 2 defines are for pins that may not have a mux register, but could
- * have a pad setting register, and vice-versa. */
-#define __NA_	0x00
-
-#define MX53_UART_PAD_CTRL		(PAD_CTL_PKE | PAD_CTL_PUE |	\
-		PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define MX53_SDHC_PAD_CTRL 	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-				PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
-				PAD_CTL_SRE_FAST)
-
-
-#define MX53_PAD_GPIO_19__KPP_COL_5			IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__GPIO4_5			IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__CCM_CLKO			IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SPDIF_OUT1			IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2		IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__ECSPI1_RDY			IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__FEC_TDATA_3			IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SRC_INT_BOOT			IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__KPP_COL_0			IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__GPIO4_6			IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC		IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__UART4_TXD_MUX		IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__ECSPI1_SCLK			IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__FEC_RDATA_3			IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST		IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__KPP_ROW_0			IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__GPIO4_7			IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD		IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX		IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI			IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__FEC_TX_ER			IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__KPP_COL_1			IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__GPIO4_8			IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS		IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__UART5_TXD_MUX		IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__ECSPI1_MISO			IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__FEC_RX_CLK			IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY		IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__KPP_ROW_1			IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__GPIO4_9			IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD		IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX		IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__ECSPI1_SS0			IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__FEC_COL			IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID		IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__KPP_COL_2			IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__GPIO4_10			IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__CAN1_TXCAN			IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_MDIO			IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__ECSPI1_SS1			IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_RDATA_2			IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE		IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__KPP_ROW_2			IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__GPIO4_11			IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__CAN1_RXCAN			IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_MDC			IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__ECSPI1_SS2			IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_TDATA_2			IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR		IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__KPP_COL_3			IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__GPIO4_12			IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBOH3_H2_DP			IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__SPDIF_IN1			IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__I2C2_SCL			IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__ECSPI1_SS3			IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__FEC_CRS			IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK		IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__KPP_ROW_3			IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__GPIO4_13			IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM			IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK		IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__I2C2_SDA			IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT		IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP			IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0		IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__KPP_COL_4			IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__GPIO4_14			IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__CAN2_TXCAN			IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__IPU_SISG_4			IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__UART5_RTS			IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC		IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1		IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__KPP_ROW_4			IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__GPIO4_15			IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__CAN2_RXCAN			IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__IPU_SISG_5			IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__UART5_CTS			IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR		IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID		IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK		IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__GPIO4_16			IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR		IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0	IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0		IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID		IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15		IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__GPIO4_17			IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC		IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1	IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1		IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID		IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2			IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__GPIO4_18			IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD		IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2	IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2		IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION		IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3			IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__GPIO4_19			IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS		IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3	IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3		IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG		IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4			IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__GPIO4_20			IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD		IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__ESDHC1_WP			IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD		IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4		IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT	IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0		IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__GPIO4_21			IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__CSPI_SCLK			IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0	IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN	IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5		IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY		IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1		IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__GPIO4_22			IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__CSPI_MOSI			IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1	IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL	\
-							IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6		IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID		IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2		IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__GPIO4_23			IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__CSPI_MISO			IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2	IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE		IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7		IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE		IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3		IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__GPIO4_24			IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__CSPI_SS0			IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3	IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR	IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8		IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR		IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4		IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__GPIO4_25			IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__CSPI_SS1			IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4	IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB		IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9		IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK		IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5		IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__GPIO4_26			IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__CSPI_SS2			IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5	IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS	IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10		IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0	IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6		IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__GPIO4_27			IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__CSPI_SS3			IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6	IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE	IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11		IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1	IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7		IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__GPIO4_28			IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__CSPI_RDY			IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7	IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12		IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID		IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8		IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__GPIO4_29			IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__PWM1_PWMO			IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B		IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13		IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID		IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9		IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__GPIO4_30			IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__PWM2_PWMO			IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B		IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2	IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14		IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0		IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10		IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__GPIO4_31			IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP		IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3	\
-							IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15		IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1		IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11		IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__GPIO5_5			IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT		IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4	\
-							IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16		IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2		IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12		IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__GPIO5_6			IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK		IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5	\
-							IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17		IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3		IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13		IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__GPIO5_7			IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS		IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0	\
-							IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18		IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4		IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14		IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__GPIO5_8			IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC		IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1	\
-							IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19		IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5		IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15		IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__GPIO5_9			IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1		IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1		IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2	\
-							IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20		IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6		IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16		IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__GPIO5_10			IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI		IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC		IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0		IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3	\
-							IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21		IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7		IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17		IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__GPIO5_11			IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO		IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD		IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1		IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4	\
-							IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22		IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18		IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__GPIO5_12			IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0		IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS		IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS		IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5	\
-							IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23		IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2		IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19		IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__GPIO5_13			IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK		IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD		IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC		IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6	\
-							IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24		IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3		IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20		IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__GPIO5_14			IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK		IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC		IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7	\
-							IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25		IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI		IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21		IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__GPIO5_15			IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI		IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD		IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0	IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26		IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO		IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22		IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__GPIO5_16			IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO		IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS		IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1	IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27		IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK		IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23		IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__GPIO5_17			IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0		IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD		IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2	IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28		IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS		IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK		IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__GPIO5_18			IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0		IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29		IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC		IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__GPIO5_19			IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK		IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1		IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30		IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL			IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN		IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__GPIO5_20			IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2		IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31		IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK		IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC		IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__GPIO5_21			IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3		IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32		IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0		IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4		IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__GPIO5_22			IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__KPP_COL_5			IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK			IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP		IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC		IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33		IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1		IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5		IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__GPIO5_23			IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__KPP_ROW_5			IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI			IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT		IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD		IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34		IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2		IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6		IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__GPIO5_24			IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__KPP_COL_6			IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO			IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK		IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS		IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35		IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3		IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7		IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__GPIO5_25			IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__KPP_ROW_6			IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0			IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR		IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD		IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36		IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4		IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8		IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__GPIO5_26			IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__KPP_COL_7			IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK			IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC		IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__I2C1_SDA			IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37		IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5		IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9		IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__GPIO5_27			IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__KPP_ROW_7			IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI			IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR		IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__I2C1_SCL			IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38		IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6		IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10		IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__GPIO5_28			IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX		IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO		IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC		IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4		IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39		IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7		IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11		IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__GPIO5_29			IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX		IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0			IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS		IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5		IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40		IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8		IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12		IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__GPIO5_30			IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX		IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0	IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6		IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41		IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9		IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13		IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__GPIO5_31			IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX		IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1	IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7		IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42		IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10		IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14		IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__GPIO6_0			IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX		IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2	IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8		IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43		IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11		IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15		IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__GPIO6_1			IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX		IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3	IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9		IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44		IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12		IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16		IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__GPIO6_2			IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__UART4_RTS			IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4	IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10		IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45		IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13		IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17		IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__GPIO6_3			IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__UART4_CTS			IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5	IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11		IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46		IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14		IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18		IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__GPIO6_4			IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__UART5_RTS			IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6	IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12		IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47		IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15		IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19		IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__GPIO6_5			IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__UART5_CTS			IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7	IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13		IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48		IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK		IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__EMI_WEIM_A_25			IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__GPIO5_2			IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__ECSPI2_RDY			IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI1_PIN12			IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__CSPI_SS1			IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS			IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__USBPHY1_BISTOK		IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2			IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__GPIO2_30			IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK		IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS		IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__ECSPI1_SS0			IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__I2C2_SCL			IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__EMI_WEIM_D_16			IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__GPIO3_16			IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DI0_PIN5			IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK		IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__ECSPI1_SCLK			IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__I2C2_SDA			IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__EMI_WEIM_D_17			IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__GPIO3_17			IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DI0_PIN6			IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN		IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__ECSPI1_MISO			IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__I2C3_SCL			IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__EMI_WEIM_D_18			IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__GPIO3_18			IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI0_PIN7			IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO		IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__ECSPI1_MOSI			IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__I2C3_SDA			IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS			IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EMI_WEIM_D_19			IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__GPIO3_19			IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DI0_PIN8			IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS		IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__ECSPI1_SS1			IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EPIT1_EPITO			IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__UART1_CTS			IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC		IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EMI_WEIM_D_20			IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__GPIO3_20			IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_DI0_PIN16			IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS		IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__CSPI_SS0			IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EPIT2_EPITO			IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__UART1_RTS			IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR		IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__EMI_WEIM_D_21			IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__GPIO3_21			IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DI0_PIN17			IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK		IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__CSPI_SCLK			IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__I2C1_SCL			IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC		IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__EMI_WEIM_D_22			IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__GPIO3_22			IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DI0_PIN1			IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN		IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__CSPI_MISO			IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR		IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__EMI_WEIM_D_23			IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__GPIO3_23			IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART3_CTS			IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART1_DCD			IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS			IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN2			IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN		IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN14			IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3			IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__GPIO2_31			IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART3_RTS			IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART1_RI			IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3			IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC		IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16			IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__EMI_WEIM_D_24			IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__GPIO3_24			IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART3_TXD_MUX			IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI1_SS2			IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__CSPI_SS2			IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS		IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI2_SS2			IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART1_DTR			IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__EMI_WEIM_D_25			IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__GPIO3_25			IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART3_RXD_MUX			IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI1_SS3			IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__CSPI_SS3			IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC		IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI2_SS3			IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART1_DSR			IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__EMI_WEIM_D_26			IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__GPIO3_26			IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__UART2_TXD_MUX			IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D26__FIRI_RXD			IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_CSI0_D_1			IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DI1_PIN11			IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_SISG_2			IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22		IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__EMI_WEIM_D_27			IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__GPIO3_27			IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__UART2_RXD_MUX			IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D27__FIRI_TXD			IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_CSI0_D_0			IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DI1_PIN13			IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_SISG_3			IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23		IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__EMI_WEIM_D_28			IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__GPIO3_28			IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__UART2_CTS			IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO		IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__CSPI_MOSI			IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__I2C1_SDA			IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, PAD_CTRL_I2C)
-#define MX53_PAD_EIM_D28__IPU_EXT_TRIG			IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DI0_PIN13			IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__EMI_WEIM_D_29			IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__GPIO3_29			IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__UART2_RTS			IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS		IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__CSPI_SS0			IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI1_PIN15			IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC		IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI0_PIN14			IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__EMI_WEIM_D_30			IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__GPIO3_30			IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__UART3_CTS			IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_CSI0_D_3			IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DI0_PIN11			IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21		IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC		IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC		IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__EMI_WEIM_D_31			IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__GPIO3_31			IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__UART3_RTS			IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_CSI0_D_2			IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DI0_PIN12			IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20		IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR		IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR		IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__EMI_WEIM_A_24			IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__GPIO5_4			IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19		IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_CSI1_D_19			IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_SISG_2			IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__USBPHY2_BVALID		IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__EMI_WEIM_A_23			IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__GPIO6_6			IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18		IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_CSI1_D_18			IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_SISG_3			IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION		IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__EMI_WEIM_A_22			IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__GPIO2_16			IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17		IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_CSI1_D_17			IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7			IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__EMI_WEIM_A_21			IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__GPIO2_17			IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16		IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_CSI1_D_16			IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6			IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__EMI_WEIM_A_20			IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__GPIO2_18			IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15		IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_CSI1_D_15			IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5			IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__EMI_WEIM_A_19			IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__GPIO2_19			IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14		IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_CSI1_D_14			IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4			IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__EMI_WEIM_A_18			IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__GPIO2_20			IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13		IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_CSI1_D_13			IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3			IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__EMI_WEIM_A_17			IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__GPIO2_21			IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12		IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_CSI1_D_12			IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2			IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__EMI_WEIM_A_16			IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__GPIO2_22			IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK		IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK		IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1			IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0			IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__GPIO2_23			IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__ECSPI2_SCLK			IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5			IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1			IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__GPIO2_24			IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__ECSPI2_MOSI			IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6			IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__EMI_WEIM_OE			IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__GPIO2_25			IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__ECSPI2_MISO			IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__IPU_DI1_PIN7			IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__USBPHY2_IDDIG			IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__EMI_WEIM_RW			IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__GPIO2_26			IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__ECSPI2_SS0			IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__IPU_DI1_PIN8			IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT		IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA			IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__GPIO2_27			IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__ECSPI2_SS1			IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17			IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0			IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0			IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPIO2_28			IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11		IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11			IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY			IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7			IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1			IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__GPIO2_29			IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10		IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10			IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6			IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0		IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__GPIO3_0			IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9		IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9			IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5			IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1		IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__GPIO3_1			IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8		IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8			IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4			IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2		IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__GPIO3_2			IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7		IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7			IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3			IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3		IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__GPIO3_3			IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6		IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6			IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2			IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4		IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__GPIO3_4			IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5		IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5			IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7			IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5		IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__GPIO3_5			IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4		IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4			IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6			IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6		IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__GPIO3_6			IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3		IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3			IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5			IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7		IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__GPIO3_7			IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2		IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2			IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4			IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8		IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__GPIO3_8			IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1		IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1			IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3			IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9		IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__GPIO3_9			IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0		IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0			IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2			IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10		IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__GPIO3_10			IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15		IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN		IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1		IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11		IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__GPIO3_11			IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2			IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC		IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12		IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__GPIO3_12			IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3			IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC		IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13		IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__GPIO3_13			IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS		IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK		IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14		IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__GPIO3_14			IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS		IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK		IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15		IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__GPIO3_15			IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1			IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4			IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B		IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__GPIO6_12			IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B		IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__GPIO6_13			IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT		IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__GPIO5_0			IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B		IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__GPIO6_22			IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3		IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__GPIO6_24			IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2		IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__GPIO6_26			IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK		IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__GPIO6_28			IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1		IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__GPIO6_30			IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0		IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__GPIO7_22			IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3		IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__GPIO7_24			IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK		IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__GPIO7_26			IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2		IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__GPIO7_28			IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1		IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__GPIO7_30			IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0		IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__GPIO4_0			IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__OSC32k_32K_OUT		IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_11__GPIO4_1			IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_12__GPIO4_2			IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_13__GPIO4_3			IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_14__GPIO4_4			IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE		IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__GPIO6_7			IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0		IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE		IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__GPIO6_8			IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1		IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B		IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__GPIO6_9			IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2		IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0		IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__GPIO6_10			IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3		IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0		IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__GPIO6_11			IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4		IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1		IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__GPIO6_14			IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__MLB_MLBCLK			IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5		IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2		IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__GPIO6_15			IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__IPU_SISG_0			IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__ESAI1_TX0			IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE		IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK		IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__MLB_MLBSIG			IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6		IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3		IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__GPIO6_16			IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__IPU_SISG_1			IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__ESAI1_TX1			IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26		IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__MLB_MLBDAT			IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7		IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_MDIO			IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__GPIO1_22			IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__ESAI1_SCKR			IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_COL			IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2		IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3	IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49		IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK		IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__GPIO1_23			IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR			IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4	IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50		IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_ER			IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__GPIO1_24			IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR			IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK			IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3		IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV			IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__GPIO1_25			IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT			IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__FEC_RDATA_1			IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__GPIO1_26			IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__ESAI1_FST			IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__MLB_MLBSIG			IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1		IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__FEC_RDATA_0			IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__GPIO1_27			IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__ESAI1_HCKT			IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT		IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__FEC_TX_EN			IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__GPIO1_28			IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2		IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__FEC_TDATA_1			IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__GPIO1_29			IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3		IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__MLB_MLBCLK			IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK		IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__FEC_TDATA_0			IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__GPIO1_30			IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1		IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0		IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__FEC_MDC			IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__GPIO1_31			IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0			IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__MLB_MLBDAT			IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG	IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1		IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__PATA_DIOW			IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__GPIO6_17			IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX		IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2		IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__PATA_DMACK			IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__GPIO6_18			IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX		IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3		IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__PATA_DMARQ			IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__GPIO7_0			IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX		IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0		IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4		IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN		IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1		IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX		IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1		IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5	IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__PATA_INTRQ			IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__GPIO7_2			IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__UART2_CTS			IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN			IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2		IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6		IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__PATA_DIOR			IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__GPIO7_3			IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__UART2_RTS			IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__CAN1_RXCAN			IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7		IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B	IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__GPIO7_4			IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD		IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__UART1_CTS		IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN		IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0	IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__PATA_IORDY			IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__GPIO7_5			IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__ESDHC3_CLK			IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__UART1_RTS			IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__CAN2_RXCAN			IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1		IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__PATA_DA_0			IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__GPIO7_6			IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__ESDHC3_RST			IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__OWIRE_LINE			IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2		IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__PATA_DA_1			IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__GPIO7_7			IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__ESDHC4_CMD			IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__UART3_CTS			IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3		IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__PATA_DA_2			IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__GPIO7_8			IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__ESDHC4_CLK			IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__UART3_RTS			IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4		IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__PATA_CS_0			IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__GPIO7_9			IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX		IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5		IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__PATA_CS_1			IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__GPIO7_10			IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX		IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6		IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__PATA_DATA_0		IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPIO2_0			IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0		IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4		IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0	IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0		IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7		IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__PATA_DATA_1		IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPIO2_1			IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1		IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5		IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1	IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1		IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__PATA_DATA_2		IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPIO2_2			IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2		IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6		IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2	IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2		IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__PATA_DATA_3		IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPIO2_3			IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3		IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7		IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3	IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3		IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__PATA_DATA_4		IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPIO2_4			IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4		IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4		IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4	IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4		IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__PATA_DATA_5		IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPIO2_5			IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5		IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5		IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5	IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5		IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__PATA_DATA_6		IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPIO2_6			IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6		IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6		IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6	IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6		IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__PATA_DATA_7		IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPIO2_7			IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7		IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7		IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7	IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7		IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__PATA_DATA_8		IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPIO2_8			IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4		IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8		IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0		IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8	IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8		IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__PATA_DATA_9		IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPIO2_9			IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5		IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9		IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1		IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9	IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9		IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__PATA_DATA_10		IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPIO2_10			IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6		IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10		IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2		IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10	IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10		IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__PATA_DATA_11		IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPIO2_11			IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7		IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11		IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3		IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11	IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11		IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__PATA_DATA_12		IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPIO2_12			IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4		IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12		IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0		IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12	IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12		IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__PATA_DATA_13		IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPIO2_13			IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5		IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13		IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1		IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13	IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13		IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__PATA_DATA_14		IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPIO2_14			IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6		IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14		IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2		IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14	IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14		IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__PATA_DATA_15		IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPIO2_15			IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7		IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15		IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3		IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15	IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15		IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0			IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPIO1_16			IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPT_CAPIN1			IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CSPI_MISO			IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP		IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1			IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPIO1_17			IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPT_CAPIN2			IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CSPI_SS0			IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP		IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__ESDHC1_CMD			IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPIO1_18			IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPT_CMPOUT1			IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CSPI_MOSI			IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP			IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2			IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPIO1_19			IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2			IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__PWM2_PWMO			IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B		IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CSPI_SS1			IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB	IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP		IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__ESDHC1_CLK			IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPIO1_20			IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT		IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPT_CLKIN			IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__CSPI_SCLK			IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0		IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3			IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPIO1_21			IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3			IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__PWM1_PWMO			IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B		IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__CSPI_SS2			IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB	IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1		IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__ESDHC2_CLK			IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__GPIO1_10			IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__KPP_COL_5			IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS		IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__CSPI_SCLK			IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__SCC_RANDOM_V			IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__ESDHC2_CMD			IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__GPIO1_11			IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__KPP_ROW_5			IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC		IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__CSPI_MOSI			IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__SCC_RANDOM			IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3			IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__GPIO1_12			IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__KPP_COL_6			IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC		IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__CSPI_SS2			IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__SJC_DONE			IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2			IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__GPIO1_13			IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__KPP_ROW_6			IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD		IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__CSPI_SS1			IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__SJC_FAIL			IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1			IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__GPIO1_14			IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__KPP_COL_7			IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS		IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__CSPI_SS0			IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO		IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0			IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__GPIO1_15			IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__KPP_ROW_7			IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD		IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__CSPI_MISO			IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT		IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_CLKO			IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__GPIO1_0			IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__KPP_COL_5			IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK		IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__EPIT1_EPITO			IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB			IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR		IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CSU_TD				IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESAI1_SCKR			IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__GPIO1_1			IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__KPP_ROW_5			IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK		IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__PWM2_PWMO			IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__WDOG2_WDOG_B			IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESDHC1_CD			IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__SRC_TESTER_ACK			IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESAI1_FSR			IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__GPIO1_9			IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__KPP_COL_6			IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__CCM_REF_EN_B			IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__PWM1_PWMO			IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__WDOG1_WDOG_B			IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESDHC1_WP			IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__SCC_FAIL_STATE			IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__ESAI1_HCKR			IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__GPIO1_3			IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__I2C3_SCL			IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN			IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__CCM_CLKO2			IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0	IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC		IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__MLB_MLBCLK			IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESAI1_SCKT			IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__GPIO1_6			IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__I2C3_SDA			IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0			IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB		IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1	IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESDHC2_LCTL			IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__MLB_MLBSIG			IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESAI1_FST			IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__GPIO1_2			IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__KPP_ROW_6			IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1			IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0		IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2	IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESDHC2_WP			IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__MLB_MLBDAT			IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESAI1_HCKT			IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__GPIO1_4			IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__KPP_COL_7			IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2			IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1		IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3	IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESDHC2_CD			IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__SCC_SEC_STATE			IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3			IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__GPIO1_5			IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__KPP_ROW_7			IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_CLKO			IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2		IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4	IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__I2C3_SCL			IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_PLL1_BYP			IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1			IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__GPIO1_7			IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__EPIT1_EPITO			IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CAN1_TXCAN			IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__UART2_TXD_MUX			IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_7__FIRI_RXD			IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__SPDIF_PLOCK			IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CCM_PLL2_BYP			IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0			IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__GPIO1_8			IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__EPIT2_EPITO			IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CAN1_RXCAN			IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__UART2_RXD_MUX			IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_8__FIRI_TXD			IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__SPDIF_SRCLK			IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CCM_PLL3_BYP			IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2			IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__GPIO7_11			IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT		IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1		IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SPDIF_IN1			IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__I2C3_SDA			IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SJC_DE_B			IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__ESAI1_TX0			IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPIO7_12			IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0		IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPC_PMIC_RDY			IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG		IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SPDIF_OUT1			IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__IPU_SNOOP2			IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SJC_JTAG_ACT			IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESAI1_TX1			IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__GPIO7_13			IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1		IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__OWIRE_LINE			IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG	IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK		IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESDHC1_LCTL			IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST		IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
-
-#endif	/* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx6.h b/arch/arm/mach-imx/include/mach/iomux-mx6.h
deleted file mode 100644
index 36e31e0657..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx6.h
+++ /dev/null
@@ -1,5616 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2011 Freescale Semiconductor, Inc. */
-
-#define MUX_PAD_CTRL(x)                ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
-
-#ifndef __MACH_IOMUX_MX6Q_H__
-#define __MACH_IOMUX_MX6Q_H__
-
-#include <mach/iomux-v3.h>
-
-#define NON_MUX_I       0x3FF
-#define NON_PAD_I       0x7FF
-
-/*
- * Use to set PAD control
- */
-#define MX6_PAD_CTL_HYS		(1 << 16)
-
-#define MX6_PAD_CTL_PUS_100K_DOWN	(0 << 14)
-#define MX6_PAD_CTL_PUS_47K_UP	(1 << 14)
-#define MX6_PAD_CTL_PUS_100K_UP	(2 << 14)
-#define MX6_PAD_CTL_PUS_22K_UP	(3 << 14)
-
-#define MX6_PAD_CTL_PUE		(1 << 13)
-#define MX6_PAD_CTL_PKE		(1 << 12)
-#define MX6_PAD_CTL_ODE		(1 << 11)
-
-#define MX6_PAD_CTL_SPEED_LOW	(1 << 6)
-#define MX6_PAD_CTL_SPEED_MED	(2 << 6)
-#define MX6_PAD_CTL_SPEED_HIGH	(3 << 6)
-
-#define MX6_PAD_CTL_DSE_DISABLE	(0 << 3)
-#define MX6_PAD_CTL_DSE_240ohm	(1 << 3)
-#define MX6_PAD_CTL_DSE_120ohm	(2 << 3)
-#define MX6_PAD_CTL_DSE_80ohm	(3 << 3)
-#define MX6_PAD_CTL_DSE_60ohm	(4 << 3)
-#define MX6_PAD_CTL_DSE_48ohm	(5 << 3)
-#define MX6_PAD_CTL_DSE_40ohm	(6 << 3)
-#define MX6_PAD_CTL_DSE_34ohm	(7 << 3)
-
-#define MX6_PAD_CTL_SRE_FAST	(1 << 0)
-#define MX6_PAD_CTL_SRE_SLOW	(0 << 0)
-
-#define MX6Q_UART_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
-		MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
-		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
-
-#define MX6Q_ECSPI_PAD_CTRL	(MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_SPEED_MED | \
-		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
-
-#define MX6Q_USDHC_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
-		MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_HIGH | \
-		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
-
-#define MX6Q_ENET_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
-		MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
-		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
-
-#define MX6Q_I2C_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
-		MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
-		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
-		MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST)
-
-#define MX6Q_PWM_PAD_CTRL	(MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
-		MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED| \
-		MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
-		MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST)
-
-#define MX6Q_USB_HSIC_PAD_CTRL	(MX6_PAD_CTL_HYS | MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE |	\
-				MX6_PAD_CTL_DSE_40ohm)
-
-#define MX6Q_HIGH_DRV (MX6_PAD_CTL_DSE_120ohm)
-
-#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1                                        \
-		IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0                                         \
-		IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2                                     \
-		IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS                                   \
-		IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7                                          \
-		IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14                                          \
-		IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT                                           \
-		IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0                              \
-		IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2                                        \
-		IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1                                         \
-		IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3                                     \
-		IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD                                    \
-		IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6                                          \
-		IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13                                          \
-		IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__CCM_STOP                                           \
-		IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1                              \
-		IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0                                        \
-		IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO                                        \
-		IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD                                    \
-		IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7                                          \
-		IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15                                          \
-		IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT                                     \
-		IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2                              \
-		IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA                                    \
-		IOMUX_PAD(0x036C, 0x0058, IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC                                    \
-		IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK                                \
-		IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19                                         \
-		IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0                          \
-		IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT                             \
-		IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY                            \
-		IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0                                    \
-		IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20                                         \
-		IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1                          \
-		IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG                             \
-		IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1                                    \
-		IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21                                         \
-		IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2                          \
-		IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP                                      \
-		IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA                             \
-		IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2                                    \
-		IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22                                         \
-		IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3                          \
-		IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP                                      \
-		IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE                             \
-		IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3                                    \
-		IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23                                         \
-		IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4                          \
-		IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA                                 \
-		IOMUX_PAD(0x0380, 0x006C, IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL                              \
-		IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
-#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24                                      \
-		IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5                       \
-		IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY                            \
-		IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0                                    \
-		IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
-#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25                                         \
-		IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6                          \
-		IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE                               \
-		IOMUX_PAD(0x0388, 0x0074, IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL                              \
-		IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26                                      \
-		IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7                       \
-		IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT                   \
-		IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG                             \
-		IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1                                    \
-		IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
-#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27                                         \
-		IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8                          \
-		IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL                                          \
-		IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA                             \
-		IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2                                    \
-		IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
-#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28                                         \
-		IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9                          \
-		IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE                             \
-		IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3                                    \
-		IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
-#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29                                         \
-		IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10                         \
-		IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE                                  \
-		IOMUX_PAD(0x0398, 0x0084, IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC                                    \
-		IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
-#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30                                         \
-		IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11                         \
-		IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25                                      \
-		IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1                                          \
-		IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY                                          \
-		IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12                                      \
-		IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS                                      \
-		IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__GPIO_5_2                                            \
-		IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE                                    \
-		IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
-#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0                             \
-		IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2                                      \
-		IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0                                          \
-		IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK                                     \
-		IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19                                      \
-		IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL                                     \
-		IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__GPIO_2_30                                           \
-		IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__I2C2_SCL                                            \
-		IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30                                       \
-		IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16                                      \
-		IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK                                         \
-		IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
-#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5                                       \
-		IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18                                      \
-		IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
-#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA                                     \
-		IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
-#define _MX6Q_PAD_EIM_D16__GPIO_3_16                                           \
-		IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D16__I2C2_SDA                                            \
-		IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
-
-#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17                                      \
-		IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO                                         \
-		IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
-#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6                                       \
-		IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK                                    \
-		IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
-#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT                                      \
-		IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D17__GPIO_3_17                                           \
-		IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D17__I2C3_SCL                                            \
-		IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
-#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1                             \
-		IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18                                      \
-		IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI                                         \
-		IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
-#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7                                       \
-		IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17                                      \
-		IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
-#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS                                      \
-		IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D18__GPIO_3_18                                           \
-		IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D18__I2C3_SDA                                            \
-		IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
-#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2                             \
-		IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19                                      \
-		IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1                                          \
-		IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
-#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8                                       \
-		IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16                                      \
-		IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
-#define _MX6Q_PAD_EIM_D19__UART1_CTS                                           \
-		IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
-#define _MX6Q_PAD_EIM_D19__GPIO_3_19                                           \
-		IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO                                         \
-		IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP                                \
-		IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20                                      \
-		IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0                                          \
-		IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
-#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16                                      \
-		IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15                                      \
-		IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
-#define _MX6Q_PAD_EIM_D20__UART1_CTS                                           \
-		IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D20__UART1_RTS                                           \
-		IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
-#define _MX6Q_PAD_EIM_D20__GPIO_3_20                                           \
-		IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO                                         \
-		IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21                                      \
-		IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK                                         \
-		IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17                                      \
-		IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11                                      \
-		IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
-#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC                                    \
-		IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
-#define _MX6Q_PAD_EIM_D21__GPIO_3_21                                           \
-		IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D21__I2C1_SCL                                            \
-		IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
-#define _MX6Q_PAD_EIM_D21__SPDIF_IN1                                           \
-		IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
-
-#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22                                      \
-		IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO                                         \
-		IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1                                       \
-		IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10                                      \
-		IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
-#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR                                   \
-		IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__GPIO_3_22                                           \
-		IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1                                          \
-		IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE                               \
-		IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23                                      \
-		IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS                                      \
-		IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__UART3_CTS                                           \
-		IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
-#define _MX6Q_PAD_EIM_D23__UART1_DCD                                           \
-		IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN                                   \
-		IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
-#define _MX6Q_PAD_EIM_D23__GPIO_3_23                                           \
-		IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2                                       \
-		IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14                                      \
-		IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3                                      \
-		IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY                                          \
-		IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__UART3_CTS                                           \
-		IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__UART3_RTS                                           \
-		IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
-#define _MX6Q_PAD_EIM_EB3__UART1_RI                                            \
-		IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC                                     \
-		IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__GPIO_2_31                                           \
-		IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3                                       \
-		IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31                                       \
-		IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24                                      \
-		IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2                                          \
-		IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__UART3_TXD                                           \
-		IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__UART3_RXD                                           \
-		IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
-#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2                                          \
-		IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
-#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2                                          \
-		IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__GPIO_3_24                                           \
-		IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS                                    \
-		IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
-#define _MX6Q_PAD_EIM_D24__UART1_DTR                                           \
-		IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25                                      \
-		IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3                                          \
-		IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__UART3_TXD                                           \
-		IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__UART3_RXD                                           \
-		IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
-#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3                                          \
-		IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
-#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3                                          \
-		IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__GPIO_3_25                                           \
-		IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC                                     \
-		IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
-#define _MX6Q_PAD_EIM_D25__UART1_DSR                                           \
-		IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26                                      \
-		IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11                                      \
-		IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1                                       \
-		IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14                                      \
-		IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
-#define _MX6Q_PAD_EIM_D26__UART2_TXD                                           \
-		IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__UART2_RXD                                           \
-		IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
-#define _MX6Q_PAD_EIM_D26__GPIO_3_26                                           \
-		IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2                                         \
-		IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22                                   \
-		IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27                                      \
-		IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13                                      \
-		IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0                                       \
-		IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13                                      \
-		IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
-#define _MX6Q_PAD_EIM_D27__UART2_TXD                                           \
-		IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__UART2_RXD                                           \
-		IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
-#define _MX6Q_PAD_EIM_D27__GPIO_3_27                                           \
-		IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3                                         \
-		IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23                                   \
-		IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28                                      \
-		IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D28__I2C1_SDA                                            \
-		IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
-#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI                                         \
-		IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12                                      \
-		IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
-#define _MX6Q_PAD_EIM_D28__UART2_CTS                                           \
-		IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
-#define _MX6Q_PAD_EIM_D28__GPIO_3_28                                           \
-		IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG                                       \
-		IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13                                      \
-		IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29                                      \
-		IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15                                      \
-		IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0                                          \
-		IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
-#define _MX6Q_PAD_EIM_D29__UART2_CTS                                           \
-		IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D29__UART2_RTS                                           \
-		IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
-#define _MX6Q_PAD_EIM_D29__GPIO_3_29                                           \
-		IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC                                     \
-		IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
-#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14                                      \
-		IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30                                      \
-		IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21                                   \
-		IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11                                      \
-		IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3                                       \
-		IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__UART3_CTS                                           \
-		IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
-#define _MX6Q_PAD_EIM_D30__GPIO_3_30                                           \
-		IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC                                     \
-		IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
-#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0                              \
-		IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31                                      \
-		IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20                                   \
-		IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12                                      \
-		IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2                                       \
-		IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__UART3_CTS                                           \
-		IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__UART3_RTS                                           \
-		IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
-#define _MX6Q_PAD_EIM_D31__GPIO_3_31                                           \
-		IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR                                    \
-		IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1                              \
-		IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24                                      \
-		IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19                                   \
-		IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19                                      \
-		IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
-#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2                                         \
-		IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2                                         \
-		IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__GPIO_5_4                                            \
-		IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2                              \
-		IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24                                       \
-		IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23                                      \
-		IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18                                   \
-		IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18                                      \
-		IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
-#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3                                         \
-		IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3                                         \
-		IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__GPIO_6_6                                            \
-		IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3                              \
-		IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23                                       \
-		IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22                                      \
-		IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17                                   \
-		IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17                                      \
-		IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
-#define _MX6Q_PAD_EIM_A22__GPIO_2_16                                           \
-		IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0                                       \
-		IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22                                       \
-		IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21                                      \
-		IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16                                   \
-		IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16                                      \
-		IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
-#define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED                                   \
-		IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18                          \
-		IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__GPIO_2_17                                           \
-		IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1                                       \
-		IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21                                       \
-		IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20                                      \
-		IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15                                   \
-		IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15                                      \
-		IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
-#define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED                                   \
-		IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19                          \
-		IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__GPIO_2_18                                           \
-		IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2                                       \
-		IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20                                       \
-		IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19                                      \
-		IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14                                   \
-		IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14                                      \
-		IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
-#define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED                                   \
-		IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20                          \
-		IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__GPIO_2_19                                           \
-		IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3                                       \
-		IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19                                       \
-		IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18                                      \
-		IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13                                   \
-		IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13                                      \
-		IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
-#define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED                                   \
-		IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21                          \
-		IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__GPIO_2_20                                           \
-		IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4                                       \
-		IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18                                       \
-		IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17                                      \
-		IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12                                   \
-		IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12                                      \
-		IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
-#define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED                                   \
-		IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22                          \
-		IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__GPIO_2_21                                           \
-		IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5                                       \
-		IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17                                       \
-		IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16                                      \
-		IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK                                   \
-		IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK                                    \
-		IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
-#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23                          \
-		IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__GPIO_2_22                                           \
-		IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6                                       \
-		IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16                                       \
-		IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0                                      \
-		IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5                                       \
-		IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK                                         \
-		IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24                          \
-		IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__GPIO_2_23                                           \
-		IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7                                       \
-		IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1                                      \
-		IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6                                       \
-		IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI                                         \
-		IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25                          \
-		IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__GPIO_2_24                                           \
-		IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8                                       \
-		IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE                                         \
-		IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7                                        \
-		IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO                                          \
-		IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
-#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26                           \
-		IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_OE__GPIO_2_25                                            \
-		IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9                                        \
-		IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW                                         \
-		IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8                                        \
-		IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0                                           \
-		IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
-#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27                           \
-		IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__GPIO_2_26                                            \
-		IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10                                       \
-		IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29                                        \
-		IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA                                       \
-		IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17                                      \
-		IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1                                          \
-		IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__GPIO_2_27                                           \
-		IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11                                      \
-		IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26                                       \
-		IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0                                      \
-		IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11                                   \
-		IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11                                      \
-		IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
-#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0                           \
-		IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY                                        \
-		IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__GPIO_2_28                                           \
-		IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12                                      \
-		IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27                                       \
-		IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1                                      \
-		IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10                                   \
-		IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10                                      \
-		IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
-#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1                           \
-		IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__GPIO_2_29                                           \
-		IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13                                      \
-		IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28                                       \
-		IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0                                    \
-		IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9                                    \
-		IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9                                       \
-		IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2                           \
-		IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__GPIO_3_0                                            \
-		IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14                                      \
-		IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0                                        \
-		IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1                                    \
-		IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8                                    \
-		IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8                                       \
-		IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3                           \
-		IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE                      \
-		IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__GPIO_3_1                                            \
-		IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15                                      \
-		IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1                                        \
-		IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2                                    \
-		IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7                                    \
-		IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7                                       \
-		IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4                           \
-		IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE                      \
-		IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__GPIO_3_2                                            \
-		IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16                                      \
-		IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2                                        \
-		IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3                                    \
-		IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6                                    \
-		IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6                                       \
-		IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5                           \
-		IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ                          \
-		IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__GPIO_3_3                                            \
-		IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17                                      \
-		IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3                                        \
-		IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4                                    \
-		IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5                                    \
-		IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5                                       \
-		IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6                           \
-		IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN                           \
-		IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__GPIO_3_4                                            \
-		IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18                                      \
-		IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4                                        \
-		IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5                                    \
-		IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4                                    \
-		IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4                                       \
-		IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7                           \
-		IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP                           \
-		IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__GPIO_3_5                                            \
-		IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19                                      \
-		IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5                                        \
-		IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6                                    \
-		IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3                                    \
-		IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3                                       \
-		IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8                           \
-		IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN                           \
-		IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__GPIO_3_6                                            \
-		IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20                                      \
-		IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6                                        \
-		IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7                                    \
-		IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2                                    \
-		IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2                                       \
-		IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9                           \
-		IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__GPIO_3_7                                            \
-		IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21                                      \
-		IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7                                        \
-		IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8                                    \
-		IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1                                    \
-		IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1                                       \
-		IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10                          \
-		IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__GPIO_3_8                                            \
-		IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22                                      \
-		IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8                                        \
-		IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9                                    \
-		IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0                                    \
-		IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0                                       \
-		IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11                          \
-		IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__GPIO_3_9                                            \
-		IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23                                      \
-		IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9                                        \
-		IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10                                  \
-		IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15                                     \
-		IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN                                  \
-		IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
-#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12                         \
-		IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__GPIO_3_10                                          \
-		IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24                                     \
-		IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10                                      \
-		IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11                                  \
-		IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2                                      \
-		IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC                                    \
-		IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
-#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13                         \
-		IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6                         \
-		IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__GPIO_3_11                                          \
-		IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25                                     \
-		IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11                                      \
-		IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12                                  \
-		IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3                                      \
-		IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC                                    \
-		IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
-#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14                         \
-		IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3                         \
-		IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__GPIO_3_12                                          \
-		IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26                                     \
-		IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12                                      \
-		IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13                                  \
-		IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS                                     \
-		IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK                                    \
-		IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
-#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15                         \
-		IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4                         \
-		IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__GPIO_3_13                                          \
-		IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27                                     \
-		IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13                                      \
-		IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14                                  \
-		IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS                                     \
-		IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK                                    \
-		IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16                         \
-		IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5                         \
-		IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__GPIO_3_14                                          \
-		IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28                                     \
-		IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14                                      \
-		IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15                                  \
-		IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1                                      \
-		IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4                                      \
-		IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17                         \
-		IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__GPIO_3_15                                          \
-		IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29                                     \
-		IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15                                      \
-		IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT                                     \
-		IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B                                  \
-		IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0                                           \
-		IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30                                     \
-		IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25                                      \
-		IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK                                     \
-		IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16                                     \
-		IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31                                          \
-		IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31                                     \
-		IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK                              \
-		IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK                              \
-		IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28                     \
-		IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0                        \
-		IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16                                      \
-		IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0                              \
-		IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15                                    \
-		IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15                                    \
-		IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC                                   \
-		IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29                        \
-		IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1                           \
-		IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17                                         \
-		IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1                                 \
-		IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2                                      \
-		IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2                                      \
-		IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD                                    \
-		IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30                         \
-		IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2                            \
-		IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18                                          \
-		IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2                                  \
-		IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9                             \
-		IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3                                      \
-		IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3                                      \
-		IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS                                   \
-		IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31                         \
-		IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3                            \
-		IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19                                          \
-		IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3                                  \
-		IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10                            \
-		IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4                                      \
-		IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4                                      \
-		IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD                                    \
-		IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP                                          \
-		IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD                                   \
-		IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20                                          \
-		IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4                                  \
-		IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11                            \
-		IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0                                 \
-		IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0                                 \
-		IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK                                      \
-		IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0                             \
-		IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                              \
-		IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21                                        \
-		IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5                                \
-		IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1                                 \
-		IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1                                 \
-		IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI                                      \
-		IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1                             \
-		IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL                     \
-		IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22                                        \
-		IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6                                \
-		IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12                          \
-		IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2                                 \
-		IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2                                 \
-		IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO                                      \
-		IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2                             \
-		IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE                                  \
-		IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23                                        \
-		IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7                                \
-		IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13                          \
-		IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3                                 \
-		IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3                                 \
-		IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0                                       \
-		IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3                             \
-		IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR                             \
-		IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24                                        \
-		IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8                                \
-		IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14                          \
-		IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4                                 \
-		IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4                                 \
-		IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1                                       \
-		IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4                             \
-		IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB                               \
-		IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25                                        \
-		IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9                                \
-		IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15                          \
-		IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5                                 \
-		IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5                                 \
-		IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2                                       \
-		IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS                                 \
-		IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS                         \
-		IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26                                        \
-		IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10                               \
-		IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16                          \
-		IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6                                 \
-		IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6                                 \
-		IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3                                       \
-		IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC                                  \
-		IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE                        \
-		IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27                                        \
-		IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11                               \
-		IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17                          \
-		IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7                                 \
-		IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7                                 \
-		IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY                                       \
-		IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5                             \
-		IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0                       \
-		IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28                                        \
-		IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12                               \
-		IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18                          \
-		IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8                                 \
-		IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8                                 \
-		IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO                                        \
-		IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B                                     \
-		IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1                       \
-		IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29                                        \
-		IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13                               \
-		IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19                          \
-		IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9                                 \
-		IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9                                 \
-		IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO                                        \
-		IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B                                     \
-		IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2                       \
-		IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30                                        \
-		IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14                               \
-		IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20                          \
-		IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10                               \
-		IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10                               \
-		IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6                            \
-		IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3                      \
-		IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31                                       \
-		IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15                              \
-		IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21                         \
-		IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11                               \
-		IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11                               \
-		IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7                            \
-		IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4                      \
-		IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5                                        \
-		IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16                              \
-		IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22                         \
-		IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12                               \
-		IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12                               \
-		IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED                               \
-		IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5                      \
-		IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6                                        \
-		IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17                              \
-		IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23                         \
-		IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13                               \
-		IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13                               \
-		IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS                                \
-		IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0                      \
-		IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7                                        \
-		IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18                              \
-		IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24                         \
-		IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14                               \
-		IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14                               \
-		IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC                                 \
-		IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1                      \
-		IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8                                        \
-		IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19                              \
-		IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15                               \
-		IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15                               \
-		IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1                                      \
-		IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1                                      \
-		IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2                      \
-		IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9                                        \
-		IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20                              \
-		IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25                         \
-		IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16                               \
-		IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16                               \
-		IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI                                     \
-		IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC                                 \
-		IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0                           \
-		IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10                                       \
-		IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21                              \
-		IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26                         \
-		IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17                               \
-		IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17                               \
-		IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO                                     \
-		IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD                                 \
-		IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1                           \
-		IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11                                       \
-		IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22                              \
-		IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27                         \
-		IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18                               \
-		IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18                               \
-		IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0                                      \
-		IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS                                \
-		IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS                                \
-		IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12                                       \
-		IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23                              \
-		IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2                                  \
-		IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19                               \
-		IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19                               \
-		IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK                                     \
-		IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD                                 \
-		IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC                                 \
-		IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13                                       \
-		IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24                              \
-		IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3                                  \
-		IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20                               \
-		IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20                               \
-		IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK                                     \
-		IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC                                 \
-		IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7                      \
-		IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14                                       \
-		IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25                              \
-		IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28                         \
-		IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21                               \
-		IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21                               \
-		IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI                                     \
-		IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD                                 \
-		IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0                         \
-		IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15                                       \
-		IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26                              \
-		IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29                         \
-		IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22                               \
-		IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22                               \
-		IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO                                     \
-		IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS                                \
-		IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1                         \
-		IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16                                       \
-		IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27                              \
-		IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30                         \
-		IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23                               \
-		IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23                               \
-		IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0                                      \
-		IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD                                 \
-		IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2                         \
-		IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17                                       \
-		IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28                              \
-		IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31                         \
-		IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED                                 \
-		IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO                                         \
-		IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR                                        \
-		IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3                           \
-		IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT                              \
-		IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22                                         \
-		IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK                                       \
-		IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED                              \
-		IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK                                    \
-		IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR                                      \
-		IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4                        \
-		IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23                                      \
-		IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK                                    \
-		IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH                 \
-		IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER                                       \
-		IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR                                       \
-		IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1                                        \
-		IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
-#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT                             \
-		IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24                                        \
-		IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI                                          \
-		IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD                    \
-		IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED                               \
-		IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN                                      \
-		IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT                                      \
-		IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK                              \
-		IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25                                       \
-		IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO                                         \
-		IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD                   \
-		IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG                                        \
-		IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1                                      \
-		IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
-#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST                                         \
-		IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT                              \
-		IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26                                         \
-		IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__PHY_TCK                                           \
-		IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET                 \
-		IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT                                    \
-		IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0                                      \
-		IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
-#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT                                        \
-		IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1                                        \
-		IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27                                         \
-		IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__PHY_TMS                                           \
-		IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV                  \
-		IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED                                \
-		IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN                                       \
-		IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2                                    \
-		IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
-#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28                                        \
-		IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI                                     \
-		IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH                   \
-		IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK                                        \
-		IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1                                      \
-		IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3                                     \
-		IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN                               \
-		IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29                                         \
-		IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO                                      \
-		IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD                     \
-		IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED                                 \
-		IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0                                      \
-		IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1                                     \
-		IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
-#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30                                         \
-		IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK                                      \
-		IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD                     \
-		IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT                                         \
-		IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__ENET_MDC                                           \
-		IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0                                      \
-		IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN                                \
-		IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__GPIO_1_31                                          \
-		IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS                                       \
-		IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET                  \
-		IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5                                 \
-		IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5                                   \
-		IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4                                   \
-		IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4                                 \
-		IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3                                 \
-		IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3                                   \
-		IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2                                 \
-		IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2                                   \
-		IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0                                       \
-		IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1                                       \
-		IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2                                       \
-		IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3                                       \
-		IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4                                       \
-		IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5                                       \
-		IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6                                       \
-		IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7                                       \
-		IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8                                       \
-		IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9                                       \
-		IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10                                     \
-		IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11                                     \
-		IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12                                     \
-		IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13                                     \
-		IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14                                     \
-		IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15                                     \
-		IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS                                      \
-		IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0                                     \
-		IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1                                     \
-		IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS                                      \
-		IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET                                  \
-		IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0                                 \
-		IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1                                 \
-		IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0                               \
-		IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2                                 \
-		IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0                               \
-		IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1                               \
-		IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1                               \
-		IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0                                 \
-		IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1                                 \
-		IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE                                    \
-		IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0                                 \
-		IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0                                   \
-		IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9                                       \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1                                 \
-		IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1                                   \
-		IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6                                 \
-		IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6                                   \
-		IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7                                 \
-		IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7                                   \
-		IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK                                        \
-		IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
-#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3                                       \
-		IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
-#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC                                    \
-		IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
-#define _MX6Q_PAD_KEY_COL0__KPP_COL_0                                          \
-		IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__UART4_TXD                                          \
-		IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__UART4_RXD                                          \
-		IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__GPIO_4_6                                           \
-		IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT                                     \
-		IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST                                     \
-		IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI                                        \
-		IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
-#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3                                       \
-		IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                                    \
-		IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
-#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0                                          \
-		IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__UART4_TXD                                          \
-		IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__UART4_RXD                                          \
-		IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
-#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7                                           \
-		IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT                                     \
-		IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0                             \
-		IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO                                        \
-		IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
-#define _MX6Q_PAD_KEY_COL1__ENET_MDIO                                          \
-		IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
-#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS                                   \
-		IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
-#define _MX6Q_PAD_KEY_COL1__KPP_COL_1                                          \
-		IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__UART5_TXD                                          \
-		IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__UART5_RXD                                          \
-		IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__GPIO_4_8                                           \
-		IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT                                     \
-		IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1                             \
-		IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0                                         \
-		IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
-#define _MX6Q_PAD_KEY_ROW1__ENET_COL                                           \
-		IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD                                    \
-		IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
-#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1                                          \
-		IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__UART5_TXD                                          \
-		IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__UART5_RXD                                          \
-		IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
-#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9                                           \
-		IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT                                     \
-		IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2                             \
-		IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1                                         \
-		IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
-#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2                                       \
-		IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
-#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN                                         \
-		IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__KPP_COL_2                                          \
-		IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__ENET_MDC                                           \
-		IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__GPIO_4_10                                          \
-		IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP                         \
-		IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3                             \
-		IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2                                         \
-		IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
-#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2                                       \
-		IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN                                         \
-		IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2                                          \
-		IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT                                     \
-		IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11                                          \
-		IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE                                   \
-		IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
-#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4                             \
-		IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3                                         \
-		IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
-#define _MX6Q_PAD_KEY_COL3__ENET_CRS                                           \
-		IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL                                    \
-		IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
-#define _MX6Q_PAD_KEY_COL3__KPP_COL_3                                          \
-		IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL3__I2C2_SCL                                           \
-		IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
-#define _MX6Q_PAD_KEY_COL3__GPIO_4_12                                          \
-		IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1                                          \
-		IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
-#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5                             \
-		IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT                                     \
-		IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK                                  \
-		IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA                                    \
-		IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
-#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3                                          \
-		IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA                                           \
-		IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
-#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13                                          \
-		IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT                                     \
-		IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6                             \
-		IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN                                         \
-		IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4                                        \
-		IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC                                   \
-		IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
-#define _MX6Q_PAD_KEY_COL4__KPP_COL_4                                          \
-		IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__UART5_CTS                                          \
-		IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__UART5_RTS                                          \
-		IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__GPIO_4_14                                          \
-		IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49                                 \
-		IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7                             \
-		IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN                                         \
-		IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5                                        \
-		IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR                                  \
-		IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4                                          \
-		IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__UART5_CTS                                          \
-		IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
-#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15                                          \
-		IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50                                 \
-		IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8                             \
-		IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_0__CCM_CLKO                                             \
-		IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_0__KPP_COL_5                                            \
-		IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
-#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK                                    \
-		IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
-#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO                                          \
-		IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_0__GPIO_1_0                                             \
-		IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR                                     \
-		IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5                           \
-		IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR                                           \
-		IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
-#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B                                         \
-		IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_1__KPP_ROW_5                                            \
-		IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
-#define _MX6Q_PAD_GPIO_1__PWM2_PWMO                                            \
-		IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_1__GPIO_1_1                                             \
-		IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_1__USDHC1_CD                                            \
-		IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK                                       \
-		IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_9__ESAI1_FSR                                            \
-		IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
-#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B                                         \
-		IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_9__KPP_COL_6                                            \
-		IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
-#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B                                         \
-		IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_9__PWM1_PWMO                                            \
-		IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_9__GPIO_1_9                                             \
-		IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_9__USDHC1_WP                                            \
-		IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
-#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST                                        \
-		IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR                                           \
-		IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
-#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0                           \
-		IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_3__I2C3_SCL                                             \
-		IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
-#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT                                \
-		IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_3__CCM_CLKO2                                            \
-		IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_3__GPIO_1_3                                             \
-		IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC                                      \
-		IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
-#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK                                           \
-		IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
-
-#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT                                           \
-		IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
-#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1                           \
-		IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__I2C3_SDA                                             \
-		IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
-#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0                                        \
-		IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB                                      \
-		IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__GPIO_1_6                                             \
-		IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL                                          \
-		IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG                                           \
-		IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
-
-#define _MX6Q_PAD_GPIO_2__ESAI1_FST                                            \
-		IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
-#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2                           \
-		IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__KPP_ROW_6                                            \
-		IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
-#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1                                        \
-		IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0                                  \
-		IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__GPIO_1_2                                             \
-		IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__USDHC2_WP                                            \
-		IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT                                           \
-		IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
-
-#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT                                           \
-		IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
-#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3                           \
-		IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__KPP_COL_7                                            \
-		IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
-#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2                                        \
-		IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1                                  \
-		IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__GPIO_1_4                                             \
-		IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__USDHC2_CD                                            \
-		IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED                      \
-		IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3                                        \
-		IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
-#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4                           \
-		IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_5__KPP_ROW_7                                            \
-		IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
-#define _MX6Q_PAD_GPIO_5__CCM_CLKO                                             \
-		IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2                                  \
-		IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_5__GPIO_1_5                                             \
-		IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_5__I2C3_SCL                                             \
-		IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
-#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI                                       \
-		IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1                                        \
-		IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
-#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY                                           \
-		IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO                                          \
-		IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN                                           \
-		IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__UART2_TXD                                            \
-		IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__UART2_RXD                                            \
-		IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
-#define _MX6Q_PAD_GPIO_7__GPIO_1_7                                             \
-		IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK                                          \
-		IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE                              \
-		IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0                                        \
-		IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
-#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT                                \
-		IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO                                          \
-		IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN                                           \
-		IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
-#define _MX6Q_PAD_GPIO_8__UART2_TXD                                            \
-		IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__UART2_RXD                                            \
-		IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
-#define _MX6Q_PAD_GPIO_8__GPIO_1_8                                             \
-		IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK                                          \
-		IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP                          \
-		IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2                                       \
-		IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
-#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN                                 \
-		IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT                        \
-		IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0)
-#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL                                         \
-		IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_16__SPDIF_IN1                                           \
-		IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
-#define _MX6Q_PAD_GPIO_16__GPIO_7_11                                           \
-		IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_16__I2C3_SDA                                            \
-		IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
-#define _MX6Q_PAD_GPIO_16__SJC_DE_B                                            \
-		IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_17__ESAI1_TX0                                           \
-		IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
-#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN                                 \
-		IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY                                        \
-		IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
-#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0                               \
-		IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
-#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1                                          \
-		IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_17__GPIO_7_12                                           \
-		IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT                                        \
-		IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_18__ESAI1_TX1                                           \
-		IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
-#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK                                         \
-		IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
-#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT                                      \
-		IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1                               \
-		IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
-#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK                                   \
-		IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
-#define _MX6Q_PAD_GPIO_18__GPIO_7_13                                           \
-		IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL                      \
-		IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST                                      \
-		IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_19__KPP_COL_5                                           \
-		IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
-#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT                                \
-		IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1                                          \
-		IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__CCM_CLKO                                            \
-		IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY                                          \
-		IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__GPIO_4_5                                            \
-		IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__ENET_TX_ER                                          \
-		IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT                                        \
-		IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK                                \
-		IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12                \
-		IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0                                 \
-		IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18                                       \
-		IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29                              \
-		IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO                                  \
-		IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC                                   \
-		IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13                  \
-		IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO                                          \
-		IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1                                   \
-		IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19                                         \
-		IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30                                \
-		IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL                                     \
-		IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN                              \
-		IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0                                  \
-		IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14               \
-		IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2                                \
-		IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20                                      \
-		IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31                             \
-		IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK                                  \
-		IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC                                  \
-		IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1                                    \
-		IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15                 \
-		IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3                                  \
-		IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21                                        \
-		IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32                               \
-		IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0                                  \
-		IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4                                     \
-		IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2                                     \
-		IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK                                       \
-		IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5                                         \
-		IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC                                   \
-		IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22                                         \
-		IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43                                \
-		IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1                                   \
-		IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5                                     \
-		IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3                                     \
-		IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI                                       \
-		IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5                                         \
-		IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD                                   \
-		IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23                                         \
-		IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44                                \
-		IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2                                   \
-		IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6                                     \
-		IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4                                     \
-		IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO                                       \
-		IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6                                         \
-		IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS                                  \
-		IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24                                         \
-		IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45                                \
-		IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3                                   \
-		IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7                                     \
-		IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5                                     \
-		IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0                                        \
-		IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6                                         \
-		IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD                                   \
-		IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25                                         \
-		IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46                                \
-		IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4                                   \
-		IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8                                     \
-		IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6                                     \
-		IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK                                       \
-		IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7                                         \
-		IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA                                          \
-		IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26                                         \
-		IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47                                \
-		IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5                                   \
-		IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9                                     \
-		IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7                                     \
-		IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI                                       \
-		IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7                                         \
-		IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL                                          \
-		IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27                                         \
-		IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48                                \
-		IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6                                   \
-		IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10                                   \
-		IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC                                  \
-		IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO                                      \
-		IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD                                        \
-		IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD                                        \
-		IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4                                  \
-		IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28                                        \
-		IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33                               \
-		IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7                                  \
-		IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11                                   \
-		IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS                                 \
-		IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0                                       \
-		IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD                                        \
-		IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD                                        \
-		IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5                                  \
-		IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29                                        \
-		IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34                               \
-		IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8                                  \
-		IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12                                   \
-		IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8                                    \
-		IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16                 \
-		IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD                                        \
-		IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD                                        \
-		IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6                                  \
-		IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30                                        \
-		IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35                               \
-		IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9                                  \
-		IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13                                   \
-		IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9                                    \
-		IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17                 \
-		IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD                                        \
-		IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD                                        \
-		IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7                                  \
-		IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31                                        \
-		IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36                               \
-		IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10                                 \
-		IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14                                   \
-		IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10                                   \
-		IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18                 \
-		IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD                                        \
-		IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD                                        \
-		IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8                                  \
-		IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0                                         \
-		IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37                               \
-		IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11                                 \
-		IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15                                   \
-		IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11                                   \
-		IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19                 \
-		IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD                                        \
-		IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD                                        \
-		IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9                                  \
-		IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1                                         \
-		IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38                               \
-		IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12                                 \
-		IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16                                   \
-		IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12                                   \
-		IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20                 \
-		IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS                                        \
-		IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS                                        \
-		IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10                                 \
-		IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2                                         \
-		IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39                               \
-		IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13                                 \
-		IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17                                   \
-		IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13                                   \
-		IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21                 \
-		IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS                                        \
-		IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11                                 \
-		IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3                                         \
-		IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40                               \
-		IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14                                 \
-		IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18                                   \
-		IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14                                   \
-		IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22                 \
-		IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS                                        \
-		IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS                                        \
-		IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12                                 \
-		IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4                                         \
-		IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41                               \
-		IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15                                 \
-		IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19                                   \
-		IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15                                   \
-		IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23                 \
-		IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS                                        \
-		IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13                                 \
-		IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5                                         \
-		IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42                               \
-		IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9                            \
-		IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TMS__SJC_TMS                                            \
-		IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_MOD__SJC_MOD                                            \
-		IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB                                        \
-		IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TDI__SJC_TDI                                            \
-		IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TCK__SJC_TCK                                            \
-		IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TDO__SJC_TDO                                            \
-		IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0                                   \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1                             \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM               \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ                            \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_POR_B__SRC_POR_B                                             \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1                                  \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B                                      \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0                                  \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE                                     \
-		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7                                        \
-		IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__UART1_TXD                                          \
-		IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__UART1_RXD                                          \
-		IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
-#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24                   \
-		IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0                               \
-		IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0                               \
-		IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17                                          \
-		IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12                          \
-		IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV                   \
-		IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6                                        \
-		IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__UART1_TXD                                          \
-		IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__UART1_RXD                                          \
-		IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
-#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25                   \
-		IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1                               \
-		IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1                               \
-		IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18                                          \
-		IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13                          \
-		IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10                             \
-		IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5                                        \
-		IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__UART2_TXD                                          \
-		IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__UART2_RXD                                          \
-		IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
-#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26                   \
-		IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2                               \
-		IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2                               \
-		IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0                                           \
-		IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14                          \
-		IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11                             \
-		IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4                                        \
-		IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__UART2_TXD                                          \
-		IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__UART2_RXD                                          \
-		IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
-#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27                   \
-		IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3                               \
-		IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3                               \
-		IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1                                           \
-		IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15                          \
-		IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12                             \
-		IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD                                          \
-		IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__UART2_CTS                                           \
-		IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
-#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN                                          \
-		IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4                                \
-		IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4                                \
-		IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__GPIO_7_2                                            \
-		IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16                           \
-		IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13                              \
-		IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK                                          \
-		IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__UART2_CTS                                           \
-		IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__UART2_RTS                                           \
-		IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
-#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN                                          \
-		IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
-#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5                                \
-		IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5                                \
-		IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__GPIO_7_3                                            \
-		IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17                           \
-		IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14                              \
-		IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0                                        \
-		IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__UART1_CTS                                          \
-		IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
-#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN                                         \
-		IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6                               \
-		IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6                               \
-		IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4                                           \
-		IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18                          \
-		IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15                             \
-		IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1                                        \
-		IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__UART1_CTS                                          \
-		IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__UART1_RTS                                          \
-		IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
-#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN                                         \
-		IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
-#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7                               \
-		IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7                               \
-		IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5                                           \
-		IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19                          \
-		IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0                              \
-		IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2                                        \
-		IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28                   \
-		IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8                               \
-		IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8                               \
-		IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6                                           \
-		IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20                          \
-		IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1                              \
-		IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3                                        \
-		IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__UART3_CTS                                          \
-		IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
-#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29                   \
-		IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9                               \
-		IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9                               \
-		IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7                                           \
-		IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21                          \
-		IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2                              \
-		IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_RST__USDHC3_RST                                          \
-		IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__UART3_CTS                                           \
-		IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__UART3_RTS                                           \
-		IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
-#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30                    \
-		IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10                               \
-		IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10                               \
-		IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__GPIO_7_8                                            \
-		IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22                           \
-		IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3                               \
-		IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE                                       \
-		IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4                                       \
-		IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31                  \
-		IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11                             \
-		IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11                             \
-		IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7                                          \
-		IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23                         \
-		IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0                                    \
-		IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE                                       \
-		IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST                                        \
-		IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0                   \
-		IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12                             \
-		IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12                             \
-		IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8                                          \
-		IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24                         \
-		IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1                                    \
-		IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN                                   \
-		IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5                                      \
-		IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1                  \
-		IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13                            \
-		IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13                            \
-		IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9                                         \
-		IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32                       \
-		IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0                           \
-		IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0                                    \
-		IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1                                     \
-		IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2                   \
-		IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14                             \
-		IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14                             \
-		IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10                                         \
-		IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33                        \
-		IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1                            \
-		IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N                                      \
-		IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15                             \
-		IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15                             \
-		IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11                                         \
-		IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2                            \
-		IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N                                      \
-		IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT                                    \
-		IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT                                    \
-		IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3                   \
-		IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14                                         \
-		IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT                          \
-		IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N                                      \
-		IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0                                       \
-		IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0                                         \
-		IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
-#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE                                     \
-		IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2                                         \
-		IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15                                         \
-		IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0                                       \
-		IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N                                      \
-		IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1                                       \
-		IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1                                         \
-		IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
-#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26                                    \
-		IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4                   \
-		IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16                                         \
-		IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1                                       \
-		IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK                                         \
-		IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD                                          \
-		IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN                                         \
-		IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__UART3_TXD                                           \
-		IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__UART3_RXD                                           \
-		IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
-#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5                     \
-		IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__GPIO_7_9                                            \
-		IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR                                     \
-		IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK                                          \
-		IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN                                         \
-		IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CLK__UART3_TXD                                           \
-		IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CLK__UART3_RXD                                           \
-		IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
-#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6                     \
-		IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CLK__GPIO_7_10                                           \
-		IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0                                         \
-		IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4                                        \
-		IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0                              \
-		IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16                              \
-		IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16                              \
-		IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__GPIO_2_0                                           \
-		IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0                                \
-		IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0                                \
-		IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1                                         \
-		IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5                                        \
-		IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1                              \
-		IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17                              \
-		IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17                              \
-		IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__GPIO_2_1                                           \
-		IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1                                \
-		IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1                                \
-		IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2                                         \
-		IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6                                        \
-		IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2                              \
-		IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18                              \
-		IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18                              \
-		IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__GPIO_2_2                                           \
-		IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2                                \
-		IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2                                \
-		IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3                                         \
-		IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7                                        \
-		IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3                              \
-		IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19                              \
-		IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19                              \
-		IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__GPIO_2_3                                           \
-		IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3                                \
-		IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3                                \
-		IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4                                         \
-		IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4                                        \
-		IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4                              \
-		IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20                              \
-		IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20                              \
-		IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__GPIO_2_4                                           \
-		IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4                                \
-		IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4                                \
-		IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5                                         \
-		IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5                                        \
-		IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5                              \
-		IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21                              \
-		IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21                              \
-		IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__GPIO_2_5                                           \
-		IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5                                \
-		IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5                                \
-		IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6                                         \
-		IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6                                        \
-		IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6                              \
-		IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22                              \
-		IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22                              \
-		IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__GPIO_2_6                                           \
-		IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6                                \
-		IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6                                \
-		IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7                                         \
-		IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7                                        \
-		IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7                              \
-		IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23                              \
-		IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23                              \
-		IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__GPIO_2_7                                           \
-		IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7                                \
-		IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7                                \
-		IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8                                         \
-		IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0                                        \
-		IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS                                        \
-		IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24                              \
-		IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24                              \
-		IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8                                           \
-		IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8                                \
-		IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8                                \
-		IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9                                         \
-		IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1                                        \
-		IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO                                          \
-		IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25                              \
-		IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25                              \
-		IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9                                           \
-		IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9                                \
-		IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9                                \
-		IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10                                        \
-		IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2                                        \
-		IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO                                          \
-		IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26                              \
-		IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26                              \
-		IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10                                          \
-		IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10                               \
-		IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10                               \
-		IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11                                        \
-		IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3                                        \
-		IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27                              \
-		IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27                              \
-		IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11                                          \
-		IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11                               \
-		IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11                               \
-		IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12                                        \
-		IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4                                        \
-		IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__UART2_TXD                                          \
-		IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__UART2_RXD                                          \
-		IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
-#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28                              \
-		IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28                              \
-		IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12                                          \
-		IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12                               \
-		IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12                               \
-		IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13                                        \
-		IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5                                        \
-		IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__UART2_CTS                                          \
-		IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__UART2_RTS                                          \
-		IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
-#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29                              \
-		IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29                              \
-		IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13                                          \
-		IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13                               \
-		IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13                               \
-		IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14                                        \
-		IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6                                        \
-		IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__UART2_CTS                                          \
-		IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
-#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30                              \
-		IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30                              \
-		IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14                                          \
-		IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14                               \
-		IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14                               \
-		IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15                                        \
-		IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7                                        \
-		IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__UART2_TXD                                          \
-		IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__UART2_RXD                                          \
-		IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
-#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31                              \
-		IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31                              \
-		IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15                                          \
-		IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15                               \
-		IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15                               \
-		IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1                                        \
-		IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0                                         \
-		IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
-#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO                                          \
-		IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2                                         \
-		IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7                    \
-		IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17                                          \
-		IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0                                  \
-		IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8                              \
-		IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0                                        \
-		IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO                                        \
-		IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
-#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS                           \
-		IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1                                         \
-		IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8                    \
-		IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16                                          \
-		IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1                                  \
-		IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7                              \
-		IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3                                        \
-		IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2                                         \
-		IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3                                        \
-		IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO                                          \
-		IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B                                       \
-		IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21                                          \
-		IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB                               \
-		IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6                              \
-		IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD                                          \
-		IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI                                         \
-		IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO                                           \
-		IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1                                         \
-		IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__GPIO_1_18                                           \
-		IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5                               \
-		IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2                                        \
-		IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1                                         \
-		IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
-#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2                                        \
-		IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO                                          \
-		IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B                                       \
-		IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19                                          \
-		IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB                               \
-		IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4                              \
-		IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK                                          \
-		IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK                                         \
-		IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT                                      \
-		IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN                                           \
-		IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__GPIO_1_20                                           \
-		IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0                                           \
-		IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0                                      \
-		IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK                                          \
-		IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK                                         \
-		IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
-#define _MX6Q_PAD_SD2_CLK__KPP_COL_5                                           \
-		IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
-#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS                                    \
-		IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
-#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9                     \
-		IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CLK__GPIO_1_10                                           \
-		IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1                                           \
-		IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1                                      \
-		IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD                                          \
-		IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI                                         \
-		IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
-#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5                                           \
-		IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
-#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC                                     \
-		IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
-#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10                    \
-		IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CMD__GPIO_1_11                                           \
-		IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3                                        \
-		IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3                                         \
-		IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6                                          \
-		IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
-#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC                                    \
-		IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
-#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11                   \
-		IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12                                          \
-		IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__SJC_DONE                                           \
-		IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3                              \
-		IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
-
-#define  MX6Q_PAD_SD2_DAT1__USDHC2_DAT1                          (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT1__ECSPI5_SS0                           (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2                       (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS                     (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT1__KPP_COL_7                            (_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT1__GPIO_1_14                            (_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT1__CCM_WAIT                             (_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0                (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD2_DAT2__USDHC2_DAT2                          (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT2__ECSPI5_SS1                           (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3                       (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD                      (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT2__KPP_ROW_6                            (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT2__GPIO_1_13                            (_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT2__CCM_STOP                             (_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1                (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD2_DAT0__USDHC2_DAT0                          (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT0__ECSPI5_MISO                          (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD                      (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT0__KPP_ROW_7                            (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT0__GPIO_1_15                            (_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT                       (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2                (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA                      (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC                      (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK                  (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TXC__GPIO_6_19                           (_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0            (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT               (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY              (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0                      (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD0__GPIO_6_20                           (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1            (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG               (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1                      (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD1__GPIO_6_21                           (_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2            (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP                        (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA               (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2                      (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD2__GPIO_6_22                           (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3            (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP                        (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE               (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3                      (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD3__GPIO_6_23                           (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4            (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA                   (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL                (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24                        (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5         (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY              (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0                      (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD0__GPIO_6_25                           (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6            (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE                 (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL                (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26                        (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7         (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT     (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG               (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1                      (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD1__GPIO_6_27                           (_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8            (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD1__SJC_FAIL                            (_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA               (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2                      (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD2__GPIO_6_28                           (_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9            (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE               (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3                      (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD3__GPIO_6_29                           (_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10           (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE                    (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC                      (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RXC__GPIO_6_30                           (_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11           (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25                        (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A25__ECSPI4_SS1                            (_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A25__ECSPI2_RDY                            (_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12                        (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS                        (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A25__GPIO_5_2                              (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE                      (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0               (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2                        (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB2__ECSPI1_SS0                            (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK                       (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19                        (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL                       (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB2__GPIO_2_30                             (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB2__I2C2_SCL                              (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30                         (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16                        (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D16__ECSPI1_SCLK                           (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5                         (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18                        (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA                       (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D16__GPIO_3_16                             (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D16__I2C2_SDA                              (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17                        (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D17__ECSPI1_MISO                           (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6                         (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK                      (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT                        (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D17__GPIO_3_17                             (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D17__I2C3_SCL                              (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1               (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18                        (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D18__ECSPI1_MOSI                           (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7                         (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17                        (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS                        (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D18__GPIO_3_18                             (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D18__I2C3_SDA                              (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2               (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19                        (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D19__ECSPI1_SS1                            (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8                         (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16                        (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D19__UART1_CTS                             (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D19__GPIO_3_19                             (_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D19__EPIT1_EPITO                           (_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP                  (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20                        (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D20__ECSPI4_SS0                            (_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16                        (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15                        (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D20__UART1_CTS                             (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D20__UART1_RTS                             (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D20__GPIO_3_20                             (_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D20__EPIT2_EPITO                           (_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21                        (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D21__ECSPI4_SCLK                           (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17                        (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11                        (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC                      (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D21__GPIO_3_21                             (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D21__I2C1_SCL                              (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D21__SPDIF_IN1                             (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22                        (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D22__ECSPI4_MISO                           (_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1                         (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10                        (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR                     (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D22__GPIO_3_22                             (_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D22__SPDIF_OUT1                            (_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE                 (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23                        (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS                        (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D23__UART3_CTS                             (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D23__UART1_DCD                             (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN                     (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D23__GPIO_3_23                             (_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2                         (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14                        (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3                        (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB3__ECSPI4_RDY                            (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB3__UART3_CTS                             (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB3__UART3_RTS                             (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB3__UART1_RI                              (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC                       (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB3__GPIO_2_31                             (_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3                         (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31                         (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24                        (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D24__ECSPI4_SS2                            (_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D24__UART3_TXD                             (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D24__UART3_RXD                             (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D24__ECSPI1_SS2                            (_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D24__ECSPI2_SS2                            (_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D24__GPIO_3_24                             (_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS                      (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D24__UART1_DTR                             (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25                        (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D25__ECSPI4_SS3                            (_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D25__UART3_TXD                             (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D25__UART3_RXD                             (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D25__ECSPI1_SS3                            (_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D25__ECSPI2_SS3                            (_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D25__GPIO_3_25                             (_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC                       (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D25__UART1_DSR                             (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26                        (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11                        (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1                         (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14                        (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D26__UART2_TXD                             (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D26__UART2_RXD                             (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D26__GPIO_3_26                             (_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D26__IPU1_SISG_2                           (_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22                     (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27                        (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13                        (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0                         (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13                        (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D27__UART2_TXD                             (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D27__UART2_RXD                             (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D27__GPIO_3_27                             (_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D27__IPU1_SISG_3                           (_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23                     (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28                        (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D28__I2C1_SDA                              (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D28__ECSPI4_MOSI                           (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12                        (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D28__UART2_CTS                             (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D28__GPIO_3_28                             (_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG                         (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13                        (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29                        (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15                        (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D29__ECSPI4_SS0                            (_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D29__UART2_CTS                             (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D29__UART2_RTS                             (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D29__GPIO_3_29                             (_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC                       (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14                        (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30                        (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21                     (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11                        (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3                         (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D30__UART3_CTS                             (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D30__GPIO_3_30                             (_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC                       (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0                (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31                        (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20                     (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12                        (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2                         (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D31__UART3_CTS                             (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D31__UART3_RTS                             (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D31__GPIO_3_31                             (_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR                      (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1                (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24                        (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19                     (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19                        (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A24__IPU2_SISG_2                           (_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A24__IPU1_SISG_2                           (_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A24__GPIO_5_4                              (_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2                (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A24__SRC_BT_CFG_24                         (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23                        (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18                     (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18                        (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A23__IPU2_SISG_3                           (_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A23__IPU1_SISG_3                           (_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A23__GPIO_6_6                              (_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3                (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A23__SRC_BT_CFG_23                         (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22                        (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17                     (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17                        (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A22__GPIO_2_16                             (_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A22__TPSMP_HDATA_0                         (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A22__SRC_BT_CFG_22                         (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21                        (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16                     (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16                        (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A21__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18            (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A21__GPIO_2_17                             (_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A21__TPSMP_HDATA_1                         (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A21__SRC_BT_CFG_21                         (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20                        (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15                     (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15                        (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A20__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19            (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A20__GPIO_2_18                             (_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A20__TPSMP_HDATA_2                         (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A20__SRC_BT_CFG_20                         (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19                        (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14                     (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14                        (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A19__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20            (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A19__GPIO_2_19                             (_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A19__TPSMP_HDATA_3                         (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A19__SRC_BT_CFG_19                         (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18                        (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13                     (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13                        (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A18__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21            (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A18__GPIO_2_20                             (_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A18__TPSMP_HDATA_4                         (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A18__SRC_BT_CFG_18                         (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17                        (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12                     (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12                        (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A17__RESERVED_RESERVED                     (_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22            (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A17__GPIO_2_21                             (_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A17__TPSMP_HDATA_5                         (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A17__SRC_BT_CFG_17                         (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16                        (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK                     (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK                      (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23            (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A16__GPIO_2_22                             (_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A16__TPSMP_HDATA_6                         (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_A16__SRC_BT_CFG_16                         (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0                        (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5                         (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS0__ECSPI2_SCLK                           (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24            (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS0__GPIO_2_23                             (_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7                         (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1                        (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6                         (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS1__ECSPI2_MOSI                           (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25            (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS1__GPIO_2_24                             (_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8                         (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_OE__WEIM_WEIM_OE                           (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7                          (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_OE__ECSPI2_MISO                            (_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26             (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_OE__GPIO_2_25                              (_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_OE__TPSMP_HDATA_9                          (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_RW__WEIM_WEIM_RW                           (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8                          (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_RW__ECSPI2_SS0                             (_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27             (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_RW__GPIO_2_26                              (_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_RW__TPSMP_HDATA_10                         (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_RW__SRC_BT_CFG_29                          (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA                         (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17                        (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_LBA__ECSPI2_SS1                            (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_LBA__GPIO_2_27                             (_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11                        (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26                         (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0                        (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11                     (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11                        (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0             (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY                          (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB0__GPIO_2_28                             (_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12                        (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27                         (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1                        (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10                     (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10                        (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1             (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB1__GPIO_2_29                             (_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13                        (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28                         (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0                      (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9                      (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9                         (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2             (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA0__GPIO_3_0                              (_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14                        (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0                          (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1                      (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8                      (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8                         (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3             (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE        (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA1__GPIO_3_1                              (_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15                        (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1                          (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2                      (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7                      (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7                         (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4             (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE        (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA2__GPIO_3_2                              (_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16                        (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2                          (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3                      (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6                      (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6                         (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5             (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ            (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA3__GPIO_3_3                              (_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17                        (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3                          (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4                      (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5                      (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5                         (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6             (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN             (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA4__GPIO_3_4                              (_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18                        (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4                          (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5                      (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4                      (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4                         (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7             (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP             (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA5__GPIO_3_5                              (_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19                        (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5                          (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6                      (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3                      (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3                         (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8             (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN             (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA6__GPIO_3_6                              (_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20                        (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6                          (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7                      (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2                      (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2                         (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9             (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA7__GPIO_3_7                              (_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21                        (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7                          (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8                      (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1                      (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1                         (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10            (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA8__GPIO_3_8                              (_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22                        (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8                          (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9                      (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0                      (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0                         (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11            (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA9__GPIO_3_9                              (_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23                        (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9                          (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10                    (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15                       (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN                    (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12           (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA10__GPIO_3_10                            (_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24                       (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10                        (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11                    (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2                        (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC                      (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13           (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6           (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA11__GPIO_3_11                            (_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25                       (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11                        (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12                    (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3                        (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC                      (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14           (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3           (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA12__GPIO_3_12                            (_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26                       (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12                        (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13                    (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS                       (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK                      (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15           (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4           (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA13__GPIO_3_13                            (_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27                       (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13                        (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14                    (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS                       (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK                      (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16           (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5           (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA14__GPIO_3_14                            (_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28                       (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14                        (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15                    (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1                        (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4                        (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17           (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA15__GPIO_3_15                            (_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29                       (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15                        (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT                       (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B                    (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_WAIT__GPIO_5_0                             (_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30                       (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25                        (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK                       (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16                       (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_BCLK__GPIO_6_31                            (_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31                       (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK                (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK                (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28       (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0          (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16                        (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0                (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15                      (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15                      (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC                     (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29          (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1             (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN15__GPIO_4_17                           (_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1                   (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2                        (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2                        (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD                      (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30           (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2              (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN2__GPIO_4_18                            (_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2                    (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9               (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3                        (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3                        (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS                     (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31           (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3              (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN3__GPIO_4_19                            (_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3                    (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10              (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4                        (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4                        (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD                      (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN4__USDHC1_WP                            (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD                     (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN4__GPIO_4_20                            (_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4                    (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11              (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0                   (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0                   (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK                        (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0               (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT0__GPIO_4_21                          (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5                  (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1                   (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1                   (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI                        (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1               (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL       (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT1__GPIO_4_22                          (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6                  (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12            (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2                   (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2                   (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO                        (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2               (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE                    (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT2__GPIO_4_23                          (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7                  (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13            (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3                   (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3                   (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0                         (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3               (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR               (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT3__GPIO_4_24                          (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8                  (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14            (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4                   (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4                   (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1                         (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4               (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB                 (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT4__GPIO_4_25                          (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9                  (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15            (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5                   (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5                   (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2                         (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS                   (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS           (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT5__GPIO_4_26                          (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10                 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16            (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6                   (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6                   (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3                         (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC                    (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE          (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT6__GPIO_4_27                          (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11                 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17            (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7                   (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7                   (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY                         (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5               (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0         (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT7__GPIO_4_28                          (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12                 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18            (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8                   (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8                   (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT8__PWM1_PWMO                          (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B                       (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1         (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT8__GPIO_4_29                          (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13                 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19            (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9                   (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9                   (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT9__PWM2_PWMO                          (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B                       (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2         (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT9__GPIO_4_30                          (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14                 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20            (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10                 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10                 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6              (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3        (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT10__GPIO_4_31                         (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15                (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21           (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11                 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11                 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7              (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4        (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT11__GPIO_5_5                          (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16                (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22           (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12                 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12                 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED                 (_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5        (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT12__GPIO_5_6                          (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17                (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23           (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13                 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13                 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS                  (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0        (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT13__GPIO_5_7                          (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18                (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24           (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14                 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14                 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC                   (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1        (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT14__GPIO_5_8                          (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19                (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15                 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15                 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1                        (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1                        (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2        (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT15__GPIO_5_9                          (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20                (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25           (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16                 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16                 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI                       (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC                   (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0             (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT16__GPIO_5_10                         (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21                (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26           (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17                 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17                 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO                       (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD                   (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1             (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT17__GPIO_5_11                         (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22                (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27           (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18                 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18                 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0                        (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS                  (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS                  (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT18__GPIO_5_12                         (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23                (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2                    (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19                 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19                 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK                       (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD                   (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC                   (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT19__GPIO_5_13                         (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24                (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3                    (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20                 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20                 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK                       (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC                   (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7        (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT20__GPIO_5_14                         (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25                (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28           (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21                 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21                 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI                       (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD                   (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0           (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT21__GPIO_5_15                         (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26                (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29           (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22                 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22                 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO                       (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS                  (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1           (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT22__GPIO_5_16                         (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27                (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30           (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23                 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23                 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0                        (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD                   (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2           (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT23__GPIO_5_17                         (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28                (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31           (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED                   (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDIO__ENET_MDIO                           (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDIO__ESAI1_SCKR                          (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3             (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT                (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDIO__GPIO_1_22                           (_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK                         (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED                (_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK                      (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR                        (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4          (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_REF_CLK__GPIO_1_23                        (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK                      (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH   (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_RX_ER__ENET_RX_ER                         (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR                         (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RX_ER__SPDIF_IN1                          (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT               (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RX_ER__GPIO_1_24                          (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RX_ER__PHY_TDI                            (_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD      (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED                 (_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN                        (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT                        (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK                (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_CRS_DV__GPIO_1_25                         (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_CRS_DV__PHY_TDO                           (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD     (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_RXD1__MLB_MLBSIG                          (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD1__ENET_RDATA_1                        (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD1__ESAI1_FST                           (_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT                (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD1__GPIO_1_26                           (_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD1__PHY_TCK                             (_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET   (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT                      (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD0__ENET_RDATA_0                        (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD0__ESAI1_HCKT                          (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD0__SPDIF_OUT1                          (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD0__GPIO_1_27                           (_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD0__PHY_TMS                             (_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV    (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED                  (_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TX_EN__ENET_TX_EN                         (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2                      (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TX_EN__GPIO_1_28                          (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI                       (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH     (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_TXD1__MLB_MLBCLK                          (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD1__ENET_TDATA_1                        (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3                       (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN                 (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD1__GPIO_1_29                           (_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO                        (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD       (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED                   (_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD0__ENET_TDATA_0                        (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1                       (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD0__GPIO_1_30                           (_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK                        (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD       (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_ENET_MDC__MLB_MLBDAT                           (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDC__ENET_MDC                             (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0                        (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN                  (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDC__GPIO_1_31                            (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDC__SATA_PHY_TMS                         (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET    (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40                       (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41                       (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42                       (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43                       (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44                       (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45                       (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46                       (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47                       (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5                   (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5                     (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32                       (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33                       (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34                       (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35                       (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36                       (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37                       (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38                       (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39                       (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4                     (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4                   (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24                       (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25                       (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26                       (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27                       (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28                       (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29                       (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3                   (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30                       (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31                       (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3                     (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16                       (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17                       (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18                       (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19                       (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20                       (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21                       (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22                       (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2                   (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23                       (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2                     (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0                         (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1                         (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2                         (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3                         (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4                         (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5                         (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6                         (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7                         (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8                         (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9                         (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10                       (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11                       (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12                       (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13                       (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14                       (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15                       (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS                        (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0                       (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1                       (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS                        (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET                    (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0                   (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1                   (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0                 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2                   (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0                 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1                 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1                 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0                   (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1                   (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE                      (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0                         (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1                         (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2                         (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3                         (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4                         (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5                         (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0                   (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6                         (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7                         (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0                     (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8                         (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9                         (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10                       (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11                       (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12                       (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13                       (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14                       (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1                   (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15                       (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1                     (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48                       (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49                       (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50                       (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51                       (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52                       (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53                       (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54                       (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55                       (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6                   (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6                     (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56                       (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7                   (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57                       (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58                       (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59                       (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60                       (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7                     (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61                       (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62                       (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63                       (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_COL0__ECSPI1_SCLK                          (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL0__ENET_RDATA_3                         (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC                      (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL0__KPP_COL_0                            (_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL0__UART4_TXD                            (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL0__UART4_RXD                            (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL0__GPIO_4_6                             (_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT                       (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST                       (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI                          (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW0__ENET_TDATA_3                         (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                      (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW0__KPP_ROW_0                            (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW0__UART4_TXD                            (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW0__UART4_RXD                            (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW0__GPIO_4_7                             (_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT                       (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0               (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_COL1__ECSPI1_MISO                          (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL1__ENET_MDIO                            (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS                     (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL1__KPP_COL_1                            (_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL1__UART5_TXD                            (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL1__UART5_RXD                            (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL1__GPIO_4_8                             (_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL1__USDHC1_VSELECT                       (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1               (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_ROW1__ECSPI1_SS0                           (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW1__ENET_COL                             (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD                      (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW1__KPP_ROW_1                            (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW1__UART5_TXD                            (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW1__UART5_RXD                            (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW1__GPIO_4_9                             (_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT                       (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2               (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_COL2__ECSPI1_SS1                           (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL2__ENET_RDATA_2                         (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL2__CAN1_TXCAN                           (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL2__KPP_COL_2                            (_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL2__ENET_MDC                             (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL2__GPIO_4_10                            (_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP           (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3      (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_ROW2__ECSPI1_SS2                           (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW2__ENET_TDATA_2                         (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW2__CAN1_RXCAN                           (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW2__KPP_ROW_2                            (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT                       (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW2__GPIO_4_11                            (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE                     (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4               (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_COL3__ECSPI1_SS3                           (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL3__ENET_CRS                             (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL                      (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL3__KPP_COL_3                            (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL3__I2C2_SCL                             (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL3__GPIO_4_12                            (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL3__SPDIF_IN1                            (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5               (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT                       (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK                    (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA                      (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW3__KPP_ROW_3                            (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW3__I2C2_SDA                             (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW3__GPIO_4_13                            (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT                       (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6      (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_COL4__CAN2_TXCAN                           (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL4__IPU1_SISG_4                          (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC                     (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL4__KPP_COL_4                            (_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL4__UART5_CTS                            (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL4__UART5_RTS                            (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL4__GPIO_4_14                            (_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49                   (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7      (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_KEY_ROW4__CAN2_RXCAN                           (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW4__IPU1_SISG_5                          (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR                    (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW4__KPP_ROW_4                            (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW4__UART5_CTS                            (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW4__GPIO_4_15                            (_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50                   (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8      (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_0__CCM_CLKO                               (_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_0__KPP_COL_5                              (_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK                      (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_0__EPIT1_EPITO                            (_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_0__GPIO_1_0                               (_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR                       (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5             (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_1__ESAI1_SCKR                             (_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_1__WDOG2_WDOG_B                           (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_1__KPP_ROW_5                              (_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_1__PWM2_PWMO                              (_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_1__GPIO_1_1                               (_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_1__USDHC1_CD                              (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_1__SRC_TESTER_ACK                         (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_9__ESAI1_FSR                              (_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_9__WDOG1_WDOG_B                           (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_9__KPP_COL_6                              (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_9__CCM_REF_EN_B                           (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_9__PWM1_PWMO                              (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_PWM_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_9__GPIO_1_9                               (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
-#define  MX6Q_PAD_GPIO_9__USDHC1_WP                              (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_9__SRC_EARLY_RST                          (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_3__ESAI1_HCKR                             (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0             (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_3__I2C3_SCL                               (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT                  (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_3__CCM_CLKO2                              (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_3__GPIO_1_3                               (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC                        (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_3__MLB_MLBCLK                             (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_6__ESAI1_SCKT                             (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1             (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_6__I2C3_SDA                               (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0                          (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB                        (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_6__GPIO_1_6                               (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_6__USDHC2_LCTL                            (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_6__MLB_MLBSIG                             (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_2__ESAI1_FST                              (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2             (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_2__KPP_ROW_6                              (_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1                          (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0                    (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_2__GPIO_1_2                               (_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_2__USDHC2_WP                              (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_2__MLB_MLBDAT                             (_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_4__ESAI1_HCKT                             (_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3             (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_4__KPP_COL_7                              (_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2                          (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1                    (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_4__GPIO_1_4                               (_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_4__USDHC2_CD                              (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED        (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3                          (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4             (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_5__KPP_ROW_7                              (_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_5__CCM_CLKO                               (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2                    (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_5__GPIO_1_5                               (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_5__I2C3_SCL                               (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_5__CHEETAH_EVENTI                         (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1                          (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_7__ECSPI5_RDY                             (_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_7__EPIT1_EPITO                            (_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_7__CAN1_TXCAN                             (_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_7__UART2_TXD                              (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_7__UART2_RXD                              (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_7__GPIO_1_7                               (_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_7__SPDIF_PLOCK                            (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE                (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0                          (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT                  (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_8__EPIT2_EPITO                            (_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_8__CAN1_RXCAN                             (_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_8__UART2_TXD                              (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_8__UART2_RXD                              (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_8__GPIO_1_8                               (_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_8__SPDIF_SRCLK                            (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP            (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2                         (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN                   (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT          (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_16__USDHC1_LCTL                           (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_16__SPDIF_IN1                             (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_16__GPIO_7_11                             (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_16__I2C3_SDA                              (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_16__SJC_DE_B                              (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_17__ESAI1_TX0                             (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN                   (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_17__CCM_PMIC_RDY                          (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0                 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_17__SPDIF_OUT1                            (_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_17__GPIO_7_12                             (_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_17__SJC_JTAG_ACT                          (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_18__ESAI1_TX1                             (_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_18__ENET_RX_CLK                           (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_18__USDHC3_VSELECT                        (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1                 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK                     (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_18__GPIO_7_13                             (_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL        (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST                        (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_GPIO_19__KPP_COL_5                             (_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT                  (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_19__SPDIF_OUT1                            (_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_19__CCM_CLKO                              (_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_19__ECSPI1_RDY                            (_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_19__GPIO_4_5                              (_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_19__ENET_TX_ER                            (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_GPIO_19__SRC_INT_BOOT                          (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK                  (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12  (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0                   (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18                         (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29                (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO                    (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC                     (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13    (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_MCLK__CCM_CLKO                            (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1                     (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_MCLK__GPIO_5_19                           (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30                  (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL                       (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN                (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0                    (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2                  (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20                        (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31               (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK                    (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC                    (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1                      (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15   (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3                    (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_VSYNC__GPIO_5_21                          (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32                 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0                    (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4                       (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2                       (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK                         (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT4__KPP_COL_5                           (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC                     (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT4__GPIO_5_22                           (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43                  (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1                     (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5                       (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3                       (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI                         (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT5__KPP_ROW_5                           (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD                     (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT5__GPIO_5_23                           (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44                  (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2                     (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6                       (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4                       (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO                         (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT6__KPP_COL_6                           (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS                    (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT6__GPIO_5_24                           (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45                  (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3                     (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7                       (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5                       (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0                          (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT7__KPP_ROW_6                           (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD                     (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT7__GPIO_5_25                           (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46                  (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4                     (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8                       (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6                       (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK                         (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT8__KPP_COL_7                           (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT8__I2C1_SDA                            (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT8__GPIO_5_26                           (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47                  (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5                     (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9                       (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7                       (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI                         (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT9__KPP_ROW_7                           (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT9__I2C1_SCL                            (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT9__GPIO_5_27                           (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48                  (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6                     (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10                     (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC                    (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO                        (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT10__UART1_TXD                          (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT10__UART1_RXD                          (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4                    (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT10__GPIO_5_28                          (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33                 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7                    (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11                     (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS                   (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0                         (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT11__UART1_TXD                          (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT11__UART1_RXD                          (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5                    (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT11__GPIO_5_29                          (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34                 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8                    (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12                     (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8                      (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16   (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT12__UART4_TXD                          (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT12__UART4_RXD                          (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6                    (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT12__GPIO_5_30                          (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35                 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9                    (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13                     (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9                      (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17   (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT13__UART4_TXD                          (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT13__UART4_RXD                          (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7                    (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT13__GPIO_5_31                          (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36                 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10                   (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14                     (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10                     (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18   (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT14__UART5_TXD                          (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT14__UART5_RXD                          (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8                    (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT14__GPIO_6_0                           (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37                 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11                   (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15                     (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11                     (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19   (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT15__UART5_TXD                          (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT15__UART5_RXD                          (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9                    (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT15__GPIO_6_1                           (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38                 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12                   (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16                     (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12                     (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20   (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT16__UART4_CTS                          (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT16__UART4_RTS                          (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10                   (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT16__GPIO_6_2                           (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39                 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13                   (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17                     (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13                     (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21   (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT17__UART4_CTS                          (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11                   (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT17__GPIO_6_3                           (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40                 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14                   (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18                     (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14                     (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22   (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT18__UART5_CTS                          (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT18__UART5_RTS                          (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12                   (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT18__GPIO_6_4                           (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41                 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15                   (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19                     (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15                     (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23   (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT19__UART5_CTS                          (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13                   (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT19__GPIO_6_5                           (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42                 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9              (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_JTAG_TMS__SJC_TMS                              (_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_JTAG_MOD__SJC_MOD                              (_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB                          (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_JTAG_TDI__SJC_TDI                              (_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_JTAG_TCK__SJC_TCK                              (_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_JTAG_TDO__SJC_TDO                              (_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3                     (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2                     (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK                     (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1                     (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0                     (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3                     (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK                     (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2                     (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1                     (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0                     (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1               (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ              (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_POR_B__SRC_POR_B                               (_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1                    (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_RESET_IN_B__SRC_RESET_B                        (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0                    (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_TEST_MODE__TCU_TEST_MODE                       (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7                          (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT7__UART1_TXD                            (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT7__UART1_RXD                            (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24     (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0                 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0                 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT7__GPIO_6_17                            (_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12            (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV     (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6                          (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT6__UART1_TXD                            (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT6__UART1_RXD                            (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25     (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1                 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1                 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT6__GPIO_6_18                            (_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13            (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10               (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5                          (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT5__UART2_TXD                            (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT5__UART2_RXD                            (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26     (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2                 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2                 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT5__GPIO_7_0                             (_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14            (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11               (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4                          (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT4__UART2_TXD                            (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT4__UART2_RXD                            (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27     (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3                 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3                 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT4__GPIO_7_1                             (_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15            (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12               (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_CMD__USDHC3_CMD                            (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CMD__UART2_CTS                             (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CMD__CAN1_TXCAN                            (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4                  (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4                  (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CMD__GPIO_7_2                              (_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16             (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13                (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_CLK__USDHC3_CLK                            (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CLK__UART2_CTS                             (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CLK__UART2_RTS                             (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CLK__CAN1_RXCAN                            (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5                  (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5                  (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CLK__GPIO_7_3                              (_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17             (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14                (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0                          (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT0__UART1_CTS                            (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT0__CAN2_TXCAN                           (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6                 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6                 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT0__GPIO_7_4                             (_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18            (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15               (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1                          (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT1__UART1_CTS                            (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT1__UART1_RTS                            (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT1__CAN2_RXCAN                           (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7                 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7                 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT1__GPIO_7_5                             (_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19            (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0                (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2                          (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28     (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8                 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8                 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT2__GPIO_7_6                             (_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20            (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1                (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3                          (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT3__UART3_CTS                            (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29     (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9                 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9                 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT3__GPIO_7_7                             (_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21            (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2                (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD3_RST__USDHC3_RST                            (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD3_RST__UART3_CTS                             (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_RST__UART3_RTS                             (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30      (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10                 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10                 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_RST__GPIO_7_8                              (_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22             (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3                 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_CLE__RAWNAND_CLE                         (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CLE__IPU2_SISG_4                         (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31    (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11               (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11               (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CLE__GPIO_6_7                            (_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23           (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0                      (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_ALE__RAWNAND_ALE                         (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_ALE__USDHC4_RST                          (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0     (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12               (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12               (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_ALE__GPIO_6_8                            (_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24           (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1                      (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN                     (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5                        (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1    (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13              (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13              (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_WP_B__GPIO_6_9                           (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32         (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0    (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_RB0__RAWNAND_READY0                      (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1                       (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2     (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14               (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14               (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_RB0__GPIO_6_10                           (_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33          (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1     (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N                        (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15               (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15               (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS0__GPIO_6_11                           (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2     (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N                        (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT                      (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT                      (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3     (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS1__GPIO_6_14                           (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT   (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N                        (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS2__IPU1_SISG_0                         (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS2__ESAI1_TX0                           (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE                       (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS2__CCM_CLKO2                           (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS2__GPIO_6_15                           (_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS2__IPU2_SISG_0                         (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N                        (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS3__IPU1_SISG_1                         (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS3__ESAI1_TX1                           (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26                      (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4     (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS3__GPIO_6_16                           (_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS3__IPU2_SISG_1                         (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_CS3__TPSMP_CLK                           (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_CMD__USDHC4_CMD                            (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CMD__RAWNAND_RDN                           (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CMD__UART3_TXD                             (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CMD__UART3_RXD                             (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5       (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CMD__GPIO_7_9                              (_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR                       (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_CLK__USDHC4_CLK                            (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CLK__RAWNAND_WRN                           (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CLK__UART3_TXD                             (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CLK__UART3_RXD                             (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6       (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_CLK__GPIO_7_10                             (_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_D0__RAWNAND_D0                           (_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D0__USDHC1_DAT4                          (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0                (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16                (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16                (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D0__GPIO_2_0                             (_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0                  (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0                  (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_D1__RAWNAND_D1                           (_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D1__USDHC1_DAT5                          (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1                (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17                (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17                (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D1__GPIO_2_1                             (_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1                  (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1                  (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_D2__RAWNAND_D2                           (_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D2__USDHC1_DAT6                          (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2                (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18                (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18                (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D2__GPIO_2_2                             (_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2                  (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2                  (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_D3__RAWNAND_D3                           (_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D3__USDHC1_DAT7                          (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3                (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19                (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19                (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D3__GPIO_2_3                             (_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3                  (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3                  (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_D4__RAWNAND_D4                           (_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D4__USDHC2_DAT4                          (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4                (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20                (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20                (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D4__GPIO_2_4                             (_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4                  (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4                  (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_D5__RAWNAND_D5                           (_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D5__USDHC2_DAT5                          (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5                (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21                (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21                (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D5__GPIO_2_5                             (_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5                  (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5                  (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_D6__RAWNAND_D6                           (_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D6__USDHC2_DAT6                          (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6                (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22                (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22                (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D6__GPIO_2_6                             (_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6                  (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6                  (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_NANDF_D7__RAWNAND_D7                           (_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D7__USDHC2_DAT7                          (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7                (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23                (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23                (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D7__GPIO_2_7                             (_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7                  (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7                  (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_DAT0__RAWNAND_D8                           (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0                          (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT0__RAWNAND_DQS                          (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24                (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24                (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT0__GPIO_2_8                             (_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8                  (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8                  (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_DAT1__RAWNAND_D9                           (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1                          (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT1__PWM3_PWMO                            (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25                (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25                (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT1__GPIO_2_9                             (_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9                  (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9                  (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_DAT2__RAWNAND_D10                          (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2                          (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT2__PWM4_PWMO                            (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26                (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26                (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT2__GPIO_2_10                            (_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10                 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10                 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_DAT3__RAWNAND_D11                          (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3                          (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27                (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27                (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT3__GPIO_2_11                            (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11                 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11                 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_DAT4__RAWNAND_D12                          (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4                          (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT4__UART2_TXD                            (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT4__UART2_RXD                            (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28                (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28                (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT4__GPIO_2_12                            (_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12                 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12                 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_DAT5__RAWNAND_D13                          (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5                          (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT5__UART2_CTS                            (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT5__UART2_RTS                            (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29                (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29                (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT5__GPIO_2_13                            (_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13                 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13                 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_DAT6__RAWNAND_D14                          (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6                          (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT6__UART2_CTS                            (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30                (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30                (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT6__GPIO_2_14                            (_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14                 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14                 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD4_DAT7__RAWNAND_D15                          (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7                          (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT7__UART2_TXD                            (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT7__UART2_RXD                            (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31                (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31                (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT7__GPIO_2_15                            (_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15                 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15                 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD1_DAT1__USDHC1_DAT1                          (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT1__ECSPI5_SS0                           (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT1__PWM3_PWMO                            (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT1__GPT_CAPIN2                           (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7      (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT1__GPIO_1_17                            (_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0                    (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8                (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD1_DAT0__USDHC1_DAT0                          (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT0__ECSPI5_MISO                          (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS             (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT0__GPT_CAPIN1                           (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8      (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT0__GPIO_1_16                            (_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1                    (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7                (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD1_DAT3__USDHC1_DAT3                          (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT3__ECSPI5_SS2                           (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3                          (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT3__PWM1_PWMO                            (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B                         (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT3__GPIO_1_21                            (_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB                 (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6                (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD1_CMD__USDHC1_CMD                            (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CMD__ECSPI5_MOSI                           (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CMD__PWM4_PWMO                             (_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CMD__GPT_CMPOUT1                           (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CMD__GPIO_1_18                             (_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5                 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD1_DAT2__USDHC1_DAT2                          (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT2__ECSPI5_SS1                           (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2                          (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT2__PWM2_PWMO                            (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B                         (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT2__GPIO_1_19                            (_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB                 (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4                (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD1_CLK__USDHC1_CLK                            (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CLK__ECSPI5_SCLK                           (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT                        (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CLK__GPT_CLKIN                             (_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CLK__GPIO_1_20                             (_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CLK__PHY_DTB_0                             (_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0                        (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD2_CLK__USDHC2_CLK                            (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CLK__ECSPI5_SCLK                           (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CLK__KPP_COL_5                             (_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS                      (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9       (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CLK__GPIO_1_10                             (_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CLK__PHY_DTB_1                             (_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1                        (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD2_CMD__USDHC2_CMD                            (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CMD__ECSPI5_MOSI                           (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CMD__KPP_ROW_5                             (_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC                       (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10      (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_CMD__GPIO_1_11                             (_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#define  MX6Q_PAD_SD2_DAT3__USDHC2_DAT3                          (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT3__ECSPI5_SS3                           (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT3__KPP_COL_6                            (_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC                      (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11     (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT3__GPIO_1_12                            (_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT3__SJC_DONE                             (_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3                (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx6ul.h b/arch/arm/mach-imx/include/mach/iomux-mx6ul.h
deleted file mode 100644
index b7727191c2..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx6ul.h
+++ /dev/null
@@ -1,1064 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __ASM_ARCH_IMX6UL_PINS_H__
-#define __ASM_ARCH_IMX6UL_PINS_H__
-
-#include <mach/iomux-v3.h>
-
-enum {
-
-	MX6_PAD_BOOT_MODE0__GPIO5_IO10	                        = IOMUX_PAD(0x02A0, 0x0014, 5, 0x0000, 0, 0),
-	MX6_PAD_BOOT_MODE1__GPIO5_IO11	                        = IOMUX_PAD(0x02A4, 0x0018, 5, 0x0000, 0, 0),
-	/*
-	 * The TAMPER Pin can be used for GPIO, which depends on
-	 * fusemap TAMPER_PIN_DISABLE[1:0] settings.
-	 */
-	MX6_PAD_SNVS_TAMPER0__GPIO5_IO00                       = IOMUX_PAD(0x02A8, 0x001C, 5, 0x0000, 0, 0),
-	MX6_PAD_SNVS_TAMPER1__GPIO5_IO01                       = IOMUX_PAD(0x02AC, 0x0020, 5, 0x0000, 0, 0),
-	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02                       = IOMUX_PAD(0x02B0, 0x0024, 5, 0x0000, 0, 0),
-	MX6_PAD_SNVS_TAMPER3__GPIO5_IO03                       = IOMUX_PAD(0x02B4, 0x0028, 5, 0x0000, 0, 0),
-	MX6_PAD_SNVS_TAMPER4__GPIO5_IO04                       = IOMUX_PAD(0x02B8, 0x002C, 5, 0x0000, 0, 0),
-	MX6_PAD_SNVS_TAMPER5__GPIO5_IO05                       = IOMUX_PAD(0x02BC, 0x0030, 5, 0x0000, 0, 0),
-	MX6_PAD_SNVS_TAMPER6__GPIO5_IO06                       = IOMUX_PAD(0x02C0, 0x0034, 5, 0x0000, 0, 0),
-	MX6_PAD_SNVS_TAMPER7__GPIO5_IO07                       = IOMUX_PAD(0x02C4, 0x0038, 5, 0x0000, 0, 0),
-	MX6_PAD_SNVS_TAMPER8__GPIO5_IO08                       = IOMUX_PAD(0x02C8, 0x003C, 5, 0x0000, 0, 0),
-	MX6_PAD_SNVS_TAMPER9__GPIO5_IO09                       = IOMUX_PAD(0x02CC, 0x0040, 5, 0x0000, 0, 0),
-
-	MX6_PAD_JTAG_MOD__SJC_MOD                              = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_MOD__GPT2_CLK                             = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0),
-	MX6_PAD_JTAG_MOD__SPDIF_OUT                            = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0),
-	MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M                    = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0),
-	MX6_PAD_JTAG_MOD__CCM_PMIC_RDY                         = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0),
-	MX6_PAD_JTAG_MOD__GPIO1_IO10                           = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0),
-	MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00                     = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0),
-
-	MX6_PAD_JTAG_TMS__SJC_TMS                              = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TMS__GPT2_CAPTURE1                        = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0),
-	MX6_PAD_JTAG_TMS__SAI2_MCLK                            = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0),
-	MX6_PAD_JTAG_TMS__CCM_CLKO1                            = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TMS__CCM_WAIT                             = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TMS__GPIO1_IO11                           = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01                     = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0),
-	MX6_PAD_JTAG_TMS__EPIT1_OUT                            = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0),
-
-	MX6_PAD_JTAG_TDO__SJC_TDO                              = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDO__GPT2_CAPTURE2                        = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0),
-	MX6_PAD_JTAG_TDO__SAI2_TX_SYNC                         = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0),
-	MX6_PAD_JTAG_TDO__CCM_CLKO2                            = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDO__CCM_STOP                             = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDO__GPIO1_IO12                           = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDO__MQS_RIGHT                            = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDO__EPIT2_OUT                            = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0),
-
-	MX6_PAD_JTAG_TDI__SJC_TDI                              = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDI__GPT2_COMPARE1                        = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDI__SAI2_TX_BCLK                         = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0),
-	MX6_PAD_JTAG_TDI__PWM6_OUT                             = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDI__GPIO1_IO13                           = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDI__MQS_LEFT                             = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL                      = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0),
-
-	MX6_PAD_JTAG_TCK__SJC_TCK                              = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TCK__GPT2_COMPARE2                        = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TCK__SAI2_RX_DATA                         = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0),
-	MX6_PAD_JTAG_TCK__PWM7_OUT                             = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TCK__GPIO1_IO14                           = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL                      = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0),
-
-	MX6_PAD_JTAG_TRST_B__SJC_TRSTB                         = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3                     = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA                      = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TRST_B__PWM8_OUT                          = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TRST_B__GPIO1_IO15                        = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS                  = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0),
-
-	MX6_PAD_GPIO1_IO00__I2C2_SCL                           = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0),
-	MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1                      = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0),
-	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID                     = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0),
-	MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1                     = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0),
-	MX6_PAD_GPIO1_IO00__MQS_RIGHT                          = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO00__GPIO1_IO00                         = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN               = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET                   = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B                       = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0),
-
-	MX6_PAD_GPIO1_IO01__I2C2_SDA                           = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0),
-	MX6_PAD_GPIO1_IO01__GPT1_COMPARE1                      = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO01__USB_OTG1_OC                        = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0),
-	MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2                     = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0),
-	MX6_PAD_GPIO1_IO01__MQS_LEFT                           = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO01__GPIO1_IO01                         = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT              = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET                    = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B                       = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0),
-
-	MX6_PAD_GPIO1_IO02__I2C1_SCL                           = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0),
-	MX6_PAD_GPIO1_IO02__GPT1_COMPARE2                      = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO02__USB_OTG2_PWR                       = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M                  = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO02__USDHC1_WP                          = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0),
-	MX6_PAD_GPIO1_IO02__GPIO1_IO02                         = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00                   = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0),
-	MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET                   = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO02__UART1_DCE_TX                       = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO02__UART1_DTE_RX                       = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0),
-
-	MX6_PAD_GPIO1_IO03__I2C1_SDA                           = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0),
-	MX6_PAD_GPIO1_IO03__GPT1_COMPARE3                      = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO03__USB_OTG2_OC                        = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0),
-	MX6_PAD_GPIO1_IO03__USDHC1_CD_B                        = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0),
-	MX6_PAD_GPIO1_IO03__GPIO1_IO03                         = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK                    = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK                     = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO03__UART1_DCE_RX                       = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0),
-	MX6_PAD_GPIO1_IO03__UART1_DTE_TX                       = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0),
-
-	MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1                     = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0),
-	MX6_PAD_GPIO1_IO04__PWM3_OUT                           = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO04__USB_OTG1_PWR                       = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO04__USDHC1_RESET_B                     = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO04__GPIO1_IO04                         = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN               = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO04__UART5_DCE_TX                       = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO04__UART5_DTE_RX                       = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0),
-
-	MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2                     = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0),
-	MX6_PAD_GPIO1_IO05__PWM4_OUT                           = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID                     = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0),
-	MX6_PAD_GPIO1_IO05__CSI_FIELD                          = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0),
-	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT                     = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO05__GPIO1_IO05                         = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT              = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO05__UART5_DCE_RX                       = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0),
-	MX6_PAD_GPIO1_IO05__UART5_DTE_TX                       = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0),
-
-	MX6_PAD_GPIO1_IO06__ENET1_MDIO                         = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0),
-	MX6_PAD_GPIO1_IO06__ENET2_MDIO                         = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0),
-	MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE                   = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO06__CSI_MCLK                           = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO06__USDHC2_WP                          = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0),
-	MX6_PAD_GPIO1_IO06__GPIO1_IO06                         = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO06__CCM_WAIT                           = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO06__CCM_REF_EN_B                       = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO06__UART1_DCE_CTS                      = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO06__UART1_DTE_RTS                      = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0),
-
-	MX6_PAD_GPIO1_IO07__ENET1_MDC                          = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO07__ENET2_MDC                          = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE                  = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO07__CSI_PIXCLK                         = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0),
-	MX6_PAD_GPIO1_IO07__USDHC2_CD_B                        = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0),
-	MX6_PAD_GPIO1_IO07__GPIO1_IO07                         = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO07__CCM_STOP                           = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO07__UART1_DCE_RTS                      = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0),
-	MX6_PAD_GPIO1_IO07__UART1_DTE_CTS                      = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0),
-
-	MX6_PAD_GPIO1_IO08__PWM1_OUT                           = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B                       = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO08__SPDIF_OUT                          = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO08__CSI_VSYNC                          = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0),
-	MX6_PAD_GPIO1_IO08__USDHC2_VSELECT                     = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO08__GPIO1_IO08                         = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY                       = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0),
-	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS                      = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0),
-	MX6_PAD_GPIO1_IO08__UART5_DTE_CTS                      = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0),
-
-	MX6_PAD_GPIO1_IO09__PWM2_OUT                           = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO09__SPDIF_IN                           = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0),
-	MX6_PAD_GPIO1_IO09__CSI_HSYNC                          = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0),
-	MX6_PAD_GPIO1_IO09__USDHC2_RESET_B                     = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO09__GPIO1_IO09                         = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO09__USDHC1_RESET_B                     = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS                      = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0),
-	MX6_PAD_GPIO1_IO09__UART5_DTE_RTS                      = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0),
-
-	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX                    = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0),
-
-	MX6_PAD_UART1_TX_DATA__UART1_DTE_RX                    = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0),
-	MX6_PAD_UART1_TX_DATA__ENET1_RDATA02                   = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0),
-	MX6_PAD_UART1_TX_DATA__I2C3_SCL                        = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0),
-	MX6_PAD_UART1_TX_DATA__CSI_DATA02                      = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0),
-	MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1                   = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0),
-	MX6_PAD_UART1_TX_DATA__GPIO1_IO16                      = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0),
-	MX6_PAD_UART1_TX_DATA__SPDIF_OUT                       = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0),
-
-	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX                    = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0),
-
-	MX6_PAD_UART1_RX_DATA__UART1_DTE_TX                    = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0),
-	MX6_PAD_UART1_RX_DATA__ENET1_RDATA03                   = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0),
-	MX6_PAD_UART1_RX_DATA__I2C3_SDA                        = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0),
-	MX6_PAD_UART1_RX_DATA__CSI_DATA03                      = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0),
-	MX6_PAD_UART1_RX_DATA__GPT1_CLK                        = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0),
-	MX6_PAD_UART1_RX_DATA__GPIO1_IO17                      = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0),
-	MX6_PAD_UART1_RX_DATA__SPDIF_IN                        = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0),
-
-	MX6_PAD_UART1_CTS_B__UART1_DCE_CTS                     = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0),
-
-	MX6_PAD_UART1_CTS_B__UART1_DTE_RTS                     = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0),
-	MX6_PAD_UART1_CTS_B__ENET1_RX_CLK                      = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0),
-	MX6_PAD_UART1_CTS_B__USDHC1_WP                         = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0),
-	MX6_PAD_UART1_CTS_B__CSI_DATA04                        = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0),
-	MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN              = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0),
-	MX6_PAD_UART1_CTS_B__GPIO1_IO18                        = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0),
-	MX6_PAD_UART1_CTS_B__USDHC2_WP                         = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0),
-
-	MX6_PAD_UART1_RTS_B__UART1_DCE_RTS                     = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0),
-
-	MX6_PAD_UART1_RTS_B__UART1_DTE_CTS                     = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0),
-	MX6_PAD_UART1_RTS_B__ENET1_TX_ER                       = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0),
-	MX6_PAD_UART1_RTS_B__USDHC1_CD_B                       = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0),
-	MX6_PAD_UART1_RTS_B__CSI_DATA05                        = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0),
-	MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT             = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0),
-	MX6_PAD_UART1_RTS_B__GPIO1_IO19                        = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0),
-	MX6_PAD_UART1_RTS_B__USDHC2_CD_B                       = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0),
-
-	MX6_PAD_UART2_TX_DATA__UART2_DCE_TX                    = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0),
-
-	MX6_PAD_UART2_TX_DATA__UART2_DTE_RX                    = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0),
-	MX6_PAD_UART2_TX_DATA__ENET1_TDATA02                   = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0),
-	MX6_PAD_UART2_TX_DATA__I2C4_SCL                        = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0),
-	MX6_PAD_UART2_TX_DATA__CSI_DATA06                      = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0),
-	MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1                   = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0),
-	MX6_PAD_UART2_TX_DATA__GPIO1_IO20                      = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0),
-	MX6_PAD_UART2_TX_DATA__ECSPI3_SS0                      = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0),
-
-	MX6_PAD_UART2_RX_DATA__UART2_DCE_RX                    = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0),
-
-	MX6_PAD_UART2_RX_DATA__UART2_DTE_TX                    = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0),
-	MX6_PAD_UART2_RX_DATA__ENET1_TDATA03                   = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0),
-	MX6_PAD_UART2_RX_DATA__I2C4_SDA                        = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0),
-	MX6_PAD_UART2_RX_DATA__CSI_DATA07                      = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0),
-	MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2                   = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0),
-	MX6_PAD_UART2_RX_DATA__GPIO1_IO21                      = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0),
-	MX6_PAD_UART2_RX_DATA__SJC_DONE                        = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0),
-	MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK                     = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0),
-
-	MX6_PAD_UART2_CTS_B__UART2_DCE_CTS                     = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0),
-
-	MX6_PAD_UART2_CTS_B__UART2_DTE_RTS                     = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0),
-	MX6_PAD_UART2_CTS_B__ENET1_CRS                         = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0),
-	MX6_PAD_UART2_CTS_B__FLEXCAN2_TX                       = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0),
-	MX6_PAD_UART2_CTS_B__CSI_DATA08                        = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0),
-	MX6_PAD_UART2_CTS_B__GPT1_COMPARE2                     = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0),
-	MX6_PAD_UART2_CTS_B__GPIO1_IO22                        = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0),
-	MX6_PAD_UART2_CTS_B__SJC_DE_B                          = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0),
-	MX6_PAD_UART2_CTS_B__ECSPI3_MOSI                       = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0),
-
-	MX6_PAD_UART2_RTS_B__UART2_DCE_RTS                     = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0),
-
-	MX6_PAD_UART2_RTS_B__UART2_DTE_CTS                     = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0),
-	MX6_PAD_UART2_RTS_B__ENET1_COL                         = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0),
-	MX6_PAD_UART2_RTS_B__FLEXCAN2_RX                       = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0),
-	MX6_PAD_UART2_RTS_B__CSI_DATA09                        = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0),
-	MX6_PAD_UART2_RTS_B__GPT1_COMPARE3                     = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0),
-	MX6_PAD_UART2_RTS_B__GPIO1_IO23                        = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0),
-	MX6_PAD_UART2_RTS_B__SJC_FAIL                          = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0),
-	MX6_PAD_UART2_RTS_B__ECSPI3_MISO                       = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0),
-
-	MX6_PAD_UART3_TX_DATA__UART3_DCE_TX                    = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0),
-
-	MX6_PAD_UART3_TX_DATA__UART3_DTE_RX                    = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0),
-	MX6_PAD_UART3_TX_DATA__ENET2_RDATA02                   = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0),
-	MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD                   = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0),
-	MX6_PAD_UART3_TX_DATA__CSI_DATA01                      = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0),
-	MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS                   = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0),
-	MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS                   = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0),
-	MX6_PAD_UART3_TX_DATA__GPIO1_IO24                      = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0),
-	MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT                    = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0),
-	MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID                  = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0),
-
-	MX6_PAD_UART3_RX_DATA__UART3_DCE_RX                    = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0),
-
-	MX6_PAD_UART3_RX_DATA__UART3_DTE_TX                    = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0),
-	MX6_PAD_UART3_RX_DATA__ENET2_RDATA03                   = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0),
-	MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD                   = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0),
-	MX6_PAD_UART3_RX_DATA__CSI_DATA00                      = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0),
-	MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS                   = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0),
-	MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS                   = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0),
-	MX6_PAD_UART3_RX_DATA__GPIO1_IO25                      = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0),
-	MX6_PAD_UART3_RX_DATA__EPIT1_OUT                       = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0),
-
-	MX6_PAD_UART3_CTS_B__UART3_DCE_CTS                     = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0),
-
-	MX6_PAD_UART3_CTS_B__UART3_DTE_RTS                     = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0),
-	MX6_PAD_UART3_CTS_B__ENET2_RX_CLK                      = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
-	MX6_PAD_UART3_CTS_B__FLEXCAN1_TX                       = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0),
-	MX6_PAD_UART3_CTS_B__CSI_DATA10                        = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0),
-	MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN              = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0),
-	MX6_PAD_UART3_CTS_B__GPIO1_IO26                        = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0),
-	MX6_PAD_UART3_CTS_B__EPIT2_OUT                         = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0),
-
-	MX6_PAD_UART3_RTS_B__UART3_DCE_RTS                     = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0),
-
-	MX6_PAD_UART3_RTS_B__UART3_DTE_CTS                     = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0),
-	MX6_PAD_UART3_RTS_B__ENET2_TX_ER                       = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0),
-	MX6_PAD_UART3_RTS_B__FLEXCAN1_RX                       = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0),
-	MX6_PAD_UART3_RTS_B__CSI_DATA11                        = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0),
-	MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT             = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0),
-	MX6_PAD_UART3_RTS_B__GPIO1_IO27                        = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0),
-	MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B                      = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0),
-
-	MX6_PAD_UART4_TX_DATA__UART4_DCE_TX                    = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0),
-
-	MX6_PAD_UART4_TX_DATA__UART4_DTE_RX                    = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0),
-	MX6_PAD_UART4_TX_DATA__ENET2_TDATA02                   = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0),
-	MX6_PAD_UART4_TX_DATA__I2C1_SCL                        = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0),
-	MX6_PAD_UART4_TX_DATA__CSI_DATA12                      = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0),
-	MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02             = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0),
-	MX6_PAD_UART4_TX_DATA__GPIO1_IO28                      = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0),
-	MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK                     = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0),
-
-	MX6_PAD_UART4_RX_DATA__UART4_DCE_RX                    = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0),
-
-	MX6_PAD_UART4_RX_DATA__UART4_DTE_TX                    = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0),
-	MX6_PAD_UART4_RX_DATA__ENET2_TDATA03                   = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0),
-	MX6_PAD_UART4_RX_DATA__I2C1_SDA                        = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0),
-	MX6_PAD_UART4_RX_DATA__CSI_DATA13                      = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0),
-	MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01             = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0),
-	MX6_PAD_UART4_RX_DATA__GPIO1_IO29                      = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0),
-	MX6_PAD_UART4_RX_DATA__ECSPI2_SS0                      = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0),
-	MX6_PAD_UART5_TX_DATA__GPIO1_IO30                      = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0),
-	MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI                     = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0),
-
-	MX6_PAD_UART5_TX_DATA__UART5_DCE_TX                    = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0),
-
-	MX6_PAD_UART5_TX_DATA__UART5_DTE_RX                    = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0),
-	MX6_PAD_UART5_TX_DATA__ENET2_CRS                       = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0),
-	MX6_PAD_UART5_TX_DATA__I2C2_SCL                        = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0),
-	MX6_PAD_UART5_TX_DATA__CSI_DATA14                      = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0),
-	MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00             = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0),
-
-	MX6_PAD_UART5_RX_DATA__UART5_DCE_RX                    = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 5, 0),
-
-	MX6_PAD_UART5_RX_DATA__UART5_DTE_TX                    = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0),
-	MX6_PAD_UART5_RX_DATA__ENET2_COL                       = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0),
-	MX6_PAD_UART5_RX_DATA__I2C2_SDA                        = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0),
-	MX6_PAD_UART5_RX_DATA__CSI_DATA15                      = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0),
-	MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB                 = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0),
-	MX6_PAD_UART5_RX_DATA__GPIO1_IO31                      = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0),
-	MX6_PAD_UART5_RX_DATA__ECSPI2_MISO                     = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0),
-
-	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00                  = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS                  = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0),
-	MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS                  = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_DATA0__PWM1_OUT                       = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_DATA0__CSI_DATA16                     = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0),
-	MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX                    = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00                     = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_DATA0__KPP_ROW00                      = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0),
-	MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL                    = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0),
-
-	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01                  = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS                  = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS                  = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0),
-	MX6_PAD_ENET1_RX_DATA1__PWM2_OUT                       = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_DATA1__CSI_DATA17                     = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0),
-	MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX                    = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0),
-	MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01                     = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_DATA1__KPP_COL00                      = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0),
-	MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL                    = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0),
-
-	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN                       = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS                     = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0),
-	MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS                     = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_EN__CSI_DATA18                        = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0),
-	MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX                       = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_EN__GPIO2_IO02                        = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_EN__KPP_ROW01                         = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0),
-	MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT                    = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0),
-
-	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00                  = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS                  = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                  = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0),
-	MX6_PAD_ENET1_TX_DATA0__CSI_DATA19                     = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0),
-	MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX                    = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0),
-	MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03                     = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_DATA0__KPP_COL01                      = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0),
-	MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT                 = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0),
-
-	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01                  = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS                  = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS                  = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0),
-	MX6_PAD_ENET1_TX_DATA1__PWM5_OUT                       = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_DATA1__CSI_DATA20                     = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0),
-	MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO                     = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0),
-	MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04                     = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_DATA1__KPP_ROW02                      = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0),
-	MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB           = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0),
-
-	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN                       = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS                     = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0),
-	MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS                     = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_EN__PWM6_OUT                          = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_EN__CSI_DATA21                        = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0),
-	MX6_PAD_ENET1_TX_EN__ENET2_MDC                         = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_EN__GPIO2_IO05                        = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_EN__KPP_COL02                         = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0),
-	MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB              = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0),
-
-	MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK                     = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS                    = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS                    = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0),
-	MX6_PAD_ENET1_TX_CLK__PWM7_OUT                         = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_CLK__CSI_DATA22                       = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0),
-	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                   = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0),
-	MX6_PAD_ENET1_TX_CLK__GPIO2_IO06                       = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_CLK__KPP_ROW03                        = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET1_TX_CLK__GPT1_CLK                         = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0),
-
-	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER                       = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS                     = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0),
-	MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS                     = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_ER__PWM8_OUT                          = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_ER__CSI_DATA23                        = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0),
-	MX6_PAD_ENET1_RX_ER__EIM_CRE                           = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_ER__GPIO2_IO07                        = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_ER__KPP_COL03                         = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2                     = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0),
-
-	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00                  = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX                   = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX                   = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0),
-	MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD                = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA0__I2C3_SCL                       = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0),
-	MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO                     = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0),
-	MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08                     = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA0__KPP_ROW04                      = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR                   = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0),
-
-	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01                  = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX                   = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0),
-	MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX                   = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK                 = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA1__I2C3_SDA                       = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0),
-	MX6_PAD_ENET2_RX_DATA1__ENET1_MDC                      = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09                     = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA1__KPP_COL04                      = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC                    = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0),
-
-	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN                       = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_EN__UART7_DCE_TX                      = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_EN__UART7_DTE_RX                      = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0),
-	MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B                  = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_EN__I2C4_SCL                          = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0),
-	MX6_PAD_ENET2_RX_EN__EIM_ADDR26                        = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_EN__GPIO2_IO10                        = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_EN__KPP_ROW05                         = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M                 = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0),
-
-	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00                  = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX                   = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0),
-	MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX                   = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN                = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA0__I2C4_SDA                       = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0),
-	MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02                     = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11                     = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA0__KPP_COL05                      = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0),
-
-	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01                  = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX                   = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX                   = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0),
-	MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD                = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK                    = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0),
-	MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03                     = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12                     = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA1__KPP_ROW06                      = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR                   = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0),
-
-	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN                       = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_EN__UART8_DCE_RX                      = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0),
-	MX6_PAD_ENET2_TX_EN__UART8_DTE_TX                      = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK                    = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI                       = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0),
-	MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN                  = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_EN__GPIO2_IO13                        = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_EN__KPP_COL06                         = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_EN__USB_OTG2_OC                       = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0),
-
-	MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK                     = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS                    = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS                    = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0),
-	MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B                 = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO                      = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0),
-	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2                   = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0),
-	MX6_PAD_ENET2_TX_CLK__GPIO2_IO14                       = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_CLK__KPP_ROW07                        = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID                   = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0),
-
-	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER                       = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS                     = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0),
-	MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS                     = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN                   = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_ER__ECSPI4_SS0                        = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0),
-	MX6_PAD_ENET2_RX_ER__EIM_ADDR25                        = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_ER__GPIO2_IO15                        = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_ER__KPP_COL07                         = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY                    = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_CLK__LCDIF_CLK                             = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_CLK__LCDIF_WR_RWN                          = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_CLK__UART4_DCE_TX                          = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0),
-	MX6_PAD_LCD_CLK__UART4_DTE_RX                          = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0),
-	MX6_PAD_LCD_CLK__SAI3_MCLK                             = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0),
-	MX6_PAD_LCD_CLK__EIM_CS2_B                             = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_CLK__GPIO3_IO00                            = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB                  = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE                       = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_ENABLE__LCDIF_RD_E                         = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_ENABLE__UART4_DCE_RX                       = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0),
-	MX6_PAD_LCD_ENABLE__UART4_DTE_TX                       = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0),
-	MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC                       = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0),
-	MX6_PAD_LCD_ENABLE__EIM_CS3_B                          = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_ENABLE__GPIO3_IO01                         = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_ENABLE__ECSPI2_RDY                         = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC                         = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0),
-	MX6_PAD_LCD_HSYNC__LCDIF_RS                            = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_HSYNC__UART4_DCE_CTS                       = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0),
-	MX6_PAD_LCD_HSYNC__UART4_DTE_RTS                       = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0),
-	MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK                        = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0),
-	MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB                = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_HSYNC__GPIO3_IO02                          = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_HSYNC__ECSPI2_SS1                          = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC                         = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_VSYNC__LCDIF_BUSY                          = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0),
-	MX6_PAD_LCD_VSYNC__UART4_DCE_RTS                       = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0),
-	MX6_PAD_LCD_VSYNC__UART4_DTE_CTS                       = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0),
-	MX6_PAD_LCD_VSYNC__SAI3_RX_DATA                        = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0),
-	MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B                        = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_VSYNC__GPIO3_IO03                          = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_VSYNC__ECSPI2_SS2                          = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_RESET__LCDIF_RESET                         = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_RESET__LCDIF_CS                            = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_RESET__CA7_MX6UL_EVENTI                    = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0),
-	MX6_PAD_LCD_RESET__SAI3_TX_DATA                        = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0),
-	MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY                      = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_RESET__GPIO3_IO04                          = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_RESET__ECSPI2_SS3                          = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_DATA00__LCDIF_DATA00                       = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA00__PWM1_OUT                           = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN               = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA00__I2C3_SDA                           = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0),
-	MX6_PAD_LCD_DATA00__GPIO3_IO05                         = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA00__SRC_BT_CFG00                       = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA00__SAI1_MCLK                          = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0),
-
-	MX6_PAD_LCD_DATA01__LCDIF_DATA01                       = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA01__PWM2_OUT                           = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT              = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA01__I2C3_SCL                           = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0),
-	MX6_PAD_LCD_DATA01__GPIO3_IO06                         = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA01__SRC_BT_CFG01                       = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA01__SAI1_TX_SYNC                       = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0),
-
-	MX6_PAD_LCD_DATA02__LCDIF_DATA02                       = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA02__PWM3_OUT                           = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN               = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA02__I2C4_SDA                           = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0),
-	MX6_PAD_LCD_DATA02__GPIO3_IO07                         = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA02__SRC_BT_CFG02                       = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA02__SAI1_TX_BCLK                       = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0),
-
-	MX6_PAD_LCD_DATA03__LCDIF_DATA03                       = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA03__PWM4_OUT                           = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT              = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA03__I2C4_SCL                           = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0),
-	MX6_PAD_LCD_DATA03__GPIO3_IO08                         = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA03__SRC_BT_CFG03                       = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA03__SAI1_RX_DATA                       = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0),
-
-	MX6_PAD_LCD_DATA04__LCDIF_DATA04                       = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA04__UART8_DCE_CTS                      = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA04__UART8_DTE_RTS                      = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0),
-	MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN               = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA04__SPDIF_SR_CLK                       = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA04__GPIO3_IO09                         = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA04__SRC_BT_CFG04                       = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA04__SAI1_TX_DATA                       = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_DATA05__LCDIF_DATA05                       = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA05__UART8_DCE_RTS                      = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0),
-	MX6_PAD_LCD_DATA05__UART8_DTE_CTS                      = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT              = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA05__SPDIF_OUT                          = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA05__GPIO3_IO10                         = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA05__SRC_BT_CFG05                       = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA05__ECSPI1_SS1                         = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_DATA06__LCDIF_DATA06                       = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA06__UART7_DCE_CTS                      = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA06__UART7_DTE_RTS                      = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0),
-	MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN               = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA06__SPDIF_LOCK                         = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA06__GPIO3_IO11                         = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA06__SRC_BT_CFG06                       = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA06__ECSPI1_SS2                         = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_DATA07__LCDIF_DATA07                       = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA07__UART7_DCE_RTS                      = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0),
-	MX6_PAD_LCD_DATA07__UART7_DTE_CTS                      = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT              = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK                      = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0),
-	MX6_PAD_LCD_DATA07__GPIO3_IO12                         = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA07__SRC_BT_CFG07                       = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA07__ECSPI1_SS3                         = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_DATA08__LCDIF_DATA08                       = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA08__SPDIF_IN                           = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0),
-	MX6_PAD_LCD_DATA08__CSI_DATA16                         = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0),
-	MX6_PAD_LCD_DATA08__EIM_DATA00                         = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA08__GPIO3_IO13                         = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA08__SRC_BT_CFG08                       = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA08__FLEXCAN1_TX                        = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_DATA09__LCDIF_DATA09                       = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA09__SAI3_MCLK                          = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0),
-	MX6_PAD_LCD_DATA09__CSI_DATA17                         = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0),
-	MX6_PAD_LCD_DATA09__EIM_DATA01                         = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA09__GPIO3_IO14                         = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA09__SRC_BT_CFG09                       = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA09__FLEXCAN1_RX                        = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0),
-
-	MX6_PAD_LCD_DATA10__LCDIF_DATA10                       = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA10__SAI3_RX_SYNC                       = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA10__CSI_DATA18                         = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0),
-	MX6_PAD_LCD_DATA10__EIM_DATA02                         = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA10__GPIO3_IO15                         = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA10__SRC_BT_CFG10                       = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA10__FLEXCAN2_TX                        = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_DATA11__LCDIF_DATA11                       = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA11__SAI3_RX_BCLK                       = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA11__CSI_DATA19                         = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0),
-	MX6_PAD_LCD_DATA11__EIM_DATA03                         = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA11__GPIO3_IO16                         = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA11__SRC_BT_CFG11                       = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA11__FLEXCAN2_RX                        = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0),
-
-	MX6_PAD_LCD_DATA12__LCDIF_DATA12                       = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA12__SAI3_TX_SYNC                       = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0),
-	MX6_PAD_LCD_DATA12__CSI_DATA20                         = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0),
-	MX6_PAD_LCD_DATA12__EIM_DATA04                         = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA12__GPIO3_IO17                         = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA12__SRC_BT_CFG12                       = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA12__ECSPI1_RDY                         = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_DATA13__LCDIF_DATA13                       = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA13__SAI3_TX_BCLK                       = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0),
-	MX6_PAD_LCD_DATA13__CSI_DATA21                         = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0),
-	MX6_PAD_LCD_DATA13__EIM_DATA05                         = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA13__GPIO3_IO18                         = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA13__SRC_BT_CFG13                       = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA13__USDHC2_RESET_B                     = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0),
-
-	MX6_PAD_LCD_DATA14__LCDIF_DATA14                       = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA14__SAI3_RX_DATA                       = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0),
-	MX6_PAD_LCD_DATA14__CSI_DATA22                         = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0),
-	MX6_PAD_LCD_DATA14__EIM_DATA06                         = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA14__GPIO3_IO19                         = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA14__SRC_BT_CFG14                       = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA14__USDHC2_DATA4                       = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0),
-
-	MX6_PAD_LCD_DATA15__LCDIF_DATA15                       = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA15__SAI3_TX_DATA                       = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA15__CSI_DATA23                         = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0),
-	MX6_PAD_LCD_DATA15__EIM_DATA07                         = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA15__GPIO3_IO20                         = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA15__SRC_BT_CFG15                       = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA15__USDHC2_DATA5                       = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0),
-
-	MX6_PAD_LCD_DATA16__LCDIF_DATA16                       = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA16__UART7_DCE_TX                       = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA16__UART7_DTE_RX                       = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0),
-	MX6_PAD_LCD_DATA16__CSI_DATA01                         = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0),
-	MX6_PAD_LCD_DATA16__EIM_DATA08                         = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA16__GPIO3_IO21                         = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA16__SRC_BT_CFG24                       = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA16__USDHC2_DATA6                       = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0),
-
-	MX6_PAD_LCD_DATA17__LCDIF_DATA17                       = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA17__UART7_DCE_RX                       = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0),
-	MX6_PAD_LCD_DATA17__UART7_DTE_TX                       = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA17__CSI_DATA00                         = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0),
-	MX6_PAD_LCD_DATA17__EIM_DATA09                         = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA17__GPIO3_IO22                         = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA17__SRC_BT_CFG25                       = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA17__USDHC2_DATA7                       = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0),
-
-	MX6_PAD_LCD_DATA18__LCDIF_DATA18                       = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA18__PWM5_OUT                           = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA18__CA7_MX6UL_EVENTO                   = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA18__CSI_DATA10                         = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0),
-	MX6_PAD_LCD_DATA18__EIM_DATA10                         = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA18__GPIO3_IO23                         = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA18__SRC_BT_CFG26                       = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA18__USDHC2_CMD                         = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0),
-	MX6_PAD_LCD_DATA19__EIM_DATA11                         = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA19__GPIO3_IO24                         = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA19__SRC_BT_CFG27                       = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA19__USDHC2_CLK                         = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0),
-
-	MX6_PAD_LCD_DATA19__LCDIF_DATA19                       = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA19__PWM6_OUT                           = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA19__CSI_DATA11                         = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0),
-	MX6_PAD_LCD_DATA20__EIM_DATA12                         = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA20__GPIO3_IO25                         = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA20__SRC_BT_CFG28                       = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA20__USDHC2_DATA0                       = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0),
-
-	MX6_PAD_LCD_DATA20__LCDIF_DATA20                       = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA20__UART8_DCE_TX                       = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA20__UART8_DTE_RX                       = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0),
-	MX6_PAD_LCD_DATA20__ECSPI1_SCLK                        = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0),
-	MX6_PAD_LCD_DATA20__CSI_DATA12                         = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0),
-
-	MX6_PAD_LCD_DATA21__LCDIF_DATA21                       = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA21__UART8_DCE_RX                       = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0),
-	MX6_PAD_LCD_DATA21__UART8_DTE_TX                       = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA21__ECSPI1_SS0                         = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0),
-	MX6_PAD_LCD_DATA21__CSI_DATA13                         = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0),
-	MX6_PAD_LCD_DATA21__EIM_DATA13                         = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA21__GPIO3_IO26                         = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA21__SRC_BT_CFG29                       = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA21__USDHC2_DATA1                       = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0),
-
-	MX6_PAD_LCD_DATA22__LCDIF_DATA22                       = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA22__MQS_RIGHT                          = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA22__ECSPI1_MOSI                        = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0),
-	MX6_PAD_LCD_DATA22__CSI_DATA14                         = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0),
-	MX6_PAD_LCD_DATA22__EIM_DATA14                         = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA22__GPIO3_IO27                         = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA22__SRC_BT_CFG30                       = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA22__USDHC2_DATA2                       = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0),
-
-	MX6_PAD_LCD_DATA23__LCDIF_DATA23                       = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA23__MQS_LEFT                           = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA23__ECSPI1_MISO                        = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0),
-	MX6_PAD_LCD_DATA23__CSI_DATA15                         = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0),
-	MX6_PAD_LCD_DATA23__EIM_DATA15                         = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA23__GPIO3_IO28                         = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA23__SRC_BT_CFG31                       = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0),
-	MX6_PAD_LCD_DATA23__USDHC2_DATA3                       = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0),
-
-	MX6_PAD_NAND_RE_B__RAWNAND_RE_B                        = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_RE_B__USDHC2_CLK                          = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0),
-	MX6_PAD_NAND_RE_B__QSPI_B_SCLK                         = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_RE_B__KPP_ROW00                           = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0),
-	MX6_PAD_NAND_RE_B__EIM_EB_B00                          = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_RE_B__GPIO4_IO00                          = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_RE_B__ECSPI3_SS2                          = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_WE_B__RAWNAND_WE_B                        = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_WE_B__USDHC2_CMD                          = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0),
-	MX6_PAD_NAND_WE_B__QSPI_B_SS0_B                        = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_WE_B__KPP_COL00                           = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0),
-	MX6_PAD_NAND_WE_B__EIM_EB_B01                          = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_WE_B__GPIO4_IO01                          = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_WE_B__ECSPI3_SS3                          = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_DATA00__RAWNAND_DATA00                    = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA00__USDHC2_DATA0                      = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0),
-	MX6_PAD_NAND_DATA00__QSPI_B_SS1_B                      = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA00__KPP_ROW01                         = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0),
-	MX6_PAD_NAND_DATA00__EIM_AD08                          = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA00__GPIO4_IO02                        = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA00__ECSPI4_RDY                        = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_DATA01__RAWNAND_DATA01                    = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA01__USDHC2_DATA1                      = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0),
-	MX6_PAD_NAND_DATA01__QSPI_B_DQS                        = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA01__KPP_COL01                         = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0),
-	MX6_PAD_NAND_DATA01__EIM_AD09                          = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA01__GPIO4_IO03                        = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA01__ECSPI4_SS1                        = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_DATA02__RAWNAND_DATA02                    = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA02__USDHC2_DATA2                      = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0),
-	MX6_PAD_NAND_DATA02__QSPI_B_DATA00                     = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA02__KPP_ROW02                         = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0),
-	MX6_PAD_NAND_DATA02__EIM_AD10                          = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA02__GPIO4_IO04                        = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA02__ECSPI4_SS2                        = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_DATA03__RAWNAND_DATA03                    = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA03__USDHC2_DATA3                      = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0),
-	MX6_PAD_NAND_DATA03__QSPI_B_DATA01                     = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA03__KPP_COL02                         = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0),
-	MX6_PAD_NAND_DATA03__EIM_AD11                          = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA03__GPIO4_IO05                        = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA03__ECSPI4_SS3                        = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_DATA04__RAWNAND_DATA04                    = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA04__USDHC2_DATA4                      = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0),
-	MX6_PAD_NAND_DATA04__QSPI_B_DATA02                     = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA04__ECSPI4_SCLK                       = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0),
-	MX6_PAD_NAND_DATA04__EIM_AD12                          = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA04__GPIO4_IO06                        = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA04__UART2_DCE_TX                      = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA04__UART2_DTE_RX                      = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0),
-
-	MX6_PAD_NAND_DATA05__RAWNAND_DATA05                    = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA05__USDHC2_DATA5                      = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0),
-	MX6_PAD_NAND_DATA05__QSPI_B_DATA03                     = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA05__ECSPI4_MOSI                       = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0),
-	MX6_PAD_NAND_DATA05__EIM_AD13                          = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA05__GPIO4_IO07                        = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA05__UART2_DCE_RX                      = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0),
-	MX6_PAD_NAND_DATA05__UART2_DTE_TX                      = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_DATA06__RAWNAND_DATA06                    = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA06__USDHC2_DATA6                      = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0),
-	MX6_PAD_NAND_DATA06__SAI2_RX_BCLK                      = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA06__ECSPI4_MISO                       = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0),
-	MX6_PAD_NAND_DATA06__EIM_AD14                          = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA06__GPIO4_IO08                        = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA06__UART2_DCE_CTS                     = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA06__UART2_DTE_RTS                     = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0),
-
-	MX6_PAD_NAND_DATA07__RAWNAND_DATA07                    = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA07__USDHC2_DATA7                      = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0),
-	MX6_PAD_NAND_DATA07__QSPI_A_SS1_B                      = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA07__ECSPI4_SS0                        = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0),
-	MX6_PAD_NAND_DATA07__EIM_AD15                          = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA07__GPIO4_IO09                        = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_DATA07__UART2_DCE_RTS                     = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0),
-	MX6_PAD_NAND_DATA07__UART2_DTE_CTS                     = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_ALE__RAWNAND_ALE                          = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_ALE__USDHC2_RESET_B                       = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0),
-	MX6_PAD_NAND_ALE__QSPI_A_DQS                           = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_ALE__PWM3_OUT                             = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0),
-	MX6_PAD_NAND_ALE__EIM_ADDR17                           = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_ALE__GPIO4_IO10                           = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_ALE__ECSPI3_SS1                           = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_WP_B__RAWNAND_WP_B                        = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_WP_B__USDHC1_RESET_B                      = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0),
-	MX6_PAD_NAND_WP_B__QSPI_A_SCLK                         = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_WP_B__PWM4_OUT                            = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0),
-	MX6_PAD_NAND_WP_B__EIM_BCLK                            = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_WP_B__GPIO4_IO11                          = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_WP_B__ECSPI3_RDY                          = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_READY_B__RAWNAND_READY_B                  = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_READY_B__USDHC1_DATA4                     = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0),
-	MX6_PAD_NAND_READY_B__QSPI_A_DATA00                    = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_READY_B__ECSPI3_SS0                       = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0),
-	MX6_PAD_NAND_READY_B__EIM_CS1_B                        = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_READY_B__GPIO4_IO12                       = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_READY_B__UART3_DCE_TX                     = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0),
-	MX6_PAD_NAND_READY_B__UART3_DTE_RX                     = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0),
-
-	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B                      = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE0_B__USDHC1_DATA5                       = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01                      = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE0_B__ECSPI3_SCLK                        = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0),
-	MX6_PAD_NAND_CE0_B__EIM_DTACK_B                        = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE0_B__GPIO4_IO13                         = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE0_B__UART3_DCE_RX                       = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0),
-	MX6_PAD_NAND_CE0_B__UART3_DTE_TX                       = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B                      = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE1_B__USDHC1_DATA6                       = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02                      = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE1_B__ECSPI3_MOSI                        = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0),
-	MX6_PAD_NAND_CE1_B__EIM_ADDR18                         = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE1_B__GPIO4_IO14                         = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE1_B__UART3_DCE_CTS                      = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0),
-	MX6_PAD_NAND_CE1_B__UART3_DTE_RTS                      = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0),
-
-	MX6_PAD_NAND_CLE__RAWNAND_CLE                          = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_CLE__USDHC1_DATA7                         = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0),
-	MX6_PAD_NAND_CLE__QSPI_A_DATA03                        = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_CLE__ECSPI3_MISO                          = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0),
-	MX6_PAD_NAND_CLE__EIM_ADDR16                           = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_CLE__GPIO4_IO15                           = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_CLE__UART3_DCE_RTS                        = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0),
-	MX6_PAD_NAND_CLE__UART3_DTE_CTS                        = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0),
-
-	MX6_PAD_NAND_DQS__RAWNAND_DQS                          = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0),
-	MX6_PAD_NAND_DQS__CSI_FIELD                            = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0),
-	MX6_PAD_NAND_DQS__QSPI_A_SS0_B                         = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0),
-	MX6_PAD_NAND_DQS__PWM5_OUT                             = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0),
-	MX6_PAD_NAND_DQS__EIM_WAIT                             = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0),
-	MX6_PAD_NAND_DQS__GPIO4_IO16                           = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0),
-	MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01                     = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0),
-	MX6_PAD_NAND_DQS__SPDIF_EXT_CLK                        = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0),
-
-	MX6_PAD_SD1_CMD__USDHC1_CMD                            = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__GPT2_COMPARE1                         = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__SAI2_RX_SYNC                          = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__SPDIF_OUT                             = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__EIM_ADDR19                            = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__GPIO2_IO16                            = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00                      = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0),
-	MX6_PAD_SD1_CMD__USB_OTG1_PWR                          = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0),
-
-	MX6_PAD_SD1_CLK__USDHC1_CLK                            = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__GPT2_COMPARE2                         = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__SAI2_MCLK                             = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0),
-	MX6_PAD_SD1_CLK__SPDIF_IN                              = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0),
-	MX6_PAD_SD1_CLK__EIM_ADDR20                            = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__GPIO2_IO17                            = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__USB_OTG1_OC                           = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0),
-
-	MX6_PAD_SD1_DATA0__USDHC1_DATA0                        = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA0__GPT2_COMPARE3                       = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA0__SAI2_TX_SYNC                        = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0),
-	MX6_PAD_SD1_DATA0__FLEXCAN1_TX                         = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA0__EIM_ADDR21                          = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA0__GPIO2_IO18                          = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID                      = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0),
-
-	MX6_PAD_SD1_DATA1__USDHC1_DATA1                        = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA1__GPT2_CLK                            = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0),
-	MX6_PAD_SD1_DATA1__SAI2_TX_BCLK                        = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0),
-	MX6_PAD_SD1_DATA1__FLEXCAN1_RX                         = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0),
-	MX6_PAD_SD1_DATA1__EIM_ADDR22                          = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA1__GPIO2_IO19                          = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA1__USB_OTG2_PWR                        = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0),
-
-	MX6_PAD_SD1_DATA2__USDHC1_DATA2                        = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA2__GPT2_CAPTURE1                       = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0),
-	MX6_PAD_SD1_DATA2__SAI2_RX_DATA                        = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0),
-	MX6_PAD_SD1_DATA2__FLEXCAN2_TX                         = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA2__EIM_ADDR23                          = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA2__GPIO2_IO20                          = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA2__CCM_CLKO1                           = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA2__USB_OTG2_OC                         = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0),
-
-	MX6_PAD_SD1_DATA3__USDHC1_DATA3                        = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA3__GPT2_CAPTURE2                       = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0),
-	MX6_PAD_SD1_DATA3__SAI2_TX_DATA                        = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA3__FLEXCAN2_RX                         = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0),
-	MX6_PAD_SD1_DATA3__EIM_ADDR24                          = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA3__GPIO2_IO21                          = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA3__CCM_CLKO2                           = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID                      = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0),
-
-	MX6_PAD_CSI_MCLK__CSI_MCLK                             = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI_MCLK__USDHC2_CD_B                          = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0),
-	MX6_PAD_CSI_MCLK__RAWNAND_CE2_B                        = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_MCLK__I2C1_SDA                             = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0),
-	MX6_PAD_CSI_MCLK__EIM_CS0_B                            = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_MCLK__GPIO4_IO17                           = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL                    = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI_MCLK__UART6_DCE_TX                         = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0),
-	MX6_PAD_CSI_MCLK__UART6_DTE_RX                         = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0),
-
-	MX6_PAD_CSI_PIXCLK__CSI_PIXCLK                         = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0),
-	MX6_PAD_CSI_PIXCLK__USDHC2_WP                          = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0),
-	MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B                      = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_PIXCLK__I2C1_SCL                           = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0),
-	MX6_PAD_CSI_PIXCLK__EIM_OE                             = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_PIXCLK__GPIO4_IO18                         = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5                      = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI_PIXCLK__UART6_DCE_RX                       = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0),
-	MX6_PAD_CSI_PIXCLK__UART6_DTE_TX                       = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0),
-
-	MX6_PAD_CSI_VSYNC__CSI_VSYNC                           = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0),
-	MX6_PAD_CSI_VSYNC__USDHC2_CLK                          = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0),
-	MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK                      = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_VSYNC__I2C2_SDA                            = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0),
-	MX6_PAD_CSI_VSYNC__EIM_RW                              = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_VSYNC__GPIO4_IO19                          = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_VSYNC__PWM7_OUT                            = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI_VSYNC__UART6_DCE_RTS                       = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0),
-	MX6_PAD_CSI_VSYNC__UART6_DTE_CTS                       = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0),
-
-	MX6_PAD_CSI_HSYNC__CSI_HSYNC                           = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0),
-	MX6_PAD_CSI_HSYNC__USDHC2_CMD                          = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0),
-	MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD                       = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_HSYNC__I2C2_SCL                            = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0),
-	MX6_PAD_CSI_HSYNC__EIM_LBA_B                           = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_HSYNC__GPIO4_IO20                          = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_HSYNC__PWM8_OUT                            = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI_HSYNC__UART6_DCE_CTS                       = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0),
-	MX6_PAD_CSI_HSYNC__UART6_DTE_RTS                       = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0),
-
-	MX6_PAD_CSI_DATA00__CSI_DATA02                         = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0),
-	MX6_PAD_CSI_DATA00__USDHC2_DATA0                       = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0),
-	MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B                   = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA00__ECSPI2_SCLK                        = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0),
-	MX6_PAD_CSI_DATA00__EIM_AD00                           = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA00__GPIO4_IO21                         = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA00__SRC_INT_BOOT                       = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA00__UART5_DCE_TX                       = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA00__UART5_DTE_RX                       = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0),
-
-	MX6_PAD_CSI_DATA01__CSI_DATA03                         = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0),
-	MX6_PAD_CSI_DATA01__USDHC2_DATA1                       = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0),
-	MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN                    = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA01__ECSPI2_SS0                         = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0),
-	MX6_PAD_CSI_DATA01__EIM_AD01                           = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA01__GPIO4_IO22                         = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA01__SAI1_MCLK                          = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0),
-	MX6_PAD_CSI_DATA01__UART5_DCE_RX                       = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0),
-	MX6_PAD_CSI_DATA01__UART5_DTE_TX                       = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0),
-
-	MX6_PAD_CSI_DATA02__CSI_DATA04                         = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0),
-	MX6_PAD_CSI_DATA02__USDHC2_DATA2                       = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0),
-	MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD                    = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA02__ECSPI2_MOSI                        = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0),
-	MX6_PAD_CSI_DATA02__EIM_AD02                           = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA02__GPIO4_IO23                         = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA02__SAI1_RX_SYNC                       = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA02__UART5_DCE_RTS                      = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0),
-	MX6_PAD_CSI_DATA02__UART5_DTE_CTS                      = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0),
-
-	MX6_PAD_CSI_DATA03__CSI_DATA05                         = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0),
-	MX6_PAD_CSI_DATA03__USDHC2_DATA3                       = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0),
-	MX6_PAD_CSI_DATA03__SIM2_PORT1_PD                      = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA03__ECSPI2_MISO                        = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0),
-	MX6_PAD_CSI_DATA03__EIM_AD03                           = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA03__GPIO4_IO24                         = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA03__SAI1_RX_BCLK                       = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA03__UART5_DCE_CTS                      = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA03__UART5_DTE_RTS                      = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0),
-
-	MX6_PAD_CSI_DATA04__CSI_DATA06                         = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0),
-	MX6_PAD_CSI_DATA04__USDHC2_DATA4                       = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0),
-	MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK                     = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA04__ECSPI1_SCLK                        = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0),
-	MX6_PAD_CSI_DATA04__EIM_AD04                           = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA04__GPIO4_IO25                         = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA04__SAI1_TX_SYNC                       = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0),
-	MX6_PAD_CSI_DATA04__USDHC1_WP                          = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0),
-
-	MX6_PAD_CSI_DATA05__CSI_DATA07                         = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0),
-	MX6_PAD_CSI_DATA05__USDHC2_DATA5                       = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0),
-	MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B                   = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA05__ECSPI1_SS0                         = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0),
-	MX6_PAD_CSI_DATA05__EIM_AD05                           = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA05__GPIO4_IO26                         = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA05__SAI1_TX_BCLK                       = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0),
-	MX6_PAD_CSI_DATA05__USDHC1_CD_B                        = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0),
-
-	MX6_PAD_CSI_DATA06__CSI_DATA08                         = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0),
-	MX6_PAD_CSI_DATA06__USDHC2_DATA6                       = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0),
-	MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN                    = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA06__ECSPI1_MOSI                        = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0),
-	MX6_PAD_CSI_DATA06__EIM_AD06                           = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA06__GPIO4_IO27                         = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA06__SAI1_RX_DATA                       = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0),
-	MX6_PAD_CSI_DATA06__USDHC1_RESET_B                     = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0),
-
-	MX6_PAD_CSI_DATA07__CSI_DATA09                         = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0),
-	MX6_PAD_CSI_DATA07__USDHC2_DATA7                       = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0),
-	MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD                    = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA07__ECSPI1_MISO                        = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0),
-	MX6_PAD_CSI_DATA07__EIM_AD07                           = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA07__GPIO4_IO28                         = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA07__SAI1_TX_DATA                       = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI_DATA07__USDHC1_VSELECT                     = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0),
-};
-#endif  /* __ASM_ARCH_IMX6UL_PINS_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx7.h b/arch/arm/mach-imx/include/mach/iomux-mx7.h
deleted file mode 100644
index def9cf4d44..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx7.h
+++ /dev/null
@@ -1,1330 +0,0 @@
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __MACH_IOMUX_IMX7D_H__
-#define __MACH_IOMUX_IMX7D_H__
-
-#include <mach/iomux-v3.h>
-#include <mach/imx7-regs.h>
-
-enum {
-	MX7D_PAD_GPIO1_IO00__GPIO1_IO0                           = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO00__PWM4_OUT				 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B                        = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
-
-	MX7D_PAD_GPIO1_IO01__GPIO1_IO1                           = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO01__PWM1_OUT                            = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3                   = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO01__SAI1_MCLK				 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
-
-	MX7D_PAD_GPIO1_IO02__GPIO1_IO2                           = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO02__PWM2_OUT                            = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1                   = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0),
-	MX7D_PAD_GPIO1_IO02__SAI2_MCLK                           = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO02__CCM_CLKO1                           = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO02__USB_OTG1_ID                         = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 7, 0x0734, 3, 0),
-
-	MX7D_PAD_GPIO1_IO03__GPIO1_IO3                           = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO03__PWM3_OUT                            = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2                   = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 2, 0x0570, 3, 0),
-	MX7D_PAD_GPIO1_IO03__SAI3_MCLK                           = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO03__CCM_CLKO2                           = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO03__USB_OTG2_ID                         = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 7, 0x0730, 3, 0),
-
-	MX7D_PAD_GPIO1_IO04__GPIO1_IO4                           = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO04__USB_OTG1_OC                         = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 1, 0x072C, 1, 0),
-	MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4                       = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 2, 0x0594, 1, 0),
-	MX7D_PAD_GPIO1_IO04__UART5_CTS_B                         = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 3, 0x0710, 4, 0),
-	MX7D_PAD_GPIO1_IO04__I2C1_SCL                            = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D4, 2, 0),
-
-	MX7D_PAD_GPIO1_IO05__GPIO1_IO5                           = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR                        = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5                      = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 2, 0x0598, 1, 0),
-	MX7D_PAD_GPIO1_IO05__UART5_RTS_B                         = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 3, 0x0710, 5, 0),
-	MX7D_PAD_GPIO1_IO05__I2C1_SDA                            = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D8, 2, 0),
-
-	MX7D_PAD_GPIO1_IO06__GPIO1_IO6                           = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO06__USB_OTG2_OC                         = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 1, 0x0728, 1, 0),
-	MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6                      = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 2, 0x059C, 1, 0),
-	MX7D_PAD_GPIO1_IO06__UART5_RX_DATA                       = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 3, 0x0714, 4, 0),
-	MX7D_PAD_GPIO1_IO06__I2C2_SCL                            = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05DC, 2, 0),
-	MX7D_PAD_GPIO1_IO06__CCM_WAIT				 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO06__KPP_ROW4				 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 6, 0x0624, 1, 0),
-
-	MX7D_PAD_GPIO1_IO07__GPIO1_IO7                           = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR                        = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7                      = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 2, 0x05A0, 1, 0),
-	MX7D_PAD_GPIO1_IO07__UART5_TX_DATA                       = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 3, 0x0714, 5, 0),
-	MX7D_PAD_GPIO1_IO07__I2C2_SDA                            = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05E0, 2, 0),
-	MX7D_PAD_GPIO1_IO07__CCM_STOP				 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO07__KPP_COL4				 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 6, 0x0604, 1, 0),
-};
-
-enum {
-	MX7D_PAD_GPIO1_IO08__GPIO1_IO8                           = IOMUX_PAD(0x026C, 0x0014, 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO08__SD1_VSELECT                         = IOMUX_PAD(0x026C, 0x0014, 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B                        = IOMUX_PAD(0x026C, 0x0014, 2, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO08__UART3_DCE_RX                        = IOMUX_PAD(0x026C, 0x0014, 3, 0x0704, 0, 0),
-	MX7D_PAD_GPIO1_IO08__UART3_DTE_TX                        = IOMUX_PAD(0x026C, 0x0014, 3, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO08__I2C3_SCL                            = IOMUX_PAD(0x026C, 0x0014, IOMUX_CONFIG_SION | 4, 0x05E4, 0, 0),
-	MX7D_PAD_GPIO1_IO08__KPP_COL5                            = IOMUX_PAD(0x026C, 0x0014, 6, 0x0608, 0, 0),
-	MX7D_PAD_GPIO1_IO08__PWM1_OUT                            = IOMUX_PAD(0x026C, 0x0014, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_GPIO1_IO09__GPIO1_IO9                           = IOMUX_PAD(0x0270, 0x0018, 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO09__SD1_LCTL                            = IOMUX_PAD(0x0270, 0x0018, 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3                   = IOMUX_PAD(0x0270, 0x0018, 2, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO09__UART3_DCE_TX                        = IOMUX_PAD(0x0270, 0x0018, 3, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO09__UART3_DTE_RX                        = IOMUX_PAD(0x0270, 0x0018, 3, 0x0704, 1, 0),
-	MX7D_PAD_GPIO1_IO09__I2C3_SDA                            = IOMUX_PAD(0x0270, 0x0018, IOMUX_CONFIG_SION | 4, 0x05E8, 0, 0),
-	MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY                      = IOMUX_PAD(0x0270, 0x0018, 5, 0x04F4, 0, 0),
-	MX7D_PAD_GPIO1_IO09__KPP_ROW5                            = IOMUX_PAD(0x0270, 0x0018, 6, 0x0628, 0, 0),
-	MX7D_PAD_GPIO1_IO09__PWM2_OUT                            = IOMUX_PAD(0x0270, 0x0018, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_GPIO1_IO10__GPIO1_IO10                          = IOMUX_PAD(0x0274, 0x001C, 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO10__SD2_LCTL                            = IOMUX_PAD(0x0274, 0x001C, 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO10__ENET1_MDIO                          = IOMUX_PAD(0x0274, 0x001C, 2, 0x0568, 0, 0),
-	MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS                       = IOMUX_PAD(0x0274, 0x001C, 3, 0x0700, 0, 0),
-	MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS                       = IOMUX_PAD(0x0274, 0x001C, 3, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO10__I2C4_SCL                            = IOMUX_PAD(0x0274, 0x001C, IOMUX_CONFIG_SION | 4, 0x05EC, 0, 0),
-	MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA                      = IOMUX_PAD(0x0274, 0x001C, 5, 0x05A4, 0, 0),
-	MX7D_PAD_GPIO1_IO10__KPP_COL6                            = IOMUX_PAD(0x0274, 0x001C, 6, 0x060C, 0, 0),
-	MX7D_PAD_GPIO1_IO10__PWM3_OUT                            = IOMUX_PAD(0x0274, 0x001C, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_GPIO1_IO11__GPIO1_IO11                          = IOMUX_PAD(0x0278, 0x0020, 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO11__SD3_LCTL                            = IOMUX_PAD(0x0278, 0x0020, 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO11__ENET1_MDC                           = IOMUX_PAD(0x0278, 0x0020, 2, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS                       = IOMUX_PAD(0x0278, 0x0020, 3, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS                       = IOMUX_PAD(0x0278, 0x0020, 3, 0x0700, 1, 0),
-	MX7D_PAD_GPIO1_IO11__I2C4_SDA                            = IOMUX_PAD(0x0278, 0x0020, IOMUX_CONFIG_SION | 4, 0x05F0, 0, 0),
-	MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB                      = IOMUX_PAD(0x0278, 0x0020, 5, 0x05A8, 0, 0),
-	MX7D_PAD_GPIO1_IO11__KPP_ROW6                            = IOMUX_PAD(0x0278, 0x0020, 6, 0x062C, 0, 0),
-	MX7D_PAD_GPIO1_IO11__PWM4_OUT                            = IOMUX_PAD(0x0278, 0x0020, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_GPIO1_IO12__GPIO1_IO12                          = IOMUX_PAD(0x027C, 0x0024, 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO12__SD2_VSELECT                         = IOMUX_PAD(0x027C, 0x0024, 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1                   = IOMUX_PAD(0x027C, 0x0024, 2, 0x0564, 0, 0),
-	MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX                         = IOMUX_PAD(0x027C, 0x0024, 3, 0x04DC, 0, 0),
-	MX7D_PAD_GPIO1_IO12__CM4_NMI                             = IOMUX_PAD(0x027C, 0x0024, 4, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1                        = IOMUX_PAD(0x027C, 0x0024, 5, 0x04E4, 0, 0),
-	MX7D_PAD_GPIO1_IO12__SNVS_VIO_5                          = IOMUX_PAD(0x027C, 0x0024, 6, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO12__USB_OTG1_ID                         = IOMUX_PAD(0x027C, 0x0024, 7, 0x0734, 0, 0),
-
-	MX7D_PAD_GPIO1_IO13__GPIO1_IO13                          = IOMUX_PAD(0x0280, 0x0028, 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO13__SD3_VSELECT                         = IOMUX_PAD(0x0280, 0x0028, 1, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2                   = IOMUX_PAD(0x0280, 0x0028, 2, 0x0570, 0, 0),
-	MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX                         = IOMUX_PAD(0x0280, 0x0028, 3, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY                      = IOMUX_PAD(0x0280, 0x0028, 4, 0x04F4, 1, 0),
-	MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2                        = IOMUX_PAD(0x0280, 0x0028, 5, 0x04E8, 0, 0),
-	MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL                      = IOMUX_PAD(0x0280, 0x0028, 6, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO13__USB_OTG2_ID                         = IOMUX_PAD(0x0280, 0x0028, 7, 0x0730, 0, 0),
-
-	MX7D_PAD_GPIO1_IO14__GPIO1_IO14                          = IOMUX_PAD(0x0284, 0x002C, 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO14__SD3_CD_B                            = IOMUX_PAD(0x0284, 0x002C, 1, 0x0738, 0, 0),
-	MX7D_PAD_GPIO1_IO14__ENET2_MDIO                          = IOMUX_PAD(0x0284, 0x002C, 2, 0x0574, 0, 0),
-	MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX                         = IOMUX_PAD(0x0284, 0x002C, 3, 0x04E0, 0, 0),
-	MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B                        = IOMUX_PAD(0x0284, 0x002C, 4, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3                        = IOMUX_PAD(0x0284, 0x002C, 5, 0x04EC, 0, 0),
-	MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0                     = IOMUX_PAD(0x0284, 0x002C, 6, 0x06D8, 0, 0),
-
-	MX7D_PAD_GPIO1_IO15__GPIO1_IO15                          = IOMUX_PAD(0x0288, 0x0030, 0, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO15__SD3_WP                              = IOMUX_PAD(0x0288, 0x0030, 1, 0x073C, 0, 0),
-	MX7D_PAD_GPIO1_IO15__ENET2_MDC                           = IOMUX_PAD(0x0288, 0x0030, 2, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX                         = IOMUX_PAD(0x0288, 0x0030, 3, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B                        = IOMUX_PAD(0x0288, 0x0030, 4, 0x0000, 0, 0),
-	MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4                        = IOMUX_PAD(0x0288, 0x0030, 5, 0x04F0, 0, 0),
-	MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1                     = IOMUX_PAD(0x0288, 0x0030, 6, 0x06DC, 0, 0),
-
-	MX7D_PAD_EPDC_DATA00__EPDC_DATA0                         = IOMUX_PAD(0x02A4, 0x0034, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD                    = IOMUX_PAD(0x02A4, 0x0034, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0                       = IOMUX_PAD(0x02A4, 0x0034, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA00__KPP_ROW3                           = IOMUX_PAD(0x02A4, 0x0034, 3, 0x0620, 0, 0),
-	MX7D_PAD_EPDC_DATA00__EIM_AD0                            = IOMUX_PAD(0x02A4, 0x0034, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA00__GPIO2_IO0                          = IOMUX_PAD(0x02A4, 0x0034, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA00__LCD_DATA0                          = IOMUX_PAD(0x02A4, 0x0034, 6, 0x0638, 0, 0),
-	MX7D_PAD_EPDC_DATA00__LCD_CLK                            = IOMUX_PAD(0x02A4, 0x0034, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA01__EPDC_DATA1                         = IOMUX_PAD(0x02A8, 0x0038, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK                     = IOMUX_PAD(0x02A8, 0x0038, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1                       = IOMUX_PAD(0x02A8, 0x0038, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA01__KPP_COL3                           = IOMUX_PAD(0x02A8, 0x0038, 3, 0x0600, 0, 0),
-	MX7D_PAD_EPDC_DATA01__EIM_AD1                            = IOMUX_PAD(0x02A8, 0x0038, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA01__GPIO2_IO1                          = IOMUX_PAD(0x02A8, 0x0038, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA01__LCD_DATA1                          = IOMUX_PAD(0x02A8, 0x0038, 6, 0x063C, 0, 0),
-	MX7D_PAD_EPDC_DATA01__LCD_ENABLE                         = IOMUX_PAD(0x02A8, 0x0038, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA02__EPDC_DATA2                         = IOMUX_PAD(0x02AC, 0x003C, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B                   = IOMUX_PAD(0x02AC, 0x003C, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2                       = IOMUX_PAD(0x02AC, 0x003C, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA02__KPP_ROW2                           = IOMUX_PAD(0x02AC, 0x003C, 3, 0x061C, 0, 0),
-	MX7D_PAD_EPDC_DATA02__EIM_AD2                            = IOMUX_PAD(0x02AC, 0x003C, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA02__GPIO2_IO2                          = IOMUX_PAD(0x02AC, 0x003C, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA02__LCD_DATA2                          = IOMUX_PAD(0x02AC, 0x003C, 6, 0x0640, 0, 0),
-	MX7D_PAD_EPDC_DATA02__LCD_VSYNC                          = IOMUX_PAD(0x02AC, 0x003C, 7, 0x0698, 0, 0),
-
-	MX7D_PAD_EPDC_DATA03__EPDC_DATA3                         = IOMUX_PAD(0x02B0, 0x0040, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN                    = IOMUX_PAD(0x02B0, 0x0040, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3                       = IOMUX_PAD(0x02B0, 0x0040, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA03__KPP_COL2                           = IOMUX_PAD(0x02B0, 0x0040, 3, 0x05FC, 0, 0),
-	MX7D_PAD_EPDC_DATA03__EIM_AD3                            = IOMUX_PAD(0x02B0, 0x0040, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA03__GPIO2_IO3                          = IOMUX_PAD(0x02B0, 0x0040, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA03__LCD_DATA3                          = IOMUX_PAD(0x02B0, 0x0040, 6, 0x0644, 0, 0),
-	MX7D_PAD_EPDC_DATA03__LCD_HSYNC                          = IOMUX_PAD(0x02B0, 0x0040, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA04__EPDC_DATA4                         = IOMUX_PAD(0x02B4, 0x0044, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD                      = IOMUX_PAD(0x02B4, 0x0044, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA04__QSPI_A_DQS                         = IOMUX_PAD(0x02B4, 0x0044, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA04__KPP_ROW1                           = IOMUX_PAD(0x02B4, 0x0044, 3, 0x0618, 0, 0),
-	MX7D_PAD_EPDC_DATA04__EIM_AD4                            = IOMUX_PAD(0x02B4, 0x0044, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA04__GPIO2_IO4                          = IOMUX_PAD(0x02B4, 0x0044, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA04__LCD_DATA4                          = IOMUX_PAD(0x02B4, 0x0044, 6, 0x0648, 0, 0),
-	MX7D_PAD_EPDC_DATA04__JTAG_FAIL                          = IOMUX_PAD(0x02B4, 0x0044, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA05__EPDC_DATA5                         = IOMUX_PAD(0x02B8, 0x0048, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD                    = IOMUX_PAD(0x02B8, 0x0048, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK                        = IOMUX_PAD(0x02B8, 0x0048, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA05__KPP_COL1                           = IOMUX_PAD(0x02B8, 0x0048, 3, 0x05F8, 0, 0),
-	MX7D_PAD_EPDC_DATA05__EIM_AD5                            = IOMUX_PAD(0x02B8, 0x0048, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA05__GPIO2_IO5                          = IOMUX_PAD(0x02B8, 0x0048, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA05__LCD_DATA5                          = IOMUX_PAD(0x02B8, 0x0048, 6, 0x064C, 0, 0),
-	MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE                        = IOMUX_PAD(0x02B8, 0x0048, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA06__EPDC_DATA6                         = IOMUX_PAD(0x02BC, 0x004C, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK                     = IOMUX_PAD(0x02BC, 0x004C, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B                       = IOMUX_PAD(0x02BC, 0x004C, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA06__KPP_ROW0                           = IOMUX_PAD(0x02BC, 0x004C, 3, 0x0614, 0, 0),
-	MX7D_PAD_EPDC_DATA06__EIM_AD6                            = IOMUX_PAD(0x02BC, 0x004C, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA06__GPIO2_IO6                          = IOMUX_PAD(0x02BC, 0x004C, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA06__LCD_DATA6                          = IOMUX_PAD(0x02BC, 0x004C, 6, 0x0650, 0, 0),
-	MX7D_PAD_EPDC_DATA06__JTAG_DE_B                          = IOMUX_PAD(0x02BC, 0x004C, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA07__EPDC_DATA7                         = IOMUX_PAD(0x02C0, 0x0050, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B                   = IOMUX_PAD(0x02C0, 0x0050, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B                       = IOMUX_PAD(0x02C0, 0x0050, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA07__KPP_COL0                           = IOMUX_PAD(0x02C0, 0x0050, 3, 0x05F4, 0, 0),
-	MX7D_PAD_EPDC_DATA07__EIM_AD7                            = IOMUX_PAD(0x02C0, 0x0050, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA07__GPIO2_IO7                          = IOMUX_PAD(0x02C0, 0x0050, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA07__LCD_DATA7                          = IOMUX_PAD(0x02C0, 0x0050, 6, 0x0654, 0, 0),
-	MX7D_PAD_EPDC_DATA07__JTAG_DONE                          = IOMUX_PAD(0x02C0, 0x0050, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA08__EPDC_DATA8                         = IOMUX_PAD(0x02C4, 0x0054, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD                    = IOMUX_PAD(0x02C4, 0x0054, 1, 0x06E4, 0, 0),
-	MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0                       = IOMUX_PAD(0x02C4, 0x0054, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA08__UART6_DCE_RX                       = IOMUX_PAD(0x02C4, 0x0054, 3, 0x071C, 0, 0),
-	MX7D_PAD_EPDC_DATA08__UART6_DTE_TX                       = IOMUX_PAD(0x02C4, 0x0054, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA08__EIM_OE                             = IOMUX_PAD(0x02C4, 0x0054, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA08__GPIO2_IO8                          = IOMUX_PAD(0x02C4, 0x0054, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA08__LCD_DATA8                          = IOMUX_PAD(0x02C4, 0x0054, 6, 0x0658, 0, 0),
-	MX7D_PAD_EPDC_DATA08__LCD_BUSY                           = IOMUX_PAD(0x02C4, 0x0054, 7, 0x0634, 0, 0),
-	MX7D_PAD_EPDC_DATA08__EPDC_SDCLK                         = IOMUX_PAD(0x02C4, 0x0054, 8, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA09__EPDC_DATA9                         = IOMUX_PAD(0x02C8, 0x0058, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK                     = IOMUX_PAD(0x02C8, 0x0058, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1                       = IOMUX_PAD(0x02C8, 0x0058, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA09__UART6_DCE_TX                       = IOMUX_PAD(0x02C8, 0x0058, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA09__UART6_DTE_RX                       = IOMUX_PAD(0x02C8, 0x0058, 3, 0x071C, 1, 0),
-	MX7D_PAD_EPDC_DATA09__EIM_RW                             = IOMUX_PAD(0x02C8, 0x0058, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA09__GPIO2_IO9                          = IOMUX_PAD(0x02C8, 0x0058, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA09__LCD_DATA9                          = IOMUX_PAD(0x02C8, 0x0058, 6, 0x065C, 0, 0),
-	MX7D_PAD_EPDC_DATA09__LCD_DATA0                          = IOMUX_PAD(0x02C8, 0x0058, 7, 0x0638, 1, 0),
-	MX7D_PAD_EPDC_DATA09__EPDC_SDLE                          = IOMUX_PAD(0x02C8, 0x0058, 8, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA10__EPDC_DATA10                        = IOMUX_PAD(0x02CC, 0x005C, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B                   = IOMUX_PAD(0x02CC, 0x005C, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2                       = IOMUX_PAD(0x02CC, 0x005C, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS                      = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0718, 0, 0),
-	MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS                      = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA10__EIM_CS0_B                          = IOMUX_PAD(0x02CC, 0x005C, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA10__GPIO2_IO10                         = IOMUX_PAD(0x02CC, 0x005C, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA10__LCD_DATA10                         = IOMUX_PAD(0x02CC, 0x005C, 6, 0x0660, 0, 0),
-	MX7D_PAD_EPDC_DATA10__LCD_DATA9                          = IOMUX_PAD(0x02CC, 0x005C, 7, 0x065C, 1, 0),
-	MX7D_PAD_EPDC_DATA10__EPDC_SDOE                          = IOMUX_PAD(0x02CC, 0x005C, 8, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA11__EPDC_DATA11                        = IOMUX_PAD(0x02D0, 0x0060, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN                    = IOMUX_PAD(0x02D0, 0x0060, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3                       = IOMUX_PAD(0x02D0, 0x0060, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS                      = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS                      = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0718, 1, 0),
-	MX7D_PAD_EPDC_DATA11__EIM_BCLK                           = IOMUX_PAD(0x02D0, 0x0060, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA11__GPIO2_IO11                         = IOMUX_PAD(0x02D0, 0x0060, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA11__LCD_DATA11                         = IOMUX_PAD(0x02D0, 0x0060, 6, 0x0664, 0, 0),
-	MX7D_PAD_EPDC_DATA11__LCD_DATA1                          = IOMUX_PAD(0x02D0, 0x0060, 7, 0x063C, 1, 0),
-	MX7D_PAD_EPDC_DATA11__EPDC_SDCE0                         = IOMUX_PAD(0x02D0, 0x0060, 8, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA12__EPDC_DATA12                        = IOMUX_PAD(0x02D4, 0x0064, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD                      = IOMUX_PAD(0x02D4, 0x0064, 1, 0x06E0, 0, 0),
-	MX7D_PAD_EPDC_DATA12__QSPI_B_DQS                         = IOMUX_PAD(0x02D4, 0x0064, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA12__UART7_DCE_RX                       = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0724, 0, 0),
-	MX7D_PAD_EPDC_DATA12__UART7_DTE_TX                       = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA12__EIM_LBA_B                          = IOMUX_PAD(0x02D4, 0x0064, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA12__GPIO2_IO12                         = IOMUX_PAD(0x02D4, 0x0064, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA12__LCD_DATA12                         = IOMUX_PAD(0x02D4, 0x0064, 6, 0x0668, 0, 0),
-	MX7D_PAD_EPDC_DATA12__LCD_DATA21                         = IOMUX_PAD(0x02D4, 0x0064, 7, 0x068C, 0, 0),
-	MX7D_PAD_EPDC_DATA12__EPDC_GDCLK                         = IOMUX_PAD(0x02D4, 0x0064, 8, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA13__EPDC_DATA13                        = IOMUX_PAD(0x02D8, 0x0068, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD                    = IOMUX_PAD(0x02D8, 0x0068, 1, 0x06EC, 0, 0),
-	MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK                        = IOMUX_PAD(0x02D8, 0x0068, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA13__UART7_DCE_TX                       = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA13__UART7_DTE_RX                       = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0724, 1, 0),
-	MX7D_PAD_EPDC_DATA13__EIM_WAIT                           = IOMUX_PAD(0x02D8, 0x0068, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA13__GPIO2_IO13                         = IOMUX_PAD(0x02D8, 0x0068, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA13__LCD_DATA13                         = IOMUX_PAD(0x02D8, 0x0068, 6, 0x066C, 0, 0),
-	MX7D_PAD_EPDC_DATA13__LCD_CS                             = IOMUX_PAD(0x02D8, 0x0068, 7, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA13__EPDC_GDOE                          = IOMUX_PAD(0x02D8, 0x0068, 8, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA14__EPDC_DATA14                        = IOMUX_PAD(0x02DC, 0x006C, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK                     = IOMUX_PAD(0x02DC, 0x006C, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B                       = IOMUX_PAD(0x02DC, 0x006C, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS                      = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0720, 0, 0),
-	MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS                      = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA14__EIM_EB_B0                          = IOMUX_PAD(0x02DC, 0x006C, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA14__GPIO2_IO14                         = IOMUX_PAD(0x02DC, 0x006C, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA14__LCD_DATA14                         = IOMUX_PAD(0x02DC, 0x006C, 6, 0x0670, 0, 0),
-	MX7D_PAD_EPDC_DATA14__LCD_DATA22                         = IOMUX_PAD(0x02DC, 0x006C, 7, 0x0690, 0, 0),
-	MX7D_PAD_EPDC_DATA14__EPDC_GDSP                          = IOMUX_PAD(0x02DC, 0x006C, 8, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_DATA15__EPDC_DATA15                        = IOMUX_PAD(0x02E0, 0x0070, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B                   = IOMUX_PAD(0x02E0, 0x0070, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B                       = IOMUX_PAD(0x02E0, 0x0070, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS                      = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS                      = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0720, 1, 0),
-	MX7D_PAD_EPDC_DATA15__EIM_CS1_B                          = IOMUX_PAD(0x02E0, 0x0070, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA15__GPIO2_IO15                         = IOMUX_PAD(0x02E0, 0x0070, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA15__LCD_DATA15                         = IOMUX_PAD(0x02E0, 0x0070, 6, 0x0674, 0, 0),
-	MX7D_PAD_EPDC_DATA15__LCD_WR_RWN                         = IOMUX_PAD(0x02E0, 0x0070, 7, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM                       = IOMUX_PAD(0x02E0, 0x0070, 8, 0x0000, 0, 0),
-
-	MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK                          = IOMUX_PAD(0x02E4, 0x0074, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN                     = IOMUX_PAD(0x02E4, 0x0074, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0                     = IOMUX_PAD(0x02E4, 0x0074, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCLK__KPP_ROW4                            = IOMUX_PAD(0x02E4, 0x0074, 3, 0x0624, 0, 0),
-	MX7D_PAD_EPDC_SDCLK__EIM_AD10                            = IOMUX_PAD(0x02E4, 0x0074, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCLK__GPIO2_IO16                          = IOMUX_PAD(0x02E4, 0x0074, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCLK__LCD_CLK                             = IOMUX_PAD(0x02E4, 0x0074, 6, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCLK__LCD_DATA20                          = IOMUX_PAD(0x02E4, 0x0074, 7, 0x0688, 0, 0),
-
-	MX7D_PAD_EPDC_SDLE__EPDC_SDLE                            = IOMUX_PAD(0x02E8, 0x0078, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD                        = IOMUX_PAD(0x02E8, 0x0078, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1                      = IOMUX_PAD(0x02E8, 0x0078, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDLE__KPP_COL4                             = IOMUX_PAD(0x02E8, 0x0078, 3, 0x0604, 0, 0),
-	MX7D_PAD_EPDC_SDLE__EIM_AD11                             = IOMUX_PAD(0x02E8, 0x0078, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDLE__GPIO2_IO17                           = IOMUX_PAD(0x02E8, 0x0078, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDLE__LCD_DATA16                           = IOMUX_PAD(0x02E8, 0x0078, 6, 0x0678, 0, 0),
-	MX7D_PAD_EPDC_SDLE__LCD_DATA8                            = IOMUX_PAD(0x02E8, 0x0078, 7, 0x0658, 1, 0),
-
-	MX7D_PAD_EPDC_SDOE__EPDC_SDOE                            = IOMUX_PAD(0x02EC, 0x007C, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0                       = IOMUX_PAD(0x02EC, 0x007C, 1, 0x0584, 0, 0),
-	MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2                      = IOMUX_PAD(0x02EC, 0x007C, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDOE__KPP_COL5                             = IOMUX_PAD(0x02EC, 0x007C, 3, 0x0608, 1, 0),
-	MX7D_PAD_EPDC_SDOE__EIM_AD12                             = IOMUX_PAD(0x02EC, 0x007C, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDOE__GPIO2_IO18                           = IOMUX_PAD(0x02EC, 0x007C, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDOE__LCD_DATA17                           = IOMUX_PAD(0x02EC, 0x007C, 6, 0x067C, 0, 0),
-	MX7D_PAD_EPDC_SDOE__LCD_DATA23                           = IOMUX_PAD(0x02EC, 0x007C, 7, 0x0694, 0, 0),
-
-	MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR                          = IOMUX_PAD(0x02F0, 0x0080, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1                      = IOMUX_PAD(0x02F0, 0x0080, 1, 0x0588, 0, 0),
-	MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3                     = IOMUX_PAD(0x02F0, 0x0080, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDSHR__KPP_ROW5                            = IOMUX_PAD(0x02F0, 0x0080, 3, 0x0628, 1, 0),
-	MX7D_PAD_EPDC_SDSHR__EIM_AD13                            = IOMUX_PAD(0x02F0, 0x0080, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDSHR__GPIO2_IO19                          = IOMUX_PAD(0x02F0, 0x0080, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDSHR__LCD_DATA18                          = IOMUX_PAD(0x02F0, 0x0080, 6, 0x0680, 0, 0),
-	MX7D_PAD_EPDC_SDSHR__LCD_DATA10                          = IOMUX_PAD(0x02F0, 0x0080, 7, 0x0660, 1, 0),
-
-	MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0                          = IOMUX_PAD(0x02F4, 0x0084, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2                      = IOMUX_PAD(0x02F4, 0x0084, 1, 0x058C, 0, 0),
-	MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL                  = IOMUX_PAD(0x02F4, 0x0084, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE0__EIM_AD14                            = IOMUX_PAD(0x02F4, 0x0084, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE0__GPIO2_IO20                          = IOMUX_PAD(0x02F4, 0x0084, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE0__LCD_DATA19                          = IOMUX_PAD(0x02F4, 0x0084, 6, 0x0684, 0, 0),
-	MX7D_PAD_EPDC_SDCE0__LCD_DATA5                           = IOMUX_PAD(0x02F4, 0x0084, 7, 0x064C, 1, 0),
-
-	MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1                          = IOMUX_PAD(0x02F8, 0x0088, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3                      = IOMUX_PAD(0x02F8, 0x0088, 1, 0x0590, 0, 0),
-	MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC                     = IOMUX_PAD(0x02F8, 0x0088, 2, 0x0578, 0, 0),
-	MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER                         = IOMUX_PAD(0x02F8, 0x0088, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE1__EIM_AD15                            = IOMUX_PAD(0x02F8, 0x0088, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE1__GPIO2_IO21                          = IOMUX_PAD(0x02F8, 0x0088, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE1__LCD_DATA20                          = IOMUX_PAD(0x02F8, 0x0088, 6, 0x0688, 1, 0),
-	MX7D_PAD_EPDC_SDCE1__LCD_DATA4                           = IOMUX_PAD(0x02F8, 0x0088, 7, 0x0648, 1, 0),
-
-	MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2                          = IOMUX_PAD(0x02FC, 0x008C, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN                     = IOMUX_PAD(0x02FC, 0x008C, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0                     = IOMUX_PAD(0x02FC, 0x008C, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE2__KPP_COL6                            = IOMUX_PAD(0x02FC, 0x008C, 3, 0x060C, 1, 0),
-	MX7D_PAD_EPDC_SDCE2__EIM_ADDR16                          = IOMUX_PAD(0x02FC, 0x008C, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE2__GPIO2_IO22                          = IOMUX_PAD(0x02FC, 0x008C, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE2__LCD_DATA21                          = IOMUX_PAD(0x02FC, 0x008C, 6, 0x068C, 1, 0),
-	MX7D_PAD_EPDC_SDCE2__LCD_DATA3                           = IOMUX_PAD(0x02FC, 0x008C, 7, 0x0644, 1, 0),
-
-	MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3                          = IOMUX_PAD(0x0300, 0x0090, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD                       = IOMUX_PAD(0x0300, 0x0090, 1, 0x06E8, 0, 0),
-	MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1                     = IOMUX_PAD(0x0300, 0x0090, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE3__KPP_ROW6                            = IOMUX_PAD(0x0300, 0x0090, 3, 0x062C, 1, 0),
-	MX7D_PAD_EPDC_SDCE3__EIM_ADDR17                          = IOMUX_PAD(0x0300, 0x0090, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE3__GPIO2_IO23                          = IOMUX_PAD(0x0300, 0x0090, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_SDCE3__LCD_DATA22                          = IOMUX_PAD(0x0300, 0x0090, 6, 0x0690, 1, 0),
-	MX7D_PAD_EPDC_SDCE3__LCD_DATA2                           = IOMUX_PAD(0x0300, 0x0090, 7, 0x0640, 1, 0),
-
-	MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK                          = IOMUX_PAD(0x0304, 0x0094, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0                      = IOMUX_PAD(0x0304, 0x0094, 1, 0x05AC, 0, 0),
-	MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2                     = IOMUX_PAD(0x0304, 0x0094, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDCLK__KPP_COL7                            = IOMUX_PAD(0x0304, 0x0094, 3, 0x0610, 0, 0),
-	MX7D_PAD_EPDC_GDCLK__EIM_ADDR18                          = IOMUX_PAD(0x0304, 0x0094, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDCLK__GPIO2_IO24                          = IOMUX_PAD(0x0304, 0x0094, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDCLK__LCD_DATA23                          = IOMUX_PAD(0x0304, 0x0094, 6, 0x0694, 1, 0),
-	MX7D_PAD_EPDC_GDCLK__LCD_DATA16                          = IOMUX_PAD(0x0304, 0x0094, 7, 0x0678, 1, 0),
-
-	MX7D_PAD_EPDC_GDOE__EPDC_GDOE                            = IOMUX_PAD(0x0308, 0x0098, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1                       = IOMUX_PAD(0x0308, 0x0098, 1, 0x05B0, 0, 0),
-	MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3                      = IOMUX_PAD(0x0308, 0x0098, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDOE__KPP_ROW7                             = IOMUX_PAD(0x0308, 0x0098, 3, 0x0630, 0, 0),
-	MX7D_PAD_EPDC_GDOE__EIM_ADDR19                           = IOMUX_PAD(0x0308, 0x0098, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDOE__GPIO2_IO25                           = IOMUX_PAD(0x0308, 0x0098, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDOE__LCD_WR_RWN                           = IOMUX_PAD(0x0308, 0x0098, 6, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDOE__LCD_DATA18                           = IOMUX_PAD(0x0308, 0x0098, 7, 0x0680, 1, 0),
-
-	MX7D_PAD_EPDC_GDRL__EPDC_GDRL                            = IOMUX_PAD(0x030C, 0x009C, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2                       = IOMUX_PAD(0x030C, 0x009C, 1, 0x05B4, 0, 0),
-	MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL                   = IOMUX_PAD(0x030C, 0x009C, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDRL__EIM_ADDR20                           = IOMUX_PAD(0x030C, 0x009C, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDRL__GPIO2_IO26                           = IOMUX_PAD(0x030C, 0x009C, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDRL__LCD_RD_E                             = IOMUX_PAD(0x030C, 0x009C, 6, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDRL__LCD_DATA19                           = IOMUX_PAD(0x030C, 0x009C, 7, 0x0684, 1, 0),
-
-	MX7D_PAD_EPDC_GDSP__EPDC_GDSP                            = IOMUX_PAD(0x0310, 0x00A0, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3                       = IOMUX_PAD(0x0310, 0x00A0, 1, 0x05B8, 0, 0),
-	MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC                      = IOMUX_PAD(0x0310, 0x00A0, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDSP__ENET2_TX_ER                          = IOMUX_PAD(0x0310, 0x00A0, 3, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDSP__EIM_ADDR21                           = IOMUX_PAD(0x0310, 0x00A0, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDSP__GPIO2_IO27                           = IOMUX_PAD(0x0310, 0x00A0, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_GDSP__LCD_BUSY                             = IOMUX_PAD(0x0310, 0x00A0, 6, 0x0634, 1, 0),
-	MX7D_PAD_EPDC_GDSP__LCD_DATA17                           = IOMUX_PAD(0x0310, 0x00A0, 7, 0x067C, 1, 0),
-
-	MX7D_PAD_EPDC_BDR0__EPDC_BDR0                            = IOMUX_PAD(0x0314, 0x00A4, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK                         = IOMUX_PAD(0x0314, 0x00A4, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2                    = IOMUX_PAD(0x0314, 0x00A4, 3, 0x0570, 1, 0),
-	MX7D_PAD_EPDC_BDR0__EIM_ADDR22                           = IOMUX_PAD(0x0314, 0x00A4, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR0__GPIO2_IO28                           = IOMUX_PAD(0x0314, 0x00A4, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR0__LCD_CS                               = IOMUX_PAD(0x0314, 0x00A4, 6, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR0__LCD_DATA7                            = IOMUX_PAD(0x0314, 0x00A4, 7, 0x0654, 1, 0),
-
-	MX7D_PAD_EPDC_BDR1__EPDC_BDR1                            = IOMUX_PAD(0x0318, 0x00A8, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN                          = IOMUX_PAD(0x0318, 0x00A8, 1, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK                         = IOMUX_PAD(0x0318, 0x00A8, 2, 0x0578, 1, 0),
-	MX7D_PAD_EPDC_BDR1__EIM_AD8                              = IOMUX_PAD(0x0318, 0x00A8, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR1__GPIO2_IO29                           = IOMUX_PAD(0x0318, 0x00A8, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR1__LCD_ENABLE                           = IOMUX_PAD(0x0318, 0x00A8, 6, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_BDR1__LCD_DATA6                            = IOMUX_PAD(0x0318, 0x00A8, 7, 0x0650, 1, 0),
-
-	MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM                      = IOMUX_PAD(0x031C, 0x00AC, 0, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA                    = IOMUX_PAD(0x031C, 0x00AC, 1, 0x05CC, 0, 0),
-	MX7D_PAD_EPDC_PWR_COM__ENET2_CRS                         = IOMUX_PAD(0x031C, 0x00AC, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_PWR_COM__EIM_AD9                           = IOMUX_PAD(0x031C, 0x00AC, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30                        = IOMUX_PAD(0x031C, 0x00AC, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC                         = IOMUX_PAD(0x031C, 0x00AC, 6, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_PWR_COM__LCD_DATA11                        = IOMUX_PAD(0x031C, 0x00AC, 7, 0x0664, 1, 0),
-
-	MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT                    = IOMUX_PAD(0x0320, 0x00B0, 0, 0x0580, 0, 0),
-	MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB                   = IOMUX_PAD(0x0320, 0x00B0, 1, 0x05D0, 0, 0),
-	MX7D_PAD_EPDC_PWR_STAT__ENET2_COL                        = IOMUX_PAD(0x0320, 0x00B0, 2, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1                        = IOMUX_PAD(0x0320, 0x00B0, 4, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31                       = IOMUX_PAD(0x0320, 0x00B0, 5, 0x0000, 0, 0),
-	MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC                        = IOMUX_PAD(0x0320, 0x00B0, 6, 0x0698, 1, 0),
-	MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12                       = IOMUX_PAD(0x0320, 0x00B0, 7, 0x0668, 1, 0),
-
-	MX7D_PAD_LCD_CLK__LCD_CLK                                = IOMUX_PAD(0x0324, 0x00B4, 0, 0x0000, 0, 0),
-	MX7D_PAD_LCD_CLK__ECSPI4_MISO                            = IOMUX_PAD(0x0324, 0x00B4, 1, 0x0558, 0, 0),
-	MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN                   = IOMUX_PAD(0x0324, 0x00B4, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_CLK__CSI_DATA16                             = IOMUX_PAD(0x0324, 0x00B4, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_CLK__UART2_DCE_RX                           = IOMUX_PAD(0x0324, 0x00B4, 4, 0x06FC, 0, 0),
-	MX7D_PAD_LCD_CLK__UART2_DTE_TX                           = IOMUX_PAD(0x0324, 0x00B4, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_CLK__GPIO3_IO0                              = IOMUX_PAD(0x0324, 0x00B4, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_ENABLE__LCD_ENABLE                          = IOMUX_PAD(0x0328, 0x00B8, 0, 0x0000, 0, 0),
-	MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI                         = IOMUX_PAD(0x0328, 0x00B8, 1, 0x055C, 0, 0),
-	MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN                = IOMUX_PAD(0x0328, 0x00B8, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_ENABLE__CSI_DATA17                          = IOMUX_PAD(0x0328, 0x00B8, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_ENABLE__UART2_DCE_TX                        = IOMUX_PAD(0x0328, 0x00B8, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_ENABLE__UART2_DTE_RX                        = IOMUX_PAD(0x0328, 0x00B8, 4, 0x06FC, 1, 0),
-	MX7D_PAD_LCD_ENABLE__GPIO3_IO1                           = IOMUX_PAD(0x0328, 0x00B8, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_HSYNC__LCD_HSYNC                            = IOMUX_PAD(0x032C, 0x00BC, 0, 0x0000, 0, 0),
-	MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK                          = IOMUX_PAD(0x032C, 0x00BC, 1, 0x0554, 0, 0),
-	MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN                 = IOMUX_PAD(0x032C, 0x00BC, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_HSYNC__CSI_DATA18                           = IOMUX_PAD(0x032C, 0x00BC, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS                        = IOMUX_PAD(0x032C, 0x00BC, 4, 0x06F8, 0, 0),
-	MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS                        = IOMUX_PAD(0x032C, 0x00BC, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_HSYNC__GPIO3_IO2                            = IOMUX_PAD(0x032C, 0x00BC, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_VSYNC__LCD_VSYNC                            = IOMUX_PAD(0x0330, 0x00C0, 0, 0x0698, 2, 0),
-	MX7D_PAD_LCD_VSYNC__ECSPI4_SS0                           = IOMUX_PAD(0x0330, 0x00C0, 1, 0x0560, 0, 0),
-	MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN                 = IOMUX_PAD(0x0330, 0x00C0, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_VSYNC__CSI_DATA19                           = IOMUX_PAD(0x0330, 0x00C0, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS                        = IOMUX_PAD(0x0330, 0x00C0, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS                        = IOMUX_PAD(0x0330, 0x00C0, 4, 0x06F8, 1, 0),
-	MX7D_PAD_LCD_VSYNC__GPIO3_IO3                            = IOMUX_PAD(0x0330, 0x00C0, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_RESET__LCD_RESET                            = IOMUX_PAD(0x0334, 0x00C4, 0, 0x0000, 0, 0),
-	MX7D_PAD_LCD_RESET__GPT1_COMPARE1                        = IOMUX_PAD(0x0334, 0x00C4, 1, 0x0000, 0, 0),
-	MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI                  = IOMUX_PAD(0x0334, 0x00C4, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_RESET__CSI_FIELD                            = IOMUX_PAD(0x0334, 0x00C4, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_RESET__EIM_DTACK_B                          = IOMUX_PAD(0x0334, 0x00C4, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_RESET__GPIO3_IO4                            = IOMUX_PAD(0x0334, 0x00C4, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA00__LCD_DATA0                           = IOMUX_PAD(0x0338, 0x00C8, 0, 0x0638, 2, 0),
-	MX7D_PAD_LCD_DATA00__GPT1_COMPARE2                       = IOMUX_PAD(0x0338, 0x00C8, 1, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA00__CSI_DATA20                          = IOMUX_PAD(0x0338, 0x00C8, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA00__EIM_DATA0                           = IOMUX_PAD(0x0338, 0x00C8, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA00__GPIO3_IO5                           = IOMUX_PAD(0x0338, 0x00C8, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0                       = IOMUX_PAD(0x0338, 0x00C8, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA01__LCD_DATA1                           = IOMUX_PAD(0x033C, 0x00CC, 0, 0x063C, 2, 0),
-	MX7D_PAD_LCD_DATA01__GPT1_COMPARE3                       = IOMUX_PAD(0x033C, 0x00CC, 1, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA01__CSI_DATA21                          = IOMUX_PAD(0x033C, 0x00CC, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA01__EIM_DATA1                           = IOMUX_PAD(0x033C, 0x00CC, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA01__GPIO3_IO6                           = IOMUX_PAD(0x033C, 0x00CC, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1                       = IOMUX_PAD(0x033C, 0x00CC, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA02__LCD_DATA2                           = IOMUX_PAD(0x0340, 0x00D0, 0, 0x0640, 2, 0),
-	MX7D_PAD_LCD_DATA02__GPT1_CLK                            = IOMUX_PAD(0x0340, 0x00D0, 1, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA02__CSI_DATA22                          = IOMUX_PAD(0x0340, 0x00D0, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA02__EIM_DATA2                           = IOMUX_PAD(0x0340, 0x00D0, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA02__GPIO3_IO7                           = IOMUX_PAD(0x0340, 0x00D0, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2                       = IOMUX_PAD(0x0340, 0x00D0, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA03__LCD_DATA3                           = IOMUX_PAD(0x0344, 0x00D4, 0, 0x0644, 2, 0),
-	MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1                       = IOMUX_PAD(0x0344, 0x00D4, 1, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA03__CSI_DATA23                          = IOMUX_PAD(0x0344, 0x00D4, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA03__EIM_DATA3                           = IOMUX_PAD(0x0344, 0x00D4, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA03__GPIO3_IO8                           = IOMUX_PAD(0x0344, 0x00D4, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3                       = IOMUX_PAD(0x0344, 0x00D4, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA04__LCD_DATA4                           = IOMUX_PAD(0x0348, 0x00D8, 0, 0x0648, 2, 0),
-	MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2                       = IOMUX_PAD(0x0348, 0x00D8, 1, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA04__CSI_VSYNC                           = IOMUX_PAD(0x0348, 0x00D8, 3, 0x0520, 0, 0),
-	MX7D_PAD_LCD_DATA04__EIM_DATA4                           = IOMUX_PAD(0x0348, 0x00D8, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA04__GPIO3_IO9                           = IOMUX_PAD(0x0348, 0x00D8, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4                       = IOMUX_PAD(0x0348, 0x00D8, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA05__LCD_DATA5                           = IOMUX_PAD(0x034C, 0x00DC, 0, 0x064C, 2, 0),
-	MX7D_PAD_LCD_DATA05__CSI_HSYNC                           = IOMUX_PAD(0x034C, 0x00DC, 3, 0x0518, 0, 0),
-	MX7D_PAD_LCD_DATA05__EIM_DATA5                           = IOMUX_PAD(0x034C, 0x00DC, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA05__GPIO3_IO10                          = IOMUX_PAD(0x034C, 0x00DC, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5                       = IOMUX_PAD(0x034C, 0x00DC, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA06__LCD_DATA6                           = IOMUX_PAD(0x0350, 0x00E0, 0, 0x0650, 2, 0),
-	MX7D_PAD_LCD_DATA06__CSI_PIXCLK                          = IOMUX_PAD(0x0350, 0x00E0, 3, 0x051C, 0, 0),
-	MX7D_PAD_LCD_DATA06__EIM_DATA6                           = IOMUX_PAD(0x0350, 0x00E0, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA06__GPIO3_IO11                          = IOMUX_PAD(0x0350, 0x00E0, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6                       = IOMUX_PAD(0x0350, 0x00E0, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA07__LCD_DATA7                           = IOMUX_PAD(0x0354, 0x00E4, 0, 0x0654, 2, 0),
-	MX7D_PAD_LCD_DATA07__CSI_MCLK                            = IOMUX_PAD(0x0354, 0x00E4, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA07__EIM_DATA7                           = IOMUX_PAD(0x0354, 0x00E4, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA07__GPIO3_IO12                          = IOMUX_PAD(0x0354, 0x00E4, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7                       = IOMUX_PAD(0x0354, 0x00E4, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA08__LCD_DATA8                           = IOMUX_PAD(0x0358, 0x00E8, 0, 0x0658, 2, 0),
-	MX7D_PAD_LCD_DATA08__CSI_DATA9                           = IOMUX_PAD(0x0358, 0x00E8, 3, 0x0514, 0, 0),
-	MX7D_PAD_LCD_DATA08__EIM_DATA8                           = IOMUX_PAD(0x0358, 0x00E8, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA08__GPIO3_IO13                          = IOMUX_PAD(0x0358, 0x00E8, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8                       = IOMUX_PAD(0x0358, 0x00E8, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA09__LCD_DATA9                           = IOMUX_PAD(0x035C, 0x00EC, 0, 0x065C, 2, 0),
-	MX7D_PAD_LCD_DATA09__CSI_DATA8                           = IOMUX_PAD(0x035C, 0x00EC, 3, 0x0510, 0, 0),
-	MX7D_PAD_LCD_DATA09__EIM_DATA9                           = IOMUX_PAD(0x035C, 0x00EC, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA09__GPIO3_IO14                          = IOMUX_PAD(0x035C, 0x00EC, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9                       = IOMUX_PAD(0x035C, 0x00EC, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA10__LCD_DATA10                          = IOMUX_PAD(0x0360, 0x00F0, 0, 0x0660, 2, 0),
-	MX7D_PAD_LCD_DATA10__CSI_DATA7                           = IOMUX_PAD(0x0360, 0x00F0, 3, 0x050C, 0, 0),
-	MX7D_PAD_LCD_DATA10__EIM_DATA10                          = IOMUX_PAD(0x0360, 0x00F0, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA10__GPIO3_IO15                          = IOMUX_PAD(0x0360, 0x00F0, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10                      = IOMUX_PAD(0x0360, 0x00F0, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA11__LCD_DATA11                          = IOMUX_PAD(0x0364, 0x00F4, 0, 0x0664, 2, 0),
-	MX7D_PAD_LCD_DATA11__CSI_DATA6                           = IOMUX_PAD(0x0364, 0x00F4, 3, 0x0508, 0, 0),
-	MX7D_PAD_LCD_DATA11__EIM_DATA11                          = IOMUX_PAD(0x0364, 0x00F4, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA11__GPIO3_IO16                          = IOMUX_PAD(0x0364, 0x00F4, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11                      = IOMUX_PAD(0x0364, 0x00F4, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA12__LCD_DATA12                          = IOMUX_PAD(0x0368, 0x00F8, 0, 0x0668, 2, 0),
-	MX7D_PAD_LCD_DATA12__CSI_DATA5                           = IOMUX_PAD(0x0368, 0x00F8, 3, 0x0504, 0, 0),
-	MX7D_PAD_LCD_DATA12__EIM_DATA12                          = IOMUX_PAD(0x0368, 0x00F8, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA12__GPIO3_IO17                          = IOMUX_PAD(0x0368, 0x00F8, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12                      = IOMUX_PAD(0x0368, 0x00F8, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA13__LCD_DATA13                          = IOMUX_PAD(0x036C, 0x00FC, 0, 0x066C, 1, 0),
-	MX7D_PAD_LCD_DATA13__CSI_DATA4                           = IOMUX_PAD(0x036C, 0x00FC, 3, 0x0500, 0, 0),
-	MX7D_PAD_LCD_DATA13__EIM_DATA13                          = IOMUX_PAD(0x036C, 0x00FC, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA13__GPIO3_IO18                          = IOMUX_PAD(0x036C, 0x00FC, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13                      = IOMUX_PAD(0x036C, 0x00FC, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA14__LCD_DATA14                          = IOMUX_PAD(0x0370, 0x0100, 0, 0x0670, 1, 0),
-	MX7D_PAD_LCD_DATA14__CSI_DATA3                           = IOMUX_PAD(0x0370, 0x0100, 3, 0x04FC, 0, 0),
-	MX7D_PAD_LCD_DATA14__EIM_DATA14                          = IOMUX_PAD(0x0370, 0x0100, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA14__GPIO3_IO19                          = IOMUX_PAD(0x0370, 0x0100, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14                      = IOMUX_PAD(0x0370, 0x0100, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA15__LCD_DATA15                          = IOMUX_PAD(0x0374, 0x0104, 0, 0x0674, 1, 0),
-	MX7D_PAD_LCD_DATA15__CSI_DATA2                           = IOMUX_PAD(0x0374, 0x0104, 3, 0x04F8, 0, 0),
-	MX7D_PAD_LCD_DATA15__EIM_DATA15                          = IOMUX_PAD(0x0374, 0x0104, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA15__GPIO3_IO20                          = IOMUX_PAD(0x0374, 0x0104, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15                      = IOMUX_PAD(0x0374, 0x0104, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA16__LCD_DATA16                          = IOMUX_PAD(0x0378, 0x0108, 0, 0x0678, 2, 0),
-	MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4                      = IOMUX_PAD(0x0378, 0x0108, 1, 0x0594, 0, 0),
-	MX7D_PAD_LCD_DATA16__CSI_DATA1                           = IOMUX_PAD(0x0378, 0x0108, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA16__EIM_CRE                             = IOMUX_PAD(0x0378, 0x0108, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA16__GPIO3_IO21                          = IOMUX_PAD(0x0378, 0x0108, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16                      = IOMUX_PAD(0x0378, 0x0108, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA17__LCD_DATA17                          = IOMUX_PAD(0x037C, 0x010C, 0, 0x067C, 2, 0),
-	MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5                      = IOMUX_PAD(0x037C, 0x010C, 1, 0x0598, 0, 0),
-	MX7D_PAD_LCD_DATA17__CSI_DATA0                           = IOMUX_PAD(0x037C, 0x010C, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN                    = IOMUX_PAD(0x037C, 0x010C, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA17__GPIO3_IO22                          = IOMUX_PAD(0x037C, 0x010C, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17                      = IOMUX_PAD(0x037C, 0x010C, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA18__LCD_DATA18                          = IOMUX_PAD(0x0380, 0x0110, 0, 0x0680, 2, 0),
-	MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6                      = IOMUX_PAD(0x0380, 0x0110, 1, 0x059C, 0, 0),
-	MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO                 = IOMUX_PAD(0x0380, 0x0110, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA18__CSI_DATA15                          = IOMUX_PAD(0x0380, 0x0110, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA18__EIM_CS2_B                           = IOMUX_PAD(0x0380, 0x0110, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA18__GPIO3_IO23                          = IOMUX_PAD(0x0380, 0x0110, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18                      = IOMUX_PAD(0x0380, 0x0110, 6, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA19__EIM_CS3_B                           = IOMUX_PAD(0x0384, 0x0114, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA19__GPIO3_IO24                          = IOMUX_PAD(0x0384, 0x0114, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19                      = IOMUX_PAD(0x0384, 0x0114, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA19__LCD_DATA19                          = IOMUX_PAD(0x0384, 0x0114, 0, 0x0684, 2, 0),
-	MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7                      = IOMUX_PAD(0x0384, 0x0114, 1, 0x05A0, 0, 0),
-	MX7D_PAD_LCD_DATA19__CSI_DATA14                          = IOMUX_PAD(0x0384, 0x0114, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA20__EIM_ADDR23                          = IOMUX_PAD(0x0388, 0x0118, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA20__GPIO3_IO25                          = IOMUX_PAD(0x0388, 0x0118, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA20__I2C3_SCL                            = IOMUX_PAD(0x0388, 0x0118, IOMUX_CONFIG_SION | 6, 0x05E4, 1, 0),
-
-	MX7D_PAD_LCD_DATA20__LCD_DATA20                          = IOMUX_PAD(0x0388, 0x0118, 0, 0x0688, 2, 0),
-	MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4                      = IOMUX_PAD(0x0388, 0x0118, 1, 0x05BC, 0, 0),
-	MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT               = IOMUX_PAD(0x0388, 0x0118, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA20__CSI_DATA13                          = IOMUX_PAD(0x0388, 0x0118, 3, 0x0000, 0, 0),
-
-	MX7D_PAD_LCD_DATA21__LCD_DATA21                          = IOMUX_PAD(0x038C, 0x011C, 0, 0x068C, 2, 0),
-	MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5                      = IOMUX_PAD(0x038C, 0x011C, 1, 0x05C0, 0, 0),
-	MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT               = IOMUX_PAD(0x038C, 0x011C, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA21__CSI_DATA12                          = IOMUX_PAD(0x038C, 0x011C, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA21__EIM_ADDR24                          = IOMUX_PAD(0x038C, 0x011C, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA21__GPIO3_IO26                          = IOMUX_PAD(0x038C, 0x011C, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA21__I2C3_SDA                            = IOMUX_PAD(0x038C, 0x011C, IOMUX_CONFIG_SION | 6, 0x05E8, 1, 0),
-
-	MX7D_PAD_LCD_DATA22__LCD_DATA22                          = IOMUX_PAD(0x0390, 0x0120, 0, 0x0690, 2, 0),
-	MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6                      = IOMUX_PAD(0x0390, 0x0120, 1, 0x05C4, 0, 0),
-	MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT               = IOMUX_PAD(0x0390, 0x0120, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA22__CSI_DATA11                          = IOMUX_PAD(0x0390, 0x0120, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA22__EIM_ADDR25                          = IOMUX_PAD(0x0390, 0x0120, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA22__GPIO3_IO27                          = IOMUX_PAD(0x0390, 0x0120, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA22__I2C4_SCL                            = IOMUX_PAD(0x0390, 0x0120, IOMUX_CONFIG_SION | 6, 0x05EC, 1, 0),
-
-	MX7D_PAD_LCD_DATA23__LCD_DATA23                          = IOMUX_PAD(0x0394, 0x0124, 0, 0x0694, 2, 0),
-	MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7                      = IOMUX_PAD(0x0394, 0x0124, 1, 0x05C8, 0, 0),
-	MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT               = IOMUX_PAD(0x0394, 0x0124, 2, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA23__CSI_DATA10                          = IOMUX_PAD(0x0394, 0x0124, 3, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA23__EIM_ADDR26                          = IOMUX_PAD(0x0394, 0x0124, 4, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA23__GPIO3_IO28                          = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0),
-	MX7D_PAD_LCD_DATA23__I2C4_SDA                            = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0),
-
-	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0),
-
-	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
-	MX7D_PAD_UART1_RX_DATA__I2C1_SCL                         = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
-	MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY                   = IOMUX_PAD(0x0398, 0x0128, 2, 0x0000, 0, 0),
-	MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1                       = IOMUX_PAD(0x0398, 0x0128, 3, 0x0000, 0, 0),
-	MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN             = IOMUX_PAD(0x0398, 0x0128, 4, 0x0000, 0, 0),
-	MX7D_PAD_UART1_RX_DATA__GPIO4_IO0                        = IOMUX_PAD(0x0398, 0x0128, 5, 0x0000, 0, 0),
-	MX7D_PAD_UART1_RX_DATA__ENET1_MDIO                       = IOMUX_PAD(0x0398, 0x0128, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX                     = IOMUX_PAD(0x039C, 0x012C, 0, 0x0000, 0, 0),
-
-	MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX                     = IOMUX_PAD(0x039C, 0x012C, 0, 0x06F4, 1, 0),
-	MX7D_PAD_UART1_TX_DATA__I2C1_SDA                         = IOMUX_PAD(0x039C, 0x012C, IOMUX_CONFIG_SION | 1, 0x05D8, 0, 0),
-	MX7D_PAD_UART1_TX_DATA__SAI3_MCLK                        = IOMUX_PAD(0x039C, 0x012C, 2, 0x0000, 0, 0),
-	MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2                       = IOMUX_PAD(0x039C, 0x012C, 3, 0x0000, 0, 0),
-	MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT            = IOMUX_PAD(0x039C, 0x012C, 4, 0x0000, 0, 0),
-	MX7D_PAD_UART1_TX_DATA__GPIO4_IO1                        = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0),
-	MX7D_PAD_UART1_TX_DATA__ENET1_MDC                        = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0),
-
-	MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
-	MX7D_PAD_UART2_RX_DATA__I2C2_SCL                         = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
-	MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK                     = IOMUX_PAD(0x03A0, 0x0130, 2, 0x0000, 0, 0),
-	MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3                       = IOMUX_PAD(0x03A0, 0x0130, 3, 0x0000, 0, 0),
-	MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN             = IOMUX_PAD(0x03A0, 0x0130, 4, 0x0000, 0, 0),
-	MX7D_PAD_UART2_RX_DATA__GPIO4_IO2                        = IOMUX_PAD(0x03A0, 0x0130, 5, 0x0000, 0, 0),
-	MX7D_PAD_UART2_RX_DATA__ENET2_MDIO                       = IOMUX_PAD(0x03A0, 0x0130, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
-
-	MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0),
-	MX7D_PAD_UART2_TX_DATA__I2C2_SDA                         = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0),
-	MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0                    = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0),
-	MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY                       = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0),
-	MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT            = IOMUX_PAD(0x03A4, 0x0134, 4, 0x0000, 0, 0),
-	MX7D_PAD_UART2_TX_DATA__GPIO4_IO3                        = IOMUX_PAD(0x03A4, 0x0134, 5, 0x0000, 0, 0),
-	MX7D_PAD_UART2_TX_DATA__ENET2_MDC                        = IOMUX_PAD(0x03A4, 0x0134, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX                     = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0704, 2, 0),
-
-	MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX                     = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0000, 0, 0),
-	MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC                      = IOMUX_PAD(0x03A8, 0x0138, 1, 0x072C, 0, 0),
-	MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC                     = IOMUX_PAD(0x03A8, 0x0138, 2, 0x06CC, 0, 0),
-	MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO                      = IOMUX_PAD(0x03A8, 0x0138, 3, 0x0528, 0, 0),
-	MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN             = IOMUX_PAD(0x03A8, 0x0138, 4, 0x0000, 0, 0),
-	MX7D_PAD_UART3_RX_DATA__GPIO4_IO4                        = IOMUX_PAD(0x03A8, 0x0138, 5, 0x0000, 0, 0),
-	MX7D_PAD_UART3_RX_DATA__SD1_LCTL                         = IOMUX_PAD(0x03A8, 0x0138, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX                     = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0000, 0, 0),
-
-	MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX                     = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0704, 3, 0),
-	MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR                     = IOMUX_PAD(0x03AC, 0x013C, 1, 0x0000, 0, 0),
-	MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK                     = IOMUX_PAD(0x03AC, 0x013C, 2, 0x06D0, 0, 0),
-	MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI                      = IOMUX_PAD(0x03AC, 0x013C, 3, 0x052C, 0, 0),
-	MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT            = IOMUX_PAD(0x03AC, 0x013C, 4, 0x0000, 0, 0),
-	MX7D_PAD_UART3_TX_DATA__GPIO4_IO5                        = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0),
-	MX7D_PAD_UART3_TX_DATA__SD2_LCTL                         = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0),
-
-	MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
-	MX7D_PAD_UART3_RTS_B__USB_OTG2_OC                        = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0),
-	MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0                      = IOMUX_PAD(0x03B0, 0x0140, 2, 0x0000, 0, 0),
-	MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK                        = IOMUX_PAD(0x03B0, 0x0140, 3, 0x0000, 0, 0),
-	MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN               = IOMUX_PAD(0x03B0, 0x0140, 4, 0x0000, 0, 0),
-	MX7D_PAD_UART3_RTS_B__GPIO4_IO6                          = IOMUX_PAD(0x03B0, 0x0140, 5, 0x0000, 0, 0),
-	MX7D_PAD_UART3_RTS_B__SD3_LCTL                           = IOMUX_PAD(0x03B0, 0x0140, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS                      = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0000, 0, 0),
-
-	MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS                      = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0700, 3, 0),
-	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR                       = IOMUX_PAD(0x03B4, 0x0144, 1, 0x0000, 0, 0),
-	MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC                       = IOMUX_PAD(0x03B4, 0x0144, 2, 0x06D4, 0, 0),
-	MX7D_PAD_UART3_CTS_B__ECSPI1_SS0                         = IOMUX_PAD(0x03B4, 0x0144, 3, 0x0530, 0, 0),
-	MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT              = IOMUX_PAD(0x03B4, 0x0144, 4, 0x0000, 0, 0),
-	MX7D_PAD_UART3_CTS_B__GPIO4_IO7                          = IOMUX_PAD(0x03B4, 0x0144, 5, 0x0000, 0, 0),
-	MX7D_PAD_UART3_CTS_B__SD1_VSELECT                        = IOMUX_PAD(0x03B4, 0x0144, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_I2C1_SCL__I2C1_SCL                              = IOMUX_PAD(0x03B8, 0x0148, IOMUX_CONFIG_SION | 0, 0x05D4, 1, 0),
-	MX7D_PAD_I2C1_SCL__UART4_DCE_CTS                         = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0000, 0, 0),
-	MX7D_PAD_I2C1_SCL__UART4_DTE_RTS                         = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0708, 0, 0),
-	MX7D_PAD_I2C1_SCL__FLEXCAN1_RX                           = IOMUX_PAD(0x03B8, 0x0148, 2, 0x04DC, 1, 0),
-	MX7D_PAD_I2C1_SCL__ECSPI3_MISO                           = IOMUX_PAD(0x03B8, 0x0148, 3, 0x0548, 0, 0),
-	MX7D_PAD_I2C1_SCL__GPIO4_IO8                             = IOMUX_PAD(0x03B8, 0x0148, 5, 0x0000, 0, 0),
-	MX7D_PAD_I2C1_SCL__SD2_VSELECT                           = IOMUX_PAD(0x03B8, 0x0148, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_I2C1_SDA__I2C1_SDA                              = IOMUX_PAD(0x03BC, 0x014C, IOMUX_CONFIG_SION | 0, 0x05D8, 1, 0),
-	MX7D_PAD_I2C1_SDA__UART4_DCE_RTS                         = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0708, 1, 0),
-	MX7D_PAD_I2C1_SDA__UART4_DTE_CTS                         = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0000, 0, 0),
-	MX7D_PAD_I2C1_SDA__FLEXCAN1_TX                           = IOMUX_PAD(0x03BC, 0x014C, 2, 0x0000, 0, 0),
-	MX7D_PAD_I2C1_SDA__ECSPI3_MOSI                           = IOMUX_PAD(0x03BC, 0x014C, 3, 0x054C, 0, 0),
-	MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1                     = IOMUX_PAD(0x03BC, 0x014C, 4, 0x0564, 1, 0),
-	MX7D_PAD_I2C1_SDA__GPIO4_IO9                             = IOMUX_PAD(0x03BC, 0x014C, 5, 0x0000, 0, 0),
-	MX7D_PAD_I2C1_SDA__SD3_VSELECT                           = IOMUX_PAD(0x03BC, 0x014C, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_I2C2_SCL__I2C2_SCL                              = IOMUX_PAD(0x03C0, 0x0150, IOMUX_CONFIG_SION | 0, 0x05DC, 1, 0),
-	MX7D_PAD_I2C2_SCL__UART4_DCE_RX                          = IOMUX_PAD(0x03C0, 0x0150, 1, 0x070C, 0, 0),
-	MX7D_PAD_I2C2_SCL__UART4_DTE_TX                          = IOMUX_PAD(0x03C0, 0x0150, 1, 0x0000, 0, 0),
-	MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B                          = IOMUX_PAD(0x03C0, 0x0150, 2, 0x0000, 0, 0),
-	MX7D_PAD_I2C2_SCL__ECSPI3_SCLK                           = IOMUX_PAD(0x03C0, 0x0150, 3, 0x0544, 0, 0),
-	MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2                     = IOMUX_PAD(0x03C0, 0x0150, 4, 0x0570, 2, 0),
-	MX7D_PAD_I2C2_SCL__GPIO4_IO10                            = IOMUX_PAD(0x03C0, 0x0150, 5, 0x0000, 0, 0),
-	MX7D_PAD_I2C2_SCL__SD3_CD_B                              = IOMUX_PAD(0x03C0, 0x0150, 6, 0x0738, 1, 0),
-
-	MX7D_PAD_I2C2_SDA__I2C2_SDA                              = IOMUX_PAD(0x03C4, 0x0154, IOMUX_CONFIG_SION | 0, 0x05E0, 1, 0),
-	MX7D_PAD_I2C2_SDA__UART4_DCE_TX                          = IOMUX_PAD(0x03C4, 0x0154, 1, 0x0000, 0, 0),
-	MX7D_PAD_I2C2_SDA__UART4_DTE_RX                          = IOMUX_PAD(0x03C4, 0x0154, 1, 0x070C, 1, 0),
-	MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB                  = IOMUX_PAD(0x03C4, 0x0154, 2, 0x0000, 0, 0),
-	MX7D_PAD_I2C2_SDA__ECSPI3_SS0                            = IOMUX_PAD(0x03C4, 0x0154, 3, 0x0550, 0, 0),
-	MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3                     = IOMUX_PAD(0x03C4, 0x0154, 4, 0x0000, 0, 0),
-	MX7D_PAD_I2C2_SDA__GPIO4_IO11                            = IOMUX_PAD(0x03C4, 0x0154, 5, 0x0000, 0, 0),
-	MX7D_PAD_I2C2_SDA__SD3_WP                                = IOMUX_PAD(0x03C4, 0x0154, 6, 0x073C, 1, 0),
-
-	MX7D_PAD_I2C3_SCL__I2C3_SCL                              = IOMUX_PAD(0x03C8, 0x0158, IOMUX_CONFIG_SION | 0, 0x05E4, 2, 0),
-	MX7D_PAD_I2C3_SCL__UART5_DCE_CTS                         = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0000, 0, 0),
-	MX7D_PAD_I2C3_SCL__UART5_DTE_RTS                         = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0710, 0, 0),
-	MX7D_PAD_I2C3_SCL__FLEXCAN2_RX                           = IOMUX_PAD(0x03C8, 0x0158, 2, 0x04E0, 1, 0),
-	MX7D_PAD_I2C3_SCL__CSI_VSYNC                             = IOMUX_PAD(0x03C8, 0x0158, 3, 0x0520, 1, 0),
-	MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0                       = IOMUX_PAD(0x03C8, 0x0158, 4, 0x06D8, 1, 0),
-	MX7D_PAD_I2C3_SCL__GPIO4_IO12                            = IOMUX_PAD(0x03C8, 0x0158, 5, 0x0000, 0, 0),
-	MX7D_PAD_I2C3_SCL__EPDC_BDR0                             = IOMUX_PAD(0x03C8, 0x0158, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_I2C3_SDA__I2C3_SDA                              = IOMUX_PAD(0x03CC, 0x015C, IOMUX_CONFIG_SION | 0, 0x05E8, 2, 0),
-	MX7D_PAD_I2C3_SDA__UART5_DCE_RTS                         = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0710, 1, 0),
-	MX7D_PAD_I2C3_SDA__UART5_DTE_CTS                         = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0000, 0, 0),
-	MX7D_PAD_I2C3_SDA__FLEXCAN2_TX                           = IOMUX_PAD(0x03CC, 0x015C, 2, 0x0000, 0, 0),
-	MX7D_PAD_I2C3_SDA__CSI_HSYNC                             = IOMUX_PAD(0x03CC, 0x015C, 3, 0x0518, 1, 0),
-	MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1                       = IOMUX_PAD(0x03CC, 0x015C, 4, 0x06DC, 1, 0),
-	MX7D_PAD_I2C3_SDA__GPIO4_IO13                            = IOMUX_PAD(0x03CC, 0x015C, 5, 0x0000, 0, 0),
-	MX7D_PAD_I2C3_SDA__EPDC_BDR1                             = IOMUX_PAD(0x03CC, 0x015C, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_I2C4_SCL__I2C4_SCL                              = IOMUX_PAD(0x03D0, 0x0160, IOMUX_CONFIG_SION | 0, 0x05EC, 2, 0),
-	MX7D_PAD_I2C4_SCL__UART5_DCE_RX                          = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0714, 0, 0),
-	MX7D_PAD_I2C4_SCL__UART5_DTE_TX                          = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0000, 0, 0),
-	MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B                          = IOMUX_PAD(0x03D0, 0x0160, 2, 0x0000, 0, 0),
-	MX7D_PAD_I2C4_SCL__CSI_PIXCLK                            = IOMUX_PAD(0x03D0, 0x0160, 3, 0x051C, 1, 0),
-	MX7D_PAD_I2C4_SCL__USB_OTG1_ID                           = IOMUX_PAD(0x03D0, 0x0160, 4, 0x0734, 1, 0),
-	MX7D_PAD_I2C4_SCL__GPIO4_IO14                            = IOMUX_PAD(0x03D0, 0x0160, 5, 0x0000, 0, 0),
-	MX7D_PAD_I2C4_SCL__EPDC_VCOM0                            = IOMUX_PAD(0x03D0, 0x0160, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_I2C4_SDA__I2C4_SDA                              = IOMUX_PAD(0x03D4, 0x0164, IOMUX_CONFIG_SION | 0, 0x05F0, 2, 0),
-	MX7D_PAD_I2C4_SDA__UART5_DCE_TX                          = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0000, 0, 0),
-	MX7D_PAD_I2C4_SDA__UART5_DTE_RX                          = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0714, 1, 0),
-	MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB                  = IOMUX_PAD(0x03D4, 0x0164, 2, 0x0000, 0, 0),
-	MX7D_PAD_I2C4_SDA__CSI_MCLK                              = IOMUX_PAD(0x03D4, 0x0164, 3, 0x0000, 0, 0),
-	MX7D_PAD_I2C4_SDA__USB_OTG2_ID                           = IOMUX_PAD(0x03D4, 0x0164, 4, 0x0730, 1, 0),
-	MX7D_PAD_I2C4_SDA__GPIO4_IO15                            = IOMUX_PAD(0x03D4, 0x0164, 5, 0x0000, 0, 0),
-	MX7D_PAD_I2C4_SDA__EPDC_VCOM1                            = IOMUX_PAD(0x03D4, 0x0164, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK                        = IOMUX_PAD(0x03D8, 0x0168, 0, 0x0524, 1, 0),
-	MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX                       = IOMUX_PAD(0x03D8, 0x0168, 1, 0x071C, 2, 0),
-	MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX                       = IOMUX_PAD(0x03D8, 0x0168, 1, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_SCLK__SD2_DATA4                          = IOMUX_PAD(0x03D8, 0x0168, 2, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_SCLK__CSI_DATA2                          = IOMUX_PAD(0x03D8, 0x0168, 3, 0x04F8, 1, 0),
-	MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16                         = IOMUX_PAD(0x03D8, 0x0168, 5, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM                       = IOMUX_PAD(0x03D8, 0x0168, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI                        = IOMUX_PAD(0x03DC, 0x016C, 0, 0x052C, 1, 0),
-	MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX                       = IOMUX_PAD(0x03DC, 0x016C, 1, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX                       = IOMUX_PAD(0x03DC, 0x016C, 1, 0x071C, 3, 0),
-	MX7D_PAD_ECSPI1_MOSI__SD2_DATA5                          = IOMUX_PAD(0x03DC, 0x016C, 2, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_MOSI__CSI_DATA3                          = IOMUX_PAD(0x03DC, 0x016C, 3, 0x04FC, 1, 0),
-	MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17                         = IOMUX_PAD(0x03DC, 0x016C, 5, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT                      = IOMUX_PAD(0x03DC, 0x016C, 6, 0x0580, 1, 0),
-
-	MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO                        = IOMUX_PAD(0x03E0, 0x0170, 0, 0x0528, 1, 0),
-	MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS                      = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0718, 2, 0),
-	MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS                      = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_MISO__SD2_DATA6                          = IOMUX_PAD(0x03E0, 0x0170, 2, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_MISO__CSI_DATA4                          = IOMUX_PAD(0x03E0, 0x0170, 3, 0x0500, 1, 0),
-	MX7D_PAD_ECSPI1_MISO__GPIO4_IO18                         = IOMUX_PAD(0x03E0, 0x0170, 5, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ                       = IOMUX_PAD(0x03E0, 0x0170, 6, 0x057C, 0, 0),
-
-	MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0                          = IOMUX_PAD(0x03E4, 0x0174, 0, 0x0530, 1, 0),
-	MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS                       = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS                       = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0718, 3, 0),
-	MX7D_PAD_ECSPI1_SS0__SD2_DATA7                           = IOMUX_PAD(0x03E4, 0x0174, 2, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_SS0__CSI_DATA5                           = IOMUX_PAD(0x03E4, 0x0174, 3, 0x0504, 1, 0),
-	MX7D_PAD_ECSPI1_SS0__GPIO4_IO19                          = IOMUX_PAD(0x03E4, 0x0174, 5, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3                      = IOMUX_PAD(0x03E4, 0x0174, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK                        = IOMUX_PAD(0x03E8, 0x0178, 0, 0x0534, 0, 0),
-	MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX                       = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0724, 2, 0),
-	MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX                       = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_SCLK__SD1_DATA4                          = IOMUX_PAD(0x03E8, 0x0178, 2, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_SCLK__CSI_DATA6                          = IOMUX_PAD(0x03E8, 0x0178, 3, 0x0508, 1, 0),
-	MX7D_PAD_ECSPI2_SCLK__LCD_DATA13                         = IOMUX_PAD(0x03E8, 0x0178, 4, 0x066C, 2, 0),
-	MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20                         = IOMUX_PAD(0x03E8, 0x0178, 5, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0                     = IOMUX_PAD(0x03E8, 0x0178, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI                        = IOMUX_PAD(0x03EC, 0x017C, 0, 0x053C, 0, 0),
-	MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX                       = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX                       = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0724, 3, 0),
-	MX7D_PAD_ECSPI2_MOSI__SD1_DATA5                          = IOMUX_PAD(0x03EC, 0x017C, 2, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_MOSI__CSI_DATA7                          = IOMUX_PAD(0x03EC, 0x017C, 3, 0x050C, 1, 0),
-	MX7D_PAD_ECSPI2_MOSI__LCD_DATA14                         = IOMUX_PAD(0x03EC, 0x017C, 4, 0x0670, 2, 0),
-	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21                         = IOMUX_PAD(0x03EC, 0x017C, 5, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1                     = IOMUX_PAD(0x03EC, 0x017C, 6, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_MISO__GPIO4_IO22                         = IOMUX_PAD(0x03F0, 0x0180, 5, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2                     = IOMUX_PAD(0x03F0, 0x0180, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO                        = IOMUX_PAD(0x03F0, 0x0180, 0, 0x0538, 0, 0),
-	MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS                      = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0720, 2, 0),
-	MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS                      = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_MISO__SD1_DATA6                          = IOMUX_PAD(0x03F0, 0x0180, 2, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_MISO__CSI_DATA8                          = IOMUX_PAD(0x03F0, 0x0180, 3, 0x0510, 1, 0),
-	MX7D_PAD_ECSPI2_MISO__LCD_DATA15                         = IOMUX_PAD(0x03F0, 0x0180, 4, 0x0674, 2, 0),
-
-	MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0                          = IOMUX_PAD(0x03F4, 0x0184, 0, 0x0540, 0, 0),
-	MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS                       = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS                       = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0720, 3, 0),
-	MX7D_PAD_ECSPI2_SS0__SD1_DATA7                           = IOMUX_PAD(0x03F4, 0x0184, 2, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_SS0__CSI_DATA9                           = IOMUX_PAD(0x03F4, 0x0184, 3, 0x0514, 1, 0),
-	MX7D_PAD_ECSPI2_SS0__LCD_RESET                           = IOMUX_PAD(0x03F4, 0x0184, 4, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_SS0__GPIO4_IO23                          = IOMUX_PAD(0x03F4, 0x0184, 5, 0x0000, 0, 0),
-	MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE                       = IOMUX_PAD(0x03F4, 0x0184, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_SD1_CD_B__SD1_CD_B                              = IOMUX_PAD(0x03F8, 0x0188, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD1_CD_B__UART6_DCE_RX                          = IOMUX_PAD(0x03F8, 0x0188, 2, 0x071C, 4, 0),
-	MX7D_PAD_SD1_CD_B__UART6_DTE_TX                          = IOMUX_PAD(0x03F8, 0x0188, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD1_CD_B__ECSPI4_MISO                           = IOMUX_PAD(0x03F8, 0x0188, 3, 0x0558, 1, 0),
-	MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0                        = IOMUX_PAD(0x03F8, 0x0188, 4, 0x0584, 1, 0),
-	MX7D_PAD_SD1_CD_B__GPIO5_IO0                             = IOMUX_PAD(0x03F8, 0x0188, 5, 0x0000, 0, 0),
-	MX7D_PAD_SD1_CD_B__CCM_CLKO1                             = IOMUX_PAD(0x03F8, 0x0188, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_SD1_WP__SD1_WP                                  = IOMUX_PAD(0x03FC, 0x018C, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD1_WP__UART6_DCE_TX                            = IOMUX_PAD(0x03FC, 0x018C, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD1_WP__UART6_DTE_RX                            = IOMUX_PAD(0x03FC, 0x018C, 2, 0x071C, 5, 0),
-	MX7D_PAD_SD1_WP__ECSPI4_MOSI                             = IOMUX_PAD(0x03FC, 0x018C, 3, 0x055C, 1, 0),
-	MX7D_PAD_SD1_WP__FLEXTIMER1_CH1                          = IOMUX_PAD(0x03FC, 0x018C, 4, 0x0588, 1, 0),
-	MX7D_PAD_SD1_WP__GPIO5_IO1                               = IOMUX_PAD(0x03FC, 0x018C, 5, 0x0000, 0, 0),
-	MX7D_PAD_SD1_WP__CCM_CLKO2                               = IOMUX_PAD(0x03FC, 0x018C, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_SD1_RESET_B__SD1_RESET_B                        = IOMUX_PAD(0x0400, 0x0190, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD1_RESET_B__SAI3_MCLK                          = IOMUX_PAD(0x0400, 0x0190, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS                      = IOMUX_PAD(0x0400, 0x0190, 2, 0x0718, 4, 0),
-	MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS                      = IOMUX_PAD(0x0400, 0x0190, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK                        = IOMUX_PAD(0x0400, 0x0190, 3, 0x0554, 1, 0),
-	MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2                     = IOMUX_PAD(0x0400, 0x0190, 4, 0x058C, 1, 0),
-	MX7D_PAD_SD1_RESET_B__GPIO5_IO2                          = IOMUX_PAD(0x0400, 0x0190, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD1_CLK__SD1_CLK                                = IOMUX_PAD(0x0404, 0x0194, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD1_CLK__SAI3_RX_SYNC                           = IOMUX_PAD(0x0404, 0x0194, 1, 0x06CC, 1, 0),
-	MX7D_PAD_SD1_CLK__UART6_DCE_CTS                          = IOMUX_PAD(0x0404, 0x0194, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD1_CLK__UART6_DTE_RTS                          = IOMUX_PAD(0x0404, 0x0194, 2, 0x0718, 5, 0),
-	MX7D_PAD_SD1_CLK__ECSPI4_SS0                             = IOMUX_PAD(0x0404, 0x0194, 3, 0x0560, 1, 0),
-	MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3                         = IOMUX_PAD(0x0404, 0x0194, 4, 0x0590, 1, 0),
-	MX7D_PAD_SD1_CLK__GPIO5_IO3                              = IOMUX_PAD(0x0404, 0x0194, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD1_CMD__SD1_CMD                                = IOMUX_PAD(0x0408, 0x0198, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD1_CMD__SAI3_RX_BCLK                           = IOMUX_PAD(0x0408, 0x0198, 1, 0x06C4, 1, 0),
-	MX7D_PAD_SD1_CMD__ECSPI4_SS1                             = IOMUX_PAD(0x0408, 0x0198, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0                         = IOMUX_PAD(0x0408, 0x0198, 4, 0x05AC, 1, 0),
-	MX7D_PAD_SD1_CMD__GPIO5_IO4                              = IOMUX_PAD(0x0408, 0x0198, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD1_DATA0__SD1_DATA0                            = IOMUX_PAD(0x040C, 0x019C, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0                        = IOMUX_PAD(0x040C, 0x019C, 1, 0x06C8, 1, 0),
-	MX7D_PAD_SD1_DATA0__UART7_DCE_RX                         = IOMUX_PAD(0x040C, 0x019C, 2, 0x0724, 4, 0),
-	MX7D_PAD_SD1_DATA0__UART7_DTE_TX                         = IOMUX_PAD(0x040C, 0x019C, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA0__ECSPI4_SS2                           = IOMUX_PAD(0x040C, 0x019C, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1                       = IOMUX_PAD(0x040C, 0x019C, 4, 0x05B0, 1, 0),
-	MX7D_PAD_SD1_DATA0__GPIO5_IO5                            = IOMUX_PAD(0x040C, 0x019C, 5, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1                         = IOMUX_PAD(0x040C, 0x019C, 6, 0x04E4, 1, 0),
-
-	MX7D_PAD_SD1_DATA1__SD1_DATA1                            = IOMUX_PAD(0x0410, 0x01A0, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK                         = IOMUX_PAD(0x0410, 0x01A0, 1, 0x06D0, 1, 0),
-	MX7D_PAD_SD1_DATA1__UART7_DCE_TX                         = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA1__UART7_DTE_RX                         = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0724, 5, 0),
-	MX7D_PAD_SD1_DATA1__ECSPI4_SS3                           = IOMUX_PAD(0x0410, 0x01A0, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2                       = IOMUX_PAD(0x0410, 0x01A0, 4, 0x05B4, 1, 0),
-	MX7D_PAD_SD1_DATA1__GPIO5_IO6                            = IOMUX_PAD(0x0410, 0x01A0, 5, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2                         = IOMUX_PAD(0x0410, 0x01A0, 6, 0x04E8, 1, 0),
-
-	MX7D_PAD_SD1_DATA2__SD1_DATA2                            = IOMUX_PAD(0x0414, 0x01A4, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC                         = IOMUX_PAD(0x0414, 0x01A4, 1, 0x06D4, 1, 0),
-	MX7D_PAD_SD1_DATA2__UART7_DCE_CTS                        = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA2__UART7_DTE_RTS                        = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0720, 4, 0),
-	MX7D_PAD_SD1_DATA2__ECSPI4_RDY                           = IOMUX_PAD(0x0414, 0x01A4, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3                       = IOMUX_PAD(0x0414, 0x01A4, 4, 0x05B8, 1, 0),
-	MX7D_PAD_SD1_DATA2__GPIO5_IO7                            = IOMUX_PAD(0x0414, 0x01A4, 5, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3                         = IOMUX_PAD(0x0414, 0x01A4, 6, 0x04EC, 1, 0),
-
-	MX7D_PAD_SD1_DATA3__SD1_DATA3                            = IOMUX_PAD(0x0418, 0x01A8, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0                        = IOMUX_PAD(0x0418, 0x01A8, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA3__UART7_DCE_RTS                        = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0720, 5, 0),
-	MX7D_PAD_SD1_DATA3__UART7_DTE_CTS                        = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA3__ECSPI3_SS1                           = IOMUX_PAD(0x0418, 0x01A8, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA                       = IOMUX_PAD(0x0418, 0x01A8, 4, 0x05A4, 1, 0),
-	MX7D_PAD_SD1_DATA3__GPIO5_IO8                            = IOMUX_PAD(0x0418, 0x01A8, 5, 0x0000, 0, 0),
-	MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4                         = IOMUX_PAD(0x0418, 0x01A8, 6, 0x04F0, 1, 0),
-
-	MX7D_PAD_SD2_CD_B__SD2_CD_B                              = IOMUX_PAD(0x041C, 0x01AC, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD2_CD_B__ENET1_MDIO                            = IOMUX_PAD(0x041C, 0x01AC, 1, 0x0568, 2, 0),
-	MX7D_PAD_SD2_CD_B__ENET2_MDIO                            = IOMUX_PAD(0x041C, 0x01AC, 2, 0x0574, 2, 0),
-	MX7D_PAD_SD2_CD_B__ECSPI3_SS2                            = IOMUX_PAD(0x041C, 0x01AC, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB                        = IOMUX_PAD(0x041C, 0x01AC, 4, 0x05A8, 1, 0),
-	MX7D_PAD_SD2_CD_B__GPIO5_IO9                             = IOMUX_PAD(0x041C, 0x01AC, 5, 0x0000, 0, 0),
-	MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0                       = IOMUX_PAD(0x041C, 0x01AC, 6, 0x06D8, 2, 0),
-
-	MX7D_PAD_SD2_WP__SD2_WP                                  = IOMUX_PAD(0x0420, 0x01B0, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD2_WP__ENET1_MDC                               = IOMUX_PAD(0x0420, 0x01B0, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD2_WP__ENET2_MDC                               = IOMUX_PAD(0x0420, 0x01B0, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD2_WP__ECSPI3_SS3                              = IOMUX_PAD(0x0420, 0x01B0, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD2_WP__USB_OTG1_ID                             = IOMUX_PAD(0x0420, 0x01B0, 4, 0x0734, 2, 0),
-	MX7D_PAD_SD2_WP__GPIO5_IO10                              = IOMUX_PAD(0x0420, 0x01B0, 5, 0x0000, 0, 0),
-	MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1                         = IOMUX_PAD(0x0420, 0x01B0, 6, 0x06DC, 2, 0),
-
-	MX7D_PAD_SD2_RESET_B__SD2_RESET_B                        = IOMUX_PAD(0x0424, 0x01B4, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD2_RESET_B__SAI2_MCLK                          = IOMUX_PAD(0x0424, 0x01B4, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD2_RESET_B__SD2_RESET                          = IOMUX_PAD(0x0424, 0x01B4, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD2_RESET_B__ECSPI3_RDY                         = IOMUX_PAD(0x0424, 0x01B4, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD2_RESET_B__USB_OTG2_ID                        = IOMUX_PAD(0x0424, 0x01B4, 4, 0x0730, 2, 0),
-	MX7D_PAD_SD2_RESET_B__GPIO5_IO11                         = IOMUX_PAD(0x0424, 0x01B4, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD2_CLK__SD2_CLK                                = IOMUX_PAD(0x0428, 0x01B8, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD2_CLK__SAI2_RX_SYNC                           = IOMUX_PAD(0x0428, 0x01B8, 1, 0x06B8, 0, 0),
-	MX7D_PAD_SD2_CLK__MQS_RIGHT                              = IOMUX_PAD(0x0428, 0x01B8, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD2_CLK__GPT4_CLK                               = IOMUX_PAD(0x0428, 0x01B8, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD2_CLK__GPIO5_IO12                             = IOMUX_PAD(0x0428, 0x01B8, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD2_CMD__SD2_CMD                                = IOMUX_PAD(0x042C, 0x01BC, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD2_CMD__SAI2_RX_BCLK                           = IOMUX_PAD(0x042C, 0x01BC, 1, 0x06B0, 0, 0),
-	MX7D_PAD_SD2_CMD__MQS_LEFT                               = IOMUX_PAD(0x042C, 0x01BC, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD2_CMD__GPT4_CAPTURE1                          = IOMUX_PAD(0x042C, 0x01BC, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD                        = IOMUX_PAD(0x042C, 0x01BC, 4, 0x06EC, 1, 0),
-	MX7D_PAD_SD2_CMD__GPIO5_IO13                             = IOMUX_PAD(0x042C, 0x01BC, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD2_DATA0__SD2_DATA0                            = IOMUX_PAD(0x0430, 0x01C0, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0                        = IOMUX_PAD(0x0430, 0x01C0, 1, 0x06B4, 0, 0),
-	MX7D_PAD_SD2_DATA0__UART4_DCE_RX                         = IOMUX_PAD(0x0430, 0x01C0, 2, 0x070C, 2, 0),
-	MX7D_PAD_SD2_DATA0__UART4_DTE_TX                         = IOMUX_PAD(0x0430, 0x01C0, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2                        = IOMUX_PAD(0x0430, 0x01C0, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK                       = IOMUX_PAD(0x0430, 0x01C0, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA0__GPIO5_IO14                           = IOMUX_PAD(0x0430, 0x01C0, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD2_DATA1__SD2_DATA1                            = IOMUX_PAD(0x0434, 0x01C4, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK                         = IOMUX_PAD(0x0434, 0x01C4, 1, 0x06BC, 0, 0),
-	MX7D_PAD_SD2_DATA1__UART4_DCE_TX                         = IOMUX_PAD(0x0434, 0x01C4, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA1__UART4_DTE_RX                         = IOMUX_PAD(0x0434, 0x01C4, 2, 0x070C, 3, 0),
-	MX7D_PAD_SD2_DATA1__GPT4_COMPARE1                        = IOMUX_PAD(0x0434, 0x01C4, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B                     = IOMUX_PAD(0x0434, 0x01C4, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA1__GPIO5_IO15                           = IOMUX_PAD(0x0434, 0x01C4, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD2_DATA2__SD2_DATA2                            = IOMUX_PAD(0x0438, 0x01C8, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC                         = IOMUX_PAD(0x0438, 0x01C8, 1, 0x06C0, 0, 0),
-	MX7D_PAD_SD2_DATA2__UART4_DCE_CTS                        = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA2__UART4_DTE_RTS                        = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0708, 2, 0),
-	MX7D_PAD_SD2_DATA2__GPT4_COMPARE2                        = IOMUX_PAD(0x0438, 0x01C8, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN                      = IOMUX_PAD(0x0438, 0x01C8, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA2__GPIO5_IO16                           = IOMUX_PAD(0x0438, 0x01C8, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD2_DATA3__SD2_DATA3                            = IOMUX_PAD(0x043C, 0x01CC, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0                        = IOMUX_PAD(0x043C, 0x01CC, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA3__UART4_DCE_RTS                        = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0708, 3, 0),
-	MX7D_PAD_SD2_DATA3__UART4_DTE_CTS                        = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA3__GPT4_COMPARE3                        = IOMUX_PAD(0x043C, 0x01CC, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD                        = IOMUX_PAD(0x043C, 0x01CC, 4, 0x06E8, 1, 0),
-	MX7D_PAD_SD2_DATA3__GPIO5_IO17                           = IOMUX_PAD(0x043C, 0x01CC, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_CLK__SD3_CLK                                = IOMUX_PAD(0x0440, 0x01D0, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_CLK__NAND_CLE                               = IOMUX_PAD(0x0440, 0x01D0, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_CLK__ECSPI4_MISO                            = IOMUX_PAD(0x0440, 0x01D0, 2, 0x0558, 2, 0),
-	MX7D_PAD_SD3_CLK__SAI3_RX_SYNC                           = IOMUX_PAD(0x0440, 0x01D0, 3, 0x06CC, 2, 0),
-	MX7D_PAD_SD3_CLK__GPT3_CLK                               = IOMUX_PAD(0x0440, 0x01D0, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD3_CLK__GPIO6_IO0                              = IOMUX_PAD(0x0440, 0x01D0, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_CMD__SD3_CMD                                = IOMUX_PAD(0x0444, 0x01D4, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_CMD__NAND_ALE                               = IOMUX_PAD(0x0444, 0x01D4, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_CMD__ECSPI4_MOSI                            = IOMUX_PAD(0x0444, 0x01D4, 2, 0x055C, 2, 0),
-	MX7D_PAD_SD3_CMD__SAI3_RX_BCLK                           = IOMUX_PAD(0x0444, 0x01D4, 3, 0x06C4, 2, 0),
-	MX7D_PAD_SD3_CMD__GPT3_CAPTURE1                          = IOMUX_PAD(0x0444, 0x01D4, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD3_CMD__GPIO6_IO1                              = IOMUX_PAD(0x0444, 0x01D4, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_DATA0__SD3_DATA0                            = IOMUX_PAD(0x0448, 0x01D8, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA0__NAND_DATA00                          = IOMUX_PAD(0x0448, 0x01D8, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA0__ECSPI4_SS0                           = IOMUX_PAD(0x0448, 0x01D8, 2, 0x0560, 2, 0),
-	MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0                        = IOMUX_PAD(0x0448, 0x01D8, 3, 0x06C8, 2, 0),
-	MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2                        = IOMUX_PAD(0x0448, 0x01D8, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA0__GPIO6_IO2                            = IOMUX_PAD(0x0448, 0x01D8, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_DATA1__SD3_DATA1                            = IOMUX_PAD(0x044C, 0x01DC, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA1__NAND_DATA01                          = IOMUX_PAD(0x044C, 0x01DC, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA1__ECSPI4_SCLK                          = IOMUX_PAD(0x044C, 0x01DC, 2, 0x0554, 2, 0),
-	MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK                         = IOMUX_PAD(0x044C, 0x01DC, 3, 0x06D0, 2, 0),
-	MX7D_PAD_SD3_DATA1__GPT3_COMPARE1                        = IOMUX_PAD(0x044C, 0x01DC, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA1__GPIO6_IO3                            = IOMUX_PAD(0x044C, 0x01DC, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_DATA2__SD3_DATA2                            = IOMUX_PAD(0x0450, 0x01E0, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA2__NAND_DATA02                          = IOMUX_PAD(0x0450, 0x01E0, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA2__I2C3_SDA                             = IOMUX_PAD(0x0450, 0x01E0, IOMUX_CONFIG_SION | 2, 0x05E8, 3, 0),
-	MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC                         = IOMUX_PAD(0x0450, 0x01E0, 3, 0x06D4, 2, 0),
-	MX7D_PAD_SD3_DATA2__GPT3_COMPARE2                        = IOMUX_PAD(0x0450, 0x01E0, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA2__GPIO6_IO4                            = IOMUX_PAD(0x0450, 0x01E0, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_DATA3__SD3_DATA3                            = IOMUX_PAD(0x0454, 0x01E4, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA3__NAND_DATA03                          = IOMUX_PAD(0x0454, 0x01E4, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA3__I2C3_SCL                             = IOMUX_PAD(0x0454, 0x01E4, IOMUX_CONFIG_SION | 2, 0x05E4, 3, 0),
-	MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0                        = IOMUX_PAD(0x0454, 0x01E4, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA3__GPT3_COMPARE3                        = IOMUX_PAD(0x0454, 0x01E4, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA3__GPIO6_IO5                            = IOMUX_PAD(0x0454, 0x01E4, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_DATA4__SD3_DATA4                            = IOMUX_PAD(0x0458, 0x01E8, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA4__NAND_DATA04                          = IOMUX_PAD(0x0458, 0x01E8, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA4__UART3_DCE_RX                         = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0704, 4, 0),
-	MX7D_PAD_SD3_DATA4__UART3_DTE_TX                         = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA4__FLEXCAN2_RX                          = IOMUX_PAD(0x0458, 0x01E8, 4, 0x04E0, 2, 0),
-	MX7D_PAD_SD3_DATA4__GPIO6_IO6                            = IOMUX_PAD(0x0458, 0x01E8, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_DATA5__SD3_DATA5                            = IOMUX_PAD(0x045C, 0x01EC, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA5__NAND_DATA05                          = IOMUX_PAD(0x045C, 0x01EC, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA5__UART3_DCE_TX                         = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA5__UART3_DTE_RX                         = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0704, 5, 0),
-	MX7D_PAD_SD3_DATA5__FLEXCAN1_TX                          = IOMUX_PAD(0x045C, 0x01EC, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA5__GPIO6_IO7                            = IOMUX_PAD(0x045C, 0x01EC, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_DATA6__SD3_DATA6                            = IOMUX_PAD(0x0460, 0x01F0, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA6__NAND_DATA06                          = IOMUX_PAD(0x0460, 0x01F0, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA6__SD3_WP                               = IOMUX_PAD(0x0460, 0x01F0, 2, 0x073C, 2, 0),
-	MX7D_PAD_SD3_DATA6__UART3_DCE_RTS                        = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0700, 4, 0),
-	MX7D_PAD_SD3_DATA6__UART3_DTE_CTS                        = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA6__FLEXCAN2_TX                          = IOMUX_PAD(0x0460, 0x01F0, 4, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA6__GPIO6_IO8                            = IOMUX_PAD(0x0460, 0x01F0, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_DATA7__SD3_DATA7                            = IOMUX_PAD(0x0464, 0x01F4, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA7__NAND_DATA07                          = IOMUX_PAD(0x0464, 0x01F4, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA7__SD3_CD_B                             = IOMUX_PAD(0x0464, 0x01F4, 2, 0x0738, 2, 0),
-	MX7D_PAD_SD3_DATA7__UART3_DCE_CTS                        = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD3_DATA7__UART3_DTE_RTS                        = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0700, 5, 0),
-	MX7D_PAD_SD3_DATA7__FLEXCAN1_RX                          = IOMUX_PAD(0x0464, 0x01F4, 4, 0x04DC, 2, 0),
-	MX7D_PAD_SD3_DATA7__GPIO6_IO9                            = IOMUX_PAD(0x0464, 0x01F4, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_STROBE__SD3_STROBE                          = IOMUX_PAD(0x0468, 0x01F8, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_STROBE__NAND_RE_B                           = IOMUX_PAD(0x0468, 0x01F8, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_STROBE__GPIO6_IO10                          = IOMUX_PAD(0x0468, 0x01F8, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SD3_RESET_B__SD3_RESET_B                        = IOMUX_PAD(0x046C, 0x01FC, 0, 0x0000, 0, 0),
-	MX7D_PAD_SD3_RESET_B__NAND_WE_B                          = IOMUX_PAD(0x046C, 0x01FC, 1, 0x0000, 0, 0),
-	MX7D_PAD_SD3_RESET_B__SD3_RESET                          = IOMUX_PAD(0x046C, 0x01FC, 2, 0x0000, 0, 0),
-	MX7D_PAD_SD3_RESET_B__SAI3_MCLK                          = IOMUX_PAD(0x046C, 0x01FC, 3, 0x0000, 0, 0),
-	MX7D_PAD_SD3_RESET_B__GPIO6_IO11                         = IOMUX_PAD(0x046C, 0x01FC, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0                     = IOMUX_PAD(0x0470, 0x0200, 0, 0x06A0, 0, 0),
-	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B                        = IOMUX_PAD(0x0470, 0x0200, 1, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX                      = IOMUX_PAD(0x0470, 0x0200, 2, 0x0714, 2, 0),
-	MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX                      = IOMUX_PAD(0x0470, 0x0200, 2, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX                       = IOMUX_PAD(0x0470, 0x0200, 3, 0x04DC, 3, 0),
-	MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD                   = IOMUX_PAD(0x0470, 0x0200, 4, 0x06E4, 1, 0),
-	MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12                        = IOMUX_PAD(0x0470, 0x0200, 5, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET                  = IOMUX_PAD(0x0470, 0x0200, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK                      = IOMUX_PAD(0x0474, 0x0204, 0, 0x06A8, 0, 0),
-	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B                        = IOMUX_PAD(0x0474, 0x0204, 1, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX                      = IOMUX_PAD(0x0474, 0x0204, 2, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX                      = IOMUX_PAD(0x0474, 0x0204, 2, 0x0714, 3, 0),
-	MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX                       = IOMUX_PAD(0x0474, 0x0204, 3, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK                    = IOMUX_PAD(0x0474, 0x0204, 4, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13                        = IOMUX_PAD(0x0474, 0x0204, 5, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET                   = IOMUX_PAD(0x0474, 0x0204, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC                      = IOMUX_PAD(0x0478, 0x0208, 0, 0x06AC, 0, 0),
-	MX7D_PAD_SAI1_TX_SYNC__NAND_DQS                          = IOMUX_PAD(0x0478, 0x0208, 1, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS                     = IOMUX_PAD(0x0478, 0x0208, 2, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS                     = IOMUX_PAD(0x0478, 0x0208, 2, 0x0710, 2, 0),
-	MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX                       = IOMUX_PAD(0x0478, 0x0208, 3, 0x04E0, 3, 0),
-	MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B                  = IOMUX_PAD(0x0478, 0x0208, 4, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14                        = IOMUX_PAD(0x0478, 0x0208, 5, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT                      = IOMUX_PAD(0x0478, 0x0208, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0                     = IOMUX_PAD(0x047C, 0x020C, 0, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B                      = IOMUX_PAD(0x047C, 0x020C, 1, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS                     = IOMUX_PAD(0x047C, 0x020C, 2, 0x0710, 3, 0),
-	MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS                     = IOMUX_PAD(0x047C, 0x020C, 2, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX                       = IOMUX_PAD(0x047C, 0x020C, 3, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN                   = IOMUX_PAD(0x047C, 0x020C, 4, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15                        = IOMUX_PAD(0x047C, 0x020C, 5, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET                  = IOMUX_PAD(0x047C, 0x020C, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC                      = IOMUX_PAD(0x0480, 0x0210, 0, 0x06A4, 0, 0),
-	MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B                        = IOMUX_PAD(0x0480, 0x0210, 1, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC                      = IOMUX_PAD(0x0480, 0x0210, 2, 0x06B8, 1, 0),
-	MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL                          = IOMUX_PAD(0x0480, 0x0210, IOMUX_CONFIG_SION | 3, 0x05EC, 3, 0),
-	MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD                     = IOMUX_PAD(0x0480, 0x0210, 4, 0x06E0, 1, 0),
-	MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16                        = IOMUX_PAD(0x0480, 0x0210, 5, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT                         = IOMUX_PAD(0x0480, 0x0210, 6, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0                  = IOMUX_PAD(0x0480, 0x0210, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK                      = IOMUX_PAD(0x0484, 0x0214, 0, 0x069C, 0, 0),
-	MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B                        = IOMUX_PAD(0x0484, 0x0214, 1, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK                      = IOMUX_PAD(0x0484, 0x0214, 2, 0x06B0, 1, 0),
-	MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA                          = IOMUX_PAD(0x0484, 0x0214, IOMUX_CONFIG_SION | 3, 0x05F0, 3, 0),
-	MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA                    = IOMUX_PAD(0x0484, 0x0214, 4, 0x05CC, 1, 0),
-	MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17                        = IOMUX_PAD(0x0484, 0x0214, 5, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT                          = IOMUX_PAD(0x0484, 0x0214, 6, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1                  = IOMUX_PAD(0x0484, 0x0214, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI1_MCLK__SAI1_MCLK                            = IOMUX_PAD(0x0488, 0x0218, 0, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_MCLK__NAND_WP_B                            = IOMUX_PAD(0x0488, 0x0218, 1, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_MCLK__SAI2_MCLK                            = IOMUX_PAD(0x0488, 0x0218, 2, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY                       = IOMUX_PAD(0x0488, 0x0218, 3, 0x04F4, 3, 0),
-	MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB                       = IOMUX_PAD(0x0488, 0x0218, 4, 0x05D0, 1, 0),
-	MX7D_PAD_SAI1_MCLK__GPIO6_IO18                           = IOMUX_PAD(0x0488, 0x0218, 5, 0x0000, 0, 0),
-	MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK                       = IOMUX_PAD(0x0488, 0x0218, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC                      = IOMUX_PAD(0x048C, 0x021C, 0, 0x06C0, 1, 0),
-	MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO                       = IOMUX_PAD(0x048C, 0x021C, 1, 0x0548, 1, 0),
-	MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX                      = IOMUX_PAD(0x048C, 0x021C, 2, 0x070C, 4, 0),
-	MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX                      = IOMUX_PAD(0x048C, 0x021C, 2, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS                     = IOMUX_PAD(0x048C, 0x021C, 3, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS                     = IOMUX_PAD(0x048C, 0x021C, 3, 0x06F0, 0, 0),
-	MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4                    = IOMUX_PAD(0x048C, 0x021C, 4, 0x05BC, 1, 0),
-	MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19                        = IOMUX_PAD(0x048C, 0x021C, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK                      = IOMUX_PAD(0x0490, 0x0220, 0, 0x06BC, 1, 0),
-	MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI                       = IOMUX_PAD(0x0490, 0x0220, 1, 0x054C, 1, 0),
-	MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX                      = IOMUX_PAD(0x0490, 0x0220, 2, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX                      = IOMUX_PAD(0x0490, 0x0220, 2, 0x070C, 5, 0),
-	MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS                     = IOMUX_PAD(0x0490, 0x0220, 3, 0x06F0, 1, 0),
-	MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS                     = IOMUX_PAD(0x0490, 0x0220, 3, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5                    = IOMUX_PAD(0x0490, 0x0220, 4, 0x05C0, 1, 0),
-	MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20                        = IOMUX_PAD(0x0490, 0x0220, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0                     = IOMUX_PAD(0x0494, 0x0224, 0, 0x06B4, 1, 0),
-	MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK                       = IOMUX_PAD(0x0494, 0x0224, 1, 0x0544, 1, 0),
-	MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS                     = IOMUX_PAD(0x0494, 0x0224, 2, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS                     = IOMUX_PAD(0x0494, 0x0224, 2, 0x0708, 4, 0),
-	MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS                     = IOMUX_PAD(0x0494, 0x0224, 3, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS                     = IOMUX_PAD(0x0494, 0x0224, 3, 0x06F8, 2, 0),
-	MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6                    = IOMUX_PAD(0x0494, 0x0224, 4, 0x05C4, 1, 0),
-	MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21                        = IOMUX_PAD(0x0494, 0x0224, 5, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_RX_DATA__KPP_COL7                          = IOMUX_PAD(0x0494, 0x0224, 6, 0x0610, 1, 0),
-
-	MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0                     = IOMUX_PAD(0x0498, 0x0228, 0, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0                        = IOMUX_PAD(0x0498, 0x0228, 1, 0x0550, 1, 0),
-	MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS                     = IOMUX_PAD(0x0498, 0x0228, 2, 0x0708, 5, 0),
-	MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS                     = IOMUX_PAD(0x0498, 0x0228, 2, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS                     = IOMUX_PAD(0x0498, 0x0228, 3, 0x06F8, 3, 0),
-	MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS                     = IOMUX_PAD(0x0498, 0x0228, 3, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7                    = IOMUX_PAD(0x0498, 0x0228, 4, 0x05C8, 1, 0),
-	MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22                        = IOMUX_PAD(0x0498, 0x0228, 5, 0x0000, 0, 0),
-	MX7D_PAD_SAI2_TX_DATA__KPP_ROW7                          = IOMUX_PAD(0x0498, 0x0228, 6, 0x0630, 1, 0),
-
-	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0                = IOMUX_PAD(0x049C, 0x022C, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT                       = IOMUX_PAD(0x049C, 0x022C, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL                       = IOMUX_PAD(0x049C, 0x022C, IOMUX_CONFIG_SION | 2, 0x05E4, 4, 0),
-	MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS                  = IOMUX_PAD(0x049C, 0x022C, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS                  = IOMUX_PAD(0x049C, 0x022C, 3, 0x06F0, 2, 0),
-	MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0                     = IOMUX_PAD(0x049C, 0x022C, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0                      = IOMUX_PAD(0x049C, 0x022C, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3                       = IOMUX_PAD(0x049C, 0x022C, 6, 0x0620, 1, 0),
-
-	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1                = IOMUX_PAD(0x04A0, 0x0230, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT                       = IOMUX_PAD(0x04A0, 0x0230, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA                       = IOMUX_PAD(0x04A0, 0x0230, IOMUX_CONFIG_SION | 2, 0x05E8, 4, 0),
-	MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS                  = IOMUX_PAD(0x04A0, 0x0230, 3, 0x06F0, 3, 0),
-	MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS                  = IOMUX_PAD(0x04A0, 0x0230, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1                     = IOMUX_PAD(0x04A0, 0x0230, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1                      = IOMUX_PAD(0x04A0, 0x0230, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3                       = IOMUX_PAD(0x04A0, 0x0230, 6, 0x0600, 1, 0),
-
-	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2                = IOMUX_PAD(0x04A4, 0x0234, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX                    = IOMUX_PAD(0x04A4, 0x0234, 1, 0x04DC, 4, 0),
-	MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK                    = IOMUX_PAD(0x04A4, 0x0234, 2, 0x0534, 1, 0),
-	MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX                   = IOMUX_PAD(0x04A4, 0x0234, 3, 0x06F4, 2, 0),
-	MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX                   = IOMUX_PAD(0x04A4, 0x0234, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4                     = IOMUX_PAD(0x04A4, 0x0234, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2                      = IOMUX_PAD(0x04A4, 0x0234, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2                       = IOMUX_PAD(0x04A4, 0x0234, 6, 0x061C, 1, 0),
-
-	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3                = IOMUX_PAD(0x04A8, 0x0238, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX                    = IOMUX_PAD(0x04A8, 0x0238, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI                    = IOMUX_PAD(0x04A8, 0x0238, 2, 0x053C, 1, 0),
-	MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX                   = IOMUX_PAD(0x04A8, 0x0238, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX                   = IOMUX_PAD(0x04A8, 0x0238, 3, 0x06F4, 3, 0),
-	MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5                     = IOMUX_PAD(0x04A8, 0x0238, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3                      = IOMUX_PAD(0x04A8, 0x0238, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2                       = IOMUX_PAD(0x04A8, 0x0238, 6, 0x05FC, 1, 0),
-
-	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL          = IOMUX_PAD(0x04AC, 0x023C, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1                  = IOMUX_PAD(0x04AC, 0x023C, 2, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6                  = IOMUX_PAD(0x04AC, 0x023C, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4                   = IOMUX_PAD(0x04AC, 0x023C, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1                    = IOMUX_PAD(0x04AC, 0x023C, 6, 0x0618, 1, 0),
-
-	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC                = IOMUX_PAD(0x04B0, 0x0240, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER                    = IOMUX_PAD(0x04B0, 0x0240, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2                     = IOMUX_PAD(0x04B0, 0x0240, 2, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7                     = IOMUX_PAD(0x04B0, 0x0240, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5                      = IOMUX_PAD(0x04B0, 0x0240, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1                       = IOMUX_PAD(0x04B0, 0x0240, 6, 0x0000, 0, 0),
-
-	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0                = IOMUX_PAD(0x04B4, 0x0244, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT                       = IOMUX_PAD(0x04B4, 0x0244, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3                     = IOMUX_PAD(0x04B4, 0x0244, 2, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8                     = IOMUX_PAD(0x04B4, 0x0244, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6                      = IOMUX_PAD(0x04B4, 0x0244, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0                       = IOMUX_PAD(0x04B4, 0x0244, 6, 0x0614, 1, 0),
-
-	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1                = IOMUX_PAD(0x04B8, 0x0248, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT                       = IOMUX_PAD(0x04B8, 0x0248, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY                     = IOMUX_PAD(0x04B8, 0x0248, 2, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9                     = IOMUX_PAD(0x04B8, 0x0248, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7                      = IOMUX_PAD(0x04B8, 0x0248, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0                       = IOMUX_PAD(0x04B8, 0x0248, 6, 0x05F4, 1, 0),
-
-	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2                = IOMUX_PAD(0x04BC, 0x024C, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX                    = IOMUX_PAD(0x04BC, 0x024C, 1, 0x04E0, 4, 0),
-	MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO                    = IOMUX_PAD(0x04BC, 0x024C, 2, 0x0538, 1, 0),
-	MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL                       = IOMUX_PAD(0x04BC, 0x024C, IOMUX_CONFIG_SION | 3, 0x05EC, 4, 0),
-	MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED                     = IOMUX_PAD(0x04BC, 0x024C, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8                      = IOMUX_PAD(0x04BC, 0x024C, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3                = IOMUX_PAD(0x04C0, 0x0250, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX                    = IOMUX_PAD(0x04C0, 0x0250, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0                     = IOMUX_PAD(0x04C0, 0x0250, 2, 0x0540, 1, 0),
-	MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA                       = IOMUX_PAD(0x04C0, 0x0250, IOMUX_CONFIG_SION | 3, 0x05F0, 4, 0),
-	MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ                     = IOMUX_PAD(0x04C0, 0x0250, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9                      = IOMUX_PAD(0x04C0, 0x0250, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS               = IOMUX_PAD(0x04C0, 0x0250, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL          = IOMUX_PAD(0x04C4, 0x0254, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC                = IOMUX_PAD(0x04C4, 0x0254, 2, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1               = IOMUX_PAD(0x04C4, 0x0254, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2              = IOMUX_PAD(0x04C4, 0x0254, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10                  = IOMUX_PAD(0x04C4, 0x0254, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC                = IOMUX_PAD(0x04C8, 0x0258, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER                    = IOMUX_PAD(0x04C8, 0x0258, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK                   = IOMUX_PAD(0x04C8, 0x0258, 2, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2                  = IOMUX_PAD(0x04C8, 0x0258, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3                 = IOMUX_PAD(0x04C8, 0x0258, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11                     = IOMUX_PAD(0x04C8, 0x0258, 5, 0x0000, 0, 0),
-
-	MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK                      = IOMUX_PAD(0x04CC, 0x025C, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1                 = IOMUX_PAD(0x04CC, 0x025C, 1, 0x0564, 2, 0),
-	MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0                     = IOMUX_PAD(0x04CC, 0x025C, 2, 0x06A0, 1, 0),
-	MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3                     = IOMUX_PAD(0x04CC, 0x025C, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ                      = IOMUX_PAD(0x04CC, 0x025C, 4, 0x057C, 1, 0),
-	MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12                        = IOMUX_PAD(0x04CC, 0x025C, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1                      = IOMUX_PAD(0x04CC, 0x025C, 6, 0x04E4, 2, 0),
-	MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0                    = IOMUX_PAD(0x04CC, 0x025C, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK                      = IOMUX_PAD(0x04D0, 0x0260, 0, 0x056C, 0, 0),
-	MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B                      = IOMUX_PAD(0x04D0, 0x0260, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK                      = IOMUX_PAD(0x04D0, 0x0260, 2, 0x06A8, 1, 0),
-	MX7D_PAD_ENET1_RX_CLK__GPT2_CLK                          = IOMUX_PAD(0x04D0, 0x0260, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE                     = IOMUX_PAD(0x04D0, 0x0260, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13                        = IOMUX_PAD(0x04D0, 0x0260, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2                      = IOMUX_PAD(0x04D0, 0x0260, 6, 0x04E8, 2, 0),
-	MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1                    = IOMUX_PAD(0x04D0, 0x0260, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_ENET1_CRS__ENET1_CRS                            = IOMUX_PAD(0x04D4, 0x0264, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB                 = IOMUX_PAD(0x04D4, 0x0264, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC                         = IOMUX_PAD(0x04D4, 0x0264, 2, 0x06AC, 1, 0),
-	MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1                        = IOMUX_PAD(0x04D4, 0x0264, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0                       = IOMUX_PAD(0x04D4, 0x0264, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_CRS__GPIO7_IO14                           = IOMUX_PAD(0x04D4, 0x0264, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3                         = IOMUX_PAD(0x04D4, 0x0264, 6, 0x04EC, 2, 0),
-	MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2                       = IOMUX_PAD(0x04D4, 0x0264, 7, 0x0000, 0, 0),
-
-	MX7D_PAD_ENET1_COL__ENET1_COL                            = IOMUX_PAD(0x04D8, 0x0268, 0, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY                       = IOMUX_PAD(0x04D8, 0x0268, 1, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_COL__SAI1_TX_DATA0                        = IOMUX_PAD(0x04D8, 0x0268, 2, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_COL__GPT2_CAPTURE2                        = IOMUX_PAD(0x04D8, 0x0268, 3, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1                       = IOMUX_PAD(0x04D8, 0x0268, 4, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_COL__GPIO7_IO15                           = IOMUX_PAD(0x04D8, 0x0268, 5, 0x0000, 0, 0),
-	MX7D_PAD_ENET1_COL__CCM_EXT_CLK4                         = IOMUX_PAD(0x04D8, 0x0268, 6, 0x04F0, 2, 0),
-	MX7D_PAD_ENET1_COL__CSU_INT_DEB                          = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0),
-};
-
-static inline void imx7_setup_pad(iomux_v3_cfg_t pad)
-{
-	void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR);
-	unsigned int flags = 0;
-	uint32_t mode = IOMUX_MODE(pad);
-
-	if (mode & IOMUX_CONFIG_LPSR) {
-		mode &= ~IOMUX_CONFIG_LPSR;
-		flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR;
-	}
-
-	iomux_v3_setup_pad(iomux, flags,
-			   IOMUX_CTRL_OFS(pad),
-			   IOMUX_PAD_CTRL_OFS(pad),
-			   IOMUX_SEL_INPUT_OFS(pad),
-			   mode,
-			   IOMUX_PAD_CTRL(pad),
-			   IOMUX_SEL_INPUT(pad));
-}
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8m.h b/arch/arm/mach-imx/include/mach/iomux-mx8m.h
deleted file mode 100644
index de6675064a..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx8m.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __MACH_IOMUX_IMX8M_H__
-#define __MACH_IOMUX_IMX8M_H__
-
-#include <mach/iomux-v3.h>
-
-#define PAD_CTL_DSE_3P3V_45_OHM	0b110
-
-static inline void imx8m_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad)
-{
-	unsigned int flags = 0;
-	uint32_t mode = IOMUX_MODE(pad);
-
-	if (mode & IOMUX_CONFIG_LPSR) {
-		mode &= ~IOMUX_CONFIG_LPSR;
-		flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR;
-	}
-
-	iomux_v3_setup_pad(iomux, flags,
-			   IOMUX_CTRL_OFS(pad),
-			   IOMUX_PAD_CTRL_OFS(pad),
-			   IOMUX_SEL_INPUT_OFS(pad),
-			   mode,
-			   IOMUX_PAD_CTRL(pad),
-			   IOMUX_SEL_INPUT(pad));
-}
-
-#endif /* __MACH_IOMUX_IMX8MQ_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mm.h b/arch/arm/mach-imx/include/mach/iomux-mx8mm.h
deleted file mode 100644
index f91671865d..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx8mm.h
+++ /dev/null
@@ -1,701 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018-2019 NXP
- */
-
-#ifndef __ASM_ARCH_IMX8MM_PINS_H__
-#define __ASM_ARCH_IMX8MM_PINS_H__
-
-#include <mach/iomux-v3.h>
-#include <mach/imx8mm-regs.h>
-#include <mach/iomux-mx8m.h>
-
-enum {
-	IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0                               =  IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT               =  IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K                     =  IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1                            =  IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1                               =  IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO01_PWM1_OUT                                =  IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M                     =  IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2                            =  IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2                               =  IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B                            =  IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY                          =  IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3                               =  IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT                          =  IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0                        =  IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4                               =  IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT                          =  IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1                        =  IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5                               =  IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI                     =  IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY                          =  IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
-	IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT                            =  IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6                               =  IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO06_ENET1_MDC                               =  IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B                             =  IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3                            =  IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7                               =  IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO                              =  IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
-	IMX8MM_PAD_GPIO1_IO07_USDHC1_WP                               =  IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4                            =  IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8                               =  IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN                    =  IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B                          =  IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO08_CCM_WAIT                                =  IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9                               =  IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT                   =  IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B                          =  IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0                        =  IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO09_CCM_STOP                                =  IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10                              =  IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID                             =  IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11                              =  IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID                             =  IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT                          =  IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY                          =  IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
-	IMX8MM_PAD_GPIO1_IO11_CCM_OUT0                                =  IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12                              =  IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR                            =  IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1                        =  IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO12_CCM_OUT1                                =  IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13                              =  IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC                             =  IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO13_PWM2_OUT                                =  IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO13_CCM_OUT2                                =  IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14                              =  IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR                            =  IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B                             =  IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0),
-	IMX8MM_PAD_GPIO1_IO14_PWM3_OUT                                =  IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1                               =  IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15                              =  IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC                             =  IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO15_USDHC3_WP                               =  IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0),
-	IMX8MM_PAD_GPIO1_IO15_PWM4_OUT                                =  IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2                               =  IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_MDC_ENET1_MDC                                 =  IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_MDC_GPIO1_IO16                                =  IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_MDIO_ENET1_MDIO                               =  IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
-	IMX8MM_PAD_ENET_MDIO_GPIO1_IO17                               =  IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3                           =  IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD3_GPIO1_IO18                                =  IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2                           =  IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK                              =  IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT                     =  IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD2_GPIO1_IO19                                =  IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1                           =  IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD1_GPIO1_IO20                                =  IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0                           =  IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD0_GPIO1_IO21                                =  IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL                     =  IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22                             =  IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC                           =  IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TXC_ENET1_TX_ER                               =  IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TXC_GPIO1_IO23                                =  IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL                     =  IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24                             =  IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC                           =  IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RXC_ENET1_RX_ER                               =  IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RXC_GPIO1_IO25                                =  IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0                           =  IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RD0_GPIO1_IO26                                =  IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1                           =  IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RD1_GPIO1_IO27                                =  IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2                           =  IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RD2_GPIO1_IO28                                =  IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3                           =  IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RD3_GPIO1_IO29                                =  IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_CLK_USDHC1_CLK                                 =  IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_CLK_GPIO2_IO0                                  =  IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_CMD_USDHC1_CMD                                 =  IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_CMD_GPIO2_IO1                                  =  IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0                             =  IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA0_GPIO2_IO2                                =  IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1                             =  IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA1_GPIO2_IO3                                =  IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2                             =  IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA2_GPIO2_IO4                                =  IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3                             =  IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA3_GPIO2_IO5                                =  IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4                             =  IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA4_GPIO2_IO6                                =  IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5                             =  IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA5_GPIO2_IO7                                =  IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6                             =  IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA6_GPIO2_IO8                                =  IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7                             =  IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA7_GPIO2_IO9                                =  IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B                         =  IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10                             =  IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE                           =  IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_STROBE_GPIO2_IO11                              =  IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B                               =  IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CD_B_GPIO2_IO12                                =  IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_CLK_USDHC2_CLK                                 =  IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CLK_GPIO2_IO13                                 =  IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0                               =  IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_CMD_USDHC2_CMD                                 =  IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CMD_GPIO2_IO14                                 =  IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1                               =  IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0                             =  IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA0_GPIO2_IO15                               =  IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2                             =  IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1                             =  IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA1_GPIO2_IO16                               =  IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA1_CCM_WAIT                                 =  IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2                             =  IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA2_GPIO2_IO17                               =  IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA2_CCM_STOP                                 =  IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3                             =  IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA3_GPIO2_IO18                               =  IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET                          =  IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B                         =  IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19                             =  IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET                       =  IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_WP_USDHC2_WP                                   =  IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_WP_GPIO2_IO20                                  =  IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_ALE_RAWNAND_ALE                               =  IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK                               =  IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_ALE_GPIO3_IO0                                 =  IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B                           =  IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B                            =  IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1                               =  IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B                           =  IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B                            =  IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE                           =  IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2                               =  IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B                           =  IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B                            =  IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5                            =  IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3                               =  IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B                           =  IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B                            =  IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6                            =  IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4                               =  IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CLE_RAWNAND_CLE                               =  IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK                               =  IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CLE_USDHC3_DATA7                              =  IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CLE_GPIO3_IO5                                 =  IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00                         =  IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0                           =  IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA00_GPIO3_IO6                              =  IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01                         =  IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1                           =  IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA01_GPIO3_IO7                              =  IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02                         =  IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2                           =  IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B                            =  IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0),
-	IMX8MM_PAD_NAND_DATA02_GPIO3_IO8                              =  IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03                         =  IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3                           =  IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA03_USDHC3_WP                              =  IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0),
-	IMX8MM_PAD_NAND_DATA03_GPIO3_IO9                              =  IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04                         =  IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0                           =  IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0                           =  IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA04_GPIO3_IO10                             =  IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05                         =  IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1                           =  IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1                           =  IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA05_GPIO3_IO11                             =  IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06                         =  IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2                           =  IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2                           =  IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA06_GPIO3_IO12                             =  IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07                         =  IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3                           =  IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3                           =  IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA07_GPIO3_IO13                             =  IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DQS_RAWNAND_DQS                               =  IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DQS_QSPI_A_DQS                                =  IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DQS_GPIO3_IO14                                =  IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B                             =  IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS                               =  IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4                             =  IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_RE_B_GPIO3_IO15                               =  IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B                       =  IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B                        =  IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_READY_B_GPIO3_IO16                            =  IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B                             =  IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_WE_B_USDHC3_CLK                               =  IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_WE_B_GPIO3_IO17                               =  IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B                             =  IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_WP_B_USDHC3_CMD                               =  IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_WP_B_GPIO3_IO18                               =  IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
-	IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0                            =  IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19                               =  IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
-	IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1                             =  IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXC_PDM_CLK                                   =  IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXC_GPIO3_IO20                                =  IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0                            =  IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
-	IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2                            =  IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0                          =  IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0),
-	IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21                               =  IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1                            =  IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3                            =  IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC                             =  IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1                          =  IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22                               =  IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2                            =  IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
-	IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4                            =  IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
-	IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK                             =  IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
-	IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2                          =  IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0),
-	IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23                               =  IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3                            =  IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
-	IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5                            =  IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
-	IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0                            =  IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3                          =  IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0),
-	IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24                               =  IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
-	IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK                             =  IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
-	IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25                               =  IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK                           =  IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC                             =  IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
-	IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
-	IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK                   =  IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0                                =  IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK                              =  IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
-	IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL                    =  IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXC_GPIO4_IO1                                 =  IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0                            =  IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0                            =  IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
-	IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1                            =  IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0                          =  IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0),
-	IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0                      =  IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2                                =  IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0                            =  IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1                            =  IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1                            =  IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
-	IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1                          =  IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0),
-	IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1                      =  IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3                                =  IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1                            =  IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2                            =  IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2                            =  IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
-	IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2                          =  IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0),
-	IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2                      =  IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4                                =  IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2                            =  IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3                            =  IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3                            =  IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0),
-	IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3                          =  IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0),
-	IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3                      =  IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5                                =  IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3                            =  IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4                            =  IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK                             =  IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK                             =  IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4                      =  IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6                                =  IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4                            =  IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5                            =  IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0                            =  IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0                            =  IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC                             =  IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
-	IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5                      =  IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7                                =  IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5                            =  IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6                            =  IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC                             =  IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC                             =  IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6                      =  IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8                                =  IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6                            =  IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7                            =  IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK                                =  IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
-	IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4                            =  IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7                      =  IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9                                =  IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7                            =  IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
-	IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC                             =  IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
-	IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO                      =  IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10                               =  IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK                              =  IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
-	IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK                              =  IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
-	IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI                       =  IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXC_GPIO4_IO11                                =  IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0                            =  IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0                            =  IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8                      =  IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12                               =  IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8                            =  IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1                            =  IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1                            =  IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9                      =  IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13                               =  IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9                            =  IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2                            =  IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2                            =  IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10                     =  IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14                               =  IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10                           =  IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3                            =  IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3                            =  IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11                     =  IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15                               =  IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11                           =  IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4                            =  IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK                             =  IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
-	IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK                             =  IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
-	IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12                     =  IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16                               =  IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12                           =  IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5                            =  IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0                            =  IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
-	IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0                            =  IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13                     =  IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17                               =  IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13                           =  IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6                            =  IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC                             =  IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
-	IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC                             =  IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
-	IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14                     =  IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18                               =  IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14                           =  IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7                            =  IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK                                =  IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
-	IMX8MM_PAD_SAI1_TXD7_PDM_CLK                                  =  IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15                     =  IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19                               =  IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15                           =  IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK                                =  IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
-	IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK                             =  IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
-	IMX8MM_PAD_SAI1_MCLK_PDM_CLK                                  =  IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20                               =  IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC                             =  IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC                             =  IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
-	IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1                            =  IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1                            =  IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXFS_UART1_TX                                 =  IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXFS_UART1_RX                                 =  IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0),
-	IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21                               =  IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK                              =  IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK                              =  IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
-	IMX8MM_PAD_SAI2_RXC_UART1_RX                                  =  IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0),
-	IMX8MM_PAD_SAI2_RXC_UART1_TX                                  =  IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXC_GPIO4_IO22                                =  IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0                            =  IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0                            =  IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B                              =  IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0),
-	IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B                              =  IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23                               =  IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC                             =  IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1                            =  IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1                            =  IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B                              =  IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B                              =  IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0),
-	IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24                               =  IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK                              =  IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2                             =  IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXC_GPIO4_IO25                                =  IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0                            =  IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3                            =  IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26                               =  IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK                                =  IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
-	IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27                               =  IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC                             =  IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1                            =  IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
-	IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1                            =  IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28                               =  IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK                              =  IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXC_GPT1_CLK                                  =  IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
-	IMX8MM_PAD_SAI3_RXC_UART2_CTS_B                               =  IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXC_UART2_RTS_B                               =  IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0),
-	IMX8MM_PAD_SAI3_RXC_GPIO4_IO29                                =  IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0                             =  IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1                             =  IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0                             =  IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
-	IMX8MM_PAD_SAI3_RXD_UART2_RTS_B                               =  IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0),
-	IMX8MM_PAD_SAI3_RXD_UART2_CTS_B                               =  IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXD_GPIO4_IO30                                =  IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC                             =  IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2                            =  IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1                            =  IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
-	IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1                            =  IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXFS_UART2_RX                                 =  IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0),
-	IMX8MM_PAD_SAI3_TXFS_UART2_TX                                 =  IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31                               =  IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK                              =  IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2                             =  IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2                             =  IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
-	IMX8MM_PAD_SAI3_TXC_UART2_TX                                  =  IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXC_UART2_RX                                  =  IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0),
-	IMX8MM_PAD_SAI3_TXC_GPIO5_IO0                                 =  IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0                             =  IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3                             =  IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3                             =  IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
-	IMX8MM_PAD_SAI3_TXD_GPIO5_IO1                                 =  IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK                                =  IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_MCLK_PWM4_OUT                                 =  IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
-	IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2                                =  IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT                                =  IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_TX_PWM3_OUT                                  =  IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_TX_GPIO5_IO3                                 =  IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SPDIF_RX_SPDIF1_IN                                 =  IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_RX_PWM2_OUT                                  =  IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_RX_GPIO5_IO4                                 =  IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK                       =  IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT                             =  IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5                            =  IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK                            =  IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_SCLK_UART3_RX                               =  IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
-	IMX8MM_PAD_ECSPI1_SCLK_UART3_TX                               =  IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6                              =  IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI                            =  IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_MOSI_UART3_TX                               =  IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_MOSI_UART3_RX                               =  IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
-	IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7                              =  IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO                            =  IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B                            =  IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B                            =  IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
-	IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8                              =  IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0                              =  IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B                             =  IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
-	IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B                             =  IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9                               =  IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK                            =  IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_SCLK_UART4_RX                               =  IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
-	IMX8MM_PAD_ECSPI2_SCLK_UART4_TX                               =  IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10                             =  IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI                            =  IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_MOSI_UART4_TX                               =  IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_MOSI_UART4_RX                               =  IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
-	IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11                             =  IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO                            =  IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B                            =  IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B                            =  IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
-	IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12                             =  IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0                              =  IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B                             =  IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
-	IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B                             =  IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13                              =  IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C1_SCL_I2C1_SCL                                  =  IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C1_SCL_ENET1_MDC                                 =  IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C1_SCL_GPIO5_IO14                                =  IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C1_SDA_I2C1_SDA                                  =  IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C1_SDA_ENET1_MDIO                                =  IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
-	IMX8MM_PAD_I2C1_SDA_GPIO5_IO15                                =  IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C2_SCL_I2C2_SCL                                  =  IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN                      =  IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B                               =  IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0),
-	IMX8MM_PAD_I2C2_SCL_GPIO5_IO16                                =  IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C2_SDA_I2C2_SDA                                  =  IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT                     =  IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C2_SDA_USDHC3_WP                                 =  IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0),
-	IMX8MM_PAD_I2C2_SDA_GPIO5_IO17                                =  IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C3_SCL_I2C3_SCL                                  =  IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SCL_PWM4_OUT                                  =  IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SCL_GPT2_CLK                                  =  IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SCL_GPIO5_IO18                                =  IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C3_SDA_I2C3_SDA                                  =  IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SDA_PWM3_OUT                                  =  IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SDA_GPT3_CLK                                  =  IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SDA_GPIO5_IO19                                =  IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C4_SCL_I2C4_SCL                                  =  IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C4_SCL_PWM2_OUT                                  =  IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B                            =  IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
-	IMX8MM_PAD_I2C4_SCL_GPIO5_IO20                                =  IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C4_SDA_I2C4_SDA                                  =  IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C4_SDA_PWM1_OUT                                  =  IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C4_SDA_GPIO5_IO21                                =  IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART1_RXD_UART1_RX                                 =  IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
-	IMX8MM_PAD_UART1_RXD_UART1_TX                                 =  IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK                              =  IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART1_RXD_GPIO5_IO22                               =  IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART1_TXD_UART1_TX                                 =  IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART1_TXD_UART1_RX                                 =  IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0),
-	IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI                              =  IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART1_TXD_GPIO5_IO23                               =  IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART2_RXD_UART2_RX                                 =  IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
-	IMX8MM_PAD_UART2_RXD_UART2_TX                                 =  IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART2_RXD_ECSPI3_MISO                              =  IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART2_RXD_GPIO5_IO24                               =  IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART2_TXD_UART2_TX                                 =  IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART2_TXD_UART2_RX                                 =  IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0),
-	IMX8MM_PAD_UART2_TXD_ECSPI3_SS0                               =  IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART2_TXD_GPIO5_IO25                               =  IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART3_RXD_UART3_RX                                 =  IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
-	IMX8MM_PAD_UART3_RXD_UART3_TX                                 =  IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_RXD_UART1_CTS_B                              =  IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_RXD_UART1_RTS_B                              =  IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
-	IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B                           =  IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_RXD_GPIO5_IO26                               =  IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART3_TXD_UART3_TX                                 =  IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_TXD_UART3_RX                                 =  IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0),
-	IMX8MM_PAD_UART3_TXD_UART1_RTS_B                              =  IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
-	IMX8MM_PAD_UART3_TXD_UART1_CTS_B                              =  IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT                           =  IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_TXD_GPIO5_IO27                               =  IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART4_RXD_UART4_RX                                 =  IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
-	IMX8MM_PAD_UART4_RXD_UART4_TX                                 =  IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART4_RXD_UART2_CTS_B                              =  IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART4_RXD_UART2_RTS_B                              =  IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
-	IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B                           =  IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
-	IMX8MM_PAD_UART4_RXD_GPIO5_IO28                               =  IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART4_TXD_UART4_TX                                 =  IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART4_TXD_UART4_RX                                 =  IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0),
-	IMX8MM_PAD_UART4_TXD_UART2_RTS_B                              =  IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
-	IMX8MM_PAD_UART4_TXD_UART2_CTS_B                              =  IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART4_TXD_GPIO5_IO29                               =  IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
-};
-
-static inline void imx8mm_setup_pad(iomux_v3_cfg_t pad)
-{
-	void __iomem *iomux = IOMEM(MX8MM_IOMUXC_BASE_ADDR);
-
-	imx8m_setup_pad(iomux, pad);
-}
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mp.h b/arch/arm/mach-imx/include/mach/iomux-mx8mp.h
deleted file mode 100644
index 2607ba21f6..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx8mp.h
+++ /dev/null
@@ -1,1103 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2019 NXP
- */
-
-#ifndef __ASM_ARCH_IMX8MP_PINS_H__
-#define __ASM_ARCH_IMX8MP_PINS_H__
-
-#include <mach/iomux-v3.h>
-#include <mach/imx8mp-regs.h>
-#include <mach/iomux-mx8m.h>
-
-enum {
-	MX8MP_PAD_GPIO1_IO00__GPIO1_IO00                         = IOMUX_PAD(0x0274, 0x0014, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0274, 0x0014, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0             = IOMUX_PAD(0x0274, 0x0014, 3, 0x05D4, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__ANAMIX_REF_CLK_32K                 = IOMUX_PAD(0x0274, 0x0014, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1              = IOMUX_PAD(0x0274, 0x0014, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__SJC_FAIL                           = IOMUX_PAD(0x0274, 0x0014, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO01__GPIO1_IO01                         = IOMUX_PAD(0x0278, 0x0018, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO01__PWM1_OUT                           = IOMUX_PAD(0x0278, 0x0018, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0        = IOMUX_PAD(0x0278, 0x0018, 3, 0x05DC, 0, 0),
-	MX8MP_PAD_GPIO1_IO01__ANAMIX_REF_CLK_24M                 = IOMUX_PAD(0x0278, 0x0018, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2              = IOMUX_PAD(0x0278, 0x0018, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO01__SJC_ACTIVE                         = IOMUX_PAD(0x0278, 0x0018, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO02__GPIO1_IO02                         = IOMUX_PAD(0x027C, 0x001C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B                       = IOMUX_PAD(0x027C, 0x001C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0          = IOMUX_PAD(0x027C, 0x001C, 3, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x027C, 0x001C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO02__SJC_DE_B                           = IOMUX_PAD(0x027C, 0x001C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO03__GPIO1_IO03                         = IOMUX_PAD(0x0280, 0x0020, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO03__USDHC1_VSELECT                     = IOMUX_PAD(0x0280, 0x0020, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0       = IOMUX_PAD(0x0280, 0x0020, 3, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO03__SDMA1_EXT_EVENT00                  = IOMUX_PAD(0x0280, 0x0020, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO03__ANAMIX_XTAL_OK                     = IOMUX_PAD(0x0280, 0x0020, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO03__SJC_DONE                           = IOMUX_PAD(0x0280, 0x0020, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO04__GPIO1_IO04                         = IOMUX_PAD(0x0284, 0x0024, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO04__USDHC2_VSELECT                     = IOMUX_PAD(0x0284, 0x0024, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0        = IOMUX_PAD(0x0284, 0x0024, 3, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO04__SDMA1_EXT_EVENT01                  = IOMUX_PAD(0x0284, 0x0024, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO04__ANAMIX_XTAL_OK_LV                  = IOMUX_PAD(0x0284, 0x0024, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO04__USDHC1_TEST_TRIG                   = IOMUX_PAD(0x0284, 0x0024, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO05__GPIO1_IO05                         = IOMUX_PAD(0x0288, 0x0028, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO05__M7_NMI                             = IOMUX_PAD(0x0288, 0x0028, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1             = IOMUX_PAD(0x0288, 0x0028, 3, 0x05D8, 0, 0),
-	MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY            = IOMUX_PAD(0x0288, 0x0028, 5, 0x0554, 0, 0),
-	MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT              = IOMUX_PAD(0x0288, 0x0028, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO05__USDHC2_TEST_TRIG                   = IOMUX_PAD(0x0288, 0x0028, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO06__GPIO1_IO06                         = IOMUX_PAD(0x028C, 0x002C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO06__ENET_QOS_MDC                       = IOMUX_PAD(0x028C, 0x002C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1        = IOMUX_PAD(0x028C, 0x002C, 3, 0x05E0, 0, 0),
-	MX8MP_PAD_GPIO1_IO06__USDHC1_CD_B                        = IOMUX_PAD(0x028C, 0x002C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3              = IOMUX_PAD(0x028C, 0x002C, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO06__ECSPI1_TEST_TRIG                   = IOMUX_PAD(0x028C, 0x002C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO07__GPIO1_IO07                         = IOMUX_PAD(0x0290, 0x0030, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO07__ENET_QOS_MDIO                      = IOMUX_PAD(0x0290, 0x0030, 1, 0x0590, 0, 0),
-	MX8MP_PAD_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1          = IOMUX_PAD(0x0290, 0x0030, 3, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO07__USDHC1_WP                          = IOMUX_PAD(0x0290, 0x0030, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4              = IOMUX_PAD(0x0290, 0x0030, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO07__ECSPI2_TEST_TRIG                   = IOMUX_PAD(0x0290, 0x0030, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO08__GPIO1_IO08                         = IOMUX_PAD(0x0294, 0x0034, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN            = IOMUX_PAD(0x0294, 0x0034, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__PWM1_OUT                           = IOMUX_PAD(0x0294, 0x0034, 2, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1       = IOMUX_PAD(0x0294, 0x0034, 3, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN        = IOMUX_PAD(0x0294, 0x0034, 4, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__USDHC2_RESET_B                     = IOMUX_PAD(0x0294, 0x0034, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__CCMSRCGPCMIX_WAIT                  = IOMUX_PAD(0x0294, 0x0034, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__FLEXSPI_TEST_TRIG                  = IOMUX_PAD(0x0294, 0x0034, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO09__GPIO1_IO09                         = IOMUX_PAD(0x0298, 0x0038, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT           = IOMUX_PAD(0x0298, 0x0038, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__PWM2_OUT                           = IOMUX_PAD(0x0298, 0x0038, 2, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1        = IOMUX_PAD(0x0298, 0x0038, 3, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__USDHC3_RESET_B                     = IOMUX_PAD(0x0298, 0x0038, 4, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__AUDIOMIX_EXT_EVENT00               = IOMUX_PAD(0x0298, 0x0038, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__CCMSRCGPCMIX_STOP                  = IOMUX_PAD(0x0298, 0x0038, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__RAWNAND_TEST_TRIG                  = IOMUX_PAD(0x0298, 0x0038, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO10__GPIO1_IO10                         = IOMUX_PAD(0x029C, 0x003C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO10__HSIOMIX_usb1_OTG_ID                = IOMUX_PAD(0x029C, 0x003C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO10__PWM3_OUT                           = IOMUX_PAD(0x029C, 0x003C, 2, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO10__OCOTP_FUSE_LATCHED                 = IOMUX_PAD(0x029C, 0x003C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO11__GPIO1_IO11                         = IOMUX_PAD(0x02A0, 0x0040, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO11__HSIOMIX_usb2_OTG_ID                = IOMUX_PAD(0x02A0, 0x0040, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO11__PWM2_OUT                           = IOMUX_PAD(0x02A0, 0x0040, 2, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO11__USDHC3_VSELECT                     = IOMUX_PAD(0x02A0, 0x0040, 4, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY            = IOMUX_PAD(0x02A0, 0x0040, 5, 0x0554, 1, 0),
-	MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_OUT0                  = IOMUX_PAD(0x02A0, 0x0040, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO11__CAAM_RNG_OSC_OBS                   = IOMUX_PAD(0x02A0, 0x0040, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO12__GPIO1_IO12                         = IOMUX_PAD(0x02A4, 0x0044, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR               = IOMUX_PAD(0x02A4, 0x0044, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO12__AUDIOMIX_EXT_EVENT01               = IOMUX_PAD(0x02A4, 0x0044, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO12__CCMSRCGPCMIX_OUT1                  = IOMUX_PAD(0x02A4, 0x0044, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT00                = IOMUX_PAD(0x02A4, 0x0044, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO13__GPIO1_IO13                         = IOMUX_PAD(0x02A8, 0x0048, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO13__HSIOMIX_usb1_OTG_OC                = IOMUX_PAD(0x02A8, 0x0048, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO13__PWM2_OUT                           = IOMUX_PAD(0x02A8, 0x0048, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO13__CCMSRCGPCMIX_OUT2                  = IOMUX_PAD(0x02A8, 0x0048, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT01                = IOMUX_PAD(0x02A8, 0x0048, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO14__GPIO1_IO14                         = IOMUX_PAD(0x02AC, 0x004C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR               = IOMUX_PAD(0x02AC, 0x004C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO14__USDHC3_CD_B                        = IOMUX_PAD(0x02AC, 0x004C, 4, 0x0608, 0, 0),
-	MX8MP_PAD_GPIO1_IO14__PWM3_OUT                           = IOMUX_PAD(0x02AC, 0x004C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO14__CCMSRCGPCMIX_CLKO1                 = IOMUX_PAD(0x02AC, 0x004C, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT02                = IOMUX_PAD(0x02AC, 0x004C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_GPIO1_IO15__GPIO1_IO15                         = IOMUX_PAD(0x02B0, 0x0050, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO15__HSIOMIX_usb2_OTG_OC                = IOMUX_PAD(0x02B0, 0x0050, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO15__USDHC3_WP                          = IOMUX_PAD(0x02B0, 0x0050, 4, 0x0634, 0, 0),
-	MX8MP_PAD_GPIO1_IO15__PWM4_OUT                           = IOMUX_PAD(0x02B0, 0x0050, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO15__CCMSRCGPCMIX_CLKO2                 = IOMUX_PAD(0x02B0, 0x0050, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO15__CSU_CSU_INT_DEB                    = IOMUX_PAD(0x02B0, 0x0050, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_MDC__ENET_QOS_MDC                         = IOMUX_PAD(0x02B4, 0x0054, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00              = IOMUX_PAD(0x02B4, 0x0054, 2, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_MDC__GPIO1_IO16                           = IOMUX_PAD(0x02B4, 0x0054, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_MDC__USDHC3_STROBE                        = IOMUX_PAD(0x02B4, 0x0054, 6, 0x0630, 0, 0),
-	MX8MP_PAD_ENET_MDC__SIM_M_HADDR15                        = IOMUX_PAD(0x02B4, 0x0054, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_MDIO__ENET_QOS_MDIO                       = IOMUX_PAD(0x02B8, 0x0058, 0, 0x0590, 1, 0),
-	MX8MP_PAD_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC               = IOMUX_PAD(0x02B8, 0x0058, 2, 0x0528, 0, 0),
-	MX8MP_PAD_ENET_MDIO__GPIO1_IO17                          = IOMUX_PAD(0x02B8, 0x0058, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_MDIO__USDHC3_DATA5                        = IOMUX_PAD(0x02B8, 0x0058, 6, 0x0624, 0, 0),
-	MX8MP_PAD_ENET_MDIO__SIM_M_HADDR16                       = IOMUX_PAD(0x02B8, 0x0058, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_TD3__ENET_QOS_RGMII_TD3                   = IOMUX_PAD(0x02BC, 0x005C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK                = IOMUX_PAD(0x02BC, 0x005C, 2, 0x0524, 0, 0),
-	MX8MP_PAD_ENET_TD3__GPIO1_IO18                           = IOMUX_PAD(0x02BC, 0x005C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TD3__USDHC3_DATA6                         = IOMUX_PAD(0x02BC, 0x005C, 6, 0x0628, 0, 0),
-	MX8MP_PAD_ENET_TD3__SIM_M_HADDR17                        = IOMUX_PAD(0x02BC, 0x005C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_TD2__ENET_QOS_RGMII_TD2                   = IOMUX_PAD(0x02C0, 0x0060, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK  = IOMUX_PAD(0x02C0, 0x0060, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00              = IOMUX_PAD(0x02C0, 0x0060, 2, 0x051C, 0, 0),
-	MX8MP_PAD_ENET_TD2__GPIO1_IO19                           = IOMUX_PAD(0x02C0, 0x0060, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TD2__USDHC3_DATA7                         = IOMUX_PAD(0x02C0, 0x0060, 6, 0x062C, 0, 0),
-	MX8MP_PAD_ENET_TD2__SIM_M_HADDR18                        = IOMUX_PAD(0x02C0, 0x0060, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_TD1__ENET_QOS_RGMII_TD1                   = IOMUX_PAD(0x02C4, 0x0064, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC                = IOMUX_PAD(0x02C4, 0x0064, 2, 0x0520, 0, 0),
-	MX8MP_PAD_ENET_TD1__GPIO1_IO20                           = IOMUX_PAD(0x02C4, 0x0064, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TD1__USDHC3_CD_B                          = IOMUX_PAD(0x02C4, 0x0064, 6, 0x0608, 1, 0),
-	MX8MP_PAD_ENET_TD1__SIM_M_HADDR19                        = IOMUX_PAD(0x02C4, 0x0064, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_TD0__ENET_QOS_RGMII_TD0                   = IOMUX_PAD(0x02C8, 0x0068, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK                = IOMUX_PAD(0x02C8, 0x0068, 2, 0x0518, 0, 0),
-	MX8MP_PAD_ENET_TD0__GPIO1_IO21                           = IOMUX_PAD(0x02C8, 0x0068, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TD0__USDHC3_WP                            = IOMUX_PAD(0x02C8, 0x0068, 6, 0x0634, 1, 0),
-	MX8MP_PAD_ENET_TD0__SIM_M_HADDR20                        = IOMUX_PAD(0x02C8, 0x0068, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL             = IOMUX_PAD(0x02CC, 0x006C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK                = IOMUX_PAD(0x02CC, 0x006C, 2, 0x0514, 0, 0),
-	MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT                = IOMUX_PAD(0x02CC, 0x006C, 3, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TX_CTL__GPIO1_IO22                        = IOMUX_PAD(0x02CC, 0x006C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TX_CTL__USDHC3_DATA0                      = IOMUX_PAD(0x02CC, 0x006C, 6, 0x0610, 0, 0),
-	MX8MP_PAD_ENET_TX_CTL__SIM_M_HADDR21                     = IOMUX_PAD(0x02CC, 0x006C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK   = IOMUX_PAD(0x02D0, 0x0070, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TXC__ENET_QOS_TX_ER                       = IOMUX_PAD(0x02D0, 0x0070, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00              = IOMUX_PAD(0x02D0, 0x0070, 2, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TXC__GPIO1_IO23                           = IOMUX_PAD(0x02D0, 0x0070, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_TXC__USDHC3_DATA1                         = IOMUX_PAD(0x02D0, 0x0070, 6, 0x0614, 0, 0),
-	MX8MP_PAD_ENET_TXC__SIM_M_HADDR22                        = IOMUX_PAD(0x02D0, 0x0070, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL             = IOMUX_PAD(0x02D4, 0x0074, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC             = IOMUX_PAD(0x02D4, 0x0074, 2, 0x0540, 0, 0),
-	MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03             = IOMUX_PAD(0x02D4, 0x0074, 3, 0x04CC, 0, 0),
-	MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24                        = IOMUX_PAD(0x02D4, 0x0074, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RX_CTL__USDHC3_DATA2                      = IOMUX_PAD(0x02D4, 0x0074, 6, 0x0618, 0, 0),
-	MX8MP_PAD_ENET_RX_CTL__SIM_M_HADDR23                     = IOMUX_PAD(0x02D4, 0x0074, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK   = IOMUX_PAD(0x02D8, 0x0078, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RXC__ENET_QOS_RX_ER                       = IOMUX_PAD(0x02D8, 0x0078, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK                = IOMUX_PAD(0x02D8, 0x0078, 2, 0x053C, 0, 0),
-	MX8MP_PAD_ENET_RXC__AUDIOMIX_BIT_STREAM02                = IOMUX_PAD(0x02D8, 0x0078, 3, 0x04C8, 0, 0),
-	MX8MP_PAD_ENET_RXC__GPIO1_IO25                           = IOMUX_PAD(0x02D8, 0x0078, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RXC__USDHC3_DATA3                         = IOMUX_PAD(0x02D8, 0x0078, 6, 0x061C, 0, 0),
-	MX8MP_PAD_ENET_RXC__SIM_M_HADDR24                        = IOMUX_PAD(0x02D8, 0x0078, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_RD0__ENET_QOS_RGMII_RD0                   = IOMUX_PAD(0x02DC, 0x007C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00              = IOMUX_PAD(0x02DC, 0x007C, 2, 0x0534, 0, 0),
-	MX8MP_PAD_ENET_RD0__AUDIOMIX_BIT_STREAM01                = IOMUX_PAD(0x02DC, 0x007C, 3, 0x04C4, 0, 0),
-	MX8MP_PAD_ENET_RD0__GPIO1_IO26                           = IOMUX_PAD(0x02DC, 0x007C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD0__USDHC3_DATA4                         = IOMUX_PAD(0x02DC, 0x007C, 6, 0x0620, 0, 0),
-	MX8MP_PAD_ENET_RD0__SIM_M_HADDR25                        = IOMUX_PAD(0x02DC, 0x007C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_RD1__ENET_QOS_RGMII_RD1                   = IOMUX_PAD(0x02E0, 0x0080, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC                = IOMUX_PAD(0x02E0, 0x0080, 2, 0x0538, 0, 0),
-	MX8MP_PAD_ENET_RD1__AUDIOMIX_BIT_STREAM00                = IOMUX_PAD(0x02E0, 0x0080, 3, 0x04C0, 0, 0),
-	MX8MP_PAD_ENET_RD1__GPIO1_IO27                           = IOMUX_PAD(0x02E0, 0x0080, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD1__USDHC3_RESET_B                       = IOMUX_PAD(0x02E0, 0x0080, 6, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD1__SIM_M_HADDR26                        = IOMUX_PAD(0x02E0, 0x0080, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_RD2__ENET_QOS_RGMII_RD2                   = IOMUX_PAD(0x02E4, 0x0084, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK                = IOMUX_PAD(0x02E4, 0x0084, 2, 0x0530, 0, 0),
-	MX8MP_PAD_ENET_RD2__AUDIOMIX_CLK                         = IOMUX_PAD(0x02E4, 0x0084, 3, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD2__GPIO1_IO28                           = IOMUX_PAD(0x02E4, 0x0084, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD2__USDHC3_CLK                           = IOMUX_PAD(0x02E4, 0x0084, 6, 0x0604, 0, 0),
-	MX8MP_PAD_ENET_RD2__SIM_M_HADDR27                        = IOMUX_PAD(0x02E4, 0x0084, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ENET_RD3__ENET_QOS_RGMII_RD3                   = IOMUX_PAD(0x02E8, 0x0088, 0, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD3__AUDIOMIX_SAI7_MCLK                   = IOMUX_PAD(0x02E8, 0x0088, 2, 0x052C, 0, 0),
-	MX8MP_PAD_ENET_RD3__AUDIOMIX_SPDIF_IN                    = IOMUX_PAD(0x02E8, 0x0088, 3, 0x0544, 0, 0),
-	MX8MP_PAD_ENET_RD3__GPIO1_IO29                           = IOMUX_PAD(0x02E8, 0x0088, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD3__USDHC3_CMD                           = IOMUX_PAD(0x02E8, 0x0088, 6, 0x060C, 0, 0),
-	MX8MP_PAD_ENET_RD3__SIM_M_HADDR28                        = IOMUX_PAD(0x02E8, 0x0088, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_CLK__USDHC1_CLK                            = IOMUX_PAD(0x02EC, 0x008C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_CLK__ENET1_MDC                             = IOMUX_PAD(0x02EC, 0x008C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_CLK__I2C5_SCL                              = IOMUX_PAD(0x02EC, 0x008C, 3 | IOMUX_CONFIG_SION, 0x05C4, 0, 0),
-	MX8MP_PAD_SD1_CLK__UART1_DCE_TX                          = IOMUX_PAD(0x02EC, 0x008C, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_CLK__UART1_DTE_RX                          = IOMUX_PAD(0x02EC, 0x008C, 4, 0x05E8, 0, 0),
-	MX8MP_PAD_SD1_CLK__GPIO2_IO00                            = IOMUX_PAD(0x02EC, 0x008C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_CLK__SIM_M_HADDR29                         = IOMUX_PAD(0x02EC, 0x008C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_CMD__USDHC1_CMD                            = IOMUX_PAD(0x02F0, 0x0090, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_CMD__ENET1_MDIO                            = IOMUX_PAD(0x02F0, 0x0090, 1, 0x057C, 0, 0),
-	MX8MP_PAD_SD1_CMD__I2C5_SDA                              = IOMUX_PAD(0x02F0, 0x0090, 3 | IOMUX_CONFIG_SION, 0x05C8, 0, 0),
-	MX8MP_PAD_SD1_CMD__UART1_DCE_RX                          = IOMUX_PAD(0x02F0, 0x0090, 4, 0x05E8, 1, 0),
-	MX8MP_PAD_SD1_CMD__UART1_DTE_TX                          = IOMUX_PAD(0x02F0, 0x0090, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_CMD__GPIO2_IO01                            = IOMUX_PAD(0x02F0, 0x0090, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_CMD__SIM_M_HADDR30                         = IOMUX_PAD(0x02F0, 0x0090, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_DATA0__USDHC1_DATA0                        = IOMUX_PAD(0x02F4, 0x0094, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA0__ENET1_RGMII_TD1                     = IOMUX_PAD(0x02F4, 0x0094, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA0__I2C6_SCL                            = IOMUX_PAD(0x02F4, 0x0094, 3 | IOMUX_CONFIG_SION, 0x05CC, 0, 0),
-	MX8MP_PAD_SD1_DATA0__UART1_DCE_RTS                       = IOMUX_PAD(0x02F4, 0x0094, 4, 0x05E4, 0, 0),
-	MX8MP_PAD_SD1_DATA0__UART1_DTE_CTS                       = IOMUX_PAD(0x02F4, 0x0094, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA0__GPIO2_IO02                          = IOMUX_PAD(0x02F4, 0x0094, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA0__SIM_M_HADDR31                       = IOMUX_PAD(0x02F4, 0x0094, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_DATA1__USDHC1_DATA1                        = IOMUX_PAD(0x02F8, 0x0098, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA1__ENET1_RGMII_TD0                     = IOMUX_PAD(0x02F8, 0x0098, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA1__I2C6_SDA                            = IOMUX_PAD(0x02F8, 0x0098, 3 | IOMUX_CONFIG_SION, 0x05D0, 0, 0),
-	MX8MP_PAD_SD1_DATA1__UART1_DCE_CTS                       = IOMUX_PAD(0x02F8, 0x0098, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA1__UART1_DTE_RTS                       = IOMUX_PAD(0x02F8, 0x0098, 4, 0x05E4, 1, 0),
-	MX8MP_PAD_SD1_DATA1__GPIO2_IO03                          = IOMUX_PAD(0x02F8, 0x0098, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA1__SIM_M_HBURST00                      = IOMUX_PAD(0x02F8, 0x0098, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_DATA2__USDHC1_DATA2                        = IOMUX_PAD(0x02FC, 0x009C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA2__ENET1_RGMII_RD0                     = IOMUX_PAD(0x02FC, 0x009C, 1, 0x0580, 0, 0),
-	MX8MP_PAD_SD1_DATA2__I2C4_SCL                            = IOMUX_PAD(0x02FC, 0x009C, 3 | IOMUX_CONFIG_SION, 0x05BC, 0, 0),
-	MX8MP_PAD_SD1_DATA2__UART2_DCE_TX                        = IOMUX_PAD(0x02FC, 0x009C, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA2__UART2_DTE_RX                        = IOMUX_PAD(0x02FC, 0x009C, 4, 0x05F0, 0, 0),
-	MX8MP_PAD_SD1_DATA2__GPIO2_IO04                          = IOMUX_PAD(0x02FC, 0x009C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA2__SIM_M_HBURST01                      = IOMUX_PAD(0x02FC, 0x009C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_DATA3__USDHC1_DATA3                        = IOMUX_PAD(0x0300, 0x00A0, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA3__ENET1_RGMII_RD1                     = IOMUX_PAD(0x0300, 0x00A0, 1, 0x0584, 0, 0),
-	MX8MP_PAD_SD1_DATA3__I2C4_SDA                            = IOMUX_PAD(0x0300, 0x00A0, 3 | IOMUX_CONFIG_SION, 0x05C0, 0, 0),
-	MX8MP_PAD_SD1_DATA3__UART2_DCE_RX                        = IOMUX_PAD(0x0300, 0x00A0, 4, 0x05F0, 1, 0),
-	MX8MP_PAD_SD1_DATA3__UART2_DTE_TX                        = IOMUX_PAD(0x0300, 0x00A0, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA3__GPIO2_IO05                          = IOMUX_PAD(0x0300, 0x00A0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA3__SIM_M_HBURST02                      = IOMUX_PAD(0x0300, 0x00A0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_DATA4__USDHC1_DATA4                        = IOMUX_PAD(0x0304, 0x00A4, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL                  = IOMUX_PAD(0x0304, 0x00A4, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA4__I2C1_SCL                            = IOMUX_PAD(0x0304, 0x00A4, 3 | IOMUX_CONFIG_SION, 0x05A4, 0, 0),
-	MX8MP_PAD_SD1_DATA4__UART2_DCE_RTS                       = IOMUX_PAD(0x0304, 0x00A4, 4, 0x05EC, 0, 0),
-	MX8MP_PAD_SD1_DATA4__UART2_DTE_CTS                       = IOMUX_PAD(0x0304, 0x00A4, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA4__GPIO2_IO06                          = IOMUX_PAD(0x0304, 0x00A4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA4__SIM_M_HRESP                         = IOMUX_PAD(0x0304, 0x00A4, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_DATA5__USDHC1_DATA5                        = IOMUX_PAD(0x0308, 0x00A8, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA5__ENET1_TX_ER                         = IOMUX_PAD(0x0308, 0x00A8, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA5__I2C1_SDA                            = IOMUX_PAD(0x0308, 0x00A8, 3 | IOMUX_CONFIG_SION, 0x05A8, 0, 0),
-	MX8MP_PAD_SD1_DATA5__UART2_DCE_CTS                       = IOMUX_PAD(0x0308, 0x00A8, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA5__UART2_DTE_RTS                       = IOMUX_PAD(0x0308, 0x00A8, 4, 0x05EC, 1, 0),
-	MX8MP_PAD_SD1_DATA5__GPIO2_IO07                          = IOMUX_PAD(0x0308, 0x00A8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA5__TPSMP_HDATA05                       = IOMUX_PAD(0x0308, 0x00A8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_DATA6__USDHC1_DATA6                        = IOMUX_PAD(0x030C, 0x00AC, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL                  = IOMUX_PAD(0x030C, 0x00AC, 1, 0x0588, 0, 0),
-	MX8MP_PAD_SD1_DATA6__I2C2_SCL                            = IOMUX_PAD(0x030C, 0x00AC, 3 | IOMUX_CONFIG_SION, 0x05AC, 0, 0),
-	MX8MP_PAD_SD1_DATA6__UART3_DCE_TX                        = IOMUX_PAD(0x030C, 0x00AC, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA6__UART3_DTE_RX                        = IOMUX_PAD(0x030C, 0x00AC, 4, 0x05F8, 0, 0),
-	MX8MP_PAD_SD1_DATA6__GPIO2_IO08                          = IOMUX_PAD(0x030C, 0x00AC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA6__TPSMP_HDATA06                       = IOMUX_PAD(0x030C, 0x00AC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_DATA7__USDHC1_DATA7                        = IOMUX_PAD(0x0310, 0x00B0, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA7__ENET1_RX_ER                         = IOMUX_PAD(0x0310, 0x00B0, 1, 0x058C, 0, 0),
-	MX8MP_PAD_SD1_DATA7__I2C2_SDA                            = IOMUX_PAD(0x0310, 0x00B0, 3 | IOMUX_CONFIG_SION, 0x05B0, 0, 0),
-	MX8MP_PAD_SD1_DATA7__UART3_DCE_RX                        = IOMUX_PAD(0x0310, 0x00B0, 4, 0x05F8, 1, 0),
-	MX8MP_PAD_SD1_DATA7__UART3_DTE_TX                        = IOMUX_PAD(0x0310, 0x00B0, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA7__GPIO2_IO09                          = IOMUX_PAD(0x0310, 0x00B0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA7__TPSMP_HDATA07                       = IOMUX_PAD(0x0310, 0x00B0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_RESET_B__USDHC1_RESET_B                    = IOMUX_PAD(0x0314, 0x00B4, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_RESET_B__ENET1_TX_CLK                      = IOMUX_PAD(0x0314, 0x00B4, 1, 0x0578, 0, 0),
-	MX8MP_PAD_SD1_RESET_B__I2C3_SCL                          = IOMUX_PAD(0x0314, 0x00B4, 3 | IOMUX_CONFIG_SION, 0x05B4, 0, 0),
-	MX8MP_PAD_SD1_RESET_B__UART3_DCE_RTS                     = IOMUX_PAD(0x0314, 0x00B4, 4, 0x05F4, 0, 0),
-	MX8MP_PAD_SD1_RESET_B__UART3_DTE_CTS                     = IOMUX_PAD(0x0314, 0x00B4, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_RESET_B__GPIO2_IO10                        = IOMUX_PAD(0x0314, 0x00B4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_RESET_B__ECSPI3_TEST_TRIG                  = IOMUX_PAD(0x0314, 0x00B4, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD1_STROBE__USDHC1_STROBE                      = IOMUX_PAD(0x0318, 0x00B8, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_STROBE__I2C3_SDA                           = IOMUX_PAD(0x0318, 0x00B8, 3 | IOMUX_CONFIG_SION, 0x05B8, 0, 0),
-	MX8MP_PAD_SD1_STROBE__UART3_DCE_CTS                      = IOMUX_PAD(0x0318, 0x00B8, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_STROBE__UART3_DTE_RTS                      = IOMUX_PAD(0x0318, 0x00B8, 4, 0x05F4, 1, 0),
-	MX8MP_PAD_SD1_STROBE__GPIO2_IO11                         = IOMUX_PAD(0x0318, 0x00B8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_STROBE__USDHC3_TEST_TRIG                   = IOMUX_PAD(0x0318, 0x00B8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD2_CD_B__USDHC2_CD_B                          = IOMUX_PAD(0x031C, 0x00BC, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CD_B__GPIO2_IO12                           = IOMUX_PAD(0x031C, 0x00BC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK              = IOMUX_PAD(0x031C, 0x00BC, 6, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD2_CLK__USDHC2_CLK                            = IOMUX_PAD(0x0320, 0x00C0, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CLK__ECSPI2_SCLK                           = IOMUX_PAD(0x0320, 0x00C0, 2, 0x0568, 0, 0),
-	MX8MP_PAD_SD2_CLK__UART4_DCE_RX                          = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0600, 0, 0),
-	MX8MP_PAD_SD2_CLK__UART4_DTE_TX                          = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CLK__GPIO2_IO13                            = IOMUX_PAD(0x0320, 0x00C0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                 = IOMUX_PAD(0x0320, 0x00C0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CLK__OBSERVE_MUX_OUT00                     = IOMUX_PAD(0x0320, 0x00C0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD2_CMD__USDHC2_CMD                            = IOMUX_PAD(0x0324, 0x00C4, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CMD__ECSPI2_MOSI                           = IOMUX_PAD(0x0324, 0x00C4, 2, 0x0570, 0, 0),
-	MX8MP_PAD_SD2_CMD__UART4_DCE_TX                          = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CMD__UART4_DTE_RX                          = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0600, 1, 0),
-	MX8MP_PAD_SD2_CMD__AUDIOMIX_CLK                          = IOMUX_PAD(0x0324, 0x00C4, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CMD__GPIO2_IO14                            = IOMUX_PAD(0x0324, 0x00C4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                 = IOMUX_PAD(0x0324, 0x00C4, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CMD__OBSERVE_MUX_OUT01                     = IOMUX_PAD(0x0324, 0x00C4, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD2_DATA0__USDHC2_DATA0                        = IOMUX_PAD(0x0328, 0x00C8, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA0__I2C4_SDA                            = IOMUX_PAD(0x0328, 0x00C8, 2 | IOMUX_CONFIG_SION, 0x05C0, 1, 0),
-	MX8MP_PAD_SD2_DATA0__UART2_DCE_RX                        = IOMUX_PAD(0x0328, 0x00C8, 3, 0x05F0, 2, 0),
-	MX8MP_PAD_SD2_DATA0__UART2_DTE_TX                        = IOMUX_PAD(0x0328, 0x00C8, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA0__AUDIOMIX_BIT_STREAM00               = IOMUX_PAD(0x0328, 0x00C8, 4, 0x04C0, 1, 0),
-	MX8MP_PAD_SD2_DATA0__GPIO2_IO15                          = IOMUX_PAD(0x0328, 0x00C8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2               = IOMUX_PAD(0x0328, 0x00C8, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA0__OBSERVE_MUX_OUT02                   = IOMUX_PAD(0x0328, 0x00C8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD2_DATA1__USDHC2_DATA1                        = IOMUX_PAD(0x032C, 0x00CC, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA1__I2C4_SCL                            = IOMUX_PAD(0x032C, 0x00CC, 2 | IOMUX_CONFIG_SION, 0x05BC, 1, 0),
-	MX8MP_PAD_SD2_DATA1__UART2_DCE_TX                        = IOMUX_PAD(0x032C, 0x00CC, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA1__UART2_DTE_RX                        = IOMUX_PAD(0x032C, 0x00CC, 3, 0x05F0, 3, 0),
-	MX8MP_PAD_SD2_DATA1__AUDIOMIX_BIT_STREAM01               = IOMUX_PAD(0x032C, 0x00CC, 4, 0x04C4, 1, 0),
-	MX8MP_PAD_SD2_DATA1__GPIO2_IO16                          = IOMUX_PAD(0x032C, 0x00CC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT                   = IOMUX_PAD(0x032C, 0x00CC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA1__OBSERVE_MUX_OUT03                   = IOMUX_PAD(0x032C, 0x00CC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD2_DATA2__USDHC2_DATA2                        = IOMUX_PAD(0x0330, 0x00D0, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA2__ECSPI2_SS0                          = IOMUX_PAD(0x0330, 0x00D0, 2, 0x0574, 0, 0),
-	MX8MP_PAD_SD2_DATA2__AUDIOMIX_SPDIF_OUT                  = IOMUX_PAD(0x0330, 0x00D0, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA2__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x0330, 0x00D0, 4, 0x04C8, 1, 0),
-	MX8MP_PAD_SD2_DATA2__GPIO2_IO17                          = IOMUX_PAD(0x0330, 0x00D0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP                   = IOMUX_PAD(0x0330, 0x00D0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA2__OBSERVE_MUX_OUT04                   = IOMUX_PAD(0x0330, 0x00D0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD2_DATA3__USDHC2_DATA3                        = IOMUX_PAD(0x0334, 0x00D4, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA3__ECSPI2_MISO                         = IOMUX_PAD(0x0334, 0x00D4, 2, 0x056C, 0, 0),
-	MX8MP_PAD_SD2_DATA3__AUDIOMIX_SPDIF_IN                   = IOMUX_PAD(0x0334, 0x00D4, 3, 0x0544, 1, 0),
-	MX8MP_PAD_SD2_DATA3__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x0334, 0x00D4, 4, 0x04CC, 1, 0),
-	MX8MP_PAD_SD2_DATA3__GPIO2_IO18                          = IOMUX_PAD(0x0334, 0x00D4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET            = IOMUX_PAD(0x0334, 0x00D4, 6, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD2_RESET_B__USDHC2_RESET_B                    = IOMUX_PAD(0x0338, 0x00D8, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_RESET_B__GPIO2_IO19                        = IOMUX_PAD(0x0338, 0x00D8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET         = IOMUX_PAD(0x0338, 0x00D8, 6, 0x0000, 0, 0),
-
-	MX8MP_PAD_SD2_WP__USDHC2_WP                              = IOMUX_PAD(0x033C, 0x00DC, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_WP__GPIO2_IO20                             = IOMUX_PAD(0x033C, 0x00DC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_WP__CORESIGHT_EVENTI                       = IOMUX_PAD(0x033C, 0x00DC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_WP__SIM_M_HMASTLOCK                        = IOMUX_PAD(0x033C, 0x00DC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_ALE__RAWNAND_ALE                          = IOMUX_PAD(0x0340, 0x00E0, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_ALE__FLEXSPI_A_SCLK                       = IOMUX_PAD(0x0340, 0x00E0, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK                = IOMUX_PAD(0x0340, 0x00E0, 2, 0x04E8, 0, 0),
-	MX8MP_PAD_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0               = IOMUX_PAD(0x0340, 0x00E0, 3, 0x05D4, 1, 0),
-	MX8MP_PAD_NAND_ALE__UART3_DCE_RX                         = IOMUX_PAD(0x0340, 0x00E0, 4, 0x05F8, 2, 0),
-	MX8MP_PAD_NAND_ALE__UART3_DTE_TX                         = IOMUX_PAD(0x0340, 0x00E0, 4, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_ALE__GPIO3_IO00                           = IOMUX_PAD(0x0340, 0x00E0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_ALE__CORESIGHT_TRACE_CLK                  = IOMUX_PAD(0x0340, 0x00E0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_ALE__SIM_M_HPROT00                        = IOMUX_PAD(0x0340, 0x00E0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_CE0_B__RAWNAND_CE0_B                      = IOMUX_PAD(0x0344, 0x00E4, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE0_B__FLEXSPI_A_SS0_B                    = IOMUX_PAD(0x0344, 0x00E4, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00            = IOMUX_PAD(0x0344, 0x00E4, 2, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0        = IOMUX_PAD(0x0344, 0x00E4, 3, 0x05DC, 1, 0),
-	MX8MP_PAD_NAND_CE0_B__UART3_DCE_TX                       = IOMUX_PAD(0x0344, 0x00E4, 4, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE0_B__UART3_DTE_RX                       = IOMUX_PAD(0x0344, 0x00E4, 4, 0x05F8, 3, 0),
-	MX8MP_PAD_NAND_CE0_B__GPIO3_IO01                         = IOMUX_PAD(0x0344, 0x00E4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE0_B__CORESIGHT_TRACE_CTL                = IOMUX_PAD(0x0344, 0x00E4, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE0_B__SIM_M_HPROT01                      = IOMUX_PAD(0x0344, 0x00E4, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_CE1_B__RAWNAND_CE1_B                      = IOMUX_PAD(0x0348, 0x00E8, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE1_B__FLEXSPI_A_SS1_B                    = IOMUX_PAD(0x0348, 0x00E8, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE                      = IOMUX_PAD(0x0348, 0x00E8, 2, 0x0630, 1, 0),
-	MX8MP_PAD_NAND_CE1_B__I2C4_SCL                           = IOMUX_PAD(0x0348, 0x00E8, 4 | IOMUX_CONFIG_SION, 0x05BC, 2, 0),
-	MX8MP_PAD_NAND_CE1_B__GPIO3_IO02                         = IOMUX_PAD(0x0348, 0x00E8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE1_B__CORESIGHT_TRACE00                  = IOMUX_PAD(0x0348, 0x00E8, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE1_B__SIM_M_HPROT02                      = IOMUX_PAD(0x0348, 0x00E8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_CE2_B__RAWNAND_CE2_B                      = IOMUX_PAD(0x034C, 0x00EC, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE2_B__FLEXSPI_B_SS0_B                    = IOMUX_PAD(0x034C, 0x00EC, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5                       = IOMUX_PAD(0x034C, 0x00EC, 2, 0x0624, 1, 0),
-	MX8MP_PAD_NAND_CE2_B__I2C4_SDA                           = IOMUX_PAD(0x034C, 0x00EC, 4 | IOMUX_CONFIG_SION, 0x05C0, 2, 0),
-	MX8MP_PAD_NAND_CE2_B__GPIO3_IO03                         = IOMUX_PAD(0x034C, 0x00EC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE2_B__CORESIGHT_TRACE01                  = IOMUX_PAD(0x034C, 0x00EC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE2_B__SIM_M_HPROT03                      = IOMUX_PAD(0x034C, 0x00EC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_CE3_B__RAWNAND_CE3_B                      = IOMUX_PAD(0x0350, 0x00F0, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE3_B__FLEXSPI_B_SS1_B                    = IOMUX_PAD(0x0350, 0x00F0, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6                       = IOMUX_PAD(0x0350, 0x00F0, 2, 0x0628, 1, 0),
-	MX8MP_PAD_NAND_CE3_B__I2C3_SDA                           = IOMUX_PAD(0x0350, 0x00F0, 4 | IOMUX_CONFIG_SION, 0x05B8, 1, 0),
-	MX8MP_PAD_NAND_CE3_B__GPIO3_IO04                         = IOMUX_PAD(0x0350, 0x00F0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE3_B__CORESIGHT_TRACE02                  = IOMUX_PAD(0x0350, 0x00F0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE3_B__SIM_M_HADDR00                      = IOMUX_PAD(0x0350, 0x00F0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_CLE__RAWNAND_CLE                          = IOMUX_PAD(0x0354, 0x00F4, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CLE__FLEXSPI_B_SCLK                       = IOMUX_PAD(0x0354, 0x00F4, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CLE__USDHC3_DATA7                         = IOMUX_PAD(0x0354, 0x00F4, 2, 0x062C, 1, 0),
-	MX8MP_PAD_NAND_CLE__UART4_DCE_RX                         = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0600, 2, 0),
-	MX8MP_PAD_NAND_CLE__UART4_DTE_TX                         = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CLE__GPIO3_IO05                           = IOMUX_PAD(0x0354, 0x00F4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CLE__CORESIGHT_TRACE03                    = IOMUX_PAD(0x0354, 0x00F4, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CLE__SIM_M_HADDR01                        = IOMUX_PAD(0x0354, 0x00F4, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_DATA00__RAWNAND_DATA00                    = IOMUX_PAD(0x0358, 0x00F8, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA00__FLEXSPI_A_DATA00                  = IOMUX_PAD(0x0358, 0x00F8, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00           = IOMUX_PAD(0x0358, 0x00F8, 2, 0x04E4, 0, 0),
-	MX8MP_PAD_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0         = IOMUX_PAD(0x0358, 0x00F8, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA00__UART4_DCE_RX                      = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0600, 3, 0),
-	MX8MP_PAD_NAND_DATA00__UART4_DTE_TX                      = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA00__GPIO3_IO06                        = IOMUX_PAD(0x0358, 0x00F8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA00__CORESIGHT_TRACE04                 = IOMUX_PAD(0x0358, 0x00F8, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA00__SIM_M_HADDR02                     = IOMUX_PAD(0x0358, 0x00F8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_DATA01__RAWNAND_DATA01                    = IOMUX_PAD(0x035C, 0x00FC, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA01__FLEXSPI_A_DATA01                  = IOMUX_PAD(0x035C, 0x00FC, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC             = IOMUX_PAD(0x035C, 0x00FC, 2, 0x04EC, 0, 0),
-	MX8MP_PAD_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0      = IOMUX_PAD(0x035C, 0x00FC, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA01__UART4_DCE_TX                      = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA01__UART4_DTE_RX                      = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0600, 4, 0),
-	MX8MP_PAD_NAND_DATA01__GPIO3_IO07                        = IOMUX_PAD(0x035C, 0x00FC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA01__CORESIGHT_TRACE05                 = IOMUX_PAD(0x035C, 0x00FC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA01__SIM_M_HADDR03                     = IOMUX_PAD(0x035C, 0x00FC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_DATA02__RAWNAND_DATA02                    = IOMUX_PAD(0x0360, 0x0100, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA02__FLEXSPI_A_DATA02                  = IOMUX_PAD(0x0360, 0x0100, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA02__USDHC3_CD_B                       = IOMUX_PAD(0x0360, 0x0100, 2, 0x0608, 2, 0),
-	MX8MP_PAD_NAND_DATA02__UART4_DCE_CTS                     = IOMUX_PAD(0x0360, 0x0100, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA02__UART4_DTE_RTS                     = IOMUX_PAD(0x0360, 0x0100, 3, 0x05FC, 0, 0),
-	MX8MP_PAD_NAND_DATA02__I2C4_SDA                          = IOMUX_PAD(0x0360, 0x0100, 4 | IOMUX_CONFIG_SION, 0x05C0, 3, 0),
-	MX8MP_PAD_NAND_DATA02__GPIO3_IO08                        = IOMUX_PAD(0x0360, 0x0100, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA02__CORESIGHT_TRACE06                 = IOMUX_PAD(0x0360, 0x0100, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA02__SIM_M_HADDR04                     = IOMUX_PAD(0x0360, 0x0100, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_DATA03__RAWNAND_DATA03                    = IOMUX_PAD(0x0364, 0x0104, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA03__FLEXSPI_A_DATA03                  = IOMUX_PAD(0x0364, 0x0104, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA03__USDHC3_WP                         = IOMUX_PAD(0x0364, 0x0104, 2, 0x0634, 2, 0),
-	MX8MP_PAD_NAND_DATA03__UART4_DCE_RTS                     = IOMUX_PAD(0x0364, 0x0104, 3, 0x05FC, 1, 0),
-	MX8MP_PAD_NAND_DATA03__UART4_DTE_CTS                     = IOMUX_PAD(0x0364, 0x0104, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1            = IOMUX_PAD(0x0364, 0x0104, 4, 0x05D8, 1, 0),
-	MX8MP_PAD_NAND_DATA03__GPIO3_IO09                        = IOMUX_PAD(0x0364, 0x0104, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA03__CORESIGHT_TRACE07                 = IOMUX_PAD(0x0364, 0x0104, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA03__SIM_M_HADDR05                     = IOMUX_PAD(0x0364, 0x0104, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_DATA04__RAWNAND_DATA04                    = IOMUX_PAD(0x0368, 0x0108, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA04__FLEXSPI_B_DATA00                  = IOMUX_PAD(0x0368, 0x0108, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA04__USDHC3_DATA0                      = IOMUX_PAD(0x0368, 0x0108, 2, 0x0610, 1, 0),
-	MX8MP_PAD_NAND_DATA04__FLEXSPI_A_DATA04                  = IOMUX_PAD(0x0368, 0x0108, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1       = IOMUX_PAD(0x0368, 0x0108, 4, 0x05E0, 1, 0),
-	MX8MP_PAD_NAND_DATA04__GPIO3_IO10                        = IOMUX_PAD(0x0368, 0x0108, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA04__CORESIGHT_TRACE08                 = IOMUX_PAD(0x0368, 0x0108, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA04__SIM_M_HADDR06                     = IOMUX_PAD(0x0368, 0x0108, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_DATA05__RAWNAND_DATA05                    = IOMUX_PAD(0x036C, 0x010C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA05__FLEXSPI_B_DATA01                  = IOMUX_PAD(0x036C, 0x010C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA05__USDHC3_DATA1                      = IOMUX_PAD(0x036C, 0x010C, 2, 0x0614, 1, 0),
-	MX8MP_PAD_NAND_DATA05__FLEXSPI_A_DATA05                  = IOMUX_PAD(0x036C, 0x010C, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1         = IOMUX_PAD(0x036C, 0x010C, 4, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA05__GPIO3_IO11                        = IOMUX_PAD(0x036C, 0x010C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA05__CORESIGHT_TRACE09                 = IOMUX_PAD(0x036C, 0x010C, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA05__SIM_M_HADDR07                     = IOMUX_PAD(0x036C, 0x010C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_DATA06__RAWNAND_DATA06                    = IOMUX_PAD(0x0370, 0x0110, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA06__FLEXSPI_B_DATA02                  = IOMUX_PAD(0x0370, 0x0110, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA06__USDHC3_DATA2                      = IOMUX_PAD(0x0370, 0x0110, 2, 0x0618, 1, 0),
-	MX8MP_PAD_NAND_DATA06__FLEXSPI_A_DATA06                  = IOMUX_PAD(0x0370, 0x0110, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1      = IOMUX_PAD(0x0370, 0x0110, 4, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA06__GPIO3_IO12                        = IOMUX_PAD(0x0370, 0x0110, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA06__CORESIGHT_TRACE10                 = IOMUX_PAD(0x0370, 0x0110, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA06__SIM_M_HADDR08                     = IOMUX_PAD(0x0370, 0x0110, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_DATA07__RAWNAND_DATA07                    = IOMUX_PAD(0x0374, 0x0114, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA07__FLEXSPI_B_DATA03                  = IOMUX_PAD(0x0374, 0x0114, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA07__USDHC3_DATA3                      = IOMUX_PAD(0x0374, 0x0114, 2, 0x061C, 1, 0),
-	MX8MP_PAD_NAND_DATA07__FLEXSPI_A_DATA07                  = IOMUX_PAD(0x0374, 0x0114, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1       = IOMUX_PAD(0x0374, 0x0114, 4, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA07__GPIO3_IO13                        = IOMUX_PAD(0x0374, 0x0114, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA07__CORESIGHT_TRACE11                 = IOMUX_PAD(0x0374, 0x0114, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA07__SIM_M_HADDR09                     = IOMUX_PAD(0x0374, 0x0114, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_DQS__RAWNAND_DQS                          = IOMUX_PAD(0x0378, 0x0118, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DQS__FLEXSPI_A_DQS                        = IOMUX_PAD(0x0378, 0x0118, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DQS__AUDIOMIX_SAI3_MCLK                   = IOMUX_PAD(0x0378, 0x0118, 2, 0x04E0, 0, 0),
-	MX8MP_PAD_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0          = IOMUX_PAD(0x0378, 0x0118, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DQS__I2C3_SCL                             = IOMUX_PAD(0x0378, 0x0118, 4 | IOMUX_CONFIG_SION, 0x05B4, 1, 0),
-	MX8MP_PAD_NAND_DQS__GPIO3_IO14                           = IOMUX_PAD(0x0378, 0x0118, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DQS__CORESIGHT_TRACE12                    = IOMUX_PAD(0x0378, 0x0118, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DQS__SIM_M_HADDR10                        = IOMUX_PAD(0x0378, 0x0118, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_RE_B__RAWNAND_RE_B                        = IOMUX_PAD(0x037C, 0x011C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_RE_B__FLEXSPI_B_DQS                       = IOMUX_PAD(0x037C, 0x011C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_RE_B__USDHC3_DATA4                        = IOMUX_PAD(0x037C, 0x011C, 2, 0x0620, 1, 0),
-	MX8MP_PAD_NAND_RE_B__UART4_DCE_TX                        = IOMUX_PAD(0x037C, 0x011C, 4, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_RE_B__UART4_DTE_RX                        = IOMUX_PAD(0x037C, 0x011C, 4, 0x0600, 5, 0),
-	MX8MP_PAD_NAND_RE_B__GPIO3_IO15                          = IOMUX_PAD(0x037C, 0x011C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_RE_B__CORESIGHT_TRACE13                   = IOMUX_PAD(0x037C, 0x011C, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_RE_B__SIM_M_HADDR11                       = IOMUX_PAD(0x037C, 0x011C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_READY_B__RAWNAND_READY_B                  = IOMUX_PAD(0x0380, 0x0120, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B                   = IOMUX_PAD(0x0380, 0x0120, 2, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_READY_B__I2C3_SCL                         = IOMUX_PAD(0x0380, 0x0120, 4 | IOMUX_CONFIG_SION, 0x05B4, 2, 0),
-	MX8MP_PAD_NAND_READY_B__GPIO3_IO16                       = IOMUX_PAD(0x0380, 0x0120, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_READY_B__CORESIGHT_TRACE14                = IOMUX_PAD(0x0380, 0x0120, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_READY_B__SIM_M_HADDR12                    = IOMUX_PAD(0x0380, 0x0120, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_WE_B__RAWNAND_WE_B                        = IOMUX_PAD(0x0384, 0x0124, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_WE_B__USDHC3_CLK                          = IOMUX_PAD(0x0384, 0x0124, 2, 0x0604, 1, 0),
-	MX8MP_PAD_NAND_WE_B__I2C3_SDA                            = IOMUX_PAD(0x0384, 0x0124, 4 | IOMUX_CONFIG_SION, 0x05B8, 2, 0),
-	MX8MP_PAD_NAND_WE_B__GPIO3_IO17                          = IOMUX_PAD(0x0384, 0x0124, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_WE_B__CORESIGHT_TRACE15                   = IOMUX_PAD(0x0384, 0x0124, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_WE_B__SIM_M_HADDR13                       = IOMUX_PAD(0x0384, 0x0124, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_NAND_WP_B__RAWNAND_WP_B                        = IOMUX_PAD(0x0388, 0x0128, 0, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_WP_B__USDHC3_CMD                          = IOMUX_PAD(0x0388, 0x0128, 2, 0x060C, 1, 0),
-	MX8MP_PAD_NAND_WP_B__I2C4_SCL                            = IOMUX_PAD(0x0388, 0x0128, 4 | IOMUX_CONFIG_SION, 0x05BC, 3, 0),
-	MX8MP_PAD_NAND_WP_B__GPIO3_IO18                          = IOMUX_PAD(0x0388, 0x0128, 5, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_WP_B__CORESIGHT_EVENTO                    = IOMUX_PAD(0x0388, 0x0128, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_WP_B__SIM_M_HADDR14                       = IOMUX_PAD(0x0388, 0x0128, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC               = IOMUX_PAD(0x038C, 0x012C, 0, 0x0508, 0, 0),
-	MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00             = IOMUX_PAD(0x038C, 0x012C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXFS__PWM4_OUT                            = IOMUX_PAD(0x038C, 0x012C, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXFS__I2C6_SCL                            = IOMUX_PAD(0x038C, 0x012C, 3 | IOMUX_CONFIG_SION, 0x05CC, 1, 0),
-	MX8MP_PAD_SAI5_RXFS__GPIO3_IO19                          = IOMUX_PAD(0x038C, 0x012C, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK                = IOMUX_PAD(0x0390, 0x0130, 0, 0x04F4, 0, 0),
-	MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01              = IOMUX_PAD(0x0390, 0x0130, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXC__PWM3_OUT                             = IOMUX_PAD(0x0390, 0x0130, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXC__I2C6_SDA                             = IOMUX_PAD(0x0390, 0x0130, 3 | IOMUX_CONFIG_SION, 0x05D0, 1, 0),
-	MX8MP_PAD_SAI5_RXC__AUDIOMIX_CLK                         = IOMUX_PAD(0x0390, 0x0130, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXC__GPIO3_IO20                           = IOMUX_PAD(0x0390, 0x0130, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00             = IOMUX_PAD(0x0394, 0x0134, 0, 0x04F8, 0, 0),
-	MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02             = IOMUX_PAD(0x0394, 0x0134, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD0__PWM2_OUT                            = IOMUX_PAD(0x0394, 0x0134, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD0__I2C5_SCL                            = IOMUX_PAD(0x0394, 0x0134, 3 | IOMUX_CONFIG_SION, 0x05C4, 1, 0),
-	MX8MP_PAD_SAI5_RXD0__AUDIOMIX_BIT_STREAM00               = IOMUX_PAD(0x0394, 0x0134, 4, 0x04C0, 2, 0),
-	MX8MP_PAD_SAI5_RXD0__GPIO3_IO21                          = IOMUX_PAD(0x0394, 0x0134, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01             = IOMUX_PAD(0x0398, 0x0138, 0, 0x04FC, 0, 0),
-	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03             = IOMUX_PAD(0x0398, 0x0138, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC               = IOMUX_PAD(0x0398, 0x0138, 2, 0x04D8, 0, 0),
-	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC               = IOMUX_PAD(0x0398, 0x0138, 3, 0x0510, 0, 0),
-	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_BIT_STREAM01               = IOMUX_PAD(0x0398, 0x0138, 4, 0x04C4, 2, 0),
-	MX8MP_PAD_SAI5_RXD1__GPIO3_IO22                          = IOMUX_PAD(0x0398, 0x0138, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD1__CAN1_TX                             = IOMUX_PAD(0x0398, 0x0138, 6, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02             = IOMUX_PAD(0x039C, 0x013C, 0, 0x0500, 0, 0),
-	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04             = IOMUX_PAD(0x039C, 0x013C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC               = IOMUX_PAD(0x039C, 0x013C, 2, 0x04D8, 1, 0),
-	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK               = IOMUX_PAD(0x039C, 0x013C, 3, 0x050C, 0, 0),
-	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x039C, 0x013C, 4, 0x04C8, 2, 0),
-	MX8MP_PAD_SAI5_RXD2__GPIO3_IO23                          = IOMUX_PAD(0x039C, 0x013C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD2__CAN1_RX                             = IOMUX_PAD(0x039C, 0x013C, 6, 0x054C, 0, 0),
-
-	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03             = IOMUX_PAD(0x03A0, 0x0140, 0, 0x0504, 0, 0),
-	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05             = IOMUX_PAD(0x03A0, 0x0140, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC               = IOMUX_PAD(0x03A0, 0x0140, 2, 0x04D8, 2, 0),
-	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00             = IOMUX_PAD(0x03A0, 0x0140, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x03A0, 0x0140, 4, 0x04CC, 2, 0),
-	MX8MP_PAD_SAI5_RXD3__GPIO3_IO24                          = IOMUX_PAD(0x03A0, 0x0140, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD3__CAN2_TX                             = IOMUX_PAD(0x03A0, 0x0140, 6, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI5_MCLK                  = IOMUX_PAD(0x03A4, 0x0144, 0, 0x04F0, 0, 0),
-	MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK               = IOMUX_PAD(0x03A4, 0x0144, 1, 0x04D4, 0, 0),
-	MX8MP_PAD_SAI5_MCLK__PWM1_OUT                            = IOMUX_PAD(0x03A4, 0x0144, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_MCLK__I2C5_SDA                            = IOMUX_PAD(0x03A4, 0x0144, 3 | IOMUX_CONFIG_SION, 0x05C8, 1, 0),
-	MX8MP_PAD_SAI5_MCLK__GPIO3_IO25                          = IOMUX_PAD(0x03A4, 0x0144, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_MCLK__CAN2_RX                             = IOMUX_PAD(0x03A4, 0x0144, 6, 0x0550, 0, 0),
-
-	MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC               = IOMUX_PAD(0x03A8, 0x0148, 0, 0x04D0, 0, 0),
-	MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC               = IOMUX_PAD(0x03A8, 0x0148, 1, 0x0508, 1, 0),
-	MX8MP_PAD_SAI1_RXFS__ENET1_1588_EVENT0_IN                = IOMUX_PAD(0x03A8, 0x0148, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXFS__GPIO4_IO00                          = IOMUX_PAD(0x03A8, 0x0148, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK                = IOMUX_PAD(0x03AC, 0x014C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK                = IOMUX_PAD(0x03AC, 0x014C, 1, 0x04F4, 1, 0),
-	MX8MP_PAD_SAI1_RXC__AUDIOMIX_CLK                         = IOMUX_PAD(0x03AC, 0x014C, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXC__ENET1_1588_EVENT0_OUT                = IOMUX_PAD(0x03AC, 0x014C, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXC__GPIO4_IO01                           = IOMUX_PAD(0x03AC, 0x014C, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00             = IOMUX_PAD(0x03B0, 0x0150, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00             = IOMUX_PAD(0x03B0, 0x0150, 1, 0x04F8, 1, 0),
-	MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01             = IOMUX_PAD(0x03B0, 0x0150, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD0__AUDIOMIX_BIT_STREAM00               = IOMUX_PAD(0x03B0, 0x0150, 3, 0x04C0, 3, 0),
-	MX8MP_PAD_SAI1_RXD0__ENET1_1588_EVENT1_IN                = IOMUX_PAD(0x03B0, 0x0150, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD0__GPIO4_IO02                          = IOMUX_PAD(0x03B0, 0x0150, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01             = IOMUX_PAD(0x03B4, 0x0154, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01             = IOMUX_PAD(0x03B4, 0x0154, 1, 0x04FC, 1, 0),
-	MX8MP_PAD_SAI1_RXD1__AUDIOMIX_BIT_STREAM01               = IOMUX_PAD(0x03B4, 0x0154, 3, 0x04C4, 3, 0),
-	MX8MP_PAD_SAI1_RXD1__ENET1_1588_EVENT1_OUT               = IOMUX_PAD(0x03B4, 0x0154, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD1__GPIO4_IO03                          = IOMUX_PAD(0x03B4, 0x0154, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02             = IOMUX_PAD(0x03B8, 0x0158, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02             = IOMUX_PAD(0x03B8, 0x0158, 1, 0x0500, 1, 0),
-	MX8MP_PAD_SAI1_RXD2__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x03B8, 0x0158, 3, 0x04C8, 3, 0),
-	MX8MP_PAD_SAI1_RXD2__ENET1_MDC                           = IOMUX_PAD(0x03B8, 0x0158, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD2__GPIO4_IO04                          = IOMUX_PAD(0x03B8, 0x0158, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03             = IOMUX_PAD(0x03BC, 0x015C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03             = IOMUX_PAD(0x03BC, 0x015C, 1, 0x0504, 1, 0),
-	MX8MP_PAD_SAI1_RXD3__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x03BC, 0x015C, 3, 0x04CC, 3, 0),
-	MX8MP_PAD_SAI1_RXD3__ENET1_MDIO                          = IOMUX_PAD(0x03BC, 0x015C, 4, 0x057C, 1, 0),
-	MX8MP_PAD_SAI1_RXD3__GPIO4_IO05                          = IOMUX_PAD(0x03BC, 0x015C, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04             = IOMUX_PAD(0x03C0, 0x0160, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK               = IOMUX_PAD(0x03C0, 0x0160, 1, 0x0524, 1, 0),
-	MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK               = IOMUX_PAD(0x03C0, 0x0160, 2, 0x0518, 1, 0),
-	MX8MP_PAD_SAI1_RXD4__ENET1_RGMII_RD0                     = IOMUX_PAD(0x03C0, 0x0160, 4, 0x0580, 1, 0),
-	MX8MP_PAD_SAI1_RXD4__GPIO4_IO06                          = IOMUX_PAD(0x03C0, 0x0160, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05             = IOMUX_PAD(0x03C4, 0x0164, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00             = IOMUX_PAD(0x03C4, 0x0164, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00             = IOMUX_PAD(0x03C4, 0x0164, 2, 0x051C, 1, 0),
-	MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC               = IOMUX_PAD(0x03C4, 0x0164, 3, 0x04D0, 1, 0),
-	MX8MP_PAD_SAI1_RXD5__ENET1_RGMII_RD1                     = IOMUX_PAD(0x03C4, 0x0164, 4, 0x0584, 1, 0),
-	MX8MP_PAD_SAI1_RXD5__GPIO4_IO07                          = IOMUX_PAD(0x03C4, 0x0164, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06             = IOMUX_PAD(0x03C8, 0x0168, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC               = IOMUX_PAD(0x03C8, 0x0168, 1, 0x0528, 1, 0),
-	MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC               = IOMUX_PAD(0x03C8, 0x0168, 2, 0x0520, 1, 0),
-	MX8MP_PAD_SAI1_RXD6__ENET1_RGMII_RD2                     = IOMUX_PAD(0x03C8, 0x0168, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD6__GPIO4_IO08                          = IOMUX_PAD(0x03C8, 0x0168, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07             = IOMUX_PAD(0x03CC, 0x016C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI6_MCLK                  = IOMUX_PAD(0x03CC, 0x016C, 1, 0x0514, 1, 0),
-	MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC               = IOMUX_PAD(0x03CC, 0x016C, 2, 0x04D8, 3, 0),
-	MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04             = IOMUX_PAD(0x03CC, 0x016C, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD7__ENET1_RGMII_RD3                     = IOMUX_PAD(0x03CC, 0x016C, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD7__GPIO4_IO09                          = IOMUX_PAD(0x03CC, 0x016C, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC               = IOMUX_PAD(0x03D0, 0x0170, 0, 0x04D8, 4, 0),
-	MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC               = IOMUX_PAD(0x03D0, 0x0170, 1, 0x0510, 1, 0),
-	MX8MP_PAD_SAI1_TXFS__ENET1_RGMII_RX_CTL                  = IOMUX_PAD(0x03D0, 0x0170, 4, 0x0588, 1, 0),
-	MX8MP_PAD_SAI1_TXFS__GPIO4_IO10                          = IOMUX_PAD(0x03D0, 0x0170, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK                = IOMUX_PAD(0x03D4, 0x0174, 0, 0x04D4, 1, 0),
-	MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK                = IOMUX_PAD(0x03D4, 0x0174, 1, 0x050C, 1, 0),
-	MX8MP_PAD_SAI1_TXC__ENET1_RGMII_RXC                      = IOMUX_PAD(0x03D4, 0x0174, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXC__GPIO4_IO11                           = IOMUX_PAD(0x03D4, 0x0174, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00             = IOMUX_PAD(0x03D8, 0x0178, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00             = IOMUX_PAD(0x03D8, 0x0178, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD0__ENET1_RGMII_TD0                     = IOMUX_PAD(0x03D8, 0x0178, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD0__GPIO4_IO12                          = IOMUX_PAD(0x03D8, 0x0178, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01             = IOMUX_PAD(0x03DC, 0x017C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01             = IOMUX_PAD(0x03DC, 0x017C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD1__ENET1_RGMII_TD1                     = IOMUX_PAD(0x03DC, 0x017C, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD1__GPIO4_IO13                          = IOMUX_PAD(0x03DC, 0x017C, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02             = IOMUX_PAD(0x03E0, 0x0180, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02             = IOMUX_PAD(0x03E0, 0x0180, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD2__ENET1_RGMII_TD2                     = IOMUX_PAD(0x03E0, 0x0180, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD2__GPIO4_IO14                          = IOMUX_PAD(0x03E0, 0x0180, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03             = IOMUX_PAD(0x03E4, 0x0184, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03             = IOMUX_PAD(0x03E4, 0x0184, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD3__ENET1_RGMII_TD3                     = IOMUX_PAD(0x03E4, 0x0184, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD3__GPIO4_IO15                          = IOMUX_PAD(0x03E4, 0x0184, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04             = IOMUX_PAD(0x03E8, 0x0188, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK               = IOMUX_PAD(0x03E8, 0x0188, 1, 0x0518, 2, 0),
-	MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK               = IOMUX_PAD(0x03E8, 0x0188, 2, 0x0524, 2, 0),
-	MX8MP_PAD_SAI1_TXD4__ENET1_RGMII_TX_CTL                  = IOMUX_PAD(0x03E8, 0x0188, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD4__GPIO4_IO16                          = IOMUX_PAD(0x03E8, 0x0188, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05             = IOMUX_PAD(0x03EC, 0x018C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00             = IOMUX_PAD(0x03EC, 0x018C, 1, 0x051C, 2, 0),
-	MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00             = IOMUX_PAD(0x03EC, 0x018C, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD5__ENET1_RGMII_TXC                     = IOMUX_PAD(0x03EC, 0x018C, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD5__GPIO4_IO17                          = IOMUX_PAD(0x03EC, 0x018C, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06             = IOMUX_PAD(0x03F0, 0x0190, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC               = IOMUX_PAD(0x03F0, 0x0190, 1, 0x0520, 2, 0),
-	MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC               = IOMUX_PAD(0x03F0, 0x0190, 2, 0x0528, 2, 0),
-	MX8MP_PAD_SAI1_TXD6__ENET1_RX_ER                         = IOMUX_PAD(0x03F0, 0x0190, 4, 0x058C, 1, 0),
-	MX8MP_PAD_SAI1_TXD6__GPIO4_IO18                          = IOMUX_PAD(0x03F0, 0x0190, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07             = IOMUX_PAD(0x03F4, 0x0194, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI6_MCLK                  = IOMUX_PAD(0x03F4, 0x0194, 1, 0x0514, 2, 0),
-	MX8MP_PAD_SAI1_TXD7__AUDIOMIX_CLK                        = IOMUX_PAD(0x03F4, 0x0194, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD7__ENET1_TX_ER                         = IOMUX_PAD(0x03F4, 0x0194, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD7__GPIO4_IO19                          = IOMUX_PAD(0x03F4, 0x0194, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_MCLK                  = IOMUX_PAD(0x03F8, 0x0198, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI5_MCLK                  = IOMUX_PAD(0x03F8, 0x0198, 1, 0x04F0, 1, 0),
-	MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK               = IOMUX_PAD(0x03F8, 0x0198, 2, 0x04D4, 2, 0),
-	MX8MP_PAD_SAI1_MCLK__ENET1_TX_CLK                        = IOMUX_PAD(0x03F8, 0x0198, 4, 0x0578, 1, 0),
-	MX8MP_PAD_SAI1_MCLK__GPIO4_IO20                          = IOMUX_PAD(0x03F8, 0x0198, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC               = IOMUX_PAD(0x03FC, 0x019C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC               = IOMUX_PAD(0x03FC, 0x019C, 1, 0x0510, 2, 0),
-	MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01             = IOMUX_PAD(0x03FC, 0x019C, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01             = IOMUX_PAD(0x03FC, 0x019C, 3, 0x04DC, 0, 0),
-	MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX                        = IOMUX_PAD(0x03FC, 0x019C, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXFS__UART1_DTE_RX                        = IOMUX_PAD(0x03FC, 0x019C, 4, 0x05E8, 2, 0),
-	MX8MP_PAD_SAI2_RXFS__GPIO4_IO21                          = IOMUX_PAD(0x03FC, 0x019C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXFS__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x03FC, 0x019C, 6, 0x04C8, 4, 0),
-	MX8MP_PAD_SAI2_RXFS__SIM_M_HSIZE00                       = IOMUX_PAD(0x03FC, 0x019C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK                = IOMUX_PAD(0x0400, 0x01A0, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK                = IOMUX_PAD(0x0400, 0x01A0, 1, 0x050C, 2, 0),
-	MX8MP_PAD_SAI2_RXC__CAN1_TX                              = IOMUX_PAD(0x0400, 0x01A0, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXC__UART1_DCE_RX                         = IOMUX_PAD(0x0400, 0x01A0, 4, 0x05E8, 3, 0),
-	MX8MP_PAD_SAI2_RXC__UART1_DTE_TX                         = IOMUX_PAD(0x0400, 0x01A0, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXC__GPIO4_IO22                           = IOMUX_PAD(0x0400, 0x01A0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXC__AUDIOMIX_BIT_STREAM01                = IOMUX_PAD(0x0400, 0x01A0, 6, 0x04C4, 4, 0),
-	MX8MP_PAD_SAI2_RXC__SIM_M_HSIZE01                        = IOMUX_PAD(0x0400, 0x01A0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00             = IOMUX_PAD(0x0404, 0x01A4, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00             = IOMUX_PAD(0x0404, 0x01A4, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT            = IOMUX_PAD(0x0404, 0x01A4, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01             = IOMUX_PAD(0x0404, 0x01A4, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXD0__UART1_DCE_RTS                       = IOMUX_PAD(0x0404, 0x01A4, 4, 0x05E4, 2, 0),
-	MX8MP_PAD_SAI2_RXD0__UART1_DTE_CTS                       = IOMUX_PAD(0x0404, 0x01A4, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXD0__GPIO4_IO23                          = IOMUX_PAD(0x0404, 0x01A4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXD0__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x0404, 0x01A4, 6, 0x04CC, 4, 0),
-	MX8MP_PAD_SAI2_RXD0__SIM_M_HSIZE02                       = IOMUX_PAD(0x0404, 0x01A4, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC               = IOMUX_PAD(0x0408, 0x01A8, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01             = IOMUX_PAD(0x0408, 0x01A8, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT            = IOMUX_PAD(0x0408, 0x01A8, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01             = IOMUX_PAD(0x0408, 0x01A8, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXFS__UART1_DCE_CTS                       = IOMUX_PAD(0x0408, 0x01A8, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXFS__UART1_DTE_RTS                       = IOMUX_PAD(0x0408, 0x01A8, 4, 0x05E4, 3, 0),
-	MX8MP_PAD_SAI2_TXFS__GPIO4_IO24                          = IOMUX_PAD(0x0408, 0x01A8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXFS__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x0408, 0x01A8, 6, 0x04C8, 5, 0),
-	MX8MP_PAD_SAI2_TXFS__SIM_M_HWRITE                        = IOMUX_PAD(0x0408, 0x01A8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK                = IOMUX_PAD(0x040C, 0x01AC, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02              = IOMUX_PAD(0x040C, 0x01AC, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXC__CAN1_RX                              = IOMUX_PAD(0x040C, 0x01AC, 3, 0x054C, 1, 0),
-	MX8MP_PAD_SAI2_TXC__GPIO4_IO25                           = IOMUX_PAD(0x040C, 0x01AC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXC__AUDIOMIX_BIT_STREAM01                = IOMUX_PAD(0x040C, 0x01AC, 6, 0x04C4, 5, 0),
-	MX8MP_PAD_SAI2_TXC__SIM_M_HREADYOUT                      = IOMUX_PAD(0x040C, 0x01AC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00             = IOMUX_PAD(0x0410, 0x01B0, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03             = IOMUX_PAD(0x0410, 0x01B0, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN             = IOMUX_PAD(0x0410, 0x01B0, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXD0__CAN2_TX                             = IOMUX_PAD(0x0410, 0x01B0, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN         = IOMUX_PAD(0x0410, 0x01B0, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXD0__GPIO4_IO26                          = IOMUX_PAD(0x0410, 0x01B0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04            = IOMUX_PAD(0x0410, 0x01B0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXD0__TPSMP_CLK                           = IOMUX_PAD(0x0410, 0x01B0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI2_MCLK                  = IOMUX_PAD(0x0414, 0x01B4, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI5_MCLK                  = IOMUX_PAD(0x0414, 0x01B4, 1, 0x04F0, 2, 0),
-	MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN             = IOMUX_PAD(0x0414, 0x01B4, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_MCLK__CAN2_RX                             = IOMUX_PAD(0x0414, 0x01B4, 3, 0x0550, 1, 0),
-	MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN         = IOMUX_PAD(0x0414, 0x01B4, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_MCLK__GPIO4_IO27                          = IOMUX_PAD(0x0414, 0x01B4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI3_MCLK                  = IOMUX_PAD(0x0414, 0x01B4, 6, 0x04E0, 1, 0),
-	MX8MP_PAD_SAI2_MCLK__TPSMP_HDATA_DIR                     = IOMUX_PAD(0x0414, 0x01B4, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC               = IOMUX_PAD(0x0418, 0x01B8, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01             = IOMUX_PAD(0x0418, 0x01B8, 1, 0x04DC, 1, 0),
-	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC               = IOMUX_PAD(0x0418, 0x01B8, 2, 0x0508, 2, 0),
-	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01             = IOMUX_PAD(0x0418, 0x01B8, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SPDIF_IN                   = IOMUX_PAD(0x0418, 0x01B8, 4, 0x0544, 2, 0),
-	MX8MP_PAD_SAI3_RXFS__GPIO4_IO28                          = IOMUX_PAD(0x0418, 0x01B8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_BIT_STREAM00               = IOMUX_PAD(0x0418, 0x01B8, 6, 0x04C0, 4, 0),
-	MX8MP_PAD_SAI3_RXFS__TPSMP_HTRANS00                      = IOMUX_PAD(0x0418, 0x01B8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK                = IOMUX_PAD(0x041C, 0x01BC, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02              = IOMUX_PAD(0x041C, 0x01BC, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK                = IOMUX_PAD(0x041C, 0x01BC, 2, 0x04F4, 2, 0),
-	MX8MP_PAD_SAI3_RXC__GPT1_CLK                             = IOMUX_PAD(0x041C, 0x01BC, 3, 0x059C, 0, 0),
-	MX8MP_PAD_SAI3_RXC__UART2_DCE_CTS                        = IOMUX_PAD(0x041C, 0x01BC, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXC__UART2_DTE_RTS                        = IOMUX_PAD(0x041C, 0x01BC, 4, 0x05EC, 2, 0),
-	MX8MP_PAD_SAI3_RXC__GPIO4_IO29                           = IOMUX_PAD(0x041C, 0x01BC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXC__AUDIOMIX_CLK                         = IOMUX_PAD(0x041C, 0x01BC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXC__TPSMP_HTRANS01                       = IOMUX_PAD(0x041C, 0x01BC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00              = IOMUX_PAD(0x0420, 0x01C0, 0, 0x04E4, 1, 0),
-	MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03              = IOMUX_PAD(0x0420, 0x01C0, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00              = IOMUX_PAD(0x0420, 0x01C0, 2, 0x04F8, 2, 0),
-	MX8MP_PAD_SAI3_RXD__UART2_DCE_RTS                        = IOMUX_PAD(0x0420, 0x01C0, 4, 0x05EC, 3, 0),
-	MX8MP_PAD_SAI3_RXD__UART2_DTE_CTS                        = IOMUX_PAD(0x0420, 0x01C0, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXD__GPIO4_IO30                           = IOMUX_PAD(0x0420, 0x01C0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXD__AUDIOMIX_BIT_STREAM01                = IOMUX_PAD(0x0420, 0x01C0, 6, 0x04C4, 6, 0),
-	MX8MP_PAD_SAI3_RXD__TPSMP_HDATA00                        = IOMUX_PAD(0x0420, 0x01C0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC               = IOMUX_PAD(0x0424, 0x01C4, 0, 0x04EC, 1, 0),
-	MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01             = IOMUX_PAD(0x0424, 0x01C4, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01             = IOMUX_PAD(0x0424, 0x01C4, 2, 0x04FC, 2, 0),
-	MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01             = IOMUX_PAD(0x0424, 0x01C4, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXFS__UART2_DCE_RX                        = IOMUX_PAD(0x0424, 0x01C4, 4, 0x05F0, 4, 0),
-	MX8MP_PAD_SAI3_TXFS__UART2_DTE_TX                        = IOMUX_PAD(0x0424, 0x01C4, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXFS__GPIO4_IO31                          = IOMUX_PAD(0x0424, 0x01C4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXFS__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x0424, 0x01C4, 6, 0x04CC, 5, 0),
-	MX8MP_PAD_SAI3_TXFS__TPSMP_HDATA01                       = IOMUX_PAD(0x0424, 0x01C4, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK                = IOMUX_PAD(0x0428, 0x01C8, 0, 0x04E8, 1, 0),
-	MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02              = IOMUX_PAD(0x0428, 0x01C8, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02              = IOMUX_PAD(0x0428, 0x01C8, 2, 0x0500, 2, 0),
-	MX8MP_PAD_SAI3_TXC__GPT1_CAPTURE1                        = IOMUX_PAD(0x0428, 0x01C8, 3, 0x0594, 0, 0),
-	MX8MP_PAD_SAI3_TXC__UART2_DCE_TX                         = IOMUX_PAD(0x0428, 0x01C8, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXC__UART2_DTE_RX                         = IOMUX_PAD(0x0428, 0x01C8, 4, 0x05F0, 5, 0),
-	MX8MP_PAD_SAI3_TXC__GPIO5_IO00                           = IOMUX_PAD(0x0428, 0x01C8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXC__AUDIOMIX_BIT_STREAM02                = IOMUX_PAD(0x0428, 0x01C8, 6, 0x04C8, 6, 0),
-	MX8MP_PAD_SAI3_TXC__TPSMP_HDATA02                        = IOMUX_PAD(0x0428, 0x01C8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00              = IOMUX_PAD(0x042C, 0x01CC, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03              = IOMUX_PAD(0x042C, 0x01CC, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03              = IOMUX_PAD(0x042C, 0x01CC, 2, 0x0504, 2, 0),
-	MX8MP_PAD_SAI3_TXD__GPT1_CAPTURE2                        = IOMUX_PAD(0x042C, 0x01CC, 3, 0x0598, 0, 0),
-	MX8MP_PAD_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK               = IOMUX_PAD(0x042C, 0x01CC, 4, 0x0548, 0, 0),
-	MX8MP_PAD_SAI3_TXD__GPIO5_IO01                           = IOMUX_PAD(0x042C, 0x01CC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05             = IOMUX_PAD(0x042C, 0x01CC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXD__TPSMP_HDATA03                        = IOMUX_PAD(0x042C, 0x01CC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI3_MCLK                  = IOMUX_PAD(0x0430, 0x01D0, 0, 0x04E0, 2, 0),
-	MX8MP_PAD_SAI3_MCLK__PWM4_OUT                            = IOMUX_PAD(0x0430, 0x01D0, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI5_MCLK                  = IOMUX_PAD(0x0430, 0x01D0, 2, 0x04F0, 3, 0),
-	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_OUT                  = IOMUX_PAD(0x0430, 0x01D0, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_MCLK__GPIO5_IO02                          = IOMUX_PAD(0x0430, 0x01D0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_IN                   = IOMUX_PAD(0x0430, 0x01D0, 6, 0x0544, 3, 0),
-	MX8MP_PAD_SAI3_MCLK__TPSMP_HDATA04                       = IOMUX_PAD(0x0430, 0x01D0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_SPDIF_TX__AUDIOMIX_SPDIF_OUT                   = IOMUX_PAD(0x0434, 0x01D4, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SPDIF_TX__PWM3_OUT                             = IOMUX_PAD(0x0434, 0x01D4, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SPDIF_TX__I2C5_SCL                             = IOMUX_PAD(0x0434, 0x01D4, 2 | IOMUX_CONFIG_SION, 0x05C4, 2, 0),
-	MX8MP_PAD_SPDIF_TX__GPT1_COMPARE1                        = IOMUX_PAD(0x0434, 0x01D4, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SPDIF_TX__CAN1_TX                              = IOMUX_PAD(0x0434, 0x01D4, 4, 0x0000, 0, 0),
-	MX8MP_PAD_SPDIF_TX__GPIO5_IO03                           = IOMUX_PAD(0x0434, 0x01D4, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SPDIF_RX__AUDIOMIX_SPDIF_IN                    = IOMUX_PAD(0x0438, 0x01D8, 0, 0x0544, 4, 0),
-	MX8MP_PAD_SPDIF_RX__PWM2_OUT                             = IOMUX_PAD(0x0438, 0x01D8, 1, 0x0000, 0, 0),
-	MX8MP_PAD_SPDIF_RX__I2C5_SDA                             = IOMUX_PAD(0x0438, 0x01D8, 2 | IOMUX_CONFIG_SION, 0x05C8, 2, 0),
-	MX8MP_PAD_SPDIF_RX__GPT1_COMPARE2                        = IOMUX_PAD(0x0438, 0x01D8, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SPDIF_RX__CAN1_RX                              = IOMUX_PAD(0x0438, 0x01D8, 4, 0x054C, 2, 0),
-	MX8MP_PAD_SPDIF_RX__GPIO5_IO04                           = IOMUX_PAD(0x0438, 0x01D8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SPDIF_EXT_CLK__GPT1_COMPARE3                   = IOMUX_PAD(0x043C, 0x01DC, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05                      = IOMUX_PAD(0x043C, 0x01DC, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK          = IOMUX_PAD(0x043C, 0x01DC, 0, 0x0548, 1, 0),
-	MX8MP_PAD_SPDIF_EXT_CLK__PWM1_OUT                        = IOMUX_PAD(0x043C, 0x01DC, 1, 0x0000, 0, 0),
-
-	MX8MP_PAD_ECSPI1_SCLK__ECSPI1_SCLK                       = IOMUX_PAD(0x0440, 0x01E0, 0, 0x0558, 0, 0),
-	MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX                      = IOMUX_PAD(0x0440, 0x01E0, 1, 0x05F8, 4, 0),
-	MX8MP_PAD_ECSPI1_SCLK__UART3_DTE_TX                      = IOMUX_PAD(0x0440, 0x01E0, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_SCLK__I2C1_SCL                          = IOMUX_PAD(0x0440, 0x01E0, 2 | IOMUX_CONFIG_SION, 0x05A4, 1, 0),
-	MX8MP_PAD_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC             = IOMUX_PAD(0x0440, 0x01E0, 3, 0x0538, 1, 0),
-	MX8MP_PAD_ECSPI1_SCLK__GPIO5_IO06                        = IOMUX_PAD(0x0440, 0x01E0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_SCLK__TPSMP_HDATA08                     = IOMUX_PAD(0x0440, 0x01E0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ECSPI1_MOSI__ECSPI1_MOSI                       = IOMUX_PAD(0x0444, 0x01E4, 0, 0x0560, 0, 0),
-	MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX                      = IOMUX_PAD(0x0444, 0x01E4, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_MOSI__UART3_DTE_RX                      = IOMUX_PAD(0x0444, 0x01E4, 1, 0x05F8, 5, 0),
-	MX8MP_PAD_ECSPI1_MOSI__I2C1_SDA                          = IOMUX_PAD(0x0444, 0x01E4, 2 | IOMUX_CONFIG_SION, 0x05A8, 1, 0),
-	MX8MP_PAD_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK             = IOMUX_PAD(0x0444, 0x01E4, 3, 0x0530, 1, 0),
-	MX8MP_PAD_ECSPI1_MOSI__GPIO5_IO07                        = IOMUX_PAD(0x0444, 0x01E4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_MOSI__TPSMP_HDATA09                     = IOMUX_PAD(0x0444, 0x01E4, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ECSPI1_MISO__ECSPI1_MISO                       = IOMUX_PAD(0x0448, 0x01E8, 0, 0x055C, 0, 0),
-	MX8MP_PAD_ECSPI1_MISO__UART3_DCE_CTS                     = IOMUX_PAD(0x0448, 0x01E8, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_MISO__UART3_DTE_RTS                     = IOMUX_PAD(0x0448, 0x01E8, 1, 0x05F4, 2, 0),
-	MX8MP_PAD_ECSPI1_MISO__I2C2_SCL                          = IOMUX_PAD(0x0448, 0x01E8, 2 | IOMUX_CONFIG_SION, 0x05AC, 1, 0),
-	MX8MP_PAD_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00           = IOMUX_PAD(0x0448, 0x01E8, 3, 0x0534, 1, 0),
-	MX8MP_PAD_ECSPI1_MISO__GPIO5_IO08                        = IOMUX_PAD(0x0448, 0x01E8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_MISO__TPSMP_HDATA10                     = IOMUX_PAD(0x0448, 0x01E8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ECSPI1_SS0__ECSPI1_SS0                         = IOMUX_PAD(0x044C, 0x01EC, 0, 0x0564, 0, 0),
-	MX8MP_PAD_ECSPI1_SS0__UART3_DCE_RTS                      = IOMUX_PAD(0x044C, 0x01EC, 1, 0x05F4, 3, 0),
-	MX8MP_PAD_ECSPI1_SS0__UART3_DTE_CTS                      = IOMUX_PAD(0x044C, 0x01EC, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_SS0__I2C2_SDA                           = IOMUX_PAD(0x044C, 0x01EC, 2 | IOMUX_CONFIG_SION, 0x05B0, 1, 0),
-	MX8MP_PAD_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC              = IOMUX_PAD(0x044C, 0x01EC, 3, 0x0540, 1, 0),
-	MX8MP_PAD_ECSPI1_SS0__GPIO5_IO09                         = IOMUX_PAD(0x044C, 0x01EC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_SS0__TPSMP_HDATA11                      = IOMUX_PAD(0x044C, 0x01EC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ECSPI2_SCLK__ECSPI2_SCLK                       = IOMUX_PAD(0x0450, 0x01F0, 0, 0x0568, 1, 0),
-	MX8MP_PAD_ECSPI2_SCLK__UART4_DCE_RX                      = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0600, 6, 0),
-	MX8MP_PAD_ECSPI2_SCLK__UART4_DTE_TX                      = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_SCLK__I2C3_SCL                          = IOMUX_PAD(0x0450, 0x01F0, 2 | IOMUX_CONFIG_SION, 0x05B4, 3, 0),
-	MX8MP_PAD_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK             = IOMUX_PAD(0x0450, 0x01F0, 3, 0x053C, 1, 0),
-	MX8MP_PAD_ECSPI2_SCLK__GPIO5_IO10                        = IOMUX_PAD(0x0450, 0x01F0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_SCLK__TPSMP_HDATA12                     = IOMUX_PAD(0x0450, 0x01F0, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ECSPI2_MOSI__ECSPI2_MOSI                       = IOMUX_PAD(0x0454, 0x01F4, 0, 0x0570, 1, 0),
-	MX8MP_PAD_ECSPI2_MOSI__UART4_DCE_TX                      = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_MOSI__UART4_DTE_RX                      = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0600, 7, 0),
-	MX8MP_PAD_ECSPI2_MOSI__I2C3_SDA                          = IOMUX_PAD(0x0454, 0x01F4, 2 | IOMUX_CONFIG_SION, 0x05B8, 3, 0),
-	MX8MP_PAD_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00           = IOMUX_PAD(0x0454, 0x01F4, 3, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_MOSI__GPIO5_IO11                        = IOMUX_PAD(0x0454, 0x01F4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_MOSI__TPSMP_HDATA13                     = IOMUX_PAD(0x0454, 0x01F4, 7, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12                        = IOMUX_PAD(0x0458, 0x01F8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_MISO__TPSMP_HDATA14                     = IOMUX_PAD(0x0458, 0x01F8, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_ECSPI2_MISO__ECSPI2_MISO                       = IOMUX_PAD(0x0458, 0x01F8, 0, 0x056C, 1, 0),
-	MX8MP_PAD_ECSPI2_MISO__UART4_DCE_CTS                     = IOMUX_PAD(0x0458, 0x01F8, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_MISO__UART4_DTE_RTS                     = IOMUX_PAD(0x0458, 0x01F8, 1, 0x05FC, 2, 0),
-	MX8MP_PAD_ECSPI2_MISO__I2C4_SCL                          = IOMUX_PAD(0x0458, 0x01F8, 2 | IOMUX_CONFIG_SION, 0x05BC, 4, 0),
-	MX8MP_PAD_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK                = IOMUX_PAD(0x0458, 0x01F8, 3, 0x052C, 1, 0),
-	MX8MP_PAD_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1                = IOMUX_PAD(0x0458, 0x01F8, 4, 0x0000, 0, 0),
-
-	MX8MP_PAD_ECSPI2_SS0__ECSPI2_SS0                         = IOMUX_PAD(0x045C, 0x01FC, 0, 0x0574, 1, 0),
-	MX8MP_PAD_ECSPI2_SS0__UART4_DCE_RTS                      = IOMUX_PAD(0x045C, 0x01FC, 1, 0x05FC, 3, 0),
-	MX8MP_PAD_ECSPI2_SS0__UART4_DTE_CTS                      = IOMUX_PAD(0x045C, 0x01FC, 1, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_SS0__I2C4_SDA                           = IOMUX_PAD(0x045C, 0x01FC, 2 | IOMUX_CONFIG_SION, 0x05C0, 4, 0),
-	MX8MP_PAD_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2                 = IOMUX_PAD(0x045C, 0x01FC, 4, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13                         = IOMUX_PAD(0x045C, 0x01FC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_SS0__TPSMP_HDATA15                      = IOMUX_PAD(0x045C, 0x01FC, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_I2C1_SCL__I2C1_SCL                             = IOMUX_PAD(0x0460, 0x0200, 0 | IOMUX_CONFIG_SION, 0x05A4, 2, 0),
-	MX8MP_PAD_I2C1_SCL__ENET_QOS_MDC                         = IOMUX_PAD(0x0460, 0x0200, 1, 0x0000, 0, 0),
-	MX8MP_PAD_I2C1_SCL__ECSPI1_SCLK                          = IOMUX_PAD(0x0460, 0x0200, 3, 0x0558, 1, 0),
-	MX8MP_PAD_I2C1_SCL__GPIO5_IO14                           = IOMUX_PAD(0x0460, 0x0200, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C1_SCL__TPSMP_HDATA16                        = IOMUX_PAD(0x0460, 0x0200, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_I2C1_SDA__I2C1_SDA                             = IOMUX_PAD(0x0464, 0x0204, 0 | IOMUX_CONFIG_SION, 0x05A8, 2, 0),
-	MX8MP_PAD_I2C1_SDA__ENET_QOS_MDIO                        = IOMUX_PAD(0x0464, 0x0204, 1, 0x0590, 2, 0),
-	MX8MP_PAD_I2C1_SDA__ECSPI1_MOSI                          = IOMUX_PAD(0x0464, 0x0204, 3, 0x0560, 1, 0),
-	MX8MP_PAD_I2C1_SDA__GPIO5_IO15                           = IOMUX_PAD(0x0464, 0x0204, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C1_SDA__TPSMP_HDATA17                        = IOMUX_PAD(0x0464, 0x0204, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_I2C2_SCL__I2C2_SCL                             = IOMUX_PAD(0x0468, 0x0208, 0 | IOMUX_CONFIG_SION, 0x05AC, 2, 0),
-	MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_IN              = IOMUX_PAD(0x0468, 0x0208, 1, 0x0000, 0, 0),
-	MX8MP_PAD_I2C2_SCL__USDHC3_CD_B                          = IOMUX_PAD(0x0468, 0x0208, 2, 0x0608, 3, 0),
-	MX8MP_PAD_I2C2_SCL__ECSPI1_MISO                          = IOMUX_PAD(0x0468, 0x0208, 3, 0x055C, 1, 0),
-	MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN          = IOMUX_PAD(0x0468, 0x0208, 4, 0x0000, 0, 0),
-	MX8MP_PAD_I2C2_SCL__GPIO5_IO16                           = IOMUX_PAD(0x0468, 0x0208, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C2_SCL__TPSMP_HDATA18                        = IOMUX_PAD(0x0468, 0x0208, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_I2C2_SDA__I2C2_SDA                             = IOMUX_PAD(0x046C, 0x020C, 0 | IOMUX_CONFIG_SION, 0x05B0, 2, 0),
-	MX8MP_PAD_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT             = IOMUX_PAD(0x046C, 0x020C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_I2C2_SDA__USDHC3_WP                            = IOMUX_PAD(0x046C, 0x020C, 2, 0x0634, 3, 0),
-	MX8MP_PAD_I2C2_SDA__ECSPI1_SS0                           = IOMUX_PAD(0x046C, 0x020C, 3, 0x0564, 1, 0),
-	MX8MP_PAD_I2C2_SDA__GPIO5_IO17                           = IOMUX_PAD(0x046C, 0x020C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C2_SDA__TPSMP_HDATA19                        = IOMUX_PAD(0x046C, 0x020C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_I2C3_SCL__I2C3_SCL                             = IOMUX_PAD(0x0470, 0x0210, 0 | IOMUX_CONFIG_SION, 0x05B4, 4, 0),
-	MX8MP_PAD_I2C3_SCL__PWM4_OUT                             = IOMUX_PAD(0x0470, 0x0210, 1, 0x0000, 0, 0),
-	MX8MP_PAD_I2C3_SCL__GPT2_CLK                             = IOMUX_PAD(0x0470, 0x0210, 2, 0x0000, 0, 0),
-	MX8MP_PAD_I2C3_SCL__ECSPI2_SCLK                          = IOMUX_PAD(0x0470, 0x0210, 3, 0x0568, 2, 0),
-	MX8MP_PAD_I2C3_SCL__GPIO5_IO18                           = IOMUX_PAD(0x0470, 0x0210, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C3_SCL__TPSMP_HDATA20                        = IOMUX_PAD(0x0470, 0x0210, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_I2C3_SDA__I2C3_SDA                             = IOMUX_PAD(0x0474, 0x0214, 0 | IOMUX_CONFIG_SION, 0x05B8, 4, 0),
-	MX8MP_PAD_I2C3_SDA__PWM3_OUT                             = IOMUX_PAD(0x0474, 0x0214, 1, 0x0000, 0, 0),
-	MX8MP_PAD_I2C3_SDA__GPT3_CLK                             = IOMUX_PAD(0x0474, 0x0214, 2, 0x0000, 0, 0),
-	MX8MP_PAD_I2C3_SDA__ECSPI2_MOSI                          = IOMUX_PAD(0x0474, 0x0214, 3, 0x0570, 2, 0),
-	MX8MP_PAD_I2C3_SDA__GPIO5_IO19                           = IOMUX_PAD(0x0474, 0x0214, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C3_SDA__TPSMP_HDATA21                        = IOMUX_PAD(0x0474, 0x0214, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_I2C4_SCL__I2C4_SCL                             = IOMUX_PAD(0x0478, 0x0218, 0 | IOMUX_CONFIG_SION, 0x05BC, 5, 0),
-	MX8MP_PAD_I2C4_SCL__PWM2_OUT                             = IOMUX_PAD(0x0478, 0x0218, 1, 0x0000, 0, 0),
-	MX8MP_PAD_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B                = IOMUX_PAD(0x0478, 0x0218, 2, 0x05A0, 0, 0),
-	MX8MP_PAD_I2C4_SCL__ECSPI2_MISO                          = IOMUX_PAD(0x0478, 0x0218, 3, 0x056C, 2, 0),
-	MX8MP_PAD_I2C4_SCL__GPIO5_IO20                           = IOMUX_PAD(0x0478, 0x0218, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C4_SCL__TPSMP_HDATA22                        = IOMUX_PAD(0x0478, 0x0218, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_I2C4_SDA__I2C4_SDA                             = IOMUX_PAD(0x047C, 0x021C, 0 | IOMUX_CONFIG_SION, 0x05C0, 5, 0),
-	MX8MP_PAD_I2C4_SDA__PWM1_OUT                             = IOMUX_PAD(0x047C, 0x021C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_I2C4_SDA__ECSPI2_SS0                           = IOMUX_PAD(0x047C, 0x021C, 3, 0x0574, 2, 0),
-	MX8MP_PAD_I2C4_SDA__GPIO5_IO21                           = IOMUX_PAD(0x047C, 0x021C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C4_SDA__TPSMP_HDATA23                        = IOMUX_PAD(0x047C, 0x021C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART1_RXD__UART1_DCE_RX                        = IOMUX_PAD(0x0480, 0x0220, 0, 0x05E8, 4, 0),
-
-	MX8MP_PAD_UART1_RXD__UART1_DTE_TX                        = IOMUX_PAD(0x0480, 0x0220, 0, 0x0000, 0, 0),
-	MX8MP_PAD_UART1_RXD__ECSPI3_SCLK                         = IOMUX_PAD(0x0480, 0x0220, 1, 0x0000, 0, 0),
-	MX8MP_PAD_UART1_RXD__GPIO5_IO22                          = IOMUX_PAD(0x0480, 0x0220, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART1_RXD__TPSMP_HDATA24                       = IOMUX_PAD(0x0480, 0x0220, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART1_TXD__UART1_DCE_TX                        = IOMUX_PAD(0x0484, 0x0224, 0, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART1_TXD__UART1_DTE_RX                        = IOMUX_PAD(0x0484, 0x0224, 0, 0x05E8, 5, 0),
-	MX8MP_PAD_UART1_TXD__ECSPI3_MOSI                         = IOMUX_PAD(0x0484, 0x0224, 1, 0x0000, 0, 0),
-	MX8MP_PAD_UART1_TXD__GPIO5_IO23                          = IOMUX_PAD(0x0484, 0x0224, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART1_TXD__TPSMP_HDATA25                       = IOMUX_PAD(0x0484, 0x0224, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART2_RXD__UART2_DCE_RX                        = IOMUX_PAD(0x0488, 0x0228, 0, 0x05F0, 6, 0),
-
-	MX8MP_PAD_UART2_RXD__UART2_DTE_TX                        = IOMUX_PAD(0x0488, 0x0228, 0, 0x0000, 0, 0),
-	MX8MP_PAD_UART2_RXD__ECSPI3_MISO                         = IOMUX_PAD(0x0488, 0x0228, 1, 0x0000, 0, 0),
-	MX8MP_PAD_UART2_RXD__GPT1_COMPARE3                       = IOMUX_PAD(0x0488, 0x0228, 3, 0x0000, 0, 0),
-	MX8MP_PAD_UART2_RXD__GPIO5_IO24                          = IOMUX_PAD(0x0488, 0x0228, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART2_RXD__TPSMP_HDATA26                       = IOMUX_PAD(0x0488, 0x0228, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART2_TXD__UART2_DCE_TX                        = IOMUX_PAD(0x048C, 0x022C, 0, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART2_TXD__UART2_DTE_RX                        = IOMUX_PAD(0x048C, 0x022C, 0, 0x05F0, 7, 0),
-	MX8MP_PAD_UART2_TXD__ECSPI3_SS0                          = IOMUX_PAD(0x048C, 0x022C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_UART2_TXD__GPT1_COMPARE2                       = IOMUX_PAD(0x048C, 0x022C, 3, 0x0000, 0, 0),
-	MX8MP_PAD_UART2_TXD__GPIO5_IO25                          = IOMUX_PAD(0x048C, 0x022C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART2_TXD__TPSMP_HDATA27                       = IOMUX_PAD(0x048C, 0x022C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART3_RXD__UART3_DCE_RX                        = IOMUX_PAD(0x0490, 0x0230, 0, 0x05F8, 6, 0),
-
-	MX8MP_PAD_UART3_RXD__UART3_DTE_TX                        = IOMUX_PAD(0x0490, 0x0230, 0, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_RXD__UART1_DCE_CTS                       = IOMUX_PAD(0x0490, 0x0230, 1, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_RXD__UART1_DTE_RTS                       = IOMUX_PAD(0x0490, 0x0230, 1, 0x05E4, 4, 0),
-	MX8MP_PAD_UART3_RXD__USDHC3_RESET_B                      = IOMUX_PAD(0x0490, 0x0230, 2, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_RXD__GPT1_CAPTURE2                       = IOMUX_PAD(0x0490, 0x0230, 3, 0x0598, 1, 0),
-	MX8MP_PAD_UART3_RXD__CAN2_TX                             = IOMUX_PAD(0x0490, 0x0230, 4, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_RXD__GPIO5_IO26                          = IOMUX_PAD(0x0490, 0x0230, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_RXD__TPSMP_HDATA28                       = IOMUX_PAD(0x0490, 0x0230, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART3_TXD__UART3_DCE_TX                        = IOMUX_PAD(0x0494, 0x0234, 0, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART3_TXD__UART3_DTE_RX                        = IOMUX_PAD(0x0494, 0x0234, 0, 0x05F8, 7, 0),
-	MX8MP_PAD_UART3_TXD__UART1_DCE_RTS                       = IOMUX_PAD(0x0494, 0x0234, 1, 0x05E4, 5, 0),
-	MX8MP_PAD_UART3_TXD__UART1_DTE_CTS                       = IOMUX_PAD(0x0494, 0x0234, 1, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_TXD__USDHC3_VSELECT                      = IOMUX_PAD(0x0494, 0x0234, 2, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_TXD__GPT1_CLK                            = IOMUX_PAD(0x0494, 0x0234, 3, 0x059C, 1, 0),
-	MX8MP_PAD_UART3_TXD__CAN2_RX                             = IOMUX_PAD(0x0494, 0x0234, 4, 0x0550, 2, 0),
-	MX8MP_PAD_UART3_TXD__GPIO5_IO27                          = IOMUX_PAD(0x0494, 0x0234, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_TXD__TPSMP_HDATA29                       = IOMUX_PAD(0x0494, 0x0234, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART4_RXD__UART4_DCE_RX                        = IOMUX_PAD(0x0498, 0x0238, 0, 0x0600, 8, 0),
-
-	MX8MP_PAD_UART4_RXD__UART4_DTE_TX                        = IOMUX_PAD(0x0498, 0x0238, 0, 0x0000, 0, 0),
-	MX8MP_PAD_UART4_RXD__UART2_DCE_CTS                       = IOMUX_PAD(0x0498, 0x0238, 1, 0x0000, 0, 0),
-	MX8MP_PAD_UART4_RXD__UART2_DTE_RTS                       = IOMUX_PAD(0x0498, 0x0238, 1, 0x05EC, 4, 0),
-	MX8MP_PAD_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B               = IOMUX_PAD(0x0498, 0x0238, 2, 0x05A0, 1, 0),
-	MX8MP_PAD_UART4_RXD__GPT1_COMPARE1                       = IOMUX_PAD(0x0498, 0x0238, 3, 0x0000, 0, 0),
-	MX8MP_PAD_UART4_RXD__I2C6_SCL                            = IOMUX_PAD(0x0498, 0x0238, 4 | IOMUX_CONFIG_SION, 0x05CC, 2, 0),
-	MX8MP_PAD_UART4_RXD__GPIO5_IO28                          = IOMUX_PAD(0x0498, 0x0238, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART4_RXD__TPSMP_HDATA30                       = IOMUX_PAD(0x0498, 0x0238, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART4_TXD__UART4_DCE_TX                        = IOMUX_PAD(0x049C, 0x023C, 0, 0x0000, 0, 0),
-
-	MX8MP_PAD_UART4_TXD__UART4_DTE_RX                        = IOMUX_PAD(0x049C, 0x023C, 0, 0x0600, 9, 0),
-	MX8MP_PAD_UART4_TXD__UART2_DCE_RTS                       = IOMUX_PAD(0x049C, 0x023C, 1, 0x05EC, 5, 0),
-	MX8MP_PAD_UART4_TXD__UART2_DTE_CTS                       = IOMUX_PAD(0x049C, 0x023C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_UART4_TXD__GPT1_CAPTURE1                       = IOMUX_PAD(0x049C, 0x023C, 3, 0x0594, 1, 0),
-	MX8MP_PAD_UART4_TXD__I2C6_SDA                            = IOMUX_PAD(0x049C, 0x023C, 4 | IOMUX_CONFIG_SION, 0x05D0, 2, 0),
-	MX8MP_PAD_UART4_TXD__GPIO5_IO29                          = IOMUX_PAD(0x049C, 0x023C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART4_TXD__TPSMP_HDATA31                       = IOMUX_PAD(0x049C, 0x023C, 7, 0x0000, 0, 0),
-
-	MX8MP_PAD_HDMI_DDC_SCL__HDMIMIX_EARC_SCL                 = IOMUX_PAD(0x04A0, 0x0240, 0, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_DDC_SCL__I2C5_SCL                         = IOMUX_PAD(0x04A0, 0x0240, 3 | IOMUX_CONFIG_SION, 0x05C4, 3, 0),
-	MX8MP_PAD_HDMI_DDC_SCL__CAN1_TX                          = IOMUX_PAD(0x04A0, 0x0240, 4, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_DDC_SCL__GPIO3_IO26                       = IOMUX_PAD(0x04A0, 0x0240, 5, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_DDC_SCL__AUDIOMIX_test_out00              = IOMUX_PAD(0x04A0, 0x0240, 6, 0x0000, 0, 0),
-
-	MX8MP_PAD_HDMI_DDC_SDA__HDMIMIX_EARC_SDA                 = IOMUX_PAD(0x04A4, 0x0244, 0, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_DDC_SDA__I2C5_SDA                         = IOMUX_PAD(0x04A4, 0x0244, 3 | IOMUX_CONFIG_SION, 0x05C8, 3, 0),
-	MX8MP_PAD_HDMI_DDC_SDA__CAN1_RX                          = IOMUX_PAD(0x04A4, 0x0244, 4, 0x054C, 3, 0),
-	MX8MP_PAD_HDMI_DDC_SDA__GPIO3_IO27                       = IOMUX_PAD(0x04A4, 0x0244, 5, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_DDC_SDA__AUDIOMIX_test_out01              = IOMUX_PAD(0x04A4, 0x0244, 6, 0x0000, 0, 0),
-
-	MX8MP_PAD_HDMI_CEC__HDMIMIX_EARC_CEC                     = IOMUX_PAD(0x04A8, 0x0248, 0, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_CEC__I2C6_SCL                             = IOMUX_PAD(0x04A8, 0x0248, 3 | IOMUX_CONFIG_SION, 0x05CC, 3, 0),
-	MX8MP_PAD_HDMI_CEC__CAN2_TX                              = IOMUX_PAD(0x04A8, 0x0248, 4, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_CEC__GPIO3_IO28                           = IOMUX_PAD(0x04A8, 0x0248, 5, 0x0000, 0, 0),
-
-	MX8MP_PAD_HDMI_HPD__HDMIMIX_EARC_DC_HPD                  = IOMUX_PAD(0x04AC, 0x024C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O             = IOMUX_PAD(0x04AC, 0x024C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_HPD__I2C6_SDA                             = IOMUX_PAD(0x04AC, 0x024C, 3 | IOMUX_CONFIG_SION, 0x05D0, 3, 0),
-	MX8MP_PAD_HDMI_HPD__CAN2_RX                              = IOMUX_PAD(0x04AC, 0x024C, 4, 0x0550, 3, 0),
-	MX8MP_PAD_HDMI_HPD__GPIO3_IO29                           = IOMUX_PAD(0x04AC, 0x024C, 5, 0x0000, 0, 0),
-};
-
-#define MX8MP_PAD_CTL_DSE1	(0 << 1)
-#define MX8MP_PAD_CTL_DSE2	(1 << 1)
-#define MX8MP_PAD_CTL_DSE4	(2 << 1)
-#define MX8MP_PAD_CTL_DSE6	(3 << 1)
-#define MX8MP_PAD_CTL_FSEL	BIT(4)
-#define MX8MP_PAD_CTL_ODE	BIT(5)
-#define MX8MP_PAD_CTL_PUE	BIT(6)
-#define MX8MP_PAD_CTL_HYS	BIT(7)
-#define MX8MP_PAD_CTL_PE	BIT(8)
-
-static inline void imx8mp_setup_pad(iomux_v3_cfg_t pad)
-{
-	void __iomem *iomux = IOMEM(MX8MP_IOMUXC_BASE_ADDR);
-
-	imx8m_setup_pad(iomux, pad);
-}
-
-#define MX8MP_IOMUXC_GPR1			0x4
-#define MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN	BIT(22)
-
-#endif  /* __ASM_ARCH_IMX8MP_PINS_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mq.h b/arch/arm/mach-imx/include/mach/iomux-mx8mq.h
deleted file mode 100644
index b6efdda4ff..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-mx8mq.h
+++ /dev/null
@@ -1,650 +0,0 @@
-/*
- * Copyright (C) 2017 NXP
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MACH_IOMUX_IMX8MQ_H__
-#define __MACH_IOMUX_IMX8MQ_H__
-
-#include <mach/iomux-v3.h>
-#include <mach/iomux-mx8m.h>
-#include <mach/imx8mq-regs.h>
-
-enum {
-	IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0			= IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT	= IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K		= IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1			= IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL			= IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1			= IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT				= IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M		= IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2			= IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE			= IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2			= IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B			= IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY			= IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B			= IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3			= IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT			= IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0			= IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK			= IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE			= IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4			= IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT			= IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1			= IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V		= IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5			= IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI		= IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY			= IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT			= IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6			= IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO06__ENET_MDC				= IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B			= IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3			= IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7			= IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO			= IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP			= IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4			= IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8			= IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN		= IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B			= IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT				= IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9			= IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT		= IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0			= IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO09__CCM_STOP				= IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10			= IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID			= IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11			= IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID			= IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY			= IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
-
-	IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12			= IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR			= IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1			= IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0		= IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13			= IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC			= IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT				= IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1		= IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14			= IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR			= IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT				= IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1			= IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2		= IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15			= IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC			= IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT				= IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2			= IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
-	IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB			= IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_MDC__ENET_MDC				= IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_MDC__GPIO1_IO16				= IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_MDIO__ENET_MDIO				= IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
-	IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17			= IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3			= IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_TD3__GPIO1_IO18				= IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2			= IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK			= IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_TD2__GPIO1_IO19				= IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1			= IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_TD1__GPIO1_IO20				= IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0			= IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_TD0__GPIO1_IO21				= IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL		= IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22			= IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC			= IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_TXC__ENET_TX_ER				= IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_TXC__GPIO1_IO23				= IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL		= IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24			= IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC			= IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_RXC__ENET_RX_ER				= IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_RXC__GPIO1_IO25				= IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0			= IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_RD0__GPIO1_IO26				= IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1			= IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_RD1__GPIO1_IO27				= IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2			= IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_RD2__GPIO1_IO28				= IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3			= IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ENET_RD3__GPIO1_IO29				= IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK				= IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_CLK__GPIO2_IO0				= IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD				= IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_CMD__GPIO2_IO1				= IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0			= IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2				= IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1			= IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3				= IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2			= IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4				= IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3			= IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5				= IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4			= IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6				= IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5			= IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7				= IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6			= IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8				= IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7			= IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9				= IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B			= IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10			= IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE			= IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11			= IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B			= IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12				= IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK				= IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_CLK__GPIO2_IO13				= IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD				= IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_CMD__GPIO2_IO14				= IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0			= IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15			= IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1			= IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16			= IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_DATA1__CCM_WAIT				= IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2			= IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17			= IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_DATA2__CCM_STOP				= IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3			= IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18			= IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET			= IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B			= IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19			= IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET		= IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SD2_WP__USDHC2_WP				= IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SD2_WP__GPIO2_IO20				= IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE			= IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK			= IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_ALE__GPIO3_IO0				= IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B			= IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B			= IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1			= IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B			= IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B			= IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2			= IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B			= IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B			= IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3			= IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B			= IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B			= IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4			= IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE			= IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK			= IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_CLE__GPIO3_IO5				= IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00			= IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0			= IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6			= IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01			= IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1			= IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7			= IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02			= IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2			= IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8			= IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03			= IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3			= IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9			= IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04			= IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0			= IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10			= IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05			= IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1			= IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11			= IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06			= IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2			= IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12			= IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07			= IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3			= IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13			= IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS			= IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS				= IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_DQS__GPIO3_IO14				= IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B			= IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS			= IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15			= IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B		= IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16			= IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B			= IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17			= IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B			= IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18			= IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC			= IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
-	IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0			= IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19			= IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK			= IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
-	IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1			= IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20				= IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0			= IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2			= IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21			= IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1			= IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3			= IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC			= IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC			= IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22			= IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2			= IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4			= IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC			= IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
-	IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK			= IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23			= IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3			= IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5			= IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC			= IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
-	IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0			= IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24			= IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK				= IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
-	IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK			= IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
-	IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK				= IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25			= IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK			= IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC			= IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
-	IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC			= IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
-	IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK		= IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0				= IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK			= IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK			= IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
-	IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL		= IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1				= IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0			= IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0			= IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
-	IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0		= IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2				= IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0			= IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1			= IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1			= IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
-	IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1		= IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3				= IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1			= IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2			= IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2			= IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
-	IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2		= IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4				= IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2			= IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3			= IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0),
-	IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3			= IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3		= IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5				= IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3			= IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4			= IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK			= IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK			= IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4		= IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6				= IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4			= IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5			= IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0			= IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0			= IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC			= IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
-	IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5		= IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7				= IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5			= IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6			= IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC			= IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC			= IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6		= IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8				= IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6			= IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7			= IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK				= IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC			= IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
-	IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4			= IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7		= IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9				= IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7			= IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC			= IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
-	IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC			= IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
-	IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO		= IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10			= IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK			= IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
-	IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK			= IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
-	IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI		= IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11				= IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0			= IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0			= IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8		= IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12			= IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8			= IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1			= IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1			= IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9		= IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13			= IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9			= IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2			= IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2			= IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10		= IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14			= IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10			= IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3			= IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3			= IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11		= IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15			= IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11			= IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4			= IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK			= IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
-	IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK			= IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
-	IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12		= IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16			= IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12			= IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5			= IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0			= IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
-	IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0			= IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13		= IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17			= IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13			= IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6			= IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC			= IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
-	IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC			= IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
-	IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14		= IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18			= IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14			= IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7			= IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK				= IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
-	IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15		= IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19			= IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15			= IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK				= IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK				= IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
-	IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK			= IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
-	IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20			= IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC			= IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC			= IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
-	IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21			= IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK			= IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK			= IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
-	IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22				= IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0			= IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0			= IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23			= IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC			= IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1			= IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24			= IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK			= IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2			= IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25				= IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0			= IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3			= IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26			= IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK				= IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK				= IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
-	IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27			= IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC			= IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1			= IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC			= IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
-	IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28			= IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK			= IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2			= IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK			= IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
-	IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29				= IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0			= IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1			= IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0			= IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
-	IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30				= IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC			= IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK				= IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1			= IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
-	IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31			= IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK			= IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2			= IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2			= IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
-	IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0				= IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0			= IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3			= IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3			= IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
-	IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1				= IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK				= IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT				= IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK				= IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
-	IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2				= IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT				= IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SPDIF_TX__PWM3_OUT				= IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3				= IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN				= IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SPDIF_RX__PWM2_OUT				= IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4				= IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK		= IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT			= IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5			= IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK			= IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX			= IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
-	IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6			= IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI			= IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX			= IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
-	IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7			= IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO			= IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B			= IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
-	IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8			= IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0			= IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B			= IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
-	IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9			= IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK			= IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX			= IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
-	IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10			= IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI			= IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX			= IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
-	IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11			= IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO			= IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B			= IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
-	IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12			= IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0			= IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B			= IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
-	IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13			= IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_I2C1_SCL__I2C1_SCL				= IOMUX_PAD(0x047C, 0x0214, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C1_SCL__ENET_MDC				= IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14				= IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_I2C1_SDA__I2C1_SDA				= IOMUX_PAD(0x0480, 0x0218, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C1_SDA__ENET_MDIO				= IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
-	IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15				= IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_I2C2_SCL__I2C2_SCL				= IOMUX_PAD(0x0484, 0x021C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN		= IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16				= IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_I2C2_SDA__I2C2_SDA				= IOMUX_PAD(0x0488, 0x0220, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT		= IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17				= IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_I2C3_SCL__I2C3_SCL				= IOMUX_PAD(0x048C, 0x0224, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C3_SCL__PWM4_OUT				= IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C3_SCL__GPT2_CLK				= IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18				= IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_I2C3_SDA__I2C3_SDA				= IOMUX_PAD(0x0490, 0x0228, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C3_SDA__PWM3_OUT				= IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C3_SDA__GPT3_CLK				= IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19				= IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_I2C4_SCL__I2C4_SCL				= IOMUX_PAD(0x0494, 0x022C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C4_SCL__PWM2_OUT				= IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B			= IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
-	IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20				= IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_I2C4_SDA__I2C4_SDA				= IOMUX_PAD(0x0498, 0x0230, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C4_SDA__PWM1_OUT				= IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B			= IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0),
-	IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21				= IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_UART1_RXD__UART1_RX				= IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
-	IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK			= IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_UART1_RXD__GPIO5_IO22			= IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_UART1_TXD__UART1_TX				= IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI			= IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_UART1_TXD__GPIO5_IO23			= IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_UART2_RXD__UART2_RX				= IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
-	IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO			= IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_UART2_RXD__GPIO5_IO24			= IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_UART2_TXD__UART2_TX				= IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0			= IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
-	IMX8MQ_PAD_UART2_TXD__GPIO5_IO25			= IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_UART3_RXD__UART3_RX				= IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
-	IMX8MQ_PAD_UART3_RXD__UART1_CTS_B			= IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
-	IMX8MQ_PAD_UART3_RXD__GPIO5_IO26			= IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_UART3_TXD__UART3_TX				= IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_UART3_TXD__UART1_RTS_B			= IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
-	IMX8MQ_PAD_UART3_TXD__GPIO5_IO27			= IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_UART4_RXD__UART4_RX				= IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
-	IMX8MQ_PAD_UART4_RXD__UART2_CTS_B			= IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
-	IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B			= IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
-	IMX8MQ_PAD_UART4_RXD__GPIO5_IO28			= IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
-
-	IMX8MQ_PAD_UART4_TXD__UART4_TX				= IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
-	IMX8MQ_PAD_UART4_TXD__UART2_RTS_B			= IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
-	IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B			= IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0),
-	IMX8MQ_PAD_UART4_TXD__GPIO5_IO29			= IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
-};
-
-#define MX8MQ_PAD_CTL_DSE_HIZ	(0 << 0)
-#define MX8MQ_PAD_CTL_DSE_255R	(1 << 0)
-#define MX8MQ_PAD_CTL_DSE_155R	(2 << 0)
-#define MX8MQ_PAD_CTL_DSE_75R	(3 << 0)
-#define MX8MQ_PAD_CTL_DSE_85R	(4 << 0)
-#define MX8MQ_PAD_CTL_DSE_65R	(5 << 0)
-#define MX8MQ_PAD_CTL_DSE_45R	(6 << 0)
-#define MX8MQ_PAD_CTL_DSE_40R	(7 << 0)
-#define MX8MQ_PAD_CTL_SR_50M	(0 << 3)
-#define MX8MQ_PAD_CTL_SR_100M	(1 << 3)
-#define MX8MQ_PAD_CTL_SR_150M	(2 << 3)
-#define MX8MQ_PAD_CTL_SR_200M	(3 << 3)
-#define MX8MQ_PAD_CTL_ODE	BIT(5)
-#define MX8MQ_PAD_CTL_PUE	BIT(6)
-#define MX8MQ_PAD_CTL_HYS	BIT(7)
-#define MX8MQ_PAD_CTL_LVTTL	BIT(8)
-
-static inline void imx8mq_setup_pad(iomux_v3_cfg_t pad)
-{
-	void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR);
-
-	imx8m_setup_pad(iomux, pad);
-}
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/iomux-v1.h b/arch/arm/mach-imx/include/mach/iomux-v1.h
deleted file mode 100644
index 8f75933e39..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-v1.h
+++ /dev/null
@@ -1,70 +0,0 @@
-#ifndef __MACH_IOMUX_V1_H__
-#define __MACH_IOMUX_V1_H__
-
-#include <linux/compiler.h>
-
-#define GPIO_PIN_MASK 0x1f
-
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-
-#define GPIO_OUT   (1 << 8)
-#define GPIO_IN    (0 << 8)
-#define GPIO_PUEN  (1 << 9)
-
-#define GPIO_PF    (1 << 10)
-#define GPIO_AF    (1 << 11)
-
-#define GPIO_OCR_SHIFT 12
-#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
-#define GPIO_AIN   (0 << GPIO_OCR_SHIFT)
-#define GPIO_BIN   (1 << GPIO_OCR_SHIFT)
-#define GPIO_CIN   (2 << GPIO_OCR_SHIFT)
-#define GPIO_GPIO  (3 << GPIO_OCR_SHIFT)
-
-#define GPIO_AOUT_SHIFT 14
-#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT     (0 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_0   (2 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_1   (3 << GPIO_AOUT_SHIFT)
-
-#define GPIO_BOUT_SHIFT 16
-#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT      (0 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_ISR  (1 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_0    (2 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_1    (3 << GPIO_BOUT_SHIFT)
-
-#define GPIO_GIUS      (1 << 16)
-
-void imx_iomuxv1_init(void __iomem *base);
-void imx_gpio_mode(void __iomem *base, int gpio_mode);
-
-#include <mach/imx1-regs.h>
-#include <mach/imx21-regs.h>
-#include <mach/imx27-regs.h>
-
-static inline void imx1_gpio_mode(int gpio_mode)
-{
-	imx_gpio_mode(IOMEM(MX1_GPIO1_BASE_ADDR), gpio_mode);
-}
-
-static inline void imx21_gpio_mode(int gpio_mode)
-{
-	imx_gpio_mode(IOMEM(MX21_GPIO1_BASE_ADDR), gpio_mode);
-}
-
-static inline void imx27_gpio_mode(int gpio_mode)
-{
-	imx_gpio_mode(IOMEM(MX27_GPIO1_BASE_ADDR), gpio_mode);
-}
-
-#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h
deleted file mode 100644
index e1d62ae4b8..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-v3.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2009 Jan Weitzel <armlinux@phytec.de>, Phytec Messtechnik GmbH */
-
-#ifndef __MACH_IOMUX_V3_H__
-#define __MACH_IOMUX_V3_H__
-
-#include <io.h>
-#include <linux/bitfield.h>
-
-/*
- *	build IOMUX_PAD structure
- *
- * This iomux scheme is based around pads, which are the physical balls
- * on the processor.
- *
- * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
- *   things like driving strength and pullup/pulldown.
- * - Each pad can have but not necessarily does have an output routing register
- *   (IOMUXC_SW_MUX_CTL_PAD_x).
- * - Each pad can have but not necessarily does have an input routing register
- *   (IOMUXC_x_SELECT_INPUT)
- *
- * The three register sets do not have a fixed offset to each other,
- * hence we order this table by pad control registers (which all pads
- * have) and put the optional i/o routing registers into additional
- * fields.
- *
- * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num>
- *
- * IOMUX/PAD Bit field definitions
- *
- * MUX_CTRL_OFS:	    0..11 (12)
- * PAD_CTRL_OFS:	   12..23 (12)
- * SEL_INPUT_OFS:	   24..35 (12)
- * MUX_MODE + SION:	   36..40  (5)
- * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
- * SEL_INP:		   59..62  (4)
- * reserved:		     63    (1)
-*/
-
-typedef u64 iomux_v3_cfg_t;
-
-#define MUX_CTRL_OFS_SHIFT	0
-#define MUX_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
-#define MUX_PAD_CTRL_OFS_SHIFT	12
-#define MUX_PAD_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
-#define MUX_SEL_INPUT_OFS_SHIFT	24
-#define MUX_SEL_INPUT_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
-
-#define MUX_MODE_SHIFT		36
-#define MUX_MODE_MASK		((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
-#define MUX_PAD_CTRL_SHIFT	41
-#define MUX_PAD_CTRL_MASK	((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
-#define MUX_SEL_INPUT_SHIFT	59
-#define MUX_SEL_INPUT_MASK	((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
-
-#define MUX_PAD_CTRL(x)		((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
-
-#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
-		_sel_input, _pad_ctrl)					\
-	(((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) |	\
-		((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) |	\
-		((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
-		((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) |	\
-		((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
-		((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
-
-#define IOMUX_PAD_FIELD(name, pad) 	(((pad) & name##_MASK) >> name##_SHIFT)
-#define IOMUX_CTRL_OFS(pad)		IOMUX_PAD_FIELD(MUX_CTRL_OFS, pad)
-#define IOMUX_MODE(pad)			IOMUX_PAD_FIELD(MUX_MODE, pad)
-#define IOMUX_SEL_INPUT_OFS(pad)	IOMUX_PAD_FIELD(MUX_SEL_INPUT_OFS, pad)
-#define IOMUX_SEL_INPUT(pad)		IOMUX_PAD_FIELD(MUX_SEL_INPUT, pad)
-#define IOMUX_PAD_CTRL_OFS(pad)		IOMUX_PAD_FIELD(MUX_PAD_CTRL_OFS, pad)
-#define IOMUX_PAD_CTRL(pad)		IOMUX_PAD_FIELD(MUX_PAD_CTRL, pad)
-
-#define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
-/*
- * Use to set PAD control
- */
-
-#define NO_PAD_CTRL			(1 << 17)
-#define PAD_CTL_DVS			(1 << 13)
-#define PAD_CTL_HYS			(1 << 8)
-
-#define SHARE_CONF_PAD_CTL_DSE	GENMASK(2, 0)
-#define SHARE_CONF_PAD_CTL_SRE	GENMASK(4, 3)
-
-#define SHARE_CONF_PAD_CTL_ODE	BIT(5)
-#define SHARE_CONF_PAD_CTL_PUE	BIT(6)
-#define SHARE_CONF_PAD_CTL_HYS	BIT(7)
-
-#define PAD_CTL_PKE			(1 << 7)
-#define PAD_CTL_PUE			(1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN		(0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP		(1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP		(2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP		(3 << 4 | PAD_CTL_PUE)
-
-#define PAD_CTL_ODE			(1 << 3)
-
-#define PAD_CTL_DSE_LOW			(0 << 1)
-#define PAD_CTL_DSE_MED			(1 << 1)
-#define PAD_CTL_DSE_HIGH		(2 << 1)
-#define PAD_CTL_DSE_MAX			(3 << 1)
-
-#define PAD_CTL_SRE_FAST		(1 << 0)
-#define PAD_CTL_SRE_SLOW		(0 << 0)
-
-#define IOMUX_CONFIG_SION		(0x1 << 4)
-#define IOMUX_CONFIG_LPSR               BIT(5)
-
-#define SHARE_MUX_CONF_REG		0x1
-#define ZERO_OFFSET_VALID		0x2
-#define IMX7_PINMUX_LPSR		0x4
-#define SHARE_CONF			BIT(3)
-
-static inline void iomux_v3_setup_pad(void __iomem *iomux, unsigned int flags,
-				      u32 mux_reg, u32 conf_reg, u32 input_reg,
-				      u32 mux_val, u32 conf_val, u32 input_val)
-{
-	const bool mux_ok   = !!mux_reg || (flags & ZERO_OFFSET_VALID);
-	const bool conf_ok  = !!conf_reg;
-	const bool input_ok = !!input_reg;
-
-	/*
-	 * The sel_input registers for the LPSR controller pins are in the regular pinmux
-	 * controller, so bend the register offset over to the other controller.
-	 */
-	if (flags & IMX7_PINMUX_LPSR)
-		input_reg += 0x70000;
-
-	if (flags & SHARE_MUX_CONF_REG) {
-		mux_val |= conf_val;
-	} else {
-		if (conf_ok)
-			writel(conf_val, iomux + conf_reg);
-	}
-
-	if (mux_ok)
-		writel(mux_val, iomux + mux_reg);
-
-	if (input_ok)
-		writel(input_val, iomux + input_reg);
-}
-
-static inline void imx_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad)
-{
-	uint32_t conf_reg, pad_ctrl;
-
-	/* dont write PAD_CTRL when NO_PAD_CTRL is set */
-	pad_ctrl = IOMUX_PAD_CTRL(pad);
-	conf_reg = IOMUX_PAD_CTRL_OFS(pad);
-	conf_reg = (pad_ctrl & NO_PAD_CTRL) ? 0 : conf_reg,
-
-	iomux_v3_setup_pad(iomux, 0,
-			   IOMUX_CTRL_OFS(pad),
-			   conf_reg,
-			   IOMUX_SEL_INPUT_OFS(pad),
-			   IOMUX_MODE(pad),
-			   pad_ctrl,
-			   IOMUX_SEL_INPUT(pad));
-}
-
-
-
-/*
- * setups a single pad in the iomuxer
- */
-int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-
-/*
- * setups mutliple pads
- * convenient way to call the above function with tables
- */
-int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count);
-
-#endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/mach-imx/include/mach/iomux-vf610.h b/arch/arm/mach-imx/include/mach/iomux-vf610.h
deleted file mode 100644
index b9e509b396..0000000000
--- a/arch/arm/mach-imx/include/mach/iomux-vf610.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MACH_IOMUX_VF610_H__
-#define __MACH_IOMUX_VF610_H__
-
-#include <mach/iomux-v3.h>
-
-#undef PAD_CTL_ODE
-#undef PAD_CTL_PKE
-#undef PAD_CTL_PUE
-
-enum {
-	PAD_MUX_MODE_SHIFT		= 20,
-	PAD_CTL_INPUT_DIFFERENTIAL	= 1 << 16,
-	PAD_CTL_SPEED_MED		= 1 << 12,
-	PAD_CTL_SPEED_HIGH		= 3 << 12,
-	PAD_CTL_SRE			= 1 << 11,
-	PAD_CTL_ODE			= 1 << 10,
-	PAD_CTL_DSE_150ohm		= 1 << 6,
-	PAD_CTL_DSE_50ohm		= 3 << 6,
-	PAD_CTL_DSE_25ohm		= 6 << 6,
-	PAD_CTL_DSE_20ohm		= 7 << 6,
-	PAD_CTL_PKE			= 1 << 3,
-	PAD_CTL_PUE			= 1 << 2 | PAD_CTL_PKE,
-	PAD_CTL_OBE_IBE_ENABLE		= 3 << 0,
-	PAD_CTL_OBE_ENABLE		= 1 << 1,
-	PAD_CTL_IBE_ENABLE		= 1 << 0,
-};
-
-/* These 2 defines are for pins that may not have a mux register, but could
- * have a pad setting register, and vice-versa. */
-#define __NA_	0x00
-
-/* Pad control groupings */
-enum {
-
-	VF610_UART_PAD_CTRL	= PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE,
-	VF610_SDHC_PAD_CTRL	= PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE,
-	VF610_ENET_PAD_CTRL	= PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE,
-	VF610_DDR_PAD_CTRL	= PAD_CTL_DSE_25ohm,
-	VF610_DDR_PAD_CTRL_1	= PAD_CTL_DSE_25ohm | PAD_CTL_INPUT_DIFFERENTIAL,
-	VF610_I2C_PAD_CTRL	= PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | PAD_CTL_OBE_IBE_ENABLE,
-	VF610_NFC_IO_PAD_CTRL	= PAD_CTL_SPEED_MED | PAD_CTL_SRE | PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | PAD_CTL_OBE_IBE_ENABLE,
-	VF610_NFC_CN_PAD_CTRL	= PAD_CTL_SPEED_MED | PAD_CTL_SRE | PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE,
-	VF610_NFC_RB_PAD_CTRL	= PAD_CTL_SPEED_MED | PAD_CTL_SRE | PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE,
-	VF610_QSPI_PAD_CTRL	= PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE,
-	VF610_GPIO_PAD_CTRL	= PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | PAD_CTL_IBE_ENABLE,
-	VF610_DSPI_PAD_CTRL	= PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH,
-	VF610_DSPI_SIN_PAD_CTRL	= PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH,
-};
-
-enum {
-	VF610_PAD_PTA6__RMII0_CLKIN	= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTA6__RMII0_CLKOUT	= IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTA7__GPIO_134	= IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTA17__GPIO_7		= IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTA20__GPIO_10	= IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTA21__GPIO_11	= IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTA30__GPIO_20	= IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTA31__GPIO_21	= IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB0__GPIO_22		= IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB1__GPIO_23		= IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB4__UART1_TX	= IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
-	VF610_PAD_PTB5__UART1_RX	= IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
-	VF610_PAD_PTB6__GPIO_28		= IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB7__GPIO_29		= IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB8__GPIO_30		= IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB9__GPIO_31		= IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB10__UART0_TX	= IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL),
-	VF610_PAD_PTB11__UART0_RX	= IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL),
-	VF610_PAD_PTB12__GPIO_34	= IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB13__GPIO_35	= IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB16__GPIO_38	= IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB17__GPIO_39	= IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB18__GPIO_40	= IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB21__GPIO_43	= IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB22__GPIO_44	= IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB23__GPIO_93	= IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB26__GPIO_96	= IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTB28__GPIO_98	= IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC1__GPIO_46		= IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC1__RMII0_MDIO	= IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC0__GPIO_45		= IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC0__RMII0_MDC	= IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC2__RMII0_CRS_DV	= IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC2__GPIO_47		= IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC3__RMII0_RD1	= IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC3__GPIO_48		= IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC4__RMII0_RD0	= IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC4__GPIO_49		= IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC5__RMII0_RXER	= IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC5__GPIO_50		= IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC6__RMII0_TD1	= IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC6__GPIO_51		= IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC7__RMII0_TD0	= IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC7__GPIO_52		= IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC8__RMII0_TXEN	= IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC8__GPIO_53		= IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC10__RMII1_MDIO	= IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC9__RMII1_MDC	= IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC11__RMII1_CRS_DV	= IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC12__RMII1_RD1	= IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC13__RMII1_RD0	= IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC14__RMII1_RXER	= IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC15__RMII1_TD1	= IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC16__RMII1_TD0	= IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTC17__RMII1_TXEN	= IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
-	VF610_PAD_PTD5__DSPI1_CS0	= IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL),
-	VF610_PAD_PTD6__DSPI1_SIN	= IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL),
-	VF610_PAD_PTD7__DSPI1_SOUT	= IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL),
-	VF610_PAD_PTD8__DSPI1_SCK	= IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL),
-	VF610_PAD_PTC29__GPIO_102	= IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTC30__GPIO_103	= IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTA24__ESDHC1_CLK	= IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
-	VF610_PAD_PTA25__ESDHC1_CMD	= IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
-	VF610_PAD_PTA26__ESDHC1_DAT0	= IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
-	VF610_PAD_PTA27__ESDHC1_DAT1	= IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
-	VF610_PAD_PTA28__ESDHC1_DAT2	= IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
-	VF610_PAD_PTA29__ESDHC1_DAT3	= IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
-	VF610_PAD_PTB14__I2C0_SCL	= IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
-	VF610_PAD_PTB15__I2C0_SDA	= IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
-	VF610_PAD_PTA22__I2C2_SCL	= IOMUX_PAD(0x0030, 0x0030, 6, 0x034c, 0, VF610_I2C_PAD_CTRL),
-	VF610_PAD_PTA23__I2C2_SDA	= IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, VF610_I2C_PAD_CTRL),
-	VF610_PAD_PTD31__NF_IO15	= IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD31__GPIO_63	= IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD30__NF_IO14	= IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD30__GPIO_64	= IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD29__NF_IO13	= IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD29__GPIO_65	= IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD28__NF_IO12	= IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD28__GPIO_66	= IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD27__NF_IO11	= IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD27__GPIO_67	= IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD26__NF_IO10	= IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD26__GPIO_68	= IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD25__NF_IO9		= IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD25__GPIO_69	= IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD24__NF_IO8		= IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD24__GPIO_70	= IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD23__NF_IO7		= IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD0__QSPI0_A_QSCK	= IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD1__QSPI0_A_CS0	= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD2__QSPI0_A_DATA3	= IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD3__QSPI0_A_DATA2	= IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD4__GPIO_83		= IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD4__QSPI0_A_DATA1	= IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD5__QSPI0_A_DATA0	= IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD7__QSPI0_B_QSCK	= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD8__QSPI0_B_CS0	= IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD9__QSPI0_B_DATA3	= IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD9__GPIO_88		= IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD10__QSPI0_B_DATA2	= IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD10__GPIO_89	= IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD11__QSPI0_B_DATA1	= IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD11__GPIO_90	= IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD12__QSPI0_B_DATA0	= IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD12__GPIO_91	= IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD13__GPIO_92	= IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD22__NF_IO6		= IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD21__NF_IO5		= IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD20__NF_IO4		= IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD19__GPIO_75	= IOMUX_PAD(0x012C, 0x012C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD19__NF_IO3		= IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD18__GPIO_76	= IOMUX_PAD(0x0120, 0x0130, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD18__NF_IO2		= IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD17__GPIO_77	= IOMUX_PAD(0x0134, 0x0134, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD17__NF_IO1		= IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTD16__GPIO_78	= IOMUX_PAD(0x0138, 0x0138, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
-	VF610_PAD_PTD16__NF_IO0		= IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
-	VF610_PAD_PTB24__NF_WE_B	= IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
-	VF610_PAD_PTB25__NF_CE0_B	= IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
-	VF610_PAD_PTB27__NF_RE_B 	= IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
-	VF610_PAD_PTC26__NF_RB_B 	= IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
-	VF610_PAD_PTC27__NF_ALE  	= IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
-	VF610_PAD_PTC28__NF_CLE  	= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
-	VF610_PAD_DDR_RESETB		= IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A15__DDR_A_15	= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A14__DDR_A_14	= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A13__DDR_A_13	= IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A12__DDR_A_12	= IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A11__DDR_A_11	= IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A10__DDR_A_10	= IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A9__DDR_A_9	= IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A8__DDR_A_8	= IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A7__DDR_A_7	= IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A6__DDR_A_6	= IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A5__DDR_A_5	= IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A4__DDR_A_4	= IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A3__DDR_A_3	= IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A2__DDR_A_2	= IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A1__DDR_A_1	= IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_A0__DDR_A_0	= IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_BA2__DDR_BA_2	= IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_BA1__DDR_BA_1	= IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_BA0__DDR_BA_0	= IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_CAS__DDR_CAS_B	= IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_CKE__DDR_CKE_0	= IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_CLK__DDR_CLK_0	= IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_CS__DDR_CS_B_0	= IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_D15__DDR_D_15	= IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D14__DDR_D_14	= IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D13__DDR_D_13	= IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D12__DDR_D_12	= IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D11__DDR_D_11	= IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D10__DDR_D_10	= IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D9__DDR_D_9	= IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D8__DDR_D_8	= IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D7__DDR_D_7	= IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D6__DDR_D_6	= IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D5__DDR_D_5	= IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D4__DDR_D_4	= IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D3__DDR_D_3	= IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D2__DDR_D_2	= IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D1__DDR_D_1	= IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_D0__DDR_D_0	= IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_DQM1__DDR_DQM_1	= IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_DQM0__DDR_DQM_0	= IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_DQS1__DDR_DQS_1	= IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_DQS0__DDR_DQS_0	= IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
-	VF610_PAD_DDR_RAS__DDR_RAS_B	= IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_WE__DDR_WE_B	= IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_ODT1__DDR_ODT_0	= IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_DDR_ODT0__DDR_ODT_1	= IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-};
-
-#define PINCTRL_VF610_MUX_SHIFT 20
-
-
-static inline void vf610_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad)
-{
-	iomux_v3_setup_pad(iomux, SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
-			   IOMUX_CTRL_OFS(pad),
-			   IOMUX_PAD_CTRL_OFS(pad),
-			   IOMUX_SEL_INPUT_OFS(pad),
-			   IOMUX_MODE(pad) << PINCTRL_VF610_MUX_SHIFT,
-			   IOMUX_PAD_CTRL(pad),
-			   IOMUX_SEL_INPUT(pad));
-}
-
-
-#endif	/* __IOMUX_VF610_H__ */
diff --git a/arch/arm/mach-imx/include/mach/ocotp-fusemap.h b/arch/arm/mach-imx/include/mach/ocotp-fusemap.h
deleted file mode 100644
index aec50dbf8a..0000000000
--- a/arch/arm/mach-imx/include/mach/ocotp-fusemap.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef __MACH_IMX_OCOTP_FUSEMAP_H
-#define __MACH_IMX_OCOTP_FUSEMAP_H
-
-#include <mach/ocotp.h>
-
-#define OCOTP_TESTER_LOCK		(OCOTP_WORD(0x400) | OCOTP_BIT(0) | OCOTP_WIDTH(2))
-#define OCOTP_BOOT_CFG_LOCK		(OCOTP_WORD(0x400) | OCOTP_BIT(2) | OCOTP_WIDTH(2))
-#define OCOTP_MEM_TRIM_LOCK		(OCOTP_WORD(0x400) | OCOTP_BIT(4) | OCOTP_WIDTH(2))
-#define OCOTP_SJC_RESP_LOCK		(OCOTP_WORD(0x400) | OCOTP_BIT(6) | OCOTP_WIDTH(1))
-#define OCOTP_MAC_ADDR_LOCK		(OCOTP_WORD(0x400) | OCOTP_BIT(8) | OCOTP_WIDTH(2))
-#define OCOTP_GP1_LOCK			(OCOTP_WORD(0x400) | OCOTP_BIT(10) | OCOTP_WIDTH(2))
-#define OCOTP_GP2_LOCK			(OCOTP_WORD(0x400) | OCOTP_BIT(12) | OCOTP_WIDTH(2))
-#define OCOTP_SRK_LOCK			(OCOTP_WORD(0x400) | OCOTP_BIT(14) | OCOTP_WIDTH(1))
-#define OCOTP_ANALOG_LOCK		(OCOTP_WORD(0x400) | OCOTP_BIT(18) | OCOTP_WIDTH(2))
-#define OCOTP_MISC_CONF_LOCK		(OCOTP_WORD(0x400) | OCOTP_BIT(22) | OCOTP_WIDTH(1))
-
-/* 0 <= n <= 1 */
-#define OCOTP_UNIQUE_ID(n)		(OCOTP_WORD(0x410 + 0x10 * (n)) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
-#define OCOTP_NUM_CORES			(OCOTP_WORD(0x430) | OCOTP_BIT(20) | OCOTP_WIDTH(2))
-#define OCOTP_MLB_DISABLE		(OCOTP_WORD(0x430) | OCOTP_BIT(26) | OCOTP_WIDTH(1))
-
-#define OCOTP_BOOT_CFG1			(OCOTP_WORD(0x450) | OCOTP_BIT(0) | OCOTP_WIDTH(8))
-#define OCOTP_BOOT_CFG2			(OCOTP_WORD(0x450) | OCOTP_BIT(8) | OCOTP_WIDTH(8))
-#define OCOTP_BOOT_CFG3			(OCOTP_WORD(0x450) | OCOTP_BIT(16) | OCOTP_WIDTH(8))
-#define OCOTP_BOOT_CFG4			(OCOTP_WORD(0x450) | OCOTP_BIT(24) | OCOTP_WIDTH(8))
-/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */
-#define OCOTP_SDP_DISABLE		(OCOTP_WORD(0x460) | OCOTP_BIT(0) | OCOTP_WIDTH(1))
-#define OCOTP_SEC_CONFIG_1		(OCOTP_WORD(0x460) | OCOTP_BIT(1) | OCOTP_WIDTH(1))
-/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */
-#define OCOTP_SDP_READ_DISABLE		(OCOTP_WORD(0x460) | OCOTP_BIT(2) | OCOTP_WIDTH(1))
-#define OCOTP_DIR_BT_DIS		(OCOTP_WORD(0x460) | OCOTP_BIT(3) | OCOTP_WIDTH(1))
-#define OCOTP_BT_FUSE_SEL		(OCOTP_WORD(0x460) | OCOTP_BIT(4) | OCOTP_WIDTH(1))
-#define OCOTP_SJC_DISABLE		(OCOTP_WORD(0x460) | OCOTP_BIT(20) | OCOTP_WIDTH(1))
-#define OCOTP_WDOG_ENABLE		(OCOTP_WORD(0x460) | OCOTP_BIT(21) | OCOTP_WIDTH(1))
-#define OCOTP_JTAG_SMODE		(OCOTP_WORD(0x460) | OCOTP_BIT(22) | OCOTP_WIDTH(2))
-#define OCOTP_KTE			(OCOTP_WORD(0x460) | OCOTP_BIT(26) | OCOTP_WIDTH(1))
-#define OCOTP_JTAG_HEO			(OCOTP_WORD(0x460) | OCOTP_BIT(27) | OCOTP_WIDTH(1))
-/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */
-#define OCOTP_FORCE_INTERNAL_BOOT	(OCOTP_WORD(0x460) | OCOTP_BIT(31) | OCOTP_WIDTH(1))
-#define OCOTP_NAND_READ_CMD_CODE1	(OCOTP_WORD(0x470) | OCOTP_BIT(0) | OCOTP_WIDTH(8))
-#define OCOTP_NAND_READ_CMD_CODE2	(OCOTP_WORD(0x470) | OCOTP_BIT(8) | OCOTP_WIDTH(8))
-#define OCOTP_TEMP_SENSE		(OCOTP_WORD(0x4e0) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
-#define OCOTP_USB_VID			(OCOTP_WORD(0x4f0) | OCOTP_BIT(0) | OCOTP_WIDTH(16))
-#define OCOTP_USB_PID			(OCOTP_WORD(0x4f0) | OCOTP_BIT(16) | OCOTP_WIDTH(16))
-/* 0 <= n <= 7 */
-#define OCOTP_SRK_HASH(n)		(OCOTP_WORD(0x580 + 0x10 * (n)) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
-#define OCOTP_SJC_RESP_31_0		(OCOTP_WORD(0x600) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
-#define OCOTP_SJC_RESP_55_32		(OCOTP_WORD(0x610) | OCOTP_BIT(0) | OCOTP_WIDTH(24))
-#define OCOTP_MAC_ADDR_31_0		(OCOTP_WORD(0x620) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
-#define OCOTP_MAC_ADDR_47_32		(OCOTP_WORD(0x630) | OCOTP_BIT(0) | OCOTP_WIDTH(16))
-#define OCOTP_GP1			(OCOTP_WORD(0x660) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
-#define OCOTP_GP2			(OCOTP_WORD(0x670) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
-#define OCOTP_PAD_SETTINGS		(OCOTP_WORD(0x6d0) | OCOTP_BIT(0) | OCOTP_WIDTH(6))
-
-#endif /* __MACH_IMX_OCOTP_FUSEMAP_H */
diff --git a/arch/arm/mach-imx/include/mach/ocotp.h b/arch/arm/mach-imx/include/mach/ocotp.h
deleted file mode 100644
index 20205c5da7..0000000000
--- a/arch/arm/mach-imx/include/mach/ocotp.h
+++ /dev/null
@@ -1,49 +0,0 @@
-#ifndef __MACH_IMX_OCOTP_H
-#define __MACH_IMX_OCOTP_H
-
-#include <linux/bitfield.h>
-#include <linux/types.h>
-
-#define OCOTP_SHADOW_OFFSET		0x400
-#define OCOTP_SHADOW_SPACING		0x10
-
-/*
- * Trivial shadow register offset -> ocotp register index.
- *
- * NOTE: Doesn't handle special mapping quirks. See
- * imx6q_addr_to_offset and vf610_addr_to_offset for more details. Use
- * with care
- */
-#define OCOTP_OFFSET_TO_INDEX(o)		\
-	(((o) - OCOTP_SHADOW_OFFSET) / OCOTP_SHADOW_SPACING)
-
-#define OCOTP_WORD_MASK		GENMASK( 7,  0)
-#define OCOTP_BIT_MASK		GENMASK(12,  8)
-#define OCOTP_WIDTH_MASK 	GENMASK(17, 13)
-
-#define OCOTP_WORD(n)		FIELD_PREP(OCOTP_WORD_MASK, \
-					   OCOTP_OFFSET_TO_INDEX(n))
-#define OCOTP_BIT(n)		FIELD_PREP(OCOTP_BIT_MASK, n)
-#define OCOTP_WIDTH(n)		FIELD_PREP(OCOTP_WIDTH_MASK, (n) - 1)
-
-#define OCOTP_UID_L		0x410
-#define OCOTP_UID_H		0x420
-
-
-int imx_ocotp_read_field(uint32_t field, unsigned *value);
-int imx_ocotp_write_field(uint32_t field, unsigned value);
-int imx_ocotp_permanent_write(int enable);
-bool imx_ocotp_sense_enable(bool enable);
-
-static inline u64 imx_ocotp_read_uid(void __iomem *ocotp)
-{
-	u64 uid;
-
-	uid  = readl(ocotp + OCOTP_UID_H);
-	uid <<= 32;
-	uid |= readl(ocotp + OCOTP_UID_L);
-
-	return uid;
-}
-
-#endif /* __MACH_IMX_OCOTP_H */
diff --git a/arch/arm/mach-imx/include/mach/reset-reason.h b/arch/arm/mach-imx/include/mach/reset-reason.h
deleted file mode 100644
index 91a8171896..0000000000
--- a/arch/arm/mach-imx/include/mach/reset-reason.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef __MACH_RESET_REASON_H__
-#define __MACH_RESET_REASON_H__
-
-#include <reset_source.h>
-
-#define IMX_SRC_SRSR_IPP_RESET		BIT(0)
-#define IMX_SRC_SRSR_CSU_RESET		BIT(2)
-#define IMX_SRC_SRSR_IPP_USER_RESET	BIT(3)
-#define IMX_SRC_SRSR_WDOG1_RESET	BIT(4)
-#define IMX_SRC_SRSR_JTAG_RESET		BIT(5)
-#define IMX_SRC_SRSR_JTAG_SW_RESET	BIT(6)
-#define IMX_SRC_SRSR_WDOG3_RESET	BIT(7)
-#define IMX_SRC_SRSR_WDOG4_RESET	BIT(8)
-#define IMX_SRC_SRSR_TEMPSENSE_RESET	BIT(9)
-#define IMX_SRC_SRSR_WARM_BOOT		BIT(16)
-
-#define IMX_SRC_SRSR	0x008
-#define IMX7_SRC_SRSR	0x05c
-
-#define VF610_SRC_SRSR_SW_RST		BIT(18)
-#define VF610_SRC_SRSR_RESETB		BIT(7)
-#define VF610_SRC_SRSR_JTAG_RST		BIT(5)
-#define VF610_SRC_SRSR_WDOG_M4		BIT(4)
-#define VF610_SRC_SRSR_WDOG_A5		BIT(3)
-#define VF610_SRC_SRSR_POR_RST		BIT(0)
-
-struct imx_reset_reason {
-	uint32_t mask;
-	enum reset_src_type type;
-	int instance;
-};
-
-void imx_set_reset_reason(void __iomem *, const struct imx_reset_reason *);
-
-extern const struct imx_reset_reason imx_reset_reasons[];
-extern const struct imx_reset_reason imx7_reset_reasons[];
-
-#endif /* __MACH_RESET_REASON_H__ */
diff --git a/arch/arm/mach-imx/include/mach/revision.h b/arch/arm/mach-imx/include/mach/revision.h
deleted file mode 100644
index d9495d967f..0000000000
--- a/arch/arm/mach-imx/include/mach/revision.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __MACH_REVISION_H__
-#define __MACH_REVISION_H__
-
-/* silicon revisions  */
-#define IMX_CHIP_REV_1_0	0x10
-#define IMX_CHIP_REV_1_1	0x11
-#define IMX_CHIP_REV_1_2	0x12
-#define IMX_CHIP_REV_1_3	0x13
-#define IMX_CHIP_REV_1_4	0x14
-#define IMX_CHIP_REV_1_5	0x15
-#define IMX_CHIP_REV_1_6	0x16
-#define IMX_CHIP_REV_2_0	0x20
-#define IMX_CHIP_REV_2_1	0x21
-#define IMX_CHIP_REV_2_2	0x22
-#define IMX_CHIP_REV_2_3	0x23
-#define IMX_CHIP_REV_3_0	0x30
-#define IMX_CHIP_REV_3_1	0x31
-#define IMX_CHIP_REV_3_2	0x32
-#define IMX_CHIP_REV_UNKNOWN	0xff
-
-int imx_silicon_revision(void);
-
-void imx_set_silicon_revision(const char *soc, int revision);
-
-#endif /* __MACH_REVISION_H__ */
diff --git a/arch/arm/mach-imx/include/mach/spi.h b/arch/arm/mach-imx/include/mach/spi.h
deleted file mode 100644
index 08be445e8e..0000000000
--- a/arch/arm/mach-imx/include/mach/spi.h
+++ /dev/null
@@ -1,27 +0,0 @@
-
-#ifndef __MACH_SPI_H_
-#define __MACH_SPI_H_
-
-/*
- * struct spi_imx_master - device.platform_data for SPI controller devices.
- * @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio
- *              pins, numbers < 0 mean internal CSPI chipselects according
- *              to MXC_SPI_CS(). Normally you want to use gpio based chip
- *              selects as the CSPI module tries to be intelligent about
- *              when to assert the chipselect: The CSPI module deasserts the
- *              chipselect once it runs out of input data. The other problem
- *              is that it is not possible to mix between high active and low
- *              active chipselects on one single bus using the internal
- *              chipselects. Unfortunately Freescale decided to put some
- *              chipselects on dedicated pins which are not usable as gpios,
- *              so we have to support the internal chipselects.
- * @num_chipselect: ARRAY_SIZE(chipselect)
- */
-struct spi_imx_master {
-	int	*chipselect;
-	int	num_chipselect;
-};
-
-#define MXC_SPI_CS(no)	((no) - 32)
-
-#endif /* __MACH_SPI_H_*/
diff --git a/arch/arm/mach-imx/include/mach/usb.h b/arch/arm/mach-imx/include/mach/usb.h
deleted file mode 100644
index 3209bf9095..0000000000
--- a/arch/arm/mach-imx/include/mach/usb.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __MACH_USB_H_
-#define __MACH_USB_H_
-
-/* configuration bits for i.MX25 and i.MX35 */
-#define MX35_H1_SIC_SHIFT	21
-#define MX35_H1_SIC_MASK	(0x3 << MX35_H1_SIC_SHIFT)
-#define MX35_H1_PM_BIT		(1 << 16)
-#define MX35_H1_IPPUE_UP_BIT	(1 << 7)
-#define MX35_H1_IPPUE_DOWN_BIT	(1 << 6)
-#define MX35_H1_TLL_BIT		(1 << 5)
-#define MX35_H1_USBTE_BIT	(1 << 4)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
-
-#define USBCMD	0x140
-#define USB_CMD_RESET	0x00000002
-
-/*
- * imx_reset_otg_controller - reset the USB OTG controller
- * @base: The base address of the controller
- *
- * When booting from USB the ROM just leaves the controller enabled. This can
- * have bad side effects when for example we change PLL frequencies. In this
- * case it is seen that the hub the board is connected to gets confused and USB
- * is no longer working properly on the remote host. This function resets the
- * OTG controller. It should be called before the clocks the controller hangs on
- * is fiddled with.
- */
-static inline void imx_reset_otg_controller(void __iomem *base)
-{
-	u32 r;
-
-	r = readl(base + USBCMD);
-	r |= USB_CMD_RESET;
-	writel(r, base + USBCMD);
-}
-
-#endif /* __MACH_USB_H_*/
diff --git a/arch/arm/mach-imx/include/mach/vf610-ddrmc-regs.h b/arch/arm/mach-imx/include/mach/vf610-ddrmc-regs.h
deleted file mode 100644
index 33c1aaddf3..0000000000
--- a/arch/arm/mach-imx/include/mach/vf610-ddrmc-regs.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * VFxxx DDRMC register addresses definitions for use in DCD
- *
- * Copyright (C) 2018 Zodiac Inflight Innovations
- */
-
-#define DDRMC_CR00	0x400ae000
-#define DDRMC_CR02	0x400ae008
-#define DDRMC_CR10	0x400ae028
-#define DDRMC_CR11	0x400ae02c
-#define DDRMC_CR12	0x400ae030
-#define DDRMC_CR13	0x400ae034
-#define DDRMC_CR14	0x400ae038
-#define DDRMC_CR16	0x400ae040
-#define DDRMC_CR17	0x400ae044
-#define DDRMC_CR18	0x400ae048
-#define DDRMC_CR20	0x400ae050
-#define DDRMC_CR21	0x400ae054
-#define DDRMC_CR22	0x400ae058
-#define DDRMC_CR23	0x400ae05c
-#define DDRMC_CR24	0x400ae060
-#define DDRMC_CR25	0x400ae064
-#define DDRMC_CR26	0x400ae068
-#define DDRMC_CR28	0x400ae070
-#define DDRMC_CR29	0x400ae074
-#define DDRMC_CR30	0x400ae078
-#define DDRMC_CR31	0x400ae07c
-#define DDRMC_CR33	0x400ae084
-#define DDRMC_CR34	0x400ae088
-#define DDRMC_CR38	0x400ae098
-#define DDRMC_CR39	0x400ae09c
-#define DDRMC_CR41	0x400ae0a4
-#define DDRMC_CR48	0x400ae0c0
-#define DDRMC_CR49	0x400ae0c4
-#define DDRMC_CR51	0x400ae0cc
-#define DDRMC_CR57	0x400ae0e4
-#define DDRMC_CR66	0x400ae108
-#define DDRMC_CR67	0x400ae10c
-#define DDRMC_CR69	0x400ae114
-#define DDRMC_CR70	0x400ae118
-#define DDRMC_CR72	0x400ae120
-#define DDRMC_CR73	0x400ae124
-#define DDRMC_CR74	0x400ae128
-#define DDRMC_CR75	0x400ae12c
-#define DDRMC_CR76	0x400ae130
-#define DDRMC_CR77	0x400ae134
-#define DDRMC_CR78	0x400ae138
-#define DDRMC_CR79	0x400ae13c
-#define DDRMC_CR82	0x400ae148
-#define DDRMC_CR87	0x400ae15c
-#define DDRMC_CR88	0x400ae160
-#define DDRMC_CR89	0x400ae164
-#define DDRMC_CR91	0x400ae16c
-#define DDRMC_CR96	0x400ae180
-#define DDRMC_CR97	0x400ae184
-#define DDRMC_CR98	0x400ae188
-#define DDRMC_CR99	0x400ae18c
-#define DDRMC_CR102	0x400ae198
-#define DDRMC_CR105	0x400ae1a4
-#define DDRMC_CR106	0x400ae1a8
-#define DDRMC_CR110	0x400ae1b8
-#define DDRMC_CR114	0x400ae1c8
-#define DDRMC_CR115	0x400ae1cc
-#define DDRMC_CR117	0x400ae1d4
-#define DDRMC_CR118	0x400ae1d8
-#define DDRMC_CR120	0x400ae1e0
-#define DDRMC_CR121	0x400ae1e4
-#define DDRMC_CR122	0x400ae1e8
-#define DDRMC_CR123	0x400ae1ec
-#define DDRMC_CR124	0x400ae1f0
-#define DDRMC_CR126	0x400ae1f8
-#define DDRMC_CR132	0x400ae210
-#define DDRMC_CR137	0x400ae224
-#define DDRMC_CR138	0x400ae228
-#define DDRMC_CR139	0x400ae22c
-#define DDRMC_CR140	0x400ae230
-#define DDRMC_CR143	0x400ae23c
-#define DDRMC_CR144	0x400ae240
-#define DDRMC_CR145	0x400ae244
-#define DDRMC_CR146	0x400ae248
-#define DDRMC_CR147	0x400ae24c
-#define DDRMC_CR148	0x400ae250
-#define DDRMC_CR151	0x400ae25c
-#define DDRMC_CR154	0x400ae268
-#define DDRMC_CR155	0x400ae26c
-#define DDRMC_CR158	0x400ae278
-#define DDRMC_CR161	0x400ae284
-
-#define DDRMC_CR00_DRAM_CLASS_DDR3		0x00000600
-#define DDRMC_CR00_DRAM_CLASS_DDR3_START	0x00000601
-
-#define DDRMC_PHY00 0x400ae400
-#define DDRMC_PHY01 0x400ae404
-#define DDRMC_PHY02 0x400ae408
-#define DDRMC_PHY03 0x400ae40c
-#define DDRMC_PHY04 0x400ae410
-#define DDRMC_PHY16 0x400ae440
-#define DDRMC_PHY17 0x400ae444
-#define DDRMC_PHY18 0x400ae448
-#define DDRMC_PHY19 0x400ae44c
-#define DDRMC_PHY20 0x400ae450
-#define DDRMC_PHY32 0x400ae480
-#define DDRMC_PHY34 0x400ae488
-#define DDRMC_PHY35 0x400ae48c
-#define DDRMC_PHY36 0x400ae490
-#define DDRMC_PHY49 0x400ae4c4
-#define DDRMC_PHY50 0x400ae4c8
-#define DDRMC_PHY52 0x400ae4d0
diff --git a/arch/arm/mach-imx/include/mach/vf610-ddrmc.h b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h
deleted file mode 100644
index 07feb036e5..0000000000
--- a/arch/arm/mach-imx/include/mach/vf610-ddrmc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __MACH_DDRMC_H
-#define __MACH_DDRMC_H
-
-#include <mach/vf610-regs.h>
-
-
-#define DDRMC_CR(x)	((x) * 4)
-
-#define DDRMC_CR01_MAX_COL_REG(reg)	(((reg) >>  8) & 0b01111)
-#define DDRMC_CR01_MAX_ROW_REG(reg)	(((reg) >>  0) & 0b11111)
-#define DDRMC_CR73_COL_DIFF(reg)	(((reg) >> 16) & 0b00111)
-#define DDRMC_CR73_ROW_DIFF(reg)	(((reg) >>  8) & 0b00011)
-#define DDRMC_CR73_BANK_DIFF(reg)	(((reg) >>  0) & 0b00011)
-
-#define DDRMC_CR78_REDUC	BIT(8)
-
-
-#endif /* __MACH_MMDC_H */
diff --git a/arch/arm/mach-imx/include/mach/vf610-fusemap.h b/arch/arm/mach-imx/include/mach/vf610-fusemap.h
deleted file mode 100644
index a56faf10cc..0000000000
--- a/arch/arm/mach-imx/include/mach/vf610-fusemap.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __MACH_VF610_OCOTP_H
-#define __MACH_VF610_OCOTP_H
-
-#include <mach/ocotp-fusemap.h>
-
-#define VF610_OCOTP_CPU_BUS_FRQ		OCOTP_WORD(0x430) | OCOTP_BIT(22) | OCOTP_WIDTH(1)
-#define VF610_OCOTP_OVG_DISABLE		OCOTP_WORD(0x430) | OCOTP_BIT(30) | OCOTP_WIDTH(1)
-#define	VF610_OCOTP_SEC_CONFIG_0	OCOTP_WORD(0x440) | OCOTP_BIT(1) | OCOTP_WIDTH(1)
-#define	VF610_OCOTP_SPEED_GRADING	OCOTP_WORD(0x440) | OCOTP_BIT(18) | OCOTP_WIDTH(4)
-#define VF610_OCOTP_MAC_ADDR0_31_0	OCOTP_MAC_ADDR_31_0
-#define VF610_OCOTP_MAC_ADDR0_47_32	OCOTP_MAC_ADDR_47_32
-#define VF610_OCOTP_MAC_ADDR1_31_0	(OCOTP_WORD(0x640) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
-#define VF610_OCOTP_MAC_ADDR1_47_32	(OCOTP_WORD(0x650) | OCOTP_BIT(0) | OCOTP_WIDTH(16))
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h b/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h
deleted file mode 100644
index c85f0b74b9..0000000000
--- a/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * VFxxx IOMUX register addresses definitions for use in DCD
- *
- * Copyright (C) 2018 Zodiac Inflight Innovations
- */
-
-#define VF610_PAD_DDR_RESETB		0x4004821c
-#define VF610_PAD_DDR_A15__DDR_A_15	0x40048220
-#define VF610_PAD_DDR_A14__DDR_A_14	0x40048224
-#define VF610_PAD_DDR_A13__DDR_A_13	0x40048228
-#define VF610_PAD_DDR_A12__DDR_A_12	0x4004822c
-#define VF610_PAD_DDR_A11__DDR_A_11	0x40048230
-#define VF610_PAD_DDR_A10__DDR_A_10	0x40048234
-#define VF610_PAD_DDR_A9__DDR_A_9	0x40048238
-#define VF610_PAD_DDR_A8__DDR_A_8	0x4004823c
-#define VF610_PAD_DDR_A7__DDR_A_7	0x40048240
-#define VF610_PAD_DDR_A6__DDR_A_6	0x40048244
-#define VF610_PAD_DDR_A5__DDR_A_5	0x40048248
-#define VF610_PAD_DDR_A4__DDR_A_4	0x4004824c
-#define VF610_PAD_DDR_A3__DDR_A_3	0x40048250
-#define VF610_PAD_DDR_A2__DDR_A_2	0x40048254
-#define VF610_PAD_DDR_A1__DDR_A_1	0x40048258
-#define VF610_PAD_DDR_A0__DDR_A_0	0x4004825c
-#define VF610_PAD_DDR_BA2__DDR_BA_2	0x40048260
-#define VF610_PAD_DDR_BA1__DDR_BA_1	0x40048264
-#define VF610_PAD_DDR_BA0__DDR_BA_0	0x40048268
-#define VF610_PAD_DDR_CAS__DDR_CAS_B	0x4004826c
-#define VF610_PAD_DDR_CKE__DDR_CKE_0	0x40048270
-#define VF610_PAD_DDR_CLK__DDR_CLK_0	0x40048274
-#define VF610_PAD_DDR_CS__DDR_CS_B_0	0x40048278
-#define VF610_PAD_DDR_D15__DDR_D_15	0x4004827c
-#define VF610_PAD_DDR_D14__DDR_D_14	0x40048280
-#define VF610_PAD_DDR_D13__DDR_D_13	0x40048284
-#define VF610_PAD_DDR_D12__DDR_D_12	0x40048288
-#define VF610_PAD_DDR_D11__DDR_D_11	0x4004828c
-#define VF610_PAD_DDR_D10__DDR_D_10	0x40048290
-#define VF610_PAD_DDR_D9__DDR_D_9	0x40048294
-#define VF610_PAD_DDR_D8__DDR_D_8	0x40048298
-#define VF610_PAD_DDR_D7__DDR_D_7	0x4004829c
-#define VF610_PAD_DDR_D6__DDR_D_6	0x400482a0
-#define VF610_PAD_DDR_D5__DDR_D_5	0x400482a4
-#define VF610_PAD_DDR_D4__DDR_D_4	0x400482a8
-#define VF610_PAD_DDR_D3__DDR_D_3	0x400482ac
-#define VF610_PAD_DDR_D2__DDR_D_2	0x400482b0
-#define VF610_PAD_DDR_D1__DDR_D_1	0x400482b4
-#define VF610_PAD_DDR_D0__DDR_D_0	0x400482b8
-#define VF610_PAD_DDR_DQM1__DDR_DQM_1	0x400482bc
-#define VF610_PAD_DDR_DQM0__DDR_DQM_0	0x400482c0
-#define VF610_PAD_DDR_DQS1__DDR_DQS_1	0x400482c4
-#define VF610_PAD_DDR_DQS0__DDR_DQS_0	0x400482c8
-#define VF610_PAD_DDR_RAS__DDR_RAS_B	0x400482cc
-#define VF610_PAD_DDR_WE__DDR_WE_B	0x400482d0
-#define VF610_PAD_DDR_ODT1__DDR_ODT_0	0x400482d4
-#define VF610_PAD_DDR_ODT0__DDR_ODT_1	0x400482d8
-
-#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	0x400482dc
-#define VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0	0x400482e0
diff --git a/arch/arm/mach-imx/include/mach/vf610-regs.h b/arch/arm/mach-imx/include/mach/vf610-regs.h
deleted file mode 100644
index 416b457aff..0000000000
--- a/arch/arm/mach-imx/include/mach/vf610-regs.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MACH_VF610_REGS_H__
-#define __MACH_VF610_REGS_H__
-
-#define VF610_IRAM_BASE_ADDR		0x3F000000	/* internal ram */
-#define VF610_IRAM_SIZE			0x00080000	/* 512 KB */
-
-#define VF610_AIPS0_BASE_ADDR		0x40000000
-#define VF610_AIPS1_BASE_ADDR		0x40080000
-
-#define VF610_RAM_BASE_ADDR		0x80000000
-
-/* AIPS 0 */
-#define VF610_MSCM_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00001000)
-#define VF610_MSCM_IR_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00001800)
-#define VF610_CA5SCU_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00002000)
-#define VF610_CA5_INTD_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00003000)
-#define VF610_CA5_L2C_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00006000)
-#define VF610_NIC0_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00008000)
-#define VF610_NIC1_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00009000)
-#define VF610_NIC2_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0000A000)
-#define VF610_NIC3_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0000B000)
-#define VF610_NIC4_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0000C000)
-#define VF610_NIC5_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0000D000)
-#define VF610_NIC6_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0000E000)
-#define VF610_NIC7_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0000F000)
-#define VF610_AHBTZASC_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00010000)
-#define VF610_TZASC_SYS0_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00011000)
-#define VF610_TZASC_SYS1_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00012000)
-#define VF610_TZASC_GFX_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00013000)
-#define VF610_TZASC_DDR0_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00014000)
-#define VF610_TZASC_DDR1_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00015000)
-#define VF610_CSU_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00017000)
-#define VF610_DMA0_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00018000)
-#define VF610_DMA0_TCD_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00019000)
-#define VF610_SEMA4_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0001D000)
-#define VF610_FB_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0001E000)
-#define VF610_DMA_MUX0_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00024000)
-#define VF610_UART1_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00027000)
-#define VF610_UART2_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00028000)
-#define VF610_UART3_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00029000)
-#define VF610_UART4_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0002A000)
-#define VF610_SPI0_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0002C000)
-#define VF610_SPI1_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0002D000)
-#define VF610_SAI0_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0002F000)
-#define VF610_SAI1_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00030000)
-#define VF610_SAI2_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00031000)
-#define VF610_SAI3_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00032000)
-#define VF610_CRC_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00033000)
-#define VF610_USBC0_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00034000)
-#define VF610_PDB_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00036000)
-#define VF610_PIT_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00037000)
-#define VF610_FTM0_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00038000)
-#define VF610_FTM1_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00039000)
-#define VF610_ADC_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0003B000)
-#define VF610_TCON0_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0003D000)
-#define VF610_WDOG1_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0003E000)
-#define VF610_LPTMR_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00040000)
-#define VF610_RLE_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00042000)
-#define VF610_MLB_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00043000)
-#define VF610_QSPI0_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00044000)
-#define VF610_IOMUXC_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00048000)
-#define VF610_ANADIG_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00050000)
-#define VF610_USB_PHY0_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00050800)
-#define VF610_USB_PHY1_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00050C00)
-#define VF610_SCSC_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00052000)
-#define VF610_ASRC_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00060000)
-#define VF610_SPDIF_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00061000)
-#define VF610_ESAI_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00062000)
-#define VF610_ESAI_FIFO_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x00063000)
-#define VF610_WDOG_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00065000)
-#define VF610_I2C1_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00066000)
-#define VF610_I2C2_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00067000)
-#define VF610_I2C3_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x000E6000)
-#define VF610_I2C4_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x000E7000)
-#define VF610_WKUP_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0006A000)
-#define VF610_CCM_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0006B000)
-#define VF610_GPC_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0006C000)
-#define VF610_VREG_DIG_BASE_ADDR	(VF610_AIPS0_BASE_ADDR + 0x0006D000)
-#define VF610_SRC_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0006E000)
-#define VF610_CMU_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x0006F000)
-#define VF610_GPIO0_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x000FF000)
-#define VF610_GPIO1_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x000FF040)
-#define VF610_GPIO2_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x000FF080)
-#define VF610_GPIO3_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x000FF0C0)
-#define VF610_GPIO4_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x000FF100)
-
-/* AIPS 1 */
-#define VF610_OCOTP_BASE_ADDR		(VF610_AIPS1_BASE_ADDR + 0x00025000)
-#define VF610_DDR_BASE_ADDR		(VF610_AIPS1_BASE_ADDR + 0x0002E000)
-#define VF610_ESDHC0_BASE_ADDR		(VF610_AIPS1_BASE_ADDR + 0x00031000)
-#define VF610_ESDHC1_BASE_ADDR		(VF610_AIPS1_BASE_ADDR + 0x00032000)
-#define VF610_USBC1_BASE_ADDR		(VF610_AIPS1_BASE_ADDR + 0x00034000)
-#define VF610_ENET_BASE_ADDR		(VF610_AIPS1_BASE_ADDR + 0x00050000)
-#define VF610_ENET1_BASE_ADDR		(VF610_AIPS1_BASE_ADDR + 0x00051000)
-#define VF610_NFC_BASE_ADDR		(VF610_AIPS1_BASE_ADDR + 0x00060000)
-
-#define VF610_QSPI0_AMBA_BASE		0x20000000
-
-
-/* MSCM interrupt rounter */
-#define VF610_MSCM_IRSPRC(n)		(0x880 + 2 * (n))
-#define VF610_MSCM_CPxTYPE		0
-#define VF610_MSCM_IRSPRC_CP0_EN	1
-#define VF610_MSCM_IRSPRC_NUM		112
-
-#define VF610_MSCM_CPxCOUNT		0x00c
-#define VF610_MSCM_CPxCFG1		0x014
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/vf610.h b/arch/arm/mach-imx/include/mach/vf610.h
deleted file mode 100644
index 7ac10a7b1e..0000000000
--- a/arch/arm/mach-imx/include/mach/vf610.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef __MACH_VF610_H
-#define __MACH_VF610_H
-
-#include <io.h>
-#include <mach/generic.h>
-#include <mach/vf610-regs.h>
-#include <mach/revision.h>
-
-#define VF610_CPUTYPE_VFx10	0x010
-
-#define VF610_CPUTYPE_VF610	0x610
-#define VF610_CPUTYPE_VF600	0x600
-#define VF610_CPUTYPE_VF510	0x510
-#define VF610_CPUTYPE_VF500	0x500
-
-#define VF610_ROM_VERSION_OFFSET	0x80
-
-static inline int __vf610_cpu_type(void)
-{
-	void __iomem *mscm = IOMEM(VF610_MSCM_BASE_ADDR);
-	const u32 cpxcount = readl(mscm + VF610_MSCM_CPxCOUNT);
-	const u32 cpxcfg1  = readl(mscm + VF610_MSCM_CPxCFG1);
-	int cpu_type;
-
-	cpu_type = cpxcount ? VF610_CPUTYPE_VF600 : VF610_CPUTYPE_VF500;
-
-	return cpxcfg1 ? cpu_type | VF610_CPUTYPE_VFx10 : cpu_type;
-}
-
-static inline int vf610_cpu_type(void)
-{
-	if (!cpu_is_vf610())
-		return 0;
-
-	return __vf610_cpu_type();
-}
-
-static inline int vf610_cpu_revision(void)
-{
-	if (!cpu_is_vf610())
-		return IMX_CHIP_REV_UNKNOWN;
-
-	/*
-	 * There doesn't seem to be a documented way of retreiving
-	 * silicon revision on VFxxx cpus, so we just report Mask ROM
-	 * version instead
-	 */
-	return readl(VF610_ROM_VERSION_OFFSET) & 0xff;
-}
-
-u64 vf610_uid(void);
-
-#endif
diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h
deleted file mode 100644
index 22d9c76d61..0000000000
--- a/arch/arm/mach-imx/include/mach/weim.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __MACH_WEIM_H
-#define __MACH_WEIM_H
-
-#include <linux/types.h>
-
-void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
-		unsigned additional);
-
-void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
-		unsigned additional);
-
-void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
-		unsigned additional);
-
-void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
-
-void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
-
-#endif /* __MACH_WEIM_H */
diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h
deleted file mode 100644
index 7187787f5b..0000000000
--- a/arch/arm/mach-imx/include/mach/xload.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __MACH_XLOAD_H
-#define __MACH_XLOAD_H
-
-int imx53_nand_start_image(void);
-int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len);
-int imx6_spi_start_image(int instance);
-int imx6_esdhc_start_image(int instance);
-int imx6_nand_start_image(void);
-int imx7_esdhc_start_image(int instance);
-int imx8m_esdhc_load_image(int instance, bool start);
-int imx8mp_esdhc_load_image(int instance, bool start);
-
-int imx_image_size(void);
-int piggydata_size(void);
-
-extern unsigned char input_data[];
-extern unsigned char input_data_end[];
-
-#endif /* __MACH_XLOAD_H */
diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c
index 7574fe80b2..bbfcfac457 100644
--- a/arch/arm/mach-imx/nand.c
+++ b/arch/arm/mach-imx/nand.c
@@ -1,23 +1,12 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <common.h>
-#include <mach/generic.h>
-#include <mach/imx21-regs.h>
-#include <mach/imx25-regs.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx-nand.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx21-regs.h>
+#include <mach/imx/imx25-regs.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/imx35-regs.h>
+#include <mach/imx/imx-nand.h>
 #include <io.h>
 
 #define RCSR_NFC_FMS		(1 << 8)
diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c
new file mode 100644
index 0000000000..0f1555abad
--- /dev/null
+++ b/arch/arm/mach-imx/romapi.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#define pr_fmt(fmt) "romapi: " fmt
+
+#include <common.h>
+#include <linux/bitfield.h>
+#include <soc/imx9/flash_header.h>
+#include <asm/sections.h>
+#include <mach/imx/romapi.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/imx8m-regs.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/generic.h>
+#include <asm/barebox-arm.h>
+#include <zero_page.h>
+#include <memory.h>
+#include <init.h>
+#include <pbl.h>
+#include <mmu.h>
+#include <bootsource.h>
+
+#define BOOTROM_INFO_VERSION		0x1
+#define BOOTROM_INFO_BOOT_DEVICE	0x2
+#define BOOTROM_INFO_DEVICE_PAGE_SIZE	0x3
+#define BOOTROM_INFO_OFFSET_IVT		0x4
+#define BOOTROM_INFO_BOOT_STAGE		0x5
+#define BOOTROM_INFO_OFFSET_IMAGE	0x6
+
+#define BOOTROM_BOOT_DEVICE_INTERFACE	GENMASK(23, 16)
+#define BOOTROM_BOOT_DEVICE_INSTANCE	GENMASK(15, 8)
+#define BOOTROM_BOOT_DEVICE_STATE	GENMASK(7, 0)
+
+static int imx_bootrom_query(struct rom_api *rom_api, uint32_t type, uint32_t *__info)
+{
+	static uint32_t info;
+	uint32_t xor = type ^ (uintptr_t)&info;
+	int ret;
+
+	ret = rom_api->query_boot_infor(type, &info, xor);
+	if (ret != ROM_API_OKAY)
+		return -EIO;
+
+	*__info = info;
+
+	return 0;
+}
+
+static int imx_romapi_load_stream(struct rom_api *rom_api, void *adr, size_t size)
+{
+	while (size) {
+		size_t chunksize = min(size, (size_t)1024);
+		int ret;
+
+		ret = rom_api->download_image(adr, 0, chunksize,
+					      (uintptr_t)adr ^ chunksize);
+		if (ret != ROM_API_OKAY) {
+			pr_err("Failed to load piggy data (ret = %x)\n", ret);
+			return -EIO;
+		}
+
+		adr += chunksize;
+		size -= chunksize;
+	}
+	return 0;
+}
+
+static int imx_romapi_load_seekable(struct rom_api *rom_api, void *adr, uint32_t offset,
+				       size_t size)
+{
+	int ret;
+
+	size = PAGE_ALIGN(size);
+
+	ret = rom_api->download_image(adr, offset, size,
+				      (uintptr_t)adr ^ offset ^ size);
+	if (ret != ROM_API_OKAY) {
+		pr_err("Failed to load piggy data (ret = %x)\n", ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* read piggydata via a bootrom callback and place it behind our copy in SDRAM */
+static int imx_romapi_load_image(struct rom_api *rom_api, void *bl33)
+{
+	return imx_romapi_load_stream(rom_api, bl33 + barebox_pbl_size,
+				      __image_end - __piggydata_start);
+}
+
+int imx8mp_romapi_load_image(void *bl33)
+{
+	struct rom_api *rom_api = (void *)0x980;
+
+	OPTIMIZER_HIDE_VAR(rom_api);
+
+	return imx_romapi_load_image(rom_api, bl33);
+}
+
+int imx8mn_romapi_load_image(void *bl33)
+{
+	return imx8mp_romapi_load_image(bl33);
+}
+
+static int imx_romapi_boot_device(struct rom_api *rom_api)
+{
+	uint32_t boot_device_type, boot_instance, boot_device;
+	enum bootsource bootsource = BOOTSOURCE_UNKNOWN;
+	int ret;
+
+	ret = imx_bootrom_query(rom_api, BOOTROM_INFO_BOOT_DEVICE, &boot_device);
+	if (ret)
+		return ret;
+
+	boot_device_type = FIELD_GET(BOOTROM_BOOT_DEVICE_INTERFACE, boot_device);
+	boot_instance = FIELD_GET(BOOTROM_BOOT_DEVICE_INSTANCE, boot_device);
+
+	switch (boot_device_type) {
+	case BT_DEV_TYPE_MMC:
+	case BT_DEV_TYPE_SD:
+		bootsource = BOOTSOURCE_MMC;
+		break;
+	case BT_DEV_TYPE_NAND:
+		bootsource = BOOTSOURCE_NAND;
+		break;
+	case BT_DEV_TYPE_FLEXSPINOR:
+	case BT_DEV_TYPE_SPI_NOR:
+		bootsource = BOOTSOURCE_SPI_NOR;
+		break;
+	case BT_DEV_TYPE_USB:
+		bootsource = BOOTSOURCE_USB;
+		break;
+	}
+
+	bootsource_set(bootsource, boot_instance);
+
+	return 0;
+}
+
+static int imx_romapi_boot_device_seekable(struct rom_api *rom_api)
+{
+	uint32_t boot_device, boot_device_type, boot_device_state;
+	int ret;
+	bool seekable;
+
+	ret = imx_bootrom_query(rom_api, BOOTROM_INFO_BOOT_DEVICE, &boot_device);
+	if (ret)
+		return ret;
+
+	boot_device_type = FIELD_GET(BOOTROM_BOOT_DEVICE_INTERFACE, boot_device);
+
+	switch (boot_device_type) {
+	case BT_DEV_TYPE_SD:
+	case BT_DEV_TYPE_NAND:
+	case BT_DEV_TYPE_FLEXSPINOR:
+	case BT_DEV_TYPE_SPI_NOR:
+		seekable = true;
+		break;
+	case BT_DEV_TYPE_USB:
+		seekable = false;
+		break;
+	case BT_DEV_TYPE_MMC:
+		boot_device_state = FIELD_GET(BOOTROM_BOOT_DEVICE_STATE, boot_device);
+		if (boot_device_state & BIT(0))
+			seekable = false;
+		else
+			seekable = true;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return seekable;
+}
+
+int imx93_romapi_load_image(void)
+{
+	struct rom_api *rom_api = (void *)0x1980;
+	int ret;
+	int seekable;
+	uint32_t offset, image_offset;
+	void *bl33 = (void *)MX93_ATF_BL33_BASE_ADDR;
+	struct flash_header_v3 *fh;
+
+	OPTIMIZER_HIDE_VAR(rom_api);
+
+	seekable = imx_romapi_boot_device_seekable(rom_api);
+	if (seekable < 0)
+		return seekable;
+
+	if (!seekable) {
+		int align_size = ALIGN(barebox_pbl_size, 1024) - barebox_pbl_size;
+		void *pbl_size_aligned = bl33 + ALIGN(barebox_pbl_size, 1024);
+
+		/*
+		 * The USB protocol uploads in chunks of 1024 bytes. This means
+		 * the initial piggy data up to the next 1KiB boundary is already
+		 * transferred. Align up the start address to this boundary.
+		 */
+
+		return imx_romapi_load_stream(rom_api,
+				pbl_size_aligned,
+				__image_end - __piggydata_start - align_size);
+	}
+
+	ret = imx_bootrom_query(rom_api, BOOTROM_INFO_OFFSET_IMAGE, &offset);
+	if (ret)
+		return ret;
+
+	pr_debug("%s: IVT offset on boot device: 0x%08x\n", __func__, offset);
+
+	ret = imx_romapi_load_seekable(rom_api, bl33, offset, 4096);
+	if (ret)
+		return ret;
+
+	fh = bl33;
+
+	if (fh->tag != 0x87) {
+		pr_err("Invalid IVT header: 0x%02x, expected 0x87\n", fh->tag);
+		return -EINVAL;
+	}
+
+	image_offset = fh->img[0].offset;
+
+	pr_debug("%s: offset in image: 0x%08x\n", __func__, image_offset);
+
+	/*
+	 * We assume the first image in the first container is the barebox image,
+	 * which is what the imx9image call in images/Makefile.imx generates.
+	 */
+	ret = imx_romapi_load_seekable(rom_api, bl33, offset + image_offset, barebox_image_size);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+const u32 *imx8m_get_bootrom_log(void)
+{
+	if (current_el() == 3) {
+		ulong *rom_log_addr_offset = (void *)0x9e0;
+		ulong rom_log_addr;
+
+		OPTIMIZER_HIDE_VAR(rom_log_addr_offset);
+
+		zero_page_access();
+		rom_log_addr = *rom_log_addr_offset;
+		zero_page_faulting();
+
+		if (rom_log_addr < MX8M_OCRAM_BASE_ADDR ||
+		    rom_log_addr >= MX8M_OCRAM_BASE_ADDR + MX8M_OCRAM_MAX_SIZE ||
+		    rom_log_addr & 0x3) {
+			pr_warn("No BootROM log found at address 0x%08lx\n", rom_log_addr);
+			return NULL;
+		}
+
+		return (u32 *)rom_log_addr;
+	}
+
+	if (!IN_PBL)
+		return imx8m_scratch_get_bootrom_log();
+
+	return NULL;
+}
+
+void imx8m_save_bootrom_log(void)
+{
+	const u32 *rom_log;
+
+	if (!IS_ENABLED(CONFIG_IMX_SAVE_BOOTROM_LOG)) {
+		pr_debug("skipping bootrom log saving\n");
+		return;
+	}
+
+	rom_log = imx8m_get_bootrom_log();
+	if (!rom_log) {
+		pr_warn("bootrom log not found\n");
+		return;
+	}
+
+	imx8m_scratch_save_bootrom_log(rom_log);
+}
+
+#define IMX93_BOOT_ROM_BASE 0x1000
+#define IMX93_BOOT_ROM_END (0x40000 - 1)
+
+void imx93_bootsource(void)
+{
+	struct rom_api *rom_api = (void *)0x1980;
+	struct resource rom = {
+		.start = IMX93_BOOT_ROM_BASE,
+		.end = IMX93_BOOT_ROM_END,
+	};
+	struct resource *r;
+	int ret;
+
+	r = request_iomem_region("Boot ROM",  rom.start, rom.end);
+	if (IS_ERR(r)) {
+		ret = PTR_ERR(r);
+		goto out;
+	}
+
+	arch_remap_range((void *)rom.start, rom.start, resource_size(&rom), MAP_CACHED);
+
+	OPTIMIZER_HIDE_VAR(rom_api);
+
+	ret = imx_romapi_boot_device(rom_api);
+out:
+	if (ret)
+		pr_err("Failed to get bootsource: %pe\n", ERR_PTR(ret));
+}
diff --git a/arch/arm/mach-imx/scratch.c b/arch/arm/mach-imx/scratch.c
new file mode 100644
index 0000000000..60d15a4f1a
--- /dev/null
+++ b/arch/arm/mach-imx/scratch.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <asm/barebox-arm.h>
+#include <init.h>
+#include <linux/err.h>
+#include <linux/printk.h>
+#include <mach/imx/imx8m-regs.h>
+#include <mach/imx/imx9-regs.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/scratch.h>
+#include <memory.h>
+#include <tee/optee.h>
+#include <pbl.h>
+
+struct imx_scratch_space {
+	u32 bootrom_log[128];
+	u32 reserved[128];		/* reserve for bootrom log */
+	struct optee_header optee_hdr;
+};
+
+static struct imx_scratch_space *scratch;
+
+void imx8m_init_scratch_space(int ddr_buswidth, bool zero_init)
+{
+	ulong endmem = MX8M_DDR_CSD1_BASE_ADDR +
+		imx8m_barebox_earlymem_size(ddr_buswidth);
+
+	scratch = (void *)arm_mem_scratch(endmem);
+
+	if (zero_init)
+		memset(scratch, 0, sizeof(*scratch));
+}
+
+void imx93_init_scratch_space(bool zero_init)
+{
+	ulong endmem = MX9_DDR_CSD1_BASE_ADDR + imx9_ddrc_sdram_size();
+
+	scratch = (void *)arm_mem_scratch(endmem);
+
+	if (zero_init)
+		memset(scratch, 0, sizeof(*scratch));
+}
+
+void imx8m_scratch_save_bootrom_log(const u32 *rom_log)
+{
+	size_t sz = sizeof(scratch->bootrom_log);
+
+	if (!scratch) {
+		pr_err("No scratch area initialized, skip saving bootrom log");
+		return;
+	}
+
+	pr_debug("Saving bootrom log to scratch area 0x%p\n", &scratch->bootrom_log);
+
+	memcpy(scratch->bootrom_log, rom_log, sz);
+}
+
+const u32 *imx8m_scratch_get_bootrom_log(void)
+{
+	if (!scratch) {
+		if (IN_PBL)
+			return ERR_PTR(-EINVAL);
+		else
+			scratch = (void *)arm_mem_scratch_get();
+	}
+
+	return scratch->bootrom_log;
+}
+
+void imx_scratch_save_optee_hdr(const struct optee_header *hdr)
+{
+	size_t sz = sizeof(*hdr);
+
+	if (!scratch) {
+		pr_err("No scratch area initialized, skip saving optee-hdr");
+		return;
+	}
+
+	pr_debug("Saving optee-hdr to scratch area 0x%p\n", &scratch->optee_hdr);
+
+	memcpy(&scratch->optee_hdr, hdr, sz);
+}
+
+const struct optee_header *imx_scratch_get_optee_hdr(void)
+{
+	if (!scratch) {
+		if (IN_PBL)
+			return ERR_PTR(-EINVAL);
+		else
+			scratch = (void *)arm_mem_scratch_get();
+	}
+
+	return &scratch->optee_hdr;
+}
+
+static int imx8m_reserve_scratch_area(void)
+{
+	return PTR_ERR_OR_ZERO(request_sdram_region("scratch area",
+				    (ulong)arm_mem_scratch_get(),
+				    sizeof(struct imx_scratch_space)));
+}
+device_initcall(imx8m_reserve_scratch_area);
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 73350d15e1..ec8d1bf6f6 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -1,11 +1,5 @@
-/*
- * Copyright 2016 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2016 Sascha Hauer <s.hauer@pengutronix.de>
 
 #include <common.h>
 #include <init.h>
@@ -16,7 +10,7 @@
 
 #define SCR_WARM_RESET_ENABLE	BIT(0)
 
-static int imx_src_reset_probe(struct device_d *dev)
+static int imx_src_reset_probe(struct device *dev)
 {
 	struct resource *res;
 	u32 val;
@@ -43,15 +37,11 @@ static const struct of_device_id imx_src_dt_ids[] = {
 	{ .compatible = "fsl,imx51-src", },
 	{ /* sentinel */ },
 };
+MODULE_DEVICE_TABLE(of, imx_src_dt_ids);
 
-static struct driver_d imx_src_reset_driver = {
+static struct driver imx_src_reset_driver = {
 	.name = "imx-src",
 	.probe	= imx_src_reset_probe,
 	.of_compatible	= DRV_OF_COMPAT(imx_src_dt_ids),
 };
-
-static int imx_src_reset_init(void)
-{
-	return platform_driver_register(&imx_src_reset_driver);
-}
-postcore_initcall(imx_src_reset_init);
+postcore_platform_driver(imx_src_reset_driver);
diff --git a/arch/arm/mach-imx/tzasc.c b/arch/arm/mach-imx/tzasc.c
new file mode 100644
index 0000000000..4cb4d7c5cf
--- /dev/null
+++ b/arch/arm/mach-imx/tzasc.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <mach/imx/generic.h>
+#include <mach/imx/tzasc.h>
+#include <linux/bitops.h>
+#include <mach/imx/imx8m-regs.h>
+#include <io.h>
+
+#define GPR_TZASC_EN					BIT(0)
+#define GPR_TZASC_ID_SWAP_BYPASS		BIT(1)
+#define GPR_TZASC_EN_LOCK				BIT(16)
+#define GPR_TZASC_ID_SWAP_BYPASS_LOCK	BIT(17)
+
+#define MX8M_TZASC_REGION_ATTRIBUTES_0		(MX8M_TZASC_BASE_ADDR + 0x108)
+#define MX8M_TZASC_REGION_ATTRIBUTES_0_SP	GENMASK(31, 28)
+
+void imx8m_tzc380_init(void)
+{
+	u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR);
+
+	/* Enable TZASC and lock setting */
+	setbits_le32(&gpr[10], GPR_TZASC_EN);
+	setbits_le32(&gpr[10], GPR_TZASC_EN_LOCK);
+
+	/*
+	 * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
+	 * order to avoid AXI Bus errors when GPU is in use
+	 */
+	if (cpu_is_mx8mm() || cpu_is_mx8mn() || cpu_is_mx8mp())
+		setbits_le32(&gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
+
+	/*
+	 * imx8mn and imx8mp implements the lock bit for
+	 * TZASC_ID_SWAP_BYPASS, enable it to lock settings
+	 */
+	if (cpu_is_mx8mn() || cpu_is_mx8mp())
+		setbits_le32(&gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
+
+	/*
+	 * set Region 0 attribute to allow secure and non-secure
+	 * read/write permission. Found some masters like usb dwc3
+	 * controllers can't work with secure memory.
+	 */
+	writel(MX8M_TZASC_REGION_ATTRIBUTES_0_SP,
+		   MX8M_TZASC_REGION_ATTRIBUTES_0);
+}
+
+bool imx8m_tzc380_is_enabled(void)
+{
+	u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR);
+
+	return (readl(&gpr[10]) & (GPR_TZASC_EN | GPR_TZASC_EN_LOCK))
+		== (GPR_TZASC_EN | GPR_TZASC_EN_LOCK);
+}
diff --git a/arch/arm/mach-imx/vf610.c b/arch/arm/mach-imx/vf610.c
index 2fbd6393ea..74d190d7bc 100644
--- a/arch/arm/mach-imx/vf610.c
+++ b/arch/arm/mach-imx/vf610.c
@@ -1,25 +1,14 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 #include <init.h>
 #include <common.h>
 #include <io.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
-#include <mach/revision.h>
-#include <mach/vf610.h>
-#include <mach/reset-reason.h>
-#include <mach/ocotp.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/revision.h>
+#include <mach/imx/vf610.h>
+#include <mach/imx/reset-reason.h>
+#include <mach/imx/ocotp.h>
 
 static const struct imx_reset_reason vf610_reset_reasons[] = {
 	{ VF610_SRC_SRSR_POR_RST,       RESET_POR,   0 },
diff --git a/arch/arm/mach-imx/xload-common.c b/arch/arm/mach-imx/xload-common.c
index bd6405258e..025d87fffc 100644
--- a/arch/arm/mach-imx/xload-common.c
+++ b/arch/arm/mach-imx/xload-common.c
@@ -1,7 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
+#include <asm/cache.h>
 #include <asm/sections.h>
 #include <linux/sizes.h>
-#include <mach/xload.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/imx8m-regs.h>
+#include <mach/imx/imx-header.h>
+#include <asm/barebox-arm.h>
 
 int imx_image_size(void)
 {
@@ -14,3 +21,150 @@ int piggydata_size(void)
 	return input_data_end - input_data;
 }
 
+#define HDR_SIZE	512
+
+static int
+imx_search_header(struct imx_flash_header_v2 **header_pointer,
+		  void *buffer, u32 *offset, u32 ivt_offset,
+		  int (*read)(void *dest, size_t len, void *priv),
+		  void *priv)
+{
+	int ret;
+	int i, header_count = 1;
+	void *buf = buffer;
+	struct imx_flash_header_v2 *hdr;
+
+	for (i = 0; i < header_count; i++) {
+		ret = read(buf, *offset + ivt_offset + HDR_SIZE, priv);
+		if (ret)
+			return ret;
+
+		hdr = buf + *offset + ivt_offset;
+
+		if (!is_imx_flash_header_v2(hdr)) {
+			pr_debug("No IVT header! "
+				 "Found tag: 0x%02x length: 0x%04x "
+				 "version: %02x\n",
+				 hdr->header.tag, hdr->header.length,
+				 hdr->header.version);
+			return -EINVAL;
+		}
+
+		if (IS_ENABLED(CONFIG_ARCH_IMX8MQ) &&
+		    hdr->boot_data.plugin & PLUGIN_HDMI_IMAGE) {
+			/*
+			 * In images that include signed HDMI
+			 * firmware, first v2 header would be
+			 * dedicated to that and would not contain any
+			 * useful for us information. In order for us
+			 * to pull the rest of the bootloader image
+			 * in, we need to re-read header from SD/MMC,
+			 * this time skipping anything HDMI firmware
+			 * related.
+			 */
+			*offset += hdr->boot_data.size + hdr->header.length;
+			header_count++;
+		}
+	}
+	*header_pointer = hdr;
+	return 0;
+}
+
+/**
+ * imx_load_image - Load i.MX barebox image from boot medium
+ * @address: Start address of SDRAM where barebox can be loaded into
+ * @entry: Address where barebox entry point should be placed.
+ *         This is ignored unless @start == false
+ * @offset: Start offset for i.MX header search
+ * @ivt_offset: offset between i.MX header and IVT
+ * @start: whether image should be started after loading
+ * @alignment: If nonzero, image size hardcoded in PBL will be aligned up
+ *             to this value
+ * @read: function pointer for reading from the beginning of the boot
+ *        medium onwards
+ * @priv: private data pointer passed to read function
+ *
+ * Return: A negative error code on failure.
+ * On success, if @start == true, the function will not return.
+ * If @start == false, the function will return 0 after placing the
+ * barebox entry point (without header) at @entry.
+ */
+int imx_load_image(ptrdiff_t address, ptrdiff_t entry, u32 offset,
+		   u32 ivt_offset, bool start, unsigned int alignment,
+		   int (*read)(void *dest, size_t len, void *priv),
+		   void *priv)
+{
+
+	void *buf = (void *)address;
+	struct imx_flash_header_v2 *hdr = NULL;
+	int ret, len;
+	void __noreturn (*bb)(void);
+	unsigned int ofs;
+
+	len = imx_image_size();
+	if (alignment)
+		len = ALIGN(len, alignment);
+
+	ret = imx_search_header(&hdr, buf, &offset, ivt_offset, read, priv);
+	if (ret)
+		return ret;
+
+	pr_debug("Check ok, loading image\n");
+
+	ofs = offset + hdr->entry - hdr->boot_data.start;
+
+	if (!start) {
+		/*
+		 * When !start, the caller will start the image later on,
+		 * expecting that it is placed such that its entry
+		 * point would be exactly at 'entry', that is:
+		 *
+		 *     buf + ofs = entry
+		 *
+		 * solving the above for 'buf' gives us the
+		 * adjustment that needs to be made:
+		 *
+		 *     buf = entry - ofs
+		 *
+		 */
+		if (WARN_ON(entry - ofs < address)) {
+			/*
+			 * We want to make sure we won't try to place
+			 * the start of the image before the beginning
+			 * of the memory buffer we were given in
+			 * address.
+			 */
+			return -EINVAL;
+		}
+
+		buf = (void *)(entry - ofs);
+	}
+
+	/*
+	 * For SD/MMC High-Capacity support (> 2G), the offset for the block
+	 * read command is in blocks, not bytes. We don't have the information
+	 * whether we have a SDHC card or not, when we run here though, because
+	 * card setup was done by BootROM. To workaround this, we just read
+	 * from offset 0 as 0 blocks == 0 bytes.
+	 *
+	 * A result of this is that we will have to read the i.MX header and
+	 * padding in front of the binary first to arrive at the barebox entry
+	 * point.
+	 */
+	ret = read(buf, ofs + len, priv);
+	if (ret) {
+		pr_err("Loading image failed with %d\n", ret);
+		return ret;
+	}
+
+	pr_debug("Image loaded successfully\n");
+
+	if (!start)
+		return 0;
+
+	bb = buf + ofs;
+
+	sync_caches_for_execution();
+
+	bb();
+}
diff --git a/arch/arm/mach-imx/xload-gpmi-nand.c b/arch/arm/mach-imx/xload-gpmi-nand.c
index b3fd479cb4..8221e1ace0 100644
--- a/arch/arm/mach-imx/xload-gpmi-nand.c
+++ b/arch/arm/mach-imx/xload-gpmi-nand.c
@@ -1,13 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 #define pr_fmt(fmt) "xload-gpmi-nand: " fmt
 
@@ -16,47 +7,16 @@
 #include <asm-generic/io.h>
 #include <linux/sizes.h>
 #include <linux/mtd/nand.h>
+#include <linux/bitfield.h>
 #include <asm/cache.h>
-#include <mach/xload.h>
+#include <mach/imx/xload.h>
 #include <soc/imx/imx-nand-bcb.h>
 #include <linux/mtd/rawnand.h>
-#include <mach/imx6-regs.h>
-#include <mach/clock-imx6.h>
-
-/*
- * MXS DMA hardware command.
- *
- * This structure describes the in-memory layout of an entire DMA command,
- * including space for the maximum number of PIO accesses. See the appropriate
- * reference manual for a detailed description of what these fields mean to the
- * DMA hardware.
- */
-#define	DMACMD_COMMAND_DMA_WRITE	0x1
-#define	DMACMD_COMMAND_DMA_READ		0x2
-#define	DMACMD_COMMAND_DMA_SENSE	0x3
-#define	DMACMD_CHAIN			(1 << 2)
-#define	DMACMD_IRQ			(1 << 3)
-#define	DMACMD_NAND_LOCK		(1 << 4)
-#define	DMACMD_NAND_WAIT_4_READY	(1 << 5)
-#define	DMACMD_DEC_SEM			(1 << 6)
-#define	DMACMD_WAIT4END			(1 << 7)
-#define	DMACMD_HALT_ON_TERMINATE	(1 << 8)
-#define	DMACMD_TERMINATE_FLUSH		(1 << 9)
-#define	DMACMD_PIO_WORDS(words)		((words) << 12)
-#define	DMACMD_XFER_COUNT(x)		((x) << 16)
-
-struct mxs_dma_cmd {
-	unsigned long		next;
-	unsigned long		data;
-	unsigned long		address;
-#define	APBH_DMA_PIO_WORDS	6
-	unsigned long		pio_words[APBH_DMA_PIO_WORDS];
-};
-
-enum mxs_dma_id {
-	IMX23_DMA,
-	IMX28_DMA,
-};
+#include <soc/imx/gpmi-nand.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/imx7-regs.h>
+#include <mach/imx/clock-imx6.h>
+#include <dma/apbh-dma.h>
 
 struct apbh_dma {
 	void __iomem *regs;
@@ -69,25 +29,6 @@ struct mxs_dma_chan {
 	struct apbh_dma *apbh;
 };
 
-#define	HW_APBHX_CTRL0				0x000
-#define	BM_APBH_CTRL0_APB_BURST8_EN		(1 << 29)
-#define	BM_APBH_CTRL0_APB_BURST_EN		(1 << 28)
-#define	BP_APBH_CTRL0_CLKGATE_CHANNEL		8
-#define	BP_APBH_CTRL0_RESET_CHANNEL		16
-#define	HW_APBHX_CTRL1				0x010
-#define	BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN	16
-#define	HW_APBHX_CTRL2				0x020
-#define	HW_APBHX_CHANNEL_CTRL			0x030
-#define	BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL	16
-#define	BP_APBHX_VERSION_MAJOR			24
-#define	HW_APBHX_CHn_NXTCMDAR_MX23(n)		(0x050 + (n) * 0x70)
-#define	HW_APBHX_CHn_NXTCMDAR_MX28(n)		(0x110 + (n) * 0x70)
-#define	HW_APBHX_CHn_SEMA_MX23(n)		(0x080 + (n) * 0x70)
-#define	HW_APBHX_CHn_SEMA_MX28(n)		(0x140 + (n) * 0x70)
-#define	NAND_ONFI_CRC_BASE			0x4f4e
-
-#define apbh_dma_is_imx23(aphb) ((apbh)->id == IMX23_DMA)
-
 /* udelay() is not available in PBL, need to improvise */
 static void __udelay(int us)
 {
@@ -111,14 +52,15 @@ static int mxs_dma_enable(struct mxs_dma_chan *pchan,
 	struct apbh_dma *apbh = pchan->apbh;
 	int channel_bit;
 	int channel = pchan->channel;
+	unsigned long pdesc32 = (unsigned long)pdesc;
 
 	if (apbh_dma_is_imx23(apbh)) {
-		writel((uint32_t)pdesc,
+		writel(pdesc32,
 			apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX23(channel));
 		writel(1, apbh->regs + HW_APBHX_CHn_SEMA_MX23(channel));
 		channel_bit = channel + BP_APBH_CTRL0_CLKGATE_CHANNEL;
 	} else {
-		writel((uint32_t)pdesc,
+		writel(pdesc32,
 			apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX28(channel));
 		writel(1, apbh->regs + HW_APBHX_CHn_SEMA_MX28(channel));
 		channel_bit = channel;
@@ -174,8 +116,8 @@ static int mxs_dma_run(struct mxs_dma_chan *pchan, struct mxs_dma_cmd *pdesc,
 
 	/* chain descriptors */
 	for (i = 0; i < num - 1; i++) {
-		pdesc[i].next = (uint32_t)(&pdesc[i + 1]);
-		pdesc[i].data |= DMACMD_CHAIN;
+		pdesc[i].next = (unsigned long)(&pdesc[i + 1]);
+		pdesc[i].data |= MXS_DMA_DESC_CHAIN;
 	}
 
 	writel(1 << (pchan->channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
@@ -211,39 +153,6 @@ static int mxs_dma_run(struct mxs_dma_chan *pchan, struct mxs_dma_cmd *pdesc,
 
 /* ----------------------------- NAND driver part -------------------------- */
 
-#define	GPMI_CTRL0					0x00000000
-#define	GPMI_CTRL0_RUN					(1 << 29)
-#define	GPMI_CTRL0_DEV_IRQ_EN				(1 << 28)
-#define	GPMI_CTRL0_UDMA					(1 << 26)
-#define	GPMI_CTRL0_COMMAND_MODE_MASK			(0x3 << 24)
-#define	GPMI_CTRL0_COMMAND_MODE_OFFSET			24
-#define	GPMI_CTRL0_COMMAND_MODE_WRITE			(0x0 << 24)
-#define	GPMI_CTRL0_COMMAND_MODE_READ			(0x1 << 24)
-#define	GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE	(0x2 << 24)
-#define	GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY		(0x3 << 24)
-#define	GPMI_CTRL0_WORD_LENGTH				(1 << 23)
-#define	GPMI_CTRL0_CS(cs)				((cs) << 20)
-#define	GPMI_CTRL0_ADDRESS_MASK				(0x7 << 17)
-#define	GPMI_CTRL0_ADDRESS_OFFSET			17
-#define	GPMI_CTRL0_ADDRESS_NAND_DATA			(0x0 << 17)
-#define	GPMI_CTRL0_ADDRESS_NAND_CLE			(0x1 << 17)
-#define	GPMI_CTRL0_ADDRESS_NAND_ALE			(0x2 << 17)
-#define	GPMI_CTRL0_ADDRESS_INCREMENT			(1 << 16)
-#define	GPMI_CTRL0_XFER_COUNT_MASK			0xffff
-#define	GPMI_CTRL0_XFER_COUNT_OFFSET			0
-
-#define	GPMI_ECCCTRL_ECC_CMD_DECODE			(0x0 << 13)
-#define	GPMI_ECCCTRL_ENABLE_ECC				(1 << 12)
-#define	GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE		0x1ff
-
-#define	BCH_CTRL					0x00000000
-#define	BCH_CTRL_COMPLETE_IRQ				(1 << 0)
-
-#define	MXS_NAND_DMA_DESCRIPTOR_COUNT			6
-#define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE			512
-#define	MXS_NAND_METADATA_SIZE				10
-#define	MXS_NAND_COMMAND_BUFFER_SIZE			128
-
 struct mxs_nand_info {
 	void __iomem *io_base;
 	void __iomem *bch_base;
@@ -321,7 +230,7 @@ static uint32_t mxs_nand_aux_status_offset(void)
 }
 
 static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
-		int oobsize, int pagenum, void *databuf, int raw)
+		int oobsize, int pagenum, void *databuf, int raw, bool randomizer)
 {
 	void __iomem *bch_regs = info->bch_base;
 	unsigned column = 0;
@@ -329,8 +238,6 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
 	int cmd_queue_len;
 	u8 *cmd_buf;
 	int ret;
-	uint8_t	*status;
-	int i;
 	int timeout;
 	int descnum = 0;
 	int max_pagenum = info->nand_size /
@@ -353,14 +260,14 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
 	if ((max_pagenum - 1) >= SZ_64K)
 		cmd_buf[cmd_queue_len++] = pagenum >> 16;
 
-	d->data = DMACMD_COMMAND_DMA_READ |
-		DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(cmd_queue_len);
+	d->data = MXS_DMA_DESC_COMMAND_DMA_READ |
+		MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(1) |
+		MXS_DMA_DESC_XFER_COUNT(cmd_queue_len);
 
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_CLE |
 		GPMI_CTRL0_ADDRESS_INCREMENT |
 		cmd_queue_len;
@@ -373,50 +280,50 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
 
 	cmd_buf[cmd_queue_len++] = NAND_CMD_READSTART;
 
-	d->data = DMACMD_COMMAND_DMA_READ |
-		DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(cmd_queue_len);
+	d->data = MXS_DMA_DESC_COMMAND_DMA_READ |
+		MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(1) |
+		MXS_DMA_DESC_XFER_COUNT(cmd_queue_len);
 
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_CLE |
 		GPMI_CTRL0_ADDRESS_INCREMENT |
 		cmd_queue_len;
 
 	/* Compile DMA descriptor - wait for ready. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_CHAIN |
-		DMACMD_NAND_WAIT_4_READY |
-		DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(2);
+	d->data = MXS_DMA_DESC_CHAIN |
+		MXS_DMA_DESC_NAND_WAIT_4_READY |
+		MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(2);
 
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_DATA;
 
 	if (raw) {
 		/* Compile DMA descriptor - read. */
 		d = &info->desc[descnum++];
-		d->data = DMACMD_WAIT4END |
-			DMACMD_PIO_WORDS(1) |
-			DMACMD_XFER_COUNT(writesize + oobsize) |
-			DMACMD_COMMAND_DMA_WRITE;
+		d->data = MXS_DMA_DESC_WAIT4END |
+			MXS_DMA_DESC_PIO_WORDS(1) |
+			MXS_DMA_DESC_XFER_COUNT(writesize + oobsize) |
+			MXS_DMA_DESC_COMMAND_DMA_WRITE;
 		d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
 			GPMI_CTRL0_WORD_LENGTH |
-			GPMI_CTRL0_CS(info->cs) |
+			FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 			GPMI_CTRL0_ADDRESS_NAND_DATA |
 			(writesize + oobsize);
 		d->address = (dma_addr_t)databuf;
 	} else {
 		/* Compile DMA descriptor - enable the BCH block and read. */
 		d = &info->desc[descnum++];
-		d->data = DMACMD_WAIT4END | DMACMD_PIO_WORDS(6);
+		d->data = MXS_DMA_DESC_WAIT4END | MXS_DMA_DESC_PIO_WORDS(6);
 		d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
 			GPMI_CTRL0_WORD_LENGTH |
-			GPMI_CTRL0_CS(info->cs) |
+			FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 			GPMI_CTRL0_ADDRESS_NAND_DATA |
 			(writesize + oobsize);
 		d->pio_words[1] = 0;
@@ -427,21 +334,27 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
 		d->pio_words[4] = (dma_addr_t)databuf;
 		d->pio_words[5] = (dma_addr_t)(databuf + writesize);
 
+		if (randomizer) {
+			d->pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE |
+					   GPMI_ECCCTRL_RANDOMIZER_TYPE2;
+			d->pio_words[3] |= (pagenum % 256) << 16;
+		}
+
 		/* Compile DMA descriptor - disable the BCH block. */
 		d = &info->desc[descnum++];
-		d->data = DMACMD_NAND_WAIT_4_READY |
-			DMACMD_WAIT4END |
-			DMACMD_PIO_WORDS(3);
+		d->data = MXS_DMA_DESC_NAND_WAIT_4_READY |
+			MXS_DMA_DESC_WAIT4END |
+			MXS_DMA_DESC_PIO_WORDS(3);
 		d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
 			GPMI_CTRL0_WORD_LENGTH |
-			GPMI_CTRL0_CS(info->cs) |
+			FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 			GPMI_CTRL0_ADDRESS_NAND_DATA |
 			(writesize + oobsize);
 	}
 
 	/* Compile DMA descriptor - de-assert the NAND lock and interrupt. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_IRQ | DMACMD_DEC_SEM;
+	d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 
 	/* Execute the DMA chain. */
 	ret = mxs_dma_run(info->dma_channel, info->desc, descnum);
@@ -468,20 +381,26 @@ static int mxs_nand_read_page(struct mxs_nand_info *info, int writesize,
 	writel(BCH_CTRL_COMPLETE_IRQ,
 		bch_regs + BCH_CTRL + STMP_OFFSET_REG_CLR);
 
-	/* Loop over status bytes, accumulating ECC status. */
-	status = databuf + writesize + mxs_nand_aux_status_offset();
-	for (i = 0; i < writesize / MXS_NAND_CHUNK_DATA_CHUNK_SIZE; i++) {
-		if (status[i] == 0xfe) {
-			ret = -EBADMSG;
-			goto err;
-		}
-	}
-
 	ret = 0;
 err:
 	return ret;
 }
 
+static int mxs_nand_get_ecc_status(struct mxs_nand_info *info, void *databuf)
+{
+	uint8_t	*status;
+	int i;
+
+	/* Loop over status bytes, accumulating ECC status. */
+	status = databuf + info->organization.pagesize + mxs_nand_aux_status_offset();
+	for (i = 0; i < info->organization.pagesize / MXS_NAND_CHUNK_DATA_CHUNK_SIZE; i++) {
+		if (status[i] == 0xfe)
+			return -EBADMSG;
+	}
+
+	return 0;
+}
+
 static int mxs_nand_get_read_status(struct mxs_nand_info *info, void *databuf)
 {
 	int ret;
@@ -500,34 +419,34 @@ static int mxs_nand_get_read_status(struct mxs_nand_info *info, void *databuf)
 	d->address = (dma_addr_t)(cmd_buf);
 	cmd_buf[cmd_queue_len++] = NAND_CMD_STATUS;
 
-	d->data = DMACMD_COMMAND_DMA_READ |
-		DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(cmd_queue_len);
+	d->data = MXS_DMA_DESC_COMMAND_DMA_READ |
+		MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(1) |
+		MXS_DMA_DESC_XFER_COUNT(cmd_queue_len);
 
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_CLE |
 		GPMI_CTRL0_ADDRESS_INCREMENT |
 		cmd_queue_len;
 
 	/* Compile DMA descriptor - read. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(1) |
-		DMACMD_COMMAND_DMA_WRITE;
+	d->data = MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(1) |
+		MXS_DMA_DESC_XFER_COUNT(1) |
+		MXS_DMA_DESC_COMMAND_DMA_WRITE;
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_DATA |
 		(1);
 	d->address = (dma_addr_t)databuf;
 
 	/* Compile DMA descriptor - de-assert the NAND lock and interrupt. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_IRQ | DMACMD_DEC_SEM;
+	d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 
 	/* Execute the DMA chain. */
 	ret = mxs_dma_run(info->dma_channel, info->desc, descnum);
@@ -558,21 +477,21 @@ static int mxs_nand_reset(struct mxs_nand_info *info, void *databuf)
 	d->address = (dma_addr_t)(cmd_buf);
 	cmd_buf[cmd_queue_len++] = NAND_CMD_RESET;
 
-	d->data = DMACMD_COMMAND_DMA_READ |
-		DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(cmd_queue_len);
+	d->data = MXS_DMA_DESC_COMMAND_DMA_READ |
+		MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(1) |
+		MXS_DMA_DESC_XFER_COUNT(cmd_queue_len);
 
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_CLE |
 		GPMI_CTRL0_ADDRESS_INCREMENT |
 		cmd_queue_len;
 
 	/* Compile DMA descriptor - de-assert the NAND lock and interrupt. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_IRQ | DMACMD_DEC_SEM;
+	d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 
 	/* Execute the DMA chain. */
 	ret = mxs_dma_run(info->dma_channel, info->desc, descnum);
@@ -630,46 +549,46 @@ static int mxs_nand_get_onfi(struct mxs_nand_info *info, void *databuf)
 	cmd_buf[cmd_queue_len++] = NAND_CMD_PARAM;
 	cmd_buf[cmd_queue_len++] = 0x00;
 
-	d->data = DMACMD_COMMAND_DMA_READ |
-		DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(cmd_queue_len);
+	d->data = MXS_DMA_DESC_COMMAND_DMA_READ |
+		MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(1) |
+		MXS_DMA_DESC_XFER_COUNT(cmd_queue_len);
 
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_CLE |
 		GPMI_CTRL0_ADDRESS_INCREMENT |
 		cmd_queue_len;
 
 	/* Compile DMA descriptor - wait for ready. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_CHAIN |
-		DMACMD_NAND_WAIT_4_READY |
-		DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(2);
+	d->data = MXS_DMA_DESC_CHAIN |
+		MXS_DMA_DESC_NAND_WAIT_4_READY |
+		MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(2);
 
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_DATA;
 
 	/* Compile DMA descriptor - read. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(sizeof(struct nand_onfi_params)) |
-		DMACMD_COMMAND_DMA_WRITE;
+	d->data = MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(1) |
+		MXS_DMA_DESC_XFER_COUNT(sizeof(struct nand_onfi_params)) |
+		MXS_DMA_DESC_COMMAND_DMA_WRITE;
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_DATA |
 		(sizeof(struct nand_onfi_params));
 	d->address = (dma_addr_t)databuf;
 
 	/* Compile DMA descriptor - de-assert the NAND lock and interrupt. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_IRQ | DMACMD_DEC_SEM;
+	d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 
 	/* Execute the DMA chain. */
 	ret = mxs_dma_run(info->dma_channel, info->desc, descnum);
@@ -708,7 +627,7 @@ static int mxs_nand_get_onfi(struct mxs_nand_info *info, void *databuf)
 	return ret;
 }
 
-static int mxs_nand_check_onfi(struct mxs_nand_info *info, void *databuf)
+static int mxs_nand_read_id(struct mxs_nand_info *info, u8 adr, void *databuf, size_t len)
 {
 	int ret;
 	u8 *cmd_buf;
@@ -716,13 +635,6 @@ static int mxs_nand_check_onfi(struct mxs_nand_info *info, void *databuf)
 	int descnum = 0;
 	int cmd_queue_len;
 
-	struct onfi_header {
-		u8 byte0;
-		u8 byte1;
-		u8 byte2;
-		u8 byte3;
-	} onfi_head;
-
 	memset(info->desc, 0,
 		sizeof(*info->desc) * MXS_NAND_DMA_DESCRIPTOR_COUNT);
 
@@ -732,152 +644,118 @@ static int mxs_nand_check_onfi(struct mxs_nand_info *info, void *databuf)
 	d = &info->desc[descnum++];
 	d->address = (dma_addr_t)(cmd_buf);
 	cmd_buf[cmd_queue_len++] = NAND_CMD_READID;
-	cmd_buf[cmd_queue_len++] = 0x20;
+	cmd_buf[cmd_queue_len++] = adr;
 
-	d->data = DMACMD_COMMAND_DMA_READ |
-		DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(cmd_queue_len);
+	d->data = MXS_DMA_DESC_COMMAND_DMA_READ |
+		MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(1) |
+		MXS_DMA_DESC_XFER_COUNT(cmd_queue_len);
 
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_CLE |
 		GPMI_CTRL0_ADDRESS_INCREMENT |
 		cmd_queue_len;
 
 	/* Compile DMA descriptor - read. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(sizeof(struct onfi_header)) |
-		DMACMD_COMMAND_DMA_WRITE;
+	d->data = MXS_DMA_DESC_WAIT4END |
+		MXS_DMA_DESC_PIO_WORDS(1) |
+		MXS_DMA_DESC_XFER_COUNT(len) |
+		MXS_DMA_DESC_COMMAND_DMA_WRITE;
 	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
 		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
+		FIELD_PREP(GPMI_CTRL0_CS, info->cs) |
 		GPMI_CTRL0_ADDRESS_NAND_DATA |
-		(sizeof(struct onfi_header));
+		len;
 	d->address = (dma_addr_t)databuf;
 
 	/* Compile DMA descriptor - de-assert the NAND lock and interrupt. */
 	d = &info->desc[descnum++];
-	d->data = DMACMD_IRQ | DMACMD_DEC_SEM;
+	d->data = MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 
 	/* Execute the DMA chain. */
 	ret = mxs_dma_run(info->dma_channel, info->desc, descnum);
-	if (ret) {
+	if (ret)
 		pr_err("DMA read error\n");
-		return ret;
-	}
-
-	memcpy(&onfi_head, databuf, sizeof(struct onfi_header));
 
-	pr_debug("ONFI Byte0: 0x%x\n", onfi_head.byte0);
-	pr_debug("ONFI Byte1: 0x%x\n", onfi_head.byte1);
-	pr_debug("ONFI Byte2: 0x%x\n", onfi_head.byte2);
-	pr_debug("ONFI Byte3: 0x%x\n", onfi_head.byte3);
-
-	/* check if returned values correspond to ascii characters "ONFI" */
-	if (onfi_head.byte0 != 0x4f || onfi_head.byte1 != 0x4e ||
-		onfi_head.byte2 != 0x46 || onfi_head.byte3 != 0x49)
-		return 1;
-
-	return 0;
+	return ret;
 }
 
-static int mxs_nand_get_readid(struct mxs_nand_info *info, void *databuf)
+struct onfi_header {
+	u8 byte0;
+	u8 byte1;
+	u8 byte2;
+	u8 byte3;
+};
+
+static int mxs_nand_check_onfi(struct mxs_nand_info *info, void *databuf)
 {
 	int ret;
-	u8 *cmd_buf;
-	struct mxs_dma_cmd *d;
-	int descnum = 0;
-	int cmd_queue_len;
-
-	struct readid_data {
-		u8 byte0;
-		u8 byte1;
-		u8 byte2;
-		u8 byte3;
-		u8 byte4;
-	} id_data;
+	struct onfi_header *onfi_head = databuf;
 
-	memset(info->desc, 0,
-		sizeof(*info->desc) * MXS_NAND_DMA_DESCRIPTOR_COUNT);
+	ret = mxs_nand_read_id(info, 0x20, databuf, sizeof(struct onfi_header));
+	if (ret)
+		return ret;
 
-	/* Compile DMA descriptor - READID */
-	cmd_buf = info->cmd_buf;
-	cmd_queue_len = 0;
-	d = &info->desc[descnum++];
-	d->address = (dma_addr_t)(cmd_buf);
-	cmd_buf[cmd_queue_len++] = NAND_CMD_READID;
-	cmd_buf[cmd_queue_len++] = 0x00;
+	pr_debug("ONFI Byte0: 0x%x\n", onfi_head->byte0);
+	pr_debug("ONFI Byte1: 0x%x\n", onfi_head->byte1);
+	pr_debug("ONFI Byte2: 0x%x\n", onfi_head->byte2);
+	pr_debug("ONFI Byte3: 0x%x\n", onfi_head->byte3);
 
-	d->data = DMACMD_COMMAND_DMA_READ |
-		DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(cmd_queue_len);
+	if (onfi_head->byte0 != 'O' || onfi_head->byte1 != 'N' ||
+		onfi_head->byte2 != 'F' || onfi_head->byte3 != 'I')
+		return 1;
 
-	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_WRITE |
-		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
-		GPMI_CTRL0_ADDRESS_NAND_CLE |
-		GPMI_CTRL0_ADDRESS_INCREMENT |
-		cmd_queue_len;
+	return 0;
+}
 
-	/* Compile DMA descriptor - read. */
-	d = &info->desc[descnum++];
-	d->data = DMACMD_WAIT4END |
-		DMACMD_PIO_WORDS(1) |
-		DMACMD_XFER_COUNT(sizeof(struct readid_data)) |
-		DMACMD_COMMAND_DMA_WRITE;
-	d->pio_words[0] = GPMI_CTRL0_COMMAND_MODE_READ |
-		GPMI_CTRL0_WORD_LENGTH |
-		GPMI_CTRL0_CS(info->cs) |
-		GPMI_CTRL0_ADDRESS_NAND_DATA |
-		(sizeof(struct readid_data));
-	d->address = (dma_addr_t)databuf;
+struct readid_data {
+	u8 byte0;
+	u8 byte1;
+	u8 byte2;
+	u8 byte3;
+	u8 byte4;
+};
 
-	/* Compile DMA descriptor - de-assert the NAND lock and interrupt. */
-	d = &info->desc[descnum++];
-	d->data = DMACMD_IRQ | DMACMD_DEC_SEM;
+static int mxs_nand_get_readid(struct mxs_nand_info *info, void *databuf)
+{
+	int ret;
+	struct readid_data *id_data = databuf;
 
-	/* Execute the DMA chain. */
-	ret = mxs_dma_run(info->dma_channel, info->desc, descnum);
-	if (ret) {
-		pr_err("DMA read error\n");
+	ret = mxs_nand_read_id(info, 0x0, databuf, sizeof(struct readid_data));
+	if (ret)
 		return ret;
-	}
 
-	memcpy(&id_data, databuf, sizeof(struct readid_data));
+	pr_debug("NAND Byte0: 0x%x\n", id_data->byte0);
+	pr_debug("NAND Byte1: 0x%x\n", id_data->byte1);
+	pr_debug("NAND Byte2: 0x%x\n", id_data->byte2);
+	pr_debug("NAND Byte3: 0x%x\n", id_data->byte3);
+	pr_debug("NAND Byte4: 0x%x\n", id_data->byte4);
 
-	pr_debug("NAND Byte0: 0x%x\n", id_data.byte0);
-	pr_debug("NAND Byte1: 0x%x\n", id_data.byte1);
-	pr_debug("NAND Byte2: 0x%x\n", id_data.byte2);
-	pr_debug("NAND Byte3: 0x%x\n", id_data.byte3);
-	pr_debug("NAND Byte4: 0x%x\n", id_data.byte4);
-
-	if (id_data.byte0 == 0xff || id_data.byte1 == 0xff ||
-		id_data.byte2 == 0xff || id_data.byte3 == 0xff ||
-		id_data.byte4 == 0xff) {
+	if (id_data->byte0 == 0xff || id_data->byte1 == 0xff ||
+		id_data->byte2 == 0xff || id_data->byte3 == 0xff ||
+		id_data->byte4 == 0xff) {
 		pr_err("\"READ ID\" returned 0xff, possible error!\n");
 		return -EOVERFLOW;
 	}
 
 	/* Fill the NAND organization struct with data */
 	info->organization.bits_per_cell =
-		(1 << ((id_data.byte2 >> 2) & 0x3)) * 2;
+		(1 << ((id_data->byte2 >> 2) & 0x3)) * 2;
 	info->organization.pagesize =
-		(1 << (id_data.byte3 & 0x3)) * SZ_1K;
-	info->organization.oobsize = id_data.byte3 & 0x4 ?
+		(1 << (id_data->byte3 & 0x3)) * SZ_1K;
+	info->organization.oobsize = id_data->byte3 & 0x4 ?
 		info->organization.pagesize / 512 * 16 :
 		info->organization.pagesize / 512 * 8;
 	info->organization.pages_per_eraseblock =
-		(1 << ((id_data.byte3 >> 4) & 0x3)) * SZ_64K /
+		(1 << ((id_data->byte3 >> 4) & 0x3)) * SZ_64K /
 		info->organization.pagesize;
 	info->organization.planes_per_lun =
-		1 << ((id_data.byte4 >> 2) & 0x3);
+		1 << ((id_data->byte4 >> 2) & 0x3);
 	info->nand_size = info->organization.planes_per_lun *
-		(1 << ((id_data.byte4 >> 4) & 0x7)) * SZ_8M;
+		(1 << ((id_data->byte4 >> 4) & 0x7)) * SZ_8M;
 	info->organization.eraseblocks_per_lun = info->nand_size /
 		(info->organization.pages_per_eraseblock *
 		info->organization.pagesize);
@@ -889,6 +767,10 @@ static int mxs_nand_get_info(struct mxs_nand_info *info, void *databuf)
 {
 	int ret, i;
 
+	ret = mxs_nand_reset(info, databuf);
+	if (ret)
+		return ret;
+
 	ret = mxs_nand_check_onfi(info, databuf);
 	if (ret) {
 		if (ret != 1)
@@ -966,7 +848,7 @@ static uint32_t calc_chksum(void *buf, size_t size)
 	return ~chksum;
 }
 
-static int get_fcb(struct mxs_nand_info *info, void *databuf)
+static int imx6_get_fcb(struct mxs_nand_info *info, void *databuf)
 {
 	int i, pagenum, ret;
 	uint32_t checksum;
@@ -974,13 +856,17 @@ static int get_fcb(struct mxs_nand_info *info, void *databuf)
 
 	/* First page read fails, this shouldn't be necessary */
 	mxs_nand_read_page(info, info->organization.pagesize,
-		info->organization.oobsize, 0, databuf, 1);
+		info->organization.oobsize, 0, databuf, 1, false);
 
 	for (i = 0; i < 4; i++) {
 		pagenum = info->organization.pages_per_eraseblock * i;
 
 		ret = mxs_nand_read_page(info, info->organization.pagesize,
-			info->organization.oobsize, pagenum, databuf, 1);
+			info->organization.oobsize, pagenum, databuf, 1, false);
+		if (ret)
+			continue;
+
+		ret = mxs_nand_get_ecc_status(info, databuf);
 		if (ret)
 			continue;
 
@@ -1002,23 +888,72 @@ static int get_fcb(struct mxs_nand_info *info, void *databuf)
 			continue;
 		}
 
-		pr_debug("Found FCB:\n");
-		pr_debug("PageDataSize:     0x%08x\n", fcb->PageDataSize);
-		pr_debug("TotalPageSize:    0x%08x\n", fcb->TotalPageSize);
-		pr_debug("SectorsPerBlock:  0x%08x\n", fcb->SectorsPerBlock);
-		pr_debug("FW1_startingPage: 0x%08x\n",
-			fcb->Firmware1_startingPage);
-		pr_debug("PagesInFW1:       0x%08x\n", fcb->PagesInFirmware1);
-		pr_debug("FW2_startingPage: 0x%08x\n",
-			fcb->Firmware2_startingPage);
-		pr_debug("PagesInFW2:       0x%08x\n", fcb->PagesInFirmware2);
-
 		return 0;
 	}
 
 	return -EINVAL;
 }
 
+static int imx7_get_fcb_n(struct mxs_nand_info *info, void *databuf, int num)
+{
+	int ret;
+	int flips = 0;
+	uint8_t	*status;
+	int i;
+
+	ret = mxs_nand_read_page(info, BCH62_WRITESIZE, BCH62_OOBSIZE,
+				 info->organization.pages_per_eraseblock * num, databuf, 0, true);
+	if (ret)
+		return ret;
+
+	/* Loop over status bytes, accumulating ECC status. */
+	status = databuf + BCH62_WRITESIZE + 32;
+
+	for (i = 0; i < 8; i++) {
+		switch (status[i]) {
+		case 0x0:
+			break;
+		case 0xff:
+			/*
+			 * A status of 0xff means the chunk is erased, but due to
+			 * the randomizer we see this as random data. Explicitly
+			 * memset it.
+			 */
+			memset(databuf + 0x80 * i, 0xff, 0x80);
+			break;
+		case 0xfe:
+			return -EBADMSG;
+		default:
+			flips += status[0];
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int imx7_get_fcb(struct mxs_nand_info *info, void *databuf)
+{
+	int i, ret;
+	struct fcb_block *fcb = &info->fcb;
+
+	mxs_nand_mode_fcb_62bit(info->bch_base);
+
+	for (i = 0; i < 4; i++) {
+		ret = imx7_get_fcb_n(info, databuf, i);
+		if (!ret)
+			break;
+	}
+
+	if (ret) {
+		pr_err("Cannot find FCB\n");
+	} else {
+		memcpy(fcb, databuf, sizeof(*fcb));
+	}
+
+	return ret;
+}
+
 static int get_dbbt(struct mxs_nand_info *info, void *databuf)
 {
 	int i, ret;
@@ -1030,7 +965,11 @@ static int get_dbbt(struct mxs_nand_info *info, void *databuf)
 		page = startpage + i * info->organization.pages_per_eraseblock;
 
 		ret = mxs_nand_read_page(info, info->organization.pagesize,
-			info->organization.oobsize, page, databuf, 0);
+			info->organization.oobsize, page, databuf, 0, false);
+		if (ret)
+			continue;
+
+		ret = mxs_nand_get_ecc_status(info, databuf);
 		if (ret)
 			continue;
 
@@ -1044,7 +983,11 @@ static int get_dbbt(struct mxs_nand_info *info, void *databuf)
 			return -ENOENT;
 
 		ret = mxs_nand_read_page(info, info->organization.pagesize,
-			info->organization.oobsize, page + 4, databuf, 0);
+			info->organization.oobsize, page + 4, databuf, 0, false);
+		if (ret)
+			continue;
+
+		ret = mxs_nand_get_ecc_status(info, databuf);
 		if (ret)
 			continue;
 
@@ -1115,7 +1058,7 @@ static int read_firmware(struct mxs_nand_info *info, int startpage,
 		}
 
 		ret = mxs_nand_read_page(info, pagesize, oobsize,
-			curpage, dest, 0);
+			curpage, dest, 0, false);
 		if (ret) {
 			pr_debug("Failed to read page %d\n", curpage);
 			return ret;
@@ -1132,49 +1075,73 @@ static int read_firmware(struct mxs_nand_info *info, int startpage,
 	return 0;
 }
 
-static int __maybe_unused imx6_nand_load_image(void *cmdbuf, void *descs,
-	void *databuf, void *dest, int len)
+struct imx_nand_params {
+	struct mxs_nand_info info;
+	struct apbh_dma apbh;
+	void *sdram;
+	int (*get_fcb)(struct mxs_nand_info *info, void *databuf);
+};
+
+static int __maybe_unused imx6_nand_load_image(struct imx_nand_params *params,
+					       void *databuf, void *dest, int len)
 {
-	struct mxs_nand_info info = {
-		.io_base = (void *)0x00112000,
-		.bch_base = (void *)0x00114000,
-	};
-	struct apbh_dma apbh = {
-		.id = IMX28_DMA,
-		.regs = (void *)0x00110000,
-	};
+	struct mxs_nand_info *info = &params->info;
 	struct mxs_dma_chan pchan = {
 		.channel = 0, /* MXS: MXS_DMA_CHANNEL_AHB_APBH_GPMI0 */
-		.apbh = &apbh,
+		.apbh = &params->apbh,
 	};
 	int ret;
 	struct fcb_block *fcb;
+	void __iomem *bch_regs = info->bch_base;
+	u32 fl0, fl1;
 
-	info.dma_channel = &pchan;
+	info->dma_channel = &pchan;
 
 	pr_debug("cmdbuf: 0x%p descs: 0x%p databuf: 0x%p dest: 0x%p\n",
-			cmdbuf, descs, databuf, dest);
-
-	/* Command buffers */
-	info.cmd_buf = cmdbuf;
-	info.desc = descs;
+			info->cmd_buf, info->desc, databuf, dest);
 
-	ret = mxs_nand_get_info(&info, databuf);
+	ret = mxs_nand_get_info(info, databuf);
 	if (ret)
 		return ret;
 
-	ret = get_fcb(&info, databuf);
+	ret = params->get_fcb(info, databuf);
 	if (ret)
 		return ret;
 
-	fcb = &info.fcb;
-
-	get_dbbt(&info, databuf);
-
-	ret = read_firmware(&info, fcb->Firmware1_startingPage, dest, len);
+	fcb = &info->fcb;
+
+	pr_debug("Found FCB:\n");
+	pr_debug("PageDataSize:     0x%08x\n", fcb->PageDataSize);
+	pr_debug("TotalPageSize:    0x%08x\n", fcb->TotalPageSize);
+	pr_debug("SectorsPerBlock:  0x%08x\n", fcb->SectorsPerBlock);
+	pr_debug("FW1_startingPage: 0x%08x\n",
+		fcb->Firmware1_startingPage);
+	pr_debug("PagesInFW1:       0x%08x\n", fcb->PagesInFirmware1);
+	pr_debug("FW2_startingPage: 0x%08x\n",
+		fcb->Firmware2_startingPage);
+	pr_debug("PagesInFW2:       0x%08x\n", fcb->PagesInFirmware2);
+
+	info->organization.oobsize = fcb->TotalPageSize - fcb->PageDataSize;
+	info->organization.pagesize = fcb->PageDataSize;
+
+	fl0 = FIELD_PREP(BCH_FLASHLAYOUT0_NBLOCKS, fcb->NumEccBlocksPerPage) |
+		FIELD_PREP(BCH_FLASHLAYOUT0_META_SIZE, fcb->MetadataBytes) |
+		FIELD_PREP(IMX6_BCH_FLASHLAYOUT0_ECC0, fcb->EccBlock0EccType) |
+		(fcb->BCHType ? BCH_FLASHLAYOUT0_GF13_0_GF14_1 : 0) |
+		FIELD_PREP(BCH_FLASHLAYOUT0_DATA0_SIZE, fcb->EccBlock0Size / 4);
+	fl1 = FIELD_PREP(BCH_FLASHLAYOUT1_PAGE_SIZE, fcb->TotalPageSize) |
+		FIELD_PREP(IMX6_BCH_FLASHLAYOUT1_ECCN, fcb->EccBlockNEccType) |
+		(fcb->BCHType ? BCH_FLASHLAYOUT1_GF13_0_GF14_1 : 0) |
+		FIELD_PREP(BCH_FLASHLAYOUT1_DATAN_SIZE, fcb->EccBlockNSize / 4);
+	writel(fl0, bch_regs + BCH_FLASH0LAYOUT0);
+	writel(fl1, bch_regs + BCH_FLASH0LAYOUT1);
+
+	get_dbbt(info, databuf);
+
+	ret = read_firmware(info, fcb->Firmware1_startingPage, dest, len);
 	if (ret) {
 		pr_err("Failed to read firmware1, trying firmware2\n");
-		ret = read_firmware(&info, fcb->Firmware2_startingPage,
+		ret = read_firmware(info, fcb->Firmware2_startingPage,
 			dest, len);
 		if (ret) {
 			pr_err("Failed to also read firmware2\n");
@@ -1185,24 +1152,21 @@ static int __maybe_unused imx6_nand_load_image(void *cmdbuf, void *descs,
 	return 0;
 }
 
-int imx6_nand_start_image(void)
+static int imx_nand_start_image(struct imx_nand_params *params)
 {
+	struct mxs_nand_info *info = &params->info;
 	int ret;
-	void *sdram = (void *)0x10000000;
 	void __noreturn (*bb)(void);
-	void *cmdbuf, *databuf, *descs;
+	void *databuf;
 
-	cmdbuf = sdram;
-	descs = sdram + MXS_NAND_COMMAND_BUFFER_SIZE;
-	databuf = descs +
+	/* Command buffers */
+	info->cmd_buf = params->sdram;
+	info->desc = params->sdram + MXS_NAND_COMMAND_BUFFER_SIZE;
+	databuf = info->desc +
 		sizeof(struct mxs_dma_cmd) * MXS_NAND_DMA_DESCRIPTOR_COUNT;
 	bb = (void *)PAGE_ALIGN((unsigned long)databuf + SZ_8K);
 
-	/* Apply ERR007117 workaround */
-	imx6_errata_007117_enable();
-
-	ret = imx6_nand_load_image(cmdbuf, descs, databuf,
-		bb, imx_image_size());
+	ret = imx6_nand_load_image(params, databuf, bb, imx_image_size());
 	if (ret) {
 		pr_err("Loading image failed: %d\n", ret);
 		return ret;
@@ -1215,3 +1179,34 @@ int imx6_nand_start_image(void)
 
 	bb();
 }
+
+int imx6_nand_start_image(void)
+{
+	static struct imx_nand_params params = {
+		.info.io_base = IOMEM(MX6_GPMI_BASE_ADDR),
+		.info.bch_base = IOMEM(MX6_BCH_BASE_ADDR),
+		.apbh.regs = IOMEM(MX6_APBH_BASE_ADDR),
+		.apbh.id = IMX28_DMA,
+		.sdram = (void *)MX6_MMDC_PORT01_BASE_ADDR,
+		.get_fcb = imx6_get_fcb,
+	};
+
+	/* Apply ERR007117 workaround */
+	imx6_errata_007117_enable();
+
+	return imx_nand_start_image(&params);
+}
+
+int imx7_nand_start_image(void)
+{
+	static struct imx_nand_params params = {
+		.info.io_base = IOMEM(MX7_GPMI_BASE),
+		.info.bch_base = IOMEM(MX7_BCH_BASE),
+		.apbh.regs = IOMEM(MX7_APBH_BASE),
+		.apbh.id = IMX28_DMA,
+		.sdram = (void *)MX7_DDR_BASE_ADDR,
+		.get_fcb = imx7_get_fcb,
+	};
+
+	return imx_nand_start_image(&params);
+}
diff --git a/arch/arm/mach-imx/xload-imx-nand.c b/arch/arm/mach-imx/xload-imx-nand.c
index ff54941a0c..e80f99eb99 100644
--- a/arch/arm/mach-imx/xload-imx-nand.c
+++ b/arch/arm/mach-imx/xload-imx-nand.c
@@ -1,15 +1,5 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+
 #define pr_fmt(fmt)	"imx-nand-boot: " fmt
 
 #include <common.h>
@@ -17,10 +7,10 @@
 #include <io.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/mtd/nand.h>
-#include <mach/imx-nand.h>
-#include <mach/generic.h>
-#include <mach/imx53-regs.h>
-#include <mach/xload.h>
+#include <mach/imx/imx-nand.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/xload.h>
 
 struct imx_nand {
 	void __iomem *base;
diff --git a/arch/arm/mach-imx/xload-qspi.c b/arch/arm/mach-imx/xload-qspi.c
new file mode 100644
index 0000000000..327a560f8b
--- /dev/null
+++ b/arch/arm/mach-imx/xload-qspi.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/imx8m-regs.h>
+#include <mach/imx/xload.h>
+
+#define IMX8M_QSPI_MMAP		0x8000000
+
+/* Make use of AHB reads */
+static
+int imx8m_qspi_read(void *dest, size_t len, void *priv)
+{
+	void __iomem *qspi_ahb = priv;
+
+	memcpy(dest, qspi_ahb, len);
+
+	return 0;
+}
+
+/**
+ * imx8mm_qspi_start_image - Load and optionally start an image from the
+ *                           FlexSPI controller.
+ * @instance: The FlexSPI controller instance
+ *
+ * This uses imx8m_qspi_load_image() to load an image from QSPI. It is assumed
+ * that the image is the currently running barebox image.
+ * The image is not started afterwards.
+ *
+ * Return: If image successfully loaded, returns 0.
+ * A negative error code is returned when this function fails.
+ */
+static
+int imx8m_qspi_load_image(int instance, off_t offset, off_t ivt_offset, void *bl33)
+{
+	void __iomem *qspi_ahb = IOMEM(IMX8M_QSPI_MMAP);
+
+	return imx_load_image(MX8M_DDR_CSD1_BASE_ADDR, (ptrdiff_t)bl33,
+			      offset, ivt_offset, false, 0,
+			      imx8m_qspi_read, qspi_ahb);
+}
+
+int imx8mm_qspi_load_image(int instance, void *bl33)
+{
+	return imx8m_qspi_load_image(instance, 0, SZ_4K, bl33);
+}
+
+int imx8mn_qspi_load_image(int instance, void *bl33)
+{
+	return imx8m_qspi_load_image(instance, SZ_4K, 0, bl33);
+}
+
+int imx8mp_qspi_load_image(int instance, void *bl33)
+	__alias(imx8mn_qspi_load_image);
diff --git a/arch/arm/mach-imx/xload-spi.c b/arch/arm/mach-imx/xload-spi.c
index e87af81e41..621e9557be 100644
--- a/arch/arm/mach-imx/xload-spi.c
+++ b/arch/arm/mach-imx/xload-spi.c
@@ -1,12 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <io.h>
 #include <spi/imx-spi.h>
-#include <mach/imx6-regs.h>
-#include <mach/generic.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/generic.h>
 #include <bootsource.h>
 #include <asm/sections.h>
 #include <linux/sizes.h>
-#include <mach/xload.h>
+#include <mach/imx/xload.h>
 
 static int cspi_2_3_read_data(void __iomem *base, u32 *data)
 {
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
new file mode 100644
index 0000000000..152d231a56
--- /dev/null
+++ b/arch/arm/mach-k3/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+menu "K3 boards"
+        depends on ARCH_K3
+
+config MACH_BEAGLEPLAY
+	bool "BeagleBoard BeaglePlay"
+	help
+	  Say Y here if you are using a TI AM62x based BeaglePlay board
+
+endmenu
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
new file mode 100644
index 0000000000..f95691b59a
--- /dev/null
+++ b/arch/arm/mach-k3/Makefile
@@ -0,0 +1 @@
+obj-y += common.o
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
new file mode 100644
index 0000000000..7c2375d3ec
--- /dev/null
+++ b/arch/arm/mach-k3/common.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <of.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <pm_domain.h>
+
+static const struct of_device_id k3_of_match[] = {
+	{
+		.compatible = "ti,am625",
+	},
+	{ /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(k3_of_match);
+
+static int am625_init(void)
+{
+	if (!of_machine_is_compatible("ti,am625"))
+		return 0;
+
+	genpd_activate();
+
+	return 0;
+}
+postcore_initcall(am625_init);
diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig
index c15d5873a5..5658a63b33 100644
--- a/arch/arm/mach-layerscape/Kconfig
+++ b/arch/arm/mach-layerscape/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_LAYERSCAPE
 
 config ARCH_LAYERSCAPE_PPA
@@ -5,7 +7,6 @@ config ARCH_LAYERSCAPE_PPA
 	select ARM_PSCI_OF
 	select ARM_SMCCC
 	select FITIMAGE
-	bool
 	help
 	  The "Primary Protected Application" (PPA) is a PSCI compliant firmware
 	  distributed by NXP. It is needed to start the secondary cores on
@@ -13,10 +14,23 @@ config ARCH_LAYERSCAPE_PPA
 	  work properly. The precompiled firmware images can be found here:
 	  https://github.com/NXP/qoriq-ppa-binary
 
-config ARCH_LS1046
+config ARCH_LS1028
+	bool
 	select CPU_V8
 	select SYS_SUPPORTS_64BIT_KERNEL
+	select ARM_ATF
+	select FIRMWARE_LS1028A_ATF
+
+config ARCH_LS1046
 	bool
+	select CPU_V8
+	select SYS_SUPPORTS_64BIT_KERNEL
+
+if 64BIT
+
+config MACH_LS1028ARDB
+	bool "QorIQ LS1028A Reference Design Board"
+	select ARCH_LS1028
 
 config MACH_LS1046ARDB
 	bool "QorIQ LS1046A Reference Design Board"
@@ -35,3 +49,19 @@ config MACH_TQMLS1046A
 	select DDR_FSL_DDR4
 
 endif
+
+config ARCH_LS1021
+	select CPU_V7
+	bool
+
+if 32BIT
+
+config MACH_LS1021AIOT
+	bool "LS1021AIOT Board"
+	select ARCH_LS1021
+	select DDR_FSL
+	select DDR_FSL_DDR3
+
+endif
+
+endif
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index 854a327c91..e4bb1b42f2 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -1,8 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj- := __dummy__.o
-lwl-y += lowlevel.o errata.o
-lwl-$(CONFIG_ARCH_LS1046) += lowlevel-ls1046a.o
-obj-y += icid.o
-obj-pbl-y += boot.o
+lwl-y += errata.o
+lwl-$(CONFIG_ARCH_LS1046) += lowlevel.o lowlevel-ls1046a.o
+obj-$(CONFIG_ARCH_LS1046) += icid.o
+obj-pbl-y += boot.o soc.o
 pbl-y += xload-qspi.o xload.o
+pbl-$(CONFIG_ARCH_LS1028) += tzc400.o
 obj-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa.o ppa-entry.o
 obj-$(CONFIG_BOOTM) += pblimage.o
+
+lwl-$(CONFIG_ARCH_LS1021) += lowlevel-ls102xa.o
+obj-$(CONFIG_ARCH_LS1021) += restart.o ls102xa_stream_id.o
+
+lwl-$(CONFIG_ARCH_LS1028) += lowlevel-ls1028a.o
diff --git a/arch/arm/mach-layerscape/boot.c b/arch/arm/mach-layerscape/boot.c
index c804977d22..4d074205cc 100644
--- a/arch/arm/mach-layerscape/boot.c
+++ b/arch/arm/mach-layerscape/boot.c
@@ -3,10 +3,12 @@
 #include <common.h>
 #include <init.h>
 #include <bootsource.h>
-#include <mach/layerscape.h>
+#include <linux/bitfield.h>
+#include <mach/layerscape/layerscape.h>
 #include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/immap_lsch3.h>
 
-enum bootsource ls1046_bootsource_get(void)
+enum bootsource ls1046a_bootsource_get(void)
 {
 	void __iomem *dcfg = IOMEM(LSCH2_DCFG_ADDR);
 	uint32_t rcw_src;
@@ -27,13 +29,55 @@ enum bootsource ls1046_bootsource_get(void)
 	return BOOTSOURCE_UNKNOWN;
 }
 
-static int ls1046a_bootsource_init(void)
+enum bootsource ls1021a_bootsource_get(void)
 {
-	if (!of_machine_is_compatible("fsl,ls1046a"))
-		return 0;
+	return ls1046a_bootsource_get();
+}
+
+void ls1021a_bootsource_init(void)
+{
+	bootsource_set_raw(ls1021a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
+}
+
+void ls1046a_bootsource_init(void)
+{
+	bootsource_set_raw(ls1046a_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
+}
+
+#define PORSR1_RCW_SRC	GENMASK(26, 23)
+
+static enum bootsource ls1028a_bootsource_get(int *instance)
+{
+	void __iomem *porsr1 = IOMEM(LSCH3_DCFG_BASE);
+	uint32_t rcw_src;
 
-	bootsource_set(ls1046_bootsource_get());
+	rcw_src = FIELD_GET(PORSR1_RCW_SRC, readl(porsr1));
+
+	printf("%s: 0x%08x\n", __func__, rcw_src);
+
+	switch (rcw_src) {
+	case 8:
+		*instance = 0;
+		return BOOTSOURCE_MMC;
+	case 9:
+		*instance = 1;
+		return BOOTSOURCE_MMC;
+	case 0xa:
+		return BOOTSOURCE_I2C;
+	case 0xd:
+	case 0xc:
+		return BOOTSOURCE_NAND;
+	case 0xf:
+		return BOOTSOURCE_SPI_NOR;
+	}
+
+	return BOOTSOURCE_UNKNOWN;
+}
+
+void ls1028a_bootsource_init(void)
+{
+	int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+	enum bootsource source = ls1028a_bootsource_get(&instance);
 
-	return 0;
+	bootsource_set_raw(source, instance);
 }
-coredevice_initcall(ls1046a_bootsource_init);
\ No newline at end of file
diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c
index 4f4b759ddb..deab584243 100644
--- a/arch/arm/mach-layerscape/errata.c
+++ b/arch/arm/mach-layerscape/errata.c
@@ -2,13 +2,12 @@
 #include <common.h>
 #include <io.h>
 #include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/immap_lsch3.h>
 #include <soc/fsl/fsl_ddr_sdram.h>
 #include <asm/system.h>
-#include <mach/errata.h>
-#include <mach/lowlevel.h>
-
-#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
-#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/lowlevel.h>
+#include <soc/fsl/scfg.h>
 
 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
 {
@@ -17,6 +16,22 @@ static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
 			SCFG_USB_PCSTXSWINGFULL << 9);
 }
 
+static void erratum_a008997_ls1021a(void)
+{
+	u32 __iomem *scfg = (u32 __iomem *)LSCH2_SCFG_ADDR;
+
+	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
+}
+
+static void erratum_a008997_ls1028a(void)
+{
+	void __iomem *dcsr = IOMEM(LSCH3_DCSR_BASE);
+
+	clrsetbits_le32(dcsr + LSCH3_DCSR_USB_IOCR1,
+			0x7f << 11,
+			LSCH3_DCSR_USB_PCSTXSWINGFULL << 11);
+}
+
 static void erratum_a008997_ls1046a(void)
 {
 	u32 __iomem *scfg = (u32 __iomem *)LSCH2_SCFG_ADDR;
@@ -26,22 +41,24 @@ static void erratum_a008997_ls1046a(void)
 	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
 }
 
-#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)      \
-	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);      \
-	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);      \
-	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);      \
-	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
+static void erratum_a009007(void __iomem *phy, u16 val1, u16 val2, u16 val3, u16 val4)
+{
+	scfg_out16(phy + SCFG_USB_PHY_RX_OVRD_IN_HI, val1);
+	scfg_out16(phy + SCFG_USB_PHY_RX_OVRD_IN_HI, val2);
+	scfg_out16(phy + SCFG_USB_PHY_RX_OVRD_IN_HI, val3);
+	scfg_out16(phy + SCFG_USB_PHY_RX_OVRD_IN_HI, val4);
+}
 
 static void erratum_a009007_ls1046a(void)
 {
-	void __iomem *usb_phy = IOMEM(SCFG_USB_PHY1);
-
-	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
-	usb_phy = (void __iomem *)SCFG_USB_PHY2;
-	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+	erratum_a009007(IOMEM(SCFG_USB_PHY1), 0x0000, 0x0080, 0x0380, 0x0b80);
+	erratum_a009007(IOMEM(SCFG_USB_PHY2), 0x0000, 0x0080, 0x0380, 0x0b80);
+	erratum_a009007(IOMEM(SCFG_USB_PHY3), 0x0000, 0x0080, 0x0380, 0x0b80);
+}
 
-	usb_phy = (void __iomem *)SCFG_USB_PHY3;
-	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+static void erratum_a009007_ls1021a(void)
+{
+	erratum_a009007(IOMEM(SCFG_USB_PHY1), 0x0000, 0x8000, 0x8004, 0x800C);
 }
 
 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
@@ -49,6 +66,18 @@ static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
 	scfg_clrsetbits32(scfg + offset / 4, 0xf << 6, SCFG_USB_TXVREFTUNE << 6);
 }
 
+static void erratum_a009007_ls1028a(void)
+{
+	erratum_a009007(IOMEM(LSCH3_DCSR_BASE), 0x0000, 0x0080, 0x0380, 0x0b80);
+}
+
+static void erratum_a009008_ls1021a(void)
+{
+	u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
+
+	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
+}
+
 static void erratum_a009008_ls1046a(void)
 {
 	u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
@@ -63,6 +92,13 @@ static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
 	scfg_clrbits32(scfg + offset / 4, SCFG_USB_SQRXTUNE_MASK << 23);
 }
 
+static void erratum_a009798_ls1021a(void)
+{
+	u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
+
+	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
+}
+
 static void erratum_a009798_ls1046a(void)
 {
 	u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR);
@@ -72,15 +108,16 @@ static void erratum_a009798_ls1046a(void)
 	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
 }
 
-static void erratum_a008850_early(void)
+static void erratum_a008850_early(struct ccsr_cci400 __iomem *cci,
+				  struct ccsr_ddr __iomem *ddr)
 {
 	/* part 1 of 2 */
-	struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR);
-	struct ccsr_ddr __iomem *ddr = IOMEM(LSCH2_DDR_ADDR);
 
 	/* Skip if running at lower exception level */
-	if (current_el() < 3)
-		return;
+#if __LINUX_ARM_ARCH__ > 7
+		if (current_el() < 3)
+			return;
+#endif
 
 	/* disables propagation of barrier transactions to DDRC from CCI400 */
 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@@ -89,27 +126,64 @@ static void erratum_a008850_early(void)
 	ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
 }
 
-/* erratum_a009942_check_cpo */
+/*
+ * This erratum requires a register write before being Memory
+ * controller 3 being enabled.
+ */
+static void erratum_a008514(void)
+{
+	u32 *eddrtqcr1;
+
+	eddrtqcr1 = IOMEM(LSCH3_DCSR_DDR3_ADDR) + 0x800;
+	out_le32(eddrtqcr1, 0x63b20002);
+}
+
+static void erratum_a009798(void)
+{
+        u32 __iomem *scfg = IOMEM(LSCH3_SCFG_BASE);
+
+        clrbits_be32(scfg + LSCH3_SCFG_USB3PRM1CR / 4,
+                        LSCH3_SCFG_USB_SQRXTUNE_MASK << 23);
+}
 
 void ls1046a_errata(void)
 {
-	erratum_a008850_early();
+	erratum_a008850_early(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
 	erratum_a009008_ls1046a();
 	erratum_a009798_ls1046a();
 	erratum_a008997_ls1046a();
 	erratum_a009007_ls1046a();
 }
 
-static void erratum_a008850_post(void)
+void ls1021a_errata(void)
+{
+	erratum_a008850_early(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
+	erratum_a009008_ls1021a();
+	erratum_a009798_ls1021a();
+	erratum_a008997_ls1021a();
+	erratum_a009007_ls1021a();
+}
+
+void ls1028a_errata(void)
+{
+	erratum_a008850_early(IOMEM(LSCH3_CCI400_ADDR), IOMEM(LSCH3_DDR_ADDR));
+	erratum_a009007_ls1028a();
+	erratum_a008997_ls1028a();
+	erratum_a008514();
+	erratum_a009798();
+}
+
+static void erratum_a008850_post(struct ccsr_cci400 __iomem *cci,
+				 struct ccsr_ddr __iomem *ddr)
 {
 	/* part 2 of 2 */
-	struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR);
-	struct ccsr_ddr __iomem *ddr = IOMEM(LSCH2_DDR_ADDR);
 	u32 tmp;
 
 	/* Skip if running at lower exception level */
-	if (current_el() < 3)
-		return;
+#if __LINUX_ARM_ARCH__ > 7
+		if (current_el() < 3)
+			return;
+#endif
 
 	/* enable propagation of barrier transactions to DDRC from CCI400 */
 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
@@ -190,6 +264,16 @@ static void erratum_a009942_check_cpo(void)
 
 void ls1046a_errata_post_ddr(void)
 {
-	erratum_a008850_post();
+	erratum_a008850_post(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
 	erratum_a009942_check_cpo();
 }
+
+void ls1021a_errata_post_ddr(void)
+{
+	erratum_a008850_post(IOMEM(LSCH2_CCI400_ADDR), IOMEM(LSCH2_DDR_ADDR));
+}
+
+void ls1028a_errata_post_ddr(void)
+{
+	erratum_a008850_post(IOMEM(LSCH3_CCI400_ADDR), IOMEM(LSCH3_DDR_ADDR));
+}
diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c
index aec57f4b3f..ebe3896075 100644
--- a/arch/arm/mach-layerscape/icid.c
+++ b/arch/arm/mach-layerscape/icid.c
@@ -1,10 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <io.h>
 #include <init.h>
 #include <of_address.h>
 #include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/immap_lsch3.h>
 #include <soc/fsl/fsl_qbman.h>
 #include <soc/fsl/fsl_fman.h>
+#include <mach/layerscape/layerscape.h>
 
 /*
  * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
@@ -65,6 +69,72 @@ struct icid_id_table {
 	phys_addr_t reg_addr;
 };
 
+static void of_set_iommu_prop(struct device_node *np, phandle iommu_handle,
+			       int stream_id)
+{
+	u32 prop[] = {
+		iommu_handle,
+		stream_id
+	};
+
+	of_property_write_u32_array(np, "iommus", prop, ARRAY_SIZE(prop));
+}
+
+static phandle of_get_iommu_handle(struct device_node *root)
+{
+	struct device_node *iommu;
+
+	iommu = of_find_compatible_node(root, NULL, "arm,mmu-500");
+	if (!iommu) {
+		pr_info("No \"arm,mmu-500\" node found, won't fixup\n");
+		return 0;
+	}
+
+	return of_node_create_phandle(iommu);
+}
+
+static int of_fixup_icid(struct device_node *root, phandle iommu_handle,
+			 const struct icid_id_table *icid_table, int num_icid)
+{
+	int i;
+
+	for (i = 0; i < num_icid; i++) {
+		const struct icid_id_table *icid = &icid_table[i];
+		struct device_node *np;
+
+		if (!icid->compat)
+			continue;
+
+		for_each_compatible_node_from(np, root, NULL, icid->compat) {
+			struct resource res;
+
+			if (of_address_to_resource(np, 0, &res))
+				continue;
+
+			if (res.start == icid->compat_addr) {
+				of_set_iommu_prop(np, iommu_handle, icid->id);
+				break;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static void setup_icid_offsets(const struct icid_id_table *icid_table, int num_icids, bool le)
+{
+	int i;
+
+	for (i = 0; i < num_icids; i++) {
+		const struct icid_id_table *icid = &icid_table[i];
+
+		if (le)
+			out_le32((u32 *)(icid->reg_addr), icid->reg);
+		else
+			out_be32((u32 *)(icid->reg_addr), icid->reg);
+	}
+}
+
 struct fman_icid_id_table {
 	u32 port_id;
 	u32 icid;
@@ -78,7 +148,7 @@ struct fman_icid_id_table {
 #define SEC_QIIC_LS	0x70024
 #define	SEC_IRBAR_JRn(n) 	(0x10000 * ((n) + 1))
 
-struct icid_id_table icid_tbl_ls1046a[] = {
+static const struct icid_id_table icid_tbl_ls1046a[] = {
 	{
 		.compat = "fsl,qman",
 		.id = DPAA1_SID_START,
@@ -206,7 +276,7 @@ struct icid_id_table icid_tbl_ls1046a[] = {
 	},
 };
 
-struct fman_icid_id_table fman_icid_tbl_ls1046a[] = {
+static const struct fman_icid_id_table fman_icid_tbl_ls1046a[] = {
 	{
 		.port_id = 0x02,
 		.icid = DPAA1_SID_END,
@@ -276,7 +346,7 @@ struct fman_icid_id_table fman_icid_tbl_ls1046a[] = {
 	},
 };
 
-static int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+static int get_fman_port_icid(int port_id, const struct fman_icid_id_table *tbl,
 		       const int size)
 {
 	int i;
@@ -289,24 +359,13 @@ static int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
 	return -ENODEV;
 }
 
-static void fdt_set_iommu_prop(struct device_node *np, phandle iommu_handle,
-			       int stream_id)
-{
-	u32 prop[2];
-
-	prop[0] = cpu_to_fdt32(iommu_handle);
-	prop[1] = cpu_to_fdt32(stream_id);
-
-	of_set_property(np, "iommus", prop, sizeof(prop), 1);
-}
-
-static void fdt_fixup_fman_port_icid_by_compat(struct device_node *root,
+static void of_fixup_fman_port_icid_by_compat(struct device_node *root,
 					       phandle iommu_handle,
 					       const char *compat)
 {
 	struct device_node *np;
-	int ret;
-	u32 cell_index, icid;
+	int ret, icid;
+	u32 cell_index;
 
 	for_each_compatible_node_from(np, root, NULL, compat) {
 		ret = of_property_read_u32(np, "cell-index", &cell_index);
@@ -321,11 +380,11 @@ static void fdt_fixup_fman_port_icid_by_compat(struct device_node *root,
 			continue;
 		}
 
-		fdt_set_iommu_prop(np, iommu_handle, icid);
+		of_set_iommu_prop(np, iommu_handle, icid);
 	}
 }
 
-static void fdt_fixup_fman_icids(struct device_node *root, phandle iommu_handle)
+static void of_fixup_fman_icids(struct device_node *root, phandle iommu_handle)
 {
 	static const char * const compats[] = {
 		"fsl,fman-v3-port-oh",
@@ -335,7 +394,7 @@ static void fdt_fixup_fman_icids(struct device_node *root, phandle iommu_handle)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(compats); i++)
-		fdt_fixup_fman_port_icid_by_compat(root, iommu_handle, compats[i]);
+		of_fixup_fman_port_icid_by_compat(root, iommu_handle, compats[i]);
 }
 
 struct qportal_info {
@@ -345,7 +404,7 @@ struct qportal_info {
 	u8 sdest;
 };
 
-struct qportal_info qp_info[] = {
+static const struct qportal_info qp_info[] = {
 	{
 		.dicid = DPAA1_SID_END,
 		.ficid = DPAA1_SID_END,
@@ -437,7 +496,7 @@ static void setup_qbman_portals(void)
 	out_be32(&qman->qcsp_bar, (u32)QMAN_MEM_PHYS);
 
 	for (i = 0; i < ARRAY_SIZE(qp_info); i++) {
-		struct qportal_info *qi = &qp_info[i];
+		const struct qportal_info *qi = &qp_info[i];
 
 		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (qi->icid << 16) | qi->dicid);
 		/* set frame icid */
@@ -449,22 +508,22 @@ static void setup_qbman_portals(void)
 	inhibit_portals(qpaddr, ARRAY_SIZE(qp_info), QMAN_SP_CINH_SIZE);
 }
 
-static void fdt_set_qportal_iommu_prop(struct device_node *np, phandle iommu_handle,
-			       struct qportal_info *qp_info)
+static void of_set_qportal_iommu_prop(struct device_node *np, phandle iommu_handle,
+			       const struct qportal_info *qp_info)
 {
-	u32 prop[6];
-
-	prop[0] = cpu_to_fdt32(iommu_handle);
-	prop[1] = cpu_to_fdt32(qp_info->icid);
-	prop[2] = cpu_to_fdt32(iommu_handle);
-	prop[3] = cpu_to_fdt32(qp_info->dicid);
-	prop[4] = cpu_to_fdt32(iommu_handle);
-	prop[5] = cpu_to_fdt32(qp_info->ficid);
+	u32 prop[] = {
+		iommu_handle,
+		qp_info->icid,
+		iommu_handle,
+		qp_info->dicid,
+		iommu_handle,
+		qp_info->ficid
+	};
 
-	of_set_property(np, "iommus", prop, sizeof(prop), 1);
+	of_property_write_u32_array(np, "iommus", prop, ARRAY_SIZE(prop));
 }
 
-static void fdt_fixup_qportals(struct device_node *root, phandle iommu_handle)
+static void of_fixup_qportals(struct device_node *root, phandle iommu_handle)
 {
 	struct device_node *np;
 	unsigned int maj, min;
@@ -484,77 +543,253 @@ static void fdt_fixup_qportals(struct device_node *root, phandle iommu_handle)
 		if (ret)
 			continue;
 
-		fdt_set_qportal_iommu_prop(np, iommu_handle, &qp_info[cell_index]);
+		of_set_qportal_iommu_prop(np, iommu_handle, &qp_info[cell_index]);
 	}
 }
 
-static int icid_of_fixup(struct device_node *root, void *context)
+static int of_fixup_ls1046a(struct device_node *root, void *context)
 {
-	int i;
-	struct device_node *iommu;
 	phandle iommu_handle;
 
-	iommu = of_find_compatible_node(root, NULL, "arm,mmu-500");
-	if (!iommu) {
-		pr_info("No \"arm,mmu-500\" node found, won't fixup\n");
+	iommu_handle = of_get_iommu_handle(root);
+	if (!iommu_handle)
 		return 0;
-	}
 
-	iommu_handle = of_node_create_phandle(iommu);
+	of_fixup_icid(root, iommu_handle, icid_tbl_ls1046a, ARRAY_SIZE(icid_tbl_ls1046a));
+	of_fixup_fman_icids(root, iommu_handle);
+	of_fixup_qportals(root, iommu_handle);
 
-	for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
-		struct icid_id_table *icid = &icid_tbl_ls1046a[i];
-		struct device_node *np;
+	return 0;
+}
 
-		if (!icid->compat)
-			continue;
+void ls1046a_setup_icids(void)
+{
+	struct ccsr_fman *fm = (void *)LSCH2_FM1_ADDR;
+	int i;
 
-		for_each_compatible_node_from(np, root, NULL, icid->compat) {
-			struct resource res;
+	setup_icid_offsets(icid_tbl_ls1046a, ARRAY_SIZE(icid_tbl_ls1046a), false);
 
-			if (of_address_to_resource(np, 0, &res))
-				continue;
+	/* setup fman icids */
+	for (i = 0; i < ARRAY_SIZE(fman_icid_tbl_ls1046a); i++) {
+		const struct fman_icid_id_table *icid = &fman_icid_tbl_ls1046a[i];
 
-			if (res.start == icid->compat_addr) {
-				fdt_set_iommu_prop(np, iommu_handle, icid->id);
-				break;
-			}
-		}
+		out_be32(&fm->fm_bmi_common.fmbm_ppid[icid->port_id - 1],
+			 icid->icid);
 	}
 
-	fdt_fixup_fman_icids(root, iommu_handle);
-	fdt_fixup_qportals(root, iommu_handle);
+	setup_qbman_portals();
+
+	of_register_fixup(of_fixup_ls1046a, NULL);
+}
+
+static const struct icid_id_table icid_tbl_ls1028a[] = {
+	{
+		.compat = "snps,dwc3",
+		.id = 1,
+		.reg = 1,
+		.compat_addr = LSCH3_XHCI_USB1_ADDR,
+		.reg_addr = offsetof(struct lsch3_ccsr_gur, usb1_amqr) + LSCH3_GUTS_ADDR,
+	}, {
+		.compat = "snps,dwc3",
+		.id = 2,
+		.reg = 2,
+		.compat_addr = LSCH3_XHCI_USB2_ADDR,
+		.reg_addr = offsetof(struct lsch3_ccsr_gur, usb2_amqr) + LSCH3_GUTS_ADDR,
+	}, {
+		.compat = "fsl,esdhc",
+		.id = 3,
+		.reg = 3,
+		.compat_addr = LSCH3_ESDHC1_BASE_ADDR,
+		.reg_addr = offsetof(struct lsch3_ccsr_gur, sdmm1_amqr) + LSCH3_GUTS_ADDR,
+	}, {
+		.compat = "fsl,esdhc",
+		.id = 69,
+		.reg = 69,
+		.compat_addr = LSCH3_ESDHC2_BASE_ADDR,
+		.reg_addr = offsetof(struct lsch3_ccsr_gur, sdmm2_amqr) + LSCH3_GUTS_ADDR,
+	}, {
+		.compat = "fsl,ls1028a-ahci",
+		.id = 4,
+		.reg = 4,
+		.compat_addr = LSCH3_AHCI1_ADDR,
+		.reg_addr = offsetof(struct lsch3_ccsr_gur, sata1_amqr) + LSCH3_GUTS_ADDR,
+	}, {
+		.compat = "fsl,vf610-edma",
+		.id = 40,
+		.reg = 40,
+		.compat_addr = LSCH3_EDMA_ADDR,
+		.reg_addr = offsetof(struct lsch3_ccsr_gur, spare3_amqr) + LSCH3_GUTS_ADDR,
+	},  {
+		.compat = "fsl,ls1028a-qdma",
+		.id = 5,
+		.reg = (1 << 31) | 5,
+		.compat_addr = LSCH3_QDMA_ADDR,
+		.reg_addr = LSCH3_QDMA_ADDR + QMAN_CQSIDR_REG,
+	}, {
+		.compat = NULL,
+		.id = 5,
+		.reg = (1 << 31) | 5,
+		.compat_addr = LSCH3_QDMA_ADDR,
+		.reg_addr = LSCH3_QDMA_ADDR + QMAN_CQSIDR_REG + 4,
+	}, {
+		.compat = "vivante,gc",
+		.id = 71,
+		.reg = 71,
+		.compat_addr = LSCH3_GPU_ADDR,
+		.reg_addr = offsetof(struct lsch3_ccsr_gur, misc1_amqr) + LSCH3_GUTS_ADDR,
+	}, {
+		.compat = "arm,mali-dp500",
+		.id = 72,
+		.reg = 72,
+		.compat_addr = LSCH3_DISPLAY_ADDR,
+		.reg_addr = offsetof(struct lsch3_ccsr_gur, spare2_amqr) + LSCH3_GUTS_ADDR,
+	}, {
+		.compat = "fsl,sec-v4.0-job-ring",
+		.id = 65,
+		.reg = 65,
+		.compat_addr = LSCH3_SEC_JR0_ADDR,
+		.reg_addr = offsetof(struct ccsr_sec, jrliodnr[0].ls) + LSCH3_SEC_ADDR,
+        }, {
+		.compat = "fsl,sec-v4.0-job-ring",
+		.id = 66,
+		.reg = 66,
+		.compat_addr = LSCH3_SEC_JR1_ADDR,
+		.reg_addr = offsetof(struct ccsr_sec, jrliodnr[1].ls) + LSCH3_SEC_ADDR,
+	}, {
+		.id = 67,
+		.reg = 67,
+		.compat_addr = LSCH3_SEC_JR2_ADDR,
+		.reg_addr = offsetof(struct ccsr_sec, jrliodnr[2].ls) + LSCH3_SEC_ADDR,
+	}, {
+		.compat = "fsl,sec-v4.0-job-ring",
+		.id = 68,
+		.reg = 68,
+		.compat_addr = LSCH3_SEC_JR3_ADDR,
+		.reg_addr = offsetof(struct ccsr_sec, jrliodnr[3].ls) + LSCH3_SEC_ADDR,
+	}, {
+		.id = 64,
+		.reg = 64,
+		.compat_addr = 0,
+		.reg_addr = offsetof(struct ccsr_sec, rticliodnr[0].ls) + LSCH3_SEC_ADDR,
+	}, {
+		.id = 64,
+		.reg = 64,
+		.compat_addr = 0,
+		.reg_addr = offsetof(struct ccsr_sec, rticliodnr[1].ls) + LSCH3_SEC_ADDR,
+	}, {
+		.id = 64,
+		.reg = 64,
+		.compat_addr = 0,
+		.reg_addr = offsetof(struct ccsr_sec, rticliodnr[2].ls) + LSCH3_SEC_ADDR,
+	}, {
+		.id = 64,
+		.reg = 64,
+		.compat_addr = 0,
+		.reg_addr = offsetof(struct ccsr_sec, rticliodnr[3].ls) + LSCH3_SEC_ADDR,
+	}, {
+		.id = 64,
+		.reg = 64,
+		.compat_addr = 0,
+		.reg_addr = offsetof(struct ccsr_sec, decoliodnr[0].ls) + LSCH3_SEC_ADDR,
+	}, {
+		.id = 64,
+		.reg = 64,
+		.compat_addr = 0,
+		.reg_addr = offsetof(struct ccsr_sec, decoliodnr[1].ls) + LSCH3_SEC_ADDR,
+	}
+};
+
+static int of_fixup_icid_ls1028a(struct device_node *root, void *context)
+{
+	phandle iommu_handle;
+
+	iommu_handle = of_get_iommu_handle(root);
+	if (!iommu_handle)
+		return 0;
+
+	of_fixup_icid(root, iommu_handle, icid_tbl_ls1028a, ARRAY_SIZE(icid_tbl_ls1028a));
 
 	return 0;
 }
 
-static int layerscape_setup_icids(void)
+/* offset of IERB config register per PCI function */
+static const int ierb_offset[] = {
+	0x0800,
+	0x1800,
+	0x2800,
+	0x3800,
+	0x4800,
+	0x5800,
+	0x6800,
+	-1,
+	0x0804,
+	0x0808,
+	0x1804,
+	0x1808,
+};
+
+#define ECAM_IERB_BASE                0x1f0800000ULL
+#define ECAM_IERB_MSICAR              (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE                0x30
+#define FSL_ECAM_STREAM_ID_START 41
+
+/*
+ * Use a custom function for LS1028A, for now this is the only SoC with IERB
+ * and we're currently considering reorganizing IERB for future SoCs.
+ */
+static void ls1028a_set_ecam_icids(void)
 {
 	int i;
-	struct ccsr_fman *fm = (void *)LSCH2_FM1_ADDR;
 
-	if (!of_machine_is_compatible("fsl,ls1046a"))
-		return 0;
+	out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
 
-	/* setup general icid offsets */
-	for (i = 0; i < ARRAY_SIZE(icid_tbl_ls1046a); i++) {
-		struct icid_id_table *icid = &icid_tbl_ls1046a[i];
+	for (i = 0; i < ARRAY_SIZE(ierb_offset); i++) {
+		if (ierb_offset[i] < 0)
+			continue;
 
-		out_be32((u32 *)(icid->reg_addr), icid->reg);
+		out_le32(ECAM_IERB_BASE + ierb_offset[i],
+			 FSL_ECAM_STREAM_ID_START + i);
 	}
+}
 
-	/* setup fman icids */
-	for (i = 0; i < ARRAY_SIZE(fman_icid_tbl_ls1046a); i++) {
-		struct fman_icid_id_table *icid = &fman_icid_tbl_ls1046a[i];
+static int of_fixup_ecam_ls1028a(struct device_node *root, void *context)
+{
+	struct device_node *np;
+	int i, ret;
+	const char *props[] = { "msi-map", "iommu-map" };
+	uint32_t map[4];
 
-		out_be32(&fm->fm_bmi_common.fmbm_ppid[icid->port_id - 1],
-			 icid->icid);
+	np = of_find_compatible_node(root, NULL, "pci-host-ecam-generic");
+	if (!np) {
+		pr_info("No \"pci-host-ecam-generic\" node found, won't fixup\n");
+		return 0;
 	}
 
-	setup_qbman_portals();
+	for (i = 0; i < ARRAY_SIZE(props); i++) {
+		ret = of_property_read_u32_array(np, props[i], map, 4);
+		if (ret) {
+			pr_err("Cannot read \"%s\" property: %pe", props[i], ERR_PTR(ret));
+			return ret;
+		}
 
-	of_register_fixup(icid_of_fixup, NULL);
+		map[2] = FSL_ECAM_STREAM_ID_START;
+		map[3] = ARRAY_SIZE(ierb_offset);
+		ret = of_property_write_u32_array(np, props[i], map, 4);
+		if (ret) {
+			pr_err("Cannot write \"%s\" property: %pe", props[i], ERR_PTR(ret));
+			return ret;
+		}
+	}
 
 	return 0;
 }
-coredevice_initcall(layerscape_setup_icids);
+
+void ls1028a_setup_icids(void)
+{
+	setup_icid_offsets(icid_tbl_ls1028a, ARRAY_SIZE(icid_tbl_ls1028a), true);
+
+	ls1028a_set_ecam_icids();
+
+	of_register_fixup(of_fixup_icid_ls1028a, NULL);
+	of_register_fixup(of_fixup_ecam_ls1028a, NULL);
+}
diff --git a/arch/arm/mach-layerscape/include/mach/bbu.h b/arch/arm/mach-layerscape/include/mach/bbu.h
deleted file mode 100644
index 1ea0cbb11f..0000000000
--- a/arch/arm/mach-layerscape/include/mach/bbu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __MACH_LAYERSCAPE_BBU_H
-#define __MACH_LAYERSCAPE_BBU_H
-
-#include <bbu.h>
-
-static inline int ls1046a_bbu_mmc_register_handler(const char *name,
-						   const char *devicefile,
-						   unsigned long flags)
-{
-	return bbu_register_std_file_update(name, flags, devicefile,
-					    filetype_layerscape_image);
-}
-
-static inline int ls1046a_bbu_qspi_register_handler(const char *name,
-						    const char *devicefile,
-						    unsigned long flags)
-{
-	return bbu_register_std_file_update(name, flags, devicefile,
-					    filetype_layerscape_qspi_image);
-}
-
-#endif /* __MACH_LAYERSCAPE_BBU_H */
\ No newline at end of file
diff --git a/arch/arm/mach-layerscape/include/mach/debug_ll.h b/arch/arm/mach-layerscape/include/mach/debug_ll.h
deleted file mode 100644
index 2658a4a7c9..0000000000
--- a/arch/arm/mach-layerscape/include/mach/debug_ll.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
-#define __INCLUDE_ARCH_DEBUG_LL_H__
-
-#include <io.h>
-#include <soc/fsl/immap_lsch2.h>
-
-#define __LS_UART_BASE(num)	LSCH2_NS16550_COM##num
-#define LS_UART_BASE(num) __LS_UART_BASE(num)
-
-static inline uint8_t debug_ll_read_reg(int reg)
-{
-	void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT));
-
-	return readb(base + reg);
-}
-
-static inline void debug_ll_write_reg(int reg, uint8_t val)
-{
-	void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT));
-
-	writeb(val, base + reg);
-}
-
-#include <debug_ll/ns16550.h>
-
-static inline void debug_ll_init(void)
-{
-	uint16_t divisor;
-
-	divisor = debug_ll_ns16550_calc_divisor(300000000);
-	debug_ll_ns16550_init(divisor);
-}
-
-#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-layerscape/include/mach/errata.h b/arch/arm/mach-layerscape/include/mach/errata.h
deleted file mode 100644
index bdefa22172..0000000000
--- a/arch/arm/mach-layerscape/include/mach/errata.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_ERRATA_H
-#define __MACH_ERRATA_H
-
-void ls1046a_errata(void);
-void ls1046a_errata_post_ddr(void);
-
-#endif /* __MACH_ERRATA_H */
diff --git a/arch/arm/mach-layerscape/include/mach/layerscape.h b/arch/arm/mach-layerscape/include/mach/layerscape.h
deleted file mode 100644
index 1f1da0f66e..0000000000
--- a/arch/arm/mach-layerscape/include/mach/layerscape.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __MACH_LAYERSCAPE_H
-#define __MACH_LAYERSCAPE_H
-
-#define LS1046A_DDR_SDRAM_BASE	0x80000000
-#define LS1046A_DDR_FREQ	2100000000
-
-enum bootsource ls1046_bootsource_get(void);
-
-#ifdef CONFIG_ARCH_LAYERSCAPE_PPA
-int ls1046a_ppa_init(resource_size_t ppa_start, resource_size_t ppa_size);
-#else
-static inline int ls1046a_ppa_init(resource_size_t ppa_start,
-				   resource_size_t ppa_size)
-{
-	return -ENOSYS;
-}
-#endif
-
-#endif /* __MACH_LAYERSCAPE_H */
diff --git a/arch/arm/mach-layerscape/include/mach/lowlevel.h b/arch/arm/mach-layerscape/include/mach/lowlevel.h
deleted file mode 100644
index 0f5f0f3aad..0000000000
--- a/arch/arm/mach-layerscape/include/mach/lowlevel.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_LOWLEVEL_H
-#define __MACH_LOWLEVEL_H
-
-void ls1046a_init_lowlevel(void);
-void ls1046a_init_l2_latency(void);
-
-#endif /* __MACH_LOWLEVEL_H */
diff --git a/arch/arm/mach-layerscape/include/mach/xload.h b/arch/arm/mach-layerscape/include/mach/xload.h
deleted file mode 100644
index eb2d998865..0000000000
--- a/arch/arm/mach-layerscape/include/mach/xload.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __MACH_XLOAD_H
-#define __MACH_XLOAD_H
-
-int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2);
-int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
-					     unsigned long r2);
-int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
-			      unsigned long r2);
-
-#endif /* __MACH_XLOAD_H */
diff --git a/arch/arm/mach-layerscape/lowlevel-ls1028a.c b/arch/arm/mach-layerscape/lowlevel-ls1028a.c
new file mode 100644
index 0000000000..fd013b2b52
--- /dev/null
+++ b/arch/arm/mach-layerscape/lowlevel-ls1028a.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <common.h>
+#include <io.h>
+#include <asm/syscounter.h>
+#include <asm/system.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/lowlevel.h>
+#include <soc/fsl/immap_lsch3.h>
+#include <soc/fsl/scfg.h>
+
+static void ls1028a_timer_init(void)
+{
+	u32 __iomem *cntcr = IOMEM(LSCH3_TIMER_ADDR);
+	u32 __iomem *cltbenr = IOMEM(LSCH3_PMU_CLTBENR);
+
+	u32 __iomem *pctbenr = IOMEM(LSCH3_PCTBENR_OFFSET);
+
+	/* Enable timebase for all clusters.
+	 * It is safe to do so even some clusters are not enabled.
+	 */
+	out_le32(cltbenr, 0xf);
+
+	/*
+	 * In certain Layerscape SoCs, the clock for each core's
+	 * has an enable bit in the PMU Physical Core Time Base Enable
+	 * Register (PCTBENR), which allows the watchdog to operate.
+	 */
+	setbits_le32(pctbenr, 0xff);
+
+	/* Enable clock for timer
+	 * This is a global setting.
+	 */
+	out_le32(cntcr, 0x1);
+}
+
+void ls1028a_init_lowlevel(void)
+{
+	scfg_init(SCFG_ENDIANESS_LITTLE);
+	set_cntfrq(25000000);
+	ls1028a_timer_init();
+	ls1028a_errata();
+}
diff --git a/arch/arm/mach-layerscape/lowlevel-ls102xa.c b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
new file mode 100644
index 0000000000..440d50282a
--- /dev/null
+++ b/arch/arm/mach-layerscape/lowlevel-ls102xa.c
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Derived from Freescale LSDK-19.09-update-311219
+ */
+#include <common.h>
+#include <io.h>
+#include <clock.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/syscounter.h>
+#include <asm/system.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/lowlevel.h>
+#include <mach/layerscape/fsl_epu.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/fsl_immap.h>
+#include <soc/fsl/scfg.h>
+
+void udelay(unsigned long usecs)
+{
+	arm_architected_timer_udelay(usecs);
+}
+
+void mdelay(unsigned long msecs)
+{
+	udelay(1000 * msecs);
+}
+
+enum csu_cslx_access {
+	CSU_NS_SUP_R = 0x08,
+	CSU_NS_SUP_W = 0x80,
+	CSU_NS_SUP_RW = 0x88,
+	CSU_NS_USER_R = 0x04,
+	CSU_NS_USER_W = 0x40,
+	CSU_NS_USER_RW = 0x44,
+	CSU_S_SUP_R = 0x02,
+	CSU_S_SUP_W = 0x20,
+	CSU_S_SUP_RW = 0x22,
+	CSU_S_USER_R = 0x01,
+	CSU_S_USER_W = 0x10,
+	CSU_S_USER_RW = 0x11,
+	CSU_ALL_RW = 0xff,
+};
+
+struct csu_ns_dev {
+	unsigned long ind;
+	uint32_t val;
+};
+
+enum csu_cslx_ind {
+	CSU_CSLX_PCIE2_IO = 0,
+	CSU_CSLX_PCIE1_IO,
+	CSU_CSLX_MG2TPR_IP,
+	CSU_CSLX_IFC_MEM,
+	CSU_CSLX_OCRAM,
+	CSU_CSLX_GIC,
+	CSU_CSLX_PCIE1,
+	CSU_CSLX_OCRAM2,
+	CSU_CSLX_QSPI_MEM,
+	CSU_CSLX_PCIE2,
+	CSU_CSLX_SATA,
+	CSU_CSLX_USB3,
+	CSU_CSLX_SERDES = 32,
+	CSU_CSLX_QDMA,
+	CSU_CSLX_LPUART2,
+	CSU_CSLX_LPUART1,
+	CSU_CSLX_LPUART4,
+	CSU_CSLX_LPUART3,
+	CSU_CSLX_LPUART6,
+	CSU_CSLX_LPUART5,
+	CSU_CSLX_DSPI2 = 40,
+	CSU_CSLX_DSPI1,
+	CSU_CSLX_QSPI,
+	CSU_CSLX_ESDHC,
+	CSU_CSLX_2D_ACE,
+	CSU_CSLX_IFC,
+	CSU_CSLX_I2C1,
+	CSU_CSLX_USB2,
+	CSU_CSLX_I2C3,
+	CSU_CSLX_I2C2,
+	CSU_CSLX_DUART2 = 50,
+	CSU_CSLX_DUART1,
+	CSU_CSLX_WDT2,
+	CSU_CSLX_WDT1,
+	CSU_CSLX_EDMA,
+	CSU_CSLX_SYS_CNT,
+	CSU_CSLX_DMA_MUX2,
+	CSU_CSLX_DMA_MUX1,
+	CSU_CSLX_DDR,
+	CSU_CSLX_QUICC,
+	CSU_CSLX_DCFG_CCU_RCPM = 60,
+	CSU_CSLX_SECURE_BOOTROM,
+	CSU_CSLX_SFP,
+	CSU_CSLX_TMU,
+	CSU_CSLX_SECURE_MONITOR,
+	CSU_CSLX_RESERVED0,
+	CSU_CSLX_ETSEC1,
+	CSU_CSLX_SEC5_5,
+	CSU_CSLX_ETSEC3,
+	CSU_CSLX_ETSEC2,
+	CSU_CSLX_GPIO2 = 70,
+	CSU_CSLX_GPIO1,
+	CSU_CSLX_GPIO4,
+	CSU_CSLX_GPIO3,
+	CSU_CSLX_PLATFORM_CONT,
+	CSU_CSLX_CSU,
+	CSU_CSLX_ASRC,
+	CSU_CSLX_SPDIF,
+	CSU_CSLX_FLEXCAN2,
+	CSU_CSLX_FLEXCAN1,
+	CSU_CSLX_FLEXCAN4 = 80,
+	CSU_CSLX_FLEXCAN3,
+	CSU_CSLX_SAI2,
+	CSU_CSLX_SAI1,
+	CSU_CSLX_SAI4,
+	CSU_CSLX_SAI3,
+	CSU_CSLX_FTM2,
+	CSU_CSLX_FTM1,
+	CSU_CSLX_FTM4,
+	CSU_CSLX_FTM3,
+	CSU_CSLX_FTM6 = 90,
+	CSU_CSLX_FTM5,
+	CSU_CSLX_FTM8,
+	CSU_CSLX_FTM7,
+	CSU_CSLX_EPU,
+	CSU_CSLX_COP_DCSR,
+	CSU_CSLX_DDI,
+	CSU_CSLX_GDI,
+	CSU_CSLX_RESERVED1,
+	CSU_CSLX_USB3_PHY = 116,
+	CSU_CSLX_RESERVED2,
+	CSU_CSLX_MAX,
+};
+
+static struct csu_ns_dev ns_dev[] = {
+	{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+	{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+	{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+	{ CSU_CSLX_OCRAM, CSU_ALL_RW },
+	{ CSU_CSLX_GIC, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE1, CSU_ALL_RW },
+	{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
+	{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+	{ CSU_CSLX_PCIE2, CSU_ALL_RW },
+	{ CSU_CSLX_SATA, CSU_ALL_RW },
+	{ CSU_CSLX_USB3, CSU_ALL_RW },
+	{ CSU_CSLX_SERDES, CSU_ALL_RW },
+	{ CSU_CSLX_QDMA, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART2, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART1, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART4, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART3, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART6, CSU_ALL_RW },
+	{ CSU_CSLX_LPUART5, CSU_ALL_RW },
+	{ CSU_CSLX_DSPI2, CSU_ALL_RW },
+	{ CSU_CSLX_DSPI1, CSU_ALL_RW },
+	{ CSU_CSLX_QSPI, CSU_ALL_RW },
+	{ CSU_CSLX_ESDHC, CSU_ALL_RW },
+	{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
+	{ CSU_CSLX_IFC, CSU_ALL_RW },
+	{ CSU_CSLX_I2C1, CSU_ALL_RW },
+	{ CSU_CSLX_USB2, CSU_ALL_RW },
+	{ CSU_CSLX_I2C3, CSU_ALL_RW },
+	{ CSU_CSLX_I2C2, CSU_ALL_RW },
+	{ CSU_CSLX_DUART2, CSU_ALL_RW },
+	{ CSU_CSLX_DUART1, CSU_ALL_RW },
+	{ CSU_CSLX_WDT2, CSU_ALL_RW },
+	{ CSU_CSLX_WDT1, CSU_ALL_RW },
+	{ CSU_CSLX_EDMA, CSU_ALL_RW },
+	{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+	{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+	{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+	{ CSU_CSLX_DDR, CSU_ALL_RW },
+	{ CSU_CSLX_QUICC, CSU_ALL_RW },
+	{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+	{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+	{ CSU_CSLX_SFP, CSU_ALL_RW },
+	{ CSU_CSLX_TMU, CSU_ALL_RW },
+	{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
+	{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
+	{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO2, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO1, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO4, CSU_ALL_RW },
+	{ CSU_CSLX_GPIO3, CSU_ALL_RW },
+	{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+	{ CSU_CSLX_CSU, CSU_ALL_RW },
+	{ CSU_CSLX_ASRC, CSU_ALL_RW },
+	{ CSU_CSLX_SPDIF, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+	{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+	{ CSU_CSLX_SAI2, CSU_ALL_RW },
+	{ CSU_CSLX_SAI1, CSU_ALL_RW },
+	{ CSU_CSLX_SAI4, CSU_ALL_RW },
+	{ CSU_CSLX_SAI3, CSU_ALL_RW },
+	{ CSU_CSLX_FTM2, CSU_ALL_RW },
+	{ CSU_CSLX_FTM1, CSU_ALL_RW },
+	{ CSU_CSLX_FTM4, CSU_ALL_RW },
+	{ CSU_CSLX_FTM3, CSU_ALL_RW },
+	{ CSU_CSLX_FTM6, CSU_ALL_RW },
+	{ CSU_CSLX_FTM5, CSU_ALL_RW },
+	{ CSU_CSLX_FTM8, CSU_ALL_RW },
+	{ CSU_CSLX_FTM7, CSU_ALL_RW },
+	{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+	{ CSU_CSLX_EPU, CSU_ALL_RW },
+	{ CSU_CSLX_GDI, CSU_ALL_RW },
+	{ CSU_CSLX_DDI, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
+	{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+	{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+
+/* Found in U-boot but not in LS1021ARM.pdf 02/2020 */
+#define DCSR_RCPM2_ADDR	0x20223000
+#define DCSR_RCPM2_CPMFSMCR0	0x400
+#define DCSR_RCPM2_CPMFSMSR0	0x404
+#define DCSR_RCPM2_CPMFSMCR1	0x414
+#define DCSR_RCPM2_CPMFSMSR1	0x418
+#define CPMFSMSR_FSM_STATE_MASK	0x7f
+
+#define DCSR_EPU_ADDR	0x20000000
+
+static void set_devices_ns_access(unsigned long index, u16 val)
+{
+	u32 *base = IOMEM(LSCH2_CSU_ADDR);
+	u32 *reg;
+	uint32_t tmp;
+
+	reg = base + index / 2;
+	tmp = in_be32(reg);
+	if (index % 2 == 0) {
+		tmp &= 0x0000ffff;
+		tmp |= val << 16;
+	} else {
+		tmp &= 0xffff0000;
+		tmp |= val;
+	}
+
+	out_be32(reg, tmp);
+}
+
+static void init_csu(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ns_dev); i++)
+		set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
+}
+
+/**
+ * fsl_epu_clean - Clear EPU registers
+ */
+static void fsl_epu_clean(void *epu_base)
+{
+	u32 offset;
+
+	/* follow the exact sequence to clear the registers */
+	/* Clear EPACRn */
+	for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+		out_be32(epu_base + offset, 0);
+
+	/* Clear EPEVTCRn */
+	for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+		out_be32(epu_base + offset, 0);
+
+	/* Clear EPGCR */
+	out_be32(epu_base + EPGCR, 0);
+
+	/* Clear EPSMCRn */
+	for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+		out_be32(epu_base + offset, 0);
+
+	/* Clear EPCCRn */
+	for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+		out_be32(epu_base + offset, 0);
+
+	/* Clear EPCMPRn */
+	for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+		out_be32(epu_base + offset, 0);
+
+	/* Clear EPCTRn */
+	for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+		out_be32(epu_base + offset, 0);
+
+	/* Clear EPIMCRn */
+	for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+		out_be32(epu_base + offset, 0);
+
+	/* Clear EPXTRIGCRn */
+	out_be32(epu_base + EPXTRIGCR, 0);
+
+	/* Clear EPECRn */
+	for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+		out_be32(epu_base + offset, 0);
+}
+
+#define TIMER_COMP_VAL			0xffffffffffffffffull
+#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
+#define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
+#define SCFG_QSPI_CLKSEL		0x50100000
+
+/* ls102xa_init_lowlevel
+ * Based on ls1046 and U-boot ls102xa arch_cpu_init
+ */
+void ls102xa_init_lowlevel(void)
+{
+	struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR);
+	struct ls102xa_ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR);
+	struct ls102xa_ccsr_gur __iomem *gur = IOMEM(LSCH2_GUTS_ADDR);
+	void *rcpm2_base = IOMEM(DCSR_RCPM2_ADDR);
+	void *epu_base = IOMEM(DCSR_EPU_ADDR);
+	uint32_t state, major, ctrl, freq;
+	uint64_t val;
+
+	cortex_a7_lowlevel_init();
+	arm_cpu_lowlevel_init();
+
+	scfg_init(SCFG_ENDIANESS_BIG);
+	init_csu();
+
+	writel(SYS_COUNTER_CTRL_ENABLE, LSCH2_SYS_COUNTER_ADDR);
+	freq = 12500000;
+	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+	/* Set PL1 Physical Timer Ctrl */
+	ctrl = ARCH_TIMER_CTRL_ENABLE;
+	asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
+
+	/* Set PL1 Physical Comp Value */
+	val = TIMER_COMP_VAL;
+	asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
+
+
+	state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
+		CPMFSMSR_FSM_STATE_MASK;
+	if (state != 0) {
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
+	}
+	state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
+		CPMFSMSR_FSM_STATE_MASK;
+	if (state != 0) {
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
+	}
+
+	fsl_epu_clean(epu_base);
+
+	/* Enable all the snoop signal for various masters */
+	out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
+				SCFG_SNPCNFGCR_DBG_RD_WR |
+				SCFG_SNPCNFGCR_EDMA_SNP);
+
+	if (IS_ENABLED(CONFIG_DRIVER_SPI_FSL_QUADSPI))
+		out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+
+	/* Configure Little endian for SAI, ASRC and SPDIF */
+	out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
+
+	/*
+	 * Enable snoop requests and DVM message requests for
+	 * All the slave interfaces.
+	 */
+	out_le32(&cci->slave[0].snoop_ctrl,
+		CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[1].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[2].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[4].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+	major = in_be32(&gur->svr);
+	if (SVR_MAJ(major) == SOC_MAJOR_VER_1_0) {
+		/*
+		 * Set CCI-400 Slave interface S1, S2 Shareable Override
+		 * Register All transactions are treated as non-shareable
+		 */
+		out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+		out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	}
+
+	/*
+	 * Memory controller require a register write before being enabled.
+	 * Affects: DDR
+	 * Register: EDDRTQCFG
+	 * Description: Memory controller performance is not optimal with
+	 *		default internal target queue register values.
+	 * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
+	 */
+	out_be32(&scfg->eddrtqcfg, 0x63b20042);
+
+	ls1021a_errata();
+}
diff --git a/arch/arm/mach-layerscape/lowlevel-ls1046a.c b/arch/arm/mach-layerscape/lowlevel-ls1046a.c
index 32f825ec25..1307c05eaf 100644
--- a/arch/arm/mach-layerscape/lowlevel-ls1046a.c
+++ b/arch/arm/mach-layerscape/lowlevel-ls1046a.c
@@ -3,10 +3,11 @@
 #include <io.h>
 #include <asm/syscounter.h>
 #include <asm/system.h>
-#include <mach/errata.h>
-#include <mach/lowlevel.h>
+#include <mach/layerscape/errata.h>
+#include <mach/layerscape/lowlevel.h>
 #include <soc/fsl/immap_lsch2.h>
 #include <soc/fsl/fsl_immap.h>
+#include <soc/fsl/scfg.h>
 
 enum csu_cslx_access {
 	CSU_NS_SUP_R = 0x08,
@@ -222,16 +223,19 @@ void ls1046a_init_lowlevel(void)
 	struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR);
 	struct ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR);
 
+	scfg_init(SCFG_ENDIANESS_BIG);
 	init_csu();
 	ls1046a_init_l2_latency();
 	set_cntfrq(25000000);
 	syscnt_enable(IOMEM(LSCH2_SYS_COUNTER_ADDR));
 
-	/* Make SEC reads and writes snoopable */
+	/* Make DMA master reads and writes snoopable */
 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-		SCFG_SNPCNFGCR_SECWRSNP |
-		SCFG_SNPCNFGCR_SATARDSNP |
-		SCFG_SNPCNFGCR_SATAWRSNP);
+		SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+		SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+		SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+		SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+		SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP);
 
 	/*
 	 * Enable snoop requests and DVM message requests for
diff --git a/arch/arm/mach-layerscape/lowlevel.S b/arch/arm/mach-layerscape/lowlevel.S
index adb3e54367..e8e6410c52 100644
--- a/arch/arm/mach-layerscape/lowlevel.S
+++ b/arch/arm/mach-layerscape/lowlevel.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 
 .section .text.ls1046a_init_l2_latency
diff --git a/arch/arm/mach-layerscape/ls102xa_stream_id.c b/arch/arm/mach-layerscape/ls102xa_stream_id.c
new file mode 100644
index 0000000000..fd9be35c1d
--- /dev/null
+++ b/arch/arm/mach-layerscape/ls102xa_stream_id.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <mach/layerscape/layerscape.h>
+
+struct smmu_stream_id {
+	uint16_t offset;
+	uint16_t stream_id;
+	char dev_name[32];
+};
+
+static struct smmu_stream_id dev_stream_id[] = {
+	{ 0x100, 0x01, "ETSEC MAC1" },
+	{ 0x104, 0x02, "ETSEC MAC2" },
+	{ 0x108, 0x03, "ETSEC MAC3" },
+	{ 0x10c, 0x04, "PEX1" },
+	{ 0x110, 0x05, "PEX2" },
+	{ 0x114, 0x06, "qDMA" },
+	{ 0x118, 0x07, "SATA" },
+	{ 0x11c, 0x08, "USB3" },
+	{ 0x120, 0x09, "QE" },
+	{ 0x124, 0x0a, "eSDHC" },
+	{ 0x128, 0x0b, "eMA" },
+	{ 0x14c, 0x0c, "2D-ACE" },
+	{ 0x150, 0x0d, "USB2" },
+	{ 0x18c, 0x0e, "DEBUG" },
+};
+
+static void
+ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
+{
+	void *scfg = (void *)LSCH2_SCFG_ADDR;
+	int i;
+	u32 icid;
+
+	for (i = 0; i < num; i++) {
+		icid = (id[i].stream_id & 0xff) << 24;
+		out_be32((u32 *)(scfg + id[i].offset), icid);
+	}
+}
+
+void ls102xa_smmu_stream_id_init(void)
+{
+	ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id));
+}
diff --git a/arch/arm/mach-layerscape/pblimage.c b/arch/arm/mach-layerscape/pblimage.c
index deaf7143b9..5a525f0933 100644
--- a/arch/arm/mach-layerscape/pblimage.c
+++ b/arch/arm/mach-layerscape/pblimage.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define pr_fmt(fmt) "pblimage: " fmt
 
 #include <bootm.h>
@@ -5,6 +7,7 @@
 #include <init.h>
 #include <memory.h>
 #include <linux/sizes.h>
+#include <mach/layerscape/layerscape.h>
 
 #define BAREBOX_STAGE2_OFFSET	SZ_128K
 
@@ -48,11 +51,8 @@ static struct image_handler image_handler_layerscape_qspi_pbl_image = {
 	.filetype = filetype_layerscape_qspi_image,
 };
 
-static int layerscape_register_pbl_image_handler(void)
+void layerscape_register_pbl_image_handler(void)
 {
 	register_image_handler(&image_handler_layerscape_pbl_image);
 	register_image_handler(&image_handler_layerscape_qspi_pbl_image);
-
-	return 0;
 }
-late_initcall(layerscape_register_pbl_image_handler);
diff --git a/arch/arm/mach-layerscape/ppa-entry.S b/arch/arm/mach-layerscape/ppa-entry.S
index 18cfa6c37e..f5f30b6719 100644
--- a/arch/arm/mach-layerscape/ppa-entry.S
+++ b/arch/arm/mach-layerscape/ppa-entry.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <linux/linkage.h>
 
 .section .text.ppa_entry
diff --git a/arch/arm/mach-layerscape/ppa.c b/arch/arm/mach-layerscape/ppa.c
index d962fba751..21efaae3ab 100644
--- a/arch/arm/mach-layerscape/ppa.c
+++ b/arch/arm/mach-layerscape/ppa.c
@@ -4,6 +4,7 @@
 
 #include <common.h>
 #include <init.h>
+#include <mmu.h>
 #include <firmware.h>
 #include <memory.h>
 #include <linux/sizes.h>
@@ -13,7 +14,7 @@
 #include <asm/system.h>
 #include <image-fit.h>
 #include <asm/psci.h>
-#include <mach/layerscape.h>
+#include <mach/layerscape/layerscape.h>
 #include <asm/cache.h>
 
 int ppa_entry(const void *, u32 *, u32 *);
@@ -46,7 +47,7 @@ static int of_psci_do_fixup(struct device_node *root, void *unused)
 		break;
 	}
 
-	return of_psci_fixup(root, psci_version);
+	return of_psci_fixup(root, psci_version, "smc");
 }
 
 static int ppa_init(void *ppa, size_t ppa_size, void *sec_firmware_addr)
@@ -54,17 +55,11 @@ static int ppa_init(void *ppa, size_t ppa_size, void *sec_firmware_addr)
 	int ret;
 	u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
 	struct ccsr_scfg __iomem *scfg = (void *)(LSCH2_SCFG_ADDR);
-	int el = current_el();
 	struct fit_handle *fit;
 	void *conf;
 	const void *buf;
 	unsigned long firmware_size;
 
-	if (el < 3) {
-		printf("EL%d, skip ppa init\n", el);
-		return 0;
-	}
-
 	boot_loc_ptr_l = &scfg->scratchrw[1];
 	boot_loc_ptr_h = &scfg->scratchrw[0];
 
@@ -115,9 +110,10 @@ int ls1046a_ppa_init(resource_size_t ppa_start, resource_size_t ppa_size)
 	struct resource *res;
 	void *ppa_fw;
 	size_t ppa_fw_size;
+	int el = current_el();
 	int ret;
 
-	res = request_sdram_region("ppa", ppa_start, ppa_size);
+	res = reserve_sdram_region("ppa", ppa_start, ppa_size);
 	if (!res) {
 		pr_err("Cannot request SDRAM region %pa - %pa\n",
 		       &ppa_start, &ppa_end);
@@ -126,11 +122,22 @@ int ls1046a_ppa_init(resource_size_t ppa_start, resource_size_t ppa_size)
 
 	get_builtin_firmware(ppa_ls1046a_bin, &ppa_fw, &ppa_fw_size);
 
-	ret = ppa_init(ppa_fw, ppa_fw_size, (void *)ppa_start);
-	if (ret)
-		return ret;
+	if (el == 3) {
+		unsigned long cr;
+
+		asm volatile("mrs %0, sctlr_el3" : "=r" (cr) : : "cc");
+		remap_range((void *)ppa_start, ppa_size, MAP_CACHED);
+
+		ret = ppa_init(ppa_fw, ppa_fw_size, (void *)ppa_start);
+
+		asm volatile("msr sctlr_el2, %0" : : "r" (cr) : "cc");
+		remap_range((void *)ppa_start, ppa_size, MAP_UNCACHED);
+
+		if (ret)
+			return ret;
+	}
 
-	of_add_reserve_entry(ppa_start, ppa_end);
+	of_register_fixup(of_fixup_reserved_memory, res);
 
 	return 0;
 }
diff --git a/arch/arm/mach-layerscape/restart.c b/arch/arm/mach-layerscape/restart.c
new file mode 100644
index 0000000000..138a82bdb5
--- /dev/null
+++ b/arch/arm/mach-layerscape/restart.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <common.h>
+#include <init.h>
+#include <restart.h>
+#include <asm/io.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <soc/fsl/fsl_immap.h>
+#include <mach/layerscape/layerscape.h>
+
+static void ls102xa_restart(struct restart_handler *rst)
+{
+	void __iomem *rcr = IOMEM(LSCH2_RST_ADDR);
+
+	/* Set RESET_REQ bit */
+	setbits_be32(rcr, 0x2);
+
+	mdelay(100);
+
+	hang();
+}
+
+void ls1021a_restart_register_feature(void)
+{
+	restart_handler_register_fn("soc-reset", ls102xa_restart);
+}
diff --git a/arch/arm/mach-layerscape/soc.c b/arch/arm/mach-layerscape/soc.c
new file mode 100644
index 0000000000..1742ff58ce
--- /dev/null
+++ b/arch/arm/mach-layerscape/soc.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <soc/fsl/scfg.h>
+#include <io.h>
+#include <init.h>
+#include <memory.h>
+#include <linux/bug.h>
+#include <linux/bitfield.h>
+#include <linux/printk.h>
+#include <mach/layerscape/layerscape.h>
+#include <of.h>
+#include <of_address.h>
+
+int __layerscape_soc_type;
+
+static enum scfg_endianess scfg_endianess = SCFG_ENDIANESS_INVALID;
+
+static void scfg_check_endianess(void)
+{
+	BUG_ON(scfg_endianess == SCFG_ENDIANESS_INVALID);
+}
+
+void scfg_clrsetbits32(void __iomem *addr, u32 clear, u32 set)
+{
+	scfg_check_endianess();
+
+	if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+		clrsetbits_le32(addr, clear, set);
+	else
+		clrsetbits_be32(addr, clear, set);
+}
+
+void scfg_clrbits32(void __iomem *addr, u32 clear)
+{
+	scfg_check_endianess();
+
+	if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+		clrbits_le32(addr, clear);
+	else
+		clrbits_be32(addr, clear);
+}
+
+void scfg_setbits32(void __iomem *addr, u32 set)
+{
+	scfg_check_endianess();
+
+	if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+		setbits_le32(addr, set);
+	else
+		setbits_be32(addr, set);
+}
+
+void scfg_out16(void __iomem *addr, u16 val)
+{
+	scfg_check_endianess();
+
+	if (scfg_endianess == SCFG_ENDIANESS_LITTLE)
+		out_le16(addr, val);
+	else
+		out_be16(addr, val);
+}
+
+void scfg_init(enum scfg_endianess endianess)
+{
+	scfg_endianess = endianess;
+}
+
+static int layerscape_soc_from_dt(void)
+{
+	if (of_machine_is_compatible("fsl,ls1021a"))
+		return LAYERSCAPE_SOC_LS1021A;
+	if (of_machine_is_compatible("fsl,ls1028a"))
+		return LAYERSCAPE_SOC_LS1028A;
+	if (of_machine_is_compatible("fsl,ls1046a"))
+		return LAYERSCAPE_SOC_LS1046A;
+
+	return 0;
+}
+
+static int ls1021a_init(void)
+{
+	if (!cpu_is_ls1021a())
+		return -EINVAL;
+
+	ls1021a_bootsource_init();
+	ls102xa_smmu_stream_id_init();
+	layerscape_register_pbl_image_handler();
+	ls1021a_restart_register_feature();
+
+	return 0;
+}
+
+static int ls1028a_init(void)
+{
+	if (!cpu_is_ls1028a())
+		return -EINVAL;
+
+	ls1028a_bootsource_init();
+	layerscape_register_pbl_image_handler();
+	ls1028a_setup_icids();
+
+	return 0;
+}
+
+static int ls1028a_reserve_tfa(void)
+{
+	resource_size_t tfa_start = LS1028A_TFA_RESERVED_START;
+	resource_size_t tfa_size = LS1028A_TFA_RESERVED_SIZE;
+	struct resource *res;
+
+	if (!cpu_is_ls1028a())
+		return 0;
+
+	res = reserve_sdram_region("tfa", tfa_start, tfa_size);
+	if (!res) {
+		pr_err("Cannot request SDRAM region %pa - %pa\n", &tfa_start, &tfa_size);
+                return -EINVAL;
+	}
+
+	of_register_fixup(of_fixup_reserved_memory, res);
+
+	return 0;
+}
+mmu_initcall(ls1028a_reserve_tfa);
+
+#define DWC3_GSBUSCFG0				0xc100
+#define DWC3_GSBUSCFG0_CACHETYPE_MASK		GENMASK(31, 16)
+
+static void layerscape_usb_enable_snooping(void)
+{
+	struct device_node *np;
+
+	for_each_compatible_node(np, NULL, "snps,dwc3") {
+		struct resource res;
+
+		if (of_address_to_resource(np, 0, &res))
+			continue;
+
+		/* Set cacheable bit for all of Data read, Descriptor read,
+		 * Data write and Descriptor write. Bufferable and read/write
+		 * allocate bits are not set. This is the recommended configurationr
+		 * in LS1046ARM Rev. 3 34.2.10.2:
+		 * "For master interface DMA access, program the GSBUSCFG0
+		 * register to 0x2222000F for better performance.".
+		 * The 0x000F is configured via snps,incr-burst-type-adjustment
+		 * (which despite the name is Layerscape-specific), so below
+		 * line only manipulates the upper 16 bits.
+		 */
+		clrsetbits_le32(IOMEM(res.start) + DWC3_GSBUSCFG0,
+				DWC3_GSBUSCFG0_CACHETYPE_MASK,
+				FIELD_PREP(DWC3_GSBUSCFG0_CACHETYPE_MASK, 0x2222));
+	}
+}
+
+static int ls1046a_init(void)
+{
+	if (!cpu_is_ls1046a())
+		return -EINVAL;
+
+	ls1046a_bootsource_init();
+	ls1046a_setup_icids();
+	layerscape_register_pbl_image_handler();
+	layerscape_usb_enable_snooping();
+
+	return 0;
+}
+
+static int layerscape_init(void)
+{
+	struct device_node *root;
+
+	root = of_get_root_node();
+	if (root) {
+		__layerscape_soc_type = layerscape_soc_from_dt();
+		if (!__layerscape_soc_type)
+			return 0;
+	}
+
+	switch (__layerscape_soc_type) {
+	case LAYERSCAPE_SOC_LS1021A:
+		return ls1021a_init();
+	case LAYERSCAPE_SOC_LS1028A:
+		return ls1028a_init();
+	case LAYERSCAPE_SOC_LS1046A:
+		return ls1046a_init();
+	}
+
+	return 0;
+}
+postcore_initcall(layerscape_init);
diff --git a/arch/arm/mach-layerscape/tzc400.c b/arch/arm/mach-layerscape/tzc400.c
new file mode 100644
index 0000000000..04a97809f5
--- /dev/null
+++ b/arch/arm/mach-layerscape/tzc400.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ *
+ */
+#define pr_fmt(fmt) "tzc400: " fmt
+
+#include <common.h>
+#include <linux/bitfield.h>
+#include <linux/sizes.h>
+#include <mach/layerscape/lowlevel.h>
+#include <mach/layerscape/layerscape.h>
+
+#include "tzc400.h"
+
+static inline void mmio_write_32(uintptr_t addr, uint32_t value)
+{
+	out_le32(addr, value);
+}
+
+static inline uint32_t mmio_read_32(uintptr_t addr)
+{
+	return in_le32(addr);
+}
+
+static inline void mmio_clrsetbits_32(uintptr_t addr,
+                                uint32_t clear,
+                                uint32_t set)
+{
+	clrsetbits_le32(addr, clear, set);
+}
+
+static inline unsigned int tzc_read_peripheral_id(uintptr_t base)
+{
+	unsigned int id;
+
+	id = mmio_read_32(base + PID0_OFF);
+	/* Masks DESC part in PID1 */
+	id |= ((mmio_read_32(base + PID1_OFF) & 0xFU) << 8U);
+
+	return id;
+}
+
+/*
+ * Implementation defined values used to validate inputs later.
+ * Filters : max of 4 ; 0 to 3
+ * Regions : max of 9 ; 0 to 8
+ * Address width : Values between 32 to 64
+ */
+struct tzc400_instance {
+	uintptr_t base;
+	uint8_t addr_width;
+	uint8_t num_filters;
+	uint8_t num_regions;
+};
+
+static struct tzc400_instance tzc400;
+
+static inline unsigned int tzc400_read_gate_keeper(void)
+{
+	uintptr_t base = tzc400.base;
+
+	return mmio_read_32(base + TZC400_GATE_KEEPER);
+}
+
+static inline void tzc400_write_gate_keeper(unsigned int val)
+{
+	uintptr_t base = tzc400.base;
+
+	mmio_write_32(base + TZC400_GATE_KEEPER, val);
+}
+
+static unsigned int tzc400_open_status(void)
+{
+	return FIELD_GET(TZC400_GATE_KEEPER_OS, tzc400_read_gate_keeper());
+}
+
+static unsigned int tzc400_get_gate_keeper(unsigned int filter)
+{
+	return (tzc400_open_status() >> filter) & GATE_KEEPER_FILTER_MASK;
+}
+
+/* This function is not MP safe. */
+static void tzc400_set_gate_keeper(unsigned int filter, int val)
+{
+	unsigned int os;
+
+	/* Upper half is current state. Lower half is requested state. */
+	os = tzc400_open_status();
+
+	if (val != 0)
+		os |=  (1UL << filter);
+	else
+		os &= ~(1UL << filter);
+
+	tzc400_write_gate_keeper(FIELD_PREP(TZC400_GATE_KEEPER_OR, os));
+
+	/* Wait here until we see the change reflected in the TZC status. */
+	while ((tzc400_open_status()) != os)
+		;
+}
+
+void tzc400_set_action(unsigned int action)
+{
+	uintptr_t base = tzc400.base;
+
+	ASSERT(base != 0U);
+	ASSERT(action <= TZC_ACTION_ERR_INT);
+
+	mmio_write_32(base + TZC400_ACTION, action);
+}
+
+void tzc400_init(uintptr_t base)
+{
+	unsigned int tzc400_id;
+	unsigned int tzc400_build;
+
+	tzc400.base = base;
+
+	tzc400_id = tzc_read_peripheral_id(base);
+	if (tzc400_id != TZC400_PERIPHERAL_ID)
+		panic("TZC-400 : Wrong device ID (0x%x).\n", tzc400_id);
+
+	/* Save values we will use later. */
+	tzc400_build = mmio_read_32(base + TZC400_BUILD_CONFIG);
+	tzc400.num_filters = FIELD_GET(TZC400_BUILD_CONFIG_NF, tzc400_build) + 1;
+	tzc400.addr_width  = FIELD_GET(TZC400_BUILD_CONFIG_AW, tzc400_build) + 1;
+	tzc400.num_regions = FIELD_GET(TZC400_BUILD_CONFIG_NR, tzc400_build) + 1;
+}
+
+/*
+ * `tzc400_configure_region` is used to program regions into the TrustZone
+ * controller. A region can be associated with more than one filter. The
+ * associated filters are passed in as a bitmap (bit0 = filter0), except that
+ * the value TZC400_REGION_ATTR_FILTER_BIT_ALL selects all filters, based on
+ * the value of tzc400.num_filters.
+ * NOTE:
+ * Region 0 is special; it is preferable to use tzc400_configure_region0
+ * for this region (see comment for that function).
+ */
+void tzc400_configure_region(unsigned int filters, unsigned int region, uint64_t region_base,
+			     uint64_t region_top, unsigned int sec_attr,
+			     unsigned int nsaid_permissions)
+{
+	uintptr_t rbase = tzc400.base + TZC_REGION_OFFSET(TZC400_REGION_SIZE, region);
+
+	/* Adjust filter mask by real filter number */
+	if (filters == TZC400_REGION_ATTR_FILTER_BIT_ALL)
+		filters = (1U << tzc400.num_filters) - 1U;
+
+	/* Do range checks on filters and regions. */
+	ASSERT(((filters >> tzc400.num_filters) == 0U) &&
+	       (region < tzc400.num_regions));
+
+	/*
+	 * Do address range check based on TZC configuration. A 64bit address is
+	 * the max and expected case.
+	 */
+	ASSERT((region_top <= (U64_MAX >> (64U - tzc400.addr_width))) &&
+		(region_base < region_top));
+
+	/* region_base and (region_top + 1) must be 4KB aligned */
+	ASSERT(((region_base | (region_top + 1U)) & (4096U - 1U)) == 0U);
+
+	ASSERT(sec_attr <= TZC_REGION_S_RDWR);
+
+	pr_debug("TrustZone : Configuring region %u\n", region);
+	pr_debug("TrustZone : ... base = %llx, top = %llx,\n", region_base, region_top);
+	pr_debug("TrustZone : ... sec_attr = 0x%x, ns_devs = 0x%x)\n",
+		sec_attr, nsaid_permissions);
+
+	/***************************************************/
+	/* Inputs look ok, start programming registers.    */
+	/* All the address registers are 32 bits wide and  */
+	/* have a LOW and HIGH				   */
+	/* component used to construct an address up to a  */
+	/* 64bit.					   */
+	/***************************************************/
+	mmio_write_32(rbase + TZC400_REGION_BASE_LOW_0, (uint32_t)region_base);
+	mmio_write_32(rbase + TZC400_REGION_BASE_HIGH_0, (uint32_t)(region_base >> 32));
+	mmio_write_32(rbase + TZC400_REGION_TOP_LOW_0, (uint32_t)region_top);
+	mmio_write_32(rbase + TZC400_REGION_TOP_HIGH_0, (uint32_t)(region_top >> 32));
+
+	/* Enable filter to the region and set secure attributes */
+	mmio_write_32(rbase + TZC400_REGION_ATTR_0,
+		      (sec_attr << TZC_REGION_ATTR_SEC_SHIFT) | (filters << TZC_REGION_ATTR_F_EN_SHIFT));
+
+	/***************************************************/
+	/* Specify which non-secure devices have permission*/
+	/* to access this region.			   */
+	/***************************************************/
+	mmio_write_32(rbase + TZC400_REGION_ID_ACCESS_0, nsaid_permissions);
+}
+
+void tzc400_update_filters(unsigned int region, unsigned int filters)
+{
+	uintptr_t rbase = tzc400.base + TZC_REGION_OFFSET(TZC400_REGION_SIZE, region);
+	uint32_t filters_mask = GENMASK(tzc400.num_filters - 1U, 0);
+
+	/* Do range checks on filters and regions. */
+	ASSERT(((filters >> tzc400.num_filters) == 0U) &&
+	       (region < tzc400.num_regions));
+
+	mmio_clrsetbits_32(rbase + TZC400_REGION_ATTR_0,
+			   filters_mask << TZC_REGION_ATTR_F_EN_SHIFT,
+			   filters << TZC_REGION_ATTR_F_EN_SHIFT);
+}
+
+void tzc400_enable_filters(void)
+{
+	unsigned int state;
+	unsigned int filter;
+
+	ASSERT(tzc400.base != 0U);
+
+	for (filter = 0U; filter < tzc400.num_filters; filter++) {
+		state = tzc400_get_gate_keeper(filter);
+		if (state != 0U) {
+			/* Filter 0 is special and cannot be disabled.
+			 * So here we allow it being already enabled. */
+			if (filter == 0U)
+				continue;
+
+			/*
+			 * The TZC filter is already configured. Changing the
+			 * programmer's view in an active system can cause
+			 * unpredictable behavior therefore panic for now rather
+			 * than try to determine whether this is safe in this
+			 * instance.
+			 *
+			 * See the 'ARM (R) CoreLink TM TZC-400 TrustZone (R)
+			 * Address Space Controller' Technical Reference Manual.
+			 */
+			panic("TZC-400 : Filter %u Gatekeeper already enabled.\n",
+			      filter);
+		}
+		tzc400_set_gate_keeper(filter, 1);
+	}
+}
+
+void tzc400_disable_filters(void)
+{
+	unsigned int filter;
+	unsigned int state;
+	unsigned int start = 0U;
+
+	ASSERT(tzc400.base != 0U);
+
+	/* Filter 0 is special and cannot be disabled. */
+	state = tzc400_get_gate_keeper(0);
+	if (state != 0U)
+		start++;
+
+	for (filter = start; filter < tzc400.num_filters; filter++)
+		tzc400_set_gate_keeper(filter, 0);
+}
+
+unsigned long ls1028a_tzc400_init(unsigned long memsize)
+{
+	unsigned long lowmem, highmem, lowmem_end;
+
+	tzc400_init(LS1028A_TZC400_BASE);
+	tzc400_disable_filters();
+
+	/* Region 0 set to no access by default */
+	mmio_write_32(tzc400.base + TZC400_REGION_ATTR_0, TZC_REGION_S_NONE << TZC_REGION_ATTR_SEC_SHIFT);
+	mmio_write_32(tzc400.base + TZC400_REGION_ID_ACCESS_0, 0);
+
+	lowmem = min_t(unsigned long, LS1028A_DDR_SDRAM_LOWMEM_SIZE, memsize);
+	lowmem_end = LS1028A_DDR_SDRAM_BASE + lowmem;
+	highmem = memsize - lowmem;
+
+	/* region 1: secure memory */
+	tzc400_configure_region(1, 1,
+		lowmem_end - LS1028A_SECURE_DRAM_SIZE,
+		lowmem_end - 1,
+		TZC_REGION_S_RDWR, TZC_REGION_NS_NONE);
+
+	/* region 2: shared memory */
+	tzc400_configure_region(1, 2,
+		lowmem_end - LS1028A_SECURE_DRAM_SIZE - LS1028A_SP_SHARED_DRAM_SIZE,
+		lowmem_end - LS1028A_SECURE_DRAM_SIZE - 1,
+		TZC_REGION_S_RDWR, TZC_NS_ACCESS_ID);
+
+	/* region 3: nonsecure low memory */
+	tzc400_configure_region(1, 3,
+		LS1028A_DDR_SDRAM_BASE,
+		lowmem_end - LS1028A_SECURE_DRAM_SIZE - LS1028A_SP_SHARED_DRAM_SIZE - 1,
+		TZC_REGION_S_RDWR, TZC_NS_ACCESS_ID);
+
+	if (highmem)
+		/* nonsecure high memory */
+		tzc400_configure_region(1, 4,
+			LS1028A_DDR_SDRAM_HIGHMEM_BASE,
+			LS1028A_DDR_SDRAM_HIGHMEM_BASE + highmem - 1,
+			TZC_REGION_S_RDWR, TZC_NS_ACCESS_ID);
+
+	tzc400_set_action(TZC_ACTION_ERR);
+
+	tzc400_enable_filters();
+
+	return lowmem - LS1028A_SECURE_DRAM_SIZE - LS1028A_SP_SHARED_DRAM_SIZE;
+}
diff --git a/arch/arm/mach-layerscape/tzc400.h b/arch/arm/mach-layerscape/tzc400.h
new file mode 100644
index 0000000000..c8d4583622
--- /dev/null
+++ b/arch/arm/mach-layerscape/tzc400.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TZC400_H
+#define TZC400_H
+
+#include <linux/bits.h>
+
+/*
+ * Offset of core registers from the start of the base of configuration
+ * registers for each region.
+ */
+
+/* ID Registers */
+#define PID0_OFF					0xfe0
+#define PID1_OFF					0xfe4
+#define PID2_OFF					0xfe8
+#define PID3_OFF					0xfec
+#define PID4_OFF					0xfd0
+#define CID0_OFF					0xff0
+#define CID1_OFF					0xff4
+#define CID2_OFF					0xff8
+#define CID3_OFF					0xffc
+
+/*
+ * What type of action is expected when an access violation occurs.
+ * The memory requested is returned as zero. But we can also raise an event to
+ * let the system know it happened.
+ * We can raise an interrupt(INT) and/or cause an exception(ERR).
+ *  TZC_ACTION_NONE    - No interrupt, no Exception
+ *  TZC_ACTION_ERR     - No interrupt, raise exception -> sync external
+ *                       data abort
+ *  TZC_ACTION_INT     - Raise interrupt, no exception
+ *  TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync
+ *                       external data abort
+ */
+#define TZC_ACTION_NONE			0
+#define TZC_ACTION_ERR			1
+#define TZC_ACTION_INT			2
+#define TZC_ACTION_ERR_INT		(TZC_ACTION_ERR | TZC_ACTION_INT)
+
+/* Bit positions of TZC_ACTION registers */
+#define TZC_ACTION_RV_SHIFT				0
+#define TZC_ACTION_RV_MASK				0x3
+#define TZC_ACTION_RV_LOWOK				0x0
+#define TZC_ACTION_RV_LOWERR				0x1
+#define TZC_ACTION_RV_HIGHOK				0x2
+#define TZC_ACTION_RV_HIGHERR				0x3
+
+/*
+ * Controls secure access to a region. If not enabled secure access is not
+ * allowed to region.
+ */
+#define TZC_REGION_S_NONE		0
+#define TZC_REGION_S_RD			1
+#define TZC_REGION_S_WR			2
+#define TZC_REGION_S_RDWR		(TZC_REGION_S_RD | TZC_REGION_S_WR)
+
+#define TZC_REGION_ATTR_S_RD_SHIFT			30
+#define TZC_REGION_ATTR_S_WR_SHIFT			31
+#define TZC_REGION_ATTR_F_EN_SHIFT			0
+#define TZC_REGION_ATTR_SEC_SHIFT			30
+#define TZC_REGION_ATTR_S_RD_MASK			0x1
+#define TZC_REGION_ATTR_S_WR_MASK			0x1
+#define TZC_REGION_ATTR_SEC_MASK			0x3
+
+#define TZC_REGION_ACCESS_WR_EN_SHIFT			16
+#define TZC_REGION_ACCESS_RD_EN_SHIFT			0
+#define TZC_REGION_ACCESS_ID_MASK			0xf
+
+/* Macros for allowing Non-Secure access to a region based on NSAID */
+#define TZC_REGION_ACCESS_RD(nsaid)				\
+	((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) <<	\
+	 TZC_REGION_ACCESS_RD_EN_SHIFT)
+#define TZC_REGION_ACCESS_WR(nsaid)				\
+	((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) <<	\
+	 TZC_REGION_ACCESS_WR_EN_SHIFT)
+#define TZC_REGION_ACCESS_RDWR(nsaid)				\
+	(TZC_REGION_ACCESS_RD(nsaid) |				\
+	TZC_REGION_ACCESS_WR(nsaid))
+
+/* Returns offset of registers to program for a given region no */
+#define TZC_REGION_OFFSET(region_size, region_no)	\
+				((region_size) * (region_no))
+
+#define TZC400_BUILD_CONFIG			0x000
+#define TZC400_GATE_KEEPER			0x008
+#define TZC400_SPECULATION_CTRL			0x00c
+#define TZC400_INT_STATUS			0x010
+#define TZC400_INT_CLEAR			0x014
+
+#define TZC400_FAIL_ADDRESS_LOW			0x020
+#define TZC400_FAIL_ADDRESS_HIGH		0x024
+#define TZC400_FAIL_CONTROL			0x028
+#define TZC400_FAIL_ID				0x02c
+
+#define TZC400_BUILD_CONFIG_NF			GENMASK(25, 24)
+#define TZC400_BUILD_CONFIG_AW			GENMASK(13, 8)
+#define TZC400_BUILD_CONFIG_NR			GENMASK(4, 0)
+
+/*
+ * Number of gate keepers is implementation defined. But we know the max for
+ * this device is 4. Get implementation details from BUILD_CONFIG.
+ */
+#define TZC400_GATE_KEEPER_OS			GENMASK(19, 16)
+#define TZC400_GATE_KEEPER_OR			GENMASK(3, 0)
+#define GATE_KEEPER_FILTER_MASK			0x1
+
+#define TZC400_FAIL_CONTROL_DIR_WRITE		BIT(24)
+#define TZC400_FAIL_CONTROL_NS_NONSECURE	BIT(21)
+#define TZC400_FAIL_CONTROL_PRIV		BIT(20)
+
+#define TZC400_PERIPHERAL_ID			0x460
+
+/* Filter enable bits in a TZC */
+#define TZC400_REGION_ATTR_F_EN_MASK		0xf
+#define TZC400_REGION_ATTR_FILTER_BIT(x)	(1) << (x))
+#define TZC400_REGION_ATTR_FILTER_BIT_ALL	TZC400_REGION_ATTR_F_EN_MASK
+
+/*
+ * All TZC region configuration registers are placed one after another. It
+ * depicts size of block of registers for programming each region.
+ */
+#define TZC400_REGION_SIZE			0x20
+#define TZC400_ACTION				0x4
+
+#define FILTER_OFFSET				0x10
+
+#define TZC400_REGION_BASE_LOW_0	0x100
+#define TZC400_REGION_BASE_HIGH_0	0x104
+#define TZC400_REGION_TOP_LOW_0	0x108
+#define TZC400_REGION_TOP_HIGH_0	0x10c
+#define TZC400_REGION_ATTR_0		0x110
+#define TZC400_REGION_ID_ACCESS_0	0x114
+
+#define TZC_REGION_NS_NONE			0x00000000U
+
+/*
+ * NXP Platforms do not support NS Access ID (NSAID) based non-secure access.
+ * Supports only non secure through generic NS ACCESS ID
+ */
+#define TZC_NS_ACCESS_ID			0xFFFFFFFFU
+
+/*******************************************************************************
+ * Function & variable prototypes
+ ******************************************************************************/
+void tzc400_init(uintptr_t base);
+void tzc400_configure_region0(unsigned int sec_attr,
+			   unsigned int ns_device_access);
+void tzc400_configure_region(unsigned int filters,
+			  unsigned int region,
+			  unsigned long long region_base,
+			  unsigned long long region_top,
+			  unsigned int sec_attr,
+			  unsigned int nsaid_permissions);
+void tzc400_update_filters(unsigned int region, unsigned int filters);
+void tzc400_set_action(unsigned int action);
+void tzc400_enable_filters(void);
+void tzc400_disable_filters(void);
+
+#endif /* TZC400_H */
diff --git a/arch/arm/mach-layerscape/xload-qspi.c b/arch/arm/mach-layerscape/xload-qspi.c
index 192aea64b4..608434bf1f 100644
--- a/arch/arm/mach-layerscape/xload-qspi.c
+++ b/arch/arm/mach-layerscape/xload-qspi.c
@@ -4,8 +4,8 @@
 #include <soc/fsl/immap_lsch2.h>
 #include <asm-generic/sections.h>
 #include <asm/cache.h>
-#include <mach/xload.h>
-#include <mach/layerscape.h>
+#include <mach/layerscape/xload.h>
+#include <mach/layerscape/layerscape.h>
 
 /*
  * The offset of the 2nd stage image in the output file. This must match with the
@@ -13,18 +13,21 @@
  */
 #define BAREBOX_START	(128 * 1024)
 
-int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
-					     unsigned long r2)
+struct layerscape_base_addr {
+	void *qspi_reg_base;
+	void *membase;
+	void *qspi_mem_base;
+};
+
+static int layerscape_qspi_start_image(struct layerscape_base_addr *base,
+		unsigned long r0, unsigned long r1, unsigned long r2)
 {
-	void *qspi_reg_base = IOMEM(LSCH2_QSPI0_BASE_ADDR);
-	void *membase = (void *)LS1046A_DDR_SDRAM_BASE;
-	void *qspi_mem_base = IOMEM(0x40000000);
-	void (*barebox)(unsigned long, unsigned long, unsigned long) = membase;
+	void (*barebox)(unsigned long, unsigned long, unsigned long) = base->membase;
 
 	/* Switch controller into little endian mode */
-	out_be32(qspi_reg_base, 0x000f400c);
+	out_be32(base->qspi_reg_base, 0x000f400c);
 
-	memcpy(membase, qspi_mem_base + BAREBOX_START, barebox_image_size);
+	memcpy(base->membase, base->qspi_mem_base + BAREBOX_START, barebox_image_size);
 
 	sync_caches_for_execution();
 
@@ -36,3 +39,27 @@ int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
 
 	return -EIO;
 }
+
+int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
+					     unsigned long r2)
+{
+	struct layerscape_base_addr base;
+
+	base.qspi_reg_base = IOMEM(LSCH2_QSPI0_BASE_ADDR);
+	base.membase = IOMEM(LS1046A_DDR_SDRAM_BASE);
+	base.qspi_mem_base = IOMEM(0x40000000);
+
+	return layerscape_qspi_start_image(&base, r0, r1, r2);
+}
+
+int ls1021a_qspi_start_image(unsigned long r0, unsigned long r1,
+					     unsigned long r2)
+{
+	struct layerscape_base_addr base;
+
+	base.qspi_reg_base = IOMEM(LSCH2_QSPI0_BASE_ADDR);
+	base.membase = IOMEM(LS1021A_DDR_SDRAM_BASE);
+	base.qspi_mem_base = IOMEM(0x40000000);
+
+	return layerscape_qspi_start_image(&base, r0, r1, r2);
+}
diff --git a/arch/arm/mach-layerscape/xload.c b/arch/arm/mach-layerscape/xload.c
index 54495d7f97..32ff158b1b 100644
--- a/arch/arm/mach-layerscape/xload.c
+++ b/arch/arm/mach-layerscape/xload.c
@@ -2,21 +2,39 @@
 
 #include <common.h>
 #include <bootsource.h>
-#include <mach/layerscape.h>
-#include <mach/xload.h>
+#include <mach/layerscape/layerscape.h>
+#include <mach/layerscape/xload.h>
 
 int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
 			      unsigned long r2)
 {
 	enum bootsource src;
 
-	src = ls1046_bootsource_get();
+	src = ls1046a_bootsource_get();
 
 	switch (src) {
 	case BOOTSOURCE_SPI_NOR:
 		return ls1046a_qspi_start_image(r0, r1, r2);
+#if defined(CONFIG_MCI_IMX_ESDHC_PBL)
 	case BOOTSOURCE_MMC:
 		return ls1046a_esdhc_start_image(r0, r1, r2);
+#endif
+	default:
+		pr_err("Unknown bootsource\n");
+		return -EINVAL;
+	}
+}
+
+int ls1021a_xload_start_image(unsigned long r0, unsigned long r1,
+			      unsigned long r2)
+{
+	enum bootsource src;
+
+	src = ls1021a_bootsource_get();
+
+	switch (src) {
+	case BOOTSOURCE_SPI_NOR:
+		return ls1021a_qspi_start_image(r0, r1, r2);
 	default:
 		pr_err("Unknown bootsource\n");
 		return -EINVAL;
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index bab22f07ff..1b26148434 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_MVEBU
 
 config ARCH_TEXT_BASE
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 6079403b83..88580cb58f 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-pbl-y			+= common.o
 obj-$(CONFIG_ARCH_ARMADA_370)	+= armada-370-xp.o
 obj-$(CONFIG_ARCH_ARMADA_XP)	+= armada-370-xp.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 9a35c51985..1bbc6bd226 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -1,18 +1,5 @@
-/*
- * Copyright
- * (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 
 #include <common.h>
 #include <init.h>
@@ -22,14 +9,15 @@
 #include <of_address.h>
 #include <asm/memory.h>
 #include <linux/mbus.h>
-#include <mach/armada-370-xp-regs.h>
-#include <mach/socid.h>
+#include <mach/mvebu/armada-370-xp-regs.h>
+#include <mach/mvebu/socid.h>
 
 static const struct of_device_id armada_370_xp_pcie_of_ids[] = {
 	{ .compatible = "marvell,armada-xp-pcie", },
 	{ .compatible = "marvell,armada-370-pcie", },
 	{ },
 };
+MODULE_DEVICE_TABLE(of, armada_370_xp_pcie_of_ids);
 
 /*
  * Marvell Armada XP MV78230-A0 incorrectly identifies itself as
diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
index 5650c1ed87..bca4a3cb1c 100644
--- a/arch/arm/mach-mvebu/common.c
+++ b/arch/arm/mach-mvebu/common.c
@@ -1,19 +1,6 @@
-/*
- * Copyright (C) 2013
- *  Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *  Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+// SPDX-FileCopyrightText: 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 
 #include <common.h>
 #include <init.h>
@@ -21,11 +8,11 @@
 #include <of.h>
 #include <of_address.h>
 #include <linux/clk.h>
-#include <mach/common.h>
-#include <mach/socid.h>
+#include <mach/mvebu/common.h>
+#include <mach/mvebu/socid.h>
 #include <asm/barebox-arm.h>
 #include <asm/memory.h>
-#include <mach/lowlevel.h>
+#include <mach/mvebu/lowlevel.h>
 
 /*
  * The different SoC headers containing register definitions (mach/dove-regs.h,
@@ -70,6 +57,7 @@ static const struct of_device_id mvebu_pcie_of_ids[] = {
 	{ .compatible = "marvell,kirkwood-pcie" },
 	{ },
 };
+MODULE_DEVICE_TABLE(of, mvebu_pcie_of_ids);
 
 static int mvebu_soc_id_init(void)
 {
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 3c6302dd2d..2dd461c5c3 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -1,18 +1,5 @@
-/*
- * Copyright
- * (C) 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 
 #include <common.h>
 #include <init.h>
@@ -20,7 +7,7 @@
 #include <restart.h>
 #include <asm/memory.h>
 #include <linux/mbus.h>
-#include <mach/dove-regs.h>
+#include <mach/mvebu/dove-regs.h>
 
 static void __noreturn dove_restart_soc(struct restart_handler *rst)
 {
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
deleted file mode 100644
index b972df151a..0000000000
--- a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright
- * (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_MVEBU_ARMADA_370_XP_REGS_H
-#define __MACH_MVEBU_ARMADA_370_XP_REGS_H
-
-#include <mach/common.h>
-
-#define ARMADA_370_XP_INT_REGS_BASE	IOMEM(MVEBU_REMAP_INT_REG_BASE)
-#define ARMADA_370_XP_UART_BASE		(ARMADA_370_XP_INT_REGS_BASE + 0x12000)
-#define ARMADA_370_XP_UARTn_BASE(n)	\
-	(ARMADA_370_XP_UART_BASE + ((n) * 0x100))
-
-#define ARMADA_370_XP_SYSCTL_BASE	(ARMADA_370_XP_INT_REGS_BASE + 0x18200)
-#define ARMADA_370_XP_SOC_CTRL		(ARMADA_370_XP_SYSCTL_BASE + 0x004)
-#define  PCIE1_QUADX1_EN		BIT(8)
-#define  PCIE0_QUADX1_EN		BIT(7)
-#define  PCIE3_EN			BIT(3)
-#define  PCIE2_EN			BIT(2)
-#define  PCIE1_EN			BIT(1)
-#define  PCIE0_EN			BIT(0)
-#define ARMADA_370_XP_SAR_LOW		(ARMADA_370_XP_SYSCTL_BASE + 0x030)
-#define  SAR_TCLK_FREQ			BIT(20)
-#define ARMADA_370_XP_SAR_HIGH		(ARMADA_370_XP_SYSCTL_BASE + 0x034)
-#define ARMADA_370_XP_CPU_SOC_ID	(ARMADA_370_XP_SYSCTL_BASE + 0x03c)
-#define  CPU_SOC_ID_DEVICE_MASK		0xffff
-#define ARMADA_XP_PUP_ENABLE		(ARMADA_370_XP_SYSCTL_BASE + 0x44c)
-#define  GE0_PUP_EN			BIT(0)
-#define  GE1_PUP_EN			BIT(1)
-#define  LCD_PUP_EN			BIT(2)
-#define  NAND_PUP_EN			BIT(4)
-#define  SPI_PUP_EN			BIT(5)
-
-#define ARMADA_370_XP_SDRAM_BASE	(ARMADA_370_XP_INT_REGS_BASE + 0x20000)
-#define  DDR_BASE_CS			0x180
-#define  DDR_BASE_CSn(n)		(DDR_BASE_CS + ((n) * 0x8))
-#define  DDR_BASE_CS_HIGH_MASK		0x0000000f
-#define  DDR_BASE_CS_LOW_MASK		0xff000000
-#define  DDR_SIZE_CS			0x184
-#define  DDR_SIZE_CSn(n)		(DDR_SIZE_CS + ((n) * 0x8))
-#define  DDR_SIZE_ENABLED		BIT(0)
-#define  DDR_SIZE_CS_MASK		0x0000001c
-#define  DDR_SIZE_CS_SHIFT		2
-#define  DDR_SIZE_MASK			0xff000000
-
-#define ARMADA_370_XP_FABRIC_BASE	(ARMADA_370_XP_INT_REGS_BASE + 0x20200)
-#define ARMADA_370_XP_FABRIC_CTRL	(ARMADA_370_XP_FABRIC_BASE + 0x000)
-#define  MBUS_ERR_PROP_EN		BIT(8)
-#define ARMADA_370_XP_FABRIC_CONF	(ARMADA_370_XP_FABRIC_BASE + 0x004)
-#define  FABRIC_NUM_CPUS_MASK		0x3
-
-#define ARMADA_370_XP_TIMER_BASE	(ARMADA_370_XP_INT_REGS_BASE + 0x20300)
-
-#define ARMADA_370_XP_PCIE_UNIT_OFFSET	0x40000
-#define ARMADA_370_XP_PCIE_PORT_OFFSET	0x04000
-#define ARMADA_370_XP_PCIE_BASE(port)				\
-	(ARMADA_370_XP_INT_REGS_BASE + 0x40000 +		\
-	 (((port) / 4) * ARMADA_370_XP_PCIE_UNIT_OFFSET) +	\
-	 (((port) % 4) * ARMADA_370_XP_PCIE_PORT_OFFSET))
-#define  PCIE_DEVICE_VENDOR_ID		0x000
-
-#define ARMADA_370_XP_USB_BASE		(ARMADA_370_XP_INT_REGS_BASE + 0x50000)
-
-#endif /* __MACH_MVEBU_ARMADA_370_XP_REGS_H */
diff --git a/arch/arm/mach-mvebu/include/mach/barebox-arm-head.h b/arch/arm/mach-mvebu/include/mach/barebox-arm-head.h
deleted file mode 100644
index 3035f40ddf..0000000000
--- a/arch/arm/mach-mvebu/include/mach/barebox-arm-head.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#include <linux/stringify.h>
-#include <mach/common.h>
-
-static inline void __barebox_arm_head(void)
-{
-	__asm__ __volatile__ (
-#ifdef CONFIG_THUMB2_BAREBOX
-		".arm\n"
-		"adr r9, 1f + 1\n"
-		"bx r9\n"
-		".thumb\n"
-		"1:\n"
-		"bl 2f\n"
-		".rept 10\n"
-		"1: b 1b\n"
-		".endr\n"
-#else
-		"b 2f\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-#endif
-		".asciz \"barebox\"\n"
-		".word _text\n"				/* text base. If copied there,
-							 * barebox can skip relocation
-							 */
-		".word _barebox_image_size\n"		/* image size to copy */
-
-		/*
-		 * The following entry (at offset 0x30) is the only intended
-		 * difference to the original arm __barebox_arm_head. This value
-		 * holds the address of the internal register window when the
-		 * image is started. If the window is not at the reset default
-		 * position any more the caller can pass the actual value here.
-		 */
-		".word " __stringify(MVEBU_BOOTUP_INT_REG_BASE) "\n"
-		".rept 7\n"
-		".word 0x55555555\n"
-		".endr\n"
-		"2:\n"
-	);
-}
-
-static inline void barebox_arm_head(void)
-{
-	__barebox_arm_head();
-	__asm__ __volatile__ (
-		"b barebox_arm_reset_vector\n"
-	);
-}
diff --git a/arch/arm/mach-mvebu/include/mach/bbu.h b/arch/arm/mach-mvebu/include/mach/bbu.h
deleted file mode 100644
index f23c3269c0..0000000000
--- a/arch/arm/mach-mvebu/include/mach/bbu.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifdef CONFIG_BAREBOX_UPDATE
-int mvebu_bbu_flash_register_handler(const char *name,
-				     char *devicefile, int version,
-				     bool isdefault);
-#else
-static inline int mvebu_bbu_flash_register_handler(const char *name,
-                                     char *devicefile, int version,
-                                     bool isdefault)
-{
-	return -ENOSYS;
-}
-#endif
diff --git a/arch/arm/mach-mvebu/include/mach/common.h b/arch/arm/mach-mvebu/include/mach/common.h
deleted file mode 100644
index 8e15723fbe..0000000000
--- a/arch/arm/mach-mvebu/include/mach/common.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2013
- *  Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *  Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_COMMON_H__
-#define __MACH_COMMON_H__
-
-#include <asm/sections.h>
-#include <asm/unaligned.h>
-
-#define MVEBU_BOOTUP_INT_REG_BASE	0xd0000000
-#define MVEBU_REMAP_INT_REG_BASE	0xf1000000
-
-/* #including <asm/barebox-arm.h> yields a circle, so we need a forward decl */
-unsigned long get_runtime_offset(void);
-
-static inline void __iomem *mvebu_get_initial_int_reg_base(void)
-{
-#ifdef __PBL__
-	u32 base = __get_unaligned_le32(_text + get_runtime_offset() + 0x30);
-	return (void __force __iomem *)base;
-#else
-	return (void __force __iomem *)MVEBU_REMAP_INT_REG_BASE;
-#endif
-}
-
-#endif
diff --git a/arch/arm/mach-mvebu/include/mach/debug_ll.h b/arch/arm/mach-mvebu/include/mach/debug_ll.h
deleted file mode 100644
index 1cf821ee2a..0000000000
--- a/arch/arm/mach-mvebu/include/mach/debug_ll.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2013
- *  Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_DEBUG_LL_H__
-#define __MACH_DEBUG_LL_H__
-
-#include <io.h>
-
-#define UART_BASE	0xf1012000
-#define UARTn_BASE(n)	(UART_BASE + ((n) * 0x100))
-#define UART_THR	0x00
-#define UART_LSR	0x14
-#define   LSR_THRE	BIT(5)
-
-#define EARLY_UART	UARTn_BASE(CONFIG_MVEBU_CONSOLE_UART)
-
-static inline void PUTC_LL(char c)
-{
-	/* Wait until there is space in the FIFO */
-	while (!(readl(EARLY_UART + UART_LSR) & LSR_THRE))
-		;
-
-	/* Send the character */
-	writel(c, EARLY_UART + UART_THR);
-
-	/* Wait to make sure it hits the line */
-	while (!(readl(EARLY_UART + UART_LSR) & LSR_THRE))
-		;
-}
-#endif
diff --git a/arch/arm/mach-mvebu/include/mach/dove-regs.h b/arch/arm/mach-mvebu/include/mach/dove-regs.h
deleted file mode 100644
index 8b4319bcab..0000000000
--- a/arch/arm/mach-mvebu/include/mach/dove-regs.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright
- * (C) 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_MVEBU_DOVE_REGS_H
-#define __MACH_MVEBU_DOVE_REGS_H
-
-#include <mach/common.h>
-
-/*
- * Even after MVEBU SoC internal register base remap. Dove MC
- * registers are still at 0xd0800000. We remap it right after
- * internal registers to 0xf1800000.
-*/
-#define DOVE_BOOTUP_MC_REGS	0xd0800000
-#define DOVE_REMAP_MC_REGS	0xf1800000
-
-#define DOVE_INT_REGS_BASE	IOMEM(MVEBU_REMAP_INT_REG_BASE)
-#define DOVE_MC_REGS_BASE	IOMEM(DOVE_REMAP_MC_REGS)
-
-#define DOVE_UART_BASE		(DOVE_INT_REGS_BASE + 0x12000)
-#define DOVE_UARTn_BASE(n)	(DOVE_UART_BASE + ((n) * 0x100))
-
-#define DOVE_SPI0_BASE		(DOVE_INT_REGS_BASE + 0x10600)
-#define DOVE_SPI1_BASE		(DOVE_INT_REGS_BASE + 0x14600)
-
-#define DOVE_BRIDGE_BASE	(DOVE_INT_REGS_BASE + 0x20000)
-#define  INT_REGS_BASE_MAP	0x080
-#define  BRIDGE_RSTOUT_MASK	0x108
-#define  SOFT_RESET_OUT_EN	BIT(2)
-#define  BRIDGE_SYS_SOFT_RESET	0x10c
-#define  SOFT_RESET_EN		BIT(0)
-#define DOVE_TIMER_BASE		(DOVE_INT_REGS_BASE + 0x20300)
-
-#define DOVE_SAR_BASE		(DOVE_INT_REGS_BASE + 0xd0214)
-#define  SAR0			0x000
-#define  TCLK_FREQ_SHIFT	23
-#define  TCLK_FREQ_MASK		(0x3 << TCLK_FREQ_SHIFT)
-#define  SAR1			0x004
-
-#define DOVE_AXI_CTRL		(DOVE_INT_REGS_BASE + 0xd0224)
-#define DOVE_CPU_CTRL		(DOVE_INT_REGS_BASE + 0xd025c)
-
-#define DOVE_SDRAM_BASE		(DOVE_MC_REGS_BASE)
-#define  SDRAM_REGS_BASE_DECODE	0x010
-#define  SDRAM_MAPn(n)		(0x100 + ((n) * 0x10))
-#define  SDRAM_START_MASK	(0x1ff << 23)
-#define  SDRAM_LENGTH_SHIFT	16
-#define  SDRAM_LENGTH_MASK	(0x00f << SDRAM_LENGTH_SHIFT)
-#define  SDRAM_ADDRESS_MASK	(0x1ff << 7)
-#define  SDRAM_MAP_VALID	BIT(0)
-
-#endif /* __MACH_MVEBU_DOVE_REGS_H */
diff --git a/arch/arm/mach-mvebu/include/mach/kirkwood-regs.h b/arch/arm/mach-mvebu/include/mach/kirkwood-regs.h
deleted file mode 100644
index 39fa37900b..0000000000
--- a/arch/arm/mach-mvebu/include/mach/kirkwood-regs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright
- * (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_MVEBU_KIRKWOOD_REGS_H
-#define __MACH_MVEBU_KIRKWOOD_REGS_H
-
-#include <mach/common.h>
-
-#define KIRKWOOD_INT_REGS_BASE	IOMEM(MVEBU_REMAP_INT_REG_BASE)
-
-#define KIRKWOOD_SDRAM_BASE	(KIRKWOOD_INT_REGS_BASE + 0x00000)
-#define DDR_BASE_CS		0x1500
-#define DDR_BASE_CSn(n)		(DDR_BASE_CS + ((n) * 0x8))
-#define  DDR_BASE_CS_HIGH_MASK	0x0000000f
-#define  DDR_BASE_CS_LOW_MASK	0xff000000
-#define DDR_SIZE_CS		0x1504
-#define DDR_SIZE_CSn(n)		(DDR_SIZE_CS + ((n) * 0x8))
-#define  DDR_SIZE_ENABLED	BIT(0)
-#define  DDR_SIZE_CS_MASK	0x1c
-#define  DDR_SIZE_CS_SHIFT	2
-#define  DDR_SIZE_MASK		0xff000000
-
-#define KIRKWOOD_SAR_BASE	(KIRKWOOD_INT_REGS_BASE + 0x10030)
-#define  SAR_TCLK_FREQ		BIT(21)
-
-#define KIRKWOOD_UART_BASE	(KIRKWOOD_INT_REGS_BASE + 0x12000)
-#define KIRKWOOD_UARTn_BASE(n)	(KIRKWOOD_UART_BASE + ((n) * 0x100))
-
-#define KIRKWOOD_BRIDGE_BASE	(KIRKWOOD_INT_REGS_BASE + 0x20000)
-#define  BRIDGE_RSTOUT_MASK	0x108
-#define  SOFT_RESET_OUT_EN	BIT(2)
-#define  BRIDGE_SYS_SOFT_RESET	0x10c
-#define  SOFT_RESET_EN		BIT(0)
-
-#define KIRKWOOD_TIMER_BASE	(KIRKWOOD_INT_REGS_BASE + 0x20300)
-
-#endif /* __MACH_MVEBU_KIRKWOOD_REGS_H */
diff --git a/arch/arm/mach-mvebu/include/mach/lowlevel.h b/arch/arm/mach-mvebu/include/mach/lowlevel.h
deleted file mode 100644
index 3e639fc1bd..0000000000
--- a/arch/arm/mach-mvebu/include/mach/lowlevel.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2013
- *  Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *  Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_LOWLEVEL_H__
-#define __MACH_LOWLEVEL_H__
-
-void mvebu_barebox_entry(void *boarddata);
-void dove_barebox_entry(void *boarddata);
-void kirkwood_barebox_entry(void *boarddata);
-void armada_370_xp_barebox_entry(void *boarddata);
-
-#endif
diff --git a/arch/arm/mach-mvebu/include/mach/socid.h b/arch/arm/mach-mvebu/include/mach/socid.h
deleted file mode 100644
index 7a29c82b30..0000000000
--- a/arch/arm/mach-mvebu/include/mach/socid.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Marvell MVEBU SoC Ids
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_MVEBU_SOCID_H
-#define __MACH_MVEBU_SOCID_H
-
-#define PCIE_VEN_DEV_ID		0x000
-#define PCIE_REV_ID		0x008
-#define  REV_ID_MASK		0xff
-
-extern u16 soc_devid;
-extern u16 soc_revid;
-
-static inline u16 mvebu_get_soc_devid(void)
-{
-	return soc_devid;
-}
-
-static inline u16 mvebu_get_soc_revid(void)
-{
-	return soc_revid;
-}
-
-/* Orion */
-#define DEVID_F5180		0x5180
-#define  REVID_F5180N_B1	0x3
-#define DEVID_F5181		0x5181
-#define  REVID_F5181_B1		0x3
-#define  REVID_F5181L		0x8
-#define DEVID_F5182		0x5182
-#define  REVID_F5182_A1		0x1
-#define DEVID_F6183		0x6183
-/* Kirkwood */
-#define DEVID_F6180		0x6180
-#define DEVID_F6190		0x6190
-#define DEVID_F6192		0x6192
-#define DEVID_F6280		0x6280
-#define DEVID_F6281		0x6281
-#define DEVID_F6282		0x1155
-/* Kirkwood Duo */
-#define DEVID_F6321		0x6321
-#define DEVID_F6322		0x6322
-#define DEVID_F6323		0x6323
-/* Avanta */
-#define DEVID_F6510		0x6510
-#define DEVID_F6530		0x6530
-#define DEVID_F6550		0x6550
-#define DEVID_F6560		0x6560
-/* Dove */
-#define DEVID_AP510		0x0510
-#define DEVID_F6781		0x6781
-/* Discovery Duo */
-#define DEVID_MV76100		0x7610
-#define DEVID_MV78100		0x7810
-#define DEVID_MV78200		0x7820
-/* Armada 370 */
-#define DEVID_F6707		0x6707
-#define DEVID_F6710		0x6710
-#define DEVID_F6711		0x6711
-/* Armada XP */
-#define DEVID_MV78130		0x7813
-#define DEVID_MV78160		0x7816
-#define DEVID_MV78230		0x7823
-#define DEVID_MV78260		0x7826
-#define DEVID_MV78460		0x7846
-#define DEVID_MV78880		0x7888
-
-#endif /* __MACH_MVEBU_SOCID_H */
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index e50d7501c8..4b5d1b716b 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -1,17 +1,5 @@
-/*
- * Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 
 #include <common.h>
 #include <init.h>
@@ -19,7 +7,7 @@
 #include <restart.h>
 #include <asm/memory.h>
 #include <linux/mbus.h>
-#include <mach/kirkwood-regs.h>
+#include <mach/mvebu/kirkwood-regs.h>
 
 static void __noreturn kirkwood_restart_soc(struct restart_handler *rst)
 {
diff --git a/arch/arm/mach-mvebu/kwb_bbu.c b/arch/arm/mach-mvebu/kwb_bbu.c
index f79464fe53..0fde9abb57 100644
--- a/arch/arm/mach-mvebu/kwb_bbu.c
+++ b/arch/arm/mach-mvebu/kwb_bbu.c
@@ -1,8 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <bbu.h>
 #include <libfile.h>
-#include <printk.h>
+#include <linux/printk.h>
 
-#include <mach/bbu.h>
+#include <mach/mvebu/bbu.h>
 
 struct mvebu_bbu_handler {
 	struct bbu_handler bbuh;
diff --git a/arch/arm/mach-mvebu/kwbootimage.c b/arch/arm/mach-mvebu/kwbootimage.c
index e379d732fe..2bcc42fe57 100644
--- a/arch/arm/mach-mvebu/kwbootimage.c
+++ b/arch/arm/mach-mvebu/kwbootimage.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <bootm.h>
 #include <common.h>
 #include <fcntl.h>
@@ -8,7 +10,7 @@
 #include <restart.h>
 #include <unistd.h>
 #include <asm/unaligned.h>
-#include <mach/common.h>
+#include <mach/mvebu/common.h>
 
 static int do_bootm_kwbimage_v0_v1(struct image_data *data)
 {
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index f4a9d3d422..c8ef2c62af 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_MXS
 
 config ARCH_TEXT_BASE
@@ -77,6 +79,7 @@ config MACH_DUCKBILL
 config MACH_CFA10036
 	bool "cfa-10036"
 	select MXS_OCOTP
+	select I2C
 	select I2C_GPIO
 	select EEPROM_AT24
 	help
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index e3843368c2..0f3fba8967 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += imx.o iomux-imx.o power.o
 pbl-y += iomux-imx.o
 obj-$(CONFIG_ARCH_IMX23) += clocksource-imx23.o usb-imx23.o soc-imx23.o
diff --git a/arch/arm/mach-mxs/bcb.c b/arch/arm/mach-mxs/bcb.c
index 860508bde7..152a7c3bca 100644
--- a/arch/arm/mach-mxs/bcb.c
+++ b/arch/arm/mach-mxs/bcb.c
@@ -1,11 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2011 Wolfram Sang, Pengutronix e.K.
+
 /*
- * (C) Copyright 2011 Wolfram Sang, Pengutronix e.K.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
  * Based on a similar function in Karo Electronics TX28-U-Boot (flash.c).
  * Probably written by Lothar Waßmann (like tx28.c).
  */
@@ -19,7 +15,7 @@
 #include <errno.h>
 #include <io.h>
 
-#include <mach/imx-regs.h>
+#include <mach/mxs/imx-regs.h>
 
 #include <linux/err.h>
 #include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-mxs/clocksource-imx23.c b/arch/arm/mach-mxs/clocksource-imx23.c
index 8279ee2f2d..d1d9f10bec 100644
--- a/arch/arm/mach-mxs/clocksource-imx23.c
+++ b/arch/arm/mach-mxs/clocksource-imx23.c
@@ -1,24 +1,11 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix
 
 #include <common.h>
 #include <init.h>
 #include <clock.h>
 #include <notifier.h>
-#include <mach/imx23-regs.h>
-#include <mach/clock.h>
+#include <mach/mxs/imx23-regs.h>
 #include <io.h>
 
 #define TIMROTCTRL 0x00
@@ -46,6 +33,7 @@ static struct clocksource cs = {
 	.read	= imx23_clocksource_read,
 	.mask	= CLOCKSOURCE_MASK(16),
 	.shift	= 10,
+	.priority = 80,
 };
 
 static int imx23_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data)
diff --git a/arch/arm/mach-mxs/clocksource-imx28.c b/arch/arm/mach-mxs/clocksource-imx28.c
index 4f38af68b4..306112ffa0 100644
--- a/arch/arm/mach-mxs/clocksource-imx28.c
+++ b/arch/arm/mach-mxs/clocksource-imx28.c
@@ -1,23 +1,11 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de>
 
 #include <common.h>
 #include <init.h>
 #include <clock.h>
 #include <notifier.h>
-#include <mach/imx28-regs.h>
-#include <mach/clock.h>
+#include <mach/mxs/imx28-regs.h>
 #include <io.h>
 
 #define TIMROTCTRL 0x00
@@ -50,6 +38,7 @@ static struct clocksource imx28_cs = {
 	.read	= imx28_clocksource_read,
 	.mask	= CLOCKSOURCE_MASK(32),
 	.shift	= 17,
+	.priority = 80,
 };
 
 static int imx28_clocksource_init(void)
diff --git a/arch/arm/mach-mxs/imx.c b/arch/arm/mach-mxs/imx.c
index b7247b9b72..2b4e682281 100644
--- a/arch/arm/mach-mxs/imx.c
+++ b/arch/arm/mach-mxs/imx.c
@@ -1,17 +1,5 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix
 
 #include <common.h>
 #include <bootsource.h>
@@ -21,9 +9,9 @@
 #include <io.h>
 #include <stmp-device.h>
 
-#include <mach/generic.h>
-#include <mach/imx-regs.h>
-#include <mach/revision.h>
+#include <mach/mxs/generic.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/revision.h>
 
 #define HW_RTC_PERSISTENT1     0x070
 
@@ -170,8 +158,7 @@ static void mxs_boot_save_loc(void)
 	case 0x9: src = BOOTSOURCE_MMC; break;		/* "SSP SD/MMC #0" */
 	}
 
-	bootsource_set(src);
-	bootsource_set_instance(instance);
+	bootsource_set_raw(src, instance);
 }
 
 static int mxs_init(void)
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
deleted file mode 100644
index adbc3304f8..0000000000
--- a/arch/arm/mach-mxs/include/mach/clock.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_CLOCK_H
-# define __MACH_CLOCK_H
-
-#endif /* __MACH_CLOCK_H */
diff --git a/arch/arm/mach-mxs/include/mach/debug_ll.h b/arch/arm/mach-mxs/include/mach/debug_ll.h
deleted file mode 100644
index 9e3ce1c1cd..0000000000
--- a/arch/arm/mach-mxs/include/mach/debug_ll.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __MACH_DEBUG_LL_H__
-#define __MACH_DEBUG_LL_H__
-
-#include <io.h>
-#include <mach/imx-regs.h>
-
-#define UARTDBGDR 0x00
-#define UARTDBGFR 0x18
-# define TXFE (1 << 7)
-# define TXFF (1 << 5)
-
-static inline void PUTC_LL(int c)
-{
-	void __iomem *base = (void *)IMX_DBGUART_BASE;
-
-	/* Wait for room in TX FIFO */
-	while (!(readl(base + UARTDBGFR) & TXFE));
-
-	writel(c, base + UARTDBGDR);
-}
-
-#endif /* __MACH_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/devices.h b/arch/arm/mach-mxs/include/mach/devices.h
deleted file mode 100644
index b212aa783e..0000000000
--- a/arch/arm/mach-mxs/include/mach/devices.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __MACH_MXS_DEVICES_H
-#define __MACH_MXS_DEVICES_H
-
-#include <common.h>
-#include <linux/sizes.h>
-#include <xfuncs.h>
-#include <driver.h>
-#include <mach/imx-regs.h>
-
-static inline struct device_d *mxs_add_nand(unsigned long gpmi_base, unsigned long bch_base)
-{
-	struct resource res[] = {
-		{
-			.start = gpmi_base,
-			.end = gpmi_base + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = bch_base,
-			.end = bch_base + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-	};
-
-	struct device_d *dev = xzalloc(sizeof(*dev));
-
-	dev->resource = xzalloc(sizeof(struct resource) * ARRAY_SIZE(res));
-	memcpy(dev->resource, res, sizeof(struct resource) * ARRAY_SIZE(res));
-	dev->num_resources = ARRAY_SIZE(res);
-	dev_set_name(dev, "mxs_nand");
-	dev->id = DEVICE_ID_DYNAMIC;
-
-	platform_device_register(dev);
-
-	return dev;
-};
-
-static inline struct device_d *imx23_add_nand(void)
-{
-	return mxs_add_nand(MXS_GPMI_BASE, MXS_BCH_BASE);
-}
-
-static inline struct device_d *imx28_add_nand(void)
-{
-	return mxs_add_nand(MXS_GPMI_BASE, MXS_BCH_BASE);
-}
-
-#endif /* __MACH_MXS_DEVICES_H */
diff --git a/arch/arm/mach-mxs/include/mach/fb.h b/arch/arm/mach-mxs/include/mach/fb.h
deleted file mode 100644
index ad28f79d57..0000000000
--- a/arch/arm/mach-mxs/include/mach/fb.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_FB_H
-# define __MACH_FB_H
-
-#include <fb.h>
-
-/** LC display uses active high data enable signal */
-#define FB_SYNC_DE_HIGH_ACT	(1 << 27)
-/** LC display will latch its data at clock's rising edge */
-#define FB_SYNC_CLK_INVERT	(1 << 28)
-/** output RGB digital data inverted */
-#define FB_SYNC_DATA_INVERT	(1 << 29)
-/** Stop clock if no data is sent (required for passive displays) */
-#define FB_SYNC_CLK_IDLE_DIS	(1 << 30)
-/** swap RGB to BGR */
-#define FB_SYNC_SWAP_RGB	(1 << 31)
-
-#define USE_LCD_RESET		1
-
-struct imx_fb_platformdata {
-	struct fb_videomode *mode_list;
-	unsigned mode_cnt;
-
-	unsigned dotclk_delay;	/**< refer manual HW_LCDIF_VDCTRL4 register */
-	unsigned ld_intf_width;	/* interface width in bits */
-	unsigned bits_per_pixel;
-
-	void *fixed_screen;	/**< if != NULL use this as framebuffer memory */
-	unsigned fixed_screen_size; /**< framebuffer memory size for fixed_screen */
-
-	unsigned flags;
-	void (*enable)(int enable); /**< hook to enable backlight */
-};
-
-#endif /* __MACH_FB_H */
-
diff --git a/arch/arm/mach-mxs/include/mach/generic.h b/arch/arm/mach-mxs/include/mach/generic.h
deleted file mode 100644
index d63fa48257..0000000000
--- a/arch/arm/mach-mxs/include/mach/generic.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifdef CONFIG_ARCH_IMX23
-# define cpu_is_mx23()	(1)
-#else
-# define cpu_is_mx23()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_IMX28
-# define cpu_is_mx28()	(1)
-#else
-# define cpu_is_mx28()	(0)
-#endif
-
-#define cpu_is_mx1()	(0)
-#define cpu_is_mx21()	(0)
-#define cpu_is_mx25()	(0)
-#define cpu_is_mx27()	(0)
-#define cpu_is_mx31()	(0)
-#define cpu_is_mx35()	(0)
-#define cpu_is_mx51()	(0)
-#define cpu_is_mx53()	(0)
-#define cpu_is_mx6()	(0)
diff --git a/arch/arm/mach-mxs/include/mach/imx-regs.h b/arch/arm/mach-mxs/include/mach/imx-regs.h
deleted file mode 100644
index f5abd8bf79..0000000000
--- a/arch/arm/mach-mxs/include/mach/imx-regs.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _IMX_REGS_H
-# define _IMX_REGS_H
-
-#if defined CONFIG_ARCH_IMX23
-# include <mach/imx23-regs.h>
-#endif
-
-#if defined CONFIG_ARCH_IMX28
-# include <mach/imx28-regs.h>
-#endif
-
-#endif /* _IMX_REGS_H */
diff --git a/arch/arm/mach-mxs/include/mach/imx23-regs.h b/arch/arm/mach-mxs/include/mach/imx23-regs.h
deleted file mode 100644
index 3fd2f3d15b..0000000000
--- a/arch/arm/mach-mxs/include/mach/imx23-regs.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MX23_REGS_H
-#define __ASM_ARCH_MX23_REGS_H
-
-#define IMX_MEMORY_BASE		0x40000000
-#define MXS_APBH_BASE		0x80004000
-#define MXS_BCH_BASE		0x8000a000
-#define MXS_GPMI_BASE		0x8000c000
-#define IMX_UART1_BASE		0x8006c000
-#define IMX_UART2_BASE		0x8006e000
-#define IMX_DBGUART_BASE	0x80070000
-#define IMX_TIM1_BASE		0x80068000
-#define IMX_IOMUXC_BASE		0x80018000
-#define IMX_EMI_BASE		0x80020000
-#define IMX_OCOTP_BASE		0x8002c000
-#define IMX_WDT_BASE		0x8005c000
-#define IMX_CCM_BASE		0x80040000
-#define IMX_LRADC_BASE		0x80050000
-#define IMX_I2C1_BASE		0x80058000
-#define IMX_SSP1_BASE		0x80010000
-#define IMX_FB_BASE		0x80030000
-#define IMX_SSP2_BASE		0x80034000
-#define IMX_POWER_BASE		0x80044000
-#define IMX_USBPHY_BASE		0x8007c000
-#define IMX_DIGCTL_BASE		0x8001c000
-#define IMX_USB_BASE		0x80080000
-#define IMX_SDRAMC_BASE		0x800e0000
-
-#endif /* __ASM_ARCH_MX23_REGS_H */
diff --git a/arch/arm/mach-mxs/include/mach/imx23.h b/arch/arm/mach-mxs/include/mach/imx23.h
deleted file mode 100644
index 56e76d5f50..0000000000
--- a/arch/arm/mach-mxs/include/mach/imx23.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __MACH_IMX23_H
-#define __MACH_IMX23_H
-
-#include <linux/bitfield.h>
-#include <io.h>
-
-#define DRAM_CTL14_CS0_EN	BIT(0)
-#define DRAM_CTL14_CS1_EN	BIT(1)
-#define DRAM_CTL11_COLUMNS_DIFF	GENMASK(10, 8)
-#define DRAM_CTL10_ROWS_DIFF	GENMASK(18, 16)
-
-#define DRAM_CTL(n)	(IMX_SDRAMC_BASE + 4 * (n))
-
-static inline u32 imx23_get_memsize(void)
-{
-	u32 ctl10 = readl(DRAM_CTL(10));
-	u32 ctl11 = readl(DRAM_CTL(11));
-	u32 ctl14 = readl(DRAM_CTL(14));
-	int rows, columns, banks = 4, cs0, cs1;
-
-	columns = 12 - FIELD_GET(DRAM_CTL11_COLUMNS_DIFF, ctl11);
-	rows = 13 - FIELD_GET(DRAM_CTL10_ROWS_DIFF, ctl10);
-	cs0 = FIELD_GET(DRAM_CTL14_CS0_EN, ctl14);
-	cs1 = FIELD_GET(DRAM_CTL14_CS1_EN, ctl14);
-
-	return (1 << columns) * (1 << rows) * banks * (cs0 + cs1);
-}
-
-#endif /* __MACH_IMX23_H */
\ No newline at end of file
diff --git a/arch/arm/mach-mxs/include/mach/imx28-regs.h b/arch/arm/mach-mxs/include/mach/imx28-regs.h
deleted file mode 100644
index 1a90ec2aa5..0000000000
--- a/arch/arm/mach-mxs/include/mach/imx28-regs.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_MX28_REGS_H
-#define __ASM_ARCH_MX28_REGS_H
-
-#define IMX_SRAM_BASE		0x00000000
-#define IMX_MEMORY_BASE		0x40000000
-
-#define MXS_APBH_BASE		0x80004000
-#define MXS_BCH_BASE		0x8000a000
-#define MXS_GPMI_BASE		0x8000c000
-#define IMX_SSP0_BASE		0x80010000
-#define IMX_SSP1_BASE		0x80012000
-#define IMX_SSP2_BASE		0x80014000
-#define IMX_SSP3_BASE		0x80016000
-#define IMX_IOMUXC_BASE		0x80018000
-#define IMX_DIGCTL_BASE		0x8001c000
-#define IMX_EMI_BASE		0x80020000
-#define IMX_OCOTP_BASE		0x8002c000
-#define IMX_FB_BASE		0x80030000
-#define IMX_CCM_BASE		0x80040000
-#define IMX_POWER_BASE		0x80044000
-#define IMX_LRADC_BASE		0x80050000
-#define IMX_WDT_BASE		0x80056000
-#define IMX_I2C0_BASE		0x80058000
-#define IMX_I2C1_BASE		0x8005a000
-#define IMX_PWM_BASE		0x80064000
-#define IMX_TIM1_BASE		0x80068000
-#define IMX_UART0_BASE		0x8006a000
-#define IMX_UART1_BASE		0x8006c000
-#define IMX_UART2_BASE		0x8006e000
-#define IMX_UART3_BASE		0x80070000
-#define IMX_UART4_BASE		0x80072000
-#define IMX_DBGUART_BASE	0x80074000
-#define IMX_USBPHY0_BASE	0x8007c000
-#define IMX_USBPHY1_BASE	0x8007e000
-#define IMX_USB0_BASE		0x80080000
-#define IMX_USB1_BASE		0x80090000
-#define IMX_SDRAMC_BASE		0x800e0000
-#define IMX_FEC0_BASE		0x800F0000
-#define IMX_FEC1_BASE		0x800F4000
-
-#endif /* __ASM_ARCH_MX28_REGS_H */
diff --git a/arch/arm/mach-mxs/include/mach/imx28.h b/arch/arm/mach-mxs/include/mach/imx28.h
deleted file mode 100644
index 5816625c89..0000000000
--- a/arch/arm/mach-mxs/include/mach/imx28.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __MACH_IMX28_H
-#define __MACH_IMX28_H
-
-#include <linux/bitfield.h>
-#include <io.h>
-
-#define DRAM_CTL29_CS0_EN	BIT(24)
-#define DRAM_CTL29_CS1_EN	BIT(25)
-#define DRAM_CTL29_COLUMNS_DIFF	GENMASK(18, 16)
-#define DRAM_CTL29_ROWS_DIFF	GENMASK(10, 8)
-#define DRAM_CTL31_EIGHT_BANKS	BIT(16)
-
-#define DRAM_CTL(n)	(IMX_SDRAMC_BASE + 4 * (n))
-
-static inline u32 imx28_get_memsize(void)
-{
-	u32 ctl29 = readl(DRAM_CTL(29));
-	u32 ctl31 = readl(DRAM_CTL(31));
-	int rows, columns, banks, cs0, cs1;
-
-	columns = 12 - FIELD_GET(DRAM_CTL29_COLUMNS_DIFF, ctl29);
-	rows = 15 - FIELD_GET(DRAM_CTL29_ROWS_DIFF, ctl29);
-	banks = FIELD_GET(DRAM_CTL31_EIGHT_BANKS, ctl31) ? 8 : 4;
-	cs0 = FIELD_GET(DRAM_CTL29_CS0_EN, ctl29);
-	cs1 = FIELD_GET(DRAM_CTL29_CS1_EN, ctl29);
-
-	return (1 << columns) * (1 << rows) * banks * (cs0 + cs1);
-}
-
-#endif /* __MACH_IMX28_H */
\ No newline at end of file
diff --git a/arch/arm/mach-mxs/include/mach/init.h b/arch/arm/mach-mxs/include/mach/init.h
deleted file mode 100644
index 53c1e05634..0000000000
--- a/arch/arm/mach-mxs/include/mach/init.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Freescale i.MX28 SPL functions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef	__M28_INIT_H__
-#define	__M28_INIT_H__
-
-void mxs_early_delay(int delay);
-
-/**
- * Power configuration of the system:
- * - POWER_USE_5V: use 5V input as power supply
- * - POWER_USE_BATTERY: use battery input when the system is supplied by a battery
- * - POWER_USE_BATTERY_INPUT: use battery input when the system is supplied by
- *   a DC source (instead of a real battery) on the battery input
- * - POWER_ENABLE_4P2: power up the 4P2 regulator (implied for POWER_USE_5V)
- */
-enum mxs_power_config {
-	POWER_USE_5V			= 0b00000000,
-	POWER_USE_BATTERY		= 0b00000001,
-	POWER_USE_BATTERY_INPUT		= 0b00000010,
-	POWER_ENABLE_4P2		= 0b00000100,
-};
-extern int power_config;
-static inline enum mxs_power_config mxs_power_config_get_use(void) {
-	return (power_config & 0b00000011);
-}
-
-
-struct mxs_power_ctrl {
-	uint32_t target;	/*< target voltage */
-	uint32_t brownout;	/*< brownout threshhold */
-};
-struct mxs_power_ctrls {
-	struct mxs_power_ctrl * vdda;	/*< if non-null, set values for VDDA */
-	struct mxs_power_ctrl * vddd;	/*< if non-null, set values for VDDD */
-	struct mxs_power_ctrl * vddio;	/*< if non-null, set values for VDDIO */
-	struct mxs_power_ctrl * vddmem;	/*< if non-null, set values for VDDMEM */
-};
-
-extern struct mxs_power_ctrl mxs_vddio_default;
-extern struct mxs_power_ctrl mxs_vddd_default;
-extern struct mxs_power_ctrl mxs_vdda_default;
-extern struct mxs_power_ctrl mx23_vddmem_default;
-extern struct mxs_power_ctrls mx23_power_default;
-extern struct mxs_power_ctrls mx28_power_default;
-
-void mx23_power_init(const int config, struct mxs_power_ctrls *ctrls);
-void mx28_power_init(const int config, struct mxs_power_ctrls *ctrls);
-void mxs_power_wait_pswitch(void);
-
-extern const uint32_t mx28_dram_vals_default[190];
-extern uint32_t mx23_dram_vals[];
-
-#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LPDDR1	(0b00 << 16)
-#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2	(0b10 << 16)
-#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2	(0b11 << 16)
-
-void mx23_mem_init(void);
-void mx28_mem_init(const int emi_ds_ctrl_ddr_mode,
-		const uint32_t dram_vals[190]);
-void mxs_mem_setup_cpu_and_hbus(void);
-void mxs_mem_setup_vdda(void);
-void mxs_mem_init_clock(const uint8_t clk_emi_div, const uint8_t clk_emi_frac);
-
-void mxs_lradc_init(void);
-void mxs_lradc_enable_batt_measurement(void);
-
-#endif	/* __M28_INIT_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-imx23.h b/arch/arm/mach-mxs/include/mach/iomux-imx23.h
deleted file mode 100644
index 1e225f8fc5..0000000000
--- a/arch/arm/mach-mxs/include/mach/iomux-imx23.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_MACH_IOMUX_MX23_H
-#define __ASM_MACH_IOMUX_MX23_H
-
-/* Bank 0, pins 0 ... 15, GPIO pins 0 ... 15 */
-#define GPMI_D15		(FUNC(0) | PORTF(0, 15) | SE | PE)
-#define GPMI_D15_AUART2_TX	(FUNC(1) | PORTF(0, 15) | SE | PE)
-#define GPMI_D15_GPMI_CE3N	(FUNC(2) | PORTF(0, 15) | SE | PE)
-#define GPMI_D15_GPIO		(FUNC(3) | PORTF(0, 15) | SE | PE)
-#define GPMI_D14		(FUNC(0) | PORTF(0, 14) | SE)
-#define GPMI_D14_AUART2_RX	(FUNC(1) | PORTF(0, 14) | SE)
-#define GPMI_D14_GPIO		(FUNC(3) | PORTF(0, 14) | SE)
-#define GPMI_D13		(FUNC(0) | PORTF(0, 13) | SE)
-#define GPMI_D13_LCD_D23	(FUNC(1) | PORTF(0, 13) | SE)
-#define GPMI_D13_GPIO		(FUNC(3) | PORTF(0, 13) | SE)
-#define GPMI_D12		(FUNC(0) | PORTF(0, 12) | SE)
-#define GPMI_D12_LCD_D22	(FUNC(1) | PORTF(0, 12) | SE)
-#define GPMI_D12_GPIO		(FUNC(3) | PORTF(0, 12) | SE)
-#define GPMI_D11		(FUNC(0) | PORTF(0, 11) | SE | PE)
-#define GPMI_D11_LCD_D21	(FUNC(1) | PORTF(0, 11) | SE | PE)
-#define GPMI_D11_SSP1_D7	(FUNC(2) | PORTF(0, 11) | SE | PE)
-#define GPMI_D11_GPIO		(FUNC(3) | PORTF(0, 11) | SE | PE)
-#define GPMI_D10		(FUNC(0) | PORTF(0, 10) | SE | PE)
-#define GPMI_D10_LCD_D20	(FUNC(1) | PORTF(0, 10) | SE | PE)
-#define GPMI_D10_SSP1_D6	(FUNC(2) | PORTF(0, 10) | SE | PE)
-#define GPMI_D10_GPIO		(FUNC(3) | PORTF(0, 10) | SE | PE)
-#define GPMI_D09		(FUNC(0) | PORTF(0, 9) | SE | PE)
-#define GPMI_D09_LCD_D19	(FUNC(1) | PORTF(0, 9) | SE | PE)
-#define GPMI_D09_SSP1_D5	(FUNC(2) | PORTF(0, 9) | SE | PE)
-#define GPMI_D09_GPIO		(FUNC(3) | PORTF(0, 9) | SE | PE)
-#define GPMI_D08		(FUNC(0) | PORTF(0, 8) | SE | PE)
-#define GPMI_D08_LCD_D18	(FUNC(1) | PORTF(0, 8) | SE | PE)
-#define GPMI_D08_SSP1_D4	(FUNC(2) | PORTF(0, 8) | SE | PE)
-#define GPMI_D08_GPIO		(FUNC(3) | PORTF(0, 8) | SE | PE)
-#define GPMI_D07		(FUNC(0) | PORTF(0, 7) | SE | PE)
-#define GPMI_D07_LCD_D15	(FUNC(1) | PORTF(0, 7) | SE | PE)
-#define GPMI_D07_SSP2_D7	(FUNC(2) | PORTF(0, 7) | SE | PE)
-#define GPMI_D07_GPIO		(FUNC(3) | PORTF(0, 7) | SE | PE)
-#define GPMI_D06		(FUNC(0) | PORTF(0, 6) | SE | PE)
-#define GPMI_D06_LCD_D14	(FUNC(1) | PORTF(0, 6) | SE | PE)
-#define GPMI_D06_SSP2_D6	(FUNC(2) | PORTF(0, 6) | SE | PE)
-#define GPMI_D06_GPIO		(FUNC(3) | PORTF(0, 6) | SE | PE)
-#define GPMI_D05		(FUNC(0) | PORTF(0, 5) | SE | PE)
-#define GPMI_D05_LCD_D13	(FUNC(1) | PORTF(0, 5) | SE | PE)
-#define GPMI_D05_SSP2_D5	(FUNC(2) | PORTF(0, 5) | SE | PE)
-#define GPMI_D05_GPIO		(FUNC(3) | PORTF(0, 5) | SE | PE)
-#define GPMI_D04		(FUNC(0) | PORTF(0, 4) | SE | PE)
-#define GPMI_D04_LCD_D12	(FUNC(1) | PORTF(0, 4) | SE | PE)
-#define GPMI_D04_SSP2_D4	(FUNC(2) | PORTF(0, 4) | SE | PE)
-#define GPMI_D04_GPIO		(FUNC(3) | PORTF(0, 4) | SE | PE)
-#define GPMI_D03		(FUNC(0) | PORTF(0, 3) | SE | PE)
-#define GPMI_D03_LCD_D11	(FUNC(1) | PORTF(0, 3) | SE | PE)
-#define GPMI_D03_SSP2_D3	(FUNC(2) | PORTF(0, 3) | SE | PE)
-#define GPMI_D03_GPIO		(FUNC(3) | PORTF(0, 3) | SE | PE)
-#define GPMI_D02		(FUNC(0) | PORTF(0, 2) | SE | PE)
-#define GPMI_D02_LCD_D10	(FUNC(1) | PORTF(0, 2) | SE | PE)
-#define GPMI_D02_SSP2_D2	(FUNC(2) | PORTF(0, 2) | SE | PE)
-#define GPMI_D02_GPIO		(FUNC(3) | PORTF(0, 2) | SE | PE)
-#define GPMI_D01		(FUNC(0) | PORTF(0, 1) | SE | PE)
-#define GPMI_D01_LCD_D9		(FUNC(1) | PORTF(0, 1) | SE | PE)
-#define GPMI_D01_SSP2_D1	(FUNC(2) | PORTF(0, 1) | SE | PE)
-#define GPMI_D01_GPIO		(FUNC(3) | PORTF(0, 1) | SE | PE)
-#define GPMI_D00		(FUNC(0) | PORTF(0, 0) | SE | PE)
-#define GPMI_D00_LCD_D8		(FUNC(1) | PORTF(0, 0) | SE | PE)
-#define GPMI_D00_SSP2_D0	(FUNC(2) | PORTF(0, 0) | SE | PE)
-#define GPMI_D00_GPIO		(FUNC(3) | PORTF(0, 0) | SE | PE)
-
-/* Bank 0, pins 16 ... 31 GPIO pins 16 ... 31 */
-#define I2C_SDA			(FUNC(0) | PORTF(1, 15) | SE)
-#define I2C_SDA_GPMI_CE2N	(FUNC(1) | PORTF(1, 15) | SE)
-#define I2C_SDA_AUART1_RX	(FUNC(2) | PORTF(1, 15) | SE)
-#define I2C_SDA_GPIO		(FUNC(3) | PORTF(1, 15) | SE)
-#define I2C_CLK			(FUNC(0) | PORTF(1, 14) | SE | PE)
-#define I2C_CLK_GPMI_RDY2	(FUNC(1) | PORTF(1, 14) | SE | PE)
-#define I2C_CLK_AUART1_TX	(FUNC(2) | PORTF(1, 14) | SE | PE)
-#define I2C_CLK_GPIO		(FUNC(3) | PORTF(1, 14) | SE | PE)
-#define AUART1_TX		(FUNC(0) | PORTF(1, 13) | SE | PE)
-#define AUART1_TX_SSP1_D7	(FUNC(2) | PORTF(1, 13) | SE | PE)
-#define AUART1_TX_GPIO		(FUNC(3) | PORTF(1, 13) | SE | PE)
-#define AUART1_RX		(FUNC(0) | PORTF(1, 12) | SE | PE)
-#define AUART1_RX_SSP1_D6	(FUNC(2) | PORTF(1, 12) | SE | PE)
-#define AUART1_RX_GPIO		(FUNC(3) | PORTF(1, 12) | SE | PE)
-#define AUART1_RTS		(FUNC(0) | PORTF(1, 11) | SE | PE)
-#define AUART1_RTS_SSP1_D5	(FUNC(2) | PORTF(1, 11) | SE | PE)
-#define AUART1_RTS_GPIO		(FUNC(3) | PORTF(1, 11) | SE | PE)
-#define AUART1_CTS		(FUNC(0) | PORTF(1, 10) | SE | PE)
-#define AUART1_CTS_SSP1_D4	(FUNC(2) | PORTF(1, 10) | SE | PE)
-#define AUART1_CTS_GPIO		(FUNC(3) | PORTF(1, 10) | SE | PE)
-#define GPMI_RDN		(FUNC(0) | PORTF(1, 9) | SE)
-#define GPMI_RDN_GPIO		(FUNC(3) | PORTF(1, 9) | SE)
-#define GPMI_WRN		(FUNC(0) | PORTF(1, 8) | SE)
-#define GPMI_WRN_SSP2_SCK	(FUNC(2) | PORTF(1, 8) | SE)
-#define GPMI_WRN_GPIO		(FUNC(3) | PORTF(1, 8) | SE)
-#define GPMI_WPM		(FUNC(0) | PORTF(1, 7) | SE)
-#define GPMI_WPM_GPIO		(FUNC(3) | PORTF(1, 7) | SE)
-#define GPMI_RDY3		(FUNC(0) | PORTF(1, 6) | SE | PE)
-#define GPMI_RDY3_GPIO		(FUNC(3) | PORTF(1, 6) | SE | PE)
-#define GPMI_RDY2		(FUNC(0) | PORTF(1, 5) | SE | PE)
-#define GPMI_RDY2_GPIO		(FUNC(3) | PORTF(1, 5) | SE | PE)
-#define GPMI_RDY1		(FUNC(0) | PORTF(1, 4) | SE | PE)
-#define GPMI_RDY1_SSP2_CMD	(FUNC(2) | PORTF(1, 4) | SE | PE)
-#define GPMI_RDY1_GPIO		(FUNC(3) | PORTF(1, 4) | SE | PE)
-#define GPMI_RDY0		(FUNC(0) | PORTF(1, 3) | SE | PE)
-#define GPMI_RDY0_SSP2_DETECT	(FUNC(2) | PORTF(1, 3) | SE | PE)
-#define GPMI_RDY0_GPIO		(FUNC(3) | PORTF(1, 3) | SE | PE)
-#define GPMI_CE2N		(FUNC(0) | PORTF(1, 2) | SE | PE)
-#define GPMI_CE2N_GPIO		(FUNC(3) | PORTF(1, 2) | SE | PE)
-#define GPMI_ALE		(FUNC(0) | PORTF(1, 1) | SE)
-#define GPMI_ALE_LCD_D17	(FUNC(1) | PORTF(1, 1) | SE)
-#define GPMI_ALE_GPIO		(FUNC(3) | PORTF(1, 1) | SE)
-#define GPMI_CLE		(FUNC(0) | PORTF(1, 0) | SE)
-#define GPMI_CLE_LCD_D16	(FUNC(1) | PORTF(1, 1) | SE)
-#define GPMI_CLE_GPIO		(FUNC(3) | PORTF(1, 0) | SE)
-
-/* Bank 1, pins 0 ... 15 GPIO pins 32 ... 47 */
-#define LCD_D15			(FUNC(0) | PORTF(2, 15) | SE)
-#define LCD_D15_ETM_DA7		(FUNC(1) | PORTF(2, 15) | SE)
-#define LCD_D15_SAIF1_SDATA1	(FUNC(2) | PORTF(2, 15) | SE)
-#define LCD_D15_GPIO		(FUNC(3) | PORTF(2, 15) | SE)
-#define LCD_D14			(FUNC(0) | PORTF(2, 14) | SE)
-#define LCD_D14_ETM_DA6		(FUNC(1) | PORTF(2, 14) | SE)
-#define LCD_D14_SAIF1_SDATA2	(FUNC(2) | PORTF(2, 14) | SE)
-#define LCD_D14_GPIO		(FUNC(3) | PORTF(2, 14) | SE)
-#define LCD_D13			(FUNC(0) | PORTF(2, 13) | SE)
-#define LCD_D13_ETM_DA5		(FUNC(1) | PORTF(2, 13) | SE)
-#define LCD_D13_SAIF2_SDATA2	(FUNC(2) | PORTF(2, 13) | SE)
-#define LCD_D13_GPIO		(FUNC(3) | PORTF(2, 13) | SE)
-#define LCD_D12			(FUNC(0) | PORTF(2, 12) | SE)
-#define LCD_D12_ETM_DA4		(FUNC(1) | PORTF(2, 12) | SE)
-#define LCD_D12_SAIF2_SDATA1	(FUNC(2) | PORTF(2, 12) | SE)
-#define LCD_D12_GPIO		(FUNC(3) | PORTF(2, 12) | SE)
-#define LCD_D11			(FUNC(0) | PORTF(2, 11) | SE)
-#define LCD_D11_ETM_DA3		(FUNC(1) | PORTF(2, 11) | SE)
-#define LCD_D11_SAIF_LRCLK	(FUNC(2) | PORTF(2, 11) | SE)
-#define LCD_D11_GPIO		(FUNC(3) | PORTF(2, 11) | SE)
-#define LCD_D10			(FUNC(0) | PORTF(2, 10) | SE)
-#define LCD_D10_ETM_DA2		(FUNC(1) | PORTF(2, 10) | SE)
-#define LCD_D10_SAIF_BITCLK	(FUNC(2) | PORTF(2, 10) | SE)
-#define LCD_D10_GPIO		(FUNC(3) | PORTF(2, 10) | SE)
-#define LCD_D9			(FUNC(0) | PORTF(2, 9) | SE)
-#define LCD_D9_ETM_DA1		(FUNC(1) | PORTF(2, 9) | SE)
-#define LCD_D9_SAIF1_SDATA0	(FUNC(2) | PORTF(2, 9) | SE)
-#define LCD_D9_GPIO		(FUNC(3) | PORTF(2, 9) | SE)
-#define LCD_D8			(FUNC(0) | PORTF(2, 8) | SE)
-#define LCD_D8_ETM_DA0		(FUNC(1) | PORTF(2, 8) | SE)
-#define LCD_D8_SAIF2_SDATA0	(FUNC(2) | PORTF(2, 8) | SE)
-#define LCD_D8_GPIO		(FUNC(3) | PORTF(2, 8) | SE)
-#define LCD_D7			(FUNC(0) | PORTF(2, 7) | SE)
-#define LCD_D7_ETM_DA15		(FUNC(1) | PORTF(2, 7) | SE)
-#define LCD_D7_GPIO		(FUNC(3) | PORTF(2, 7) | SE)
-#define LCD_D6			(FUNC(0) | PORTF(2, 6) | SE)
-#define LCD_D6_ETM_DA14		(FUNC(1) | PORTF(2, 6) | SE)
-#define LCD_D6_GPIO		(FUNC(3) | PORTF(2, 6) | SE)
-#define LCD_D5			(FUNC(0) | PORTF(2, 5) | SE)
-#define LCD_D5_ETM_DA13		(FUNC(1) | PORTF(2, 5) | SE)
-#define LCD_D5_GPIO		(FUNC(3) | PORTF(2, 5) | SE)
-#define LCD_D4			(FUNC(0) | PORTF(2, 4) | SE)
-#define LCD_D4_ETM_DA12		(FUNC(1) | PORTF(2, 4) | SE)
-#define LCD_D4_GPIO		(FUNC(3) | PORTF(2, 4) | SE)
-#define LCD_D3			(FUNC(0) | PORTF(2, 3) | SE)
-#define LCD_D3_ETM_DA11		(FUNC(1) | PORTF(2, 3) | SE)
-#define LCD_D3_GPIO		(FUNC(3) | PORTF(2, 3) | SE)
-#define LCD_D2			(FUNC(0) | PORTF(2, 2) | SE)
-#define LCD_D2_ETM_DA10		(FUNC(1) | PORTF(2, 2) | SE)
-#define LCD_D2_GPIO		(FUNC(3) | PORTF(2, 2) | SE)
-#define LCD_D1			(FUNC(0) | PORTF(2, 1) | SE)
-#define LCD_D1_ETM_DA9		(FUNC(1) | PORTF(2, 1) | SE)
-#define LCD_D1_GPIO		(FUNC(3) | PORTF(2, 1) | SE)
-#define LCD_D0			(FUNC(0) | PORTF(2, 0) | SE)
-#define LCD_D0_ETM_DA8		(FUNC(1) | PORTF(2, 0) | SE)
-#define LCD_D0_GPIO		(FUNC(3) | PORTF(2, 0) | SE)
-
-/* Bank 1, pins 16 ... 30 GPIO pins 48 ... 63 */
-#define PWM4			(FUNC(0) | PORTF(3, 14) | SE)
-#define PWM4_ETM_CLK		(FUNC(1) | PORTF(3, 14) | SE)
-#define PWM4_AUART1_RTS		(FUNC(2) | PORTF(3, 14) | SE)
-#define PWM4_GPIO		(FUNC(3) | PORTF(3, 14) | SE)
-#define PWM3			(FUNC(0) | PORTF(3, 13) | SE)
-#define PWM3_ETM_TCTL		(FUNC(1) | PORTF(3, 13) | SE)
-#define PWM3_AUART1_CTS		(FUNC(2) | PORTF(3, 13) | SE)
-#define PWM3_GPIO		(FUNC(3) | PORTF(3, 13) | SE)
-#define PWM2			(FUNC(0) | PORTF(3, 12) | SE | PE)
-#define PWM2_GPMI_READY3	(FUNC(1) | PORTF(3, 12) | SE | PE)
-#define PWM2_GPIO		(FUNC(3) | PORTF(3, 12) | SE | PE)
-#define PWM1			(FUNC(0) | PORTF(3, 11) | SE)
-#define PWM1_TIMROT2		(FUNC(1) | PORTF(3, 11) | SE)
-#define PWM1_DUART_TX		(FUNC(2) | PORTF(3, 11) | SE)
-#define PWM1_GPIO		(FUNC(3) | PORTF(3, 11) | SE)
-#define PWM0			(FUNC(0) | PORTF(3, 10) | SE)
-#define PWM0_TIMROT1		(FUNC(1) | PORTF(3, 10) | SE)
-#define PWM0_DUART_RX		(FUNC(2) | PORTF(3, 10) | SE)
-#define PWM0_GPIO		(FUNC(3) | PORTF(3, 10) | SE)
-#define LCD_VSYNC		(FUNC(0) | PORTF(3, 9) | SE)
-#define LCD_VSYNC_LCD_BUSY	(FUNC(1) | PORTF(3, 9) | SE)
-#define LCD_VSYNC_GPIO		(FUNC(3) | PORTF(3, 9) | SE)
-#define LCD_HSYNC		(FUNC(0) | PORTF(3, 8) | SE)
-#define LCD_HSYNC_I2C_SD	(FUNC(1) | PORTF(3, 8) | SE)
-#define LCD_HSYNC_GPIO		(FUNC(3) | PORTF(3, 8) | SE)
-#define LCD_ENABE		(FUNC(0) | PORTF(3, 7) | SE)
-#define LCD_ENABE_I2C_CLK	(FUNC(1) | PORTF(3, 7) | SE)
-#define LCD_ENABE_GPIO		(FUNC(3) | PORTF(3, 7) | SE)
-#define LCD_DOTCLOCK		(FUNC(0) | PORTF(3, 6) | SE | PE)
-#define LCD_DOTCLOCK_GPMI_READY3 (FUNC(1) | PORTF(3, 6) | SE | PE)
-#define LCD_DOTCLOCK_GPIO	(FUNC(3) | PORTF(3, 6) | SE | PE)
-#define LCD_CS			(FUNC(0) | PORTF(3, 5) | SE)
-#define LCD_CS_GPIO		(FUNC(3) | PORTF(3, 5) | SE)
-#define LCD_WR			(FUNC(0) | PORTF(3, 4) | SE)
-#define LCD_WR_GPIO		(FUNC(3) | PORTF(3, 4) | SE)
-#define LCD_RS			(FUNC(0) | PORTF(3, 3) | SE)
-#define LCD_RS_ETM_TCLK		(FUNC(1) | PORTF(3, 3) | SE)
-#define LCD_RS_GPIO		(FUNC(3) | PORTF(3, 3) | SE)
-#define LCD_RESET		(FUNC(0) | PORTF(3, 2) | SE | PE)
-#define LCD_RESET_ETM_TCTL	(FUNC(1) | PORTF(3, 2) | SE | PE)
-#define LCD_RESET_GPMI_CE3N	(FUNC(2) | PORTF(3, 2) | SE | PE)
-#define LCD_RESET_GPIO		(FUNC(3) | PORTF(3, 2) | SE | PE)
-#define LCD_D17			(FUNC(0) | PORTF(3, 1) | SE)
-#define LCD_D17_GPIO		(FUNC(3) | PORTF(3, 1) | SE)
-#define LCD_D16			(FUNC(0) | PORTF(3, 0) | SE)
-#define LCD_D16_SAIF_ALT_BITCLK	(FUNC(2) | PORTF(3, 0) | SE)
-#define LCD_D16_GPIO		(FUNC(3) | PORTF(3, 0) | SE)
-
-/* Bank 2, pins 0 ... 15 GPIO pins 64 ... 79 */
-#define EMI_A6			(FUNC(0) | PORTF(4, 15) | SE | VE)
-#define EMI_A6_GPIO		(FUNC(3) | PORTF(4, 15) | SE | VE)
-#define EMI_A5			(FUNC(0) | PORTF(4, 14) | SE | VE)
-#define EMI_A5_GPIO		(FUNC(3) | PORTF(4, 14) | SE | VE)
-#define EMI_A4			(FUNC(0) | PORTF(4, 13) | SE | VE)
-#define EMI_A4_GPIO		(FUNC(3) | PORTF(4, 13) | SE | VE)
-#define EMI_A3			(FUNC(0) | PORTF(4, 12) | SE | VE)
-#define EMI_A3_GPIO		(FUNC(3) | PORTF(4, 12) | SE | VE)
-#define EMI_A2			(FUNC(0) | PORTF(4, 11) | SE | VE)
-#define EMI_A2_GPIO		(FUNC(3) | PORTF(4, 11) | SE | VE)
-#define EMI_A1			(FUNC(0) | PORTF(4, 10) | SE | VE)
-#define EMI_A1_GPIO		(FUNC(3) | PORTF(4, 10) | SE | VE)
-#define EMI_A0			(FUNC(0) | PORTF(4, 9) | SE | VE)
-#define EMI_A0_GPIO		(FUNC(3) | PORTF(4, 9) | SE | VE)
-#define ROTARYB			(FUNC(0) | PORTF(4, 8) | SE | PE)
-#define ROTARYB_AUART2_CTS	(FUNC(1) | PORTF(4, 8) | SE | PE)
-#define ROTARYB_GPMI_CE3N	(FUNC(2) | PORTF(4, 8) | SE | PE)
-#define ROTARYB_GPIO		(FUNC(3) | PORTF(4, 8) | SE | PE)
-#define ROTARYA			(FUNC(0) | PORTF(4, 7) | SE)
-#define ROTARYA_AUART2_RTS	(FUNC(1) | PORTF(4, 7) | SE)
-#define ROTARYA_SPDIF		(FUNC(2) | PORTF(4, 7) | SE)
-#define ROTARYA_GPIO		(FUNC(3) | PORTF(4, 7) | SE)
-#define SSP1_SCK		(FUNC(0) | PORTF(4, 6) | SE)
-#define SSP1_SCK_ALT_JTAG_TRST	(FUNC(2) | PORTF(4, 6) | SE)
-#define SSP1_SCK_GPIO		(FUNC(3) | PORTF(4, 6) | SE)
-#define SSP1_DATA3		(FUNC(0) | PORTF(4, 5) | SE | PE)
-#define SSP1_DATA3_ALT_JTAG_TMS	(FUNC(2) | PORTF(4, 5) | SE | PE)
-#define SSP1_DATA3_GPIO		(FUNC(3) | PORTF(4, 5) | SE | PE)
-#define SSP1_DATA2		(FUNC(0) | PORTF(4, 4) | SE | PE)
-#define SSP1_DATA2_I2C_SD	(FUNC(1) | PORTF(4, 4) | SE | PE)
-#define SSP1_DATA2_ALT_JTAG_RTCK (FUNC(2) | PORTF(4, 4) | SE | PE)
-#define SSP1_DATA2_GPIO		(FUNC(3) | PORTF(4, 4) | SE | PE)
-#define SSP1_DATA1		(FUNC(0) | PORTF(4, 3) | SE | PE)
-#define SSP1_DATA1_I2C_CLK	(FUNC(1) | PORTF(4, 3) | SE | PE)
-#define SSP1_DATA1_ALT_JTAG_TCK	(FUNC(2) | PORTF(4, 3) | SE | PE)
-#define SSP1_DATA1_GPIO		(FUNC(3) | PORTF(4, 3) | SE | PE)
-#define SSP1_DATA0		(FUNC(0) | PORTF(4, 2) | SE | PE)
-#define SSP1_DATA0_ALT_JTAG_TDI	(FUNC(2) | PORTF(4, 2) | SE | PE)
-#define SSP1_DATA0_GPIO		(FUNC(3) | PORTF(4, 2) | SE | PE)
-#define SSP1_DETECT		(FUNC(0) | PORTF(4, 1) | SE | PE)
-#define SSP1_DETECT_GPMI_CE3N	(FUNC(1) | PORTF(4, 1) | SE | PE)
-#define SSP1_DETECT_USB_ID	(FUNC(2) | PORTF(4, 1) | SE | PE)
-#define SSP1_DETECT_GPIO	(FUNC(3) | PORTF(4, 1) | SE | PE)
-#define SSP1_CMD		(FUNC(0) | PORTF(4, 0) | SE | PE)
-#define SSP1_CMD_JTAG_TDO	(FUNC(2) | PORTF(4, 0) | SE | PE)
-#define SSP1_CMD_GPIO		(FUNC(3) | PORTF(4, 0) | SE | PE)
-
-/* Bank 2, pins 16 ... 31 GPIO pins 80 ... 95 */
-#define EMI_WEN			(FUNC(0) | PORTF(5, 15) | SE | VE)
-#define EMI_WEN_GPIO		(FUNC(3) | PORTF(5, 15) | SE | VE)
-#define EMI_RASN		(FUNC(0) | PORTF(5, 14) | SE | VE)
-#define EMI_RASN_GPIO		(FUNC(3) | PORTF(5, 14) | SE | VE)
-#define EMI_CKE			(FUNC(0) | PORTF(5, 13) | SE | VE)
-#define EMI_CKE_GPIO		(FUNC(3) | PORTF(5, 13) | SE | VE)
-#define GPMI_CE0N		(FUNC(0) | PORTF(5, 12) | SE)
-#define GPMI_CE0N_GPIO		(FUNC(3) | PORTF(5, 12) | SE)
-#define GPMI_CE1N		(FUNC(0) | PORTF(5, 11) | SE | PE)
-#define GPMI_CE1N_GPIO		(FUNC(3) | PORTF(5, 11) | SE | PE)
-#define EMI_CE1N		(FUNC(0) | PORTF(5, 10) | SE | VE | PE)
-#define EMI_CE1N_GPIO		(FUNC(3) | PORTF(5, 10) | SE | VE | PE)
-#define EMI_CE0N		(FUNC(0) | PORTF(5, 9) | SE | VE)
-#define EMI_CE0N_GPIO		(FUNC(3) | PORTF(5, 9) | SE | VE)
-#define EMI_CASN		(FUNC(0) | PORTF(5, 8) | SE | VE)
-#define EMI_CASN_GPIO		(FUNC(3) | PORTF(5, 8) | SE | VE)
-#define EMI_BA1			(FUNC(0) | PORTF(5, 7) | SE | VE)
-#define EMI_BA1_GPIO		(FUNC(3) | PORTF(5, 7) | SE | VE)
-#define EMI_BA0			(FUNC(0) | PORTF(5, 6) | SE | VE)
-#define EMI_BA0_GPIO		(FUNC(3) | PORTF(5, 6) | SE | VE)
-#define EMI_A12			(FUNC(0) | PORTF(5, 5) | SE | VE)
-#define EMI_A12_GPIO		(FUNC(3) | PORTF(5, 5) | SE | VE)
-#define EMI_A11			(FUNC(0) | PORTF(5, 4) | SE | VE)
-#define EMI_A11_GPIO		(FUNC(3) | PORTF(5, 4) | SE | VE)
-#define EMI_A10			(FUNC(0) | PORTF(5, 3) | SE | VE)
-#define EMI_A10_GPIO		(FUNC(3) | PORTF(5, 3) | SE | VE)
-#define EMI_A9			(FUNC(0) | PORTF(5, 2) | SE | VE)
-#define EMI_A9_GPIO		(FUNC(3) | PORTF(5, 2) | SE | VE)
-#define EMI_A8			(FUNC(0) | PORTF(5, 1) | SE | VE)
-#define EMI_A8_GPIO		(FUNC(3) | PORTF(5, 1) | SE | VE)
-#define EMI_A7			(FUNC(0) | PORTF(5, 0) | SE | VE)
-#define EMI_A7_GPIO		(FUNC(3) | PORTF(5, 0) | SE | VE)
-
-/* Bank 3, pins 0 ... 15 GPIO pins 96 ... 111 */
-#define EMI_D15			(FUNC(0) | PORTF(6, 15) | SE | VE | PE)
-#define EMI_D15_DISABLED	(FUNC(3) | PORTF(6, 15) | SE | VE | PE)
-#define EMI_D14			(FUNC(0) | PORTF(6, 14) | SE | VE | PE)
-#define EMI_D14_DISABLED	(FUNC(3) | PORTF(6, 14) | SE | VE | PE)
-#define EMI_D13			(FUNC(0) | PORTF(6, 13) | SE | VE | PE)
-#define EMI_D13_DISABLED	(FUNC(3) | PORTF(6, 13) | SE | VE | PE)
-#define EMI_D12			(FUNC(0) | PORTF(6, 12) | SE | VE | PE)
-#define EMI_D12_DISABLED	(FUNC(3) | PORTF(6, 12) | SE | VE | PE)
-#define EMI_D11			(FUNC(0) | PORTF(6, 11) | SE | VE | PE)
-#define EMI_D11_DISABLED	(FUNC(3) | PORTF(6, 11) | SE | VE | PE)
-#define EMI_D10			(FUNC(0) | PORTF(6, 10) | SE | VE | PE)
-#define EMI_D10_DISABLED	(FUNC(3) | PORTF(6, 10) | SE | VE | PE)
-#define EMI_D9			(FUNC(0) | PORTF(6, 9) | SE | VE | PE)
-#define EMI_D9_DISABLED		(FUNC(3) | PORTF(6, 9) | SE | VE | PE)
-#define EMI_D8			(FUNC(0) | PORTF(6, 8) | SE | VE | PE)
-#define EMI_D8_DISABLED		(FUNC(3) | PORTF(6, 8) | SE | VE | PE)
-#define EMI_D7			(FUNC(0) | PORTF(6, 7) | SE | VE | PE)
-#define EMI_D7_DISABLED		(FUNC(3) | PORTF(6, 7) | SE | VE | PE)
-#define EMI_D6			(FUNC(0) | PORTF(6, 6) | SE | VE | PE)
-#define EMI_D6_DISABLED		(FUNC(3) | PORTF(6, 6) | SE | VE | PE)
-#define EMI_D5			(FUNC(0) | PORTF(6, 5) | SE | VE | PE)
-#define EMI_D5_DISABLED		(FUNC(3) | PORTF(6, 5) | SE | VE | PE)
-#define EMI_D4			(FUNC(0) | PORTF(6, 4) | SE | VE | PE)
-#define EMI_D4_DISABLED		(FUNC(3) | PORTF(6, 4) | SE | VE | PE)
-#define EMI_D3			(FUNC(0) | PORTF(6, 3) | SE | VE | PE)
-#define EMI_D3_DISABLED		(FUNC(3) | PORTF(6, 3) | SE | VE | PE)
-#define EMI_D2			(FUNC(0) | PORTF(6, 2) | SE | VE | PE)
-#define EMI_D2_DISABLED		(FUNC(3) | PORTF(6, 2) | SE | VE | PE)
-#define EMI_D1			(FUNC(0) | PORTF(6, 1) | SE | VE | PE)
-#define EMI_D1_DISABLED		(FUNC(3) | PORTF(6, 1) | SE | VE | PE)
-#define EMI_D0			(FUNC(0) | PORTF(6, 0) | SE | VE | PE)
-#define EMI_D0_DISABLED		(FUNC(3) | PORTF(6, 0) | SE | VE | PE)
-
-/* Bank 3, pins 16 ... 21 GPIO pins 112 ... 117 */
-#define EMI_CLKN		(FUNC(0) | PORTF(7, 5) | SE | VE)
-#define EMI_CLKN_DISABLED	(FUNC(3) | PORTF(7, 5) | SE | VE)
-#define EMI_CLK			(FUNC(0) | PORTF(7, 4) | SE | VE)
-#define EMI_CLK_DISABLED	(FUNC(3) | PORTF(7, 4) | SE | VE)
-#define EMI_DQS1		(FUNC(0) | PORTF(7, 3) | SE | VE)
-#define EMI_DQS1_DISABLED	(FUNC(3) | PORTF(7, 3) | SE | VE)
-#define EMI_DQS0		(FUNC(0) | PORTF(7, 2) | SE | VE)
-#define EMI_DQS0_DISABLED	(FUNC(3) | PORTF(7, 2) | SE | VE)
-#define EMI_DQM1		(FUNC(0) | PORTF(7, 1) | SE | VE | PE)
-#define EMI_DQM1_DISABLED	(FUNC(3) | PORTF(7, 1) | SE | VE | PE)
-#define EMI_DQM0		(FUNC(0) | PORTF(7, 0) | SE | VE | PE)
-#define EMI_DQM0_DISABLED	(FUNC(3) | PORTF(7, 0) | SE | VE | PE)
-
-#endif /* __ASM_MACH_IOMUX_MX23_H */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-imx28.h b/arch/arm/mach-mxs/include/mach/iomux-imx28.h
deleted file mode 100644
index 6119f3caf9..0000000000
--- a/arch/arm/mach-mxs/include/mach/iomux-imx28.h
+++ /dev/null
@@ -1,571 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_IOMUX_IMX28_H
-#define __MACH_IOMUX_IMX28_H
-
-/* Bank 0, GPIO pins 0 ... 31 */
-#define GPMI_RESETN		(FUNC(0) | PORTF(0, 28) | SE | VE | PE)
-#define GPMI_RESETN_SSP3_CMD	(FUNC(1) | PORTF(0, 28) | SE | VE | PE)
-#define GPMI_RESETN_GPIO	(FUNC(3) | PORTF(0, 28) | SE | VE | PE)
-#define GPMI_CLE		(FUNC(0) | PORTF(0, 27) | SE | VE | PE)
-#define GPMI_CLE_SSP3_D2	(FUNC(1) | PORTF(0, 27) | SE | VE | PE)
-#define GPMI_CLE_SSP3_D5	(FUNC(2) | PORTF(0, 27) | SE | VE | PE)
-#define GPMI_CLE_GPIO		(FUNC(3) | PORTF(0, 27) | SE | VE | PE)
-#define GPMI_ALE		(FUNC(0) | PORTF(0, 26) | SE | VE | PE)
-#define GPMI_ALE_SSP3_D1	(FUNC(1) | PORTF(0, 26) | SE | VE | PE)
-#define GPMI_ALE_SSP3_D4	(FUNC(2) | PORTF(0, 26) | SE | VE | PE)
-#define GPMI_ALE_GPIO		(FUNC(3) | PORTF(0, 26) | SE | VE | PE)
-#define GPMI_WRN		(FUNC(0) | PORTF(0, 25) | SE | VE | BK)
-#define GPMI_WRN_SSP1_SCK	(FUNC(1) | PORTF(0, 25) | SE | VE | BK)
-#define GPMI_WRN_GPIO		(FUNC(3) | PORTF(0, 25) | SE | VE | BK)
-#define GPMI_RDN		(FUNC(0) | PORTF(0, 24) | SE | VE | PE)
-#define GPMI_RDN_SSP3_SCK	(FUNC(1) | PORTF(0, 24) | SE | VE | PE)
-#define GPMI_RDN_GPIO		(FUNC(3) | PORTF(0, 24) | SE | VE | PE)
-#define GPMI_READY3		(FUNC(0) | PORTF(0, 23) | SE | VE | PE)
-#define GPMI_READY3_CAN0_RX	(FUNC(1) | PORTF(0, 23) | SE | VE | PE)
-#define GPMI_READY3_HSDAC_TRIG	(FUNC(2) | PORTF(0, 23) | SE | VE | PE)
-#define GPMI_READY3_GPIO	(FUNC(3) | PORTF(0, 23) | SE | VE | PE)
-#define GPMI_READY2		(FUNC(0) | PORTF(0, 22) | SE | VE | PE)
-#define GPMI_READY2_CAN0_TX	(FUNC(1) | PORTF(0, 22) | SE | VE | PE)
-#define GPMI_READY2_ENET0_TX_ER	(FUNC(2) | PORTF(0, 22) | SE | VE | PE)
-#define GPMI_READY2_GPIO	(FUNC(3) | PORTF(0, 22) | SE | VE | PE)
-#define GPMI_READY1		(FUNC(0) | PORTF(0, 21) | SE | VE | PE)
-#define GPMI_READY1_SSP1_CMD	(FUNC(1) | PORTF(0, 21) | SE | VE | PE)
-#define GPMI_READY1_GPIO	(FUNC(3) | PORTF(0, 21) | SE | VE | PE)
-#define GPMI_READY0		(FUNC(0) | PORTF(0, 20) | SE | VE | PE)
-#define GPMI_READY0_SSP1_CD	(FUNC(1) | PORTF(0, 20) | SE | VE | PE)
-#define GPMI_READY0_USB0_ID	(FUNC(2) | PORTF(0, 20) | SE | VE | PE)
-#define GPMI_READY0_GPIO	(FUNC(3) | PORTF(0, 20) | SE | VE | PE)
-#define GPMI_CE3N		(FUNC(0) | PORTF(0, 19) | SE | VE | PE)
-#define GPMI_CE3N_CAN1_RX	(FUNC(1) | PORTF(0, 19) | SE | VE | PE)
-#define GPMI_CE3N_SAIF1_MCLK	(FUNC(2) | PORTF(0, 19) | SE | VE | PE)
-#define GPMI_CE3N_GPIO		(FUNC(3) | PORTF(0, 19) | SE | VE | PE)
-#define GPMI_CE2N		(FUNC(0) | PORTF(0, 18) | SE | VE | PE)
-#define GPMI_CE2N_CAN1_TX	(FUNC(1) | PORTF(0, 18) | SE | VE | PE)
-#define GPMI_CE2N_ENET0_RX_ER	(FUNC(2) | PORTF(0, 18) | SE | VE | PE)
-#define GPMI_CE2N_GPIO		(FUNC(3) | PORTF(0, 18) | SE | VE | PE)
-#define GPMI_CE1N		(FUNC(0) | PORTF(0, 17) | SE | VE | PE)
-#define GPMI_CE1N_SSP3_D3	(FUNC(1) | PORTF(0, 17) | SE | VE | PE)
-#define GPMI_CE1N_GPIO		(FUNC(3) | PORTF(0, 17) | SE | VE | PE)
-#define GPMI_CE0N		(FUNC(0) | PORTF(0, 16) | SE | VE | PE)
-#define GPMI_CE0N_SSP3_D0	(FUNC(1) | PORTF(0, 16) | SE | VE | PE)
-#define GPMI_CE0N_GPIO		(FUNC(3) | PORTF(0, 16) | SE | VE | PE)
-#define GPMI_D7			(FUNC(0) | PORTF(0, 7) | SE | VE | PE)
-#define GPMI_D7_SSP1_D7		(FUNC(1) | PORTF(0, 7) | SE | VE | PE)
-#define GPMI_D7_GPIO		(FUNC(3) | PORTF(0, 7) | SE | VE | PE)
-#define GPMI_D6			(FUNC(0) | PORTF(0, 6) | SE | VE | PE)
-#define GPMI_D6_SSP1_D6		(FUNC(1) | PORTF(0, 6) | SE | VE | PE)
-#define GPMI_D6_GPIO		(FUNC(3) | PORTF(0, 6) | SE | VE | PE)
-#define GPMI_D5			(FUNC(0) | PORTF(0, 5) | SE | VE | PE)
-#define GPMI_D5_SSP1_D5		(FUNC(1) | PORTF(0, 5) | SE | VE | PE)
-#define GPMI_D5_GPIO		(FUNC(3) | PORTF(0, 5) | SE | VE | PE)
-#define GPMI_D4			(FUNC(0) | PORTF(0, 4) | SE | VE | PE)
-#define GPMI_D4_SSP1_D4		(FUNC(1) | PORTF(0, 4) | SE | VE | PE)
-#define GPMI_D4_GPIO		(FUNC(3) | PORTF(0, 4) | SE | VE | PE)
-#define GPMI_D3			(FUNC(0) | PORTF(0, 3) | SE | VE | PE)
-#define GPMI_D3_SSP1_D3		(FUNC(1) | PORTF(0, 3) | SE | VE | PE)
-#define GPMI_D3_GPIO		(FUNC(3) | PORTF(0, 3) | SE | VE | PE)
-#define GPMI_D2			(FUNC(0) | PORTF(0, 2) | SE | VE | PE)
-#define GPMI_D2_SSP1_D2		(FUNC(1) | PORTF(0, 2) | SE | VE | PE)
-#define GPMI_D2_GPIO		(FUNC(3) | PORTF(0, 2) | SE | VE | PE)
-#define GPMI_D1			(FUNC(0) | PORTF(0, 1) | SE | VE | PE)
-#define GPMI_D1_SSP1_D1		(FUNC(1) | PORTF(0, 1) | SE | VE | PE)
-#define GPMI_D1_GPIO		(FUNC(3) | PORTF(0, 1) | SE | VE | PE)
-#define GPMI_D0			(FUNC(0) | PORTF(0, 0) | SE | VE | PE)
-#define GPMI_D0_SSP1_D0		(FUNC(1) | PORTF(0, 0) | SE | VE | PE)
-#define GPMI_D0_GPIO		(FUNC(3) | PORTF(0, 0) | SE | VE | PE)
-
-/* Bank 1, GPIO pins 32 ... 63 */
-#define LCD_ENABLE		(FUNC(0) | PORTF(1, 31) | SE | VE | BK)
-#define LCD_ENABLE_GPIO		(FUNC(3) | PORTF(1, 31) | SE | VE | BK)
-#define LCD_DOTCLK		(FUNC(0) | PORTF(1, 30) | SE | VE | BK)
-#define LCD_DOTCLK_SAIF1_MCLK	(FUNC(1) | PORTF(1, 30) | SE | VE | BK)
-#define LCD_DOTCLK_ETM_TCLK	(FUNC(2) | PORTF(1, 30) | SE | VE | BK)
-#define LCD_DOTCLK_GPIO		(FUNC(3) | PORTF(1, 30) | SE | VE | BK)
-#define LCD_HSYNC		(FUNC(0) | PORTF(1, 29) | SE | VE | BK)
-#define LCD_HSYNC_SAIF1_SDATA1	(FUNC(1) | PORTF(1, 29) | SE | VE | BK)
-#define LCD_HSYNC_ETM_TCTL	(FUNC(2) | PORTF(1, 29) | SE | VE | BK)
-#define LCD_HSYNC_GPIO		(FUNC(3) | PORTF(1, 29) | SE | VE | BK)
-#define LCD_VSYNC		(FUNC(0) | PORTF(1, 28) | SE | VE | BK)
-#define LCD_VSYNC_SAIF1_SDATA0	(FUNC(1) | PORTF(1, 28) | SE | VE | BK)
-#define LCD_VSYNC_GPIO		(FUNC(3) | PORTF(1, 28) | SE | VE | BK)
-#define LCD_CS			(FUNC(0) | PORTF(1, 27) | SE | VE | BK)
-#define LCD_CS_LCD_ENABLE	(FUNC(1) | PORTF(1, 27) | SE | VE | BK)
-#define LCD_CS_GPIO		(FUNC(3) | PORTF(1, 27) | SE | VE | BK)
-#define LCD_RS			(FUNC(0) | PORTF(1, 26) | SE | VE | BK)
-#define LCD_RS_LCD_DOTCLK	(FUNC(1) | PORTF(1, 26) | SE | VE | BK)
-#define LCD_RS_GPIO		(FUNC(3) | PORTF(1, 26) | SE | VE | BK)
-#define LCD_WR_RWN		(FUNC(0) | PORTF(1, 25) | SE | VE | BK)
-#define LCD_WR_RWN_LCD_HSYNC	(FUNC(1) | PORTF(1, 25) | SE | VE | BK)
-#define LCD_WR_RWN_ETM_TCLK	(FUNC(2) | PORTF(1, 25) | SE | VE | BK)
-#define LCD_WR_RWN_GPIO		(FUNC(3) | PORTF(1, 25) | SE | VE | BK)
-#define LCD_RD_E		(FUNC(0) | PORTF(1, 24) | SE | VE | BK)
-#define LCD_RD_E_LCD_VSYNC	(FUNC(1) | PORTF(1, 24) | SE | VE | BK)
-#define LCD_RD_E_ETM_TCTL	(FUNC(2) | PORTF(1, 24) | SE | VE | BK)
-#define LCD_RD_E_GPIO		(FUNC(3) | PORTF(1, 24) | SE | VE | BK)
-#define LCD_D23			(FUNC(0) | PORTF(1, 23) | SE | VE | BK)
-#define LCD_D23_ENET1_1588_EVENT3_IN (FUNC(1) | PORTF(1, 23) | SE | VE | BK)
-#define LCD_D23_ETM_DA0		(FUNC(2) | PORTF(1, 23) | SE | VE | BK)
-#define LCD_D23_GPIO		(FUNC(3) | PORTF(1, 23) | SE | VE | BK)
-#define LCD_D22			(FUNC(0) | PORTF(1, 22) | SE | VE | BK)
-#define LCD_D22_ENET1_1588_EVENT3_OUT (FUNC(1) | PORTF(1, 22) | SE | VE | BK)
-#define LCD_D22_ETM_DA1		(FUNC(2) | PORTF(1, 22) | SE | VE | BK)
-#define LCD_D22_GPIO		(FUNC(3) | PORTF(1, 22) | SE | VE | BK)
-#define LCD_D21			(FUNC(0) | PORTF(1, 21) | SE | VE | BK)
-#define LCD_D21_ENET1_1588_EVENT2_IN (FUNC(1) | PORTF(1, 21) | SE | VE | BK)
-#define LCD_D21_ETM_DA2		(FUNC(2) | PORTF(1, 21) | SE | VE | BK)
-#define LCD_D21_GPIO		(FUNC(3) | PORTF(1, 21) | SE | VE | BK)
-#define LCD_D20			(FUNC(0) | PORTF(1, 20) | SE | VE | BK)
-#define LCD_D20_ENET1_1588_EVENT2_OUT (FUNC(1) | PORTF(1, 20) | SE | VE | BK)
-#define LCD_D20_ETM_DA3		(FUNC(2) | PORTF(1, 20) | SE | VE | BK)
-#define LCD_D20_GPIO		(FUNC(3) | PORTF(1, 20) | SE | VE | BK)
-#define LCD_D19			(FUNC(0) | PORTF(1, 19) | SE | VE | BK)
-#define LCD_D19_ETM_DA4		(FUNC(2) | PORTF(1, 19) | SE | VE | BK)
-#define LCD_D19_GPIO		(FUNC(3) | PORTF(1, 19) | SE | VE | BK)
-#define LCD_D18			(FUNC(0) | PORTF(1, 18) | SE | VE | BK)
-#define LCD_D18_ETM_DA5		(FUNC(2) | PORTF(1, 18) | SE | VE | BK)
-#define LCD_D18_GPIO		(FUNC(3) | PORTF(1, 18) | SE | VE | BK)
-#define LCD_D17			(FUNC(0) | PORTF(1, 17) | SE | VE | BK)
-#define LCD_D17_ETM_DA6		(FUNC(2) | PORTF(1, 17) | SE | VE | BK)
-#define LCD_D17_GPIO		(FUNC(3) | PORTF(1, 17) | SE | VE | BK)
-#define LCD_D16			(FUNC(0) | PORTF(1, 16) | SE | VE | BK)
-#define LCD_D16_ETM_DA7		(FUNC(2) | PORTF(1, 16) | SE | VE | BK)
-#define LCD_D16_GPIO		(FUNC(3) | PORTF(1, 16) | SE | VE | BK)
-#define LCD_D15			(FUNC(0) | PORTF(1, 15) | SE | VE | BK)
-#define LCD_D15_ETM_DA15	(FUNC(2) | PORTF(1, 15) | SE | VE | BK)
-#define LCD_D15_GPIO		(FUNC(3) | PORTF(1, 15) | SE | VE | BK)
-#define LCD_D14			(FUNC(0) | PORTF(1, 14) | SE | VE | BK)
-#define LCD_D14_ETM_DA14	(FUNC(2) | PORTF(1, 14) | SE | VE | BK)
-#define LCD_D14_GPIO		(FUNC(3) | PORTF(1, 14) | SE | VE | BK)
-#define LCD_D13			(FUNC(0) | PORTF(1, 13) | SE | VE | BK)
-#define LCD_D13_ETM_DA13	(FUNC(2) | PORTF(1, 13) | SE | VE | BK)
-#define LCD_D13_GPIO		(FUNC(3) | PORTF(1, 13) | SE | VE | BK)
-#define LCD_D12			(FUNC(0) | PORTF(1, 12) | SE | VE | BK)
-#define LCD_D12_ETM_DA12	(FUNC(2) | PORTF(1, 12) | SE | VE | BK)
-#define LCD_D12_GPIO		(FUNC(3) | PORTF(1, 12) | SE | VE | BK)
-#define LCD_D11			(FUNC(0) | PORTF(1, 11) | SE | VE | BK)
-#define LCD_D11_ETM_DA11	(FUNC(2) | PORTF(1, 11) | SE | VE | BK)
-#define LCD_D11_GPIO		(FUNC(3) | PORTF(1, 11) | SE | VE | BK)
-#define LCD_D10			(FUNC(0) | PORTF(1, 10) | SE | VE | BK)
-#define LCD_D10_ETM_DA10	(FUNC(2) | PORTF(1, 10) | SE | VE | BK)
-#define LCD_D10_GPIO		(FUNC(3) | PORTF(1, 10) | SE | VE | BK)
-#define LCD_D9			(FUNC(0) | PORTF(1, 9) | SE | VE | BK)
-#define LCD_D9_ETM_DA4		(FUNC(1) | PORTF(1, 9) | SE | VE | BK)
-#define LCD_D9_ETM_DA9		(FUNC(2) | PORTF(1, 9) | SE | VE | BK)
-#define LCD_D9_GPIO		(FUNC(3) | PORTF(1, 9) | SE | VE | BK)
-#define LCD_D8			(FUNC(0) | PORTF(1, 8) | SE | VE | BK)
-#define LCD_D8_ETM_DA3		(FUNC(1) | PORTF(1, 8) | SE | VE | BK)
-#define LCD_D8_ETM_DA8		(FUNC(2) | PORTF(1, 8) | SE | VE | BK)
-#define LCD_D8_GPIO		(FUNC(3) | PORTF(1, 8) | SE | VE | BK)
-#define LCD_D7			(FUNC(0) | PORTF(1, 7) | SE | VE | BK)
-#define LCD_D7_ETM_DA7		(FUNC(2) | PORTF(1, 7) | SE | VE | BK)
-#define LCD_D7_GPIO		(FUNC(3) | PORTF(1, 7) | SE | VE | BK)
-#define LCD_D6			(FUNC(0) | PORTF(1, 6) | SE | VE | BK)
-#define LCD_D6_ETM_DA6		(FUNC(2) | PORTF(1, 6) | SE | VE | BK)
-#define LCD_D6_GPIO		(FUNC(3) | PORTF(1, 6) | SE | VE | BK)
-#define LCD_D5			(FUNC(0) | PORTF(1, 5) | SE | VE | BK)
-#define LCD_D5_ETM_DA5		(FUNC(2) | PORTF(1, 5) | SE | VE | BK)
-#define LCD_D5_GPIO		(FUNC(3) | PORTF(1, 5) | SE | VE | BK)
-#define LCD_D4			(FUNC(0) | PORTF(1, 4) | SE | VE | BK)
-#define LCD_D4_ETM_DA9		(FUNC(1) | PORTF(1, 4) | SE | VE | BK)
-#define LCD_D4_ETM_DA4		(FUNC(2) | PORTF(1, 4) | SE | VE | BK)
-#define LCD_D4_GPIO		(FUNC(3) | PORTF(1, 4) | SE | VE | BK)
-#define LCD_D3			(FUNC(0) | PORTF(1, 3) | SE | VE | BK)
-#define LCD_D3_ETM_DA8		(FUNC(1) | PORTF(1, 3) | SE | VE | BK)
-#define LCD_D3_ETM_DA3		(FUNC(2) | PORTF(1, 3) | SE | VE | BK)
-#define LCD_D3_GPIO		(FUNC(3) | PORTF(1, 3) | SE | VE | BK)
-#define LCD_D2			(FUNC(0) | PORTF(1, 2) | SE | VE | BK)
-#define LCD_D2_ETM_DA2		(FUNC(2) | PORTF(1, 2) | SE | VE | BK)
-#define LCD_D2_GPIO		(FUNC(3) | PORTF(1, 2) | SE | VE | BK)
-#define LCD_D1			(FUNC(0) | PORTF(1, 1) | SE | VE | BK)
-#define LCD_D1_ETM_DA1		(FUNC(2) | PORTF(1, 1) | SE | VE | BK)
-#define LCD_D1_GPIO		(FUNC(3) | PORTF(1, 1) | SE | VE | BK)
-#define LCD_D0			(FUNC(0) | PORTF(1, 0) | SE | VE | BK)
-#define LCD_D0_ETM_DA0		(FUNC(2) | PORTF(1, 0) | SE | VE | BK)
-#define LCD_D0_GPIO		(FUNC(3) | PORTF(1, 0) | SE | VE | BK)
-
-/* Bank 2, GPIO pins 64 ... 95 */
-#define SSP3_D3			(FUNC(0) | PORTF(2, 27) | SE | VE | PE)
-#define SSP3_D3_AUART4_CTS	(FUNC(1) | PORTF(2, 27) | SE | VE | PE)
-#define SSP3_D3_ENET1_1588_EVENT1_IN (FUNC(2) | PORTF(2, 27) | SE | VE | PE)
-#define SSP3_D3_GPIO		(FUNC(3) | PORTF(2, 27) | SE | VE | PE)
-#define SSP3_D0			(FUNC(0) | PORTF(2, 26) | SE | VE | PE)
-#define SSP3_D0_AUART4_RTS	(FUNC(1) | PORTF(2, 26) | SE | VE | PE)
-#define SSP3_D0_ENET1_1588_EVENT1_OUT (FUNC(2) | PORTF(2, 26) | SE | VE | PE)
-#define SSP3_D0_GPIO		(FUNC(3) | PORTF(2, 26) | SE | VE | PE)
-#define SSP3_CMD		(FUNC(0) | PORTF(2, 25) | SE | VE | PE)
-#define SSP3_CMD_AUART4_RX	(FUNC(1) | PORTF(2, 25) | SE | VE | PE)
-#define SSP3_CMD_ENET1_1588_EVENT0_IN (FUNC(2) | PORTF(2, 25) | SE | VE | PE)
-#define SSP3_CMD_GPIO		(FUNC(3) | PORTF(2, 25) | SE | VE | PE)
-#define SSP3_SCK		(FUNC(0) | PORTF(2, 24) | SE | VE | PE)
-#define SSP3_SCK_AUART4_TX	(FUNC(1) | PORTF(2, 24) | SE | VE | BK)
-#define SSP3_SCK_ENET1_1588_EVENT0_OUT (FUNC(2) | PORTF(2, 24) | SE | VE | BK)
-#define SSP3_SCK_GPIO		(FUNC(3) | PORTF(2, 24) | SE | VE | BK)
-#define SSP2_D5			(FUNC(0) | PORTF(2, 21) | SE | VE | PE)
-#define SSP2_D5_SSP2_D2		(FUNC(1) | PORTF(2, 21) | SE | VE | PE)
-#define SSP2_D5_USB0_OC		(FUNC(2) | PORTF(2, 21) | SE | VE | PE)
-#define SSP2_D5_GPIO		(FUNC(3) | PORTF(2, 21) | SE | VE | PE)
-#define SSP2_D4			(FUNC(0) | PORTF(2, 20) | SE | VE | PE)
-#define SSP2_D4_SSP2_D1		(FUNC(1) | PORTF(2, 20) | SE | VE | PE)
-#define SSP2_D4_USB1_OC		(FUNC(2) | PORTF(2, 20) | SE | VE | PE)
-#define SSP2_D4_GPIO		(FUNC(3) | PORTF(2, 20) | SE | VE | PE)
-#define SSP2_D3			(FUNC(0) | PORTF(2, 19) | SE | VE | PE)
-#define SSP2_D3_AUART3_TX	(FUNC(1) | PORTF(2, 19) | SE | VE | PE)
-#define SSP2_D3_SAIF1_SDATA2	(FUNC(2) | PORTF(2, 19) | SE | VE | PE)
-#define SSP2_D3_GPIO		(FUNC(3) | PORTF(2, 19) | SE | VE | PE)
-#define SSP2_D0			(FUNC(0) | PORTF(2, 18) | SE | VE | PE)
-#define SSP2_D0_AUART3_RX	(FUNC(1) | PORTF(2, 18) | SE | VE | PE)
-#define SSP2_D0_SAIF1_SDATA1	(FUNC(2) | PORTF(2, 18) | SE | VE | PE)
-#define SSP2_D0_GPIO		(FUNC(3) | PORTF(2, 18) | SE | VE | PE)
-#define SSP2_CMD		(FUNC(0) | PORTF(2, 17) | SE | VE | PE)
-#define SSP2_CMD_AUART2_TX	(FUNC(1) | PORTF(2, 17) | SE | VE | PE)
-#define SSP2_CMD_SAIF0_SDATA2	(FUNC(2) | PORTF(2, 17) | SE | VE | PE)
-#define SSP2_CMD_GPIO		(FUNC(3) | PORTF(2, 17) | SE | VE | PE)
-#define SSP2_SCK		(FUNC(0) | PORTF(2, 16) | SE | VE | BK)
-#define SSP2_SCK_AUART2_RX	(FUNC(1) | PORTF(2, 16) | SE | VE | BK)
-#define SSP2_SCK_SAIF0_SDATA1	(FUNC(2) | PORTF(2, 16) | SE | VE | BK)
-#define SSP2_SCK_GPIO		(FUNC(3) | PORTF(2, 16) | SE | VE | PE)
-#define SSP1_D3			(FUNC(0) | PORTF(2, 15) | SE | VE | PE)
-#define SSP1_D3_SSP2_D7		(FUNC(1) | PORTF(2, 15) | SE | VE | PE)
-#define SSP1_D3_ENET_1588_EVENT3_IN (FUNC(2) | PORTF(4, 15) | SE | VE | PE)
-#define SSP1_D3_GPIO		(FUNC(3) | PORTF(2, 15) | SE | VE | PE)
-#define SSP1_D0			(FUNC(0) | PORTF(2, 14) | SE | VE | PE)
-#define SSP1_D0_SSP2_D6		(FUNC(1) | PORTF(2, 14) | SE | VE | PE)
-#define SSP1_D0_ENET_1588_EVENT3_OUT (FUNC(2) | PORTF(2, 14) | SE | VE | PE)
-#define SSP1_D0_GPIO		(FUNC(3) | PORTF(2, 14) | SE | VE | PE)
-#define SSP1_CMD		(FUNC(0) | PORTF(2, 13) | SE | VE | PE)
-#define SSP1_CMD_SSP2_D2	(FUNC(1) | PORTF(2, 13) | SE | VE | PE)
-#define SSP1_CMD_ENET_1588_EVENT2_IN (FUNC(2) | PORTF(2, 13) | SE | VE | PE)
-#define SSP1_CMD_GPIO		(FUNC(3) | PORTF(2, 13) | SE | VE | PE)
-#define SSP1_SCK		(FUNC(0) | PORTF(2, 12) | SE | VE | PE)
-#define SSP1_SCK_SSP2_D1	(FUNC(1) | PORTF(2, 12) | SE | VE | PE)
-#define SSP1_SCK_ENET_1588_EVENT2_OUT (FUNC(2) | PORTF(2, 12) | SE | VE | PE)
-#define SSP1_SCK_GPIO		(FUNC(3) | PORTF(2, 12) | SE | VE | PE)
-#define SSP0_SCK		(FUNC(0) | PORTF(2, 10) | SE | VE | BK)
-#define SSP0_SCK_GPIO		(FUNC(3) | PORTF(2, 10) | SE | VE | BK)
-#define SSP0_CD			(FUNC(0) | PORTF(2, 9) | SE | VE | PE)
-#define SSP0_CD_GPIO		(FUNC(3) | PORTF(2, 9) | SE | VE | PE)
-#define SSP0_CMD		(FUNC(0) | PORTF(2, 8) | SE | VE | PE)
-#define SSP0_CMD_GPIO		(FUNC(3) | PORTF(2, 8) | SE | VE | PE)
-#define SSP0_D7			(FUNC(0) | PORTF(2, 7) | SE | VE | PE)
-#define SSP0_D7_SSP2_SCK	(FUNC(1) | PORTF(2, 7) | SE | VE | PE)
-#define SSP0_D7_GPIO		(FUNC(3) | PORTF(2, 7) | SE | VE | PE)
-#define SSP0_D6			(FUNC(0) | PORTF(2, 6) | SE | VE | PE)
-#define SSP0_D6_SSP2_CMD	(FUNC(1) | PORTF(2, 6) | SE | VE | PE)
-#define SSP0_D6_GPIO		(FUNC(3) | PORTF(2, 6) | SE | VE | PE)
-#define SSP0_D5			(FUNC(0) | PORTF(2, 5) | SE | VE | PE)
-#define SSP0_D5_SSP2_D3		(FUNC(1) | PORTF(2, 5) | SE | VE | PE)
-#define SSP0_D5_GPIO		(FUNC(3) | PORTF(2, 5) | SE | VE | PE)
-#define SSP0_D4			(FUNC(0) | PORTF(2, 4) | SE | VE | PE)
-#define SSP0_D4_SSP2_D0		(FUNC(1) | PORTF(2, 4) | SE | VE | PE)
-#define SSP0_D4_GPIO		(FUNC(3) | PORTF(2, 4) | SE | VE | PE)
-#define SSP0_D3			(FUNC(0) | PORTF(2, 3) | SE | VE | PE)
-#define SSP0_D3_GPIO		(FUNC(3) | PORTF(2, 3) | SE | VE | PE)
-#define SSP0_D2			(FUNC(0) | PORTF(2, 2) | SE | VE | PE)
-#define SSP0_D2_GPIO		(FUNC(3) | PORTF(2, 2) | SE | VE | PE)
-#define SSP0_D1			(FUNC(0) | PORTF(2, 1) | SE | VE | PE)
-#define SSP0_D1_GPIO		(FUNC(3) | PORTF(2, 1) | SE | VE | PE)
-#define SSP0_D0			(FUNC(0) | PORTF(2, 0) | SE | VE | PE)
-#define SSP0_D0_GPIO		(FUNC(3) | PORTF(2, 0) | SE | VE | PE)
-
-/* Bank 3, GPIO pins 96 ... 127 */
-#define LCD_RESET		(FUNC(0) | PORTF(3, 30) | SE | VE | BK)
-#define LCD_RESET_LCD_VSYNC	(FUNC(1) | PORTF(3, 30) | SE | VE | BK)
-#define LCD_RESET_GPIO		(FUNC(3) | PORTF(3, 30) | SE | VE | BK)
-#define PWM4			(FUNC(0) | PORTF(3, 29) | SE | VE | BK)
-#define PWM4_GPIO		(FUNC(3) | PORTF(3, 29) | SE | VE | BK)
-#define PWM3			(FUNC(0) | PORTF(3, 28) | SE | VE | BK)
-#define PWM3_GPIO		(FUNC(3) | PORTF(3, 28) | SE | VE | BK)
-#define SPDIF_TX		(FUNC(0) | PORTF(3, 27) | SE | VE | BK)
-#define SPDIF_TX_ENET1_RX_ER	(FUNC(2) | PORTF(3, 27) | SE | VE | BK)
-#define SPDIF_TX_GPIO		(FUNC(3) | PORTF(3, 27) | SE | VE | BK)
-#define SAIF1_SDATA0		(FUNC(0) | PORTF(3, 26) | SE | VE | BK)
-#define SAIF1_SDATA0_PWM7	(FUNC(1) | PORTF(3, 26) | SE | VE | BK)
-#define SAIF1_SDATA0_SAIF0_SDATA1 (FUNC(2) | PORTF(3, 26) | SE | VE | BK)
-#define SAIF1_SDATA0_GPIO	(FUNC(3) | PORTF(3, 26) | SE | VE | BK)
-#define I2C0_SDA		(FUNC(0) | PORTF(3, 25) | SE | VE | BK)
-#define I2C0_SDA_TIMROT_ROTARYB	(FUNC(1) | PORTF(3, 25) | SE | VE | BK)
-#define I2C0_SDA_DUART_TX	(FUNC(2) | PORTF(3, 25) | SE | VE | BK)
-#define I2C0_SDA_GPIO		(FUNC(3) | PORTF(3, 25) | SE | VE | BK)
-#define I2C0_SCL		(FUNC(0) | PORTF(3, 24) | SE | VE | BK)
-#define I2C0_SCL_TIMROT_ROTARYA	(FUNC(1) | PORTF(3, 24) | SE | VE | BK)
-#define I2C0_SCL_DUART_RX	(FUNC(2) | PORTF(3, 24) | SE | VE | BK)
-#define I2C0_SCL_GPIO		(FUNC(3) | PORTF(3, 24) | SE | VE | BK)
-#define SAIF0_SDATA0		(FUNC(0) | PORTF(3, 23) | SE | VE | BK)
-#define SAIF0_SDATA0_PWM6	(FUNC(1) | PORTF(3, 23) | SE | VE | BK)
-#define SAIF0_SDATA0_AUART4_TX	(FUNC(2) | PORTF(3, 23) | SE | VE | BK)
-#define SAIF0_SDATA0_GPIO	(FUNC(3) | PORTF(3, 23) | SE | VE | BK)
-#define SAIF0_BITCLK		(FUNC(0) | PORTF(3, 22) | SE | VE | BK)
-#define SAIF0_BITCLK_PWM5	(FUNC(1) | PORTF(3, 22) | SE | VE | BK)
-#define SAIF0_BITCLK_AUART4_RX	(FUNC(2) | PORTF(3, 22) | SE | VE | BK)
-#define SAIF0_BITCLK_GPIO	(FUNC(3) | PORTF(3, 22) | SE | VE | BK)
-#define SAIF0_LRCLK		(FUNC(0) | PORTF(3, 21) | SE | VE | BK)
-#define SAIF0_LRCLK_PWM4	(FUNC(1) | PORTF(3, 21) | SE | VE | BK)
-#define SAIF0_LRCLK_AUART4_RTS	(FUNC(2) | PORTF(3, 21) | SE | VE | BK)
-#define SAIF0_LRCLK_GPIO	(FUNC(3) | PORTF(3, 21) | SE | VE | BK)
-#define SAIF0_MCLK		(FUNC(0) | PORTF(3, 20) | SE | VE | BK)
-#define SAIF0_MCLK_PWM3		(FUNC(1) | PORTF(3, 20) | SE | VE | BK)
-#define SAIF0_MCLK_AUART4_CTS	(FUNC(2) | PORTF(3, 20) | SE | VE | BK)
-#define SAIF0_MCLK_GPIO		(FUNC(3) | PORTF(3, 20) | SE | VE | BK)
-#define PWM2			(FUNC(0) | PORTF(3, 18) | SE | VE | PE)
-#define PWM2_USB0_ID		(FUNC(1) | PORTF(3, 18) | SE | VE | PE)
-#define PWM2_USB1_OC		(FUNC(2) | PORTF(3, 18) | SE | VE | PE)
-#define PWM2_GPIO		(FUNC(3) | PORTF(3, 18) | SE | VE | PE)
-#define PWM1			(FUNC(0) | PORTF(3, 17) | SE | VE | BK)
-#define PWM1_I2C1_SDA		(FUNC(1) | PORTF(3, 17) | SE | VE | BK)
-#define PWM1_DUART_TX		(FUNC(2) | PORTF(3, 17) | SE | VE | BK)
-#define PWM1_GPIO		(FUNC(3) | PORTF(3, 17) | SE | VE | BK)
-#define PWM0			(FUNC(0) | PORTF(3, 16) | SE | VE | BK)
-#define PWM0_I2C1_SCL		(FUNC(1) | PORTF(3, 16) | SE | VE | BK)
-#define PWM0_DUART_RX		(FUNC(2) | PORTF(3, 16) | SE | VE | BK)
-#define PWM0_GPIO		(FUNC(3) | PORTF(3, 16) | SE | VE | BK)
-#define AUART3_RTS		(FUNC(0) | PORTF(3, 15) | SE | VE | BK)
-#define AUART3_RTS_CAN1_RX	(FUNC(1) | PORTF(3, 15) | SE | VE | BK)
-#define AUART3_RTS_ENET0_1588_EVENT1_IN	(FUNC(2) | PORTF(3, 15) | SE | VE | BK)
-#define AUART3_RTS_GPIO		(FUNC(3) | PORTF(3, 15) | SE | VE | BK)
-#define AUART3_CTS		(FUNC(0) | PORTF(3, 14) | SE | VE | BK)
-#define AUART3_CTS_CAN1_TX	(FUNC(1) | PORTF(3, 14) | SE | VE | BK)
-#define AUART3_CTS_ENET0_1588_EVENT1_OUT (FUNC(2) | PORTF(3, 14) | SE | VE | BK)
-#define AUART3_CTS_GPIO		(FUNC(3) | PORTF(3, 14) | SE | VE | BK)
-#define AUART3_TX		(FUNC(0) | PORTF(3, 13) | SE | VE | BK)
-#define AUART3_TX_CAN0_RX	(FUNC(1) | PORTF(3, 13) | SE | VE | BK)
-#define AUART3_TX_ENET0_1588_EVENT0_IN	(FUNC(2) | PORTF(3, 13) | SE | VE | BK)
-#define AUART3_TX_GPIO		(FUNC(3) | PORTF(3, 13) | SE | VE | BK)
-#define AUART3_RX		(FUNC(0) | PORTF(3, 12) | SE | VE | BK)
-#define AUART3_RX_CAN0_TX	(FUNC(1) | PORTF(3, 12) | SE | VE | BK)
-#define AUART3_RX_ENET0_1588_EVENT0_OUT	(FUNC(2) | PORTF(3, 12) | SE | VE | BK)
-#define AUART3_RX_GPIO		(FUNC(3) | PORTF(3, 12) | SE | VE | BK)
-#define AUART2_RTS		(FUNC(0) | PORTF(3, 11) | SE | VE | BK)
-#define AUART2_RTS_I2C1_SDA	(FUNC(1) | PORTF(3, 11) | SE | VE | BK)
-#define AUART2_RTS_SAIF1_IRCLK	(FUNC(2) | PORTF(3, 11) | SE | VE | BK)
-#define AUART2_RTS_GPIO		(FUNC(3) | PORTF(3, 11) | SE | VE | BK)
-#define AUART2_CTS		(FUNC(0) | PORTF(3, 10) | SE | VE | BK)
-#define AUART2_CTS_I2C1_SCL	(FUNC(1) | PORTF(3, 10) | SE | VE | BK)
-#define AUART2_CTS_SAIF1_BITCLK	(FUNC(2) | PORTF(3, 10) | SE | VE | BK)
-#define AUART2_CTS_GPIO		(FUNC(3) | PORTF(3, 10) | SE | VE | BK)
-#define AUART2_TX		(FUNC(0) | PORTF(3, 9) | SE | VE | PE)
-#define AUART2_TX_SSP3_D2	(FUNC(1) | PORTF(3, 9) | SE | VE | PE)
-#define AUART2_TX_SSP3_D5	(FUNC(2) | PORTF(3, 9) | SE | VE | PE)
-#define AUART2_TX_GPIO		(FUNC(3) | PORTF(3, 9) | SE | VE | PE)
-#define AUART2_RX		(FUNC(0) | PORTF(3, 8) | SE | VE | PE)
-#define AUART2_RX_SSP3_D1	(FUNC(1) | PORTF(3, 8) | SE | VE | PE)
-#define AUART2_RX_SSP3_D4	(FUNC(2) | PORTF(3, 8) | SE | VE | PE)
-#define AUART2_RX_GPIO		(FUNC(3) | PORTF(3, 8) | SE | VE | PE)
-#define AUART1_RTS		(FUNC(0) | PORTF(3, 7) | SE | VE | PE)
-#define AUART1_RTS_USB0_ID	(FUNC(1) | PORTF(3, 7) | SE | VE | PE)
-#define AUART1_RTS_ROTARYB	(FUNC(2) | PORTF(3, 7) | SE | VE | PE)
-#define AUART1_RTS_GPIO		(FUNC(3) | PORTF(3, 7) | SE | VE | PE)
-#define AUART1_CTS		(FUNC(0) | PORTF(3, 6) | SE | VE | PE)
-#define AUART1_CTS_USB0_OC	(FUNC(1) | PORTF(3, 6) | SE | VE | PE)
-#define AUART1_CTS_ROTARYA	(FUNC(2) | PORTF(3, 6) | SE | VE | PE)
-#define AUART1_CTS_GPIO		(FUNC(3) | PORTF(3, 6) | SE | VE | PE)
-#define AUART1_TX		(FUNC(0) | PORTF(3, 5) | SE | VE | BK)
-#define AUART1_TX_SSP3_CD	(FUNC(1) | PORTF(3, 5) | SE | VE | BK)
-#define AUART1_TX_PWM1		(FUNC(2) | PORTF(3, 5) | SE | VE | BK)
-#define AUART1_TX_GPIO		(FUNC(3) | PORTF(3, 5) | SE | VE | BK)
-#define AUART1_RX		(FUNC(0) | PORTF(3, 4) | SE | VE | BK)
-#define AUART1_RX_SSP2_CD	(FUNC(1) | PORTF(3, 4) | SE | VE | BK)
-#define AUART1_RX_PWM0		(FUNC(2) | PORTF(3, 4) | SE | VE | BK)
-#define AUART1_RX_GPIO		(FUNC(3) | PORTF(3, 4) | SE | VE | BK)
-#define AUART0_RTS		(FUNC(0) | PORTF(3, 3) | SE | VE | BK)
-#define AUART0_RTS_AUART4_TX	(FUNC(1) | PORTF(3, 3) | SE | VE | BK)
-#define AUART0_RTS_DUART_TX	(FUNC(2) | PORTF(3, 3) | SE | VE | BK)
-#define AUART0_RTS_GPIO		(FUNC(3) | PORTF(3, 3) | SE | VE | BK)
-#define AUART0_CTS		(FUNC(0) | PORTF(3, 2) | SE | VE | BK)
-#define AUART0_CTS_AUART4_RX	(FUNC(1) | PORTF(3, 2) | SE | VE | BK)
-#define AUART0_CTS_DUART_RX	(FUNC(2) | PORTF(3, 2) | SE | VE | BK)
-#define AUART0_CTS_GPIO		(FUNC(3) | PORTF(3, 2) | SE | VE | BK)
-#define AUART0_TX		(FUNC(0) | PORTF(3, 1) | SE | VE | BK)
-#define AUART0_TX_I2C0_SDA	(FUNC(1) | PORTF(3, 1) | SE | VE | BK)
-#define AUART0_TX_DUART_RTS	(FUNC(2) | PORTF(3, 1) | SE | VE | BK)
-#define AUART0_TX_GPIO		(FUNC(3) | PORTF(3, 1) | SE | VE | BK)
-#define AUART0_RX		(FUNC(0) | PORTF(3, 0) | SE | VE | BK)
-#define AUART0_RX_I2C0_SCL	(FUNC(1) | PORTF(3, 0) | SE | VE | BK)
-#define AUART0_RX_DUART_CTS	(FUNC(2) | PORTF(3, 0) | SE | VE | BK)
-#define AUART0_RX_GPIO		(FUNC(3) | PORTF(3, 0) | SE | VE | BK)
-
-/* Bank 4, GPIO pins 128 ... 159 */
-#define JTAG_RTCK		(FUNC(0) | PORTF(4, 20) | SE | VE | BK)
-#define JTAG_RTCK_GPIO		(FUNC(3) | PORTF(4, 20) | SE | VE | BK)
-#define ENET_CLK		(FUNC(0) | PORTF(4, 16) | SE | VE | BK)
-#define ENET_CLK_GPIO		(FUNC(3) | PORTF(4, 16) | SE | VE | BK)
-#define ENET0_CRS		(FUNC(0) | PORTF(4, 15) | SE | VE | BK)
-#define ENET0_CRS_ENET1_RX_EN	(FUNC(1) | PORTF(4, 15) | SE | VE | BK)
-#define ENET0_CRS_ENET0_1588_EVENT3_IN (FUNC(2) | PORTF(4, 15) | SE | VE | BK)
-#define ENET0_CRS_GPIO		(FUNC(3) | PORTF(4, 15) | SE | VE | BK)
-#define ENET0_COL		(FUNC(0) | PORTF(4, 14) | SE | VE | BK)
-#define ENET0_COL_ENET1_TX_EN	(FUNC(1) | PORTF(4, 14) | SE | VE | BK)
-#define ENET0_COL_1588_EVENT3_OUT (FUNC(2) | PORTF(4, 14) | SE | VE | BK)
-#define ENET0_COL_GPIO		(FUNC(3) | PORTF(4, 14) | SE | VE | BK)
-#define ENET0_RX_CLK		(FUNC(0) | PORTF(4, 13) | SE | VE | BK)
-#define ENET0_RX_CLK_RX_ER	(FUNC(1) | PORTF(4, 13) | SE | VE | BK)
-#define ENET0_RX_ENET0_1588_EVENT2_IN (FUNC(2) | PORTF(4, 13) | SE | VE | BK)
-#define ENET0_RX_CLK_GPIO	(FUNC(3) | PORTF(4, 13) | SE | VE | BK)
-#define ENET0_TXD3		(FUNC(0) | PORTF(4, 12) | SE | VE | BK)
-#define ENET0_TXD3_ENET1_TXD1	(FUNC(1) | PORTF(4, 12) | SE | VE | BK)
-#define ENET0_TXD3_ENET0_1588_EVENT1_IN (FUNC(2) | PORTF(4, 12) | SE | VE | BK)
-#define ENET0_TXD3_GPIO		(FUNC(3) | PORTF(4, 12) | SE | VE | BK)
-#define ENET0_TXD2		(FUNC(0) | PORTF(4, 11) | SE | VE | BK)
-#define ENET0_TXD2_ENET1_TXD0	(FUNC(1) | PORTF(4, 11) | SE | VE | BK)
-#define ENET0_TXD2_ENET0_1588_EVENT1_OUT (FUNC(2) | PORTF(4, 11) | SE | VE | BK)
-#define ENET0_TXD2_GPIO		(FUNC(3) | PORTF(4, 11) | SE | VE | BK)
-#define ENET0_RXD3		(FUNC(0) | PORTF(4, 10) | SE | VE | BK)
-#define ENET0_RXD3_ENET1_RXD1	(FUNC(1) | PORTF(4, 10) | SE | VE | BK)
-#define ENET0_RXD3_ENET0_1588_EVENT0_IN (FUNC(2) | PORTF(4, 10) | SE | VE | BK)
-#define ENET0_RXD3_GPIO		(FUNC(3) | PORTF(4, 10) | SE | VE | BK)
-#define ENET0_RXD2		(FUNC(0) | PORTF(4, 9) | SE | VE | BK)
-#define ENET0_RXD2_ENET1_RXD0	(FUNC(1) | PORTF(4, 9) | SE | VE | BK)
-#define ENET0_RXD2_ENET0_1588_EVENT0_OUT (FUNC(2) | PORTF(4, 9) | SE | VE | BK)
-#define ENET0_RXD2_GPIO		(FUNC(3) | PORTF(4, 9) | SE | VE | BK)
-#define ENET0_TXD1		(FUNC(0) | PORTF(4, 8) | SE | VE | PE)
-#define ENET0_TXD1_GPMI_READY7	(FUNC(1) | PORTF(4, 8) | SE | VE | PE)
-#define ENET0_TXD1_GPIO		(FUNC(3) | PORTF(4, 8) | SE | VE | PE)
-#define ENET0_TXD0		(FUNC(0) | PORTF(4, 7) | SE | VE | PE)
-#define ENET0_TXD0_GPMI_READY6	(FUNC(1) | PORTF(4, 7) | SE | VE | PE)
-#define ENET0_TXD0_GPIO		(FUNC(3) | PORTF(4, 7) | SE | VE | PE)
-#define ENET0_TX_EN		(FUNC(0) | PORTF(4, 6) | SE | VE | PE)
-#define ENET0_TX_EN_GPMI_READY5	(FUNC(1) | PORTF(4, 6) | SE | VE | PE)
-#define ENET0_TX_EN_GPIO	(FUNC(3) | PORTF(4, 6) | SE | VE | PE)
-#define ENET0_TX_CLK		(FUNC(0) | PORTF(4, 5) | SE | VE | BK)
-#define ENET0_TX_CLK_HSADC_TRIGGER (FUNC(1) | PORTF(4, 5) | SE | VE | BK)
-#define ENET0_TX_CLK_ENET0_1588_EVENT2_OUT (FUNC(2) | PORTF(4, 5) | SE | VE | BK)
-#define ENET0_TX_CLK_GPIO	(FUNC(3) | PORTF(4, 5) | SE | VE | BK)
-#define ENET0_RXD1		(FUNC(0) | PORTF(4, 4) | SE | VE | PE)
-#define ENET0_RXD1_GPMI_READY4	(FUNC(1) | PORTF(4, 4) | SE | VE | PE)
-#define ENET0_RXD1_GPIO		(FUNC(3) | PORTF(4, 4) | SE | VE | PE)
-#define ENET0_RXD0		(FUNC(0) | PORTF(4, 3) | SE | VE | PE)
-#define ENET0_RXD0_GPMI_CE7N	(FUNC(1) | PORTF(4, 3) | SE | VE | PE)
-#define ENET0_RXD0_SAIF1_SDATA2	(FUNC(2) | PORTF(4, 3) | SE | VE | PE)
-#define ENET0_RXD0_GPIO		(FUNC(3) | PORTF(4, 3) | SE | VE | PE)
-#define ENET0_RX_EN		(FUNC(0) | PORTF(4, 2) | SE | VE | PE)
-#define ENET0_RX_EN_GPMI_CE6N	(FUNC(1) | PORTF(4, 2) | SE | VE | PE)
-#define ENET0_RX_EN_SAIF1_SDATA1 (FUNC(2) | PORTF(4, 2) | SE | VE | PE)
-#define ENET0_RX_EN_GPIO	(FUNC(3) | PORTF(4, 2) | SE | VE | PE)
-#define ENET0_MDIO		(FUNC(0) | PORTF(4, 1) | SE | VE | PE)
-#define ENET0_MDIO_GPMI_CE5N	(FUNC(1) | PORTF(4, 1) | SE | VE | PE)
-#define ENET0_MDIO_SAIF0_SDATA2	(FUNC(2) | PORTF(4, 1) | SE | VE | PE)
-#define ENET0_MDIO_GPIO		(FUNC(3) | PORTF(4, 1) | SE | VE | PE)
-#define ENET0_MDC		(FUNC(0) | PORTF(4, 0) | SE | VE | PE)
-#define ENET0_MDC_GPMI_CE4N	(FUNC(1) | PORTF(4, 0) | SE | VE | PE)
-#define ENET0_MDC_SAIF0_SDATA1	(FUNC(2) | PORTF(4, 0) | SE | VE | PE)
-#define ENET0_MDC_GPIO		(FUNC(3) | PORTF(4, 0) | SE | VE | PE)
-
-/*
- * Bank 5, GPIO pins 160 ... 191
- * Note: These pins are disabled instead of being GPIOs
- */
-#define EMI_DDR_OPEN		(FUNC(0) | PORTF(5, 26) | BK)
-#define EMI_DDR_OPEN_OFF	(FUNC(3) | PORTF(5, 26) | BK)
-#define EMI_DSQ1		(FUNC(0) | PORTF(5, 23) | BK)
-#define EMI_DSQ1_OFF		(FUNC(3) | PORTF(5, 23) | BK)
-#define EMI_DSQ0		(FUNC(0) | PORTF(5, 22) | BK)
-#define EMI_DSQ0_OFF		(FUNC(3) | PORTF(5, 22) | BK)
-#define EMI_CLK			(FUNC(0) | PORTF(5, 21) | BK)
-#define EMI_CLK_OFF		(FUNC(3) | PORTF(5, 21) | BK)
-#define EMI_DDR_OPEN_FB		(FUNC(0) | PORTF(5, 20) | BK)
-#define EMI_DDR_OPEN_FB_OFF	(FUNC(3) | PORTF(5, 20) | BK)
-#define EMI_DQM1		(FUNC(0) | PORTF(5, 19) | BK)
-#define EMI_DQM1_OFF		(FUNC(3) | PORTF(5, 19) | BK)
-#define EMI_ODT1		(FUNC(0) | PORTF(5, 18) | BK)
-#define EMI_ODT1_OFF		(FUNC(3) | PORTF(5, 18) | BK)
-#define EMI_DQM0		(FUNC(0) | PORTF(5, 17) | BK)
-#define EMI_DQM0_OFF		(FUNC(3) | PORTF(5, 17) | BK)
-#define EMI_ODT0		(FUNC(0) | PORTF(5, 16) | BK)
-#define EMI_ODT0_OFF		(FUNC(3) | PORTF(5, 16) | BK)
-#define EMI_DATA15		(FUNC(0) | PORTF(5, 15) | BK)
-#define EMI_DATA15_OFF		(FUNC(3) | PORTF(5, 15) | BK)
-#define EMI_DATA14		(FUNC(0) | PORTF(5, 14) | BK)
-#define EMI_DATA14_OFF		(FUNC(3) | PORTF(5, 14) | BK)
-#define EMI_DATA13		(FUNC(0) | PORTF(5, 13) | BK)
-#define EMI_DATA13_OFF		(FUNC(3) | PORTF(5, 13) | BK)
-#define EMI_DATA12		(FUNC(0) | PORTF(5, 12) | BK)
-#define EMI_DATA12_OFF		(FUNC(3) | PORTF(5, 12) | BK)
-#define EMI_DATA11		(FUNC(0) | PORTF(5, 11) | BK)
-#define EMI_DATA10_OFF		(FUNC(3) | PORTF(5, 10) | BK)
-#define EMI_DATA10		(FUNC(0) | PORTF(5, 10) | BK)
-#define EMI_DATA10_OFF		(FUNC(3) | PORTF(5, 10) | BK)
-#define EMI_DATA9		(FUNC(0) | PORTF(5, 9) | BK)
-#define EMI_DATA9_OFF		(FUNC(3) | PORTF(5, 9) | BK)
-#define EMI_DATA8		(FUNC(0) | PORTF(5, 8) | BK)
-#define EMI_DATA8_OFF		(FUNC(3) | PORTF(5, 8) | BK)
-#define EMI_DATA7		(FUNC(0) | PORTF(5, 7) | BK)
-#define EMI_DATA7_OFF		(FUNC(3) | PORTF(5, 7) | BK)
-#define EMI_DATA6		(FUNC(0) | PORTF(5, 6) | BK)
-#define EMI_DATA6_OFF		(FUNC(3) | PORTF(5, 6) | BK)
-#define EMI_DATA5		(FUNC(0) | PORTF(5, 5) | BK)
-#define EMI_DATA5_OFF		(FUNC(3) | PORTF(5, 5) | BK)
-#define EMI_DATA4		(FUNC(0) | PORTF(5, 4) | BK)
-#define EMI_DATA4_OFF		(FUNC(3) | PORTF(5, 4) | BK)
-#define EMI_DATA3		(FUNC(0) | PORTF(5, 3) | BK)
-#define EMI_DATA3_OFF		(FUNC(3) | PORTF(5, 3) | BK)
-#define EMI_DATA2		(FUNC(0) | PORTF(5, 2) | BK)
-#define EMI_DATA2_OFF		(FUNC(3) | PORTF(5, 2) | BK)
-#define EMI_DATA1		(FUNC(0) | PORTF(5, 1) | BK)
-#define EMI_DATA1_OFF		(FUNC(3) | PORTF(5, 1) | BK)
-#define EMI_DATA0		(FUNC(0) | PORTF(5, 0) | BK)
-#define EMI_DATA0_OFF		(FUNC(3) | PORTF(5, 0) | BK)
-
-/*
- * Bank 6, GPIO pins 192 ... 223
- * Note: This pins are disabled instead of being GPIOs
- */
-#define EMI_CKE			(FUNC(0) | PORTF(6, 24) | BK)
-#define EMI_CKE_OFF		(FUNC(3) | PORTF(6, 24) | BK)
-#define EMI_CE1N		(FUNC(0) | PORTF(6, 23) | BK)
-#define EMI_CE1N_OFF		(FUNC(3) | PORTF(6, 23) | BK)
-#define EMI_CE0N		(FUNC(0) | PORTF(6, 22) | BK)
-#define EMI_CE0N_OFF		(FUNC(3) | PORTF(6, 22) | BK)
-#define EMI_WEN			(FUNC(0) | PORTF(6, 21) | BK)
-#define EMI_WEN_OFF		(FUNC(3) | PORTF(6, 21) | BK)
-#define EMI_RASN		(FUNC(0) | PORTF(6, 20) | BK)
-#define EMI_RASN_OFF		(FUNC(3) | PORTF(6, 20) | BK)
-#define EMI_CASN		(FUNC(0) | PORTF(6, 19) | BK)
-#define EMI_CASN_OFF		(FUNC(3) | PORTF(6, 19) | BK)
-#define EMI_BA2			(FUNC(0) | PORTF(6, 18) | BK)
-#define EMI_BA2_OFF		(FUNC(3) | PORTF(6, 18) | BK)
-#define EMI_BA1			(FUNC(0) | PORTF(6, 17) | BK)
-#define EMI_BA1_OFF		(FUNC(3) | PORTF(6, 17) | BK)
-#define EMI_BA0			(FUNC(0) | PORTF(6, 16) | BK)
-#define EMI_BA0_OFF		(FUNC(3) | PORTF(6, 16) | BK)
-#define EMI_A14			(FUNC(0) | PORTF(6, 14) | BK)
-#define EMI_A14_OFF		(FUNC(3) | PORTF(6, 14) | BK)
-#define EMI_A13			(FUNC(0) | PORTF(6, 13) | BK)
-#define EMI_A13_OFF		(FUNC(3) | PORTF(6, 13) | BK)
-#define EMI_A12			(FUNC(0) | PORTF(6, 12) | BK)
-#define EMI_A12_OFF		(FUNC(3) | PORTF(6, 12) | BK)
-#define EMI_A11			(FUNC(0) | PORTF(6, 11) | BK)
-#define EMI_A11_OFF		(FUNC(3) | PORTF(6, 11) | BK)
-#define EMI_A10			(FUNC(0) | PORTF(6, 10) | BK)
-#define EMI_A10_OFF		(FUNC(3) | PORTF(6, 10) | BK)
-#define EMI_A9			(FUNC(0) | PORTF(6, 9) | BK)
-#define EMI_A9_OFF		(FUNC(3) | PORTF(6, 9) | BK)
-#define EMI_A8			(FUNC(0) | PORTF(6, 8) | BK)
-#define EMI_A8_OFF		(FUNC(3) | PORTF(6, 8) | BK)
-#define EMI_A7			(FUNC(0) | PORTF(6, 7) | BK)
-#define EMI_A7_OFF		(FUNC(3) | PORTF(6, 7) | BK)
-#define EMI_A6			(FUNC(0) | PORTF(6, 6) | BK)
-#define EMI_A6_OFF		(FUNC(3) | PORTF(6, 6) | BK)
-#define EMI_A5			(FUNC(0) | PORTF(6, 5) | BK)
-#define EMI_A5_OFF		(FUNC(3) | PORTF(6, 5) | BK)
-#define EMI_A4			(FUNC(0) | PORTF(6, 4) | BK)
-#define EMI_A4_OFF		(FUNC(3) | PORTF(6, 4) | BK)
-#define EMI_A3			(FUNC(0) | PORTF(6, 3) | BK)
-#define EMI_A3_OFF		(FUNC(3) | PORTF(6, 3) | BK)
-#define EMI_A2			(FUNC(0) | PORTF(6, 2) | BK)
-#define EMI_A2_OFF		(FUNC(3) | PORTF(6, 2) | BK)
-#define EMI_A1			(FUNC(0) | PORTF(6, 1) | BK)
-#define EMI_A1_OFF		(FUNC(3) | PORTF(6, 1) | BK)
-#define EMI_A0			(FUNC(0) | PORTF(6, 0) | BK)
-#define EMI_A0_OFF		(FUNC(3) | PORTF(6, 0) | BK)
-
-#endif /* __MACH_IOMUX_IMX28_H */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
deleted file mode 100644
index 0091dbae11..0000000000
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_MACH_IOMUX_H
-#define __ASM_MACH_IOMUX_H
-
-#include <types.h>
-
-/*
- * The muxable pins on i.MX23 are organized in 4 banks. On i.MX28 there are 7
- * banks. Each bank has up to 32 pins each. Furthermore for each pin some of the
- * following properties can be configured:
- *  - drive strength: 4 mA, 8 mA, 12 mA or 16 mA
- *  - pull up enabled or bit keeper enabled (a pin cannot have both)
- *  - voltage: 1.8 V, 2.5 V (i.MX23 only) or 3.3 V (i.MX28 only)
- *  - function: 0..3, with 3 being the GPIO functionality
- *
- * So a configuration for a given pin can be described in an unsigned integer of
- * length 32:
- *  - [ 4: 0] bank pin
- *  - [ 7: 5] bank
- *  - [    8] 1 iff pin has a switchable pull up
- *  - [    9] 1 iff pin has a switchable bit keeper
- *  - [   10] 1 iff pin has switchable drive strength
- *  - [   11] 1 iff pin has switchable voltage
- *  - [13:12] function
- *  - [   14] 1 for enabled pull up
- *  - [   15] 1 iff [14] is a valid pull up value
- *  - [   16] 1 for enabled bit keeper
- *  - [   17] 1 iff [16] is a valid bit keeper value
- *  - [19:18] value for drive strength i -> i * 4 mA
- *  - [   20] 1 iff [19:18] is valid
- *  - [   21] 0 for 1.8 V, 1 for 2.5 V resp. 3.3 V
- *  - [   22] 1 iff [21] is valid
- *  - [   23] 1 iff configure as GPIO out if function == 3 (i.e. GPIO)
- *  - [   24] initial value iff configured as GPIO out
- *  - [   25] error
- */
-
-#define BANKPIN(p)	(((p) & 31) | ERROR((p) & ~31))
-#define BANK(b)		((((b) & 7) << 5) | (ERROR((b) & ~7)))
-#define PE		(1 << 8)
-#define BK		(1 << 9)
-#define SE		(1 << 10)
-#define VE		(1 << 11)
-#define FUNC(f)		((((f) & 3) << 12) | (ERROR((f) & ~3)))
-#define PULLUP(p)	((((p) & 1) << 14) | PEVALID | ERROR((p) & ~1))
-#define PEVALID		(1 << 15)
-#define BITKEEPER(b)	((((b) & 1) << 16) | BKVALID | ERROR((b) & ~1))
-#define BKVALID		(1 << 17)
-#define STRENGTH(s)	((((s) & 3) << 18) | SEVALID | ERROR((s) & ~3))
-#define S4MA		0
-#define S8MA		1
-#define S12MA		2
-#define S16MA		3
-#define SEVALID		(1 << 20)
-#define VOLTAGE(v)	((((v) & 1) << 21) | VEVALID | ERROR((v) & ~1))
-#define VE_1_8V		VOLTAGE(0)
-#define VEVALID		(1 << 22)
-
-#define GPIO_OUT	(1 << 23)
-#define GPIO_IN		(0 << 23)
-#define GPIO_VALUE(v)	((((v) & 1) << 24) | ERROR((v) & ~1))
-
-#define ERROR(x)	(!!(x) << 25)
-
-#define GET_GPIO_NO(m)	((m) & 0xff)
-#define GET_FUNC(m)	(((m) >> 12) & 3)
-#define PE_PRESENT(m)	((m) & PE)
-#define GET_PULLUP(m)	(((m) >> 14) & 1)
-#define BK_PRESENT(m)	((m) & BK)
-#define GET_BITKEEPER(m)(((m) >> 16) & 1)
-#define SE_PRESENT(m)	((m) & SE)
-#define GET_STRENGTH(m)	(((m) >> 18) & 3)
-#define VE_PRESENT(m)	((m) & VE)
-#define GET_VOLTAGE(m)	(((m) >> 21) & 1)
-#define GET_GPIODIR(m)	(!!((m) & GPIO_OUT))
-#define GET_GPIOVAL(m)	(!!((m) & GPIO_VALUE(1)))
-#define IS_GPIO		3
-
-#if defined CONFIG_ARCH_IMX23
-/*
- * The pin definition of i.MX23 are strange. Bank 0's pins 0 .. 15 are defined
- * using PORTF(0, 0) .. PORTF(0, 15). Its pins 16 .. 31 however use PORTF(1, 0)
- * .. PORTF(1, 15). So the PORTF macro is more ugly than necessary.
- */
-# define PORTF(bank,bit)	(BANK((bank) / 2) | BANKPIN((((bank) & 1) << 4) | (bit)) | ERROR((bit) & ~15) | ERROR((bank) & ~7))
-# define VE_2_5V		VOLTAGE(0)
-# include <mach/iomux-imx23.h>
-#endif
-
-#if defined CONFIG_ARCH_IMX28
-# define PORTF(bank,bit)	(BANK(bank) | BANKPIN(bit))
-# define VE_3_3V	VOLTAGE(1)
-# include <mach/iomux-imx28.h>
-#endif
-
-void imx_gpio_mode(uint32_t);
-
-#endif /* __ASM_MACH_IOMUX_H */
diff --git a/arch/arm/mach-mxs/include/mach/mci.h b/arch/arm/mach-mxs/include/mach/mci.h
deleted file mode 100644
index c47c24cba8..0000000000
--- a/arch/arm/mach-mxs/include/mach/mci.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_MMC_H
-#define __MACH_MMC_H
-
-struct mxs_mci_platform_data {
-	const char *devname;
-	unsigned caps;	/**< supported operating modes (MMC_MODE_*) */
-	unsigned voltages; /**< supported voltage range (MMC_VDD_*) */
-	unsigned f_min;	/**< min operating frequency in Hz (0 -> no limit) */
-	unsigned f_max;	/**< max operating frequency in Hz (0 -> no limit) */
-	/* TODO */
-	/* function to modify the voltage */
-	/* function to switch the voltage */
-	/* function to detect the presence of a SD card in the socket */
-};
-
-#endif /* __MACH_MMC_H */
diff --git a/arch/arm/mach-mxs/include/mach/ocotp.h b/arch/arm/mach-mxs/include/mach/ocotp.h
deleted file mode 100644
index 86b30c96e1..0000000000
--- a/arch/arm/mach-mxs/include/mach/ocotp.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Header file for mxs ocotp driver - same license as driver
- *
- * Copyright (C) 2012 by Wolfram Sang, Pengutronix e.K.
- */
-
-#ifndef __MACH_OCOTP_H
-#define __MACH_OCOTP_H
-
-int mxs_ocotp_read(void *buf, int count, int offset);
-
-#endif /* __MACH_OCOTP_H */
diff --git a/arch/arm/mach-mxs/include/mach/power.h b/arch/arm/mach-mxs/include/mach/power.h
deleted file mode 100644
index f429b3c31c..0000000000
--- a/arch/arm/mach-mxs/include/mach/power.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __MACH_POWER_H
-#define __MACH_POWER_H
-
-void imx_power_prepare_usbphy(void);
-int imx_get_vddio(void);
-int imx_set_vddio(int);
-
-#endif /* __MACH_POWER_H */
diff --git a/arch/arm/mach-mxs/include/mach/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/include/mach/regs-clkctrl-mx23.h
deleted file mode 100644
index 289b159b74..0000000000
--- a/arch/arm/mach-mxs/include/mach/regs-clkctrl-mx23.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Freescale i.MX23 CLKCTRL Register Definitions
- *
- * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MX23_REGS_CLKCTRL_H__
-#define __MX23_REGS_CLKCTRL_H__
-
-#include <mach/regs-common.h>
-
-#ifndef	__ASSEMBLY__
-struct mxs_clkctrl_regs {
-	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
-	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
-	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
-	mxs_reg_32(hw_clkctrl_cpu)		/* 0x20 */
-	mxs_reg_32(hw_clkctrl_hbus)		/* 0x30 */
-	mxs_reg_32(hw_clkctrl_xbus)		/* 0x40 */
-	mxs_reg_32(hw_clkctrl_xtal)		/* 0x50 */
-	mxs_reg_32(hw_clkctrl_pix)		/* 0x60 */
-	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x70 */
-	mxs_reg_32(hw_clkctrl_gpmi)		/* 0x80 */
-	mxs_reg_32(hw_clkctrl_spdif)		/* 0x90 */
-	mxs_reg_32(hw_clkctrl_emi)		/* 0xa0 */
-
-	uint32_t	reserved1[4];
-
-	mxs_reg_32(hw_clkctrl_saif0)		/* 0xc0 */
-	mxs_reg_32(hw_clkctrl_tv)		/* 0xd0 */
-	mxs_reg_32(hw_clkctrl_etm)		/* 0xe0 */
-	mxs_reg_8(hw_clkctrl_frac0)		/* 0xf0 */
-	mxs_reg_8(hw_clkctrl_frac1)		/* 0x100 */
-	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x110 */
-	mxs_reg_32(hw_clkctrl_reset)		/* 0x120 */
-	mxs_reg_32(hw_clkctrl_status)		/* 0x130 */
-	mxs_reg_32(hw_clkctrl_version)		/* 0x140 */
-};
-#endif
-
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
-#define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
-#define	CLKCTRL_PLL0CTRL0_POWER			(1 << 16)
-
-#define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
-#define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
-#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
-#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
-
-#define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
-#define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
-#define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
-#define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
-#define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
-#define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
-#define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
-#define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
-#define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
-
-#define	CLKCTRL_HBUS_BUSY			(1 << 29)
-#define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 28)
-#define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 27)
-#define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
-#define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
-#define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
-#define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
-#define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
-#define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
-#define	CLKCTRL_HBUS_AUTO_SLOW_MODE		(1 << 20)
-#define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
-#define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
-#define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
-#define	CLKCTRL_HBUS_DIV_MASK			0x1f
-#define	CLKCTRL_HBUS_DIV_OFFSET			0
-
-#define	CLKCTRL_XBUS_BUSY			(1 << 31)
-#define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
-#define	CLKCTRL_XBUS_DIV_MASK			0x3ff
-#define	CLKCTRL_XBUS_DIV_OFFSET			0
-
-#define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
-#define	CLKCTRL_XTAL_FILT_CLK24M_GATE		(1 << 30)
-#define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
-#define	CLKCTRL_XTAL_DRI_CLK24M_GATE		(1 << 28)
-#define	CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE		(1 << 27)
-#define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
-#define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
-#define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
-
-#define	CLKCTRL_PIX_CLKGATE			(1 << 31)
-#define	CLKCTRL_PIX_BUSY			(1 << 29)
-#define	CLKCTRL_PIX_DIV_FRAC_EN			(1 << 12)
-#define	CLKCTRL_PIX_DIV_MASK			0xfff
-#define	CLKCTRL_PIX_DIV_OFFSET			0
-
-#define	CLKCTRL_SSP_CLKGATE			(1 << 31)
-#define	CLKCTRL_SSP_BUSY			(1 << 29)
-#define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
-#define	CLKCTRL_SSP_DIV_MASK			0x1ff
-#define	CLKCTRL_SSP_DIV_OFFSET			0
-
-#define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
-#define	CLKCTRL_GPMI_BUSY			(1 << 29)
-#define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
-#define	CLKCTRL_GPMI_DIV_MASK			0x3ff
-#define	CLKCTRL_GPMI_DIV_OFFSET			0
-
-#define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
-
-#define	CLKCTRL_EMI_CLKGATE			(1 << 31)
-#define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
-#define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
-#define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
-#define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
-#define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
-#define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
-#define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
-#define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
-#define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
-#define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
-#define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
-
-#define	CLKCTRL_IR_CLKGATE			(1 << 31)
-#define	CLKCTRL_IR_AUTO_DIV			(1 << 29)
-#define	CLKCTRL_IR_IR_BUSY			(1 << 28)
-#define	CLKCTRL_IR_IROV_BUSY			(1 << 27)
-#define	CLKCTRL_IR_IROV_DIV_MASK		(0x1ff << 16)
-#define	CLKCTRL_IR_IROV_DIV_OFFSET		16
-#define	CLKCTRL_IR_IR_DIV_MASK			0x3ff
-#define	CLKCTRL_IR_IR_DIV_OFFSET		0
-
-#define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
-#define	CLKCTRL_SAIF0_BUSY			(1 << 29)
-#define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
-#define	CLKCTRL_SAIF0_DIV_MASK			0xffff
-#define	CLKCTRL_SAIF0_DIV_OFFSET		0
-
-#define	CLKCTRL_TV_CLK_TV108M_GATE		(1 << 31)
-#define	CLKCTRL_TV_CLK_TV_GATE			(1 << 30)
-
-#define	CLKCTRL_ETM_CLKGATE			(1 << 31)
-#define	CLKCTRL_ETM_BUSY			(1 << 29)
-#define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 6)
-#define	CLKCTRL_ETM_DIV_MASK			0x3f
-#define	CLKCTRL_ETM_DIV_OFFSET			0
-
-#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
-#define	CLKCTRL_FRAC_STABLE			(1 << 6)
-#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
-#define	CLKCTRL_FRAC_FRAC_OFFSET		0
-#define	CLKCTRL_FRAC0_CPU			0
-#define	CLKCTRL_FRAC0_EMI			1
-#define	CLKCTRL_FRAC0_PIX			2
-#define	CLKCTRL_FRAC0_IO0			3
-#define	CLKCTRL_FRAC1_VID			3
-
-#define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
-#define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 7)
-#define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 6)
-#define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 5)
-#define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 4)
-#define	CLKCTRL_CLKSEQ_BYPASS_IR		(1 << 3)
-#define	CLKCTRL_CLKSEQ_BYPASS_PIX		(1 << 1)
-#define	CLKCTRL_CLKSEQ_BYPASS_SAIF		(1 << 0)
-
-#define	CLKCTRL_RESET_CHIP			(1 << 1)
-#define	CLKCTRL_RESET_DIG			(1 << 0)
-
-#define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
-#define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
-
-#define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
-#define	CLKCTRL_VERSION_MAJOR_OFFSET		24
-#define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
-#define	CLKCTRL_VERSION_MINOR_OFFSET		16
-#define	CLKCTRL_VERSION_STEP_MASK		0xffff
-#define	CLKCTRL_VERSION_STEP_OFFSET		0
-
-#endif /* __MX23_REGS_CLKCTRL_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/include/mach/regs-clkctrl-mx28.h
deleted file mode 100644
index aebb489d4b..0000000000
--- a/arch/arm/mach-mxs/include/mach/regs-clkctrl-mx28.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * Freescale i.MX28 CLKCTRL Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MX28_REGS_CLKCTRL_H__
-#define __MX28_REGS_CLKCTRL_H__
-
-#include <mach/regs-common.h>
-
-#ifndef	__ASSEMBLY__
-struct mxs_clkctrl_regs {
-	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
-	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
-	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
-	mxs_reg_32(hw_clkctrl_pll1ctrl0)	/* 0x20 */
-	uint32_t	hw_clkctrl_pll1ctrl1;	/* 0x30 */
-	uint32_t	reserved_pll1ctrl1[3];	/* 0x34-0x3c */
-	mxs_reg_32(hw_clkctrl_pll2ctrl0)	/* 0x40 */
-	mxs_reg_32(hw_clkctrl_cpu)		/* 0x50 */
-	mxs_reg_32(hw_clkctrl_hbus)		/* 0x60 */
-	mxs_reg_32(hw_clkctrl_xbus)		/* 0x70 */
-	mxs_reg_32(hw_clkctrl_xtal)		/* 0x80 */
-	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x90 */
-	mxs_reg_32(hw_clkctrl_ssp1)		/* 0xa0 */
-	mxs_reg_32(hw_clkctrl_ssp2)		/* 0xb0 */
-	mxs_reg_32(hw_clkctrl_ssp3)		/* 0xc0 */
-	mxs_reg_32(hw_clkctrl_gpmi)		/* 0xd0 */
-	mxs_reg_32(hw_clkctrl_spdif)		/* 0xe0 */
-	mxs_reg_32(hw_clkctrl_emi)		/* 0xf0 */
-	mxs_reg_32(hw_clkctrl_saif0)		/* 0x100 */
-	mxs_reg_32(hw_clkctrl_saif1)		/* 0x110 */
-	mxs_reg_32(hw_clkctrl_lcdif)		/* 0x120 */
-	mxs_reg_32(hw_clkctrl_etm)		/* 0x130 */
-	mxs_reg_32(hw_clkctrl_enet)		/* 0x140 */
-	mxs_reg_32(hw_clkctrl_hsadc)		/* 0x150 */
-	mxs_reg_32(hw_clkctrl_flexcan)		/* 0x160 */
-
-	uint32_t	reserved[16];
-
-	mxs_reg_8(hw_clkctrl_frac0)		/* 0x1b0 */
-	mxs_reg_8(hw_clkctrl_frac1)		/* 0x1c0 */
-	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x1d0 */
-	mxs_reg_32(hw_clkctrl_reset)		/* 0x1e0 */
-	mxs_reg_32(hw_clkctrl_status)		/* 0x1f0 */
-	mxs_reg_32(hw_clkctrl_version)		/* 0x200 */
-};
-#endif
-
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
-#define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
-#define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
-#define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
-#define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
-#define	CLKCTRL_PLL0CTRL0_POWER			(1 << 17)
-
-#define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
-#define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
-#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
-#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
-
-#define	CLKCTRL_PLL1CTRL0_CLKGATEEMI		(1 << 31)
-#define	CLKCTRL_PLL1CTRL0_LFR_SEL_MASK		(0x3 << 28)
-#define	CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET	28
-#define	CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
-#define	CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
-#define	CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
-#define	CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
-#define	CLKCTRL_PLL1CTRL0_CP_SEL_MASK		(0x3 << 24)
-#define	CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET		24
-#define	CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
-#define	CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
-#define	CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
-#define	CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
-#define	CLKCTRL_PLL1CTRL0_DIV_SEL_MASK		(0x3 << 20)
-#define	CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET	20
-#define	CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
-#define	CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER		(0x1 << 20)
-#define	CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
-#define	CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
-#define	CLKCTRL_PLL1CTRL0_EN_USB_CLKS		(1 << 18)
-#define	CLKCTRL_PLL1CTRL0_POWER			(1 << 17)
-
-#define	CLKCTRL_PLL1CTRL1_LOCK			(1 << 31)
-#define	CLKCTRL_PLL1CTRL1_FORCE_LOCK		(1 << 30)
-#define	CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK	0xffff
-#define	CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET	0
-
-#define	CLKCTRL_PLL2CTRL0_CLKGATE		(1 << 31)
-#define	CLKCTRL_PLL2CTRL0_LFR_SEL_MASK		(0x3 << 28)
-#define	CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET	28
-#define	CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B	(1 << 26)
-#define	CLKCTRL_PLL2CTRL0_CP_SEL_MASK		(0x3 << 24)
-#define	CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET		24
-#define	CLKCTRL_PLL2CTRL0_POWER			(1 << 23)
-
-#define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
-#define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
-#define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
-#define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
-#define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
-#define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
-#define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
-#define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
-#define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
-
-#define	CLKCTRL_HBUS_ASM_BUSY			(1 << 31)
-#define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 30)
-#define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 29)
-#define	CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE	(1 << 27)
-#define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
-#define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
-#define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
-#define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
-#define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
-#define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
-#define	CLKCTRL_HBUS_ASM_ENABLE			(1 << 20)
-#define	CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE	(1 << 19)
-#define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
-#define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
-#define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
-#define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
-#define	CLKCTRL_HBUS_DIV_MASK			0x1f
-#define	CLKCTRL_HBUS_DIV_OFFSET			0
-
-#define	CLKCTRL_XBUS_BUSY			(1 << 31)
-#define	CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE	(1 << 11)
-#define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
-#define	CLKCTRL_XBUS_DIV_MASK			0x3ff
-#define	CLKCTRL_XBUS_DIV_OFFSET			0
-
-#define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
-#define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
-#define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
-#define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
-#define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
-
-#define	CLKCTRL_SSP_CLKGATE			(1 << 31)
-#define	CLKCTRL_SSP_BUSY			(1 << 29)
-#define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
-#define	CLKCTRL_SSP_DIV_MASK			0x1ff
-#define	CLKCTRL_SSP_DIV_OFFSET			0
-
-#define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
-#define	CLKCTRL_GPMI_BUSY			(1 << 29)
-#define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
-#define	CLKCTRL_GPMI_DIV_MASK			0x3ff
-#define	CLKCTRL_GPMI_DIV_OFFSET			0
-
-#define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
-
-#define	CLKCTRL_EMI_CLKGATE			(1 << 31)
-#define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
-#define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
-#define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
-#define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
-#define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
-#define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
-#define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
-#define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
-#define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
-#define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
-#define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
-
-#define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
-#define	CLKCTRL_SAIF0_BUSY			(1 << 29)
-#define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
-#define	CLKCTRL_SAIF0_DIV_MASK			0xffff
-#define	CLKCTRL_SAIF0_DIV_OFFSET		0
-
-#define	CLKCTRL_SAIF1_CLKGATE			(1 << 31)
-#define	CLKCTRL_SAIF1_BUSY			(1 << 29)
-#define	CLKCTRL_SAIF1_DIV_FRAC_EN		(1 << 16)
-#define	CLKCTRL_SAIF1_DIV_MASK			0xffff
-#define	CLKCTRL_SAIF1_DIV_OFFSET		0
-
-#define	CLKCTRL_DIS_LCDIF_CLKGATE		(1 << 31)
-#define	CLKCTRL_DIS_LCDIF_BUSY			(1 << 29)
-#define	CLKCTRL_DIS_LCDIF_DIV_FRAC_EN		(1 << 13)
-#define	CLKCTRL_DIS_LCDIF_DIV_MASK		0x1fff
-#define	CLKCTRL_DIS_LCDIF_DIV_OFFSET		0
-
-#define	CLKCTRL_ETM_CLKGATE			(1 << 31)
-#define	CLKCTRL_ETM_BUSY			(1 << 29)
-#define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 7)
-#define	CLKCTRL_ETM_DIV_MASK			0x7f
-#define	CLKCTRL_ETM_DIV_OFFSET			0
-
-#define	CLKCTRL_ENET_SLEEP			(1 << 31)
-#define	CLKCTRL_ENET_DISABLE			(1 << 30)
-#define	CLKCTRL_ENET_STATUS			(1 << 29)
-#define	CLKCTRL_ENET_BUSY_TIME			(1 << 27)
-#define	CLKCTRL_ENET_DIV_TIME_MASK		(0x3f << 21)
-#define	CLKCTRL_ENET_DIV_TIME_OFFSET		21
-#define	CLKCTRL_ENET_TIME_SEL_MASK		(0x3 << 19)
-#define	CLKCTRL_ENET_TIME_SEL_OFFSET		19
-#define	CLKCTRL_ENET_TIME_SEL_XTAL		(0x0 << 19)
-#define	CLKCTRL_ENET_TIME_SEL_PLL		(0x1 << 19)
-#define	CLKCTRL_ENET_TIME_SEL_RMII_CLK		(0x2 << 19)
-#define	CLKCTRL_ENET_TIME_SEL_UNDEFINED		(0x3 << 19)
-#define	CLKCTRL_ENET_CLK_OUT_EN			(1 << 18)
-#define	CLKCTRL_ENET_RESET_BY_SW_CHIP		(1 << 17)
-#define	CLKCTRL_ENET_RESET_BY_SW		(1 << 16)
-
-#define	CLKCTRL_HSADC_RESETB			(1 << 30)
-#define	CLKCTRL_HSADC_FREQDIV_MASK		(0x3 << 28)
-#define	CLKCTRL_HSADC_FREQDIV_OFFSET		28
-
-#define	CLKCTRL_FLEXCAN_STOP_CAN0		(1 << 30)
-#define	CLKCTRL_FLEXCAN_CAN0_STATUS		(1 << 29)
-#define	CLKCTRL_FLEXCAN_STOP_CAN1		(1 << 28)
-#define	CLKCTRL_FLEXCAN_CAN1_STATUS		(1 << 27)
-
-#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
-#define	CLKCTRL_FRAC_STABLE			(1 << 6)
-#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
-#define	CLKCTRL_FRAC_FRAC_OFFSET		0
-#define	CLKCTRL_FRAC0_CPU			0
-#define	CLKCTRL_FRAC0_EMI			1
-#define	CLKCTRL_FRAC0_IO1			2
-#define	CLKCTRL_FRAC0_IO0			3
-#define	CLKCTRL_FRAC1_PIX			0
-#define	CLKCTRL_FRAC1_HSADC			1
-#define	CLKCTRL_FRAC1_GPMI			2
-
-#define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 18)
-#define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF		(1 << 14)
-#define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS	(0x1 << 14)
-#define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD	(0x0 << 14)
-#define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
-#define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 7)
-#define	CLKCTRL_CLKSEQ_BYPASS_SSP3		(1 << 6)
-#define	CLKCTRL_CLKSEQ_BYPASS_SSP2		(1 << 5)
-#define	CLKCTRL_CLKSEQ_BYPASS_SSP1		(1 << 4)
-#define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 3)
-#define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 2)
-#define	CLKCTRL_CLKSEQ_BYPASS_SAIF1		(1 << 1)
-#define	CLKCTRL_CLKSEQ_BYPASS_SAIF0		(1 << 0)
-
-#define	CLKCTRL_RESET_WDOG_POR_DISABLE		(1 << 5)
-#define	CLKCTRL_RESET_EXTERNAL_RESET_ENABLE	(1 << 4)
-#define	CLKCTRL_RESET_THERMAL_RESET_ENABLE	(1 << 3)
-#define	CLKCTRL_RESET_THERMAL_RESET_DEFAULT	(1 << 2)
-#define	CLKCTRL_RESET_CHIP			(1 << 1)
-#define	CLKCTRL_RESET_DIG			(1 << 0)
-
-#define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
-#define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
-
-#define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
-#define	CLKCTRL_VERSION_MAJOR_OFFSET		24
-#define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
-#define	CLKCTRL_VERSION_MINOR_OFFSET		16
-#define	CLKCTRL_VERSION_STEP_MASK		0xffff
-#define	CLKCTRL_VERSION_STEP_OFFSET		0
-
-#endif /* __MX28_REGS_CLKCTRL_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/regs-common.h b/arch/arm/mach-mxs/include/mach/regs-common.h
deleted file mode 100644
index e54a220fa3..0000000000
--- a/arch/arm/mach-mxs/include/mach/regs-common.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Freescale i.MXS Register Accessors
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MXS_REGS_COMMON_H__
-#define __MXS_REGS_COMMON_H__
-
-/*
- * The i.MXS has interesting feature when it comes to register access. There
- * are four kinds of access to one particular register. Those are:
- *
- * 1) Common read/write access. To use this mode, just write to the address of
- *    the register.
- * 2) Set bits only access. To set bits, write which bits you want to set to the
- *    address of the register + 0x4.
- * 3) Clear bits only access. To clear bits, write which bits you want to clear
- *    to the address of the register + 0x8.
- * 4) Toggle bits only access. To toggle bits, write which bits you want to
- *    toggle to the address of the register + 0xc.
- *
- * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
- * can be set/cleared by pure write as in access type 1, some need to be
- * explicitly set/cleared by using access type 2-3.
- *
- * The following macros and structures allow the user to either access the
- * register in all aforementioned modes (by accessing reg_name, reg_name_set,
- * reg_name_clr, reg_name_tog) or pass the register structure further into
- * various functions with correct type information (by accessing reg_name_reg).
- *
- */
-
-#define	__mxs_reg_8(name)		\
-	uint8_t	name[4];		\
-	uint8_t	name##_set[4];		\
-	uint8_t	name##_clr[4];		\
-	uint8_t	name##_tog[4];		\
-
-#define	__mxs_reg_32(name)		\
-	uint32_t name;			\
-	uint32_t name##_set;		\
-	uint32_t name##_clr;		\
-	uint32_t name##_tog;
-
-struct mxs_register_8 {
-	__mxs_reg_8(reg)
-};
-
-struct mxs_register_32 {
-	__mxs_reg_32(reg)
-};
-
-#define	mxs_reg_8(name)				\
-	union {						\
-		struct { __mxs_reg_8(name) };		\
-		struct mxs_register_8 name##_reg;	\
-	};
-
-#define	mxs_reg_32(name)				\
-	union {						\
-		struct { __mxs_reg_32(name) };		\
-		struct mxs_register_32 name##_reg;	\
-	};
-
-#endif	/* __MXS_REGS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/regs-lradc.h b/arch/arm/mach-mxs/include/mach/regs-lradc.h
deleted file mode 100644
index 7f624be4c5..0000000000
--- a/arch/arm/mach-mxs/include/mach/regs-lradc.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * Freescale i.MX28 LRADC Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Based on code from LTIB:
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MX28_REGS_LRADC_H__
-#define __MX28_REGS_LRADC_H__
-
-#include <mach/regs-common.h>
-
-#ifndef	__ASSEMBLY__
-struct mxs_lradc_regs {
-	mxs_reg_32(hw_lradc_ctrl0);
-	mxs_reg_32(hw_lradc_ctrl1);
-	mxs_reg_32(hw_lradc_ctrl2);
-	mxs_reg_32(hw_lradc_ctrl3);
-	mxs_reg_32(hw_lradc_status);
-	mxs_reg_32(hw_lradc_ch0);
-	mxs_reg_32(hw_lradc_ch1);
-	mxs_reg_32(hw_lradc_ch2);
-	mxs_reg_32(hw_lradc_ch3);
-	mxs_reg_32(hw_lradc_ch4);
-	mxs_reg_32(hw_lradc_ch5);
-	mxs_reg_32(hw_lradc_ch6);
-	mxs_reg_32(hw_lradc_ch7);
-	mxs_reg_32(hw_lradc_delay0);
-	mxs_reg_32(hw_lradc_delay1);
-	mxs_reg_32(hw_lradc_delay2);
-	mxs_reg_32(hw_lradc_delay3);
-	mxs_reg_32(hw_lradc_debug0);
-	mxs_reg_32(hw_lradc_debug1);
-	mxs_reg_32(hw_lradc_conversion);
-	mxs_reg_32(hw_lradc_ctrl4);
-	mxs_reg_32(hw_lradc_treshold0);
-	mxs_reg_32(hw_lradc_treshold1);
-	mxs_reg_32(hw_lradc_version);
-};
-#endif
-
-#define	LRADC_CTRL0_SFTRST					(1 << 31)
-#define	LRADC_CTRL0_CLKGATE					(1 << 30)
-#define	LRADC_CTRL0_ONCHIP_GROUNDREF				(1 << 26)
-#define	LRADC_CTRL0_BUTTON1_DETECT_ENABLE			(1 << 25)
-#define	LRADC_CTRL0_BUTTON0_DETECT_ENABLE			(1 << 24)
-#define	LRADC_CTRL0_TOUCH_DETECT_ENABLE				(1 << 23)
-#define	LRADC_CTRL0_TOUCH_SCREEN_TYPE				(1 << 22)
-#define	LRADC_CTRL0_YNLRSW					(1 << 21)
-#define	LRADC_CTRL0_YPLLSW_MASK					(0x3 << 19)
-#define	LRADC_CTRL0_YPLLSW_OFFSET				19
-#define	LRADC_CTRL0_XNURSW_MASK					(0x3 << 17)
-#define	LRADC_CTRL0_XNURSW_OFFSET				17
-#define	LRADC_CTRL0_XPULSW					(1 << 16)
-#define	LRADC_CTRL0_SCHEDULE_MASK				0xff
-#define	LRADC_CTRL0_SCHEDULE_OFFSET				0
-
-#define	LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN			(1 << 28)
-#define	LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN			(1 << 27)
-#define	LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN			(1 << 26)
-#define	LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN			(1 << 25)
-#define	LRADC_CTRL1_TOUCH_DETECT_IRQ_EN				(1 << 24)
-#define	LRADC_CTRL1_LRADC7_IRQ_EN				(1 << 23)
-#define	LRADC_CTRL1_LRADC6_IRQ_EN				(1 << 22)
-#define	LRADC_CTRL1_LRADC5_IRQ_EN				(1 << 21)
-#define	LRADC_CTRL1_LRADC4_IRQ_EN				(1 << 20)
-#define	LRADC_CTRL1_LRADC3_IRQ_EN				(1 << 19)
-#define	LRADC_CTRL1_LRADC2_IRQ_EN				(1 << 18)
-#define	LRADC_CTRL1_LRADC1_IRQ_EN				(1 << 17)
-#define	LRADC_CTRL1_LRADC0_IRQ_EN				(1 << 16)
-#define	LRADC_CTRL1_BUTTON1_DETECT_IRQ				(1 << 12)
-#define	LRADC_CTRL1_BUTTON0_DETECT_IRQ				(1 << 11)
-#define	LRADC_CTRL1_THRESHOLD1_DETECT_IRQ			(1 << 10)
-#define	LRADC_CTRL1_THRESHOLD0_DETECT_IRQ			(1 << 9)
-#define	LRADC_CTRL1_TOUCH_DETECT_IRQ				(1 << 8)
-#define	LRADC_CTRL1_LRADC7_IRQ					(1 << 7)
-#define	LRADC_CTRL1_LRADC6_IRQ					(1 << 6)
-#define	LRADC_CTRL1_LRADC5_IRQ					(1 << 5)
-#define	LRADC_CTRL1_LRADC4_IRQ					(1 << 4)
-#define	LRADC_CTRL1_LRADC3_IRQ					(1 << 3)
-#define	LRADC_CTRL1_LRADC2_IRQ					(1 << 2)
-#define	LRADC_CTRL1_LRADC1_IRQ					(1 << 1)
-#define	LRADC_CTRL1_LRADC0_IRQ					(1 << 0)
-
-#define	LRADC_CTRL2_DIVIDE_BY_TWO_MASK				(0xff << 24)
-#define	LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET			24
-#define	LRADC_CTRL2_TEMPSENSE_PWD				(1 << 15)
-#define	LRADC_CTRL2_VTHSENSE_MASK				(0x3 << 13)
-#define	LRADC_CTRL2_VTHSENSE_OFFSET				13
-#define	LRADC_CTRL2_DISABLE_MUXAMP_BYPASS			(1 << 12)
-#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE1			(1 << 9)
-#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE0			(1 << 8)
-#define	LRADC_CTRL2_TEMP_ISRC1_MASK				(0xf << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_OFFSET				4
-#define	LRADC_CTRL2_TEMP_ISRC1_300				(0xf << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_280				(0xe << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_260				(0xd << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_240				(0xc << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_220				(0xb << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_200				(0xa << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_180				(0x9 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_160				(0x8 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_140				(0x7 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_120				(0x6 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_100				(0x5 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_80				(0x4 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_60				(0x3 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_40				(0x2 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_20				(0x1 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC1_ZERO				(0x0 << 4)
-#define	LRADC_CTRL2_TEMP_ISRC0_MASK				(0xf << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_OFFSET				0
-#define	LRADC_CTRL2_TEMP_ISRC0_300				(0xf << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_280				(0xe << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_260				(0xd << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_240				(0xc << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_220				(0xb << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_200				(0xa << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_180				(0x9 << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_160				(0x8 << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_140				(0x7 << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_120				(0x6 << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_100				(0x5 << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_80				(0x4 << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_60				(0x3 << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_40				(0x2 << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_20				(0x1 << 0)
-#define	LRADC_CTRL2_TEMP_ISRC0_ZERO				(0x0 << 0)
-
-#define	LRADC_CTRL3_DISCARD_MASK				(0x3 << 24)
-#define	LRADC_CTRL3_DISCARD_OFFSET				24
-#define	LRADC_CTRL3_DISCARD_1_SAMPLE				(0x1 << 24)
-#define	LRADC_CTRL3_DISCARD_2_SAMPLES				(0x2 << 24)
-#define	LRADC_CTRL3_DISCARD_3_SAMPLES				(0x3 << 24)
-#define	LRADC_CTRL3_FORCE_ANALOG_PWUP				(1 << 23)
-#define	LRADC_CTRL3_FORCE_ANALOG_PWDN				(1 << 22)
-#define	LRADC_CTRL3_CYCLE_TIME_MASK				(0x3 << 8)
-#define	LRADC_CTRL3_CYCLE_TIME_OFFSET				8
-#define	LRADC_CTRL3_CYCLE_TIME_6MHZ				(0x0 << 8)
-#define	LRADC_CTRL3_CYCLE_TIME_4MHZ				(0x1 << 8)
-#define	LRADC_CTRL3_CYCLE_TIME_3MHZ				(0x2 << 8)
-#define	LRADC_CTRL3_CYCLE_TIME_2MHZ				(0x3 << 8)
-#define	LRADC_CTRL3_HIGH_TIME_MASK				(0x3 << 4)
-#define	LRADC_CTRL3_HIGH_TIME_OFFSET				4
-#define	LRADC_CTRL3_HIGH_TIME_42NS				(0x0 << 4)
-#define	LRADC_CTRL3_HIGH_TIME_83NS				(0x1 << 4)
-#define	LRADC_CTRL3_HIGH_TIME_125NS				(0x2 << 4)
-#define	LRADC_CTRL3_HIGH_TIME_250NS				(0x3 << 4)
-#define	LRADC_CTRL3_DELAY_CLOCK					(1 << 1)
-#define	LRADC_CTRL3_INVERT_CLOCK				(1 << 0)
-
-#define	LRADC_STATUS_BUTTON1_PRESENT				(1 << 28)
-#define	LRADC_STATUS_BUTTON0_PRESENT				(1 << 27)
-#define	LRADC_STATUS_TEMP1_PRESENT				(1 << 26)
-#define	LRADC_STATUS_TEMP0_PRESENT				(1 << 25)
-#define	LRADC_STATUS_TOUCH_PANEL_PRESENT			(1 << 24)
-#define	LRADC_STATUS_CHANNEL7_PRESENT				(1 << 23)
-#define	LRADC_STATUS_CHANNEL6_PRESENT				(1 << 22)
-#define	LRADC_STATUS_CHANNEL5_PRESENT				(1 << 21)
-#define	LRADC_STATUS_CHANNEL4_PRESENT				(1 << 20)
-#define	LRADC_STATUS_CHANNEL3_PRESENT				(1 << 19)
-#define	LRADC_STATUS_CHANNEL2_PRESENT				(1 << 18)
-#define	LRADC_STATUS_CHANNEL1_PRESENT				(1 << 17)
-#define	LRADC_STATUS_CHANNEL0_PRESENT				(1 << 16)
-#define	LRADC_STATUS_BUTTON1_DETECT_RAW				(1 << 2)
-#define	LRADC_STATUS_BUTTON0_DETECT_RAW				(1 << 1)
-#define	LRADC_STATUS_TOUCH_DETECT_RAW				(1 << 0)
-
-#define	LRADC_CH_TOGGLE						(1 << 31)
-#define	LRADC_CH7_TESTMODE_TOGGLE				(1 << 30)
-#define	LRADC_CH_ACCUMULATE					(1 << 29)
-#define	LRADC_CH_NUM_SAMPLES_MASK				(0x1f << 24)
-#define	LRADC_CH_NUM_SAMPLES_OFFSET				24
-#define	LRADC_CH_VALUE_MASK					0x3ffff
-#define	LRADC_CH_VALUE_OFFSET					0
-
-#define	LRADC_DELAY_TRIGGER_LRADCS_MASK				(0xff << 24)
-#define	LRADC_DELAY_TRIGGER_LRADCS_OFFSET			24
-#define	LRADC_DELAY_KICK					(1 << 20)
-#define	LRADC_DELAY_TRIGGER_DELAYS_MASK				(0xf << 16)
-#define	LRADC_DELAY_TRIGGER_DELAYS_OFFSET			16
-#define	LRADC_DELAY_LOOP_COUNT_MASK				(0x1f << 11)
-#define	LRADC_DELAY_LOOP_COUNT_OFFSET				11
-#define	LRADC_DELAY_DELAY_MASK					0x7ff
-#define	LRADC_DELAY_DELAY_OFFSET				0
-
-#define	LRADC_DEBUG0_READONLY_MASK				(0xffff << 16)
-#define	LRADC_DEBUG0_READONLY_OFFSET				16
-#define	LRADC_DEBUG0_STATE_MASK					(0xfff << 0)
-#define	LRADC_DEBUG0_STATE_OFFSET				0
-
-#define	LRADC_DEBUG1_REQUEST_MASK				(0xff << 16)
-#define	LRADC_DEBUG1_REQUEST_OFFSET				16
-#define	LRADC_DEBUG1_TESTMODE_COUNT_MASK			(0x1f << 8)
-#define	LRADC_DEBUG1_TESTMODE_COUNT_OFFSET			8
-#define	LRADC_DEBUG1_TESTMODE6					(1 << 2)
-#define	LRADC_DEBUG1_TESTMODE5					(1 << 1)
-#define	LRADC_DEBUG1_TESTMODE					(1 << 0)
-
-#define	LRADC_CONVERSION_AUTOMATIC				(1 << 20)
-#define	LRADC_CONVERSION_SCALE_FACTOR_MASK			(0x3 << 16)
-#define	LRADC_CONVERSION_SCALE_FACTOR_OFFSET			16
-#define	LRADC_CONVERSION_SCALE_FACTOR_NIMH			(0x0 << 16)
-#define	LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH			(0x1 << 16)
-#define	LRADC_CONVERSION_SCALE_FACTOR_LI_ION			(0x2 << 16)
-#define	LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION		(0x3 << 16)
-#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK		0x3ff
-#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET		0
-
-#define	LRADC_CTRL4_LRADC7SELECT_MASK				(0xf << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_OFFSET				28
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL0			(0x0 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL1			(0x1 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL2			(0x2 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL3			(0x3 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL4			(0x4 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL5			(0x5 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL6			(0x6 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL7			(0x7 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL8			(0x8 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL9			(0x9 << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL10			(0xa << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL11			(0xb << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL12			(0xc << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL13			(0xd << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL14			(0xe << 28)
-#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL15			(0xf << 28)
-#define	LRADC_CTRL4_LRADC6SELECT_MASK				(0xf << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_OFFSET				24
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL0			(0x0 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL1			(0x1 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL2			(0x2 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL3			(0x3 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL4			(0x4 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL5			(0x5 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL6			(0x6 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL7			(0x7 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL8			(0x8 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL9			(0x9 << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL10			(0xa << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL11			(0xb << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL12			(0xc << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL13			(0xd << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL14			(0xe << 24)
-#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL15			(0xf << 24)
-#define	LRADC_CTRL4_LRADC5SELECT_MASK				(0xf << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_OFFSET				20
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL0			(0x0 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL1			(0x1 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL2			(0x2 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL3			(0x3 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL4			(0x4 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL5			(0x5 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL6			(0x6 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL7			(0x7 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL8			(0x8 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL9			(0x9 << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL10			(0xa << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL11			(0xb << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL12			(0xc << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL13			(0xd << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL14			(0xe << 20)
-#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL15			(0xf << 20)
-#define	LRADC_CTRL4_LRADC4SELECT_MASK				(0xf << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_OFFSET				16
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL0			(0x0 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL1			(0x1 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL2			(0x2 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL3			(0x3 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL4			(0x4 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL5			(0x5 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL6			(0x6 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL7			(0x7 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL8			(0x8 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL9			(0x9 << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL10			(0xa << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL11			(0xb << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL12			(0xc << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL13			(0xd << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL14			(0xe << 16)
-#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL15			(0xf << 16)
-#define	LRADC_CTRL4_LRADC3SELECT_MASK				(0xf << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_OFFSET				12
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL0			(0x0 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL1			(0x1 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL2			(0x2 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL3			(0x3 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL4			(0x4 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL5			(0x5 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL6			(0x6 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL7			(0x7 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL8			(0x8 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL9			(0x9 << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL10			(0xa << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL11			(0xb << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL12			(0xc << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL13			(0xd << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL14			(0xe << 12)
-#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL15			(0xf << 12)
-#define	LRADC_CTRL4_LRADC2SELECT_MASK				(0xf << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_OFFSET				8
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL0			(0x0 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL1			(0x1 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL2			(0x2 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL3			(0x3 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL4			(0x4 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL5			(0x5 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL6			(0x6 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL7			(0x7 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL8			(0x8 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL9			(0x9 << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL10			(0xa << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL11			(0xb << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL12			(0xc << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL13			(0xd << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL14			(0xe << 8)
-#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL15			(0xf << 8)
-#define	LRADC_CTRL4_LRADC1SELECT_MASK				(0xf << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_OFFSET				4
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL0			(0x0 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL1			(0x1 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL2			(0x2 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL3			(0x3 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL4			(0x4 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL5			(0x5 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL6			(0x6 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL7			(0x7 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL8			(0x8 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL9			(0x9 << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL10			(0xa << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL11			(0xb << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL12			(0xc << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL13			(0xd << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL14			(0xe << 4)
-#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL15			(0xf << 4)
-#define	LRADC_CTRL4_LRADC0SELECT_MASK				0xf
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL0			(0x0 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL1			(0x1 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL2			(0x2 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL3			(0x3 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL4			(0x4 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL5			(0x5 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL6			(0x6 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL7			(0x7 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL8			(0x8 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL9			(0x9 << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL10			(0xa << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL11			(0xb << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL12			(0xc << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL13			(0xd << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL14			(0xe << 0)
-#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL15			(0xf << 0)
-
-#define	LRADC_THRESHOLD_ENABLE					(1 << 24)
-#define	LRADC_THRESHOLD_BATTCHRG_DISABLE			(1 << 23)
-#define	LRADC_THRESHOLD_CHANNEL_SEL_MASK			(0x7 << 20)
-#define	LRADC_THRESHOLD_CHANNEL_SEL_OFFSET			20
-#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0			(0x0 << 20)
-#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1			(0x1 << 20)
-#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2			(0x2 << 20)
-#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3			(0x3 << 20)
-#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4			(0x4 << 20)
-#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5			(0x5 << 20)
-#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6			(0x6 << 20)
-#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7			(0x7 << 20)
-#define	LRADC_THRESHOLD_SETTING_MASK				(0x3 << 18)
-#define	LRADC_THRESHOLD_SETTING_OFFSET				18
-#define	LRADC_THRESHOLD_SETTING_NO_COMPARE			(0x0 << 18)
-#define	LRADC_THRESHOLD_SETTING_DETECT_LOW			(0x1 << 18)
-#define	LRADC_THRESHOLD_SETTING_DETECT_HIGH			(0x2 << 18)
-#define	LRADC_THRESHOLD_SETTING_RESERVED			(0x3 << 18)
-#define	LRADC_THRESHOLD_VALUE_MASK				0x3ffff
-#define	LRADC_THRESHOLD_VALUE_OFFSET				0
-
-#define	LRADC_VERSION_MAJOR_MASK				(0xff << 24)
-#define	LRADC_VERSION_MAJOR_OFFSET				24
-#define	LRADC_VERSION_MINOR_MASK				(0xff << 16)
-#define	LRADC_VERSION_MINOR_OFFSET				16
-#define	LRADC_VERSION_STEP_MASK					0xffff
-#define	LRADC_VERSION_STEP_OFFSET				0
-
-#endif	/* __MX28_REGS_LRADC_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/regs-power-mx28.h b/arch/arm/mach-mxs/include/mach/regs-power-mx28.h
deleted file mode 100644
index 7b7349662b..0000000000
--- a/arch/arm/mach-mxs/include/mach/regs-power-mx28.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * Freescale i.MX28 Power Controller Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MX28_REGS_POWER_H__
-#define __MX28_REGS_POWER_H__
-
-#include <mach/regs-common.h>
-
-#ifndef	__ASSEMBLY__
-struct mxs_power_regs {
-	mxs_reg_32(hw_power_ctrl)
-	mxs_reg_32(hw_power_5vctrl)
-	mxs_reg_32(hw_power_minpwr)
-	mxs_reg_32(hw_power_charge)
-	uint32_t	hw_power_vdddctrl;
-	uint32_t	reserved_vddd[3];
-	uint32_t	hw_power_vddactrl;
-	uint32_t	reserved_vdda[3];
-	uint32_t	hw_power_vddioctrl;
-	uint32_t	reserved_vddio[3];
-	uint32_t	hw_power_vddmemctrl;
-	uint32_t	reserved_vddmem[3];
-	uint32_t	hw_power_dcdc4p2;
-	uint32_t	reserved_dcdc4p2[3];
-	uint32_t	hw_power_misc;
-	uint32_t	reserved_misc[3];
-	uint32_t	hw_power_dclimits;
-	uint32_t	reserved_dclimits[3];
-	mxs_reg_32(hw_power_loopctrl)
-	uint32_t	hw_power_sts;
-	uint32_t	reserved_sts[3];
-	mxs_reg_32(hw_power_speed)
-	uint32_t	hw_power_battmonitor;
-	uint32_t	reserved_battmonitor[3];
-
-	uint32_t	reserved[4];
-
-	mxs_reg_32(hw_power_reset)
-};
-#endif
-
-#define	MX23_POWER_CTRL_CLKGATE				(1 << 30)
-#define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
-#define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
-#define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
-#define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
-#define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
-#define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
-#define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
-#define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
-#define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
-#define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
-#define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
-#define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
-#define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
-#define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
-#define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
-#define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
-#define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
-#define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
-#define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
-#define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
-#define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
-#define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
-#define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
-#define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
-#define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
-#define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
-
-#define	MX28_POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 30)
-#define	MX28_POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		30
-#define	MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V3		(0x0 << 30)
-#define	MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V4		(0x1 << 30)
-#define	MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V5		(0x2 << 30)
-#define	MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V7		(0x3 << 30)
-
-#define	MX23_POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 28)
-#define	MX23_POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		28
-#define	MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V3		(0x0 << 28)
-#define	MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V4		(0x1 << 28)
-#define	MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V5		(0x2 << 28)
-#define	MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V7		(0x3 << 28)
-
-#define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
-#define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
-#define	MX28_POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x3 << 20)
-#define MX23_POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x1 << 20)
-#define	POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET		20
-#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
-#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
-#define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
-#define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
-#define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
-#define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
-#define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
-#define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
-#define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
-#define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
-#define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
-#define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
-#define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
-#define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
-#define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
-#define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
-#define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
-#define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
-#define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
-#define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
-
-#define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
-#define	MX23_POWER_MINPWR_VDAC_DUMP_CTRL		(1 << 13)
-#define	POWER_MINPWR_PWD_BO				(1 << 12)
-#define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
-#define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
-#define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
-#define	POWER_MINPWR_SELECT_OSC				(1 << 8)
-#define	POWER_MINPWR_VBG_OFF				(1 << 7)
-#define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
-#define	POWER_MINPWR_HALFFETS				(1 << 5)
-#define	POWER_MINPWR_LESSANA_I				(1 << 4)
-#define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
-#define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
-#define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
-#define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
-
-#define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
-#define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
-#define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
-#define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
-#define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
-#define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
-#define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
-#define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
-#define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
-#define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
-#define MX23_POWER_CHARGE_ENABLE_CHARGER_RESISTORS	(1 << 21)
-#define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
-#define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
-#define	MX28_POWER_CHARGE_LIION_4P1			(1 << 18)
-#define	MX23_POWER_CHARGE_USE_EXTERN_R			(1 << 17)
-#define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
-#define	MX28_POWER_CHARGE_ENABLE_CHARGER_USB1		(1 << 13)
-#define	MX28_POWER_CHARGE_ENABLE_CHARGER_USB0		(1 << 12)
-#define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
-#define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
-#define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
-#define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
-#define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
-#define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
-#define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
-#define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
-#define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
-#define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
-#define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
-#define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
-#define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
-#define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
-
-#define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
-#define	POWER_VDDDCTRL_ADJTN_OFFSET			28
-#define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
-#define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
-#define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
-#define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
-#define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
-#define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
-#define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
-#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
-#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
-#define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
-#define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
-#define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
-#define	POWER_VDDDCTRL_TRG_MASK				0x1f
-#define	POWER_VDDDCTRL_TRG_OFFSET			0
-
-#define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
-#define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
-#define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
-#define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
-#define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
-#define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
-#define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
-#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
-#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
-#define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
-#define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
-#define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
-#define	POWER_VDDACTRL_TRG_MASK				0x1f
-#define	POWER_VDDACTRL_TRG_OFFSET			0
-
-#define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
-#define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
-#define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
-#define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
-#define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
-#define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
-#define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
-#define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
-#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
-#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
-#define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
-#define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
-#define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
-#define	POWER_VDDIOCTRL_TRG_MASK			0x1f
-#define	POWER_VDDIOCTRL_TRG_OFFSET			0
-
-#define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
-#define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
-#define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
-#define	MX28_POWER_VDDMEMCTRL_BO_OFFSET_MASK		(0x7 << 5)
-#define	MX28_POWER_VDDMEMCTRL_BO_OFFSET_OFFSET		5
-#define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
-#define	POWER_VDDMEMCTRL_TRG_OFFSET			0
-
-#define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
-#define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
-#define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
-#define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
-#define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
-#define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
-#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
-#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
-#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
-#define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
-#define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
-#define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
-#define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
-#define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
-#define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
-#define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
-#define	POWER_DCDC4P2_TRG_OFFSET			16
-#define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
-#define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
-#define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
-#define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
-#define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
-#define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
-#define	POWER_DCDC4P2_BO_OFFSET				8
-#define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
-#define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
-
-#define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
-#define	POWER_MISC_FREQSEL_OFFSET			4
-#define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
-#define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
-#define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
-#define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
-#define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
-#define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
-#define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
-#define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
-#define	POWER_MISC_DELAY_TIMING				(1 << 2)
-#define	POWER_MISC_TEST					(1 << 1)
-#define	POWER_MISC_SEL_PLLCLK				(1 << 0)
-
-#define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
-#define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
-#define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
-#define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
-
-#define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
-#define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
-#define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
-#define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
-#define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
-#define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
-#define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
-#define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
-#define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
-#define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
-#define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
-#define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
-#define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
-#define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
-#define	POWER_LOOPCTRL_DC_FF_OFFSET			8
-#define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
-#define	POWER_LOOPCTRL_DC_R_OFFSET			4
-#define	POWER_LOOPCTRL_DC_C_MASK			0x3
-#define	POWER_LOOPCTRL_DC_C_OFFSET			0
-#define	POWER_LOOPCTRL_DC_C_MAX				0x0
-#define	POWER_LOOPCTRL_DC_C_2X				0x1
-#define	POWER_LOOPCTRL_DC_C_4X				0x2
-#define	POWER_LOOPCTRL_DC_C_MIN				0x3
-
-#define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
-#define	POWER_STS_PWRUP_SOURCE_OFFSET			24
-#define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
-#define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
-#define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
-#define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
-#define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
-#define	POWER_STS_PSWITCH_OFFSET			20
-#define	MX28_POWER_STS_THERMAL_WARNING			(1 << 19)
-#define	MX28_POWER_STS_VDDMEM_BO			(1 << 18)
-#define	POWER_STS_AVALID0_STATUS			(1 << 17)
-#define	POWER_STS_BVALID0_STATUS			(1 << 16)
-#define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
-#define	POWER_STS_SESSEND0_STATUS			(1 << 14)
-#define	POWER_STS_BATT_BO				(1 << 13)
-#define	POWER_STS_VDD5V_FAULT				(1 << 12)
-#define	POWER_STS_CHRGSTS				(1 << 11)
-#define	POWER_STS_DCDC_4P2_BO				(1 << 10)
-#define	POWER_STS_DC_OK					(1 << 9)
-#define	POWER_STS_VDDIO_BO				(1 << 8)
-#define	POWER_STS_VDDA_BO				(1 << 7)
-#define	POWER_STS_VDDD_BO				(1 << 6)
-#define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
-#define	POWER_STS_VDD5V_DROOP				(1 << 4)
-#define	POWER_STS_AVALID0				(1 << 3)
-#define	POWER_STS_BVALID0				(1 << 2)
-#define	POWER_STS_VBUSVALID0				(1 << 1)
-#define	POWER_STS_SESSEND0				(1 << 0)
-
-#define	MX23_POWER_SPEED_STATUS_MASK			(0xff << 16)
-#define	MX23_POWER_SPEED_STATUS_OFFSET			16
-#define	MX28_POWER_SPEED_STATUS_MASK			(0xffff << 8)
-#define	MX28_POWER_SPEED_STATUS_OFFSET			8
-#define	MX28_POWER_SPEED_STATUS_SEL_MASK		(0x3 << 6)
-#define	MX28_POWER_SPEED_STATUS_SEL_OFFSET		6
-#define	MX28_POWER_SPEED_STATUS_SEL_DCDC_STAT		(0x0 << 6)
-#define	MX28_POWER_SPEED_STATUS_SEL_CORE_STAT		(0x1 << 6)
-#define	MX28_POWER_SPEED_STATUS_SEL_ARM_STAT		(0x2 << 6)
-#define	POWER_SPEED_CTRL_MASK				0x3
-#define	POWER_SPEED_CTRL_OFFSET				0
-#define	POWER_SPEED_CTRL_SS_OFF				0x0
-#define	POWER_SPEED_CTRL_SS_ON				0x1
-#define	POWER_SPEED_CTRL_SS_ENABLE			0x3
-
-#define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
-#define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
-#define	MX28_POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN	(1 << 11)
-#define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
-#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
-#define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
-#define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
-#define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
-
-#define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
-#define	POWER_RESET_UNLOCK_OFFSET			16
-#define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
-#define	MX28_POWER_RESET_FASTFALL_PSWITCH_OFF		(1 << 2)
-#define	POWER_RESET_PWD_OFF				(1 << 1)
-#define	POWER_RESET_PWD					(1 << 0)
-
-#define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
-#define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
-#define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
-#define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
-
-#define	MX28_POWER_THERMAL_TEST				(1 << 8)
-#define	MX28_POWER_THERMAL_PWD				(1 << 7)
-#define	MX28_POWER_THERMAL_LOW_POWER			(1 << 6)
-#define	MX28_POWER_THERMAL_OFFSET_ADJ_MASK		(0x3 << 4)
-#define	MX28_POWER_THERMAL_OFFSET_ADJ_OFFSET		4
-#define	MX28_POWER_THERMAL_OFFSET_ADJ_ENABLE		(1 << 3)
-#define	MX28_POWER_THERMAL_TEMP_THRESHOLD_MASK		0x7
-#define	MX28_POWER_THERMAL_TEMP_THRESHOLD_OFFSET	0
-
-#define	MX28_POWER_USB1CTRL_AVALID1			(1 << 3)
-#define	MX28_POWER_USB1CTRL_BVALID1			(1 << 2)
-#define	MX28_POWER_USB1CTRL_VBUSVALID1			(1 << 1)
-#define	MX28_POWER_USB1CTRL_SESSEND1			(1 << 0)
-
-#define	POWER_SPECIAL_TEST_MASK				0xffffffff
-#define	POWER_SPECIAL_TEST_OFFSET			0
-
-#define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
-#define	POWER_VERSION_MAJOR_OFFSET			24
-#define	POWER_VERSION_MINOR_MASK			(0xff << 16)
-#define	POWER_VERSION_MINOR_OFFSET			16
-#define	POWER_VERSION_STEP_MASK				0xffff
-#define	POWER_VERSION_STEP_OFFSET			0
-
-#define	MX28_POWER_ANACLKCTRL_CLKGATE_0			(1 << 31)
-#define	MX28_POWER_ANACLKCTRL_OUTDIV_MASK		(0x7 << 28)
-#define	MX28_POWER_ANACLKCTRL_OUTDIV_OFFSET		28
-#define	MX28_POWER_ANACLKCTRL_INVERT_OUTCLK		(1 << 27)
-#define	MX28_POWER_ANACLKCTRL_CLKGATE_I			(1 << 26)
-#define	MX28_POWER_ANACLKCTRL_DITHER_OFF		(1 << 10)
-#define	MX28_POWER_ANACLKCTRL_SLOW_DITHER		(1 << 9)
-#define	MX28_POWER_ANACLKCTRL_INVERT_INCLK		(1 << 8)
-#define	MX28_POWER_ANACLKCTRL_INCLK_SHIFT_MASK		(0x3 << 4)
-#define	MX28_POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET	4
-#define	MX28_POWER_ANACLKCTRL_INDIV_MASK		0x7
-#define	MX28_POWER_ANACLKCTRL_INDIV_OFFSET		0
-
-#define	MX28_POWER_REFCTRL_FASTSETTLING			(1 << 26)
-#define	MX28_POWER_REFCTRL_RAISE_REF			(1 << 25)
-#define	MX28_POWER_REFCTRL_XTAL_BGR_BIAS		(1 << 24)
-#define	MX28_POWER_REFCTRL_VBG_ADJ_MASK			(0x7 << 20)
-#define	MX28_POWER_REFCTRL_VBG_ADJ_OFFSET		20
-#define	MX28_POWER_REFCTRL_LOW_PWR			(1 << 19)
-#define	MX28_POWER_REFCTRL_BIAS_CTRL_MASK		(0x3 << 16)
-#define	MX28_POWER_REFCTRL_BIAS_CTRL_OFFSET		16
-#define	MX28_POWER_REFCTRL_VDDXTAL_TO_VDDD		(1 << 14)
-#define	MX28_POWER_REFCTRL_ADJ_ANA			(1 << 13)
-#define	MX28_POWER_REFCTRL_ADJ_VAG			(1 << 12)
-#define	MX28_POWER_REFCTRL_ANA_REFVAL_MASK		(0xf << 8)
-#define	MX28_POWER_REFCTRL_ANA_REFVAL_OFFSET		8
-#define	MX28_POWER_REFCTRL_VAG_VAL_MASK			(0xf << 4)
-#define	MX28_POWER_REFCTRL_VAG_VAL_OFFSET		4
-
-#endif	/* __MX28_REGS_POWER_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/regs-rtc.h b/arch/arm/mach-mxs/include/mach/regs-rtc.h
deleted file mode 100644
index bd8fdad4f7..0000000000
--- a/arch/arm/mach-mxs/include/mach/regs-rtc.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Freescale i.MX28 RTC Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MX28_REGS_RTC_H__
-#define __MX28_REGS_RTC_H__
-
-#include <mach/regs-common.h>
-
-#ifndef	__ASSEMBLY__
-struct mxs_rtc_regs {
-	mxs_reg_32(hw_rtc_ctrl)
-	mxs_reg_32(hw_rtc_stat)
-	mxs_reg_32(hw_rtc_milliseconds)
-	mxs_reg_32(hw_rtc_seconds)
-	mxs_reg_32(hw_rtc_rtc_alarm)
-	mxs_reg_32(hw_rtc_watchdog)
-	mxs_reg_32(hw_rtc_persistent0)
-	mxs_reg_32(hw_rtc_persistent1)
-	mxs_reg_32(hw_rtc_persistent2)
-	mxs_reg_32(hw_rtc_persistent3)
-	mxs_reg_32(hw_rtc_persistent4)
-	mxs_reg_32(hw_rtc_persistent5)
-	mxs_reg_32(hw_rtc_debug)
-	mxs_reg_32(hw_rtc_version)
-};
-#endif
-
-#define	RTC_CTRL_SFTRST				(1 << 31)
-#define	RTC_CTRL_CLKGATE			(1 << 30)
-#define	RTC_CTRL_SUPPRESS_COPY2ANALOG		(1 << 6)
-#define	RTC_CTRL_FORCE_UPDATE			(1 << 5)
-#define	RTC_CTRL_WATCHDOGEN			(1 << 4)
-#define	RTC_CTRL_ONEMSEC_IRQ			(1 << 3)
-#define	RTC_CTRL_ALARM_IRQ			(1 << 2)
-#define	RTC_CTRL_ONEMSEC_IRQ_EN			(1 << 1)
-#define	RTC_CTRL_ALARM_IRQ_EN			(1 << 0)
-
-#define	RTC_STAT_RTC_PRESENT			(1 << 31)
-#define	RTC_STAT_ALARM_PRESENT			(1 << 30)
-#define	RTC_STAT_WATCHDOG_PRESENT		(1 << 29)
-#define	RTC_STAT_XTAL32000_PRESENT		(1 << 28)
-#define	RTC_STAT_XTAL32768_PRESENT		(1 << 27)
-#define	RTC_STAT_STALE_REGS_MASK		(0xff << 16)
-#define	RTC_STAT_STALE_REGS_OFFSET		16
-#define	RTC_STAT_NEW_REGS_MASK			(0xff << 8)
-#define	RTC_STAT_NEW_REGS_OFFSET		8
-
-#define	RTC_MILLISECONDS_COUNT_MASK		0xffffffff
-#define	RTC_MILLISECONDS_COUNT_OFFSET		0
-
-#define	RTC_SECONDS_COUNT_MASK			0xffffffff
-#define	RTC_SECONDS_COUNT_OFFSET		0
-
-#define	RTC_ALARM_VALUE_MASK			0xffffffff
-#define	RTC_ALARM_VALUE_OFFSET			0
-
-#define	RTC_WATCHDOG_COUNT_MASK			0xffffffff
-#define	RTC_WATCHDOG_COUNT_OFFSET		0
-
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK	(0xf << 28)
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET	28
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83	(0x0 << 28)
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78	(0x1 << 28)
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73	(0x2 << 28)
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68	(0x3 << 28)
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62	(0x4 << 28)
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57	(0x5 << 28)
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52	(0x6 << 28)
-#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48	(0x7 << 28)
-#define	RTC_PERSISTENT0_EXTERNAL_RESET		(1 << 21)
-#define	RTC_PERSISTENT0_THERMAL_RESET		(1 << 20)
-#define	RTC_PERSISTENT0_ENABLE_LRADC_PWRUP	(1 << 18)
-#define	RTC_PERSISTENT0_AUTO_RESTART		(1 << 17)
-#define	RTC_PERSISTENT0_DISABLE_PSWITCH		(1 << 16)
-#define	RTC_PERSISTENT0_LOWERBIAS_MASK		(0xf << 14)
-#define	RTC_PERSISTENT0_LOWERBIAS_OFFSET	14
-#define	RTC_PERSISTENT0_LOWERBIAS_NOMINAL	(0x0 << 14)
-#define	RTC_PERSISTENT0_LOWERBIAS_M25P		(0x1 << 14)
-#define	RTC_PERSISTENT0_LOWERBIAS_M50P		(0x3 << 14)
-#define	RTC_PERSISTENT0_DISABLE_XTALOK		(1 << 13)
-#define	RTC_PERSISTENT0_MSEC_RES_MASK		(0x1f << 8)
-#define	RTC_PERSISTENT0_MSEC_RES_OFFSET		8
-#define	RTC_PERSISTENT0_MSEC_RES_1MS		(0x01 << 8)
-#define	RTC_PERSISTENT0_MSEC_RES_2MS		(0x02 << 8)
-#define	RTC_PERSISTENT0_MSEC_RES_4MS		(0x04 << 8)
-#define	RTC_PERSISTENT0_MSEC_RES_8MS		(0x08 << 8)
-#define	RTC_PERSISTENT0_MSEC_RES_16MS		(0x10 << 8)
-#define	RTC_PERSISTENT0_ALARM_WAKE		(1 << 7)
-#define	RTC_PERSISTENT0_XTAL32_FREQ		(1 << 6)
-#define	RTC_PERSISTENT0_XTAL32KHZ_PWRUP		(1 << 5)
-#define	RTC_PERSISTENT0_XTAL24KHZ_PWRUP		(1 << 4)
-#define	RTC_PERSISTENT0_LCK_SECS		(1 << 3)
-#define	RTC_PERSISTENT0_ALARM_EN		(1 << 2)
-#define	RTC_PERSISTENT0_ALARM_WAKE_EN		(1 << 1)
-#define	RTC_PERSISTENT0_CLOCKSOURCE		(1 << 0)
-
-#define	RTC_PERSISTENT1_GENERAL_MASK		0xffffffff
-#define	RTC_PERSISTENT1_GENERAL_OFFSET		0
-#define	RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE	0x0080
-#define	RTC_PERSISTENT1_GENERAL_OTG_HNP		0x0100
-#define	RTC_PERSISTENT1_GENERAL_USB_LPM		0x0200
-#define	RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK	0x0400
-#define	RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER	0x0800
-#define	RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X	0x1000
-
-#define	RTC_PERSISTENT2_GENERAL_MASK		0xffffffff
-#define	RTC_PERSISTENT2_GENERAL_OFFSET		0
-
-#define	RTC_PERSISTENT3_GENERAL_MASK		0xffffffff
-#define	RTC_PERSISTENT3_GENERAL_OFFSET		0
-
-#define	RTC_PERSISTENT4_GENERAL_MASK		0xffffffff
-#define	RTC_PERSISTENT4_GENERAL_OFFSET		0
-
-#define	RTC_PERSISTENT5_GENERAL_MASK		0xffffffff
-#define	RTC_PERSISTENT5_GENERAL_OFFSET		0
-
-#define	RTC_DEBUG_WATCHDOG_RESET_MASK		(1 << 1)
-#define	RTC_DEBUG_WATCHDOG_RESET		(1 << 0)
-
-#define	RTC_VERSION_MAJOR_MASK			(0xff << 24)
-#define	RTC_VERSION_MAJOR_OFFSET		24
-#define	RTC_VERSION_MINOR_MASK			(0xff << 16)
-#define	RTC_VERSION_MINOR_OFFSET		16
-#define	RTC_VERSION_STEP_MASK			0xffff
-#define	RTC_VERSION_STEP_OFFSET			0
-
-#endif	/* __MX28_REGS_RTC_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/revision.h b/arch/arm/mach-mxs/include/mach/revision.h
deleted file mode 100644
index 91f174d8b0..0000000000
--- a/arch/arm/mach-mxs/include/mach/revision.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef __MACH_REVISION_H__
-#define __MACH_REVISION_H__
-
-/* silicon revisions  */
-enum silicon_revision {
-	SILICON_REVISION_1_0 = 0x10,
-	SILICON_REVISION_1_1 = 0x11,
-	SILICON_REVISION_1_2 = 0x12,
-	SILICON_REVISION_1_3 = 0x13,
-	SILICON_REVISION_1_4 = 0x14,
-	SILICON_REVISION_2_0 = 0x20,
-	SILICON_REVISION_2_1 = 0x21,
-	SILICON_REVISION_2_2 = 0x22,
-	SILICON_REVISION_2_3 = 0x23,
-	SILICON_REVISION_3_0 = 0x30,
-	SILICON_REVISION_3_1 = 0x31,
-	SILICON_REVISION_3_2 = 0x32,
-	SILICON_REVISION_UNKNOWN =0xff
-};
-
-int silicon_revision_get(void);
-void silicon_revision_set(const char *soc, int revision);
-
-#endif /* __MACH_REVISION_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/ssp.h b/arch/arm/mach-mxs/include/mach/ssp.h
deleted file mode 100644
index 5eee5c010a..0000000000
--- a/arch/arm/mach-mxs/include/mach/ssp.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Freescale MXS SSP
- *
- * Copyright (C) 2013 Michael Grzeschik <mgr@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- */
-
-#ifndef __SSP_H__
-#define __SSP_H__
-
-#ifdef CONFIG_ARCH_IMX23
-# define HW_SSP_CTRL0		0x000
-# define HW_SSP_CMD0		0x010
-# define HW_SSP_CMD1		0x020
-# define HW_SSP_COMPREF		0x030
-# define HW_SSP_COMPMASK	0x040
-# define HW_SSP_TIMING		0x050
-# define HW_SSP_CTRL1		0x060
-# define HW_SSP_DATA		0x070
-# define HW_SSP_SDRESP0		0x080
-# define HW_SSP_SDRESP1		0x090
-# define HW_SSP_SDRESP2		0x0A0
-# define HW_SSP_SDRESP3		0x0B0
-# define HW_SSP_STATUS		0x0C0
-# define HW_SSP_DEBUG		0x100
-# define HW_SSP_VERSION		0x110
-#endif
-
-#ifdef CONFIG_ARCH_IMX28
-# define HW_SSP_CTRL0		0x000
-# define HW_SSP_CMD0		0x010
-# define HW_SSP_CMD1		0x020
-# define HW_SSP_XFER_COUNT	0x030
-# define HW_SSP_BLOCK_SIZE	0x040
-# define HW_SSP_COMPREF		0x050
-# define HW_SSP_COMPMASK	0x060
-# define HW_SSP_TIMING		0x070
-# define HW_SSP_CTRL1		0x080
-# define HW_SSP_DATA		0x090
-# define HW_SSP_SDRESP0		0x0A0
-# define HW_SSP_SDRESP1		0x0B0
-# define HW_SSP_SDRESP2		0x0C0
-# define HW_SSP_SDRESP3		0x0D0
-# define HW_SSP_DDR_CTRL	0x0E0
-# define HW_SSP_DLL_CTRL	0x0F0
-# define HW_SSP_STATUS		0x100
-# define HW_SSP_DLL_STS		0x110
-# define HW_SSP_DEBUG		0x120
-# define HW_SSP_VERSION		0x130
-#endif
-
-#define SSP_CTRL0_SFTRST		(1 << 31)
-#define SSP_CTRL0_CLKGATE		(1 << 30)
-#define SSP_CTRL0_RUN			(1 << 29)
-#define SSP_CTRL0_LOCK_CS		(1 << 27)
-#define SSP_CTRL0_READ			(1 << 25)
-#define SSP_CTRL0_IGNORE_CRC		(1 << 26)
-#define SSP_CTRL0_DATA_XFER		(1 << 24)
-#define SSP_CTRL0_BUS_WIDTH(x)		(((x) & 0x3) << 22)
-#define SSP_CTRL0_WAIT_FOR_IRQ		(1 << 21)
-#define SSP_CTRL0_WAIT_FOR_CMD		(1 << 20)
-#define SSP_CTRL0_SSP_ASSERT_OUT(x)	(((x) & 0x3) << 20)
-#define SSP_CTRL0_LONG_RESP		(1 << 19)
-#define SSP_CTRL0_GET_RESP		(1 << 17)
-#define SSP_CTRL0_ENABLE		(1 << 16)
-
-#define SSP_CMD0_SLOW_CLK		(1 << 22)
-#define SSP_CMD0_CONT_CLK		(1 << 21)
-#define SSP_CMD0_APPEND_8CYC		(1 << 20)
-#ifdef CONFIG_ARCH_IMX23
-# define SSP_CTRL0_XFER_COUNT(x)	((x) & 0xffff)
-# define SSP_CMD0_BLOCK_SIZE(x)		(((x) & 0xf) << 16)
-# define SSP_CMD0_BLOCK_COUNT(x)	(((x) & 0xff) << 8)
-#endif
-#define SSP_CMD0_CMD(x)			((x) & 0xff)
-
-#ifdef CONFIG_ARCH_IMX28
-# define SSP_BLOCK_SIZE(x)		((x) & 0xf)
-# define SSP_BLOCK_COUNT(x)		(((x) & 0xffffff) << 4)
-#endif
-
-/* bit definition for register HW_SSP_TIMING */
-#define SSP_TIMING_TIMEOUT_MASK	(0xffff0000)
-#define SSP_TIMING_TIMEOUT(x)		((x) << 16)
-#define SSP_TIMING_CLOCK_DIVIDE(x)	(((x) & 0xff) << 8)
-#define SSP_TIMING_CLOCK_RATE(x)	((x) & 0xff)
-
-/* bit definition for register HW_SSP_CTRL1 */
-#define SSP_CTRL1_POLARITY		(1 << 9)
-#define SSP_CTRL1_PHASE			(1 << 10)
-#define SSP_CTRL1_DMA_ENABLE		(1 << 13)
-#define SSP_CTRL1_WORD_LENGTH(x)	(((x) & 0xf) << 4)
-#define SSP_CTRL1_SSP_MODE(x)		((x) & 0xf)
-
-/* bit definition for register HW_SSP_STATUS */
-# define SSP_STATUS_PRESENT		(1 << 31)
-# define SSP_STATUS_SD_PRESENT		(1 << 29)
-# define SSP_STATUS_CARD_DETECT		(1 << 28)
-# define SSP_STATUS_RESP_CRC_ERR	(1 << 16)
-# define SSP_STATUS_RESP_ERR		(1 << 15)
-# define SSP_STATUS_RESP_TIMEOUT	(1 << 14)
-# define SSP_STATUS_DATA_CRC_ERR	(1 << 13)
-# define SSP_STATUS_TIMEOUT		(1 << 12)
-# define SSP_STATUS_FIFO_OVRFLW		(1 << 9)
-# define SSP_STATUS_FIFO_FULL		(1 << 8)
-# define SSP_STATUS_FIFO_EMPTY		(1 << 5)
-# define SSP_STATUS_FIFO_UNDRFLW	(1 << 4)
-# define SSP_STATUS_CMD_BUSY		(1 << 3)
-# define SSP_STATUS_DATA_BUSY		(1 << 2)
-# define SSP_STATUS_BUSY		(1 << 0)
-# define SSP_STATUS_ERROR		(SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW | \
-	SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR | \
-	SSP_STATUS_RESP_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | SSP_STATUS_TIMEOUT)
-
-#endif	/* __SSP_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/usb.h b/arch/arm/mach-mxs/include/mach/usb.h
deleted file mode 100644
index 2d31b0d0f2..0000000000
--- a/arch/arm/mach-mxs/include/mach/usb.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __MACH_USB_H
-#define __MACH_USB_H
-
-int imx23_usb_phy_enable(void);
-
-int imx28_usb_phy0_enable(void);
-int imx28_usb_phy1_enable(void);
-
-#endif /* __MACH_USB_H */
diff --git a/arch/arm/mach-mxs/iomux-imx.c b/arch/arm/mach-mxs/iomux-imx.c
index 68a4e3cbd6..bf9d600bc7 100644
--- a/arch/arm/mach-mxs/iomux-imx.c
+++ b/arch/arm/mach-mxs/iomux-imx.c
@@ -1,26 +1,14 @@
-/*
- * (C) Copyright 2010 Juergen Beisert - Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix
 
 #include <common.h>
 #include <init.h>
 #include <gpio.h>
 #include <errno.h>
 #include <io.h>
-#include <mach/iomux.h>
+#include <mach/mxs/iomux.h>
 #include <stmp-device.h>
-#include <mach/imx-regs.h>
+#include <mach/mxs/imx-regs.h>
 
 #define HW_PINCTRL_CTRL 0x000
 #define HW_PINCTRL_MUXSEL0 0x100
diff --git a/arch/arm/mach-mxs/lradc-init.c b/arch/arm/mach-mxs/lradc-init.c
index 682a47530d..10d0be77fd 100644
--- a/arch/arm/mach-mxs/lradc-init.c
+++ b/arch/arm/mach-mxs/lradc-init.c
@@ -10,9 +10,9 @@
 #include <common.h>
 #include <config.h>
 #include <asm/io.h>
-#include <mach/imx-regs.h>
-#include <mach/regs-lradc.h>
-#include <mach/init.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/regs-lradc.h>
+#include <mach/mxs/init.h>
 
 void mxs_lradc_init(void)
 {
diff --git a/arch/arm/mach-mxs/mem-init.c b/arch/arm/mach-mxs/mem-init.c
index 44785c2bfc..0d289266d0 100644
--- a/arch/arm/mach-mxs/mem-init.c
+++ b/arch/arm/mach-mxs/mem-init.c
@@ -12,16 +12,16 @@
 #include <common.h>
 #include <config.h>
 #include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/mxs/imx-regs.h>
 #include <linux/compiler.h>
 
-#include <mach/init.h>
-#include <mach/regs-power-mx28.h>
+#include <mach/mxs/init.h>
+#include <mach/mxs/regs-power-mx28.h>
 #if defined CONFIG_ARCH_IMX23
-# include <mach/regs-clkctrl-mx23.h>
+#include <mach/mxs/regs-clkctrl-mx23.h>
 #endif
 #if defined CONFIG_ARCH_IMX28
-# include <mach/regs-clkctrl-mx28.h>
+#include <mach/mxs/regs-clkctrl-mx28.h>
 #endif
 
 /* 1 second delay should be plenty of time for block reset. */
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
index a4df39c2e9..9e86ac9559 100644
--- a/arch/arm/mach-mxs/ocotp.c
+++ b/arch/arm/mach-mxs/ocotp.c
@@ -1,15 +1,8 @@
-/*
- * ocotp.c - barebox driver for the On-Chip One Time Programmable for MXS
- *
- * Copyright (C) 2012 by Wolfram Sang, Pengutronix e.K.
- * based on the kernel driver which is
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2012 Wolfram Sang, Pengutronix e.K.
+// SPDX-FileCopyrightText: 2010 Freescale Semiconductor, Inc.
+
+/* ocotp.c - barebox driver for the On-Chip One Time Programmable for MXS */
 
 #include <common.h>
 #include <init.h>
@@ -25,9 +18,9 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
-#include <mach/generic.h>
-#include <mach/ocotp.h>
-#include <mach/power.h>
+#include <mach/mxs/generic.h>
+#include <mach/mxs/ocotp.h>
+#include <mach/mxs/power.h>
 
 #define DRIVERNAME "ocotp"
 
@@ -43,7 +36,7 @@
 #define OCOTP_WORD_OFFSET		0x20
 
 struct ocotp_priv {
-	struct device_d dev;
+	struct device dev;
 	struct cdev cdev;
 	void __iomem *base;
 	unsigned int write_enable;
@@ -176,7 +169,7 @@ static struct cdev_operations mxs_ocotp_ops = {
 	.read	= mxs_ocotp_cdev_read,
 };
 
-static int mxs_ocotp_probe(struct device_d *dev)
+static int mxs_ocotp_probe(struct device *dev)
 {
 	struct resource *iores;
 	int err;
@@ -222,8 +215,9 @@ static __maybe_unused struct of_device_id mxs_ocotp_compatible[] = {
 		/* sentinel */
 	}
 };
+MODULE_DEVICE_TABLE(of, mxs_ocotp_compatible);
 
-static struct driver_d mxs_ocotp_driver = {
+static struct driver mxs_ocotp_driver = {
 	.name	= DRIVERNAME,
 	.probe	= mxs_ocotp_probe,
 	.of_compatible = DRV_OF_COMPAT(mxs_ocotp_compatible),
@@ -236,7 +230,7 @@ int mxs_ocotp_read(void *buf, int count, int offset)
 	struct cdev *cdev;
 	int ret;
 
-	cdev = cdev_open(DRIVERNAME, O_RDONLY);
+	cdev = cdev_open_by_name(DRIVERNAME, O_RDONLY);
 	if (!cdev)
 		return -ENODEV;
 
diff --git a/arch/arm/mach-mxs/power-init.c b/arch/arm/mach-mxs/power-init.c
index c89f1f5f5d..408ff8ba99 100644
--- a/arch/arm/mach-mxs/power-init.c
+++ b/arch/arm/mach-mxs/power-init.c
@@ -10,19 +10,19 @@
 #include <common.h>
 #include <config.h>
 #include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/mxs/imx-regs.h>
 
-#include <mach/generic.h>
-#include <mach/init.h>
+#include <mach/mxs/generic.h>
+#include <mach/mxs/init.h>
 #ifdef CONFIG_ARCH_IMX23
-#include <mach/regs-clkctrl-mx23.h>
+#include <mach/mxs/regs-clkctrl-mx23.h>
 #endif
 #ifdef CONFIG_ARCH_IMX28
-#include <mach/regs-clkctrl-mx28.h>
+#include <mach/mxs/regs-clkctrl-mx28.h>
 #endif
-#include <mach/regs-power-mx28.h>
-#include <mach/regs-rtc.h>
-#include <mach/regs-lradc.h>
+#include <mach/mxs/regs-power-mx28.h>
+#include <mach/mxs/regs-rtc.h>
+#include <mach/mxs/regs-lradc.h>
 
 int power_config;
 
diff --git a/arch/arm/mach-mxs/power.c b/arch/arm/mach-mxs/power.c
index 6febf5dbaa..2672a014a1 100644
--- a/arch/arm/mach-mxs/power.c
+++ b/arch/arm/mach-mxs/power.c
@@ -1,20 +1,15 @@
-/*
- * i.MX28 power related functions
- *
- * Copyright 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- * Copyright (C) 2012 Wolfram Sang, Pengutronix <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+// SPDX-FileCopyrightText: 2012 Wolfram Sang <w.sang@pengutronix.de>, Pengutronix
+
+/* i.MX28 power related functions */
+
 #include <common.h>
 #include <io.h>
 #include <stmp-device.h>
 #include <errno.h>
-#include <mach/imx-regs.h>
-#include <mach/power.h>
+#include <mach/mxs/imx-regs.h>
+#include <mach/mxs/power.h>
 
 #define POWER_CTRL			(IMX_POWER_BASE + 0x0)
 #define POWER_CTRL_CLKGATE		0x40000000
diff --git a/arch/arm/mach-mxs/soc-imx23.c b/arch/arm/mach-mxs/soc-imx23.c
index 8c47c766cc..b799812c52 100644
--- a/arch/arm/mach-mxs/soc-imx23.c
+++ b/arch/arm/mach-mxs/soc-imx23.c
@@ -1,26 +1,15 @@
-/*
- * (c) 2012 Juergen Beisert <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * Collection of some SoC specific functions
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2012 Juergen Beisert <kernel@pengutronix.de>
+
+/* Collection of some SoC specific functions */
 
 #include <common.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/imx23-regs.h>
+#include <mach/mxs/imx23-regs.h>
 #include <io.h>
 #include <asm/memory.h>
-#include <mach/imx23.h>
+#include <mach/mxs/imx23.h>
 
 #define HW_CLKCTRL_RESET 0x120
 # define HW_CLKCTRL_RESET_CHIP (1 << 1)
diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c
index a214e2b7a6..4a9697b8e4 100644
--- a/arch/arm/mach-mxs/soc-imx28.c
+++ b/arch/arm/mach-mxs/soc-imx28.c
@@ -1,26 +1,15 @@
-/*
- * (c) 2012 Juergen Beisert <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * Collection of some SoC specific functions
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2012 Juergen Beisert <kernel@pengutronix.de>
+
+/* Collection of some SoC specific functions */
 
 #include <common.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/imx28-regs.h>
+#include <mach/mxs/imx28-regs.h>
 #include <io.h>
 #include <asm/memory.h>
-#include <mach/imx28.h>
+#include <mach/mxs/imx28.h>
 
 #define HW_CLKCTRL_RESET 0x1e0
 # define HW_CLKCTRL_RESET_CHIP (1 << 1)
diff --git a/arch/arm/mach-mxs/usb-imx23.c b/arch/arm/mach-mxs/usb-imx23.c
index d9a54b66f8..37d267b4a9 100644
--- a/arch/arm/mach-mxs/usb-imx23.c
+++ b/arch/arm/mach-mxs/usb-imx23.c
@@ -1,23 +1,13 @@
-/*
- * i.MX23 USBPHY setup
- *
- * Copyright 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+
+/* i.MX23 USBPHY setup */
+
 #include <common.h>
 #include <io.h>
-#include <mach/imx23-regs.h>
-#include <mach/power.h>
-#include <mach/usb.h>
+#include <mach/mxs/imx23-regs.h>
+#include <mach/mxs/power.h>
+#include <mach/mxs/usb.h>
 
 #define USBPHY_PWD			(IMX_USBPHY_BASE + 0x0)
 
diff --git a/arch/arm/mach-mxs/usb-imx28.c b/arch/arm/mach-mxs/usb-imx28.c
index a4e1bdb280..9c65dc7212 100644
--- a/arch/arm/mach-mxs/usb-imx28.c
+++ b/arch/arm/mach-mxs/usb-imx28.c
@@ -1,24 +1,13 @@
-/*
- * i.MX28 USBPHY setup
- *
- * Copyright 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+
+/* i.MX28 USBPHY setup */
+
 #include <common.h>
 #include <io.h>
 #include <errno.h>
-#include <mach/imx28-regs.h>
-#include <mach/usb.h>
+#include <mach/mxs/imx28-regs.h>
+#include <mach/mxs/usb.h>
 
 #define POWER_CTRL			(IMX_POWER_BASE + 0x0)
 #define POWER_CTRL_CLKGATE		0x40000000
diff --git a/arch/arm/mach-nomadik/8815.c b/arch/arm/mach-nomadik/8815.c
index 9f9c0342b4..78b4ed8d5e 100644
--- a/arch/arm/mach-nomadik/8815.c
+++ b/arch/arm/mach-nomadik/8815.c
@@ -17,10 +17,10 @@
 #include <common.h>
 #include <init.h>
 #include <linux/clkdev.h>
-#include <mach/hardware.h>
-#include <mach/board.h>
+#include <mach/nomadik/hardware.h>
+#include <mach/nomadik/board.h>
 #include <asm/armlinux.h>
-#include <generated/mach-types.h>
+#include <asm/mach-types.h>
 #include <linux/amba/bus.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 51d490df1b..8237779173 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_NOMADIK
 
 config ARCH_TEXT_BASE
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
index 1d77c4cf52..0ab83f61c8 100644
--- a/arch/arm/mach-nomadik/Makefile
+++ b/arch/arm/mach-nomadik/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 obj-y	+= clock.o reset.o timer.o
 obj-y	+= 8815.o
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
index f3ea958aec..e68097ade8 100644
--- a/arch/arm/mach-nomadik/clock.c
+++ b/arch/arm/mach-nomadik/clock.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 /*
  * linux/arch/arm/mach-nomadik/clock.c
  *
diff --git a/arch/arm/mach-nomadik/include/mach/board.h b/arch/arm/mach-nomadik/include/mach/board.h
deleted file mode 100644
index 49004a6825..0000000000
--- a/arch/arm/mach-nomadik/include/mach/board.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-
-void st8815_add_device_sdram(u32 size);
-
-void st8815_register_uart(unsigned id);
-
-#endif
diff --git a/arch/arm/mach-nomadik/include/mach/fsmc.h b/arch/arm/mach-nomadik/include/mach/fsmc.h
deleted file mode 100644
index e010c7215c..0000000000
--- a/arch/arm/mach-nomadik/include/mach/fsmc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Definitions for the Nomadik FSMC "Flexible Static Memory controller" */
-
-#ifndef __ASM_ARCH_FSMC_H
-#define __ASM_ARCH_FSMC_H
-
-#include <mach/hardware.h>
-/*
- * Register list
- */
-
-/* bus control reg. and bus timing reg. for CS0..CS3 */
-#define FSMC_BCR(x)     (NOMADIK_FSMC_VA + (x << 3))
-#define FSMC_BTR(x)     (NOMADIK_FSMC_VA + (x << 3) + 0x04)
-
-/* PC-card and NAND:
- * PCR = control register
- * PMEM = memory timing
- * PATT = attribute timing
- * PIO = I/O timing
- * PECCR = ECC result
- */
-#define FSMC_PCR(x)     (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x00)
-#define FSMC_PMEM(x)    (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x08)
-#define FSMC_PATT(x)    (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x0c)
-#define FSMC_PIO(x)     (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x10)
-#define FSMC_PECCR(x)   (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x14)
-
-#endif /* __ASM_ARCH_FSMC_H */
diff --git a/arch/arm/mach-nomadik/include/mach/hardware.h b/arch/arm/mach-nomadik/include/mach/hardware.h
deleted file mode 100644
index c050b2f421..0000000000
--- a/arch/arm/mach-nomadik/include/mach/hardware.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file contains the hardware definitions of the Nomadik.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* Nomadik registers live from 0x1000.0000 to 0x1023.0000 -- currently */
-#define NOMADIK_IO_VIRTUAL	0xF0000000	/* VA of IO */
-#define NOMADIK_IO_PHYSICAL	0x10000000	/* PA of IO */
-#define NOMADIK_IO_SIZE		0x00300000	/* 3MB for all regs */
-
-#ifndef CONFIG_MMU
-#define io_p2v(x) (x)
-#define io_v2p(x) (x)
-#else
-#define io_p2v(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
-#define io_v2p(x) ((x) - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
-#endif
-
-#define IO_ADDRESS(x) (io_p2v(x)) /* used in asm and more */
-
-/*
- * Base address defination for Nomadik Onchip Logic Block
- */
-#define NOMADIK_FSMC_BASE	0x10100000	/* FSMC registers */
-#define NOMADIK_SDRAMC_BASE	0x10110000	/* SDRAM Controller */
-#define NOMADIK_CLCDC_BASE	0x10120000	/* CLCD Controller */
-#define NOMADIK_MDIF_BASE	0x10120000	/* MDIF */
-#define NOMADIK_DMA0_BASE	0x10130000	/* DMA0 Controller */
-#define NOMADIK_IC_BASE		0x10140000	/* Vectored Irq Controller */
-#define NOMADIK_DMA1_BASE	0x10150000	/* DMA1 Controller */
-#define NOMADIK_USB_BASE	0x10170000	/* USB-OTG conf reg base */
-#define NOMADIK_CRYP_BASE	0x10180000	/* Crypto processor */
-#define NOMADIK_SHA1_BASE	0x10190000	/* SHA-1 Processor */
-#define NOMADIK_XTI_BASE	0x101A0000	/* XTI */
-#define NOMADIK_RNG_BASE	0x101B0000	/* Random number generator */
-#define NOMADIK_SRC_BASE	0x101E0000	/* SRC base */
-#define NOMADIK_WDOG_BASE	0x101E1000	/* Watchdog */
-#define NOMADIK_MTU0_BASE	0x101E2000	/* Multiple Timer 0 */
-#define NOMADIK_MTU1_BASE	0x101E3000	/* Multiple Timer 1 */
-#define NOMADIK_GPIO0_BASE	0x101E4000	/* GPIO0 */
-#define NOMADIK_GPIO1_BASE	0x101E5000	/* GPIO1 */
-#define NOMADIK_GPIO2_BASE	0x101E6000	/* GPIO2 */
-#define NOMADIK_GPIO3_BASE	0x101E7000	/* GPIO3 */
-#define NOMADIK_RTC_BASE	0x101E8000	/* Real Time Clock base */
-#define NOMADIK_PMU_BASE	0x101E9000	/* Power Management Unit */
-#define NOMADIK_OWM_BASE	0x101EA000	/* One wire master */
-#define NOMADIK_SCR_BASE	0x101EF000	/* Secure Control registers */
-#define NOMADIK_MSP2_BASE	0x101F0000	/* MSP 2 interface */
-#define NOMADIK_MSP1_BASE	0x101F1000	/* MSP 1 interface */
-#define NOMADIK_UART2_BASE	0x101F2000	/* UART 2 interface */
-#define NOMADIK_SSIRx_BASE	0x101F3000	/* SSI 8-ch rx interface */
-#define NOMADIK_SSITx_BASE	0x101F4000	/* SSI 8-ch tx interface */
-#define NOMADIK_MSHC_BASE	0x101F5000	/* Memory Stick(Pro) Host */
-#define NOMADIK_SDI_BASE	0x101F6000	/* SD-card/MM-Card */
-#define NOMADIK_I2C1_BASE	0x101F7000	/* I2C1 interface */
-#define NOMADIK_I2C0_BASE	0x101F8000	/* I2C0 interface */
-#define NOMADIK_MSP0_BASE	0x101F9000	/* MSP 0 interface */
-#define NOMADIK_FIRDA_BASE	0x101FA000	/* FIrDA interface */
-#define NOMADIK_UART1_BASE	0x101FB000	/* UART 1 interface */
-#define NOMADIK_SSP_BASE	0x101FC000	/* SSP interface */
-#define NOMADIK_UART0_BASE	0x101FD000	/* UART 0 interface */
-#define NOMADIK_SGA_BASE	0x101FE000	/* SGA interface */
-#define NOMADIK_L2CC_BASE	0x10210000	/* L2 Cache controller */
-
-/* Other ranges, not for p2v/v2p */
-#define NOMADIK_BACKUP_RAM	0x80010000
-#define NOMADIK_EBROM		0x80000000	/* Embedded boot ROM */
-#define NOMADIK_HAMACV_DMEM_BASE 0xA0100000	/* HAMACV Data Memory Start */
-#define NOMADIK_HAMACV_DMEM_END	0xA01FFFFF	/* HAMACV Data Memory End */
-#define NOMADIK_HAMACA_DMEM	0xA0200000	/* HAMACA Data Memory Space */
-
-#define NOMADIK_FSMC_VA		IO_ADDRESS(NOMADIK_FSMC_BASE)
-#define NOMADIK_MTU0_VA		IO_ADDRESS(NOMADIK_MTU0_BASE)
-#define NOMADIK_MTU1_VA		IO_ADDRESS(NOMADIK_MTU1_BASE)
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-nomadik/include/mach/nand.h b/arch/arm/mach-nomadik/include/mach/nand.h
deleted file mode 100644
index 544f0e02c7..0000000000
--- a/arch/arm/mach-nomadik/include/mach/nand.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_ARCH_NAND_H
-#define __ASM_ARCH_NAND_H
-
-struct nomadik_nand_platform_data {
-	int options;
-	int (*init) (void);
-};
-
-#define NAND_IO_DATA	0x40000000
-#define NAND_IO_CMD	0x40800000
-#define NAND_IO_ADDR	0x41000000
-
-#endif				/* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/mach-nomadik/reset.c b/arch/arm/mach-nomadik/reset.c
index d5266068e2..d3d54de07e 100644
--- a/arch/arm/mach-nomadik/reset.c
+++ b/arch/arm/mach-nomadik/reset.c
@@ -18,7 +18,7 @@
 #include <init.h>
 #include <io.h>
 #include <restart.h>
-#include <mach/hardware.h>
+#include <mach/nomadik/hardware.h>
 
 static void __noreturn nomadik_restart_soc(struct restart_handler *rst)
 {
diff --git a/arch/arm/mach-nomadik/timer.c b/arch/arm/mach-nomadik/timer.c
index 0b8dc866eb..73abbe9b91 100644
--- a/arch/arm/mach-nomadik/timer.c
+++ b/arch/arm/mach-nomadik/timer.c
@@ -11,7 +11,7 @@
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/hardware.h>
+#include <mach/nomadik/hardware.h>
 
 /* Initial value for SRC control register: all timers use MXTAL/8 source */
 #define SRC_CR_INIT_MASK	0x00007fff
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 220b635167..f0e035e31e 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -168,6 +168,12 @@ config MACH_BEAGLEBONE
 	help
 	  Say Y here if you are using Beagle Bone
 
+config MACH_MYIRTECH_X335X
+	bool "MYIR Tech Limited SOMs"
+	select ARCH_AM33XX
+	help
+	  Say Y here if you are using a TI AM335X based MYIR SOM
+
 config MACH_PHYTEC_SOM_AM335X
 	bool "Phytec AM335X SOMs"
 	select ARCH_AM33XX
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 36b2aa090e..6b42196b23 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -15,14 +15,14 @@
 # GNU General Public License for more details.
 #
 #
-obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o
-pbl-$(CONFIG_ARCH_OMAP) += syslib.o
+obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o
+pbl-$(CONFIG_ARCH_OMAP) += syslib.o omap_generic.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
 pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
-obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o
-obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o am35xx_emif4.o
+obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o emif4.o
+obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o emif4.o
 obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_clock.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_clock.o
diff --git a/arch/arm/mach-omap/am33xx_bbu_emmc.c b/arch/arm/mach-omap/am33xx_bbu_emmc.c
index 29e13de778..3cae31d34c 100644
--- a/arch/arm/mach-omap/am33xx_bbu_emmc.c
+++ b/arch/arm/mach-omap/am33xx_bbu_emmc.c
@@ -18,7 +18,7 @@
 #include <fs.h>
 #include <fcntl.h>
 #include <filetype.h>
-#include <mach/bbu.h>
+#include <mach/omap/bbu.h>
 
 #define PART_TABLE_SIZE		66
 #define PART_TABLE_OFFSET	0x1BE
@@ -42,16 +42,15 @@ static int emmc_mlo_handler(struct bbu_handler *handler, struct bbu_data *data)
 
 	fd = open(handler->devicefile, O_RDWR);
 	if (fd < 0) {
-		pr_err("could not open %s: %s\n", handler->devicefile,
-			errno_str());
+		pr_err("could not open %s: %m\n", handler->devicefile);
 		return fd;
 	}
 
 	/* save the partition table */
 	ret = pread(fd, part_table, PART_TABLE_SIZE, PART_TABLE_OFFSET);
 	if (ret < 0) {
-		pr_err("could not read partition table from fd %s: %s\n",
-			handler->devicefile, errno_str());
+		pr_err("could not read partition table from fd %s: %m\n",
+			handler->devicefile);
 		goto error;
 	}
 
@@ -59,8 +58,8 @@ static int emmc_mlo_handler(struct bbu_handler *handler, struct bbu_data *data)
 	for (i = 0; i < 4; i++) {
 		ret = pwrite(fd, image, size, i * 0x20000);
 		if (ret < 0) {
-			pr_err("could not write MLO %i/4 to fd %s: %s\n",
-				i + 1, handler->devicefile, errno_str());
+			pr_err("could not write MLO %i/4 to fd %s: %m\n",
+				i + 1, handler->devicefile);
 			goto error_save_part_table;
 		}
 	}
@@ -69,8 +68,8 @@ error_save_part_table:
 	/* write the partition table back */
 	ret = pwrite(fd, part_table, PART_TABLE_SIZE, PART_TABLE_OFFSET);
 	if (ret < 0)
-		pr_err("could not write partition table to fd %s: %s\n",
-			handler->devicefile, errno_str());
+		pr_err("could not write partition table to fd %s: %m\n",
+			handler->devicefile);
 
 error:
 	close(fd);
diff --git a/arch/arm/mach-omap/am33xx_bbu_nand.c b/arch/arm/mach-omap/am33xx_bbu_nand.c
index 8c487c8ebb..40e382780a 100644
--- a/arch/arm/mach-omap/am33xx_bbu_nand.c
+++ b/arch/arm/mach-omap/am33xx_bbu_nand.c
@@ -24,7 +24,7 @@
 #include <filetype.h>
 #include <linux/mtd/mtd.h>
 #include <mtd/mtd-peb.h>
-#include <mach/bbu.h>
+#include <mach/omap/bbu.h>
 
 struct nand_bbu_handler {
 	struct bbu_handler bbu_handler;
@@ -213,7 +213,7 @@ static int nand_update_handler_complete(struct bbu_handler *handler,
 
 		buf = xzalloc(mtd->erasesize);
 		memcpy(buf, data->image, data->len);
-	
+
 		for (i = 0; i < 4; i++) {
 			if (mtd_peb_is_bad(mtd, i)) {
 				pr_info("PEB%d is bad, skipping\n", i);
diff --git a/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c
index 7d2ef1f0f2..2c58c9ae69 100644
--- a/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c
+++ b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c
@@ -20,7 +20,7 @@
 #include <fs.h>
 #include <fcntl.h>
 #include <linux/stat.h>
-#include <mach/bbu.h>
+#include <mach/omap/bbu.h>
 
 /*
  * AM35xx, AM33xx chips use big endian MLO for SPI NOR flash
@@ -51,7 +51,7 @@ static int spi_nor_mlo_handler(struct bbu_handler *handler,
 
 	ret = stat(data->devicefile, &s);
 	if (ret) {
-		printf("could not open %s: %s", data->devicefile, errno_str());
+		printf("could not open %s: %m", data->devicefile);
 		return ret;
 	}
 
@@ -66,14 +66,14 @@ static int spi_nor_mlo_handler(struct bbu_handler *handler,
 
 	dstfd = open(data->devicefile, O_WRONLY);
 	if (dstfd < 0) {
-		printf("could not open %s: %s", data->devicefile, errno_str());
+		printf("could not open %s: %m", data->devicefile);
 		ret = dstfd;
 		goto out;
 	}
 
 	ret = erase(dstfd, ERASE_SIZE_ALL, 0);
 	if (ret < 0) {
-		printf("could not erase %s: %s", data->devicefile, errno_str());
+		printf("could not erase %s: %m", data->devicefile);
 		goto out1;
 	}
 
diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c
index a5ac6f68c0..4ba10491be 100644
--- a/arch/arm/mach-omap/am33xx_clock.c
+++ b/arch/arm/mach-omap/am33xx_clock.c
@@ -14,8 +14,8 @@
  */
 #include <common.h>
 #include <asm/io.h>
-#include <mach/am33xx-clock.h>
-#include <mach/am33xx-generic.h>
+#include <mach/omap/am33xx-clock.h>
+#include <mach/omap/am33xx-generic.h>
 #include <linux/math64.h>
 
 #define PRCM_MOD_EN		0x2
@@ -169,6 +169,11 @@ void am33xx_enable_per_clocks(void)
 	__raw_writel(PRCM_MOD_EN, CM_WKUP_ADC_TSC_CLKCTRL);
 	while (__raw_readl(CM_WKUP_ADC_TSC_CLKCTRL) != PRCM_MOD_EN);
 
+	if (IS_ENABLED(CONFIG_HW_RANDOM_OMAP)) {
+		__raw_writel(PRCM_MOD_EN, CM_PER_RNG_CLKCTRL);
+		while ((__raw_readl(CM_PER_RNG_CLKCTRL) & 0x30000) != 0x0);
+	}
+
 	clkdcoldo = __raw_readl(CM_CLKDCOLDO_DPLL_PER);
 	clkdcoldo = clkdcoldo | 0x100;
 	__raw_writel(clkdcoldo, CM_CLKDCOLDO_DPLL_PER);
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index 3c5cdf065c..850fbceaec 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -21,12 +21,13 @@
 #include <net.h>
 #include <restart.h>
 #include <asm/barebox-arm.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/am33xx-clock.h>
-#include <mach/generic.h>
-#include <mach/sys_info.h>
-#include <mach/am33xx-generic.h>
-#include <mach/gpmc.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/am33xx-clock.h>
+#include <mach/omap/emif4.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/am33xx-generic.h>
+#include <mach/omap/gpmc.h>
 #include <reset_source.h>
 
 static void __noreturn am33xx_restart_soc(struct restart_handler *rst)
@@ -152,8 +153,7 @@ static int am33xx_bootsource(void)
 	default:
 		src = BOOTSOURCE_UNKNOWN;
 	}
-	bootsource_set(src);
-	bootsource_set_instance(instance);
+	bootsource_set_raw(src, instance);
 	return 0;
 }
 
@@ -307,18 +307,20 @@ void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl)
 
 void am33xx_config_sdram(const struct am33xx_emif_regs *regs)
 {
-	writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
-	writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
-	writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
-	writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
-	writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
-	writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
-	writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
-	writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
-	writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
+	const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE);
+
+	writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1);
+	writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW);
+	writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_2);
+	writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1);
+	writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW);
+	writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2);
+	writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW);
+	writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3);
+	writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW);
 
 	if (regs->ocp_config)
-		writel(regs->ocp_config, AM33XX_EMIF4_0_REG(OCP_CONFIG));
+		writel(regs->ocp_config, emif4 + EMIF4_OCP_CONFIG);
 
 	if (regs->zq_config) {
 		/*
@@ -326,75 +328,23 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs)
 		 * about 570us for a delay, which will be long enough
 		 * to configure things.
 		 */
-		writel(0x2800, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-		writel(regs->zq_config, AM33XX_EMIF4_0_REG(ZQ_CONFIG));
+		writel(0x2800, emif4 + EMIF4_SDRAM_REF_CTRL);
+		writel(regs->zq_config, emif4 + EMIF4_ZQ_CONFIG);
 		writel(regs->sdram_config, CM_EMIF_SDRAM_CONFIG);
-		writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-		writel(regs->sdram_ref_ctrl,
-				AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-		writel(regs->sdram_ref_ctrl,
-			AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
+		writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG);
+		writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL);
+		writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
 	}
 
-	writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-	writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-}
-
-/**
- * am335x_sdram_size - read back SDRAM size from sdram_config register
- *
- * @return: The SDRAM size
- */
-unsigned long am335x_sdram_size(void)
-{
-	int rows, cols, width, banks;
-	unsigned long size;
-	uint32_t sdram_config = readl(CM_EMIF_SDRAM_CONFIG);
-
-	rows = ((sdram_config >> 7) & 0x7) + 9;
-	cols = (sdram_config & 0x7) + 8;
-
-	switch ((sdram_config >> 14) & 0x3) {
-	case 0:
-		width = 4;
-		break;
-	case 1:
-		width = 2;
-		break;
-	default:
-		return 0;
-	}
-
-	switch ((sdram_config >> 4) & 0x7) {
-	case 0:
-		banks = 1;
-		break;
-	case 1:
-		banks = 2;
-		break;
-	case 2:
-		banks = 4;
-		break;
-	case 3:
-		banks = 8;
-		break;
-	default:
-		return 0;
-	}
-
-	size = (1 << rows) * (1 << cols) * banks * width;
-
-	debug("%s: sdram_config: 0x%08x cols: %2d rows: %2d width: %2d banks: %2d size: 0x%08lx\n",
-			__func__, sdram_config, cols, rows, width, banks, size);
-
-	return size;
+	writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL);
+	writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
+	writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG);
 }
 
 void __noreturn am335x_barebox_entry(void *boarddata)
 {
-	barebox_arm_entry(0x80000000, am335x_sdram_size(), boarddata);
+	barebox_arm_entry(0x80000000,
+			  emif4_sdram_size(IOMEM(AM33XX_EMIF4_BASE)), boarddata);
 }
 
 void am33xx_config_io_ctrl(int ioctrl)
@@ -469,7 +419,7 @@ void am33xx_select_rmii2_crs_dv(void)
 
 int am33xx_of_register_bootdevice(void)
 {
-	struct device_d *dev;
+	struct device *dev;
 
 	switch (bootsource_get()) {
 	case BOOTSOURCE_MMC:
diff --git a/arch/arm/mach-omap/am33xx_mux.c b/arch/arm/mach-omap/am33xx_mux.c
index cc96ced18e..3192e332c6 100644
--- a/arch/arm/mach-omap/am33xx_mux.c
+++ b/arch/arm/mach-omap/am33xx_mux.c
@@ -15,8 +15,8 @@
 #include <common.h>
 #include <config.h>
 #include <asm/io.h>
-#include <mach/am33xx-mux.h>
-#include <mach/am33xx-silicon.h>
+#include <mach/omap/am33xx-mux.h>
+#include <mach/omap/am33xx-silicon.h>
 
 #define MUX_CFG(value, offset)	\
 	__raw_writel(value, (AM33XX_CTRL_BASE + offset));
diff --git a/arch/arm/mach-omap/am33xx_scrm.c b/arch/arm/mach-omap/am33xx_scrm.c
index 80510cf5b4..431e72fdda 100644
--- a/arch/arm/mach-omap/am33xx_scrm.c
+++ b/arch/arm/mach-omap/am33xx_scrm.c
@@ -20,13 +20,13 @@
 #include <of.h>
 #include <asm/barebox-arm.h>
 #include <asm/memory.h>
-#include <mach/am33xx-silicon.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/emif4.h>
 
-static int am33xx_scrm_probe(struct device_d *dev)
+static int am33xx_scrm_probe(struct device *dev)
 {
-	arm_add_mem_device("ram0", 0x80000000, am335x_sdram_size());
-
-	return 0;
+	return arm_add_mem_device("ram0", 0x80000000,
+				  emif4_sdram_size(IOMEM(AM33XX_EMIF4_BASE)));
 }
 
 static __maybe_unused struct of_device_id am33xx_scrm_dt_ids[] = {
@@ -36,8 +36,9 @@ static __maybe_unused struct of_device_id am33xx_scrm_dt_ids[] = {
 		/* sentinel */
 	}
 };
+MODULE_DEVICE_TABLE(of, am33xx_scrm_dt_ids);
 
-static struct driver_d am33xx_scrm_driver = {
+static struct driver am33xx_scrm_driver = {
 	.name   = "am33xx-scrm",
 	.probe  = am33xx_scrm_probe,
 	.of_compatible = DRV_OF_COMPAT(am33xx_scrm_dt_ids),
diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c
deleted file mode 100644
index 678a338fd6..0000000000
--- a/arch/arm/mach-omap/am35xx_emif4.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Author :
- *     Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Based on mem.c and sdrc.c
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <io.h>
-#include <mach/emif4.h>
-#include <mach/omap3-silicon.h>
-
-/*
- * do_pac200_emif4_init -
- *  - Init the emif4 module for DDR access
- *  - Early init routines, called from flash or SRAM.
- */
-void am35xx_emif4_init(void)
-{
-	unsigned int regval;
-	struct emif4 *emif4_base = IOMEM(OMAP3_SDRC_BASE);
-
-	/* Set the DDR PHY parameters in PHY ctrl registers */
-	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
-		EMIF4_DDR1_EXT_STRB_DIS);
-	writel(regval, &emif4_base->ddr_phyctrl1);
-	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
-	writel(0, &emif4_base->ddr_phyctrl2);
-
-	/* Reset the DDR PHY and wait till completed */
-	regval = readl(&emif4_base->sdram_iodft_tlgc);
-	regval |= (1 << 10);
-	writel(regval, &emif4_base->sdram_iodft_tlgc);
-
-	/* Wait till that bit clears*/
-	while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10));
-
-	/* Re-verify the DDR PHY status*/
-	while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0);
-
-	regval |= (1 << 0);
-	writel(regval, &emif4_base->sdram_iodft_tlgc);
-
-	/* Set SDR timing registers */
-	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
-		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
-		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
-		EMIF4_TIM1_T_RP);
-	writel(regval, &emif4_base->sdram_time1);
-	writel(regval, &emif4_base->sdram_time1_shdw);
-
-	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
-		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
-		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
-	writel(regval, &emif4_base->sdram_time2);
-	writel(regval, &emif4_base->sdram_time2_shdw);
-
-	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
-	writel(regval, &emif4_base->sdram_time3);
-	writel(regval, &emif4_base->sdram_time3_shdw);
-
-	/* Set the PWR control register */
-	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
-		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
-	writel(regval, &emif4_base->sdram_pwr_mgmt);
-	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
-
-	/* Set the DDR refresh rate control register */
-	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
-	writel(regval, &emif4_base->sdram_refresh_ctrl);
-	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
-
-	/* set the SDRAM configuration register */
-	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
-		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
-		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
-		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
-		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
-		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
-	writel(regval, &emif4_base->sdram_config);
-}
diff --git a/arch/arm/mach-omap/am3xxx.c b/arch/arm/mach-omap/am3xxx.c
index 75965a8e0e..faf230a027 100644
--- a/arch/arm/mach-omap/am3xxx.c
+++ b/arch/arm/mach-omap/am3xxx.c
@@ -1,6 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <io.h>
-#include <mach/am3xxx-silicon.h>
+#include <mach/omap/am3xxx-silicon.h>
 
 /* UART Defines */
 #define UART_SYSCFG_OFFSET	0x54
@@ -29,4 +31,4 @@ void am3xxx_uart_soft_reset(void __iomem *uart_base)
 }
 
 void am33xx_uart_soft_reset(void __iomem *uart_base)
-	__alias(am3xxx_uart_soft_reset);
\ No newline at end of file
+	__alias(am3xxx_uart_soft_reset);
diff --git a/arch/arm/mach-omap/boot_order.c b/arch/arm/mach-omap/boot_order.c
index 4b74fdba66..4fed99743f 100644
--- a/arch/arm/mach-omap/boot_order.c
+++ b/arch/arm/mach-omap/boot_order.c
@@ -15,7 +15,7 @@
 #include <common.h>
 #include <command.h>
 #include <complete.h>
-#include <mach/omap4-silicon.h>
+#include <mach/omap/omap4-silicon.h>
 
 struct bootsrc {
 	const char *name;
diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c
index c4ddc951fe..1cfba5af71 100644
--- a/arch/arm/mach-omap/devices-gpmc-nand.c
+++ b/arch/arm/mach-omap/devices-gpmc-nand.c
@@ -24,8 +24,8 @@
 #include <clock.h>
 #include <io.h>
 
-#include <mach/gpmc.h>
-#include <mach/gpmc_nand.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/gpmc_nand.h>
 
 #define GPMC_CONF1_VALx8	0x00000800
 #define GPMC_CONF1_VALx16	0x00001800
diff --git a/arch/arm/mach-omap/emif4.c b/arch/arm/mach-omap/emif4.c
new file mode 100644
index 0000000000..db16d6c760
--- /dev/null
+++ b/arch/arm/mach-omap/emif4.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on mem.c and sdrc.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <io.h>
+#include <mach/omap/emif4.h>
+
+/*
+ * AM35xx configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x7 << 12)
+#define EMIF4_TIM1_T_RC		(0xa << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1c << 16)
+#define EMIF4_TIM2_T_XSRD	(0xc8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x15 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0xf)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x257)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x3 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+/**
+ * emif4_sdram_size - read back SDRAM size from sdram_config register
+ *
+ * @return: The SDRAM size
+ */
+unsigned long emif4_sdram_size(const void __iomem *emif4)
+{
+	uint32_t sdram_config = readl(emif4 + EMIF4_SDRAM_CONFIG);
+	int rows, cols, width, banks;
+	unsigned long size;
+
+	rows = ((sdram_config >> 7) & 0x7) + 9;
+	cols = (sdram_config & 0x7) + 8;
+
+	switch ((sdram_config >> 14) & 0x3) {
+	case 0:
+		width = 4;
+		break;
+	case 1:
+		width = 2;
+		break;
+	default:
+		return 0;
+	}
+
+	switch ((sdram_config >> 4) & 0x7) {
+	case 0:
+		banks = 1;
+		break;
+	case 1:
+		banks = 2;
+		break;
+	case 2:
+		banks = 4;
+		break;
+	case 3:
+		banks = 8;
+		break;
+	default:
+		return 0;
+	}
+
+	size = (1 << rows) * (1 << cols) * banks * width;
+
+	debug("SDRAM_CONFIG: 0x%08x, cols: %2d, rows: %2d, width: %2d, banks: %2d, size: 0x%08lx\n",
+	      sdram_config, cols, rows, width, banks, size);
+
+	return size;
+}
+
+/*
+ *  - Init the emif4 module for DDR access
+ *  - Early init routines, called from flash or SRAM.
+ */
+void am35xx_emif4_init(const void __iomem *emif4)
+{
+	unsigned int regval;
+
+	/* Set the DDR PHY parameters in PHY ctrl registers */
+	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
+		EMIF4_DDR1_EXT_STRB_DIS);
+	writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1);
+	writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW);
+	writel(0, emif4 + EMIF4_DDR_PHY_CTRL_2);
+
+	/* Reset the DDR PHY and wait till completed */
+	regval = readl(emif4 + EMIF4_IODFT_TLGC);
+	regval |= (1 << 10);
+	writel(regval, emif4 + EMIF4_IODFT_TLGC);
+
+	/* Wait till that bit clears*/
+	while (readl(emif4 + EMIF4_IODFT_TLGC) & (1 << 10));
+
+	/* Re-verify the DDR PHY status*/
+	while ((readl(emif4 + EMIF4_STATUS) & (1 << 2)) == 0x0);
+
+	regval |= (1 << 0);
+	writel(regval, emif4 + EMIF4_IODFT_TLGC);
+
+	/* Set SDR timing registers */
+	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
+		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
+		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
+		EMIF4_TIM1_T_RP);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_1);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_1_SHADOW);
+
+	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
+		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
+		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_2);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_2_SHADOW);
+
+	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_3);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_3_SHADOW);
+
+	/* Set the PWR control register */
+	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
+		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
+	writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL);
+	writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL_SHADOW);
+
+	/* Set the DDR refresh rate control register */
+	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
+	writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL);
+	writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
+
+	/* set the SDRAM configuration register */
+	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
+		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
+		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
+		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
+		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
+		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
+	writel(regval, emif4 + EMIF4_SDRAM_CONFIG);
+}
diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c
index 07eeae1ace..1cee845012 100644
--- a/arch/arm/mach-omap/gpmc.c
+++ b/arch/arm/mach-omap/gpmc.c
@@ -24,13 +24,13 @@
 #include <init.h>
 #include <io.h>
 #include <errno.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap4-silicon.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/gpmc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/generic.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/generic.h>
 
 /**
  * @brief Do a Generic initialization of GPMC. if you choose otherwise,
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h
deleted file mode 100644
index e71ecbcd24..0000000000
--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef _AM33XX_CLOCKS_H_
-#define _AM33XX_CLOCKS_H_
-
-#include "am33xx-silicon.h"
-
-/* Put the pll config values over here */
-
-/* MAIN PLL Fdll = 1 GHZ, */
-#define MPUPLL_M_500	500	/* 125 * n */
-#define MPUPLL_M_550	550	/* 125 * n */
-#define MPUPLL_M_600	600	/* 125 * n */
-#define MPUPLL_M_720	720	/* 125 * n */
-
-#define MPUPLL_M2	1
-
-/* Core PLL Fdll = 1 GHZ, */
-#define COREPLL_M	1000	/* 125 * n */
-
-#define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
-#define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
-#define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
-
-/*
- * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
- * frequency needs to be set to 960 MHZ. Hence,
- * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
- */
-#define PERPLL_M	960
-#define PERPLL_M2	5
-
-/* DDR Freq is 266 MHZ for now*/
-/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
-#define DDRPLL_M_200	200
-#define DDRPLL_M_266	266
-#define DDRPLL_M_303	303
-#define DDRPLL_M_400	400
-#define DDRPLL_N	(OSC - 1)
-#define DDRPLL_M2	1
-
-/* PRCM */
-/* Module Offsets */
-#define CM_PER                          (AM33XX_PRM_BASE + 0x0)
-#define CM_WKUP                         (AM33XX_PRM_BASE + 0x400)
-#define CM_DPLL                         (AM33XX_PRM_BASE + 0x500)
-#define CM_DEVICE                       (AM33XX_PRM_BASE + 0x0700)
-#define CM_CEFUSE                       (AM33XX_PRM_BASE + 0x0A00)
-#define PRM_DEVICE                      (AM33XX_PRM_BASE + 0x0F00)
-/* Register Offsets */
-/* Core PLL ADPLLS */
-#define CM_CLKSEL_DPLL_CORE             (CM_WKUP + 0x68)
-#define CM_CLKMODE_DPLL_CORE            (CM_WKUP + 0x90)
-
-/* Core HSDIV */
-#define CM_DIV_M4_DPLL_CORE             (CM_WKUP + 0x80)
-#define CM_DIV_M5_DPLL_CORE             (CM_WKUP + 0x84)
-#define CM_DIV_M6_DPLL_CORE             (CM_WKUP + 0xD8)
-#define CM_IDLEST_DPLL_CORE             (CM_WKUP + 0x5c)
-
-/* Peripheral PLL */
-#define CM_CLKSEL_DPLL_PER              (CM_WKUP + 0x9c)
-#define CM_CLKMODE_DPLL_PER             (CM_WKUP + 0x8c)
-#define CM_DIV_M2_DPLL_PER              (CM_WKUP + 0xAC)
-#define CM_IDLEST_DPLL_PER              (CM_WKUP + 0x70)
-#define CM_CLKDCOLDO_DPLL_PER           (CM_WKUP + 0x7C) /* for USB_PHY clock */
-
-/* Display PLL */
-#define CM_CLKSEL_DPLL_DISP             (CM_WKUP + 0x54)
-#define CM_CLKMODE_DPLL_DISP            (CM_WKUP + 0x98)
-#define CM_DIV_M2_DPLL_DISP             (CM_WKUP + 0xA4)
-
-/* DDR PLL */
-#define CM_CLKSEL_DPLL_DDR              (CM_WKUP + 0x40)
-#define CM_CLKMODE_DPLL_DDR             (CM_WKUP + 0x94)
-#define CM_DIV_M2_DPLL_DDR              (CM_WKUP + 0xA0)
-#define CM_IDLEST_DPLL_DDR              (CM_WKUP + 0x34)
-
-/* MPU PLL */
-#define CM_CLKSEL_DPLL_MPU              (CM_WKUP + 0x2c)
-#define CM_CLKMODE_DPLL_MPU             (CM_WKUP + 0x88)
-#define CM_DIV_M2_DPLL_MPU              (CM_WKUP + 0xA8)
-#define CM_IDLEST_DPLL_MPU              (CM_WKUP + 0x20)
-
-/* TIMER Clock Source Select */
-#define CLKSEL_TIMER2_CLK               (CM_DPLL + 0x8)
-
-/* Interconnect clocks */
-#define CM_PER_L4LS_CLKCTRL             (CM_PER + 0x60) /* EMIF */
-#define CM_PER_L4FW_CLKCTRL             (CM_PER + 0x64) /* EMIF FW */
-#define CM_PER_L3_CLKCTRL               (CM_PER + 0xE0) /* OCMC RAM */
-#define CM_PER_L3_INSTR_CLKCTRL         (CM_PER + 0xDC)
-#define CM_PER_L4HS_CLKCTRL             (CM_PER + 0x120)
-#define CM_WKUP_L4WKUP_CLKCTRL          (CM_WKUP + 0x0c)/* UART0 */
-
-/* Domain Wake UP */
-#define CM_WKUP_CLKSTCTRL               (CM_WKUP + 0)   /* UART0 */
-#define CM_PER_L4LS_CLKSTCTRL           (CM_PER + 0x0)  /* TIMER2 */
-#define CM_PER_L3_CLKSTCTRL             (CM_PER + 0x0c) /* EMIF */
-#define CM_PER_L4FW_CLKSTCTRL           (CM_PER + 0x08) /* EMIF FW */
-#define CM_PER_L3S_CLKSTCTRL            (CM_PER + 0x4)
-#define CM_PER_L4HS_CLKSTCTRL           (CM_PER + 0x011c)
-#define CM_CEFUSE_CLKSTCTRL             (CM_CEFUSE + 0x0)
-
-/* Module Enable Registers */
-#define CM_PER_TIMER2_CLKCTRL           (CM_PER + 0x80) /* Timer2 */
-#define CM_WKUP_UART0_CLKCTRL           (CM_WKUP + 0xB4)/* UART0 */
-#define CM_WKUP_CONTROL_CLKCTRL         (CM_WKUP + 0x4) /* Control Module */
-#define CM_PER_EMIF_CLKCTRL             (CM_PER + 0x28) /* EMIF */
-#define CM_PER_EMIF_FW_CLKCTRL          (CM_PER + 0xD0) /* EMIF FW */
-#define CM_PER_GPMC_CLKCTRL             (CM_PER + 0x30) /* GPMC */
-#define CM_PER_ELM_CLKCTRL              (CM_PER + 0x40) /* ELM */
-#define CM_PER_SPI0_CLKCTRL             (CM_PER + 0x4c) /* SPI0 */
-#define CM_PER_SPI1_CLKCTRL             (CM_PER + 0x50) /* SPI1 */
-#define CM_WKUP_I2C0_CLKCTRL            (CM_WKUP + 0xB8) /* I2C0 */
-#define CM_PER_CPGMAC0_CLKCTRL          (CM_PER + 0x14) /* Ethernet */
-#define CM_PER_CPSW_CLKSTCTRL           (CM_PER + 0x144)/* Ethernet */
-#define CM_PER_OCMCRAM_CLKCTRL          (CM_PER + 0x2C) /* OCMC RAM */
-#define CM_PER_GPIO1_CLKCTRL            (CM_PER + 0xAC) /* GPIO1 */
-#define CM_PER_GPIO2_CLKCTRL            (CM_PER + 0xB0) /* GPIO2 */
-#define CM_PER_GPIO3_CLKCTRL            (CM_PER + 0xB4) /* GPIO3 */
-#define CM_PER_UART1_CLKCTRL            (CM_PER + 0x6C) /* UART1 */
-#define CM_PER_UART2_CLKCTRL            (CM_PER + 0x70) /* UART2 */
-#define CM_PER_UART3_CLKCTRL            (CM_PER + 0x74) /* UART3 */
-#define CM_PER_UART4_CLKCTRL            (CM_PER + 0x78) /* UART4 */
-#define CM_PER_I2C1_CLKCTRL             (CM_PER + 0x48) /* I2C1 */
-#define CM_PER_I2C2_CLKCTRL             (CM_PER + 0x44) /* I2C2 */
-#define CM_WKUP_GPIO0_CLKCTRL           (CM_WKUP + 0x8) /* GPIO0 */
-#define CM_WKUP_ADC_TSC_CLKCTRL         (CM_WKUP + 0xbc)/* TSCADC */
-
-#define CM_PER_MMC0_CLKCTRL             (CM_PER + 0x3C)
-#define CM_PER_MMC1_CLKCTRL             (CM_PER + 0xF4)
-#define CM_PER_MMC2_CLKCTRL             (CM_PER + 0xF8)
-#define CM_PER_USB0_CLKCTRL             (CM_PER + 0x1c) /* USB */
-
-/* PRCM */
-#define CM_DPLL_OFFSET                  (AM33XX_PRM_BASE + 0x0300)
-
-#define CM_ALWON_WDTIMER_CLKCTRL        (AM33XX_PRM_BASE + 0x158C)
-#define CM_ALWON_SPI_CLKCTRL            (AM33XX_PRM_BASE + 0x1590)
-#define CM_ALWON_CONTROL_CLKCTRL        (AM33XX_PRM_BASE + 0x15C4)
-
-#define CM_ALWON_L3_SLOW_CLKSTCTRL      (AM33XX_PRM_BASE + 0x1400)
-
-#define CM_ALWON_GPIO_0_CLKCTRL         (AM33XX_PRM_BASE + 0x155c)
-#define CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK (AM33XX_PRM_BASE + 0x155c)
-
-/* Ethernet */
-#define CM_ETHERNET_CLKSTCTRL           (AM33XX_PRM_BASE + 0x1404)
-#define CM_ALWON_ETHERNET_0_CLKCTRL     (AM33XX_PRM_BASE + 0x15D4)
-#define CM_ALWON_ETHERNET_1_CLKCTRL     (AM33XX_PRM_BASE + 0x15D8)
-
-/* UARTs */
-#define CM_ALWON_UART_0_CLKCTRL         (AM33XX_PRM_BASE + 0x1550)
-#define CM_ALWON_UART_1_CLKCTRL         (AM33XX_PRM_BASE + 0x1554)
-#define CM_ALWON_UART_2_CLKCTRL         (AM33XX_PRM_BASE + 0x1558)
-
-/* I2C */
-/* Note: In ti814x I2C0 and I2C2 have common clk control */
-#define CM_ALWON_I2C_0_CLKCTRL          (AM33XX_PRM_BASE + 0x1564)
-
-/* EMIF4 PRCM Defintion */
-#define CM_DEFAULT_L3_FAST_CLKSTCTRL    (AM33XX_PRM_BASE + 0x0508)
-#define CM_DEFAULT_EMIF_0_CLKCTRL       (AM33XX_PRM_BASE + 0x0520)
-#define CM_DEFAULT_EMIF_1_CLKCTRL       (AM33XX_PRM_BASE + 0x0524)
-#define CM_DEFAULT_DMM_CLKCTRL          (AM33XX_PRM_BASE + 0x0528)
-#define CM_DEFAULT_FW_CLKCTRL           (AM33XX_PRM_BASE + 0x052C)
-
-/* ALWON PRCM */
-#define CM_ALWON_OCMC_0_CLKSTCTRL       CM_PER_L3_CLKSTCTRL
-#define CM_ALWON_OCMC_0_CLKCTRL         CM_PER_OCMCRAM_CLKCTRL
-
-#define CM_ALWON_GPMC_CLKCTRL           CM_PER_GPMC_CLKCTRL
-
-void am33xx_pll_init(int mpupll_M, int ddrpll_M);
-void am33xx_enable_ddr_clocks(void);
-int am33xx_get_osc_clock(void);
-
-#endif  /* endif _AM33XX_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h b/arch/arm/mach-omap/include/mach/am33xx-generic.h
deleted file mode 100644
index 7e64e74d5c..0000000000
--- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __MACH_AM33XX_GENERIC_H
-#define __MACH_AM33XX_GENERIC_H
-
-#include <string.h>
-#include <mach/generic.h>
-#include <mach/am33xx-silicon.h>
-
-int am33xx_register_ethaddr(int eth_id, int mac_id);
-
-u32 am33xx_get_cpu_rev(void);
-
-static inline void am33xx_save_bootinfo(uint32_t *info)
-{
-	unsigned long i = (unsigned long)info;
-	uint32_t *scratch = (void *)AM33XX_SRAM_SCRATCH_SPACE;
-
-	if (i & 0x3)
-		return;
-	if (i < AM33XX_SRAM0_START)
-		return;
-	if (i > AM33XX_SRAM0_START + AM33XX_SRAM0_SIZE)
-		return;
-
-	memcpy(scratch, info, 3 * sizeof(uint32_t));
-}
-
-u32 am33xx_running_in_flash(void);
-u32 am33xx_running_in_sram(void);
-u32 am33xx_running_in_sdram(void);
-
-void am33xx_enable_per_clocks(void);
-int am33xx_init(void);
-int am33xx_devices_init(void);
-void am33xx_select_rmii2_crs_dv(void);
-int am33xx_of_register_bootdevice(void);
-
-#endif /* __MACH_AM33XX_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-mux.h b/arch/arm/mach-omap/include/mach/am33xx-mux.h
deleted file mode 100644
index af9f14dd5b..0000000000
--- a/arch/arm/mach-omap/include/mach/am33xx-mux.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __AM33XX_MUX_H__
-#define __AM33XX_MUX_H__
-
-/* PAD Control Fields */
-#define SLEWCTRL	(0x1 << 6)
-#define	RXACTIVE	(0x1 << 5)
-#define	PULLUP_EN	(0x1 << 4) /* Pull UP Selection */
-#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
-#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
-#define MODE(val)	val
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-/* TODO replace with defines */
-struct pad_signals {
-	int gpmc_ad0;
-	int gpmc_ad1;
-	int gpmc_ad2;
-	int gpmc_ad3;
-	int gpmc_ad4;
-	int gpmc_ad5;
-	int gpmc_ad6;
-	int gpmc_ad7;
-	int gpmc_ad8;
-	int gpmc_ad9;
-	int gpmc_ad10;
-	int gpmc_ad11;
-	int gpmc_ad12;
-	int gpmc_ad13;
-	int gpmc_ad14;
-	int gpmc_ad15;
-	int gpmc_a0;
-	int gpmc_a1;
-	int gpmc_a2;
-	int gpmc_a3;
-	int gpmc_a4;
-	int gpmc_a5;
-	int gpmc_a6;
-	int gpmc_a7;
-	int gpmc_a8;
-	int gpmc_a9;
-	int gpmc_a10;
-	int gpmc_a11;
-	int gpmc_wait0;
-	int gpmc_wpn;
-	int gpmc_be1n;
-	int gpmc_csn0;
-	int gpmc_csn1;
-	int gpmc_csn2;
-	int gpmc_csn3;
-	int gpmc_clk;
-	int gpmc_advn_ale;
-	int gpmc_oen_ren;
-	int gpmc_wen;
-	int gpmc_be0n_cle;
-	int lcd_data0;
-	int lcd_data1;
-	int lcd_data2;
-	int lcd_data3;
-	int lcd_data4;
-	int lcd_data5;
-	int lcd_data6;
-	int lcd_data7;
-	int lcd_data8;
-	int lcd_data9;
-	int lcd_data10;
-	int lcd_data11;
-	int lcd_data12;
-	int lcd_data13;
-	int lcd_data14;
-	int lcd_data15;
-	int lcd_vsync;
-	int lcd_hsync;
-	int lcd_pclk;
-	int lcd_ac_bias_en;
-	int mmc0_dat3;
-	int mmc0_dat2;
-	int mmc0_dat1;
-	int mmc0_dat0;
-	int mmc0_clk;
-	int mmc0_cmd;
-	int mii1_col;
-	int mii1_crs;
-	int mii1_rxerr;
-	int mii1_txen;
-	int mii1_rxdv;
-	int mii1_txd3;
-	int mii1_txd2;
-	int mii1_txd1;
-	int mii1_txd0;
-	int mii1_txclk;
-	int mii1_rxclk;
-	int mii1_rxd3;
-	int mii1_rxd2;
-	int mii1_rxd1;
-	int mii1_rxd0;
-	int rmii1_refclk;
-	int mdio_data;
-	int mdio_clk;
-	int spi0_sclk;
-	int spi0_d0;
-	int spi0_d1;
-	int spi0_cs0;
-	int spi0_cs1;
-	int ecap0_in_pwm0_out;
-	int uart0_ctsn;
-	int uart0_rtsn;
-	int uart0_rxd;
-	int uart0_txd;
-	int uart1_ctsn;
-	int uart1_rtsn;
-	int uart1_rxd;
-	int uart1_txd;
-	int i2c0_sda;
-	int i2c0_scl;
-	int mcasp0_aclkx;
-	int mcasp0_fsx;
-	int mcasp0_axr0;
-	int mcasp0_ahclkr;
-	int mcasp0_aclkr;
-	int mcasp0_fsr;
-	int mcasp0_axr1;
-	int mcasp0_ahclkx;
-	int xdma_event_intr0;
-	int xdma_event_intr1;
-	int nresetin_out;
-	int porz;
-	int nnmi;
-	int osc0_in;
-	int osc0_out;
-	int rsvd1;
-	int tms;
-	int tdi;
-	int tdo;
-	int tck;
-	int ntrst;
-	int emu0;
-	int emu1;
-	int osc1_in;
-	int osc1_out;
-	int pmic_power_en;
-	int rtc_porz;
-	int rsvd2;
-	int ext_wakeup;
-	int enz_kaldo_1p8v;
-	int usb0_dm;
-	int usb0_dp;
-	int usb0_ce;
-	int usb0_id;
-	int usb0_vbus;
-	int usb0_drvvbus;
-	int usb1_dm;
-	int usb1_dp;
-	int usb1_ce;
-	int usb1_id;
-	int usb1_vbus;
-	int usb1_drvvbus;
-	int ddr_resetn;
-	int ddr_csn0;
-	int ddr_cke;
-	int ddr_ck;
-	int ddr_nck;
-	int ddr_casn;
-	int ddr_rasn;
-	int ddr_wen;
-	int ddr_ba0;
-	int ddr_ba1;
-	int ddr_ba2;
-	int ddr_a0;
-	int ddr_a1;
-	int ddr_a2;
-	int ddr_a3;
-	int ddr_a4;
-	int ddr_a5;
-	int ddr_a6;
-	int ddr_a7;
-	int ddr_a8;
-	int ddr_a9;
-	int ddr_a10;
-	int ddr_a11;
-	int ddr_a12;
-	int ddr_a13;
-	int ddr_a14;
-	int ddr_a15;
-	int ddr_odt;
-	int ddr_d0;
-	int ddr_d1;
-	int ddr_d2;
-	int ddr_d3;
-	int ddr_d4;
-	int ddr_d5;
-	int ddr_d6;
-	int ddr_d7;
-	int ddr_d8;
-	int ddr_d9;
-	int ddr_d10;
-	int ddr_d11;
-	int ddr_d12;
-	int ddr_d13;
-	int ddr_d14;
-	int ddr_d15;
-	int ddr_dqm0;
-	int ddr_dqm1;
-	int ddr_dqs0;
-	int ddr_dqsn0;
-	int ddr_dqs1;
-	int ddr_dqsn1;
-	int ddr_vref;
-	int ddr_vtp;
-	int ddr_strben0;
-	int ddr_strben1;
-	int ain7;
-	int ain6;
-	int ain5;
-	int ain4;
-	int ain3;
-	int ain2;
-	int ain1;
-	int ain0;
-	int vrefp;
-	int vrefn;
-};
-
-struct module_pin_mux {
-	short reg_offset;
-	unsigned char val;
-};
-
-#define PAD_CTRL_BASE	0x800
-#define OFFSET(x)	(unsigned int) (&((struct pad_signals *) \
-				(PAD_CTRL_BASE))->x)
-
-extern void configure_module_pin_mux(const struct module_pin_mux *mod_pin_mux);
-
-/* Standard mux settings */
-extern void am33xx_enable_mii1_pin_mux(void);
-extern void am33xx_enable_rmii1_pin_mux(void);
-extern void am33xx_enable_rmii2_pin_mux(void);
-extern void am33xx_enable_i2c0_pin_mux(void);
-extern void am33xx_enable_i2c1_pin_mux(void);
-extern void am33xx_enable_i2c2_pin_mux(void);
-extern void am33xx_enable_uart0_pin_mux(void);
-extern void am33xx_enable_uart1_pin_mux(void);
-extern void am33xx_enable_uart2_pin_mux(void);
-extern void am33xx_enable_mmc0_pin_mux(void);
-extern void am33xx_enable_spi0_pin_mux(void);
-extern void am33xx_enable_nand_pin_mux(void);
-
-#endif /*__AM33XX_MUX_H__ */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
deleted file mode 100644
index 0729369255..0000000000
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * This file contains the address info for various AM33XX modules.
- *
- * Copyright (C) 2012 Teresa Gámez <t.gamez@phytec.de>,
- *		 Phytec Messtechnik GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_AM33XX_H
-#define __ASM_ARCH_AM33XX_H
-
-#include <linux/sizes.h>
-
-/** AM335x Internal Bus Base addresses */
-#define AM33XX_L4_WKUP_BASE		0x44C00000
-#define AM33XX_L4_PER_BASE		0x48000000
-#define AM33XX_L4_FAST_BASE		0x4A000000
-
-/* the device numbering is the same as in the TRM memory map (SPRUH73G) */
-
-/* UART */
-#define AM33XX_UART0_BASE		(AM33XX_L4_WKUP_BASE + 0x209000)
-#define AM33XX_UART1_BASE		(AM33XX_L4_PER_BASE + 0x22000)
-#define AM33XX_UART2_BASE		(AM33XX_L4_PER_BASE + 0x24000)
-
-/* GPIO */
-#define AM33XX_GPIO0_BASE		(AM33XX_L4_WKUP_BASE + 0x207000 + 0x100)
-#define AM33XX_GPIO1_BASE		(AM33XX_L4_PER_BASE + 0x4C000 + 0x100)
-#define AM33XX_GPIO2_BASE		(AM33XX_L4_PER_BASE + 0x1AC000 + 0x100)
-#define AM33XX_GPIO3_BASE		(AM33XX_L4_PER_BASE + 0x1AE000 + 0x100)
-
-/* EMFI Registers */
-#define AM33XX_EMFI0_BASE		0x4C000000
-
-#define AM33XX_DRAM_ADDR_SPACE_START	0x80000000
-#define AM33XX_DRAM_ADDR_SPACE_END	0xC0000000
-
-/* I2C */
-#define AM33XX_I2C0_BASE	(AM33XX_L4_WKUP_BASE + 0x20B000)
-#define AM33XX_I2C1_BASE	(AM33XX_L4_PER_BASE + 0x02A000)
-#define AM33XX_I2C2_BASE	(AM33XX_L4_PER_BASE + 0x19C000)
-
-/* GPMC */
-#define AM33XX_GPMC_BASE		0x50000000
-
-/* MMC */
-#define AM33XX_MMCHS0_BASE		(AM33XX_L4_PER_BASE + 0x60000)
-#define AM33XX_MMC1_BASE		(AM33XX_L4_PER_BASE + 0x1D8000)
-#define AM33XX_MMCHS2_BASE		0x47810000
-
-/* SPI */
-#define AM33XX_MCSPI0_BASE		(AM33XX_L4_PER_BASE + 0x30000)
-#define AM33XX_MCSPI1_BASE		(AM33XX_L4_PER_BASE + 0x1A0000)
-
-/* DTMTimer0 */
-#define AM33XX_DMTIMER0_BASE		(AM33XX_L4_WKUP_BASE + 0x205000)
-/* DMTIimer2 */
-#define AM33XX_DMTIMER2_BASE		(AM33XX_L4_PER_BASE + 0x40000)
-#define AM33XX_CM_DPLL			(AM33XX_L4_WKUP_BASE + 0x200500)
-
-/* PRM */
-#define AM33XX_PRM_BASE			(AM33XX_L4_WKUP_BASE + 0x200000)
-
-#define AM33XX_PRM_RSTCTRL		(AM33XX_PRM_BASE + 0x0f00)
-#define AM33XX_PRM_RSTCTRL_RESET	0x1
-#define AM33XX_PRM_RSTTIME		(AM33XX_PRM_BASE + 0x0f04)
-#define AM33XX_PRM_RSTST		(AM33XX_PRM_BASE + 0x0f08)
-
-/* CTRL */
-#define AM33XX_CTRL_BASE		(AM33XX_L4_WKUP_BASE + 0x210000)
-#define AM33XX_IDCODE_REG		(AM33XX_CTRL_BASE + 0x600)
-#define AM33XX_CTRL_STATUS		(AM33XX_CTRL_BASE + 0x40)
-
-/* Watchdog Timer */
-#define AM33XX_WDT_BASE			0x44E35000
-
-/* EMIF Base address */
-#define AM33XX_EMIF4_0_CFG_BASE		0x4C000000
-#define AM33XX_EMIF4_1_CFG_BASE		0x4D000000
-#define AM33XX_DMM_BASE			0x4E000000
-
-#define AM335X_CPSW_BASE		0x4A100000
-#define AM335X_CPSW_MDIO_BASE		0x4A101000
-
-/*DMM & EMIF4 MMR Declaration*/
-#define AM33XX_DMM_LISA_MAP__0		(AM33XX_DMM_BASE + 0x40)
-#define AM33XX_DMM_LISA_MAP__1		(AM33XX_DMM_BASE + 0x44)
-#define AM33XX_DMM_LISA_MAP__2		(AM33XX_DMM_BASE + 0x48)
-#define AM33XX_DMM_LISA_MAP__3		(AM33XX_DMM_BASE + 0x4C)
-#define AM33XX_DMM_PAT_BASE_ADDR	(AM33XX_DMM_BASE + 0x460)
-
-#define AM33XX_EMIF4_0_REG(REGNAME)	(AM33XX_EMIF4_0_CFG_BASE + EMIF4_##REGNAME)
-#define AM33XX_EMIF4_1_REG(REGNAME)	(AM33XX_EMIF4_1_CFG_BASE + EMIF4_##REGNAME)
-
-#define EMIF4_MOD_ID_REV		0x0
-#define EMIF4_SDRAM_STATUS		0x04
-#define EMIF4_SDRAM_CONFIG		0x08
-#define EMIF4_SDRAM_CONFIG2		0x0C
-#define EMIF4_SDRAM_REF_CTRL		0x10
-#define EMIF4_SDRAM_REF_CTRL_SHADOW	0x14
-#define EMIF4_SDRAM_TIM_1		0x18
-#define EMIF4_SDRAM_TIM_1_SHADOW	0x1C
-#define EMIF4_SDRAM_TIM_2		0x20
-#define EMIF4_SDRAM_TIM_2_SHADOW	0x24
-#define EMIF4_SDRAM_TIM_3		0x28
-#define EMIF4_SDRAM_TIM_3_SHADOW	0x2C
-#define EMIF0_SDRAM_MGMT_CTRL		0x38
-#define EMIF0_SDRAM_MGMT_CTRL_SHD	0x3C
-#define EMIF4_OCP_CONFIG		0x54
-#define EMIF4_ZQ_CONFIG			0xC8
-#define EMIF4_DDR_PHY_CTRL_1		0xE4
-#define EMIF4_DDR_PHY_CTRL_1_SHADOW	0xE8
-#define EMIF4_DDR_PHY_CTRL_2		0xEC
-#define EMIF4_IODFT_TLGC		0x60
-
-#define AM33XX_VTP0_CTRL_REG		0x44E10E0C
-#define AM33XX_VTP1_CTRL_REG		0x48140E10
-
-/* OCMC */
-#define AM33XX_SRAM0_START			0x402f0400
-#define AM33XX_SRAM0_SIZE			(SZ_128K - SZ_1K)
-#define AM33XX_SRAM_SCRATCH_SPACE		0x4030b800 /* start of public stack */
-#define AM33XX_SRAM_GPMC_STACK_SIZE		(0x40)
-
-/* DDR offsets */
-#define	AM33XX_DDR_PHY_BASE_ADDR		0x44E12000
-#define	AM33XX_CONTROL_BASE_ADDR		0x44E10000
-
-#define	AM33XX_DDR_IO_CTRL			(AM33XX_CONTROL_BASE_ADDR + 0x0E04)
-#define	AM33XX_DDR_CKE_CTRL			(AM33XX_CONTROL_BASE_ADDR + 0x131C)
-#define	AM33XX_DDR_CMD0_IOCTRL			(AM33XX_CONTROL_BASE_ADDR + 0x1404)
-#define	AM33XX_DDR_CMD1_IOCTRL			(AM33XX_CONTROL_BASE_ADDR + 0x1408)
-#define	AM33XX_DDR_CMD2_IOCTRL			(AM33XX_CONTROL_BASE_ADDR + 0x140C)
-#define	AM33XX_DDR_DATA0_IOCTRL			(AM33XX_CONTROL_BASE_ADDR + 0x1440)
-#define	AM33XX_DDR_DATA1_IOCTRL			(AM33XX_CONTROL_BASE_ADDR + 0x1444)
-
-#define	AM33XX_CMD0_CTRL_SLAVE_RATIO_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x01C)
-#define	AM33XX_CMD0_CTRL_SLAVE_FORCE_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x020)
-#define	AM33XX_CMD0_CTRL_SLAVE_DELAY_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x024)
-#define	AM33XX_CMD0_DLL_LOCK_DIFF_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x028)
-#define	AM33XX_CMD0_INVERT_CLKOUT_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x02C)
-
-#define	AM33XX_CMD1_CTRL_SLAVE_RATIO_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x050)
-#define	AM33XX_CMD1_CTRL_SLAVE_FORCE_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x054)
-#define	AM33XX_CMD1_CTRL_SLAVE_DELAY_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x058)
-#define	AM33XX_CMD1_DLL_LOCK_DIFF_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x05C)
-#define	AM33XX_CMD1_INVERT_CLKOUT_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x060)
-
-#define	AM33XX_CMD2_CTRL_SLAVE_RATIO_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x084)
-#define	AM33XX_CMD2_CTRL_SLAVE_FORCE_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x088)
-#define	AM33XX_CMD2_CTRL_SLAVE_DELAY_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x08C)
-#define	AM33XX_CMD2_DLL_LOCK_DIFF_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x090)
-#define	AM33XX_CMD2_INVERT_CLKOUT_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x094)
-
-#define AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x0C8)
-#define AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1	(AM33XX_DDR_PHY_BASE_ADDR + 0x0CC)
-#define	AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x0DC)
-
-#define	AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1	(AM33XX_DDR_PHY_BASE_ADDR + 0x0E0)
-#define	AM33XX_DATA0_WRLVL_INIT_RATIO_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x0F0)
-
-#define	AM33XX_DATA0_WRLVL_INIT_RATIO_1		(AM33XX_DDR_PHY_BASE_ADDR + 0x0F4)
-#define	AM33XX_DATA0_WRLVL_INIT_MODE_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x0F8)
-#define	AM33XX_DATA0_GATELVL_INIT_RATIO_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x0FC)
-
-#define	AM33XX_DATA0_GATELVL_INIT_RATIO_1	(AM33XX_DDR_PHY_BASE_ADDR + 0x100)
-#define	AM33XX_DATA0_GATELVL_INIT_MODE_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x104)
-#define	AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x108)
-
-#define	AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1	(AM33XX_DDR_PHY_BASE_ADDR + 0x10C)
-#define	AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x120)
-
-#define	AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1	(AM33XX_DDR_PHY_BASE_ADDR + 0x124)
-#define AM33XX_DATA0_DLL_LOCK_DIFF_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x138)
-
-#define AM33XX_DATA0_RANK0_DELAYS_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x134)
-
-#define	AM33XX_DATA1_RD_DQS_SLAVE_RATIO_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x16C)
-#define	AM33XX_DATA1_WR_DQS_SLAVE_RATIO_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x180)
-
-#define	AM33XX_DATA1_WRLVL_INIT_MODE_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x19C)
-#define	AM33XX_DATA1_GATELVL_INIT_MODE_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x1A8)
-
-#define	AM33XX_DATA1_FIFO_WE_SLAVE_RATIO_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x1AC)
-#define	AM33XX_DATA1_WR_DATA_SLAVE_RATIO_0	(AM33XX_DDR_PHY_BASE_ADDR + 0x1C4)
-
-#define	AM33XX_DATA1_RANK0_DELAYS_0		(AM33XX_DDR_PHY_BASE_ADDR + 0x1D8)
-
-/* Ethernet MAC ID from EFuse */
-#define AM33XX_MAC_ID0_LO	(AM33XX_CTRL_BASE + 0x630)
-#define AM33XX_MAC_ID0_HI	(AM33XX_CTRL_BASE + 0x634)
-#define AM33XX_MAC_ID1_LO	(AM33XX_CTRL_BASE + 0x638)
-#define AM33XX_MAC_ID1_HI	(AM33XX_CTRL_BASE + 0x63c)
-#define AM33XX_MAC_MII_SEL	(AM33XX_CTRL_BASE + 0x650)
-
-struct am33xx_cmd_control {
-	u32 slave_ratio0;
-	u32 dll_lock_diff0;
-	u32 invert_clkout0;
-	u32 slave_ratio1;
-	u32 dll_lock_diff1;
-	u32 invert_clkout1;
-	u32 slave_ratio2;
-	u32 dll_lock_diff2;
-	u32 invert_clkout2;
-};
-
-struct am33xx_emif_regs {
-	u32 emif_read_latency;
-	u32 emif_tim1;
-	u32 emif_tim2;
-	u32 emif_tim3;
-	u32 ocp_config;
-	u32 sdram_config;
-	u32 sdram_config2;
-	u32 zq_config;
-	u32 sdram_ref_ctrl;
-};
-
-struct am33xx_ddr_data {
-	u32 rd_slave_ratio0;
-	u32 wr_dqs_slave_ratio0;
-	u32 wrlvl_init_ratio0;
-	u32 gatelvl_init_ratio0;
-	u32 fifo_we_slave_ratio0;
-	u32 wr_slave_ratio0;
-	u32 use_rank0_delay;
-	u32 dll_lock_diff0;
-};
-
-void am33xx_uart_soft_reset(void __iomem *uart_base);
-void am33xx_config_vtp(void);
-void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl);
-void am33xx_config_io_ctrl(int ioctrl);
-void am33xx_config_sdram(const struct am33xx_emif_regs *regs);
-void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr);
-void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
-			const struct am33xx_emif_regs *emif_regs,
-			const struct am33xx_ddr_data *ddr_data);
-unsigned long am335x_sdram_size(void);
-void am335x_barebox_entry(void *boarddata);
-
-#endif
diff --git a/arch/arm/mach-omap/include/mach/am3xxx-silicon.h b/arch/arm/mach-omap/include/mach/am3xxx-silicon.h
deleted file mode 100644
index c5f73ad457..0000000000
--- a/arch/arm/mach-omap/include/mach/am3xxx-silicon.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARCH_AM33XX_H
-#define __ASM_ARCH_AM33XX_H
-
-void am3xxx_uart_soft_reset(void __iomem *uart_base);
-
-#endif /* __ASM_ARCH_AM33XX_H */
\ No newline at end of file
diff --git a/arch/arm/mach-omap/include/mach/bbu.h b/arch/arm/mach-omap/include/mach/bbu.h
deleted file mode 100644
index 94d3f96bb4..0000000000
--- a/arch/arm/mach-omap/include/mach/bbu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef __MACH_BBU_H
-#define __MACH_BBU_H
-
-#include <bbu.h>
-
-#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO
-int am33xx_bbu_spi_nor_mlo_register_handler(const char *name, char *devicefile);
-#else
-static inline int am33xx_bbu_spi_nor_mlo_register_handler(const char *name, char *devicefile)
-{
-	return 0;
-}
-#endif
-
-static inline int am33xx_bbu_spi_nor_register_handler(const char *name, char *devicefile)
-{
-	return bbu_register_std_file_update(name, 0, devicefile, filetype_arm_barebox);
-}
-
-#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_NAND
-int am33xx_bbu_nand_xloadslots_register_handler(const char *name,
-						char **devicefile,
-						int num_devicefiles);
-int am33xx_bbu_nand_slots_register_handler(const char *name, char **devicefile,
-						int num_devicefiles);
-int am33xx_bbu_nand_register_handler(const char *device);
-#else
-static inline int am33xx_bbu_nand_xloadslots_register_handler(const char *name,
-							char **devicefile,
-							int num_devicefiles)
-{
-	return 0;
-}
-
-static inline int am33xx_bbu_nand_slots_register_handler(const char *name,
-							 char **devicefile,
-							int num_devicefiles)
-{
-	return 0;
-}
-
-static inline int am33xx_bbu_nand_register_handler(const char *device)
-{
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_EMMC
-int am33xx_bbu_emmc_mlo_register_handler(const char *name, char *devicefile);
-int am33xx_bbu_emmc_register_handler(const char *name, char *devicefile);
-#else
-static inline int am33xx_bbu_emmc_mlo_register_handler(const char *name,
-							char *devicefile)
-{
-	return 0;
-}
-
-static inline int am33xx_bbu_emmc_register_handler(const char *name,
-							char *devicefile)
-{
-	return 0;
-}
-#endif
-
-
-#endif
diff --git a/arch/arm/mach-omap/include/mach/clocks.h b/arch/arm/mach-omap/include/mach/clocks.h
deleted file mode 100644
index e44d98b914..0000000000
--- a/arch/arm/mach-omap/include/mach/clocks.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/**
- * @file
- * @brief Generic Clock wrapper header.
- *
- * This includes each of the architecture Clock definitions under it.
- *
- * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
- *
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __OMAP_CLOCKS_H_
-#define __OMAP_CLOCKS_H_
-
-#define LDELAY		12000000
-
-/* Standard defines for Various clocks */
-#define S12M		12000000
-#define S13M		13000000
-#define S19_2M		19200000
-#define S24M		24000000
-#define S26M		26000000
-#define S38_4M		38400000
-
-#endif /* __OMAP_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/include/mach/cm-regbits-34xx.h b/arch/arm/mach-omap/include/mach/cm-regbits-34xx.h
deleted file mode 100644
index 16a0201328..0000000000
--- a/arch/arm/mach-omap/include/mach/cm-regbits-34xx.h
+++ /dev/null
@@ -1,799 +0,0 @@
-#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
-#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
-
-/*
- * OMAP3430 Clock Management register bits
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/* Bits shared between registers */
-
-/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
-#define OMAP3430ES2_EN_MMC3_MASK			(1 << 30)
-#define OMAP3430ES2_EN_MMC3_SHIFT			30
-#define OMAP3430_EN_MSPRO_MASK				(1 << 23)
-#define OMAP3430_EN_MSPRO_SHIFT				23
-#define OMAP3430_EN_HDQ_MASK				(1 << 22)
-#define OMAP3430_EN_HDQ_SHIFT				22
-#define OMAP3430ES1_EN_FSHOSTUSB_MASK			(1 << 5)
-#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT			5
-#define OMAP3430ES1_EN_D2D_MASK				(1 << 3)
-#define OMAP3430ES1_EN_D2D_SHIFT			3
-#define OMAP3430_EN_SSI_MASK				(1 << 0)
-#define OMAP3430_EN_SSI_SHIFT				0
-
-/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
-#define OMAP3430ES2_EN_USBTLL_SHIFT			2
-#define OMAP3430ES2_EN_USBTLL_MASK			(1 << 2)
-
-/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
-#define OMAP3430_EN_WDT2_MASK				(1 << 5)
-#define OMAP3430_EN_WDT2_SHIFT				5
-
-/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
-#define OMAP3430_EN_CAM_MASK				(1 << 0)
-#define OMAP3430_EN_CAM_SHIFT				0
-
-/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
-#define OMAP3430_EN_WDT3_MASK				(1 << 12)
-#define OMAP3430_EN_WDT3_SHIFT				12
-
-/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
-#define OMAP3430_OVERRIDE_ENABLE_MASK			(1 << 19)
-
-
-/* Bits specific to each register */
-
-/* CM_FCLKEN_IVA2 */
-#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK		(1 << 0)
-#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT		0
-
-/* CM_CLKEN_PLL_IVA2 */
-#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT		8
-#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK		(0x3 << 8)
-#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT		4
-#define OMAP3430_IVA2_DPLL_FREQSEL_MASK			(0xf << 4)
-#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT		3
-#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK		(1 << 3)
-#define OMAP3430_EN_IVA2_DPLL_SHIFT			0
-#define OMAP3430_EN_IVA2_DPLL_MASK			(0x7 << 0)
-
-/* CM_IDLEST_IVA2 */
-#define OMAP3430_ST_IVA2_MASK				(1 << 0)
-
-/* CM_IDLEST_PLL_IVA2 */
-#define OMAP3430_ST_IVA2_CLK_SHIFT			0
-#define OMAP3430_ST_IVA2_CLK_MASK			(1 << 0)
-
-/* CM_AUTOIDLE_PLL_IVA2 */
-#define OMAP3430_AUTO_IVA2_DPLL_SHIFT			0
-#define OMAP3430_AUTO_IVA2_DPLL_MASK			(0x7 << 0)
-
-/* CM_CLKSEL1_PLL_IVA2 */
-#define OMAP3430_IVA2_CLK_SRC_SHIFT			19
-#define OMAP3430_IVA2_CLK_SRC_MASK			(0x3 << 19)
-#define OMAP3430_IVA2_DPLL_MULT_SHIFT			8
-#define OMAP3430_IVA2_DPLL_MULT_MASK			(0x7ff << 8)
-#define OMAP3430_IVA2_DPLL_DIV_SHIFT			0
-#define OMAP3430_IVA2_DPLL_DIV_MASK			(0x7f << 0)
-
-/* CM_CLKSEL2_PLL_IVA2 */
-#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT		0
-#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
-
-/* CM_CLKSTCTRL_IVA2 */
-#define OMAP3430_CLKTRCTRL_IVA2_SHIFT			0
-#define OMAP3430_CLKTRCTRL_IVA2_MASK			(0x3 << 0)
-
-/* CM_CLKSTST_IVA2 */
-#define OMAP3430_CLKACTIVITY_IVA2_SHIFT			0
-#define OMAP3430_CLKACTIVITY_IVA2_MASK			(1 << 0)
-
-/* CM_REVISION specific bits */
-
-/* CM_SYSCONFIG specific bits */
-
-/* CM_CLKEN_PLL_MPU */
-#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT		8
-#define OMAP3430_MPU_DPLL_RAMPTIME_MASK			(0x3 << 8)
-#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT			4
-#define OMAP3430_MPU_DPLL_FREQSEL_MASK			(0xf << 4)
-#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT		3
-#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK		(1 << 3)
-#define OMAP3430_EN_MPU_DPLL_SHIFT			0
-#define OMAP3430_EN_MPU_DPLL_MASK			(0x7 << 0)
-
-/* CM_IDLEST_MPU */
-#define OMAP3430_ST_MPU_MASK				(1 << 0)
-
-/* CM_IDLEST_PLL_MPU */
-#define OMAP3430_ST_MPU_CLK_SHIFT			0
-#define OMAP3430_ST_MPU_CLK_MASK			(1 << 0)
-
-/* CM_AUTOIDLE_PLL_MPU */
-#define OMAP3430_AUTO_MPU_DPLL_SHIFT			0
-#define OMAP3430_AUTO_MPU_DPLL_MASK			(0x7 << 0)
-
-/* CM_CLKSEL1_PLL_MPU */
-#define OMAP3430_MPU_CLK_SRC_SHIFT			19
-#define OMAP3430_MPU_CLK_SRC_MASK			(0x3 << 19)
-#define OMAP3430_MPU_DPLL_MULT_SHIFT			8
-#define OMAP3430_MPU_DPLL_MULT_MASK			(0x7ff << 8)
-#define OMAP3430_MPU_DPLL_DIV_SHIFT			0
-#define OMAP3430_MPU_DPLL_DIV_MASK			(0x7f << 0)
-
-/* CM_CLKSEL2_PLL_MPU */
-#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT		0
-#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
-
-/* CM_CLKSTCTRL_MPU */
-#define OMAP3430_CLKTRCTRL_MPU_SHIFT			0
-#define OMAP3430_CLKTRCTRL_MPU_MASK			(0x3 << 0)
-
-/* CM_CLKSTST_MPU */
-#define OMAP3430_CLKACTIVITY_MPU_SHIFT			0
-#define OMAP3430_CLKACTIVITY_MPU_MASK			(1 << 0)
-
-/* CM_FCLKEN1_CORE specific bits */
-#define OMAP3430_EN_MODEM_MASK				(1 << 31)
-#define OMAP3430_EN_MODEM_SHIFT				31
-
-/* CM_ICLKEN1_CORE specific bits */
-#define OMAP3430_EN_ICR_MASK				(1 << 29)
-#define OMAP3430_EN_ICR_SHIFT				29
-#define OMAP3430_EN_AES2_MASK				(1 << 28)
-#define OMAP3430_EN_AES2_SHIFT				28
-#define OMAP3430_EN_SHA12_MASK				(1 << 27)
-#define OMAP3430_EN_SHA12_SHIFT				27
-#define OMAP3430_EN_DES2_MASK				(1 << 26)
-#define OMAP3430_EN_DES2_SHIFT				26
-#define OMAP3430ES1_EN_FAC_MASK				(1 << 8)
-#define OMAP3430ES1_EN_FAC_SHIFT			8
-#define OMAP3430_EN_MAILBOXES_MASK			(1 << 7)
-#define OMAP3430_EN_MAILBOXES_SHIFT			7
-#define OMAP3430_EN_OMAPCTRL_MASK			(1 << 6)
-#define OMAP3430_EN_OMAPCTRL_SHIFT			6
-#define OMAP3430_EN_SAD2D_MASK				(1 << 3)
-#define OMAP3430_EN_SAD2D_SHIFT				3
-#define OMAP3430_EN_SDRC_MASK				(1 << 1)
-#define OMAP3430_EN_SDRC_SHIFT				1
-
-/* AM35XX specific CM_ICLKEN1_CORE bits */
-#define AM35XX_EN_IPSS_MASK				(1 << 4)
-#define AM35XX_EN_IPSS_SHIFT				4
-#define AM35XX_EN_UART4_MASK				(1 << 23)
-#define AM35XX_EN_UART4_SHIFT				23
-
-/* CM_ICLKEN2_CORE */
-#define OMAP3430_EN_PKA_MASK				(1 << 4)
-#define OMAP3430_EN_PKA_SHIFT				4
-#define OMAP3430_EN_AES1_MASK				(1 << 3)
-#define OMAP3430_EN_AES1_SHIFT				3
-#define OMAP3430_EN_RNG_MASK				(1 << 2)
-#define OMAP3430_EN_RNG_SHIFT				2
-#define OMAP3430_EN_SHA11_MASK				(1 << 1)
-#define OMAP3430_EN_SHA11_SHIFT				1
-#define OMAP3430_EN_DES1_MASK				(1 << 0)
-#define OMAP3430_EN_DES1_SHIFT				0
-
-/* CM_ICLKEN3_CORE */
-#define OMAP3430_EN_MAD2D_SHIFT				3
-#define OMAP3430_EN_MAD2D_MASK				(1 << 3)
-
-/* CM_FCLKEN3_CORE specific bits */
-#define OMAP3430ES2_EN_TS_SHIFT				1
-#define OMAP3430ES2_EN_TS_MASK				(1 << 1)
-#define OMAP3430ES2_EN_CPEFUSE_SHIFT			0
-#define OMAP3430ES2_EN_CPEFUSE_MASK			(1 << 0)
-
-/* CM_IDLEST1_CORE specific bits */
-#define OMAP3430ES2_ST_MMC3_SHIFT			30
-#define OMAP3430ES2_ST_MMC3_MASK			(1 << 30)
-#define OMAP3430_ST_ICR_SHIFT				29
-#define OMAP3430_ST_ICR_MASK				(1 << 29)
-#define OMAP3430_ST_AES2_SHIFT				28
-#define OMAP3430_ST_AES2_MASK				(1 << 28)
-#define OMAP3430_ST_SHA12_SHIFT				27
-#define OMAP3430_ST_SHA12_MASK				(1 << 27)
-#define OMAP3430_ST_DES2_SHIFT				26
-#define OMAP3430_ST_DES2_MASK				(1 << 26)
-#define OMAP3430_ST_MSPRO_SHIFT				23
-#define OMAP3430_ST_MSPRO_MASK				(1 << 23)
-#define OMAP3430_ST_HDQ_SHIFT				22
-#define OMAP3430_ST_HDQ_MASK				(1 << 22)
-#define OMAP3430ES1_ST_FAC_SHIFT			8
-#define OMAP3430ES1_ST_FAC_MASK				(1 << 8)
-#define OMAP3430ES2_ST_SSI_IDLE_SHIFT			8
-#define OMAP3430ES2_ST_SSI_IDLE_MASK			(1 << 8)
-#define OMAP3430_ST_MAILBOXES_SHIFT			7
-#define OMAP3430_ST_MAILBOXES_MASK			(1 << 7)
-#define OMAP3430_ST_OMAPCTRL_SHIFT			6
-#define OMAP3430_ST_OMAPCTRL_MASK			(1 << 6)
-#define OMAP3430_ST_SDMA_SHIFT				2
-#define OMAP3430_ST_SDMA_MASK				(1 << 2)
-#define OMAP3430_ST_SDRC_SHIFT				1
-#define OMAP3430_ST_SDRC_MASK				(1 << 1)
-#define OMAP3430_ST_SSI_STDBY_SHIFT			0
-#define OMAP3430_ST_SSI_STDBY_MASK			(1 << 0)
-
-/* AM35xx specific CM_IDLEST1_CORE bits */
-#define AM35XX_ST_IPSS_SHIFT				5
-#define AM35XX_ST_IPSS_MASK 				(1 << 5)
-
-/* CM_IDLEST2_CORE */
-#define OMAP3430_ST_PKA_SHIFT				4
-#define OMAP3430_ST_PKA_MASK				(1 << 4)
-#define OMAP3430_ST_AES1_SHIFT				3
-#define OMAP3430_ST_AES1_MASK				(1 << 3)
-#define OMAP3430_ST_RNG_SHIFT				2
-#define OMAP3430_ST_RNG_MASK				(1 << 2)
-#define OMAP3430_ST_SHA11_SHIFT				1
-#define OMAP3430_ST_SHA11_MASK				(1 << 1)
-#define OMAP3430_ST_DES1_SHIFT				0
-#define OMAP3430_ST_DES1_MASK				(1 << 0)
-
-/* CM_IDLEST3_CORE */
-#define OMAP3430ES2_ST_USBTLL_SHIFT			2
-#define OMAP3430ES2_ST_USBTLL_MASK			(1 << 2)
-#define OMAP3430ES2_ST_CPEFUSE_SHIFT			0
-#define OMAP3430ES2_ST_CPEFUSE_MASK			(1 << 0)
-
-/* CM_AUTOIDLE1_CORE */
-#define OMAP3430_AUTO_MODEM_MASK			(1 << 31)
-#define OMAP3430_AUTO_MODEM_SHIFT			31
-#define OMAP3430ES2_AUTO_MMC3_MASK			(1 << 30)
-#define OMAP3430ES2_AUTO_MMC3_SHIFT			30
-#define OMAP3430ES2_AUTO_ICR_MASK			(1 << 29)
-#define OMAP3430ES2_AUTO_ICR_SHIFT			29
-#define OMAP3430_AUTO_AES2_MASK				(1 << 28)
-#define OMAP3430_AUTO_AES2_SHIFT			28
-#define OMAP3430_AUTO_SHA12_MASK			(1 << 27)
-#define OMAP3430_AUTO_SHA12_SHIFT			27
-#define OMAP3430_AUTO_DES2_MASK				(1 << 26)
-#define OMAP3430_AUTO_DES2_SHIFT			26
-#define OMAP3430_AUTO_MMC2_MASK				(1 << 25)
-#define OMAP3430_AUTO_MMC2_SHIFT			25
-#define OMAP3430_AUTO_MMC1_MASK				(1 << 24)
-#define OMAP3430_AUTO_MMC1_SHIFT			24
-#define OMAP3430_AUTO_MSPRO_MASK			(1 << 23)
-#define OMAP3430_AUTO_MSPRO_SHIFT			23
-#define OMAP3430_AUTO_HDQ_MASK				(1 << 22)
-#define OMAP3430_AUTO_HDQ_SHIFT				22
-#define OMAP3430_AUTO_MCSPI4_MASK			(1 << 21)
-#define OMAP3430_AUTO_MCSPI4_SHIFT			21
-#define OMAP3430_AUTO_MCSPI3_MASK			(1 << 20)
-#define OMAP3430_AUTO_MCSPI3_SHIFT			20
-#define OMAP3430_AUTO_MCSPI2_MASK			(1 << 19)
-#define OMAP3430_AUTO_MCSPI2_SHIFT			19
-#define OMAP3430_AUTO_MCSPI1_MASK			(1 << 18)
-#define OMAP3430_AUTO_MCSPI1_SHIFT			18
-#define OMAP3430_AUTO_I2C3_MASK				(1 << 17)
-#define OMAP3430_AUTO_I2C3_SHIFT			17
-#define OMAP3430_AUTO_I2C2_MASK				(1 << 16)
-#define OMAP3430_AUTO_I2C2_SHIFT			16
-#define OMAP3430_AUTO_I2C1_MASK				(1 << 15)
-#define OMAP3430_AUTO_I2C1_SHIFT			15
-#define OMAP3430_AUTO_UART2_MASK			(1 << 14)
-#define OMAP3430_AUTO_UART2_SHIFT			14
-#define OMAP3430_AUTO_UART1_MASK			(1 << 13)
-#define OMAP3430_AUTO_UART1_SHIFT			13
-#define OMAP3430_AUTO_GPT11_MASK			(1 << 12)
-#define OMAP3430_AUTO_GPT11_SHIFT			12
-#define OMAP3430_AUTO_GPT10_MASK			(1 << 11)
-#define OMAP3430_AUTO_GPT10_SHIFT			11
-#define OMAP3430_AUTO_MCBSP5_MASK			(1 << 10)
-#define OMAP3430_AUTO_MCBSP5_SHIFT			10
-#define OMAP3430_AUTO_MCBSP1_MASK			(1 << 9)
-#define OMAP3430_AUTO_MCBSP1_SHIFT			9
-#define OMAP3430ES1_AUTO_FAC_MASK			(1 << 8)
-#define OMAP3430ES1_AUTO_FAC_SHIFT			8
-#define OMAP3430_AUTO_MAILBOXES_MASK			(1 << 7)
-#define OMAP3430_AUTO_MAILBOXES_SHIFT			7
-#define OMAP3430_AUTO_OMAPCTRL_MASK			(1 << 6)
-#define OMAP3430_AUTO_OMAPCTRL_SHIFT			6
-#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK			(1 << 5)
-#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT		5
-#define OMAP3430_AUTO_HSOTGUSB_MASK			(1 << 4)
-#define OMAP3430_AUTO_HSOTGUSB_SHIFT			4
-#define OMAP3430ES1_AUTO_D2D_MASK			(1 << 3)
-#define OMAP3430ES1_AUTO_D2D_SHIFT			3
-#define OMAP3430_AUTO_SAD2D_MASK			(1 << 3)
-#define OMAP3430_AUTO_SAD2D_SHIFT			3
-#define OMAP3430_AUTO_SSI_MASK				(1 << 0)
-#define OMAP3430_AUTO_SSI_SHIFT				0
-
-/* CM_AUTOIDLE2_CORE */
-#define OMAP3430_AUTO_PKA_MASK				(1 << 4)
-#define OMAP3430_AUTO_PKA_SHIFT				4
-#define OMAP3430_AUTO_AES1_MASK				(1 << 3)
-#define OMAP3430_AUTO_AES1_SHIFT			3
-#define OMAP3430_AUTO_RNG_MASK				(1 << 2)
-#define OMAP3430_AUTO_RNG_SHIFT				2
-#define OMAP3430_AUTO_SHA11_MASK			(1 << 1)
-#define OMAP3430_AUTO_SHA11_SHIFT			1
-#define OMAP3430_AUTO_DES1_MASK				(1 << 0)
-#define OMAP3430_AUTO_DES1_SHIFT			0
-
-/* CM_AUTOIDLE3_CORE */
-#define	OMAP3430ES2_AUTO_USBHOST			(1 << 0)
-#define	OMAP3430ES2_AUTO_USBHOST_SHIFT			0
-#define	OMAP3430ES2_AUTO_USBTLL				(1 << 2)
-#define OMAP3430ES2_AUTO_USBTLL_SHIFT			2
-#define OMAP3430ES2_AUTO_USBTLL_MASK			(1 << 2)
-#define OMAP3430_AUTO_MAD2D_SHIFT			3
-#define OMAP3430_AUTO_MAD2D_MASK			(1 << 3)
-
-/* CM_CLKSEL_CORE */
-#define OMAP3430_CLKSEL_SSI_SHIFT			8
-#define OMAP3430_CLKSEL_SSI_MASK			(0xf << 8)
-#define OMAP3430_CLKSEL_GPT11_MASK			(1 << 7)
-#define OMAP3430_CLKSEL_GPT11_SHIFT			7
-#define OMAP3430_CLKSEL_GPT10_MASK			(1 << 6)
-#define OMAP3430_CLKSEL_GPT10_SHIFT			6
-#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT		4
-#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK		(0x3 << 4)
-#define OMAP3430_CLKSEL_L4_SHIFT			2
-#define OMAP3430_CLKSEL_L4_MASK				(0x3 << 2)
-#define OMAP3430_CLKSEL_L3_SHIFT			0
-#define OMAP3430_CLKSEL_L3_MASK				(0x3 << 0)
-#define OMAP3630_CLKSEL_96M_SHIFT			12
-#define OMAP3630_CLKSEL_96M_MASK			(0x3 << 12)
-
-/* CM_CLKSTCTRL_CORE */
-#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT			4
-#define OMAP3430ES1_CLKTRCTRL_D2D_MASK			(0x3 << 4)
-#define OMAP3430_CLKTRCTRL_L4_SHIFT			2
-#define OMAP3430_CLKTRCTRL_L4_MASK			(0x3 << 2)
-#define OMAP3430_CLKTRCTRL_L3_SHIFT			0
-#define OMAP3430_CLKTRCTRL_L3_MASK			(0x3 << 0)
-
-/* CM_CLKSTST_CORE */
-#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT		2
-#define OMAP3430ES1_CLKACTIVITY_D2D_MASK		(1 << 2)
-#define OMAP3430_CLKACTIVITY_L4_SHIFT			1
-#define OMAP3430_CLKACTIVITY_L4_MASK			(1 << 1)
-#define OMAP3430_CLKACTIVITY_L3_SHIFT			0
-#define OMAP3430_CLKACTIVITY_L3_MASK			(1 << 0)
-
-/* CM_FCLKEN_GFX */
-#define OMAP3430ES1_EN_3D_MASK				(1 << 2)
-#define OMAP3430ES1_EN_3D_SHIFT				2
-#define OMAP3430ES1_EN_2D_MASK				(1 << 1)
-#define OMAP3430ES1_EN_2D_SHIFT				1
-
-/* CM_ICLKEN_GFX specific bits */
-
-/* CM_IDLEST_GFX specific bits */
-
-/* CM_CLKSEL_GFX specific bits */
-
-/* CM_SLEEPDEP_GFX specific bits */
-
-/* CM_CLKSTCTRL_GFX */
-#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT			0
-#define OMAP3430ES1_CLKTRCTRL_GFX_MASK			(0x3 << 0)
-
-/* CM_CLKSTST_GFX */
-#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT		0
-#define OMAP3430ES1_CLKACTIVITY_GFX_MASK		(1 << 0)
-
-/* CM_FCLKEN_SGX */
-#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT		1
-#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK		(1 << 1)
-
-/* CM_IDLEST_SGX */
-#define OMAP3430ES2_ST_SGX_SHIFT			1
-#define OMAP3430ES2_ST_SGX_MASK				(1 << 1)
-
-/* CM_ICLKEN_SGX */
-#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT		0
-#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK		(1 << 0)
-
-/* CM_CLKSEL_SGX */
-#define OMAP3430ES2_CLKSEL_SGX_SHIFT			0
-#define OMAP3430ES2_CLKSEL_SGX_MASK			(0x7 << 0)
-
-/* CM_CLKSTCTRL_SGX */
-#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT			0
-#define OMAP3430ES2_CLKTRCTRL_SGX_MASK			(0x3 << 0)
-
-/* CM_CLKSTST_SGX */
-#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT		0
-#define OMAP3430ES2_CLKACTIVITY_SGX_MASK		(1 << 0)
-
-/* CM_FCLKEN_WKUP specific bits */
-#define OMAP3430ES2_EN_USIMOCP_SHIFT			9
-#define OMAP3430ES2_EN_USIMOCP_MASK			(1 << 9)
-
-/* CM_ICLKEN_WKUP specific bits */
-#define OMAP3430_EN_WDT1_MASK				(1 << 4)
-#define OMAP3430_EN_WDT1_SHIFT				4
-#define OMAP3430_EN_32KSYNC_MASK			(1 << 2)
-#define OMAP3430_EN_32KSYNC_SHIFT			2
-
-/* CM_IDLEST_WKUP specific bits */
-#define OMAP3430ES2_ST_USIMOCP_SHIFT			9
-#define OMAP3430ES2_ST_USIMOCP_MASK			(1 << 9)
-#define OMAP3430_ST_WDT2_SHIFT				5
-#define OMAP3430_ST_WDT2_MASK				(1 << 5)
-#define OMAP3430_ST_WDT1_SHIFT				4
-#define OMAP3430_ST_WDT1_MASK				(1 << 4)
-#define OMAP3430_ST_32KSYNC_SHIFT			2
-#define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
-
-/* CM_AUTOIDLE_WKUP */
-#define OMAP3430ES2_AUTO_USIMOCP_MASK			(1 << 9)
-#define OMAP3430ES2_AUTO_USIMOCP_SHIFT			9
-#define OMAP3430_AUTO_WDT2_MASK				(1 << 5)
-#define OMAP3430_AUTO_WDT2_SHIFT			5
-#define OMAP3430_AUTO_WDT1_MASK				(1 << 4)
-#define OMAP3430_AUTO_WDT1_SHIFT			4
-#define OMAP3430_AUTO_GPIO1_MASK			(1 << 3)
-#define OMAP3430_AUTO_GPIO1_SHIFT			3
-#define OMAP3430_AUTO_32KSYNC_MASK			(1 << 2)
-#define OMAP3430_AUTO_32KSYNC_SHIFT			2
-#define OMAP3430_AUTO_GPT12_MASK			(1 << 1)
-#define OMAP3430_AUTO_GPT12_SHIFT			1
-#define OMAP3430_AUTO_GPT1_MASK				(1 << 0)
-#define OMAP3430_AUTO_GPT1_SHIFT			0
-
-/* CM_CLKSEL_WKUP */
-#define OMAP3430ES2_CLKSEL_USIMOCP_MASK			(0xf << 3)
-#define OMAP3430_CLKSEL_RM_SHIFT			1
-#define OMAP3430_CLKSEL_RM_MASK				(0x3 << 1)
-#define OMAP3430_CLKSEL_GPT1_SHIFT			0
-#define OMAP3430_CLKSEL_GPT1_MASK			(1 << 0)
-
-/* CM_CLKEN_PLL */
-#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT			31
-#define OMAP3430_PWRDN_CAM_SHIFT			30
-#define OMAP3430_PWRDN_DSS1_SHIFT			29
-#define OMAP3430_PWRDN_TV_SHIFT				28
-#define OMAP3430_PWRDN_96M_SHIFT			27
-#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT		24
-#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK		(0x3 << 24)
-#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT		20
-#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK		(0xf << 20)
-#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT	19
-#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK		(1 << 19)
-#define OMAP3430_EN_PERIPH_DPLL_SHIFT			16
-#define OMAP3430_EN_PERIPH_DPLL_MASK			(0x7 << 16)
-#define OMAP3430_PWRDN_EMU_CORE_SHIFT			12
-#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT		8
-#define OMAP3430_CORE_DPLL_RAMPTIME_MASK		(0x3 << 8)
-#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT		4
-#define OMAP3430_CORE_DPLL_FREQSEL_MASK			(0xf << 4)
-#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT		3
-#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK		(1 << 3)
-#define OMAP3430_EN_CORE_DPLL_SHIFT			0
-#define OMAP3430_EN_CORE_DPLL_MASK			(0x7 << 0)
-
-/* CM_CLKEN2_PLL */
-#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT	10
-#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK		(0x3 << 8)
-#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT		4
-#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK		(0xf << 4)
-#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT	3
-#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT		0
-#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK		(0x7 << 0)
-
-/* CM_IDLEST_CKGEN */
-#define OMAP3430_ST_54M_CLK_MASK			(1 << 5)
-#define OMAP3430_ST_12M_CLK_MASK			(1 << 4)
-#define OMAP3430_ST_48M_CLK_MASK			(1 << 3)
-#define OMAP3430_ST_96M_CLK_MASK			(1 << 2)
-#define OMAP3430_ST_PERIPH_CLK_SHIFT			1
-#define OMAP3430_ST_PERIPH_CLK_MASK			(1 << 1)
-#define OMAP3430_ST_CORE_CLK_SHIFT			0
-#define OMAP3430_ST_CORE_CLK_MASK			(1 << 0)
-
-/* CM_IDLEST2_CKGEN */
-#define OMAP3430ES2_ST_USIM_CLK_SHIFT			2
-#define OMAP3430ES2_ST_USIM_CLK_MASK			(1 << 2)
-#define OMAP3430ES2_ST_120M_CLK_SHIFT			1
-#define OMAP3430ES2_ST_120M_CLK_MASK			(1 << 1)
-#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT		0
-#define OMAP3430ES2_ST_PERIPH2_CLK_MASK			(1 << 0)
-
-/* CM_AUTOIDLE_PLL */
-#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT			3
-#define OMAP3430_AUTO_PERIPH_DPLL_MASK			(0x7 << 3)
-#define OMAP3430_AUTO_CORE_DPLL_SHIFT			0
-#define OMAP3430_AUTO_CORE_DPLL_MASK			(0x7 << 0)
-
-/* CM_AUTOIDLE2_PLL */
-#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT		0
-#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK		(0x7 << 0)
-
-/* CM_CLKSEL1_PLL */
-/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
-#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT		27
-#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK		(0x1f << 27)
-#define OMAP3430_CORE_DPLL_MULT_SHIFT			16
-#define OMAP3430_CORE_DPLL_MULT_MASK			(0x7ff << 16)
-#define OMAP3430_CORE_DPLL_DIV_SHIFT			8
-#define OMAP3430_CORE_DPLL_DIV_MASK			(0x7f << 8)
-#define OMAP3430_SOURCE_96M_SHIFT			6
-#define OMAP3430_SOURCE_96M_MASK			(1 << 6)
-#define OMAP3430_SOURCE_54M_SHIFT			5
-#define OMAP3430_SOURCE_54M_MASK			(1 << 5)
-#define OMAP3430_SOURCE_48M_SHIFT			3
-#define OMAP3430_SOURCE_48M_MASK			(1 << 3)
-
-/* CM_CLKSEL2_PLL */
-#define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
-#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)
-#define OMAP3630_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
-#define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
-#define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)
-#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
-#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK		(0x7 << 21)
-#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT		24
-#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK		(0xff << 24)
-
-/* CM_CLKSEL3_PLL */
-#define OMAP3430_DIV_96M_SHIFT				0
-#define OMAP3430_DIV_96M_MASK				(0x1f << 0)
-#define OMAP3630_DIV_96M_MASK				(0x3f << 0)
-
-/* CM_CLKSEL4_PLL */
-#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT		8
-#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK		(0x7ff << 8)
-#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT		0
-#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK		(0x7f << 0)
-
-/* CM_CLKSEL5_PLL */
-#define OMAP3430ES2_DIV_120M_SHIFT			0
-#define OMAP3430ES2_DIV_120M_MASK			(0x1f << 0)
-
-/* CM_CLKOUT_CTRL */
-#define OMAP3430_CLKOUT2_EN_SHIFT			7
-#define OMAP3430_CLKOUT2_EN_MASK			(1 << 7)
-#define OMAP3430_CLKOUT2_DIV_SHIFT			3
-#define OMAP3430_CLKOUT2_DIV_MASK			(0x7 << 3)
-#define OMAP3430_CLKOUT2SOURCE_SHIFT			0
-#define OMAP3430_CLKOUT2SOURCE_MASK			(0x3 << 0)
-
-/* CM_FCLKEN_DSS */
-#define OMAP3430_EN_TV_MASK				(1 << 2)
-#define OMAP3430_EN_TV_SHIFT				2
-#define OMAP3430_EN_DSS2_MASK				(1 << 1)
-#define OMAP3430_EN_DSS2_SHIFT				1
-#define OMAP3430_EN_DSS1_MASK				(1 << 0)
-#define OMAP3430_EN_DSS1_SHIFT				0
-
-/* CM_ICLKEN_DSS */
-#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK		(1 << 0)
-#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0
-
-/* CM_IDLEST_DSS */
-#define OMAP3430ES2_ST_DSS_IDLE_SHIFT			1
-#define OMAP3430ES2_ST_DSS_IDLE_MASK			(1 << 1)
-#define OMAP3430ES2_ST_DSS_STDBY_SHIFT			0
-#define OMAP3430ES2_ST_DSS_STDBY_MASK			(1 << 0)
-#define OMAP3430ES1_ST_DSS_SHIFT			0
-#define OMAP3430ES1_ST_DSS_MASK				(1 << 0)
-
-/* CM_AUTOIDLE_DSS */
-#define OMAP3430_AUTO_DSS_MASK				(1 << 0)
-#define OMAP3430_AUTO_DSS_SHIFT				0
-
-/* CM_CLKSEL_DSS */
-#define OMAP3430_CLKSEL_TV_SHIFT			8
-#define OMAP3430_CLKSEL_TV_MASK				(0x1f << 8)
-#define OMAP3630_CLKSEL_TV_MASK				(0x3f << 8)
-#define OMAP3430_CLKSEL_DSS1_SHIFT			0
-#define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)
-#define OMAP3630_CLKSEL_DSS1_MASK			(0x3f << 0)
-
-/* CM_SLEEPDEP_DSS specific bits */
-
-/* CM_CLKSTCTRL_DSS */
-#define OMAP3430_CLKTRCTRL_DSS_SHIFT			0
-#define OMAP3430_CLKTRCTRL_DSS_MASK			(0x3 << 0)
-
-/* CM_CLKSTST_DSS */
-#define OMAP3430_CLKACTIVITY_DSS_SHIFT			0
-#define OMAP3430_CLKACTIVITY_DSS_MASK			(1 << 0)
-
-/* CM_FCLKEN_CAM specific bits */
-#define OMAP3430_EN_CSI2_MASK				(1 << 1)
-#define OMAP3430_EN_CSI2_SHIFT				1
-
-/* CM_ICLKEN_CAM specific bits */
-
-/* CM_IDLEST_CAM */
-#define OMAP3430_ST_CAM_MASK				(1 << 0)
-
-/* CM_AUTOIDLE_CAM */
-#define OMAP3430_AUTO_CAM_MASK				(1 << 0)
-#define OMAP3430_AUTO_CAM_SHIFT				0
-
-/* CM_CLKSEL_CAM */
-#define OMAP3430_CLKSEL_CAM_SHIFT			0
-#define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)
-#define OMAP3630_CLKSEL_CAM_MASK			(0x3f << 0)
-
-/* CM_SLEEPDEP_CAM specific bits */
-
-/* CM_CLKSTCTRL_CAM */
-#define OMAP3430_CLKTRCTRL_CAM_SHIFT			0
-#define OMAP3430_CLKTRCTRL_CAM_MASK			(0x3 << 0)
-
-/* CM_CLKSTST_CAM */
-#define OMAP3430_CLKACTIVITY_CAM_SHIFT			0
-#define OMAP3430_CLKACTIVITY_CAM_MASK			(1 << 0)
-
-/* CM_FCLKEN_PER specific bits */
-
-/* CM_ICLKEN_PER specific bits */
-
-/* CM_IDLEST_PER */
-#define OMAP3430_ST_WDT3_SHIFT				12
-#define OMAP3430_ST_WDT3_MASK				(1 << 12)
-#define OMAP3430_ST_MCBSP4_SHIFT			2
-#define OMAP3430_ST_MCBSP4_MASK				(1 << 2)
-#define OMAP3430_ST_MCBSP3_SHIFT			1
-#define OMAP3430_ST_MCBSP3_MASK				(1 << 1)
-#define OMAP3430_ST_MCBSP2_SHIFT			0
-#define OMAP3430_ST_MCBSP2_MASK				(1 << 0)
-
-/* CM_AUTOIDLE_PER */
-#define OMAP3430_AUTO_GPIO6_MASK			(1 << 17)
-#define OMAP3430_AUTO_GPIO6_SHIFT			17
-#define OMAP3430_AUTO_GPIO5_MASK			(1 << 16)
-#define OMAP3430_AUTO_GPIO5_SHIFT			16
-#define OMAP3430_AUTO_GPIO4_MASK			(1 << 15)
-#define OMAP3430_AUTO_GPIO4_SHIFT			15
-#define OMAP3430_AUTO_GPIO3_MASK			(1 << 14)
-#define OMAP3430_AUTO_GPIO3_SHIFT			14
-#define OMAP3430_AUTO_GPIO2_MASK			(1 << 13)
-#define OMAP3430_AUTO_GPIO2_SHIFT			13
-#define OMAP3430_AUTO_WDT3_MASK				(1 << 12)
-#define OMAP3430_AUTO_WDT3_SHIFT			12
-#define OMAP3430_AUTO_UART3_MASK			(1 << 11)
-#define OMAP3430_AUTO_UART3_SHIFT			11
-#define OMAP3430_AUTO_GPT9_MASK				(1 << 10)
-#define OMAP3430_AUTO_GPT9_SHIFT			10
-#define OMAP3430_AUTO_GPT8_MASK				(1 << 9)
-#define OMAP3430_AUTO_GPT8_SHIFT			9
-#define OMAP3430_AUTO_GPT7_MASK				(1 << 8)
-#define OMAP3430_AUTO_GPT7_SHIFT			8
-#define OMAP3430_AUTO_GPT6_MASK				(1 << 7)
-#define OMAP3430_AUTO_GPT6_SHIFT			7
-#define OMAP3430_AUTO_GPT5_MASK				(1 << 6)
-#define OMAP3430_AUTO_GPT5_SHIFT			6
-#define OMAP3430_AUTO_GPT4_MASK				(1 << 5)
-#define OMAP3430_AUTO_GPT4_SHIFT			5
-#define OMAP3430_AUTO_GPT3_MASK				(1 << 4)
-#define OMAP3430_AUTO_GPT3_SHIFT			4
-#define OMAP3430_AUTO_GPT2_MASK				(1 << 3)
-#define OMAP3430_AUTO_GPT2_SHIFT			3
-#define OMAP3430_AUTO_MCBSP4_MASK			(1 << 2)
-#define OMAP3430_AUTO_MCBSP4_SHIFT			2
-#define OMAP3430_AUTO_MCBSP3_MASK			(1 << 1)
-#define OMAP3430_AUTO_MCBSP3_SHIFT			1
-#define OMAP3430_AUTO_MCBSP2_MASK			(1 << 0)
-#define OMAP3430_AUTO_MCBSP2_SHIFT			0
-
-/* CM_CLKSEL_PER */
-#define OMAP3430_CLKSEL_GPT9_MASK			(1 << 7)
-#define OMAP3430_CLKSEL_GPT9_SHIFT			7
-#define OMAP3430_CLKSEL_GPT8_MASK			(1 << 6)
-#define OMAP3430_CLKSEL_GPT8_SHIFT			6
-#define OMAP3430_CLKSEL_GPT7_MASK			(1 << 5)
-#define OMAP3430_CLKSEL_GPT7_SHIFT			5
-#define OMAP3430_CLKSEL_GPT6_MASK			(1 << 4)
-#define OMAP3430_CLKSEL_GPT6_SHIFT			4
-#define OMAP3430_CLKSEL_GPT5_MASK			(1 << 3)
-#define OMAP3430_CLKSEL_GPT5_SHIFT			3
-#define OMAP3430_CLKSEL_GPT4_MASK			(1 << 2)
-#define OMAP3430_CLKSEL_GPT4_SHIFT			2
-#define OMAP3430_CLKSEL_GPT3_MASK			(1 << 1)
-#define OMAP3430_CLKSEL_GPT3_SHIFT			1
-#define OMAP3430_CLKSEL_GPT2_MASK			(1 << 0)
-#define OMAP3430_CLKSEL_GPT2_SHIFT			0
-
-/* CM_SLEEPDEP_PER specific bits */
-#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK		(1 << 2)
-
-/* CM_CLKSTCTRL_PER */
-#define OMAP3430_CLKTRCTRL_PER_SHIFT			0
-#define OMAP3430_CLKTRCTRL_PER_MASK			(0x3 << 0)
-
-/* CM_CLKSTST_PER */
-#define OMAP3430_CLKACTIVITY_PER_SHIFT			0
-#define OMAP3430_CLKACTIVITY_PER_MASK			(1 << 0)
-
-/* CM_CLKSEL1_EMU */
-#define OMAP3430_DIV_DPLL4_SHIFT			24
-#define OMAP3430_DIV_DPLL4_MASK				(0x1f << 24)
-#define OMAP3630_DIV_DPLL4_MASK				(0x3f << 24)
-#define OMAP3430_DIV_DPLL3_SHIFT			16
-#define OMAP3430_DIV_DPLL3_MASK				(0x1f << 16)
-#define OMAP3430_CLKSEL_TRACECLK_SHIFT			11
-#define OMAP3430_CLKSEL_TRACECLK_MASK			(0x7 << 11)
-#define OMAP3430_CLKSEL_PCLK_SHIFT			8
-#define OMAP3430_CLKSEL_PCLK_MASK			(0x7 << 8)
-#define OMAP3430_CLKSEL_PCLKX2_SHIFT			6
-#define OMAP3430_CLKSEL_PCLKX2_MASK			(0x3 << 6)
-#define OMAP3430_CLKSEL_ATCLK_SHIFT			4
-#define OMAP3430_CLKSEL_ATCLK_MASK			(0x3 << 4)
-#define OMAP3430_TRACE_MUX_CTRL_SHIFT			2
-#define OMAP3430_TRACE_MUX_CTRL_MASK			(0x3 << 2)
-#define OMAP3430_MUX_CTRL_SHIFT				0
-#define OMAP3430_MUX_CTRL_MASK				(0x3 << 0)
-
-/* CM_CLKSTCTRL_EMU */
-#define OMAP3430_CLKTRCTRL_EMU_SHIFT			0
-#define OMAP3430_CLKTRCTRL_EMU_MASK			(0x3 << 0)
-
-/* CM_CLKSTST_EMU */
-#define OMAP3430_CLKACTIVITY_EMU_SHIFT			0
-#define OMAP3430_CLKACTIVITY_EMU_MASK			(1 << 0)
-
-/* CM_CLKSEL2_EMU specific bits */
-#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT		8
-#define OMAP3430_CORE_DPLL_EMU_MULT_MASK		(0x7ff << 8)
-#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT		0
-#define OMAP3430_CORE_DPLL_EMU_DIV_MASK			(0x7f << 0)
-
-/* CM_CLKSEL3_EMU specific bits */
-#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT		8
-#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK		(0x7ff << 8)
-#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT		0
-#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK		(0x7f << 0)
-
-/* CM_POLCTRL */
-#define OMAP3430_CLKOUT2_POL_MASK			(1 << 0)
-
-/* CM_IDLEST_NEON */
-#define OMAP3430_ST_NEON_MASK				(1 << 0)
-
-/* CM_CLKSTCTRL_NEON */
-#define OMAP3430_CLKTRCTRL_NEON_SHIFT			0
-#define OMAP3430_CLKTRCTRL_NEON_MASK			(0x3 << 0)
-
-/* CM_FCLKEN_USBHOST */
-#define OMAP3430ES2_EN_USBHOST2_SHIFT			1
-#define OMAP3430ES2_EN_USBHOST2_MASK			(1 << 1)
-#define OMAP3430ES2_EN_USBHOST1_SHIFT			0
-#define OMAP3430ES2_EN_USBHOST1_MASK			(1 << 0)
-
-/* CM_ICLKEN_USBHOST */
-#define OMAP3430ES2_EN_USBHOST_SHIFT			0
-#define OMAP3430ES2_EN_USBHOST_MASK			(1 << 0)
-
-/* CM_IDLEST_USBHOST */
-#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT		1
-#define OMAP3430ES2_ST_USBHOST_IDLE_MASK		(1 << 1)
-#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT		0
-#define OMAP3430ES2_ST_USBHOST_STDBY_MASK		(1 << 0)
-
-/* CM_AUTOIDLE_USBHOST */
-#define OMAP3430ES2_AUTO_USBHOST_SHIFT			0
-#define OMAP3430ES2_AUTO_USBHOST_MASK			(1 << 0)
-
-/* CM_SLEEPDEP_USBHOST */
-#define OMAP3430ES2_EN_MPU_SHIFT			1
-#define OMAP3430ES2_EN_MPU_MASK				(1 << 1)
-#define OMAP3430ES2_EN_IVA2_SHIFT			2
-#define OMAP3430ES2_EN_IVA2_MASK			(1 << 2)
-
-/* CM_CLKSTCTRL_USBHOST */
-#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT		0
-#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK		(3 << 0)
-
-/* CM_CLKSTST_USBHOST */
-#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT		0
-#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK		(1 << 0)
-
-#endif
diff --git a/arch/arm/mach-omap/include/mach/control.h b/arch/arm/mach-omap/include/mach/control.h
deleted file mode 100644
index 1cc4cd4ae4..0000000000
--- a/arch/arm/mach-omap/include/mach/control.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- * @file
- * @brief This file contains the Control register defines
- *
- * Originally from Linux kernel:
- * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
- * include/asm-arm/arch-omap/omap34xx.h
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * Copyright (C) 2007 Texas Instruments, <www.ti.com>
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_OMAP_CONTROL_H
-#define __ASM_ARCH_OMAP_CONTROL_H
-
-/**
- * Control register defintion which unwraps to the real register
- * offset + base address
- */
-#define OMAP3_CONTROL_REG(REGNAME)	(OMAP3_CTRL_BASE + CONTROL_##REGNAME)
-
-#define CONTROL_SCALABLE_OMAP_STATUS    (0x44C)
-#define CONTROL_SCALABLE_OMAP_OCP       (0x534)
-#define CONTROL_SCRATCHPAD_BASE		(0x910)
-#define CONTROL_SCRATCHPAD_ROM_BASE	(0x860)
-#define CONTROL_STATUS			(0x2f0)
-#define CONTROL_SYSCONFIG               (0x010)
-#define CONTROL_DEVCONF0		(0x274)
-#define CONTROL_DEVCONF1		(0x2D8)
-#define CONTROL_IVA2_BOOTMOD		(0x404)
-#define CONTROL_IVA2_BOOTADDR		(0x400)
-#define CONTROL_PBIAS_1			(0x520)
-#define CONTROL_GENERAL_PURPOSE_STATUS	(0x2F4)
-#define CONTROL_MEM_DFTRW0		(0x278)
-#define CONTROL_MEM_DFTRW1		(0x27C)
-#define CONTROL_MSUSPENDMUX_0		(0x290)
-#define CONTROL_MSUSPENDMUX_1		(0x294)
-#define CONTROL_MSUSPENDMUX_2		(0x298)
-#define CONTROL_MSUSPENDMUX_3		(0x29C)
-#define CONTROL_MSUSPENDMUX_4		(0x2A0)
-#define CONTROL_MSUSPENDMUX_5		(0x2A4)
-#define CONTROL_SEC_CTRL		(0x2B0)
-#define CONTROL_CSIRXFE			(0x2DC)
-#define CONTROL_DEBOBS_0		(0x420)
-#define CONTROL_DEBOBS_1		(0x424)
-#define CONTROL_DEBOBS_2		(0x428)
-#define CONTROL_DEBOBS_3		(0x42C)
-#define CONTROL_DEBOBS_4		(0x430)
-#define CONTROL_DEBOBS_5		(0x434)
-#define CONTROL_DEBOBS_6		(0x438)
-#define CONTROL_DEBOBS_7		(0x43C)
-#define CONTROL_DEBOBS_8		(0x440)
-#define CONTROL_PROG_IO0		(0x444)
-#define CONTROL_PROG_IO1		(0x448)
-#define CONTROL_DSS_DPLL_SPREADING	(0x450)
-#define CONTROL_CORE_DPLL_SPREADING	(0x454)
-#define CONTROL_PER_DPLL_SPREADING	(0x458)
-#define CONTROL_USBHOST_DPLL_SPREADING	(0x45C)
-#define CONTROL_TEMP_SENSOR		(0x524)
-#define CONTROL_SRAMLDO4		(0x528)
-#define CONTROL_SRAMLDO5		(0x52C)
-#define CONTROL_CSI			(0x530)
-#define CONTROL_SCALABLE_OMAP_OCP	(0x534)
-#define CONTROL_SCALABLE_OMAP_STATUS	(0x44C)
-
-/** Provide the Regoffset, Value */
-#define	MUX_VAL(OFFSET,VALUE)\
-	writew((VALUE), OMAP3_CTRL_BASE + (OFFSET))
-
-/**
- * macro for Padconfig Registers @see
- * include/mach-arm/arch-omap/omap3-mux.h
- */
-#define	CP(X) (CONTROL_PADCONF_##X)
-
-#endif /* __ASM_ARCH_OMAP_CONTROL_H */
diff --git a/arch/arm/mach-omap/include/mach/cpsw.h b/arch/arm/mach-omap/include/mach/cpsw.h
deleted file mode 100644
index 5474667a01..0000000000
--- a/arch/arm/mach-omap/include/mach/cpsw.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * CPSW Ethernet Switch Driver
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _CPSW_H_
-#define _CPSW_H_
-
-struct cpsw_slave_data {
-	int		phy_id;
-	int		phy_if;
-};
-
-struct cpsw_platform_data {
-	struct cpsw_slave_data	*slave_data;
-	int			num_slaves;
-};
-
-#endif /* _CPSW_H_  */
diff --git a/arch/arm/mach-omap/include/mach/debug_ll.h b/arch/arm/mach-omap/include/mach/debug_ll.h
deleted file mode 100644
index 25ddd485be..0000000000
--- a/arch/arm/mach-omap/include/mach/debug_ll.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2011
- * Author: Jan Weitzel <j.weitzel@phytec.de>
- * based on arch/arm/mach-versatile/include/mach/debug_ll.h
- *
- * barebox is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * barebox is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_DEBUG_LL_H__
-#define   __MACH_DEBUG_LL_H__
-
-#include <io.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap4-silicon.h>
-#include <mach/am33xx-silicon.h>
-
-#define LSR_THRE	0x20	/* Xmit holding register empty */
-#define LCR_BKSE	0x80	/* Bank select enable */
-#define LSR		(5 << 2)
-#define THR		(0 << 2)
-#define DLL		(0 << 2)
-#define IER		(1 << 2)
-#define DLM		(1 << 2)
-#define FCR		(2 << 2)
-#define LCR		(3 << 2)
-#define MCR		(4 << 2)
-#define MDR		(8 << 2)
-
-static inline void omap_uart_lowlevel_init(void __iomem *base)
-{
-	writeb(0x00, base + LCR);
-	writeb(0x00, base + IER);
-	writeb(0x07, base + MDR);
-	writeb(LCR_BKSE, base + LCR);
-	writeb(26, base + DLL); /* 115200 */
-	writeb(0, base + DLM);
-	writeb(0x03, base + LCR);
-	writeb(0x03, base + MCR);
-	writeb(0x07, base + FCR);
-	writeb(0x00, base + MDR);
-}
-
-#ifdef CONFIG_DEBUG_LL
-
-#ifdef CONFIG_DEBUG_OMAP3_UART
-#define OMAP_DEBUG_SOC OMAP3
-#elif defined CONFIG_DEBUG_OMAP4_UART
-#define OMAP_DEBUG_SOC OMAP44XX
-#elif defined CONFIG_DEBUG_AM33XX_UART
-#define OMAP_DEBUG_SOC AM33XX
-#else
-#error "unknown OMAP debug uart soc type"
-#endif
-
-#define __OMAP_UART_BASE(soc, num) soc##_UART##num##_BASE
-#define OMAP_UART_BASE(soc, num) __OMAP_UART_BASE(soc, num)
-
-static inline void PUTC_LL(char c)
-{
-	void __iomem *base = (void *)OMAP_UART_BASE(OMAP_DEBUG_SOC,
-			CONFIG_DEBUG_OMAP_UART_PORT);
-
-	/* Wait until there is space in the FIFO */
-	while ((readb(base + LSR) & LSR_THRE) == 0);
-	/* Send the character */
-	writeb(c, base + THR);
-	/* Wait to make sure it hits the line, in case we die too soon. */
-	while ((readb(base + LSR) & LSR_THRE) == 0);
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap/include/mach/devices.h b/arch/arm/mach-omap/include/mach/devices.h
deleted file mode 100644
index 537213fb90..0000000000
--- a/arch/arm/mach-omap/include/mach/devices.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __MACH_OMAP_DEVICES_H
-#define __MACH_OMAP_DEVICES_H
-
-#include <mach/omap_hsmmc.h>
-
-void omap_add_ram0(resource_size_t size);
-
-void omap_add_sram0(resource_size_t base, resource_size_t size);
-
-struct device_d *omap_add_uart(int id, unsigned long base);
-
-#endif /* __MACH_OMAP_DEVICES_H */
diff --git a/arch/arm/mach-omap/include/mach/ehci.h b/arch/arm/mach-omap/include/mach/ehci.h
deleted file mode 100644
index cccb9ad364..0000000000
--- a/arch/arm/mach-omap/include/mach/ehci.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de>
- *
- * This file is released under the GPLv2
- *
- */
-
-#ifndef __OMAP_EHCI_H
-#define __OMAP_EHCI_H
-
-/* TLL Register Set */
-#define	OMAP_USBTLL_REVISION				(0x00)
-#define	OMAP_USBTLL_SYSCONFIG				(0x10)
-#define	OMAP_USBTLL_SYSCONFIG_CACTIVITY			(1 << 8)
-#define	OMAP_USBTLL_SYSCONFIG_SIDLEMODE			(1 << 3)
-#define	OMAP_USBTLL_SYSCONFIG_ENAWAKEUP			(1 << 2)
-#define	OMAP_USBTLL_SYSCONFIG_SOFTRESET			(1 << 1)
-#define	OMAP_USBTLL_SYSCONFIG_AUTOIDLE			(1 << 0)
-
-#define	OMAP_USBTLL_SYSSTATUS				(0x14)
-#define	OMAP_USBTLL_SYSSTATUS_RESETDONE			(1 << 0)
-
-#define	OMAP_USBTLL_IRQSTATUS				(0x18)
-#define	OMAP_USBTLL_IRQENABLE				(0x1C)
-
-#define	OMAP_TLL_SHARED_CONF				(0x30)
-#define	OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN		(1 << 6)
-#define	OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN		(1 << 5)
-#define	OMAP_TLL_SHARED_CONF_USB_DIVRATION		(1 << 2)
-#define	OMAP_TLL_SHARED_CONF_FCLK_REQ			(1 << 1)
-#define	OMAP_TLL_SHARED_CONF_FCLK_IS_ON			(1 << 0)
-
-#define	OMAP_TLL_CHANNEL_CONF(num)			(0x040 + 0x004 * num)
-#define	OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF		(1 << 11)
-#define	OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE		(1 << 10)
-#define	OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE		(1 << 9)
-#define	OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE		(1 << 8)
-#define	OMAP_TLL_CHANNEL_CONF_CHANEN			(1 << 0)
-
-#define	OMAP_TLL_ULPI_FUNCTION_CTRL(num)		(0x804 + 0x100 * num)
-#define	OMAP_TLL_ULPI_INTERFACE_CTRL(num)		(0x807 + 0x100 * num)
-#define	OMAP_TLL_ULPI_OTG_CTRL(num)			(0x80A + 0x100 * num)
-#define	OMAP_TLL_ULPI_INT_EN_RISE(num)			(0x80D + 0x100 * num)
-#define	OMAP_TLL_ULPI_INT_EN_FALL(num)			(0x810 + 0x100 * num)
-#define	OMAP_TLL_ULPI_INT_STATUS(num)			(0x813 + 0x100 * num)
-#define	OMAP_TLL_ULPI_INT_LATCH(num)			(0x814 + 0x100 * num)
-#define	OMAP_TLL_ULPI_DEBUG(num)			(0x815 + 0x100 * num)
-#define	OMAP_TLL_ULPI_SCRATCH_REGISTER(num)		(0x816 + 0x100 * num)
-
-#define OMAP_TLL_CHANNEL_COUNT				3
-#define OMAP_TLL_CHANNEL_1_EN_MASK			(1 << 1)
-#define OMAP_TLL_CHANNEL_2_EN_MASK			(1 << 2)
-#define OMAP_TLL_CHANNEL_3_EN_MASK			(1 << 4)
-
-/* UHH Register Set */
-#define	OMAP_UHH_REVISION				(0x00)
-#define	OMAP_UHH_SYSCONFIG				(0x10)
-#define	OMAP_UHH_SYSCONFIG_MIDLEMODE			(1 << 12)
-#define	OMAP_UHH_SYSCONFIG_CACTIVITY			(1 << 8)
-#define	OMAP_UHH_SYSCONFIG_SIDLEMODE			(1 << 3)
-#define	OMAP_UHH_SYSCONFIG_ENAWAKEUP			(1 << 2)
-#define	OMAP_UHH_SYSCONFIG_SOFTRESET			(1 << 1)
-#define	OMAP_UHH_SYSCONFIG_AUTOIDLE			(1 << 0)
-
-#define	OMAP_UHH_SYSSTATUS				(0x14)
-#define	OMAP_UHH_HOSTCONFIG				(0x40)
-#define	OMAP_UHH_HOSTCONFIG_ULPI_BYPASS			(1 << 0)
-#define	OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS		(1 << 0)
-#define	OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS		(1 << 11)
-#define	OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS		(1 << 12)
-#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN		(1 << 2)
-#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN		(1 << 3)
-#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN		(1 << 4)
-#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN		(1 << 5)
-#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS		(1 << 8)
-#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS		(1 << 9)
-#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS		(1 << 10)
-
-#define	OMAP_UHH_DEBUG_CSR				(0x44)
-
-/* EHCI Register Set */
-#define	EHCI_INSNREG05_ULPI				(0xA4)
-#define	EHCI_INSNREG05_ULPI_CONTROL_SHIFT		31
-#define	EHCI_INSNREG05_ULPI_PORTSEL_SHIFT		24
-#define	EHCI_INSNREG05_ULPI_OPSEL_SHIFT			22
-#define	EHCI_INSNREG05_ULPI_REGADD_SHIFT		16
-#define	EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT		8
-#define	EHCI_INSNREG05_ULPI_WRDATA_SHIFT		0
-
-#define OMAP3_HS_USB_PORTS      3
-
-enum ehci_hcd_omap_mode {
-        EHCI_HCD_OMAP_MODE_UNKNOWN,
-        EHCI_HCD_OMAP_MODE_PHY,
-        EHCI_HCD_OMAP_MODE_TLL,
-};
-
-struct omap_hcd {
-        enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
-        unsigned                        phy_reset:1;
-
-        /* have to be valid if phy_reset is true and portx is in phy mode */
-        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
-};
-
-void omap_usb_utmi_init(struct omap_hcd *omap, u8 tll_channel_mask);
-int ehci_omap_init(struct omap_hcd *omap);
-
-#endif /* __OMAP_EHCI_H */
diff --git a/arch/arm/mach-omap/include/mach/emac_defs.h b/arch/arm/mach-omap/include/mach/emac_defs.h
deleted file mode 100644
index 568de6a12a..0000000000
--- a/arch/arm/mach-omap/include/mach/emac_defs.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Based on:
- *
- * ----------------------------------------------------------------------------
- *
- * dm644x_emac.h
- *
- * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
- *
- * Copyright (C) 2005 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- * ----------------------------------------------------------------------------
-
- * Modifications:
- * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
- *
- */
-
-#ifndef _AM3517_EMAC_H_
-#define _AM3517_EMAC_H_
-
-#define EMAC_BASE_ADDR                 0x5C010000
-#define EMAC_WRAPPER_BASE_ADDR         0x5C000000
-#define EMAC_WRAPPER_RAM_ADDR          0x5C020000
-#define EMAC_MDIO_BASE_ADDR            0x5C030000
-#define EMAC_HW_RAM_ADDR               0x01E20000
-
-#define EMAC_MDIO_BUS_FREQ             166000000       /* 166 MHZ check */
-#define EMAC_MDIO_CLOCK_FREQ           1000000         /* 2.0 MHz */
-
-#endif  /* _AM3517_EMAC_H_ */
diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h
deleted file mode 100644
index 1f9c2938a1..0000000000
--- a/arch/arm/mach-omap/include/mach/emif4.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Auther:
- *       Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _EMIF_H_
-#define _EMIF_H_
-
-/*
- * Configuration values
- */
-#define EMIF4_TIM1_T_RP		(0x3 << 25)
-#define EMIF4_TIM1_T_RCD	(0x3 << 21)
-#define EMIF4_TIM1_T_WR		(0x3 << 17)
-#define EMIF4_TIM1_T_RAS	(0x7 << 12) /* 8->7 */
-#define EMIF4_TIM1_T_RC		(0xA << 6)
-#define EMIF4_TIM1_T_RRD	(0x2 << 3)
-#define EMIF4_TIM1_T_WTR	(0x2)
-
-#define EMIF4_TIM2_T_XP		(0x2 << 28)
-#define EMIF4_TIM2_T_ODT	(0x0 << 25) /* 2? */
-#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
-#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
-#define EMIF4_TIM2_T_RTP	(0x1 << 3)
-#define EMIF4_TIM2_T_CKE	(0x2)
-
-#define EMIF4_TIM3_T_RFC	(0x15 << 4) /* 25->15 */
-#define EMIF4_TIM3_T_RAS_MAX	(0xf)	    /* 7->f */
-
-#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
-#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
-#define EMIF4_PWR_DPD_EN	(0x1 << 10)
-#define EMIF4_PWR_LP_MODE	(0x0 << 8)
-#define EMIF4_PWR_PM_TIM	(0x0)
-
-#define EMIF4_INITREF_DIS	(0x0 << 31)
-#define EMIF4_REFRESH_RATE	(0x257) /* 50f->257 */
-
-#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
-#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
-#define EMIF4_CFG_DDR_TERM	(0x3 << 24) /* --> 0x3 */
-#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
-#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
-#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
-#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
-#define EMIF4_CFG_CL		(0x5 << 10)
-#define EMIF4_CFG_ROWSIZE	(0x0 << 7) /* --> 0x4: a0..a12 */
-#define EMIF4_CFG_IBANK		(0x3 << 4)
-#define EMIF4_CFG_EBANK		(0x0 << 3)
-#define EMIF4_CFG_PGSIZE	(0x2)      /* 10 columns */
-
-/*
- * EMIF4 PHY Control 1 register configuration
- */
-#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
-#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
-#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
-#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
-#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
-
-struct emif4 {
-	unsigned int emif_mod_id_rev;
-	unsigned int sdram_sts;
-	unsigned int sdram_config;
-	unsigned int res1;
-	unsigned int sdram_refresh_ctrl;
-	unsigned int sdram_refresh_ctrl_shdw;
-	unsigned int sdram_time1;
-	unsigned int sdram_time1_shdw;
-	unsigned int sdram_time2;
-	unsigned int sdram_time2_shdw;
-	unsigned int sdram_time3;
-	unsigned int sdram_time3_shdw;
-	unsigned char res2[8];
-	unsigned int sdram_pwr_mgmt;
-	unsigned int sdram_pwr_mgmt_shdw;
-	unsigned char res3[32];
-	unsigned int sdram_iodft_tlgc;
-	unsigned char res4[128];
-	unsigned int ddr_phyctrl1;
-	unsigned int ddr_phyctrl1_shdw;
-	unsigned int ddr_phyctrl2;
-};
-
-void am35xx_emif4_init(void);
-
-#endif /* endif _EMIF_H_ */
diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h
deleted file mode 100644
index fe194b3921..0000000000
--- a/arch/arm/mach-omap/include/mach/generic.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef _MACH_GENERIC_H
-#define _MACH_GENERIC_H
-
-/* I2C controller revisions */
-#define OMAP_I2C_OMAP1_REV_2            0x20
-
-/* I2C controller revisions present on specific hardware */
-#define OMAP_I2C_REV_ON_2430		0x00000036
-#define OMAP_I2C_REV_ON_3430_3530       0x0000003C
-#define OMAP_I2C_REV_ON_3630            0x00000040
-#define OMAP_I2C_REV_ON_4430_PLUS       0x50400002
-
-extern unsigned int __omap_cpu_type;
-
-#define OMAP_CPU_OMAP3		3
-#define OMAP_CPU_OMAP4		4
-#define OMAP_CPU_AM33XX		33
-
-#ifdef CONFIG_ARCH_OMAP3
-# ifdef omap_cpu_type
-#  undef omap_cpu_type
-#  define omap_cpu_type __omap_cpu_type
-# else
-#  define omap_cpu_type OMAP_CPU_OMAP3
-# endif
-# define cpu_is_omap3()		(omap_cpu_type == OMAP_CPU_OMAP3)
-#else
-# define cpu_is_omap3()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-# ifdef omap_cpu_type
-#  undef omap_cpu_type
-#  define omap_cpu_type __omap_cpu_type
-# else
-#  define omap_cpu_type OMAP_CPU_OMAP4
-# endif
-# define cpu_is_omap4()		(omap_cpu_type == OMAP_CPU_OMAP4)
-#else
-# define cpu_is_omap4()		(0)
-#endif
-
-#ifdef CONFIG_ARCH_AM33XX
-# ifdef omap_cpu_type
-#  undef omap_cpu_type
-#  define omap_cpu_type __omap_cpu_type
-# else
-#  define omap_cpu_type OMAP_CPU_AM33XX
-# endif
-# define cpu_is_am33xx()		(omap_cpu_type == OMAP_CPU_AM33XX)
-#else
-# define cpu_is_am33xx()	(0)
-#endif
-
-struct omap_barebox_part {
-	unsigned int nand_offset;
-	unsigned int nand_size;
-	unsigned int nand_bkup_offset;
-	unsigned int nand_bkup_size;
-	unsigned int nor_offset;
-	unsigned int nor_size;
-};
-
-#ifdef CONFIG_SHELL_NONE
-int omap_set_barebox_part(struct omap_barebox_part *part);
-int omap_set_mmc_dev(const char *mmcdev);
-#else
-static inline int omap_set_barebox_part(struct omap_barebox_part *part)
-{
-	return 0;
-}
-static inline int omap_set_mmc_dev(const char *mmcdev)
-{
-	return 0;
-}
-#endif
-
-void __noreturn omap_start_barebox(void *barebox);
-
-void omap_set_bootmmc_devname(const char *devname);
-const char *omap_get_bootmmc_devname(void);
-
-#endif
diff --git a/arch/arm/mach-omap/include/mach/gpmc.h b/arch/arm/mach-omap/include/mach/gpmc.h
deleted file mode 100644
index d4eac79717..0000000000
--- a/arch/arm/mach-omap/include/mach/gpmc.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/**
- * @file
- * @brief This file contains the GPMC's generic definitions
- *
- * OMAP's General Purpose Memory Controller(GPMC) provides features
- * allowing us to communicate with memory devices such as NOR, NAND,
- * OneNAND, SRAM etc.. This file defines certain generic parameters
- * allowing us to configure the same painlessly.
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * Originally from Linux kernel:
- * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
- * include/asm-arm/arch-omap/omap34xx.h
- *
- * Copyright (C) 2007 Texas Instruments, <www.ti.com>
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_OMAP_GPMC_H
-#define __ASM_ARCH_OMAP_GPMC_H
-
-extern void __iomem *omap_gpmc_base;
-
-/** GPMC Reg Wrapper */
-#define GPMC_REG(REGNAME)	(omap_gpmc_base + GPMC_##REGNAME)
-
-#define GPMC_SYS_CONFIG		(0x10)
-#define GPMC_SYS_STATUS		(0x14)
-#define GPMC_IRQSTATUS		(0x18)
-#define GPMC_IRQ_ENABLE		(0x1C)
-#define GPMC_TIMEOUT_CONTROL	(0x40)
-#define GPMC_CFG		(0x50)
-#define GPMC_STATUS		(0x54)
-#define GPMC_PREFETCH_CONFIG1	(0x1E0)
-#define GPMC_PREFETCH_CONFIG2	(0x1E4)
-#define GPMC_PREFETCH_CONTROL	(0x1EC)
-#define GPMC_PREFETCH_STATUS	(0x1f0)
-#define GPMC_ECC_CONFIG		(0x1F4)
-#define GPMC_ECC_CONTROL	(0x1F8)
-#define GPMC_ECC_SIZE_CONFIG	(0x1FC)
-#define GPMC_ECC1_RESULT	(0x200)
-#define GPMC_ECC2_RESULT	(0x204)
-#define GPMC_ECC3_RESULT	(0x208)
-#define GPMC_ECC4_RESULT	(0x20C)
-#define GPMC_ECC5_RESULT	(0x210)
-#define GPMC_ECC6_RESULT	(0x214)
-#define GPMC_ECC7_RESULT	(0x218)
-#define GPMC_ECC8_RESULT	(0x21C)
-#define GPMC_ECC9_RESULT	(0x220)
-#define GPMC_ECC_BCH_RESULT_0	0x240
-
-#define GPMC_CONFIG1_0		(0x60)
-#define GPMC_CONFIG1_1		(0x90)
-#define GPMC_CONFIG1_2		(0xC0)
-#define GPMC_CONFIG1_3		(0xF0)
-#define GPMC_CONFIG1_4		(0x120)
-#define GPMC_CONFIG1_5		(0x150)
-#define GPMC_CONFIG1_6		(0x180)
-#define GPMC_CONFIG1_7		(0x1B0)
-#define GPMC_CONFIG2_0		(0x64)
-#define GPMC_CONFIG2_1		(0x94)
-#define GPMC_CONFIG2_2		(0xC4)
-#define GPMC_CONFIG2_3		(0xF4)
-#define GPMC_CONFIG2_4		(0x124)
-#define GPMC_CONFIG2_5		(0x154)
-#define GPMC_CONFIG2_6		(0x184)
-#define GPMC_CONFIG2_7		(0x1B4)
-#define GPMC_CONFIG3_0		(0x68)
-#define GPMC_CONFIG3_1		(0x98)
-#define GPMC_CONFIG3_2		(0xC8)
-#define GPMC_CONFIG3_3		(0xF8)
-#define GPMC_CONFIG3_4		(0x128)
-#define GPMC_CONFIG3_5		(0x158)
-#define GPMC_CONFIG3_6		(0x188)
-#define GPMC_CONFIG3_7		(0x1B8)
-#define GPMC_CONFIG4_0		(0x6C)
-#define GPMC_CONFIG4_1		(0x9C)
-#define GPMC_CONFIG4_2		(0xCC)
-#define GPMC_CONFIG4_3		(0xFC)
-#define GPMC_CONFIG4_4		(0x12C)
-#define GPMC_CONFIG4_5		(0x15C)
-#define GPMC_CONFIG4_6		(0x18C)
-#define GPMC_CONFIG4_7		(0x1BC)
-#define GPMC_CONFIG5_0		(0x70)
-#define GPMC_CONFIG5_1		(0xA0)
-#define GPMC_CONFIG5_2		(0xD0)
-#define GPMC_CONFIG5_3		(0x100)
-#define GPMC_CONFIG5_4		(0x130)
-#define GPMC_CONFIG5_5		(0x160)
-#define GPMC_CONFIG5_6		(0x190)
-#define GPMC_CONFIG5_7		(0x1C0)
-#define GPMC_CONFIG6_0		(0x74)
-#define GPMC_CONFIG6_1		(0xA4)
-#define GPMC_CONFIG6_2		(0xD4)
-#define GPMC_CONFIG6_3		(0x104)
-#define GPMC_CONFIG6_4		(0x134)
-#define GPMC_CONFIG6_5		(0x164)
-#define GPMC_CONFIG6_6		(0x194)
-#define GPMC_CONFIG6_7		(0x1C4)
-#define GPMC_CONFIG7_0		(0x78)
-#define GPMC_CONFIG7_1		(0xA8)
-#define GPMC_CONFIG7_2		(0xD8)
-#define GPMC_CONFIG7_3		(0x108)
-#define GPMC_CONFIG7_4		(0x138)
-#define GPMC_CONFIG7_5		(0x168)
-#define GPMC_CONFIG7_6		(0x198)
-#define GPMC_CONFIG7_7		(0x1C8)
-
-#define GPMC_NUM_CS		8
-#define GPMC_CONFIG_CS_SIZE	(GPMC_CONFIG1_1 - GPMC_CONFIG1_0)
-#define GPMC_CONFIG_REG_OFF	(GPMC_CONFIG2_0 - GPMC_CONFIG1_0)
-
-#define GPMC_CS_NAND_COMMAND	(0x1C)
-#define GPMC_CS_NAND_ADDRESS	(0x20)
-#define GPMC_CS_NAND_DATA	(0x24)
-
-#define GPMC_SIZE_128M		0x08
-#define GPMC_SIZE_64M		0x0C
-#define GPMC_SIZE_32M		0x0E
-#define GPMC_SIZE_16M		0x0F
-
-#define PREFETCH_FIFOTHRESHOLD_MAX	0x40
-#define PREFETCH_FIFOTHRESHOLD(val)	((val) << 8)
-#define GPMC_PREFETCH_STATUS_FIFO_CNT(val)	((val >> 24) & 0x7F)
-#define GPMC_PREFETCH_STATUS_COUNT(val)	(val & 0x00003fff)
-
-int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
-				unsigned int u32_count, int is_write);
-int gpmc_prefetch_reset(int cs);
-
-#define NAND_WP_BIT		0x00000010
-
-#ifndef __ASSEMBLY__
-
-/** Generic GPMC configuration structure to be used to configure a
- *  chip select
- */
-struct gpmc_config {
-	unsigned int cfg[6];
-	unsigned int base;
-	unsigned char size;
-};
-
-/** Generic configuration - will reset all the cs configs. */
-void gpmc_generic_init(unsigned int cfg);
-
-/** Configuration for a specific chip select */
-void gpmc_cs_config(char cs, struct gpmc_config *config);
-
-#endif
-
-#endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/arch/arm/mach-omap/include/mach/gpmc_nand.h b/arch/arm/mach-omap/include/mach/gpmc_nand.h
deleted file mode 100644
index f172b576eb..0000000000
--- a/arch/arm/mach-omap/include/mach/gpmc_nand.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/**
- * @file
- * @brief This file contains exported structure for NAND
- *
- * OMAP's General Purpose Memory Controller (GPMC) has a NAND controller
- * embedded. this file provides the platform data structure required to
- * hook on to it.
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * Originally from Linux kernel:
- * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.3.tar.gz
- * include/asm-arm/arch-omap/nand.h
- *
- * Copyright (C) 2006 Micron Technology Inc.
- * Author: Shahrom Sharif-Kashani
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_OMAP_NAND_GPMC_H
-#define  __ASM_OMAP_NAND_GPMC_H
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-
-enum gpmc_ecc_mode {
-	OMAP_ECC_SOFT,
-	OMAP_ECC_HAMMING_CODE_HW_ROMCODE,
-	OMAP_ECC_BCH8_CODE_HW,
-	OMAP_ECC_BCH8_CODE_HW_ROMCODE,
-	OMAP_ECC_BCH16_CODE_HW,
-};
-
-/** omap nand platform data structure */
-struct gpmc_nand_platform_data {
-	/** Chip select you want to use */
-	int cs;
-	struct mtd_partition *parts;
-	int nr_parts;
-	/** If there are any special setups you'd want to do */
-	int (*nand_setup) (struct gpmc_nand_platform_data *);
-
-	/** ecc mode to use */
-	enum gpmc_ecc_mode ecc_mode;
-	/** setup any special options */
-	unsigned int options;
-	/** set up device access as 8,16 as per GPMC config */
-	char device_width;
-	/** Set this to WAITx+1, so GPMC WAIT0 will be 1 and so on. */
-	char wait_mon_pin;
-
-	/* if you like a custom oob use this. */
-	struct nand_ecclayout *oob;
-	/** gpmc config for nand */
-	struct gpmc_config *nand_cfg;
-
-	struct device_node *of_node;
-	struct device_node *elm_of_node;
-};
-
-int omap_add_gpmc_nand_device(struct gpmc_nand_platform_data *pdata);
-
-extern struct gpmc_config omap3_nand_cfg;
-extern struct gpmc_config omap4_nand_cfg;
-extern struct gpmc_config am33xx_nand_cfg;
-
-#endif				/* __ASM_OMAP_NAND_GPMC_H */
diff --git a/arch/arm/mach-omap/include/mach/intc.h b/arch/arm/mach-omap/include/mach/intc.h
deleted file mode 100644
index 6c53528db2..0000000000
--- a/arch/arm/mach-omap/include/mach/intc.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/**
- * @file
- * @brief This file contains the Interrupt controller register defines
- *
- * Originally from Linux kernel:
- * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
- * include/asm-arm/arch-omap/omap34xx.h
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * Copyright (C) 2007 Texas Instruments, <www.ti.com>
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_OMAP_INTC_H
-#define __ASM_ARCH_OMAP_INTC_H
-
-/** Interrupt Controller Register wrapper */
-#define INTC_REG(REGNAME)	(OMAP_INTC_BASE + INTC_##REGNAME)
-
-#define INTC_MIR_0		(0x084)
-#define INTC_MIR_1		(0x0A4)
-#define INTC_MIR_2		(0x0C4)
-#define INTC_MIR_SET_0		(0x08C)
-#define INTC_MIR_SET_1		(0x0AC)
-#define INTC_MIR_SET_2		(0x0CC)
-#define INTC_MIR_CLEAR_0	(0x094)
-#define INTC_MIR_CLEAR_1	(0x0B4)
-#define INTC_MIR_CLEAR_2	(0x0D4)
-#define INTC_PS_SYSCONFIG       (0x010)
-#define INTC_PS_PROTECTION      (0x04C)
-#define INTC_PS_IDLE            (0x050)
-#define INTC_PS_THRESHOLD       (0x068)
-#define INTC_PS_PENDING_IRQ0	(0x098)
-#define INTC_PS_PENDING_IRQ1	(0x0B8)
-#define INTC_PS_PENDING_IRQ2	(0x0D8)
-
-#endif /* __ASM_ARCH_OMAP_INTC_H */
diff --git a/arch/arm/mach-omap/include/mach/mcspi.h b/arch/arm/mach-omap/include/mach/mcspi.h
deleted file mode 100644
index dbde67a5da..0000000000
--- a/arch/arm/mach-omap/include/mach/mcspi.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __OMAP_MCSPI_H
-#define  __OMAP_MCSPI_H
-
-#define OMAP3_MCSPI1_BASE	0x48098000
-#define OMAP3_MCSPI2_BASE	0x4809A000
-#define OMAP3_MCSPI3_BASE	0x480B8000
-#define OMAP3_MCSPI4_BASE	0x480BA000
-
-int mcspi_devices_init(void);
-
-#endif /* __OMAP_MCSPI_H */
diff --git a/arch/arm/mach-omap/include/mach/omap-fb.h b/arch/arm/mach-omap/include/mach/omap-fb.h
deleted file mode 100644
index f68dc1a142..0000000000
--- a/arch/arm/mach-omap/include/mach/omap-fb.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
-#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
-
-#include <fb.h>
-
-#define OMAP_DSS_LCD_TFT	(1u << 0)
-#define OMAP_DSS_LCD_IVS	(1u << 1)
-#define OMAP_DSS_LCD_IHS	(1u << 2)
-#define OMAP_DSS_LCD_IPC	(1u << 3)
-#define OMAP_DSS_LCD_IEO	(1u << 4)
-#define OMAP_DSS_LCD_RF	(1u << 5)
-#define OMAP_DSS_LCD_ONOFF	(1u << 6)
-
-#define OMAP_DSS_LCD_DATALINES(_l)	((_l) << 10)
-#define OMAP_DSS_LCD_DATALINES_msk	OMAP_DSS_LCD_DATALINES(3u)
-#define OMAP_DSS_LCD_DATALINES_12	OMAP_DSS_LCD_DATALINES(0u)
-#define OMAP_DSS_LCD_DATALINES_16	OMAP_DSS_LCD_DATALINES(1u)
-#define OMAP_DSS_LCD_DATALINES_18	OMAP_DSS_LCD_DATALINES(2u)
-#define OMAP_DSS_LCD_DATALINES_24	OMAP_DSS_LCD_DATALINES(3u)
-
-struct omapfb_display {
-	struct fb_videomode mode;
-
-	unsigned long config;
-
-	unsigned int power_on_delay;
-	unsigned int power_off_delay;
-};
-
-struct omapfb_platform_data {
-	struct omapfb_display const *displays;
-	size_t num_displays;
-
-	unsigned int dss_clk_hz;
-
-	unsigned int bpp;
-
-	struct resource const *screen;
-
-	void (*enable)(int p);
-};
-
-struct device_d;
-struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata);
-
-
-#endif	/* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
deleted file mode 100644
index 849964ab3e..0000000000
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/**
- * @file
- * @brief Contains the PRM and CM definitions
- *
- * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
- *
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _OMAP343X_CLOCKS_H_
-#define _OMAP343X_CLOCKS_H_
-
-/** CM Clock Regs Wrapper */
-#define OMAP3_CM_REG(REGNAME)	(OMAP3_CM_BASE + CM_##REGNAME)
-
-#define CM_FCLKEN_IVA2		0X0000
-#define CM_CLKEN_PLL_IVA2	0X0004
-#define CM_IDLEST_PLL_IVA2	0X0024
-#define CM_CLKSEL1_PLL_IVA2	0X0040
-#define CM_CLKSEL2_PLL_IVA2	0X0044
-#define CM_CLKEN_PLL_MPU	0X0904
-#define CM_IDLEST_PLL_MPU	0X0924
-#define CM_CLKSEL1_PLL_MPU	0X0940
-#define CM_CLKSEL2_PLL_MPU	0X0944
-#define CM_FCLKEN1_CORE		0X0A00
-#define CM_FCLKEN3_CORE		0X0A08
-#define CM_ICLKEN1_CORE		0X0A10
-#define CM_ICLKEN2_CORE		0X0A14
-#define CM_ICLKEN3_CORE		0X0A18
-#define CM_AIDLE3_CORE		0X0A38
-#define CM_CLKSEL_CORE		0X0A40
-#define CM_FCLKEN_GFX		0X0B00
-#define CM_ICLKEN_GFX		0X0B10
-#define CM_CLKSEL_GFX		0X0B40
-#define CM_FCLKEN_WKUP		0X0C00
-#define CM_ICLKEN_WKUP		0X0C10
-#define CM_CLKSEL_WKUP		0X0C40
-#define CM_IDLEST_WKUP		0X0C20
-#define CM_CLKEN_PLL		0X0D00
-#define CM_CLKEN2_PLL		0X0D04
-#define CM_IDLEST_CKGEN		0X0D20
-#define CM_CLKSEL1_PLL		0X0D40
-#define CM_CLKSEL2_PLL		0X0D44
-#define CM_CLKSEL3_PLL		0X0D48
-#define CM_CLKSEL4_PLL		0X0D4C
-#define CM_CLKSEL5_PLL		0X0D50
-#define CM_FCLKEN_DSS		0X0E00
-#define CM_ICLKEN_DSS		0X0E10
-#define CM_CLKSEL_DSS		0X0E40
-#define CM_FCLKEN_CAM		0X0F00
-#define CM_ICLKEN_CAM		0X0F10
-#define CM_CLKSEL_CAM		0X0f40
-#define CM_FCLKEN_PER		0X1000
-#define CM_ICLKEN_PER		0X1010
-#define CM_IDLEST_PER		0X1020
-#define CM_AUTOIDLE_PER		0X1030
-#define CM_CLKSEL_PER		0X1040
-#define CM_CLKSEL1_EMU		0X1140
-#define CM_FCLKEN_USBH		0x1400
-#define CM_ICLKEN_USBH		0x1410
-#define CM_AIDLE_USBH		0x1430
-#define CM_SLEEPD_USBH		0x1444
-#define CM_CLKSTCTRL_USBH	0x1448
-
-/** PRM Clock Regs */
-#define OMAP3_PRM_REG(REGNAME)	(OMAP3_PRM_BASE + PRM_##REGNAME)
-#define PRM_CLKSEL		0x0D40
-#define PRM_RSTCTRL		0x1250
-#define PRM_CLKSRC_CTRL		0x1270
-
-/*************** Clock Values */
-#define PLL_STOP		1	/* PER & IVA */
-#define PLL_LOW_POWER_BYPASS	5	/* MPU, IVA & CORE */
-#define PLL_FAST_RELOCK_BYPASS	6	/* CORE */
-#define PLL_LOCK		7	/* MPU, IVA, CORE & PER */
-
-/*
- * Bit positions indicating current SYSCLK divider
- */
-#define SYSCLK_DIV_1		(1 << 6)
-#define SYSCLK_DIV_2		(1 << 7)
-
-/* The following configurations are OPP and SysClk value independant
- * and hence are defined here.
- */
-
-/* CORE DPLL */
-#define CORE_M3X2		2        /* 332MHz : CM_CLKSEL1_EMU */
-#define CORE_SSI_DIV		3        /* 221MHz : CM_CLKSEL_CORE */
-#define CORE_FUSB_DIV		2        /* 41.5MHz: */
-#define CORE_L4_DIV		2        /*  83MHz : L4 */
-#define CORE_L3_DIV		2        /* 166MHz : L3 {DDR} */
-#define GFX_DIV_34X		3        /*  96MHz : CM_CLKSEL_GFX (OMAP34XX) */
-#define GFX_DIV_36X		5        /* 200MHz : CM_CLKSEL_GFX (OMAP36XX) */
-#define WKUP_RSM		2        /* 41.5MHz: CM_CLKSEL_WKUP */
-
-/* PER DPLL */
-#define PER_M6X2		3         /* 288MHz: CM_CLKSEL1_EMU */
-#define PER_M5X2		4         /* 216MHz: CM_CLKSEL_CAM */
-#define PER_M4X2		2         /* 432MHz: CM_CLKSEL_DSS-dss1 */
-#define PER_M3X2		16        /* 54MHz : CM_CLKSEL_DSS-tv */
-
-#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50))
-
-#define MAX_SIL_INDEX	1
-
-#ifndef __ASSEMBLY__
-void prcm_init(void);
-/* Used to index into DPLL parameter tables -See TRM for further details */
-struct dpll_param {
-	unsigned int m;
-	unsigned int n;
-	unsigned int fsel;
-	unsigned int m2;
-};
-
-struct dpll_param_per_36x {
-	unsigned int m;
-	unsigned int n;
-	unsigned int m2;
-	unsigned int m3;
-	unsigned int m4;
-	unsigned int m5;
-	unsigned int m6;
-	unsigned int m2div;
-};
-
-#endif /* __ASSEMBLY__ */
-
-#endif  /* endif _OMAP343X_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/include/mach/omap3-devices.h b/arch/arm/mach-omap/include/mach/omap3-devices.h
deleted file mode 100644
index 8c62c99005..0000000000
--- a/arch/arm/mach-omap/include/mach/omap3-devices.h
+++ /dev/null
@@ -1,102 +0,0 @@
-#ifndef __MACH_OMAP3_DEVICES_H
-#define __MACH_OMAP3_DEVICES_H
-
-#include <driver.h>
-#include <linux/sizes.h>
-#include <mach/omap3-silicon.h>
-#include <mach/devices.h>
-#include <mach/mcspi.h>
-#include <mach/omap_hsmmc.h>
-
-
-static inline void omap3_add_sram0(void)
-{
-	return omap_add_sram0(OMAP3_SRAM_BASE, 64 * SZ_1K);
-}
-
-/* the device numbering is the same as in the device tree */
-
-static inline struct device_d *omap3_add_spi(int id, resource_size_t start)
-{
-	return add_generic_device("omap3_spi", id, NULL, start, SZ_4K,
-				   IORESOURCE_MEM, NULL);
-}
-
-static inline struct device_d *omap3_add_spi1(void)
-{
-	return omap3_add_spi(1, OMAP3_MCSPI1_BASE);
-}
-
-static inline struct device_d *omap3_add_spi2(void)
-{
-	return omap3_add_spi(2, OMAP3_MCSPI2_BASE);
-}
-
-static inline struct device_d *omap3_add_spi3(void)
-{
-	return omap3_add_spi(3, OMAP3_MCSPI3_BASE);
-}
-
-static inline struct device_d *omap3_add_spi4(void)
-{
-	return omap3_add_spi(4, OMAP3_MCSPI4_BASE);
-}
-
-static inline struct device_d *omap3_add_uart1(void)
-{
-	return omap_add_uart(0, OMAP3_UART1_BASE);
-}
-
-static inline struct device_d *omap3_add_uart2(void)
-{
-	return omap_add_uart(1, OMAP3_UART2_BASE);
-}
-
-static inline struct device_d *omap3_add_uart3(void)
-{
-	return omap_add_uart(2, OMAP3_UART3_BASE);
-}
-
-static inline struct device_d *omap3_add_mmc1(struct omap_hsmmc_platform_data *pdata)
-{
-	return add_generic_device("omap3-hsmmc", 0, NULL,
-			OMAP3_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap3_add_mmc2(struct omap_hsmmc_platform_data *pdata)
-{
-	return add_generic_device("omap3-hsmmc", 1, NULL,
-			OMAP3_MMC2_BASE, SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap3_add_mmc3(struct omap_hsmmc_platform_data *pdata)
-{
-	return add_generic_device("omap3-hsmmc", 2, NULL,
-			OMAP3_MMC3_BASE, SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap3_add_i2c1(void *pdata)
-{
-	return add_generic_device("i2c-omap3", 0, NULL, OMAP3_I2C1_BASE,
-			SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap3_add_i2c2(void *pdata)
-{
-	return add_generic_device("i2c-omap3", 1, NULL, OMAP3_I2C2_BASE,
-			SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap3_add_i2c3(void *pdata)
-{
-	return add_generic_device("i2c-omap3", 2, NULL, OMAP3_I2C3_BASE,
-			SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap3_add_ehci(void *pdata)
-{
-	return add_usb_ehci_device(DEVICE_ID_DYNAMIC, OMAP3_EHCI_BASE,
-					OMAP3_EHCI_BASE + 0x10, pdata);
-}
-
-#endif /* __MACH_OMAP3_DEVICES_H */
diff --git a/arch/arm/mach-omap/include/mach/omap3-generic.h b/arch/arm/mach-omap/include/mach/omap3-generic.h
deleted file mode 100644
index 177862e4b1..0000000000
--- a/arch/arm/mach-omap/include/mach/omap3-generic.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __MACH_OMAP3_GENERIC_H
-#define __MACH_OMAP3_GENERIC_H
-
-#include <linux/sizes.h>
-#include <linux/string.h>
-#include <mach/generic.h>
-#include <mach/omap3-silicon.h>
-
-static inline void omap3_save_bootinfo(uint32_t *info)
-{
-	unsigned long i = (unsigned long)info;
-
-	if (i & 0x3)
-		return;
-	if (i < OMAP3_SRAM_BASE)
-		return;
-	if (i > OMAP3_SRAM_BASE + SZ_64K)
-		return;
-
-	memcpy((void *)OMAP3_SRAM_SCRATCH_SPACE, info, 3 * sizeof(uint32_t));
-}
-
-u32 omap3_running_in_flash(void);
-u32 omap3_running_in_sram(void);
-u32 omap3_running_in_sdram(void);
-
-int omap3_init(void);
-int omap3_devices_init(void);
-
-void *omap3_xload_boot_usb(void);
-
-#endif /* __MACH_OMAP3_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/omap3-mux.h b/arch/arm/mach-omap/include/mach/omap3-mux.h
deleted file mode 100644
index a679e25567..0000000000
--- a/arch/arm/mach-omap/include/mach/omap3-mux.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/**
- * @file
- * @brief Mux Configuration Register defines for OMAP3
- *
- * This file defines the various Pin Mux registers
- * @see include/asm-arm/arch-omap/control.h
- * The @ref MUX_VAL macro uses the defines from this file
- *
- * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
- *
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _ASM_ARCH_OMAP3_MUX_H_
-#define _ASM_ARCH_OMAP3_MUX_H_
-
-/**
- * Pin Mux Enable Defines
- *
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0-7 - Mode 0-7
- *
- * @see MUX_VAL
- */
-#define IEN	(1 << 8)
-
-#define IDIS	(0 << 8)
-#define PTU	(1 << 4)
-#define PTD	(0 << 4)
-#define EN	(1 << 3)
-#define DIS	(0 << 3)
-
-#define M0	0
-#define M1	1
-#define M2	2
-#define M3	3
-#define M4	4
-#define M5	5
-#define M6	6
-#define M7	7
-
-/*
- * To get the actual address the offset has to added
- * with OMAP_CTRL_BASE to get the actual address
- */
-
-/* SDRC */
-#define CONTROL_PADCONF_SDRC_D0		0x0030
-#define CONTROL_PADCONF_SDRC_D1		0x0032
-#define CONTROL_PADCONF_SDRC_D2		0x0034
-#define CONTROL_PADCONF_SDRC_D3		0x0036
-#define CONTROL_PADCONF_SDRC_D4		0x0038
-#define CONTROL_PADCONF_SDRC_D5		0x003A
-#define CONTROL_PADCONF_SDRC_D6		0x003C
-#define CONTROL_PADCONF_SDRC_D7		0x003E
-#define CONTROL_PADCONF_SDRC_D8		0x0040
-#define CONTROL_PADCONF_SDRC_D9		0x0042
-#define CONTROL_PADCONF_SDRC_D10	0x0044
-#define CONTROL_PADCONF_SDRC_D11	0x0046
-#define CONTROL_PADCONF_SDRC_D12	0x0048
-#define CONTROL_PADCONF_SDRC_D13	0x004A
-#define CONTROL_PADCONF_SDRC_D14	0x004C
-#define CONTROL_PADCONF_SDRC_D15	0x004E
-#define CONTROL_PADCONF_SDRC_D16	0x0050
-#define CONTROL_PADCONF_SDRC_D17	0x0052
-#define CONTROL_PADCONF_SDRC_D18	0x0054
-#define CONTROL_PADCONF_SDRC_D19	0x0056
-#define CONTROL_PADCONF_SDRC_D20	0x0058
-#define CONTROL_PADCONF_SDRC_D21	0x005A
-#define CONTROL_PADCONF_SDRC_D22	0x005C
-#define CONTROL_PADCONF_SDRC_D23	0x005E
-#define CONTROL_PADCONF_SDRC_D24	0x0060
-#define CONTROL_PADCONF_SDRC_D25	0x0062
-#define CONTROL_PADCONF_SDRC_D26	0x0064
-#define CONTROL_PADCONF_SDRC_D27	0x0066
-#define CONTROL_PADCONF_SDRC_D28	0x0068
-#define CONTROL_PADCONF_SDRC_D29	0x006A
-#define CONTROL_PADCONF_SDRC_D30	0x006C
-#define CONTROL_PADCONF_SDRC_D31	0x006E
-#define CONTROL_PADCONF_SDRC_CLK	0x0070
-#define CONTROL_PADCONF_SDRC_DQS0	0x0072
-#define CONTROL_PADCONF_SDRC_DQS1	0x0074
-#define CONTROL_PADCONF_SDRC_DQS2	0x0076
-#define CONTROL_PADCONF_SDRC_DQS3	0x0078
-/* GPMC */
-#define CONTROL_PADCONF_GPMC_A1		0x007A
-#define CONTROL_PADCONF_GPMC_A2		0x007C
-#define CONTROL_PADCONF_GPMC_A3		0x007E
-#define CONTROL_PADCONF_GPMC_A4		0x0080
-#define CONTROL_PADCONF_GPMC_A5		0x0082
-#define CONTROL_PADCONF_GPMC_A6		0x0084
-#define CONTROL_PADCONF_GPMC_A7		0x0086
-#define CONTROL_PADCONF_GPMC_A8		0x0088
-#define CONTROL_PADCONF_GPMC_A9		0x008A
-#define CONTROL_PADCONF_GPMC_A10	0x008C
-#define CONTROL_PADCONF_GPMC_D0		0x008E
-#define CONTROL_PADCONF_GPMC_D1		0x0090
-#define CONTROL_PADCONF_GPMC_D2		0x0092
-#define CONTROL_PADCONF_GPMC_D3		0x0094
-#define CONTROL_PADCONF_GPMC_D4		0x0096
-#define CONTROL_PADCONF_GPMC_D5		0x0098
-#define CONTROL_PADCONF_GPMC_D6		0x009A
-#define CONTROL_PADCONF_GPMC_D7		0x009C
-#define CONTROL_PADCONF_GPMC_D8		0x009E
-#define CONTROL_PADCONF_GPMC_D9		0x00A0
-#define CONTROL_PADCONF_GPMC_D10	0x00A2
-#define CONTROL_PADCONF_GPMC_D11	0x00A4
-#define CONTROL_PADCONF_GPMC_D12	0x00A6
-#define CONTROL_PADCONF_GPMC_D13	0x00A8
-#define CONTROL_PADCONF_GPMC_D14	0x00AA
-#define CONTROL_PADCONF_GPMC_D15	0x00AC
-#define CONTROL_PADCONF_GPMC_NCS0	0x00AE
-#define CONTROL_PADCONF_GPMC_NCS1	0x00B0
-#define CONTROL_PADCONF_GPMC_NCS2	0x00B2
-#define CONTROL_PADCONF_GPMC_NCS3	0x00B4
-#define CONTROL_PADCONF_GPMC_NCS4	0x00B6
-#define CONTROL_PADCONF_GPMC_NCS5	0x00B8
-#define CONTROL_PADCONF_GPMC_NCS6	0x00BA
-#define CONTROL_PADCONF_GPMC_NCS7	0x00BC
-#define CONTROL_PADCONF_GPMC_CLK	0x00BE
-#define CONTROL_PADCONF_GPMC_NADV_ALE	0x00C0
-#define CONTROL_PADCONF_GPMC_NOE	0x00C2
-#define CONTROL_PADCONF_GPMC_NWE	0x00C4
-#define CONTROL_PADCONF_GPMC_NBE0_CLE	0x00C6
-#define CONTROL_PADCONF_GPMC_NBE1	0x00C8
-#define CONTROL_PADCONF_GPMC_NWP	0x00CA
-#define CONTROL_PADCONF_GPMC_WAIT0	0x00CC
-#define CONTROL_PADCONF_GPMC_WAIT1	0x00CE
-#define CONTROL_PADCONF_GPMC_WAIT2	0x00D0
-#define CONTROL_PADCONF_GPMC_WAIT3	0x00D2
-/* DSS */
-#define CONTROL_PADCONF_DSS_PCLK	0x00D4
-#define CONTROL_PADCONF_DSS_HSYNC	0x00D6
-#define CONTROL_PADCONF_DSS_VSYNC	0x00D8
-#define CONTROL_PADCONF_DSS_ACBIAS	0x00DA
-#define CONTROL_PADCONF_DSS_DATA0	0x00DC
-#define CONTROL_PADCONF_DSS_DATA1	0x00DE
-#define CONTROL_PADCONF_DSS_DATA2	0x00E0
-#define CONTROL_PADCONF_DSS_DATA3	0x00E2
-#define CONTROL_PADCONF_DSS_DATA4	0x00E4
-#define CONTROL_PADCONF_DSS_DATA5	0x00E6
-#define CONTROL_PADCONF_DSS_DATA6	0x00E8
-#define CONTROL_PADCONF_DSS_DATA7	0x00EA
-#define CONTROL_PADCONF_DSS_DATA8	0x00EC
-#define CONTROL_PADCONF_DSS_DATA9	0x00EE
-#define CONTROL_PADCONF_DSS_DATA10	0x00F0
-#define CONTROL_PADCONF_DSS_DATA11	0x00F2
-#define CONTROL_PADCONF_DSS_DATA12	0x00F4
-#define CONTROL_PADCONF_DSS_DATA13	0x00F6
-#define CONTROL_PADCONF_DSS_DATA14	0x00F8
-#define CONTROL_PADCONF_DSS_DATA15	0x00FA
-#define CONTROL_PADCONF_DSS_DATA16	0x00FC
-#define CONTROL_PADCONF_DSS_DATA17	0x00FE
-#define CONTROL_PADCONF_DSS_DATA18	0x0100
-#define CONTROL_PADCONF_DSS_DATA19	0x0102
-#define CONTROL_PADCONF_DSS_DATA20	0x0104
-#define CONTROL_PADCONF_DSS_DATA21	0x0106
-#define CONTROL_PADCONF_DSS_DATA22	0x0108
-#define CONTROL_PADCONF_DSS_DATA23	0x010A
-/* CAMERA */
-#define CONTROL_PADCONF_CAM_HS		0x010C
-#define CONTROL_PADCONF_CAM_VS		0x010E
-#define CONTROL_PADCONF_CAM_XCLKA	0x0110
-#define CONTROL_PADCONF_CAM_PCLK	0x0112
-#define CONTROL_PADCONF_CAM_FLD		0x0114
-#define CONTROL_PADCONF_CAM_D0		0x0116
-#define CONTROL_PADCONF_CAM_D1		0x0118
-#define CONTROL_PADCONF_CAM_D2		0x011A
-#define CONTROL_PADCONF_CAM_D3		0x011C
-#define CONTROL_PADCONF_CAM_D4		0x011E
-#define CONTROL_PADCONF_CAM_D5		0x0120
-#define CONTROL_PADCONF_CAM_D6		0x0122
-#define CONTROL_PADCONF_CAM_D7		0x0124
-#define CONTROL_PADCONF_CAM_D8		0x0126
-#define CONTROL_PADCONF_CAM_D9		0x0128
-#define CONTROL_PADCONF_CAM_D10		0x012A
-#define CONTROL_PADCONF_CAM_D11		0x012C
-#define CONTROL_PADCONF_CAM_XCLKB	0x012E
-#define CONTROL_PADCONF_CAM_WEN		0x0130
-#define CONTROL_PADCONF_CAM_STROBE	0x0132
-#define CONTROL_PADCONF_CSI2_DX0	0x0134
-#define CONTROL_PADCONF_CSI2_DY0	0x0136
-#define CONTROL_PADCONF_CSI2_DX1	0x0138
-#define CONTROL_PADCONF_CSI2_DY1	0x013A
-/* Audio Interface */
-#define CONTROL_PADCONF_MCBSP2_FSX	0x013C
-#define CONTROL_PADCONF_MCBSP2_CLKX	0x013E
-#define CONTROL_PADCONF_MCBSP2_DR	0x0140
-#define CONTROL_PADCONF_MCBSP2_DX	0x0142
-#define CONTROL_PADCONF_
-#define CONTROL_PADCONF_MMC1_CLK	0x0144
-#define CONTROL_PADCONF_MMC1_CMD	0x0146
-#define CONTROL_PADCONF_MMC1_DAT0	0x0148
-#define CONTROL_PADCONF_MMC1_DAT1	0x014A
-#define CONTROL_PADCONF_MMC1_DAT2	0x014C
-#define CONTROL_PADCONF_MMC1_DAT3	0x014E
-#define CONTROL_PADCONF_MMC1_DAT4	0x0150
-#define CONTROL_PADCONF_MMC1_DAT5	0x0152
-#define CONTROL_PADCONF_MMC1_DAT6	0x0154
-#define CONTROL_PADCONF_MMC1_DAT7	0x0156
-/* WirelesS LAN */
-#define CONTROL_PADCONF_MMC2_CLK	0x0158
-#define CONTROL_PADCONF_MMC2_CMD	0x015A
-#define CONTROL_PADCONF_MMC2_DAT0	0x015C
-#define CONTROL_PADCONF_MMC2_DAT1	0x015E
-#define CONTROL_PADCONF_MMC2_DAT2	0x0160
-#define CONTROL_PADCONF_MMC2_DAT3	0x0162
-#define CONTROL_PADCONF_MMC2_DAT4	0x0164
-#define CONTROL_PADCONF_MMC2_DAT5	0x0166
-#define CONTROL_PADCONF_MMC2_DAT6	0x0168
-#define CONTROL_PADCONF_MMC2_DAT7	0x016A
-/* Bluetooth */
-#define CONTROL_PADCONF_MCBSP3_DX	0x016C
-#define CONTROL_PADCONF_MCBSP3_DR	0x016E
-#define CONTROL_PADCONF_MCBSP3_CLKX	0x0170
-#define CONTROL_PADCONF_MCBSP3_FSX	0x0172
-#define CONTROL_PADCONF_UART2_CTS	0x0174
-#define CONTROL_PADCONF_UART2_RTS	0x0176
-#define CONTROL_PADCONF_UART2_TX	0x0178
-#define CONTROL_PADCONF_UART2_RX	0x017A
-/* Modem Interface */
-#define CONTROL_PADCONF_UART1_TX	0x017C
-#define CONTROL_PADCONF_UART1_RTS	0x017E
-#define CONTROL_PADCONF_UART1_CTS	0x0180
-#define CONTROL_PADCONF_UART1_RX	0x0182
-#define CONTROL_PADCONF_MCBSP4_CLKX	0x0184
-#define CONTROL_PADCONF_MCBSP4_DR	0x0186
-#define CONTROL_PADCONF_MCBSP4_DX	0x0188
-#define CONTROL_PADCONF_MCBSP4_FSX	0x018A
-#define CONTROL_PADCONF_MCBSP1_CLKR	0x018C
-#define CONTROL_PADCONF_MCBSP1_FSR	0x018E
-#define CONTROL_PADCONF_MCBSP1_DX	0x0190
-#define CONTROL_PADCONF_MCBSP1_DR	0x0192
-#define CONTROL_PADCONF_MCBSP_CLKS	0x0194
-#define CONTROL_PADCONF_MCBSP1_FSX	0x0196
-#define CONTROL_PADCONF_MCBSP1_CLKX	0x0198
-/* Serial Interface */
-#define CONTROL_PADCONF_UART3_CTS_RCTX	0x019A
-#define CONTROL_PADCONF_UART3_RTS_SD	0x019C
-#define CONTROL_PADCONF_UART3_RX_IRRX	0x019E
-#define CONTROL_PADCONF_UART3_TX_IRTX	0x01A0
-#define CONTROL_PADCONF_HSUSB0_CLK	0x01A2
-#define CONTROL_PADCONF_HSUSB0_STP	0x01A4
-#define CONTROL_PADCONF_HSUSB0_DIR	0x01A6
-#define CONTROL_PADCONF_HSUSB0_NXT	0x01A8
-#define CONTROL_PADCONF_HSUSB0_DATA0	0x01AA
-#define CONTROL_PADCONF_HSUSB0_DATA1	0x01AC
-#define CONTROL_PADCONF_HSUSB0_DATA2	0x01AE
-#define CONTROL_PADCONF_HSUSB0_DATA3	0x01B0
-#define CONTROL_PADCONF_HSUSB0_DATA4	0x01B2
-#define CONTROL_PADCONF_HSUSB0_DATA5	0x01B4
-#define CONTROL_PADCONF_HSUSB0_DATA6	0x01B6
-#define CONTROL_PADCONF_HSUSB0_DATA7	0x01B8
-#define CONTROL_PADCONF_I2C1_SCL	0x01BA
-#define CONTROL_PADCONF_I2C1_SDA	0x01BC
-#define CONTROL_PADCONF_I2C2_SCL	0x01BE
-#define CONTROL_PADCONF_I2C2_SDA	0x01C0
-#define CONTROL_PADCONF_I2C3_SCL	0x01C2
-#define CONTROL_PADCONF_I2C3_SDA	0x01C4
-#define CONTROL_PADCONF_I2C4_SCL	0x0A00
-#define CONTROL_PADCONF_I2C4_SDA	0x0A02
-#define CONTROL_PADCONF_HDQ_SIO		0x01C6
-#define CONTROL_PADCONF_MCSPI1_CLK	0x01C8
-#define CONTROL_PADCONF_MCSPI1_SIMO	0x01CA
-#define CONTROL_PADCONF_MCSPI1_SOMI	0x01CC
-#define CONTROL_PADCONF_MCSPI1_CS0	0x01CE
-#define CONTROL_PADCONF_MCSPI1_CS1	0x01D0
-#define CONTROL_PADCONF_MCSPI1_CS2	0x01D2
-#define CONTROL_PADCONF_MCSPI1_CS3	0x01D4
-#define CONTROL_PADCONF_MCSPI2_CLK	0x01D6
-#define CONTROL_PADCONF_MCSPI2_SIMO	0x01D8
-#define CONTROL_PADCONF_MCSPI2_SOMI	0x01DA
-#define CONTROL_PADCONF_MCSPI2_CS0	0x01DC
-#define CONTROL_PADCONF_MCSPI2_CS1	0x01DE
-/* Control and debug */
-#define CONTROL_PADCONF_SYS_32K		0x0A04
-#define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
-#define CONTROL_PADCONF_SYS_NIRQ	0x01E0
-#define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
-#define CONTROL_PADCONF_SYS_BOOT1	0x0A0C
-#define CONTROL_PADCONF_SYS_BOOT2	0x0A0E
-#define CONTROL_PADCONF_SYS_BOOT3	0x0A10
-#define CONTROL_PADCONF_SYS_BOOT4	0x0A12
-#define CONTROL_PADCONF_SYS_BOOT5	0x0A14
-#define CONTROL_PADCONF_SYS_BOOT6	0x0A16
-#define CONTROL_PADCONF_SYS_OFF_MODE	0x0A18
-#define CONTROL_PADCONF_SYS_CLKOUT1	0x0A1A
-#define CONTROL_PADCONF_SYS_CLKOUT2	0x01E2
-#define CONTROL_PADCONF_JTAG_NTRST	0x0A1C
-#define CONTROL_PADCONF_JTAG_TCK	0x0A1E
-#define CONTROL_PADCONF_JTAG_TMS	0x0A20
-#define CONTROL_PADCONF_JTAG_TDI	0x0A22
-#define CONTROL_PADCONF_JTAG_EMU0	0x0A24
-#define CONTROL_PADCONF_JTAG_EMU1	0x0A26
-#define CONTROL_PADCONF_ETK_CLK		0x0A28
-#define CONTROL_PADCONF_ETK_CTL		0x0A2A
-#define CONTROL_PADCONF_ETK_D0		0x0A2C
-#define CONTROL_PADCONF_ETK_D1		0x0A2E
-#define CONTROL_PADCONF_ETK_D2		0x0A30
-#define CONTROL_PADCONF_ETK_D3		0x0A32
-#define CONTROL_PADCONF_ETK_D4		0x0A34
-#define CONTROL_PADCONF_ETK_D5		0x0A36
-#define CONTROL_PADCONF_ETK_D6		0x0A38
-#define CONTROL_PADCONF_ETK_D7		0x0A3A
-#define CONTROL_PADCONF_ETK_D8		0x0A3C
-#define CONTROL_PADCONF_ETK_D9		0x0A3E
-#define CONTROL_PADCONF_ETK_D10		0x0A40
-#define CONTROL_PADCONF_ETK_D11		0x0A42
-#define CONTROL_PADCONF_ETK_D12		0x0A44
-#define CONTROL_PADCONF_ETK_D13		0x0A46
-#define CONTROL_PADCONF_ETK_D14		0x0A48
-#define CONTROL_PADCONF_ETK_D15		0x0A4A
-#define CONTROL_PADCONF_ETK_CLK_ES2	0x05D8
-#define CONTROL_PADCONF_ETK_CTL_ES2	0x05DA
-#define CONTROL_PADCONF_ETK_D0_ES2	0x05DC
-#define CONTROL_PADCONF_ETK_D1_ES2	0x05DE
-#define CONTROL_PADCONF_ETK_D2_ES2	0x05E0
-#define CONTROL_PADCONF_ETK_D3_ES2	0x05E2
-#define CONTROL_PADCONF_ETK_D4_ES2	0x05E4
-#define CONTROL_PADCONF_ETK_D5_ES2	0x05E6
-#define CONTROL_PADCONF_ETK_D6_ES2	0x05E8
-#define CONTROL_PADCONF_ETK_D7_ES2	0x05EA
-#define CONTROL_PADCONF_ETK_D8_ES2	0x05EC
-#define CONTROL_PADCONF_ETK_D9_ES2	0x05EE
-#define CONTROL_PADCONF_ETK_D10_ES2	0x05F0
-#define CONTROL_PADCONF_ETK_D11_ES2	0x05F2
-#define CONTROL_PADCONF_ETK_D12_ES2	0x05F4
-#define CONTROL_PADCONF_ETK_D13_ES2	0x05F6
-#define CONTROL_PADCONF_ETK_D14_ES2	0x05F8
-#define CONTROL_PADCONF_ETK_D15_ES2	0x05FA
-/* Die to die */
-#define CONTROL_PADCONF_D2D_MCAD0	0x01E4
-#define CONTROL_PADCONF_D2D_MCAD1	0x01E6
-#define CONTROL_PADCONF_D2D_MCAD2	0x01E8
-#define CONTROL_PADCONF_D2D_MCAD3	0x01EA
-#define CONTROL_PADCONF_D2D_MCAD4	0x01EC
-#define CONTROL_PADCONF_D2D_MCAD5	0x01EE
-#define CONTROL_PADCONF_D2D_MCAD6	0x01F0
-#define CONTROL_PADCONF_D2D_MCAD7	0x01F2
-#define CONTROL_PADCONF_D2D_MCAD8	0x01F4
-#define CONTROL_PADCONF_D2D_MCAD9	0x01F6
-#define CONTROL_PADCONF_D2D_MCAD10	0x01F8
-#define CONTROL_PADCONF_D2D_MCAD11	0x01FA
-#define CONTROL_PADCONF_D2D_MCAD12	0x01FC
-#define CONTROL_PADCONF_D2D_MCAD13	0x01FE
-#define CONTROL_PADCONF_D2D_MCAD14	0x0200
-#define CONTROL_PADCONF_D2D_MCAD15	0x0202
-#define CONTROL_PADCONF_D2D_MCAD16	0x0204
-#define CONTROL_PADCONF_D2D_MCAD17	0x0206
-#define CONTROL_PADCONF_D2D_MCAD18	0x0208
-#define CONTROL_PADCONF_D2D_MCAD19	0x020A
-#define CONTROL_PADCONF_D2D_MCAD20	0x020C
-#define CONTROL_PADCONF_D2D_MCAD21	0x020E
-#define CONTROL_PADCONF_D2D_MCAD22	0x0210
-#define CONTROL_PADCONF_D2D_MCAD23	0x0212
-#define CONTROL_PADCONF_D2D_MCAD24	0x0214
-#define CONTROL_PADCONF_D2D_MCAD25	0x0216
-#define CONTROL_PADCONF_D2D_MCAD26	0x0218
-#define CONTROL_PADCONF_D2D_MCAD27	0x021A
-#define CONTROL_PADCONF_D2D_MCAD28	0x021C
-#define CONTROL_PADCONF_D2D_MCAD29	0x021E
-#define CONTROL_PADCONF_D2D_MCAD30	0x0220
-#define CONTROL_PADCONF_D2D_MCAD31	0x0222
-#define CONTROL_PADCONF_D2D_MCAD32	0x0224
-#define CONTROL_PADCONF_D2D_MCAD33	0x0226
-#define CONTROL_PADCONF_D2D_MCAD34	0x0228
-#define CONTROL_PADCONF_D2D_MCAD35	0x022A
-#define CONTROL_PADCONF_D2D_MCAD36	0x022C
-#define CONTROL_PADCONF_D2D_CLK26MI	0x022E
-#define CONTROL_PADCONF_D2D_NRESPWRON	0x0230
-#define CONTROL_PADCONF_D2D_NRESWARM	0x0232
-#define CONTROL_PADCONF_D2D_ARM9NIRQ	0x0234
-#define CONTROL_PADCONF_D2D_UMA2P6FIQ	0x0236
-#define CONTROL_PADCONF_D2D_SPINT	0x0238
-#define CONTROL_PADCONF_D2D_FRINT	0x023A
-#define CONTROL_PADCONF_D2D_DMAREQ0	0x023C
-#define CONTROL_PADCONF_D2D_DMAREQ1	0x023E
-#define CONTROL_PADCONF_D2D_DMAREQ2	0x0240
-#define CONTROL_PADCONF_D2D_DMAREQ3	0x0242
-#define CONTROL_PADCONF_D2D_N3GTRST	0x0244
-#define CONTROL_PADCONF_D2D_N3GTDI	0x0246
-#define CONTROL_PADCONF_D2D_N3GTDO	0x0248
-#define CONTROL_PADCONF_D2D_N3GTMS	0x024A
-#define CONTROL_PADCONF_D2D_N3GTCK	0x024C
-#define CONTROL_PADCONF_D2D_N3GRTCK	0x024E
-#define CONTROL_PADCONF_D2D_MSTDBY	0x0250
-#define CONTROL_PADCONF_D2D_SWAKEUP	0x0A4C
-#define CONTROL_PADCONF_D2D_IDLEREQ	0x0252
-#define CONTROL_PADCONF_D2D_IDLEACK	0x0254
-#define CONTROL_PADCONF_D2D_MWRITE	0x0256
-#define CONTROL_PADCONF_D2D_SWRITE	0x0258
-#define CONTROL_PADCONF_D2D_MREAD	0x025A
-#define CONTROL_PADCONF_D2D_SREAD	0x025C
-#define CONTROL_PADCONF_D2D_MBUSFLAG	0x025E
-#define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
-#define CONTROL_PADCONF_SDRC_CKE0	0x0262
-#define CONTROL_PADCONF_SDRC_CKE1	0x0264
-
-/* AM3517 specific mux configuration */
-#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
-/* CCDC */
-#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
-#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
-#define CONTROL_PADCONF_CCDC_HD		0x01E8
-#define CONTROL_PADCONF_CCDC_VD		0x01EA
-#define CONTROL_PADCONF_CCDC_WEN	0x01EC
-#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
-#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
-#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
-#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
-#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
-#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
-#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
-#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
-/* RMII */
-#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
-#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
-#define CONTROL_PADCONF_RMII_RXD0	0x0202
-#define CONTROL_PADCONF_RMII_RXD1	0x0204
-#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
-#define CONTROL_PADCONF_RMII_RXER	0x0208
-#define CONTROL_PADCONF_RMII_TXD0	0x020A
-#define CONTROL_PADCONF_RMII_TXD1	0x020C
-#define CONTROL_PADCONF_RMII_TXEN	0x020E
-#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
-#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
-/* CAN */
-#define CONTROL_PADCONF_HECC1_TXD	0x0214
-#define CONTROL_PADCONF_HECC1_RXD	0x0216
-
-#define CONTROL_PADCONF_SYS_BOOT7	0x0218
-#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
-#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
-#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
-#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
-#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
-#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
-#define CONTROL_PADCONF_SYS_BOOT8	0x0226
-
-/* AM/DM37xx specific */
-#define CONTROL_PADCONF_GPIO127		0x0A54
-#define CONTROL_PADCONF_GPIO126		0x0A56
-#define CONTROL_PADCONF_GPIO128		0x0A58
-#define CONTROL_PADCONF_GPIO129		0x0A5A
-
-#endif
diff --git a/arch/arm/mach-omap/include/mach/omap3-silicon.h b/arch/arm/mach-omap/include/mach/omap3-silicon.h
deleted file mode 100644
index b4de045652..0000000000
--- a/arch/arm/mach-omap/include/mach/omap3-silicon.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * @file
- * @brief This file contains the processor specific definitions of
- * the TI OMAP34XX. For more info on OMAP34XX,
- * See http://focus.ti.com/pdfs/wtbu/swpu114g.pdf
- *
- * OMAP34XX base address defines go here.
- *
- * Originally from Linux kernel:
- * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
- * include/asm-arm/arch-omap/omap3-silicon.h
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * Copyright (C) 2007 Texas Instruments, <www.ti.com>
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_OMAP3_H
-#define __ASM_ARCH_OMAP3_H
-
-/* PLEASE PLACE ONLY BASE DEFINES HERE */
-
-/** OMAP Internal Bus Base addresses */
-#define OMAP3_L4_CORE_BASE	0x48000000
-#define OMAP3_INTC_BASE		0x48200000
-#define OMAP3_L4_WKUP_BASE	0x48300000
-#define OMAP3_L4_PER_BASE	0x49000000
-#define OMAP3_L4_EMU_BASE	0x54000000
-#define OMAP3_SGX_BASE		0x50000000
-#define OMAP3_IVA_BASE		0x5C000000
-#define OMAP3_SMX_APE_BASE	0x68000000
-#define OMAP3_SMS_BASE		0x6C000000
-#define OMAP3_SDRC_BASE		0x6D000000
-#define OMAP3_GPMC_BASE		0x6E000000
-
-/** Peripheral Base Addresses */
-#define OMAP3_CTRL_BASE		(OMAP3_L4_CORE_BASE + 0x02000)
-#define OMAP3_CM_BASE		(OMAP3_L4_CORE_BASE + 0x04000)
-#define OMAP3_PRM_BASE		(OMAP3_L4_WKUP_BASE + 0x06000)
-
-#define OMAP3_UART1_BASE	(OMAP3_L4_CORE_BASE + 0x6A000)
-#define OMAP3_UART2_BASE	(OMAP3_L4_CORE_BASE + 0x6C000)
-#define OMAP3_UART3_BASE	(OMAP3_L4_PER_BASE + 0x20000)
-
-#define OMAP3_I2C1_BASE		(OMAP3_L4_CORE_BASE + 0x70000)
-#define OMAP3_I2C2_BASE		(OMAP3_L4_CORE_BASE + 0x72000)
-#define OMAP3_I2C3_BASE		(OMAP3_L4_CORE_BASE + 0x60000)
-
-#define OMAP3_GPTIMER1_BASE	(OMAP3_L4_WKUP_BASE + 0x18000)
-#define OMAP3_GPTIMER2_BASE	(OMAP3_L4_PER_BASE + 0x32000)
-#define OMAP3_GPTIMER3_BASE	(OMAP3_L4_PER_BASE + 0x34000)
-#define OMAP3_GPTIMER4_BASE	(OMAP3_L4_PER_BASE + 0x36000)
-#define OMAP3_GPTIMER5_BASE	(OMAP3_L4_PER_BASE + 0x38000)
-#define OMAP3_GPTIMER6_BASE	(OMAP3_L4_PER_BASE + 0x3A000)
-#define OMAP3_GPTIMER7_BASE	(OMAP3_L4_PER_BASE + 0x3C000)
-#define OMAP3_GPTIMER8_BASE	(OMAP3_L4_PER_BASE + 0x3E000)
-#define OMAP3_GPTIMER9_BASE	(OMAP3_L4_PER_BASE + 0x40000)
-#define OMAP3_GPTIMER10_BASE	(OMAP3_L4_CORE_BASE + 0x86000)
-#define OMAP3_GPTIMER11_BASE	(OMAP3_L4_CORE_BASE + 0x88000)
-
-#define OMAP3_WDTIMER2_BASE	(OMAP3_L4_WKUP_BASE + 0x14000)
-#define OMAP3_WDTIMER3_BASE	(OMAP3_L4_PER_BASE + 0x30000)
-
-#define OMAP3_32KTIMER_BASE	(OMAP3_L4_WKUP_BASE + 0x20000)
-
-#define OMAP3_MMC1_BASE		(OMAP3_L4_CORE_BASE + 0x9C000)
-#define OMAP3_MMC2_BASE		(OMAP3_L4_CORE_BASE + 0xB4000)
-#define OMAP3_MMC3_BASE		(OMAP3_L4_CORE_BASE + 0xAD000)
-
-#define OMAP3_MUSB0_BASE	(OMAP3_L4_CORE_BASE + 0xAB000)
-
-#define OMAP3_GPIO1_BASE	(OMAP3_L4_WKUP_BASE + 0x10000)
-#define OMAP3_GPIO2_BASE	(OMAP3_L4_PER_BASE + 0x50000)
-#define OMAP3_GPIO3_BASE	(OMAP3_L4_PER_BASE + 0x52000)
-#define OMAP3_GPIO4_BASE	(OMAP3_L4_PER_BASE + 0x54000)
-#define OMAP3_GPIO5_BASE	(OMAP3_L4_PER_BASE + 0x56000)
-#define OMAP3_GPIO6_BASE	(OMAP3_L4_PER_BASE + 0x58000)
-
-/** MPU WDT Definition */
-#define OMAP3_MPU_WDTIMER_BASE	OMAP3_WDTIMER2_BASE
-
-#define OMAP3_HSUSB_OTG_BASE    (OMAP3_L4_CORE_BASE + 0xAB000)
-#define OMAP3_USBTLL_BASE       (OMAP3_L4_CORE_BASE + 0x62000)
-#define OMAP3_UHH_CONFIG_BASE   (OMAP3_L4_CORE_BASE + 0x64000)
-#define OMAP3_OHCI_BASE         (OMAP3_L4_CORE_BASE + 0x64400)
-#define OMAP3_EHCI_BASE         (OMAP3_L4_CORE_BASE + 0x64800)
-
-/** Interrupt Vector base address */
-#define OMAP3_SRAM_BASE		0x40200000
-#define OMAP3_SRAM_SCRATCH_SPACE	0x4020f000 /* start of public stack */
-#define OMAP3_SRAM_INTVECT	0x4020F800
-#define OMAP3_SRAM_INTVECT_COPYSIZE	0x64
-
-/** Gives the silicon revision */
-#define OMAP3_TAP_BASE		(OMAP3_L4_WKUP_BASE + 0xA000)
-#define OMAP3_IDCODE_REG	(OMAP3_TAP_BASE + 0x204)
-#define OMAP3_DIE_ID_0		(OMAP3_TAP_BASE + 0x218)
-#define OMAP3_DIE_ID_1		(OMAP3_TAP_BASE + 0x21c)
-#define OMAP3_DIE_ID_2		(OMAP3_TAP_BASE + 0x220)
-#define OMAP3_DIE_ID_3		(OMAP3_TAP_BASE + 0x224)
-
-/** Masks to extract information from ID code register */
-#define IDCODE_HAWKEYE_MASK	0x0FFFF000
-#define IDCODE_VERSION_MASK	0xF0000000
-
- #define get_hawkeye(v)		(((v) & IDCODE_HAWKEYE_MASK) >> 12)
- #define get_version(v)		(((v) & IDCODE_VERSION_MASK) >> 28)
-
-#define HAWKEYE_ES1		0x0B6D6000
-#define HAWKEYE_ES2		0x0B7AE000
-#define HAWKEYE_ES2_1		0x1B7AE000
-
-#define DEVICE_MASK		((0x1 << 8)|(0x1 << 9)|(0x1 << 10))
-
-#define OMAP_SDRC_CS0		0x80000000
-#define OMAP_SDRC_CS1		0xA0000000
-
-/* PRM */
-#define OMAP3_PRM_RSTCTRL_RESET	0x04
-
-/*
- * ROM code API related flags
- */
-#define OMAP3_GP_ROMCODE_API_L2_INVAL		1
-#define OMAP3_GP_ROMCODE_API_WRITE_ACR		3
-
-/* If Architecture specific init functions are present */
-#ifndef __ASSEMBLY__
-void omap3_core_init(void);
-void omap3_gp_romcode_call(u32 service_id, u32 parameter);
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARCH_OMAP3_H */
diff --git a/arch/arm/mach-omap/include/mach/omap3-smx.h b/arch/arm/mach-omap/include/mach/omap3-smx.h
deleted file mode 100644
index fb444b8cf3..0000000000
--- a/arch/arm/mach-omap/include/mach/omap3-smx.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/**
- * @file
- * @brief This file contains the SMX specific register definitions
- *
- * Originally from Linux kernel:
- * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
- * include/asm-arm/arch-omap/omap34xx.h
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * Copyright (C) 2007 Texas Instruments, <www.ti.com>
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_OMAP_SMX_H
-#define __ASM_ARCH_OMAP_SMX_H
-
-/* SMX-APE */
-#define PM_RT_APE_BASE_ADDR_ARM		(OMAP3_SMX_APE_BASE + 0x10000)
-#define PM_GPMC_BASE_ADDR_ARM		(OMAP3_SMX_APE_BASE + 0x12400)
-#define PM_OCM_RAM_BASE_ADDR_ARM	(OMAP3_SMX_APE_BASE + 0x12800)
-#define PM_OCM_ROM_BASE_ADDR_ARM	(OMAP3_SMX_APE_BASE + 0x12C00)
-#define PM_IVA2_BASE_ADDR_ARM		(OMAP3_SMX_APE_BASE + 0x14000)
-
-#define RT_REQ_INFO_PERMISSION_1	(PM_RT_APE_BASE_ADDR_ARM + 0x68)
-#define RT_READ_PERMISSION_0		(PM_RT_APE_BASE_ADDR_ARM + 0x50)
-#define RT_WRITE_PERMISSION_0		(PM_RT_APE_BASE_ADDR_ARM + 0x58)
-#define RT_ADDR_MATCH_1			(PM_RT_APE_BASE_ADDR_ARM + 0x60)
-
-#define GPMC_REQ_INFO_PERMISSION_0	(PM_GPMC_BASE_ADDR_ARM + 0x48)
-#define GPMC_READ_PERMISSION_0		(PM_GPMC_BASE_ADDR_ARM + 0x50)
-#define GPMC_WRITE_PERMISSION_0		(PM_GPMC_BASE_ADDR_ARM + 0x58)
-
-#define OCM_REQ_INFO_PERMISSION_0	(PM_OCM_RAM_BASE_ADDR_ARM + 0x48)
-#define OCM_READ_PERMISSION_0		(PM_OCM_RAM_BASE_ADDR_ARM + 0x50)
-#define OCM_WRITE_PERMISSION_0		(PM_OCM_RAM_BASE_ADDR_ARM + 0x58)
-#define OCM_ADDR_MATCH_2		(PM_OCM_RAM_BASE_ADDR_ARM + 0x80)
-
-/* IVA2 */
-#define IVA2_REQ_INFO_PERMISSION_0	(PM_IVA2_BASE_ADDR_ARM + 0x48)
-#define IVA2_READ_PERMISSION_0		(PM_IVA2_BASE_ADDR_ARM + 0x50)
-#define IVA2_WRITE_PERMISSION_0		(PM_IVA2_BASE_ADDR_ARM + 0x58)
-
-/* SMS */
-#define SMS_SYSCONFIG			(OMAP3_SMS_BASE + 0x10)
-#define SMS_RG_ATT0			(OMAP3_SMS_BASE + 0x48)
-#define SMS_CLASS_ARB0			(OMAP3_SMS_BASE + 0xD0)
-#define BURSTCOMPLETE_GROUP7		(0x1 << 31)
-
-#endif /* __ASM_ARCH_OMAP_SMX_H */
diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
deleted file mode 100644
index 8f49aa3761..0000000000
--- a/arch/arm/mach-omap/include/mach/omap4-clock.h
+++ /dev/null
@@ -1,345 +0,0 @@
-#ifndef __MACH_OMAP4_CLOCK_H
-#define __MACH_OMAP4_CLOCK_H
-
-/* PRCM */
-#define CM_SYS_CLKSEL				0x4a306110
-
-#define CM_SYS_CLKSEL_19M2		0x4
-#define CM_SYS_CLKSEL_38M4		0x7
-
-/* PRM.CKGEN module registers */
-#define CM_ABE_PLL_REF_CLKSEL		0x4a30610c
-
-
-/* PRM.WKUP_CM module registers */
-#define CM_WKUP_CLKSTCTRL		0x4a307800
-#define CM_WKUP_L4WKUP_CLKCTRL		0x4a307820
-#define CM_WKUP_WDT1_CLKCTRL		0x4a307828
-#define CM_WKUP_WDT2_CLKCTRL		0x4a307830
-#define CM_WKUP_GPIO1_CLKCTRL		0x4a307838
-#define CM_WKUP_TIMER1_CLKCTRL		0x4a307840
-#define CM_WKUP_TIMER12_CLKCTRL		0x4a307848
-#define CM_WKUP_SYNCTIMER_CLKCTRL	0x4a307850
-#define CM_WKUP_USIM_CLKCTRL		0x4a307858
-#define CM_WKUP_SARRAM_CLKCTRL		0x4a307860
-#define CM_WKUP_KEYBOARD_CLKCTRL	0x4a307878
-#define CM_WKUP_RTC_CLKCTRL		0x4a307880
-#define CM_WKUP_BANDGAP_CLKCTRL		0x4a307888
-
-/* CM1.CKGEN module registers */
-#define CM_CLKSEL_CORE				0x4a004100
-#define CM_CLKSEL_ABE				0x4a004108
-#define CM_DLL_CTRL				0x4a004110
-#define CM_CLKMODE_DPLL_CORE			0x4a004120
-#define CM_IDLEST_DPLL_CORE			0x4a004124
-#define CM_AUTOIDLE_DPLL_CORE			0x4a004128
-#define CM_CLKSEL_DPLL_CORE			0x4a00412c
-#define CM_DIV_M2_DPLL_CORE			0x4a004130
-#define CM_DIV_M3_DPLL_CORE			0x4a004134
-#define CM_DIV_M4_DPLL_CORE			0x4a004138
-#define CM_DIV_M5_DPLL_CORE			0x4a00413c
-#define CM_DIV_M6_DPLL_CORE			0x4a004140
-#define CM_DIV_M7_DPLL_CORE			0x4a004144
-#define CM_SSC_DELTAMSTEP_DPLL_CORE		0x4a004148
-#define CM_SSC_MODFREQDIV_DPLL_CORE		0x4a00414c
-#define CM_EMU_OVERRIDE_DPLL_CORE		0x4a004150
-#define CM_CLKMODE_DPLL_MPU			0x4a004160
-#define CM_IDLEST_DPLL_MPU			0x4a004164
-#define CM_AUTOIDLE_DPLL_MPU			0x4a004168
-#define CM_CLKSEL_DPLL_MPU			0x4a00416c
-#define CM_DIV_M2_DPLL_MPU			0x4a004170
-#define CM_SSC_DELTAMSTEP_DPLL_MPU		0x4a004188
-#define CM_SSC_MODFREQDIV_DPLL_MPU		0x4a00418c
-#define CM_BYPCLK_DPLL_MPU			0x4a00419c
-#define CM_CLKMODE_DPLL_IVA			0x4a0041a0
-#define CM_IDLEST_DPLL_IVA			0x4a0041a4
-#define CM_AUTOIDLE_DPLL_IVA			0x4a0041a8
-#define CM_CLKSEL_DPLL_IVA			0x4a0041ac
-#define CM_DIV_M4_DPLL_IVA			0x4a0041b8
-#define CM_DIV_M5_DPLL_IVA			0x4a0041bc
-#define CM_SSC_DELTAMSTEP_DPLL_IVA		0x4a0041c8
-#define CM_SSC_MODFREQDIV_DPLL_IVA		0x4a0041cc
-#define CM_BYPCLK_DPLL_IVA			0x4a0041dc
-#define CM_CLKMODE_DPLL_ABE			0x4a0041e0
-#define CM_IDLEST_DPLL_ABE			0x4a0041e4
-#define CM_AUTOIDLE_DPLL_ABE			0x4a0041e8
-#define CM_CLKSEL_DPLL_ABE			0x4a0041ec
-#define CM_DIV_M2_DPLL_ABE			0x4a0041f0
-#define CM_DIV_M3_DPLL_ABE			0x4a0041f4
-#define CM_SSC_DELTAMSTEP_DPLL_ABE		0x4a004208
-#define CM_SSC_MODFREQDIV_DPLL_ABE		0x4a00420c
-#define CM_CLKMODE_DPLL_DDRPHY			0x4a004220
-#define CM_IDLEST_DPLL_DDRPHY			0x4a004224
-#define CM_AUTOIDLE_DPLL_DDRPHY			0x4a004228
-#define CM_CLKSEL_DPLL_DDRPHY			0x4a00422c
-#define CM_DIV_M2_DPLL_DDRPHY			0x4a004230
-#define CM_DIV_M4_DPLL_DDRPHY			0x4a004238
-#define CM_DIV_M5_DPLL_DDRPHY			0x4a00423c
-#define CM_DIV_M6_DPLL_DDRPHY			0x4a004240
-#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY		0x4a004248
-
-/* CM1.ABE register offsets */
-#define CM1_ABE_CLKSTCTRL		0x4a004500
-#define CM1_ABE_L4ABE_CLKCTRL		0x4a004520
-#define CM1_ABE_AESS_CLKCTRL		0x4a004528
-#define CM1_ABE_PDM_CLKCTRL		0x4a004530
-#define CM1_ABE_DMIC_CLKCTRL		0x4a004538
-#define CM1_ABE_MCASP_CLKCTRL		0x4a004540
-#define CM1_ABE_MCBSP1_CLKCTRL		0x4a004548
-#define CM1_ABE_MCBSP2_CLKCTRL		0x4a004550
-#define CM1_ABE_MCBSP3_CLKCTRL		0x4a004558
-#define CM1_ABE_SLIMBUS_CLKCTRL		0x4a004560
-#define CM1_ABE_TIMER5_CLKCTRL		0x4a004568
-#define CM1_ABE_TIMER6_CLKCTRL		0x4a004570
-#define CM1_ABE_TIMER7_CLKCTRL		0x4a004578
-#define CM1_ABE_TIMER8_CLKCTRL		0x4a004580
-#define CM1_ABE_WDT3_CLKCTRL		0x4a004588
-
-/* CM1.DSP register offsets */
-#define DSP_CLKSTCTRL			0x4a004400
-#define	DSP_DSP_CLKCTRL			0x4a004420
-
-/* CM2.CKGEN module registers */
-#define CM_CLKSEL_DUCATI_ISS_ROOT		0x4a008100
-#define CM_CLKSEL_USB_60MHz			0x4a008104
-#define CM_SCALE_FCLK				0x4a008108
-#define CM_CORE_DVFS_PERF1			0x4a008110
-#define CM_CORE_DVFS_PERF2			0x4a008114
-#define CM_CORE_DVFS_PERF3			0x4a008118
-#define CM_CORE_DVFS_PERF4			0x4a00811c
-#define CM_CORE_DVFS_CURRENT			0x4a008124
-#define CM_IVA_DVFS_PERF_TESLA			0x4a008128
-#define CM_IVA_DVFS_PERF_IVAHD			0x4a00812c
-#define CM_IVA_DVFS_PERF_ABE			0x4a008130
-#define CM_IVA_DVFS_CURRENT			0x4a008138
-#define CM_CLKMODE_DPLL_PER			0x4a008140
-#define CM_IDLEST_DPLL_PER			0x4a008144
-#define CM_AUTOIDLE_DPLL_PER			0x4a008148
-#define CM_CLKSEL_DPLL_PER			0x4a00814c
-#define CM_DIV_M2_DPLL_PER			0x4a008150
-#define CM_DIV_M3_DPLL_PER			0x4a008154
-#define CM_DIV_M4_DPLL_PER			0x4a008158
-#define CM_DIV_M5_DPLL_PER			0x4a00815c
-#define CM_DIV_M6_DPLL_PER			0x4a008160
-#define CM_DIV_M7_DPLL_PER			0x4a008164
-#define CM_SSC_DELTAMSTEP_DPLL_PER		0x4a008168
-#define CM_SSC_MODFREQDIV_DPLL_PER		0x4a00816c
-#define CM_EMU_OVERRIDE_DPLL_PER		0x4a008170
-#define CM_CLKMODE_DPLL_USB			0x4a008180
-#define CM_IDLEST_DPLL_USB			0x4a008184
-#define CM_AUTOIDLE_DPLL_USB			0x4a008188
-#define CM_CLKSEL_DPLL_USB			0x4a00818c
-#define CM_DIV_M2_DPLL_USB			0x4a008190
-#define CM_SSC_DELTAMSTEP_DPLL_USB		0x4a0081a8
-#define CM_SSC_MODFREQDIV_DPLL_USB		0x4a0081ac
-#define CM_CLKDCOLDO_DPLL_USB			0x4a0081b4
-#define CM_CLKMODE_DPLL_UNIPRO			0x4a0081c0
-#define CM_IDLEST_DPLL_UNIPRO			0x4a0081c4
-#define CM_AUTOIDLE_DPLL_UNIPRO			0x4a0081c8
-#define CM_CLKSEL_DPLL_UNIPRO			0x4a0081cc
-#define CM_DIV_M2_DPLL_UNIPRO			0x4a0081d0
-#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO		0x4a0081e8
-#define CM_SSC_MODFREQDIV_DPLL_UNIPRO		0x4a0081ec
-
-/* CM2.CORE module registers */
-#define CM_L3_1_CLKSTCTRL		0x4a008700
-#define CM_L3_1_DYNAMICDEP		0x4a008708
-#define CM_L3_1_L3_1_CLKCTRL		0x4a008720
-#define CM_L3_2_CLKSTCTRL		0x4a008800
-#define CM_L3_2_DYNAMICDEP		0x4a008808
-#define CM_L3_2_L3_2_CLKCTRL		0x4a008820
-#define CM_L3_2_GPMC_CLKCTRL		0x4a008828
-#define CM_L3_2_OCMC_RAM_CLKCTRL	0x4a008830
-#define CM_DUCATI_CLKSTCTRL		0x4a008900
-#define CM_DUCATI_STATICDEP		0x4a008904
-#define CM_DUCATI_DYNAMICDEP		0x4a008908
-#define CM_DUCATI_DUCATI_CLKCTRL	0x4a008920
-#define CM_SDMA_CLKSTCTRL		0x4a008a00
-#define CM_SDMA_STATICDEP		0x4a008a04
-#define CM_SDMA_DYNAMICDEP		0x4a008a08
-#define CM_SDMA_SDMA_CLKCTRL		0x4a008a20
-#define CM_MEMIF_CLKSTCTRL		0x4a008b00
-#define CM_MEMIF_DMM_CLKCTRL		0x4a008b20
-#define CM_MEMIF_EMIF_FW_CLKCTRL	0x4a008b28
-#define CM_MEMIF_EMIF_1_CLKCTRL		0x4a008b30
-#define CM_MEMIF_EMIF_2_CLKCTRL		0x4a008b38
-#define CM_MEMIF_DLL_CLKCTRL		0x4a008b40
-#define CM_MEMIF_EMIF_H1_CLKCTRL	0x4a008b50
-#define CM_MEMIF_EMIF_H2_CLKCTRL	0x4a008b58
-#define CM_MEMIF_DLL_H_CLKCTRL		0x4a008b60
-#define CM_D2D_CLKSTCTRL		0x4a008c00
-#define CM_D2D_STATICDEP		0x4a008c04
-#define CM_D2D_DYNAMICDEP		0x4a008c08
-#define CM_D2D_SAD2D_CLKCTRL		0x4a008c20
-#define CM_D2D_MODEM_ICR_CLKCTRL	0x4a008c28
-#define CM_D2D_SAD2D_FW_CLKCTRL		0x4a008c30
-#define CM_L4CFG_CLKSTCTRL		0x4a008d00
-#define CM_L4CFG_DYNAMICDEP		0x4a008d08
-#define CM_L4CFG_L4_CFG_CLKCTRL		0x4a008d20
-#define CM_L4CFG_HW_SEM_CLKCTRL		0x4a008d28
-#define CM_L4CFG_MAILBOX_CLKCTRL	0x4a008d30
-#define CM_L4CFG_SAR_ROM_CLKCTRL	0x4a008d38
-#define CM_L3INSTR_CLKSTCTRL		0x4a008e00
-#define CM_L3INSTR_L3_3_CLKCTRL		0x4a008e20
-#define CM_L3INSTR_L3_INSTR_CLKCTRL	0x4a008e28
-#define CM_L3INSTR_OCP_WP1_CLKCTRL	0x4a008e40
-
-/* CM2.L4PER register offsets */
-#define CM_L4PER_CLKSTCTRL		0x4a009400
-#define CM_L4PER_DYNAMICDEP		0x4a009408
-#define CM_L4PER_ADC_CLKCTRL		0x4a009420
-#define CM_L4PER_DMTIMER10_CLKCTRL	0x4a009428
-#define CM_L4PER_DMTIMER11_CLKCTRL	0x4a009430
-#define CM_L4PER_DMTIMER2_CLKCTRL	0x4a009438
-#define CM_L4PER_DMTIMER3_CLKCTRL	0x4a009440
-#define CM_L4PER_DMTIMER4_CLKCTRL	0x4a009448
-#define CM_L4PER_DMTIMER9_CLKCTRL	0x4a009450
-#define CM_L4PER_ELM_CLKCTRL		0x4a009458
-#define CM_L4PER_GPIO2_CLKCTRL		0x4a009460
-#define CM_L4PER_GPIO3_CLKCTRL		0x4a009468
-#define CM_L4PER_GPIO4_CLKCTRL		0x4a009470
-#define CM_L4PER_GPIO5_CLKCTRL		0x4a009478
-#define CM_L4PER_GPIO6_CLKCTRL		0x4a009480
-#define CM_L4PER_HDQ1W_CLKCTRL		0x4a009488
-#define CM_L4PER_HECC1_CLKCTRL		0x4a009490
-#define CM_L4PER_HECC2_CLKCTRL		0x4a009498
-#define CM_L4PER_I2C1_CLKCTRL		0x4a0094a0
-#define CM_L4PER_I2C2_CLKCTRL		0x4a0094a8
-#define CM_L4PER_I2C3_CLKCTRL		0x4a0094b0
-#define CM_L4PER_I2C4_CLKCTRL		0x4a0094b8
-#define CM_L4PER_L4PER_CLKCTRL		0x4a0094c0
-#define CM_L4PER_MCASP2_CLKCTRL		0x4a0094d0
-#define CM_L4PER_MCASP3_CLKCTRL		0x4a0094d8
-#define CM_L4PER_MCBSP4_CLKCTRL		0x4a0094e0
-#define CM_L4PER_MGATE_CLKCTRL		0x4a0094e8
-#define CM_L4PER_MCSPI1_CLKCTRL		0x4a0094f0
-#define CM_L4PER_MCSPI2_CLKCTRL		0x4a0094f8
-#define CM_L4PER_MCSPI3_CLKCTRL		0x4a009500
-#define CM_L4PER_MCSPI4_CLKCTRL		0x4a009508
-#define CM_L4PER_MMCSD3_CLKCTRL		0x4a009520
-#define CM_L4PER_MMCSD4_CLKCTRL		0x4a009528
-#define CM_L4PER_MSPROHG_CLKCTRL	0x4a009530
-#define CM_L4PER_SLIMBUS2_CLKCTRL	0x4a009538
-#define CM_L4PER_UART1_CLKCTRL		0x4a009540
-#define CM_L4PER_UART2_CLKCTRL		0x4a009548
-#define CM_L4PER_UART3_CLKCTRL		0x4a009550
-#define CM_L4PER_UART4_CLKCTRL		0x4a009558
-#define CM_L4PER_MMCSD5_CLKCTRL		0x4a009560
-#define CM_L4PER_I2C5_CLKCTRL		0x4a009568
-#define CM_L4SEC_CLKSTCTRL		0x4a009580
-#define CM_L4SEC_STATICDEP		0x4a009584
-#define CM_L4SEC_DYNAMICDEP		0x4a009588
-#define CM_L4SEC_AES1_CLKCTRL		0x4a0095a0
-#define CM_L4SEC_AES2_CLKCTRL		0x4a0095a8
-#define CM_L4SEC_DES3DES_CLKCTRL	0x4a0095b0
-#define CM_L4SEC_PKAEIP29_CLKCTRL	0x4a0095b8
-#define CM_L4SEC_RNG_CLKCTRL		0x4a0095c0
-#define CM_L4SEC_SHA2MD51_CLKCTRL	0x4a0095c8
-#define CM_L4SEC_CRYPTODMA_CLKCTRL	0x4a0095d8
-
-/* CM2.IVAHD */
-#define IVAHD_CLKSTCTRL			0x4a008f00
-#define IVAHD_IVAHD_CLKCTRL		0x4a008f20
-#define IVAHD_SL2_CLKCTRL		0x4a008f28
-
-/* CM2.L3INIT */
-#define CM_L3INIT_HSMMC1_CLKCTRL	0x4a009328
-#define CM_L3INIT_HSMMC2_CLKCTRL	0x4a009330
-#define CM_L3INIT_HSI_CLKCTRL           0x4a009338
-#define CM_L3INIT_UNIPRO1_CLKCTRL       0x4a009340
-#define CM_L3INIT_HSUSBHOST_CLKCTRL     0x4a009358
-#define CM_L3INIT_HSUSBOTG_CLKCTRL      0x4a009360
-#define CM_L3INIT_HSUSBTLL_CLKCTRL      0x4a009368
-#define CM_L3INIT_P1500_CLKCTRL         0x4a009378
-#define CM_L3INIT_FSUSB_CLKCTRL         0x4a0093d0
-#define CM_L3INIT_USBPHY_CLKCTRL        0x4a0093e0
-
-/* CM2.CAM */
-#define CM_CAM_CLKSTCTRL                0x4a009000
-#define CM_CAM_ISS_CLKCTRL              0x4a009020
-#define CM_CAM_FDIF_CLKCTRL             0x4a009028
-
-/* CM2.DSS */
-#define CM_DSS_CLKSTCTRL                0x4a009100
-#define CM_DSS_DSS_CLKCTRL              0x4a009120
-#define CM_DSS_DEISS_CLKCTRL            0x4a009128
-
-/* CM2.SGX */
-#define CM_SGX_CLKSTCTRL                0x4a009200
-#define CM_SGX_SGX_CLKCTRL              0x4a009220
-
-#define PLL_STOP		1 /* PER & IVA */
-#define PLL_MN_POWER_BYPASS	4
-#define PLL_LOW_POWER_BYPASS	5 /* MPU, IVA & CORE */
-#define PLL_FAST_RELOCK_BYPASS	6 /* CORE */
-#define PLL_LOCK		7 /* MPU, IVA, CORE & PER */
-
-/* TPS */
-#define TPS62361_I2C_SLAVE_ADDR		0x60
-#define TPS62361_REG_ADDR_SET0		0x0
-#define TPS62361_REG_ADDR_SET1		0x1
-#define TPS62361_REG_ADDR_SET2		0x2
-#define TPS62361_REG_ADDR_SET3		0x3
-#define TPS62361_REG_ADDR_CTRL		0x4
-#define TPS62361_REG_ADDR_TEMP		0x5
-#define TPS62361_REG_ADDR_RMP_CTRL	0x6
-#define TPS62361_REG_ADDR_CHIP_ID	0x8
-#define TPS62361_REG_ADDR_CHIP_ID_2	0x9
-
-#define TPS62361_BASE_VOLT_MV	500
-
-/* Used to index into DPLL parameter tables */
-struct dpll_param {
-	unsigned int m;
-	unsigned int n;
-	unsigned int m2;
-	unsigned int m3;
-	unsigned int m4;
-	unsigned int m5;
-	unsigned int m6;
-	unsigned int m7;
-};
-
-#define OMAP4_MPU_DPLL_PARAM_19M2		{0x34, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
-#define OMAP4_MPU_DPLL_PARAM_19M2_MPU600	{0x7d, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
-#define OMAP4_MPU_DPLL_PARAM_19M2_MPU1000	{0x69, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
-#define OMAP4_MPU_DPLL_PARAM_38M4		{0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
-#define OMAP4_MPU_DPLL_PARAM_38M4_MPU600	{0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
-#define OMAP4_MPU_DPLL_PARAM_38M4_MPU1000	{0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
-/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
-#define OMAP4_MPU_DPLL_PARAM_19M2_MPU920	{0x30, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
-#define OMAP4_MPU_DPLL_PARAM_19M2_MPU1200	{0x7d, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
-#define OMAP4_MPU_DPLL_PARAM_19M2_MPU1500	{0x4e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
-
-#define OMAP4_IVA_DPLL_PARAM_19M2		{0x61, 0x01, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
-#define OMAP4_IVA_DPLL_PARAM_38M4		{0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
-
-#define OMAP4_PER_DPLL_PARAM_19M2		{0x28, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05}
-#define OMAP4_PER_DPLL_PARAM_38M4		{0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05}
-
-#define OMAP4_ABE_DPLL_PARAM_19M2		{0x80, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00}
-#define OMAP4_ABE_DPLL_PARAM_38M4		{0x40, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00}
-
-#define OMAP4_USB_DPLL_PARAM_19M2		{0x32, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}
-#define OMAP4_USB_DPLL_PARAM_38M4		{0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}
-
-#define OMAP4_CORE_DPLL_PARAM_19M2_DDR200	{0x7d, 0x02, 0x02, 0x05, 0x08, 0x04, 0x06, 0x06}
-#define OMAP4_CORE_DPLL_PARAM_19M2_DDR333	{0x410,	0x09, 0x03, 0x0c, 0x14, 0x0a, 0x0f, 0x0c}
-#define OMAP4_CORE_DPLL_PARAM_19M2_DDR400	{0x7d, 0x02, 0x01, 0x05, 0x08, 0x04, 0x06, 0x06}
-#define OMAP4_CORE_DPLL_PARAM_38M4_DDR200	{0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x06}
-#define OMAP4_CORE_DPLL_PARAM_38M4_DDR400	{0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x06}
-
-void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param);
-void omap4_configure_iva_dpll(const struct dpll_param *dpll_param);
-void omap4_configure_per_dpll(const struct dpll_param *dpll_param);
-void omap4_configure_abe_dpll(const struct dpll_param *dpll_param);
-void omap4_configure_usb_dpll(const struct dpll_param *dpll_param);
-void omap4_configure_core_dpll_no_lock(const struct dpll_param *param);
-void omap4_lock_core_dpll(void);
-void omap4_lock_core_dpll_shadow(const struct dpll_param *param);
-void omap4_enable_gpio1_wup_clocks(void);
-void omap4_enable_gpio_clocks(void);
-void omap4_enable_all_clocks(void);
-void omap4_do_scale_tps62361(u32 reg, u32 volt_mv);
-
-#endif /* __MACH_OMAP4_CLOCK_H */
diff --git a/arch/arm/mach-omap/include/mach/omap4-devices.h b/arch/arm/mach-omap/include/mach/omap4-devices.h
deleted file mode 100644
index 7ac940b2d7..0000000000
--- a/arch/arm/mach-omap/include/mach/omap4-devices.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef __MACH_OMAP4_DEVICES_H
-#define __MACH_OMAP4_DEVICES_H
-
-#include <driver.h>
-#include <linux/sizes.h>
-#include <mach/devices.h>
-#include <mach/omap4-silicon.h>
-#include <mach/mcspi.h>
-#include <mach/omap_hsmmc.h>
-
-static inline void omap44xx_add_sram0(void)
-{
-	return omap_add_sram0(OMAP44XX_SRAM_BASE, 48 * SZ_1K);
-}
-
-static inline struct device_d *omap44xx_add_uart1(void)
-{
-	return omap_add_uart(0, OMAP44XX_UART1_BASE);
-}
-
-static inline struct device_d *omap44xx_add_uart2(void)
-{
-	return omap_add_uart(1, OMAP44XX_UART2_BASE);
-}
-
-static inline struct device_d *omap44xx_add_uart3(void)
-{
-	return omap_add_uart(2, OMAP44XX_UART3_BASE);
-}
-
-static inline struct device_d *omap44xx_add_mmc1(struct omap_hsmmc_platform_data *pdata)
-{
-	return add_generic_device("omap4-hsmmc", 0, NULL,
-			OMAP44XX_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap44xx_add_mmc2(struct omap_hsmmc_platform_data *pdata)
-{
-	return add_generic_device("omap4-hsmmc", 1, NULL,
-			OMAP44XX_MMC2_BASE, SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap44xx_add_mmc3(struct omap_hsmmc_platform_data *pdata)
-{
-	return add_generic_device("omap4-hsmmc", 2, NULL,
-			OMAP44XX_MMC3_BASE, SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap44xx_add_mmc4(struct omap_hsmmc_platform_data *pdata)
-{
-	return add_generic_device("omap4-hsmmc", 3, NULL,
-			OMAP44XX_MMC4_BASE, SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap44xx_add_mmc5(struct omap_hsmmc_platform_data *pdata)
-{
-	return add_generic_device("omap4-hsmmc", 4, NULL,
-			OMAP44XX_MMC5_BASE, SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap44xx_add_i2c1(void *pdata)
-{
-	return add_generic_device("i2c-omap4", 0, NULL, OMAP44XX_I2C1_BASE,
-			SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap44xx_add_i2c2(void *pdata)
-{
-	return add_generic_device("i2c-omap4", 1, NULL, OMAP44XX_I2C2_BASE,
-			SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap44xx_add_i2c3(void *pdata)
-{
-	return add_generic_device("i2c-omap4", 2, NULL, OMAP44XX_I2C3_BASE,
-			SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap44xx_add_i2c4(void *pdata)
-{
-	return add_generic_device("i2c-omap4", 3, NULL, OMAP44XX_I2C4_BASE,
-			SZ_4K, IORESOURCE_MEM, pdata);
-}
-
-static inline struct device_d *omap44xx_add_ehci(void *pdata)
-{
-	return add_usb_ehci_device(DEVICE_ID_DYNAMIC, OMAP44XX_EHCI_BASE,
-				OMAP44XX_EHCI_BASE + 0x10, pdata);
-}
-
-#endif /* __MACH_OMAP4_DEVICES_H */
diff --git a/arch/arm/mach-omap/include/mach/omap4-generic.h b/arch/arm/mach-omap/include/mach/omap4-generic.h
deleted file mode 100644
index c1d0a3c900..0000000000
--- a/arch/arm/mach-omap/include/mach/omap4-generic.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __MACH_OMAP4_GENERIC_H
-#define __MACH_OMAP4_GENERIC_H
-
-#include <linux/sizes.h>
-#include <mach/generic.h>
-#include <mach/omap4-silicon.h>
-
-static inline void omap4_save_bootinfo(uint32_t *info)
-{
-	unsigned long i = (unsigned long)info;
-
-	if (i & 0x3)
-		return;
-	if (i < OMAP44XX_SRAM_BASE)
-		return;
-	if (i > OMAP44XX_SRAM_BASE + SZ_64K)
-		return;
-
-	memcpy((void *)OMAP44XX_SRAM_SCRATCH_SPACE, info, 3 * sizeof(uint32_t));
-}
-
-int omap4_init(void);
-int omap4_devices_init(void);
-
-#endif /* __MACH_OMAP4_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/omap4-mux.h b/arch/arm/mach-omap/include/mach/omap4-mux.h
deleted file mode 100644
index 8ef9ae0847..0000000000
--- a/arch/arm/mach-omap/include/mach/omap4-mux.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff		<r-woodruff2@ti.com>
- * Aneesh V			<aneesh@ti.com>
- * Balaji Krishnamoorthy	<balajitk@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#ifndef _MUX_OMAP4_H_
-#define _MUX_OMAP4_H_
-
-#include <asm/types.h>
-
-struct pad_conf_entry {
-
-	u16 offset;
-
-	u16 val;
-
-};
-
-#define WAKEUP_EN       (1 << 14)
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_PD          (1 << 12)
-#define OFF_PU          (3 << 12)
-#define OFF_OUT_PTD     (0 << 10)
-#define OFF_OUT_PTU     (2 << 10)
-#define OFF_IN          (1 << 10)
-#define OFF_OUT         (0 << 10)
-#define OFF_EN          (1 << 9)
-#else
-#define OFF_PD          (0 << 12)
-#define OFF_PU          (0 << 12)
-#define OFF_OUT_PTD     (0 << 10)
-#define OFF_OUT_PTU     (0 << 10)
-#define OFF_IN          (0 << 10)
-#define OFF_OUT         (0 << 10)
-#define OFF_EN          (0 << 9)
-#endif
-
-#define IEN             (1 << 8)
-#define IDIS            (0 << 8)
-#define PTU             (3 << 3)
-#define PTD             (1 << 3)
-#define EN              (1 << 3)
-#define DIS             (0 << 3)
-
-#define M0              0
-#define M1              1
-#define M2              2
-#define M3              3
-#define M4              4
-#define M5              5
-#define M6              6
-#define M7              7
-
-#define SAFE_MODE	M7
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
-#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
-#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
-#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
-#else
-#define OFF_IN_PD       0
-#define OFF_IN_PU       0
-#define OFF_OUT_PD      0
-#define OFF_OUT_PU      0
-#endif
-
-#define CORE_REVISION		0x0000
-#define CORE_HWINFO		0x0004
-#define CORE_SYSCONFIG		0x0010
-#define GPMC_AD0		0x0040
-#define GPMC_AD1		0x0042
-#define GPMC_AD2		0x0044
-#define GPMC_AD3		0x0046
-#define GPMC_AD4		0x0048
-#define GPMC_AD5		0x004A
-#define GPMC_AD6		0x004C
-#define GPMC_AD7		0x004E
-#define GPMC_AD8		0x0050
-#define GPMC_AD9		0x0052
-#define GPMC_AD10		0x0054
-#define GPMC_AD11		0x0056
-#define GPMC_AD12		0x0058
-#define GPMC_AD13		0x005A
-#define GPMC_AD14		0x005C
-#define GPMC_AD15		0x005E
-#define GPMC_A16		0x0060
-#define GPMC_A17		0x0062
-#define GPMC_A18		0x0064
-#define GPMC_A19		0x0066
-#define GPMC_A20		0x0068
-#define GPMC_A21		0x006A
-#define GPMC_A22		0x006C
-#define GPMC_A23		0x006E
-#define GPMC_A24		0x0070
-#define GPMC_A25		0x0072
-#define GPMC_NCS0		0x0074
-#define GPMC_NCS1		0x0076
-#define GPMC_NCS2		0x0078
-#define GPMC_NCS3		0x007A
-#define GPMC_NWP		0x007C
-#define GPMC_CLK		0x007E
-#define GPMC_NADV_ALE		0x0080
-#define GPMC_NOE		0x0082
-#define GPMC_NWE		0x0084
-#define GPMC_NBE0_CLE		0x0086
-#define GPMC_NBE1		0x0088
-#define GPMC_WAIT0		0x008A
-#define GPMC_WAIT1		0x008C
-#define C2C_DATA11		0x008E
-#define GPMC_WAIT2          0x008E
-#define C2C_DATA12		0x0090
-#define GPMC_NCS4           0x0090
-#define C2C_DATA13		0x0092
-#define GPMC_NCS5           0x0092
-#define C2C_DATA14		0x0094
-#define GPMC_NCS6           0x0094
-#define C2C_DATA15		0x0096
-#define GPMC_NCS7           0x0096
-#define HDMI_HPD		0x0098
-#define GPIO63              0x0098
-#define HDMI_CEC		0x009A
-#define GPIO64              0x009A
-#define HDMI_DDC_SCL		0x009C
-#define GPIO65              0x009C
-#define HDMI_DDC_SDA		0x009E
-#define GPIO66              0x009E
-#define CSI21_DX0		0x00A0
-#define CSI21_DY0		0x00A2
-#define CSI21_DX1		0x00A4
-#define CSI21_DY1		0x00A6
-#define CSI21_DX2		0x00A8
-#define CSI21_DY2		0x00AA
-#define CSI21_DX3		0x00AC
-#define CSI21_DY3		0x00AE
-#define CSI21_DX4		0x00B0
-#define CSI21_DY4		0x00B2
-#define CSI22_DX0		0x00B4
-#define CSI22_DY0		0x00B6
-#define CSI22_DX1		0x00B8
-#define CSI22_DY1		0x00BA
-#define CAM_SHUTTER		0x00BC
-#define CAM_STROBE		0x00BE
-#define CAM_GLOBALRESET		0x00C0
-#define USBB1_ULPITLL_CLK	0x00C2
-#define USBB1_ULPITLL_STP	0x00C4
-#define USBB1_ULPITLL_DIR	0x00C6
-#define USBB1_ULPITLL_NXT	0x00C8
-#define USBB1_ULPITLL_DAT0	0x00CA
-#define USBB1_ULPITLL_DAT1	0x00CC
-#define USBB1_ULPITLL_DAT2	0x00CE
-#define USBB1_ULPITLL_DAT3	0x00D0
-#define USBB1_ULPITLL_DAT4	0x00D2
-#define USBB1_ULPITLL_DAT5	0x00D4
-#define USBB1_ULPITLL_DAT6	0x00D6
-#define USBB1_ULPITLL_DAT7	0x00D8
-#define USBB1_HSIC_DATA		0x00DA
-#define USBB1_HSIC_STROBE	0x00DC
-#define USBC1_ICUSB_DP		0x00DE
-#define USBC1_ICUSB_DM		0x00E0
-#define SDMMC1_CLK		0x00E2
-#define SDMMC1_CMD		0x00E4
-#define SDMMC1_DAT0		0x00E6
-#define SDMMC1_DAT1		0x00E8
-#define SDMMC1_DAT2		0x00EA
-#define SDMMC1_DAT3		0x00EC
-#define SDMMC1_DAT4		0x00EE
-#define SDMMC1_DAT5		0x00F0
-#define SDMMC1_DAT6		0x00F2
-#define SDMMC1_DAT7		0x00F4
-#define ABE_MCBSP2_CLKX		0x00F6
-#define ABE_MCBSP2_DR		0x00F8
-#define ABE_MCBSP2_DX		0x00FA
-#define ABE_MCBSP2_FSX		0x00FC
-#define ABE_MCBSP1_CLKX		0x00FE
-#define ABE_MCBSP1_DR		0x0100
-#define ABE_MCBSP1_DX		0x0102
-#define ABE_MCBSP1_FSX		0x0104
-#define ABE_PDM_UL_DATA		0x0106
-#define ABE_PDM_DL_DATA		0x0108
-#define ABE_PDM_FRAME		0x010A
-#define ABE_PDM_LB_CLK		0x010C
-#define ABE_CLKS		0x010E
-#define ABE_DMIC_CLK1		0x0110
-#define ABE_DMIC_DIN1		0x0112
-#define ABE_DMIC_DIN2		0x0114
-#define ABE_DMIC_DIN3		0x0116
-#define UART2_CTS		0x0118
-#define UART2_RTS		0x011A
-#define UART2_RX		0x011C
-#define UART2_TX		0x011E
-#define HDQ_SIO			0x0120
-#define I2C1_SCL		0x0122
-#define I2C1_SDA		0x0124
-#define I2C2_SCL		0x0126
-#define I2C2_SDA		0x0128
-#define I2C3_SCL		0x012A
-#define I2C3_SDA		0x012C
-#define I2C4_SCL		0x012E
-#define I2C4_SDA		0x0130
-#define MCSPI1_CLK		0x0132
-#define MCSPI1_SOMI		0x0134
-#define MCSPI1_SIMO		0x0136
-#define MCSPI1_CS0		0x0138
-#define MCSPI1_CS1		0x013A
-#define MCSPI1_CS2		0x013C
-#define MCSPI1_CS3		0x013E
-#define UART3_CTS_RCTX		0x0140
-#define UART3_RTS_SD		0x0142
-#define UART3_RX_IRRX		0x0144
-#define UART3_TX_IRTX		0x0146
-#define SDMMC5_CLK		0x0148
-#define SDMMC5_CMD		0x014A
-#define SDMMC5_DAT0		0x014C
-#define SDMMC5_DAT1		0x014E
-#define SDMMC5_DAT2		0x0150
-#define SDMMC5_DAT3		0x0152
-#define MCSPI4_CLK		0x0154
-#define MCSPI4_SIMO		0x0156
-#define MCSPI4_SOMI		0x0158
-#define MCSPI4_CS0		0x015A
-#define UART4_RX		0x015C
-#define UART4_TX		0x015E
-#define USBB2_ULPITLL_CLK	0x0160
-#define USBB2_ULPITLL_STP	0x0162
-#define USBB2_ULPITLL_DIR	0x0164
-#define USBB2_ULPITLL_NXT	0x0166
-#define USBB2_ULPITLL_DAT0	0x0168
-#define USBB2_ULPITLL_DAT1	0x016A
-#define USBB2_ULPITLL_DAT2	0x016C
-#define USBB2_ULPITLL_DAT3	0x016E
-#define USBB2_ULPITLL_DAT4	0x0170
-#define USBB2_ULPITLL_DAT5	0x0172
-#define USBB2_ULPITLL_DAT6	0x0174
-#define USBB2_ULPITLL_DAT7	0x0176
-#define USBB2_HSIC_DATA		0x0178
-#define USBB2_HSIC_STROBE	0x017A
-#define UNIPRO_TX0		0x017C
-#define KPD_COL3            0x017C
-#define UNIPRO_TY0		0x017E
-#define KPD_COL4            0x017E
-#define UNIPRO_TX1		0x0180
-#define KPD_COL5            0x0180
-#define UNIPRO_TY1		0x0182
-#define KPD_COL0            0x0182
-#define UNIPRO_TX2		0x0184
-#define KPD_COL1            0x0184
-#define UNIPRO_TY2		0x0186
-#define KPD_COL2            0x0186
-#define UNIPRO_RX0		0x0188
-#define KPD_ROW3            0x0188
-#define UNIPRO_RY0		0x018A
-#define KPD_ROW4            0x018A
-#define UNIPRO_RX1		0x018C
-#define KPD_ROW5            0x018C
-#define UNIPRO_RY1		0x018E
-#define KPD_ROW0            0x018E
-#define UNIPRO_RX2		0x0190
-#define KPD_ROW1            0x0190
-#define UNIPRO_RY2		0x0192
-#define KPD_ROW2            0x0192
-#define USBA0_OTG_CE		0x0194
-#define USBA0_OTG_DP		0x0196
-#define USBA0_OTG_DM		0x0198
-#define FREF_CLK1_OUT		0x019A
-#define FREF_CLK2_OUT		0x019C
-#define SYS_NIRQ1		0x019E
-#define SYS_NIRQ2		0x01A0
-#define SYS_BOOT0		0x01A2
-#define SYS_BOOT1		0x01A4
-#define SYS_BOOT2		0x01A6
-#define SYS_BOOT3		0x01A8
-#define SYS_BOOT4		0x01AA
-#define SYS_BOOT5		0x01AC
-#define DPM_EMU0		0x01AE
-#define DPM_EMU1		0x01B0
-#define DPM_EMU2		0x01B2
-#define DPM_EMU3		0x01B4
-#define DPM_EMU4		0x01B6
-#define DPM_EMU5		0x01B8
-#define DPM_EMU6		0x01BA
-#define DPM_EMU7		0x01BC
-#define DPM_EMU8		0x01BE
-#define DPM_EMU9		0x01C0
-#define DPM_EMU10		0x01C2
-#define DPM_EMU11		0x01C4
-#define DPM_EMU12		0x01C6
-#define DPM_EMU13		0x01C8
-#define DPM_EMU14		0x01CA
-#define DPM_EMU15		0x01CC
-#define DPM_EMU16		0x01CE
-#define DPM_EMU17		0x01D0
-#define DPM_EMU18		0x01D2
-#define DPM_EMU19		0x01D4
-#define CSI22_DX2           0x01D6
-#define CSI22_DY2           0x01F4
-#define WAKEUPEVENT_0		0x01D8
-#define WAKEUPEVENT_1		0x01DC
-#define WAKEUPEVENT_2		0x01E0
-#define WAKEUPEVENT_3		0x01E4
-#define WAKEUPEVENT_4		0x01E8
-#define WAKEUPEVENT_5		0x01EC
-#define WAKEUPEVENT_6		0x01F0
-
-#define WKUP_REVISION		0x0000
-#define WKUP_HWINFO		0x0004
-#define WKUP_SYSCONFIG		0x0010
-#define GPIO_WK0            0x0040
-#define GPIO_WK1            0x0042
-#define GPIO_WK2            0x0044
-#define GPIO_WK3            0x0046
-#define GPIO_WK4            0x0048
-#define SR_SCL              0x004A
-#define SR_SDA              0x004C
-#define FREF_XTAL_IN        0x004E
-#define FREF_SLICER_IN      0x0050
-#define FREF_CLK_IOREQ      0x0052
-#define FREF_CLK0_OUT       0x0054
-#define FREF_CLK3_REQ       0x0056
-#define FREF_CLK3_OUT       0x0058
-#define FREF_CLK4_REQ       0x005A
-#define FREF_CLK4_OUT       0x005C
-#define SYS_32K             0x005E
-#define SYS_NRESPWRON       0x0060
-#define SYS_NRESWARM        0x0062
-#define SYS_PWR_REQ         0x0064
-#define SYS_PWRON_RESET_OUT 0x0066
-#define SYS_BOOT6           0x0068
-#define SYS_BOOT7           0x006A
-#define JTAG_NTRST          0x006C
-#define JTAG_TCK            0x006E
-#define JTAG_RTCK           0x0070
-#define JTAG_TMS_TMSC       0x0072
-#define JTAG_TDI            0x0074
-#define JTAG_TDO            0x0076
-#define PADCONF_WAKEUPEVENT_0	0x007C
-#define CONTROL_SMART1NOPMIO_PADCONF_0		0x05A0
-#define CONTROL_SMART1NOPMIO_PADCONF_1		0x05A4
-#define PADCONF_MODE		0x05A8
-#define CONTROL_XTAL_OSCILLATOR			0x05AC
-#define CONTROL_CONTROL_I2C_2			0x0604
-#define CONTROL_CONTROL_JTAG			0x0608
-#define CONTROL_CONTROL_SYS			0x060C
-#define CONTROL_SPARE_RW		0x0614
-#define CONTROL_SPARE_R		0x0618
-#define CONTROL_SPARE_R_C0		0x061C
-
-void omap4_do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
-
-#endif /* _MUX_OMAP4_H_ */
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
deleted file mode 100644
index b9f6119894..0000000000
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Authors:
- *	Aneesh V <aneesh@ti.com>
- *
- * Derived from OMAP3 work by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _OMAP4_H_
-#define _OMAP4_H_
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-/*
- * L4 Peripherals - L4 Wakeup and L4 Core now
- */
-#define OMAP44XX_L4_CORE_BASE		0x4A000000
-#define OMAP44XX_WAKEUP_L4_IO_BASE	0x4A300000
-#define OMAP44XX_L4_WKUP_BASE		0x4A300000
-#define OMAP44XX_L4_PER_BASE		0x48000000
-
-#define OMAP44XX_SRAM_BASE		0x40300000
-#define OMAP44XX_SRAM_SCRATCH_SPACE	0x4030c000 /* start of public stack */
-
-/* EMIF and DMM registers */
-#define OMAP44XX_EMIF1_BASE		0x4c000000
-#define OMAP44XX_EMIF2_BASE		0x4d000000
-
-#define OMAP44XX_DRAM_ADDR_SPACE_START	0x80000000
-#define OMAP44XX_DRAM_ADDR_SPACE_END	0xD0000000
-
-
-/* CONTROL */
-#define OMAP44XX_CTRL_BASE		(OMAP44XX_L4_CORE_BASE + 0x2000)
-#define OMAP44XX_CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
-#define OMAP44XX_CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
-
-/* PRM */
-#define OMAP44XX_PRM_VC_VAL_BYPASS	(OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba0)
-#define OMAP44XX_PRM_VC_CFG_I2C_MODE	(OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba8)
-#define OMAP44XX_PRM_VC_CFG_I2C_CLK	(OMAP44XX_WAKEUP_L4_IO_BASE + 0x7bac)
-#define OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT		0x1000000
-#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
-#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
-#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_SHIFT	8
-#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
-#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_SHIFT		16
-#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
-
-/* IRQ */
-#define OMAP44XX_PRM_IRQSTATUS_MPU_A9	(OMAP44XX_WAKEUP_L4_IO_BASE + 0x6010)
-
-/* UART */
-#define OMAP44XX_UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
-#define OMAP44XX_UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
-#define OMAP44XX_UART3_BASE		(OMAP44XX_L4_PER_BASE + 0x20000)
-
-/* I2C */
-#define OMAP44XX_I2C1_BASE		(OMAP44XX_L4_PER_BASE + 0x070000)
-#define OMAP44XX_I2C2_BASE		(OMAP44XX_L4_PER_BASE + 0x072000)
-#define OMAP44XX_I2C3_BASE		(OMAP44XX_L4_PER_BASE + 0x060000)
-#define OMAP44XX_I2C4_BASE		(OMAP44XX_L4_PER_BASE + 0x350000)
-
-/* General Purpose Timers */
-#define OMAP44XX_GPT1_BASE		(OMAP44XX_L4_WKUP_BASE + 0x18000)
-#define OMAP44XX_GPT2_BASE		(OMAP44XX_L4_PER_BASE  + 0x32000)
-#define OMAP44XX_GPT3_BASE		(OMAP44XX_L4_PER_BASE  + 0x34000)
-
-/* Watchdog Timer2 - MPU watchdog */
-#define OMAP44XX_WDT2_BASE		(OMAP44XX_L4_WKUP_BASE + 0x14000)
-
-#define OMAP44XX_SCRM_BASE              0x4a30a000
-#define OMAP44XX_SCRM_ALTCLKSRC         (OMAP44XX_SCRM_BASE + 0x110)
-#define OMAP44XX_SCRM_AUXCLK1           (OMAP44XX_SCRM_BASE + 0x314)
-#define OMAP44XX_SCRM_AUXCLK3           (OMAP44XX_SCRM_BASE + 0x31c)
-
-/* 32KTIMER */
-#define OMAP44XX_32KTIMER_BASE		(OMAP44XX_L4_WKUP_BASE + 0x4000)
-
-/* MMC */
-#define OMAP44XX_MMC1_BASE		(OMAP44XX_L4_PER_BASE + 0x09C000)
-#define OMAP44XX_MMC2_BASE		(OMAP44XX_L4_PER_BASE + 0x0B4000)
-#define OMAP44XX_MMC3_BASE		(OMAP44XX_L4_PER_BASE + 0x0AD000)
-#define OMAP44XX_MMC4_BASE		(OMAP44XX_L4_PER_BASE + 0x0D1000)
-#define OMAP44XX_MMC5_BASE		(OMAP44XX_L4_PER_BASE + 0x0D5000)
-
-/* GPIO
- *
- *  Note that, while the GPIO controller is the same as on an OMAP3,
- * the base address has an additional offset of 0x100, which you can
- * see being added here so that the OMAP_GPIO_* macros you see in
- * mach-omap/gpio.c don't need to be adjusted based on the platform.
- */
-
-#define OMAP44XX_GPIO1_BASE		(OMAP44XX_L4_WKUP_BASE + 0x10100)
-#define OMAP44XX_GPIO2_BASE		(OMAP44XX_L4_PER_BASE  + 0x55100)
-#define OMAP44XX_GPIO3_BASE		(OMAP44XX_L4_PER_BASE  + 0x57100)
-#define OMAP44XX_GPIO4_BASE		(OMAP44XX_L4_PER_BASE  + 0x59100)
-#define OMAP44XX_GPIO5_BASE		(OMAP44XX_L4_PER_BASE  + 0x5B100)
-#define OMAP44XX_GPIO6_BASE		(OMAP44XX_L4_PER_BASE  + 0x5D100)
-
-/* GPMC */
-#define OMAP44XX_GPMC_BASE		0x50000000
-
-/* EHCI */
-#define OMAP44XX_EHCI_BASE		(OMAP44XX_L4_CORE_BASE + 0x64C00)
-
-/* DMM */
-#define OMAP44XX_DMM_BASE		0x4E000000
-#define DMM_LISA_MAP_BASE		(OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
-#define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
-
-/* Memory Adapter (4460 onwards) */
-#define OMAP44XX_MA_BASE		0x482AF000
-
-/*
- * Hardware Register Details
- */
-
-/* Watchdog Timer */
-#define WD_UNLOCK1		0xAAAA
-#define WD_UNLOCK2		0x5555
-
-/* GP Timer */
-#define TCLR_ST			(0x1 << 0)
-#define TCLR_AR			(0x1 << 1)
-#define TCLR_PRE		(0x1 << 5)
-
-/*
- * PRCM
- */
-
-/* PRM */
-#define OMAP44XX_PRM_BASE		0x4A306000
-#define OMAP44XX_PRM_DEVICE_BASE	(OMAP44XX_PRM_BASE + 0x1B00)
-
-#define OMAP44XX_PRM_RSTCTRL		OMAP44XX_PRM_DEVICE_BASE
-#define OMAP44XX_PRM_RSTCTRL_RESET	0x01
-
-/*
- * SAR (Save & Rescue) memory region
- */
-#define OMAP44XX_SAR_RAM_BASE      0x4a326000
-#define OMAP44XX_SAR_CH_ADDRESS    (OMAP44XX_SAR_RAM_BASE + 0xA00)
-#define OMAP44XX_SAR_CH_START      (OMAP44XX_SAR_RAM_BASE + 0xA0C)
-#define OMAP44XX_SAR_BOOT_VOID     0x00
-#define OMAP44XX_SAR_BOOT_XIP      0x01
-#define OMAP44XX_SAR_BOOT_XIPWAIT  0x02
-#define OMAP44XX_SAR_BOOT_NAND     0x03
-#define OMAP44XX_SAR_BOOT_ONENAND  0x04
-#define OMAP44XX_SAR_BOOT_MMC1     0x05
-#define OMAP44XX_SAR_BOOT_MMC2_1   0x06
-#define OMAP44XX_SAR_BOOT_MMC2_2   0x07
-#define OMAP44XX_SAR_BOOT_UART     0x43
-#define OMAP44XX_SAR_BOOT_USB_1    0x45
-#define OMAP44XX_SAR_BOOT_USB_ULPI 0x46
-#define OMAP44XX_SAR_BOOT_USB_2    0x47
-
-/*
- * Non-secure SRAM Addresses
- * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
- * at 0x40304000(EMU base) so that our code works for both EMU and GP
- */
-#define NON_SECURE_SRAM_START	0x40304000
-#define NON_SECURE_SRAM_END	0x4030E000	/* Not inclusive */
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_ROM_VECT_BASE	0x4030D000
-
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10	1
-#define CPU_OMAP4430_ES20	2
-
-#define CM_DLL_CTRL		0x4a004110
-#define CM_MEMIF_EMIF_1_CLKCTRL	0x4a008b30
-#define CM_MEMIF_EMIF_2_CLKCTRL 0x4a008b38
-
-/* Silicon revisions */
-#define OMAP4430_SILICON_ID_INVALID	0
-#define OMAP4430_ES1_0	1
-#define OMAP4430_ES2_0	2
-#define OMAP4430_ES2_1	3
-#define OMAP4430_ES2_2	4
-#define OMAP4430_ES2_3	5
-#define OMAP4460_ES1_0	6
-#define OMAP4460_ES1_1	7
-
-#ifndef __ASSEMBLY__
-
-struct ddr_regs {
-	u32 tim1;
-	u32 tim2;
-	u32 tim3;
-	u32 phy_ctrl_1;
-	u32 ref_ctrl;
-	u32 config_init;
-	u32 config_final;
-	u32 zq_config;
-	u8 mr1;
-	u8 mr2;
-};
-
-struct dpll_param;
-
-void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
-void omap4_power_i2c_send(u32);
-unsigned int omap4_revision(void);
-int omap4430_scale_vcores(void);
-int omap4460_scale_vcores(unsigned vsel0_pin, unsigned volt_mv);
-void omap4_set_warmboot_order(u32 *device_list);
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap/include/mach/omap4_rom_usb.h b/arch/arm/mach-omap/include/mach/omap4_rom_usb.h
deleted file mode 100644
index bf8bd159ad..0000000000
--- a/arch/arm/mach-omap/include/mach/omap4_rom_usb.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2010 The Android Open Source Project
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _OMAP4_ROM_USB_H_
-#define _OMAP4_ROM_USB_H_
-
-/* public api */
-#define PUBLIC_API_BASE_4430		(0x28400)
-#define PUBLIC_API_BASE_4460		(0x30400)
-
-#define PUBLIC_GET_DRIVER_MEM_OFFSET (0x04)
-#define PUBLIC_GET_DRIVER_PER_OFFSET (0x08)
-#define PUBLIC_GET_DEVICE_MEM_OFFSET (0x80)
-#define PUBLIC_GET_DEVICE_PER_OFFSET (0x84)
-
-#define DEVICE_NULL	0x40
-#define DEVICE_UART1	0x41
-#define DEVICE_UART2	0x42
-#define DEVICE_UART3	0x43
-#define DEVICE_UART4	0x44
-#define DEVICE_USB	0x45
-#define DEVICE_USBEXT	0x46
-
-#define XFER_MODE_CPU 0
-#define XFER_MODE_DMA 1
-
-#define STATUS_OKAY		0
-#define STATUS_FAILED		1
-#define STATUS_TIMEOUT		2
-#define STATUS_BAD_PARAM	3
-#define STATUS_WAITING		4
-#define STATUS_NO_MEMORY	5
-#define STATUS_INVALID_PTR	6
-
-/* Memory ROM interface */
-struct read_desc {
-	u32 sector_start;
-	u32 sector_count;
-	void *destination;
-};
-
-struct mem_device {
-	u32 initialized;
-	u8 device_type;
-	u8 trials_count;
-	u32 xip_device;
-	u16 search_size;
-	u32 base_address;
-	u16 hs_toc_mask;
-	u16 gp_toc_mask;
-	void *device_data;
-	u16 *boot_options;
-};
-
-struct mem_driver {
-	int (*init)(struct mem_device *md);
-	int (*read)(struct mem_device *md, struct read_desc *rd);
-	int (*configure)(struct mem_device *md, void *config);
-};
-
-
-/* Peripheral ROM interface */
-struct per_handle {
-	void *set_to_null;
-	void (*callback)(struct per_handle *rh);
-	void *data;
-	u32 length;
-	u16 *options;
-	u32 xfer_mode;
-	u32 device_type;
-	u32 status;
-	u16 hs_toc_mask;
-	u16 gp_toc_mask;
-	u32 config_timeout;
-};
-
-struct per_driver {
-	int (*init)(struct per_handle *rh);
-	int (*read)(struct per_handle *rh);
-	int (*write)(struct per_handle *rh);
-	int (*close)(struct per_handle *rh);
-	int (*config)(struct per_handle *rh, void *x);
-};
-
-#define USB_SETCONFIGDESC_ATTRIBUTES      (0)
-#define USB_SETCONFIGDESC_MAXPOWER        (1)
-#define USB_SETSUSPEND_CALLBACK           (2)
-struct per_usb_config {
-	u32 configid;
-	u32 value;
-};
-
-#define API(n) ((void *) (*((u32 *) (n))))
-/* ROM API End */
-
-struct omap4_usbboot {
-	struct per_handle dread;
-	struct per_handle dwrite;
-	struct per_driver *io;
-	int ready;
-};
-
-int omap4_usbboot_open(void);
-int omap4_usbboot_ready(void);
-void omap4_usbboot_close(void);
-
-void omap4_usbboot_queue_read(void *data, unsigned len);
-int omap4_usbboot_wait_read(void);
-int omap4_usbboot_is_read_waiting(void);
-int omap4_usbboot_is_read_ok(void);
-
-void omap4_usbboot_queue_write(void *data, unsigned len);
-int omap4_usbboot_wait_write(void);
-
-int omap4_usbboot_read(void *data, unsigned len);
-int omap4_usbboot_write(void *data, unsigned len);
-void omap4_usbboot_puts(const char *s);
-
-#endif
diff --git a/arch/arm/mach-omap/include/mach/omap4_twl6030_mmc.h b/arch/arm/mach-omap/include/mach/omap4_twl6030_mmc.h
deleted file mode 100644
index e5e2d9c229..0000000000
--- a/arch/arm/mach-omap/include/mach/omap4_twl6030_mmc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2011 Alexander Aring <a.aring@phytec.de>
- */
-
-#ifndef __OMAP4_TWL6030_MMC_H__
-#define __OMAP4_TWL6030_MMC_H__
-
-/*
- * Sets up voltage for mmc slot.
- */
-void set_up_mmc_voltage_omap4(void);
-
-/* __OMAP4_TWL6030_MMC_H__ */
-#endif
diff --git a/arch/arm/mach-omap/include/mach/omap_hsmmc.h b/arch/arm/mach-omap/include/mach/omap_hsmmc.h
deleted file mode 100644
index 19942df587..0000000000
--- a/arch/arm/mach-omap/include/mach/omap_hsmmc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/**
- * @file
- * @brief This file contains exported structure for OMAP hsmmc
- *
- * OMAP3 and OMAP4 has a MMC/SD controller embedded.
- * This file provides the platform data structure required to
- * addapt to platform specialities.
- *
- * (C) Copyright 2011
- * Phytec Messtechnik GmbH, <www.phytec.de>
- * Juergen Kilb <j.kilb@phytec.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_OMAP_HSMMC_H
-#define  __ASM_OMAP_HSMMC_H
-
-/** omapmmc platform data structure */
-struct omap_hsmmc_platform_data {
-	unsigned f_max;         /* host interface upper limit */
-	char *devname;		/* The mci device name, optional */
-};
-#endif /* __ASM_OMAP_HSMMC_H */
diff --git a/arch/arm/mach-omap/include/mach/sdrc.h b/arch/arm/mach-omap/include/mach/sdrc.h
deleted file mode 100644
index 1cccbc63e2..0000000000
--- a/arch/arm/mach-omap/include/mach/sdrc.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * @file
- * @brief This file contains the SDRC specific register definitions
- *
- * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
- *
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _ASM_ARCH_SDRC_H
-#define _ASM_ARCH_SDRC_H
-
-#define OMAP3_SDRC_REG(REGNAME)	(OMAP3_SDRC_BASE + OMAP_SDRC_##REGNAME)
-#define OMAP_SDRC_SYSCONFIG	(0x10)
-#define OMAP_SDRC_STATUS	(0x14)
-#define OMAP_SDRC_CS_CFG	(0x40)
-#define OMAP_SDRC_SHARING	(0x44)
-#define OMAP_SDRC_DLLA_CTRL	(0x60)
-#define OMAP_SDRC_DLLA_STATUS	(0x64)
-#define OMAP_SDRC_DLLB_CTRL	(0x68)
-#define OMAP_SDRC_DLLB_STATUS	(0x6C)
-#define DLLPHASE		(0x1 << 1)
-#define LOADDLL			(0x1 << 2)
-#define DLL_DELAY_MASK		0xFF00
-#define DLL_NO_FILTER_MASK	((0x1 << 8)|(0x1 << 9))
-
-#define OMAP_SDRC_POWER		(0x70)
-#define WAKEUPPROC		(0x1 << 26)
-
-#define OMAP_SDRC_MCFG_0	(0x80)
-#define OMAP_SDRC_MCFG_1	(0xB0)
-#define OMAP_SDRC_MR_0		(0x84)
-#define OMAP_SDRC_MR_1		(0xB4)
-#define OMAP_SDRC_ACTIM_CTRLA_0	(0x9C)
-#define OMAP_SDRC_ACTIM_CTRLB_0	(0xA0)
-#define OMAP_SDRC_ACTIM_CTRLA_1	(0xC4)
-#define OMAP_SDRC_ACTIM_CTRLB_1	(0xC8)
-#define OMAP_SDRC_RFR_CTRL_0	(0xA4)
-#define OMAP_SDRC_RFR_CTRL_1	(0xD4)
-#define OMAP_SDRC_MANUAL_0	(0xA8)
-#define CMD_NOP			0x0
-#define CMD_PRECHARGE		0x1
-#define CMD_AUTOREFRESH		0x2
-#define CMD_ENTR_PWRDOWN	0x3
-#define CMD_EXIT_PWRDOWN	0x4
-#define CMD_ENTR_SRFRSH		0x5
-#define CMD_CKE_HIGH		0x6
-#define CMD_CKE_LOW		0x7
-#define SOFTRESET		(0x1 << 1)
-#define SMART_IDLE		(0x2 << 3)
-#define REF_ON_IDLE		(0x1 << 6)
-
-#define SDRC_CS0_OSET		0x0
-/* Mirror CS1 regs appear offset 0x30 from CS0 */
-#define SDRC_CS1_OSET		0x30
-
-#define SDRC_STACKED		0
-#define SDRC_IP_DDR		1
-#define SDRC_COMBO_DDR		2
-#define SDRC_IP_SDR		3
-
-
-#define SDRC_B_R_C		(0 << 6)	/* bank-row-column */
-#define SDRC_B1_R_B0_C		(1 << 6)	/* bank1-row-bank0-column */
-#define SDRC_R_B_C		(2 << 6)	/* row-bank-column */
-
-#define DLL_OFFSET              0
-#define DLL_WRITEDDRCLKX2DIS    1
-#define DLL_ENADLL              1
-#define DLL_LOCKDLL             0
-#define DLL_DLLPHASE_72         0
-#define DLL_DLLPHASE_90         1
-
-#endif /* _ASM_ARCH_SDRC_H */
diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
deleted file mode 100644
index 57bfb3c680..0000000000
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- * @file
- * @brief This file defines the macros apis which are useful for most OMAP
- * platforms.
- *
- * These are implemented by the System specific code in omapX-generic.c
- *
- * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
- *
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_SYS_INFO_H_
-#define __ASM_ARCH_SYS_INFO_H_
-
-#define XDR_POP		5      /* package on package part */
-#define SDR_DISCRETE	4      /* 128M memory SDR module*/
-#define DDR_STACKED	3      /* stacked part on 2422 */
-#define DDR_COMBO	2      /* combo part on cpu daughter card (menalaeus) */
-#define DDR_DISCRETE	1      /* 2x16 parts on daughter card */
-
-#define DDR_100		100    /* type found on most mem d-boards */
-#define DDR_111		111    /* some combo parts */
-#define DDR_133		133    /* most combo, some mem d-boards */
-#define DDR_165		165    /* future parts */
-
-#define CPU_1610	0x1610
-#define CPU_1710	0x1710
-#define CPU_2420	0x2420
-#define CPU_2430	0x2430
-#define CPU_3350	0x3350
-#define CPU_3430	0x3430
-#define CPU_3630	0x3630
-#define CPU_AM35XX	0x3500
-
-/**
- * Define CPU revisions
- */
-#define	cpu_revision(cpu,rev)	(((cpu) << 16) | (rev))
-
-#define OMAP34XX_ES1		cpu_revision(CPU_3430, 0)
-#define OMAP34XX_ES2		cpu_revision(CPU_3430, 1)
-#define OMAP34XX_ES2_1		cpu_revision(CPU_3430, 2)
-#define OMAP34XX_ES3		cpu_revision(CPU_3430, 3)
-#define OMAP34XX_ES3_1		cpu_revision(CPU_3430, 4)
-
-#define AM335X_ES1_0		cpu_revision(CPU_3350, 0)
-#define AM335X_ES2_0		cpu_revision(CPU_3350, 1)
-#define AM335X_ES2_1		cpu_revision(CPU_3350, 2)
-
-#define OMAP36XX_ES1		cpu_revision(CPU_3630, 0)
-#define OMAP36XX_ES1_1		cpu_revision(CPU_3630, 1)
-#define OMAP36XX_ES1_2		cpu_revision(CPU_3630, 2)
-
-#define GPMC_MUXED		1
-#define GPMC_NONMUXED		0
-
-#define TYPE_NAND		0x800	/* bit pos for nand in gpmc reg */
-#define TYPE_NOR		0x000
-#define TYPE_ONENAND		0x800
-
-#define WIDTH_8BIT		0x0000
-#define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
-
-#define TST_DEVICE              0x0
-#define EMU_DEVICE              0x1
-#define HS_DEVICE               0x2
-#define GP_DEVICE               0x3
-
-/**
- * Hawkeye definitions to identify silicon families
- */
-#define OMAP_HAWKEYE_34XX	0xB7AE /* OMAP34xx */
-#define OMAP_HAWKEYE_36XX	0xB891 /* OMAP36xx */
-#define OMAP_HAWKEYE_335X	0xB944 /* AM335x */
-#define OMAP_HAWKEYE_AM35XX	0xb868 /* AM35xx */
-
-/** These are implemented by the System specific code in omapX-generic.c */
-u32 get_cpu_type(void);
-u32 get_cpu_rev(void);
-u32 get_sdr_cs_size(u32 offset);
-u32 get_sdr_cs1_base(void);
-u32 get_sysboot_value(void);
-u32 get_boot_type(void);
-u32 get_device_type(void);
-
-#endif /*__ASM_ARCH_SYS_INFO_H_ */
diff --git a/arch/arm/mach-omap/include/mach/syslib.h b/arch/arm/mach-omap/include/mach/syslib.h
deleted file mode 100644
index fe8d71d802..0000000000
--- a/arch/arm/mach-omap/include/mach/syslib.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**
- * @file
- * @brief These Apis are OMAP independent support functions
- *
- * Implemented by arch/arm/mach-omap/syslib.c
- *
- * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_OMAP_SYSLIB_H_
-#define __ASM_ARCH_OMAP_SYSLIB_H_
-#include <io.h>
-
-/** System Independent functions */
-
-/**
- * @brief clear & set a value in a bit range for a 32 bit address
- *
- * @param[in] addr Address to set/read from
- * @param[in] start_bit Where to put the value
- * @param[in] num_bits number of bits the value should be set
- * @param[in] value the value to set
- *
- * @return void
- */
-static inline void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
-{
-	u32 tmp, msk = 0;
-	msk = 1 << num_bits;
-	--msk;
-	tmp = readl(addr) & ~(msk << start_bit);
-	tmp |=  value << start_bit;
-	writel(tmp, addr);
-}
-
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
-void sdelay(unsigned long loops);
-
-#endif /* __ASM_ARCH_OMAP_SYSLIB_H_ */
diff --git a/arch/arm/mach-omap/include/mach/timers.h b/arch/arm/mach-omap/include/mach/timers.h
deleted file mode 100644
index 8e4cb929ba..0000000000
--- a/arch/arm/mach-omap/include/mach/timers.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/**
- * @file
- * @brief This defines the Register defines for OMAP GPTimers and Sync32 timers.
- *
- * FileName: include/asm-arm/arch-omap/timers.h
- *
- * Originally from Linux kernel:
- * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * Copyright (C) 2007 Texas Instruments, <www.ti.com>
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_GPT_H
-#define __ASM_ARCH_GPT_H
-
-/** General Purpose timer regs offsets (32 bit regs) */
-#define TIDR			0x0      /* r */
-#define TIOCP_CFG		0x10     /* rw */
-#define TISTAT			0x14     /* r */
-#define TISR			0x18     /* rw */
-#define TIER			0x1C     /* rw */
-#define TWER			0x20     /* rw */
-#define TCLR			0x24     /* rw */
-#define TCRR			0x28     /* rw */
-#define TLDR			0x2C     /* rw */
-#define TTGR			0x30     /* rw */
-#define TWPS			0x34     /* r */
-#define TMAR			0x38     /* rw */
-#define TCAR1			0x3c     /* r */
-#define TSICR			0x40     /* rw */
-#define TCAR2			0x44     /* r */
-/* Enable sys_clk NO-prescale /1 */
-#define GPT_EN			((0 << 2) | (0x1 << 1) | (0x1 << 0))
-
-#endif /*__ASM_ARCH_GPT_H */
diff --git a/arch/arm/mach-omap/include/mach/wdt.h b/arch/arm/mach-omap/include/mach/wdt.h
deleted file mode 100644
index 9a5288d386..0000000000
--- a/arch/arm/mach-omap/include/mach/wdt.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/**
- * @file
- * @brief This file contains the Watchdog timer specific register definitions
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_OMAP_WDT_H
-#define __ASM_ARCH_OMAP_WDT_H
-
-/** Watchdog Register defines */
-#define OMAP3_WDT_REG(REGNAME)	(OMAP3_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME)
-#define AM33XX_WDT_REG(REGNAME)	(AM33XX_WDT_BASE + OMAP_WDT_##REGNAME)
-
-#define OMAP_WDT_WIDR		(0x000)
-#define OMAP_WDT_SYSCONFIG	(0x010)
-#define OMAP_WDT_WD_SYSSTATUS	(0x014)
-#define OMAP_WDT_WISR		(0x018)
-#define OMAP_WDT_WIER		(0x01C)
-#define OMAP_WDT_WCLR		(0x024)
-#define OMAP_WDT_WCRR		(0x028)
-#define OMAP_WDT_WLDR		(0x02C)
-#define OMAP_WDT_WTGR		(0x030)
-#define OMAP_WDT_WWPS		(0x034)
-#define OMAP_WDT_WSPR		(0x048)
-
-/* Unlock Code for Watchdog timer to disable the same */
-#define WDT_DISABLE_CODE1	0xAAAA
-#define WDT_DISABLE_CODE2	0x5555
-
-#endif /* __ASM_ARCH_OMAP_WDT_H */
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 03b866c28e..f66316a536 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -32,13 +32,13 @@
 
 #include <common.h>
 #include <io.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap3-generic.h>
-#include <mach/clocks.h>
-#include <mach/omap3-clock.h>
-#include <mach/timers.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap3-generic.h>
+#include <mach/omap/clocks.h>
+#include <mach/omap/omap3-clock.h>
+#include <mach/omap/timers.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
 
 #define S32K_CR			(OMAP3_32KTIMER_BASE + 0x10)
 
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 3f6a346277..8230b37619 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -32,18 +32,17 @@
 #include <init.h>
 #include <io.h>
 #include <restart.h>
-#include <mach/omap3-silicon.h>
-#include <mach/gpmc.h>
-#include <mach/generic.h>
-#include <mach/sdrc.h>
-#include <mach/control.h>
-#include <mach/omap3-smx.h>
-#include <mach/clocks.h>
-#include <mach/omap3-clock.h>
-#include <mach/wdt.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/omap3-generic.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/sdrc.h>
+#include <mach/omap/control.h>
+#include <mach/omap/omap3-smx.h>
+#include <mach/omap/clocks.h>
+#include <mach/omap/omap3-clock.h>
+#include <mach/omap/sys_info.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/omap3-generic.h>
 #include <reset_source.h>
 
 /**
@@ -379,19 +378,10 @@ static void secureworld_exit(void)
  */
 static void watchdog_init(void)
 {
-	int pending = 1;
-
 	sr32(OMAP3_CM_REG(FCLKEN_WKUP), 5, 1, 1);
 	sr32(OMAP3_CM_REG(ICLKEN_WKUP), 5, 1, 1);
-	wait_on_value((0x1 << 5), 0x20, OMAP3_CM_REG(IDLEST_WKUP), 5);
-
-	writel(WDT_DISABLE_CODE1, OMAP3_WDT_REG(WSPR));
-
-	do {
-		pending = readl(OMAP3_WDT_REG(WWPS));
-	} while (pending);
 
-	writel(WDT_DISABLE_CODE2, OMAP3_WDT_REG(WSPR));
+	omap_watchdog_disable(IOMEM(OMAP3_MPU_WDTIMER_BASE));
 }
 
 /**
@@ -485,8 +475,7 @@ static int omap3_bootsource(void)
 		src = BOOTSOURCE_UNKNOWN;
 	}
 
-	bootsource_set(src);
-	bootsource_set_instance(0);
+	bootsource_set_raw(src, 0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap/omap3_xload_usb.c b/arch/arm/mach-omap/omap3_xload_usb.c
index ac6a434643..01e958da6f 100644
--- a/arch/arm/mach-omap/omap3_xload_usb.c
+++ b/arch/arm/mach-omap/omap3_xload_usb.c
@@ -19,8 +19,8 @@
 #include <common.h>
 #include <io.h>
 #include <malloc.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap3-generic.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap3-generic.h>
 
 static void __iomem *omap3_usb_base = (void __iomem *)OMAP3_MUSB0_BASE;
 
diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
index 72f72a17a1..aa314b70ec 100644
--- a/arch/arm/mach-omap/omap4_clock.c
+++ b/arch/arm/mach-omap/omap4_clock.c
@@ -1,9 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <io.h>
-#include <mach/syslib.h>
-#include <mach/omap4-silicon.h>
-#include <mach/clocks.h>
-#include <mach/omap4-clock.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/clocks.h>
+#include <mach/omap/omap4-clock.h>
 
 #define LDELAY	12000000
 
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 848a664064..10190b152b 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -1,16 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <bootsource.h>
 #include <init.h>
 #include <restart.h>
 #include <io.h>
-#include <mach/omap4-clock.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4-mux.h>
-#include <mach/syslib.h>
-#include <mach/generic.h>
-#include <mach/gpmc.h>
-#include <mach/omap4_rom_usb.h>
-#include <mach/omap4-generic.h>
+#include <mach/omap/omap4-clock.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4-mux.h>
+#include <mach/omap/syslib.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/omap4_rom_usb.h>
+#include <mach/omap/omap4-generic.h>
 
 /*
  *  The following several lines are taken from U-Boot to support
@@ -63,18 +65,6 @@ void omap4_set_warmboot_order(u32 *device_list)
 	writel(OMAP44XX_SAR_CH_START, OMAP44XX_SAR_CH_ADDRESS);
 }
 
-#define WATCHDOG_WSPR	0x48
-#define WATCHDOG_WWPS	0x34
-
-static void wait_for_command_complete(void)
-{
-	int pending = 1;
-
-	do {
-		pending = readl(OMAP44XX_WDT2_BASE + WATCHDOG_WWPS);
-	} while (pending);
-}
-
 /* EMIF */
 #define EMIF_MOD_ID_REV			0x0000
 #define EMIF_STATUS			0x0004
@@ -431,38 +421,29 @@ unsigned int omap4_revision(void)
 		return OMAP4430_ES1_0;
 	case MIDR_CORTEX_A9_R1P2:
 		switch (readl(CONTROL_ID_CODE)) {
-		case OMAP4_CONTROL_ID_CODE_ES2_0:
-			return OMAP4430_ES2_0;
-			break;
 		case OMAP4_CONTROL_ID_CODE_ES2_1:
 			return OMAP4430_ES2_1;
-			break;
 		case OMAP4_CONTROL_ID_CODE_ES2_2:
 			return OMAP4430_ES2_2;
-			break;
 		default:
-			return OMAP4430_ES2_0;
 			break;
 		}
-		break;
+		return OMAP4430_ES2_0;
 	case MIDR_CORTEX_A9_R1P3:
 		return OMAP4430_ES2_3;
-		break;
 	case MIDR_CORTEX_A9_R2P10:
 		switch (readl(CONTROL_ID_CODE)) {
 		case OMAP4460_CONTROL_ID_CODE_ES1_1:
 			return OMAP4460_ES1_1;
-			break;
-		case OMAP4460_CONTROL_ID_CODE_ES1_0:
 		default:
-			return OMAP4460_ES1_0;
 			break;
 		}
-		break;
+		return OMAP4460_ES1_0;
 	default:
-		return OMAP4430_SILICON_ID_INVALID;
 		break;
 	}
+
+	return OMAP4430_SILICON_ID_INVALID;
 }
 
 /*
@@ -470,14 +451,8 @@ unsigned int omap4_revision(void)
  */
 static int watchdog_init(void)
 {
-	void __iomem *wd2_base = (void *)OMAP44XX_WDT2_BASE;
-
-	if (!cpu_is_omap4())
-		return 0;
-
-	writel(WD_UNLOCK1, wd2_base + WATCHDOG_WSPR);
-	wait_for_command_complete();
-	writel(WD_UNLOCK2, wd2_base + WATCHDOG_WSPR);
+	if (cpu_is_omap4())
+		omap_watchdog_disable(IOMEM(OMAP44XX_WDT2_BASE));
 
 	return 0;
 }
@@ -523,8 +498,7 @@ static int omap4_bootsource(void)
 		src = BOOTSOURCE_UNKNOWN;
 	}
 
-	bootsource_set(src);
-	bootsource_set_instance(0);
+	bootsource_set_raw(src, 0);
 
 	omap_vector_init();
 
diff --git a/arch/arm/mach-omap/omap4_rom_usb.c b/arch/arm/mach-omap/omap4_rom_usb.c
index 0b31240590..01c5565a68 100644
--- a/arch/arm/mach-omap/omap4_rom_usb.c
+++ b/arch/arm/mach-omap/omap4_rom_usb.c
@@ -31,9 +31,9 @@
  */
 
 #include <common.h>
-#include <mach/omap4-silicon.h>
-#include <mach/omap4_rom_usb.h>
-#include <mach/generic.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/omap4_rom_usb.h>
+#include <mach/omap/generic.h>
 #include <init.h>
 
 static struct omap4_usbboot omap4_usbboot_data;
@@ -46,6 +46,9 @@ int omap4_usbboot_open(void)
 	int n;
 	u32 base;
 
+	if (omap4_usbboot_ready())
+		return 0;
+
 	if (omap4_revision() >= OMAP4460_ES1_0)
 		base = PUBLIC_API_BASE_4460;
 	else
@@ -82,7 +85,6 @@ int omap4_usbboot_open(void)
 	omap4_usbboot_puts("USB communications initialized\n");
 	return 0;
 }
-core_initcall(omap4_usbboot_open);
 
 int omap4_usbboot_ready(void){
 	return omap4_usbboot_data.ready;
diff --git a/arch/arm/mach-omap/omap4_twl6030_mmc.c b/arch/arm/mach-omap/omap4_twl6030_mmc.c
index 67a9a5d6b5..c5fa0e77aa 100644
--- a/arch/arm/mach-omap/omap4_twl6030_mmc.c
+++ b/arch/arm/mach-omap/omap4_twl6030_mmc.c
@@ -17,7 +17,7 @@
 #include <io.h>
 
 #include <mfd/twl6030.h>
-#include <mach/omap4_twl6030_mmc.h>
+#include <mach/omap/omap4_twl6030_mmc.h>
 
 /* MMC voltage */
 #define OMAP4_CONTROL_PBIASLITE			0x4A100600
diff --git a/arch/arm/mach-omap/omap_devices.c b/arch/arm/mach-omap/omap_devices.c
index f577fa6ea7..3ade3225df 100644
--- a/arch/arm/mach-omap/omap_devices.c
+++ b/arch/arm/mach-omap/omap_devices.c
@@ -1,8 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <driver.h>
-#include <platform_data/serial-ns16550.h>
 #include <asm/armlinux.h>
 
-#include <mach/omap3-devices.h>
+#include <mach/omap/omap3-devices.h>
 
 void omap_add_ram0(resource_size_t size)
 {
@@ -14,13 +15,37 @@ void omap_add_sram0(resource_size_t base, resource_size_t size)
 	add_mem_device("sram0", base, size, IORESOURCE_MEM_WRITEABLE);
 }
 
-static struct NS16550_plat serial_plat = {
-	.clock = 48000000,      /* 48MHz (APLL96/2) */
-	.shift = 2,
+struct device *omap_add_uart(int id, unsigned long base)
+{
+	return add_generic_device("omap-uart", id, NULL, base, 1024,
+				  IORESOURCE_MEM | IORESOURCE_MEM_8BIT, NULL);
+}
+
+#if defined(CONFIG_DRIVER_VIDEO_OMAP)
+static struct resource omapfb_resources[] = {
+	{
+		.name	= "omap4_dss",
+		.start	= 0x48040000,
+		.end	= 0x48040000 + 512 - 1,
+		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+	}, {
+		.name	= "omap4_dispc",
+		.start	= 0x48041000,
+		.end	= 0x48041000 + 3072 - 1,
+		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+	},
 };
 
-struct device_d *omap_add_uart(int id, unsigned long base)
+struct device *omap_add_display(struct omapfb_platform_data *o_pdata)
 {
-	return add_generic_device("omap-uart", id, NULL, base, 1024,
-				  IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat);
+	return add_generic_device_res("omap_fb", -1,
+				      omapfb_resources,
+				      ARRAY_SIZE(omapfb_resources),
+				      o_pdata);
+}
+#else
+struct device *omap_add_display(struct omapfb_platform_data *o_pdata)
+{
+	return NULL;
 }
+#endif
diff --git a/arch/arm/mach-omap/omap_fb.c b/arch/arm/mach-omap/omap_fb.c
deleted file mode 100644
index ae318d85fe..0000000000
--- a/arch/arm/mach-omap/omap_fb.c
+++ /dev/null
@@ -1,34 +0,0 @@
-#include <driver.h>
-#include <common.h>
-#include <linux/ioport.h>
-#include <mach/omap-fb.h>
-
-#if defined(CONFIG_DRIVER_VIDEO_OMAP)
-static struct resource omapfb_resources[] = {
-	{
-		.name	= "omap4_dss",
-		.start	= 0x48040000,
-		.end	= 0x48040000 + 512 - 1,
-		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
-	}, {
-		.name	= "omap4_dispc",
-		.start	= 0x48041000,
-		.end	= 0x48041000 + 3072 - 1,
-		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
-	},
-};
-
-struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata)
-{
-	return add_generic_device_res("omap_fb", -1,
-				      omapfb_resources,
-				      ARRAY_SIZE(omapfb_resources),
-				      o_pdata);
-}
-#else
-struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata)
-{
-	return NULL;
-}
-#endif
-EXPORT_SYMBOL(omap_add_display);
diff --git a/arch/arm/mach-omap/omap_generic.c b/arch/arm/mach-omap/omap_generic.c
index a1c0aeb595..99e14fb540 100644
--- a/arch/arm/mach-omap/omap_generic.c
+++ b/arch/arm/mach-omap/omap_generic.c
@@ -22,14 +22,14 @@
 #include <malloc.h>
 #include <libfile.h>
 #include <linux/stat.h>
-#include <mach/gpmc.h>
-#include <mach/generic.h>
-#include <mach/am33xx-silicon.h>
-#include <mach/omap3-silicon.h>
-#include <mach/omap4-silicon.h>
-#include <mach/am33xx-generic.h>
-#include <mach/omap3-generic.h>
-#include <mach/omap4-generic.h>
+#include <mach/omap/gpmc.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/am33xx-silicon.h>
+#include <mach/omap/omap3-silicon.h>
+#include <mach/omap/omap4-silicon.h>
+#include <mach/omap/am33xx-generic.h>
+#include <mach/omap/omap3-generic.h>
+#include <mach/omap/omap4-generic.h>
 
 void __iomem *omap_gpmc_base;
 
@@ -70,6 +70,24 @@ void __noreturn omap_start_barebox(void *barebox)
 	hang();
 }
 
+#define OMAP_WDT_WWPS		0x34
+#define OMAP_WDT_WSPR		0x48
+#define WDT_DISABLE_CODE1	0xaaaa
+#define WDT_DISABLE_CODE2	0x5555
+
+void omap_watchdog_disable(const void __iomem *wdt)
+{
+	/* WDT is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	__raw_writel(WDT_DISABLE_CODE1, wdt + OMAP_WDT_WSPR);
+
+	do {
+	} while (__raw_readl(wdt + OMAP_WDT_WWPS));
+
+	__raw_writel(WDT_DISABLE_CODE2, wdt + OMAP_WDT_WSPR);
+}
+
 #ifdef CONFIG_BOOTM
 static int do_bootm_omap_barebox(struct image_data *data)
 {
@@ -95,6 +113,9 @@ static struct image_handler omap_barebox_handler = {
 
 static int omap_bootm_barebox(void)
 {
+	if (!cpu_is_omap())
+		return 0;
+
 	return register_image_handler(&omap_barebox_handler);
 }
 device_initcall(omap_bootm_barebox);
@@ -123,6 +144,9 @@ static int omap_env_init(void)
 	struct cdev *cdev;
 	const char *rootpath;
 
+	if (!cpu_is_omap())
+		return 0;
+
 	if (bootsource_get() != BOOTSOURCE_MMC)
 		return 0;
 
@@ -156,6 +180,7 @@ static int omap_env_init(void)
 								partname);
 	default_environment_path_set(envpath);
 
+	free(envpath);
 out:
 	free(partname);
 
@@ -185,7 +210,7 @@ static int omap_init(void)
 	if (root) {
 		__omap_cpu_type = omap_soc_from_dt();
 		if (!__omap_cpu_type)
-			hang();
+			return 0;
 	}
 
 	if (cpu_is_omap3())
diff --git a/arch/arm/mach-omap/syslib.c b/arch/arm/mach-omap/syslib.c
index 42da348c5a..f8fad243c6 100644
--- a/arch/arm/mach-omap/syslib.c
+++ b/arch/arm/mach-omap/syslib.c
@@ -25,7 +25,7 @@
 #include <config.h>
 #include <common.h>
 #include <io.h>
-#include <mach/syslib.h>
+#include <mach/omap/syslib.h>
 
 /**
  * @brief simple spin loop
@@ -52,19 +52,16 @@ void sdelay(unsigned long loops)
  * @param[in] read_addr  address to read from
  * @param[in] bound max iterations
  *
- * @return 1 if match_value is found, else if bound iterations reached,
+ * @return non zero if match_value is found, else if bound iterations reached,
  *         returns 0
  */
 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
 {
-	u32 i = 0, val;
 	do {
-		++i;
-		val = readl(read_addr) & read_bit_mask;
+		u32 val = readl(read_addr) & read_bit_mask;
 		if (val == match_value)
-			return 1;
-		if (i == bound)
-			return 0;
-	} while (1);
-}
+			break;
+	} while (--bound);
 
+	return bound;
+}
diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c
index 47aa8275b9..e632b53788 100644
--- a/arch/arm/mach-omap/xload.c
+++ b/arch/arm/mach-omap/xload.c
@@ -1,6 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <bootsource.h>
-#include <partition.h>
 #include <nand.h>
 #include <init.h>
 #include <driver.h>
@@ -12,12 +13,13 @@
 #include <malloc.h>
 #include <filetype.h>
 #include <xymodem.h>
-#include <mach/generic.h>
-#include <mach/am33xx-generic.h>
-#include <mach/omap3-generic.h>
+#include <mach/omap/generic.h>
+#include <mach/omap/am33xx-generic.h>
+#include <mach/omap/omap3-generic.h>
 #include <net.h>
 #include <environment.h>
 #include <dhcp.h>
+#include <mtd/mtd-peb.h>
 
 struct omap_barebox_part *barebox_part;
 
@@ -30,29 +32,6 @@ static struct omap_barebox_part default_part = {
 	.nor_size = SZ_1M,
 };
 
-static void *read_image_head(const char *name)
-{
-	void *header = xmalloc(ARM_HEAD_SIZE);
-	struct cdev *cdev;
-	int ret;
-
-	cdev = cdev_open(name, O_RDONLY);
-	if (!cdev) {
-		printf("failed to open %s\n", name);
-		return NULL;
-	}
-
-	ret = cdev_read(cdev, header, ARM_HEAD_SIZE, 0, 0);
-	cdev_close(cdev);
-
-	if (ret != ARM_HEAD_SIZE) {
-		printf("failed to read from %s\n", name);
-		return NULL;
-	}
-
-	return header;
-}
-
 static unsigned int get_image_size(void *head)
 {
 	unsigned int ret = 0;
@@ -65,57 +44,67 @@ static unsigned int get_image_size(void *head)
 	return ret;
 }
 
-static void *read_mtd_barebox(const char *partition)
+static void *read_mtd_barebox(const char *part, unsigned int start, unsigned int size)
 {
 	int ret;
-	int size;
-	void *to, *header;
+	void *to;
 	struct cdev *cdev;
+	struct mtd_info *mtd;
+	unsigned int ps, pe;
 
-	header = read_image_head(partition);
-	if (header == NULL)
-		return NULL;
-
-	size = get_image_size(header);
-	if (!size) {
-		printf("failed to get image size\n");
+	if (!IS_ENABLED(CONFIG_MTD)) {
+		printf("Cannot load from nand/nor: MTD support is disabled\n");
 		return NULL;
 	}
 
-	to = xmalloc(size);
-
-	cdev = cdev_open(partition, O_RDONLY);
+	cdev = cdev_open_by_name(part, O_RDONLY);
 	if (!cdev) {
 		printf("failed to open partition\n");
 		return NULL;
 	}
 
-	ret = cdev_read(cdev, to, size, 0, 0);
-	if (ret != size) {
-		printf("failed to read from partition\n");
+	mtd = cdev->mtd;
+	if (!mtd)
+		return NULL;
+
+	if (mtd_mod_by_eb(start, mtd) != 0) {
+		printf("Start must be eraseblock aligned\n");
 		return NULL;
 	}
 
+	to = xmalloc(size);
+
+	ps = mtd_div_by_eb(start, mtd);
+	pe = mtd_div_by_eb(start + size, mtd);
+	ret = mtd_peb_read_file(mtd, ps, pe, to, size);
+	if (ret) {
+		printf("Can't read image from %s: %d\n", part, ret);
+		goto err;
+	}
+
+	size = get_image_size(to);
+	if (!size) {
+		printf("failed to get image size\n");
+		goto err;
+	}
+
 	return to;
+
+err:
+	free(to);
+	return NULL;
 }
 
 static void *omap_xload_boot_nand(struct omap_barebox_part *part)
 {
 	void *to;
 
-	devfs_add_partition("nand0", part->nand_offset, part->nand_size,
-					DEVFS_PARTITION_FIXED, "x");
-	dev_add_bb_dev("x", "bbx");
-
-	to = read_mtd_barebox("bbx");
+	to = read_mtd_barebox("nand0", part->nand_offset, part->nand_size);
 	if (to == NULL && part->nand_bkup_size != 0) {
 		printf("trying to load image from backup partition.\n");
-		devfs_add_partition("nand0", part->nand_bkup_offset,
-				part->nand_bkup_size,
-				DEVFS_PARTITION_FIXED, "x_bkup");
-		dev_add_bb_dev("x_bkup", "bbx_bkup");
 
-		to = read_mtd_barebox("bbx_bkup");
+		to = read_mtd_barebox("nand0", part->nand_bkup_offset,
+				part->nand_bkup_size);
 	}
 
 	return to;
@@ -125,7 +114,6 @@ static void *omap_xload_boot_mmc(void)
 {
 	int ret;
 	void *buf;
-	int len;
 	const char *diskdev;
 	char *partname;
 
@@ -147,9 +135,9 @@ static void *omap_xload_boot_mmc(void)
 
 	free(partname);
 
-	buf = read_file("/barebox.bin", &len);
+	buf = read_file("/barebox.bin", NULL);
 	if (!buf)
-		buf = read_file("/boot/barebox.bin", &len);
+		buf = read_file("/boot/barebox.bin", NULL);
 	if (!buf) {
 		printf("could not read barebox.bin from sd card\n");
 		return NULL;
@@ -160,16 +148,12 @@ static void *omap_xload_boot_mmc(void)
 
 static void *omap_xload_boot_spi(struct omap_barebox_part *part)
 {
-	devfs_add_partition("m25p0", part->nor_offset, part->nor_size,
-					DEVFS_PARTITION_FIXED, "x");
-
-	return read_mtd_barebox("x");
+	return read_mtd_barebox("m25p0", part->nor_offset, part->nor_size);
 }
 
 static void *omap4_xload_boot_usb(void){
 	int ret;
 	void *buf;
-	int len;
 
 	ret = mount("omap4_usbboot", "omap4_usbbootfs", "/", NULL);
 	if (ret) {
@@ -177,7 +161,7 @@ static void *omap4_xload_boot_usb(void){
 		return NULL;
 	}
 
-	buf = read_file("/barebox.bin", &len);
+	buf = read_file("/barebox.bin", NULL);
 	if (!buf)
 		printf("could not read barebox.bin from omap4_usbbootfs\n");
 
@@ -188,7 +172,6 @@ static void *omap_serial_boot(void){
 	struct console_device *cdev;
 	int ret;
 	void *buf;
-	int len;
 	int fd;
 
 	/* need temporary place to store file */
@@ -216,7 +199,7 @@ static void *omap_serial_boot(void){
 		return NULL;
 	}
 
-	buf = read_file("/barebox.bin", &len);
+	buf = read_file("/barebox.bin", NULL);
 	if (!buf)
 		printf("could not read barebox.bin from serial\n");
 
@@ -229,7 +212,6 @@ static void *am33xx_net_boot(void)
 {
 	void *buf = NULL;
 	int err;
-	int len;
 	struct dhcp_req_param dhcp_param;
 	const char *bootfile;
 	IPaddr_t ip;
@@ -289,7 +271,7 @@ static void *am33xx_net_boot(void)
 
 	file = basprintf("%s/%s", TFTP_MOUNT, bootfile);
 
-	buf = read_file(file, &len);
+	buf = read_file(file, NULL);
 	if (!buf)
 		printf("could not read %s.\n", bootfile);
 
@@ -373,6 +355,9 @@ int omap_set_barebox_part(struct omap_barebox_part *part)
 
 static int omap_set_xload(void)
 {
+	if (!cpu_is_omap())
+		return 0;
+
 	barebox_main = omap_xload;
 
 	return 0;
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index fd9084f83e..a506c8e892 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_PXA
 
 config ARCH_TEXT_BASE
@@ -18,7 +20,6 @@ config ARCH_PXA3XX
        bool
        select CPU_XSC3
        select HAVE_CLK
-       select CLKDEV_LOOKUP
        select COMMON_CLK
 
 config ARCH_PXA310
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 0c3219807b..9249c8fe14 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += clocksource.o
 obj-y += common.o
 obj-y += gpio.o
diff --git a/arch/arm/mach-pxa/clocksource.c b/arch/arm/mach-pxa/clocksource.c
index ebfe6f1c33..3bc95827d8 100644
--- a/arch/arm/mach-pxa/clocksource.c
+++ b/arch/arm/mach-pxa/clocksource.c
@@ -28,6 +28,7 @@ static struct clocksource cs = {
 	.read	= pxa_clocksource_read,
 	.mask	= 0xffffffff,
 	.shift	= 20,
+	.priority = 80,
 };
 
 static int clocksource_init(void)
diff --git a/arch/arm/mach-pxa/common.c b/arch/arm/mach-pxa/common.c
index 5b980cb81b..e0bf1de461 100644
--- a/arch/arm/mach-pxa/common.c
+++ b/arch/arm/mach-pxa/common.c
@@ -15,7 +15,7 @@
 #include <common.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa/pxa-regs.h>
 #include <asm/io.h>
 
 #define OSMR3	0x40A0000C
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 16f45273af..b5d098bd91 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -14,38 +14,38 @@
  */
 #include <common.h>
 #include <driver.h>
-#include <mach/devices.h>
-#include <mach/pxafb.h>
+#include <mach/pxa/devices.h>
+#include <mach/pxa/pxafb.h>
 
-static inline struct device_d *pxa_add_device(char *name, int id, void *base,
+static inline struct device *pxa_add_device(char *name, int id, void *base,
 					      int size, void *pdata)
 {
 	return add_generic_device(name, id, NULL, (resource_size_t)base, size,
 				  IORESOURCE_MEM, pdata);
 }
 
-struct device_d *pxa_add_i2c(void *base, int id,
+struct device *pxa_add_i2c(void *base, int id,
 			     struct i2c_platform_data *pdata)
 {
 	return pxa_add_device("i2c-pxa", id, base, 0x1000, pdata);
 }
 
-struct device_d *pxa_add_uart(void *base, int id)
+struct device *pxa_add_uart(void *base, int id)
 {
 	return pxa_add_device("pxa_serial", id, base, 0x1000, NULL);
 }
 
-struct device_d *pxa_add_fb(void *base, struct pxafb_platform_data *pdata)
+struct device *pxa_add_fb(void *base, struct pxafb_platform_data *pdata)
 {
 	return pxa_add_device("pxafb", -1, base, 0x1000, pdata);
 }
 
-struct device_d *pxa_add_mmc(void *base, int id, void *pdata)
+struct device *pxa_add_mmc(void *base, int id, void *pdata)
 {
 	return pxa_add_device("pxa-mmc", id, base, 0x1000, pdata);
 }
 
-struct device_d *pxa_add_pwm(void *base, int id)
+struct device *pxa_add_pwm(void *base, int id)
 {
 	return pxa_add_device("pxa_pwm", id, base, 0x10, NULL);
 }
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c
index ebda6bbe2a..130faa404b 100644
--- a/arch/arm/mach-pxa/gpio.c
+++ b/arch/arm/mach-pxa/gpio.c
@@ -14,7 +14,7 @@
 #include <errno.h>
 #include <gpio.h>
 
-#include <mach/gpio.h>
+#include <mach/pxa/gpio.h>
 #include <asm/io.h>
 
 int pxa_last_gpio;
diff --git a/arch/arm/mach-pxa/include/mach/clock.h b/arch/arm/mach-pxa/include/mach/clock.h
deleted file mode 100644
index f86152f7af..0000000000
--- a/arch/arm/mach-pxa/include/mach/clock.h
+++ /dev/null
@@ -1,19 +0,0 @@
-
-/*
- * clock.h - definitions of the PXA clock functions
- *
- * Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
- *
- * This file is released under the GPLv2
- *
- */
-
-#ifndef __MACH_CLOCK_H
-#define __MACH_CLOCK_H
-
-unsigned long pxa_get_uartclk(void);
-unsigned long pxa_get_mmcclk(void);
-unsigned long pxa_get_lcdclk(void);
-unsigned long pxa_get_pwmclk(void);
-
-#endif	/* !__MACH_CLOCK_H */
diff --git a/arch/arm/mach-pxa/include/mach/devices.h b/arch/arm/mach-pxa/include/mach/devices.h
deleted file mode 100644
index 0f2e38dbae..0000000000
--- a/arch/arm/mach-pxa/include/mach/devices.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <i2c/i2c.h>
-#include <mach/pxafb.h>
-
-struct device_d *pxa_add_i2c(void *base, int id,
-			     struct i2c_platform_data *pdata);
-struct device_d *pxa_add_uart(void *base, int id);
-struct device_d *pxa_add_fb(void *base, struct pxafb_platform_data *pdata);
-struct device_d *pxa_add_mmc(void *base, int id, void *pdata);
-struct device_d *pxa_add_pwm(void *base, int id);
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
deleted file mode 100644
index e6724e1caf..0000000000
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/gpio.h
- *
- * PXA GPIO wrappers for arch-neutral GPIO calls
- *
- * Written by Philipp Zabel <philipp.zabel@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_PXA_GPIO_H
-#define __ASM_ARCH_PXA_GPIO_H
-
-#include <mach/hardware.h>
-
-#define GPIO_REGS_VIRT	(0x40E00000)
-
-#define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
-#define GPIO_REG(x)	(*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
-
-/* GPIO Pin Level Registers */
-#define GPLR0		GPIO_REG(BANK_OFF(0) + 0x00)
-#define GPLR1		GPIO_REG(BANK_OFF(1) + 0x00)
-#define GPLR2		GPIO_REG(BANK_OFF(2) + 0x00)
-#define GPLR3		GPIO_REG(BANK_OFF(3) + 0x00)
-
-/* GPIO Pin Direction Registers */
-#define GPDR0		GPIO_REG(BANK_OFF(0) + 0x0c)
-#define GPDR1		GPIO_REG(BANK_OFF(1) + 0x0c)
-#define GPDR2		GPIO_REG(BANK_OFF(2) + 0x0c)
-#define GPDR3		GPIO_REG(BANK_OFF(3) + 0x0c)
-
-/* GPIO Pin Output Set Registers */
-#define GPSR0		GPIO_REG(BANK_OFF(0) + 0x18)
-#define GPSR1		GPIO_REG(BANK_OFF(1) + 0x18)
-#define GPSR2		GPIO_REG(BANK_OFF(2) + 0x18)
-#define GPSR3		GPIO_REG(BANK_OFF(3) + 0x18)
-
-/* GPIO Pin Output Clear Registers */
-#define GPCR0		GPIO_REG(BANK_OFF(0) + 0x24)
-#define GPCR1		GPIO_REG(BANK_OFF(1) + 0x24)
-#define GPCR2		GPIO_REG(BANK_OFF(2) + 0x24)
-#define GPCR3		GPIO_REG(BANK_OFF(3) + 0x24)
-
-/* GPIO Rising Edge Detect Registers */
-#define GRER0		GPIO_REG(BANK_OFF(0) + 0x30)
-#define GRER1		GPIO_REG(BANK_OFF(1) + 0x30)
-#define GRER2		GPIO_REG(BANK_OFF(2) + 0x30)
-#define GRER3		GPIO_REG(BANK_OFF(3) + 0x30)
-
-/* GPIO Falling Edge Detect Registers */
-#define GFER0		GPIO_REG(BANK_OFF(0) + 0x3c)
-#define GFER1		GPIO_REG(BANK_OFF(1) + 0x3c)
-#define GFER2		GPIO_REG(BANK_OFF(2) + 0x3c)
-#define GFER3		GPIO_REG(BANK_OFF(3) + 0x3c)
-
-/* GPIO Edge Detect Status Registers */
-#define GEDR0		GPIO_REG(BANK_OFF(0) + 0x48)
-#define GEDR1		GPIO_REG(BANK_OFF(1) + 0x48)
-#define GEDR2		GPIO_REG(BANK_OFF(2) + 0x48)
-#define GEDR3		GPIO_REG(BANK_OFF(3) + 0x48)
-
-/* GPIO Alternate Function Select Registers */
-#define GAFR0_L		GPIO_REG(0x0054)
-#define GAFR0_U		GPIO_REG(0x0058)
-#define GAFR1_L		GPIO_REG(0x005C)
-#define GAFR1_U		GPIO_REG(0x0060)
-#define GAFR2_L		GPIO_REG(0x0064)
-#define GAFR2_U		GPIO_REG(0x0068)
-#define GAFR3_L		GPIO_REG(0x006C)
-#define GAFR3_U		GPIO_REG(0x0070)
-
-/* More handy macros.  The argument is a literal GPIO number. */
-
-#define GPIO_bit(x)	(1 << ((x) & 0x1f))
-
-#define GPLR(x)		GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
-#define GPDR(x)		GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
-#define GPSR(x)		GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
-#define GPCR(x)		GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
-#define GRER(x)		GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
-#define GFER(x)		GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
-#define GEDR(x)		GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
-#define GAFR(x)		GPIO_REG(0x54 + (((x) & 0x70) >> 2))
-
-
-#define NR_BUILTIN_GPIO 128
-
-#define gpio_to_bank(gpio)	((gpio) >> 5)
-
-#ifdef CONFIG_CPU_PXA26x
-/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
- * as well as their Alternate Function value being '1' for GPIO in GAFRx.
- */
-static inline int __gpio_is_inverted(unsigned gpio)
-{
-	return cpu_is_pxa25x() && gpio > 85;
-}
-#else
-static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
-#endif
-
-/*
- * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
- * function of a GPIO, and GPDRx cannot be altered once configured. It
- * is attributed as "occupied" here (I know this terminology isn't
- * accurate, you are welcome to propose a better one :-)
- */
-static inline int __gpio_is_occupied(unsigned gpio)
-{
-	if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
-		int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
-		int dir = GPDR(gpio) & GPIO_bit(gpio);
-
-		if (__gpio_is_inverted(gpio))
-			return af != 1 || dir == 0;
-		else
-			return af != 0 || dir != 0;
-	} else
-		return GPDR(gpio) & GPIO_bit(gpio);
-}
-#include <plat/gpio.h>
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
deleted file mode 100644
index d968a11880..0000000000
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (c) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
- *
- * Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
- *
- * This file is released under the GPLv2
- *
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#ifdef CONFIG_ARCH_PXA2XX
-#define cpu_is_pxa2xx()	(1)
-#else
-#define cpu_is_pxa2xx()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA25X
-#define cpu_is_pxa25x()	(1)
-#else
-#define cpu_is_pxa25x()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA27X
-#define cpu_is_pxa27x()	(1)
-#else
-#define cpu_is_pxa27x()	(0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA3XX
-#define cpu_is_pxa3xx()	(1)
-# ifdef CONFIG_ARCH_PXA320
-# define cpu_is_pxa320() (1)
-# else
-# define cpu_is_pxa320() (0)
-# endif
-# ifdef CONFIG_ARCH_PXA310
-# define cpu_is_pxa310() (1)
-# else
-# define cpu_is_pxa310() (0)
-# endif
-#else
-#define cpu_is_pxa3xx()	(0)
-#endif
-
-#ifdef __ASSEMBLY__
-#define __REG(x) (x)
-#else
-
-void pxa_clear_reset_source(void);
-
-#endif
-
-#endif	/* !__MACH_HARDWARE_H */
diff --git a/arch/arm/mach-pxa/include/mach/mci_pxa2xx.h b/arch/arm/mach-pxa/include/mach/mci_pxa2xx.h
deleted file mode 100644
index b24bc58afe..0000000000
--- a/arch/arm/mach-pxa/include/mach/mci_pxa2xx.h
+++ /dev/null
@@ -1,10 +0,0 @@
-
-struct mci_host;
-struct device_d;
-
-struct pxamci_platform_data {
-	int gpio_power;
-	int gpio_power_invert;
-	int (*init)(struct mci_host*, struct device_d*);
-	int (*setpower)(struct mci_host*, int on);
-};
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
deleted file mode 100644
index f6a27a20db..0000000000
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ /dev/null
@@ -1,470 +0,0 @@
-#ifndef __ASM_ARCH_MFP_PXA27X_H
-#define __ASM_ARCH_MFP_PXA27X_H
-
-/*
- * NOTE:  for those special-function bidirectional GPIOs, as described
- * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input
- * alternative is preserved, the direction is actually selected by the
- * specific controller, and this should work in most cases.
- */
-
-#include <mach/mfp-pxa2xx.h>
-
-/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN
- * bit is set, regardless of the GPIO configuration
- */
-#define GPIO3_GPIO		MFP_CFG_IN(GPIO3, AF0)
-#define GPIO4_GPIO		MFP_CFG_IN(GPIO4, AF0)
-
-/* GPIO */
-#define GPIO85_GPIO		MFP_CFG_IN(GPIO85, AF0)
-#define GPIO86_GPIO		MFP_CFG_IN(GPIO86, AF0)
-#define GPIO87_GPIO		MFP_CFG_IN(GPIO87, AF0)
-#define GPIO88_GPIO		MFP_CFG_IN(GPIO88, AF0)
-#define GPIO89_GPIO		MFP_CFG_IN(GPIO89, AF0)
-#define GPIO90_GPIO		MFP_CFG_IN(GPIO90, AF0)
-#define GPIO91_GPIO		MFP_CFG_IN(GPIO91, AF0)
-#define GPIO92_GPIO		MFP_CFG_IN(GPIO92, AF0)
-#define GPIO93_GPIO		MFP_CFG_IN(GPIO93, AF0)
-#define GPIO94_GPIO		MFP_CFG_IN(GPIO94, AF0)
-#define GPIO95_GPIO		MFP_CFG_IN(GPIO95, AF0)
-#define GPIO96_GPIO		MFP_CFG_IN(GPIO96, AF0)
-#define GPIO97_GPIO		MFP_CFG_IN(GPIO97, AF0)
-#define GPIO98_GPIO		MFP_CFG_IN(GPIO98, AF0)
-#define GPIO99_GPIO		MFP_CFG_IN(GPIO99, AF0)
-#define GPIO100_GPIO		MFP_CFG_IN(GPIO100, AF0)
-#define GPIO101_GPIO		MFP_CFG_IN(GPIO101, AF0)
-#define GPIO102_GPIO		MFP_CFG_IN(GPIO102, AF0)
-#define GPIO103_GPIO		MFP_CFG_IN(GPIO103, AF0)
-#define GPIO104_GPIO		MFP_CFG_IN(GPIO104, AF0)
-#define GPIO105_GPIO		MFP_CFG_IN(GPIO105, AF0)
-#define GPIO106_GPIO		MFP_CFG_IN(GPIO106, AF0)
-#define GPIO107_GPIO		MFP_CFG_IN(GPIO107, AF0)
-#define GPIO108_GPIO		MFP_CFG_IN(GPIO108, AF0)
-#define GPIO109_GPIO		MFP_CFG_IN(GPIO109, AF0)
-#define GPIO110_GPIO		MFP_CFG_IN(GPIO110, AF0)
-#define GPIO111_GPIO		MFP_CFG_IN(GPIO111, AF0)
-#define GPIO112_GPIO		MFP_CFG_IN(GPIO112, AF0)
-#define GPIO113_GPIO		MFP_CFG_IN(GPIO113, AF0)
-#define GPIO114_GPIO		MFP_CFG_IN(GPIO114, AF0)
-#define GPIO115_GPIO		MFP_CFG_IN(GPIO115, AF0)
-#define GPIO116_GPIO		MFP_CFG_IN(GPIO116, AF0)
-#define GPIO117_GPIO		MFP_CFG_IN(GPIO117, AF0)
-#define GPIO118_GPIO		MFP_CFG_IN(GPIO118, AF0)
-#define GPIO119_GPIO		MFP_CFG_IN(GPIO119, AF0)
-#define GPIO120_GPIO		MFP_CFG_IN(GPIO120, AF0)
-
-/* Crystal and Clock Signals */
-#define GPIO9_HZ_CLK		MFP_CFG_OUT(GPIO9,  AF1, DRIVE_LOW)
-#define GPIO10_HZ_CLK		MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
-#define GPIO11_48_MHz		MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW)
-#define GPIO12_48_MHz		MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW)
-#define GPIO13_CLK_EXT		MFP_CFG_IN(GPIO13, AF1)
-
-/* OS Timer Signals */
-#define GPIO11_EXT_SYNC_0	MFP_CFG_IN(GPIO11, AF1)
-#define GPIO12_EXT_SYNC_1	MFP_CFG_IN(GPIO12, AF1)
-#define GPIO9_CHOUT_0		MFP_CFG_OUT(GPIO9,  AF3, DRIVE_LOW)
-#define GPIO10_CHOUT_1		MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW)
-#define GPIO11_CHOUT_0		MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
-#define GPIO12_CHOUT_1		MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
-
-/* SDRAM and Static Memory I/O Signals */
-#define GPIO20_nSDCS_2		MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH)
-#define GPIO21_nSDCS_3		MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH)
-#define GPIO15_nCS_1		MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
-#define GPIO78_nCS_2		MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
-#define GPIO79_nCS_3		MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
-#define GPIO80_nCS_4		MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
-#define GPIO33_nCS_5		MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
-
-/* Miscellaneous I/O and DMA Signals */
-#define GPIO21_DVAL_0		MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH)
-#define GPIO116_DVAL_0		MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH)
-#define GPIO33_DVAL_1		MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH)
-#define GPIO96_DVAL_1		MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH)
-#define GPIO18_RDY		MFP_CFG_IN(GPIO18, AF1)
-#define GPIO20_DREQ_0		MFP_CFG_IN(GPIO20, AF1)
-#define GPIO115_DREQ_0		MFP_CFG_IN(GPIO115, AF1)
-#define GPIO80_DREQ_1		MFP_CFG_IN(GPIO80, AF1)
-#define GPIO97_DREQ_1		MFP_CFG_IN(GPIO97, AF2)
-#define GPIO85_DREQ_2		MFP_CFG_IN(GPIO85, AF2)
-#define GPIO100_DREQ_2		MFP_CFG_IN(GPIO100, AF2)
-
-/* Alternate Bus Master Mode I/O Signals */
-#define GPIO20_MBREQ		MFP_CFG_IN(GPIO20, AF2)
-#define GPIO80_MBREQ		MFP_CFG_IN(GPIO80, AF2)
-#define GPIO96_MBREQ		MFP_CFG_IN(GPIO96, AF2)
-#define GPIO115_MBREQ		MFP_CFG_IN(GPIO115, AF3)
-#define GPIO21_MBGNT		MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW)
-#define GPIO33_MBGNT		MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW)
-#define GPIO97_MBGNT		MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW)
-#define GPIO116_MBGNT		MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW)
-
-/* PC CARD */
-#define GPIO15_nPCE_1		MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH)
-#define GPIO85_nPCE_1		MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH)
-#define GPIO86_nPCE_1		MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH)
-#define GPIO102_nPCE_1		MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH)
-#define GPIO54_nPCE_2		MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
-#define GPIO78_nPCE_2		MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
-#define GPIO87_nPCE_2		MFP_CFG_IN(GPIO87, AF1)
-#define GPIO55_nPREG		MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
-#define GPIO50_nPIOR		MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
-#define GPIO51_nPIOW		MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
-#define GPIO49_nPWE		MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
-#define GPIO48_nPOE		MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
-#define GPIO57_nIOIS16		MFP_CFG_IN(GPIO57, AF1)
-#define GPIO56_nPWAIT		MFP_CFG_IN(GPIO56, AF1)
-#define GPIO79_PSKTSEL		MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
-#define GPIO104_PSKTSEL		MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH)
-
-/* I2C */
-#define GPIO117_I2C_SCL		MFP_CFG_IN(GPIO117, AF1)
-#define GPIO118_I2C_SDA		MFP_CFG_IN(GPIO118, AF1)
-
-/* FFUART */
-#define GPIO9_FFUART_CTS	MFP_CFG_IN(GPIO9, AF3)
-#define GPIO26_FFUART_CTS	MFP_CFG_IN(GPIO26, AF3)
-#define GPIO35_FFUART_CTS	MFP_CFG_IN(GPIO35, AF1)
-#define GPIO100_FFUART_CTS	MFP_CFG_IN(GPIO100, AF3)
-#define GPIO10_FFUART_DCD	MFP_CFG_IN(GPIO10, AF1)
-#define GPIO36_FFUART_DCD	MFP_CFG_IN(GPIO36, AF1)
-#define GPIO33_FFUART_DSR	MFP_CFG_IN(GPIO33, AF2)
-#define GPIO37_FFUART_DSR	MFP_CFG_IN(GPIO37, AF1)
-#define GPIO38_FFUART_RI	MFP_CFG_IN(GPIO38, AF1)
-#define GPIO89_FFUART_RI	MFP_CFG_IN(GPIO89, AF3)
-#define GPIO19_FFUART_RXD	MFP_CFG_IN(GPIO19, AF3)
-#define GPIO33_FFUART_RXD	MFP_CFG_IN(GPIO33, AF1)
-#define GPIO34_FFUART_RXD	MFP_CFG_IN(GPIO34, AF1)
-#define GPIO41_FFUART_RXD	MFP_CFG_IN(GPIO41, AF1)
-#define GPIO53_FFUART_RXD	MFP_CFG_IN(GPIO53, AF1)
-#define GPIO85_FFUART_RXD	MFP_CFG_IN(GPIO85, AF1)
-#define GPIO96_FFUART_RXD	MFP_CFG_IN(GPIO96, AF3)
-#define GPIO102_FFUART_RXD	MFP_CFG_IN(GPIO102, AF3)
-#define GPIO16_FFUART_TXD	MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH)
-#define GPIO37_FFUART_TXD	MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH)
-#define GPIO39_FFUART_TXD	MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
-#define GPIO83_FFUART_TXD	MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH)
-#define GPIO99_FFUART_TXD	MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH)
-#define GPIO27_FFUART_RTS	MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH)
-#define GPIO41_FFUART_RTS	MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
-#define GPIO83_FFUART_RTS	MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH)
-#define GPIO98_FFUART_RTS	MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH)
-#define GPIO40_FFUART_DTR	MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
-#define GPIO82_FFUART_DTR	MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH)
-
-/* BTUART */
-#define GPIO44_BTUART_CTS	MFP_CFG_IN(GPIO44, AF1)
-#define GPIO42_BTUART_RXD	MFP_CFG_IN(GPIO42, AF1)
-#define GPIO45_BTUART_RTS	MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
-#define GPIO43_BTUART_TXD	MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
-
-/* STUART */
-#define GPIO46_STUART_RXD	MFP_CFG_IN(GPIO46, AF2)
-#define GPIO47_STUART_TXD	MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
-
-/* FICP */
-#define GPIO42_FICP_RXD		MFP_CFG_IN(GPIO42, AF2)
-#define GPIO46_FICP_RXD		MFP_CFG_IN(GPIO46, AF1)
-#define GPIO43_FICP_TXD		MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH)
-#define GPIO47_FICP_TXD		MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
-
-/* PWM 0/1/2/3 */
-#define GPIO11_PWM2_OUT		MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW)
-#define GPIO12_PWM3_OUT		MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW)
-#define GPIO16_PWM0_OUT		MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
-#define GPIO17_PWM1_OUT		MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
-#define GPIO38_PWM1_OUT		MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW)
-#define GPIO46_PWM2_OUT		MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW)
-#define GPIO47_PWM3_OUT		MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW)
-#define GPIO79_PWM2_OUT		MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW)
-#define GPIO80_PWM3_OUT		MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW)
-#define GPIO115_PWM1_OUT	MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW)
-
-/* AC97 */
-#define GPIO31_AC97_SYNC	MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
-#define GPIO94_AC97_SYNC	MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW)
-#define GPIO30_AC97_SDATA_OUT	MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
-#define GPIO93_AC97_SDATA_OUT	MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW)
-#define GPIO45_AC97_SYSCLK	MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW)
-#define GPIO89_AC97_SYSCLK	MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW)
-#define GPIO98_AC97_SYSCLK	MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW)
-#define GPIO95_AC97_nRESET	MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW)
-#define GPIO113_AC97_nRESET	MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW)
-#define GPIO28_AC97_BITCLK	MFP_CFG_IN(GPIO28, AF1)
-#define GPIO29_AC97_SDATA_IN_0	MFP_CFG_IN(GPIO29, AF1)
-#define GPIO116_AC97_SDATA_IN_0	MFP_CFG_IN(GPIO116, AF2)
-#define GPIO99_AC97_SDATA_IN_1	MFP_CFG_IN(GPIO99, AF2)
-
-/* I2S */
-#define GPIO28_I2S_BITCLK_IN	MFP_CFG_IN(GPIO28, AF2)
-#define GPIO28_I2S_BITCLK_OUT	MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
-#define GPIO29_I2S_SDATA_IN	MFP_CFG_IN(GPIO29, AF2)
-#define GPIO30_I2S_SDATA_OUT	MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
-#define GPIO31_I2S_SYNC		MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
-#define GPIO113_I2S_SYSCLK	MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW)
-
-/* SSP 1 */
-#define GPIO23_SSP1_SCLK	MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
-#define GPIO29_SSP1_SCLK	MFP_CFG_IN(GPIO29, AF3)
-#define GPIO27_SSP1_SYSCLK	MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW)
-#define GPIO53_SSP1_SYSCLK	MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW)
-#define GPIO24_SSP1_SFRM	MFP_CFG_IN(GPIO24, AF2)
-#define GPIO28_SSP1_SFRM	MFP_CFG_IN(GPIO28, AF3)
-#define GPIO25_SSP1_TXD		MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
-#define GPIO57_SSP1_TXD		MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW)
-#define GPIO26_SSP1_RXD		MFP_CFG_IN(GPIO26, AF1)
-#define GPIO27_SSP1_SCLKEN	MFP_CFG_IN(GPIO27, AF2)
-
-/* SSP 2 */
-#define GPIO19_SSP2_SCLK	MFP_CFG_IN(GPIO19, AF1)
-#define GPIO22_SSP2_SCLK	MFP_CFG_IN(GPIO22, AF3)
-#define GPIO29_SSP2_SCLK	MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW)
-#define GPIO36_SSP2_SCLK	MFP_CFG_IN(GPIO36, AF2)
-#define GPIO50_SSP2_SCLK	MFP_CFG_IN(GPIO50, AF3)
-#define GPIO22_SSP2_SYSCLK	MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW)
-#define GPIO14_SSP2_SFRM	MFP_CFG_IN(GPIO14, AF2)
-#define GPIO37_SSP2_SFRM	MFP_CFG_IN(GPIO37, AF2)
-#define GPIO87_SSP2_SFRM	MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW)
-#define GPIO88_SSP2_SFRM	MFP_CFG_IN(GPIO88, AF3)
-#define GPIO13_SSP2_TXD		MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW)
-#define GPIO38_SSP2_TXD		MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW)
-#define GPIO87_SSP2_TXD		MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW)
-#define GPIO89_SSP2_TXD		MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW)
-#define GPIO11_SSP2_RXD		MFP_CFG_IN(GPIO11, AF2)
-#define GPIO29_SSP2_RXD		MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW)
-#define GPIO40_SSP2_RXD		MFP_CFG_IN(GPIO40, AF1)
-#define GPIO86_SSP2_RXD		MFP_CFG_IN(GPIO86, AF1)
-#define GPIO88_SSP2_RXD		MFP_CFG_IN(GPIO88, AF2)
-#define GPIO22_SSP2_EXTCLK	MFP_CFG_IN(GPIO22, AF1)
-#define GPIO27_SSP2_EXTCLK	MFP_CFG_IN(GPIO27, AF1)
-#define GPIO22_SSP2_SCLKEN	MFP_CFG_IN(GPIO22, AF2)
-#define GPIO23_SSP2_SCLKEN	MFP_CFG_IN(GPIO23, AF2)
-
-/* SSP 3 */
-#define GPIO34_SSP3_SCLK	MFP_CFG_IN(GPIO34, AF3)
-#define GPIO40_SSP3_SCLK	MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW)
-#define GPIO52_SSP3_SCLK	MFP_CFG_IN(GPIO52, AF2)
-#define GPIO84_SSP3_SCLK	MFP_CFG_IN(GPIO84, AF1)
-#define GPIO45_SSP3_SYSCLK	MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW)
-#define GPIO35_SSP3_SFRM	MFP_CFG_IN(GPIO35, AF3)
-#define GPIO39_SSP3_SFRM	MFP_CFG_IN(GPIO39, AF3)
-#define GPIO83_SSP3_SFRM	MFP_CFG_IN(GPIO83, AF1)
-#define GPIO35_SSP3_TXD		MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW)
-#define GPIO38_SSP3_TXD		MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW)
-#define GPIO81_SSP3_TXD		MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
-#define GPIO41_SSP3_RXD		MFP_CFG_IN(GPIO41, AF3)
-#define GPIO82_SSP3_RXD		MFP_CFG_IN(GPIO82, AF1)
-#define GPIO89_SSP3_RXD		MFP_CFG_IN(GPIO89, AF1)
-
-/* MMC */
-#define GPIO32_MMC_CLK		MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW)
-#define GPIO92_MMC_DAT_0	MFP_CFG_IN(GPIO92, AF1)
-#define GPIO109_MMC_DAT_1	MFP_CFG_IN(GPIO109, AF1)
-#define GPIO110_MMC_DAT_2	MFP_CFG_IN(GPIO110, AF1)
-#define GPIO111_MMC_DAT_3	MFP_CFG_IN(GPIO111, AF1)
-#define GPIO112_MMC_CMD		MFP_CFG_IN(GPIO112, AF1)
-
-/* LCD */
-#define GPIO58_LCD_LDD_0	MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
-#define GPIO59_LCD_LDD_1	MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
-#define GPIO60_LCD_LDD_2	MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
-#define GPIO61_LCD_LDD_3	MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
-#define GPIO62_LCD_LDD_4	MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
-#define GPIO63_LCD_LDD_5	MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
-#define GPIO64_LCD_LDD_6	MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
-#define GPIO65_LCD_LDD_7	MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
-#define GPIO66_LCD_LDD_8	MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
-#define GPIO67_LCD_LDD_9	MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
-#define GPIO68_LCD_LDD_10	MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
-#define GPIO69_LCD_LDD_11	MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
-#define GPIO70_LCD_LDD_12	MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
-#define GPIO71_LCD_LDD_13	MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
-#define GPIO72_LCD_LDD_14	MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
-#define GPIO73_LCD_LDD_15	MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
-#define GPIO86_LCD_LDD_16	MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW)
-#define GPIO87_LCD_LDD_17	MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW)
-#define GPIO74_LCD_FCLK		MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
-#define GPIO75_LCD_LCLK		MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
-#define GPIO76_LCD_PCLK		MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
-#define GPIO77_LCD_BIAS		MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
-#define GPIO14_LCD_VSYNC	MFP_CFG_IN(GPIO14, AF1)
-#define GPIO19_LCD_CS		MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW)
-
-/* Keypad */
-#define GPIO93_KP_DKIN_0	MFP_CFG_IN(GPIO93, AF1)
-#define GPIO94_KP_DKIN_1	MFP_CFG_IN(GPIO94, AF1)
-#define GPIO95_KP_DKIN_2	MFP_CFG_IN(GPIO95, AF1)
-#define GPIO96_KP_DKIN_3	MFP_CFG_IN(GPIO96, AF1)
-#define GPIO97_KP_DKIN_4	MFP_CFG_IN(GPIO97, AF1)
-#define GPIO98_KP_DKIN_5	MFP_CFG_IN(GPIO98, AF1)
-#define GPIO99_KP_DKIN_6	MFP_CFG_IN(GPIO99, AF1)
-#define GPIO13_KP_KDIN_7	MFP_CFG_IN(GPIO13, AF2)
-#define GPIO100_KP_MKIN_0	MFP_CFG_IN(GPIO100, AF1)
-#define GPIO101_KP_MKIN_1	MFP_CFG_IN(GPIO101, AF1)
-#define GPIO102_KP_MKIN_2	MFP_CFG_IN(GPIO102, AF1)
-#define GPIO34_KP_MKIN_3	MFP_CFG_IN(GPIO34, AF2)
-#define GPIO37_KP_MKIN_3	MFP_CFG_IN(GPIO37, AF3)
-#define GPIO97_KP_MKIN_3	MFP_CFG_IN(GPIO97, AF3)
-#define GPIO98_KP_MKIN_4	MFP_CFG_IN(GPIO98, AF3)
-#define GPIO38_KP_MKIN_4	MFP_CFG_IN(GPIO38, AF2)
-#define GPIO39_KP_MKIN_4	MFP_CFG_IN(GPIO39, AF1)
-#define GPIO16_KP_MKIN_5	MFP_CFG_IN(GPIO16, AF1)
-#define GPIO90_KP_MKIN_5	MFP_CFG_IN(GPIO90, AF1)
-#define GPIO99_KP_MKIN_5	MFP_CFG_IN(GPIO99, AF3)
-#define GPIO17_KP_MKIN_6	MFP_CFG_IN(GPIO17, AF1)
-#define GPIO91_KP_MKIN_6	MFP_CFG_IN(GPIO91, AF1)
-#define GPIO95_KP_MKIN_6	MFP_CFG_IN(GPIO95, AF3)
-#define GPIO13_KP_MKIN_7	MFP_CFG_IN(GPIO13, AF3)
-#define GPIO36_KP_MKIN_7	MFP_CFG_IN(GPIO36, AF3)
-#define GPIO103_KP_MKOUT_0	MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH)
-#define GPIO104_KP_MKOUT_1	MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH)
-#define GPIO105_KP_MKOUT_2	MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH)
-#define GPIO106_KP_MKOUT_3	MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH)
-#define GPIO107_KP_MKOUT_4	MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH)
-#define GPIO108_KP_MKOUT_5	MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH)
-#define GPIO35_KP_MKOUT_6	MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH)
-#define GPIO22_KP_MKOUT_7	MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH)
-#define GPIO40_KP_MKOUT_6	MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH)
-#define GPIO41_KP_MKOUT_7	MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH)
-#define GPIO96_KP_MKOUT_6	MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH)
-
-/* USB P3 */
-#define GPIO10_USB_P3_5		MFP_CFG_IN(GPIO10, AF3)
-#define GPIO11_USB_P3_1		MFP_CFG_IN(GPIO11, AF3)
-#define GPIO30_USB_P3_2		MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
-#define GPIO31_USB_P3_6		MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
-#define GPIO56_USB_P3_4		MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
-#define GPIO86_USB_P3_5		MFP_CFG_IN(GPIO86, AF3)
-#define GPIO87_USB_P3_1		MFP_CFG_IN(GPIO87, AF3)
-#define GPIO90_USB_P3_5		MFP_CFG_IN(GPIO90, AF2)
-#define GPIO91_USB_P3_1		MFP_CFG_IN(GPIO91, AF2)
-#define GPIO113_USB_P3_3	MFP_CFG_IN(GPIO113, AF3)
-
-/* USB P2 */
-#define GPIO34_USB_P2_2		MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW)
-#define GPIO35_USB_P2_1		MFP_CFG_IN(GPIO35, AF2)
-#define GPIO36_USB_P2_4		MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW)
-#define GPIO37_USB_P2_8		MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW)
-#define GPIO38_USB_P2_3		MFP_CFG_IN(GPIO38, AF3)
-#define GPIO39_USB_P2_6		MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
-#define GPIO40_USB_P2_5		MFP_CFG_IN(GPIO40, AF3)
-#define GPIO41_USB_P2_7		MFP_CFG_IN(GPIO41, AF2)
-#define GPIO53_USB_P2_3		MFP_CFG_IN(GPIO53, AF2)
-
-/* USB Host Port 1/2 */
-#define GPIO88_USBH1_PWR	MFP_CFG_IN(GPIO88, AF1)
-#define GPIO89_USBH1_PEN	MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW)
-#define GPIO119_USBH2_PWR	MFP_CFG_IN(GPIO119, AF1)
-#define GPIO120_USBH2_PEN	MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW)
-
-/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */
-#define GPIO115_CIF_DD_3	MFP_CFG_IN(GPIO115, AF2)
-#define GPIO116_CIF_DD_2	MFP_CFG_IN(GPIO116, AF1)
-#define GPIO12_CIF_DD_7		MFP_CFG_IN(GPIO12, AF2)
-#define GPIO17_CIF_DD_6		MFP_CFG_IN(GPIO17, AF2)
-#define GPIO23_CIF_MCLK		MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW)
-#define GPIO24_CIF_FV		MFP_CFG_IN(GPIO24, AF1)
-#define GPIO25_CIF_LV		MFP_CFG_IN(GPIO25, AF1)
-#define GPIO26_CIF_PCLK		MFP_CFG_IN(GPIO26, AF2)
-#define GPIO27_CIF_DD_0		MFP_CFG_IN(GPIO27, AF3)
-#define GPIO42_CIF_MCLK		MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW)
-#define GPIO43_CIF_FV		MFP_CFG_IN(GPIO43, AF3)
-#define GPIO44_CIF_LV		MFP_CFG_IN(GPIO44, AF3)
-#define GPIO45_CIF_PCLK		MFP_CFG_IN(GPIO45, AF3)
-#define GPIO47_CIF_DD_0		MFP_CFG_IN(GPIO47, AF1)
-#define GPIO48_CIF_DD_5		MFP_CFG_IN(GPIO48, AF1)
-#define GPIO50_CIF_DD_3		MFP_CFG_IN(GPIO50, AF1)
-#define GPIO51_CIF_DD_2		MFP_CFG_IN(GPIO51, AF1)
-#define GPIO52_CIF_DD_4		MFP_CFG_IN(GPIO52, AF1)
-#define GPIO53_CIF_MCLK		MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW)
-#define GPIO54_CIF_PCLK		MFP_CFG_IN(GPIO54, AF3)
-#define GPIO55_CIF_DD_1		MFP_CFG_IN(GPIO55, AF1)
-#define GPIO81_CIF_DD_0		MFP_CFG_IN(GPIO81, AF2)
-#define GPIO82_CIF_DD_5		MFP_CFG_IN(GPIO82, AF3)
-#define GPIO83_CIF_DD_4		MFP_CFG_IN(GPIO83, AF3)
-#define GPIO84_CIF_FV		MFP_CFG_IN(GPIO84, AF3)
-#define GPIO85_CIF_LV		MFP_CFG_IN(GPIO85, AF3)
-#define GPIO90_CIF_DD_4		MFP_CFG_IN(GPIO90, AF3)
-#define GPIO91_CIF_DD_5		MFP_CFG_IN(GPIO91, AF3)
-#define GPIO93_CIF_DD_6		MFP_CFG_IN(GPIO93, AF2)
-#define GPIO94_CIF_DD_5		MFP_CFG_IN(GPIO94, AF2)
-#define GPIO95_CIF_DD_4		MFP_CFG_IN(GPIO95, AF2)
-#define GPIO98_CIF_DD_0		MFP_CFG_IN(GPIO98, AF2)
-#define GPIO103_CIF_DD_3	MFP_CFG_IN(GPIO103, AF1)
-#define GPIO104_CIF_DD_2	MFP_CFG_IN(GPIO104, AF1)
-#define GPIO105_CIF_DD_1	MFP_CFG_IN(GPIO105, AF1)
-#define GPIO106_CIF_DD_9	MFP_CFG_IN(GPIO106, AF1)
-#define GPIO107_CIF_DD_8	MFP_CFG_IN(GPIO107, AF1)
-#define GPIO108_CIF_DD_7	MFP_CFG_IN(GPIO108, AF1)
-#define GPIO114_CIF_DD_1	MFP_CFG_IN(GPIO114, AF1)
-
-/* Universal Subscriber ID Interface */
-#define GPIO114_UVS0		MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW)
-#define GPIO115_nUVS1		MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW)
-#define GPIO116_nUVS2		MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW)
-#define GPIO14_UCLK		MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW)
-#define GPIO91_UCLK		MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW)
-#define GPIO19_nURST		MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW)
-#define GPIO90_nURST		MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW)
-#define GPIO116_UDET		MFP_CFG_IN(GPIO116, AF3)
-#define GPIO114_UEN		MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW)
-#define GPIO115_UEN		MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW)
-
-/* Mobile Scalable Link (MSL) Interface */
-#define GPIO81_BB_OB_DAT_0	MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW)
-#define GPIO48_BB_OB_DAT_1	MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW)
-#define GPIO50_BB_OB_DAT_2	MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW)
-#define GPIO51_BB_OB_DAT_3	MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW)
-#define GPIO52_BB_OB_CLK	MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW)
-#define GPIO53_BB_OB_STB	MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
-#define GPIO54_BB_OB_WAIT	MFP_CFG_IN(GPIO54, AF2)
-#define GPIO82_BB_IB_DAT_0	MFP_CFG_IN(GPIO82, AF2)
-#define GPIO55_BB_IB_DAT_1	MFP_CFG_IN(GPIO55, AF2)
-#define GPIO56_BB_IB_DAT_2	MFP_CFG_IN(GPIO56, AF2)
-#define GPIO57_BB_IB_DAT_3	MFP_CFG_IN(GPIO57, AF2)
-#define GPIO83_BB_IB_CLK	MFP_CFG_IN(GPIO83, AF2)
-#define GPIO84_BB_IB_STB	MFP_CFG_IN(GPIO84, AF2)
-#define GPIO85_BB_IB_WAIT	MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW)
-
-/* Memory Stick Host Controller */
-#define GPIO92_MSBS		MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW)
-#define GPIO109_MSSDIO		MFP_CFG_IN(GPIO109, AF2)
-#define GPIO112_nMSINS		MFP_CFG_IN(GPIO112, AF2)
-#define GPIO32_MSSCLK		MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
-
-/* commonly used pin configurations */
-#define GPIOxx_LCD_16BPP	\
-	GPIO58_LCD_LDD_0,	\
-	GPIO59_LCD_LDD_1,	\
-	GPIO60_LCD_LDD_2,	\
-	GPIO61_LCD_LDD_3,	\
-	GPIO62_LCD_LDD_4,	\
-	GPIO63_LCD_LDD_5,	\
-	GPIO64_LCD_LDD_6,	\
-	GPIO65_LCD_LDD_7,	\
-	GPIO66_LCD_LDD_8,	\
-	GPIO67_LCD_LDD_9,	\
-	GPIO68_LCD_LDD_10,	\
-	GPIO69_LCD_LDD_11,	\
-	GPIO70_LCD_LDD_12,	\
-	GPIO71_LCD_LDD_13,	\
-	GPIO72_LCD_LDD_14,	\
-	GPIO73_LCD_LDD_15
-
-#define GPIOxx_LCD_DSTN_16BPP	\
-	GPIOxx_LCD_16BPP,	\
-	GPIO74_LCD_FCLK,	\
-	GPIO75_LCD_LCLK,	\
-	GPIO76_LCD_PCLK
-
-#define GPIOxx_LCD_TFT_16BPP	\
-	GPIOxx_LCD_16BPP,	\
-	GPIO74_LCD_FCLK,	\
-	GPIO75_LCD_LCLK,	\
-	GPIO76_LCD_PCLK,	\
-	GPIO77_LCD_BIAS
-
-extern int keypad_set_wake(unsigned int on);
-#endif /* __ASM_ARCH_MFP_PXA27X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
deleted file mode 100644
index 658b28ed12..0000000000
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ /dev/null
@@ -1,133 +0,0 @@
-#ifndef __ASM_ARCH_MFP_PXA2XX_H
-#define __ASM_ARCH_MFP_PXA2XX_H
-
-#include <plat/mfp.h>
-
-/*
- * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
- *
- *  MFP_PIN(x)
- *  MFP_AFx
- *  MFP_LPM_DRIVE_{LOW, HIGH}
- *  MFP_LPM_EDGE_x
- *
- * other MFP_x bit definitions will be ignored
- *
- * and adds the below two bits specifically for pxa2xx:
- *
- * bit     23 - Input/Output (PXA2xx specific)
- * bit     24 - Wakeup Enable(PXA2xx specific)
- */
-
-#define MFP_DIR_IN		(0x0 << 23)
-#define MFP_DIR_OUT		(0x1 << 23)
-#define MFP_DIR_MASK		(0x1 << 23)
-#define MFP_DIR(x)		(((x) >> 23) & 0x1)
-
-#define MFP_LPM_CAN_WAKEUP	(0x1 << 24)
-#define WAKEUP_ON_EDGE_RISE	(MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
-#define WAKEUP_ON_EDGE_FALL	(MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
-#define WAKEUP_ON_EDGE_BOTH	(MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
-
-/* specifically for enabling wakeup on keypad GPIOs */
-#define WAKEUP_ON_LEVEL_HIGH	(MFP_LPM_CAN_WAKEUP)
-
-#define MFP_CFG_IN(pin, af)		\
-	((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
-	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN))
-
-/* NOTE:  pins configured as output _must_ provide a low power state,
- * and this state should help to minimize the power dissipation.
- */
-#define MFP_CFG_OUT(pin, af, state)	\
-	((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
-	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
-
-/* Common configurations for pxa25x and pxa27x
- *
- * Note: pins configured as GPIO are always initialized to input
- * so not to cause any side effect
- */
-#define GPIO0_GPIO	MFP_CFG_IN(GPIO0, AF0)
-#define GPIO1_GPIO	MFP_CFG_IN(GPIO1, AF0)
-#define GPIO9_GPIO	MFP_CFG_IN(GPIO9, AF0)
-#define GPIO10_GPIO	MFP_CFG_IN(GPIO10, AF0)
-#define GPIO11_GPIO	MFP_CFG_IN(GPIO11, AF0)
-#define GPIO12_GPIO	MFP_CFG_IN(GPIO12, AF0)
-#define GPIO13_GPIO	MFP_CFG_IN(GPIO13, AF0)
-#define GPIO14_GPIO	MFP_CFG_IN(GPIO14, AF0)
-#define GPIO15_GPIO	MFP_CFG_IN(GPIO15, AF0)
-#define GPIO16_GPIO	MFP_CFG_IN(GPIO16, AF0)
-#define GPIO17_GPIO	MFP_CFG_IN(GPIO17, AF0)
-#define GPIO18_GPIO	MFP_CFG_IN(GPIO18, AF0)
-#define GPIO19_GPIO	MFP_CFG_IN(GPIO19, AF0)
-#define GPIO20_GPIO	MFP_CFG_IN(GPIO20, AF0)
-#define GPIO21_GPIO	MFP_CFG_IN(GPIO21, AF0)
-#define GPIO22_GPIO	MFP_CFG_IN(GPIO22, AF0)
-#define GPIO23_GPIO	MFP_CFG_IN(GPIO23, AF0)
-#define GPIO24_GPIO	MFP_CFG_IN(GPIO24, AF0)
-#define GPIO25_GPIO	MFP_CFG_IN(GPIO25, AF0)
-#define GPIO26_GPIO	MFP_CFG_IN(GPIO26, AF0)
-#define GPIO27_GPIO	MFP_CFG_IN(GPIO27, AF0)
-#define GPIO28_GPIO	MFP_CFG_IN(GPIO28, AF0)
-#define GPIO29_GPIO	MFP_CFG_IN(GPIO29, AF0)
-#define GPIO30_GPIO	MFP_CFG_IN(GPIO30, AF0)
-#define GPIO31_GPIO	MFP_CFG_IN(GPIO31, AF0)
-#define GPIO32_GPIO	MFP_CFG_IN(GPIO32, AF0)
-#define GPIO33_GPIO	MFP_CFG_IN(GPIO33, AF0)
-#define GPIO34_GPIO	MFP_CFG_IN(GPIO34, AF0)
-#define GPIO35_GPIO	MFP_CFG_IN(GPIO35, AF0)
-#define GPIO36_GPIO	MFP_CFG_IN(GPIO36, AF0)
-#define GPIO37_GPIO	MFP_CFG_IN(GPIO37, AF0)
-#define GPIO38_GPIO	MFP_CFG_IN(GPIO38, AF0)
-#define GPIO39_GPIO	MFP_CFG_IN(GPIO39, AF0)
-#define GPIO40_GPIO	MFP_CFG_IN(GPIO40, AF0)
-#define GPIO41_GPIO	MFP_CFG_IN(GPIO41, AF0)
-#define GPIO42_GPIO	MFP_CFG_IN(GPIO42, AF0)
-#define GPIO43_GPIO	MFP_CFG_IN(GPIO43, AF0)
-#define GPIO44_GPIO	MFP_CFG_IN(GPIO44, AF0)
-#define GPIO45_GPIO	MFP_CFG_IN(GPIO45, AF0)
-#define GPIO46_GPIO	MFP_CFG_IN(GPIO46, AF0)
-#define GPIO47_GPIO	MFP_CFG_IN(GPIO47, AF0)
-#define GPIO48_GPIO	MFP_CFG_IN(GPIO48, AF0)
-#define GPIO49_GPIO	MFP_CFG_IN(GPIO49, AF0)
-#define GPIO50_GPIO	MFP_CFG_IN(GPIO50, AF0)
-#define GPIO51_GPIO	MFP_CFG_IN(GPIO51, AF0)
-#define GPIO52_GPIO	MFP_CFG_IN(GPIO52, AF0)
-#define GPIO53_GPIO	MFP_CFG_IN(GPIO53, AF0)
-#define GPIO54_GPIO	MFP_CFG_IN(GPIO54, AF0)
-#define GPIO55_GPIO	MFP_CFG_IN(GPIO55, AF0)
-#define GPIO56_GPIO	MFP_CFG_IN(GPIO56, AF0)
-#define GPIO57_GPIO	MFP_CFG_IN(GPIO57, AF0)
-#define GPIO58_GPIO	MFP_CFG_IN(GPIO58, AF0)
-#define GPIO59_GPIO	MFP_CFG_IN(GPIO59, AF0)
-#define GPIO60_GPIO	MFP_CFG_IN(GPIO60, AF0)
-#define GPIO61_GPIO	MFP_CFG_IN(GPIO61, AF0)
-#define GPIO62_GPIO	MFP_CFG_IN(GPIO62, AF0)
-#define GPIO63_GPIO	MFP_CFG_IN(GPIO63, AF0)
-#define GPIO64_GPIO	MFP_CFG_IN(GPIO64, AF0)
-#define GPIO65_GPIO	MFP_CFG_IN(GPIO65, AF0)
-#define GPIO66_GPIO	MFP_CFG_IN(GPIO66, AF0)
-#define GPIO67_GPIO	MFP_CFG_IN(GPIO67, AF0)
-#define GPIO68_GPIO	MFP_CFG_IN(GPIO68, AF0)
-#define GPIO69_GPIO	MFP_CFG_IN(GPIO69, AF0)
-#define GPIO70_GPIO	MFP_CFG_IN(GPIO70, AF0)
-#define GPIO71_GPIO	MFP_CFG_IN(GPIO71, AF0)
-#define GPIO72_GPIO	MFP_CFG_IN(GPIO72, AF0)
-#define GPIO73_GPIO	MFP_CFG_IN(GPIO73, AF0)
-#define GPIO74_GPIO	MFP_CFG_IN(GPIO74, AF0)
-#define GPIO75_GPIO	MFP_CFG_IN(GPIO75, AF0)
-#define GPIO76_GPIO	MFP_CFG_IN(GPIO76, AF0)
-#define GPIO77_GPIO	MFP_CFG_IN(GPIO77, AF0)
-#define GPIO78_GPIO	MFP_CFG_IN(GPIO78, AF0)
-#define GPIO79_GPIO	MFP_CFG_IN(GPIO79, AF0)
-#define GPIO80_GPIO	MFP_CFG_IN(GPIO80, AF0)
-#define GPIO81_GPIO	MFP_CFG_IN(GPIO81, AF0)
-#define GPIO82_GPIO	MFP_CFG_IN(GPIO82, AF0)
-#define GPIO83_GPIO	MFP_CFG_IN(GPIO83, AF0)
-#define GPIO84_GPIO	MFP_CFG_IN(GPIO84, AF0)
-
-extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
-extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm);
-extern int gpio_set_wake(unsigned int gpio, unsigned int on);
-#endif /* __ASM_ARCH_MFP_PXA2XX_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
deleted file mode 100644
index 7bdd44db13..0000000000
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __ASM_ARCH_MFP_PXA3XX_H
-#define __ASM_ARCH_MFP_PXA3XX_H
-
-#include <plat/mfp.h>
-
-#define MFPR_BASE	(0x40e10000)
-
-/* NOTE: usage of these two functions is not recommended,
- * use pxa3xx_mfp_config() instead.
- */
-static inline unsigned long pxa3xx_mfp_read(int mfp)
-{
-	return mfp_read(mfp);
-}
-
-static inline void pxa3xx_mfp_write(int mfp, unsigned long val)
-{
-	mfp_write(mfp, val);
-}
-
-static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num)
-{
-	mfp_config(mfp_cfg, num);
-}
-#endif /* __ASM_ARCH_MFP_PXA3XX_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h
deleted file mode 100644
index 271e249ae3..0000000000
--- a/arch/arm/mach-pxa/include/mach/mfp.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/mfp.h
- *
- * Multi-Function Pin Definitions
- *
- * Copyright (C) 2007 Marvell International Ltd.
- *
- * 2007-8-21: eric miao <eric.miao@marvell.com>
- *            initial version
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MFP_H
-#define __ASM_ARCH_MFP_H
-
-#include <plat/mfp.h>
-
-#endif /* __ASM_ARCH_MFP_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
deleted file mode 100644
index 9bcb5efb7f..0000000000
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * (c) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
- *
- * Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
- *
- * This file is released under the GPLv2
- *
- */
-
-#ifndef __MACH_PXA_REGS_H
-#define __MACH_PXA_REGS_H
-
-#ifndef __ASSEMBLY__
-# define __REG(x)	(*((volatile u32 *)(x)))
-# define __REG16(x)	(*(volatile u16 *)(x))
-# define __REG2(x, y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
-#else
-# define __REG(x)	(x)
-# define __REG16(x)	(x)
-# define __REG2(x, y)	((x) + (y))
-#endif
-
-#ifdef CONFIG_ARCH_PXA2XX
-# include <mach/pxa2xx-regs.h>
-#endif
-
-#if defined(CONFIG_ARCH_PXA27X)
-# include <mach/pxa27x-regs.h>
-#elif defined(CONFIG_ARCH_PXA3XX)
-# include <mach/pxa3xx-regs.h>
-#elif defined(CONFIG_ARCH_PXA25X)
-# include <mach/pxa25x-regs.h>
-#else
-# error "unknown PXA soc type"
-#endif
-
-#endif	/* !__MACH_PXA_REGS_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x-regs.h b/arch/arm/mach-pxa/include/mach/pxa25x-regs.h
deleted file mode 100644
index a7f16bd418..0000000000
--- a/arch/arm/mach-pxa/include/mach/pxa25x-regs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MACH_PXA25X_REGS
-#define __MACH_PXA25X_REGS
-
-/* this file intentionally left blank */
-
-#endif	/* !__MACH_PXA25X_REGS */
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x-regs.h b/arch/arm/mach-pxa/include/mach/pxa27x-regs.h
deleted file mode 100644
index f4d88d47ab..0000000000
--- a/arch/arm/mach-pxa/include/mach/pxa27x-regs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MACH_PXA27X_REGS
-#define __MACH_PXA27X_REGS
-
-/* this file intentionally left blank */
-
-#endif	/* !__MACH_PXA27X_REGS */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
deleted file mode 100644
index dc7704eda2..0000000000
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- *  arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
- *
- *  Taken from pxa-regs.h by Russell King
- *
- *  Author:	Nicolas Pitre
- *  Copyright:	MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __PXA2XX_REGS_H
-#define __PXA2XX_REGS_H
-
-#include <mach/hardware.h>
-
-/*
- * PXA Chip selects
- */
-#define PXA_CS0_PHYS	0x00000000
-#define PXA_CS1_PHYS	0x04000000
-#define PXA_CS2_PHYS	0x08000000
-#define PXA_CS3_PHYS	0x0C000000
-#define PXA_CS4_PHYS	0x10000000
-#define PXA_CS5_PHYS	0x14000000
-
-/*
- * Memory controller
- */
-#define MDCNFG_OFFSET	0x00000000
-#define MDREFR_OFFSET	0x00000004
-#define MSC0_OFFSET	0x00000008
-#define MSC1_OFFSET	0x0000000C
-#define MSC2_OFFSET	0x00000010
-#define MECR_OFFSET	0x00000014
-#define SXCNFG_OFFSET	0x0000001C
-#define FLYCNFG_OFFSET	0x00000020
-#define MCMEM0_OFFSET	0x00000028
-#define MCMEM1_OFFSET	0x0000002C
-#define MCATT0_OFFSET	0x00000030
-#define MCATT1_OFFSET	0x00000034
-#define MCIO0_OFFSET	0x00000038
-#define MCIO1_OFFSET	0x0000003C
-#define MDMRS_OFFSET	0x00000040
-
-#define MDCNFG		__REG(0x48000000)  /* SDRAM Configuration Register 0 */
-#define MDREFR		__REG(0x48000004)  /* SDRAM Refresh Control Register */
-#define MSC0		__REG(0x48000008)  /* Static Memory Control Register 0 */
-#define MSC1		__REG(0x4800000C)  /* Static Memory Control Register 1 */
-#define MSC2		__REG(0x48000010)  /* Static Memory Control Register 2 */
-#define MECR		__REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR		__REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG		__REG(0x4800001C)  /* Synchronous Static Memory Control Register */
-#define FLYCNFG		__REG(0x48000020)  /* Flycnfg Register */
-#define SXMRS		__REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0		__REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1		__REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0		__REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1		__REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0		__REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1		__REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS		__REG(0x48000040)  /* MRS value to be written to SDRAM */
-#define BOOT_DEF	__REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
-
-/*
- * More handy macros for PCMCIA
- *
- * Arg is socket number
- */
-#define MCMEM(s)	__REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
-#define MCATT(s)	__REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
-#define MCIO(s)		__REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
-
-/* MECR register defines */
-#define MECR_NOS	(1 << 0)	/* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
-#define MECR_CIT	(1 << 1)	/* Card Is There: 0 -> no card, 1 -> card inserted */
-
-#define MDCNFG_DE0	(1 << 0)	/* SDRAM Bank 0 Enable */
-#define MDCNFG_DE1	(1 << 1)	/* SDRAM Bank 1 Enable */
-#define MDCNFG_DE2	(1 << 16)	/* SDRAM Bank 2 Enable */
-#define MDCNFG_DE3	(1 << 17)	/* SDRAM Bank 3 Enable */
-
-#define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
-#define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
-#define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
-#define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
-#define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
-#define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
-#define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
-#define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
-#define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
-#define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
-#define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
-#define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
-#define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
-#define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
-
-/*
- * Power Manager
- */
-
-#define PMCR		__REG(0x40F00000)  /* Power Manager Control Register */
-#define PSSR		__REG(0x40F00004)  /* Power Manager Sleep Status Register */
-#define PSPR		__REG(0x40F00008)  /* Power Manager Scratch Pad Register */
-#define PWER		__REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
-#define PRER		__REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER		__REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR		__REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR		__REG(0x40F0001C)  /* Power Manager General Configuration Register */
-#define PGSR0		__REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1		__REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2		__REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3		__REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR		__REG(0x40F00030)  /* Reset Controller Status Register */
-
-#define PSLR		__REG(0x40F00034)	/* Power Manager Sleep Config Register */
-#define PSTR		__REG(0x40F00038)	/* Power Manager Standby Config Register */
-#define PSNR		__REG(0x40F0003C)	/* Power Manager Sense Config Register */
-#define PVCR		__REG(0x40F00040)	/* Power Manager VoltageControl Register */
-#define PKWR		__REG(0x40F00050)	/* Power Manager KB Wake-up Enable Reg */
-#define PKSR		__REG(0x40F00054)	/* Power Manager KB Level-Detect Register */
-#define PCMD(x)	__REG2(0x40F00080, (x)<<2)
-#define PCMD0	__REG(0x40F00080 + 0 * 4)
-#define PCMD1	__REG(0x40F00080 + 1 * 4)
-#define PCMD2	__REG(0x40F00080 + 2 * 4)
-#define PCMD3	__REG(0x40F00080 + 3 * 4)
-#define PCMD4	__REG(0x40F00080 + 4 * 4)
-#define PCMD5	__REG(0x40F00080 + 5 * 4)
-#define PCMD6	__REG(0x40F00080 + 6 * 4)
-#define PCMD7	__REG(0x40F00080 + 7 * 4)
-#define PCMD8	__REG(0x40F00080 + 8 * 4)
-#define PCMD9	__REG(0x40F00080 + 9 * 4)
-#define PCMD10	__REG(0x40F00080 + 10 * 4)
-#define PCMD11	__REG(0x40F00080 + 11 * 4)
-#define PCMD12	__REG(0x40F00080 + 12 * 4)
-#define PCMD13	__REG(0x40F00080 + 13 * 4)
-#define PCMD14	__REG(0x40F00080 + 14 * 4)
-#define PCMD15	__REG(0x40F00080 + 15 * 4)
-#define PCMD16	__REG(0x40F00080 + 16 * 4)
-#define PCMD17	__REG(0x40F00080 + 17 * 4)
-#define PCMD18	__REG(0x40F00080 + 18 * 4)
-#define PCMD19	__REG(0x40F00080 + 19 * 4)
-#define PCMD20	__REG(0x40F00080 + 20 * 4)
-#define PCMD21	__REG(0x40F00080 + 21 * 4)
-#define PCMD22	__REG(0x40F00080 + 22 * 4)
-#define PCMD23	__REG(0x40F00080 + 23 * 4)
-#define PCMD24	__REG(0x40F00080 + 24 * 4)
-#define PCMD25	__REG(0x40F00080 + 25 * 4)
-#define PCMD26	__REG(0x40F00080 + 26 * 4)
-#define PCMD27	__REG(0x40F00080 + 27 * 4)
-#define PCMD28	__REG(0x40F00080 + 28 * 4)
-#define PCMD29	__REG(0x40F00080 + 29 * 4)
-#define PCMD30	__REG(0x40F00080 + 30 * 4)
-#define PCMD31	__REG(0x40F00080 + 31 * 4)
-
-#define PCMD_MBC	(1<<12)
-#define PCMD_DCE	(1<<11)
-#define PCMD_LC	(1<<10)
-/* FIXME:  PCMD_SQC need be checked.   */
-#define PCMD_SQC	(3<<8)	/* currently only bit 8 is changeable,
-				   bit 9 should be 0 all day. */
-#define PVCR_VCSA	(0x1<<14)
-#define PVCR_CommandDelay (0xf80)
-#define PCFR_PI2C_EN	(0x1 << 6)
-
-#define PSSR_OTGPH	(1 << 6)	/* OTG Peripheral control Hold */
-#define PSSR_RDH	(1 << 5)	/* Read Disable Hold */
-#define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */
-#define PSSR_STS	(1 << 3)	/* Standby Mode Status */
-#define PSSR_VFS	(1 << 2)	/* VDD Fault Status */
-#define PSSR_BFS	(1 << 1)	/* Battery Fault Status */
-#define PSSR_SSS	(1 << 0)	/* Software Sleep Status */
-
-#define PSLR_SL_ROD	(1 << 20)	/* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
-
-#define PCFR_RO		(1 << 15)	/* RDH Override */
-#define PCFR_PO		(1 << 14)	/* PH Override */
-#define PCFR_GPROD	(1 << 12)	/* GPIO nRESET_OUT Disable */
-#define PCFR_L1_EN	(1 << 11)	/* Sleep Mode L1 converter Enable */
-#define PCFR_FVC	(1 << 10)	/* Frequency/Voltage Change */
-#define PCFR_DC_EN	(1 << 7)	/* Sleep/deep-sleep DC-DC Converter Enable */
-#define PCFR_PI2CEN	(1 << 6)	/* Enable PI2C controller */
-#define PCFR_GPR_EN	(1 << 4)	/* nRESET_GPIO Pin Enable */
-#define PCFR_DS		(1 << 3)	/* Deep Sleep Mode */
-#define PCFR_FS		(1 << 2)	/* Float Static Chip Selects */
-#define PCFR_FP		(1 << 1)	/* Float PCMCIA controls */
-#define PCFR_OPDE	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */
-
-#define RCSR_GPR	(1 << 3)	/* GPIO Reset */
-#define RCSR_SMR	(1 << 2)	/* Sleep Mode */
-#define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
-#define RCSR_HWR	(1 << 0)	/* Hardware Reset */
-
-#define PWER_GPIO(Nb)	(1 << Nb)	/* GPIO [0..15] wake-up enable     */
-#define PWER_GPIO0	PWER_GPIO(0)	/* GPIO  [0] wake-up enable        */
-#define PWER_GPIO1	PWER_GPIO(1)	/* GPIO  [1] wake-up enable        */
-#define PWER_GPIO2	PWER_GPIO(2)	/* GPIO  [2] wake-up enable        */
-#define PWER_GPIO3	PWER_GPIO(3)	/* GPIO  [3] wake-up enable        */
-#define PWER_GPIO4	PWER_GPIO(4)	/* GPIO  [4] wake-up enable        */
-#define PWER_GPIO5	PWER_GPIO(5)	/* GPIO  [5] wake-up enable        */
-#define PWER_GPIO6	PWER_GPIO(6)	/* GPIO  [6] wake-up enable        */
-#define PWER_GPIO7	PWER_GPIO(7)	/* GPIO  [7] wake-up enable        */
-#define PWER_GPIO8	PWER_GPIO(8)	/* GPIO  [8] wake-up enable        */
-#define PWER_GPIO9	PWER_GPIO(9)	/* GPIO  [9] wake-up enable        */
-#define PWER_GPIO10	PWER_GPIO(10)	/* GPIO [10] wake-up enable        */
-#define PWER_GPIO11	PWER_GPIO(11)	/* GPIO [11] wake-up enable        */
-#define PWER_GPIO12	PWER_GPIO(12)	/* GPIO [12] wake-up enable        */
-#define PWER_GPIO13	PWER_GPIO(13)	/* GPIO [13] wake-up enable        */
-#define PWER_GPIO14	PWER_GPIO(14)	/* GPIO [14] wake-up enable        */
-#define PWER_GPIO15	PWER_GPIO(15)	/* GPIO [15] wake-up enable        */
-#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */
-
-/*
- * PXA2xx specific Core clock definitions
- */
-#define CCCR		__REG(0x41300000)  /* Core Clock Configuration Register */
-#define CCSR		__REG(0x4130000C)  /* Core Clock Status Register */
-#define CKEN		__REG(0x41300004)  /* Clock Enable Register */
-#define OSCC		__REG(0x41300008)  /* Oscillator Configuration Register */
-
-#define CCCR_N_MASK	0x0380	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define CCCR_M_MASK	0x0060	/* Memory Frequency to Run Mode Frequency Multiplier */
-#define CCCR_L_MASK	0x001f	/* Crystal Frequency to Memory Frequency Multiplier */
-#define CCCR_CPDIS	(1 << 31)
-#define CCCR_PPDIS	(1 << 30)
-#define CCCR_LCD26	(1 << 27)
-#define CCCR_PLL_EARLY	(1 << 26)
-#define CCCR_A		(1 << 25)
-
-#define CKEN_AC97CONF   (1 << 31)    /* AC97 Controller Configuration */
-#define CKEN_CAMERA	(1 << 24)	/* Camera Interface Clock Enable */
-#define CKEN_SSP1	(1 << 23)	/* SSP1 Unit Clock Enable */
-#define CKEN_MEMC	(1 << 22)	/* Memory Controller Clock Enable */
-#define CKEN_MEMSTK	(1 << 21)	/* Memory Stick Host Controller */
-#define CKEN_IM		(1 << 20)	/* Internal Memory Clock Enable */
-#define CKEN_KEYPAD	(1 << 19)	/* Keypad Interface Clock Enable */
-#define CKEN_USIM	(1 << 18)	/* USIM Unit Clock Enable */
-#define CKEN_MSL	(1 << 17)	/* MSL Unit Clock Enable */
-#define CKEN_LCD	(1 << 16)	/* LCD Unit Clock Enable */
-#define CKEN_PWRI2C	(1 << 15)	/* PWR I2C Unit Clock Enable */
-#define CKEN_I2C	(1 << 14)	/* I2C Unit Clock Enable */
-#define CKEN_FICP	(1 << 13)	/* FICP Unit Clock Enable */
-#define CKEN_MMC	(1 << 12)	/* MMC Unit Clock Enable */
-#define CKEN_USB	(1 << 11)	/* USB Unit Clock Enable */
-#define CKEN_ASSP	(1 << 10)	/* ASSP (1 << SSP3) Clock Enable */
-#define CKEN_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
-#define CKEN_OSTIMER	(1 << 9)	/* OS Timer Unit Clock Enable */
-#define CKEN_NSSP	(1 << 9)	/* NSSP (1 << SSP2) Clock Enable */
-#define CKEN_I2S	(1 << 8)	/* I2S Unit Clock Enable */
-#define CKEN_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
-#define CKEN_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
-#define CKEN_STUART	(1 << 5)	/* STUART Unit Clock Enable */
-#define CKEN_HWUART	(1 << 4)	/* HWUART Unit Clock Enable */
-#define CKEN_SSP3	(1 << 4)	/* SSP3 Unit Clock Enable */
-#define CKEN_SSP	(1 << 3)	/* SSP Unit Clock Enable */
-#define CKEN_SSP2	(1 << 3)	/* SSP2 Unit Clock Enable */
-#define CKEN_AC97	(1 << 2)	/* AC97 Unit Clock Enable */
-#define CKEN_PWM1	(1 << 1)	/* PWM1 Clock Enable */
-#define CKEN_PWM0	(1 << 0)	/* PWM0 Clock Enable */
-
-#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
-
-/* PWRMODE register M field values */
-
-#define PWRMODE_IDLE		0x1
-#define PWRMODE_STANDBY		0x2
-#define PWRMODE_SLEEP		0x3
-#define PWRMODE_DEEPSLEEP	0x7
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
deleted file mode 100644
index 373711d92f..0000000000
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
- *
- * PXA3xx specific register definitions
- *
- * Copyright (C) 2007 Marvell International Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_PXA3XX_REGS
-#define __MACH_PXA3XX_REGS
-
-#include <mach/hardware.h>
-
-/*
- * Oscillator Configuration Register (OSCC)
- */
-#define OSCC           __REG(0x41350000)  /* Oscillator Configuration Register */
-
-#define OSCC_PEN       (1 << 11)       /* 13MHz POUT */
-
-
-/*
- * Service Power Management Unit (MPMU)
- */
-#define PMCR		__REG(0x40F50000)	/* Power Manager Control Register */
-#define PSR		__REG(0x40F50004)	/* Power Manager S2 Status Register */
-#define PSPR		__REG(0x40F50008)	/* Power Manager Scratch Pad Register */
-#define PCFR		__REG(0x40F5000C)	/* Power Manager General Configuration Register */
-#define PWER		__REG(0x40F50010)	/* Power Manager Wake-up Enable Register */
-#define PWSR		__REG(0x40F50014)	/* Power Manager Wake-up Status Register */
-#define PECR		__REG(0x40F50018)	/* Power Manager EXT_WAKEUP[1:0] Control Register */
-#define DCDCSR		__REG(0x40F50080)	/* DC-DC Controller Status Register */
-#define PVCR		__REG(0x40F50100)	/* Power Manager Voltage Change Control Register */
-#define PCMD(x)		__REG(0x40F50110 + ((x) << 2))
-
-/*
- * Slave Power Management Unit
- */
-#define ASCR		__REG(0x40f40000)	/* Application Subsystem Power Status/Configuration */
-#define ARSR		__REG(0x40f40004)	/* Application Subsystem Reset Status */
-#define AD3ER		__REG(0x40f40008)	/* Application Subsystem Wake-Up from D3 Enable */
-#define AD3SR		__REG(0x40f4000c)	/* Application Subsystem Wake-Up from D3 Status */
-#define AD2D0ER		__REG(0x40f40010)	/* Application Subsystem Wake-Up from D2 to D0 Enable */
-#define AD2D0SR		__REG(0x40f40014)	/* Application Subsystem Wake-Up from D2 to D0 Status */
-#define AD2D1ER		__REG(0x40f40018)	/* Application Subsystem Wake-Up from D2 to D1 Enable */
-#define AD2D1SR		__REG(0x40f4001c)	/* Application Subsystem Wake-Up from D2 to D1 Status */
-#define AD1D0ER		__REG(0x40f40020)	/* Application Subsystem Wake-Up from D1 to D0 Enable */
-#define AD1D0SR		__REG(0x40f40024)	/* Application Subsystem Wake-Up from D1 to D0 Status */
-#define AGENP		__REG(0x40f4002c)	/* Application Subsystem General Purpose */
-#define AD3R		__REG(0x40f40030)	/* Application Subsystem D3 Configuration */
-#define AD2R		__REG(0x40f40034)	/* Application Subsystem D2 Configuration */
-#define AD1R		__REG(0x40f40038)	/* Application Subsystem D1 Configuration */
-
-/*
- * Application Subsystem Configuration bits.
- */
-#define ASCR_RDH		(1 << 31)
-#define ASCR_D1S		(1 << 2)
-#define ASCR_D2S		(1 << 1)
-#define ASCR_D3S		(1 << 0)
-
-/*
- * Application Reset Status bits.
- */
-#define ARSR_GPR		(1 << 3)
-#define ARSR_LPMR		(1 << 2)
-#define ARSR_WDT		(1 << 1)
-#define ARSR_HWR		(1 << 0)
-
-/*
- * Application Subsystem Wake-Up bits.
- */
-#define ADXER_WRTC		(1 << 31)	/* RTC */
-#define ADXER_WOST		(1 << 30)	/* OS Timer */
-#define ADXER_WTSI		(1 << 29)	/* Touchscreen */
-#define ADXER_WUSBH		(1 << 28)	/* USB host */
-#define ADXER_WUSB2		(1 << 26)	/* USB client 2.0 */
-#define ADXER_WMSL0		(1 << 24)	/* MSL port 0*/
-#define ADXER_WDMUX3		(1 << 23)	/* USB EDMUX3 */
-#define ADXER_WDMUX2		(1 << 22)	/* USB EDMUX2 */
-#define ADXER_WKP		(1 << 21)	/* Keypad */
-#define ADXER_WUSIM1		(1 << 20)	/* USIM Port 1 */
-#define ADXER_WUSIM0		(1 << 19)	/* USIM Port 0 */
-#define ADXER_WOTG		(1 << 16)	/* USBOTG input */
-#define ADXER_MFP_WFLASH	(1 << 15)	/* MFP: Data flash busy */
-#define ADXER_MFP_GEN12		(1 << 14)	/* MFP: MMC3/GPIO/OST inputs */
-#define ADXER_MFP_WMMC2		(1 << 13)	/* MFP: MMC2 */
-#define ADXER_MFP_WMMC1		(1 << 12)	/* MFP: MMC1 */
-#define ADXER_MFP_WI2C		(1 << 11)	/* MFP: I2C */
-#define ADXER_MFP_WSSP4		(1 << 10)	/* MFP: SSP4 */
-#define ADXER_MFP_WSSP3		(1 << 9)	/* MFP: SSP3 */
-#define ADXER_MFP_WMAXTRIX	(1 << 8)	/* MFP: matrix keypad */
-#define ADXER_MFP_WUART3	(1 << 7)	/* MFP: UART3 */
-#define ADXER_MFP_WUART2	(1 << 6)	/* MFP: UART2 */
-#define ADXER_MFP_WUART1	(1 << 5)	/* MFP: UART1 */
-#define ADXER_MFP_WSSP2		(1 << 4)	/* MFP: SSP2 */
-#define ADXER_MFP_WSSP1		(1 << 3)	/* MFP: SSP1 */
-#define ADXER_MFP_WAC97		(1 << 2)	/* MFP: AC97 */
-#define ADXER_WEXTWAKE1		(1 << 1)	/* External Wake 1 */
-#define ADXER_WEXTWAKE0		(1 << 0)	/* External Wake 0 */
-
-/*
- * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
- */
-#define ADXR_L2			(1 << 8)
-#define ADXR_R5			(1 << 5)
-#define ADXR_R4			(1 << 4)
-#define ADXR_R3			(1 << 3)
-#define ADXR_R2			(1 << 2)
-#define ADXR_R1			(1 << 1)
-#define ADXR_R0			(1 << 0)
-
-/*
- * Values for PWRMODE CP15 register
- */
-#define PXA3xx_PM_S3D4C4	0x07	/* aka deep sleep */
-#define PXA3xx_PM_S2D3C4	0x06	/* aka sleep */
-#define PXA3xx_PM_S0D2C2	0x03	/* aka standby */
-#define PXA3xx_PM_S0D1C2	0x02	/* aka LCD refresh */
-#define PXA3xx_PM_S0D0C1	0x01
-
-/*
- * Application Subsystem Clock
- */
-#define ACCR		__REG(0x41340000)	/* Application Subsystem Clock Configuration Register */
-#define ACSR		__REG(0x41340004)	/* Application Subsystem Clock Status Register */
-#define AICSR		__REG(0x41340008)	/* Application Subsystem Interrupt Control/Status Register */
-#define CKENA		__REG(0x4134000C)	/* A Clock Enable Register */
-#define CKENB		__REG(0x41340010)	/* B Clock Enable Register */
-#define CKENC		__REG(0x41340024)	/* C Clock Enable Register */
-#define AC97_DIV	__REG(0x41340014)	/* AC97 clock divisor value register */
-
-#define ACCR_XPDIS		(1 << 31)	/* Core PLL Output Disable */
-#define ACCR_SPDIS		(1 << 30)	/* System PLL Output Disable */
-#define ACCR_D0CS		(1 << 26)	/* D0 Mode Clock Select */
-#define ACCR_PCCE		(1 << 11)	/* Power Mode Change Clock Enable */
-#define ACCR_DDR_D0CS		(1 << 7)	/* DDR SDRAM clock frequency in D0CS (PXA31x only) */
-
-#define ACCR_SMCFS_MASK		(0x7 << 23)	/* Static Memory Controller Frequency Select */
-#define ACCR_SFLFS_MASK		(0x3 << 18)	/* Frequency Select for Internal Memory Controller */
-#define ACCR_XSPCLK_MASK	(0x3 << 16)	/* Core Frequency during Frequency Change */
-#define ACCR_HSS_MASK		(0x3 << 14)	/* System Bus-Clock Frequency Select */
-#define ACCR_DMCFS_MASK		(0x3 << 12)	/* Dynamic Memory Controller Clock Frequency Select */
-#define ACCR_XN_MASK		(0x7 << 8)	/* Core PLL Turbo-Mode-to-Run-Mode Ratio */
-#define ACCR_XL_MASK		(0x1f)		/* Core PLL Run-Mode-to-Oscillator Ratio */
-
-#define ACCR_SMCFS(x)		(((x) & 0x7) << 23)
-#define ACCR_SFLFS(x)		(((x) & 0x3) << 18)
-#define ACCR_XSPCLK(x)		(((x) & 0x3) << 16)
-#define ACCR_HSS(x)		(((x) & 0x3) << 14)
-#define ACCR_DMCFS(x)		(((x) & 0x3) << 12)
-#define ACCR_XN(x)		(((x) & 0x7) << 8)
-#define ACCR_XL(x)		((x) & 0x1f)
-
-/*
- * Clock Enable Bit
- */
-#define CKEN_LCD	1	/* < LCD Clock Enable */
-#define CKEN_USBH	2	/* < USB host clock enable */
-#define CKEN_CAMERA	3	/* < Camera interface clock enable */
-#define CKEN_NAND	4	/* < NAND Flash Controller Clock Enable */
-#define CKEN_USB2	6	/* < USB 2.0 client clock enable. */
-#define CKEN_DMC	8	/* < Dynamic Memory Controller clock enable */
-#define CKEN_SMC	9	/* < Static Memory Controller clock enable */
-#define CKEN_ISC	10	/* < Internal SRAM Controller clock enable */
-#define CKEN_BOOT	11	/* < Boot rom clock enable */
-#define CKEN_MMC1	12	/* < MMC1 Clock enable */
-#define CKEN_MMC2	13	/* < MMC2 clock enable */
-#define CKEN_KEYPAD	14	/* < Keypand Controller Clock Enable */
-#define CKEN_CIR	15	/* < Consumer IR Clock Enable */
-#define CKEN_USIM0	17	/* < USIM[0] Clock Enable */
-#define CKEN_USIM1	18	/* < USIM[1] Clock Enable */
-#define CKEN_TPM	19	/* < TPM clock enable */
-#define CKEN_UDC	20	/* < UDC clock enable */
-#define CKEN_BTUART	21	/* < BTUART clock enable */
-#define CKEN_FFUART	22	/* < FFUART clock enable */
-#define CKEN_STUART	23	/* < STUART clock enable */
-#define CKEN_AC97	24	/* < AC97 clock enable */
-#define CKEN_TOUCH	25	/* < Touch screen Interface Clock Enable */
-#define CKEN_SSP1	26	/* < SSP1 clock enable */
-#define CKEN_SSP2	27	/* < SSP2 clock enable */
-#define CKEN_SSP3	28	/* < SSP3 clock enable */
-#define CKEN_SSP4	29	/* < SSP4 clock enable */
-#define CKEN_MSL0	30	/* < MSL0 clock enable */
-#define CKEN_PWM0	32	/* < PWM[0] clock enable */
-#define CKEN_PWM1	33	/* < PWM[1] clock enable */
-#define CKEN_I2C	36	/* < I2C clock enable */
-#define CKEN_INTC	38	/* < Interrupt controller clock enable */
-#define CKEN_GPIO	39	/* < GPIO clock enable */
-#define CKEN_1WIRE	40	/* < 1-wire clock enable */
-#define CKEN_HSIO2	41	/* < HSIO2 clock enable */
-#define CKEN_MINI_IM	48	/* < Mini-IM */
-#define CKEN_MINI_LCD	49	/* < Mini LCD */
-
-#define CKEN_MMC3	5	/* < MMC3 Clock Enable */
-#define CKEN_MVED	43	/* < MVED clock enable */
-
-/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
-#define CKEN_PXA300_GCU		42	/* Graphics controller clock enable */
-#define CKEN_PXA320_GCU		7	/* Graphics controller clock enable */
-
-/*
- * Static Memory Controller
- */
-#define MSC0		__REG(0x4a000008)	/* Static Memory Control 0 */
-#define MSC1		__REG(0x4a00000c)	/* Static Memory Control 1 */
-#define MECR		__REG(0x4a000014)	/* Expansion Memory Configuration */
-#define SXCNFG		__REG(0x4a00001c)	/* Synchronous Static Memory Control */
-#define MCMEM0		__REG(0x4a000028)	/* Expansion Memory Timing */
-#define MCATT0		__REG(0x4a000030)	/* Expansion Memory Timing */
-#define MCIO0		__REG(0x4a000038)	/* Expansion Memory Timing */
-#define MEMCLKCFG	__REG(0x4a000068)	/* Clock configuration */
-#define CSADRCFG0	__REG(0x4a000080)	/* CS0 address configuration */
-#define CSADRCFG1	__REG(0x4a000084)	/* CS1 address configuration */
-#define CSADRCFG2	__REG(0x4a000088)	/* CS2 address configuration */
-#define CSADRCFG3	__REG(0x4a00008c)	/* CS3 address configuration */
-#define CSADRCFGP	__REG(0x4a000090)	/* CSP address configuration */
-#define CSMSADRCFG	__REG(0x4a0000a0)	/* CSP address configuration */
-
-#endif	/* !__MACH_PXA3XX_REGS */
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
deleted file mode 100644
index 23cbea99c8..0000000000
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This structure describes the machine which we are running on.
- */
-#ifndef _PXAFB_
-#define _PXAFB_
-
-#include <fb.h>
-
-/*
- * Supported LCD connections
- *
- * bits 0 - 3: for LCD panel type:
- *
- *   STN  - for passive matrix
- *   DSTN - for dual scan passive matrix
- *   TFT  - for active matrix
- *
- * bits 4 - 9 : for bus width
- * bits 10-17 : for AC Bias Pin Frequency
- * bit     18 : for output enable polarity
- * bit     19 : for pixel clock edge
- * bit     20 : for output pixel format when base is RGBT16
- */
-#define LCD_CONN_TYPE(_x)	((_x) & 0x0f)
-#define LCD_CONN_WIDTH(_x)	(((_x) >> 4) & 0x1f)
-
-#define LCD_TYPE_MASK		0xf
-#define LCD_TYPE_UNKNOWN	0
-#define LCD_TYPE_MONO_STN	1
-#define LCD_TYPE_MONO_DSTN	2
-#define LCD_TYPE_COLOR_STN	3
-#define LCD_TYPE_COLOR_DSTN	4
-#define LCD_TYPE_COLOR_TFT	5
-#define LCD_TYPE_SMART_PANEL	6
-#define LCD_TYPE_MAX		7
-
-#define LCD_MONO_STN_4BPP	((4  << 4) | LCD_TYPE_MONO_STN)
-#define LCD_MONO_STN_8BPP	((8  << 4) | LCD_TYPE_MONO_STN)
-#define LCD_MONO_DSTN_8BPP	((8  << 4) | LCD_TYPE_MONO_DSTN)
-#define LCD_COLOR_STN_8BPP	((8  << 4) | LCD_TYPE_COLOR_STN)
-#define LCD_COLOR_DSTN_16BPP	((16 << 4) | LCD_TYPE_COLOR_DSTN)
-#define LCD_COLOR_TFT_8BPP	((8  << 4) | LCD_TYPE_COLOR_TFT)
-#define LCD_COLOR_TFT_16BPP	((16 << 4) | LCD_TYPE_COLOR_TFT)
-#define LCD_COLOR_TFT_18BPP	((18 << 4) | LCD_TYPE_COLOR_TFT)
-#define LCD_SMART_PANEL_8BPP	((8  << 4) | LCD_TYPE_SMART_PANEL)
-#define LCD_SMART_PANEL_16BPP	((16 << 4) | LCD_TYPE_SMART_PANEL)
-#define LCD_SMART_PANEL_18BPP	((18 << 4) | LCD_TYPE_SMART_PANEL)
-
-#define LCD_AC_BIAS_FREQ(x)	(((x) & 0xff) << 10)
-#define LCD_BIAS_ACTIVE_HIGH	(0 << 18)
-#define LCD_BIAS_ACTIVE_LOW	(1 << 18)
-#define LCD_PCLK_EDGE_RISE	(0 << 19)
-#define LCD_PCLK_EDGE_FALL	(1 << 19)
-#define LCD_ALTERNATE_MAPPING	(1 << 20)
-
-struct pxafb_videomode {
-	struct fb_videomode	mode;
-	u8			bpp;
-};
-
-/**
- * Define relevant framebuffer information
- */
-struct pxafb_platform_data {
-	struct pxafb_videomode	*mode;
-	unsigned int		lcd_conn;
-
-	/** force a memory area to be used, else NULL for dynamic allocation */
-	void			*framebuffer;
-
-	void			(*lcd_power)(int);
-	void			(*backlight_power)(int);
-};
-
-/**
- * @file
- * @brief PXA related framebuffer declarations
- */
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
deleted file mode 100644
index 68464ce1c1..0000000000
--- a/arch/arm/mach-pxa/include/mach/regs-intc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __ASM_MACH_REGS_INTC_H
-#define __ASM_MACH_REGS_INTC_H
-
-#include <mach/hardware.h>
-
-/*
- * Interrupt Controller
- */
-
-#define ICIP		__REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
-#define ICMR		__REG(0x40D00004)  /* Interrupt Controller Mask Register */
-#define ICLR		__REG(0x40D00008)  /* Interrupt Controller Level Register */
-#define ICFP		__REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
-#define ICPR		__REG(0x40D00010)  /* Interrupt Controller Pending Register */
-#define ICCR		__REG(0x40D00014)  /* Interrupt Controller Control Register */
-#define ICHP		__REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
-
-#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
-#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
-#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
-
-#define ICIP3		__REG(0x40D00130)  /* Interrupt Controller IRQ Pending Register 3 */
-#define ICMR3		__REG(0x40D00134)  /* Interrupt Controller Mask Register 3 */
-#define ICLR3		__REG(0x40D00138)  /* Interrupt Controller Level Register 3 */
-#define ICFP3		__REG(0x40D0013C)  /* Interrupt Controller FIQ Pending Register 3 */
-#define ICPR3		__REG(0x40D00140)  /* Interrupt Controller Pending Register 3 */
-
-#define IPR(x)		__REG(0x40D0001C + (x < 32 ? (x << 2)		\
-				: (x < 64 ? (0x94 + ((x - 32) << 2))	\
-				: (0x128 + ((x - 64) << 2)))))
-
-#endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
deleted file mode 100644
index a6d0817ae6..0000000000
--- a/arch/arm/mach-pxa/include/mach/regs-lcd.h
+++ /dev/null
@@ -1,180 +0,0 @@
-#ifndef __ASM_ARCH_REGS_LCD_H
-#define __ASM_ARCH_REGS_LCD_H
-
-/*
- * LCD Controller Registers and Bits Definitions
- */
-#define LCCR0		(0x000)	/* LCD Controller Control Register 0 */
-#define LCCR1		(0x004)	/* LCD Controller Control Register 1 */
-#define LCCR2		(0x008)	/* LCD Controller Control Register 2 */
-#define LCCR3		(0x00C)	/* LCD Controller Control Register 3 */
-#define LCCR4		(0x010)	/* LCD Controller Control Register 4 */
-#define LCCR5		(0x014)	/* LCD Controller Control Register 5 */
-#define LCSR		(0x038)	/* LCD Controller Status Register 0 */
-#define LCSR1		(0x034)	/* LCD Controller Status Register 1 */
-#define LIIDR		(0x03C)	/* LCD Controller Interrupt ID Register */
-#define TMEDRGBR	(0x040)	/* TMED RGB Seed Register */
-#define TMEDCR		(0x044)	/* TMED Control Register */
-
-#define FBR0		(0x020)	/* DMA Channel 0 Frame Branch Register */
-#define FBR1		(0x024)	/* DMA Channel 1 Frame Branch Register */
-#define FBR2		(0x028) /* DMA Channel 2 Frame Branch Register */
-#define FBR3		(0x02C) /* DMA Channel 2 Frame Branch Register */
-#define FBR4		(0x030) /* DMA Channel 2 Frame Branch Register */
-#define FBR5		(0x110) /* DMA Channel 2 Frame Branch Register */
-#define FBR6		(0x114) /* DMA Channel 2 Frame Branch Register */
-
-#define OVL1C1		(0x050)	/* Overlay 1 Control Register 1 */
-#define OVL1C2		(0x060)	/* Overlay 1 Control Register 2 */
-#define OVL2C1		(0x070)	/* Overlay 2 Control Register 1 */
-#define OVL2C2		(0x080)	/* Overlay 2 Control Register 2 */
-
-#define CMDCR		(0x100)	/* Command Control Register */
-#define PRSR		(0x104)	/* Panel Read Status Register */
-
-#define LCCR3_BPP(x)	((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0))
-
-#define LCCR3_PDFOR_0	(0 << 30)
-#define LCCR3_PDFOR_1	(1 << 30)
-#define LCCR3_PDFOR_2	(2 << 30)
-#define LCCR3_PDFOR_3	(3 << 30)
-
-#define LCCR4_PAL_FOR_0	(0 << 15)
-#define LCCR4_PAL_FOR_1	(1 << 15)
-#define LCCR4_PAL_FOR_2	(2 << 15)
-#define LCCR4_PAL_FOR_3	(3 << 15)
-#define LCCR4_PAL_FOR_MASK	(3 << 15)
-
-#define FDADR0		(0x200)	/* DMA Channel 0 Frame Descriptor Address Register */
-#define FDADR1		(0x210)	/* DMA Channel 1 Frame Descriptor Address Register */
-#define FDADR2		(0x220)	/* DMA Channel 2 Frame Descriptor Address Register */
-#define FDADR3		(0x230)	/* DMA Channel 3 Frame Descriptor Address Register */
-#define FDADR4		(0x240)	/* DMA Channel 4 Frame Descriptor Address Register */
-#define FDADR5		(0x250)	/* DMA Channel 5 Frame Descriptor Address Register */
-#define FDADR6		(0x260) /* DMA Channel 6 Frame Descriptor Address Register */
-
-#define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
-#define LCCR0_CMS	(1 << 1)	/* Color/Monochrome Display Select */
-#define LCCR0_Color	(LCCR0_CMS*0)	/*  Color display */
-#define LCCR0_Mono	(LCCR0_CMS*1)	/*  Monochrome display */
-#define LCCR0_SDS	(1 << 2)	/* Single/Dual Panel Display Select */
-#define LCCR0_Sngl	(LCCR0_SDS*0)	/*  Single panel display */
-#define LCCR0_Dual	(LCCR0_SDS*1)	/*  Dual panel display */
-
-#define LCCR0_LDM	(1 << 3)	/* LCD Disable Done Mask */
-#define LCCR0_SFM	(1 << 4)	/* Start of frame mask */
-#define LCCR0_IUM	(1 << 5)	/* Input FIFO underrun mask */
-#define LCCR0_EFM	(1 << 6)	/* End of Frame mask */
-#define LCCR0_PAS	(1 << 7)	/* Passive/Active display Select */
-#define LCCR0_Pas	(LCCR0_PAS*0)	/*  Passive display (STN) */
-#define LCCR0_Act	(LCCR0_PAS*1)	/*  Active display (TFT) */
-#define LCCR0_DPD	(1 << 9)	/* Double Pixel Data (monochrome) */
-#define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome display */
-#define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome display */
-#define LCCR0_DIS	(1 << 10)	/* LCD Disable */
-#define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
-#define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
-#define LCCR0_PDD_S	12
-#define LCCR0_BM	(1 << 20)	/* Branch mask */
-#define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
-#define LCCR0_LCDT	(1 << 22)	/* LCD panel type */
-#define LCCR0_RDSTM	(1 << 23)	/* Read status interrupt mask */
-#define LCCR0_CMDIM	(1 << 24)	/* Command interrupt mask */
-#define LCCR0_OUC	(1 << 25)	/* Overlay Underlay control bit */
-#define LCCR0_LDDALT	(1 << 26)	/* LDD alternate mapping control */
-
-#define LCCR1_DisWdth(Pixel)	(((Pixel) - 1) << 0)	/* Pixels Per Line - 1 */
-#define LCCR1_HorSnchWdth(Tpix)	(((Tpix) - 1) << 10)	/* Horizontal Synchronization */
-#define LCCR1_EndLnDel(Tpix)	(((Tpix) - 1) << 16)	/* End-of-Line pixel clock Wait - 1 */
-#define LCCR1_BegLnDel(Tpix)	(((Tpix) - 1) << 24)	/* Beginning-of-Line pixel clock */
-
-#define LCCR2_DisHght(Line)	(((Line) - 1) << 0)	/* Line Per Panel - 1 */
-#define LCCR2_VrtSnchWdth(Tln)	(((Tln) - 1) << 10)	/* Vertical Synchronization pulse - 1 */
-#define LCCR2_EndFrmDel(Tln)	((Tln) << 16)	/* End-of-Frame line clock Wait */
-#define LCCR2_BegFrmDel(Tln)	((Tln) << 24)	/* Beginning-of-Frame line clock */
-
-#define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
-#define LCCR3_API_S	16
-#define LCCR3_VSP	(1 << 20)	/* vertical sync polarity */
-#define LCCR3_HSP	(1 << 21)	/* horizontal sync polarity */
-#define LCCR3_PCP	(1 << 22)	/* Pixel Clock Polarity (L_PCLK) */
-#define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge */
-#define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge */
-
-#define LCCR3_OEP	(1 << 23)	/* Output Enable Polarity */
-#define LCCR3_OutEnH	(LCCR3_OEP*0)	/*  Output Enable active High */
-#define LCCR3_OutEnL	(LCCR3_OEP*1)	/*  Output Enable active Low */
-
-#define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
-#define LCCR3_PixClkDiv(Div)	((Div) << 0)	/* Pixel Clock Divisor */
-
-#define LCCR3_Acb(Acb)	((Acb) << 8)	/* AC Bias */
-
-#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  HSP Active High */
-#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  HSP Active Low */
-
-#define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  VSP Active High */
-#define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  VSP Active Low */
-
-#define LCCR5_IUM(x)	(1 << ((x) + 23)) /* input underrun mask */
-#define LCCR5_BSM(x)	(1 << ((x) + 15)) /* branch mask */
-#define LCCR5_EOFM(x)	(1 << ((x) + 7))  /* end of frame mask */
-#define LCCR5_SOFM(x)	(1 << ((x) + 0))  /* start of frame mask */
-
-#define LCSR_LDD	(1 << 0)	/* LCD Disable Done */
-#define LCSR_SOF	(1 << 1)	/* Start of frame */
-#define LCSR_BER	(1 << 2)	/* Bus error */
-#define LCSR_ABC	(1 << 3)	/* AC Bias count */
-#define LCSR_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
-#define LCSR_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
-#define LCSR_OU		(1 << 6)	/* output FIFO underrun */
-#define LCSR_QD		(1 << 7)	/* quick disable */
-#define LCSR_EOF	(1 << 8)	/* end of frame */
-#define LCSR_BS		(1 << 9)	/* branch status */
-#define LCSR_SINT	(1 << 10)	/* subsequent interrupt */
-#define LCSR_RD_ST	(1 << 11)	/* read status */
-#define LCSR_CMD_INT	(1 << 12)	/* command interrupt */
-
-#define LCSR1_IU(x)	(1 << ((x) + 23)) /* Input FIFO underrun */
-#define LCSR1_BS(x)	(1 << ((x) + 15)) /* Branch Status */
-#define LCSR1_EOF(x)	(1 << ((x) + 7))  /* End of Frame Status */
-#define LCSR1_SOF(x)	(1 << ((x) - 1))  /* Start of Frame Status */
-
-#define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
-#define LDCMD_EOFINT	(1 << 21)	/* End of Frame Interrupt */
-
-/* overlay control registers */
-#define OVLxC1_PPL(x)	((((x) - 1) & 0x3ff) << 0)	/* Pixels Per Line */
-#define OVLxC1_LPO(x)	((((x) - 1) & 0x3ff) << 10)	/* Number of Lines */
-#define OVLxC1_BPP(x)	(((x) & 0xf) << 20)	/* Bits Per Pixel */
-#define OVLxC1_OEN	(1 << 31)		/* Enable bit for Overlay */
-#define OVLxC2_XPOS(x)	(((x) & 0x3ff) << 0)	/* Horizontal Position */
-#define OVLxC2_YPOS(x)	(((x) & 0x3ff) << 10)	/* Vertical Position */
-#define OVL2C2_PFOR(x)	(((x) & 0x7) << 20)	/* Pixel Format */
-
-/* smartpanel related */
-#define PRSR_DATA(x)	((x) & 0xff)	/* Panel Data */
-#define PRSR_A0		(1 << 8)	/* Read Data Source */
-#define PRSR_ST_OK	(1 << 9)	/* Status OK */
-#define PRSR_CON_NT	(1 << 10)	/* Continue to Next Command */
-
-#define SMART_CMD_A0			 (0x1 << 8)
-#define SMART_CMD_READ_STATUS_REG	 (0x0 << 9)
-#define SMART_CMD_READ_FRAME_BUFFER	((0x0 << 9) | SMART_CMD_A0)
-#define SMART_CMD_WRITE_COMMAND		 (0x1 << 9)
-#define SMART_CMD_WRITE_DATA		((0x1 << 9) | SMART_CMD_A0)
-#define SMART_CMD_WRITE_FRAME		((0x2 << 9) | SMART_CMD_A0)
-#define SMART_CMD_WAIT_FOR_VSYNC	 (0x3 << 9)
-#define SMART_CMD_NOOP			 (0x4 << 9)
-#define SMART_CMD_INTERRUPT		 (0x5 << 9)
-
-#define SMART_CMD(x)	(SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
-#define SMART_DAT(x)	(SMART_CMD_WRITE_DATA | ((x) & 0xff))
-
-/* SMART_DELAY() is introduced for software controlled delay primitive which
- * can be inserted between command sequences, unused command 0x6 is used here
- * and delay ranges from 0ms ~ 255ms
- */
-#define SMART_CMD_DELAY		(0x6 << 9)
-#define SMART_DELAY(ms)		(SMART_CMD_DELAY | ((ms) & 0xff))
-#endif /* __ASM_ARCH_REGS_LCD_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h
deleted file mode 100644
index a3e5f86ef6..0000000000
--- a/arch/arm/mach-pxa/include/mach/regs-ost.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __ASM_MACH_REGS_OST_H
-#define __ASM_MACH_REGS_OST_H
-
-#include <mach/hardware.h>
-
-/*
- * OS Timer & Match Registers
- */
-
-#define OSMR0		__REG(0x40A00000)  /* */
-#define OSMR1		__REG(0x40A00004)  /* */
-#define OSMR2		__REG(0x40A00008)  /* */
-#define OSMR3		__REG(0x40A0000C)  /* */
-#define OSMR4		__REG(0x40A00080)  /* */
-#define OSCR		__REG(0x40A00010)  /* OS Timer Counter Register */
-#define OSCR4		__REG(0x40A00040)  /* OS Timer Counter Register */
-#define OMCR4		__REG(0x40A000C0)  /* */
-#define OSSR		__REG(0x40A00014)  /* OS Timer Status Register */
-#define OWER		__REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
-#define OIER		__REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
-
-#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
-#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
-#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
-#define OSSR_M0		(1 << 0)	/* Match status channel 0 */
-
-#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */
-
-#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
-#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
-#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
-#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
-
-#endif /* __ASM_MACH_REGS_OST_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-pwm.h b/arch/arm/mach-pxa/include/mach/regs-pwm.h
deleted file mode 100644
index 9fdcbb64ae..0000000000
--- a/arch/arm/mach-pxa/include/mach/regs-pwm.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#ifndef __ASM_MACH_REGS_PWM_H
-#define __ASM_MACH_REGS_PWM_H
-
-#include <mach/hardware.h>
-
-/*
- * Pulse modulator registers
- */
-#define PWM0		0x40B00000
-#define PWM1		0x40C00000
-#define PWM0slave	0x40B00010
-#define PWM1slave	0x40C00010
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/udc_pxa2xx.h b/arch/arm/mach-pxa/include/mach/udc_pxa2xx.h
deleted file mode 100644
index dcdd36a3b4..0000000000
--- a/arch/arm/mach-pxa/include/mach/udc_pxa2xx.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/udc_pxa2xx.h
- *
- * This supports machine-specific differences in how the PXA2xx
- * USB Device Controller (UDC) is wired.
- *
- * It is set in linux/arch/arm/mach-pxa/<machine>.c or in
- * linux/arch/mach-ixp4xx/<machine>.c and used in
- * the probe routine of linux/drivers/usb/gadget/pxa2xx_udc.c
- */
-
-struct pxa2xx_udc_mach_info {
-	int  (*udc_is_connected)(void);		/* do we see host? */
-	void (*udc_command)(int cmd);
-#define	PXA2XX_UDC_CMD_CONNECT		0	/* let host see us */
-#define	PXA2XX_UDC_CMD_DISCONNECT	1	/* so host won't see us */
-
-	/* Boards following the design guidelines in the developer's manual,
-	 * with on-chip GPIOs not Lubbock's weird hardware, can have a sane
-	 * VBUS IRQ and omit the methods above.  Store the GPIO number
-	 * here.  Note that sometimes the signals go through inverters...
-	 */
-	bool	gpio_pullup_inverted;
-	int	gpio_pullup;			/* high == pullup activated */
-};
-
diff --git a/arch/arm/mach-pxa/include/plat/gpio.h b/arch/arm/mach-pxa/include/plat/gpio.h
deleted file mode 100644
index 35f90715e0..0000000000
--- a/arch/arm/mach-pxa/include/plat/gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef __PLAT_GPIO_H
-#define __PLAT_GPIO_H
-
-#include <mach/gpio.h>
-
-/*
- * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
- * one set of registers. The register offsets are organized below:
- *
- *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
- * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
- * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
- * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
- *
- * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
- * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
- * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
- *
- * NOTE:
- *   BANK 3 is only available on PXA27x and later processors.
- *   BANK 4 and 5 are only available on PXA935
- */
-
-#define GPIO_BANK(n)	(GPIO_REGS_VIRT + BANK_OFF(n))
-
-#define GPLR_OFFSET	0x00
-#define GPDR_OFFSET	0x0C
-#define GPSR_OFFSET	0x18
-#define GPCR_OFFSET	0x24
-#define GRER_OFFSET	0x30
-#define GFER_OFFSET	0x3C
-#define GEDR_OFFSET	0x48
-
-/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
- * Those cases currently cause holes in the GPIO number space, the
- * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
- */
-extern int pxa_last_gpio;
-
-extern int pxa_init_gpio(int start, int end);
-
-#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/mach-pxa/include/plat/mfp.h b/arch/arm/mach-pxa/include/plat/mfp.h
deleted file mode 100644
index aedb956cd3..0000000000
--- a/arch/arm/mach-pxa/include/plat/mfp.h
+++ /dev/null
@@ -1,469 +0,0 @@
-/*
- * arch/arm/plat-pxa/include/plat/mfp.h
- *
- *   Common Multi-Function Pin Definitions
- *
- * Copyright (C) 2007 Marvell International Ltd.
- *
- * 2007-8-21: eric miao <eric.miao@marvell.com>
- *            initial version
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_PLAT_MFP_H
-#define __ASM_PLAT_MFP_H
-
-#define mfp_to_gpio(m)	((m) % 256)
-
-/* list of all the configurable MFP pins */
-enum {
-	MFP_PIN_INVALID = -1,
-
-	MFP_PIN_GPIO0 = 0,
-	MFP_PIN_GPIO1,
-	MFP_PIN_GPIO2,
-	MFP_PIN_GPIO3,
-	MFP_PIN_GPIO4,
-	MFP_PIN_GPIO5,
-	MFP_PIN_GPIO6,
-	MFP_PIN_GPIO7,
-	MFP_PIN_GPIO8,
-	MFP_PIN_GPIO9,
-	MFP_PIN_GPIO10,
-	MFP_PIN_GPIO11,
-	MFP_PIN_GPIO12,
-	MFP_PIN_GPIO13,
-	MFP_PIN_GPIO14,
-	MFP_PIN_GPIO15,
-	MFP_PIN_GPIO16,
-	MFP_PIN_GPIO17,
-	MFP_PIN_GPIO18,
-	MFP_PIN_GPIO19,
-	MFP_PIN_GPIO20,
-	MFP_PIN_GPIO21,
-	MFP_PIN_GPIO22,
-	MFP_PIN_GPIO23,
-	MFP_PIN_GPIO24,
-	MFP_PIN_GPIO25,
-	MFP_PIN_GPIO26,
-	MFP_PIN_GPIO27,
-	MFP_PIN_GPIO28,
-	MFP_PIN_GPIO29,
-	MFP_PIN_GPIO30,
-	MFP_PIN_GPIO31,
-	MFP_PIN_GPIO32,
-	MFP_PIN_GPIO33,
-	MFP_PIN_GPIO34,
-	MFP_PIN_GPIO35,
-	MFP_PIN_GPIO36,
-	MFP_PIN_GPIO37,
-	MFP_PIN_GPIO38,
-	MFP_PIN_GPIO39,
-	MFP_PIN_GPIO40,
-	MFP_PIN_GPIO41,
-	MFP_PIN_GPIO42,
-	MFP_PIN_GPIO43,
-	MFP_PIN_GPIO44,
-	MFP_PIN_GPIO45,
-	MFP_PIN_GPIO46,
-	MFP_PIN_GPIO47,
-	MFP_PIN_GPIO48,
-	MFP_PIN_GPIO49,
-	MFP_PIN_GPIO50,
-	MFP_PIN_GPIO51,
-	MFP_PIN_GPIO52,
-	MFP_PIN_GPIO53,
-	MFP_PIN_GPIO54,
-	MFP_PIN_GPIO55,
-	MFP_PIN_GPIO56,
-	MFP_PIN_GPIO57,
-	MFP_PIN_GPIO58,
-	MFP_PIN_GPIO59,
-	MFP_PIN_GPIO60,
-	MFP_PIN_GPIO61,
-	MFP_PIN_GPIO62,
-	MFP_PIN_GPIO63,
-	MFP_PIN_GPIO64,
-	MFP_PIN_GPIO65,
-	MFP_PIN_GPIO66,
-	MFP_PIN_GPIO67,
-	MFP_PIN_GPIO68,
-	MFP_PIN_GPIO69,
-	MFP_PIN_GPIO70,
-	MFP_PIN_GPIO71,
-	MFP_PIN_GPIO72,
-	MFP_PIN_GPIO73,
-	MFP_PIN_GPIO74,
-	MFP_PIN_GPIO75,
-	MFP_PIN_GPIO76,
-	MFP_PIN_GPIO77,
-	MFP_PIN_GPIO78,
-	MFP_PIN_GPIO79,
-	MFP_PIN_GPIO80,
-	MFP_PIN_GPIO81,
-	MFP_PIN_GPIO82,
-	MFP_PIN_GPIO83,
-	MFP_PIN_GPIO84,
-	MFP_PIN_GPIO85,
-	MFP_PIN_GPIO86,
-	MFP_PIN_GPIO87,
-	MFP_PIN_GPIO88,
-	MFP_PIN_GPIO89,
-	MFP_PIN_GPIO90,
-	MFP_PIN_GPIO91,
-	MFP_PIN_GPIO92,
-	MFP_PIN_GPIO93,
-	MFP_PIN_GPIO94,
-	MFP_PIN_GPIO95,
-	MFP_PIN_GPIO96,
-	MFP_PIN_GPIO97,
-	MFP_PIN_GPIO98,
-	MFP_PIN_GPIO99,
-	MFP_PIN_GPIO100,
-	MFP_PIN_GPIO101,
-	MFP_PIN_GPIO102,
-	MFP_PIN_GPIO103,
-	MFP_PIN_GPIO104,
-	MFP_PIN_GPIO105,
-	MFP_PIN_GPIO106,
-	MFP_PIN_GPIO107,
-	MFP_PIN_GPIO108,
-	MFP_PIN_GPIO109,
-	MFP_PIN_GPIO110,
-	MFP_PIN_GPIO111,
-	MFP_PIN_GPIO112,
-	MFP_PIN_GPIO113,
-	MFP_PIN_GPIO114,
-	MFP_PIN_GPIO115,
-	MFP_PIN_GPIO116,
-	MFP_PIN_GPIO117,
-	MFP_PIN_GPIO118,
-	MFP_PIN_GPIO119,
-	MFP_PIN_GPIO120,
-	MFP_PIN_GPIO121,
-	MFP_PIN_GPIO122,
-	MFP_PIN_GPIO123,
-	MFP_PIN_GPIO124,
-	MFP_PIN_GPIO125,
-	MFP_PIN_GPIO126,
-	MFP_PIN_GPIO127,
-
-	MFP_PIN_GPIO128,
-	MFP_PIN_GPIO129,
-	MFP_PIN_GPIO130,
-	MFP_PIN_GPIO131,
-	MFP_PIN_GPIO132,
-	MFP_PIN_GPIO133,
-	MFP_PIN_GPIO134,
-	MFP_PIN_GPIO135,
-	MFP_PIN_GPIO136,
-	MFP_PIN_GPIO137,
-	MFP_PIN_GPIO138,
-	MFP_PIN_GPIO139,
-	MFP_PIN_GPIO140,
-	MFP_PIN_GPIO141,
-	MFP_PIN_GPIO142,
-	MFP_PIN_GPIO143,
-	MFP_PIN_GPIO144,
-	MFP_PIN_GPIO145,
-	MFP_PIN_GPIO146,
-	MFP_PIN_GPIO147,
-	MFP_PIN_GPIO148,
-	MFP_PIN_GPIO149,
-	MFP_PIN_GPIO150,
-	MFP_PIN_GPIO151,
-	MFP_PIN_GPIO152,
-	MFP_PIN_GPIO153,
-	MFP_PIN_GPIO154,
-	MFP_PIN_GPIO155,
-	MFP_PIN_GPIO156,
-	MFP_PIN_GPIO157,
-	MFP_PIN_GPIO158,
-	MFP_PIN_GPIO159,
-	MFP_PIN_GPIO160,
-	MFP_PIN_GPIO161,
-	MFP_PIN_GPIO162,
-	MFP_PIN_GPIO163,
-	MFP_PIN_GPIO164,
-	MFP_PIN_GPIO165,
-	MFP_PIN_GPIO166,
-	MFP_PIN_GPIO167,
-	MFP_PIN_GPIO168,
-	MFP_PIN_GPIO169,
-	MFP_PIN_GPIO170,
-	MFP_PIN_GPIO171,
-	MFP_PIN_GPIO172,
-	MFP_PIN_GPIO173,
-	MFP_PIN_GPIO174,
-	MFP_PIN_GPIO175,
-	MFP_PIN_GPIO176,
-	MFP_PIN_GPIO177,
-	MFP_PIN_GPIO178,
-	MFP_PIN_GPIO179,
-	MFP_PIN_GPIO180,
-	MFP_PIN_GPIO181,
-	MFP_PIN_GPIO182,
-	MFP_PIN_GPIO183,
-	MFP_PIN_GPIO184,
-	MFP_PIN_GPIO185,
-	MFP_PIN_GPIO186,
-	MFP_PIN_GPIO187,
-	MFP_PIN_GPIO188,
-	MFP_PIN_GPIO189,
-	MFP_PIN_GPIO190,
-	MFP_PIN_GPIO191,
-
-	MFP_PIN_GPIO255 = 255,
-
-	MFP_PIN_GPIO0_2,
-	MFP_PIN_GPIO1_2,
-	MFP_PIN_GPIO2_2,
-	MFP_PIN_GPIO3_2,
-	MFP_PIN_GPIO4_2,
-	MFP_PIN_GPIO5_2,
-	MFP_PIN_GPIO6_2,
-	MFP_PIN_GPIO7_2,
-	MFP_PIN_GPIO8_2,
-	MFP_PIN_GPIO9_2,
-	MFP_PIN_GPIO10_2,
-	MFP_PIN_GPIO11_2,
-	MFP_PIN_GPIO12_2,
-	MFP_PIN_GPIO13_2,
-	MFP_PIN_GPIO14_2,
-	MFP_PIN_GPIO15_2,
-	MFP_PIN_GPIO16_2,
-	MFP_PIN_GPIO17_2,
-
-	MFP_PIN_ULPI_STP,
-	MFP_PIN_ULPI_NXT,
-	MFP_PIN_ULPI_DIR,
-
-	MFP_PIN_nXCVREN,
-	MFP_PIN_DF_CLE_nOE,
-	MFP_PIN_DF_nADV1_ALE,
-	MFP_PIN_DF_SCLK_E,
-	MFP_PIN_DF_SCLK_S,
-	MFP_PIN_nBE0,
-	MFP_PIN_nBE1,
-	MFP_PIN_DF_nADV2_ALE,
-	MFP_PIN_DF_INT_RnB,
-	MFP_PIN_DF_nCS0,
-	MFP_PIN_DF_nCS1,
-	MFP_PIN_nLUA,
-	MFP_PIN_nLLA,
-	MFP_PIN_DF_nWE,
-	MFP_PIN_DF_ALE_nWE,
-	MFP_PIN_DF_nRE_nOE,
-	MFP_PIN_DF_ADDR0,
-	MFP_PIN_DF_ADDR1,
-	MFP_PIN_DF_ADDR2,
-	MFP_PIN_DF_ADDR3,
-	MFP_PIN_DF_IO0,
-	MFP_PIN_DF_IO1,
-	MFP_PIN_DF_IO2,
-	MFP_PIN_DF_IO3,
-	MFP_PIN_DF_IO4,
-	MFP_PIN_DF_IO5,
-	MFP_PIN_DF_IO6,
-	MFP_PIN_DF_IO7,
-	MFP_PIN_DF_IO8,
-	MFP_PIN_DF_IO9,
-	MFP_PIN_DF_IO10,
-	MFP_PIN_DF_IO11,
-	MFP_PIN_DF_IO12,
-	MFP_PIN_DF_IO13,
-	MFP_PIN_DF_IO14,
-	MFP_PIN_DF_IO15,
-	MFP_PIN_DF_nCS0_SM_nCS2,
-	MFP_PIN_DF_nCS1_SM_nCS3,
-	MFP_PIN_SM_nCS0,
-	MFP_PIN_SM_nCS1,
-	MFP_PIN_DF_WEn,
-	MFP_PIN_DF_REn,
-	MFP_PIN_DF_CLE_SM_OEn,
-	MFP_PIN_DF_ALE_SM_WEn,
-	MFP_PIN_DF_RDY0,
-	MFP_PIN_DF_RDY1,
-
-	MFP_PIN_SM_SCLK,
-	MFP_PIN_SM_BE0,
-	MFP_PIN_SM_BE1,
-	MFP_PIN_SM_ADV,
-	MFP_PIN_SM_ADVMUX,
-	MFP_PIN_SM_RDY,
-
-	MFP_PIN_MMC1_DAT7,
-	MFP_PIN_MMC1_DAT6,
-	MFP_PIN_MMC1_DAT5,
-	MFP_PIN_MMC1_DAT4,
-	MFP_PIN_MMC1_DAT3,
-	MFP_PIN_MMC1_DAT2,
-	MFP_PIN_MMC1_DAT1,
-	MFP_PIN_MMC1_DAT0,
-	MFP_PIN_MMC1_CMD,
-	MFP_PIN_MMC1_CLK,
-	MFP_PIN_MMC1_CD,
-	MFP_PIN_MMC1_WP,
-
-	/* additional pins on PXA930 */
-	MFP_PIN_GSIM_UIO,
-	MFP_PIN_GSIM_UCLK,
-	MFP_PIN_GSIM_UDET,
-	MFP_PIN_GSIM_nURST,
-	MFP_PIN_PMIC_INT,
-	MFP_PIN_RDY,
-
-	MFP_PIN_MAX,
-};
-
-/*
- * a possible MFP configuration is represented by a 32-bit integer
- *
- * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
- * bit 10..12 - Alternate Function Selection
- * bit 13..15 - Drive Strength
- * bit 16..18 - Low Power Mode State
- * bit 19..20 - Low Power Mode Edge Detection
- * bit 21..22 - Run Mode Pull State
- *
- * to facilitate the definition, the following macros are provided
- *
- * MFP_CFG_DEFAULT - default MFP configuration value, with
- *		alternate function = 0,
- *		drive strength = fast 3mA (MFP_DS03X)
- *		low power mode = default
- *		edge detection = none
- *
- * MFP_CFG	- default MFPR value with alternate function
- * MFP_CFG_DRV	- default MFPR value with alternate function and
- *		  pin drive strength
- * MFP_CFG_LPM	- default MFPR value with alternate function and
- *		  low power mode
- * MFP_CFG_X	- default MFPR value with alternate function,
- *		  pin drive strength and low power mode
- */
-
-typedef unsigned long mfp_cfg_t;
-
-#define MFP_PIN(x)		((x) & 0x3ff)
-
-#define MFP_AF0			(0x0 << 10)
-#define MFP_AF1			(0x1 << 10)
-#define MFP_AF2			(0x2 << 10)
-#define MFP_AF3			(0x3 << 10)
-#define MFP_AF4			(0x4 << 10)
-#define MFP_AF5			(0x5 << 10)
-#define MFP_AF6			(0x6 << 10)
-#define MFP_AF7			(0x7 << 10)
-#define MFP_AF_MASK		(0x7 << 10)
-#define MFP_AF(x)		(((x) >> 10) & 0x7)
-
-#define MFP_DS01X		(0x0 << 13)
-#define MFP_DS02X		(0x1 << 13)
-#define MFP_DS03X		(0x2 << 13)
-#define MFP_DS04X		(0x3 << 13)
-#define MFP_DS06X		(0x4 << 13)
-#define MFP_DS08X		(0x5 << 13)
-#define MFP_DS10X		(0x6 << 13)
-#define MFP_DS13X		(0x7 << 13)
-#define MFP_DS_MASK		(0x7 << 13)
-#define MFP_DS(x)		(((x) >> 13) & 0x7)
-
-#define MFP_LPM_DEFAULT		(0x0 << 16)
-#define MFP_LPM_DRIVE_LOW	(0x1 << 16)
-#define MFP_LPM_DRIVE_HIGH	(0x2 << 16)
-#define MFP_LPM_PULL_LOW	(0x3 << 16)
-#define MFP_LPM_PULL_HIGH	(0x4 << 16)
-#define MFP_LPM_FLOAT		(0x5 << 16)
-#define MFP_LPM_INPUT		(0x6 << 16)
-#define MFP_LPM_STATE_MASK	(0x7 << 16)
-#define MFP_LPM_STATE(x)	(((x) >> 16) & 0x7)
-
-#define MFP_LPM_EDGE_NONE	(0x0 << 19)
-#define MFP_LPM_EDGE_RISE	(0x1 << 19)
-#define MFP_LPM_EDGE_FALL	(0x2 << 19)
-#define MFP_LPM_EDGE_BOTH	(0x3 << 19)
-#define MFP_LPM_EDGE_MASK	(0x3 << 19)
-#define MFP_LPM_EDGE(x)		(((x) >> 19) & 0x3)
-
-#define MFP_PULL_NONE		(0x0 << 21)
-#define MFP_PULL_LOW		(0x1 << 21)
-#define MFP_PULL_HIGH		(0x2 << 21)
-#define MFP_PULL_BOTH		(0x3 << 21)
-#define MFP_PULL_FLOAT		(0x4 << 21)
-#define MFP_PULL_MASK		(0x7 << 21)
-#define MFP_PULL(x)		(((x) >> 21) & 0x7)
-
-#define MFP_CFG_DEFAULT		(MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
-				 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
-
-#define MFP_CFG(pin, af)		\
-	((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
-	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
-
-#define MFP_CFG_DRV(pin, af, drv)	\
-	((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
-	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
-
-#define MFP_CFG_LPM(pin, af, lpm)	\
-	((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
-	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
-
-#define MFP_CFG_X(pin, af, drv, lpm)	\
-	((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
-	 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
-
-#if defined(CONFIG_ARCH_PXA3XX)
-/*
- * each MFP pin will have a MFPR register, since the offset of the
- * register varies between processors, the processor specific code
- * should initialize the pin offsets by mfp_init()
- *
- * mfp_init_base() - accepts a virtual base for all MFPR registers and
- * initialize the MFP table to a default state
- *
- * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which
- * represents a range of MFP pins from "start" to "end", with the offset
- * begining at "offset", to define a single pin, let "end" = -1.
- *
- * use
- *
- * MFP_ADDR_X() to define a range of pins
- * MFP_ADDR()   to define a single pin
- * MFP_ADDR_END to signal the end of pin offset definitions
- */
-struct mfp_addr_map {
-	unsigned int	start;
-	unsigned int	end;
-	unsigned long	offset;
-};
-
-#define MFP_ADDR_X(start, end, offset) \
-	{ MFP_PIN_##start, MFP_PIN_##end, offset }
-
-#define MFP_ADDR(pin, offset) \
-	{ MFP_PIN_##pin, -1, offset }
-
-#define MFP_ADDR_END	{ MFP_PIN_INVALID, 0 }
-
-void __init mfp_init_base(void __iomem *mfpr_base);
-void __init mfp_init_addr(struct mfp_addr_map *map);
-
-/*
- * mfp_{read, write}()	- for direct read/write access to the MFPR register
- * mfp_config()		- for configuring a group of MFPR registers
- * mfp_config_lpm()	- configuring all low power MFPR registers for suspend
- * mfp_config_run()	- configuring all run time  MFPR registers after resume
- */
-unsigned long mfp_read(int mfp);
-void mfp_write(int mfp, unsigned long mfpr_val);
-void mfp_config(unsigned long *mfp_cfgs, int num);
-void mfp_config_run(void);
-void mfp_config_lpm(void);
-void mfp_init(void);
-#endif /* CONFIG_ARCH_PXA3XX */
-
-#endif /* __ASM_PLAT_MFP_H */
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 2456cef936..aca46c45b3 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -17,10 +17,10 @@
 #include <errno.h>
 #include <init.h>
 
-#include <mach/gpio.h>
-#include <mach/hardware.h>
-#include <mach/mfp-pxa2xx.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa/gpio.h>
+#include <mach/pxa/hardware.h>
+#include <mach/pxa/mfp-pxa2xx.h>
+#include <mach/pxa/pxa-regs.h>
 
 #define PGSR(x)		__REG2(0x40F00020, (x) << 2)
 #define __GAFR(u, x)	__REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c
index df4922453d..7f9e5113b8 100644
--- a/arch/arm/mach-pxa/mfp-pxa3xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa3xx.c
@@ -16,9 +16,9 @@
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/hardware.h>
-#include <mach/mfp-pxa3xx.h>
-#include <plat/mfp.h>
+#include <mach/pxa/hardware.h>
+#include <mach/pxa/mfp-pxa3xx.h>
+#include <mach/pxa/mfp.h>
 
 #define MFPR_SIZE	(PAGE_SIZE)
 
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
index e28378e6db..496ceb39d5 100644
--- a/arch/arm/mach-pxa/pxa2xx.c
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -16,8 +16,8 @@
 #include <init.h>
 #include <poweroff.h>
 #include <reset_source.h>
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa/hardware.h>
+#include <mach/pxa/pxa-regs.h>
 
 extern void pxa_suspend(int mode);
 
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index ccfd952b5e..ec49983962 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -16,8 +16,8 @@
 #include <init.h>
 #include <poweroff.h>
 #include <reset_source.h>
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa/hardware.h>
+#include <mach/pxa/pxa-regs.h>
 
 extern void pxa3xx_suspend(int mode);
 
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 1c678158c9..3d12dc54de 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -13,8 +13,8 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <mach/hardware.h>
-#include <mach/pxa2xx-regs.h>
+#include <mach/pxa/hardware.h>
+#include <mach/pxa/pxa2xx-regs.h>
 
 #define MDREFR_KDIV	0x200a4000	// all banks
 #define CCCR_SLEEP	0x00000107	// L=7 2N=2 A=0 PPDIS=0 CPDIS=0
diff --git a/arch/arm/mach-pxa/speed-pxa25x.c b/arch/arm/mach-pxa/speed-pxa25x.c
index 69143431e4..de3d5c251c 100644
--- a/arch/arm/mach-pxa/speed-pxa25x.c
+++ b/arch/arm/mach-pxa/speed-pxa25x.c
@@ -8,8 +8,8 @@
  */
 
 #include <common.h>
-#include <mach/clock.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa/clock.h>
+#include <mach/pxa/pxa-regs.h>
 
 /* Crystal clock: 13MHz */
 #define BASE_CLK	13000000
diff --git a/arch/arm/mach-pxa/speed-pxa27x.c b/arch/arm/mach-pxa/speed-pxa27x.c
index 1de034c677..5441dc3d70 100644
--- a/arch/arm/mach-pxa/speed-pxa27x.c
+++ b/arch/arm/mach-pxa/speed-pxa27x.c
@@ -8,8 +8,8 @@
  */
 
 #include <common.h>
-#include <mach/clock.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa/clock.h>
+#include <mach/pxa/pxa-regs.h>
 
 /* Crystal clock: 13MHz */
 #define BASE_CLK	13000000
diff --git a/arch/arm/mach-pxa/speed-pxa3xx.c b/arch/arm/mach-pxa/speed-pxa3xx.c
index b24b7a8fc3..2579966f41 100644
--- a/arch/arm/mach-pxa/speed-pxa3xx.c
+++ b/arch/arm/mach-pxa/speed-pxa3xx.c
@@ -11,8 +11,8 @@
 #include <init.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa/clock.h>
+#include <mach/pxa/pxa-regs.h>
 
 /* Crystal clock: 13MHz */
 #define BASE_CLK	13000000
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index f2fa3c6345..8cdf2c28a9 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 menu "Rockchip Features"
 	depends on ARCH_ROCKCHIP
@@ -5,36 +6,134 @@ menu "Rockchip Features"
 config ARCH_TEXT_BASE
 	hex
 	default 0x68000000 if ARCH_RK3188
-	default 0x0 if ARCH_RK3288
+	default 0x0
 
 config RK_TIMER
 	hex
 	default 1
 
-choice
-	prompt "Select Rockchip SoC"
+config ARCH_ROCKCHIP_V7
+	bool
+	select CPU_V7
+	select ARM_SMP_TWD
+	select ARCH_HAS_L2X0
 
 config ARCH_RK3188
-	bool "Rockchip RK3188 SoCs"
+	bool
+	select ARCH_ROCKCHIP_V7
 
 config ARCH_RK3288
-	bool "Rockchip RK3288 SoCs"
+	bool
+	select ARCH_ROCKCHIP_V7
 	select CLOCKSOURCE_ROCKCHIP
-endchoice
+
+config ARCH_ROCKCHIP_V8
+	bool
+	select CPU_V8
+	select ARM_ATF
+	select RELOCATABLE
+
+config ARCH_RK3399
+	bool
+	select ARCH_ROCKCHIP_V8
+	select ARCH_HAS_RESET_CONTROLLER
+
+config ARCH_RK3399PRO
+	bool
+	select ARCH_RK3399
+
+config ARCH_RK3568
+	bool
+	select ARCH_ROCKCHIP_V8
+	select HW_HAS_PCI
+
+config ARCH_RK3588
+	bool
+	select ARCH_ROCKCHIP_V8
+	select HW_HAS_PCI
 
 comment "select Rockchip boards:"
 
+if 32BIT
+
 config MACH_RADXA_ROCK
-	depends on ARCH_RK3188
+	select ARCH_RK3188
 	select I2C
 	select MFD_ACT8846
 	bool "Radxa rock board"
 
 config MACH_PHYTEC_SOM_RK3288
-	depends on ARCH_RK3288
+	select ARCH_RK3288
 	select I2C
 	bool "RK3288 phyCORE SOM"
 	help
 	  Say Y here if you are using a RK3288 based Phytecs SOM
 
+endif
+
+if 64BIT
+
+config MACH_RK3568_EVB
+	select ARCH_RK3568
+	bool "RK3568 EVB"
+	help
+	  Say Y here if you are using a RK3568 EVB
+
+config MACH_RK3568_BPI_R2PRO
+	select ARCH_RK3568
+	bool "RK3568 BPI R2PRO"
+	help
+	  Say Y here if you are using a RK3568 Bananpi R2 Pro
+
+config MACH_PINE64_QUARTZ64
+	select ARCH_RK3568
+	bool "Pine64 Quartz64"
+	help
+	  Say Y here if you are using a Pine64 Quartz64
+
+config MACH_RADXA_ROCK3
+	select ARCH_RK3568
+	bool "Radxa ROCK3"
+	help
+	  Say Y here if you are using a Radxa ROCK3
+
+config MACH_RADXA_ROCK5
+	select ARCH_RK3588
+	bool "Radxa ROCK5"
+	help
+	  Say Y here if you are using a Radxa ROCK5
+
+config MACH_RADXA_CM3
+	select ARCH_RK3568
+	bool "Radxa CM3"
+	help
+	  Say Y here if you are using a Radxa CM3
+
+endif
+
+comment "select board features:"
+
+config ARCH_ROCKCHIP_ATF
+	bool "Build rockchip ATF binaries into barebox"
+	depends on ARCH_ROCKCHIP_V8
+	default y
+	help
+	  When deselected, barebox proper will run in EL3. This can be
+	  useful for debugging early startup, but for all other cases,
+	  say y here.
+
+config ARCH_RK3399_OPTEE
+	bool "Build rk3399 OP-TEE binary into barebox"
+	depends on ARCH_ROCKCHIP_ATF && ARCH_RK3399
+	help
+	  With this option enabled the RK3399 OP-TEE binary is compiled
+	  into barebox and started along with the BL31 trusted firmware.
+
+config ARCH_RK3568_OPTEE
+	bool "Build rk3568 OP-TEE binary into barebox"
+	depends on ARCH_ROCKCHIP_ATF && ARCH_RK3568
+	help
+	  With this option enabled the RK3568 OP-TEE binary is compiled
+	  into barebox and started along with the BL31 trusted firmware.
+
 endmenu
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 4ca7f17d8c..28ba3ebec8 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,2 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += rockchip.o bootrom.o
+pbl-$(CONFIG_ARCH_ROCKCHIP_ATF) += atf.o
 obj-$(CONFIG_ARCH_RK3188) += rk3188.o
 obj-$(CONFIG_ARCH_RK3288) += rk3288.o
+obj-pbl-$(CONFIG_ARCH_RK3568) += rk3568.o
+obj-pbl-$(CONFIG_ARCH_RK3588) += rk3588.o
+obj-$(CONFIG_ARCH_ROCKCHIP_V8) += bootm.o
+obj-pbl-$(CONFIG_ARCH_ROCKCHIP_V8) += dmc.o
+obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
new file mode 100644
index 0000000000..eaba209ff3
--- /dev/null
+++ b/arch/arm/mach-rockchip/atf.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <common.h>
+#include <firmware.h>
+#include <asm/system.h>
+#include <mach/rockchip/atf.h>
+#include <elf.h>
+#include <asm/atf_common.h>
+#include <asm/barebox-arm.h>
+#include <mach/rockchip/dmc.h>
+#include <mach/rockchip/rockchip.h>
+#include <mach/rockchip/bootrom.h>
+#include <mach/rockchip/rk3568-regs.h>
+#include <mach/rockchip/rk3588-regs.h>
+
+static unsigned long load_elf64_image_phdr(const void *elf)
+{
+	const Elf64_Ehdr *ehdr; /* Elf header structure pointer */
+	const Elf64_Phdr *phdr; /* Program header structure pointer */
+	int i;
+
+	ehdr = elf;
+	phdr = elf + ehdr->e_phoff;
+
+	/* Load each program header */
+	for (i = 0; i < ehdr->e_phnum; ++i) {
+		void *dst = (void *)(ulong)phdr->p_paddr;
+		const void *src = elf + phdr->p_offset;
+
+		pr_debug("Loading phdr %i to 0x%p (%lu bytes)\n",
+			 i, dst, (ulong)phdr->p_filesz);
+		if (phdr->p_filesz)
+			memcpy(dst, src, phdr->p_filesz);
+		if (phdr->p_filesz != phdr->p_memsz)
+			memset(dst + phdr->p_filesz, 0x00,
+				phdr->p_memsz - phdr->p_filesz);
+		++phdr;
+	}
+
+	return ehdr->e_entry;
+}
+
+#define rockchip_atf_load_bl31(SOC, atf_bin, tee_bin, fdt) do {                 \
+	const void *bl31_elf, *optee;                                           \
+	unsigned long bl31;                                                     \
+	size_t bl31_elf_size, optee_size;                                       \
+	uintptr_t optee_load_address = 0;                                       \
+										\
+	get_builtin_firmware(atf_bin, &bl31_elf, &bl31_elf_size);               \
+										\
+	bl31 = load_elf64_image_phdr(bl31_elf);                                 \
+										\
+	if (IS_ENABLED(CONFIG_ARCH_##SOC##_OPTEE)) {                            \
+		optee_load_address = SOC##_OPTEE_LOAD_ADDRESS;                  \
+										\
+		get_builtin_firmware(tee_bin, &optee, &optee_size);             \
+										\
+		memcpy((void *)optee_load_address, optee, optee_size);          \
+	}                                                                       \
+										\
+	/* Setup an initial stack for EL2 */                                    \
+	asm volatile("msr sp_el2, %0" : :                                       \
+			"r" (SOC##_BAREBOX_LOAD_ADDRESS - 16) :                 \
+			"cc");                                                  \
+										\
+	bl31_entry(bl31, optee_load_address,                                    \
+		   SOC##_BAREBOX_LOAD_ADDRESS, (uintptr_t)fdt);                 \
+} while (0)                                                                     \
+
+void rk3399_atf_load_bl31(void *fdt)
+{
+	rockchip_atf_load_bl31(RK3399, rk3399_bl31_bin, rk3399_op_tee_bin, fdt);
+}
+
+void rk3568_atf_load_bl31(void *fdt)
+{
+	rockchip_atf_load_bl31(RK3568, rk3568_bl31_bin, rk3568_op_tee_bin, fdt);
+}
+
+void __noreturn rk3568_barebox_entry(void *fdt)
+{
+	unsigned long membase, memsize;
+
+	membase = RK3568_DRAM_BOTTOM;
+	memsize = rk3568_ram0_size() - RK3568_DRAM_BOTTOM;
+
+	if (current_el() == 3) {
+		rk3568_lowlevel_init();
+		rockchip_store_bootrom_iram(membase, memsize, IOMEM(RK3568_IRAM_BASE));
+
+		/*
+		 * The downstream TF-A doesn't cope with our device tree when
+		 * CONFIG_OF_OVERLAY_LIVE is enabled, supposedly because it is
+		 * too big for some reason. Otherwise it doesn't have any visible
+		 * effect if we pass a device tree or not, except that the TF-A
+		 * fills in the ethernet MAC address into the device tree.
+		 * The upstream TF-A doesn't use the device tree at all.
+		 *
+		 * Pass NULL for now until we have a good reason to pass a real
+		 * device tree.
+		 */
+		rk3568_atf_load_bl31(NULL);
+		/* not reached when CONFIG_ARCH_ROCKCHIP_ATF */
+	}
+
+	barebox_arm_entry(membase, memsize, fdt);
+}
+
+void rk3588_atf_load_bl31(void *fdt)
+{
+	rockchip_atf_load_bl31(RK3588, rk3588_bl31_bin, rk3588_op_tee_bin, fdt);
+}
+
+void __noreturn rk3588_barebox_entry(void *fdt)
+{
+       unsigned long membase, memsize;
+
+       membase = RK3588_DRAM_BOTTOM;
+       memsize = rk3588_ram0_size() - RK3588_DRAM_BOTTOM;
+
+       if (current_el() == 3) {
+               rk3588_lowlevel_init();
+               rockchip_store_bootrom_iram(membase, memsize, IOMEM(RK3588_IRAM_BASE));
+
+               /*
+                * The downstream TF-A doesn't cope with our device tree when
+                * CONFIG_OF_OVERLAY_LIVE is enabled, supposedly because it is
+                * too big for some reason. Otherwise it doesn't have any visible
+                * effect if we pass a device tree or not, except that the TF-A
+                * fills in the ethernet MAC address into the device tree.
+                * The upstream TF-A doesn't use the device tree at all.
+                *
+                * Pass NULL for now until we have a good reason to pass a real
+                * device tree.
+                */
+               rk3588_atf_load_bl31(NULL);
+               /* not reached when CONFIG_ARCH_ROCKCHIP_ATF */
+       }
+
+       barebox_arm_entry(membase, memsize, fdt);
+}
diff --git a/arch/arm/mach-rockchip/bbu.c b/arch/arm/mach-rockchip/bbu.c
new file mode 100644
index 0000000000..3ab6c1e685
--- /dev/null
+++ b/arch/arm/mach-rockchip/bbu.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include <common.h>
+#include <malloc.h>
+#include <bbu.h>
+#include <filetype.h>
+#include <errno.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <linux/sizes.h>
+#include <linux/stat.h>
+#include <ioctl.h>
+#include <environment.h>
+#include <mach/rockchip/bbu.h>
+#include <libfile.h>
+#include <linux/bitfield.h>
+#include <mach/rockchip/rk3568-regs.h>
+#include <mach/rockchip/bootrom.h>
+
+/* The MaskROM looks for images on these locations: */
+#define IMG_OFFSET_0	(0 * SZ_1K + SZ_32K)
+#define IMG_OFFSET_1	(512 * SZ_1K + SZ_32K)
+#define IMG_OFFSET_2	(1024 * SZ_1K + SZ_32K)
+#define IMG_OFFSET_3	(1536 * SZ_1K + SZ_32K)
+#define IMG_OFFSET_4	(2048 * SZ_1K + SZ_32K)
+
+/*
+ * The strategy here is:
+ * The MaskROM iterates over the above five locations until it finds a valid
+ * boot image. The images are protected with sha sums, so any change to an
+ * image on disk is invalidating it. We first check if we have enough space to
+ * write two copies of barebox. To make it simple we only use IMG_OFFSET_0 and
+ * IMG_OFFSET_4 which leaves the maximum size for a single image. When there's
+ * not enough free space on the beginning of the disk we only write a single
+ * image. When we have enough space for two images we first write the inactive one
+ * (leaving the active one intact). Afterwards we write the active one which
+ * leaves the previously written inactive image as a fallback in case writing the
+ * first one gets interrupted.
+ */
+static int rk3568_bbu_mmc_handler(struct bbu_handler *handler,
+				  struct bbu_data *data)
+{
+	enum filetype filetype;
+	int ret, fd, wr0, wr1;
+	loff_t space;
+	const char *cdevname;
+
+	filetype = file_detect_type(data->image, data->len);
+	if (filetype != filetype_rockchip_rkns_image) {
+		if (!bbu_force(data, "incorrect image type. Expected: %s, got %s",
+				file_type_to_string(filetype_rockchip_rkns_image),
+				file_type_to_string(filetype)))
+			return -EINVAL;
+	}
+
+	cdevname = devpath_to_name(data->devicefile);
+
+	device_detect_by_name(cdevname);
+
+	ret = bbu_confirm(data);
+	if (ret)
+		return ret;
+
+	space = cdev_unallocated_space(cdev_by_name(cdevname));
+
+	if (space < IMG_OFFSET_0 + data->len) {
+		pr_err("Unallocated space on %s is too small for one image\n",
+		       data->devicefile);
+		return -ENOSPC;
+	}
+
+	fd = open(data->devicefile, O_WRONLY);
+	if (fd < 0)
+		return fd;
+
+	if (space >= IMG_OFFSET_4 + data->len) {
+		int slot = rockchip_bootsource_get_active_slot();
+
+		pr_info("Unallocated space is enough for two copies, doing failsafe update\n");
+
+		if (slot == 0) {
+			wr0 = IMG_OFFSET_4;
+			wr1 = IMG_OFFSET_0;
+		} else {
+			wr0 = IMG_OFFSET_0;
+			wr1 = IMG_OFFSET_4;
+		}
+	} else {
+		wr0 = IMG_OFFSET_0;
+		wr1 = 0;
+	}
+
+	ret = pwrite_full(fd, data->image, data->len, wr0);
+	if (ret < 0) {
+		pr_err("writing to %s failed with %s\n", data->devicefile,
+			strerror(-ret));
+		goto err_close;
+	}
+
+	if (wr1) {
+		ret = pwrite_full(fd, data->image, data->len, wr1);
+		if (ret < 0) {
+			pr_err("writing to %s failed with %s\n", data->devicefile,
+				strerror(-ret));
+			goto err_close;
+		}
+	}
+
+	ret = 0;
+
+err_close:
+	close(fd);
+
+	return ret;
+}
+
+int rk3568_bbu_mmc_register(const char *name, unsigned long flags,
+                const char *devicefile)
+{
+	struct bbu_handler *handler;
+	int ret;
+
+	handler = xzalloc(sizeof(*handler));
+
+	handler->flags = flags;
+	handler->devicefile = devicefile;
+	handler->name = name;
+	handler->handler = rk3568_bbu_mmc_handler;
+
+	ret = bbu_register_handler(handler);
+	if (ret)
+		free(handler);
+
+	return ret;
+}
diff --git a/arch/arm/mach-rockchip/bootm.c b/arch/arm/mach-rockchip/bootm.c
new file mode 100644
index 0000000000..6f4aa27808
--- /dev/null
+++ b/arch/arm/mach-rockchip/bootm.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#define pr_fmt(fmt) "rockchip-bootm-barebox: " fmt
+
+#include <bootm.h>
+#include <common.h>
+#include <init.h>
+#include <memory.h>
+#include <mach/rockchip/rockchip.h>
+
+struct newidb_entry {
+	uint32_t sector;
+	uint32_t unknown_ffffffff;
+	uint32_t unknown1;
+	uint32_t image_number;
+	unsigned char unknown2[8];
+	unsigned char hash[64];
+};
+
+struct newidb {
+	uint32_t magic;
+	unsigned char unknown1[4];
+	uint32_t n_files;
+	uint32_t hashtype;
+	unsigned char unknown2[8];
+	unsigned char unknown3[8];
+	unsigned char unknown4[88];
+	struct newidb_entry entries[4];
+	unsigned char unknown5[40];
+	unsigned char unknown6[512];
+	unsigned char unknown7[16];
+	unsigned char unknown8[32];
+	unsigned char unknown9[464];
+	unsigned char hash[512];
+};
+
+#define SECTOR_SIZE 512
+
+static int do_bootm_rkns_barebox_image(struct image_data *data)
+{
+	void (*barebox)(unsigned long x0, unsigned long x1, unsigned long x2,
+			unsigned long x3);
+	resource_size_t start, end;
+	struct newidb *idb;
+	int ret, i, n_files;
+	void *buf;
+	resource_size_t image_size;
+
+	ret = memory_bank_first_find_space(&start, &end);
+	if (ret)
+		return ret;
+
+	ret = bootm_load_os(data, start);
+	if (ret)
+		return ret;
+
+	idb = (void *)data->os_res->start;
+	buf = (void *)data->os_res->start;
+
+	image_size = resource_size(data->os_res);
+
+	if (image_size < SECTOR_SIZE)
+		return -EINVAL;
+
+	n_files = idb->n_files >> 16;
+	if (n_files > 4)
+		n_files = 4;
+
+	if (data->verbose)
+		printf("RKNS image contains %d binaries:\n", n_files);
+
+	for (i = 0; i < n_files; i++) {
+		struct newidb_entry *entry = &idb->entries[i];
+		unsigned int entry_size = (entry->sector >> 16) * SECTOR_SIZE;
+		unsigned int entry_start = (entry->sector & 0xffff) * SECTOR_SIZE;
+		enum filetype filetype;
+
+		filetype = file_detect_type(buf + entry_start, SECTOR_SIZE);
+
+		if (entry_start + entry_size > image_size) {
+			printf("image %d expands outside the image\n", i);
+			continue;
+		}
+
+		if (data->verbose)
+			printf("image %d: size: %d offset: %d type: %s\n",
+				i, entry_size, entry_start,
+				file_type_to_string(filetype));
+
+		if (filetype == filetype_arm_barebox) {
+			memmove(buf, buf + entry_start, image_size - entry_start);
+			barebox = buf;
+			goto found;
+		}
+	}
+
+	return -EIO;
+
+found:
+
+	printf("Starting barebox image at 0x%p\n", barebox);
+
+	shutdown_barebox();
+
+	barebox(0, 0, 0, 0);
+
+	return -EINVAL;
+}
+
+static struct image_handler image_handler_rkns_barebox_image = {
+	.name = "Rockchip RKNS barebox image",
+	.bootm = do_bootm_rkns_barebox_image,
+	.filetype = filetype_rockchip_rkns_image,
+};
+
+static int rockchip_register_barebox_image_handler(void)
+{
+	if (rockchip_soc() < 0)
+		return 0;
+
+	return register_image_handler(&image_handler_rkns_barebox_image);
+}
+late_initcall(rockchip_register_barebox_image_handler);
diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
new file mode 100644
index 0000000000..cdd0536cda
--- /dev/null
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <mach/rockchip/bootrom.h>
+#include <io.h>
+#include <bootsource.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <errno.h>
+
+#define BROM_BOOTSOURCE_ID	0x10
+#define BROM_BOOTSOURCE_SLOT	0x14
+#define	BROM_BOOTSOURCE_SLOT_ACTIVE	GENMASK(12, 10)
+
+static const void __iomem *rk_iram;
+
+int rockchip_bootsource_get_active_slot(void)
+{
+	if (!rk_iram)
+		return -EINVAL;
+
+	return FIELD_GET(BROM_BOOTSOURCE_SLOT_ACTIVE,
+			 readl(IOMEM(rk_iram) + BROM_BOOTSOURCE_SLOT));
+}
+
+struct rk_bootsource {
+	enum bootsource src;
+	int instance;
+};
+
+static struct rk_bootsource bootdev_map[] = {
+	[0x1] = { .src = BOOTSOURCE_NAND, .instance = 0 },
+	[0x2] = { .src = BOOTSOURCE_MMC, .instance = 0 },
+	[0x3] = { .src = BOOTSOURCE_SPI_NOR, .instance = 0 },
+	[0x4] = { .src = BOOTSOURCE_SPI_NAND, .instance = 0 },
+	[0x5] = { .src = BOOTSOURCE_MMC, .instance = 1 },
+	[0xa] = { .src = BOOTSOURCE_USB, .instance = 0 },
+};
+
+void rockchip_parse_bootrom_iram(const void *iram)
+{
+	u32 v;
+
+	rk_iram = iram;
+
+	v = readl(iram + BROM_BOOTSOURCE_ID);
+
+	if (v >= ARRAY_SIZE(bootdev_map))
+		return;
+
+	bootsource_set(bootdev_map[v].src, bootdev_map[v].instance);
+}
diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
new file mode 100644
index 0000000000..6bc9d9aabc
--- /dev/null
+++ b/arch/arm/mach-rockchip/dmc.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#define pr_fmt(fmt) "rockchip-dmc: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <asm/barebox-arm.h>
+#include <asm/memory.h>
+#include <pbl.h>
+#include <io.h>
+#include <linux/regmap.h>
+#include <mfd/syscon.h>
+#include <mach/rockchip/dmc.h>
+#include <mach/rockchip/rk3399-regs.h>
+#include <mach/rockchip/rk3568-regs.h>
+
+#define RK3399_PMUGRF_OS_REG2		0x308
+#define RK3399_PMUGRF_OS_REG3		0x30C
+
+#define RK3568_PMUGRF_OS_REG2           0x208
+#define RK3568_PMUGRF_OS_REG3           0x20c
+
+#define RK3399_INT_REG_START		0xf0000000
+#define RK3568_INT_REG_START		RK3399_INT_REG_START
+#define RK3588_INT_REG_START		RK3399_INT_REG_START
+
+struct rockchip_dmc_drvdata {
+	unsigned int os_reg2;
+	unsigned int os_reg3;
+	unsigned int os_reg4;
+	unsigned int os_reg5;
+	resource_size_t internal_registers_start;
+};
+
+static resource_size_t rockchip_sdram_size(u32 sys_reg2, u32 sys_reg3)
+{
+	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
+	resource_size_t chipsize_mb, size_mb = 0;
+	u32 ch;
+	u32 cs1_col;
+	u32 bg = 0;
+	u32 dbw, dram_type;
+	u32 ch_num = 1 + FIELD_GET(SYS_REG_NUM_CH, sys_reg2);
+	u32 version = FIELD_GET(SYS_REG_VERSION, sys_reg3);
+
+	pr_debug("%s(reg2=%x, reg3=%x)\n", __func__, sys_reg2, sys_reg3);
+
+	dram_type = FIELD_GET(SYS_REG_DDRTYPE, sys_reg2);
+
+	if (version >= 3)
+		dram_type |= FIELD_GET(SYS_REG_EXTEND_DDRTYPE, sys_reg3) << 3;
+
+	for (ch = 0; ch < ch_num; ch++) {
+		rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK);
+		cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
+		cs1_col = cs0_col;
+
+		bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+
+		cs0_row = sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK;
+		cs1_row = sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK;
+
+		if (version >= 2) {
+			cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
+				  SYS_REG_CS1_COL_MASK);
+
+			cs0_row |= (sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
+					SYS_REG_EXTEND_CS0_ROW_MASK) << 2;
+
+			if (cs0_row == 7)
+				cs0_row = 12;
+			else
+				cs0_row += 13;
+
+			cs1_row |= (sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
+					SYS_REG_EXTEND_CS1_ROW_MASK) << 2;
+
+			if (cs1_row == 7)
+				cs1_row = 12;
+			else
+				cs1_row += 13;
+		} else {
+			cs0_row += 13;
+			cs1_row += 13;
+		}
+
+		bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & SYS_REG_BW_MASK));
+		row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK;
+
+		if (dram_type == DDR4) {
+			dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & SYS_REG_DBW_MASK;
+			bg = (dbw == 2) ? 2 : 1;
+		}
+
+		chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
+
+		if (rank > 1)
+			chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
+				       (cs0_col - cs1_col));
+		if (row_3_4)
+			chipsize_mb = chipsize_mb * 3 / 4;
+
+		size_mb += chipsize_mb;
+
+		if (rank > 1)
+			pr_debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d "
+				 "cs1_row %d bw %d row_3_4 %d\n",
+				 rank, cs0_col, cs1_col, bk, cs0_row,
+				 cs1_row, bw, row_3_4);
+		else
+			pr_debug("rank %d cs0_col %d bk %d cs0_row %d "
+				 "bw %d row_3_4 %d\n",
+				 rank, cs0_col, bk, cs0_row,
+				 bw, row_3_4);
+	}
+
+	return (resource_size_t)size_mb << 20;
+}
+
+resource_size_t rk3399_ram0_size(void)
+{
+	void __iomem *pmugrf = IOMEM(RK3399_PMUGRF_BASE);
+	u32 sys_reg2, sys_reg3;
+	resource_size_t size;
+
+	sys_reg2 = readl(pmugrf + RK3399_PMUGRF_OS_REG2);
+	sys_reg3 = readl(pmugrf + RK3399_PMUGRF_OS_REG3);
+
+	size = rockchip_sdram_size(sys_reg2, sys_reg3);
+	size = min_t(resource_size_t, RK3399_INT_REG_START, size);
+
+	pr_debug("%s() = %llu\n", __func__, (u64)size);
+
+	return size;
+}
+
+resource_size_t rk3568_ram0_size(void)
+{
+	void __iomem *pmugrf = IOMEM(RK3568_PMUGRF_BASE);
+	u32 sys_reg2, sys_reg3;
+	resource_size_t size;
+
+	sys_reg2 = readl(pmugrf + RK3568_PMUGRF_OS_REG2);
+	sys_reg3 = readl(pmugrf + RK3568_PMUGRF_OS_REG3);
+
+	size = rockchip_sdram_size(sys_reg2, sys_reg3);
+	size = min_t(resource_size_t, RK3568_INT_REG_START, size);
+
+	pr_debug("%s() = %llu\n", __func__, (u64)size);
+
+	return size;
+}
+
+#define RK3588_PMUGRF_BASE 0xfd58a000
+#define RK3588_PMUGRF_OS_REG2           0x208
+#define RK3588_PMUGRF_OS_REG3           0x20c
+#define RK3588_PMUGRF_OS_REG4           0x210
+#define RK3588_PMUGRF_OS_REG5           0x214
+
+resource_size_t rk3588_ram0_size(void)
+{
+	void __iomem *pmugrf = IOMEM(RK3588_PMUGRF_BASE);
+	u32 sys_reg2, sys_reg3, sys_reg4, sys_reg5;
+	resource_size_t size, size1, size2;
+
+	sys_reg2 = readl(pmugrf + RK3588_PMUGRF_OS_REG2);
+	sys_reg3 = readl(pmugrf + RK3588_PMUGRF_OS_REG3);
+	sys_reg4 = readl(pmugrf + RK3588_PMUGRF_OS_REG4);
+	sys_reg5 = readl(pmugrf + RK3588_PMUGRF_OS_REG5);
+
+	size1 = rockchip_sdram_size(sys_reg2, sys_reg3);
+	size2 = rockchip_sdram_size(sys_reg4, sys_reg5);
+
+	pr_info("%s() size1 = 0x%08llx, size2 = 0x%08llx\n", __func__, (u64)size1, (u64)size2);
+
+	size = min_t(resource_size_t, RK3568_INT_REG_START, size1 + size2);
+
+	return size;
+}
+
+static int rockchip_dmc_probe(struct device *dev)
+{
+	const struct rockchip_dmc_drvdata *drvdata;
+	resource_size_t membase, memsize;
+	struct regmap *regmap;
+	u32 sys_rega, sys_regb;
+
+	regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	drvdata = device_get_match_data(dev);
+	if (!drvdata)
+		return -ENOENT;
+
+	regmap_read(regmap, drvdata->os_reg2, &sys_rega);
+	regmap_read(regmap, drvdata->os_reg3, &sys_regb);
+	memsize = rockchip_sdram_size(sys_rega, sys_regb);
+
+	if (drvdata->os_reg4) {
+		regmap_read(regmap, drvdata->os_reg4, &sys_rega);
+		regmap_read(regmap, drvdata->os_reg5, &sys_regb);
+		memsize += rockchip_sdram_size(sys_rega, sys_regb);
+	}
+
+	dev_info(dev, "Detected memory size: %pa\n", &memsize);
+
+	/* lowest 10M are shaved off for secure world firmware */
+	membase = 0xa00000;
+
+	/* ram0, from 0xa00000 up to SoC internal register space start */
+	arm_add_mem_device("ram0", membase,
+		min_t(resource_size_t, drvdata->internal_registers_start, memsize) - membase);
+
+	/* ram1, remaining RAM beyond 32bit space */
+	if (memsize > SZ_4G)
+		arm_add_mem_device("ram1", SZ_4G, memsize - SZ_4G);
+
+	return 0;
+}
+
+static const struct rockchip_dmc_drvdata rk3399_drvdata = {
+	.os_reg2 = RK3399_PMUGRF_OS_REG2,
+	.os_reg3 = RK3399_PMUGRF_OS_REG3,
+	.internal_registers_start = RK3399_INT_REG_START,
+};
+
+static const struct rockchip_dmc_drvdata rk3568_drvdata = {
+	.os_reg2 = RK3568_PMUGRF_OS_REG2,
+	.os_reg3 = RK3568_PMUGRF_OS_REG3,
+	.internal_registers_start = RK3568_INT_REG_START,
+};
+
+static const struct rockchip_dmc_drvdata rk3588_drvdata = {
+	.os_reg2 = RK3588_PMUGRF_OS_REG2,
+	.os_reg3 = RK3588_PMUGRF_OS_REG3,
+	.os_reg4 = RK3588_PMUGRF_OS_REG4,
+	.os_reg5 = RK3588_PMUGRF_OS_REG5,
+	.internal_registers_start = RK3588_INT_REG_START,
+};
+
+static struct of_device_id rockchip_dmc_dt_ids[] = {
+	{
+		.compatible = "rockchip,rk3399-dmc",
+		.data = &rk3399_drvdata,
+	},
+	{
+		.compatible = "rockchip,rk3568-dmc",
+		.data = &rk3568_drvdata,
+	},
+	{
+		.compatible = "rockchip,rk3588-dmc",
+		.data = &rk3588_drvdata,
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rockchip_dmc_dt_ids);
+
+static struct driver rockchip_dmc_driver = {
+	.name   = "rockchip-dmc",
+	.probe  = rockchip_dmc_probe,
+	.of_compatible = rockchip_dmc_dt_ids,
+};
+mem_platform_driver(rockchip_dmc_driver);
diff --git a/arch/arm/mach-rockchip/include/mach/cru_rk3288.h b/arch/arm/mach-rockchip/include/mach/cru_rk3288.h
deleted file mode 100644
index c898514c6b..0000000000
--- a/arch/arm/mach-rockchip/include/mach/cru_rk3288.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * (C) Copyright 2008-2014 Rockchip Electronics
- * Peter, Software Engineering, <superpeter.cai@gmail.com>.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#ifndef _ASM_ARCH_CRU_RK3288_H
-#define _ASM_ARCH_CRU_RK3288_H
-
-#define OSC_HZ		(24 * 1000 * 1000)
-
-#define APLL_HZ		(1800 * 1000000)
-#define GPLL_HZ		(594 * 1000000)
-#define CPLL_HZ		(384 * 1000000)
-#define NPLL_HZ		(384 * 1000000)
-
-/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
-#define PD_BUS_ACLK_HZ	297000000
-#define PD_BUS_HCLK_HZ	148500000
-#define PD_BUS_PCLK_HZ	74250000
-
-#define PERI_ACLK_HZ	148500000
-#define PERI_HCLK_HZ	148500000
-#define PERI_PCLK_HZ	74250000
-
-struct rk3288_cru {
-	struct rk3288_pll {
-		u32 con0;
-		u32 con1;
-		u32 con2;
-		u32 con3;
-	} pll[5];
-	u32 cru_mode_con;
-	u32 reserved0[3];
-	u32 cru_clksel_con[43];
-	u32 reserved1[21];
-	u32 cru_clkgate_con[19];
-	u32 reserved2;
-	u32 cru_glb_srst_fst_value;
-	u32 cru_glb_srst_snd_value;
-	u32 cru_softrst_con[12];
-	u32 cru_misc_con;
-	u32 cru_glb_cnt_th;
-	u32 cru_glb_rst_con;
-	u32 reserved3;
-	u32 cru_glb_rst_st;
-	u32 reserved4;
-	u32 cru_sdmmc_con[2];
-	u32 cru_sdio0_con[2];
-	u32 cru_sdio1_con[2];
-	u32 cru_emmc_con[2];
-};
-
-/* CRU_CLKSEL11_CON */
-enum {
-	HSICPHY_DIV_SHIFT	= 8,
-	HSICPHY_DIV_MASK	= 0x3f,
-
-	MMC0_PLL_SHIFT		= 6,
-	MMC0_PLL_MASK		= 3,
-	MMC0_PLL_SELECT_CODEC	= 0,
-	MMC0_PLL_SELECT_GENERAL,
-	MMC0_PLL_SELECT_24MHZ,
-
-	MMC0_DIV_SHIFT		= 0,
-	MMC0_DIV_MASK		= 0x3f,
-};
-
-/* CRU_CLKSEL12_CON */
-enum {
-	EMMC_PLL_SHIFT		= 0xe,
-	EMMC_PLL_MASK		= 3,
-	EMMC_PLL_SELECT_CODEC	= 0,
-	EMMC_PLL_SELECT_GENERAL,
-	EMMC_PLL_SELECT_24MHZ,
-
-	EMMC_DIV_SHIFT		= 8,
-	EMMC_DIV_MASK		= 0x3f,
-
-	SDIO0_PLL_SHIFT		= 6,
-	SDIO0_PLL_MASK		= 3,
-	SDIO0_PLL_SELECT_CODEC	= 0,
-	SDIO0_PLL_SELECT_GENERAL,
-	SDIO0_PLL_SELECT_24MHZ,
-
-	SDIO0_DIV_SHIFT		= 0,
-	SDIO0_DIV_MASK		= 0x3f,
-};
-
-/* CRU_CLKSEL25_CON */
-enum {
-	SPI1_PLL_SHIFT		= 0xf,
-	SPI1_PLL_MASK		= 1,
-	SPI1_PLL_SELECT_CODEC	= 0,
-	SPI1_PLL_SELECT_GENERAL,
-
-	SPI1_DIV_SHIFT		= 8,
-	SPI1_DIV_MASK		= 0x7f,
-
-	SPI0_PLL_SHIFT		= 7,
-	SPI0_PLL_MASK		= 1,
-	SPI0_PLL_SELECT_CODEC	= 0,
-	SPI0_PLL_SELECT_GENERAL,
-
-	SPI0_DIV_SHIFT		= 0,
-	SPI0_DIV_MASK		= 0x7f,
-};
-
-/* CRU_CLKSEL39_CON */
-enum {
-	ACLK_HEVC_PLL_SHIFT	= 0xe,
-	ACLK_HEVC_PLL_MASK	= 3,
-	ACLK_HEVC_PLL_SELECT_CODEC = 0,
-	ACLK_HEVC_PLL_SELECT_GENERAL,
-	ACLK_HEVC_PLL_SELECT_NEW,
-
-	ACLK_HEVC_DIV_SHIFT	= 8,
-	ACLK_HEVC_DIV_MASK	= 0x1f,
-
-	SPI2_PLL_SHIFT		= 7,
-	SPI2_PLL_MASK		= 1,
-	SPI2_PLL_SELECT_CODEC	= 0,
-	SPI2_PLL_SELECT_GENERAL,
-
-	SPI2_DIV_SHIFT		= 0,
-	SPI2_DIV_MASK		= 0x7f,
-};
-
-/* CRU_MODE_CON */
-enum {
-	NPLL_WORK_SHIFT		= 0xe,
-	NPLL_WORK_MASK		= 3,
-	NPLL_WORK_SLOW		= 0,
-	NPLL_WORK_NORMAL,
-	NPLL_WORK_DEEP,
-
-	GPLL_WORK_SHIFT		= 0xc,
-	GPLL_WORK_MASK		= 3,
-	GPLL_WORK_SLOW		= 0,
-	GPLL_WORK_NORMAL,
-	GPLL_WORK_DEEP,
-
-	CPLL_WORK_SHIFT		= 8,
-	CPLL_WORK_MASK		= 3,
-	CPLL_WORK_SLOW		= 0,
-	CPLL_WORK_NORMAL,
-	CPLL_WORK_DEEP,
-
-	DPLL_WORK_SHIFT		= 4,
-	DPLL_WORK_MASK		= 3,
-	DPLL_WORK_SLOW		= 0,
-	DPLL_WORK_NORMAL,
-	DPLL_WORK_DEEP,
-
-	APLL_WORK_SHIFT		= 0,
-	APLL_WORK_MASK		= 3,
-	APLL_WORK_SLOW		= 0,
-	APLL_WORK_NORMAL,
-	APLL_WORK_DEEP,
-};
-
-/* CRU_APLL_CON0 */
-enum {
-	CLKR_SHIFT		= 8,
-	CLKR_MASK		= 0x3f,
-
-	CLKOD_SHIFT		= 0,
-	CLKOD_MASK		= 0xf,
-};
-
-/* CRU_APLL_CON1 */
-enum {
-	LOCK_SHIFT		= 0x1f,
-	LOCK_MASK		= 1,
-	LOCK_UNLOCK		= 0,
-	LOCK_LOCK,
-
-	CLKF_SHIFT		= 0,
-	CLKF_MASK		= 0x1fff,
-};
-
-#endif
diff --git a/arch/arm/mach-rockchip/include/mach/debug_ll.h b/arch/arm/mach-rockchip/include/mach/debug_ll.h
deleted file mode 100644
index 9fde2976f1..0000000000
--- a/arch/arm/mach-rockchip/include/mach/debug_ll.h
+++ /dev/null
@@ -1,73 +0,0 @@
-#ifndef __MACH_DEBUG_LL_H__
-#define __MACH_DEBUG_LL_H__
-
-#include <common.h>
-#include <io.h>
-#include <mach/rk3188-regs.h>
-#include <mach/rk3288-regs.h>
-
-#ifdef CONFIG_ARCH_RK3188
-
-#define UART_CLOCK		100000000
-#define RK_DEBUG_SOC		RK3188
-#define serial_out(a, v)	writeb(v, a)
-#define serial_in(a)		readb(a)
-
-#elif defined CONFIG_ARCH_RK3288
-
-#define UART_CLOCK		24000000
-#define RK_DEBUG_SOC		RK3288
-#define serial_out(a, v)	writel(v, a)
-#define serial_in(a)		readl(a)
-
-#endif
-
-#define __RK_UART_BASE(soc, num) soc##_UART##num##_BASE
-#define RK_UART_BASE(soc, num) __RK_UART_BASE(soc, num)
-
-#define LSR_THRE	0x20	/* Xmit holding register empty */
-#define LCR_BKSE	0x80	/* Bank select enable */
-#define LSR		(5 << 2)
-#define THR		(0 << 2)
-#define DLL		(0 << 2)
-#define IER		(1 << 2)
-#define DLM		(1 << 2)
-#define FCR		(2 << 2)
-#define LCR		(3 << 2)
-#define MCR		(4 << 2)
-#define MDR		(8 << 2)
-
-static inline void INIT_LL(void)
-{
-	void __iomem *base = IOMEM(RK_UART_BASE(RK_DEBUG_SOC,
-		CONFIG_DEBUG_ROCKCHIP_UART_PORT));
-	unsigned int divisor = DIV_ROUND_CLOSEST(UART_CLOCK,
-		16 * CONFIG_BAUDRATE);
-
-	serial_out(base + LCR, 0x00);
-	serial_out(base + IER, 0x00);
-	serial_out(base + MDR, 0x07);
-	serial_out(base + LCR, LCR_BKSE);
-	serial_out(base + DLL, divisor & 0xff);
-	serial_out(base + DLM, divisor >> 8);
-	serial_out(base + LCR, 0x03);
-	serial_out(base + MCR, 0x03);
-	serial_out(base + FCR, 0x07);
-	serial_out(base + MDR, 0x00);
-}
-
-static inline void PUTC_LL(char c)
-{
-	void __iomem *base = IOMEM(RK_UART_BASE(RK_DEBUG_SOC,
-		CONFIG_DEBUG_ROCKCHIP_UART_PORT));
-
-	/* Wait until there is space in the FIFO */
-	while ((serial_in(base + LSR) & LSR_THRE) == 0)
-		;
-	/* Send the character */
-	serial_out(base + THR, c);
-	/* Wait to make sure it hits the line, in case we die too soon. */
-	while ((serial_in(base + LSR) & LSR_THRE) == 0)
-		;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/include/mach/grf_rk3288.h b/arch/arm/mach-rockchip/include/mach/grf_rk3288.h
deleted file mode 100644
index 0117a179c9..0000000000
--- a/arch/arm/mach-rockchip/include/mach/grf_rk3288.h
+++ /dev/null
@@ -1,768 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- * Copyright 2014 Rockchip Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef _ASM_ARCH_GRF_RK3288_H
-#define _ASM_ARCH_GRF_RK3288_H
-
-struct rk3288_grf_gpio_lh {
-	u32 l;
-	u32 h;
-};
-
-struct rk3288_grf {
-	u32 reserved[3];
-	u32 gpio1d_iomux;
-	u32 gpio2a_iomux;
-	u32 gpio2b_iomux;
-
-	u32 gpio2c_iomux;
-	u32 reserved2;
-	u32 gpio3a_iomux;
-	u32 gpio3b_iomux;
-
-	u32 gpio3c_iomux;
-	u32 gpio3dl_iomux;
-	u32 gpio3dh_iomux;
-	u32 gpio4al_iomux;
-
-	u32 gpio4ah_iomux;
-	u32 gpio4bl_iomux;
-	u32 reserved3;
-	u32 gpio4c_iomux;
-
-	u32 gpio4d_iomux;
-	u32 reserved4;
-	u32 gpio5b_iomux;
-	u32 gpio5c_iomux;
-
-	u32 reserved5;
-	u32 gpio6a_iomux;
-	u32 gpio6b_iomux;
-	u32 gpio6c_iomux;
-	u32 reserved6;
-	u32 gpio7a_iomux;
-	u32 gpio7b_iomux;
-	u32 gpio7cl_iomux;
-	u32 gpio7ch_iomux;
-	u32 reserved7;
-	u32 gpio8a_iomux;
-	u32 gpio8b_iomux;
-	u32 reserved8[30];
-	struct rk3288_grf_gpio_lh gpio_sr[8];
-	u32 gpio1_p[8][4];
-	u32 gpio1_e[8][4];
-	u32 gpio_smt;
-	u32 soc_con0;
-	u32 soc_con1;
-	u32 soc_con2;
-	u32 soc_con3;
-	u32 soc_con4;
-	u32 soc_con5;
-	u32 soc_con6;
-	u32 soc_con7;
-	u32 soc_con8;
-	u32 soc_con9;
-	u32 soc_con10;
-	u32 soc_con11;
-	u32 soc_con12;
-	u32 soc_con13;
-	u32 soc_con14;
-	u32 soc_status[22];
-	u32 reserved9[2];
-	u32 peridmac_con[4];
-	u32 ddrc0_con0;
-	u32 ddrc1_con0;
-	u32 cpu_con[5];
-	u32 reserved10[3];
-	u32 cpu_status0;
-	u32 reserved11;
-	u32 uoc0_con[5];
-	u32 uoc1_con[5];
-	u32 uoc2_con[4];
-	u32 uoc3_con[2];
-	u32 uoc4_con[2];
-	u32 pvtm_con[3];
-	u32 pvtm_status[3];
-	u32 io_vsel;
-	u32 saradc_testbit;
-	u32 tsadc_testbit_l;
-	u32 tsadc_testbit_h;
-	u32 os_reg[4];
-	u32 reserved12;
-	u32 soc_con15;
-	u32 soc_con16;
-};
-
-struct rk3288_sgrf {
-	u32 soc_con0;
-	u32 soc_con1;
-	u32 soc_con2;
-	u32 soc_con3;
-	u32 soc_con4;
-	u32 soc_con5;
-	u32 reserved1[(0x20-0x18)/4];
-	u32 busdmac_con[2];
-	u32 reserved2[(0x40-0x28)/4];
-	u32 cpu_con[3];
-	u32 reserved3[(0x50-0x4c)/4];
-	u32 soc_con6;
-	u32 soc_con7;
-	u32 soc_con8;
-	u32 soc_con9;
-	u32 soc_con10;
-	u32 soc_con11;
-	u32 soc_con12;
-	u32 soc_con13;
-	u32 soc_con14;
-	u32 soc_con15;
-	u32 soc_con16;
-	u32 soc_con17;
-	u32 soc_con18;
-	u32 soc_con19;
-	u32 soc_con20;
-	u32 soc_con21;
-	u32 reserved4[(0x100-0x90)/4];
-	u32 soc_status[2];
-	u32 reserved5[(0x120-0x108)/4];
-	u32 fast_boot_addr;
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
-	GPIO1D3_SHIFT		= 6,
-	GPIO1D3_MASK		= 1,
-	GPIO1D3_GPIO		= 0,
-	GPIO1D3_LCDC0_DCLK,
-
-	GPIO1D2_SHIFT		= 4,
-	GPIO1D2_MASK		= 1,
-	GPIO1D2_GPIO		= 0,
-	GPIO1D2_LCDC0_DEN,
-
-	GPIO1D1_SHIFT		= 2,
-	GPIO1D1_MASK		= 1,
-	GPIO1D1_GPIO		= 0,
-	GPIO1D1_LCDC0_VSYNC,
-
-	GPIO1D0_SHIFT		= 0,
-	GPIO1D0_MASK		= 1,
-	GPIO1D0_GPIO		= 0,
-	GPIO1D0_LCDC0_HSYNC,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
-	GPIO2C1_SHIFT		= 2,
-	GPIO2C1_MASK		= 1,
-	GPIO2C1_GPIO		= 0,
-	GPIO2C1_I2C3CAM_SDA,
-
-	GPIO2C0_SHIFT		= 0,
-	GPIO2C0_MASK		= 1,
-	GPIO2C0_GPIO		= 0,
-	GPIO2C0_I2C3CAM_SCL,
-};
-
-/* GRF_GPIO3A_IOMUX */
-enum {
-	GPIO3A7_SHIFT		= 14,
-	GPIO3A7_MASK		= 3,
-	GPIO3A7_GPIO		= 0,
-	GPIO3A7_FLASH0_DATA7,
-	GPIO3A7_EMMC_DATA7,
-
-	GPIO3A6_SHIFT		= 12,
-	GPIO3A6_MASK		= 3,
-	GPIO3A6_GPIO		= 0,
-	GPIO3A6_FLASH0_DATA6,
-	GPIO3A6_EMMC_DATA6,
-
-	GPIO3A5_SHIFT		= 10,
-	GPIO3A5_MASK		= 3,
-	GPIO3A5_GPIO		= 0,
-	GPIO3A5_FLASH0_DATA5,
-	GPIO3A5_EMMC_DATA5,
-
-	GPIO3A4_SHIFT		= 8,
-	GPIO3A4_MASK		= 3,
-	GPIO3A4_GPIO		= 0,
-	GPIO3A4_FLASH0_DATA4,
-	GPIO3A4_EMMC_DATA4,
-
-	GPIO3A3_SHIFT		= 6,
-	GPIO3A3_MASK		= 3,
-	GPIO3A3_GPIO		= 0,
-	GPIO3A3_FLASH0_DATA3,
-	GPIO3A3_EMMC_DATA3,
-
-	GPIO3A2_SHIFT		= 4,
-	GPIO3A2_MASK		= 3,
-	GPIO3A2_GPIO		= 0,
-	GPIO3A2_FLASH0_DATA2,
-	GPIO3A2_EMMC_DATA2,
-
-	GPIO3A1_SHIFT		= 2,
-	GPIO3A1_MASK		= 3,
-	GPIO3A1_GPIO		= 0,
-	GPIO3A1_FLASH0_DATA1,
-	GPIO3A1_EMMC_DATA1,
-
-	GPIO3A0_SHIFT		= 0,
-	GPIO3A0_MASK		= 3,
-	GPIO3A0_GPIO		= 0,
-	GPIO3A0_FLASH0_DATA0,
-	GPIO3A0_EMMC_DATA0,
-};
-
-/* GRF_GPIO3B_IOMUX */
-enum {
-	GPIO3B7_SHIFT		= 14,
-	GPIO3B7_MASK		= 1,
-	GPIO3B7_GPIO		= 0,
-	GPIO3B7_FLASH0_CSN1,
-
-	GPIO3B6_SHIFT		= 12,
-	GPIO3B6_MASK		= 1,
-	GPIO3B6_GPIO		= 0,
-	GPIO3B6_FLASH0_CSN0,
-
-	GPIO3B5_SHIFT		= 10,
-	GPIO3B5_MASK		= 1,
-	GPIO3B5_GPIO		= 0,
-	GPIO3B5_FLASH0_WRN,
-
-	GPIO3B4_SHIFT		= 8,
-	GPIO3B4_MASK		= 1,
-	GPIO3B4_GPIO		= 0,
-	GPIO3B4_FLASH0_CLE,
-
-	GPIO3B3_SHIFT		= 6,
-	GPIO3B3_MASK		= 1,
-	GPIO3B3_GPIO		= 0,
-	GPIO3B3_FLASH0_ALE,
-
-	GPIO3B2_SHIFT		= 4,
-	GPIO3B2_MASK		= 1,
-	GPIO3B2_GPIO		= 0,
-	GPIO3B2_FLASH0_RDN,
-
-	GPIO3B1_SHIFT		= 2,
-	GPIO3B1_MASK		= 3,
-	GPIO3B1_GPIO		= 0,
-	GPIO3B1_FLASH0_WP,
-	GPIO3B1_EMMC_PWREN,
-
-	GPIO3B0_SHIFT		= 0,
-	GPIO3B0_MASK		= 1,
-	GPIO3B0_GPIO		= 0,
-	GPIO3B0_FLASH0_RDY,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
-	GPIO3C2_SHIFT		= 4,
-	GPIO3C2_MASK		= 3,
-	GPIO3C2_GPIO		= 0,
-	GPIO3C2_FLASH0_DQS,
-	GPIO3C2_EMMC_CLKOUT,
-
-	GPIO3C1_SHIFT		= 2,
-	GPIO3C1_MASK		= 3,
-	GPIO3C1_GPIO		= 0,
-	GPIO3C1_FLASH0_CSN3,
-	GPIO3C1_EMMC_RSTNOUT,
-
-	GPIO3C0_SHIFT		= 0,
-	GPIO3C0_MASK		= 3,
-	GPIO3C0_GPIO		= 0,
-	GPIO3C0_FLASH0_CSN2,
-	GPIO3C0_EMMC_CMD,
-};
-
-/* GRF_GPIO4C_IOMUX */
-enum {
-	GPIO4C7_SHIFT		= 14,
-	GPIO4C7_MASK		= 1,
-	GPIO4C7_GPIO		= 0,
-	GPIO4C7_SDIO0_DATA3,
-
-	GPIO4C6_SHIFT		= 12,
-	GPIO4C6_MASK		= 1,
-	GPIO4C6_GPIO		= 0,
-	GPIO4C6_SDIO0_DATA2,
-
-	GPIO4C5_SHIFT		= 10,
-	GPIO4C5_MASK		= 1,
-	GPIO4C5_GPIO		= 0,
-	GPIO4C5_SDIO0_DATA1,
-
-	GPIO4C4_SHIFT		= 8,
-	GPIO4C4_MASK		= 1,
-	GPIO4C4_GPIO		= 0,
-	GPIO4C4_SDIO0_DATA0,
-
-	GPIO4C3_SHIFT		= 6,
-	GPIO4C3_MASK		= 1,
-	GPIO4C3_GPIO		= 0,
-	GPIO4C3_UART0BT_RTSN,
-
-	GPIO4C2_SHIFT		= 4,
-	GPIO4C2_MASK		= 1,
-	GPIO4C2_GPIO		= 0,
-	GPIO4C2_UART0BT_CTSN,
-
-	GPIO4C1_SHIFT		= 2,
-	GPIO4C1_MASK		= 1,
-	GPIO4C1_GPIO		= 0,
-	GPIO4C1_UART0BT_SOUT,
-
-	GPIO4C0_SHIFT		= 0,
-	GPIO4C0_MASK		= 1,
-	GPIO4C0_GPIO		= 0,
-	GPIO4C0_UART0BT_SIN,
-};
-
-/* GRF_GPIO5B_IOMUX */
-enum {
-	GPIO5B7_SHIFT		= 14,
-	GPIO5B7_MASK		= 3,
-	GPIO5B7_GPIO		= 0,
-	GPIO5B7_SPI0_RXD,
-	GPIO5B7_TS0_DATA7,
-	GPIO5B7_UART4EXP_SIN,
-
-	GPIO5B6_SHIFT		= 12,
-	GPIO5B6_MASK		= 3,
-	GPIO5B6_GPIO		= 0,
-	GPIO5B6_SPI0_TXD,
-	GPIO5B6_TS0_DATA6,
-	GPIO5B6_UART4EXP_SOUT,
-
-	GPIO5B5_SHIFT		= 10,
-	GPIO5B5_MASK		= 3,
-	GPIO5B5_GPIO		= 0,
-	GPIO5B5_SPI0_CSN0,
-	GPIO5B5_TS0_DATA5,
-	GPIO5B5_UART4EXP_RTSN,
-
-	GPIO5B4_SHIFT		= 8,
-	GPIO5B4_MASK		= 3,
-	GPIO5B4_GPIO		= 0,
-	GPIO5B4_SPI0_CLK,
-	GPIO5B4_TS0_DATA4,
-	GPIO5B4_UART4EXP_CTSN,
-
-	GPIO5B3_SHIFT		= 6,
-	GPIO5B3_MASK		= 3,
-	GPIO5B3_GPIO		= 0,
-	GPIO5B3_UART1BB_RTSN,
-	GPIO5B3_TS0_DATA3,
-
-	GPIO5B2_SHIFT		= 4,
-	GPIO5B2_MASK		= 3,
-	GPIO5B2_GPIO		= 0,
-	GPIO5B2_UART1BB_CTSN,
-	GPIO5B2_TS0_DATA2,
-
-	GPIO5B1_SHIFT		= 2,
-	GPIO5B1_MASK		= 3,
-	GPIO5B1_GPIO		= 0,
-	GPIO5B1_UART1BB_SOUT,
-	GPIO5B1_TS0_DATA1,
-
-	GPIO5B0_SHIFT		= 0,
-	GPIO5B0_MASK		= 3,
-	GPIO5B0_GPIO		= 0,
-	GPIO5B0_UART1BB_SIN,
-	GPIO5B0_TS0_DATA0,
-};
-
-/* GRF_GPIO5C_IOMUX */
-enum {
-	GPIO5C3_SHIFT		= 6,
-	GPIO5C3_MASK		= 1,
-	GPIO5C3_GPIO		= 0,
-	GPIO5C3_TS0_ERR,
-
-	GPIO5C2_SHIFT		= 4,
-	GPIO5C2_MASK		= 1,
-	GPIO5C2_GPIO		= 0,
-	GPIO5C2_TS0_CLK,
-
-	GPIO5C1_SHIFT		= 2,
-	GPIO5C1_MASK		= 1,
-	GPIO5C1_GPIO		= 0,
-	GPIO5C1_TS0_VALID,
-
-	GPIO5C0_SHIFT		= 0,
-	GPIO5C0_MASK		= 3,
-	GPIO5C0_GPIO		= 0,
-	GPIO5C0_SPI0_CSN1,
-	GPIO5C0_TS0_SYNC,
-};
-
-/* GRF_GPIO6B_IOMUX */
-enum {
-	GPIO6B3_SHIFT		= 6,
-	GPIO6B3_MASK		= 1,
-	GPIO6B3_GPIO		= 0,
-	GPIO6B3_SPDIF_TX,
-
-	GPIO6B2_SHIFT		= 4,
-	GPIO6B2_MASK		= 1,
-	GPIO6B2_GPIO		= 0,
-	GPIO6B2_I2C1AUDIO_SCL,
-
-	GPIO6B1_SHIFT		= 2,
-	GPIO6B1_MASK		= 1,
-	GPIO6B1_GPIO		= 0,
-	GPIO6B1_I2C1AUDIO_SDA,
-
-	GPIO6B0_SHIFT		= 0,
-	GPIO6B0_MASK		= 1,
-	GPIO6B0_GPIO		= 0,
-	GPIO6B0_I2S_CLK,
-};
-
-/* GRF_GPIO6C_IOMUX */
-enum {
-	GPIO6C6_SHIFT		= 12,
-	GPIO6C6_MASK		= 1,
-	GPIO6C6_GPIO		= 0,
-	GPIO6C6_SDMMC0_DECTN,
-
-	GPIO6C5_SHIFT		= 10,
-	GPIO6C5_MASK		= 1,
-	GPIO6C5_GPIO		= 0,
-	GPIO6C5_SDMMC0_CMD,
-
-	GPIO6C4_SHIFT		= 8,
-	GPIO6C4_MASK		= 3,
-	GPIO6C4_GPIO		= 0,
-	GPIO6C4_SDMMC0_CLKOUT,
-	GPIO6C4_JTAG_TDO,
-
-	GPIO6C3_SHIFT		= 6,
-	GPIO6C3_MASK		= 3,
-	GPIO6C3_GPIO		= 0,
-	GPIO6C3_SDMMC0_DATA3,
-	GPIO6C3_JTAG_TCK,
-
-	GPIO6C2_SHIFT		= 4,
-	GPIO6C2_MASK		= 3,
-	GPIO6C2_GPIO		= 0,
-	GPIO6C2_SDMMC0_DATA2,
-	GPIO6C2_JTAG_TDI,
-
-	GPIO6C1_SHIFT		= 2,
-	GPIO6C1_MASK		= 3,
-	GPIO6C1_GPIO		= 0,
-	GPIO6C1_SDMMC0_DATA1,
-	GPIO6C1_JTAG_TRSTN,
-
-	GPIO6C0_SHIFT		= 0,
-	GPIO6C0_MASK		= 3,
-	GPIO6C0_GPIO		= 0,
-	GPIO6C0_SDMMC0_DATA0,
-	GPIO6C0_JTAG_TMS,
-};
-
-/* GRF_GPIO7A_IOMUX */
-enum {
-	GPIO7A7_SHIFT		= 14,
-	GPIO7A7_MASK		= 3,
-	GPIO7A7_GPIO		= 0,
-	GPIO7A7_UART3GPS_SIN,
-	GPIO7A7_GPS_MAG,
-	GPIO7A7_HSADCT1_DATA0,
-
-	GPIO7A1_SHIFT		= 2,
-	GPIO7A1_MASK		= 1,
-	GPIO7A1_GPIO		= 0,
-	GPIO7A1_PWM_1,
-
-	GPIO7A0_SHIFT		= 0,
-	GPIO7A0_MASK		= 3,
-	GPIO7A0_GPIO		= 0,
-	GPIO7A0_PWM_0,
-	GPIO7A0_VOP0_PWM,
-	GPIO7A0_VOP1_PWM,
-};
-
-/* GRF_GPIO7B_IOMUX */
-enum {
-	GPIO7B7_SHIFT		= 14,
-	GPIO7B7_MASK		= 3,
-	GPIO7B7_GPIO		= 0,
-	GPIO7B7_ISP_SHUTTERTRIG,
-	GPIO7B7_SPI1_TXD,
-
-	GPIO7B6_SHIFT		= 12,
-	GPIO7B6_MASK		= 3,
-	GPIO7B6_GPIO		= 0,
-	GPIO7B6_ISP_PRELIGHTTRIG,
-	GPIO7B6_SPI1_RXD,
-
-	GPIO7B5_SHIFT		= 10,
-	GPIO7B5_MASK		= 3,
-	GPIO7B5_GPIO		= 0,
-	GPIO7B5_ISP_FLASHTRIGOUT,
-	GPIO7B5_SPI1_CSN0,
-
-	GPIO7B4_SHIFT		= 8,
-	GPIO7B4_MASK		= 3,
-	GPIO7B4_GPIO		= 0,
-	GPIO7B4_ISP_SHUTTEREN,
-	GPIO7B4_SPI1_CLK,
-
-	GPIO7B3_SHIFT		= 6,
-	GPIO7B3_MASK		= 3,
-	GPIO7B3_GPIO		= 0,
-	GPIO7B3_USB_DRVVBUS1,
-	GPIO7B3_EDP_HOTPLUG,
-
-	GPIO7B2_SHIFT		= 4,
-	GPIO7B2_MASK		= 3,
-	GPIO7B2_GPIO		= 0,
-	GPIO7B2_UART3GPS_RTSN,
-	GPIO7B2_USB_DRVVBUS0,
-
-	GPIO7B1_SHIFT		= 2,
-	GPIO7B1_MASK		= 3,
-	GPIO7B1_GPIO		= 0,
-	GPIO7B1_UART3GPS_CTSN,
-	GPIO7B1_GPS_RFCLK,
-	GPIO7B1_GPST1_CLK,
-
-	GPIO7B0_SHIFT		= 0,
-	GPIO7B0_MASK		= 3,
-	GPIO7B0_GPIO		= 0,
-	GPIO7B0_UART3GPS_SOUT,
-	GPIO7B0_GPS_SIG,
-	GPIO7B0_HSADCT1_DATA1,
-};
-
-/* GRF_GPIO7CL_IOMUX */
-enum {
-	GPIO7C3_SHIFT		= 12,
-	GPIO7C3_MASK		= 3,
-	GPIO7C3_GPIO		= 0,
-	GPIO7C3_I2C5HDMI_SDA,
-	GPIO7C3_EDPHDMII2C_SDA,
-
-	GPIO7C2_SHIFT		= 8,
-	GPIO7C2_MASK		= 1,
-	GPIO7C2_GPIO		= 0,
-	GPIO7C2_I2C4TP_SCL,
-
-	GPIO7C1_SHIFT		= 4,
-	GPIO7C1_MASK		= 1,
-	GPIO7C1_GPIO		= 0,
-	GPIO7C1_I2C4TP_SDA,
-
-	GPIO7C0_SHIFT		= 0,
-	GPIO7C0_MASK		= 3,
-	GPIO7C0_GPIO		= 0,
-	GPIO7C0_ISP_FLASHTRIGIN,
-	GPIO7C0_EDPHDMI_CECINOUTT1,
-};
-
-/* GRF_GPIO7CH_IOMUX */
-enum {
-	GPIO7C7_SHIFT		= 12,
-	GPIO7C7_MASK		= 7,
-	GPIO7C7_GPIO		= 0,
-	GPIO7C7_UART2DBG_SOUT,
-	GPIO7C7_UART2DBG_SIROUT,
-	GPIO7C7_PWM_3,
-	GPIO7C7_EDPHDMI_CECINOUT,
-
-	GPIO7C6_SHIFT		= 8,
-	GPIO7C6_MASK		= 3,
-	GPIO7C6_GPIO		= 0,
-	GPIO7C6_UART2DBG_SIN,
-	GPIO7C6_UART2DBG_SIRIN,
-	GPIO7C6_PWM_2,
-
-	GPIO7C4_SHIFT		= 0,
-	GPIO7C4_MASK		= 3,
-	GPIO7C4_GPIO		= 0,
-	GPIO7C4_I2C5HDMI_SCL,
-	GPIO7C4_EDPHDMII2C_SCL,
-};
-
-/* GRF_GPIO8A_IOMUX */
-enum {
-	GPIO8A7_SHIFT		= 14,
-	GPIO8A7_MASK		= 3,
-	GPIO8A7_GPIO		= 0,
-	GPIO8A7_SPI2_CSN0,
-	GPIO8A7_SC_DETECT,
-	GPIO8A7_RESERVE,
-
-	GPIO8A6_SHIFT		= 12,
-	GPIO8A6_MASK		= 3,
-	GPIO8A6_GPIO		= 0,
-	GPIO8A6_SPI2_CLK,
-	GPIO8A6_SC_IO,
-	GPIO8A6_RESERVE,
-
-	GPIO8A5_SHIFT		= 10,
-	GPIO8A5_MASK		= 3,
-	GPIO8A5_GPIO		= 0,
-	GPIO8A5_I2C2SENSOR_SCL,
-	GPIO8A5_SC_CLK,
-
-	GPIO8A4_SHIFT		= 8,
-	GPIO8A4_MASK		= 3,
-	GPIO8A4_GPIO		= 0,
-	GPIO8A4_I2C2SENSOR_SDA,
-	GPIO8A4_SC_RST,
-
-	GPIO8A3_SHIFT		= 6,
-	GPIO8A3_MASK		= 3,
-	GPIO8A3_GPIO		= 0,
-	GPIO8A3_SPI2_CSN1,
-	GPIO8A3_SC_IOT1,
-
-	GPIO8A2_SHIFT		= 4,
-	GPIO8A2_MASK		= 1,
-	GPIO8A2_GPIO		= 0,
-	GPIO8A2_SC_DETECTT1,
-
-	GPIO8A1_SHIFT		= 2,
-	GPIO8A1_MASK		= 3,
-	GPIO8A1_GPIO		= 0,
-	GPIO8A1_PS2_DATA,
-	GPIO8A1_SC_VCC33V,
-
-	GPIO8A0_SHIFT		= 0,
-	GPIO8A0_MASK		= 3,
-	GPIO8A0_GPIO		= 0,
-	GPIO8A0_PS2_CLK,
-	GPIO8A0_SC_VCC18V,
-};
-
-/* GRF_GPIO8B_IOMUX */
-enum {
-	GPIO8B1_SHIFT		= 2,
-	GPIO8B1_MASK		= 3,
-	GPIO8B1_GPIO		= 0,
-	GPIO8B1_SPI2_TXD,
-	GPIO8B1_SC_CLK,
-
-	GPIO8B0_SHIFT		= 0,
-	GPIO8B0_MASK		= 3,
-	GPIO8B0_GPIO		= 0,
-	GPIO8B0_SPI2_RXD,
-	GPIO8B0_SC_RST,
-};
-
-/* GRF_SOC_CON0 */
-enum {
-	PAUSE_MMC_PERI_SHIFT	= 0xf,
-	PAUSE_MMC_PERI_MASK	= 1,
-
-	PAUSE_EMEM_PERI_SHIFT	= 0xe,
-	PAUSE_EMEM_PERI_MASK	= 1,
-
-	PAUSE_USB_PERI_SHIFT	= 0xd,
-	PAUSE_USB_PERI_MASK	= 1,
-
-	GRF_FORCE_JTAG_SHIFT	= 0xc,
-	GRF_FORCE_JTAG_MASK	= 1,
-
-	GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
-	GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
-
-	GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
-	GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
-
-	DDR1_16BIT_EN_SHIFT	= 9,
-	DDR1_16BIT_EN_MASK	= 1,
-
-	DDR0_16BIT_EN_SHIFT	= 8,
-	DDR0_16BIT_EN_MASK	= 1,
-
-	VCODEC_SHIFT		= 7,
-	VCODEC_MASK		= 1,
-	VCODEC_SELECT_VEPU_ACLK	= 0,
-	VCODEC_SELECT_VDPU_ACLK,
-
-	UPCTL1_C_ACTIVE_IN_SHIFT = 6,
-	UPCTL1_C_ACTIVE_IN_MASK	= 1,
-	UPCTL1_C_ACTIVE_IN_MAY	= 0,
-	UPCTL1_C_ACTIVE_IN_WILL,
-
-	UPCTL0_C_ACTIVE_IN_SHIFT = 5,
-	UPCTL0_C_ACTIVE_IN_MASK	= 1,
-	UPCTL0_C_ACTIVE_IN_MAY	= 0,
-	UPCTL0_C_ACTIVE_IN_WILL,
-
-	MSCH1_MAINDDR3_SHIFT	= 4,
-	MSCH1_MAINDDR3_MASK	= 1,
-	MSCH1_MAINDDR3_DDR3	= 1,
-
-	MSCH0_MAINDDR3_SHIFT	= 3,
-	MSCH0_MAINDDR3_MASK	= 1,
-	MSCH0_MAINDDR3_DDR3	= 1,
-
-	MSCH1_MAINPARTIALPOP_SHIFT = 2,
-	MSCH1_MAINPARTIALPOP_MASK = 1,
-
-	MSCH0_MAINPARTIALPOP_SHIFT = 1,
-	MSCH0_MAINPARTIALPOP_MASK = 1,
-};
-
-/* GRF_SOC_CON2 */
-enum {
-	UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
-	UPCTL1_LPDDR3_ODT_EN_MASK = 1,
-	UPCTL1_LPDDR3_ODT_EN_ODT = 1,
-
-	UPCTL1_BST_DIABLE_SHIFT	= 0xc,
-	UPCTL1_BST_DIABLE_MASK	= 1,
-	UPCTL1_BST_DIABLE_DISABLE = 1,
-
-	LPDDR3_EN1_SHIFT	= 0xb,
-	LPDDR3_EN1_MASK		= 1,
-	LPDDR3_EN1_LPDDR3	= 1,
-
-	UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
-	UPCTL0_LPDDR3_ODT_EN_MASK = 1,
-	UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
-
-	UPCTL0_BST_DIABLE_SHIFT	= 9,
-	UPCTL0_BST_DIABLE_MASK	= 1,
-	UPCTL0_BST_DIABLE_DISABLE = 1,
-
-	LPDDR3_EN0_SHIFT	= 8,
-	LPDDR3_EN0_MASK		= 1,
-	LPDDR3_EN0_LPDDR3	= 1,
-
-	GRF_POC_FLASH0_CTRL_SHIFT = 7,
-	GRF_POC_FLASH0_CTRL_MASK = 1,
-	GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
-	GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
-
-	SIMCARD_MUX_SHIFT	= 6,
-	SIMCARD_MUX_MASK	= 1,
-	SIMCARD_MUX_USE_A	= 1,
-	SIMCARD_MUX_USE_B	= 0,
-
-	GRF_SPDIF_2CH_EN_SHIFT	= 1,
-	GRF_SPDIF_2CH_EN_MASK	= 1,
-	GRF_SPDIF_2CH_EN_8CH	= 0,
-	GRF_SPDIF_2CH_EN_2CH,
-
-	PWM_SHIFT		= 0,
-	PWM_MASK		= 1,
-	PWM_RK			= 1,
-	PWM_PWM			= 0,
-};
-
-#endif
diff --git a/arch/arm/mach-rockchip/include/mach/hardware.h b/arch/arm/mach-rockchip/include/mach/hardware.h
deleted file mode 100644
index b0afd1f3d4..0000000000
--- a/arch/arm/mach-rockchip/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_HARDWARE_H
-#define _ASM_ARCH_HARDWARE_H
-
-#define RK_CLRSETBITS(clr, set)		((((clr) | (set)) << 16) | set)
-#define RK_SETBITS(set)			RK_CLRSETBITS(0, set)
-#define RK_CLRBITS(clr)			RK_CLRSETBITS(clr, 0)
-
-#define rk_clrsetreg(addr, clr, set)	writel((clr) << 16 | (set), addr)
-#define rk_clrreg(addr, clr)		writel((clr) << 16, addr)
-#define rk_setreg(addr, set)		writel(set, addr)
-
-#endif
diff --git a/arch/arm/mach-rockchip/include/mach/rk3188-regs.h b/arch/arm/mach-rockchip/include/mach/rk3188-regs.h
deleted file mode 100644
index f147fe27fe..0000000000
--- a/arch/arm/mach-rockchip/include/mach/rk3188-regs.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_RK3188_REGS_H
-#define __MACH_RK3188_REGS_H
-
-#define RK_CRU_BASE		0x20000000
-#define RK_GRF_BASE		0x20008000
-
-#define RK_CRU_GLB_SRST_SND	0x0104
-#define RK_GRF_SOC_CON0		0x00a0
-
-#define RK_SOC_CON0_REMAP	(1 << 12)
-
-/* UART */
-#define RK3188_UART0_BASE	0x10124000
-#define RK3188_UART1_BASE	0x10126000
-#define RK3188_UART2_BASE	0x20064000
-#define RK3188_UART3_BASE	0x20068000
-
-#endif /* __MACH_RK3188_REGS_H */
diff --git a/arch/arm/mach-rockchip/include/mach/rk3288-regs.h b/arch/arm/mach-rockchip/include/mach/rk3288-regs.h
deleted file mode 100644
index a83a3a818b..0000000000
--- a/arch/arm/mach-rockchip/include/mach/rk3288-regs.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2016 PHYTEC Messtechnik GmbH,
- * Author: Wadim Egorov <w.egorov@phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_RK3288_REGS_H
-#define __MACH_RK3288_REGS_H
-
-#define RK3288_CRU_BASE		0xff760000
-#define RK3288_GRF_BASE		0xff770000
-
-/* UART */
-#define RK3288_UART0_BASE	0xff180000
-#define RK3288_UART1_BASE	0xff190000
-#define RK3288_UART2_BASE	0xff690000
-#define RK3288_UART3_BASE	0xff1b0000
-#define RK3288_UART4_BASE	0xff1c0000
-
-#endif /* __MACH_RK3288_REGS_H */
diff --git a/arch/arm/mach-rockchip/include/mach/timer.h b/arch/arm/mach-rockchip/include/mach/timer.h
deleted file mode 100644
index e6ed0e4e3e..0000000000
--- a/arch/arm/mach-rockchip/include/mach/timer.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_TIMER_H
-#define _ASM_ARCH_TIMER_H
-
-struct rk_timer {
-	unsigned int timer_load_count0;
-	unsigned int timer_load_count1;
-	unsigned int timer_curr_value0;
-	unsigned int timer_curr_value1;
-	unsigned int timer_ctrl_reg;
-	unsigned int timer_int_status;
-};
-
-#endif
diff --git a/arch/arm/mach-rockchip/rk3188.c b/arch/arm/mach-rockchip/rk3188.c
index 572e9dc58f..f1c20f6e52 100644
--- a/arch/arm/mach-rockchip/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188.c
@@ -15,7 +15,8 @@
 #include <common.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/rk3188-regs.h>
+#include <mach/rockchip/rk3188-regs.h>
+#include <mach/rockchip/rockchip.h>
 
 static void __noreturn rockchip_restart_soc(struct restart_handler *rst)
 {
@@ -27,10 +28,9 @@ static void __noreturn rockchip_restart_soc(struct restart_handler *rst)
 	hang();
 }
 
-static int restart_register_feature(void)
+int rk3188_init(void)
 {
 	restart_handler_register_fn("soc", rockchip_restart_soc);
 
 	return 0;
 }
-coredevice_initcall(restart_register_feature);
diff --git a/arch/arm/mach-rockchip/rk3288.c b/arch/arm/mach-rockchip/rk3288.c
index 9076fd9227..3a43e911db 100644
--- a/arch/arm/mach-rockchip/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288.c
@@ -18,9 +18,10 @@
 #include <restart.h>
 #include <reset_source.h>
 #include <bootsource.h>
-#include <mach/rk3288-regs.h>
-#include <mach/cru_rk3288.h>
-#include <mach/hardware.h>
+#include <mach/rockchip/rk3288-regs.h>
+#include <mach/rockchip/cru_rk3288.h>
+#include <mach/rockchip/hardware.h>
+#include <mach/rockchip/rockchip.h>
 
 static void __noreturn rockchip_restart_soc(struct restart_handler *rst)
 {
@@ -58,17 +59,6 @@ static void rk3288_detect_reset_reason(void)
 	}
 }
 
-static int rk3288_init(void)
-{
-	restart_handler_register_fn("soc", rockchip_restart_soc);
-
-	if (IS_ENABLED(CONFIG_RESET_SOURCE))
-		rk3288_detect_reset_reason();
-
-	return 0;
-}
-postcore_initcall(rk3288_init);
-
 /*
  * ATM we are not able to determine the boot source.
  * So let's handle the environment on eMMC, regardless which device
@@ -79,8 +69,7 @@ static int rk3288_env_init(void)
 	const char *envpath = "/chosen/environment-emmc";
 	int ret;
 
-	bootsource_set(BOOTSOURCE_MMC);
-	bootsource_set_instance(0);
+	bootsource_set_raw(BOOTSOURCE_MMC, 0);
 
 	ret = of_device_enable_path(envpath);
 	if (ret < 0)
@@ -89,4 +78,15 @@ static int rk3288_env_init(void)
 
 	return 0;
 }
-device_initcall(rk3288_env_init);
+
+int rk3288_init(void)
+{
+	restart_handler_register_fn("soc", rockchip_restart_soc);
+
+	if (IS_ENABLED(CONFIG_RESET_SOURCE))
+		rk3288_detect_reset_reason();
+
+	rk3288_env_init();
+
+	return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3568.c b/arch/arm/mach-rockchip/rk3568.c
new file mode 100644
index 0000000000..75b0824479
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier:     GPL-2.0+
+#include <common.h>
+#include <io.h>
+#include <bootsource.h>
+#include <mach/rockchip/bootrom.h>
+#include <mach/rockchip/rk3568-regs.h>
+#include <mach/rockchip/rockchip.h>
+
+#define GRF_BASE		0xfdc60000
+#define GRF_GPIO1B_DS_2		0x218
+#define GRF_GPIO1B_DS_3		0x21c
+#define GRF_GPIO1C_DS_0		0x220
+#define GRF_GPIO1C_DS_1		0x224
+#define GRF_GPIO1C_DS_2		0x228
+#define GRF_GPIO1C_DS_3		0x22c
+#define GRF_GPIO1D_DS_0		0x230
+#define GRF_GPIO1D_DS_1		0x234
+#define GRF_SOC_CON4		0x510
+#define EDP_PHY_GRF_BASE	0xfdcb0000
+#define EDP_PHY_GRF_CON0	(EDP_PHY_GRF_BASE + 0x00)
+#define EDP_PHY_GRF_CON10	(EDP_PHY_GRF_BASE + 0x28)
+#define PMU_BASE_ADDR		0xfdd90000
+#define PMU_NOC_AUTO_CON0	0x70
+#define PMU_NOC_AUTO_CON1	0x74
+#define CRU_BASE		0xfdd20000
+#define CRU_SOFTRST_CON26	0x468
+#define CRU_SOFTRST_CON28	0x470
+#define SGRF_BASE		0xFDD18000
+#define SGRF_SOC_CON3		0xC
+#define SGRF_SOC_CON4		0x10
+#define PMUGRF_SOC_CON15	0xfdc20100
+#define CPU_GRF_BASE		0xfdc30000
+#define GRF_CORE_PVTPLL_CON0	0x10
+#define USBPHY_U3_GRF		0xfdca0000
+#define USBPHY_U3_GRF_CON1	(USBPHY_U3_GRF + 0x04)
+#define USBPHY_U2_GRF		0xfdca8000
+#define USBPHY_U2_GRF_CON0	(USBPHY_U2_GRF + 0x00)
+#define USBPHY_U2_GRF_CON1	(USBPHY_U2_GRF + 0x04)
+
+#define PMU_PWR_GATE_SFTCON	0xA0
+#define PMU_PWR_DWN_ST		0x98
+#define PMU_BUS_IDLE_SFTCON0	0x50
+#define PMU_BUS_IDLE_ST		0x68
+#define PMU_BUS_IDLE_ACK	0x60
+
+#define EBC_PRIORITY_REG	0xfe158008
+
+static void qos_priority_init(void)
+{
+	u32 delay;
+
+	/* enable all pd except npu and gpu */
+	writel(0xffff0000 & ~(BIT(0 + 16) | BIT(1 + 16)),
+	       PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
+	delay = 1000;
+	do {
+		udelay(1);
+		delay--;
+		if (delay == 0) {
+			printf("Fail to set domain.");
+			hang();
+		}
+	} while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & ~(BIT(0) | BIT(1)));
+
+	/* release all idle request except npu and gpu */
+	writel(0xffff0000 & ~(BIT(1 + 16) | BIT(2 + 16)),
+	       PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON0);
+
+	delay = 1000;
+	/* wait ack status */
+	do {
+		udelay(1);
+		delay--;
+		if (delay == 0) {
+			printf("Fail to get ack on domain.\n");
+			hang();
+		}
+	} while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK) & ~(BIT(1) | BIT(2)));
+
+	delay = 1000;
+	/* wait idle status */
+	do {
+		udelay(1);
+		delay--;
+		if (delay == 0) {
+			printf("Fail to set idle on domain.\n");
+			hang();
+		}
+	} while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST) & ~(BIT(1) | BIT(2)));
+
+	writel(0x303, EBC_PRIORITY_REG);
+}
+
+void rk3568_lowlevel_init(void)
+{
+	arm_cpu_lowlevel_init();
+
+	/*
+	 * When perform idle operation, corresponding clock can
+	 * be opened or gated automatically.
+	 */
+	writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
+	writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
+
+	/* Set the emmc sdmmc0 to secure */
+	writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
+	/* set the emmc ds to level 2 */
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+
+	/* Set the fspi to secure */
+	writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
+
+	/* Disable eDP phy by default */
+	writel(0x00070007, EDP_PHY_GRF_CON10);
+	writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
+
+	/* Set core pvtpll ring length */
+	writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
+
+	/*
+	 * Assert reset the pipephy0, pipephy1 and pipephy2,
+	 * and de-assert reset them in Kernel combphy driver.
+	 */
+	writel(0x02a002a0, CRU_BASE + CRU_SOFTRST_CON28);
+
+	/*
+	 * Set USB 2.0 PHY0 port1 and PHY1 port0 and port1
+	 * enter suspend mode to to save power. And USB 2.0
+	 * PHY0 port0 for OTG interface still in normal mode.
+	 */
+	writel(0x01ff01d1, USBPHY_U3_GRF_CON1);
+	writel(0x01ff01d1, USBPHY_U2_GRF_CON0);
+	writel(0x01ff01d1, USBPHY_U2_GRF_CON1);
+
+	qos_priority_init();
+}
+
+int rk3568_init(void)
+{
+	rockchip_parse_bootrom_iram(rockchip_scratch_space());
+
+	return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3588.c b/arch/arm/mach-rockchip/rk3588.c
new file mode 100644
index 0000000000..25f1481296
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier:     GPL-2.0+
+#include <common.h>
+#include <io.h>
+#include <bootsource.h>
+#include <mach/rockchip/rk3588-regs.h>
+#include <mach/rockchip/rockchip.h>
+#include <asm/barebox-arm-head.h>
+#include <mach/rockchip/bootrom.h>
+
+void rk3588_lowlevel_init(void)
+{
+	arm_cpu_lowlevel_init();
+}
+
+int rk3588_init(void)
+{
+	rockchip_parse_bootrom_iram(rockchip_scratch_space());
+
+	return 0;
+}
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
new file mode 100644
index 0000000000..1c962ad8c8
--- /dev/null
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <common.h>
+#include <init.h>
+#include <mach/rockchip/rockchip.h>
+
+static int __rockchip_soc;
+
+int rockchip_soc(void)
+{
+	if (__rockchip_soc)
+		return __rockchip_soc;
+
+	if (of_machine_is_compatible("rockchip,rk3188"))
+		__rockchip_soc = 3188;
+	else if (of_machine_is_compatible("rockchip,rk3288"))
+		__rockchip_soc = 3288;
+	else if (of_machine_is_compatible("rockchip,rk3566"))
+		__rockchip_soc = 3566;
+	else if (of_machine_is_compatible("rockchip,rk3568"))
+		__rockchip_soc = 3568;
+	else if (of_machine_is_compatible("rockchip,rk3588"))
+		__rockchip_soc = 3588;
+
+	return __rockchip_soc;
+}
+
+static int rockchip_init(void)
+{
+	switch (rockchip_soc()) {
+	case 3188:
+		return rk3188_init();
+	case 3288:
+		return rk3288_init();
+	case 3566:
+		return rk3568_init();
+	case 3568:
+		return rk3568_init();
+	case 3588:
+		return rk3588_init();
+	}
+
+	return 0;
+}
+postcore_initcall(rockchip_init);
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
deleted file mode 100644
index fa1a3ddcc4..0000000000
--- a/arch/arm/mach-samsung/Kconfig
+++ /dev/null
@@ -1,176 +0,0 @@
-config ARCH_SAMSUNG
-	bool
-
-if ARCH_SAMSUNG
-
-config ARCH_TEXT_BASE
-	hex
-	default 0x31fc0000 if MACH_MINI2440
-	default 0x57fc0000 if MACH_MINI6410
-	default 0x57fc0000 if MACH_TINY6410
-	default 0x31fc0000 if MACH_A9M2440
-	default 0x31fc0000 if MACH_A9M2410
-	default 0x23e00000 if MACH_TINY210
-
-config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
-	hex
-	default 0x1ff0 if ARCH_S5PCxx
-# TODO
-	default 0x2000 if ARCH_S3C64xx
-
-if ARCH_S3C24xx
-
-config CPU_S3C2410
-	bool
-
-config CPU_S3C2440
-	bool
-
-choice
-	prompt "S3C24xx Board Type"
-
-config MACH_A9M2410
-	bool "Digi A9M2410"
-	select CPU_S3C2410
-	select S3C_PLL_INIT
-	select S3C_SDRAM_INIT
-	help
-	  Say Y here if you are using Digi's Connect Core 9M equipped
-	  with a Samsung S3C2410 Processor
-
-config MACH_A9M2440
-	bool "Digi A9M2440"
-	select CPU_S3C2440
-	select S3C_PLL_INIT
-	help
-	  Say Y here if you are using Digi's Connect Core 9M equipped
-	  with a Samsung S3C2440 Processor
-
-config MACH_MINI2440
-	bool "Mini 2440"
-	select CPU_S3C2440
-	select S3C_PLL_INIT
-	select S3C_SDRAM_INIT
-	select HAS_DM9000
-	help
-	  Say Y here if you are using Mini 2440 dev board equipped
-	  with a Samsung S3C2440 Processor
-
-endchoice
-
-menu "Board specific settings"
-
-choice
-	prompt "A9M2440 baseboard"
-	depends on MACH_A9M2440
-
-config MACH_A9M2410DEV
-	bool
-	prompt "A9M2410dev"
-	select HAS_CS8900
-	help
-	  Digi's evaluation board.
-
-endchoice
-
-source "arch/arm/boards/friendlyarm-mini2440/Kconfig"
-
-endmenu
-
-endif
-
-if ARCH_S3C64xx
-
-config CPU_S3C6410
-	bool
-
-choice
-	prompt "S3C64xx Board Type"
-
-config MACH_MINI6410
-	bool "Mini 6410"
-	select CPU_S3C6410
-	select HAS_DM9000
-	help
-	  Say Y here if you are using FriendlyARM Mini6410 board equipped
-	  with a Samsung S3C6410 Processor
-
-config MACH_TINY6410
-	bool "Tiny 6410"
-	select CPU_S3C6410
-	help
-	  Say Y here if you are using FriendlyARM Tiny6410 CPU card equipped
-	  with a Samsung S3C6410 Processor
-
-endchoice
-
-menu "Board specific settings"
-
-source "arch/arm/boards/friendlyarm-tiny6410/Kconfig"
-
-endmenu
-
-endif
-
-if ARCH_S5PCxx
-
-config CPU_S5PC110
-	bool
-
-config CPU_S5PV210
-	bool
-
-choice
-	prompt "S5PCxx board type"
-
-config MACH_TINY210
-	bool "Tiny 210"
-	select CPU_S5PV210
-	select S3C_SDRAM_INIT
-
-endchoice
-
-endif
-
-menu "S3C Features"
-
-config S3C_LOWLEVEL_INIT
-	bool
-
-config S3C_PLL_INIT
-	bool
-	prompt "Reconfigure PLL"
-	select S3C_LOWLEVEL_INIT
-	help
-	  This adds generic code to reconfigure the internal PLL very early
-	  after reset.
-
-config S3C_SDRAM_INIT
-	bool
-	prompt "Initialize SDRAM"
-	select S3C_LOWLEVEL_INIT
-	help
-	  This adds generic code to configure the SDRAM controller after reset.
-	  The initialisation will be skipped if the code is already running
-	  from SDRAM.
-
-config S3C_NAND_BOOT
-	bool
-	prompt "Booting from NAND"
-	depends on ARCH_S3C24xx
-	select MTD
-	select NAND
-	select NAND_S3C24XX
-	help
-	  Add generic support to boot from NAND flash. Image loading will be
-	  skipped if the code is running from NOR or already from SDRAM.
-
-config BAREBOX_UPDATE_NAND_S3C24XX
-	bool
-	depends on BAREBOX_UPDATE
-	depends on S3C_NAND_BOOT
-	default y
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
deleted file mode 100644
index 284c80a2ad..0000000000
--- a/arch/arm/mach-samsung/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-obj-y += s3c-timer.o generic.o
-obj-$(CONFIG_RESET_SOURCE) += reset_source.o
-obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
-obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
-pbl-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
-pbl-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
-obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
-obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o mem-s3c64xx.o
-obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
-pbl-$(CONFIG_ARCH_S5PCxx) += mem-s5pcxx.o
-obj-$(CONFIG_BAREBOX_UPDATE_NAND_S3C24XX) += bbu-nand-s3c24x0.o
-obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/bbu-nand-s3c24x0.c b/arch/arm/mach-samsung/bbu-nand-s3c24x0.c
deleted file mode 100644
index 0d25abfeb7..0000000000
--- a/arch/arm/mach-samsung/bbu-nand-s3c24x0.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2014 Michael Olbrich, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation.
- *
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <bbu.h>
-#include <fs.h>
-#include <fcntl.h>
-
-static int nand_update(struct bbu_handler *handler, struct bbu_data *data)
-{
-	int fd, ret;
-
-	if (file_detect_type(data->image, data->len) != filetype_arm_barebox &&
-			!bbu_force(data, "Not an ARM barebox image"))
-		return -EINVAL;
-
-	ret = bbu_confirm(data);
-	if (ret)
-		return ret;
-
-	fd = open(data->devicefile, O_WRONLY);
-	if (fd < 0)
-		return fd;
-
-	debug("%s: eraseing %s from 0 to 0x%08x\n", __func__,
-			data->devicefile, data->len);
-	ret = erase(fd, data->len, 0);
-	if (ret) {
-		printf("erasing %s failed with %s\n", data->devicefile,
-				strerror(-ret));
-		goto err_close;
-	}
-
-	ret = write(fd, data->image, data->len);
-	if (ret < 0) {
-		printf("writing update to %s failed with %s\n", data->devicefile,
-				strerror(-ret));
-		goto err_close;
-	}
-
-	ret = 0;
-
-err_close:
-	close(fd);
-
-	return ret;
-}
-
-/*
- * Register a s3c24x0 update handler for NAND
- */
-int s3c24x0_bbu_nand_register_handler(void)
-{
-	struct bbu_handler *handler;
-	int ret;
-
-	handler = xzalloc(sizeof(*handler));
-	handler->devicefile = "/dev/nand0.barebox";
-	handler->name = "nand";
-	handler->handler = nand_update;
-	handler->flags = BBU_HANDLER_FLAG_DEFAULT;
-
-	ret = bbu_register_handler(handler);
-	if (ret)
-		free(handler);
-
-	return ret;
-}
diff --git a/arch/arm/mach-samsung/clocks-s3c24xx.c b/arch/arm/mach-samsung/clocks-s3c24xx.c
deleted file mode 100644
index a2dd869672..0000000000
--- a/arch/arm/mach-samsung/clocks-s3c24xx.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-clocks.h>
-#include <mach/s3c-busctl.h>
-
-/**
- * Calculate the current M-PLL clock.
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_mpllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	reg_val = readl(S3C_MPLLCON);
-	m = ((reg_val & 0xFF000) >> 12) + 8;
-	p = ((reg_val & 0x003F0) >> 4) + 2;
-	s = reg_val & 0x3;
-#ifdef CONFIG_CPU_S3C2410
-	return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-#endif
-#ifdef CONFIG_CPU_S3C2440
-	return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
-#endif
-}
-
-/**
- * Calculate the current U-PLL clock
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_upllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	reg_val = readl(S3C_UPLLCON);
-	m = ((reg_val & 0xFF000) >> 12) + 8;
-	p = ((reg_val & 0x003F0) >> 4) + 2;
-	s = reg_val & 0x3;
-
-	return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-/**
- * Calculate the FCLK frequency used for the ARM CPU core
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_fclk(void)
-{
-	return s3c_get_mpllclk();
-}
-
-/**
- * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_hclk(void)
-{
-	uint32_t f_clk;
-
-	f_clk = s3c_get_fclk();
-#ifdef CONFIG_CPU_S3C2410
-	if (readl(S3C_CLKDIVN) & 0x02)
-		return f_clk >> 1;
-#endif
-#ifdef CONFIG_CPU_S3C2440
-	switch(readl(S3C_CLKDIVN) & 0x06) {
-	case 2:
-		return f_clk >> 1;
-	case 4:
-		return f_clk >> 2;	/* TODO consider CAMDIVN */
-	case 6:
-		return f_clk / 3;	/* TODO consider CAMDIVN */
-	}
-#endif
-	return f_clk;
-}
-
-/**
- * Calculate the PCLK frequency used for the slower peripherals
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_pclk(void)
-{
-	uint32_t p_clk;
-
-	p_clk = s3c_get_hclk();
-	if (readl(S3C_CLKDIVN) & 0x01)
-		return p_clk >> 1;
-	return p_clk;
-}
-
-/**
- * Return correct UART frequency based on the UCON register
- */
-unsigned s3c_get_uart_clk(unsigned src)
-{
-	switch (src & 3) {
-	case 0:
-	case 2:
-		return s3c_get_pclk();
-	case 1:
-		return 0; /* TODO UEXTCLK */
-	case 3:
-		return 0; /* TODO FCLK/n */
-	}
-	return 0; /* not reached, to make compiler happy */
-}
-
-/**
- * Show the user the current clock settings
- */
-static int s3c24xx_dump_clocks(void)
-{
-	printf("refclk:  %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
-	printf("mpll:    %7d kHz\n", s3c_get_mpllclk() / 1000);
-	printf("upll:    %7d kHz\n", s3c_get_upllclk() / 1000);
-	printf("fclk:    %7d kHz\n", s3c_get_fclk() / 1000);
-	printf("hclk:    %7d kHz\n", s3c_get_hclk() / 1000);
-	printf("pclk:    %7d kHz\n", s3c_get_pclk() / 1000);
-	printf("SDRAM1:   CL%d@%dMHz\n", ((readl(S3C_BANKCON6) & 0xc) >> 2) + 2,
-						s3c_get_hclk() / 1000000);
-	if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
-		printf("SDRAM2:   CL%d@%dMHz\n",
-			((readl(S3C_BANKCON7) & 0xc) >> 2) + 2,
-			s3c_get_hclk() / 1000000);
-	return 0;
-}
-
-late_initcall(s3c24xx_dump_clocks);
diff --git a/arch/arm/mach-samsung/clocks-s3c64xx.c b/arch/arm/mach-samsung/clocks-s3c64xx.c
deleted file mode 100644
index 2229ed0529..0000000000
--- a/arch/arm/mach-samsung/clocks-s3c64xx.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <linux/math64.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-clocks.h>
-
-/*
- * The main clock tree:
- *
- * ref_in
- *    |
- *    v
- *    o-----------\
- *    |            MUX -o------------\
- *    |           / ^   |             MUX --- DIV_APLL ------- ARMCLK -> CPU core
- *    o--- APLL --  |   |            / |
- *    |             |   o--/2 -------  |
- *    |       APLL_SEL  |              |<-MISC_CON_SYN667
- *    |                 \              |
- *    o-----------\      MUX-o-------\ |
- *    |            MUX--/ ^  |        MUX --- DIV -o--------- HCLKx2 -> SDRAM (max. 266 MHz)
- *    |           / ^     |  |       /             |
- *    o---- MPLL--  |     |  o--/5 --              o-- DIV -- HCLK -> AXI / AHB (max. 133 MHz)
- *    |             |     |                        |
- *    |       MPLL_SEL  OTHERS_CLK_SELECT          o-- DIV -- PCLK -> APB (max. 66 MHz)
- *    |
- *    o-----------\
- *    |            MUX---- to various hardware
- *    |           / ^
- *    o---- EPLL--  EPLL_SEL
- *
- */
-
-static unsigned s3c_get_apllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	if (!(readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTAPLL))
-		return S3C64XX_CLOCK_REFERENCE;
-
-	reg_val = readl(S3C_APLLCON);
-	if (!(reg_val & S3C_APLLCON_ENABLE))
-		return 0;
-	m = S3C_APLLCON_GET_MDIV(reg_val);
-	p = S3C_APLLCON_GET_PDIV(reg_val);
-	s = S3C_APLLCON_GET_SDIV(reg_val);
-
-	return (S3C64XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-uint32_t s3c_get_mpllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	if (!(readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTMPLL))
-		return S3C64XX_CLOCK_REFERENCE;
-
-	reg_val = readl(S3C_MPLLCON);
-	if (!(reg_val & S3C_MPLLCON_ENABLE))
-		return 0;
-
-	m = S3C_MPLLCON_GET_MDIV(reg_val);
-	p = S3C_MPLLCON_GET_PDIV(reg_val);
-	s = S3C_MPLLCON_GET_SDIV(reg_val);
-
-	return (S3C64XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-unsigned s3c_get_epllclk(void)
-{
-	u32 m, p, s, k, reg0_val, reg1_val;
-	u64 tmp;
-
-	if (!(readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTEPLL))
-		return S3C64XX_CLOCK_REFERENCE;
-
-	reg0_val = readl(S3C_EPLLCON0);
-	if (!(reg0_val & S3C_EPLLCON0_ENABLE))
-		return 0;	/* PLL is disabled */
-
-	reg1_val = readl(S3C_EPLLCON1);
-	m = S3C_EPLLCON0_GET_MDIV(reg0_val);
-	p = S3C_EPLLCON0_GET_PDIV(reg0_val);
-	s = S3C_EPLLCON0_GET_SDIV(reg0_val);
-	k = S3C_EPLLCON1_GET_KDIV(reg1_val);
-
-	tmp = S3C64XX_CLOCK_REFERENCE;
-	tmp *= (m << 16) + k;
-	do_div(tmp, (p << s));
-
-	return (unsigned)(tmp >> 16);
-}
-
-unsigned s3c_set_epllclk(unsigned m, unsigned p, unsigned s, unsigned k)
-{
-	u32 con0, con1, src = readl(S3C_CLK_SRC) & ~S3C_CLK_SRC_FOUTEPLL;
-
-	/* do not use the EPLL clock when it is in transit to the new frequency */
-	writel(src, S3C_CLK_SRC);
-
-	con0 = S3C_EPLLCON0_SET_MDIV(m) | S3C_EPLLCON0_SET_PDIV(p) |
-				S3C_EPLLCON0_SET_SDIV(s) | S3C_EPLLCON0_ENABLE;
-	con1 = S3C_EPLLCON1_SET_KDIV(k);
-
-	/*
-	 * After changing the multiplication value 'm' the PLL output will
-	 * be masked for the time set in the EPLL_LOCK register until it
-	 * settles to the new frequency. EPLL_LOCK contains a value for a
-	 * simple counter which counts the external reference clock.
-	 */
-	writel(con0, S3C_EPLLCON0);
-	writel(con1, S3C_EPLLCON1);
-
-	udelay((1000000000 / S3C64XX_CLOCK_REFERENCE)
-		* (S3C_EPLL_LOCK_PLL_LOCKTIME(readl(S3C_EPLL_LOCK)) + 1) / 1000);
-
-	/* enable the EPLL's clock output to the system */
-	writel(src | S3C_CLK_SRC_FOUTEPLL, S3C_CLK_SRC);
-
-	return s3c_get_epllclk();
-}
-
-uint32_t s3c_get_fclk(void)
-{
-	unsigned clk;
-
-	clk = s3c_get_apllclk();
-	if (readl(S3C_MISC_CON) & S3C_MISC_CON_SYN667)
-		clk /= 2;
-
-	return clk / (S3C_CLK_DIV0_GET_ADIV(readl(S3C_CLK_DIV0)) + 1);
-}
-
-static unsigned s3c_get_hclk_in(void)
-{
-	unsigned clk;
-
-	if (readl(S3C_OTHERS) & S3C_OTHERS_CLK_SELECT)
-		clk = s3c_get_apllclk();
-	else
-		clk = s3c_get_mpllclk();
-
-	if (readl(S3C_MISC_CON) & S3C_MISC_CON_SYN667)
-		clk /= 5;
-
-	return clk;
-}
-
-static unsigned s3c_get_hclkx2(void)
-{
-	return s3c_get_hclk_in() /
-			(S3C_CLK_DIV0_GET_HCLK2(readl(S3C_CLK_DIV0)) + 1);
-}
-
-uint32_t s3c_get_hclk(void)
-{
-	return s3c_get_hclkx2() /
-			(S3C_CLK_DIV0_GET_HCLK(readl(S3C_CLK_DIV0)) + 1);
-}
-
-uint32_t s3c_get_pclk(void)
-{
-	return s3c_get_hclkx2() /
-			(S3C_CLK_DIV0_GET_PCLK(readl(S3C_CLK_DIV0)) + 1);
-}
-
-static void s3c_init_mpll_dout(void)
-{
-	unsigned reg;
-
-	/* keep it at the same frequency as HCLKx2 */
-	reg = readl(S3C_CLK_DIV0) | S3C_CLK_DIV0_SET_MPLL_DIV(1); /* e.g. / 2 */
-	writel(reg, S3C_CLK_DIV0);
-}
-
-/* configure and enable UCLK1 */
-static int s3c_init_uart_clock(void)
-{
-	unsigned reg;
-
-	s3c_init_mpll_dout();	/* to have a reliable clock source */
-
-	/* source the UART clock from the MPLL, currently *not* from EPLL */
-	reg = readl(S3C_CLK_SRC) | S3C_CLK_SRC_UARTMPLL;
-	writel(reg, S3C_CLK_SRC);
-
-	/* keep UART clock at the same frequency than the PCLK */
-	reg = readl(S3C_CLK_DIV2) & ~S3C_CLK_DIV2_UART_MASK;
-	reg |= S3C_CLK_DIV2_SET_UART(0x3);	/* / 4 */
-	writel(reg, S3C_CLK_DIV2);
-
-	/* ensure this very special clock is running */
-	reg = readl(S3C_SCLK_GATE) | S3C_SCLK_GATE_UART;
-	writel(reg, S3C_SCLK_GATE);
-
-	return 0;
-}
-core_initcall(s3c_init_uart_clock);
-
-/*                                         UART source selection
- * The UART related clock path:                     |
- *                                                  v
- * PCLK --------------------------------------o-----0-\
- * ???? -------------------------------UCLK0--|-----1--\MUX----- UART
- * MPLL -----DIV0------\                      +-----2--/
- *                     MUX---DIV2------UCLK1--------3-/
- * EPLL ---------------/
- *                      ^SRC_UARTMPLL
- */
-unsigned s3c_get_uart_clk(unsigned source)
-{
-	u32 reg;
-	unsigned clk, pdiv, uartpdiv;
-
-	switch (source) {
-	default: /* PCLK */
-		clk = s3c_get_pclk();
-		pdiv = uartpdiv = 1;
-		break;
-	case 1: /* UCLK0 */
-		clk = 0;
-		pdiv = uartpdiv = 1;	/* TODO */
-		break;
-	case 3: /* UCLK1 */
-		reg = readl(S3C_CLK_SRC);
-		if (reg & S3C_CLK_SRC_UARTMPLL) {
-			clk = s3c_get_mpllclk();
-			pdiv = S3C_CLK_DIV0_GET_MPLL_DIV(readl(S3C_CLK_DIV0)) + 1;
-		} else {
-			clk = s3c_get_epllclk();
-			pdiv = 1;
-		}
-		uartpdiv = S3C_CLK_DIV2_GET_UART(readl(S3C_CLK_DIV2)) + 1;
-		break;
-	}
-
-	return clk / pdiv / uartpdiv;
-}
-
-/*
- * The MMC related clock path:
- *
- *              MMCx_SEL
- *                 |
- *                 v
- * EPLLout --------0-\
- * MPLLout --DIV0--1--\-------SCLK_MMCx----DIV_MMCx------>HSMMCx
- * EPLLin  --------2--/        on/off      / 1..16
- * 27 MHz  --------3-/
- *
- * The datasheet is not very precise here, so the schematic shown above was
- * made by checking various bits in the SYSCON.
- */
-unsigned s3c_get_hsmmc_clk(int id)
-{
-	u32 sel, div, sclk = readl(S3C_SCLK_GATE);
-	unsigned bclk;
-
-	if (!(sclk & S3C_SCLK_GATE_MMC(id)))
-		return 0; /* disabled */
-
-	sel = S3C_CLK_SRC_GET_MMC_SEL(id, readl(S3C_CLK_SRC));
-	switch (sel) {
-	case 0:
-		bclk = s3c_get_epllclk();
-		break;
-	case 1:
-		bclk = s3c_get_mpllclk();
-		bclk >>= S3C_CLK_DIV0_GET_MPLL_DIV(readl(S3C_CLK_DIV0));
-		break;
-	case 2:
-		bclk = S3C64XX_CLOCK_REFERENCE;
-		break;
-	case 3:
-		bclk = 27000000;
-		break;
-	}
-
-	div = S3C_CLK_DIV0_GET_MMC(id, readl(S3C_CLK_DIV0)) + 1;
-
-	return bclk / div;
-}
-
-void s3c_set_hsmmc_clk(int id, int src, unsigned div)
-{
-	u32 reg;
-
-	if (!div)
-		div = 1;
-
-	writel(readl(S3C_SCLK_GATE) & ~S3C_SCLK_GATE_MMC(id), S3C_SCLK_GATE);
-
-	/* select the new clock source */
-	reg = readl(S3C_CLK_SRC) & ~S3C_CLK_SRC_SET_MMC_SEL(id, ~0);
-	reg |= S3C_CLK_SRC_SET_MMC_SEL(id, src);
-	writel(reg, S3C_CLK_SRC);
-
-	/* select the new pre-divider */
-	reg = readl(S3C_CLK_DIV0) & ~ S3C_CLK_DIV0_SET_MMC(id, ~0);
-	reg |= S3C_CLK_DIV0_SET_MMC(id, div - 1);
-	writel(reg, S3C_CLK_DIV0);
-
-	/* calling this function implies enabling of the clock */
-	writel(readl(S3C_SCLK_GATE) | S3C_SCLK_GATE_MMC(id), S3C_SCLK_GATE);
-}
-
-static int s3c64xx_dump_clocks(void)
-{
-	printf("refclk:  %7d kHz\n", S3C64XX_CLOCK_REFERENCE / 1000);
-	printf("apll:    %7d kHz\n", s3c_get_apllclk() / 1000);
-	printf("mpll:    %7d kHz\n", s3c_get_mpllclk() / 1000);
-	printf("epll:    %7d kHz\n", s3c_get_epllclk() / 1000);
-	printf("CPU:     %7d kHz\n", s3c_get_fclk() / 1000);
-	printf("hclkx2:  %7d kHz\n", s3c_get_hclkx2() / 1000);
-	printf("hclk:    %7d kHz\n", s3c_get_hclk() / 1000);
-	printf("pclk:    %7d kHz\n", s3c_get_pclk() / 1000);
-	return 0;
-}
-
-late_initcall(s3c64xx_dump_clocks);
diff --git a/arch/arm/mach-samsung/clocks-s5pcxx.c b/arch/arm/mach-samsung/clocks-s5pcxx.c
deleted file mode 100644
index 4a1574bd89..0000000000
--- a/arch/arm/mach-samsung/clocks-s5pcxx.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- * Copyright (C) 2012 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-clocks.h>
-
-static inline uint32_t clkdiv(uint32_t clk, unsigned bit, unsigned mask)
-{
-	uint32_t ratio = (readl(S5P_CLK_DIV0) >> bit) & mask;
-	return clk / (ratio + 1);
-}
-
-uint32_t s3c_get_mpllclk(void)
-{
-	uint32_t m, p, s;
-	uint32_t reg = readl(S5P_xPLL_CON + S5P_MPLL);
-	m = (reg >> 16) & 0x3ff;
-	p = (reg >> 8) & 0x3f;
-	s = (reg >> 0) & 0x7;
-	return m * ((S5PCXX_CLOCK_REFERENCE) / (p << s));
-}
-
-static uint32_t s3c_get_apllclk(void)
-{
-	uint32_t m, p, s;
-	uint32_t reg = readl(S5P_xPLL_CON + S5P_APLL);
-	m = (reg >> 16) & 0x3ff;
-	p = (reg >> 8) & 0x3f;
-	s = (reg >> 0) & 0x7;
-	s -= 1;
-	return m * ((S5PCXX_CLOCK_REFERENCE) / (p << s));
-}
-
-static uint32_t s5p_get_a2mclk(void)
-{
-	return clkdiv(s3c_get_apllclk(), 4, 0x7);
-}
-
-static uint32_t s5p_get_moutpsysclk(void)
-{
-	if (readl(S5P_CLK_SRC0) & (1 << 24)) /* MUX_PSYS */
-		return s5p_get_a2mclk();
-        else
-		return s3c_get_mpllclk();
-}
-
-uint32_t s3c_get_hclk(void)
-{
-	return clkdiv(s5p_get_moutpsysclk(), 24, 0xf);
-}
-
-uint32_t s3c_get_pclk(void)
-{
-	return clkdiv(s3c_get_hclk(), 28, 0x7);
-}
-
-/* we are using the internal 'uclk1' as the UART source */
-static unsigned s3c_get_uart_clk_uclk1(void)
-{
-	unsigned clk = s3c_get_mpllclk();	/* TODO check for EPLL */
-	unsigned uartpdiv = ((readl(S5P_CLK_DIV4) >> 16) & 0x3) + 1; /* TODO this is UART0 only */
-	return clk / uartpdiv;
-}
-
-unsigned s3c_get_uart_clk(unsigned src) {
-	return (src & 1) ? s3c_get_uart_clk_uclk1() : s3c_get_pclk();
-}
-
-static int s5pcxx_dump_clocks(void)
-{
-	printf("refclk:  %7d kHz\n", S5PCXX_CLOCK_REFERENCE / 1000);
-	printf("apll:    %7d kHz\n", s3c_get_apllclk() / 1000);
-	printf("mpll:    %7d kHz\n", s3c_get_mpllclk() / 1000);
-/*	printf("CPU:     %7d kHz\n", s3c_get_cpuclk() / 1000); */
-	printf("hclk:    %7d kHz\n", s3c_get_hclk() / 1000);
-	printf("pclk:    %7d kHz\n", s3c_get_pclk() / 1000);
-	return 0;
-}
-
-late_initcall(s5pcxx_dump_clocks);
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
deleted file mode 100644
index ed3d30d995..0000000000
--- a/arch/arm/mach-samsung/generic.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-/**
- * @file
- * @brief Basic clock, sdram and timer handling for S3C24xx CPUs
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <restart.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-
-#define S3C_WTCON (S3C_WATCHDOG_BASE)
-#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
-#define S3C_WTCNT (S3C_WATCHDOG_BASE + 0x08)
-
-static void __noreturn samsung_restart_soc(struct restart_handler *rst)
-{
-	/* Disable watchdog */
-	writew(0x0000, S3C_WTCON);
-
-	/* Initialize watchdog timer count register */
-	writew(0x0001, S3C_WTCNT);
-
-	/* Enable watchdog timer; assert reset at timer timeout */
-	writew(0x0021, S3C_WTCON);
-
-	/* loop forever and wait for reset to happen */
-	hang();
-}
-
-static int restart_register_feature(void)
-{
-	restart_handler_register_fn("soc-wdt", samsung_restart_soc);
-
-	return 0;
-}
-coredevice_initcall(restart_register_feature);
diff --git a/arch/arm/mach-samsung/gpio-s3c24x0.c b/arch/arm/mach-samsung/gpio-s3c24x0.c
deleted file mode 100644
index 58ca284eab..0000000000
--- a/arch/arm/mach-samsung/gpio-s3c24x0.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <errno.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <gpio.h>
-#include <mach/s3c24xx-gpio.h>
-#include <mach/iomux.h>
-
-static const unsigned char group_offset[] =
-{
-	0x00,	/* GPA */
-	0x10,	/* GPB */
-	0x20,	/* GPC */
-	0x30,	/* GPD */
-	0x40,	/* GPE */
-	0x50,	/* GPF */
-	0x60,	/* GPG */
-	0x70,	/* GPH */
-#ifdef CONFIG_CPU_S3C2440
-	0xd0,	/* GPJ */
-#endif
-};
-
-void gpio_set_value(unsigned gpio, int value)
-{
-	unsigned group = gpio >> 5;
-	unsigned bit = gpio % 32;
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	reg = readl(S3C_GPADAT + offset);
-	reg &= ~(1 << bit);
-	reg |= (!!value) << bit;
-	writel(reg, S3C_GPADAT + offset);
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	unsigned group = gpio >> 5;
-	unsigned bit = gpio % 32;
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	reg = readl(S3C_GPACON + offset);
-	reg &= ~(0x3 << (bit << 1));
-	writel(reg, S3C_GPACON + offset);
-
-	return 0;
-}
-
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	unsigned group = gpio >> 5;
-	unsigned bit = gpio % 32;
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	/* value */
-	gpio_set_value(gpio,value);
-	/* direction */
-	if (group == 0) {	/* GPA is special */
-		reg = readl(S3C_GPACON);
-		reg &= ~(1 << bit);
-		writel(reg, S3C_GPACON);
-	} else {
-		reg = readl(S3C_GPACON + offset);
-		reg &= ~(0x3 << (bit << 1));
-		reg |= 0x1 << (bit << 1);
-		writel(reg, S3C_GPACON + offset);
-	}
-
-	return 0;
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	unsigned group = gpio >> 5;
-	unsigned bit = gpio % 32;
-	unsigned offset;
-	uint32_t reg;
-
-	if (group == 0)	/* GPA is special: no input mode available */
-		return -ENODEV;
-
-	offset = group_offset[group];
-
-	/* value */
-	reg = readl(S3C_GPADAT + offset);
-
-	return !!(reg & (1 << bit));
-}
-
-void s3c_gpio_mode(unsigned gpio_mode)
-{
-	unsigned group, func, bit, offset, gpio;
-	uint32_t reg;
-
-	group = GET_GROUP(gpio_mode);
-	func = GET_FUNC(gpio_mode);
-	bit = GET_BIT(gpio_mode);
-	gpio = GET_GPIO_NO(gpio_mode);
-
-	if (group == 0) {
-		/* GPA is special */
-		switch (func) {
-		case 0:		/* GPIO input */
-			pr_debug("Cannot set GPA pin to GPIO input\n");
-			break;
-		case 1:		/* GPIO output */
-			gpio_direction_output(bit, GET_GPIOVAL(gpio_mode));
-			break;
-		default:
-			reg = readl(S3C_GPACON);
-			reg |= 1 << bit;
-			writel(reg, S3C_GPACON);
-			break;
-		}
-		return;
-	}
-
-	offset = group_offset[group];
-
-	if (PU_PRESENT(gpio_mode)) {
-		reg = readl(S3C_GPACON + offset + 8);
-		if (GET_PU(gpio_mode))
-			reg |= (1 << bit);	/* set means _disabled_ */
-		else
-			reg &= ~(1 << bit);
-		writel(reg, S3C_GPACON + offset + 8);
-	}
-
-	switch (func) {
-	case 0: /* input */
-		gpio_direction_input(gpio);
-		break;
-	case 1:	/* output */
-		gpio_direction_output(gpio, GET_GPIOVAL(gpio_mode));
-		break;
-	case 2: /* function one */
-	case 3: /* function two */
-		reg = readl(S3C_GPACON + offset);
-		reg &= ~(0x3 << (bit << 1));
-		reg |= func << (bit << 1);
-		writel(reg, S3C_GPACON + offset);
-		break;
-	}
-}
diff --git a/arch/arm/mach-samsung/gpio-s3c64xx.c b/arch/arm/mach-samsung/gpio-s3c64xx.c
deleted file mode 100644
index d70a8716c9..0000000000
--- a/arch/arm/mach-samsung/gpio-s3c64xx.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This code bases partially on code from the Linux kernel:
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <io.h>
-#include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/s3c-iomap.h>
-
-#define S3C_GPACON (S3C_GPIO_BASE)
-#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
-#define S3C_GPAPUD (S3C_GPIO_BASE + 0x08)
-
-static const unsigned short group_offset[] = {
-	0x000,	/* GPA */ /* 8 pins, 4 bit each */
-	0x020,	/* GPB */ /* 7 pins, 4 bit each */
-	0x040,	/* GPC */ /* 8 pins, 4 bit each */
-	0x060,	/* GPD */ /* 5 pins, 4 bit each */
-	0x080,	/* GPE */ /* 5 pins, 4 bit each */
-	0x0a0,	/* GPF */ /* 16 pins, 2 bit each */
-	0x0c0,	/* GPG */ /* 7 pins, 4 bit each */
-	0x0e0,	/* GPH */ /* two registers, 8 + 2 pins, 4 bit each */
-	0x100,	/* GPI */ /* 16 pins, 2 bit each */
-	0x120,	/* GPJ */ /* 12 pins, 2 bit each */
-	0x800,	/* GPK */ /* two registers, 8 + 8 pins, 4 bit each */
-	0x810,	/* GPL */ /* two registers, 8 + 8 pins, 4 bit each */
-	0x820,	/* GPM */ /* 6 pins, 4 bit each */
-	0x830,	/* GPN */ /* 16 pins, 2 bit each */
-	0x140,	/* GPO */ /* 16 pins, 2 bit each */
-	0x160,	/* GPP */ /* 15 pins, 2 bit each */
-	0x180,	/* GPQ */ /* 9 pins, 2 bit each */
-};
-
-void gpio_set_value(unsigned gpio, int value)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	switch (group) {
-	case 7:		/* GPH */
-	case 10:	/* GPK */
-	case 11:	/* GPL */
-		offset += 4;
-		break;
-	}
-
-	reg = readl(S3C_GPADAT + offset);
-	reg &= ~(1 << bit);
-	reg |= (!!value) << bit;
-	writel(reg, S3C_GPADAT + offset);
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset;
-	uint32_t reg;
-
-	offset = group_offset[group];
-
-	switch (group) {
-	case 7:		/* GPH */
-	case 10:	/* GPK */
-	case 11:	/* GPL */
-		offset += 4;
-		break;
-	}
-
-	/* value */
-	reg = readl(S3C_GPADAT + offset);
-
-	return !!(reg & (1 << bit));
-}
-
-static void gpio_direction_input_4b(unsigned offset, unsigned bit)
-{
-	uint32_t reg;
-
-	if (bit > 31) {
-		offset += 4;
-		bit -= 32;
-	}
-
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	writel(reg, S3C_GPACON + offset); /* b0000 means 'GPIO input' */
-}
-
-static void gpio_direction_input_2b(unsigned offset, unsigned bit)
-{
-	uint32_t reg;
-
-	reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
-	writel(reg, S3C_GPACON + offset); /* b00 means 'GPIO input' */
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset;
-
-	offset = group_offset[group];
-
-	switch (group) {
-	case 5:		/* GPF */
-	case 8:		/* GPI */
-	case 9:		/* GPJ */
-	case 13:	/* GPN */
-	case 14:	/* GPO */
-	case 15:	/* GPP */
-	case 16:	/* GPQ */
-		gpio_direction_input_2b(offset, bit << 1);
-		break;
-	default:
-		gpio_direction_input_4b(offset, bit << 2);
-	}
-
-	return 0;
-}
-
-static void gpio_direction_output_4b(unsigned offset, unsigned bit)
-{
-	uint32_t reg;
-
-	if (bit > 31) {
-		offset += 4;
-		bit -= 32;
-	}
-
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	reg |= 0x1 << bit;
-	writel(reg, S3C_GPACON + offset); /* b0001 means 'GPIO output' */
-}
-
-static void gpio_direction_output_2b(unsigned offset, unsigned bit)
-{
-	uint32_t reg;
-
-	/* direction */
-	reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
-	reg |= 0x1 << bit;
-	writel(reg, S3C_GPACON + offset);
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset;
-
-	gpio_set_value(gpio, value);
-
-	offset = group_offset[group];
-	switch (group) {
-	case 5:		/* GPF */
-	case 8:		/* GPI */
-	case 9:		/* GPJ */
-	case 13:	/* GPN */
-	case 14:	/* GPO */
-	case 15:	/* GPP */
-	case 16:	/* GPQ */
-		gpio_direction_output_2b(offset, bit << 1);
-		break;
-	default:
-		gpio_direction_output_4b(offset, bit << 2);
-	}
-
-	return 0;
-}
-
-/* one register, 2 bits per function -> GPF, GPI, GPJ, GPN, GPO, GPP, GPQ */
-static void s3c_d2pins(unsigned offset, unsigned pin_mode)
-{
-	unsigned bit = GET_BIT(pin_mode);
-	unsigned func = GET_FUNC(pin_mode);
-	unsigned reg;
-
-	if (PUD_PRESENT(pin_mode)) {
-		reg = readl(S3C_GPAPUD + offset);
-		reg &= ~(PUD_MASK << bit);
-		reg |= GET_PUD(pin_mode) << bit;
-		writel(reg, S3C_GPAPUD + offset);
-	}
-
-	/* in the case of pin's function is GPIO it also sets up the direction */
-	reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
-	writel(reg | (func << bit), S3C_GPACON + offset);
-
-	if (func == 1) { /* output? if yes, also set the initial value */
-		reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 1));
-		reg |= GET_GPIOVAL(pin_mode) << (bit >> 1);
-		writel(reg, S3C_GPADAT + offset);
-	}
-}
-
-/* one register, 4 bits per function -> GPA, GPB, GPC, GPD, GPE, GPG, GPM */
-static void s3c_d4pins(unsigned offset, unsigned pin_mode)
-{
-	unsigned bit = GET_BIT(pin_mode);
-	unsigned func = GET_FUNC(pin_mode);
-	unsigned reg;
-
-	if (PUD_PRESENT(pin_mode)) {
-		reg = readl(S3C_GPAPUD + offset);
-		reg &= ~(PUD_MASK << (bit >> 1));
-		reg |= GET_PUD(pin_mode) << (bit >> 1);
-		writel(reg, S3C_GPAPUD + offset);
-	}
-
-	/* in the case of pin's function is GPIO it also sets up the direction */
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	writel(reg | (func << bit), S3C_GPACON + offset);
-
-	if (func == 1) { /* output? if yes, also set the initial value */
-		reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 2));
-		reg |= GET_GPIOVAL(pin_mode) << (bit >> 2);
-		writel(reg, S3C_GPADAT + offset);
-	}
-}
-
-/* two registers, 4 bits per pin -> GPH, GPK, GPL */
-static void s3c_d42pins(unsigned offset, unsigned pin_mode)
-{
-	unsigned bit = GET_BIT(pin_mode);
-	unsigned func = GET_FUNC(pin_mode);
-	uint32_t reg;
-	unsigned reg_offs = 0;
-
-	if (PUD_PRESENT(pin_mode)) {
-		reg = readl(S3C_GPAPUD + 4 + offset);
-		reg &= ~(PUD_MASK << (bit >> 1));
-		reg |= GET_PUD(pin_mode) << (bit >> 1);
-		writel(reg, S3C_GPACON + 4 + offset);
-	}
-
-	if (bit > 31) {
-		reg_offs = 4;
-		bit -= 32;
-	}
-
-	/* in the case of pin's function is GPIO it also sets up the direction */
-	reg = readl(S3C_GPACON + offset + reg_offs) & ~(0xf << bit);
-	writel(reg | (func << bit), S3C_GPACON + offset + reg_offs);
-
-	if (func == 1) { /* output? if yes, also set the initial value */
-		reg = readl(S3C_GPADAT + 4 + offset) & ~(1 << (bit >> 2));
-		reg |= GET_GPIOVAL(pin_mode) << (bit >> 2);
-		writel(reg, S3C_GPADAT + 4 + offset);
-	}
-}
-
-/* 'gpio_mode' must be one of the 'GP?_*' macros */
-void s3c_gpio_mode(unsigned gpio_mode)
-{
-	unsigned group, offset;
-
-	group = GET_GROUP(gpio_mode);
-	offset = group_offset[group];
-
-	switch (group) {
-	case 5:		/* GPF */
-	case 8:		/* GPI */
-	case 9:		/* GPJ */
-	case 13:	/* GPN */
-	case 14:	/* GPO */
-	case 15:	/* GPP */
-	case 16:	/* GPQ */
-		s3c_d2pins(offset, gpio_mode);
-		break;
-	case 7:		/* GPH */
-	case 10:	/* GPK */
-	case 11:	/* GPL */
-		s3c_d42pins(offset, gpio_mode);
-		break;
-	default:
-		s3c_d4pins(offset, gpio_mode);
-	}
-}
diff --git a/arch/arm/mach-samsung/gpio-s5pcxx.c b/arch/arm/mach-samsung/gpio-s5pcxx.c
deleted file mode 100644
index 1a422f1746..0000000000
--- a/arch/arm/mach-samsung/gpio-s5pcxx.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- * Copyright (C) 2012 Juergen Beisert, Pengutronix
- *
- * This codes bases partially on code from the Linux kernel:
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <io.h>
-#include <gpio.h>
-#include <mach/iomux.h>
-#include <mach/s3c-iomap.h>
-
-#define S3C_GPACON (S3C_GPIO_BASE)
-#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
-#define S3C_GPAPUD (S3C_GPIO_BASE + 0x08)
-
-static inline unsigned group_offset(unsigned group)
-{
-    return group * 0x20;
-}
-
-void gpio_set_value(unsigned gpio, int value)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset = group_offset(group);
-	uint32_t reg;
-
-	reg = readl(S3C_GPADAT + offset);
-	reg &= ~(1 << bit);
-	reg |= (!!value) << bit;
-	writel(reg, S3C_GPADAT + offset);
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset = group_offset(group);
-	uint32_t reg;
-
-	/* value */
-	reg = readl(S3C_GPADAT + offset);
-
-	return !!(reg & (1 << bit));
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset = group_offset(group);
-	uint32_t reg;
-
-	bit <<= 2;
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	writel(reg, S3C_GPACON + offset);
-
-	return 0;
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	unsigned group = GET_GROUP(gpio);
-	unsigned bit = GET_BIT(gpio);
-	unsigned offset = group_offset(group);
-	uint32_t reg;
-
-	gpio_set_value(gpio, value);
-
-	bit <<= 2;
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	reg |= 0x1 << bit;
-	writel(reg, S3C_GPACON + offset);
-
-	return 0;
-}
-
-
-/* 'gpio_mode' must be one of the 'GP?_*' macros */
-void s3c_gpio_mode(unsigned gpio_mode)
-{
-	unsigned group = GET_GROUP(gpio_mode);
-	unsigned bit = GET_BIT(gpio_mode);
-	unsigned func = GET_FUNC(gpio_mode);
-	unsigned offset = group_offset(group);
-	unsigned reg;
-
-	bit <<= 1;
-	if (PUD_PRESENT(gpio_mode)) {
-		reg = readl(S3C_GPAPUD + offset);
-		reg &= ~(PUD_MASK << bit);
-		reg |= GET_PUD(gpio_mode) << bit;
-		writel(reg, S3C_GPAPUD + offset);
-	}
-
-	bit <<= 1;
-	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
-	writel(reg | (func << bit), S3C_GPACON + offset);
-
-	if (func == 1) { /* output? if yes, also set the initial value */
-		reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 2));
-		reg |= GET_GPIOVAL(gpio_mode) << (bit >> 2);
-		writel(reg, S3C_GPADAT + offset);
-	}
-
-}
diff --git a/arch/arm/mach-samsung/include/mach/bbu.h b/arch/arm/mach-samsung/include/mach/bbu.h
deleted file mode 100644
index 7ce7052bcf..0000000000
--- a/arch/arm/mach-samsung/include/mach/bbu.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __MACH_BBU_H
-#define __MACH_BBU_H
-
-#include <bbu.h>
-#include <errno.h>
-
-#ifdef CONFIG_BAREBOX_UPDATE_NAND_S3C24XX
-int s3c24x0_bbu_nand_register_handler(void);
-#else
-static inline int s3c24x0_bbu_nand_register_handler(void)
-{
-	return -ENOSYS;
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
deleted file mode 100644
index 51fd9a1825..0000000000
--- a/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef INCLUDE_MACH_DEVICES_S3C24XX_H
-# define INCLUDE_MACH_DEVICES_S3C24XX_H
-
-#include <driver.h>
-#include <mach/s3c24xx-iomap.h>
-#include <mach/s3c24xx-nand.h>
-#include <mach/s3c-mci.h>
-#include <mach/s3c24xx-fb.h>
-
-static inline void s3c24xx_add_nand(struct s3c24x0_nand_platform_data *d)
-{
-	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL,
-				S3C24X0_NAND_BASE, 0x80, IORESOURCE_MEM, d);
-}
-
-static inline void s3c24xx_add_mci(struct s3c_mci_platform_data *d)
-{
-	add_generic_device("s3c_mci", DEVICE_ID_DYNAMIC, NULL,
-				S3C2410_SDI_BASE, 0x80, IORESOURCE_MEM, d);
-}
-
-static inline void s3c24xx_add_fb(struct s3c_fb_platform_data *d)
-{
-	add_generic_device("s3c_fb", DEVICE_ID_DYNAMIC, NULL,
-				S3C2410_LCD_BASE, 0x80, IORESOURCE_MEM, d);
-}
-
-static inline void s3c24xx_add_ohci(void)
-{
-	add_generic_device("ohci", DEVICE_ID_DYNAMIC, NULL,
-			S3C2410_USB_HOST_BASE, 0x100, IORESOURCE_MEM, NULL);
-}
-
-static inline void s3c24xx_add_uart1(void)
-{
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
-			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
-}
-
-#endif /* INCLUDE_MACH_DEVICES_S3C24XX_H */
diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h b/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
deleted file mode 100644
index bcbee972e6..0000000000
--- a/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef INCLUDE_MACH_DEVICES_S3C64XX_H
-# define INCLUDE_MACH_DEVICES_S3C64XX_H
-
-#include <driver.h>
-#include <mach/s3c64xx-iomap.h>
-
-static inline void s3c64xx_add_uart1(void)
-{
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
-			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
-}
-
-static inline void s3c64xx_add_uart2(void)
-{
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART2_BASE,
-			S3C_UART2_SIZE, IORESOURCE_MEM, NULL);
-}
-
-static inline void s3c64xx_add_uart3(void)
-{
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART3_BASE,
-			S3C_UART3_SIZE, IORESOURCE_MEM, NULL);
-}
-
-#endif /* INCLUDE_MACH_DEVICES_S3C64XX_H */
diff --git a/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h b/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
deleted file mode 100644
index b042505f25..0000000000
--- a/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_IOMUX_S3C24x0_H
-#define __MACH_IOMUX_S3C24x0_H
-
-/* 3322222222221111111111
- * 10987654321098765432109876543210
- *                            ^^^^^_ Bit offset
- *                        ^^^^______ Group Number
- *                    ^^____________ Function
- *                   ^______________ initial GPIO out value
- *                  ^_______________ Pull up feature present
- *                 ^________________ initial pull up setting
- */
-
-
-#define PIN(group,bit) (group * 32 + bit)
-#define FUNC(x) (((x) & 0x3) << 11)
-#define GET_FUNC(x) (((x) >> 11) & 0x3)
-#define GET_GROUP(x) (((x) >> 5) & 0xf)
-#define GET_BIT(x) (((x) & 0x1ff) % 32)
-#define GET_GPIOVAL(x) (((x) >> 13) & 0x1)
-#define GET_GPIO_NO(x) ((x & 0x1ff))
-#define GPIO_OUT FUNC(1)
-#define GPIO_IN FUNC(0)
-#define GPIO_VAL(x) ((!!(x)) << 13)
-#define PU (1 << 14)
-#define PU_PRESENT(x) (!!((x) & (1 << 14)))
-#define ENABLE_PU (0 << 15)
-#define DISABLE_PU (1 << 15)
-#define GET_PU(x) (!!((x) & DISABLE_PU))
-
-/*
- * Group 0: GPIO 0...31
- * Used GPIO: 0...22
- * These pins can also act as GPIO outputs
- */
-#define GPA0_ADDR0		(PIN(0,0) | FUNC(2))
-#define GPA0_ADDR0_GPIO		(PIN(0,0) | FUNC(0))
-#define GPA1_ADDR16		(PIN(0,1) | FUNC(2))
-#define GPA1_ADDR16_GPIO	(PIN(0,1) | FUNC(0))
-#define GPA2_ADDR17		(PIN(0,2) | FUNC(2))
-#define GPA2_ADDR17_GPIO	(PIN(0,2) | FUNC(0))
-#define GPA3_ADDR18		(PIN(0,3) | FUNC(2))
-#define GPA3_ADDR18_GPIO	(PIN(0,3) | FUNC(0))
-#define GPA4_ADDR19		(PIN(0,4) | FUNC(2))
-#define GPA4_ADDR19_GPIO	(PIN(0,4) | FUNC(0))
-#define GPA5_ADDR20		(PIN(0,5) | FUNC(2))
-#define GPA5_ADDR20_GPIO	(PIN(0,5) | FUNC(0))
-#define GPA6_ADDR21		(PIN(0,6) | FUNC(2))
-#define GPA6_ADDR21_GPIO	(PIN(0,6) | FUNC(0))
-#define GPA7_ADDR22		(PIN(0,7) | FUNC(2))
-#define GPA7_ADDR22_GPIO	(PIN(0,7) | FUNC(0))
-#define GPA8_ADDR23		(PIN(0,8) | FUNC(2))
-#define GPA8_ADDR23_GPIO	(PIN(0,8) | FUNC(0))
-#define GPA9_ADDR24		(PIN(0,9) | FUNC(2))
-#define GPA9_ADDR24_GPIO	(PIN(0,9) | FUNC(0))
-#define GPA10_ADDR25		(PIN(0,10) | FUNC(2))
-#define GPA10_ADDR25_GPIO	(PIN(0,10) | FUNC(0))
-#define GPA11_ADDR26		(PIN(0,11) | FUNC(2))
-#define GPA11_ADDR26_GPIO	(PIN(0,11) | FUNC(0))
-#define GPA12_NGCS1		(PIN(0,12) | FUNC(2))
-#define GPA12_NGCS1_GPIO	(PIN(0,12) | FUNC(0))
-#define GPA13_NGCS2		(PIN(0,13) | FUNC(2))
-#define GPA13_NGCS2_GPIO	(PIN(0,13) | FUNC(0))
-#define GPA14_NGCS3		(PIN(0,14) | FUNC(2))
-#define GPA14_NGCS3_GPIO	(PIN(0,14) | FUNC(0))
-#define GPA15_NGCS4		(PIN(0,15) | FUNC(2))
-#define GPA15_NGCS4_GPIO	(PIN(0,15) | FUNC(0))
-#define GPA16_NGCS5		(PIN(0,16) | FUNC(2))
-#define GPA16_NGCS5_GPIO	(PIN(0,16) | FUNC(0))
-#define GPA17_CLE		(PIN(0,17) | FUNC(2))
-#define GPA17_CLE_GPIO		(PIN(0,17) | FUNC(0))
-#define GPA18_ALE		(PIN(0,18) | FUNC(2))
-#define GPA18_ALE_GPIO		(PIN(0,18) | FUNC(0))
-#define GPA19_NFWE		(PIN(0,19) | FUNC(2))
-#define GPA19_NFWE_GPIO		(PIN(0,19) | FUNC(0))
-#define GPA20_NFRE		(PIN(0,20) | FUNC(2))
-#define GPA20_NFRE_GPIO		(PIN(0,20) | FUNC(0))
-#define GPA21_NRSTOUT		(PIN(0,21) | FUNC(2))
-#define GPA21_NRSTOUT_GPIO	(PIN(0,21) | FUNC(0))
-#define GPA22_NFCE		(PIN(0,22) | FUNC(2))
-#define GPA22_NFCE_GPIO		(PIN(0,22) | FUNC(0))
-
-/*
- * Group 1: GPIO 32...63
- * Used GPIO: 0...10
- * these pins can also act as GPIO inputs/outputs
- */
-#define GPB0_TOUT0	(PIN(1,0) | FUNC(2) | PU)
-#define GPB0_GPIO	(PIN(1,0) | FUNC(0) | PU)
-#define GPB1_TOUT1	(PIN(1,1) | FUNC(2) | PU)
-#define GPB1_GPIO	(PIN(1,1) | FUNC(0) | PU)
-#define GPB2_TOUT2	(PIN(1,2) | FUNC(2) | PU)
-#define GPB2_GPIO	(PIN(1,2) | FUNC(0) | PU)
-#define GPB3_TOUT3	(PIN(1,3) | FUNC(2) | PU)
-#define GPB3_GPIO	(PIN(1,3) | FUNC(0) | PU)
-#define GPB4_TCLK0	(PIN(1,4) | FUNC(2) | PU)
-#define GPB4_GPIO	(PIN(1,4) | FUNC(0) | PU)
-#define GPB5_NXBACK	(PIN(1,5) | FUNC(2) | PU)
-#define GPB5_GPIO	(PIN(1,5) | FUNC(0) | PU)
-#define GPB6_NXBREQ	(PIN(1,6) | FUNC(2) | PU)
-#define GPB6_GPIO	(PIN(1,6) | FUNC(0) | PU)
-#define GPB7_NXDACK1	(PIN(1,7) | FUNC(2) | PU)
-#define GPB7_GPIO	(PIN(1,7) | FUNC(0) | PU)
-#define GPB8_NXDREQ1	(PIN(1,8) | FUNC(2) | PU)
-#define GPB8_GPIO	(PIN(1,8) | FUNC(0) | PU)
-#define GPB9_NXDACK0	(PIN(1,9) | FUNC(2) | PU)
-#define GPB9_GPIO	(PIN(1,9) | FUNC(0) | PU)
-#define GPB10_NXDREQ0	(PIN(1,10) | FUNC(2) | PU)
-#define GPB10_GPIO	(PIN(1,10) | FUNC(0) | PU)
-
-/*
- * Group 1: GPIO 64...95
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPC0_LEND	(PIN(2,0) | FUNC(2) | PU)
-#define GPC0_GPIO	(PIN(2,0) | FUNC(0) | PU)
-#define GPC1_VCLK	(PIN(2,1) | FUNC(2) | PU)
-#define GPC1_GPIO	(PIN(2,1) | FUNC(0) | PU)
-#define GPC2_VLINE	(PIN(2,2) | FUNC(2) | PU)
-#define GPC2_GPIO	(PIN(2,2) | FUNC(0) | PU)
-#define GPC3_VFRAME	(PIN(2,3) | FUNC(2) | PU)
-#define GPC3_GPIO	(PIN(2,3) | FUNC(0) | PU)
-#define GPC4_VM		(PIN(2,4) | FUNC(2) | PU)
-#define GPC4_GPIO	(PIN(2,4) | FUNC(0) | PU)
-#define GPC5_LPCOE	(PIN(2,5) | FUNC(2) | PU)
-#define GPC5_GPIO	(PIN(2,5) | FUNC(0) | PU)
-#define GPC6_LPCREV	(PIN(2,6) | FUNC(2) | PU)
-#define GPC6_GPIO	(PIN(2,6) | FUNC(0) | PU)
-#define GPC7_LPCREVB	(PIN(2,7) | FUNC(2) | PU)
-#define GPC7_GPIO	(PIN(2,7) | FUNC(0) | PU)
-#define GPC8_VD0	(PIN(2,8) | FUNC(2) | PU)
-#define GPC8_GPIO	(PIN(2,8) | FUNC(0) | PU)
-#define GPC9_VD1	(PIN(2,9) | FUNC(2) | PU)
-#define GPC9_GPIO	(PIN(2,9) | FUNC(0) | PU)
-#define GPC10_VD2	(PIN(2,10) | FUNC(2) | PU)
-#define GPC10_GPIO	(PIN(2,10) | FUNC(0) | PU)
-#define GPC11_VD3	(PIN(2,11) | FUNC(2) | PU)
-#define GPC11_GPIO	(PIN(2,11) | FUNC(0) | PU)
-#define GPC12_VD4	(PIN(2,12) | FUNC(2) | PU)
-#define GPC12_GPIO	(PIN(2,12) | FUNC(0) | PU)
-#define GPC13_VD5	(PIN(2,13) | FUNC(2) | PU)
-#define GPC13_GPIO	(PIN(2,13) | FUNC(0) | PU)
-#define GPC14_VD6	(PIN(2,14) | FUNC(2) | PU)
-#define GPC14_GPIO	(PIN(2,14) | FUNC(0) | PU)
-#define GPC15_VD7	(PIN(2,15) | FUNC(2) | PU)
-#define GPC15_GPIO	(PIN(2,15) | FUNC(0) | PU)
-
-/*
- * Group 1: GPIO 96...127
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPD0_VD8	(PIN(3,0) | FUNC(2) | PU)
-#define GPD0_GPIO	(PIN(3,0) | FUNC(0) | PU)
-#define GPD1_VD9	(PIN(3,1) | FUNC(2) | PU)
-#define GPD1_GPIO	(PIN(3,1) | FUNC(0) | PU)
-#define GPD2_VD10	(PIN(3,2) | FUNC(2) | PU)
-#define GPD2_GPIO	(PIN(3,2) | FUNC(0) | PU)
-#define GPD3_VD11	(PIN(3,3) | FUNC(2) | PU)
-#define GPD3_GPIO	(PIN(3,3) | FUNC(0) | PU)
-#define GPD4_VD12	(PIN(3,4) | FUNC(2) | PU)
-#define GPD4_GPIO	(PIN(3,4) | FUNC(0) | PU)
-#define GPD5_VD13	(PIN(3,5) | FUNC(2) | PU)
-#define GPD5_GPIO	(PIN(3,5) | FUNC(0) | PU)
-#define GPD6_VD14	(PIN(3,6) | FUNC(2) | PU)
-#define GPD6_GPIO	(PIN(3,6) | FUNC(0) | PU)
-#define GPD7_VD15	(PIN(3,7) | FUNC(2) | PU)
-#define GPD7_GPIO	(PIN(3,7) | FUNC(0) | PU)
-#define GPD8_VD16	(PIN(3,8) | FUNC(2) | PU)
-#define GPD8_GPIO	(PIN(3,8) | FUNC(0) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPD8_SPIMISO1	(PIN(3,8) | FUNC(3) | PU)
-#endif
-#define GPD9_VD17	(PIN(3,9) | FUNC(2) | PU)
-#define GPD9_GPIO	(PIN(3,9) | FUNC(0) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPD9_SPIMOSI1	(PIN(3,9) | FUNC(3) | PU)
-#endif
-#define GPD10_VD18	(PIN(3,10) | FUNC(2) | PU)
-#define GPD10_GPIO	(PIN(3,10) | FUNC(0) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPD10_SPICLK	(PIN(3,10) | FUNC(3) | PU)
-#endif
-#define GPD11_VD19	(PIN(3,11) | FUNC(2) | PU)
-#define GPD11_GPIO	(PIN(3,11) | FUNC(0) | PU)
-#define GPD12_VD20	(PIN(3,12) | FUNC(2) | PU)
-#define GPD12_GPIO	(PIN(3,12) | FUNC(0) | PU)
-#define GPD13_VD21	(PIN(3,13) | FUNC(2) | PU)
-#define GPD13_GPIO	(PIN(3,13) | FUNC(0) | PU)
-#define GPD14_VD22	(PIN(3,14) | FUNC(2) | PU)
-#define GPD14_GPIO	(PIN(3,14) | FUNC(0) | PU)
-#define GPD14_NSS1	(PIN(3,14) | FUNC(3) | PU)
-#define GPD15_VD23	(PIN(3,15) | FUNC(2) | PU)
-#define GPD15_GPIO	(PIN(3,15) | FUNC(0) | PU)
-#define GPD15_NSS0	(PIN(3,15) | FUNC(3) | PU)
-
-/*
- * Group 1: GPIO 128...159
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPE0_I2SLRCK	(PIN(4,0) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE0_AC_SYNC	(PIN(4,0) | FUNC(3) | PU)
-#endif
-#define GPE0_GPIO	(PIN(4,0) | FUNC(0) | PU)
-#define GPE1_I2SSCLK	(PIN(4,1) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE1_AC_BIT_CLK (PIN(4,1) | FUNC(3) | PU)
-#endif
-#define GPE1_GPIO	(PIN(4,1) | FUNC(0) | PU)
-#define GPE2_CDCLK	(PIN(4,2) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE2_AC_NRESET	(PIN(4,2) | FUNC(3) | PU)
-#endif
-#define GPE2_GPIO	(PIN(4,2) | FUNC(0) | PU)
-#define GPE3_I2SDI	(PIN(4,3) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE3_AC_SDATA_IN (PIN(4,3) | FUNC(3) | PU)
-#endif
-#ifdef CONFIG_CPU_S3C2410
-# define GPE_NSS0	(PIN(4,3) | FUNC(3) | PU)
-#endif
-#define GPE3_GPIO	(PIN(4,3) | FUNC(0) | PU)
-#define GPE4_I2SDO	(PIN(4,4) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE4_AC_SDATA_OUT (PIN(4,4) | FUNC(3) | PU)
-#endif
-#ifdef CONFIG_CPU_S3C2440
-# define GPE4_I2SSDI	(PIN(4,4) | FUNC(3) | PU)
-#endif
-#define GPE4_GPIO	(PIN(4,4) | FUNC(0) | PU)
-#define GPE5_SDCLK	(PIN(4,5) | FUNC(2) | PU)
-#define GPE5_GPIO	(PIN(4,5) | FUNC(0) | PU)
-#define GPE6_SDCMD	(PIN(4,6) | FUNC(2) | PU)
-#define GPE6_GPIO	(PIN(4,6) | FUNC(0) | PU)
-#define GPE7_SDDAT0	(PIN(4,7) | FUNC(2) | PU)
-#define GPE7_GPIO	(PIN(4,7) | FUNC(0) | PU)
-#define GPE8_SDDAT1	(PIN(4,8) | FUNC(2) | PU)
-#define GPE8_GPIO	(PIN(4,8) | FUNC(0) | PU)
-#define GPE9_SDDAT2	(PIN(4,9) | FUNC(2) | PU)
-#define GPE9_GPIO	(PIN(4,9) | FUNC(0) | PU)
-#define GPE10_SDDAT3	(PIN(4,10) | FUNC(2) | PU)
-#define GPE10_GPIO	(PIN(4,10) | FUNC(0) | PU)
-#define GPE11_SPIMISO0	(PIN(4,11) | FUNC(2) | PU)
-#define GPE11_GPIO	(PIN(4,11) | FUNC(0) | PU)
-#define GPE12_SPIMOSI0	(PIN(4,12) | FUNC(2) | PU)
-#define GPE12_GPIO	(PIN(4,12) | FUNC(0) | PU)
-#define GPE13_SPICLK0	(PIN(4,13) | FUNC(2) | PU)
-#define GPE13_GPIO	(PIN(4,13) | FUNC(0) | PU)
-#define GPE14_IICSCL	(PIN(4,14) | FUNC(2))	/* no pullup option */
-#define GPE14_GPIO	(PIN(4,14) | FUNC(0))	/* no pullup option */
-#define GPE15_IICSDA	(PIN(4,15) | FUNC(2))	/* no pullup option */
-#define GPE15_GPIO	(PIN(4,15) | FUNC(0))	/* no pullup option */
-
-/*
- * Group 1: GPIO 160...191
- * Used GPIO: 0...7
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPF0_EINT0	(PIN(5,0) | FUNC(2) | PU)
-#define GPF0_GPIO	(PIN(5,0) | FUNC(0) | PU)
-#define GPF1_EINT1	(PIN(5,1) | FUNC(2) | PU)
-#define GPF1_GPIO	(PIN(5,1) | FUNC(0) | PU)
-#define GPF2_EINT2	(PIN(5,2) | FUNC(2) | PU)
-#define GPF2_GPIO	(PIN(5,2) | FUNC(0) | PU)
-#define GPF3_EINT3	(PIN(5,3) | FUNC(2) | PU)
-#define GPF3_GPIO	(PIN(5,3) | FUNC(0) | PU)
-#define GPF4_EINT4	(PIN(5,4) | FUNC(2) | PU)
-#define GPF4_GPIO	(PIN(5,4) | FUNC(0) | PU)
-#define GPF5_EINT5	(PIN(5,5) | FUNC(2) | PU)
-#define GPF5_GPIO	(PIN(5,5) | FUNC(0) | PU)
-#define GPF6_EINT6	(PIN(5,6) | FUNC(2) | PU)
-#define GPF6_GPIO	(PIN(5,6) | FUNC(0) | PU)
-#define GPF7_EINT7	(PIN(5,7) | FUNC(2) | PU)
-#define GPF7_GPIO	(PIN(5,7) | FUNC(0) | PU)
-
-/*
- * Group 1: GPIO 192..223
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPG0_EINT8	(PIN(6,0) | FUNC(2) | PU)
-#define GPG0_GPIO	(PIN(6,0) | FUNC(0) | PU)
-#define GPG1_EINT9	(PIN(6,1) | FUNC(2) | PU)
-#define GPG1_GPIO	(PIN(6,1) | FUNC(0) | PU)
-#define GPG2_EINT10	(PIN(6,2) | FUNC(2) | PU)
-#define GPG2_NSS0	(PIN(6,2) | FUNC(3) | PU)
-#define GPG2_GPIO	(PIN(6,2) | FUNC(0) | PU)
-#define GPG3_EINT11	(PIN(6,3) | FUNC(2) | PU)
-#define GPG3_NSS1	(PIN(6,3) | FUNC(3) | PU)
-#define GPG3_GPIO	(PIN(6,3) | FUNC(0) | PU)
-#define GPG4_EINT12	(PIN(6,4) | FUNC(2) | PU)
-#define GPG4_LCD_PWREN	(PIN(6,4) | FUNC(3) | PU)
-#define GPG4_GPIO	(PIN(6,4) | FUNC(0) | PU)
-#define GPG5_EINT13	(PIN(6,5) | FUNC(2) | PU)
-#define GPG5_SPIMISO1	(PIN(6,5) | FUNC(3) | PU)
-#define GPG5_GPIO	(PIN(6,5) | FUNC(0) | PU)
-#define GPG6_EINT14	(PIN(6,6) | FUNC(2) | PU)
-#define GPG6_SPIMOSI1	(PIN(6,6) | FUNC(3) | PU)
-#define GPG6_GPIO	(PIN(6,6) | FUNC(0) | PU)
-#define GPG7_EINT15	(PIN(6,7) | FUNC(2) | PU)
-#define GPG7_SPICLK1	(PIN(6,7) | FUNC(3) | PU)
-#define GPG7_GPIO	(PIN(6,7) | FUNC(0) | PU)
-#define GPG8_EINT16	(PIN(6,8) | FUNC(2) | PU)
-#define GPG8_GPIO	(PIN(6,8) | FUNC(0) | PU)
-#define GPG9_EINT17	(PIN(6,9) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPG9_NRTS1	(PIN(6,9) | FUNC(3) | PU)
-#endif
-#define GPG9_GPIO	(PIN(6,9) | FUNC(0) | PU)
-#define GPG10_EINT18	(PIN(6,10) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPG10_NCTS1	(PIN(6,10) | FUNC(3) | PU)
-#endif
-#define GPG10_GPIO	(PIN(6,10) | FUNC(0) | PU)
-#define GPG11_EINT19	(PIN(6,11) | FUNC(2) | PU)
-#define GPG11_TCLK	(PIN(6,11) | FUNC(3) | PU)
-#define GPG11_GPIO	(PIN(6,11) | FUNC(0) | PU)
-#define GPG12_EINT20	(PIN(6,12) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG12_XMON	(PIN(6,12) | FUNC(3) | PU)
-#endif
-#define GPG12_GPIO	(PIN(6,12) | FUNC(0) | PU)
-#define GPG13_EINT21	(PIN(6,13) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG13_NXPON	(PIN(6,13) | FUNC(3) | PU)
-#endif
-#define GPG13_GPIO	(PIN(6,13) | FUNC(0) | PU)	/* must be input in NAND boot mode */
-#define GPG14_EINT22	(PIN(6,14) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG14_YMON	(PIN(6,14) | FUNC(3) | PU)
-#endif
-#define GPG14_GPIO	(PIN(6,14) | FUNC(0) | PU)	/* must be input in NAND boot mode */
-#define GPG15_EINT23	(PIN(6,15) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG15_YPON	(PIN(6,15) | FUNC(3) | PU)
-#endif
-#define GPG15_GPIO	(PIN(6,15) | FUNC(0) | PU)	/* must be input in NAND boot mode */
-
-/*
- * Group 1: GPIO 224..255
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPH0_NCTS0	(PIN(7,0) | FUNC(2) | PU)
-#define GPH0_GPIO	(PIN(7,0) | FUNC(0) | PU)
-#define GPH1_NRTS0	(PIN(7,1) | FUNC(2) | PU)
-#define GPH1_GPIO	(PIN(7,1) | FUNC(0) | PU)
-#define GPH2_TXD0	(PIN(7,2) | FUNC(2) | PU)
-#define GPH2_GPIO	(PIN(7,2) | FUNC(0) | PU)
-#define GPH3_RXD0	(PIN(7,3) | FUNC(2) | PU)
-#define GPH3_GPIO	(PIN(7,3) | FUNC(0) | PU)
-#define GPH4_TXD1	(PIN(7,4) | FUNC(2) | PU)
-#define GPH4_GPIO	(PIN(7,4) | FUNC(0) | PU)
-#define GPH5_RXD1	(PIN(7,5) | FUNC(2) | PU)
-#define GPH5_GPIO	(PIN(7,5) | FUNC(0) | PU)
-#define GPH6_TXD2	(PIN(7,6) | FUNC(2) | PU)
-#define GPH6_NRTS1	(PIN(7,6) | FUNC(3) | PU)
-#define GPH6_GPIO	(PIN(7,6) | FUNC(0) | PU)
-#define GPH7_RXD2	(PIN(7,7) | FUNC(2) | PU)
-#define GPH7_NCTS1	(PIN(7,7) | FUNC(3) | PU)
-#define GPH7_GPIO	(PIN(7,7) | FUNC(0) | PU)
-#define GPH8_UEXTCLK	(PIN(7,8) | FUNC(2) | PU)
-#define GPH8_GPIO	(PIN(7,8) | FUNC(0) | PU)
-#define GPH9_CLOCKOUT0	(PIN(7,9) | FUNC(2) | PU)
-#define GPH9_GPIO	(PIN(7,9) | FUNC(0) | PU)
-#define GPH10_CLKOUT1	(PIN(7,10) | FUNC(2) | PU)
-#define GPH10_GPIO	(PIN(7,10) | FUNC(0) | PU)
-
-#ifdef CONFIG_CPU_S3C2440
-/*
- * Group 1: GPIO 256..287
- * Used GPIO: 0...12
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPJ0_CAMDATA0	(PIN(8,0) | FUNC(2) | PU)
-#define GPJ0_GPIO	(PIN(8,0) | FUNC(0) | PU)
-#define GPJ1_CAMDATA1	(PIN(8,1) | FUNC(2) | PU)
-#define GPJ1_GPIO	(PIN(8,1) | FUNC(0) | PU)
-#define GPJ2_CAMDATA2	(PIN(8,2) | FUNC(2) | PU)
-#define GPJ2_GPIO	(PIN(8,2) | FUNC(0) | PU)
-#define GPJ3_CAMDATA3	(PIN(8,3) | FUNC(2) | PU)
-#define GPJ3_GPIO	(PIN(8,3) | FUNC(0) | PU)
-#define GPJ4_CAMDATA4	(PIN(8,4) | FUNC(2) | PU)
-#define GPJ4_GPIO	(PIN(8,4) | FUNC(0) | PU)
-#define GPJ5_CAMDATA5	(PIN(8,5) | FUNC(2) | PU)
-#define GPJ5_GPIO	(PIN(8,5) | FUNC(0) | PU)
-#define GPJ6_CAMDATA6	(PIN(8,6) | FUNC(2) | PU)
-#define GPJ6_GPIO	(PIN(8,6) | FUNC(0) | PU)
-#define GPJ7_CAMDATA7	(PIN(8,7) | FUNC(2) | PU)
-#define GPJ7_GPIO	(PIN(8,7) | FUNC(0) | PU)
-#define GPJ8_CAMPCLK	(PIN(8,8) | FUNC(2) | PU)
-#define GPJ8_GPIO	(PIN(8,8) | FUNC(0) | PU)
-#define GPJ9_CAMVSYNC	(PIN(8,9) | FUNC(2) | PU)
-#define GPJ9_GPIO	(PIN(8,9) | FUNC(0) | PU)
-#define GPJ10_CAMHREF	(PIN(8,10) | FUNC(2) | PU)
-#define GPJ10_GPIO	(PIN(8,10) | FUNC(0) | PU)
-#define GPJ11_CAMCLKOUT	(PIN(8,11) | FUNC(2) | PU)
-#define GPJ11_GPIO	(PIN(8,11) | FUNC(0) | PU)
-#define GPJ12_CAMRESET	(PIN(8,12) | FUNC(0) | PU)
-#define GPJ12_GPIO	(PIN(8,12) | FUNC(0) | PU)
-
-#endif
-
-#endif /* __MACH_IOMUX_S3C24x0_H */
diff --git a/arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h b/arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h
deleted file mode 100644
index 5d68b71ae7..0000000000
--- a/arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h
+++ /dev/null
@@ -1,542 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_IOMUX_S3C64XX_H
-# define __MACH_IOMUX_S3C64XX_H
-
-/* 3322222222221111111111
- * 10987654321098765432109876543210
- *                           ^^^^^^_ Bit offset
- *                      ^^^^^_______ Group Number
- *                  ^^^^____________ Function
- *                 ^________________ initial GPIO out value
- *                ^_________________ Pull up/down feature present
- *              ^^__________________ initial pull up/down setting
- */
-
-#define PIN(group,bit) ((group << 6) + bit)
-#define FUNC(x) (((x) & 0xf) << 11)
-#define GET_FUNC(x) (((x) >> 11) & 0xf)
-#define GET_GROUP(x) (((x) >> 6) & 0x1f)
-#define GET_BIT(x) ((x) & 0x3f)
-#define GET_GPIOVAL(x) (!!((x) & (1 << 15)))
-#define GPIO_OUT (1 << 11)
-#define GPIO_IN (0 << 11)
-#define GPIO_VAL(x) ((!!(x)) << 15)
-#define PUD_MASK 0x3
-#define PUD (1 << 16)
-#define PUD_PRESENT(x) (!!((x) & (1 << 16)))
-#define DISABLE_PUD (0 << 17)
-#define ENABLE_PU (2 << 17)
-#define ENABLE_PD (1 << 17)
-#define GET_PUD(x) (((x) >> 17) & PUD_MASK)
-
-/*
- * To have a chance for simple GPIO manipulation routines
- * define the GPIO numbers with a real simple scheme.
- *
- * Keep in mind: The 'GPIO_2_NO' creates a value to be used with the real gpio
- * routines and *not* for the multiplexer routines!
- */
-#define GPIO_2_NO(x,y) (PIN(x,y))
-
-/*
- * Group A: GPIO 0...7
- * Used GPIO: 0...7
- * These pins can also act as GPIO outputs
- */
-#define GPA0		(PIN(0,0) | PUD)
-#define GPA0_GPIO	(GPA0 | FUNC(0))
-#define GPA0_RXD0	(GPA0 | FUNC(2))
-#define GPA1		(PIN(0,4) | PUD)
-#define GPA1_GPIO	(GPA1 | FUNC(0))
-#define GPA1_TXD0	(GPA1 | FUNC(2))
-#define GPA2		(PIN(0,8) | PUD)
-#define GPA2_GPIO	(GPA2 | FUNC(0))
-#define GPA2_NCTS0	(GPA2 | FUNC(2))
-#define GPA3		(PIN(0,12) | PUD)
-#define GPA3_GPIO	(GPA3 | FUNC(0))
-#define GPA3_NRTS0	(GPA3 | FUNC(2))
-#define GPA4		(PIN(0,16) | PUD)
-#define GPA4_GPIO	(GPA4 | FUNC(0))
-#define GPA4_RXD1	(GPA4 | FUNC(2))
-#define GPA5		(PIN(0,20) | PUD)
-#define GPA5_GPIO	(GPA5 | FUNC(0))
-#define GPA5_TXD1	(GPA5 | FUNC(2))
-#define GPA6		(PIN(0,24) | PUD)
-#define GPA6_GPIO	(GPA6 | FUNC(0))
-#define GPA6_NCTS1	(GPA6 | FUNC(2))
-#define GPA7		(PIN(0,28) | PUD)
-#define GPA7_GPIO	(GPA7 | FUNC(0))
-#define GPA7_NRTS1	(GPA7 | FUNC(2))
-
-/*
- * Group B: GPIO 0...7
- * Used GPIO: 8...15
- * These pins can also act as GPIO outputs
- */
-#define GPB0		(PIN(1,0) | PUD)
-#define GPB0_GPIO	(GPB0 | FUNC(0))
-#define GPB0_RXD2	(GPB0 | FUNC(2))
-#define GPB0_DMAREQ	(GPB0 | FUNC(3))
-#define GPB0_IRDA_RXD	(GPB0 | FUNC(4))
-#define GPB0_ADDR_CF0	(GPB0 | FUNC(5))
-#define GPB1		(PIN(1,4) | PUD)
-#define GPB1_GPIO	(GPB1 | FUNC(0))
-#define GPB1_TXD2	(GPB1 | FUNC(2))
-#define GPB1_DMAREQ	(GPB1 | FUNC(3))
-#define GPB1_IRDA_TXD	(GPB1 | FUNC(4))
-#define GPB1_ADDR_CF1	(GPB1 | FUNC(5))
-#define GPB2		(PIN(1,8) | PUD)
-#define GPB2_GPIO	(GPB2 | FUNC(0))
-#define GPB2_RXD3	(GPB2 | FUNC(2))
-#define GPB2_IRDA_RXD	(GPB2 | FUNC(3))
-#define GPB2_DMAREQ	(GPB2 | FUNC(4))
-#define GPB2_ADDR_CF2	(GPB2 | FUNC(5))
-#define GPB2_IIC1_SCL	(GPB2 | FUNC(6))
-#define GPB3		(PIN(1,12) | PUD)
-#define GPB3_GPIO	(GPB3 | FUNC(0))
-#define GPB3_TXD3	(GPB3 | FUNC(2))
-#define GPB3_IRDA_TXD	(GPB3 | FUNC(3))
-#define GPB3_DMAREQ	(GPB3 | FUNC(4))
-#define GPB3_IIC1_SDA	(GPB3 | FUNC(6))
-#define GPB4		(PIN(1,16) | PUD)
-#define GPB4_GPIO	(GPB4 | FUNC(0))
-#define GPB4_SDBW	(GPB4 | FUNC(2))
-#define GPB4_CAM_FLD	(GPB4 | FUNC(3))
-#define GPB4_CF_DIR	(GPB4 | FUNC(4))
-#define GPB5		(PIN(1,20) | PUD)
-#define GPB5_GPIO	(GPB5 | FUNC(0))
-#define GPB5_IIC0_SCL	(GPB5 | FUNC(2))
-#define GPB6		(PIN(1,24) | PUD)
-#define GPB6_GPIO	(GPB6 | FUNC(0))
-#define GPB6_IIC0_SDA	(GPB6 | FUNC(2))
-
-#define GPC0		(PIN(2,0) | PUD)
-#define GPC0_GPIO	(GPC0 | FUNC(0))
-#define GPC0_SPI0_MISO	(GPC0 | FUNC(2))
-#define GPC1		(PIN(2,4) | PUD)
-#define GPC1_GPIO	(GPC1 | FUNC(0))
-#define GPC1_SPI0_CLK	(GPC1 | FUNC(2))
-#define GPC2		(PIN(2,8) | PUD)
-#define GPC2_GPIO	(GPC2 | FUNC(0))
-#define GPC2_SPI0_MOSI	(GPC2 | FUNC(2))
-#define GPC3		(PIN(2,12) | PUD)
-#define GPC3_GPIO	(GPC3 | FUNC(0))
-#define GPC3_SPI0_NCS	(GPC3 | FUNC(2))
-#define GPC4		(PIN(2,16) | PUD)
-#define GPC4_GPIO	(GPC4 | FUNC(0))
-#define GPC4_SPI1_MISO	(GPC4 | FUNC(2))
-#define GPC5		(PIN(2,20) | PUD)
-#define GPC5_GPIO	(GPC5 | FUNC(0))
-#define GPC5_SPI1_CLK	(GPC5 | FUNC(2))
-#define GPC6		(PIN(2,24) | PUD)
-#define GPC6_GPIO	(GPC6 | FUNC(0))
-#define GPC6_SPI1_MOSI	(GPC6 | FUNC(2))
-#define GPC7		(PIN(2,28) | PUD)
-#define GPC7_GPIO	(GPC7 | FUNC(0))
-#define GPC7_SPI1_NCS	(GPC7 | FUNC(2))
-
-#define GPD0		(PIN(3,0) | PUD)
-#define GPD0_AC97_BITCLK (GPD0 | FUNC(4))
-#define GPD1		(PIN(3,4) | PUD)
-#define GPD1_AC97_NRST	(GPD1 | FUNC(4))
-#define GPD2		(PIN(3,8) | PUD)
-#define GPD2_AC97_SYNC	(GPD2 | FUNC(4))
-#define GPD3		(PIN(3,12) | PUD)
-#define GPD3_AC97_SDI	(GPD3 | FUNC(4))
-#define GPD4		(PIN(3,16) | PUD)
-#define GPD4_AC97_SDO	(GPD4 | FUNC(4))
-
-#define GPE0		(PIN(4,0) | PUD)
-#define GPE0_GPIO	(GPE0 | FUNC(0))
-#define GPE1		(PIN(4,4) | PUD)
-#define GPE1_GPIO	(GPE1 | FUNC(0))
-#define GPE2		(PIN(4,8) | PUD)
-#define GPE2_GPIO	(GPE2 | FUNC(0))
-#define GPE3		(PIN(4,12) | PUD)
-#define GPE3_GPIO	(GPE3 | FUNC(0))
-#define GPE4		(PIN(4,16) | PUD)
-#define GPE4_GPIO	(GPE4 | FUNC(0))
-
-#define GPF0		(PIN(5,0) | PUD)
-#define GPF0_GPIO	(GPF0 | FUNC(0))
-#define GPF1		(PIN(5,2) | PUD)
-#define GPF1_GPIO	(GPF1 | FUNC(0))
-#define GPF2		(PIN(5,4) | PUD)
-#define GPF2_GPIO	(GPF2 | FUNC(0))
-#define GPF3		(PIN(5,6) | PUD)
-#define GPF3_GPIO	(GPF3 | FUNC(0))
-#define GPF4		(PIN(5,8) | PUD)
-#define GPF4_GPIO	(GPF4 | FUNC(0))
-#define GPF5		(PIN(5,10) | PUD)
-#define GPF5_GPIO	(GPF5 | FUNC(0))
-#define GPF6		(PIN(5,12) | PUD)
-#define GPF6_GPIO	(GPF6 | FUNC(0))
-#define GPF7		(PIN(5,14) | PUD)
-#define GPF7_GPIO	(GPF7 | FUNC(0))
-#define GPF8		(PIN(5,16) | PUD)
-#define GPF8_GPIO	(GPF8 | FUNC(0))
-#define GPF9		(PIN(5,18) | PUD)
-#define GPF9_GPIO	(GPF9 | FUNC(0))
-#define GPF10		(PIN(5,20) | PUD)
-#define GPF10_GPIO	(GPF10 | FUNC(0))
-#define GPF11		(PIN(5,22) | PUD)
-#define GPF11_GPIO	(GPF11 | FUNC(0))
-#define GPF12		(PIN(5,24) | PUD)
-#define GPF12_GPIO	(GPF12 | FUNC(0))
-#define GPF13		(PIN(5,26) | PUD)
-#define GPF13_GPIO	(GPF13 | FUNC(0))
-#define GPF14		(PIN(5,28) | PUD)
-#define GPF14_GPIO	(GPF14 | FUNC(0))
-#define GPF14_PWM0	(GPF14 | FUNC(2))
-#define GPF14_CLKOUT	(GPF14 | FUNC(3))
-#define GPF15		(PIN(5,30) | PUD)
-#define GPF15_GPIO	(GPF15 | FUNC(0))
-#define GPF15_PWM1	(GPF15 | FUNC(2))
-
-#define GPG0		(PIN(6,0) | PUD)
-#define GPG0_MMC0_CLK	(GPG0 | FUNC(2))
-#define GPG1		(PIN(6,4) | PUD)
-#define GPG1_MMC0_CMD	(GPG1 | FUNC(2))
-#define GPG2		(PIN(6,8) | PUD)
-#define GPG2_MMC0_DAT0	(GPG2 | FUNC(2))
-#define GPG3		(PIN(6,12) | PUD)
-#define GPG3_MMC0_DAT1	(GPG3 | FUNC(2))
-#define GPG4		(PIN(6,16) | PUD)
-#define GPG4_MMC0_DAT2	(GPG4 | FUNC(2))
-#define GPG5		(PIN(6,20) | PUD)
-#define GPG5_MMC0_DAT3	(GPG5 | FUNC(2))
-#define GPG6		(PIN(6,24) | PUD)
-#define GPG6_MMC0_NCD	(GPG6 | FUNC(2))
-
-#define GPH0		(PIN(7,0) | PUD)
-#define GPH0_GPIO	(GPH0 | FUNC(0))
-#define GPH1		(PIN(7,4) | PUD)
-#define GPH1_GPIO	(GPH1 | FUNC(0))
-#define GPH2		(PIN(7,8) | PUD)
-#define GPH2_GPIO	(GPH2 | FUNC(0))
-#define GPH3		(PIN(7,12) | PUD)
-#define GPH3_GPIO	(GPH3 | FUNC(0))
-#define GPH4		(PIN(7,16) | PUD)
-#define GPH4_GPIO	(GPH4 | FUNC(0))
-#define GPH5		(PIN(7,20) | PUD)
-#define GPH5_GPIO	(GPH5 | FUNC(0))
-#define GPH6		(PIN(7,24) | PUD)
-#define GPH6_GPIO	(GPH6 | FUNC(0))
-#define GPH7		(PIN(7,28) | PUD)
-#define GPH7_GPIO	(GPH7 | FUNC(0))
-#define GPH8		(PIN(7,32) | PUD)
-#define GPH8_GPIO	(GPH8 | FUNC(0))
-#define GPH9		(PIN(7,36) | PUD)
-#define GPH9_GPIO	(GPH9 | FUNC(0))
-
-#define GPI0		(PIN(8,0) | PUD)
-#define GPI0_GPIO	(GPI0 | FUNC(0))
-#define GPI1		(PIN(8,2) | PUD)
-#define GPI1_GPIO	(GPI1 | FUNC(0))
-#define GPI2		(PIN(8,4) | PUD)
-#define GPI2_GPIO	(GPI2 | FUNC(0))
-#define GPI3		(PIN(8,6) | PUD)
-#define GPI3_GPIO	(GPI3 | FUNC(0))
-#define GPI4		(PIN(8,8) | PUD)
-#define GPI4_GPIO	(GPI4 | FUNC(0))
-#define GPI5		(PIN(8,10) | PUD)
-#define GPI5_GPIO	(GPI5 | FUNC(0))
-#define GPI6		(PIN(8,12) | PUD)
-#define GPI6_GPIO	(GPI6 | FUNC(0))
-#define GPI7		(PIN(8,14) | PUD)
-#define GPI7_GPIO	(GPI7 | FUNC(0))
-#define GPI8		(PIN(8,16) | PUD)
-#define GPI8_GPIO	(GPI8 | FUNC(0))
-#define GPI9		(PIN(8,18) | PUD)
-#define GPI9_GPIO	(GPI9 | FUNC(0))
-#define GPI10		(PIN(8,20) | PUD)
-#define GPI10_GPIO	(GPI10 | FUNC(0))
-#define GPI11		(PIN(8,22) | PUD)
-#define GPI11_GPIO	(GPI11 | FUNC(0))
-#define GPI12		(PIN(8,24) | PUD)
-#define GPI12_GPIO	(GPI12 | FUNC(0))
-#define GPI13		(PIN(8,26) | PUD)
-#define GPI13_GPIO	(GPI13 | FUNC(0))
-#define GPI14		(PIN(8,28) | PUD)
-#define GPI14_GPIO	(GPI14 | FUNC(0))
-#define GPI15		(PIN(8,30) | PUD)
-#define GPI15_GPIO	(GPI15 | FUNC(0))
-
-#define GPJ0		(PIN(9,0) | PUD)
-#define GPJ0_GPIO	(GPJ0 | FUNC(0))
-#define GPJ1		(PIN(9,2) | PUD)
-#define GPJ1_GPIO	(GPJ1 | FUNC(0))
-#define GPJ2		(PIN(9,4) | PUD)
-#define GPJ2_GPIO	(GPJ2 | FUNC(0))
-#define GPJ3		(PIN(9,6) | PUD)
-#define GPJ3_GPIO	(GPJ3 | FUNC(0))
-#define GPJ4		(PIN(9,8) | PUD)
-#define GPJ4_GPIO	(GPJ4 | FUNC(0))
-#define GPJ5		(PIN(9,10) | PUD)
-#define GPJ5_GPIO	(GPJ5 | FUNC(0))
-#define GPJ6		(PIN(9,12) | PUD)
-#define GPJ6_GPIO	(GPJ6 | FUNC(0))
-#define GPJ7		(PIN(9,14) | PUD)
-#define GPJ7_GPIO	(GPJ7 | FUNC(0))
-#define GPJ8		(PIN(9,16) | PUD)
-#define GPJ8_GPIO	(GPJ8 | FUNC(0))
-#define GPJ9		(PIN(9,18) | PUD)
-#define GPJ9_GPIO	(GPJ9 | FUNC(0))
-#define GPJ10		(PIN(9,20) | PUD)
-#define GPJ10_GPIO	(GPJ10 | FUNC(0))
-#define GPJ11		(PIN(9,22) | PUD)
-#define GPJ11_GPIO	(GPJ11 | FUNC(0))
-
-#define GPK0		(PIN(10,0) | PUD)
-#define GPK0_DATA0	(GPK0 | FUNC(2))
-#define GPK0_GPIO	(GPK0 | FUNC(0))
-#define GPK1		(PIN(10,4) | PUD)
-#define GPK1_DATA1	(GPK1 | FUNC(2))
-#define GPK1_GPIO	(GPK1 | FUNC(0))
-#define GPK2		(PIN(10,8) | PUD)
-#define GPK2_DATA2	(GPK2 | FUNC(2))
-#define GPK2_GPIO	(GPK2 | FUNC(0))
-#define GPK3		(PIN(10,12) | PUD)
-#define GPK3_DATA3	(GPK3 | FUNC(2))
-#define GPK3_GPIO	(GPK3 | FUNC(0))
-#define GPK4		(PIN(10,16) | PUD)
-#define GPK4_DATA4	(GPK4 | FUNC(2))
-#define GPK4_GPIO	(GPK4 | FUNC(0))
-#define GPK5		(PIN(10,20) | PUD)
-#define GPK5_DATA5	(GPK5 | FUNC(2))
-#define GPK5_GPIO	(GPK5 | FUNC(0))
-#define GPK6		(PIN(10,24) | PUD)
-#define GPK6_DATA6	(GPK6 | FUNC(2))
-#define GPK6_GPIO	(GPK6 | FUNC(0))
-#define GPK7		(PIN(10,28) | PUD)
-#define GPK7_DATA7	(GPK7 | FUNC(2))
-#define GPK7_GPIO	(GPK7 | FUNC(0))
-#define GPK8		(PIN(10,32) | PUD)
-#define GPK8_DATA8	(GPK8 | FUNC(2))
-#define GPK8_GPIO	(GPK8 | FUNC(0))
-#define GPK9		(PIN(10,36) | PUD)
-#define GPK9_DATA9	(GPK9 | FUNC(2))
-#define GPK9_GPIO	(GPK9 | FUNC(0))
-#define GPK10		(PIN(10,40) | PUD)
-#define GPK10_DATA10	(GPK10 | FUNC(2))
-#define GPK10_GPIO	(GPK10 | FUNC(0))
-#define GPK11		(PIN(10,44) | PUD)
-#define GPK11_DATA11	(GPK11 | FUNC(2))
-#define GPK11_GPIO	(GPK11 | FUNC(0))
-#define GPK12		(PIN(10,48) | PUD)
-#define GPK12_DATA12	(GPK12 | FUNC(2))
-#define GPK12_GPIO	(GPK12 | FUNC(0))
-#define GPK13		(PIN(10,52) | PUD)
-#define GPK13_DATA13	(GPK13 | FUNC(2))
-#define GPK13_GPIO	(GPK13 | FUNC(0))
-#define GPK14		(PIN(10,56) | PUD)
-#define GPK14_DATA14	(GPK14 | FUNC(2))
-#define GPK14_GPIO	(GPK14 | FUNC(0))
-#define GPK15		(PIN(10,60) | PUD)
-#define GPK15_DATA15	(GPK15 | FUNC(2))
-#define GPK15_GPIO	(GPK15 | FUNC(0))
-
-#define GPL0		(PIN(11,0) | PUD)
-#define GPL0_ADDR0	(GPL0 | FUNC(2))
-#define GPL0_GPIO	(GPL0 | FUNC(0))
-#define GPL1		(PIN(11,4) | PUD)
-#define GPL1_ADDR1	(GPL1 | FUNC(2))
-#define GPL1_GPIO	(GPL1 | FUNC(0))
-#define GPL2		(PIN(11,8) | PUD)
-#define GPL2_ADDR2	(GPL2 | FUNC(2))
-#define GPL2_GPIO	(GPL2 | FUNC(0))
-#define GPL3		(PIN(11,12) | PUD)
-#define GPL3_ADDR3	(GPL3 | FUNC(2))
-#define GPL3_GPIO	(GPL3 | FUNC(0))
-#define GPL4		(PIN(11,16) | PUD)
-#define GPL4_ADDR3	(GPL4 | FUNC(2))
-#define GPL4_GPIO	(GPL4 | FUNC(0))
-#define GPL5		(PIN(11,20) | PUD)
-#define GPL5_ADDR3	(GPL5 | FUNC(2))
-#define GPL5_GPIO	(GPL5 | FUNC(0))
-#define GPL6		(PIN(11,24) | PUD)
-#define GPL6_ADDR3	(GPL6 | FUNC(2))
-#define GPL6_GPIO	(GPL6 | FUNC(0))
-#define GPL7		(PIN(11,28) | PUD)
-#define GPL7_ADDR3	(GPL7 | FUNC(2))
-#define GPL7_GPIO	(GPL7 | FUNC(0))
-#define GPL8		(PIN(11,32) | PUD)
-#define GPL8_ADDR3	(GPL8 | FUNC(2))
-#define GPL8_GPIO	(GPL8 | FUNC(0))
-#define GPL9		(PIN(11,36) | PUD)
-#define GPL9_ADDR3	(GPL9 | FUNC(2))
-#define GPL9_GPIO	(GPL9 | FUNC(0))
-#define GPL10		(PIN(11,40) | PUD)
-#define GPL10_ADDR3	(GPL10 | FUNC(2))
-#define GPL10_GPIO	(GPL10 | FUNC(0))
-#define GPL11		(PIN(11,44) | PUD)
-#define GPL11_ADDR3	(GPL11 | FUNC(2))
-#define GPL11_GPIO	(GPL11 | FUNC(0))
-#define GPL12		(PIN(11,48) | PUD)
-#define GPL12_ADDR3	(GPL12 | FUNC(2))
-#define GPL12_GPIO	(GPL12 | FUNC(0))
-#define GPL13		(PIN(11,52) | PUD)
-#define GPL13_ADDR16	(GPL13 | FUNC(2))
-#define GPL13_GPIO	(GPL13 | FUNC(0))
-#define GPL14		(PIN(11,65) | PUD)
-#define GPL14_ADDR17	(GPL14 | FUNC(2))
-#define GPL14_GPIO	(GPL14 | FUNC(0))
-
-#define GPM0		(PIN(12,0) | PUD)
-#define GPM0_GPIO	(GPM0 | FUNC(0))
-#define GPM1		(PIN(12,4) | PUD)
-#define GPM1_GPIO	(GPM1 | FUNC(0))
-#define GPM2		(PIN(12,8) | PUD)
-#define GPM2_GPIO	(GPM2 | FUNC(0))
-#define GPM3		(PIN(12,12) | PUD)
-#define GPM3_GPIO	(GPM3 | FUNC(0))
-#define GPM4		(PIN(12,16) | PUD)
-#define GPM4_GPIO	(GPM4 | FUNC(0))
-#define GPM5		(PIN(12,20) | PUD)
-#define GPM5_GPIO	(GPM5 | FUNC(0))
-
-#define GPN0		(PIN(13,0) | PUD)
-#define GPN0_GPIO	(GPN0 | FUNC(0))
-#define GPN1		(PIN(13,0) | PUD)
-#define GPN1_GPIO	(GPN1 | FUNC(0))
-#define GPN2		(PIN(13,0) | PUD)
-#define GPN2_GPIO	(GPN2 | FUNC(0))
-#define GPN3		(PIN(13,0) | PUD)
-#define GPN3_GPIO	(GPN3 | FUNC(0))
-#define GPN4		(PIN(13,0) | PUD)
-#define GPN4_GPIO	(GPN4 | FUNC(0))
-#define GPN5		(PIN(13,0) | PUD)
-#define GPN5_GPIO	(GPN5 | FUNC(0))
-#define GPN6		(PIN(13,0) | PUD)
-#define GPN6_GPIO	(GPN6 | FUNC(0))
-#define GPN7		(PIN(13,0) | PUD)
-#define GPN7_GPIO	(GPN7 | FUNC(0))
-#define GPN8		(PIN(13,0) | PUD)
-#define GPN8_GPIO	(GPN8 | FUNC(0))
-#define GPN9		(PIN(13,0) | PUD)
-#define GPN9_GPIO	(GPN9 | FUNC(0))
-#define GPN10		(PIN(13,20) | PUD)
-#define GPN10_GPIO	(GPN10 | FUNC(0))
-#define GPN11		(PIN(13,20) | PUD)
-#define GPN11_GPIO	(GPN11 | FUNC(0))
-#define GPN12		(PIN(13,20) | PUD)
-#define GPN12_GPIO	(GPN12 | FUNC(0))
-#define GPN13		(PIN(13,20) | PUD)
-#define GPN13_GPIO	(GPN13 | FUNC(0))
-#define GPN14		(PIN(13,20) | PUD)
-#define GPN14_GPIO	(GPN14 | FUNC(0))
-#define GPN15		(PIN(13,20) | PUD)
-#define GPN15_GPIO	(GPN15 | FUNC(0))
-
-#define GPO0		(PIN(14,0) | PUD)
-#define GPO0_GPIO	(GPO0 | FUNC(0))
-#define GPO0_NCS2	(GPO0 | FUNC(2))
-#define GPO1		(PIN(14,2) | PUD)
-#define GPO1_GPIO	(GPO1 | FUNC(0))
-#define GPO1_NCS3	(GPO1 | FUNC(2))
-#define GPO2		(PIN(14,4) | PUD)
-#define GPO2_GPIO	(GPO2 | FUNC(0))
-#define GPO2_NCS4	(GPO2 | FUNC(2))
-#define GPO3		(PIN(14,6) | PUD)
-#define GPO3_GPIO	(GPO3 | FUNC(0))
-#define GPO3_NCS5	(GPO3 | FUNC(2))
-#define GPO4		(PIN(14,8) | PUD)
-#define GPO4_GPIO	(GPO4 | FUNC(0))
-#define GPO5		(PIN(14,10) | PUD)
-#define GPO5_GPIO	(GPO5 | FUNC(0))
-#define GPO6		(PIN(14,12) | PUD)
-#define GPO6_GPIO	(GPO6 | FUNC(0))
-#define GPO6_ADDR6	(GPO6 | FUNC(2))
-#define GPO7		(PIN(14,14) | PUD)
-#define GPO7_GPIO	(GPO7 | FUNC(0))
-#define GPO7_ADDR7	(GPO7 | FUNC(2))
-#define GPO8		(PIN(14,16) | PUD)
-#define GPO8_GPIO	(GPO8 | FUNC(0))
-#define GPO8_ADDR8	(GPO8 | FUNC(2))
-#define GPO9		(PIN(14,18) | PUD)
-#define GPO9_GPIO	(GPO9 | FUNC(0))
-#define GPO9_ADDR9	(GPO9 | FUNC(2))
-#define GPO10		(PIN(14,20) | PUD)
-#define GPO10_GPIO	(GPO10 | FUNC(2))
-#define GPO10_ADDR10	(GPO10 | FUNC(2))
-#define GPO11		(PIN(14,22) | PUD)
-#define GPO11_GPIO	(GPO11 | FUNC(0))
-#define GPO11_ADDR11	(GPO11 | FUNC(2))
-#define GPO12		(PIN(14,24) | PUD)
-#define GPO12_GPIO	(GPO12 | FUNC(0))
-#define GPO12_ADDR12	(GPO12 | FUNC(2))
-#define GPO13		(PIN(14,26) | PUD)
-#define GPO13_GPIO	(GPO13 | FUNC(0))
-#define GPO13_ADDR13	(GPO13 | FUNC(2))
-#define GPO14		(PIN(14,28) | PUD)
-#define GPO14_GPIO	(GPO14 | FUNC(0))
-#define GPO14_ADDR14	(GPO14 | FUNC(2))
-#define GPO15		(PIN(14,30) | PUD)
-#define GPO15_GPIO	(GPO15 | FUNC(0))
-#define GPO15_ADDR15	(GPO15 | FUNC(2))
-
-#define GPP0		(PIN(15,0) | PUD)
-#define GPP0_GPIO	(GPP0 | FUNC(0))
-#define GPP1		(PIN(15,2) | PUD)
-#define GPP1_GPIO	(GPP1 | FUNC(0))
-#define GPP2		(PIN(15,4) | PUD)
-#define GPP2_NWAIT	(GPP2 | FUNC(2))
-#define GPP3		(PIN(15,6) | PUD)
-#define GPP3_FALE	(GPP3 | FUNC(2))
-#define GPP4		(PIN(15,8) | PUD)
-#define GPP4_FCLE	(GPP4 | FUNC(2))
-#define GPP5		(PIN(15,10) | PUD)
-#define GPP5_FWE	(GPP5 | FUNC(2))
-#define GPP6		(PIN(15,12) | PUD)
-#define GPP6_FRE	(GPP6 | FUNC(2))
-#define GPP7		(PIN(15,14) | PUD)
-#define GPP7_RNB	(GPP7 | FUNC(2))
-#define GPP8		(PIN(15,16) | PUD)
-#define GPP8_GPIO	(GPP8 | FUNC(0))
-#define GPP9		(PIN(15,18) | PUD)
-#define GPP9_GPIO	(GPP9 | FUNC(0))
-#define GPP10		(PIN(15,20) | PUD)
-#define GPP10_GPIO	(GPP10 | FUNC(0))
-#define GPP11		(PIN(15,22) | PUD)
-#define GPP11_GPIO	(GPP11 | FUNC(0))
-#define GPP12		(PIN(15,24) | PUD)
-#define GPP12_GPIO	(GPP12 | FUNC(0))
-#define GPP13		(PIN(15,26) | PUD)
-#define GPP13_GPIO	(GPP13 | FUNC(0))
-#define GPP14		(PIN(15,28) | PUD)
-#define GPP14_GPIO	(GPP14 | FUNC(0))
-
-#define GPQ0		(PIN(16,0) | PUD)
-#define GPQ0_GPIO	(GPQ0 | FUNC(0))
-#define GPQ1		(PIN(16,2) | PUD)
-#define GPQ1_GPIO	(GPQ1 | FUNC(0))
-#define GPQ2		(PIN(16,4) | PUD)
-#define GPQ2_GPIO	(GPQ2 | FUNC(0))
-#define GPQ3		(PIN(16,8) | PUD)
-#define GPQ3_GPIO	(GPQ3 | FUNC(0))
-#define GPQ4		(PIN(16,8) | PUD)
-#define GPQ4_GPIO	(GPQ4 | FUNC(0))
-#define GPQ5		(PIN(16,10) | PUD)
-#define GPQ5_GPIO	(GPQ5 | FUNC(0))
-#define GPQ6		(PIN(16,12) | PUD)
-#define GPQ6_GPIO	(GPQ6 | FUNC(0))
-#define GPQ7		(PIN(16,14) | PUD)
-#define GPQ7_GPIO	(GPQ7 | FUNC(0))
-#define GPQ8		(PIN(16,16) | PUD)
-#define GPQ8_GPIO	(GPQ7 | FUNC(0))
-
-
-#endif /* __MACH_IOMUX_S3C64XX_H */
diff --git a/arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h b/arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h
deleted file mode 100644
index 0677de46dd..0000000000
--- a/arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h
+++ /dev/null
@@ -1,798 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- * Copyright (C) 2012 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Tested with S5PV210 */
-
-#ifndef __MACH_IOMUX_S5PCXX_H
-# define __MACH_IOMUX_S5PCXX_H
-
-/* 3322222222221111111111
- * 10987654321098765432109876543210
- *                           ^^^^^^_ Bit offset
- *                      ^^^^^_______ Group Number
- *                  ^^^^____________ Function
- *                 ^________________ initial GPIO out value
- *                ^_________________ Pull up/down feature present
- *              ^^__________________ initial pull up/down setting
- */
-
-#define PIN(group,bit) ((group << 6) + bit)
-#define FUNC(x) (((x) & 0xf) << 11)
-#define GET_FUNC(x) (((x) >> 11) & 0xf)
-#define GET_GROUP(x) (((x) >> 6) & 0x1f)
-#define GET_BIT(x) ((x) & 0x3f)
-#define GET_GPIOVAL(x) (!!((x) & (1 << 15)))
-#define GPIO_OUT (1 << 11)
-#define GPIO_IN (0 << 11)
-#define GPIO_VAL(x) ((!!(x)) << 15)
-#define PUD_MASK 0x3
-#define PUD (1 << 16)
-#define PUD_PRESENT(x) (!!((x) & (1 << 16)))
-#define DISABLE_PUD (0 << 17)
-#define ENABLE_PU (2 << 17)
-#define ENABLE_PD (1 << 17)
-#define GET_PUD(x) (((x) >> 17) & PUD_MASK)
-
-/*
- * To have a chance for simple GPIO manipulation routines
- * define the GPIO numbers with a real simple scheme.
- *
- * Keep in mind: The 'GPIO_2_NO' creates a value to be used with the real gpio
- * routines and *not* for the multiplexer routines!
- */
-#define GPIO_2_NO(x,y) (PIN(x,y))
-
-/*
- * Group A0: GPIO 0...7
- * Used GPIO: 0...7
- * These pins can also act as GPIO outputs
- */
-#define GPA00		(PIN(0,0) | PUD)
-#define GPA00_GPIO	(GPA00 | FUNC(0))
-#define GPA00_RXD0	(GPA00 | FUNC(2))
-#define GPA01		(PIN(0,1) | PUD)
-#define GPA01_GPIO	(GPA01 | FUNC(0))
-#define GPA01_TXD0	(GPA01 | FUNC(2))
-#define GPA02		(PIN(0,2) | PUD)
-#define GPA02_GPIO	(GPA02 | FUNC(0))
-#define GPA02_NCTS0	(GPA02 | FUNC(2))
-#define GPA03		(PIN(0,3) | PUD)
-#define GPA03_GPIO	(GPA03 | FUNC(0))
-#define GPA03_NRTS0	(GPA03 | FUNC(2))
-#define GPA04		(PIN(0,4) | PUD)
-#define GPA04_GPIO	(GPA04 | FUNC(0))
-#define GPA04_RXD1	(GPA04 | FUNC(2))
-#define GPA05		(PIN(0,5) | PUD)
-#define GPA05_GPIO	(GPA05 | FUNC(0))
-#define GPA05_TXD1	(GPA05 | FUNC(2))
-#define GPA06		(PIN(0,6) | PUD)
-#define GPA06_GPIO	(GPA06 | FUNC(0))
-#define GPA06_NCTS1	(GPA06 | FUNC(2))
-#define GPA07		(PIN(0,7) | PUD)
-#define GPA07_GPIO	(GPA07 | FUNC(0))
-#define GPA07_NRTS1	(GPA07 | FUNC(2))
-
-/*
- * Group A1: GPIO 0..3
- * Used GPIO: 0..3
- * These pins can also act as GPIO outputs
- */
-#define GPA10		(PIN(1,0) | PUD)
-#define GPA10_GPIO	(GPA10 | FUNC(0))
-#define GPA10_RXD2	(GPA10 | FUNC(2))
-#define GPA10_RXDAUD	(GPA0 | FUNC(4))
-#define GPA11		(PIN(1,1) | PUD)
-#define GPA11_GPIO	(GPA11 | FUNC(0))
-#define GPA11_TXD2	(GPA11 | FUNC(2))
-#define GPA11_TXDAUD	(GPA1 | FUNC(4))
-#define GPA12		(PIN(1,2) | PUD)
-#define GPA12_GPIO	(GPA12 | FUNC(0))
-#define GPA12_RXD3	(GPA12 | FUNC(2))
-#define GPA12_NCTS2	(GPA12 | FUNC(3))
-#define GPA13		(PIN(1,3) | PUD)
-#define GPA13_GPIO	(GPA13 | FUNC(0))
-#define GPA13_TXD3	(GPA13 | FUNC(2))
-#define GPA13_NRTS2	(GPA13 | FUNC(3))
-
-
-/*
- * Group B: GPIO 0...7
- * Used GPIO: 0...7
- * These pins can also act as GPIO outputs
- */
-#define GPB0		(PIN(2,0) | PUD)
-#define GPB0_GPIO	(GPB0 | FUNC(0))
-#define GPB0_SPI0_CLK   (GPB0 | FUNC(2))
-#define GPB1		(PIN(2,1) | PUD)
-#define GPB1_GPIO	(GPB1 | FUNC(0))
-#define GPB1_SPI0_NCS	(GPB1 | FUNC(2))
-#define GPB2		(PIN(2,2) | PUD)
-#define GPB2_GPIO	(GPB2 | FUNC(0))
-#define GPB2_SPI0_MISO	(GPB2 | FUNC(2))
-#define GPB3		(PIN(2,3) | PUD)
-#define GPB3_GPIO	(GPB3 | FUNC(0))
-#define GPB3_SPI0_MOSI	(GPB3 | FUNC(2))
-#define GPB4		(PIN(2,4) | PUD)
-#define GPB4_GPIO	(GPB4 | FUNC(0))
-#define GPB4_SPI1_CLK	(GPB4 | FUNC(2))
-#define GPB5		(PIN(2,5) | PUD)
-#define GPB5_GPIO	(GPB5 | FUNC(0))
-#define GPB5_SPI1_NCS	(GPB5 | FUNC(0))
-#define GPB6		(PIN(2,6) | PUD)
-#define GPB6_GPIO	(GPB6 | FUNC(0))
-#define GPB6_SPI1_MISO	(GPB6 | FUNC(0))
-#define GPB7		(PIN(2,7) | PUD)
-#define GPB7_GPIO	(GPB7 | FUNC(0))
-#define GPB7_SPI1_MOSI	(GPB7 | FUNC(0))
-
-/*
- * Group C0: GPIO 0...4
- */
-#define GPC00			(PIN(3,0) | PUD)
-#define GPC00_GPIO		(GPC00 | FUNC(0))
-#define GPC00_I2S1_SCLK		(GPC00 | FUNC(2))
-#define GPC00_PCM1_SCLK		(GPC00 | FUNC(3))
-#define GPC00_AC97_BITCLK	(GPC00 | FUNC(4))
-#define GPC01			(PIN(3,1) | PUD)
-#define GPC01_GPIO		(GPC01 | FUNC(0))
-#define GPC01_I2S1_CDCLK	(GPC01 | FUNC(2))
-#define GPC01_PCM1_EXTCLK	(GPC01 | FUNC(3))
-#define GPC01_AC97_NRESET	(GPC01 | FUNC(4))
-#define GPC02			(PIN(3,2) | PUD)
-#define GPC02_GPIO		(GPC02 | FUNC(0))
-#define GPC02_I2S1_LRCK		(GPC02 | FUNC(2))
-#define GPC02_PCM1_FSYNC	(GPC02 | FUNC(3))
-#define GPC02_AC97_SYNC		(GPC02 | FUNC(4))
-#define GPC03			(PIN(3,3) | PUD)
-#define GPC03_GPIO		(GPC03 | FUNC(0))
-#define GPC03_I2S1_SDI		(GPC03 | FUNC(2))
-#define GPC03_PCM1_SIN		(GPC03 | FUNC(3))
-#define GPC03_AC97_SDI		(GPC03 | FUNC(4))
-#define GPC04			(PIN(3,4) | PUD)
-#define GPC04_GPIO		(GPC04 | FUNC(0))
-#define GPC04_I2S1_SDO		(GPC04 | FUNC(2))
-#define GPC04_PCM1_SOUT		(GPC04 | FUNC(3))
-#define GPC04_AC97_SDO		(GPC04 | FUNC(4))
-
-/*
- * Group C1: GPIO 0...4
- */
-#define GPC10			(PIN(4,0) | PUD)
-#define GPC10_GPIO		(GPC10 | FUNC(0))
-#define GPC10_PCM2_SCLK		(GPC10 | FUNC(2))
-#define GPC10_SPDIF_0_OUT	(GPC10 | FUNC(3))
-#define GPC10_I2S2_SCLK		(GPC10 | FUNC(4))
-#define GPC11			(PIN(4,1) | PUD)
-#define GPC11_GPIO		(GPC11 | FUNC(0))
-#define GPC11_PCM2_EXTCLK	(GPC11 | FUNC(2))
-#define GPC11_SPDIF_EXTCLK	(GPC11 | FUNC(3))
-#define GPC11_I2S2_CDCLK	(GPC11 | FUNC(4))
-#define GPC12			(PIN(4,2) | PUD)
-#define GPC12_GPIO		(GPC12 | FUNC(0))
-#define GPC12_PCM2_FSYNC	(GPC12 | FUNC(2))
-#define GPC12_LCD_FRM		(GPC12 | FUNC(3))
-#define GPC12_I2S2_LRCK		(GPC12 | FUNC(4))
-#define GPC13			(PIN(4,3) | PUD)
-#define GPC13_GPIO		(GPC13 | FUNC(0))
-#define GPC13_PCM2_SIN		(GPC13 | FUNC(2))
-#define GPC13_I2S2_SDI		(GPC13 | FUNC(4))
-#define GPC14			(PIN(4,4) | PUD)
-#define GPC14_GPIO		(GPC14 | FUNC(0))
-#define GPC14_PCM2_SOUT		(GPC14 | FUNC(2))
-#define GPC14_I2S2_SDO		(GPC14 | FUNC(4))
-
-/*
- * Group D0: GPIO 0...3
- */
-#define GPD00		(PIN(5,0) | PUD)
-#define GPD00_GPIO	(GPD00 | FUNC(0))
-#define GPD00_TOUT_0	(GPD00 | FUNC(2))
-#define GPD01		(PIN(5,1) | PUD)
-#define GPD01_GPIO	(GPD01 | FUNC(0))
-#define GPD01_TOUT_1	(GPD01 | FUNC(2))
-#define GPD02		(PIN(5,2) | PUD)
-#define GPD02_GPIO	(GPD02 | FUNC(0))
-#define GPD02_TOUT_2	(GPD02 | FUNC(2))
-#define GPD03		(PIN(5,3) | PUD)
-#define GPD03_GPIO	(GPD03 | FUNC(0))
-#define GPD03_TOUT_3	(GPD03 | FUNC(2))
-
-/*
- * Group D1: GPIO 0...5
- */
-#define GPD10		(PIN(6,0) | PUD)
-#define GPD10_GPIO	(GPD10 | FUNC(0))
-#define GPD10_I2C0_SDA	(GPD10 | FUNC(2))
-#define GPD11		(PIN(6,0) | PUD)
-#define GPD11_GPIO	(GPD11 | FUNC(0))
-#define GPD11_I2C0_SCL	(GPD11 | FUNC(2))
-#define GPD12		(PIN(6,0) | PUD)
-#define GPD12_GPIO	(GPD12 | FUNC(0))
-#define GPD12_I2C1_SDA	(GPD12 | FUNC(2))
-#define GPD13		(PIN(6,0) | PUD)
-#define GPD13_GPIO	(GPD13 | FUNC(0))
-#define GPD13_I2C1_SCL	(GPD13 | FUNC(2))
-#define GPD14		(PIN(6,0) | PUD)
-#define GPD14_GPIO	(GPD14 | FUNC(0))
-#define GPD14_I2C2_SDA	(GPD14 | FUNC(2))
-#define GPD15		(PIN(6,0) | PUD)
-#define GPD15_GPIO	(GPD15 | FUNC(0))
-#define GPD15_I2C2_SCL	(GPD15 | FUNC(2))
-
-/*
- * Group E0: GPIO 0...7
- */
-#define GPE00			(PIN(7,0) | PUD)
-#define GPE00_GPIO		(GPE00 | FUNC(0))
-#define GPE00_CAM_A_PCLK	(GPE00 | FUNC(2))
-#define GPE01			(PIN(7,1) | PUD)
-#define GPE01_GPIO		(GPE01 | FUNC(0))
-#define GPE01_CAM_A_VSYNC	(GPE01 | FUNC(2))
-#define GPE02			(PIN(7,2) | PUD)
-#define GPE02_GPIO		(GPE02 | FUNC(0))
-#define GPE02_CAM_A_HREF	(GPE02 | FUNC(2))
-#define GPE03			(PIN(7,3) | PUD)
-#define GPE03_GPIO		(GPE03 | FUNC(0))
-#define GPE03_CAM_A_DATA0	(GPE03 | FUNC(2))
-#define GPE04			(PIN(7,4) | PUD)
-#define GPE04_GPIO		(GPE04 | FUNC(0))
-#define GPE04_CAM_A_DATA1	(GPE04 | FUNC(2))
-#define GPE05			(PIN(7,5) | PUD)
-#define GPE05_GPIO		(GPE05 | FUNC(0))
-#define GPE05_CAM_A_DATA2	(GPE05 | FUNC(2))
-#define GPE06			(PIN(7,6) | PUD)
-#define GPE06_GPIO		(GPE06 | FUNC(0))
-#define GPE06_CAM_A_DATA3	(GPE06 | FUNC(2))
-#define GPE07			(PIN(7,7) | PUD)
-#define GPE07_GPIO		(GPE07 | FUNC(0))
-#define GPE07_CAM_A_DATA4	(GPE07 | FUNC(2))
-
-/*
- * Group E1: GPIO 0...4
- */
-#define GPE10			(PIN(8,0) | PUD)
-#define GPE10_GPIO		(GPE10 | FUNC(0))
-#define GPE10_CAM_A_DATA5	(GPE10 | FUNC(2))
-#define GPE11			(PIN(8,1) | PUD)
-#define GPE11_GPIO		(GPE11 | FUNC(0))
-#define GPE11_CAM_A_DATA6	(GPE11 | FUNC(2))
-#define GPE12			(PIN(8,2) | PUD)
-#define GPE12_GPIO		(GPE12 | FUNC(0))
-#define GPE12_CAM_A_DATA7	(GPE12 | FUNC(2))
-#define GPE13			(PIN(8,3) | PUD)
-#define GPE13_GPIO		(GPE13 | FUNC(0))
-#define GPE13_CAM_A_CLKOUT	(GPE13 | FUNC(2))
-#define GPE14			(PIN(8,4) | PUD)
-#define GPE14_GPIO		(GPE14 | FUNC(0))
-#define GPE14_CAM_A_FIELD	(GPE14 | FUNC(2))
-
-/*
- * Group F0: GPIO 0...7
- */
-#define GPF00		(PIN(9,0) | PUD)
-#define GPF00_GPIO	(GPF00 | FUNC(0))
-#define GPF00_LCD_HSYNC	(GPF00 | FUNC(2))
-#define GPF00_SYS_CS0	(GPF00 | FUNC(3))
-#define GPF00_VEN_HSYNC	(GPF00 | FUNC(4))
-#define GPF01		(PIN(9,1) | PUD)
-#define GPF01_GPIO	(GPF01 | FUNC(0))
-#define GPF01_LCD_VSYNC	(GPF01 | FUNC(2))
-#define GPF01_SYS_CS1	(GPF01 | FUNC(3))
-#define GPF01_VEN_VSYNC	(GPF01 | FUNC(4))
-#define GPF02		(PIN(9,2) | PUD)
-#define GPF02_GPIO	(GPF02 | FUNC(0))
-#define GPF02_LCD_VDEN	(GPF02 | FUNC(2))
-#define GPF02_SYS_RS	(GPF02 | FUNC(3))
-#define GPF02_VEN_HREF	(GPF02 | FUNC(4))
-#define GPF03		(PIN(9,3) | PUD)
-#define GPF03_GPIO	(GPF03 | FUNC(0))
-#define GPF03_LCD_VCLK	(GPF03 | FUNC(2))
-#define GPF03_SYS_WE	(GPF03 | FUNC(3))
-#define GPF03_V601_CLK	(GPF03 | FUNC(4))
-#define GPF04		(PIN(9,4) | PUD)
-#define GPF04_GPIO	(GPF04 | FUNC(0))
-#define GPF04_LCD_VD0	(GPF04 | FUNC(2))
-#define GPF04_SYS_VS0	(GPF04 | FUNC(3))
-#define GPF04_VEN_DATA0	(GPF04 | FUNC(4))
-#define GPF05		(PIN(9,5) | PUD)
-#define GPF05_GPIO	(GPF05 | FUNC(0))
-#define GPF05_LCD_VD1	(GPF05 | FUNC(2))
-#define GPF05_SYS_VD1	(GPF05 | FUNC(3))
-#define GPF05_VEN_DATA1	(GPF05 | FUNC(4))
-#define GPF06		(PIN(9,6) | PUD)
-#define GPF06_GPIO	(GPF06 | FUNC(0))
-#define GPF06_LCD_VD2	(GPF06 | FUNC(2))
-#define GPF06_SYS_VD2	(GPF06 | FUNC(3))
-#define GPF06_VEN_DATA2	(GPF06 | FUNC(4))
-#define GPF07		(PIN(9,7) | PUD)
-#define GPF07_GPIO	(GPF07 | FUNC(0))
-#define GPF07_LCD_VD3	(GPF07 | FUNC(2))
-#define GPF07_SYS_VD3	(GPF07 | FUNC(3))
-#define GPF07_VEN_DATA3	(GPF07 | FUNC(4))
-
-/*
- * Group F1: GPIO 0...7
- */
-#define GPF10			(PIN(10,0) | PUD)
-#define GPF10_GPIO		(GPF10 | FUNC(0))
-#define GPF10_LCD_VD4		(GPF10 | FUNC(2))
-#define GPF10_SYS_VD4		(GPF10 | FUNC(3))
-#define GPF10_VEN_DATA4		(GPF10 | FUNC(4))
-#define GPF11			(PIN(10,1) | PUD)
-#define GPF11_GPIO		(GPF11 | FUNC(0))
-#define GPF11_LCD_VD5		(GPF11 | FUNC(2))
-#define GPF11_SYS_VD5		(GPF11 | FUNC(3))
-#define GPF11_VEN_DATA5		(GPF11 | FUNC(4))
-#define GPF12			(PIN(10,2) | PUD)
-#define GPF12_GPIO		(GPF12 | FUNC(0))
-#define GPF12_LCD_VD6		(GPF12 | FUNC(2))
-#define GPF12_SYS_VD6		(GPF12 | FUNC(3))
-#define GPF12_VEN_DATA6		(GPF12 | FUNC(4))
-#define GPF13			(PIN(10,3) | PUD)
-#define GPF13_GPIO		(GPF13 | FUNC(0))
-#define GPF13_LCD_VD7		(GPF13 | FUNC(2))
-#define GPF13_SYS_VD7		(GPF13 | FUNC(3))
-#define GPF13_VEN_DATA7		(GPF13 | FUNC(4))
-#define GPF14			(PIN(10,4) | PUD)
-#define GPF14_GPIO		(GPF14 | FUNC(0))
-#define GPF14_LCD_VD8		(GPF14 | FUNC(2))
-#define GPF14_SYS_VD8		(GPF14 | FUNC(3))
-#define GPF14_V656_DATA0	(GPF14 | FUNC(4))
-#define GPF15			(PIN(10,5) | PUD)
-#define GPF15_GPIO		(GPF15 | FUNC(0))
-#define GPF15_LCD_VD9		(GPF15 | FUNC(2))
-#define GPF15_SYS_VD9		(GPF15 | FUNC(3))
-#define GPF15_V656_DATA1	(GPF15 | FUNC(4))
-#define GPF16			(PIN(10,6) | PUD)
-#define GPF16_GPIO		(GPF16 | FUNC(0))
-#define GPF16_LCD_VD10		(GPF16 | FUNC(2))
-#define GPF16_SYS_VD10		(GPF16 | FUNC(3))
-#define GPF16_V656_DATA2	(GPF16 | FUNC(4))
-#define GPF17			(PIN(10,7) | PUD)
-#define GPF17_GPIO		(GPF17 | FUNC(0))
-#define GPF17_LCD_VD11		(GPF17 | FUNC(2))
-#define GPF17_SYS_VD11		(GPF17 | FUNC(3))
-#define GPF17_V656_DATA3	(GPF17 | FUNC(4))
-
-/*
- * Group F2: GPIO 0...7
- */
-#define GPF20			(PIN(11,0) | PUD)
-#define GPF20_GPIO		(GPF20 | FUNC(0))
-#define GPF20_LCD_VD_12		(GPF20 | FUNC(2))
-#define GPF20_SYS_VD_12		(GPF20 | FUNC(3))
-#define GPF20_V656_DATA_4	(GPF20 | FUNC(4))
-#define GPF21			(PIN(11,1) | PUD)
-#define GPF21_GPIO		(GPF21 | FUNC(0))
-#define GPF21_LCD_VD_13		(GPF21 | FUNC(2))
-#define GPF21_SYS_VD_13		(GPF21 | FUNC(3))
-#define GPF21_V656_DATA_5	(GPF21 | FUNC(4))
-#define GPF22			(PIN(11,2) | PUD)
-#define GPF22_GPIO		(GPF22 | FUNC(0))
-#define GPF22_LCD_VD_14		(GPF22 | FUNC(2))
-#define GPF22_SYS_VD_14		(GPF22 | FUNC(3))
-#define GPF22_V656_DATA_6	(GPF22 | FUNC(4))
-#define GPF23			(PIN(11,3) | PUD)
-#define GPF23_GPIO		(GPF23 | FUNC(0))
-#define GPF23_LCD_VD_15		(GPF23 | FUNC(2))
-#define GPF23_SYS_VD_15		(GPF23 | FUNC(3))
-#define GPF23_V656_DATA_7	(GPF23 | FUNC(4))
-#define GPF24			(PIN(11,4) | PUD)
-#define GPF24_GPIO		(GPF24 | FUNC(0))
-#define GPF24_LCD_VD_16		(GPF24 | FUNC(2))
-#define GPF24_SYS_VD_16		(GPF24 | FUNC(3))
-#define GPF25			(PIN(11,5) | PUD)
-#define GPF25_GPIO		(GPF25 | FUNC(0))
-#define GPF25_LCD_VD_17		(GPF25 | FUNC(2))
-#define GPF25_SYS_VD_17		(GPF25 | FUNC(3))
-#define GPF26			(PIN(11,6) | PUD)
-#define GPF26_GPIO		(GPF26 | FUNC(0))
-#define GPF26_LCD_VD_18		(GPF26 | FUNC(2))
-#define GPF26_SYS_VD_18		(GPF26 | FUNC(3))
-#define GPF27			(PIN(11,7) | PUD)
-#define GPF27_GPIO		(GPF27 | FUNC(0))
-#define GPF27_LCD_VD_19		(GPF27 | FUNC(2))
-#define GPF27_SYS_VD_19		(GPF27 | FUNC(3))
-
-/*
- * Group F3: GPIO 0...5
- */
-#define GPF30		(PIN(12,0) | PUD)
-#define GPF30_GPIO	(GPF30 | FUNC(0))
-#define GPF30_LCD_VD20	(GPF30 | FUNC(2))
-#define GPF30_SYS_VD20	(GPF30 | FUNC(3))
-#define GPF31		(PIN(12,1) | PUD)
-#define GPF31_GPIO	(GPF31 | FUNC(0))
-#define GPF31_LCD_VD21	(GPF31 | FUNC(2))
-#define GPF31_SYS_VD21	(GPF31 | FUNC(3))
-#define GPF32		(PIN(12,2) | PUD)
-#define GPF32_GPIO	(GPF32 | FUNC(0))
-#define GPF32_LCD_VD22	(GPF32 | FUNC(2))
-#define GPF32_SYS_VD22	(GPF32 | FUNC(3))
-#define GPF33		(PIN(12,3) | PUD)
-#define GPF33_GPIO	(GPF33 | FUNC(0))
-#define GPF33_LCD_VD23	(GPF33 | FUNC(2))
-#define GPF33_SYS_VD23	(GPF33 | FUNC(3))
-#define GPF33_V656_CLK	(GPF33 | FUNC(4))
-#define GPF34		(PIN(12,4) | PUD)
-#define GPF34_GPIO	(GPF34 | FUNC(0))
-#define GPF34_VSYNC_LDI	(GPF34 | FUNC(3))
-#define GPF35		(PIN(12,5) | PUD)
-#define GPF35_GPIO	(GPF35 | FUNC(0))
-#define GPF35_SYS_OE	(GPF35 | FUNC(3))
-#define GPF35_VEN_FIELD	(GPF35 | FUNC(4))
-
-/*
- * Group G0: GPIO 0...6
- */
-#define GPG00		(PIN(13,0) | PUD)
-#define GPG00_GPIO	(GPG00 | FUNC(0))
-#define GPG00_SD0_CLK	(GPG00 | FUNC(2))
-#define GPG01		(PIN(13,1) | PUD)
-#define GPG01_GPIO	(GPG01 | FUNC(0))
-#define GPG01_SD0_CMD	(GPG01 | FUNC(2))
-#define GPG02		(PIN(13,2) | PUD)
-#define GPG02_GPIO	(GPG02 | FUNC(0))
-#define GPG02_SD0_NCD	(GPG02 | FUNC(2))
-#define GPG03		(PIN(13,3) | PUD)
-#define GPG03_GPIO	(GPG03 | FUNC(0))
-#define GPG03_SD0_DATA0	(GPG03 | FUNC(2))
-#define GPG04		(PIN(13,4) | PUD)
-#define GPG04_GPIO	(GPG04 | FUNC(0))
-#define GPG04_SD0_DATA1	(GPG04 | FUNC(2))
-#define GPG05		(PIN(13,5) | PUD)
-#define GPG05_GPIO	(GPG05 | FUNC(0))
-#define GPG05_SD0_DATA2	(GPG05 | FUNC(2))
-#define GPG06		(PIN(13,6) | PUD)
-#define GPG06_GPIO	(GPG06 | FUNC(0))
-#define GPG06_SD0_DATA3	(GPG06 | FUNC(2))
-
-/*
- * Group G1: GPIO 0...6
- */
-#define GPG10		(PIN(14,0) | PUD)
-#define GPG10_GPIO	(GPG10 | FUNC(0))
-#define GPG10_SD1_CLK	(GPG10 | FUNC(2))
-#define GPG11		(PIN(14,1) | PUD)
-#define GPG11_GPIO	(GPG11 | FUNC(0))
-#define GPG11_SD1_CMD	(GPG11 | FUNC(2))
-#define GPG12		(PIN(14,2) | PUD)
-#define GPG12_GPIO	(GPG12 | FUNC(0))
-#define GPG12_SD1_NCD	(GPG12 | FUNC(2))
-#define GPG13		(PIN(14,3) | PUD)
-#define GPG13_GPIO	(GPG13 | FUNC(0))
-#define GPG13_SD1_DATA0	(GPG13 | FUNC(2))
-#define GPG13_SD0_DATA4	(GPG13 | FUNC(3))
-#define GPG14		(PIN(14,4) | PUD)
-#define GPG14_GPIO	(GPG14 | FUNC(0))
-#define GPG14_SD1_DATA1	(GPG14 | FUNC(2))
-#define GPG14_SD0_DATA5	(GPG14 | FUNC(3))
-#define GPG15		(PIN(14,5) | PUD)
-#define GPG15_GPIO	(GPG15 | FUNC(0))
-#define GPG15_SD1_DATA2	(GPG15 | FUNC(2))
-#define GPG15_SD0_DATA6	(GPG15 | FUNC(3))
-#define GPG16		(PIN(14,6) | PUD)
-#define GPG16_GPIO	(GPG16 | FUNC(0))
-#define GPG16_SD1_DATA3	(GPG16 | FUNC(2))
-#define GPG16_SD0_DATA7	(GPG16 | FUNC(3))
-
-/*
- * Group G2: GPIO 0...6
- */
-#define GPG20		(PIN(15,0) | PUD)
-#define GPG20_GPIO	(GPG20 | FUNC(0))
-#define GPG20_SD2_CLK	(GPG20 | FUNC(2))
-#define GPG21		(PIN(15,1) | PUD)
-#define GPG21_GPIO	(GPG21 | FUNC(0))
-#define GPG21_SD2_CMD	(GPG21 | FUNC(2))
-#define GPG22		(PIN(15,2) | PUD)
-#define GPG22_GPIO	(GPG22 | FUNC(0))
-#define GPG22_SD2_NCD	(GPG22 | FUNC(2))
-#define GPG23		(PIN(15,3) | PUD)
-#define GPG23_GPIO	(GPG23 | FUNC(0))
-#define GPG23_SD2_DATA0	(GPG23 | FUNC(2))
-#define GPG24		(PIN(15,4) | PUD)
-#define GPG24_GPIO	(GPG24 | FUNC(0))
-#define GPG24_SD2_DATA1	(GPG24 | FUNC(2))
-#define GPG25		(PIN(15,5) | PUD)
-#define GPG25_GPIO	(GPG25 | FUNC(0))
-#define GPG25_SD2_DATA2	(GPG25 | FUNC(2))
-#define GPG26		(PIN(15,6) | PUD)
-#define GPG26_GPIO	(GPG26 | FUNC(0))
-#define GPG26_SD2_DATA3	(GPG26 | FUNC(2))
-
-/*
- * Group G3: GPIO 0...6
- */
-#define GPG30		(PIN(16,0) | PUD)
-#define GPG30_GPIO	(GPG30 | FUNC(0))
-#define GPG30_SD3_CLK	(GPG30 | FUNC(2))
-#define GPG31		(PIN(16,1) | PUD)
-#define GPG31_GPIO	(GPG31 | FUNC(0))
-#define GPG31_SD3_CMD	(GPG31 | FUNC(2))
-#define GPG32		(PIN(16,2) | PUD)
-#define GPG32_GPIO	(GPG32 | FUNC(0))
-#define GPG32_SD3_NCD	(GPG32 | FUNC(2))
-#define GPG33		(PIN(16,3) | PUD)
-#define GPG33_GPIO	(GPG33 | FUNC(0))
-#define GPG33_SD3_DATA0	(GPG33 | FUNC(2))
-#define GPG33_SD2_DATA4	(GPG33 | FUNC(3))
-#define GPG34		(PIN(16,4) | PUD)
-#define GPG34_GPIO	(GPG34 | FUNC(0))
-#define GPG34_SD3_DATA1	(GPG34 | FUNC(2))
-#define GPG34_SD2_DATA5	(GPG34 | FUNC(3))
-#define GPG35		(PIN(16,5) | PUD)
-#define GPG35_GPIO	(GPG35 | FUNC(0))
-#define GPG35_SD3_DATA2	(GPG35 | FUNC(2))
-#define GPG35_SD2_DATA6	(GPG35 | FUNC(3))
-#define GPG36		(PIN(16,6) | PUD)
-#define GPG36_GPIO	(GPG36 | FUNC(0))
-#define GPG36_SD3_DATA3	(GPG36 | FUNC(2))
-#define GPG36_SD2_DATA7	(GPG36 | FUNC(3))
-
-/*
- * Group I - no GPIO
- */
-#define GPI0			(PIN(17,0) | PUD)
-#define GPI0_I2S0_SCLK		(GPI0 | FUNC(2))
-#define GPI0_PCM0_SCLK		(GPI0 | FUNC(3))
-#define GPI1			(PIN(17,1) | PUD)
-#define GPI1_I2S0_CDCLK		(GPI1 | FUNC(2))
-#define GPI1_PCM0_EXTCLK	(GPI1 | FUNC(3))
-#define GPI2			(PIN(17,2) | PUD)
-#define GPI2_I2S0_LRCK		(GPI2 | FUNC(2))
-#define GPI2_PCM0_FSYNC		(GPI2 | FUNC(3))
-#define GPI3			(PIN(17,3) | PUD)
-#define GPI3_I2S0_SDI		(GPI3 | FUNC(2))
-#define GPI3_PCM0_SIN		(GPI3 | FUNC(3))
-#define GPI4			(PIN(17,4) | PUD)
-#define GPI4_I2S0_SDO0		(GPI4 | FUNC(2))
-#define GPI4_PCM0_SOUT		(GPI4 | FUNC(3))
-#define GPI5			(PIN(17,5) | PUD)
-#define GPI5_I2S0_SDO1		(GPI5 | FUNC(2))
-#define GPI6			(PIN(17,6) | PUD)
-#define GPI6_I2S0_SDO2		(GPI6 | FUNC(2))
-
-/*
- * Group J0: GPIO 0...7
- */
-#define GPJ00			(PIN(18,0) | PUD)
-#define GPJ00_GPIO		(GPJ00 | FUNC(0))
-#define GPJ00_MSM_ADDR0		(GPJ00 | FUNC(2))
-#define GPJ00_CAM_B_DATA0	(GPJ00 | FUNC(3))
-#define GPJ00_CF_ADDR0		(GPJ00 | FUNC(4))
-#define GPJ00_MIPI_BYTE_CLK	(GPJ00 | FUNC(5))
-#define GPJ01			(PIN(18,1) | PUD)
-#define GPJ01_GPIO		(GPJ01 | FUNC(0))
-#define GPJ01_MSM_ADDR1		(GPJ01 | FUNC(2))
-#define GPJ01_CAM_B_DATA1	(GPJ01 | FUNC(3))
-#define GPJ01_CF_ADDR1		(GPJ01 | FUNC(4))
-#define GPJ01_MIPI_ESC_CLK	(GPJ01 | FUNC(5))
-#define GPJ02			(PIN(18,2) | PUD)
-#define GPJ02_GPIO		(GPJ02 | FUNC(0))
-#define GPJ02_MSM_ADDR2		(GPJ02 | FUNC(2))
-#define GPJ02_CAM_B_DATA2	(GPJ02 | FUNC(3))
-#define GPJ02_CF_ADDR2		(GPJ02 | FUNC(4))
-#define GPJ02_TS_CLK		(GPJ02 | FUNC(5))
-#define GPJ03			(PIN(18,3) | PUD)
-#define GPJ03_GPIO		(GPJ03 | FUNC(0))
-#define GPJ03_MSM_ADDR3		(GPJ03 | FUNC(2))
-#define GPJ03_CAM_B_DATA3	(GPJ03 | FUNC(3))
-#define GPJ03_CF_IORDY		(GPJ03 | FUNC(4))
-#define GPJ03_TS_SYNC		(GPJ03 | FUNC(5))
-#define GPJ04			(PIN(18,4) | PUD)
-#define GPJ04_GPIO		(GPJ04 | FUNC(0))
-#define GPJ04_MSM_ADDR4		(GPJ04 | FUNC(2))
-#define GPJ04_CAM_B_DATA4	(GPJ04 | FUNC(3))
-#define GPJ04_CF_INTRQ		(GPJ04 | FUNC(4))
-#define GPJ04_TS_VAL		(GPJ04 | FUNC(5))
-#define GPJ05			(PIN(18,5) | PUD)
-#define GPJ05_GPIO		(GPJ05 | FUNC(0))
-#define GPJ05_MSM_ADDR5		(GPJ05 | FUNC(2))
-#define GPJ05_CAM_B_DATA5	(GPJ05 | FUNC(3))
-#define GPJ05_CF_DMARQ		(GPJ05 | FUNC(4))
-#define GPJ05_TS_DATA		(GPJ05 | FUNC(5))
-#define GPJ06			(PIN(18,6) | PUD)
-#define GPJ06_GPIO		(GPJ06 | FUNC(0))
-#define GPJ06_MSM_ADDR6		(GPJ06 | FUNC(2))
-#define GPJ06_CAM_B_DATA6	(GPJ06 | FUNC(3))
-#define GPJ06_CF_NDRESET	(GPJ06 | FUNC(4))
-#define GPJ06_TS_ERROR		(GPJ06 | FUNC(5))
-#define GPJ07			(PIN(18,7) | PUD)
-#define GPJ07_GPIO		(GPJ07 | FUNC(0))
-#define GPJ07_MSM_ADDR7		(GPJ07 | FUNC(2))
-#define GPJ07_CAM_B_DATA7	(GPJ07 | FUNC(3))
-#define GPJ07_CF_NDMACK		(GPJ07 | FUNC(4))
-#define GPJ07_MHL_D0		(GPJ07 | FUNC(5))
-
-/*
- * Group J1: GPIO 0...5
- */
-#define GPJ10			(PIN(19,0) | PUD)
-#define GPJ10_GPIO		(GPJ10 | FUNC(0))
-#define GPJ10_MSM_ADDR8		(GPJ10 | FUNC(2))
-#define GPJ10_CAM_B_PCLK	(GPJ10 | FUNC(3))
-#define GPJ10_SROM_ADDR_16to220	(GPJ10 | FUNC(4))
-#define GPJ10_MHL_D1		(GPJ10 | FUNC(5))
-#define GPJ11			(PIN(19,1) | PUD)
-#define GPJ11_GPIO		(GPJ11 | FUNC(0))
-#define GPJ11_MSM_ADDR9		(GPJ11 | FUNC(2))
-#define GPJ11_CAM_B_VSYNC	(GPJ11 | FUNC(3))
-#define GPJ11_SROM_ADDR_16to221	(GPJ11 | FUNC(4))
-#define GPJ11_MHL_D2		(GPJ11 | FUNC(5))
-#define GPJ12			(PIN(19,2) | PUD)
-#define GPJ12_GPIO		(GPJ12 | FUNC(0))
-#define GPJ12_MSM_ADDR10	(GPJ12 | FUNC(2))
-#define GPJ12_CAM_B_HREF	(GPJ12 | FUNC(3))
-#define GPJ12_SROM_ADDR_16to222	(GPJ12 | FUNC(4))
-#define GPJ12_MHL_D3		(GPJ12 | FUNC(5))
-#define GPJ13			(PIN(19,3) | PUD)
-#define GPJ13_GPIO		(GPJ13 | FUNC(0))
-#define GPJ13_MSM_ADDR11	(GPJ13 | FUNC(2))
-#define GPJ13_CAM_B_FIELD	(GPJ13 | FUNC(3))
-#define GPJ13_SROM_ADDR_16to223	(GPJ13 | FUNC(4))
-#define GPJ13_MHL_D4		(GPJ13 | FUNC(5))
-#define GPJ14			(PIN(19,4) | PUD)
-#define GPJ14_GPIO		(GPJ14 | FUNC(0))
-#define GPJ14_MSM_ADDR12	(GPJ14 | FUNC(2))
-#define GPJ14_CAM_B_CLKOUT	(GPJ14 | FUNC(3))
-#define GPJ14_SROM_ADDR_16to224	(GPJ14 | FUNC(4))
-#define GPJ14_MHL_D5		(GPJ14 | FUNC(5))
-#define GPJ15			(PIN(19,5) | PUD)
-#define GPJ15_GPIO		(GPJ15 | FUNC(0))
-#define GPJ15_MSM_ADDR13	(GPJ15 | FUNC(2))
-#define GPJ15_KP_COL0		(GPJ15 | FUNC(3))
-#define GPJ15_SROM_ADDR_16to225	(GPJ15 | FUNC(4))
-#define GPJ15_MHL_D6		(GPJ15 | FUNC(5))
-
-/*
- * Group J2: GPIO 0...7
- */
-#define GPJ20		(PIN(20,0) | PUD)
-#define GPJ20_GPIO	(GPJ20 | FUNC(0))
-#define GPJ20_MSM_DATA0	(GPJ20 | FUNC(2))
-#define GPJ20_KP_COL1	(GPJ20 | FUNC(3))
-#define GPJ20_CF_DATA0	(GPJ20 | FUNC(4))
-#define GPJ20_MHL_D7	(GPJ20 | FUNC(5))
-#define GPJ21		(PIN(20,1) | PUD)
-#define GPJ21_GPIO	(GPJ21 | FUNC(0))
-#define GPJ21_MSM_DATA1	(GPJ21 | FUNC(2))
-#define GPJ21_KP_COL2	(GPJ21 | FUNC(3))
-#define GPJ21_CF_DATA1	(GPJ21 | FUNC(4))
-#define GPJ21_MHL_D8	(GPJ21 | FUNC(5))
-#define GPJ22		(PIN(20,2) | PUD)
-#define GPJ22_GPIO	(GPJ22 | FUNC(0))
-#define GPJ22_MSM_DATA2	(GPJ22 | FUNC(2))
-#define GPJ22_KP_COL3	(GPJ22 | FUNC(3))
-#define GPJ22_CF_DATA2	(GPJ22 | FUNC(4))
-#define GPJ22_MHL_D9	(GPJ22 | FUNC(5))
-#define GPJ23		(PIN(20,3) | PUD)
-#define GPJ23_GPIO	(GPJ23 | FUNC(0))
-#define GPJ23_MSM_DATA3	(GPJ23 | FUNC(2))
-#define GPJ23_KP_COL4	(GPJ23 | FUNC(3))
-#define GPJ23_CF_DATA3	(GPJ23 | FUNC(4))
-#define GPJ23_MHL_D10	(GPJ23 | FUNC(5))
-#define GPJ24		(PIN(20,4) | PUD)
-#define GPJ24_GPIO	(GPJ24 | FUNC(0))
-#define GPJ24_MSM_DATA4	(GPJ24 | FUNC(2))
-#define GPJ24_KP_COL5	(GPJ24 | FUNC(3))
-#define GPJ24_CF_DATA4	(GPJ24 | FUNC(4))
-#define GPJ24_MHL_D11	(GPJ24 | FUNC(5))
-#define GPJ25		(PIN(20,5) | PUD)
-#define GPJ25_GPIO	(GPJ25 | FUNC(0))
-#define GPJ25_MSM_DATA5	(GPJ25 | FUNC(2))
-#define GPJ25_KP_COL6	(GPJ25 | FUNC(3))
-#define GPJ25_CF_DATA5	(GPJ25 | FUNC(4))
-#define GPJ25_MHL_D12	(GPJ25 | FUNC(5))
-#define GPJ26		(PIN(20,6) | PUD)
-#define GPJ26_GPIO	(GPJ26 | FUNC(0))
-#define GPJ26_MSM_DATA6	(GPJ26 | FUNC(2))
-#define GPJ26_KP_COL7	(GPJ26 | FUNC(3))
-#define GPJ26_CF_DATA6	(GPJ26 | FUNC(4))
-#define GPJ26_MHL_D13	(GPJ26 | FUNC(5))
-#define GPJ27		(PIN(20,7) | PUD)
-#define GPJ27_GPIO	(GPJ27 | FUNC(0))
-#define GPJ27_MSM_DATA7	(GPJ27 | FUNC(2))
-#define GPJ27_KP_ROW0	(GPJ27 | FUNC(3))
-#define GPJ27_CF_DATA7	(GPJ27 | FUNC(4))
-#define GPJ27_MHL_D14	(GPJ27 | FUNC(5))
-
-/*
- * Group J3: GPIO 0...7
- */
-#define GPJ30			(PIN(21,0) | PUD)
-#define GPJ30_GPIO		(GPJ30 | FUNC(0))
-#define GPJ30_MSM_DATA8		(GPJ30 | FUNC(2))
-#define GPJ30_KP_ROW1		(GPJ30 | FUNC(3))
-#define GPJ30_CF_DATA8		(GPJ30 | FUNC(4))
-#define GPJ30_MHL_D15		(GPJ30 | FUNC(5))
-#define GPJ31			(PIN(21,1) | PUD)
-#define GPJ31_GPIO		(GPJ31 | FUNC(0))
-#define GPJ31_MSM_DATA9		(GPJ31 | FUNC(2))
-#define GPJ31_KP_ROW2		(GPJ31 | FUNC(3))
-#define GPJ31_CF_DATA9		(GPJ31 | FUNC(4))
-#define GPJ31_MHL_D16		(GPJ31 | FUNC(5))
-#define GPJ32			(PIN(21,2) | PUD)
-#define GPJ32_GPIO		(GPJ32 | FUNC(0))
-#define GPJ32_MSM_DATA10	(GPJ32 | FUNC(2))
-#define GPJ32_KP_ROW3		(GPJ32 | FUNC(3))
-#define GPJ32_CF_DATA10		(GPJ32 | FUNC(4))
-#define GPJ32_MHL_D17		(GPJ32 | FUNC(5))
-#define GPJ33			(PIN(21,3) | PUD)
-#define GPJ33_GPIO		(GPJ33 | FUNC(0))
-#define GPJ33_MSM_DATA11	(GPJ33 | FUNC(2))
-#define GPJ33_KP_ROW4		(GPJ33 | FUNC(3))
-#define GPJ33_CF_DATA11		(GPJ33 | FUNC(4))
-#define GPJ33_MHL_D18		(GPJ33 | FUNC(5))
-#define GPJ34			(PIN(21,4) | PUD)
-#define GPJ34_GPIO		(GPJ34 | FUNC(0))
-#define GPJ34_MSM_DATA12	(GPJ34 | FUNC(2))
-#define GPJ34_KP_ROW5		(GPJ34 | FUNC(3))
-#define GPJ34_CF_DATA12		(GPJ34 | FUNC(4))
-#define GPJ34_MHL_D19		(GPJ34 | FUNC(5))
-#define GPJ35			(PIN(21,5) | PUD)
-#define GPJ35_GPIO		(GPJ35 | FUNC(0))
-#define GPJ35_MSM_DATA13	(GPJ35 | FUNC(2))
-#define GPJ35_KP_ROW6		(GPJ35 | FUNC(3))
-#define GPJ35_CF_DATA13		(GPJ35 | FUNC(4))
-#define GPJ35_MHL_D20		(GPJ35 | FUNC(5))
-#define GPJ36			(PIN(21,6) | PUD)
-#define GPJ36_GPIO		(GPJ36 | FUNC(0))
-#define GPJ36_MSM_DATA14	(GPJ36 | FUNC(2))
-#define GPJ36_KP_ROW7		(GPJ36 | FUNC(3))
-#define GPJ36_CF_DATA14		(GPJ36 | FUNC(4))
-#define GPJ36_MHL_D21		(GPJ36 | FUNC(5))
-#define GPJ37			(PIN(21,7) | PUD)
-#define GPJ37_GPIO		(GPJ37 | FUNC(0))
-#define GPJ37_MSM_DATA15	(GPJ37 | FUNC(2))
-#define GPJ37_KP_ROW8		(GPJ37 | FUNC(3))
-#define GPJ37_CF_DATA15		(GPJ37 | FUNC(4))
-#define GPJ37_MHL_D22		(GPJ37 | FUNC(5))
-
-/*
- * Group J4: GPIO 0...4
- */
-#define GPJ40		(PIN(22,0) | PUD)
-#define GPJ40_GPIO	(GPJ40 | FUNC(0))
-#define GPJ40_MSM_NCS	(GPJ40 | FUNC(2))
-#define GPJ40_KP_ROW9	(GPJ40 | FUNC(3))
-#define GPJ40_CF_NCS0	(GPJ40 | FUNC(4))
-#define GPJ40_MHL_D23	(GPJ40 | FUNC(5))
-#define GPJ41		(PIN(22,1) | PUD)
-#define GPJ41_GPIO	(GPJ41 | FUNC(0))
-#define GPJ41_MSM_NWE	(GPJ41 | FUNC(2))
-#define GPJ41_KP_ROW10	(GPJ41 | FUNC(3))
-#define GPJ41_CF_NCS1	(GPJ41 | FUNC(4))
-#define GPJ41_MHL_IDCK	(GPJ41 | FUNC(5))
-#define GPJ42		(PIN(22,2) | PUD)
-#define GPJ42_GPIO	(GPJ42 | FUNC(0))
-#define GPJ42_MSM_NR	(GPJ42 | FUNC(2))
-#define GPJ42_KP_ROW11	(GPJ42 | FUNC(3))
-#define GPJ42_CF_IORN	(GPJ42 | FUNC(4))
-#define GPJ42_MHL_IDCK	(GPJ42 | FUNC(5))
-#define GPJ43		(PIN(22,3) | PUD)
-#define GPJ43_GPIO	(GPJ43 | FUNC(0))
-#define GPJ43_MSM_NIRQ	(GPJ43 | FUNC(2))
-#define GPJ43_KP_ROW12	(GPJ43 | FUNC(3))
-#define GPJ43_CF_IOWN	(GPJ43 | FUNC(4))
-#define GPJ43_MHL_VSYNC	(GPJ43 | FUNC(5))
-#define GPJ44		(PIN(22,4) | PUD)
-#define GPJ44_GPIO	(GPJ44 | FUNC(0))
-#define GPJ44_MSM_ADVN	(GPJ44 | FUNC(2))
-#define GPJ44_KP_ROW13	(GPJ44 | FUNC(3))
-#define GPJ44_SROM_ADDR_16to226	(GPJ44 | FUNC(4))
-#define GPJ44_MHL_DE	(GPJ44 | FUNC(5))
-
-#endif /* __MACH_IOMUX_S5PCXX_H */
diff --git a/arch/arm/mach-samsung/include/mach/iomux.h b/arch/arm/mach-samsung/include/mach/iomux.h
deleted file mode 100644
index 48651d85c3..0000000000
--- a/arch/arm/mach-samsung/include/mach/iomux.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_MACH_IOMUX_H
-#define __ASM_MACH_IOMUX_H
-
-#ifdef CONFIG_ARCH_S3C24xx
-# include <mach/iomux-s3c24x0.h>
-#endif
-#ifdef CONFIG_ARCH_S3C64xx
-# include <mach/iomux-s3c64xx.h>
-#endif
-#ifdef CONFIG_ARCH_S5PCxx
-# include <mach/iomux-s5pcxx.h>
-#endif
-
-void s3c_gpio_mode(unsigned);
-
-#endif /* __ASM_MACH_IOMUX_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-busctl.h b/arch/arm/mach-samsung/include/mach/s3c-busctl.h
deleted file mode 100644
index 4bcf0a7013..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-busctl.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2011 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_S3C_BUSCTL_H
-# define __MACH_S3C_BUSCTL_H
-
-#define S3C_BWSCON (S3C_MEMCTL_BASE)
-#define S3C_BANKCON0 (S3C_MEMCTL_BASE + 0x04)
-#define S3C_BANKCON1 (S3C_MEMCTL_BASE + 0x08)
-#define S3C_BANKCON2 (S3C_MEMCTL_BASE + 0x0c)
-#define S3C_BANKCON3 (S3C_MEMCTL_BASE + 0x10)
-#define S3C_BANKCON4 (S3C_MEMCTL_BASE + 0x14)
-#define S3C_BANKCON5 (S3C_MEMCTL_BASE + 0x18)
-#define S3C_BANKCON6 (S3C_MEMCTL_BASE + 0x1c)
-#define S3C_BANKCON7 (S3C_MEMCTL_BASE + 0x20)
-#define S3C_REFRESH (S3C_MEMCTL_BASE + 0x24)
-#define S3C_BANKSIZE (S3C_MEMCTL_BASE + 0x28)
-#define S3C_MRSRB6 (S3C_MEMCTL_BASE + 0x2c)
-#define S3C_MRSRB7 (S3C_MEMCTL_BASE + 0x30)
-
-#endif /* __MACH_S3C_BUSCTL_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-clocks.h b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
deleted file mode 100644
index ef7900285c..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-clocks.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifndef __MACH_S3C_CLOCKS_H
-#define __MACH_S3C_CLOCKS_H
-
-#ifdef CONFIG_ARCH_S3C24xx
-# include <mach/s3c24xx-clocks.h>
-#endif
-#ifdef CONFIG_ARCH_S3C64xx
-# include <mach/s3c64xx-clocks.h>
-#endif
-#ifdef CONFIG_ARCH_S5PCxx
-# include <mach/s5pcxx-clocks.h>
-#endif
-
-#endif /* __MACH_S3C_CLOCKS_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
deleted file mode 100644
index 27f264ce25..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * (C) Copyright 2009
- * Juergen Beisert, Pengutronix
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-
-uint32_t s3c_get_mpllclk(void);
-uint32_t s3c_get_upllclk(void);
-uint32_t s3c_get_fclk(void);
-uint32_t s3c_get_hclk(void);
-uint32_t s3c_get_pclk(void);
-uint32_t s3c_get_uclk(void);
-
-unsigned s3c_get_uart_clk(unsigned src);
-
-#ifdef CONFIG_ARCH_S3C24xx
-uint32_t s3c24xx_get_memory_size(void);
-void s3c24xx_disable_second_sdram_bank(void);
-#endif
-
-#ifdef CONFIG_ARCH_S5PCxx
-void s5p_init_pll(void);
-void s5p_init_dram_bank_lpddr(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
-void s5p_init_dram_bank_lpddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
-void s5p_init_dram_bank_ddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
-uint32_t s5p_get_memory_size(void);
-#endif
-
-#ifdef CONFIG_ARCH_S3C64xx
-unsigned s3c_set_epllclk(unsigned, unsigned, unsigned, unsigned);
-uint32_t s3c_get_epllclk(void);
-unsigned s3c_get_hsmmc_clk(int);
-void s3c_set_hsmmc_clk(int, int, unsigned);
-unsigned s3c6410_get_memory_size(void);
-struct s3c6410_chipselect {
-	unsigned adr_setup_t; /* in [ns] */
-	unsigned access_setup_t; /* in [ns] */
-	unsigned access_t; /* in [ns] */
-	unsigned cs_hold_t; /* in [ns] */
-	unsigned adr_hold_t; /* in [ns] */
-	unsigned char width; /* 8 or 16 */
-};
-int s3c6410_setup_chipselect(int, const struct s3c6410_chipselect*);
-#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
deleted file mode 100644
index 67fb18e5b2..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifdef CONFIG_ARCH_S3C24xx
-# include <mach/s3c24xx-iomap.h>
-#endif
-#ifdef CONFIG_ARCH_S3C64xx
-# include <mach/s3c64xx-iomap.h>
-#endif
-#ifdef CONFIG_ARCH_S5PCxx
-# include <mach/s5pcxx-iomap.h>
-#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c-mci.h b/arch/arm/mach-samsung/include/mach/s3c-mci.h
deleted file mode 100644
index d3ffb5e637..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c-mci.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert, Pengutronix
- *
- * This code is partially based on u-boot code:
- *
- * Copyright 2008, Freescale Semiconductor, Inc
- * Andy Fleming
- *
- * Based (loosely) on the Linux code
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_MMC_H_
-#define __MACH_MMC_H_
-
-struct s3c_mci_platform_data {
-	unsigned caps;	/**< supported operating modes (MMC_MODE_*) */
-	unsigned voltages; /**< supported voltage range (MMC_VDD_*) */
-	unsigned f_min;	/**< min operating frequency in Hz (0 -> no limit) */
-	unsigned f_max;	/**< max operating frequency in Hz (0 -> no limit) */
-	/* TODO */
-	/* function to modify the voltage */
-	/* function to switch the voltage */
-	/* function to detect the presence of a SD card in the socket */
-	unsigned gpio_detect;
-	unsigned detect_invert;
-};
-
-#endif /* __MACH_MMC_H_ */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h b/arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h
deleted file mode 100644
index 839dfe3c99..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2011 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-# define S3C_LOCKTIME (S3C_CLOCK_POWER_BASE)
-# define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x4)
-# define S3C_UPLLCON (S3C_CLOCK_POWER_BASE + 0x8)
-# define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
-# define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
-# define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
-
-# define S3C_MPLLCON_GET_MDIV(x) ((((x) >> 12) & 0xff) + 8)
-# define S3C_MPLLCON_GET_PDIV(x) ((((x) >> 4) & 0x3f) + 2)
-# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x3)
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h b/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
deleted file mode 100644
index 2fa48e7c3c..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- * Copyright (C) 2011 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifndef __MACH_FB_H_
-# define __MACH_FB_H_
-
-#include <fb.h>
-
-/** Proprietary flags corresponding to  S3C24x0 LCDCON5 register */
-
-/** ! INVVDEN - DE active high */
-#define FB_SYNC_DE_HIGH_ACT	(1 << 23)
-/** INVVCLK - invert CLK signal */
-#define FB_SYNC_CLK_INVERT	(1 << 24)
-/** INVVD - invert data */
-#define FB_SYNC_DATA_INVERT	(1 << 25)
-/** INVPWREN - use PWREN signal */
-#define FB_SYNC_INVERT_PWREN	(1 << 26)
-/** INVLEND - use LEND signal */
-#define FB_SYNC_INVERT_LEND	(1 << 27)
-/** PWREN - use PWREN signal */
-#define FB_SYNC_USE_PWREN	(1 << 28)
-/** ENLEND - use LEND signal */
-#define FB_SYNC_USE_LEND	(1 << 29)
-/** BSWP - swap bytes */
-#define FB_SYNC_SWAP_BYTES	(1 << 30)
-/** HWSWP - swap half words */
-#define FB_SYNC_SWAP_HW		(1 << 31)
-
-struct s3c_fb_platform_data {
-	struct fb_videomode *mode_list;
-	unsigned mode_cnt;
-
-	unsigned bits_per_pixel;
-	int passive_display;	/**< enable support for STN or CSTN displays */
-
-	/** hook to enable backlight and stuff */
-	void (*enable)(int enable);
-};
-
-#endif /* __MACH_FB_H_ */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h b/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
deleted file mode 100644
index ffb57fbd1f..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2011 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_GPIO_S3C24X0_H
-# define __MACH_GPIO_S3C24X0_H
-
-#define S3C_GPACON (S3C_GPIO_BASE)
-#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
-
-#define S3C_GPBCON (S3C_GPIO_BASE + 0x10)
-#define S3C_GPBDAT (S3C_GPIO_BASE + 0x14)
-#define S3C_GPBUP (S3C_GPIO_BASE + 0x18)
-
-#define S3C_GPCCON (S3C_GPIO_BASE + 0x20)
-#define S3C_GPCDAT (S3C_GPIO_BASE + 0x24)
-#define S3C_GPCUP (S3C_GPIO_BASE + 0x28)
-
-#define S3C_GPDCON (S3C_GPIO_BASE + 0x30)
-#define S3C_GPDDAT (S3C_GPIO_BASE + 0x34)
-#define S3C_GPDUP (S3C_GPIO_BASE + 0x38)
-
-#define S3C_GPECON (S3C_GPIO_BASE + 0x40)
-#define S3C_GPEDAT (S3C_GPIO_BASE + 0x44)
-#define S3C_GPEUP (S3C_GPIO_BASE + 0x48)
-
-#define S3C_GPFCON (S3C_GPIO_BASE + 0x50)
-#define S3C_GPFDAT (S3C_GPIO_BASE + 0x54)
-#define S3C_GPFUP (S3C_GPIO_BASE + 0x58)
-
-#define S3C_GPGCON (S3C_GPIO_BASE + 0x60)
-#define S3C_GPGDAT (S3C_GPIO_BASE + 0x64)
-#define S3C_GPGUP (S3C_GPIO_BASE + 0x68)
-
-#define S3C_GPHCON (S3C_GPIO_BASE + 0x70)
-#define S3C_GPHDAT (S3C_GPIO_BASE + 0x74)
-#define S3C_GPHUP (S3C_GPIO_BASE + 0x78)
-
-#ifdef CONFIG_CPU_S3C2440
-# define S3C_GPJCON (S3C_GPIO_BASE + 0xd0)
-# define S3C_GPJDAT (S3C_GPIO_BASE + 0xd4)
-# define S3C_GPJUP (S3C_GPIO_BASE + 0xd8)
-#endif
-
-#define S3C_MISCCR  (S3C_GPIO_BASE + 0x80)
-#define S3C_DCLKCON (S3C_GPIO_BASE + 0x84)
-#define S3C_EXTINT0 (S3C_GPIO_BASE + 0x88)
-#define S3C_EXTINT1 (S3C_GPIO_BASE + 0x8c)
-#define S3C_EXTINT2 (S3C_GPIO_BASE + 0x90)
-#define S3C_EINTFLT0 (S3C_GPIO_BASE + 0x94)
-#define S3C_EINTFLT1 (S3C_GPIO_BASE + 0x98)
-#define S3C_EINTFLT2 (S3C_GPIO_BASE + 0x9c)
-#define S3C_EINTFLT3 (S3C_GPIO_BASE + 0xa0)
-#define S3C_EINTMASK (S3C_GPIO_BASE + 0xa4)
-#define S3C_EINTPEND (S3C_GPIO_BASE + 0xa8)
-#define S3C_GSTATUS0 (S3C_GPIO_BASE + 0xac)
-#define S3C_GSTATUS1 (S3C_GPIO_BASE + 0xb0)
-#define S3C_GSTATUS2 (S3C_GPIO_BASE + 0xb4)
-#define S3C_GSTATUS3 (S3C_GPIO_BASE + 0xb8)
-#define S3C_GSTATUS4 (S3C_GPIO_BASE + 0xbc)
-
-#ifdef CONFIG_CPU_S3C2440
-# define S3C_DSC0 (S3C_GPIO_BASE + 0xc4)
-# define S3C_DSC1 (S3C_GPIO_BASE + 0xc8)
-#endif
-
-#endif /* __MACH_GPIO_S3C24X0_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h b/arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h
deleted file mode 100644
index ada23042fb..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-/* S3C2410 device base addresses */
-#define S3C_MEMCTL_BASE			0x48000000
-#define S3C2410_USB_HOST_BASE		0x49000000
-#define S3C2410_INTERRUPT_BASE		0x4A000000
-#define S3C2410_DMA_BASE		0x4B000000
-#define S3C_CLOCK_POWER_BASE		0x4C000000
-#define S3C2410_LCD_BASE		0x4D000000
-#define S3C24X0_NAND_BASE		0x4E000000
-#define S3C_UART_BASE			0x50000000
-#define S3C_TIMER_BASE			0x51000000
-#define S3C2410_USB_DEVICE_BASE		0x52000140
-#define S3C_WATCHDOG_BASE		0x53000000
-#define S3C2410_I2C_BASE		0x54000000
-#define S3C2410_I2S_BASE		0x55000000
-#define S3C_GPIO_BASE			0x56000000
-#define S3C2410_RTC_BASE		0x57000000
-#define S3C2410_ADC_BASE		0x58000000
-#define S3C2410_SPI_BASE		0x59000000
-#define S3C2410_SDI_BASE		0x5A000000
-
-/* external IO space */
-#define S3C_CS0_BASE 0x00000000
-#define S3C_CS1_BASE 0x08000000
-#define S3C_CS2_BASE 0x10000000
-#define S3C_CS3_BASE 0x18000000
-#define S3C_CS4_BASE 0x20000000
-#define S3C_CS5_BASE 0x28000000
-#define S3C_CS6_BASE 0x30000000
-
-#define S3C_SDRAM_BASE S3C_CS6_BASE
-#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
-
-/*
- * if we are booting from NAND, its internal SRAM occures at
- * a different address than without this feature
- */
-#ifdef CONFIG_S3C_NAND_BOOT
-# define NFC_RAM_AREA 0x00000000
-#else
-# define NFC_RAM_AREA 0x40000000
-#endif
-#define NFC_RAM_SIZE 4096
-
-#define S3C_UART1_BASE (S3C_UART_BASE)
-#define S3C_UART1_SIZE 0x4000
-#define S3C_UART2_BASE (S3C_UART_BASE + 0x4000)
-#define S3C_UART2_SIZE 0x4000
-#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
-#define S3C_UART3_SIZE 0x4000
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
deleted file mode 100644
index 52642ee81f..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifndef MACH_S3C24XX_NAND_H
-# define MACH_S3C24XX_NAND_H
-
-#ifdef CONFIG_S3C_NAND_BOOT
-extern void s3c24x0_nand_load_image(void*, int, int);
-#endif
-
-/**
- * Locate the timing bits for the NFCONF register
- * @param setup is the TACLS clock count
- * @param access is the TWRPH0 clock count
- * @param hold is the TWRPH1 clock count
- *
- * @note A clock count of 0 means always 1 HCLK clock.
- * @note Clock count settings depend on the NAND flash requirements and the current HCLK speed
- */
-#ifdef CONFIG_CPU_S3C2410
-# define CALC_NFCONF_TIMING(setup, access, hold) \
-	((setup << 8) + (access << 4) + (hold << 0))
-#endif
-#ifdef CONFIG_CPU_S3C2440
-# define CALC_NFCONF_TIMING(setup, access, hold) \
-	((setup << 12) + (access << 8) + (hold << 4))
-#endif
-
-/**
- * Define platform specific data for the NAND controller and its device
- */
-struct s3c24x0_nand_platform_data {
-	uint32_t nand_timing;	/**< value for the NFCONF register (timing bits only) */
-	char flash_bbt;	/**< force a flash based BBT */
-};
-
-/**
- * @file
- * @brief Basic declaration to use the s3c24x0 NAND driver
- */
-
-void nand_boot(void);
-
-#endif /* MACH_S3C24XX_NAND_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h b/arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h
deleted file mode 100644
index 8aa60bcb04..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define S3C_EPLL_LOCK  (S3C_CLOCK_POWER_BASE + 0x08)
-# define S3C_EPLL_LOCK_PLL_LOCKTIME(x) ((x) & 0xffff)
-#define S3C_APLLCON (S3C_CLOCK_POWER_BASE + 0x0c)
-# define S3C_APLLCON_ENABLE (1 << 31)
-# define S3C_APLLCON_GET_MDIV(x) (((x) >> 16) & 0x3ff)
-# define S3C_APLLCON_GET_PDIV(x) (((x) >> 8) & 0x3f)
-# define S3C_APLLCON_GET_SDIV(x) ((x) & 0x7)
-#define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x10)
-# define S3C_MPLLCON_ENABLE (1 << 31)
-# define S3C_MPLLCON_GET_MDIV(x) (((x) >> 16) & 0x3ff)
-# define S3C_MPLLCON_GET_PDIV(x) (((x) >> 8) & 0x3f)
-# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x7)
-#define S3C_EPLLCON0 (S3C_CLOCK_POWER_BASE + 0x14)
-# define S3C_EPLLCON0_ENABLE (1 << 31)
-# define S3C_EPLLCON0_GET_MDIV(x) (((x) >> 16) & 0xff)
-# define S3C_EPLLCON0_SET_MDIV(x) (((x) & 0xff) << 16)
-# define S3C_EPLLCON0_GET_PDIV(x) (((x) >> 8) & 0x3f)
-# define S3C_EPLLCON0_SET_PDIV(x) (((x) & 0x3f) << 8)
-# define S3C_EPLLCON0_GET_SDIV(x) ((x) & 0x7)
-# define S3C_EPLLCON0_SET_SDIV(x) ((x) & 0x7)
-#define S3C_EPLLCON1 (S3C_CLOCK_POWER_BASE + 0x18)
-# define S3C_EPLLCON1_GET_KDIV(x) ((x) & 0xffff)
-# define S3C_EPLLCON1_SET_KDIV(x) ((x) & 0xffff)
-#define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
-#define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
-#define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
-#define S3C_CLK_SRC (S3C_CLOCK_POWER_BASE + 0x01c)
-# define S3C_CLK_SRC_GET_MMC_SEL(x, v) (((v) >> (18 + (x * 2))) & 0x3)
-# define S3C_CLK_SRC_SET_MMC_SEL(x, v) (((v) & 0x3) << (18 + (x * 2)))
-# define S3C_CLK_SRC_UARTMPLL (1 << 13)
-# define S3C_CLK_SRC_FOUTEPLL (1 << 2)
-# define S3C_CLK_SRC_FOUTMPLL (1 << 1)
-# define S3C_CLK_SRC_FOUTAPLL (1 << 0)
-#define S3C_CLK_DIV0 (S3C_CLOCK_POWER_BASE + 0x020)
-# define S3C_CLK_DIV0_GET_ADIV(x) ((x) & 0xf)
-# define S3C_CLK_DIV0_GET_HCLK2(x) (((x) >> 9) & 0x7)
-# define S3C_CLK_DIV0_GET_HCLK(x) (((x) >> 8) & 0x1)
-# define S3C_CLK_DIV0_GET_PCLK(x) (((x) >> 12) & 0xf)
-# define S3C_CLK_DIV0_SET_MPLL_DIV(x) (((x) & 0x1) << 4)
-# define S3C_CLK_DIV0_GET_MPLL_DIV(x) (((x) >> 4) & 0x1)
-# define S3C_CLK_DIV0_GET_MMC(x, v) (((v) >> (4 * x)) & 0xf)
-# define S3C_CLK_DIV0_SET_MMC(x, v) (((v) & 0xf) << (4 * x))
-#define S3C_CLK_DIV2 (S3C_CLOCK_POWER_BASE + 0x028)
-# define S3C_CLK_DIV2_UART_MASK (0xf << 16)
-# define S3C_CLK_DIV2_SET_UART(x) ((x) << 16)
-# define S3C_CLK_DIV2_GET_UART(x) (((x) >> 16) & 0xf)
-#define S3C_SCLK_GATE (S3C_CLOCK_POWER_BASE + 0x038)
-# define S3C_SCLK_GATE_UART (1 << 5)
-# define S3C_SCLK_GATE_MMC(x) (1 << (24 + x))
-#define S3C_MISC_CON (S3C_CLOCK_POWER_BASE + 0x838)
-# define S3C_MISC_CON_SYN667 (1 << 19)
-#define S3C_OTHERS (S3C_CLOCK_POWER_BASE + 0x900)
-# define S3C_OTHERS_CLK_SELECT (1 << 6)
diff --git a/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
deleted file mode 100644
index 9cc3a1bcba..0000000000
--- a/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* S3C64xx device base addresses */
-#define S3C_SROM_SFR		0x70000000
-#define S3C_NAND_BASE		0x70200000
-#define S3C_SDI0_BASE		0x7c200000
-#define S3C_SDI0_SIZE		0x100
-#define S3C_SDI1_BASE		0x7c300000
-#define S3C_SDI1_SIZE		0x100
-#define S3C_SDI2_BASE		0x7c400000
-#define S3C_SDI2_SIZE		0x100
-#define S3C_DRAMC		0x7e001000
-#define S3C_WATCHDOG_BASE	0x7e004000
-#define S3C_CLOCK_POWER_BASE	0x7e00f000
-#define S3C_UART_BASE		0x7f005000
-#define S3C_TIMER_BASE		0x7f006000
-#define S3C_GPIO_BASE		0x7f008000
-
-#define S3C_UART1_BASE (S3C_UART_BASE)
-#define S3C_UART1_SIZE 0x400
-#define S3C_UART2_BASE (S3C_UART_BASE + 0x400)
-#define S3C_UART2_SIZE 0x400
-#define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
-#define S3C_UART3_SIZE 0x400
-#define S3C_UART4_BASE (S3C_UART_BASE + 0xc00)
-#define S3C_UART4_SIZE 0x400
-
-#define S3C_SDRAM_BASE 0x50000000
-#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
-
-#define S3C_SROM_BW (S3C_SROM_SFR)
-#define S3C_SROM_BC0 (S3C_SROM_SFR + 4)
-
-#define S3C_CS0_BASE 0x10000000
-#define S3C_CS1_BASE 0x18000000
-#define S3C_CS2_BASE 0x20000000
-#define S3C_CS3_BASE 0x28000000
-#define S3C_CS4_BASE 0x30000000
-#define S3C_CS5_BASE 0x38000000
diff --git a/arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h b/arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h
deleted file mode 100644
index f9d49c5156..0000000000
--- a/arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-# define S5P_APLL 0x00
-# define S5P_MPLL 0x08
-# define S5P_EPLL 0x10
-# define S5P_VPLL 0x20
-# define S5P_xPLL_LOCK (S5P_CLOCK_POWER_BASE)
-# define S5P_xPLL_CON  (S5P_CLOCK_POWER_BASE + 0x100)
-# define S5P_xPLL_CON0 (S5P_xPLL_CON)
-# define S5P_xPLL_CON1 (S5P_xPLL_CON + 0x4)
-
-# define S5P_xPLLCON_GET_MDIV(x)  (((x) >> 16) & 0x3ff)
-# define S5P_xPLLCON_GET_PDIV(x)  (((x) >> 8) & 0x3f)
-# define S5P_xPLLCON_GET_SDIV(x)  ((x) & 0x3)
-
-# define S5P_CLK_SRC0 (S5P_CLOCK_POWER_BASE + 0x200)
-# define S5P_CLK_SRC1 (S5P_CLOCK_POWER_BASE + 0x204)
-# define S5P_CLK_SRC2 (S5P_CLOCK_POWER_BASE + 0x208)
-# define S5P_CLK_SRC3 (S5P_CLOCK_POWER_BASE + 0x20C)
-# define S5P_CLK_SRC4 (S5P_CLOCK_POWER_BASE + 0x210)
-# define S5P_CLK_SRC5 (S5P_CLOCK_POWER_BASE + 0x214)
-# define S5P_CLK_SRC6 (S5P_CLOCK_BASE + 0x218)
-
-# define S5P_CLK_DIV0 (S5P_CLOCK_POWER_BASE + 0x300)
-# define S5P_CLK_DIV1 (S5P_CLOCK_POWER_BASE + 0x304)
-# define S5P_CLK_DIV2 (S5P_CLOCK_POWER_BASE + 0x308)
-# define S5P_CLK_DIV3 (S5P_CLOCK_POWER_BASE + 0x30C)
-# define S5P_CLK_DIV4 (S5P_CLOCK_POWER_BASE + 0x310)
-# define S5P_CLK_DIV5 (S5P_CLOCK_POWER_BASE + 0x314)
-# define S5P_CLK_DIV6 (S5P_CLOCK_POWER_BASE + 0x318)
-# define S5P_CLK_DIV7 (S5P_CLOCK_POWER_BASE + 0x31C)
-
-# define S5P_CLK_GATE_SCLK  (S5P_CLOCK_POWER_BASE + 0x444)
-# define S5P_CLK_GATE_IP0   (S5P_CLOCK_POWER_BASE + 0x460)
-# define S5P_CLK_GATE_IP1   (S5P_CLOCK_POWER_BASE + 0x464)
-# define S5P_CLK_GATE_IP2   (S5P_CLOCK_POWER_BASE + 0x468)
-# define S5P_CLK_GATE_IP3   (S5P_CLOCK_POWER_BASE + 0x46C)
-# define S5P_CLK_GATE_IP4   (S5P_CLOCK_POWER_BASE + 0x470)
-# define S5P_CLK_GATE_BLOCK (S5P_CLOCK_POWER_BASE + 0x480)
-# define S5P_CLK_GATE_IP5   (S5P_CLOCK_POWER_BASE + 0x484)
-
-# define S5P_OTHERS (S5P_CLOCK_POWER_BASE + 0xE000)
-# define S5P_USB_PHY_CONTROL (S5P_CLOCK_POWER_BASE + 0xE80C)
diff --git a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
deleted file mode 100644
index c0f763371b..0000000000
--- a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-/* S5PV210 device base addresses */
-
-#define S5P_CLOCK_POWER_BASE	0xE0100000
-#define S3C_GPIO_BASE		0xE0200000
-#define S3C_TIMER_BASE		0xE2500000
-#define S3C_WATCHDOG_BASE	0xE2700000
-#define S3C_UART_BASE		0xE2900000
-#define S3C_USB_HOST_BASE	0xEC200000
-#define S3C_NAND_BASE		0xB0E00000
-
-/* external IO space */
-#define S3C_CS0_BASE 0x80000000
-#define S3C_CS1_BASE 0x88000000
-#define S3C_CS2_BASE 0x90000000
-#define S3C_CS3_BASE 0x98000000
-#define S3C_CS4_BASE 0xA0000000
-#define S3C_CS5_BASE 0xA8000000
-
-#define S3C_SDRAM_BASE 0x20000000
-#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x60000000)
-
-#define S3C_UART1_BASE (S3C_UART_BASE)
-#define S3C_UART1_SIZE 0x400
-#define S3C_UART2_BASE (S3C_UART_BASE + 0x400)
-#define S3C_UART2_SIZE 0x400
-#define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
-#define S3C_UART3_SIZE 0x400
-
-#define S5P_DMC0_BASE 0xF0000000
-#define S5P_DMC1_BASE 0xF1400000
diff --git a/arch/arm/mach-samsung/lowlevel-s3c24x0.S b/arch/arm/mach-samsung/lowlevel-s3c24x0.S
deleted file mode 100644
index d43cdff528..0000000000
--- a/arch/arm/mach-samsung/lowlevel-s3c24x0.S
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * (C) Copyright 2009
- * Juergen Beisert <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <config.h>
-#include <mach/s3c-iomap.h>
-
-	.section ".text_bare_init.s3c24x0_disable_wd","ax"
-
-/*
- * Disable the watchdog, else it continues to bark
- */
-.globl s3c24x0_disable_wd
-s3c24x0_disable_wd:
-
-	ldr r0, =S3C_WATCHDOG_BASE
-	mov r1, #0x0
-	str r1, [r0]
-	mov pc, lr
-
-/*
- * S3C2410 PLL configuration
- * -------------------------
- *
- * Basic frequency calculation
- *
- *            m * REFclk         s = SDIV
- * PLLclk = ------------         p = PDIV + 2
- *             p * 2^s           m = MDIV + 8
- *
- * After reset the PLL of the s3c2410 processor uses:
- *
- *         MPLL   UPLL
- *  MDIV   0x5c   0x28
- *  PDIV   0x08   0x08
- *  SDIV   0x0    0x0
- *
- *            100 * 12MHz     1200MHz
- * MPLLclk = ------------- = -------- = 120MHz
- *             10 * 2^0         10
- *
- *            48 * 12MHz      576MHz
- * UPLLclk = ------------- = -------- = 57,6MHz
- *             10 * 2^0        10
- *
- * Note: Do not use "r10" here in this code
- */
-
-#ifdef CONFIG_S3C_PLL_INIT
-
-	.section ".text_bare_init.s3c24x0_pll_init","ax"
-
-.globl s3c24x0_pll_init
-s3c24x0_pll_init:
-
-	mov r0, #S3C_CLOCK_POWER_BASE
-
-	/* configure internal clock ratio */
-	mov r1, #BOARD_SPECIFIC_CLKDIVN
-	str r1, [r0, #20]
-
-	/* enable all devices on this chip */
-	mov r1, #0xFFFFFFF0
-	str r1, [r0, #12]
-
-	/* ??????? */
-#ifdef CONFIG_CPU_S3C2440
-	mov r1, #0xFFFFFFFF
-#endif
-#ifdef CONFIG_CPU_S3C2410
-	mov r1, #0x00FFFFFF
-#endif
-	str r1, [r0, #0]
-
-#ifdef CONFIG_CPU_S3C2440
-	/*
-	 * Most of the time HDIVN is not 0, so we must use the
-	 * asynchronous bus mode (refer datasheet "Clock and Power Management")
-	 */
-	mrc p15, 0, r1, c1, c0, 0
-	orr r1, r1, #0xc0000000
-	mcr p15, 0, r1, c1, c0, 0
-#endif
-
-	/* configure UPLL */
-	ldr r1, =BOARD_SPECIFIC_UPLL
-	str r1, [r0, #8]
-
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	/* configure MPLL */
-	ldr r1, =BOARD_SPECIFIC_MPLL
-	str r1, [r0, #4]
-
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	mov pc, lr
-
-#endif
-
-/**
-@page dev_s3c24xx_pll_handling PLL clock handling
-
-To control the speed of your machine the PLLs must be reconfigured after reset.
-
-For example the S3C2410 CPU wakes up after reset at 120MHz main PLL speed,
-shared with all other system on chip components. Most of the time this
-configuration is to slow for the CPU and to fast for the other components.
-
-PLL reprogramming can be done in the machine specific manner very early when
-the CONFIG_S3C_PLL_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT symbols are
-defined. The board must provide a board_init_lowlevel() assembler function in
-this case and calling the s3c24x0_pll_init() assembler function.
-
-If the s3c24x0_pll_init() is called a few further symbols must be defined to
-setup the correct values for the machine.
-
-Define in the machine specific config.h the following symbols:
-
-- S3C24XX_CLOCK_REFERENCE with the frequency in Hz of your reference crystal.
-- BOARD_SPECIFIC_CLKDIVN with the value for the main clock ratio register (CLKDIVN)
-- BOARD_SPECIFIC_MPLL with the value for the main PLL setup register
-- BOARD_SPECIFIC_UPLL with the value for the USB PLL setup register
-
-@note Valid values for the PLL settings can be found in the CPU manual.
-
-@par Background: PLL frequency calculation for the S3C2410 CPU (both PLLs) and S3C2440 (UPLL only)
-
-@f[
-	f_{PLL} = \frac{m * f_{Ref}}{p * 2^s}
-@f]
-
-With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
-
-@par Background: PLL frequency calculation for the S3C2440 CPU (MPLL only)
-
-@f[
-	f_{PLL} = \frac{2 * m * f_{Ref}}{p * 2^s}
-@f]
-
-With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
-
-@note This routine can be used for the S3C2410 and the S3C2440 CPU.
-
-*/
-
-/* ----------------------------------------------------------------------- */
-
-#ifdef CONFIG_S3C_SDRAM_INIT
-
-	.section ".text_bare_init.s3c24x0_sdram_init","ax"
-
-	.globl s3c24x0_sdram_init
-s3c24x0_sdram_init:
-
-	adr r0, SDRAMDATA	/* get the current relative address of the table */
-	mov r1, #S3C_MEMCTL_BASE
-	mov r2, #6		/* we *know* it contains 6 entries */
-
-	ldr r3, [r0], #4	/* write BSWCON first */
-	str r3, [r1], #0x1c	/* post add register offset for bank6 */
-/*
- * Initializing the SDRAM controller is very simple:
- * Just write some useful values into the SDRAM controller.
- */
-0:	ldr r3, [r0], #4
-	str r3, [r1], #4
-	subs r2, r2, #1
-	bne 0b
-
-	mov pc, lr
-
-SDRAMDATA:
-	.word BOARD_SPECIFIC_BWSCON
-	.word BOARD_SPECIFIC_BANKCON6
-	.word BOARD_SPECIFIC_BANKCON7
-	.word BOARD_SPECIFIC_REFRESH
-	.word BOARD_SPECIFIC_BANKSIZE
-	.word BOARD_SPECIFIC_MRSRB6
-	.word BOARD_SPECIFIC_MRSRB7
-
-#endif
-
-/**
-@page dev_s3c24xx_sdram_handling SDRAM controller initialisation
-
-The SDRAM controller is very simple and its initialisation requires only a
-few steps. barebox provides a generic routine to do this step.
-
-Enable CONFIG_S3C_SDRAM_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be able
-to call the generic s3c24x0_sdram_init() assembler function from within the
-machine specific board_init_lowlevel() assembler function.
-
-To use the s3c24x0_sdram_init() assembler function a few symbols must be
-defined to setup correct values for the machine.
-
-Define in the machine specific config.h the following list of symbols:
-
-- BOARD_SPECIFIC_BWSCON with the values for SDRAM banks 6 and 7
-- BOARD_SPECIFIC_BANKCON6 with the value for the BANKCON6 register
-- BOARD_SPECIFIC_BANKCON7 with the value for the BANKCON7 register
-- BOARD_SPECIFIC_REFRESH with the value for the REFRESH register
-- BOARD_SPECIFIC_BANKSIZE with the value for the BANKSIZE register
-- BOARD_SPECIFIC_MRSRB6 with the value for the MRSRB6 register
-- BOARD_SPECIFIC_MRSRB7 with the value for the MRSRB7 register
-*/
-
-/* ----------------------------------------------------------------------- */
-
-#ifdef CONFIG_S3C_NAND_BOOT
-
-	.section ".text_bare_init.s3c24x0_nand_boot","ax"
-
-	.globl s3c24x0_nand_boot
-s3c24x0_nand_boot:
-/*
- * In the case of NOR boot we are running from the same address space.
- * Detect this case to handle it correctly.
- */
-	mov r1, #S3C_MEMCTL_BASE
-	ldr r3, [r1]
-	and r3, r3, #0x6
-	cmp r3, #0x0	/* check for NAND case */
-	beq 2f
-	mov pc, lr	/* NOR case: nothing to do here */
-
-2:	ldr sp, =_text	/* Setup a temporary stack in SDRAM */
-/*
- * We still run at a location we are not linked to. But lets still running
- * from the internal SRAM, this may speed up the boot
- */
-	push {lr}
-	bl nand_boot
-	pop {lr}
-/*
- * Adjust the return address to the correct address in SDRAM
- */
-	ldr r1, =_text
-	add lr, lr, r1
-
-	mov pc, lr
-
-#endif
-
-/**
-@page dev_s3c24xx_nandboot_handling Booting from NAND
-
-To be able to boot from NAND memory only, enable the S3C24x0 NAND driver. Also
-enable CONFIG_S3C_NAND_BOOT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be
-able to call the s3c24x0_nand_boot() assembler routine from within the
-machine specific board_init_lowlevel() assembler function.
-
-@note This routine assumes an already working SDRAM controller and
-an initialized stack pointer.
-
-@note Basicly this routine runs from inside the internal SRAM. After load of
-the whole barebox image from the NAND flash memory into the SDRAM it adjusts
-the link register to the final SDRAM adress and returns.
-
-@note In the NAND boot mode, ECC is not checked. So, the first x KBytes used
-by barebox should have no bit error.
-
-Due to the fact the code to load the whole barebox from NAND must fit into
-the first 4kiB of the barebox image, the shrinked NAND driver is very
-minimalistic. Setup the NAND access timing is done in a safe manner, what
-means: Slowest possible values are used. If you want to increase the speed you
-should define the BOARD_DEFAULT_NAND_TIMING to a valid setting into the
-NFCONF register and add it to your board specific config.h. Refer S3C24x0's
-datasheet for further details. The macro #CALC_NFCONF_TIMING could help to
-calculate the register setting in a hardware independent manner.
-
-@note The regular NAND driver uses a platform data structure to define the
-NAND access timings.
-
-@note Its still possible to boot this image from NOR memory. If this routine
-detects it is running from NOR instead of the internal SRAM it skips any
-loading and returns immediately.
-
-*/
diff --git a/arch/arm/mach-samsung/lowlevel-s5pcxx.c b/arch/arm/mach-samsung/lowlevel-s5pcxx.c
deleted file mode 100644
index 15afa47ce3..0000000000
--- a/arch/arm/mach-samsung/lowlevel-s5pcxx.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- *
- * Based on code from u-boot found somewhere on the web
- * that seems to originate from Samsung
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <io.h>
-#include <init.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-clocks.h>
-#include <mach/s3c-generic.h>
-
-#ifdef CONFIG_S3C_PLL_INIT
-void  __bare_init s5p_init_pll(void)
-{
-    uint32_t reg;
-    int i;
-
-    /* Set Mux to FIN */
-    writel(0, S5P_CLK_SRC0);
-
-    writel(BOARD_APLL_LOCKTIME, S5P_xPLL_LOCK + S5P_APLL);
-
-    /* Disable PLL */
-    writel(0, S5P_xPLL_CON + S5P_APLL);
-    writel(0, S5P_xPLL_CON + S5P_MPLL);
-
-    /* Set up dividers */
-    reg = readl(S5P_CLK_DIV0);
-    reg &= ~(BOARD_CLK_DIV0_MASK);
-    reg |= (BOARD_CLK_DIV0_VAL);
-    writel(reg, S5P_CLK_DIV0);
-
-    /* Set up PLLs */
-    writel(BOARD_APLL_VAL, S5P_xPLL_CON + S5P_APLL);
-    writel(BOARD_MPLL_VAL, S5P_xPLL_CON + S5P_MPLL);
-    writel(BOARD_EPLL_VAL, S5P_xPLL_CON + S5P_EPLL);
-    writel(BOARD_VPLL_VAL, S5P_xPLL_CON + S5P_VPLL);
-
-    /* Wait for sync */
-    for (i = 0; i < 0x10000; ++i)
-        barrier();
-
-    reg = readl(S5P_CLK_SRC0);
-    reg |= 0x1111; /* switch MUX to PLL outputs */
-    writel(reg, S5P_CLK_SRC0);
-}
-#endif /* CONFIG_S3C_PLL_INIT */
diff --git a/arch/arm/mach-samsung/mem-s3c24x0.c b/arch/arm/mach-samsung/mem-s3c24x0.c
deleted file mode 100644
index 8d20f6d102..0000000000
--- a/arch/arm/mach-samsung/mem-s3c24x0.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-/**
- * @file
- * @brief Basic clock, sdram and timer handling for S3C24xx CPUs
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <linux/sizes.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-/**
- * Calculate the amount of connected and available memory
- * @return Memory size in bytes
- */
-uint32_t s3c24xx_get_memory_size(void)
-{
-	uint32_t reg, size;
-
-	/*
-	 * detect the current memory size
-	 */
-	reg = readl(S3C_BANKSIZE);
-
-	switch (reg & 0x7) {
-	case 0:
-		size = SZ_32M;
-		break;
-	case 1:
-		size = SZ_64M;
-		break;
-	case 2:
-		size = SZ_128M;
-		break;
-	case 4:
-		size = SZ_2M;
-		break;
-	case 5:
-		size = SZ_4M;
-		break;
-	case 6:
-		size = SZ_8M;
-		break;
-	default:
-		size = SZ_16M;
-		break;
-	}
-
-	/*
-	 * Is bank7 also configured for SDRAM usage?
-	 */
-	if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
-		size <<= 1;	/* also count this bank */
-
-	return size;
-}
-
-void s3c24xx_disable_second_sdram_bank(void)
-{
-	writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
-	writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
-}
diff --git a/arch/arm/mach-samsung/mem-s3c64xx.c b/arch/arm/mach-samsung/mem-s3c64xx.c
deleted file mode 100644
index c51245a378..0000000000
--- a/arch/arm/mach-samsung/mem-s3c64xx.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2012 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-
-#define S3C_DRAMC_CHIP_0_CFG (S3C_DRAMC + 0x200)
-
-/* note: this routine honors the first memory bank only */
-unsigned s3c6410_get_memory_size(void)
-{
-	unsigned reg = readl(S3C_DRAMC_CHIP_0_CFG) & 0xff;
-
-	return ~(reg << 24) + 1;
-}
-
-/* configure the timing of one of the available external chip select lines */
-int s3c6410_setup_chipselect(int no, const struct s3c6410_chipselect *c)
-{
-	unsigned per_t = 1000000000 / s3c_get_hclk();
-	unsigned tacs, tcos, tacc, tcoh, tcah, shift;
-	uint32_t reg;
-
-	/* start of cycle to chip select assertion (= address/data setup) */
-	tacs = DIV_ROUND_UP(c->adr_setup_t, per_t);
-	/* start of CS to read/write assertion (= access setup) */
-	tcos = DIV_ROUND_UP(c->access_setup_t, per_t);
-	/* length of read/write assertion (= access length) */
-	tacc = DIV_ROUND_UP(c->access_t, per_t) - 1;
-	/* CS hold after access is finished */
-	tcoh = DIV_ROUND_UP(c->cs_hold_t, per_t);
-	/* adress/data hold after CS is deasserted */
-	tcah = DIV_ROUND_UP(c->adr_hold_t, per_t);
-
-	shift = no * 4;
-	reg = readl(S3C_SROM_BW) & ~(0xf << shift);
-	if (c->width == 16)
-		reg |= 0x1 << shift;
-	writel(reg, S3C_SROM_BW);
-#ifdef DEBUG
-	if (tacs > 15 || tcos > 15 || tacc > 31 || tcoh > 15 || tcah > 15) {
-		pr_err("At least one of the timings are invalid\n");
-		return -EINVAL;
-	}
-	pr_info("Will write 0x%08X\n", tacs << 28 | tcos << 24 | tacc << 16 |
-					tcoh << 12 | tcah << 8);
-#endif
-	writel(tacs << 28 | tcos << 24 | tacc << 16 | tcoh << 12 | tcah << 8,
-						S3C_SROM_BC0 + shift);
-
-	return 0;
-}
diff --git a/arch/arm/mach-samsung/mem-s5pcxx.c b/arch/arm/mach-samsung/mem-s5pcxx.c
deleted file mode 100644
index 943f691769..0000000000
--- a/arch/arm/mach-samsung/mem-s5pcxx.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * Copyright (C) 2012 Alexey Galakhov
- *
- * Based on code from u-boot found somewhere on the web
- * that seems to originate from Samsung
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <io.h>
-#include <init.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-iomap.h>
-
-#define S5P_DMC_CONCONTROL	0x00
-#define S5P_DMC_MEMCONTROL	0x04
-#define S5P_DMC_MEMCONFIG0	0x08
-#define S5P_DMC_MEMCONFIG1	0x0C
-#define S5P_DMC_DIRECTCMD	0x10
-#define S5P_DMC_PRECHCONFIG	0x14
-#define S5P_DMC_PHYCONTROL0	0x18
-#define S5P_DMC_PHYCONTROL1	0x1C
-#define S5P_DMC_PWRDNCONFIG	0x28
-#define S5P_DMC_TIMINGAREF	0x30
-#define S5P_DMC_TIMINGROW	0x34
-#define S5P_DMC_TIMINGDATA	0x38
-#define S5P_DMC_TIMINGPOWER	0x3C
-#define S5P_DMC_PHYSTATUS	0x40
-#define S5P_DMC_MRSTATUS	0x54
-
-/* DRAM commands */
-#define CMD(x)  ((x) << 24)
-#define BANK(x) ((x) << 16)
-#define CHIP(x) ((x) << 20)
-#define ADDR(x) (x)
-
-/**
- *  MR definition:
- *  1 11
- *  2 1098 7654 3210
- *      |     |  ^^^- burst length, 010=4, 011=8
- *      |     | ^- burst type 0=sequnential, 1=interleaved
- *      |   ^^^-- CAS latency
- *      |  ^----- test, 0=normal, 1=test
- *      |^---- DLL reset, 1=yes
- *    ^^^----- WR, 1=2, 2=3 etc.
- *  ^------- PD, 0=fast exit, 1=low power
- *
- *  EMR1 definition:
- *  1 11
- *  2 1098 7654 3210
- *         |       ^- DLL, 0=enable
- *         |      ^-- output strength, 0=full, 1=reduced
- *         |^.. .^--- Rtt, 00=off, 01=75, 10=150, 11=50 Ohm
- *         | ^^ ^-- Posted CAS# AL, 0-6
- *      ^^ ^------ OCD: 000=OCD exit, 111=enable defaults
- *     ^------ DQS#, 0=enable, 1=disable
- *    ^------- RDQS enable, 0=no, 1=yes
- *  ^-------- outputs, 0=enabled, 1=disabled
- *
- *  EMR2 definition:
- *  bit 7
- *  1 1
- *  2 1098 7654 3210
- *         ^-- SRT, 0=1x (0-85 deg.C), 1=2x (>85 deg.C)
- *  all other bits = 0
- *
- *  EMR3 definition: all bits 0
- */
-
-#define MRS	CMD(0x0)
-#define PALL	CMD(0x1)
-#define PRE	CMD(0x2)
-#define DPD	CMD(0x3)
-#define REFS	CMD(0x4)
-#define REFA	CMD(0x5)
-#define CKEL	CMD(0x6)
-#define NOP	CMD(0x7)
-#define REFSX	CMD(0x8)
-#define MRR	CMD(0x9)
-
-#define EMRS1 (MRS | BANK(1))
-#define EMRS2 (MRS | BANK(2))
-#define EMRS3 (MRS | BANK(3))
-
-/* Burst is (1 << S5P_DRAM_BURST), i.e. S5P_DRAM_BURST=2 for burst 4 */
-#ifndef S5P_DRAM_BURST
-/* (LP)DDR2 supports burst 4 only, make it default */
-# define S5P_DRAM_BURST 2
-#endif
-
-/**
- * Initialization sequences for different kinds of DRAM
- */
-#define dcmd(x) writel((x) | CHIP(chip), base + S5P_DMC_DIRECTCMD)
-
-static void __bare_init s5p_dram_init_seq_lpddr(phys_addr_t base, unsigned chip)
-{
-	const uint32_t emr = 0x400; /* DQS disable */
-	const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
-			  | ((S5P_DRAM_CAS) << 4)
-			  | (S5P_DRAM_BURST);
-	/* TODO this sequence is untested */
-	dcmd(PALL); dcmd(REFA); dcmd(REFA);
-	dcmd(MRS   | ADDR(mr));
-	dcmd(EMRS1 | ADDR(emr));
-}
-
-static void __bare_init s5p_dram_init_seq_lpddr2(phys_addr_t base, unsigned chip)
-{
-	const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
-			  | ((S5P_DRAM_CAS) << 4)
-			  | (S5P_DRAM_BURST);
-	/* TODO this sequence is untested */
-	dcmd(NOP);
-	dcmd(MRS | ADDR(mr));
-	do {
-		dcmd(MRR);
-	} while (readl(base + S5P_DMC_MRSTATUS) & 0x01); /* poll DAI */
-}
-
-static void __bare_init s5p_dram_init_seq_ddr2(phys_addr_t base, unsigned chip)
-{
-	const uint32_t emr = 0x400; /* DQS disable */
-	const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
-			  | ((S5P_DRAM_CAS) << 4)
-			  | (S5P_DRAM_BURST);
-	dcmd(NOP);
-	/* FIXME wait here? JEDEC recommends but nobody does */
-	dcmd(PALL); dcmd(EMRS2); dcmd(EMRS3);
-	dcmd(EMRS1 | ADDR(emr));         /* DQS disable */
-	dcmd(MRS   | ADDR(mr | 0x100));  /* DLL reset */
-	dcmd(PALL); dcmd(REFA); dcmd(REFA);
-	dcmd(MRS   | ADDR(mr));          /* DLL no reset */
-	dcmd(EMRS1 | ADDR(emr | 0x380)); /* OCD defaults */
-	dcmd(EMRS1 | ADDR(emr));         /* OCD exit */
-}
-
-#undef dcmd
-
-static inline void __bare_init s5p_dram_start_dll(phys_addr_t base, uint32_t phycon1)
-{
-	uint32_t pc0 = 0x00101000; /* the only legal initial value */
-	uint32_t lv;
-
-	/* Init DLL */
-	writel(pc0, base + S5P_DMC_PHYCONTROL0);
-	writel(phycon1, base + S5P_DMC_PHYCONTROL1);
-
-	/* DLL on */
-	pc0 |= 0x2;
-	writel(pc0, base + S5P_DMC_PHYCONTROL0);
-
-	/* DLL start */
-	pc0 |= 0x1;
-	writel(pc0, base + S5P_DMC_PHYCONTROL0);
-
-	/* Find lock val */
-	do {
-		lv = readl(base + S5P_DMC_PHYSTATUS);
-	} while ((lv & 0x7) != 0x7);
-
-	lv >>= 6;
-	lv &= 0xff; /* ctrl_lock_value[9:2] - coarse */
-	pc0 |= (lv << 24); /* ctrl_force */
-	writel(pc0, base + S5P_DMC_PHYCONTROL0); /* force value locking */
-}
-
-static inline void __bare_init s5p_dram_setup(phys_addr_t base, uint32_t mc0, uint32_t mc1,
-				       int bus16, uint32_t mcon)
-{
-	mcon |= (S5P_DRAM_BURST) << 20;
-	/* 16 or 32-bit bus ? */
-	mcon |= bus16 ? 0x1000 : 0x2000;
-	if (mc1)
-		mcon |= 0x10000; /* two chips */
-
-	writel(mcon, base + S5P_DMC_MEMCONTROL);
-
-	/* Set up memory layout */
-	writel(mc0, base + S5P_DMC_MEMCONFIG0);
-	if (mc1)
-		writel(mc1, base + S5P_DMC_MEMCONFIG1);
-
-	/* Open page precharge policy - reasonable defaults */
-	writel(0xFF000000, base + S5P_DMC_PRECHCONFIG);
-
-	/* Set up timings */
-	writel(DMC_TIMING_AREF, base + S5P_DMC_TIMINGAREF);
-	writel(DMC_TIMING_ROW,  base + S5P_DMC_TIMINGROW);
-	writel(DMC_TIMING_DATA, base + S5P_DMC_TIMINGDATA);
-	writel(DMC_TIMING_PWR,  base + S5P_DMC_TIMINGPOWER);
-}
-
-static inline void __bare_init s5p_dram_start(phys_addr_t base)
-{
-	/* Reasonable defaults and auto-refresh on */
-	writel(0x0FFF1070, base + S5P_DMC_CONCONTROL);
-	/* Reasonable defaults */
-	writel(0xFFFF00FF, base + S5P_DMC_PWRDNCONFIG);
-}
-
-/*
- * Initialize LPDDR memory bank
- * TODO: this function is untested, see also init_seq function
- */
-void __bare_init s5p_init_dram_bank_lpddr(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
-{
-	/* refcount 8, 90 deg. shift */
-	s5p_dram_start_dll(base, 0x00000085);
-	/* LPDDR type */
-	s5p_dram_setup(base, mc0, mc1, bus16, 0x100);
-
-	/* Start-Up Commands */
-	s5p_dram_init_seq_lpddr(base, 0);
-	if (mc1)
-		s5p_dram_init_seq_lpddr(base, 1);
-
-	s5p_dram_start(base);
-}
-
-/*
- * Initialize LPDDR2 memory bank
- * TODO: this function is untested, see also init_seq function
- */
-void __bare_init s5p_init_dram_bank_lpddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
-{
-	/* refcount 8, 90 deg. shift */
-	s5p_dram_start_dll(base, 0x00000085);
-	/* LPDDR2 type */
-	s5p_dram_setup(base, mc0, mc1, bus16, 0x200);
-
-	/* Start-Up Commands */
-	s5p_dram_init_seq_lpddr2(base, 0);
-	if (mc1)
-		s5p_dram_init_seq_lpddr2(base, 1);
-
-	s5p_dram_start(base);
-}
-
-/*
- * Initialize DDR2 memory bank
- */
-void __bare_init s5p_init_dram_bank_ddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
-{
-	/* refcount 8, 180 deg. shift */
-	s5p_dram_start_dll(base, 0x00000086);
-	/* DDR2 type */
-	s5p_dram_setup(base, mc0, mc1, bus16, 0x400);
-
-	/* Start-Up Commands */
-	s5p_dram_init_seq_ddr2(base, 0);
-	if (mc1)
-		s5p_dram_init_seq_ddr2(base, 1);
-
-	s5p_dram_start(base);
-}
-
-
-#define BANK_ENABLED(base) (readl((base) + S5P_DMC_PHYCONTROL0) & 1)
-#define NUM_EXTRA_CHIPS(base) ((readl((base) + S5P_DMC_MEMCONTROL) >> 16) & 0xF)
-
-#define BANK_START(x) ((x) & 0xFF000000)
-#define BANK_END(x) (BANK_START(x) | ~(((x) & 0x00FF0000) << 8))
-#define BANK_LEN(x) (BANK_END(x) - BANK_START(x) + 1)
-
-static inline void sortswap(uint32_t *x, uint32_t *y)
-{
-	if (*y < *x) {
-		*x ^= *y;
-		*y ^= *x;
-		*x ^= *y;
-	}
-}
-
-uint32_t s5p_get_memory_size(void)
-{
-	int i;
-	uint32_t len;
-	uint32_t mc[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
-	/* Read MEMCONFIG registers */
-	if (BANK_ENABLED(S5P_DMC0_BASE)) {
-		mc[0] = readl(S5P_DMC0_BASE + S5P_DMC_MEMCONFIG0);
-		if (NUM_EXTRA_CHIPS(S5P_DMC0_BASE) > 0)
-			mc[1] = readl(S5P_DMC0_BASE + S5P_DMC_MEMCONFIG1);
-	}
-	if (BANK_ENABLED(S5P_DMC1_BASE)) {
-		mc[2] = readl(S5P_DMC1_BASE + S5P_DMC_MEMCONFIG0);
-		if (NUM_EXTRA_CHIPS(S5P_DMC1_BASE) > 0)
-			mc[3] = readl(S5P_DMC1_BASE + S5P_DMC_MEMCONFIG1);
-	}
-	/* Sort using a sorting network */
-	sortswap(mc + 0, mc + 2);
-	sortswap(mc + 1, mc + 3);
-	sortswap(mc + 0, mc + 1);
-	sortswap(mc + 2, mc + 3);
-	sortswap(mc + 1, mc + 2);
-	/* Is at least one chip enabled? */
-	if (mc[0] == 0xFFFFFFFF)
-		return 0;
-	/* Determine maximum continuous region at start */
-	len = BANK_LEN(mc[0]);
-	for (i = 1; i < 4; ++i) {
-		if (BANK_START(mc[i]) == BANK_END(mc[i - 1]) + 1)
-			len += BANK_LEN(mc[i]);
-		else
-			break;
-	}
-	return len;
-}
diff --git a/arch/arm/mach-samsung/reset_source.c b/arch/arm/mach-samsung/reset_source.c
deleted file mode 100644
index c1365b2003..0000000000
--- a/arch/arm/mach-samsung/reset_source.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2012 Juergen Beisert - <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <init.h>
-#include <io.h>
-#include <reset_source.h>
-#include <mach/s3c-iomap.h>
-
-/* S3C2440 relevant */
-#define S3C2440_GSTATUS2 0xb4
-# define S3C2440_GSTATUS2_PWRST (1 << 0)
-# define S3C2440_GSTATUS2_SLEEPRST (1 << 1)
-# define S3C2440_GSTATUS2_WDRST (1 << 2)
-
-static int s3c_detect_reset_source(void)
-{
-	u32 reg = readl(S3C_GPIO_BASE + S3C2440_GSTATUS2);
-
-	if (reg & S3C2440_GSTATUS2_PWRST) {
-		reset_source_set(RESET_POR);
-		writel(S3C2440_GSTATUS2_PWRST,
-					S3C_GPIO_BASE + S3C2440_GSTATUS2);
-		return 0;
-	}
-
-	if (reg & S3C2440_GSTATUS2_SLEEPRST) {
-		reset_source_set(RESET_WKE);
-		writel(S3C2440_GSTATUS2_SLEEPRST,
-					S3C_GPIO_BASE + S3C2440_GSTATUS2);
-		return 0;
-	}
-
-	if (reg & S3C2440_GSTATUS2_WDRST) {
-		reset_source_set(RESET_WDG);
-		writel(S3C2440_GSTATUS2_WDRST,
-					S3C_GPIO_BASE + S3C2440_GSTATUS2);
-		return 0;
-	}
-
-	/* else keep the default 'unknown' state */
-	return 0;
-}
-
-device_initcall(s3c_detect_reset_source);
diff --git a/arch/arm/mach-samsung/s3c-timer.c b/arch/arm/mach-samsung/s3c-timer.c
deleted file mode 100644
index 6f38df3958..0000000000
--- a/arch/arm/mach-samsung/s3c-timer.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-
-#define S3C_TCFG0 (S3C_TIMER_BASE + 0x00)
-# define S3C_TCFG0_T4MASK 0xff00
-# define S3C_TCFG0_SET_PSCL234(x) ((x) << 8)
-# define S3C_TCFG0_GET_PSCL234(x) (((x) >> 8) & 0xff)
-#define S3C_TCFG1 (S3C_TIMER_BASE + 0x04)
-# define S3C_TCFG1_T4MASK 0xf0000
-# define S3C_TCFG1_SET_T4MUX(x) ((x) << 16)
-# define S3C_TCFG1_GET_T4MUX(x) (((x) >> 16) & 0xf)
-#define S3C_TCON (S3C_TIMER_BASE + 0x08)
-# define S3C_TCON_T4MASK (7 << 20)
-# define S3C_TCON_T4START (1 << 20)
-# define S3C_TCON_T4MANUALUPD (1 << 21)
-# define S3C_TCON_T4RELOAD (1 <<22)
-#define S3C_TCNTB4 (S3C_TIMER_BASE + 0x3c)
-#define S3C_TCNTO4 (S3C_TIMER_BASE + 0x40)
-
-#ifdef CONFIG_ARCH_S3C24xx
-# define TIMER_WIDTH 16
-# define TIMER_SHIFT 10
-# define PRE_MUX 3
-# define PRE_MUX_ADD 1
-static const uint32_t max = 0x0000ffff;
-#else /* for S3C64xx and S5Pxx */
-# define TIMER_WIDTH 32
-# define TIMER_SHIFT 10
-# define PRE_MUX 4
-# define PRE_MUX_ADD 0
-static const uint32_t max = ~0;
-#endif
-
-static void s3c_init_t4_clk_source(void)
-{
-	unsigned reg;
-
-	reg = readl(S3C_TCON) & ~S3C_TCON_T4MASK; /* stop timer 4 */
-	writel(reg, S3C_TCON);
-	reg = readl(S3C_TCFG0) & ~S3C_TCFG0_T4MASK;
-	reg |= S3C_TCFG0_SET_PSCL234(0); /* 0 means pre scaler is '256' */
-	writel(reg, S3C_TCFG0);
-	reg = readl(S3C_TCFG1) & ~S3C_TCFG1_T4MASK;
-	reg |= S3C_TCFG1_SET_T4MUX(PRE_MUX); /* / 16 */
-	writel(reg, S3C_TCFG1);
-}
-
-static unsigned s3c_get_t4_clk(void)
-{
-	unsigned clk = s3c_get_pclk();
-	unsigned pre = S3C_TCFG0_GET_PSCL234(readl(S3C_TCFG0)) + 1;
-	unsigned div = S3C_TCFG1_GET_T4MUX(readl(S3C_TCFG1)) + PRE_MUX_ADD;
-
-	return clk / pre / (1 << div);
-}
-
-static void s3c_timer_init(void)
-{
-	unsigned tcon;
-
-	tcon = readl(S3C_TCON) & ~S3C_TCON_T4MASK;
-
-	writel(max, S3C_TCNTB4);	/* reload value */
-	/* force a manual counter update */
-	writel(tcon | S3C_TCON_T4MANUALUPD, S3C_TCON);
-}
-
-static void s3c_timer_start(void)
-{
-	unsigned tcon;
-
-	tcon  = readl(S3C_TCON) & ~S3C_TCON_T4MANUALUPD;
-	tcon |= S3C_TCON_T4START | S3C_TCON_T4RELOAD;
-	writel(tcon, S3C_TCON);
-}
-
-static uint64_t s3c_clocksource_read(void)
-{
-	/* note: its a down counter */
-	return max - readl(S3C_TCNTO4);
-}
-
-static struct clocksource cs = {
-	.read = s3c_clocksource_read,
-	.mask = CLOCKSOURCE_MASK(TIMER_WIDTH),
-	.shift = TIMER_SHIFT,
-};
-
-static int s3c_clk_src_init(void)
-{
-	/* select its clock source first */
-	s3c_init_t4_clk_source();
-
-	s3c_timer_init();
-	s3c_timer_start();
-
-	cs.mult = clocksource_hz2mult(s3c_get_t4_clk(), cs.shift);
-
-	return init_clock(&cs);
-}
-core_initcall(s3c_clk_src_init);
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 2da875cef0..b23a41d3f9 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_SOCFPGA
 
 config ARCH_TEXT_BASE
@@ -21,6 +23,7 @@ config ARCH_SOCFPGA_CYCLONE5
 config ARCH_SOCFPGA_ARRIA10
 	bool
 	select CPU_V7
+	select ARM_USE_COMPRESSED_DTB
 	select RESET_CONTROLLER
 	select HAVE_PBL_MULTI_IMAGES
 	select OFDEVICE
@@ -34,6 +37,10 @@ config MACH_SOCFPGA_EBV_SOCRATES
 	select ARCH_SOCFPGA_CYCLONE5
 	bool "EBV Socrates"
 
+config MACH_SOCFPGA_ENCLUSTRA_AA1
+	select ARCH_SOCFPGA_ARRIA10
+	bool "Enclustra AA1"
+
 config MACH_SOCFPGA_REFLEX_ACHILLES
 	select ARCH_SOCFPGA_ARRIA10
 	bool "Reflex Achilles"
@@ -42,6 +49,10 @@ config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC
 	select ARCH_SOCFPGA_CYCLONE5
 	bool "Terasic DE0-NANO-SoC aka Atlas"
 
+config MACH_SOCFPGA_TERASIC_DE10_NANO
+	select ARCH_SOCFPGA_CYCLONE5
+	bool "Terasic DE10-NANO"
+
 config MACH_SOCFPGA_TERASIC_SOCKIT
 	select ARCH_SOCFPGA_CYCLONE5
 	bool "Terasic SoCKit"
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 3a3a2fc57d..008dbc3887 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -1,6 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o
 pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-clock-manager.o
 obj-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o
+lwl-y += cpu_init.o
 
 pbl-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-xload.o \
 				      arria10-xload-emmc.o
diff --git a/arch/arm/mach-socfpga/arria10-bootsource.c b/arch/arm/mach-socfpga/arria10-bootsource.c
index 3319dc4bf9..4aa36a7ffe 100644
--- a/arch/arm/mach-socfpga/arria10-bootsource.c
+++ b/arch/arm/mach-socfpga/arria10-bootsource.c
@@ -15,8 +15,8 @@
 #include <bootsource.h>
 #include <init.h>
 #include <io.h>
-#include <mach/generic.h>
-#include <mach/arria10-system-manager.h>
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/arria10-system-manager.h>
 
 enum bootsource arria10_get_bootsource(void) {
 	enum bootsource src = BOOTSOURCE_UNKNOWN;
@@ -55,8 +55,7 @@ static int arria10_boot_save_loc(void)
 
 	src = arria10_get_bootsource();
 
-	bootsource_set(src);
-	bootsource_set_instance(0);
+	bootsource_set_raw(src, 0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-socfpga/arria10-clock-manager.c b/arch/arm/mach-socfpga/arria10-clock-manager.c
index 8052afe2d8..372617acb9 100644
--- a/arch/arm/mach-socfpga/arria10-clock-manager.c
+++ b/arch/arm/mach-socfpga/arria10-clock-manager.c
@@ -6,9 +6,9 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <mach/generic.h>
-#include <mach/arria10-regs.h>
-#include <mach/arria10-clock-manager.h>
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-clock-manager.h>
 
 static const struct arria10_clock_manager *arria10_clkmgr_base =
 	(void *)ARRIA10_CLKMGR_ADDR;
diff --git a/arch/arm/mach-socfpga/arria10-generic.c b/arch/arm/mach-socfpga/arria10-generic.c
index 38558309f8..fc2ef3e292 100644
--- a/arch/arm/mach-socfpga/arria10-generic.c
+++ b/arch/arm/mach-socfpga/arria10-generic.c
@@ -1,11 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <io.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/generic.h>
-#include <mach/arria10-reset-manager.h>
-#include <mach/arria10-system-manager.h>
-#include <mach/arria10-regs.h>
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/arria10-reset-manager.h>
+#include <mach/socfpga/arria10-system-manager.h>
+#include <mach/socfpga/arria10-regs.h>
 
 /* Some initialization for the EMAC */
 static void arria10_init_emac(void)
diff --git a/arch/arm/mach-socfpga/arria10-init.c b/arch/arm/mach-socfpga/arria10-init.c
index 2fa44c21c5..d1586c2d40 100644
--- a/arch/arm/mach-socfpga/arria10-init.c
+++ b/arch/arm/mach-socfpga/arria10-init.c
@@ -6,12 +6,12 @@
 
 #include <common.h>
 #include <debug_ll.h>
-#include <mach/arria10-regs.h>
-#include <mach/arria10-clock-manager.h>
-#include <mach/arria10-pinmux.h>
-#include <mach/arria10-reset-manager.h>
-#include <mach/arria10-system-manager.h>
-#include <mach/generic.h>
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-clock-manager.h>
+#include <mach/socfpga/arria10-pinmux.h>
+#include <mach/socfpga/arria10-reset-manager.h>
+#include <mach/socfpga/arria10-system-manager.h>
+#include <mach/socfpga/generic.h>
 #include <asm/io.h>
 #include <asm/cache-l2x0.h>
 #include <asm/errata.h>
@@ -174,7 +174,7 @@ void arria10_init(struct arria10_mainpll_cfg *mainpll,
 	 * Enable address filtering (Bit[0])
 	 */
 	writel(0x00000001, ARRIA10_MPUL2_ADRFLTR_START);
-	writel(0x00000002, ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE);
+	writel(0x00000000, ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE);
 
 	arria10_reset_peripherals();
 
diff --git a/arch/arm/mach-socfpga/arria10-reset-manager.c b/arch/arm/mach-socfpga/arria10-reset-manager.c
index 76adc1702c..05440cf903 100644
--- a/arch/arm/mach-socfpga/arria10-reset-manager.c
+++ b/arch/arm/mach-socfpga/arria10-reset-manager.c
@@ -8,11 +8,11 @@
 #include <bootsource.h>
 #include <errno.h>
 #include <io.h>
-#include <mach/generic.h>
-#include <mach/arria10-pinmux.h>
-#include <mach/arria10-regs.h>
-#include <mach/arria10-reset-manager.h>
-#include <mach/arria10-system-manager.h>
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/arria10-pinmux.h>
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-reset-manager.h>
+#include <mach/socfpga/arria10-system-manager.h>
 
 void arria10_reset_peripherals(void)
 {
diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
index 35c355df71..70d4edd973 100644
--- a/arch/arm/mach-socfpga/arria10-sdram.c
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -7,10 +7,10 @@
 #include <common.h>
 #include <io.h>
 #include <debug_ll.h>
-#include <mach/generic.h>
-#include <mach/arria10-sdram.h>
-#include <mach/arria10-regs.h>
-#include <mach/arria10-reset-manager.h>
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/arria10-sdram.h>
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-reset-manager.h>
 
 
 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
@@ -468,6 +468,18 @@ static void arria10_sdram_mmr_init(void)
 	}
 }
 
+static void arria10_f2sdram_bridges_reset(void)
+{
+	uint32_t val;
+
+	/* Release F2SDRAM bridges from reset */
+	val = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
+	val &= ~(ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0 |
+		ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1 |
+		ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2);
+	writel(val, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
+}
+
 static int arria10_sdram_firewall_setup(void)
 {
 	uint32_t mpu_en = 0;
@@ -486,7 +498,7 @@ static int arria10_sdram_firewall_setup(void)
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR);
 	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR);
 
-	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN;
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN;
 	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
 
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR);
@@ -494,7 +506,7 @@ static int arria10_sdram_firewall_setup(void)
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR);
 	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR);
 
-	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN;
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN;
 	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
 
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR);
@@ -502,7 +514,7 @@ static int arria10_sdram_firewall_setup(void)
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR);
 	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR);
 
-	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN;
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN;
 	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
 
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR);
@@ -512,6 +524,8 @@ static int arria10_sdram_firewall_setup(void)
 	writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR);
 	writel(ARRIA10_NOC_FW_DDR_L3_HPSREG0EN, ARRIA10_NOC_FW_DDR_L3_EN);
 
+	arria10_f2sdram_bridges_reset();
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-socfpga/arria10-xload-emmc.c b/arch/arm/mach-socfpga/arria10-xload-emmc.c
index dcc38cf4a2..ed24faf9bf 100644
--- a/arch/arm/mach-socfpga/arria10-xload-emmc.c
+++ b/arch/arm/mach-socfpga/arria10-xload-emmc.c
@@ -1,10 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <init.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
-#include <mach/arria10-regs.h>
-#include <mach/arria10-system-manager.h>
-#include <mach/arria10-xload.h>
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-system-manager.h>
+#include <mach/socfpga/arria10-xload.h>
 #include <mci.h>
 #include "../../../drivers/mci/sdhci.h"
 #include "../../../drivers/mci/dw_mmc.h"
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index 6f137e300e..db3cc209ee 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <asm/sections.h>
 #include <debug_ll.h>
@@ -6,12 +8,12 @@
 #include <filetype.h>
 #include <io.h>
 #include <asm/unaligned.h>
-#include <mach/arria10-pinmux.h>
-#include <mach/arria10-regs.h>
-#include <mach/arria10-system-manager.h>
-#include <mach/arria10-fpga.h>
-#include <mach/arria10-xload.h>
-#include <mach/generic.h>
+#include <mach/socfpga/arria10-pinmux.h>
+#include <mach/socfpga/arria10-regs.h>
+#include <mach/socfpga/arria10-system-manager.h>
+#include <mach/socfpga/arria10-fpga.h>
+#include <mach/socfpga/arria10-xload.h>
+#include <mach/socfpga/generic.h>
 #include <linux/sizes.h>
 
 int a10_update_bits(unsigned int reg, unsigned int mask,
@@ -136,7 +138,7 @@ static int a10_fpga_init(void *buf)
 {
 	uint32_t stat, mask;
 	uint32_t val;
-	uint32_t timeout;
+	int timeout;
 
 	val = CFGWDTH_32 << A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT;
 	a10_update_bits(A10_FPGAMGR_IMGCFG_CTL_02_OFST,
@@ -351,17 +353,9 @@ int arria10_prepare_mmc(int barebox_part, int rbf_part)
 	return 0;
 }
 
-int arria10_load_fpga(int offset, int bitstream_size)
+static inline int __arria10_load_fpga(void *buf, uint32_t count, uint32_t size)
 {
-	void *buf = (void *)0xffe00000 + SZ_256K - 256 - SZ_16K;
 	int ret;
-	uint32_t count;
-	uint32_t size = bitstream_size / SECTOR_SIZE;
-
-	if (offset)
-		offset = offset / SECTOR_SIZE;
-
-	count = offset;
 
 	arria10_read_blocks(buf, count + bitstream.first_sec, SZ_16K);
 
@@ -369,23 +363,56 @@ int arria10_load_fpga(int offset, int bitstream_size)
 
 	ret = a10_fpga_init(buf);
 	if (ret)
-		hang();
+		return -EAGAIN;
 
 	while (count <= size) {
 		ret = a10_fpga_write(buf, SZ_16K);
 		if (ret == -ENOSPC)
-			break;
+			return -EAGAIN;
+
 		count += SZ_16K / SECTOR_SIZE;
 		ret = arria10_read_blocks(buf, count, SZ_16K);
+		// Reading failed, consider this a failed attempt to configure the FPGA and retry
+		if (ret)
+			return -EAGAIN;
 	}
 
 	ret = a10_fpga_write_complete();
 	if (ret)
-		hang();
+		return -EAGAIN;
 
 	return 0;
 }
 
+int arria10_load_fpga(int offset, int bitstream_size)
+{
+	int ret;
+	void *buf = (void *)0xffe00000 + SZ_256K - 256 - SZ_16K;
+	uint32_t count;
+	uint32_t size = bitstream_size / SECTOR_SIZE;
+	uint32_t retryCount;
+
+	if (offset)
+		offset = offset / SECTOR_SIZE;
+
+	/* Up to 4 retries have been seen on the Enclustra Mercury AA1+ board, as
+	 * FPGA configuration is mandatory to be able to continue the boot, take
+	 * some margin and try up to 10 times
+	 */
+	for (retryCount = 0; retryCount < 10; ++retryCount) {
+		count = offset;
+
+		ret = __arria10_load_fpga(buf, count, size);
+		if (!ret)
+			return 0;
+		else if (ret == -EAGAIN)
+			continue;
+	}
+
+	hang();
+	return -EIO;
+}
+
 void arria10_start_image(int offset)
 {
 	void *buf = (void *)0x0;
diff --git a/arch/arm/mach-socfpga/cpu_init.c b/arch/arm/mach-socfpga/cpu_init.c
new file mode 100644
index 0000000000..73b69c34c5
--- /dev/null
+++ b/arch/arm/mach-socfpga/cpu_init.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/errata.h>
+#include <mach/socfpga/init.h>
+
+void arria10_cpu_lowlevel_init(void)
+{
+	enable_arm_errata_794072_war();
+	enable_arm_errata_845369_war();
+}
diff --git a/arch/arm/mach-socfpga/cyclone5-bootsource.c b/arch/arm/mach-socfpga/cyclone5-bootsource.c
index 717a003425..d69eb65ce4 100644
--- a/arch/arm/mach-socfpga/cyclone5-bootsource.c
+++ b/arch/arm/mach-socfpga/cyclone5-bootsource.c
@@ -16,9 +16,9 @@
 #include <environment.h>
 #include <init.h>
 #include <io.h>
-#include <mach/cyclone5-system-manager.h>
-#include <mach/cyclone5-regs.h>
-#include <mach/arria10-system-manager.h>
+#include <mach/socfpga/cyclone5-system-manager.h>
+#include <mach/socfpga/cyclone5-regs.h>
+#include <mach/socfpga/arria10-system-manager.h>
 
 #define CYCLONE5_SYSMGR_BOOTINFO	0x14
 
@@ -50,8 +50,7 @@ static int cyclone5_boot_save_loc(void)
 		break;
 	}
 
-	bootsource_set(src);
-	bootsource_set_instance(0);
+	bootsource_set_raw(src, 0);
 
 	return 0;
 }
@@ -84,8 +83,7 @@ static int arria10_boot_save_loc(void)
 		break;
 	}
 
-	bootsource_set(src);
-	bootsource_set_instance(0);
+	bootsource_set_raw(src, 0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-socfpga/cyclone5-clock-manager.c b/arch/arm/mach-socfpga/cyclone5-clock-manager.c
index 79c8b6bf28..06ca1af22c 100644
--- a/arch/arm/mach-socfpga/cyclone5-clock-manager.c
+++ b/arch/arm/mach-socfpga/cyclone5-clock-manager.c
@@ -17,9 +17,9 @@
 
 #include <common.h>
 #include <io.h>
-#include <mach/cyclone5-clock-manager.h>
-#include <mach/cyclone5-regs.h>
-#include <mach/generic.h>
+#include <mach/socfpga/cyclone5-clock-manager.h>
+#include <mach/socfpga/cyclone5-regs.h>
+#include <mach/socfpga/generic.h>
 
 static inline void cm_wait_for_lock(void __iomem *cm, uint32_t mask)
 {
diff --git a/arch/arm/mach-socfpga/cyclone5-freeze-controller.c b/arch/arm/mach-socfpga/cyclone5-freeze-controller.c
index 87160161b0..53fb6a2b50 100644
--- a/arch/arm/mach-socfpga/cyclone5-freeze-controller.c
+++ b/arch/arm/mach-socfpga/cyclone5-freeze-controller.c
@@ -17,8 +17,8 @@
 
 #include <common.h>
 #include <io.h>
-#include <mach/generic.h>
-#include <mach/cyclone5-freeze-controller.h>
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/cyclone5-freeze-controller.h>
 
 #define SYSMGR_FRZCTRL_LOOP_PARAM       (1000)
 #define SYSMGR_FRZCTRL_DELAY_LOOP_PARAM (10)
diff --git a/arch/arm/mach-socfpga/cyclone5-generic.c b/arch/arm/mach-socfpga/cyclone5-generic.c
index dfb1f49e4d..0cb46b51e9 100644
--- a/arch/arm/mach-socfpga/cyclone5-generic.c
+++ b/arch/arm/mach-socfpga/cyclone5-generic.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
 #include <malloc.h>
 #include <envfs.h>
@@ -10,11 +12,11 @@
 #include <linux/stat.h>
 #include <linux/sizes.h>
 #include <asm/memory.h>
-#include <mach/cyclone5-system-manager.h>
-#include <mach/cyclone5-reset-manager.h>
-#include <mach/cyclone5-regs.h>
-#include <mach/generic.h>
-#include <mach/nic301.h>
+#include <mach/socfpga/cyclone5-system-manager.h>
+#include <mach/socfpga/cyclone5-reset-manager.h>
+#include <mach/socfpga/cyclone5-regs.h>
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/nic301.h>
 #include <platform_data/dw_mmc.h>
 #include <platform_data/serial-ns16550.h>
 #include <platform_data/cadence_qspi.h>
@@ -60,7 +62,7 @@ static struct cadence_qspi_platform_data qspi_pdata = {
 static void add_cadence_qspi_device(int id, resource_size_t ctrl,
 				    resource_size_t data, void *pdata)
 {
-	struct device_d *dev;
+	struct device *dev;
 	struct resource *res;
 
 	res = xzalloc(sizeof(struct resource) * 2);
@@ -100,7 +102,7 @@ static struct NS16550_plat uart_pdata = {
 
 void socfpga_cyclone5_uart_init(void)
 {
-	struct device_d *dev;
+	struct device *dev;
 
 	clks[uart] = clk_fixed("uart", 100000000);
 	clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL);
@@ -113,7 +115,7 @@ void socfpga_cyclone5_uart_init(void)
 
 void socfpga_cyclone5_timer_init(void)
 {
-	struct device_d *dev;
+	struct device *dev;
 
 	clks[timer] = clk_fixed("timer", 200000000);
 	clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL);
@@ -126,7 +128,8 @@ void socfpga_cyclone5_timer_init(void)
 static int socfpga_detect_sdram(void)
 {
 	void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS;
-	uint32_t dramaddrw, ctrlwidth, memsize;
+	uint32_t dramaddrw, ctrlwidth;
+	uint64_t memsize;
 	int colbits, rowbits, bankbits;
 	int width_bytes;
 
@@ -151,12 +154,20 @@ static int socfpga_detect_sdram(void)
 		break;
 	}
 
-	memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes;
+	memsize = (1ULL << colbits) * (1ULL << rowbits) * (1ULL << bankbits) *
+		  width_bytes;
 
-	pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n",
+	pr_debug(
+		"%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08llx\n",
 			__func__, colbits, rowbits, bankbits, width_bytes, memsize);
 
-	arm_add_mem_device("ram0", 0x0, memsize);
+	/* To work around an erratum in the dram controller, the previous booting
+	 * stage may have increased the amount of rows to fake having 4G of RAM. In
+	 * that case, we assume the previous booting stage will have fixed up a
+	 * proper memory size into the device tree and don't add a bank here */
+	if (memsize < SZ_4G) {
+		arm_add_mem_device("ram0", 0x0, memsize);
+	}
 
 	return 0;
 }
diff --git a/arch/arm/mach-socfpga/cyclone5-init.c b/arch/arm/mach-socfpga/cyclone5-init.c
index 412808b841..79a9b15d87 100644
--- a/arch/arm/mach-socfpga/cyclone5-init.c
+++ b/arch/arm/mach-socfpga/cyclone5-init.c
@@ -1,13 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <debug_ll.h>
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/cyclone5-freeze-controller.h>
-#include <mach/cyclone5-system-manager.h>
-#include <mach/cyclone5-clock-manager.h>
-#include <mach/cyclone5-reset-manager.h>
-#include <mach/cyclone5-scan-manager.h>
-#include <mach/generic.h>
+#include <mach/socfpga/cyclone5-freeze-controller.h>
+#include <mach/socfpga/cyclone5-system-manager.h>
+#include <mach/socfpga/cyclone5-clock-manager.h>
+#include <mach/socfpga/cyclone5-reset-manager.h>
+#include <mach/socfpga/cyclone5-scan-manager.h>
+#include <mach/socfpga/generic.h>
 
 void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
 			   struct socfpga_io_config *io_config)
diff --git a/arch/arm/mach-socfpga/cyclone5-reset-manager.c b/arch/arm/mach-socfpga/cyclone5-reset-manager.c
index 4ee90b1bb0..5ddf379e3d 100644
--- a/arch/arm/mach-socfpga/cyclone5-reset-manager.c
+++ b/arch/arm/mach-socfpga/cyclone5-reset-manager.c
@@ -19,8 +19,8 @@
 #include <io.h>
 #include <init.h>
 #include <restart.h>
-#include <mach/cyclone5-regs.h>
-#include <mach/cyclone5-reset-manager.h>
+#include <mach/socfpga/cyclone5-regs.h>
+#include <mach/socfpga/cyclone5-reset-manager.h>
 
 /* Write the reset manager register to cause reset */
 static void __noreturn socfpga_restart_soc(struct restart_handler *rst)
diff --git a/arch/arm/mach-socfpga/cyclone5-scan-manager.c b/arch/arm/mach-socfpga/cyclone5-scan-manager.c
index cf076c3885..0978ed832f 100644
--- a/arch/arm/mach-socfpga/cyclone5-scan-manager.c
+++ b/arch/arm/mach-socfpga/cyclone5-scan-manager.c
@@ -17,8 +17,8 @@
 
 #include <common.h>
 #include <io.h>
-#include <mach/cyclone5-freeze-controller.h>
-#include <mach/cyclone5-scan-manager.h>
+#include <mach/socfpga/cyclone5-freeze-controller.h>
+#include <mach/socfpga/cyclone5-scan-manager.h>
 
 /*
  * @fn scan_mgr_io_scan_chain_engine_is_idle
diff --git a/arch/arm/mach-socfpga/cyclone5-system-manager.c b/arch/arm/mach-socfpga/cyclone5-system-manager.c
index 7e86692c39..aab2813da5 100644
--- a/arch/arm/mach-socfpga/cyclone5-system-manager.c
+++ b/arch/arm/mach-socfpga/cyclone5-system-manager.c
@@ -17,8 +17,8 @@
 
 #include <common.h>
 #include <io.h>
-#include <mach/cyclone5-system-manager.h>
-#include <mach/cyclone5-regs.h>
+#include <mach/socfpga/cyclone5-system-manager.h>
+#include <mach/socfpga/cyclone5-regs.h>
 
 void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num)
 {
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
deleted file mode 100644
index c0a57439af..0000000000
--- a/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef	_ARRIA10_CLOCK_MANAGER_H_
-#define	_ARRIA10_CLOCK_MANAGER_H_
-
-struct arria10_clock_manager {
-	/* clkmgr */
-	volatile uint32_t  ctrl;
-	volatile uint32_t  intr;
-	volatile uint32_t  intrs;
-	volatile uint32_t  intrr;
-	volatile uint32_t  intren;
-	volatile uint32_t  intrens;
-	volatile uint32_t  intrenr;
-	volatile uint32_t  stat;
-	volatile uint32_t  testioctrl;
-	volatile uint32_t  _pad_0x24_0x40[7];
-
-	/* mainpllgrp*/
-	volatile uint32_t  main_pll_vco0;
-	volatile uint32_t  main_pll_vco1;
-	volatile uint32_t  main_pll_en;
-	volatile uint32_t  main_pll_ens;
-	volatile uint32_t  main_pll_enr;
-	volatile uint32_t  main_pll_bypass;
-	volatile uint32_t  main_pll_bypasss;
-	volatile uint32_t  main_pll_bypassr;
-	volatile uint32_t  main_pll_mpuclk;
-	volatile uint32_t  main_pll_nocclk;
-	volatile uint32_t  main_pll_cntr2clk;
-	volatile uint32_t  main_pll_cntr3clk;
-	volatile uint32_t  main_pll_cntr4clk;
-	volatile uint32_t  main_pll_cntr5clk;
-	volatile uint32_t  main_pll_cntr6clk;
-	volatile uint32_t  main_pll_cntr7clk;
-	volatile uint32_t  main_pll_cntr8clk;
-	volatile uint32_t  main_pll_cntr9clk;
-	volatile uint32_t  main_pll__pad_0x48_0x5b[5];
-	volatile uint32_t  main_pll_cntr15clk;
-	volatile uint32_t  main_pll_outrst;
-	volatile uint32_t  main_pll_outrststat;
-	volatile uint32_t  main_pll_nocdiv;
-	volatile uint32_t  main_pll__pad_0x6c_0x80[5];
-
-	/* perpllgrp*/
-	volatile uint32_t  per_pll_vco0;
-	volatile uint32_t  per_pll_vco1;
-	volatile uint32_t  per_pll_en;
-	volatile uint32_t  per_pll_ens;
-	volatile uint32_t  per_pll_enr;
-	volatile uint32_t  per_pll_bypass;
-	volatile uint32_t  per_pll_bypasss;
-	volatile uint32_t  per_pll_bypassr;
-	volatile uint32_t  per_pll__pad_0x20_0x27[2];
-	volatile uint32_t  per_pll_cntr2clk;
-	volatile uint32_t  per_pll_cntr3clk;
-	volatile uint32_t  per_pll_cntr4clk;
-	volatile uint32_t  per_pll_cntr5clk;
-	volatile uint32_t  per_pll_cntr6clk;
-	volatile uint32_t  per_pll_cntr7clk;
-	volatile uint32_t  per_pll_cntr8clk;
-	volatile uint32_t  per_pll_cntr9clk;
-	volatile uint32_t  per_pll__pad_0x48_0x5f[6];
-	volatile uint32_t  per_pll_outrst;
-	volatile uint32_t  per_pll_outrststat;
-	volatile uint32_t  per_pll_emacctl;
-	volatile uint32_t  per_pll_gpiodiv;
-	volatile uint32_t  per_pll__pad_0x70_0x80[4];
-};
-
-struct arria10_mainpll_cfg {
-	uint32_t vco0_psrc;
-	uint32_t vco1_denom;
-	uint32_t vco1_numer;
-	uint32_t mpuclk;
-	uint32_t mpuclk_cnt;
-	uint32_t mpuclk_src;
-	uint32_t nocclk;
-	uint32_t nocclk_cnt;
-	uint32_t nocclk_src;
-	uint32_t cntr2clk_cnt;
-	uint32_t cntr3clk_cnt;
-	uint32_t cntr4clk_cnt;
-	uint32_t cntr5clk_cnt;
-	uint32_t cntr6clk_cnt;
-	uint32_t cntr7clk_cnt;
-	uint32_t cntr7clk_src;
-	uint32_t cntr8clk_cnt;
-	uint32_t cntr9clk_cnt;
-	uint32_t cntr9clk_src;
-	uint32_t cntr15clk_cnt;
-	uint32_t nocdiv_l4mainclk;
-	uint32_t nocdiv_l4mpclk;
-	uint32_t nocdiv_l4spclk;
-	uint32_t nocdiv_csatclk;
-	uint32_t nocdiv_cstraceclk;
-	uint32_t nocdiv_cspdbgclk;
-};
-
-struct arria10_perpll_cfg {
-	uint32_t vco0_psrc;
-	uint32_t vco1_denom;
-	uint32_t vco1_numer;
-	uint32_t cntr2clk_cnt;
-	uint32_t cntr2clk_src;
-	uint32_t cntr3clk_cnt;
-	uint32_t cntr3clk_src;
-	uint32_t cntr4clk_cnt;
-	uint32_t cntr4clk_src;
-	uint32_t cntr5clk_cnt;
-	uint32_t cntr5clk_src;
-	uint32_t cntr6clk_cnt;
-	uint32_t cntr6clk_src;
-	uint32_t cntr7clk_cnt;
-	uint32_t cntr8clk_cnt;
-	uint32_t cntr8clk_src;
-	uint32_t cntr9clk_cnt;
-	uint32_t cntr9clk_src;
-	uint32_t emacctl_emac0sel;
-	uint32_t emacctl_emac1sel;
-	uint32_t emacctl_emac2sel;
-	uint32_t gpiodiv_gpiodbclk;
-};
-
-extern int arria10_cm_basic_init(struct arria10_mainpll_cfg *mainpll_cfg,
-				 struct arria10_perpll_cfg *perpll_cfg);
-unsigned int arria10_cm_get_mmc_controller_clk_hz(void);
-extern unsigned int cm_get_mmc_controller_clk_hz(void);
-extern void arria10_cm_use_intosc(void);
-extern uint32_t cm_l4_main_clk_hz;
-extern uint32_t cm_l4_sp_clk_hz;
-extern uint32_t cm_l4_mp_clk_hz;
-extern uint32_t cm_l4_sys_free_clk_hz;
-
-#define ARRIA10_CLKMGR_ALTERAGRP_MPU_CLK_OFFSET			0x140
-#define ARRIA10_CLKMGR_MAINPLL_NOC_CLK_OFFSET			0x144
-
-/* value */
-#define ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET			0x0000003f
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_RESET			0x00010053
-#define ARRIA10_CLKMGR_MAINPLL_VCO1_RESET			0x00010001
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC			0x0
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC		0x1
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S			0x2
-#define ARRIA10_CLKMGR_PERPLL_BYPASS_RESET			0x000000ff
-#define ARRIA10_CLKMGR_PERPLL_VCO0_RESET			0x00010053
-#define ARRIA10_CLKMGR_PERPLL_VCO1_RESET			0x00010001
-#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC			0x0
-#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC		0x1
-#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S			0x2
-#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN			0x3
-
-/* mask */
-#define ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK		0x00000040
-#define ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK	0x00000080
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK		0x00000001
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK		0x00000002
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_EN_SET_MSK			0x00000004
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK		0x00000008
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK		0x00000010
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_MSK			0x00000003
-#define ARRIA10_CLKMGR_MAINPLL_VCO1_NUMER_MSK			0x00001fff
-#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_MSK			0x0000003f
-#define ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK			0x000003ff
-#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK			0x000003ff
-#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN			0
-#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI			1
-#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_OSC1			2
-#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC		3
-#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_FPGA			4
-#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_MSK			0x00000003
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK			0x000003ff
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MSK			0x00000007
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN			0
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI			1
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_OSC1			2
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC		3
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_FPGA			4
-#define ARRIA10_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK			0x00000001
-#define ARRIA10_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK	0x00000100
-#define ARRIA10_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK		0x00000200
-#define ARRIA10_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK		0x00020000
-#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK		0x00000800
-#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK	0x00000400
-#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK		0x00000200
-#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK	0x00000100
-#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK		0x00000008
-#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK		0x00000004
-#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK	0x00000001
-#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK	0x00000002
-#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK		0x00000001
-#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK	0x00000300
-#define ARRIA10_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK		0x00000001
-#define ARRIA10_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK		0x00000002
-#define ARRIA10_CLKMGR_PERPLL_VCO0_EN_SET_MSK			0x00000004
-#define ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK		0x00000008
-#define ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK		0x00000010
-#define ARRIA10_CLKMGR_PERPLL_EN_RESET				0x00000f7f
-#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MSK			0x00000003
-#define ARRIA10_CLKMGR_PERPLL_VCO1_NUMER_MSK			0x00001fff
-#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_MSK			0x0000003f
-#define ARRIA10_CLKMGR_PERPLL_CNTRCLK_MSK			0x000003ff
-
-#define ARRIA10_CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000020
-#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MSK			0x00000007
-#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MAIN			0
-#define ARRIA10_CLKMGR_PERPLLGRP_SRC_PERI			1
-#define ARRIA10_CLKMGR_PERPLLGRP_SRC_OSC1			2
-#define ARRIA10_CLKMGR_PERPLLGRP_SRC_INTOSC			3
-#define ARRIA10_CLKMGR_PERPLLGRP_SRC_FPGA			4
-
-/* bit shifting macro */
-#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB			8
-#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB			16
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB		16
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB		0
-#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB		8
-#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB		16
-#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB		24
-#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB		26
-#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB		28
-#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB		16
-#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB			16
-#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB			8
-#define ARRIA10_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB			16
-#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB		26
-#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB		27
-#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB		28
-
-/* PLL ramping work around */
-#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ		900000000
-#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ		300000000
-#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ		100000000
-#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ		 33000000
-
-#endif /* _ARRIA10_CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-fpga.h b/arch/arm/mach-socfpga/include/mach/arria10-fpga.h
deleted file mode 100644
index 2e29c864f6..0000000000
--- a/arch/arm/mach-socfpga/include/mach/arria10-fpga.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * FPGA Manager Driver for Altera Arria10 SoCFPGA
- *
- * Copyright (C) 2015-2016 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef  __A10_FPGAMGR_H__
-#define	__A10_FPGAMGR_H__
-
-#include <linux/bitops.h>
-#include <mach/arria10-regs.h>
-
-#define A10_FPGAMGR_DCLKCNT_OFST				0x08
-#define A10_FPGAMGR_DCLKSTAT_OFST				0x0c
-#define A10_FPGAMGR_IMGCFG_CTL_00_OFST				0x70
-#define A10_FPGAMGR_IMGCFG_CTL_01_OFST				0x74
-#define A10_FPGAMGR_IMGCFG_CTL_02_OFST				0x78
-#define A10_FPGAMGR_IMGCFG_STAT_OFST				0x80
-
-#define A10_FPGAMGR_DCLKSTAT_DCLKDONE				BIT(0)
-
-#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG		BIT(0)
-#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS		BIT(1)
-#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE		BIT(2)
-#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG			BIT(8)
-#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE		BIT(16)
-#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE		BIT(24)
-
-#define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG		BIT(0)
-#define A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST		BIT(16)
-#define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE			BIT(24)
-
-#define A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL			BIT(0)
-#define A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA			BIT(8)
-#define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK			(BIT(16) | BIT(17))
-#define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT			16
-#define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH			BIT(24)
-#define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT		24
-
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR			BIT(0)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE		BIT(1)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE			BIT(2)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN			BIT(4)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN			BIT(6)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE			BIT(7)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY			BIT(9)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE			BIT(10)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR			BIT(11)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN			BIT(12)
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK			(BIT(16) | BIT(17) | BIT(18))
-#define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT		        16
-
-/* FPGA CD Ratio Value */
-#define CDRATIO_x1						0x0
-#define CDRATIO_x2						0x1
-#define CDRATIO_x4						0x2
-#define CDRATIO_x8						0x3
-
-/* Configuration width 16/32 bit */
-#define CFGWDTH_32						1
-#define CFGWDTH_16						0
-
-static inline int a10_wait_for_usermode(int timeout) {
-	while ((readl(ARRIA10_FPGAMGRREGS_ADDR +
-		      A10_FPGAMGR_IMGCFG_STAT_OFST) &
-		(A10_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE |
-		 A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE)) == 0)
-		if (timeout-- <= 0)
-			return -ETIMEDOUT;
-
-	return 0;
-}
-
-#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h b/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
deleted file mode 100644
index 979e4769db..0000000000
--- a/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- *  Copyright (C) 2017 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ARRIA10_PINMUX_H_
-#define _ARRIA10_PINMUX_H_
-
-#include <mach/arria10-regs.h>
-
-#define ARRIA10_PINMUX_SHARED_IO_Q1_1_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x00
-#define ARRIA10_PINMUX_SHARED_IO_Q1_2_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x04
-#define ARRIA10_PINMUX_SHARED_IO_Q1_3_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x08
-#define ARRIA10_PINMUX_SHARED_IO_Q1_4_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x0c
-#define ARRIA10_PINMUX_SHARED_IO_Q1_5_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x10
-#define ARRIA10_PINMUX_SHARED_IO_Q1_6_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x14
-#define ARRIA10_PINMUX_SHARED_IO_Q1_7_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x18
-#define ARRIA10_PINMUX_SHARED_IO_Q1_8_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x1c
-#define ARRIA10_PINMUX_SHARED_IO_Q1_9_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x20
-#define ARRIA10_PINMUX_SHARED_IO_Q1_10_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x24
-#define ARRIA10_PINMUX_SHARED_IO_Q1_11_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x28
-#define ARRIA10_PINMUX_SHARED_IO_Q1_12_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x2c
-#define ARRIA10_PINMUX_SHARED_IO_Q2_1_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x30
-#define ARRIA10_PINMUX_SHARED_IO_Q2_2_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x34
-#define ARRIA10_PINMUX_SHARED_IO_Q2_3_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x38
-#define ARRIA10_PINMUX_SHARED_IO_Q2_4_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x3c
-#define ARRIA10_PINMUX_SHARED_IO_Q2_5_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x40
-#define ARRIA10_PINMUX_SHARED_IO_Q2_6_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x44
-#define ARRIA10_PINMUX_SHARED_IO_Q2_7_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x48
-#define ARRIA10_PINMUX_SHARED_IO_Q2_8_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x4c
-#define ARRIA10_PINMUX_SHARED_IO_Q2_9_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x50
-#define ARRIA10_PINMUX_SHARED_IO_Q2_10_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x54
-#define ARRIA10_PINMUX_SHARED_IO_Q2_11_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x58
-#define ARRIA10_PINMUX_SHARED_IO_Q2_12_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x5c
-#define ARRIA10_PINMUX_SHARED_IO_Q3_1_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x60
-#define ARRIA10_PINMUX_SHARED_IO_Q3_2_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x64
-#define ARRIA10_PINMUX_SHARED_IO_Q3_3_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x68
-#define ARRIA10_PINMUX_SHARED_IO_Q3_4_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x6c
-#define ARRIA10_PINMUX_SHARED_IO_Q3_5_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x70
-#define ARRIA10_PINMUX_SHARED_IO_Q3_6_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x74
-#define ARRIA10_PINMUX_SHARED_IO_Q3_7_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x78
-#define ARRIA10_PINMUX_SHARED_IO_Q3_8_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x7c
-#define ARRIA10_PINMUX_SHARED_IO_Q3_9_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x80
-#define ARRIA10_PINMUX_SHARED_IO_Q3_10_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x84
-#define ARRIA10_PINMUX_SHARED_IO_Q3_11_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x88
-#define ARRIA10_PINMUX_SHARED_IO_Q3_12_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x8c
-#define ARRIA10_PINMUX_SHARED_IO_Q4_1_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x90
-#define ARRIA10_PINMUX_SHARED_IO_Q4_2_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x94
-#define ARRIA10_PINMUX_SHARED_IO_Q4_3_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x98
-#define ARRIA10_PINMUX_SHARED_IO_Q4_4_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x9c
-#define ARRIA10_PINMUX_SHARED_IO_Q4_5_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa0
-#define ARRIA10_PINMUX_SHARED_IO_Q4_6_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa4
-#define ARRIA10_PINMUX_SHARED_IO_Q4_7_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa8
-#define ARRIA10_PINMUX_SHARED_IO_Q4_8_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xac
-#define ARRIA10_PINMUX_SHARED_IO_Q4_9_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb0
-#define ARRIA10_PINMUX_SHARED_IO_Q4_10_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb4
-#define ARRIA10_PINMUX_SHARED_IO_Q4_11_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb8
-#define ARRIA10_PINMUX_SHARED_IO_Q4_12_ADDR	ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xbc
-
-#define ARRIA10_PINMUX_SHARED_IO_Q1_I2C		0
-#define ARRIA10_PINMUX_SHARED_IO_Q1_EMAC	1
-#define ARRIA10_PINMUX_SHARED_IO_Q1_SPIS	2
-#define ARRIA10_PINMUX_SHARED_IO_Q1_SPIM	3
-#define ARRIA10_PINMUX_SHARED_IO_Q1_SDMMC	4
-#define ARRIA10_PINMUX_SHARED_IO_Q1_USB		8
-#define ARRIA10_PINMUX_SHARED_IO_Q1_QSPI	12
-#define ARRIA10_PINMUX_SHARED_IO_Q1_UART	13
-#define ARRIA10_PINMUX_SHARED_IO_Q1_NAND	14
-#define ARRIA10_PINMUX_SHARED_IO_Q1_GPIO	15
-
-#define ARRIA10_PINMUX_SHARED_IO_Q2_I2C		0
-#define ARRIA10_PINMUX_SHARED_IO_Q2_SPIS	2
-#define ARRIA10_PINMUX_SHARED_IO_Q2_SPIM	3
-#define ARRIA10_PINMUX_SHARED_IO_Q2_EMAC	4
-#define ARRIA10_PINMUX_SHARED_IO_Q2_USB		8
-#define ARRIA10_PINMUX_SHARED_IO_Q2_UART	13
-#define ARRIA10_PINMUX_SHARED_IO_Q2_NAND	14
-#define ARRIA10_PINMUX_SHARED_IO_Q2_GPIO	15
-
-#define ARRIA10_PINMUX_SHARED_IO_Q3_I2C		0
-#define ARRIA10_PINMUX_SHARED_IO_Q3_EMAC0	1
-#define ARRIA10_PINMUX_SHARED_IO_Q3_SPIS	2
-#define ARRIA10_PINMUX_SHARED_IO_Q3_SPIM	3
-#define ARRIA10_PINMUX_SHARED_IO_Q3_EMAC1	8
-#define ARRIA10_PINMUX_SHARED_IO_Q3_UART	13
-#define ARRIA10_PINMUX_SHARED_IO_Q3_NAND	14
-#define ARRIA10_PINMUX_SHARED_IO_Q3_GPIO	15
-
-#define ARRIA10_PINMUX_SHARED_IO_Q4_I2C		0
-#define ARRIA10_PINMUX_SHARED_IO_Q4_EMAC0	1
-#define ARRIA10_PINMUX_SHARED_IO_Q4_SPIS	2
-#define ARRIA10_PINMUX_SHARED_IO_Q4_SPIM	3
-#define ARRIA10_PINMUX_SHARED_IO_Q4_SDMMC	4
-#define ARRIA10_PINMUX_SHARED_IO_Q4_EMAC1	8
-#define ARRIA10_PINMUX_SHARED_IO_Q4_QSPI	12
-#define ARRIA10_PINMUX_SHARED_IO_Q4_UART	13
-#define ARRIA10_PINMUX_SHARED_IO_Q4_NAND	14
-#define ARRIA10_PINMUX_SHARED_IO_Q4_GPIO	15
-
-#define ARRIA10_PINMUX_DEDICATED_IO_1_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x00
-#define ARRIA10_PINMUX_DEDICATED_IO_2_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x04
-#define ARRIA10_PINMUX_DEDICATED_IO_3_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x08
-#define ARRIA10_PINMUX_DEDICATED_IO_4_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x0c
-#define ARRIA10_PINMUX_DEDICATED_IO_5_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x10
-#define ARRIA10_PINMUX_DEDICATED_IO_6_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x14
-#define ARRIA10_PINMUX_DEDICATED_IO_7_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x18
-#define ARRIA10_PINMUX_DEDICATED_IO_8_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x1c
-#define ARRIA10_PINMUX_DEDICATED_IO_9_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x20
-#define ARRIA10_PINMUX_DEDICATED_IO_10_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x24
-#define ARRIA10_PINMUX_DEDICATED_IO_11_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x28
-#define ARRIA10_PINMUX_DEDICATED_IO_12_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x2c
-#define ARRIA10_PINMUX_DEDICATED_IO_13_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x30
-#define ARRIA10_PINMUX_DEDICATED_IO_14_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x34
-#define ARRIA10_PINMUX_DEDICATED_IO_15_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x38
-#define ARRIA10_PINMUX_DEDICATED_IO_16_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x3c
-#define ARRIA10_PINMUX_DEDICATED_IO_17_ADDR	ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x40
-
-#define ARRIA10_PINCFG_DEDICATED_IO_BANK_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x00
-#define ARRIA10_PINCFG_DEDICATED_IO_1_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x04
-#define ARRIA10_PINCFG_DEDICATED_IO_2_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x08
-#define ARRIA10_PINCFG_DEDICATED_IO_3_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x0c
-#define ARRIA10_PINCFG_DEDICATED_IO_4_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x10
-#define ARRIA10_PINCFG_DEDICATED_IO_5_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x14
-#define ARRIA10_PINCFG_DEDICATED_IO_6_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x18
-#define ARRIA10_PINCFG_DEDICATED_IO_7_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x1c
-#define ARRIA10_PINCFG_DEDICATED_IO_8_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x20
-#define ARRIA10_PINCFG_DEDICATED_IO_9_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x24
-#define ARRIA10_PINCFG_DEDICATED_IO_10_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x28
-#define ARRIA10_PINCFG_DEDICATED_IO_11_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x2c
-#define ARRIA10_PINCFG_DEDICATED_IO_12_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x30
-#define ARRIA10_PINCFG_DEDICATED_IO_13_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x34
-#define ARRIA10_PINCFG_DEDICATED_IO_14_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x38
-#define ARRIA10_PINCFG_DEDICATED_IO_15_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x3c
-#define ARRIA10_PINCFG_DEDICATED_IO_16_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x40
-#define ARRIA10_PINCFG_DEDICATED_IO_17_ADDR	ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x44
-
-enum arria10_pinmux_io_addr {
-	arria10_pinmux_shared_io_q1_1,
-	arria10_pinmux_shared_io_q1_2,
-	arria10_pinmux_shared_io_q1_3,
-	arria10_pinmux_shared_io_q1_4,
-	arria10_pinmux_shared_io_q1_5,
-	arria10_pinmux_shared_io_q1_6,
-	arria10_pinmux_shared_io_q1_7,
-	arria10_pinmux_shared_io_q1_8,
-	arria10_pinmux_shared_io_q1_9,
-	arria10_pinmux_shared_io_q1_10,
-	arria10_pinmux_shared_io_q1_11,
-	arria10_pinmux_shared_io_q1_12,
-	arria10_pinmux_shared_io_q2_1,
-	arria10_pinmux_shared_io_q2_2,
-	arria10_pinmux_shared_io_q2_3,
-	arria10_pinmux_shared_io_q2_4,
-	arria10_pinmux_shared_io_q2_5,
-	arria10_pinmux_shared_io_q2_6,
-	arria10_pinmux_shared_io_q2_7,
-	arria10_pinmux_shared_io_q2_8,
-	arria10_pinmux_shared_io_q2_9,
-	arria10_pinmux_shared_io_q2_10,
-	arria10_pinmux_shared_io_q2_11,
-	arria10_pinmux_shared_io_q2_12,
-	arria10_pinmux_shared_io_q3_1,
-	arria10_pinmux_shared_io_q3_2,
-	arria10_pinmux_shared_io_q3_3,
-	arria10_pinmux_shared_io_q3_4,
-	arria10_pinmux_shared_io_q3_5,
-	arria10_pinmux_shared_io_q3_6,
-	arria10_pinmux_shared_io_q3_7,
-	arria10_pinmux_shared_io_q3_8,
-	arria10_pinmux_shared_io_q3_9,
-	arria10_pinmux_shared_io_q3_10,
-	arria10_pinmux_shared_io_q3_11,
-	arria10_pinmux_shared_io_q3_12,
-	arria10_pinmux_shared_io_q4_1,
-	arria10_pinmux_shared_io_q4_2,
-	arria10_pinmux_shared_io_q4_3,
-	arria10_pinmux_shared_io_q4_4,
-	arria10_pinmux_shared_io_q4_5,
-	arria10_pinmux_shared_io_q4_6,
-	arria10_pinmux_shared_io_q4_7,
-	arria10_pinmux_shared_io_q4_8,
-	arria10_pinmux_shared_io_q4_9,
-	arria10_pinmux_shared_io_q4_10,
-	arria10_pinmux_shared_io_q4_11,
-	arria10_pinmux_shared_io_q4_12,
-	arria10_pinmux_dedicated_io_1,
-	arria10_pinmux_dedicated_io_2,
-	arria10_pinmux_dedicated_io_3,
-	arria10_pinmux_dedicated_io_4,
-	arria10_pinmux_dedicated_io_5,
-	arria10_pinmux_dedicated_io_6,
-	arria10_pinmux_dedicated_io_7,
-	arria10_pinmux_dedicated_io_8,
-	arria10_pinmux_dedicated_io_9,
-	arria10_pinmux_dedicated_io_10,
-	arria10_pinmux_dedicated_io_11,
-	arria10_pinmux_dedicated_io_12,
-	arria10_pinmux_dedicated_io_13,
-	arria10_pinmux_dedicated_io_14,
-	arria10_pinmux_dedicated_io_15,
-	arria10_pinmux_dedicated_io_16,
-	arria10_pinmux_dedicated_io_17,
-	arria10_pincfg_dedicated_io_bank,
-	arria10_pincfg_dedicated_io_1,
-	arria10_pincfg_dedicated_io_2,
-	arria10_pincfg_dedicated_io_3,
-	arria10_pincfg_dedicated_io_4,
-	arria10_pincfg_dedicated_io_5,
-	arria10_pincfg_dedicated_io_6,
-	arria10_pincfg_dedicated_io_7,
-	arria10_pincfg_dedicated_io_8,
-	arria10_pincfg_dedicated_io_9,
-	arria10_pincfg_dedicated_io_10,
-	arria10_pincfg_dedicated_io_11,
-	arria10_pincfg_dedicated_io_12,
-	arria10_pincfg_dedicated_io_13,
-	arria10_pincfg_dedicated_io_14,
-	arria10_pincfg_dedicated_io_15,
-	arria10_pincfg_dedicated_io_16,
-	arria10_pincfg_dedicated_io_17,
-	arria10_pinmux_rgmii0_usefpga,
-	arria10_pinmux_rgmii1_usefpga,
-	arria10_pinmux_rgmii2_usefpga,
-	arria10_pinmux_i2c0_usefpga,
-	arria10_pinmux_i2c1_usefpga,
-	arria10_pinmux_i2cemac0_usefpga,
-	arria10_pinmux_i2cemac1_usefpga,
-	arria10_pinmux_i2cemac2_usefpga,
-	arria10_pinmux_nand_usefpga,
-	arria10_pinmux_qspi_usefpga,
-	arria10_pinmux_sdmmc_usefpga,
-	arria10_pinmux_spim0_usefpga,
-	arria10_pinmux_spim1_usefpga,
-	arria10_pinmux_spis0_usefpga,
-	arria10_pinmux_spis1_usefpga,
-	arria10_pinmux_uart0_usefpga,
-	arria10_pinmux_uart1_usefpga,
-	arria10_pinmux_max
-};
-#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-regs.h b/arch/arm/mach-socfpga/include/mach/arria10-regs.h
deleted file mode 100644
index 4464f06231..0000000000
--- a/arch/arm/mach-socfpga/include/mach/arria10-regs.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ARRIA10_HARDWARE_H_
-#define _ARRIA10_HARDWARE_H_
-
-#define ARRIA10_EMAC0_ADDR				(0xff800000)
-#define ARRIA10_EMAC1_ADDR				(0xff802000)
-#define ARRIA10_EMAC2_ADDR				(0xff804000)
-#define ARRIA10_SDMMC_ADDR				(0xff808000)
-#define ARRIA10_QSPIREGS_ADDR				(0xff809000)
-#define ARRIA10_ECC_OCRAM_ADDR				(0xff8c3000)
-#define ARRIA10_QSPIDATA_ADDR				(0xffa00000)
-#define ARRIA10_UART0_ADDR				(0xffc02000)
-#define ARRIA10_UART1_ADDR				(0xffc02100)
-#define ARRIA10_I2C0_ADDR				(0xffc02200)
-#define ARRIA10_I2C1_ADDR				(0xffc02300)
-#define ARRIA10_GPIO0_ADDR				(0xffc02900)
-#define ARRIA10_GPIO1_ADDR				(0xffc02a00)
-#define ARRIA10_GPIO2_ADDR				(0xffc02b00)
-#define ARRIA10_HMC_MMR_IO48_ADDR			(0xffcfa000)
-#define ARRIA10_SDR_ADDR				(0xffcfb000)
-#define ARRIA10_FPGAMGRDATA_ADDR			(0xffcfe400)
-#define ARRIA10_OSC1TIMER0_ADDR				(0xffd00000)
-#define ARRIA10_L4WD0_ADDR				(0xffd00200)
-#define ARRIA10_FPGAMGRREGS_ADDR			(0xffd03000)
-#define ARRIA10_CLKMGR_ADDR				(0xffd04000)
-#define ARRIA10_RSTMGR_ADDR				(0xffd05000)
-#define ARRIA10_SYSMGR_ADDR				(0xffd06000)
-#define ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR		(0xffd07000)
-#define ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR		(0xffd07200)
-#define ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR	(0xffd07300)
-#define ARRIA10_PINMUX_FPGA_INTERFACE_ADDR		(0xffd07400)
-#define ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR		(0xffd11000)
-#define ARRIA10_SDR_SCHEDULER_ADDR			(0xffd12400)
-#define ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR		(0xffd13000)
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR		(0xffd13200)
-#define ARRIA10_SDR_FW_MPU_FPGA_ADDR			(0xffd13300)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR		(0xffd13400)
-#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR	(0xffd13500)
-#define ARRIA10_DMANONSECURE_ADDR			(0xffda0000)
-#define ARRIA10_DMASECURE_ADDR				(0xffda1000)
-#define ARRIA10_OCRAM_ADDR				(0xffe00000)
-#define ARRIA10_MPUSCU_ADDR				(0xffffc000)
-#define ARRIA10_SMP_TWD_ADDR				(0xffffc600)
-#define ARRIA10_MPUL2_ADDR				(0xfffff000)
-
-/* L2 cache controller */
-#define ARRIA10_MPUL2_ADRFLTR_START			(ARRIA10_MPUL2_ADDR + 0xC00)
-
-/* NOC L4 Priv */
-#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV		(ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x00)
-#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_SET		(ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x04)
-#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_CLR		(ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x08)
-
-/* NOC L4 Permissions */
-#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_REG		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x00)
-#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_DATA		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x04)
-#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI_DATA		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x08)
-#define ARRIA10_NOC_FW_L4_PER_SCR_USB0_REG		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x0c)
-#define ARRIA10_NOC_FW_L4_PER_SCR_USB1_REG		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x10)
-#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_NONSECURE		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x14)
-#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_SECURE		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x18)
-#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x1c)
-#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x20)
-#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x24)
-#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x28)
-#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x2c)
-#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x30)
-#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC2			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x34)
-#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC3			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x38)
-#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x3c)
-#define ARRIA10_NOC_FW_L4_PER_SCR_SDMMC			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x40)
-#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x44)
-#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x48)
-#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO2			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x4c)
-#define ARRIA10_NOC_FW_L4_PER_SCR_I2C0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x50)
-#define ARRIA10_NOC_FW_L4_PER_SCR_I2C1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x54)
-#define ARRIA10_NOC_FW_L4_PER_SCR_I2C2			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x58)
-#define ARRIA10_NOC_FW_L4_PER_SCR_I2C3			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x5c)
-#define ARRIA10_NOC_FW_L4_PER_SCR_I2C4			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x60)
-#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER0		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x64)
-#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER1		(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x68)
-#define ARRIA10_NOC_FW_L4_PER_SCR_UART0			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x6c)
-#define ARRIA10_NOC_FW_L4_PER_SCR_UART1			(ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x70)
-
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x00)
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_SET		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x04)
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_CLR		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x08)
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x0c)
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION1		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x10)
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION2		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x14)
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION3		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x18)
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION4		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x1c)
-#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION5		(ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x20)
-
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_SET		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_CLR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION0		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION1		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION2		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION3		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION4		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION5		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION6		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION7		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28)
-#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_GLOBAL		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c)
-
-#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_LWSOC2FPGA	(ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x00)
-#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_SOC2FPGA	(ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x04)
-
-#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
deleted file mode 100644
index 2033de77a3..0000000000
--- a/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef	_ARRIA10_RESET_MANAGER_H_
-#define	_ARRIA10_RESET_MANAGER_H_
-
-#define ARRIA10_RSTMGR_STATUS		0x0
-#define ARRIA10_RSTMGR_RAMSTAT		0x4
-#define ARRIA10_RSTMGR_MISCSTAT		0x8
-#define ARRIA10_RSTMGR_CTRL		0xc
-#define ARRIA10_RSTMGR_HDSKEN		0x10
-#define ARRIA10_RSTMGR_HDSKREQ		0x14
-#define ARRIA10_RSTMGR_HDSKACK		0x18
-#define ARRIA10_RSTMGR_COUNTS		0x1c
-#define ARRIA10_RSTMGR_MPUMODRST	0x20
-#define ARRIA10_RSTMGR_PER0MODRST	0x24
-#define ARRIA10_RSTMGR_PER1MODRST	0x28
-#define ARRIA10_RSTMGR_BRGMODRST	0x2c
-#define ARRIA10_RSTMGR_SYSMODRST	0x30
-#define ARRIA10_RSTMGR_COLDMODRST	0x34
-#define ARRIA10_RSTMGR_NRSTMODRST	0x38
-#define ARRIA10_RSTMGR_DBGMODRST	0x3c
-#define ARRIA10_RSTMGR_MPUWARMMASK	0x40
-#define ARRIA10_RSTMGR_PER0WARMMASK	0x44
-#define ARRIA10_RSTMGR_PER1WARMMASK	0x48
-#define ARRIA10_RSTMGR_BRGWARMMASK	0x4c
-#define ARRIA10_RSTMGR_SYSWARMMASK	0x50
-#define ARRIA10_RSTMGR_NRSTWARMMASK	0x54
-#define ARRIA10_RSTMGR_L3WARMMASK	0x58
-#define ARRIA10_RSTMGR_TSTSTA		0x5c
-#define ARRIA10_RSTMGR_TSTSCRATCH	0x60
-#define ARRIA10_RSTMGR_HDSKTIMEOUT	0x64
-#define ARRIA10_RSTMGR_HMCINTR		0x68
-#define ARRIA10_RSTMGR_HMCINTREN	0x6c
-#define ARRIA10_RSTMGR_HMCINTRENS	0x70
-#define ARRIA10_RSTMGR_HMCINTRENR	0x74
-#define ARRIA10_RSTMGR_HMCGPOUT		0x78
-#define ARRIA10_RSTMGR_HMCGPIN		0x7c
-
-#define ARRIA10_RSTMGR_CTL_SWWARMRSTREQ		BIT(1)
-#define ARRIA10_RSTMGR_PER0MODRST_EMAC0		BIT(0)
-#define ARRIA10_RSTMGR_PER0MODRST_EMAC1		BIT(1)
-#define ARRIA10_RSTMGR_PER0MODRST_EMAC2		BIT(2)
-#define ARRIA10_RSTMGR_PER0MODRST_USB0		BIT(3)
-#define ARRIA10_RSTMGR_PER0MODRST_USB1		BIT(4)
-#define ARRIA10_RSTMGR_PER0MODRST_NAND		BIT(5)
-#define ARRIA10_RSTMGR_PER0MODRST_QSPI		BIT(6)
-#define ARRIA10_RSTMGR_PER0MODRST_SDMMC		BIT(7)
-#define ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP	BIT(8)
-#define ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP	BIT(9)
-#define ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP	BIT(10)
-#define ARRIA10_RSTMGR_PER0MODRST_USB0OCP	BIT(11)
-#define ARRIA10_RSTMGR_PER0MODRST_USB1OCP	BIT(12)
-#define ARRIA10_RSTMGR_PER0MODRST_NANDOCP	BIT(13)
-#define ARRIA10_RSTMGR_PER0MODRST_QSPIOCP	BIT(14)
-#define ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP	BIT(15)
-#define ARRIA10_RSTMGR_PER0MODRST_DMA		BIT(16)
-#define ARRIA10_RSTMGR_PER0MODRST_SPIM0		BIT(17)
-#define ARRIA10_RSTMGR_PER0MODRST_SPIM1		BIT(18)
-#define ARRIA10_RSTMGR_PER0MODRST_SPIS0		BIT(19)
-#define ARRIA10_RSTMGR_PER0MODRST_SPIS1		BIT(20)
-#define ARRIA10_RSTMGR_PER0MODRST_DMAOCP	BIT(21)
-#define ARRIA10_RSTMGR_PER0MODRST_EMACPTP	BIT(22)
-#define ARRIA10_RSTMGR_PER0MODRST_DMAIF0	BIT(24)
-#define ARRIA10_RSTMGR_PER0MODRST_DMAIF1	BIT(25)
-#define ARRIA10_RSTMGR_PER0MODRST_DMAIF2	BIT(26)
-#define ARRIA10_RSTMGR_PER0MODRST_DMAIF3	BIT(27)
-#define ARRIA10_RSTMGR_PER0MODRST_DMAIF4	BIT(28)
-#define ARRIA10_RSTMGR_PER0MODRST_DMAIF5	BIT(29)
-#define ARRIA10_RSTMGR_PER0MODRST_DMAIF6	BIT(30)
-#define ARRIA10_RSTMGR_PER0MODRST_DMAIF7	BIT(31)
-
-#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG0	BIT(0)
-#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG1	BIT(1)
-#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER0	BIT(2)
-#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER1	BIT(3)
-#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER0	BIT(4)
-#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER1	BIT(5)
-#define ARRIA10_RSTMGR_PER1MODRST_I2C0		BIT(8)
-#define ARRIA10_RSTMGR_PER1MODRST_I2C1		BIT(9)
-#define ARRIA10_RSTMGR_PER1MODRST_I2C2		BIT(10)
-#define ARRIA10_RSTMGR_PER1MODRST_I2C3		BIT(11)
-#define ARRIA10_RSTMGR_PER1MODRST_I2C4		BIT(12)
-#define ARRIA10_RSTMGR_PER1MODRST_UART0		BIT(16)
-#define ARRIA10_RSTMGR_PER1MODRST_UART1		BIT(17)
-#define ARRIA10_RSTMGR_PER1MODRST_GPIO0		BIT(24)
-#define ARRIA10_RSTMGR_PER1MODRST_GPIO1		BIT(25)
-#define ARRIA10_RSTMGR_PER1MODRST_GPIO2		BIT(26)
-
-#define ARRIA10_RSTMGR_BRGMODRST_HPS2FPGA	BIT(0)
-#define ARRIA10_RSTMGR_BRGMODRST_LWHPS2FPGA	BIT(1)
-#define ARRIA10_RSTMGR_BRGMODRST_FPGA2HPS	BIT(2)
-#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0	BIT(3)
-#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1	BIT(4)
-#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2	BIT(5)
-#define ARRIA10_RSTMGR_BRGMODRST_DDRSCH		BIT(6)
-
-#define ARRIA10_RSTMGR_OCP_MASK (ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP |	\
-				 ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP |	\
-				 ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP |	\
-				 ARRIA10_RSTMGR_PER0MODRST_NANDOCP  |	\
-				 ARRIA10_RSTMGR_PER0MODRST_QSPIOCP  |	\
-				 ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP)
-
-void arria10_reset_peripherals(void);
-void arria10_reset_deassert_dedicated_peripherals(void);
-void arria10_reset_deassert_shared_peripherals(void);
-void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0, uint32_t *mask1);
-void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0, uint32_t *mask1);
-void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0, uint32_t *mask1);
-void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1);
-void arria10_reset_deassert_fpga_peripherals(void);
-
-#endif
-
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-sdram.h b/arch/arm/mach-socfpga/include/mach/arria10-sdram.h
deleted file mode 100644
index 07e4dd0130..0000000000
--- a/arch/arm/mach-socfpga/include/mach/arria10-sdram.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#include <mach/arria10-system-manager.h>
-
-#ifndef	_ARRIA10_SDRAM_H_
-#define	_ARRIA10_SDRAM_H_
-
-#define ARRIA10_ECC_HMC_OCP_IP_REV_ID			(ARRIA10_SDR_ADDR + 0x00)
-#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL			(ARRIA10_SDR_ADDR + 0x08)
-#define ARRIA10_ECC_HMC_OCP_DDRCALSTAT			(ARRIA10_SDR_ADDR + 0x0c)
-#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT1			(ARRIA10_SDR_ADDR + 0x10)
-#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT1			(ARRIA10_SDR_ADDR + 0x14)
-#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT1			(ARRIA10_SDR_ADDR + 0x18)
-#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT1			(ARRIA10_SDR_ADDR + 0x1c)
-#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT1			(ARRIA10_SDR_ADDR + 0x20)
-#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT1			(ARRIA10_SDR_ADDR + 0x24)
-#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT1			(ARRIA10_SDR_ADDR + 0x28)
-#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT1			(ARRIA10_SDR_ADDR + 0x2c)
-#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT1			(ARRIA10_SDR_ADDR + 0x30)
-#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT2			(ARRIA10_SDR_ADDR + 0x34)
-#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT2			(ARRIA10_SDR_ADDR + 0x38)
-#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT2			(ARRIA10_SDR_ADDR + 0x3c)
-#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT2			(ARRIA10_SDR_ADDR + 0x40)
-#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT2			(ARRIA10_SDR_ADDR + 0x44)
-#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT2			(ARRIA10_SDR_ADDR + 0x48)
-#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT2			(ARRIA10_SDR_ADDR + 0x4c)
-#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT2			(ARRIA10_SDR_ADDR + 0x50)
-#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT2			(ARRIA10_SDR_ADDR + 0x54)
-#define ARRIA10_ECC_HMC_OCP_MPR_AUTO_PRECHARGE		(ARRIA10_SDR_ADDR + 0x60)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1		(ARRIA10_SDR_ADDR + 0x100)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2		(ARRIA10_SDR_ADDR + 0x104)
-#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTEN		(ARRIA10_SDR_ADDR + 0x110)
-#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENS		(ARRIA10_SDR_ADDR + 0x114)
-#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENR		(ARRIA10_SDR_ADDR + 0x118)
-#define ARRIA10_ECC_HMC_OCP_MPR_INTMODE			(ARRIA10_SDR_ADDR + 0x11c)
-#define ARRIA10_ECC_HMC_OCP_MPR_INTSTAT			(ARRIA10_SDR_ADDR + 0x120)
-#define ARRIA10_ECC_HMC_OCP_MPR_DIAGINTTEST		(ARRIA10_SDR_ADDR + 0x124)
-#define ARRIA10_ECC_HMC_OCP_MPR_MODSTAT			(ARRIA10_SDR_ADDR + 0x128)
-#define ARRIA10_ECC_HMC_OCP_MPR_DERRADDRA		(ARRIA10_SDR_ADDR + 0x12c)
-#define ARRIA10_ECC_HMC_OCP_MPR_SERRADDRA		(ARRIA10_SDR_ADDR + 0x130)
-#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_CORRADDR		(ARRIA10_SDR_ADDR + 0x138)
-#define ARRIA10_ECC_HMC_OCP_MPR_SERRCNTREG		(ARRIA10_SDR_ADDR + 0x13c)
-#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_DROP_CNTREG	(ARRIA10_SDR_ADDR + 0x140)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2WRECCDATABUS	(ARRIA10_SDR_ADDR + 0x144)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_RDECCDATA2REGBUS	(ARRIA10_SDR_ADDR + 0x148)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDECCDATABUS	(ARRIA10_SDR_ADDR + 0x14c)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DIAGON		(ARRIA10_SDR_ADDR + 0x150)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DECSTAT		(ARRIA10_SDR_ADDR + 0x154)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_0	(ARRIA10_SDR_ADDR + 0x160)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_1	(ARRIA10_SDR_ADDR + 0x164)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_2	(ARRIA10_SDR_ADDR + 0x168)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_3	(ARRIA10_SDR_ADDR + 0x16c)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT0	(ARRIA10_SDR_ADDR + 0x170)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT1	(ARRIA10_SDR_ADDR + 0x174)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT2	(ARRIA10_SDR_ADDR + 0x178)
-#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT3	(ARRIA10_SDR_ADDR + 0x17c)
-
-#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_COREID		(ARRIA10_SDR_SCHEDULER_ADDR + 0x00)
-#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_REVISIONID		(ARRIA10_SDR_SCHEDULER_ADDR + 0x04)
-#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRCONF		(ARRIA10_SDR_SCHEDULER_ADDR + 0x08)
-#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRTIMING		(ARRIA10_SDR_SCHEDULER_ADDR + 0x0c)
-#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRMODE		(ARRIA10_SDR_SCHEDULER_ADDR + 0x10)
-#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_READLATENCY		(ARRIA10_SDR_SCHEDULER_ADDR + 0x14)
-#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ACTIVATE		(ARRIA10_SDR_SCHEDULER_ADDR + 0x38)
-#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DEVTODEV		(ARRIA10_SDR_SCHEDULER_ADDR + 0x3c)
-
-#define ARRIA10_IO48_HMC_MMR_DBGCFG0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x00)
-#define ARRIA10_IO48_HMC_MMR_DBGCFG1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x04)
-#define ARRIA10_IO48_HMC_MMR_DBGCFG2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x08)
-#define ARRIA10_IO48_HMC_MMR_DBGCFG3		(ARRIA10_HMC_MMR_IO48_ADDR + 0x0c)
-#define ARRIA10_IO48_HMC_MMR_DBGCFG4		(ARRIA10_HMC_MMR_IO48_ADDR + 0x10)
-#define ARRIA10_IO48_HMC_MMR_DBGCFG5		(ARRIA10_HMC_MMR_IO48_ADDR + 0x14)
-#define ARRIA10_IO48_HMC_MMR_DBGCFG6		(ARRIA10_HMC_MMR_IO48_ADDR + 0x18)
-#define ARRIA10_IO48_HMC_MMR_RESERVE0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x1c)
-#define ARRIA10_IO48_HMC_MMR_RESERVE1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x20)
-#define ARRIA10_IO48_HMC_MMR_RESERVE2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x24)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x28)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x2c)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x30)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG3		(ARRIA10_HMC_MMR_IO48_ADDR + 0x34)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG4		(ARRIA10_HMC_MMR_IO48_ADDR + 0x38)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG5		(ARRIA10_HMC_MMR_IO48_ADDR + 0x3c)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG6		(ARRIA10_HMC_MMR_IO48_ADDR + 0x40)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG7		(ARRIA10_HMC_MMR_IO48_ADDR + 0x44)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG8		(ARRIA10_HMC_MMR_IO48_ADDR + 0x48)
-#define ARRIA10_IO48_HMC_MMR_CTRLCFG9		(ARRIA10_HMC_MMR_IO48_ADDR + 0x4c)
-#define ARRIA10_IO48_HMC_MMR_DRAMTIMING0	(ARRIA10_HMC_MMR_IO48_ADDR + 0x50)
-#define ARRIA10_IO48_HMC_MMR_DRAMODT0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x54)
-#define ARRIA10_IO48_HMC_MMR_DRAMODT1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x58)
-#define ARRIA10_IO48_HMC_MMR_SBCFG0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x5c)
-#define ARRIA10_IO48_HMC_MMR_SBCFG1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x60)
-#define ARRIA10_IO48_HMC_MMR_SBCFG2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x64)
-#define ARRIA10_IO48_HMC_MMR_SBCFG3		(ARRIA10_HMC_MMR_IO48_ADDR + 0x68)
-#define ARRIA10_IO48_HMC_MMR_SBCFG4		(ARRIA10_HMC_MMR_IO48_ADDR + 0x6c)
-#define ARRIA10_IO48_HMC_MMR_SBCFG5		(ARRIA10_HMC_MMR_IO48_ADDR + 0x70)
-#define ARRIA10_IO48_HMC_MMR_SBCFG6		(ARRIA10_HMC_MMR_IO48_ADDR + 0x74)
-#define ARRIA10_IO48_HMC_MMR_SBCFG7		(ARRIA10_HMC_MMR_IO48_ADDR + 0x78)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING0		(ARRIA10_HMC_MMR_IO48_ADDR + 0x7c)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING1		(ARRIA10_HMC_MMR_IO48_ADDR + 0x80)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING2		(ARRIA10_HMC_MMR_IO48_ADDR + 0x84)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING3		(ARRIA10_HMC_MMR_IO48_ADDR + 0x88)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING4		(ARRIA10_HMC_MMR_IO48_ADDR + 0x8c)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING5		(ARRIA10_HMC_MMR_IO48_ADDR + 0x90)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING6		(ARRIA10_HMC_MMR_IO48_ADDR + 0x94)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING7		(ARRIA10_HMC_MMR_IO48_ADDR + 0x98)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING8		(ARRIA10_HMC_MMR_IO48_ADDR + 0x9c)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING9		(ARRIA10_HMC_MMR_IO48_ADDR + 0xa0)
-#define ARRIA10_IO48_HMC_MMR_CALTIMING10	(ARRIA10_HMC_MMR_IO48_ADDR + 0xa4)
-#define ARRIA10_IO48_HMC_MMR_DRAMADDRW		(ARRIA10_HMC_MMR_IO48_ADDR + 0xa8)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND0		(ARRIA10_HMC_MMR_IO48_ADDR + 0xac)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND1		(ARRIA10_HMC_MMR_IO48_ADDR + 0xb0)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND2		(ARRIA10_HMC_MMR_IO48_ADDR + 0xb4)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND3		(ARRIA10_HMC_MMR_IO48_ADDR + 0xb8)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND4		(ARRIA10_HMC_MMR_IO48_ADDR + 0xbc)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND5		(ARRIA10_HMC_MMR_IO48_ADDR + 0xc0)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND6		(ARRIA10_HMC_MMR_IO48_ADDR + 0xc4)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND7		(ARRIA10_HMC_MMR_IO48_ADDR + 0xc8)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND8		(ARRIA10_HMC_MMR_IO48_ADDR + 0xcc)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND9		(ARRIA10_HMC_MMR_IO48_ADDR + 0xd0)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND10		(ARRIA10_HMC_MMR_IO48_ADDR + 0xd4)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND11		(ARRIA10_HMC_MMR_IO48_ADDR + 0xd8)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND12		(ARRIA10_HMC_MMR_IO48_ADDR + 0xdc)
-#define ARRIA10_IO48_HMC_MMR_SIDEBANB13		(ARRIA10_HMC_MMR_IO48_ADDR + 0xe0)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND14		(ARRIA10_HMC_MMR_IO48_ADDR + 0xe4)
-#define ARRIA10_IO48_HMC_MMR_SIDEBAND15		(ARRIA10_HMC_MMR_IO48_ADDR + 0xe8)
-#define ARRIA10_IO48_HMC_MMR_DRAMSTS		(ARRIA10_HMC_MMR_IO48_ADDR + 0xec)
-#define ARRIA10_IO48_HMC_MMR_DBGDONE		(ARRIA10_HMC_MMR_IO48_ADDR + 0xf0)
-#define ARRIA10_IO48_HMC_MMR_DBGSIGNALS		(ARRIA10_HMC_MMR_IO48_ADDR + 0xf4)
-#define ARRIA10_IO48_HMC_MMR_DBGRESET		(ARRIA10_HMC_MMR_IO48_ADDR + 0xf8)
-#define ARRIA10_IO48_HMC_MMR_DBGMATCH		(ARRIA10_HMC_MMR_IO48_ADDR + 0xfc)
-#define ARRIA10_IO48_HMC_MMR_COUNTER0MASK	(ARRIA10_HMC_MMR_IO48_ADDR + 0x100)
-#define ARRIA10_IO48_HMC_MMR_COUNTER1MASK	(ARRIA10_HMC_MMR_IO48_ADDR + 0x104)
-#define ARRIA10_IO48_HMC_MMR_COUNTER0MATCH	(ARRIA10_HMC_MMR_IO48_ADDR + 0x108)
-#define ARRIA10_IO48_HMC_MMR_COUNTER1MATCH	(ARRIA10_HMC_MMR_IO48_ADDR + 0x10c)
-#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE0	(ARRIA10_HMC_MMR_IO48_ADDR + 0x110)
-#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE1	(ARRIA10_HMC_MMR_IO48_ADDR + 0x114)
-#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE2	(ARRIA10_HMC_MMR_IO48_ADDR + 0x118)
-
-union dramaddrw_reg {
-	struct {
-		u32 cfg_col_addr_width:5;
-		u32 cfg_row_addr_width:5;
-		u32 cfg_bank_addr_width:4;
-		u32 cfg_bank_group_addr_width:2;
-		u32 cfg_cs_addr_width:3;
-		u32 reserved:13;
-	};
-	u32 word;
-};
-
-union ctrlcfg0_reg {
-	struct {
-		u32 cfg_mem_type:4;
-		u32 cfg_dimm_type:3;
-		u32 cfg_ac_pos:2;
-		u32 cfg_ctrl_burst_len:5;
-		u32 reserved:18;  /* Other fields unused */
-	};
-	u32 word;
-};
-
-union ctrlcfg1_reg {
-	struct {
-		u32 cfg_dbc3_burst_len:5;
-		u32 cfg_addr_order:2;
-		u32 cfg_ctrl_enable_ecc:1;
-		u32 reserved:24;  /* Other fields unused */
-	};
-	u32 word;
-};
-
-union caltiming0_reg {
-	struct {
-		u32 cfg_act_to_rdwr:6;
-		u32 cfg_act_to_pch:6;
-		u32 cfg_act_to_act:6;
-		u32 cfg_act_to_act_db:6;
-		u32 reserved:8;  /* Other fields unused */
-	};
-	u32 word;
-};
-
-union caltiming1_reg {
-	struct {
-		u32 cfg_rd_to_rd:6;
-		u32 cfg_rd_to_rd_dc:6;
-		u32 cfg_rd_to_rd_db:6;
-		u32 cfg_rd_to_wr:6;
-		u32 cfg_rd_to_wr_dc:6;
-		u32 reserved:2;
-	};
-	u32 word;
-};
-
-union caltiming2_reg {
-	struct {
-		u32 cfg_rd_to_wr_db:6;
-		u32 cfg_rd_to_pch:6;
-		u32 cfg_rd_ap_to_valid:6;
-		u32 cfg_wr_to_wr:6;
-		u32 cfg_wr_to_wr_dc:6;
-		u32 reserved:2;
-	};
-	u32 word;
-};
-
-union caltiming3_reg {
-	struct {
-		u32 cfg_wr_to_wr_db:6;
-		u32 cfg_wr_to_rd:6;
-		u32 cfg_wr_to_rd_dc:6;
-		u32 cfg_wr_to_rd_db:6;
-		u32 cfg_wr_to_pch:6;
-		u32 reserved:2;
-	};
-	u32 word;
-};
-
-union caltiming4_reg {
-	struct {
-		u32 cfg_wr_ap_to_valid:6;
-		u32 cfg_pch_to_valid:6;
-		u32 cfg_pch_all_to_valid:6;
-		u32 cfg_arf_to_valid:8;
-		u32 cfg_pdn_to_valid:6;
-	};
-	u32 word;
-};
-
-union caltiming9_reg {
-	struct {
-		u32 cfg_4_act_to_act:8;
-		u32 reserved:24;
-	};
-	u32 word;
-};
-
-#define IRQ_ECC_SERR						34
-#define IRQ_ECC_DERR						32
-
-#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE			0x00000001
-
-#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERRPENA			0x00000001
-#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRPENA			0x00000002
-#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERRINTEN			0x00000001
-#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERRINTEN			0x00000002
-#define ARRIA10_ECC_HMC_OCP_INTMOD_INTONCMP			0x00010000
-#define ARRIA10_ECC_HMC_OCP_INTMOD_SERR				0x00000001
-#define ARRIA10_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY		0x00000100
-#define ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST			0x00010000
-#define ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST			0x00000100
-#define ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN			0x00000000
-#define ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN			0x00000100
-#define ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN			0x00000001
-#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERR			0x00000001
-#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERR			0x00000002
-#define ARRIA10_ECC_HMC_OCP_ERRINTEN_HMI			0x00000004
-#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERR			0x00000001
-#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERR			0x00000002
-#define ARRIA10_ECC_HMC_OCP_INTSTAT_HMI				0x00000004
-#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG			0x00010000
-#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRPARFLG			0x00020000
-#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRBUSFLG			0x00040000
-
-#define ARRIA10_ECC_HMC_OCP_SERRCNTREG_VALUE			8
-
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB	22
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB	0
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB	0
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB	2
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB	6
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB	15
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB	0
-
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB	0
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB	0
-
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB		4
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB		13
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB	4
-
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB	4
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB	6
-#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB	6
-
-#define ARRIA10_SDR_FW_MPU_FPGA_EN			(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x00)
-#define ARRIA10_SDR_FW_MPU_FPGA_EN_SET			(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x04)
-#define ARRIA10_SDR_FW_MPU_FPGA_EN_CLR			(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x08)
-#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION0ADDR		(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x10)
-#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION1ADDR		(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x14)
-#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION2ADDR		(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x18)
-#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR		(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x1c)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x20)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x24)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION2ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x28)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x2c)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x30)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x34)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION2ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x38)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x3c)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x40)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x44)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION2ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x48)
-#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION3ADDR	(ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x4c)
-
-#define ARRIA10_NOC_FW_DDR_MPU_MPUREG0EN		BIT(0)
-#define ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN		BIT(1)
-#define ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN		BIT(2)
-#define ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN		BIT(3)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN		BIT(4)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG1EN		BIT(5)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG2EN		BIT(6)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG3EN		BIT(7)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN		BIT(8)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG1EN		BIT(9)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG2EN		BIT(10)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG3EN		BIT(11)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN		BIT(12)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG1EN		BIT(13)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG2EN		BIT(14)
-#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG3EN		BIT(15)
-
-#define ARRIA10_NOC_FW_DDR_L3_EN			(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00)
-#define ARRIA10_NOC_FW_DDR_L3_EN_SET			(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04)
-#define ARRIA10_NOC_FW_DDR_L3_EN_CLR			(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREGION1ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREGION2ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREGION3ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREGION4ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREGION5ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREGION6ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREGION7ADDR		(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28)
-#define ARRIA10_NOC_FW_DDR_L3_GLOBAL			(ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c)
-
-#define ARRIA10_NOC_FW_DDR_L3_HPSREG0EN			BIT(0)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREG1EN			BIT(1)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREG2EN			BIT(2)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREG3EN			BIT(3)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREG4EN			BIT(4)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREG5EN			BIT(5)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREG6EN			BIT(6)
-#define ARRIA10_NOC_FW_DDR_L3_HPSREG7EN			BIT(7)
-
-#define ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY		0x0000003f
-
-int arria10_ddr_calibration_sequence(void);
-
-#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
deleted file mode 100644
index 9117a93b18..0000000000
--- a/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef	_ARRIA10_SYSTEM_MANAGER_H_
-#define	_ARRIA10_SYSTEM_MANAGER_H_
-
-#include <mach/arria10-regs.h>
-
-#define ARRIA10_SYSMGR_SILICONID1		(ARRIA10_SYSMGR_ADDR + 0x00)
-#define ARRIA10_SYSMGR_SILICONID2		(ARRIA10_SYSMGR_ADDR + 0x04)
-#define ARRIA10_SYSMGR_WDDBG			(ARRIA10_SYSMGR_ADDR + 0x08)
-#define ARRIA10_SYSMGR_BOOTINFO			(ARRIA10_SYSMGR_ADDR + 0x0c)
-#define ARRIA10_SYSMGR_MPU_CTRL_L2_ECC		(ARRIA10_SYSMGR_ADDR + 0x10)
-#define ARRIA10_SYSMGR_DMA			(ARRIA10_SYSMGR_ADDR + 0x20)
-#define ARRIA10_SYSMGR_DMA_PERIPH		(ARRIA10_SYSMGR_ADDR + 0x24)
-#define ARRIA10_SYSMGR_SDMMC			(ARRIA10_SYSMGR_ADDR + 0x28)
-#define ARRIA10_SYSMGR_SDMMC_L3MASTER		(ARRIA10_SYSMGR_ADDR + 0x2c)
-#define ARRIA10_SYSMGR_NAND_BOOTSTRAP		(ARRIA10_SYSMGR_ADDR + 0x30)
-#define ARRIA10_SYSMGR_NAND_L3MASTER		(ARRIA10_SYSMGR_ADDR + 0x34)
-#define ARRIA10_SYSMGR_USB0_L3MASTER		(ARRIA10_SYSMGR_ADDR + 0x38)
-#define ARRIA10_SYSMGR_USB1_L3MASTER		(ARRIA10_SYSMGR_ADDR + 0x3c)
-#define ARRIA10_SYSMGR_EMAC_GLOBAL		(ARRIA10_SYSMGR_ADDR + 0x40)
-#define ARRIA10_SYSMGR_EMAC0			(ARRIA10_SYSMGR_ADDR + 0x44)
-#define ARRIA10_SYSMGR_EMAC1			(ARRIA10_SYSMGR_ADDR + 0x48)
-#define ARRIA10_SYSMGR_EMAC2			(ARRIA10_SYSMGR_ADDR + 0x4c)
-#define ARRIA10_SYSMGR_FPGAINTF_GLOBAL		(ARRIA10_SYSMGR_ADDR + 0x60)
-#define ARRIA10_SYSMGR_FPGAINTF_EN_0		(ARRIA10_SYSMGR_ADDR + 0x64)
-#define ARRIA10_SYSMGR_FPGAINTF_EN_1		(ARRIA10_SYSMGR_ADDR + 0x68)
-#define ARRIA10_SYSMGR_FPGAINTF_EN_2		(ARRIA10_SYSMGR_ADDR + 0x6c)
-#define ARRIA10_SYSMGR_FPGAINTF_EN_3		(ARRIA10_SYSMGR_ADDR + 0x70)
-#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE 	(ARRIA10_SYSMGR_ADDR + 0x80)
-#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_SET 	(ARRIA10_SYSMGR_ADDR + 0x84)
-#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_CLEAR 	(ARRIA10_SYSMGR_ADDR + 0x88)
-#define ARRIA10_SYSMGR_ECC_INTMASK_VALUE 	(ARRIA10_SYSMGR_ADDR + 0x90)
-#define ARRIA10_SYSMGR_ECC_INTMASK_SET 		(ARRIA10_SYSMGR_ADDR + 0x94)
-#define ARRIA10_SYSMGR_ECC_INTMASK_CLR 		(ARRIA10_SYSMGR_ADDR + 0x98)
-#define ARRIA10_SYSMGR_ECC_INTSTATUS_SERR 	(ARRIA10_SYSMGR_ADDR + 0x9c)
-#define ARRIA10_SYSMGR_ECC_INTSTATUS_DERR 	(ARRIA10_SYSMGR_ADDR + 0xa0)
-#define ARRIA10_SYSMGR_MPU_STATUS_L2_ECC 	(ARRIA10_SYSMGR_ADDR + 0xa4)
-#define ARRIA10_SYSMGR_MPU_CLEAR_L2_ECC 	(ARRIA10_SYSMGR_ADDR + 0xa8)
-#define ARRIA10_SYSMGR_MPU_STATUS_L1_PARITY 	(ARRIA10_SYSMGR_ADDR + 0xac)
-#define ARRIA10_SYSMGR_MPU_CLEAR_L1_PARITY 	(ARRIA10_SYSMGR_ADDR + 0xb0)
-#define ARRIA10_SYSMGR_MPU_SET_L1_PARITY 	(ARRIA10_SYSMGR_ADDR + 0xb4)
-#define ARRIA10_SYSMGR_NOC_TIMEOUT 		(ARRIA10_SYSMGR_ADDR + 0xc0)
-#define ARRIA10_SYSMGR_NOC_IDLEREQ_SET		(ARRIA10_SYSMGR_ADDR + 0xc4)
-#define ARRIA10_SYSMGR_NOC_IDLEREQ_CLR		(ARRIA10_SYSMGR_ADDR + 0xc8)
-#define ARRIA10_SYSMGR_NOC_IDLEREQ_VALUE	(ARRIA10_SYSMGR_ADDR + 0xcc)
-#define ARRIA10_SYSMGR_NOC_IDLEACK		(ARRIA10_SYSMGR_ADDR + 0xd0)
-#define ARRIA10_SYSMGR_NOC_IDLESTATUS		(ARRIA10_SYSMGR_ADDR + 0xd4)
-#define ARRIA10_SYSMGR_FPGA2SOC_CTRL		(ARRIA10_SYSMGR_ADDR + 0xd8)
-
-#define ARRIA10_SYSMGR_ROM_INITSWLASTLD		(ARRIA10_SYSMGR_ADDR + 0x10)
-
-
-#define ARRIA10_SYSMGR_BOOTINFO_BSEL_MASK	0x00007000
-#define ARRIA10_SYSMGR_BOOTINFO_BSEL_SHIFT	12
-
-/* pin mux */
-#define ARRIA10_SYSMGR_PINMUXGRP		(ARRIA10_SYSMGR_ADDR + 0x400)
-#define ARRIA10_SYSMGR_PINMUXGRP_NANDUSEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x2F0)
-#define ARRIA10_SYSMGR_PINMUXGRP_EMAC1USEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x2F8)
-#define ARRIA10_SYSMGR_PINMUXGRP_SDMMCUSEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x308)
-#define ARRIA10_SYSMGR_PINMUXGRP_EMAC0USEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x314)
-#define ARRIA10_SYSMGR_PINMUXGRP_SPIM1USEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x330)
-#define ARRIA10_SYSMGR_PINMUXGRP_SPIM0USEFPGA	(ARRIA10_SYSMGR_PINMUXGRP + 0x338)
-
-/* bit fields */
-#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX		BIT(0)
-#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO		BIT(1)
-#define ARRIA10_SYSMGR_ECC_OCRAM_EN				BIT(0)
-#define ARRIA10_SYSMGR_ECC_OCRAM_SERR				BIT(3)
-#define ARRIA10_SYSMGR_ECC_OCRAM_DERR				BIT(4)
-#define ARRIA10_SYSMGR_FPGAINTF_USEFPGA				BIT(1)
-#define ARRIA10_SYSMGR_FPGAINTF_SPIM0				BIT(0)
-#define ARRIA10_SYSMGR_FPGAINTF_SPIM1				BIT(1)
-#define ARRIA10_SYSMGR_FPGAINTF_EMAC0				BIT(2)
-#define ARRIA10_SYSMGR_FPGAINTF_EMAC1				BIT(3)
-#define ARRIA10_SYSMGR_FPGAINTF_NAND				BIT(4)
-#define ARRIA10_SYSMGR_FPGAINTF_SDMMC				BIT(5)
-
-#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
-#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
-#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
-#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_LSB			0
-#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x00000003
-
-#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0	BIT(0)
-#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0_SW	BIT(4)
-#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1	BIT(8)
-#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1_SW	BIT(12)
-#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2	BIT(16)
-#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2_SW	BIT(20)
-
-#define ARRIA10_SYSMGR_SDMMC_SMPLSEL(smplsel)	(((smplsel) & 0x7) << 4)
-#define ARRIA10_SYSMGR_SDMMC_DRVSEL(drvsel)	((drvsel) & 0x7)
-
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
-	((drvsel << 0) & 0x7) | ((smplsel << 4) & 0x70)
-
-#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-xload.h b/arch/arm/mach-socfpga/include/mach/arria10-xload.h
deleted file mode 100644
index 7575231bbf..0000000000
--- a/arch/arm/mach-socfpga/include/mach/arria10-xload.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __MACH_ARRIA10_XLOAD_H
-#define __MACH_ARRIA10_XLOAD_H
-
-void arria10_init_mmc(void);
-int arria10_prepare_mmc(int barebox_part, int rbf_part);
-int arria10_read_blocks(void *dst, int blocknum, size_t len);
-int a10_update_bits(unsigned int reg, unsigned int mask, unsigned int val);
-
-struct partition {
-	uint64_t first_sec;
-	uint8_t type;
-};
-
-#endif /* __MACH_ARRIA10_XLOAD_H */
diff --git a/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h b/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h
deleted file mode 100644
index 28fb1c92fc..0000000000
--- a/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h
+++ /dev/null
@@ -1,42 +0,0 @@
-static inline void __barebox_arm_head(void)
-{
-	__asm__ __volatile__ (
-#ifdef CONFIG_THUMB2_BAREBOX
-		".arm\n"
-		"adr r9, 1f + 1\n"
-		"bx r9\n"
-		".thumb\n"
-		"1:\n"
-		"bl 2f\n"
-		".rept 10\n"
-		"1: b 1b\n"
-		".endr\n"
-#else
-		"b 2f\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-		"1: b 1b\n"
-#endif
-		".asciz \"barebox\"\n"
-		".word _text\n"				/* text base. If copied there,
-							 * barebox can skip relocation
-							 */
-		".word _barebox_image_size\n"		/* image size to copy */
-
-		".rept 10\n"
-		".word 0x55555555\n"
-		".endr\n"
-		"2:\n"
-	);
-}
-static inline void barebox_arm_head(void)
-{
-	__barebox_arm_head();
-	__asm__ __volatile__ (
-		"b barebox_arm_reset_vector\n"
-	);
-}
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h
deleted file mode 100644
index 797aa5d3cf..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef	_CLOCK_MANAGER_CYCLONE5_H_
-#define	_CLOCK_MANAGER_CYCLONE5_H_
-
-struct socfpga_cm_config {
-	/* main group */
-	uint32_t main_vco_base;
-	uint32_t mpuclk;
-	uint32_t mainclk;
-	uint32_t dbgatclk;
-	uint32_t mainqspiclk;
-	uint32_t mainnandsdmmcclk;
-	uint32_t cfg2fuser0clk;
-	uint32_t maindiv;
-	uint32_t dbgdiv;
-	uint32_t tracediv;
-	uint32_t l4src;
-
-	/* peripheral group */
-	uint32_t peri_vco_base;
-	uint32_t emac0clk;
-	uint32_t emac1clk;
-	uint32_t perqspiclk;
-	uint32_t pernandsdmmcclk;
-	uint32_t perbaseclk;
-	uint32_t s2fuser1clk;
-	uint32_t perdiv;
-	uint32_t gpiodiv;
-	uint32_t persrc;
-
-	/* sdram pll group */
-	uint32_t sdram_vco_base;
-	uint32_t ddrdqsclk;
-	uint32_t ddr2xdqsclk;
-	uint32_t ddrdqclk;
-	uint32_t s2fuser2clk;
-
-	/* altera group */
-	uint32_t alteragrp_mpu;
-	uint32_t alteregrp_main;
-};
-
-void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg);
-
-#define CLKMGR_CTRL_ADDRESS 0x0
-#define CLKMGR_BYPASS_ADDRESS 0x4
-#define CLKMGR_INTER_ADDRESS 0x8
-#define CLKMGR_INTREN_ADDRESS 0xc
-#define CLKMGR_DBCTRL_ADDRESS 0x10
-#define CLKMGR_STAT_ADDRESS 0x14
-#define CLKMGR_MAINPLLGRP_ADDRESS 0x40
-#define CLKMGR_MAINPLLGRP_VCO_ADDRESS 0x40
-#define CLKMGR_MAINPLLGRP_MISC_ADDRESS 0x44
-#define CLKMGR_MAINPLLGRP_MPUCLK_ADDRESS 0x48
-#define CLKMGR_MAINPLLGRP_MAINCLK_ADDRESS 0x4c
-#define CLKMGR_MAINPLLGRP_DBGATCLK_ADDRESS 0x50
-#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
-#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
-#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_ADDRESS 0x5c
-#define CLKMGR_MAINPLLGRP_EN_ADDRESS 0x60
-#define CLKMGR_MAINPLLGRP_MAINDIV_ADDRESS 0x64
-#define CLKMGR_MAINPLLGRP_DBGDIV_ADDRESS 0x68
-#define CLKMGR_MAINPLLGRP_TRACEDIV_ADDRESS 0x6c
-#define CLKMGR_MAINPLLGRP_L4SRC_ADDRESS 0x70
-#define CLKMGR_PERPLLGRP_ADDRESS 0x80
-#define CLKMGR_PERPLLGRP_VCO_ADDRESS 0x80
-#define CLKMGR_PERPLLGRP_MISC_ADDRESS 0x84
-#define CLKMGR_PERPLLGRP_EMAC0CLK_ADDRESS 0x88
-#define CLKMGR_PERPLLGRP_EMAC1CLK_ADDRESS 0x8c
-#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
-#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
-#define CLKMGR_PERPLLGRP_PERBASECLK_ADDRESS 0x98
-#define CLKMGR_PERPLLGRP_S2FUSER1CLK_ADDRESS 0x9c
-#define CLKMGR_PERPLLGRP_EN_ADDRESS 0xa0
-#define CLKMGR_PERPLLGRP_DIV_ADDRESS 0xa4
-#define CLKMGR_PERPLLGRP_GPIODIV_ADDRESS 0xa8
-#define CLKMGR_PERPLLGRP_SRC_ADDRESS 0xac
-#define CLKMGR_SDRPLLGRP_ADDRESS 0xc0
-#define CLKMGR_SDRPLLGRP_VCO_ADDRESS 0xc0
-#define CLKMGR_SDRPLLGRP_CTRL_ADDRESS 0xc4
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_ADDRESS 0xc8
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_ADDRESS 0xcc
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_ADDRESS 0xd0
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_ADDRESS 0xd4
-#define CLKMGR_SDRPLLGRP_EN_ADDRESS 0xd8
-#define CLKMGR_ALTERAGRP_MPUCLK 0xe0
-#define CLKMGR_ALTERAGRP_MAINCLK 0xe4
-
-#define CLKMGR_DBCTRL_STAYOSC1_MASK 0x00000001
-#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
-#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
-#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
-#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
-#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
-#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
-#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x)  (((x) << 7) & 0x00000380)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
-#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
-#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
-#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
-#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
-#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
-#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
-#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
-#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
-#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
-#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
-#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
-#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
-#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
-#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
-#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
-#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
-#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
-#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
-#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
-#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
-#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
-#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
-#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
-#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
-#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
-#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
-#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
-#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
-#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
-#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
-#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
-#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
-#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
-#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
-#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
-
-#define CLEAR_BGP_EN_PWRDN \
-	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
-	CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
-	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
-#endif
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h b/arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h
deleted file mode 100644
index 93ce5152ed..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _CYCLONE5_FREEZE_CONTROLLER_H_
-#define _CYCLONE5_FREEZE_CONTROLLER_H_
-
-#include <mach/cyclone5-regs.h>
-
-#define SYSMGR_FRZCTRL_ADDRESS		0x40
-#define SYSMGR_FRZCTRL_VIOCTRL_ADDRESS	0x40
-#define SYSMGR_FRZCTRL_HIOCTRL_ADDRESS	0x50
-#define SYSMGR_FRZCTRL_SRC_ADDRESS	0x54
-#define SYSMGR_FRZCTRL_HWCTRL_ADDRESS	0x58
-
-#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
-#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
-#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
-#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
-#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
-#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
-#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
-#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
-#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
-#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
-#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
-#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
-#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
-#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
-#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
-#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
-#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
-#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
-#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
-
-#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_GET(x) (((x) & 0x00000006) >> 1)
-
-/*
- * FreezeChannelSelect
- * Definition of enum for freeze channel
- */
-enum frz_channel_id {
-	FREEZE_CHANNEL_0 = 0,   /* EMAC_IO & MIXED2_IO */
-	FREEZE_CHANNEL_1,   /* MIXED1_IO and FLASH_IO */
-	FREEZE_CHANNEL_2,   /* General IO */
-	FREEZE_CHANNEL_3,   /* DDR IO */
-};
-
-/* Shift count needed to calculte for FRZCTRL VIO control register offset */
-#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT    (2)
-
-/*
- * Freeze HPS IOs
- *
- * FreezeChannelSelect [in] - Freeze channel ID
- * FreezeControllerFSMSelect [in] - To use hardware or software state machine
- * If FREEZE_CONTROLLER_FSM_HW is selected for FSM select then the
- *       the freeze channel id is input is ignored. It is default to channel 1
- */
-int sys_mgr_frzctrl_freeze_req(enum frz_channel_id channel_id);
-
-/*
- * Unfreeze/Thaw HPS IOs
- *
- * FreezeChannelSelect [in] - Freeze channel ID
- * FreezeControllerFSMSelect [in] - To use hardware or software state machine
- * If FREEZE_CONTROLLER_FSM_HW is selected for FSM select then the
- *       the freeze channel id is input is ignored. It is default to channel 1
- */
-int sys_mgr_frzctrl_thaw_req(enum frz_channel_id channel_id);
-
-#endif	/* _FREEZE_CONTROLLER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
deleted file mode 100644
index e88daf7189..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __MACH_SOCFPGA_REGS_H
-#define __MACH_SOCFPGA_REGS_H
-
-#define CYCLONE5_SDMMC_ADDRESS		0xff704000
-#define CYCLONE5_QSPI_CTRL_ADDRESS	0xff705000
-#define CYCLONE5_QSPI_DATA_ADDRESS	0xffa00000
-#define CYCLONE5_FPGAMGRREGS_ADDRESS	0xff706000
-#define CYCLONE5_GPIO0_BASE		0xff708000
-#define CYCLONE5_GPIO1_BASE		0xff709000
-#define CYCLONE5_GPIO2_BASE		0xff70A000
-#define CYCLONE5_L3REGS_ADDRESS		0xff800000
-#define CYCLONE5_FPGAMGRDATA_ADDRESS	0xffb90000
-#define CYCLONE5_UART0_ADDRESS		0xffc02000
-#define CYCLONE5_UART1_ADDRESS		0xffc03000
-#define CYCLONE5_SDR_ADDRESS		0xffc20000
-#define CYCLONE5_CLKMGR_ADDRESS		0xffd04000
-#define CYCLONE5_RSTMGR_ADDRESS		0xffd05000
-#define CYCLONE5_SYSMGR_ADDRESS		0xffd08000
-#define CYCLONE5_SCANMGR_ADDRESS	0xfff02000
-#define CYCLONE5_SMP_TWD_ADDRESS	0xfffec600
-
-#endif /* __MACH_SOCFPGA_REGS_H */
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h
deleted file mode 100644
index 899401ce3c..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef	_RESET_MANAGER_H_
-#define	_RESET_MANAGER_H_
-
-#define RESET_MGR_STATUS_OFS		0x0
-#define RESET_MGR_CTRL_OFS		0x4
-#define RESET_MGR_COUNTS_OFS		0x8
-#define RESET_MGR_MPU_MOD_RESET_OFS	0x10
-#define RESET_MGR_PER_MOD_RESET_OFS	0x14
-#define RESET_MGR_PER2_MOD_RESET_OFS	0x18
-#define RESET_MGR_BRG_MOD_RESET_OFS	0x1c
-
-#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
-#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8
-
-#define RSTMGR_PERMODRST_EMAC0_LSB 0
-#define RSTMGR_PERMODRST_EMAC1_LSB 1
-#define RSTMGR_PERMODRST_L4WD0_LSB 6
-#define RSTMGR_PERMODRST_SDR_LSB 29
-#define RSTMGR_BRGMODRST_HPS2FPGA_MASK		0x00000001
-#define RSTMGR_BRGMODRST_LWHPS2FPGA_MASK	0x00000002
-#define RSTMGR_BRGMODRST_FPGA2HPS_MASK		0x00000004
-
-/* Warm Reset mask */
-#define RSTMGR_STAT_L4WD1RST_MASK		0x00008000
-#define RSTMGR_STAT_L4WD0RST_MASK		0x00004000
-#define RSTMGR_STAT_MPUWD1RST_MASK		0x00002000
-#define RSTMGR_STAT_MPUWD0RST_MASK		0x00001000
-#define RSTMGR_STAT_SWWARMRST_MASK		0x00000400
-#define RSTMGR_STAT_FPGAWARMRST_MASK		0x00000200
-#define RSTMGR_STAT_NRSTPINRST_MASK		0x00000100
-#define RSTMGR_WARMRST_MASK			0x0000f700
-
-#define RSTMGR_CTRL_SDRSELFREFEN_MASK		0x00000010
-#define RSTMGR_CTRL_FPGAHSEN_MASK		0x00010000
-#define RSTMGR_CTRL_ETRSTALLEN_MASK		0x00100000
-
-#define RSTMGR_PERMODRST_EMAC0		(1 << 0)
-#define RSTMGR_PERMODRST_EMAC1		(1 << 1)
-#define RSTMGR_PERMODRST_USB0		(1 << 2)
-#define RSTMGR_PERMODRST_USB1		(1 << 3)
-#define RSTMGR_PERMODRST_NAND		(1 << 4)
-#define RSTMGR_PERMODRST_QSPI		(1 << 5)
-#define RSTMGR_PERMODRST_L4WD0		(1 << 6)
-#define RSTMGR_PERMODRST_L4WD1		(1 << 7)
-#define RSTMGR_PERMODRST_OSC1TIMER1	(1 << 9)
-#define RSTMGR_PERMODRST_SPTIMER0	(1 << 10)
-#define RSTMGR_PERMODRST_SPTIMER1	(1 << 11)
-#define RSTMGR_PERMODRST_I2C0		(1 << 12)
-#define RSTMGR_PERMODRST_I2C1		(1 << 13)
-#define RSTMGR_PERMODRST_I2C2		(1 << 14)
-#define RSTMGR_PERMODRST_I2C3		(1 << 15)
-#define RSTMGR_PERMODRST_UART0		(1 << 16)
-#define RSTMGR_PERMODRST_UART1		(1 << 17)
-#define RSTMGR_PERMODRST_SPIM0		(1 << 18)
-#define RSTMGR_PERMODRST_SPIM1		(1 << 19)
-#define RSTMGR_PERMODRST_SPIS0		(1 << 20)
-#define RSTMGR_PERMODRST_SPIS1		(1 << 21)
-#define RSTMGR_PERMODRST_SDMMC		(1 << 22)
-#define RSTMGR_PERMODRST_CAN0		(1 << 23)
-#define RSTMGR_PERMODRST_CAN1		(1 << 24)
-#define RSTMGR_PERMODRST_GPIO0		(1 << 25)
-#define RSTMGR_PERMODRST_GPIO1		(1 << 26)
-#define RSTMGR_PERMODRST_GPIO2		(1 << 27)
-#define RSTMGR_PERMODRST_DMA		(1 << 28)
-#define RSTMGR_PERMODRST_SDR		(1 << 29)
-
-#define RSTMGR_PER2MODRST_DMAIF0	(1 << 0)
-#define RSTMGR_PER2MODRST_DMAIF1	(1 << 1)
-#define RSTMGR_PER2MODRST_DMAIF2	(1 << 2)
-#define RSTMGR_PER2MODRST_DMAIF3	(1 << 3)
-#define RSTMGR_PER2MODRST_DMAIF4	(1 << 4)
-#define RSTMGR_PER2MODRST_DMAIF5	(1 << 5)
-#define RSTMGR_PER2MODRST_DMAIF6	(1 << 6)
-#define RSTMGR_PER2MODRST_DMAIF7	(1 << 7)
-
-#endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h
deleted file mode 100644
index df720a7e08..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _SCAN_MANAGER_H_
-#define _SCAN_MANAGER_H_
-
-#include <io.h>
-#include <mach/cyclone5-regs.h>
-
-/***********************************************************
- *                                                         *
- * Cyclone5 specific stuff. Get rid of this.               *
- *                                                         *
- ***********************************************************/
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH        (764)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH        (1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH        (955)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH        (16766)
-
-typedef unsigned long Scan_mgr_entry_t;
-
-#define NUM_OF_CHAINS     (4)
-#define SHIFT_COUNT_32BIT (5)
-#define MASK_COUNT_32BIT  (0x1F)
-
-#define SCANMGR_STAT_ADDRESS 0x0
-#define SCANMGR_EN_ADDRESS 0x4
-#define SCANMGR_FIFOSINGLEBYTE_ADDRESS 0x10
-#define SCANMGR_FIFODOUBLEBYTE_ADDRESS 0x14
-#define SCANMGR_FIFOQUADBYTE_ADDRESS 0x1c
-
-#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31)
-#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28)
-
-enum io_scan_chain {
-	IO_SCAN_CHAIN_0 = 0,    /* EMAC_IO and MIXED2_IO */
-	IO_SCAN_CHAIN_1,        /* MIXED1_IO and FLASH_IO */
-	IO_SCAN_CHAIN_2,        /* General IO */
-	IO_SCAN_CHAIN_3,        /* DDR IO */
-	IO_SCAN_CHAIN_UNDEFINED
-};
-
-#define IO_SCAN_CHAIN_NUM		NUM_OF_CHAINS
-/* Maximum number of IO scan chains */
-
-#define IO_SCAN_CHAIN_128BIT_SHIFT	(7)
-/*
- * Shift count to get number of IO scan chain data in granularity
- * of 128-bit ( N / 128 )
- */
-
-#define IO_SCAN_CHAIN_128BIT_MASK	(0x7F)
-/*
- * Mask to get residual IO scan chain data in
- * granularity of 128-bit ( N mod 128 )
- */
-
-#define IO_SCAN_CHAIN_32BIT_SHIFT	SHIFT_COUNT_32BIT
-/*
- * Shift count to get number of IO scan chain
- * data in granularity of 32-bit ( N / 32 )
- */
-
-#define IO_SCAN_CHAIN_32BIT_MASK	MASK_COUNT_32BIT
-/*
- * Mask to get residual IO scan chain data in
- * granularity of 32-bit ( N mod 32 )
- */
-
-#define IO_SCAN_CHAIN_BYTE_MASK		(0xFF)
-/* Byte mask */
-
-#define IO_SCAN_CHAIN_PAYLOAD_24BIT	(24)
-/* 24-bits (3 bytes) IO scan chain payload definition */
-
-#define TDI_TDO_MAX_PAYLOAD		(127)
-/*
- * Maximum length of TDI_TDO packet payload is 128 bits,
- * represented by (length - 1) in TDI_TDO header
- */
-
-#define TDI_TDO_HEADER_FIRST_BYTE	(0x80)
-/* TDI_TDO packet header for IO scan chain program */
-
-#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT	(8)
-/* Position of second command byte for TDI_TDO packet */
-
-#define MAX_WAITING_DELAY_IO_SCAN_ENGINE	(100)
-/*
- * Maximum polling loop to wait for IO scan chain engine
- * becomes idle to prevent infinite loop
- */
-
-/*
- * scan_mgr_io_scan_chain_prg
- *
- * Program HPS IO Scan Chain
- *
- * io_scan_chain_id @ref IOScanChainSelect [in] - IO scan chain ID with
- *        range of enumIOScanChainSelect *
- * io_scan_chain_len_in_bits uint32_t [in] - IO scan chain length in bits
- * *iocsr_scan_chain @ref Scan_mgr_entry_t [in] - IO scan chain table
- */
-int scan_mgr_io_scan_chain_prg(enum io_scan_chain io_scan_chain_id,
-		uint32_t io_scan_chain_len_in_bits,
-		const unsigned long *iocsr_scan_chain);
-
-struct socfpga_io_config {
-	unsigned long *pinmux;
-	unsigned int num_pin;
-	const unsigned long *iocsr_emac_mixed2;
-	const unsigned long *iocsr_mixed1_flash;
-	const unsigned long *iocsr_general;
-	const unsigned long *iocsr_ddr;
-};
-
-#endif	/* _SCAN_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h
deleted file mode 100644
index a19a837994..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h
+++ /dev/null
@@ -1,161 +0,0 @@
-#ifndef __MACH_SDRAM_CONFIG_H
-#define __MACH_SDRAM_CONFIG_H
-
-#include <mach/cyclone5-sdram.h>
-#include <mach/cyclone5-regs.h>
-#include <mach/cyclone5-system-manager.h>
-
-static inline void sdram_write(unsigned register_offset, unsigned val)
-{
-	debug("0x%08x Data 0x%08x\n",
-		(CYCLONE5_SDR_ADDRESS + register_offset), val);
-	/* Write to register */
-	writel(val, (CYCLONE5_SDR_ADDRESS + register_offset));
-}
-
-static inline void socfpga_sdram_mmr_init(void)
-{
-	uint32_t val;
-
-	val = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << SDR_CTRLGRP_CTRLCFG_MEMBL_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << SDR_CTRLGRP_CTRLCFG_ECCEN_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB;
-	sdram_write(SDR_CTRLGRP_CTRLCFG_ADDRESS, val);
-
-	val =  CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << SDR_CTRLGRP_DRAMTIMING1_TAL_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<  SDR_CTRLGRP_DRAMTIMING1_TCL_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB;
-	sdram_write(SDR_CTRLGRP_DRAMTIMING1_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << SDR_CTRLGRP_DRAMTIMING2_TRP_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << SDR_CTRLGRP_DRAMTIMING2_TWR_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB;
-	sdram_write(SDR_CTRLGRP_DRAMTIMING2_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << SDR_CTRLGRP_DRAMTIMING3_TRC_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB;
-	sdram_write(SDR_CTRLGRP_DRAMTIMING3_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB;
-	sdram_write(SDR_CTRLGRP_DRAMTIMING4_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB;
-	sdram_write(SDR_CTRLGRP_LOWPWRTIMING_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS << SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
-	sdram_write(SDR_CTRLGRP_DRAMADDRW_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB;
-	sdram_write(SDR_CTRLGRP_DRAMIFWIDTH_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB;
-	sdram_write(SDR_CTRLGRP_DRAMDEVWIDTH_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << SDR_CTRLGRP_DRAMINTR_INTREN_LSB;
-	sdram_write(SDR_CTRLGRP_DRAMINTR_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << SDR_CTRLGRP_STATICCFG_MEMBL_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB;
-	sdram_write(SDR_CTRLGRP_STATICCFG_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB;
-	sdram_write(SDR_CTRLGRP_CTRLWIDTH_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB;
-	sdram_write(SDR_CTRLGRP_PORTCFG_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB;
-	sdram_write(SDR_CTRLGRP_FIFOCFG_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB;
-	sdram_write(SDR_CTRLGRP_MPPRIORITY_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB;
-	sdram_write(SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB;
-	sdram_write(SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB;
-	sdram_write(SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB;
-	sdram_write(SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB;
-	sdram_write(SDR_CTRLGRP_MPPACING_MPPACING_0_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB;
-	sdram_write(SDR_CTRLGRP_MPPACING_MPPACING_1_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB;
-	sdram_write(SDR_CTRLGRP_MPPACING_MPPACING_2_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB;
-	sdram_write(SDR_CTRLGRP_MPPACING_MPPACING_3_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
-		SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB;
-	sdram_write(SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
-		SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB;
-	sdram_write(SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
-		SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB;
-	sdram_write(SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0;
-	sdram_write(SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB;
-	sdram_write(SDR_CTRLGRP_CPORTWIDTH_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB;
-	sdram_write(SDR_CTRLGRP_CPORTWMAP_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB;
-	sdram_write(SDR_CTRLGRP_CPORTRMAP_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB;
-	sdram_write(SDR_CTRLGRP_RFIFOCMAP_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB;
-	sdram_write(SDR_CTRLGRP_WFIFOCMAP_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB;
-	sdram_write(SDR_CTRLGRP_CPORTRDWR_ADDRESS, val);
-
-	val = CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << SDR_CTRLGRP_DRAMODT_READ_LSB |
-		CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << SDR_CTRLGRP_DRAMODT_WRITE_LSB;
-	sdram_write(SDR_CTRLGRP_DRAMODT_ADDRESS, val);
-
-	val = readl(CYCLONE5_SDR_ADDRESS + SDR_CTRLGRP_STATICCFG_ADDRESS);
-	val &= ~(SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK);
-	val |= 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB;
-	writel(val, (CYCLONE5_SDR_ADDRESS + SDR_CTRLGRP_STATICCFG_ADDRESS));
-}
-#endif /* __MACH_SDRAM_CONFIG_H */
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h
deleted file mode 100644
index ebd331e83e..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h
+++ /dev/null
@@ -1,399 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef	_SDRAM_H_
-#define	_SDRAM_H_
-
-/* Group: sdr.phygrp.sccgrp                                                */
-#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
-/* Group: sdr.phygrp.phymgrgrp                                             */
-#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000
-/* Group: sdr.phygrp.rwmgrgrp                                              */
-#define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000
-/* Group: sdr.phygrp.datamgrgrp                                            */
-#define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000
-/* Group: sdr.phygrp.regfilegrp                                            */
-#define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800
-/* Group: sdr.ctrlgrp                                                      */
-#define SDR_CTRLGRP_ADDRESS 0x5000
-/* Register: sdr.ctrlgrp.ctrlcfg                                           */
-#define SDR_CTRLGRP_CTRLCFG_ADDRESS 0x5000
-/* Register: sdr.ctrlgrp.dramtiming1                                       */
-#define SDR_CTRLGRP_DRAMTIMING1_ADDRESS 0x5004
-/* Register: sdr.ctrlgrp.dramtiming2                                       */
-#define SDR_CTRLGRP_DRAMTIMING2_ADDRESS 0x5008
-/* Register: sdr.ctrlgrp.dramtiming3                                       */
-#define SDR_CTRLGRP_DRAMTIMING3_ADDRESS 0x500c
-/* Register: sdr.ctrlgrp.dramtiming4                                       */
-#define SDR_CTRLGRP_DRAMTIMING4_ADDRESS 0x5010
-/* Register: sdr.ctrlgrp.lowpwrtiming                                      */
-#define SDR_CTRLGRP_LOWPWRTIMING_ADDRESS 0x5014
-/* Register: sdr.ctrlgrp.dramodt                                           */
-#define SDR_CTRLGRP_DRAMODT_ADDRESS 0x5018
-/* Register: sdr.ctrlgrp.dramaddrw                                         */
-#define SDR_CTRLGRP_DRAMADDRW_ADDRESS 0x502c
-/* Register: sdr.ctrlgrp.dramifwidth                                       */
-#define SDR_CTRLGRP_DRAMIFWIDTH_ADDRESS 0x5030
-/* Register: sdr.ctrlgrp.dramdevwidth                                      */
-#define SDR_CTRLGRP_DRAMDEVWIDTH_ADDRESS 0x5034
-/* Register: sdr.ctrlgrp.dramsts                                           */
-#define SDR_CTRLGRP_DRAMSTS_ADDRESS 0x5038
-/* Register: sdr.ctrlgrp.dramintr                                          */
-#define SDR_CTRLGRP_DRAMINTR_ADDRESS 0x503c
-/* Register: sdr.ctrlgrp.sbecount                                          */
-#define SDR_CTRLGRP_SBECOUNT_ADDRESS 0x5040
-/* Register: sdr.ctrlgrp.dbecount                                          */
-#define SDR_CTRLGRP_DBECOUNT_ADDRESS 0x5044
-/* Register: sdr.ctrlgrp.erraddr                                           */
-#define SDR_CTRLGRP_ERRADDR_ADDRESS 0x5048
-/* Register: sdr.ctrlgrp.dropcount                                         */
-#define SDR_CTRLGRP_DROPCOUNT_ADDRESS 0x504c
-/* Register: sdr.ctrlgrp.dropaddr                                          */
-#define SDR_CTRLGRP_DROPADDR_ADDRESS 0x5050
-/* Register: sdr.ctrlgrp.staticcfg                                         */
-#define SDR_CTRLGRP_STATICCFG_ADDRESS 0x505c
-/* Register: sdr.ctrlgrp.ctrlwidth                                         */
-#define SDR_CTRLGRP_CTRLWIDTH_ADDRESS 0x5060
-/* Register: sdr.ctrlgrp.cportwidth                                        */
-#define SDR_CTRLGRP_CPORTWIDTH_ADDRESS 0x5064
-/* Register: sdr.ctrlgrp.cportwmap                                         */
-#define SDR_CTRLGRP_CPORTWMAP_ADDRESS 0x5068
-/* Register: sdr.ctrlgrp.cportrmap                                         */
-#define SDR_CTRLGRP_CPORTRMAP_ADDRESS 0x506c
-/* Register: sdr.ctrlgrp.rfifocmap                                         */
-#define SDR_CTRLGRP_RFIFOCMAP_ADDRESS 0x5070
-/* Register: sdr.ctrlgrp.wfifocmap                                         */
-#define SDR_CTRLGRP_WFIFOCMAP_ADDRESS 0x5074
-/* Register: sdr.ctrlgrp.cportrdwr                                         */
-#define SDR_CTRLGRP_CPORTRDWR_ADDRESS 0x5078
-/* Register: sdr.ctrlgrp.portcfg                                           */
-#define SDR_CTRLGRP_PORTCFG_ADDRESS 0x507c
-/* Register: sdr.ctrlgrp.fpgaportrst                                       */
-#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
-/* Register: sdr.ctrlgrp.fifocfg                                           */
-#define SDR_CTRLGRP_FIFOCFG_ADDRESS 0x5088
-/* Register: sdr.ctrlgrp.mppriority                                        */
-#define SDR_CTRLGRP_MPPRIORITY_ADDRESS 0x50ac
-/* Wide Register: sdr.ctrlgrp.mpweight                                     */
-#define SDR_CTRLGRP_MPWEIGHT_ADDRESS 0x50b0
-/* Register: sdr.ctrlgrp.mpweight.mpweight_0                               */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_ADDRESS 0x50b0
-/* Register: sdr.ctrlgrp.mpweight.mpweight_1                               */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_ADDRESS 0x50b4
-/* Register: sdr.ctrlgrp.mpweight.mpweight_2                               */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_ADDRESS 0x50b8
-/* Register: sdr.ctrlgrp.mpweight.mpweight_3                               */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_ADDRESS 0x50bc
-/* Register: sdr.ctrlgrp.mppacing.mppacing_0                               */
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_ADDRESS 0x50c0
-/* Register: sdr.ctrlgrp.mppacing.mppacing_1                               */
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_ADDRESS 0x50c4
-/* Register: sdr.ctrlgrp.mppacing.mppacing_2                               */
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_ADDRESS 0x50c8
-/* Register: sdr.ctrlgrp.mppacing.mppacing_3                               */
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_ADDRESS 0x50cc
-/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_0                   */
-#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_ADDRESS 0x50d0
-/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_1                   */
-#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_ADDRESS 0x50d4
-/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_2                   */
-#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_ADDRESS 0x50d8
-/* Wide Register: sdr.ctrlgrp.phyctrl                                      */
-#define SDR_CTRLGRP_PHYCTRL_ADDRESS 0x5150
-/* Register: sdr.ctrlgrp.phyctrl.phyctrl_0                                 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDRESS 0x5150
-/* Register: sdr.ctrlgrp.phyctrl.phyctrl_1                                 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_ADDRESS 0x5154
-/* Register: sdr.ctrlgrp.phyctrl.phyctrl_2                                 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_ADDRESS 0x5158
-/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_0                      */
-/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_0          */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
-/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_1                      */
-/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_1          */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
-/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_2                      */
-/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_2          */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
-
-/* Register template: sdr::ctrlgrp::ctrlcfg                                */
-#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_LSB 26
-#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_MASK 0x04000000
-#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_LSB 25
-#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_MASK 0x02000000
-#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_LSB 24
-#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_MASK 0x01000000
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
-#define SDR_CTRLGRP_CTRLCFG_GENDBE_LSB 14
-#define SDR_CTRLGRP_CTRLCFG_GENDBE_MASK 0x00004000
-#define SDR_CTRLGRP_CTRLCFG_GENSBE_LSB 13
-#define SDR_CTRLGRP_CTRLCFG_GENSBE_MASK 0x00002000
-#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_LSB 12
-#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_MASK 0x00001000
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
-/* Register template: sdr::ctrlgrp::dramtiming1                            */
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming2                            */
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
-/* Register template: sdr::ctrlgrp::dramtiming3                            */
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming4                            */
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::lowpwrtiming                           */
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
-/* Register template: sdr::ctrlgrp::dramaddrw                              */
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
-/* Register template: sdr::ctrlgrp::dramifwidth                            */
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::dramdevwidth                           */
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramintr                               */
-#define SDR_CTRLGRP_DRAMINTR_INTRCLR_LSB 4
-#define SDR_CTRLGRP_DRAMINTR_INTRCLR_MASK 0x00000010
-#define SDR_CTRLGRP_DRAMINTR_CORRDROPMASK_LSB 3
-#define SDR_CTRLGRP_DRAMINTR_CORRDROPMASK_MASK 0x00000008
-#define SDR_CTRLGRP_DRAMINTR_DBEMASK_LSB 2
-#define SDR_CTRLGRP_DRAMINTR_DBEMASK_MASK 0x00000004
-#define SDR_CTRLGRP_DRAMINTR_SBEMASK_LSB 1
-#define SDR_CTRLGRP_DRAMINTR_SBEMASK_MASK 0x00000002
-#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
-#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
-/* Register template: sdr::ctrlgrp::sbecount                               */
-#define SDR_CTRLGRP_SBECOUNT_COUNT_LSB 0
-#define SDR_CTRLGRP_SBECOUNT_COUNT_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::dbecount                               */
-#define SDR_CTRLGRP_DBECOUNT_COUNT_LSB 0
-#define SDR_CTRLGRP_DBECOUNT_COUNT_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::staticcfg                              */
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
-#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
-#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::ctrlwidth                              */
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::cportwidth                             */
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::cportwmap                              */
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::cportrmap                              */
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::rfifocmap                              */
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::wfifocmap                              */
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::cportrdwr                              */
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::portcfg                                */
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::fifocfg                                */
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::mppriority                             */
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
-/* Wide Register template: sdr::ctrlgrp::mpweight                          */
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_0                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_1                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_2                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_3                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
-/* Wide Register template: sdr::ctrlgrp::mppacing                          */
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_0                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_1                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_2                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_3                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
-/* Wide Register template: sdr::ctrlgrp::mpthresholdrst                    */
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
-#define  \
-SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
-0x0000ffff
-/* Register template: sdr::ctrlgrp::remappriority                          */
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
-/* Wide Register template: sdr::ctrlgrp::phyctrl                           */
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_MASK 0xfffff000
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_LSB 10
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_MASK 0x00000c00
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
- (((x) << 10) & 0x00000c00)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_LSB 9
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_MASK 0x00000200
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
- (((x) << 9) & 0x00000200)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_LSB 8
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_MASK 0x00000100
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
- (((x) << 8) & 0x00000100)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_LSB 6
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_MASK 0x000000c0
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
- (((x) << 6) & 0x000000c0)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_LSB 4
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_MASK 0x00000030
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
- (((x) << 4) & 0x00000030)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_LSB 2
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_MASK 0x0000000c
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
- (((x) << 2) & 0x0000000c)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_LSB 0
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_MASK 0x00000003
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
- (((x) << 0) & 0x00000003)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_LSB 12
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_MASK 0xfffff000
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_LSB 0
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_MASK 0x00000fff
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_LSB 0
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_MASK 0x00000fff
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::dramodt                                */
-#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
-#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
-#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
-#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::fpgaportrst                            */
-#define SDR_CTRLGRP_FPGAPORTRST_READ_PORT_0_LSB 0
-#define SDR_CTRLGRP_FPGAPORTRST_WRITE_PORT_0_LSB 4
-#define SDR_CTRLGRP_FPGAPORTRST_COMMAND_PORT_0_LSB 8
-/* Field instance: sdr::ctrlgrp::dramsts                                   */
-#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
-#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
-
-#endif /* _SDRAM_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
deleted file mode 100644
index e5ecb0f1b8..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
+++ /dev/null
@@ -1,5241 +0,0 @@
-/*
-* Copyright Altera Corporation (C) 2012-2014. All rights reserved
-*
-* SPDX-License-Identifier:  BSD-3-Clause
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*  * Redistributions of source code must retain the above copyright
-*  notice, this list of conditions and the following disclaimer.
-*  * Redistributions in binary form must reproduce the above copyright
-*  notice, this list of conditions and the following disclaimer in the
-*  documentation and/or other materials provided with the distribution.
-*  * Neither the name of Altera Corporation nor the
-*  names of its contributors may be used to endorse or promote products
-*  derived from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "system.h"
-#include "sdram_io.h"
-#include "cyclone5-sequencer.h"
-#include "tclrpt.h"
-
-/******************************************************************************
- ******************************************************************************
- ** NOTE: Special Rules for Globale Variables                                **
- **                                                                          **
- ** All global variables that are explicitly initialized (including          **
- ** explicitly initialized to zero), are only initialized once, during       **
- ** configuration time, and not again on reset.  This means that they        **
- ** preserve their current contents across resets, which is needed for some  **
- ** special cases involving communication with external modules.  In         **
- ** addition, this avoids paying the price to have the memory initialized,   **
- ** even for zeroed data, provided it is explicitly set to zero in the code, **
- ** and doesn't rely on implicit initialization.                             **
- ******************************************************************************
- ******************************************************************************/
-
-#ifndef ARMCOMPILER
-
-// Temporary workaround to place the initial stack pointer at a safe offset from end
-#define STRINGIFY(s)		STRINGIFY_STR(s)
-#define STRINGIFY_STR(s)	#s
-asm(".global __alt_stack_pointer");
-asm("__alt_stack_pointer = " STRINGIFY(STACK_POINTER));
-#endif
-
-#include <mach/cyclone5-sdram.h>
-
-#define NEWVERSION_RDDESKEW 1
-#define NEWVERSION_WRDESKEW 1
-#define NEWVERSION_GW 1
-#define NEWVERSION_WL 1
-#define NEWVERSION_DQSEN 1
-
-// Just to make the debugging code more uniform
-
-#define HALF_RATE_MODE 0
-
-#define QUARTER_RATE_MODE 0
-#define DELTA_D 1
-
-// case:56390
-// VFIFO_CONTROL_WIDTH_PER_DQS is the number of VFIFOs actually instantiated per DQS. This is always one except:
-// AV QDRII where it is 2 for x18 and x18w2, and 4 for x36 and x36w2
-// RLDRAMII x36 and x36w2 where it is 2.
-// In 12.0sp1 we set this to 4 for all of the special cases above to keep it simple.
-// In 12.0sp2 or 12.1 this should get moved to generation and unified with the same constant used in the phy mgr
-
-#define VFIFO_CONTROL_WIDTH_PER_DQS 1
-
-// In order to reduce ROM size, most of the selectable calibration steps are
-// decided at compile time based on the user's calibration mode selection,
-// as captured by the STATIC_CALIB_STEPS selection below.
-//
-// However, to support simulation-time selection of fast simulation mode, where
-// we skip everything except the bare minimum, we need a few of the steps to
-// be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
-// check, which is based on the rtl-supplied value, or we dynamically compute the
-// value to use based on the dynamically-chosen calibration mode
-
-#define BTFLD_FMT "%lx"
-
-// For HPS running on actual hardware
-
-#define DLEVEL 0
-#ifdef HPS_HW_SERIAL_SUPPORT
-// space around comma is required for varargs macro to remove comma if args is empty
-#define DPRINT(level, fmt, args...) 	if (DLEVEL >= (level)) printf("SEQ.C: " fmt "\n" , ## args)
-#define IPRINT(fmt, args...) 	        printf("SEQ.C: " fmt "\n" , ## args)
-#else
-#define DPRINT(level, fmt, args...)
-#define IPRINT(fmt, args...)
-#endif
-#define BFM_GBL_SET(field,value)
-#define BFM_GBL_GET(field) 		((long unsigned int)0)
-#define BFM_STAGE(stage)
-#define BFM_INC_VFIFO
-#define COV(label)
-
-#define TRACE_FUNC(fmt, args...) DPRINT(1, "%s[%d]: " fmt, __func__, __LINE__ , ## args)
-
-#define DYNAMIC_CALIB_STEPS (dyn_calib_steps)
-
-#define STATIC_IN_RTL_SIM 0
-
-#define STATIC_SKIP_DELAY_LOOPS 0
-
-#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | STATIC_SKIP_DELAY_LOOPS)
-
-// calibration steps requested by the rtl
-static uint16_t dyn_calib_steps = 0;
-
-// To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
-// instead of static, we use boolean logic to select between
-// non-skip and skip values
-//
-// The mask is set to include all bits when not-skipping, but is
-// zero when skipping
-
-static uint16_t skip_delay_mask = 0;	// mask off bits when skipping/not-skipping
-
-#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
-	((non_skip_value) & skip_delay_mask)
-
-// TODO: The skip group strategy is completely missing
-
-static gbl_t *gbl = 0;
-static param_t *param = 0;
-
-static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, uint32_t write_group,
-						uint32_t use_dm, uint32_t all_correct,
-						t_btfld * bit_chk, uint32_t all_ranks);
-
-// This (TEST_SIZE) is used to test handling of large roms, to make
-// sure we are sizing things correctly
-// Note, the initialized data takes up twice the space in rom, since
-// there needs to be a copy with the initial value and a copy that is
-// written too, since on soft-reset, it needs to have the initial values
-// without reloading the memory from external sources
-
-// #define TEST_SIZE    (6*1024)
-
-#ifdef TEST_SIZE
-
-#define PRE_POST_TEST_SIZE 3
-
-static unsigned int pre_test_size_mem[PRE_POST_TEST_SIZE] = { 1, 2, 3 };
-
-static unsigned int test_size_mem[TEST_SIZE / sizeof(unsigned int)] = { 100, 200, 300 };
-
-static unsigned int post_test_size_mem[PRE_POST_TEST_SIZE] = { 10, 20, 30 };
-
-static void write_test_mem(void)
-{
-	int i;
-
-	for (i = 0; i < PRE_POST_TEST_SIZE; i++) {
-		pre_test_size_mem[i] = (i + 1) * 10;
-		post_test_size_mem[i] = (i + 1);
-	}
-
-	for (i = 0; i < sizeof(test_size_mem) / sizeof(unsigned int); i++) {
-		test_size_mem[i] = i;
-	}
-
-}
-
-static int check_test_mem(int start)
-{
-	int i;
-
-	for (i = 0; i < PRE_POST_TEST_SIZE; i++) {
-		if (start) {
-			if (pre_test_size_mem[i] != (i + 1)) {
-				return 0;
-			}
-			if (post_test_size_mem[i] != (i + 1) * 10) {
-				return 0;
-			}
-		} else {
-			if (pre_test_size_mem[i] != (i + 1) * 10) {
-				return 0;
-			}
-			if (post_test_size_mem[i] != (i + 1)) {
-				return 0;
-			}
-		}
-	}
-
-	for (i = 0; i < sizeof(test_size_mem) / sizeof(unsigned int); i++) {
-		if (start) {
-			if (i < 3) {
-				if (test_size_mem[i] != (i + 1) * 100) {
-					return 0;
-				}
-			} else {
-				if (test_size_mem[i] != 0) {
-					return 0;
-				}
-			}
-		} else {
-			if (test_size_mem[i] != i) {
-				return 0;
-			}
-		}
-	}
-
-	return 1;
-}
-
-#endif // TEST_SIZE
-
-static void set_failing_group_stage(uint32_t group, uint32_t stage, uint32_t substage)
-{
-	if (gbl->error_stage == CAL_STAGE_NIL) {
-		gbl->error_substage = substage;
-		gbl->error_stage = stage;
-		gbl->error_group = group;
-
-	}
-
-}
-
-static inline void reg_file_set_group(uint32_t set_group)
-{
-	// Read the current group and stage
-	uint32_t cur_stage_group = IORD_32DIRECT(REG_FILE_CUR_STAGE, 0);
-
-	// Clear the group
-	cur_stage_group &= 0x0000FFFF;
-
-	// Set the group
-	cur_stage_group |= (set_group << 16);
-
-	// Write the data back
-	IOWR_32DIRECT(REG_FILE_CUR_STAGE, 0, cur_stage_group);
-}
-
-static inline void reg_file_set_stage(uint32_t set_stage)
-{
-	// Read the current group and stage
-	uint32_t cur_stage_group = IORD_32DIRECT(REG_FILE_CUR_STAGE, 0);
-
-	// Clear the stage and substage
-	cur_stage_group &= 0xFFFF0000;
-
-	// Set the stage
-	cur_stage_group |= (set_stage & 0x000000FF);
-
-	// Write the data back
-	IOWR_32DIRECT(REG_FILE_CUR_STAGE, 0, cur_stage_group);
-}
-
-static inline void reg_file_set_sub_stage(uint32_t set_sub_stage)
-{
-	// Read the current group and stage
-	uint32_t cur_stage_group = IORD_32DIRECT(REG_FILE_CUR_STAGE, 0);
-
-	// Clear the substage
-	cur_stage_group &= 0xFFFF00FF;
-
-	// Set the sub stage
-	cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00);
-
-	// Write the data back
-	IOWR_32DIRECT(REG_FILE_CUR_STAGE, 0, cur_stage_group);
-}
-
-static inline uint32_t is_write_group_enabled_for_dm(uint32_t write_group)
-{
-	return 1;
-}
-
-static inline void select_curr_shadow_reg_using_rank(uint32_t rank)
-{
-}
-
-static void initialize(void)
-{
-	IOWR_32DIRECT(PHY_MGR_MUX_SEL, 0, 0x3);
-
-	//USER memory clock is not stable we begin initialization
-
-	IOWR_32DIRECT(PHY_MGR_RESET_MEM_STBL, 0, 0);
-
-	//USER calibration status all set to zero
-
-	IOWR_32DIRECT(PHY_MGR_CAL_STATUS, 0, 0);
-	IOWR_32DIRECT(PHY_MGR_CAL_DEBUG_INFO, 0, 0);
-
-	if (((DYNAMIC_CALIB_STEPS) & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
-		param->read_correct_mask_vg =
-		    ((t_btfld) 1 <<
-		     (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
-		param->write_correct_mask_vg =
-		    ((t_btfld) 1 <<
-		     (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
-		param->read_correct_mask = ((t_btfld) 1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
-		param->write_correct_mask = ((t_btfld) 1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
-		param->dm_correct_mask =
-		    ((t_btfld) 1 << (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH)) - 1;
-	}
-}
-
-static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
-{
-	uint32_t odt_mask_0 = 0;
-	uint32_t odt_mask_1 = 0;
-	uint32_t cs_and_odt_mask;
-
-	if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
-
-		if (LRDIMM) {
-			// USER LRDIMMs have two cases to consider: single-slot and dual-slot.
-			// USER In single-slot, assert ODT for write only.
-			// USER In dual-slot, assert ODT for both slots for write,
-			// USER and on the opposite slot only for reads.
-			// USER
-			// USER Further complicating this is that both DIMMs have either 1 or 2 ODT
-			// USER inputs, which do the same thing (only one is actually required).
-			if ((RW_MGR_MEM_CHIP_SELECT_WIDTH / RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM) == 1) {
-				// USER Single-slot case
-				if (RW_MGR_MEM_ODT_WIDTH == 1) {
-					// USER Read = 0, Write = 1
-					odt_mask_0 = 0x0;
-					odt_mask_1 = 0x1;
-				} else if (RW_MGR_MEM_ODT_WIDTH == 2) {
-					// USER Read = 00, Write = 11
-					odt_mask_0 = 0x0;
-					odt_mask_1 = 0x3;
-				}
-			} else if ((RW_MGR_MEM_CHIP_SELECT_WIDTH / RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM)
-				   == 2) {
-				// USER Dual-slot case
-				if (RW_MGR_MEM_ODT_WIDTH == 2) {
-					// USER Read: asserted for opposite slot, Write: asserted for both
-					odt_mask_0 = (rank < 2) ? 0x2 : 0x1;
-					odt_mask_1 = 0x3;
-				} else if (RW_MGR_MEM_ODT_WIDTH == 4) {
-					// USER Read: asserted for opposite slot, Write: asserted for both
-					odt_mask_0 = (rank < 2) ? 0xC : 0x3;
-					odt_mask_1 = 0xF;
-				}
-			}
-		} else if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
-			//USER 1 Rank
-			//USER Read: ODT = 0
-			//USER Write: ODT = 1
-			odt_mask_0 = 0x0;
-			odt_mask_1 = 0x1;
-		} else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
-			//USER 2 Ranks
-			if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1 ||
-			    (RDIMM && RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 2
-			     && RW_MGR_MEM_CHIP_SELECT_WIDTH == 4)) {
-				//USER - Dual-Slot , Single-Rank (1 chip-select per DIMM)
-				//USER OR
-				//USER - RDIMM, 4 total CS (2 CS per DIMM) means 2 DIMM
-				//USER Since MEM_NUMBER_OF_RANKS is 2 they are both single rank
-				//USER with 2 CS each (special for RDIMM)
-				//USER Read: Turn on ODT on the opposite rank
-				//USER Write: Turn on ODT on all ranks
-				odt_mask_0 = 0x3 & ~(1 << rank);
-				odt_mask_1 = 0x3;
-			} else {
-				//USER - Single-Slot , Dual-rank DIMMs (2 chip-selects per DIMM)
-				//USER Read: Turn on ODT off on all ranks
-				//USER Write: Turn on ODT on active rank
-				odt_mask_0 = 0x0;
-				odt_mask_1 = 0x3 & (1 << rank);
-			}
-		} else {
-			//USER 4 Ranks
-			//USER Read:
-			//USER ----------+-----------------------+
-			//USER           |                       |
-			//USER           |         ODT           |
-			//USER Read From +-----------------------+
-			//USER   Rank    |  3  |  2  |  1  |  0  |
-			//USER ----------+-----+-----+-----+-----+
-			//USER     0     |  0  |  1  |  0  |  0  |
-			//USER     1     |  1  |  0  |  0  |  0  |
-			//USER     2     |  0  |  0  |  0  |  1  |
-			//USER     3     |  0  |  0  |  1  |  0  |
-			//USER ----------+-----+-----+-----+-----+
-			//USER
-			//USER Write:
-			//USER ----------+-----------------------+
-			//USER           |                       |
-			//USER           |         ODT           |
-			//USER Write To  +-----------------------+
-			//USER   Rank    |  3  |  2  |  1  |  0  |
-			//USER ----------+-----+-----+-----+-----+
-			//USER     0     |  0  |  1  |  0  |  1  |
-			//USER     1     |  1  |  0  |  1  |  0  |
-			//USER     2     |  0  |  1  |  0  |  1  |
-			//USER     3     |  1  |  0  |  1  |  0  |
-			//USER ----------+-----+-----+-----+-----+
-			switch (rank) {
-			case 0:
-				odt_mask_0 = 0x4;
-				odt_mask_1 = 0x5;
-				break;
-			case 1:
-				odt_mask_0 = 0x8;
-				odt_mask_1 = 0xA;
-				break;
-			case 2:
-				odt_mask_0 = 0x1;
-				odt_mask_1 = 0x5;
-				break;
-			case 3:
-				odt_mask_0 = 0x2;
-				odt_mask_1 = 0xA;
-				break;
-			}
-		}
-	} else {
-		odt_mask_0 = 0x0;
-		odt_mask_1 = 0x0;
-	}
-
-	if (RDIMM && RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 2
-	    && RW_MGR_MEM_CHIP_SELECT_WIDTH == 4 && RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
-		//USER See RDIMM special case above
-		cs_and_odt_mask =
-		    (0xFF & ~(1 << (2 * rank))) |
-		    ((0xFF & odt_mask_0) << 8) | ((0xFF & odt_mask_1) << 16);
-	} else if (LRDIMM) {
-	} else {
-		cs_and_odt_mask =
-		    (0xFF & ~(1 << rank)) |
-		    ((0xFF & odt_mask_0) << 8) | ((0xFF & odt_mask_1) << 16);
-	}
-
-	IOWR_32DIRECT(RW_MGR_SET_CS_AND_ODT_MASK, 0, cs_and_odt_mask);
-}
-
-//USER Given a rank, select the set of shadow registers that is responsible for the
-//USER delays of such rank, so that subsequent SCC updates will go to those shadow
-//USER registers.
-static void select_shadow_regs_for_update(uint32_t rank, uint32_t group,
-					  uint32_t update_scan_chains)
-{
-}
-
-static void scc_mgr_initialize(void)
-{
-	// Clear register file for HPS
-	// 16 (2^4) is the size of the full register file in the scc mgr:
-	//      RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS + MEM_IF_READ_DQS_WIDTH - 1) + 1;
-	uint32_t i;
-	for (i = 0; i < 16; i++) {
-		DPRINT(1, "Clearing SCC RFILE index %lu", i);
-		IOWR_32DIRECT(SCC_MGR_HHP_RFILE, i << 2, 0);
-	}
-}
-
-static inline void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
-{
-	WRITE_SCC_DQS_IN_DELAY(read_group, delay);
-
-}
-
-static inline void scc_mgr_set_dqs_io_in_delay(uint32_t write_group, uint32_t delay)
-{
-	WRITE_SCC_DQS_IO_IN_DELAY(delay);
-
-}
-
-static inline void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
-{
-	WRITE_SCC_DQS_EN_PHASE(read_group, phase);
-
-}
-
-static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, uint32_t phase)
-{
-	uint32_t r;
-	uint32_t update_scan_chains;
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-		//USER although the h/w doesn't support different phases per shadow register,
-		//USER for simplicity our scc manager modeling keeps different phase settings per
-		//USER shadow reg, and it's important for us to keep them in sync to match h/w.
-		//USER for efficiency, the scan chain update should occur only once to sr0.
-		update_scan_chains = (r == 0) ? 1 : 0;
-
-		select_shadow_regs_for_update(r, read_group, update_scan_chains);
-		scc_mgr_set_dqs_en_phase(read_group, phase);
-
-		if (update_scan_chains) {
-			IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, read_group);
-			IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-		}
-	}
-}
-
-static inline void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
-{
-	WRITE_SCC_DQDQS_OUT_PHASE(write_group, phase);
-
-}
-
-static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, uint32_t phase)
-{
-	uint32_t r;
-	uint32_t update_scan_chains;
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-		//USER although the h/w doesn't support different phases per shadow register,
-		//USER for simplicity our scc manager modeling keeps different phase settings per
-		//USER shadow reg, and it's important for us to keep them in sync to match h/w.
-		//USER for efficiency, the scan chain update should occur only once to sr0.
-		update_scan_chains = (r == 0) ? 1 : 0;
-
-		select_shadow_regs_for_update(r, write_group, update_scan_chains);
-		scc_mgr_set_dqdqs_output_phase(write_group, phase);
-
-		if (update_scan_chains) {
-			IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, write_group);
-			IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-		}
-	}
-}
-
-static inline void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
-{
-	WRITE_SCC_DQS_EN_DELAY(read_group, delay);
-
-}
-
-static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, uint32_t delay)
-{
-	uint32_t r;
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-
-		select_shadow_regs_for_update(r, read_group, 0);
-
-		scc_mgr_set_dqs_en_delay(read_group, delay);
-
-		IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, read_group);
-
-		// In shadow register mode, the T11 settings are stored in registers
-		// in the core, which are updated by the DQS_ENA signals. Not issuing
-		// the SCC_MGR_UPD command allows us to save lots of rank switching
-		// overhead, by calling select_shadow_regs_for_update with update_scan_chains
-		// set to 0.
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	}
-}
-
-static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
-{
-	uint32_t read_group;
-
-	// Load the setting in the SCC manager
-	// Although OCT affects only write data, the OCT delay is controlled by the DQS logic block
-	// which is instantiated once per read group. For protocols where a write group consists
-	// of multiple read groups, the setting must be set multiple times.
-	for (read_group =
-	     write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
-	     read_group <
-	     (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
-	     ++read_group) {
-
-		WRITE_SCC_OCT_OUT1_DELAY(read_group, delay);
-	}
-
-}
-
-static void scc_mgr_set_oct_out2_delay(uint32_t write_group, uint32_t delay)
-{
-	uint32_t read_group;
-
-	// Load the setting in the SCC manager
-	// Although OCT affects only write data, the OCT delay is controlled by the DQS logic block
-	// which is instantiated once per read group. For protocols where a write group consists
-	// of multiple read groups, the setting must be set multiple times.
-	for (read_group =
-	     write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
-	     read_group <
-	     (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
-	     ++read_group) {
-
-		WRITE_SCC_OCT_OUT2_DELAY(read_group, delay);
-	}
-
-}
-
-static inline void scc_mgr_set_dqs_bypass(uint32_t write_group, uint32_t bypass)
-{
-	// Load the setting in the SCC manager
-	WRITE_SCC_DQS_BYPASS(write_group, bypass);
-}
-
-static inline void scc_mgr_set_dq_out1_delay(uint32_t write_group, uint32_t dq_in_group,
-					     uint32_t delay)
-{
-
-	// Load the setting in the SCC manager
-	WRITE_SCC_DQ_OUT1_DELAY(dq_in_group, delay);
-
-}
-
-static inline void scc_mgr_set_dq_out2_delay(uint32_t write_group, uint32_t dq_in_group,
-					     uint32_t delay)
-{
-
-	// Load the setting in the SCC manager
-	WRITE_SCC_DQ_OUT2_DELAY(dq_in_group, delay);
-
-}
-
-static inline void scc_mgr_set_dq_in_delay(uint32_t write_group, uint32_t dq_in_group,
-					   uint32_t delay)
-{
-
-	// Load the setting in the SCC manager
-	WRITE_SCC_DQ_IN_DELAY(dq_in_group, delay);
-
-}
-
-static inline void scc_mgr_set_dq_bypass(uint32_t write_group, uint32_t dq_in_group,
-					 uint32_t bypass)
-{
-	// Load the setting in the SCC manager
-	WRITE_SCC_DQ_BYPASS(dq_in_group, bypass);
-}
-
-static inline void scc_mgr_set_rfifo_mode(uint32_t write_group, uint32_t dq_in_group, uint32_t mode)
-{
-	// Load the setting in the SCC manager
-	WRITE_SCC_RFIFO_MODE(dq_in_group, mode);
-}
-
-static inline void scc_mgr_set_hhp_extras(void)
-{
-	// Load the fixed setting in the SCC manager
-	// bits: 0:0 = 1'b1   - dqs bypass
-	// bits: 1:1 = 1'b1   - dq bypass
-	// bits: 4:2 = 3'b001   - rfifo_mode
-	// bits: 6:5 = 2'b01  - rfifo clock_select
-	// bits: 7:7 = 1'b0  - separate gating from ungating setting
-	// bits: 8:8 = 1'b0  - separate OE from Output delay setting
-	uint32_t value = (0 << 8) | (0 << 7) | (1 << 5) | (1 << 2) | (1 << 1) | (1 << 0);
-	WRITE_SCC_HHP_EXTRAS(value);
-}
-
-static inline void scc_mgr_set_hhp_dqse_map(void)
-{
-	// Load the fixed setting in the SCC manager
-	WRITE_SCC_HHP_DQSE_MAP(0);
-}
-
-static inline void scc_mgr_set_dqs_out1_delay(uint32_t write_group, uint32_t delay)
-{
-	WRITE_SCC_DQS_IO_OUT1_DELAY(delay);
-
-}
-
-static inline void scc_mgr_set_dqs_out2_delay(uint32_t write_group, uint32_t delay)
-{
-	WRITE_SCC_DQS_IO_OUT2_DELAY(delay);
-
-}
-
-static inline void scc_mgr_set_dm_out1_delay(uint32_t write_group, uint32_t dm, uint32_t delay)
-{
-	WRITE_SCC_DM_IO_OUT1_DELAY(dm, delay);
-}
-
-static inline void scc_mgr_set_dm_out2_delay(uint32_t write_group, uint32_t dm, uint32_t delay)
-{
-	WRITE_SCC_DM_IO_OUT2_DELAY(dm, delay);
-}
-
-static inline void scc_mgr_set_dm_in_delay(uint32_t write_group, uint32_t dm, uint32_t delay)
-{
-	WRITE_SCC_DM_IO_IN_DELAY(dm, delay);
-}
-
-static inline void scc_mgr_set_dm_bypass(uint32_t write_group, uint32_t dm, uint32_t bypass)
-{
-	// Load the setting in the SCC manager
-	WRITE_SCC_DM_BYPASS(dm, bypass);
-}
-
-//USER Zero all DQS config
-// TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
-static void scc_mgr_zero_all(void)
-{
-	uint32_t i, r;
-
-	//USER Zero all DQS config settings, across all groups and all shadow registers
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-
-		// Strictly speaking this should be called once per group to make
-		// sure each group's delay chain is refreshed from the SCC register file,
-		// but since we're resetting all delay chains anyway, we can save some
-		// runtime by calling select_shadow_regs_for_update just once to switch
-		// rank.
-		select_shadow_regs_for_update(r, 0, 1);
-
-		for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
-			// The phases actually don't exist on a per-rank basis, but there's
-			// no harm updating them several times, so let's keep the code simple.
-			scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
-			scc_mgr_set_dqs_en_phase(i, 0);
-			scc_mgr_set_dqs_en_delay(i, 0);
-		}
-
-		for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
-			scc_mgr_set_dqdqs_output_phase(i, 0);
-			// av/cv don't have out2
-			scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
-		}
-
-		//USER multicast to all DQS group enables
-		IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, 0xff);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	}
-}
-
-static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
-{
-	// mode = 0 : Do NOT bypass - Half Rate Mode
-	// mode = 1 : Bypass - Full Rate Mode
-
-	// only need to set once for all groups, pins, dq, dqs, dm
-	if (write_group == 0) {
-		DPRINT(1, "Setting HHP Extras");
-		scc_mgr_set_hhp_extras();
-		DPRINT(1, "Done Setting HHP Extras");
-	}
-
-	//USER multicast to all DQ enables
-	IOWR_32DIRECT(SCC_MGR_DQ_ENA, 0, 0xff);
-
-	IOWR_32DIRECT(SCC_MGR_DM_ENA, 0, 0xff);
-
-	//USER update current DQS IO enable
-	IOWR_32DIRECT(SCC_MGR_DQS_IO_ENA, 0, 0);
-
-	//USER update the DQS logic
-	IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, write_group);
-
-	//USER hit update
-	IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-}
-
-// Moving up to avoid warnings
-static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
-{
-	uint32_t read_group;
-
-	// Although OCT affects only write data, the OCT delay is controlled by the DQS logic block
-	// which is instantiated once per read group. For protocols where a write group consists
-	// of multiple read groups, the setting must be scanned multiple times.
-	for (read_group =
-	     write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
-	     read_group <
-	     (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
-	     ++read_group) {
-
-		IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, read_group);
-	}
-}
-
-static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, int32_t out_only)
-{
-	uint32_t i, r;
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-
-		select_shadow_regs_for_update(r, write_group, 1);
-
-		//USER Zero all DQ config settings
-		for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-			scc_mgr_set_dq_out1_delay(write_group, i, 0);
-			scc_mgr_set_dq_out2_delay(write_group, i, IO_DQ_OUT_RESERVE);
-			if (!out_only) {
-				scc_mgr_set_dq_in_delay(write_group, i, 0);
-			}
-		}
-
-		//USER multicast to all DQ enables
-		IOWR_32DIRECT(SCC_MGR_DQ_ENA, 0, 0xff);
-
-		//USER Zero all DM config settings
-		for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
-			if (!out_only) {
-				// Do we really need this?
-				scc_mgr_set_dm_in_delay(write_group, i, 0);
-			}
-			scc_mgr_set_dm_out1_delay(write_group, i, 0);
-			scc_mgr_set_dm_out2_delay(write_group, i, IO_DM_OUT_RESERVE);
-		}
-
-		//USER multicast to all DM enables
-		IOWR_32DIRECT(SCC_MGR_DM_ENA, 0, 0xff);
-
-		//USER zero all DQS io settings
-		if (!out_only) {
-			scc_mgr_set_dqs_io_in_delay(write_group, 0);
-		}
-		// av/cv don't have out2
-		scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE);
-		scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
-		scc_mgr_load_dqs_for_write_group(write_group);
-
-		//USER multicast to all DQS IO enables (only 1)
-		IOWR_32DIRECT(SCC_MGR_DQS_IO_ENA, 0, 0);
-
-		//USER hit update to zero everything
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	}
-}
-
-//USER load up dqs config settings
-
-static void scc_mgr_load_dqs(uint32_t dqs)
-{
-	IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, dqs);
-}
-
-//USER load up dqs io config settings
-
-static void scc_mgr_load_dqs_io(void)
-{
-	IOWR_32DIRECT(SCC_MGR_DQS_IO_ENA, 0, 0);
-}
-
-//USER load up dq config settings
-
-static void scc_mgr_load_dq(uint32_t dq_in_group)
-{
-	IOWR_32DIRECT(SCC_MGR_DQ_ENA, 0, dq_in_group);
-}
-
-//USER load up dm config settings
-
-static void scc_mgr_load_dm(uint32_t dm)
-{
-	IOWR_32DIRECT(SCC_MGR_DM_ENA, 0, dm);
-}
-
-//USER apply and load a particular input delay for the DQ pins in a group
-//USER group_bgn is the index of the first dq pin (in the write group)
-
-static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group, uint32_t group_bgn,
-					    uint32_t delay)
-{
-	uint32_t i, p;
-
-	for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
-		scc_mgr_set_dq_in_delay(write_group, p, delay);
-		scc_mgr_load_dq(p);
-	}
-}
-
-//USER apply and load a particular output delay for the DQ pins in a group
-
-static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group, uint32_t group_bgn,
-					      uint32_t delay1)
-{
-	uint32_t i, p;
-
-	for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
-		scc_mgr_set_dq_out1_delay(write_group, i, delay1);
-		scc_mgr_load_dq(i);
-	}
-}
-
-//USER apply and load a particular output delay for the DM pins in a group
-
-static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group, uint32_t delay1)
-{
-	uint32_t i;
-
-	for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
-		scc_mgr_set_dm_out1_delay(write_group, i, delay1);
-		scc_mgr_load_dm(i);
-	}
-}
-
-//USER apply and load delay on both DQS and OCT out1
-static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group, uint32_t delay)
-{
-	scc_mgr_set_dqs_out1_delay(write_group, delay);
-	scc_mgr_load_dqs_io();
-
-	scc_mgr_set_oct_out1_delay(write_group, delay);
-	scc_mgr_load_dqs_for_write_group(write_group);
-}
-
-//USER set delay on both DQS and OCT out1 by incrementally changing
-//USER the settings one dtap at a time towards the target value, to avoid
-//USER breaking the lock of the DLL/PLL on the memory device.
-static void scc_mgr_set_group_dqs_io_and_oct_out1_gradual(uint32_t write_group, uint32_t delay)
-{
-	uint32_t d = READ_SCC_DQS_IO_OUT1_DELAY();
-
-	while (d > delay) {
-		--d;
-		scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, d);
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-		if (QDRII) {
-			rw_mgr_mem_dll_lock_wait();
-		}
-	}
-	while (d < delay) {
-		++d;
-		scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, d);
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-		if (QDRII) {
-			rw_mgr_mem_dll_lock_wait();
-		}
-	}
-}
-
-//USER apply a delay to the entire output side: DQ, DM, DQS, OCT
-
-static void scc_mgr_apply_group_all_out_delay(uint32_t write_group, uint32_t group_bgn,
-					      uint32_t delay)
-{
-	//USER dq shift
-
-	scc_mgr_apply_group_dq_out1_delay(write_group, group_bgn, delay);
-
-	//USER dm shift
-
-	scc_mgr_apply_group_dm_out1_delay(write_group, delay);
-
-	//USER dqs and oct shift
-
-	scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, delay);
-}
-
-//USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks
-static void scc_mgr_apply_group_all_out_delay_all_ranks(uint32_t write_group, uint32_t group_bgn,
-							uint32_t delay)
-{
-	uint32_t r;
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-
-		select_shadow_regs_for_update(r, write_group, 1);
-
-		scc_mgr_apply_group_all_out_delay(write_group, group_bgn, delay);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	}
-}
-
-//USER apply a delay to the entire output side: DQ, DM, DQS, OCT
-
-static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, uint32_t group_bgn,
-						  uint32_t delay)
-{
-	uint32_t i, p, new_delay;
-
-	//USER dq shift
-
-	for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
-
-		new_delay = READ_SCC_DQ_OUT2_DELAY(i);
-		new_delay += delay;
-
-		if (new_delay > IO_IO_OUT2_DELAY_MAX) {
-			DPRINT(1, "%s(%lu, %lu, %lu) DQ[%lu,%lu]: %lu > %lu => %lu",
-			       __func__, write_group, group_bgn, delay, i, p,
-			       new_delay, (long unsigned int)IO_IO_OUT2_DELAY_MAX,
-			       (long unsigned int)IO_IO_OUT2_DELAY_MAX);
-			new_delay = IO_IO_OUT2_DELAY_MAX;
-		}
-
-		scc_mgr_set_dq_out2_delay(write_group, i, new_delay);
-		scc_mgr_load_dq(i);
-	}
-
-	//USER dm shift
-
-	for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
-		new_delay = READ_SCC_DM_IO_OUT2_DELAY(i);
-		new_delay += delay;
-
-		if (new_delay > IO_IO_OUT2_DELAY_MAX) {
-			DPRINT(1, "%s(%lu, %lu, %lu) DM[%lu]: %lu > %lu => %lu",
-			       __func__, write_group, group_bgn, delay, i,
-			       new_delay, (long unsigned int)IO_IO_OUT2_DELAY_MAX,
-			       (long unsigned int)IO_IO_OUT2_DELAY_MAX);
-			new_delay = IO_IO_OUT2_DELAY_MAX;
-		}
-
-		scc_mgr_set_dm_out2_delay(write_group, i, new_delay);
-		scc_mgr_load_dm(i);
-	}
-
-	//USER dqs shift
-
-	new_delay = READ_SCC_DQS_IO_OUT2_DELAY();
-	new_delay += delay;
-
-	if (new_delay > IO_IO_OUT2_DELAY_MAX) {
-		DPRINT(1, "%s(%lu, %lu, %lu) DQS: %lu > %d => %d; adding %lu to OUT1",
-		       __func__, write_group, group_bgn, delay,
-		       new_delay, IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
-		       new_delay - IO_IO_OUT2_DELAY_MAX);
-		scc_mgr_set_dqs_out1_delay(write_group, new_delay - IO_IO_OUT2_DELAY_MAX);
-		new_delay = IO_IO_OUT2_DELAY_MAX;
-	}
-
-	scc_mgr_set_dqs_out2_delay(write_group, new_delay);
-	scc_mgr_load_dqs_io();
-
-	//USER oct shift
-
-	new_delay = READ_SCC_OCT_OUT2_DELAY(write_group);
-	new_delay += delay;
-
-	if (new_delay > IO_IO_OUT2_DELAY_MAX) {
-		DPRINT(1, "%s(%lu, %lu, %lu) DQS: %lu > %d => %d; adding %lu to OUT1",
-		       __func__, write_group, group_bgn, delay,
-		       new_delay, IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
-		       new_delay - IO_IO_OUT2_DELAY_MAX);
-		scc_mgr_set_oct_out1_delay(write_group, new_delay - IO_IO_OUT2_DELAY_MAX);
-		new_delay = IO_IO_OUT2_DELAY_MAX;
-	}
-
-	scc_mgr_set_oct_out2_delay(write_group, new_delay);
-	scc_mgr_load_dqs_for_write_group(write_group);
-}
-
-//USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks
-static void scc_mgr_apply_group_all_out_delay_add_all_ranks(uint32_t write_group,
-							    uint32_t group_bgn, uint32_t delay)
-{
-	uint32_t r;
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-
-		select_shadow_regs_for_update(r, write_group, 1);
-
-		scc_mgr_apply_group_all_out_delay_add(write_group, group_bgn, delay);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	}
-}
-
-static inline void scc_mgr_spread_out2_delay_all_ranks(uint32_t write_group, uint32_t test_bgn)
-{
-}
-
-// optimization used to recover some slots in ddr3 inst_rom
-// could be applied to other protocols if we wanted to
-static void set_jump_as_return(void)
-{
-	// to save space, we replace return with jump to special shared RETURN instruction
-	// so we set the counter to large value so that we always jump
-	IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0xFF);
-	IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_RETURN);
-
-}
-
-// should always use constants as argument to ensure all computations are performed at compile time
-static inline void delay_for_n_mem_clocks(const uint32_t clocks)
-{
-	uint32_t afi_clocks;
-	uint8_t inner;
-	uint8_t outer;
-	uint16_t c_loop;
-
-	afi_clocks = (clocks + AFI_RATE_RATIO - 1) / AFI_RATE_RATIO;	/* scale (rounding up) to get afi clocks */
-
-	// Note, we don't bother accounting for being off a little bit because of a few extra instructions in outer loops
-	// Note, the loops have a test at the end, and do the test before the decrement, and so always perform the loop
-	// 1 time more than the counter value
-	if (afi_clocks == 0) {
-		inner = outer = c_loop = 0;
-	} else if (afi_clocks <= 0x100) {
-		inner = afi_clocks - 1;
-		outer = 0;
-		c_loop = 0;
-	} else if (afi_clocks <= 0x10000) {
-		inner = 0xff;
-		outer = (afi_clocks - 1) >> 8;
-		c_loop = 0;
-	} else {
-		inner = 0xff;
-		outer = 0xff;
-		c_loop = (afi_clocks - 1) >> 16;
-	}
-
-	// rom instructions are structured as follows:
-	//
-	//    IDLE_LOOP2: jnz cntr0, TARGET_A
-	//    IDLE_LOOP1: jnz cntr1, TARGET_B
-	//                return
-	//
-	// so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and TARGET_B is
-	// set to IDLE_LOOP2 as well
-	//
-	// if we have no outer loop, though, then we can use IDLE_LOOP1 only, and set
-	// TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
-	//
-	// a little confusing, but it helps save precious space in the inst_rom and sequencer rom
-	// and keeps the delays more accurate and reduces overhead
-	if (afi_clocks <= 0x100) {
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner));
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_IDLE_LOOP1);
-		IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP1);
-
-	} else {
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner));
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer));
-
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_IDLE_LOOP2);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_IDLE_LOOP2);
-
-		// hack to get around compiler not being smart enough
-		if (afi_clocks <= 0x10000) {
-			// only need to run once
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP2);
-		} else {
-			do {
-				IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP2);
-			} while (c_loop-- != 0);
-		}
-	}
-}
-
-// should always use constants as argument to ensure all computations are performed at compile time
-static inline void delay_for_n_ns(const uint32_t nanoseconds)
-{
-	delay_for_n_mem_clocks((1000 * nanoseconds) / (1000000 / AFI_CLK_FREQ) * AFI_RATE_RATIO);
-}
-
-// Special routine to recover memory device from illegal state after
-// ck/dqs relationship is violated.
-static inline void recover_mem_device_after_ck_dqs_violation(void)
-{
-	// Current protocol doesn't require any special recovery
-}
-
-static void rw_mgr_rdimm_initialize(void)
-{
-}
-
-static void rw_mgr_mem_initialize(void)
-{
-	uint32_t r;
-
-	//USER The reset / cke part of initialization is broadcasted to all ranks
-	IOWR_32DIRECT(RW_MGR_SET_CS_AND_ODT_MASK, 0, RW_MGR_RANK_ALL);
-
-	// Here's how you load register for a loop
-	//USER Counters are located @ 0x800
-	//USER Jump address are located @ 0xC00
-	//USER For both, registers 0 to 3 are selected using bits 3 and 2, like in
-	//USER 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
-	// I know this ain't pretty, but Avalon bus throws away the 2 least significant bits
-
-	//USER start with memory RESET activated
-
-	//USER tINIT is typically 200us (but can be adjusted in the GUI)
-	//USER The total number of cycles required for this nested counter structure to
-	//USER complete is defined by:
-	//USER        num_cycles = (CTR2 + 1) * [(CTR1 + 1) * (2 * (CTR0 + 1) + 1) + 1] + 1
-
-	//USER Load counters
-	IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL));
-	IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL));
-	IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL));
-
-	//USER Load jump address
-	IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_0_CKE_0);
-	IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_0_CKE_0);
-	IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_INIT_RESET_0_CKE_0);
-
-	//USER Execute count instruction
-	IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_0_CKE_0);
-
-	//USER indicate that memory is stable
-	IOWR_32DIRECT(PHY_MGR_RESET_MEM_STBL, 0, 1);
-
-	//USER transition the RESET to high
-	//USER Wait for 500us
-	//USER        num_cycles = (CTR2 + 1) * [(CTR1 + 1) * (2 * (CTR0 + 1) + 1) + 1] + 1
-	//USER Load counters
-	IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL));
-	IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL));
-	IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL));
-
-	//USER Load jump address
-	IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_1_CKE_0);
-	IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_1_CKE_0);
-	IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_INIT_RESET_1_CKE_0);
-
-	IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_1_CKE_0);
-
-	//USER bring up clock enable
-
-	//USER tXRP < 250 ck cycles
-	delay_for_n_mem_clocks(250);
-
-	// USER initialize RDIMM buffer so MRS and RZQ Calibrate commands will be
-	// USER propagated to discrete memory devices
-	rw_mgr_rdimm_initialize();
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
-		if (param->skip_ranks[r]) {
-			//USER request to skip the rank
-
-			continue;
-		}
-
-		//USER set rank
-		set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
-
-		//USER Use Mirror-ed commands for odd ranks if address mirrorring is on
-		if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2_MIRR);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3_MIRR);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1_MIRR);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET_MIRR);
-		} else {
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET);
-		}
-
-		set_jump_as_return();
-		IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ZQCL);
-
-		//USER tZQinit = tDLLK = 512 ck cycles
-		delay_for_n_mem_clocks(512);
-	}
-}
-
-static void rw_mgr_mem_dll_lock_wait(void)
-{
-}
-
-//USER  At the end of calibration we have to program the user settings in, and
-//USER  hand off the memory to the user.
-
-static void rw_mgr_mem_handoff(void)
-{
-	uint32_t r;
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
-		if (param->skip_ranks[r]) {
-			//USER request to skip the rank
-
-			continue;
-		}
-		//USER set rank
-		set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
-
-		//USER precharge all banks ...
-
-		IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
-
-		//USER load up MR settings specified by user
-
-		//USER Use Mirror-ed commands for odd ranks if address mirrorring is on
-		if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2_MIRR);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3_MIRR);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1_MIRR);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_USER_MIRR);
-		} else {
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1);
-			delay_for_n_mem_clocks(4);
-			set_jump_as_return();
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_USER);
-		}
-		//USER  need to wait tMOD (12CK or 15ns) time before issuing other commands,
-		//USER  but we will have plenty of NIOS cycles before actual handoff so its okay.
-	}
-
-}
-
-//USER performs a guaranteed read on the patterns we are going to use during a read test to ensure memory works
-static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, uint32_t group,
-							uint32_t num_tries, t_btfld * bit_chk,
-							uint32_t all_ranks)
-{
-	uint32_t r, vg;
-	t_btfld correct_mask_vg;
-	t_btfld tmp_bit_chk;
-	uint32_t rank_end =
-	    all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
-
-	*bit_chk = param->read_correct_mask;
-	correct_mask_vg = param->read_correct_mask_vg;
-
-	for (r = rank_bgn; r < rank_end; r++) {
-		if (param->skip_ranks[r]) {
-			//USER request to skip the rank
-
-			continue;
-		}
-		//USER set rank
-		set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
-
-		//USER Load up a constant bursts of read commands
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0x20);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_GUARANTEED_READ);
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, 0x20);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_GUARANTEED_READ_CONT);
-
-		tmp_bit_chk = 0;
-		for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;; vg--) {
-			//USER reset the fifos to get pointers to known state
-
-			IOWR_32DIRECT(PHY_MGR_CMD_FIFO_RESET, 0, 0);
-			IOWR_32DIRECT(RW_MGR_RESET_READ_DATAPATH, 0, 0);
-
-			tmp_bit_chk =
-			    tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS /
-					    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
-
-			IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP,
-				      ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS + vg) << 2),
-				      __RW_MGR_GUARANTEED_READ);
-			tmp_bit_chk =
-			    tmp_bit_chk | (correct_mask_vg & ~(IORD_32DIRECT(BASE_RW_MGR, 0)));
-
-			if (vg == 0) {
-				break;
-			}
-		}
-		*bit_chk &= tmp_bit_chk;
-	}
-
-	IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, (group << 2), __RW_MGR_CLEAR_DQS_ENABLE);
-
-	set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
-	DPRINT(2, "test_load_patterns(%lu,ALL) => (%lu == %lu) => %lu", group, *bit_chk,
-	       param->read_correct_mask, (long unsigned int)(*bit_chk == param->read_correct_mask));
-	return (*bit_chk == param->read_correct_mask);
-}
-
-static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks(uint32_t group,
-								  uint32_t num_tries,
-								  t_btfld * bit_chk)
-{
-	if (rw_mgr_mem_calibrate_read_test_patterns(0, group, num_tries, bit_chk, 1)) {
-		return 1;
-	} else {
-		// case:139851 - if guaranteed read fails, we can retry using different dqs enable phases.
-		// It is possible that with the initial phase, dqs enable is asserted/deasserted too close
-		// to an dqs edge, truncating the read burst.
-		uint32_t p;
-		for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++) {
-			scc_mgr_set_dqs_en_phase_all_ranks(group, p);
-			if (rw_mgr_mem_calibrate_read_test_patterns
-			    (0, group, num_tries, bit_chk, 1)) {
-				return 1;
-			}
-		}
-		return 0;
-	}
-}
-
-//USER load up the patterns we are going to use during a read test
-static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn, uint32_t all_ranks)
-{
-	uint32_t r;
-	uint32_t rank_end =
-	    all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
-
-	for (r = rank_bgn; r < rank_end; r++) {
-		if (param->skip_ranks[r]) {
-			//USER request to skip the rank
-
-			continue;
-		}
-		//USER set rank
-		set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
-
-		//USER Load up a constant bursts
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0x20);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_GUARANTEED_WRITE_WAIT0);
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, 0x20);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_GUARANTEED_WRITE_WAIT1);
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, 0x04);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_GUARANTEED_WRITE_WAIT2);
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_3, 0, 0x04);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_GUARANTEED_WRITE_WAIT3);
-
-		IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_GUARANTEED_WRITE);
-	}
-
-	set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
-}
-
-static inline void rw_mgr_mem_calibrate_read_load_patterns_all_ranks(void)
-{
-	rw_mgr_mem_calibrate_read_load_patterns(0, 1);
-}
-
-// pe checkout pattern for harden managers
-//void pe_checkout_pattern (void)
-//{
-//    // test RW manager
-//
-//    // do some reads to check load buffer
-//      IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0);
-//      IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1);
-//
-//      IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x0);
-//      IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2);
-//
-//      IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0);
-//      IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B);
-//
-//      IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0);
-//      IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B);
-//
-//      // clear error word
-//      IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0);
-//
-//      IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_READ_B2B);
-//
-//      uint32_t readdata;
-//
-//      // read error word
-//      readdata = IORD_32DIRECT(BASE_RW_MGR, 0);
-//
-//      // read DI buffer
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 0*4, 0);
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 1*4, 0);
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 2*4, 0);
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 3*4, 0);
-//
-//      IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0);
-//      IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1);
-//
-//      IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x0);
-//      IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2);
-//
-//      IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0);
-//      IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B);
-//
-//      IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0);
-//      IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B);
-//
-//      // clear error word
-//      IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0);
-//
-//      // do read
-//      IOWR_32DIRECT (RW_MGR_LOOPBACK_MODE, 0, __RW_MGR_READ_B2B);
-//
-//      // read error word
-//      readdata = IORD_32DIRECT(BASE_RW_MGR, 0);
-//
-//      // error word should be 0x00
-//
-//      // read DI buffer
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 0*4, 0);
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 1*4, 0);
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 2*4, 0);
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 3*4, 0);
-//
-//      // clear error word
-//      IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0);
-//
-//      // do dm read
-//      IOWR_32DIRECT (RW_MGR_LOOPBACK_MODE, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1);
-//
-//      // read error word
-//      readdata = IORD_32DIRECT(BASE_RW_MGR, 0);
-//
-//      // error word should be ff
-//
-//      // read DI buffer
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 0*4, 0);
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 1*4, 0);
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 2*4, 0);
-//      readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 3*4, 0);
-//
-//      // exit loopback mode
-//      IOWR_32DIRECT (BASE_RW_MGR, 0, __RW_MGR_IDLE_LOOP2);
-//
-//      // start of phy manager access
-//
-//      readdata = IORD_32DIRECT (PHY_MGR_MAX_RLAT_WIDTH, 0);
-//      readdata = IORD_32DIRECT (PHY_MGR_MAX_AFI_WLAT_WIDTH, 0);
-//      readdata = IORD_32DIRECT (PHY_MGR_MAX_AFI_RLAT_WIDTH, 0);
-//      readdata = IORD_32DIRECT (PHY_MGR_CALIB_SKIP_STEPS, 0);
-//      readdata = IORD_32DIRECT (PHY_MGR_CALIB_VFIFO_OFFSET, 0);
-//      readdata = IORD_32DIRECT (PHY_MGR_CALIB_LFIFO_OFFSET, 0);
-//
-//      // start of data manager test
-//
-//      readdata = IORD_32DIRECT (DATA_MGR_DRAM_CFG         , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_MEM_T_WL         , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_MEM_T_ADD    , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_MEM_T_RL         , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_MEM_T_RFC    , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_MEM_T_REFI   , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_MEM_T_WR         , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_MEM_T_MRD    , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_COL_WIDTH    , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_ROW_WIDTH    , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_BANK_WIDTH   , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_CS_WIDTH         , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_ITF_WIDTH    , 0);
-//      readdata = IORD_32DIRECT (DATA_MGR_DVC_WIDTH    , 0);
-//
-//}
-
-//USER  try a read and see if it returns correct data back. has dummy reads inserted into the mix
-//USER  used to align dqs enable. has more thorough checks than the regular read test.
-
-static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
-					       uint32_t num_tries, uint32_t all_correct,
-					       t_btfld * bit_chk, uint32_t all_groups,
-					       uint32_t all_ranks)
-{
-	uint32_t r, vg;
-	t_btfld correct_mask_vg;
-	t_btfld tmp_bit_chk;
-	uint32_t rank_end =
-	    all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
-	uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_DELAY_SWEEPS)
-				    && ENABLE_SUPER_QUICK_CALIBRATION) || BFM_MODE;
-
-	*bit_chk = param->read_correct_mask;
-	correct_mask_vg = param->read_correct_mask_vg;
-
-	for (r = rank_bgn; r < rank_end; r++) {
-		if (param->skip_ranks[r]) {
-			//USER request to skip the rank
-
-			continue;
-		}
-		//USER set rank
-		set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, 0x10);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1);
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, 0x10);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2);
-
-		if (quick_read_mode) {
-			IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0x1);	/* need at least two (1+1) reads to capture failures */
-		} else if (all_groups) {
-			IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0x06);
-		} else {
-			IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0x32);
-		}
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B);
-		if (all_groups) {
-			IOWR_32DIRECT(RW_MGR_LOAD_CNTR_3, 0,
-				      RW_MGR_MEM_IF_READ_DQS_WIDTH *
-				      RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1);
-		} else {
-			IOWR_32DIRECT(RW_MGR_LOAD_CNTR_3, 0, 0x0);
-		}
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B);
-
-		tmp_bit_chk = 0;
-		for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;; vg--) {
-			//USER reset the fifos to get pointers to known state
-
-			IOWR_32DIRECT(PHY_MGR_CMD_FIFO_RESET, 0, 0);
-			IOWR_32DIRECT(RW_MGR_RESET_READ_DATAPATH, 0, 0);
-
-			tmp_bit_chk =
-			    tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS /
-					    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
-
-			IOWR_32DIRECT(all_groups ? RW_MGR_RUN_ALL_GROUPS : RW_MGR_RUN_SINGLE_GROUP,
-				      ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS + vg) << 2),
-				      __RW_MGR_READ_B2B);
-			tmp_bit_chk =
-			    tmp_bit_chk | (correct_mask_vg & ~(IORD_32DIRECT(BASE_RW_MGR, 0)));
-
-			if (vg == 0) {
-				break;
-			}
-		}
-		*bit_chk &= tmp_bit_chk;
-	}
-
-	IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, (group << 2), __RW_MGR_CLEAR_DQS_ENABLE);
-
-	if (all_correct) {
-		set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
-		DPRINT(2, "read_test(%lu,ALL,%lu) => (%lu == %lu) => %lu", group, all_groups,
-		       *bit_chk, param->read_correct_mask,
-		       (long unsigned int)(*bit_chk == param->read_correct_mask));
-		return (*bit_chk == param->read_correct_mask);
-	} else {
-		set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
-		DPRINT(2, "read_test(%lu,ONE,%lu) => (%lu != %lu) => %lu", group, all_groups,
-		       *bit_chk, (long unsigned int)0, (long unsigned int)(*bit_chk != 0x00));
-		return (*bit_chk != 0x00);
-	}
-}
-
-static inline uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group, uint32_t num_tries,
-								uint32_t all_correct,
-								t_btfld * bit_chk,
-								uint32_t all_groups)
-{
-	return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct, bit_chk, all_groups,
-					      1);
-}
-
-static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t * v)
-{
-	//USER fiddle with FIFO
-	if (HARD_PHY) {
-		IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_HARD_PHY, 0, grp);
-	} else if (QUARTER_RATE_MODE && !HARD_VFIFO) {
-		if ((*v & 3) == 3) {
-			IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_QR, 0, grp);
-		} else if ((*v & 2) == 2) {
-			IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_FR_HR, 0, grp);
-		} else if ((*v & 1) == 1) {
-			IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_HR, 0, grp);
-		} else {
-			IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_FR, 0, grp);
-		}
-	} else if (HARD_VFIFO) {
-		// Arria V & Cyclone V have a hard full-rate VFIFO that only has a single incr signal
-		IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_FR, 0, grp);
-	} else {
-		if (!HALF_RATE_MODE || (*v & 1) == 1) {
-			IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_HR, 0, grp);
-		} else {
-			IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_FR, 0, grp);
-		}
-	}
-
-	(*v)++;
-	BFM_INC_VFIFO;
-}
-
-//Used in quick cal to properly loop through the duplicated VFIFOs in AV QDRII/RLDRAM
-static inline void rw_mgr_incr_vfifo_all(uint32_t grp, uint32_t * v)
-{
-#if VFIFO_CONTROL_WIDTH_PER_DQS == 1
-	rw_mgr_incr_vfifo(grp, v);
-#else
-	uint32_t i;
-	for (i = 0; i < VFIFO_CONTROL_WIDTH_PER_DQS; i++) {
-		rw_mgr_incr_vfifo(grp * VFIFO_CONTROL_WIDTH_PER_DQS + i, v);
-		if (i != 0) {
-			(*v)--;
-		}
-	}
-#endif
-}
-
-static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t * v)
-{
-
-	uint32_t i;
-
-	for (i = 0; i < VFIFO_SIZE - 1; i++) {
-		rw_mgr_incr_vfifo(grp, v);
-	}
-}
-
-//USER find a good dqs enable to use
-
-#if NEWVERSION_DQSEN
-
-// Navid's version
-
-static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
-{
-	uint32_t i, d, v, p;
-	uint32_t max_working_cnt;
-	uint32_t fail_cnt;
-	t_btfld bit_chk;
-	uint32_t dtaps_per_ptap;
-	uint32_t found_begin, found_end;
-	uint32_t work_bgn, work_mid, work_end, tmp_delay;
-	uint32_t test_status;
-	uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
-
-	reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
-
-	scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
-	scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
-
-	fail_cnt = 0;
-
-	//USER **************************************************************
-	//USER * Step 0 : Determine number of delay taps for each phase tap *
-
-	dtaps_per_ptap = 0;
-	tmp_delay = 0;
-	while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
-		dtaps_per_ptap++;
-		tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
-	}
-	dtaps_per_ptap--;
-	tmp_delay = 0;
-
-	// VFIFO sweep
-
-	//USER *********************************************************
-	//USER * Step 1 : First push vfifo until we get a failing read *
-	for (v = 0; v < VFIFO_SIZE;) {
-		DPRINT(2, "find_dqs_en_phase: vfifo %lu", BFM_GBL_GET(vfifo_idx));
-		test_status =
-		    rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, &bit_chk, 0);
-		if (!test_status) {
-			fail_cnt++;
-
-			if (fail_cnt == 2) {
-				break;
-			}
-		}
-		//USER fiddle with FIFO
-		rw_mgr_incr_vfifo(grp, &v);
-	}
-
-	if (v >= VFIFO_SIZE) {
-		//USER no failing read found!! Something must have gone wrong
-		DPRINT(2, "find_dqs_en_phase: vfifo failed");
-		return 0;
-	}
-
-	max_working_cnt = 0;
-
-	//USER ********************************************************
-	//USER * step 2: find first working phase, increment in ptaps *
-	found_begin = 0;
-	work_bgn = 0;
-	for (d = 0; d <= dtaps_per_ptap; d++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
-		work_bgn = tmp_delay;
-		scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-		for (i = 0; i < VFIFO_SIZE; i++) {
-			for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++, work_bgn += IO_DELAY_PER_OPA_TAP) {
-				DPRINT(2, "find_dqs_en_phase: begin: vfifo=%lu ptap=%lu dtap=%lu",
-				       BFM_GBL_GET(vfifo_idx), p, d);
-				scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-
-				test_status =
-				    rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT,
-									     &bit_chk, 0);
-
-				if (test_status) {
-					max_working_cnt = 1;
-					found_begin = 1;
-					break;
-				}
-			}
-
-			if (found_begin) {
-				break;
-			}
-
-			if (p > IO_DQS_EN_PHASE_MAX) {
-				//USER fiddle with FIFO
-				rw_mgr_incr_vfifo(grp, &v);
-			}
-		}
-
-		if (found_begin) {
-			break;
-		}
-	}
-
-	if (i >= VFIFO_SIZE) {
-		//USER cannot find working solution
-		DPRINT(2, "find_dqs_en_phase: no vfifo/ptap/dtap");
-		return 0;
-	}
-
-	work_end = work_bgn;
-
-	//USER  If d is 0 then the working window covers a phase tap and we can follow the old procedure
-	//USER  otherwise, we've found the beginning, and we need to increment the dtaps until we find the end
-	if (d == 0) {
-		//USER ********************************************************************
-		//USER * step 3a: if we have room, back off by one and increment in dtaps *
-		COV(EN_PHASE_PTAP_OVERLAP);
-
-		//USER Special case code for backing up a phase
-		if (p == 0) {
-			p = IO_DQS_EN_PHASE_MAX;
-			rw_mgr_decr_vfifo(grp, &v);
-		} else {
-			p = p - 1;
-		}
-		tmp_delay = work_bgn - IO_DELAY_PER_OPA_TAP;
-		scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-
-		found_begin = 0;
-		for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < work_bgn;
-		     d++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
-
-			DPRINT(2, "find_dqs_en_phase: begin-2: vfifo=%lu ptap=%lu dtap=%lu",
-			       BFM_GBL_GET(vfifo_idx), p, d);
-
-			scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-			if (rw_mgr_mem_calibrate_read_test_all_ranks
-			    (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-				found_begin = 1;
-				work_bgn = tmp_delay;
-				break;
-			}
-		}
-
-		//USER We have found a working dtap before the ptap found above
-		if (found_begin == 1) {
-			max_working_cnt++;
-		}
-		//USER Restore VFIFO to old state before we decremented it (if needed)
-		p = p + 1;
-		if (p > IO_DQS_EN_PHASE_MAX) {
-			p = 0;
-			rw_mgr_incr_vfifo(grp, &v);
-		}
-
-		scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
-
-		//USER ***********************************************************************************
-		//USER * step 4a: go forward from working phase to non working phase, increment in ptaps *
-		p = p + 1;
-		work_end += IO_DELAY_PER_OPA_TAP;
-		if (p > IO_DQS_EN_PHASE_MAX) {
-			//USER fiddle with FIFO
-			p = 0;
-			rw_mgr_incr_vfifo(grp, &v);
-		}
-
-		found_end = 0;
-		for (; i < VFIFO_SIZE + 1; i++) {
-			for (; p <= IO_DQS_EN_PHASE_MAX; p++, work_end += IO_DELAY_PER_OPA_TAP) {
-				DPRINT(2, "find_dqs_en_phase: end: vfifo=%lu ptap=%lu dtap=%lu",
-				       BFM_GBL_GET(vfifo_idx), p, (long unsigned int)0);
-				scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-
-				if (!rw_mgr_mem_calibrate_read_test_all_ranks
-				    (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-					found_end = 1;
-					break;
-				} else {
-					max_working_cnt++;
-				}
-			}
-
-			if (found_end) {
-				break;
-			}
-
-			if (p > IO_DQS_EN_PHASE_MAX) {
-				//USER fiddle with FIFO
-				rw_mgr_incr_vfifo(grp, &v);
-				p = 0;
-			}
-		}
-
-		if (i >= VFIFO_SIZE + 1) {
-			//USER cannot see edge of failing read
-			DPRINT(2, "find_dqs_en_phase: end: failed");
-			return 0;
-		}
-		//USER *********************************************************
-		//USER * step 5a:  back off one from last, increment in dtaps  *
-
-		//USER Special case code for backing up a phase
-		if (p == 0) {
-			p = IO_DQS_EN_PHASE_MAX;
-			rw_mgr_decr_vfifo(grp, &v);
-		} else {
-			p = p - 1;
-		}
-
-		work_end -= IO_DELAY_PER_OPA_TAP;
-		scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-
-		//USER * The actual increment of dtaps is done outside of the if/else loop to share code
-		d = 0;
-
-		DPRINT(2, "find_dqs_en_phase: found end v/p: vfifo=%lu ptap=%lu",
-		       BFM_GBL_GET(vfifo_idx), p);
-	} else {
-
-		//USER ********************************************************************
-		//USER * step 3-5b:  Find the right edge of the window using delay taps   *
-		COV(EN_PHASE_PTAP_NO_OVERLAP);
-
-		DPRINT(2, "find_dqs_en_phase: begin found: vfifo=%lu ptap=%lu dtap=%lu begin=%lu",
-		       BFM_GBL_GET(vfifo_idx), p, d, work_bgn);
-		BFM_GBL_SET(dqs_enable_left_edge[grp].v, BFM_GBL_GET(vfifo_idx));
-		BFM_GBL_SET(dqs_enable_left_edge[grp].p, p);
-		BFM_GBL_SET(dqs_enable_left_edge[grp].d, d);
-		BFM_GBL_SET(dqs_enable_left_edge[grp].ps, work_bgn);
-
-		work_end = work_bgn;
-
-		//USER * The actual increment of dtaps is done outside of the if/else loop to share code
-
-		//USER Only here to counterbalance a subtract later on which is not needed if this branch
-		//USER  of the algorithm is taken
-		max_working_cnt++;
-	}
-
-	//USER The dtap increment to find the failing edge is done here
-	for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
-
-		DPRINT(2, "find_dqs_en_phase: end-2: dtap=%lu", d);
-		scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-		if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-			break;
-		}
-	}
-
-	//USER Go back to working dtap
-	if (d != 0) {
-		work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
-	}
-
-	DPRINT(2, "find_dqs_en_phase: found end v/p/d: vfifo=%lu ptap=%lu dtap=%lu end=%lu",
-	       BFM_GBL_GET(vfifo_idx), p, d - 1, work_end);
-	BFM_GBL_SET(dqs_enable_right_edge[grp].v, BFM_GBL_GET(vfifo_idx));
-	BFM_GBL_SET(dqs_enable_right_edge[grp].p, p);
-	BFM_GBL_SET(dqs_enable_right_edge[grp].d, d - 1);
-	BFM_GBL_SET(dqs_enable_right_edge[grp].ps, work_end);
-
-	if (work_end >= work_bgn) {
-		//USER we have a working range
-	} else {
-		//USER nil range
-		DPRINT(2, "find_dqs_en_phase: end-2: failed");
-		return 0;
-	}
-
-	DPRINT(2, "find_dqs_en_phase: found range [%lu,%lu]", work_bgn, work_end);
-
-	// ***************************************************************
-	//USER * We need to calculate the number of dtaps that equal a ptap
-	//USER * To do that we'll back up a ptap and re-find the edge of the
-	//USER * window using dtaps
-
-	DPRINT(2, "find_dqs_en_phase: calculate dtaps_per_ptap for tracking");
-
-	//USER Special case code for backing up a phase
-	if (p == 0) {
-		p = IO_DQS_EN_PHASE_MAX;
-		rw_mgr_decr_vfifo(grp, &v);
-		DPRINT(2, "find_dqs_en_phase: backed up cycle/phase: v=%lu p=%lu",
-		       BFM_GBL_GET(vfifo_idx), p);
-	} else {
-		p = p - 1;
-		DPRINT(2, "find_dqs_en_phase: backed up phase only: v=%lu p=%lu",
-		       BFM_GBL_GET(vfifo_idx), p);
-	}
-
-	scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-
-	//USER Increase dtap until we first see a passing read (in case the window is smaller than a ptap),
-	//USER and then a failing read to mark the edge of the window again
-
-	//USER Find a passing read
-	DPRINT(2, "find_dqs_en_phase: find passing read");
-	found_passing_read = 0;
-	found_failing_read = 0;
-	initial_failing_dtap = d;
-	for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
-		DPRINT(2, "find_dqs_en_phase: testing read d=%lu", d);
-		scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-		if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-			found_passing_read = 1;
-			break;
-		}
-	}
-
-	if (found_passing_read) {
-		//USER Find a failing read
-		DPRINT(2, "find_dqs_en_phase: find failing read");
-		for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
-			DPRINT(2, "find_dqs_en_phase: testing read d=%lu", d);
-			scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-			if (!rw_mgr_mem_calibrate_read_test_all_ranks
-			    (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-				found_failing_read = 1;
-				break;
-			}
-		}
-	} else {
-		DPRINT(1,
-		       "find_dqs_en_phase: failed to calculate dtaps per ptap. Fall back on static value");
-	}
-
-	//USER The dynamically calculated dtaps_per_ptap is only valid if we found a passing/failing read
-	//USER If we didn't, it means d hit the max (IO_DQS_EN_DELAY_MAX).
-	//USER Otherwise, dtaps_per_ptap retains its statically calculated value.
-	if (found_passing_read && found_failing_read) {
-		dtaps_per_ptap = d - initial_failing_dtap;
-	}
-
-	IOWR_32DIRECT(REG_FILE_DTAPS_PER_PTAP, 0, dtaps_per_ptap);
-
-	DPRINT(2, "find_dqs_en_phase: dtaps_per_ptap=%lu - %lu = %lu", d, initial_failing_dtap,
-	       dtaps_per_ptap);
-
-	//USER ********************************************
-	//USER * step 6:  Find the centre of the window   *
-
-	work_mid = (work_bgn + work_end) / 2;
-	tmp_delay = 0;
-
-	DPRINT(2, "work_bgn=%ld work_end=%ld work_mid=%ld", work_bgn, work_end, work_mid);
-	//USER Get the middle delay to be less than a VFIFO delay
-	for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++, tmp_delay += IO_DELAY_PER_OPA_TAP) ;
-	DPRINT(2, "vfifo ptap delay %ld", tmp_delay);
-	while (work_mid > tmp_delay)
-		work_mid -= tmp_delay;
-	DPRINT(2, "new work_mid %ld", work_mid);
-	tmp_delay = 0;
-	for (p = 0; p <= IO_DQS_EN_PHASE_MAX && tmp_delay < work_mid;
-	     p++, tmp_delay += IO_DELAY_PER_OPA_TAP) ;
-	tmp_delay -= IO_DELAY_PER_OPA_TAP;
-	DPRINT(2, "new p %ld, tmp_delay=%ld", p - 1, tmp_delay);
-	for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < work_mid;
-	     d++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) ;
-	DPRINT(2, "new d %ld, tmp_delay=%ld", d, tmp_delay);
-
-	scc_mgr_set_dqs_en_phase_all_ranks(grp, p - 1);
-	scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-	//USER push vfifo until we can successfully calibrate. We can do this because
-	//USER the largest possible margin in 1 VFIFO cycle
-
-	for (i = 0; i < VFIFO_SIZE; i++) {
-		DPRINT(2, "find_dqs_en_phase: center: vfifo=%lu", BFM_GBL_GET(vfifo_idx));
-		if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-			break;
-		}
-		//USER fiddle with FIFO
-		rw_mgr_incr_vfifo(grp, &v);
-	}
-
-	if (i >= VFIFO_SIZE) {
-		DPRINT(2, "find_dqs_en_phase: center: failed");
-		return 0;
-	}
-	DPRINT(2, "find_dqs_en_phase: center found: vfifo=%li ptap=%lu dtap=%lu",
-	       BFM_GBL_GET(vfifo_idx), p - 1, d);
-	BFM_GBL_SET(dqs_enable_mid[grp].v, BFM_GBL_GET(vfifo_idx));
-	BFM_GBL_SET(dqs_enable_mid[grp].p, p - 1);
-	BFM_GBL_SET(dqs_enable_mid[grp].d, d);
-	BFM_GBL_SET(dqs_enable_mid[grp].ps, work_mid);
-	return 1;
-}
-
-#if 0
-// Ryan's algorithm
-
-static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
-{
-	uint32_t i, d, v, p;
-	uint32_t min_working_p, max_working_p, min_working_d, max_working_d, max_working_cnt;
-	uint32_t fail_cnt;
-	t_btfld bit_chk;
-	uint32_t dtaps_per_ptap;
-	uint32_t found_begin, found_end;
-	uint32_t tmp_delay;
-
-	TRACE_FUNC("%lu", grp);
-
-	reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
-
-	scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
-	scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
-
-	fail_cnt = 0;
-
-	//USER **************************************************************
-	//USER * Step 0 : Determine number of delay taps for each phase tap *
-
-	dtaps_per_ptap = 0;
-	tmp_delay = 0;
-	while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
-		dtaps_per_ptap++;
-		tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
-	}
-	dtaps_per_ptap--;
-
-	//USER *********************************************************
-	//USER * Step 1 : First push vfifo until we get a failing read *
-	for (v = 0; v < VFIFO_SIZE;) {
-		if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-			fail_cnt++;
-
-			if (fail_cnt == 2) {
-				break;
-			}
-		}
-		//USER fiddle with FIFO
-		rw_mgr_incr_vfifo(grp, &v);
-	}
-
-	if (i >= VFIFO_SIZE) {
-		//USER no failing read found!! Something must have gone wrong
-		return 0;
-	}
-
-	max_working_cnt = 0;
-	min_working_p = 0;
-
-	//USER ********************************************************
-	//USER * step 2: find first working phase, increment in ptaps *
-	found_begin = 0;
-	for (d = 0; d <= dtaps_per_ptap; d++) {
-		scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-		for (i = 0; i < VFIFO_SIZE; i++) {
-			for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++) {
-				scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-
-				if (rw_mgr_mem_calibrate_read_test_all_ranks
-				    (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-					max_working_cnt = 1;
-					found_begin = 1;
-					break;
-				}
-			}
-
-			if (found_begin) {
-				break;
-			}
-
-			if (p > IO_DQS_EN_PHASE_MAX) {
-				//USER fiddle with FIFO
-				rw_mgr_incr_vfifo(grp, &v);
-			}
-		}
-
-		if (found_begin) {
-			break;
-		}
-	}
-
-	if (i >= VFIFO_SIZE) {
-		//USER cannot find working solution
-		return 0;
-	}
-
-	min_working_p = p;
-
-	//USER  If d is 0 then the working window covers a phase tap and we can follow the old procedure
-	//USER  otherwise, we've found the beginning, and we need to increment the dtaps until we find the end
-	if (d == 0) {
-		//USER ********************************************************************
-		//USER * step 3a: if we have room, back off by one and increment in dtaps *
-		min_working_d = 0;
-
-		//USER Special case code for backing up a phase
-		if (p == 0) {
-			p = IO_DQS_EN_PHASE_MAX;
-			rw_mgr_decr_vfifo(grp, &v);
-		} else {
-			p = p - 1;
-		}
-		scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-
-		found_begin = 0;
-		for (d = 0; d <= dtaps_per_ptap; d++) {
-			scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-			if (rw_mgr_mem_calibrate_read_test_all_ranks
-			    (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-				found_begin = 1;
-				min_working_d = d;
-				break;
-			}
-		}
-
-		//USER We have found a working dtap before the ptap found above
-		if (found_begin == 1) {
-			min_working_p = p;
-			max_working_cnt++;
-		}
-		//USER Restore VFIFO to old state before we decremented it
-		p = p + 1;
-		if (p > IO_DQS_EN_PHASE_MAX) {
-			p = 0;
-			rw_mgr_incr_vfifo(grp, &v);
-		}
-
-		scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
-
-		//USER ***********************************************************************************
-		//USER * step 4a: go forward from working phase to non working phase, increment in ptaps *
-		p = p + 1;
-		if (p > IO_DQS_EN_PHASE_MAX) {
-			//USER fiddle with FIFO
-			p = 0;
-			rw_mgr_incr_vfifo(grp, &v);
-		}
-
-		found_end = 0;
-		for (; i < VFIFO_SIZE + 1; i++) {
-			for (; p <= IO_DQS_EN_PHASE_MAX; p++) {
-				scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-
-				if (!rw_mgr_mem_calibrate_read_test_all_ranks
-				    (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-					found_end = 1;
-					break;
-				} else {
-					max_working_cnt++;
-				}
-			}
-
-			if (found_end) {
-				break;
-			}
-
-			if (p > IO_DQS_EN_PHASE_MAX) {
-				//USER fiddle with FIFO
-				rw_mgr_incr_vfifo(grp, &v);
-				p = 0;
-			}
-		}
-
-		if (i >= VFIFO_SIZE + 1) {
-			//USER cannot see edge of failing read
-			return 0;
-		}
-		//USER *********************************************************
-		//USER * step 5a:  back off one from last, increment in dtaps  *
-		max_working_d = 0;
-
-		//USER Special case code for backing up a phase
-		if (p == 0) {
-			p = IO_DQS_EN_PHASE_MAX;
-			rw_mgr_decr_vfifo(grp, &v);
-		} else {
-			p = p - 1;
-		}
-
-		max_working_p = p;
-		scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-
-		for (d = 0; d <= IO_DQS_EN_DELAY_MAX; d++) {
-			scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-			if (!rw_mgr_mem_calibrate_read_test_all_ranks
-			    (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-				break;
-			}
-		}
-
-		//USER Go back to working dtap
-		if (d != 0) {
-			max_working_d = d - 1;
-		}
-
-	} else {
-
-		//USER ********************************************************************
-		//USER * step 3-5b:  Find the right edge of the window using delay taps   *
-
-		max_working_p = min_working_p;
-		min_working_d = d;
-
-		for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
-			scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-			if (!rw_mgr_mem_calibrate_read_test_all_ranks
-			    (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-				break;
-			}
-		}
-
-		//USER Go back to working dtap
-		if (d != 0) {
-			max_working_d = d - 1;
-		}
-		//USER Only here to counterbalance a subtract later on which is not needed if this branch
-		//USER of the algorithm is taken
-		max_working_cnt++;
-	}
-
-	//USER ********************************************
-	//USER * step 6:  Find the centre of the window   *
-
-	//USER If the number of working phases is even we will step back a phase and find the
-	//USER  edge with a larger delay chain tap
-	if ((max_working_cnt & 1) == 0) {
-		p = min_working_p + (max_working_cnt - 1) / 2;
-
-		//USER Special case code for backing up a phase
-		if (max_working_p == 0) {
-			max_working_p = IO_DQS_EN_PHASE_MAX;
-			rw_mgr_decr_vfifo(grp, &v);
-		} else {
-			max_working_p = max_working_p - 1;
-		}
-
-		scc_mgr_set_dqs_en_phase_all_ranks(grp, max_working_p);
-
-		//USER Code to determine at which dtap we should start searching again for a failure
-		//USER If we've moved back such that the max and min p are the same, we should start searching
-		//USER from where the window actually exists
-		if (max_working_p == min_working_p) {
-			d = min_working_d;
-		} else {
-			d = max_working_d;
-		}
-
-		for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
-			scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-			if (!rw_mgr_mem_calibrate_read_test_all_ranks
-			    (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-				break;
-			}
-		}
-
-		//USER Go back to working dtap
-		if (d != 0) {
-			max_working_d = d - 1;
-		}
-	} else {
-		p = min_working_p + (max_working_cnt) / 2;
-	}
-
-	while (p > IO_DQS_EN_PHASE_MAX) {
-		p -= (IO_DQS_EN_PHASE_MAX + 1);
-	}
-
-	d = (min_working_d + max_working_d) / 2;
-
-	scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
-	scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
-	//USER push vfifo until we can successfully calibrate
-
-	for (i = 0; i < VFIFO_SIZE; i++) {
-		if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-			break;
-		}
-		//USER fiddle with FIFO
-		rw_mgr_incr_vfifo(grp, &v);
-	}
-
-	if (i >= VFIFO_SIZE) {
-		return 0;
-	}
-
-	return 1;
-}
-
-#endif
-
-#else
-// Val's original version
-
-static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
-{
-	uint32_t i, j, v, d;
-	uint32_t min_working_d, max_working_cnt;
-	uint32_t fail_cnt;
-	t_btfld bit_chk;
-	uint32_t delay_per_ptap_mid;
-
-	reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
-
-	scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
-	scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
-
-	fail_cnt = 0;
-
-	//USER first push vfifo until we get a failing read
-	v = 0;
-	for (i = 0; i < VFIFO_SIZE; i++) {
-		if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
-			fail_cnt++;
-
-			if (fail_cnt == 2) {
-				break;
-			}
-		}
-		//USER fiddle with FIFO
-		rw_mgr_incr_vfifo(grp, &v);
-	}
-
-	if (v >= VFIFO_SIZE) {
-		//USER no failing read found!! Something must have gone wrong
-
-		return 0;
-	}
-
-	max_working_cnt = 0;
-	min_working_d = 0;
-
-	for (i = 0; i < VFIFO_SIZE + 1; i++) {
-		for (d = 0; d <= IO_DQS_EN_PHASE_MAX; d++) {
-			scc_mgr_set_dqs_en_phase_all_ranks(grp, d);
-
-			rw_mgr_mem_calibrate_read_test_all_ranks(grp, NUM_READ_PB_TESTS,
-								 PASS_ONE_BIT, &bit_chk, 0);
-			if (bit_chk) {
-				//USER passing read
-
-				if (max_working_cnt == 0) {
-					min_working_d = d;
-				}
-
-				max_working_cnt++;
-			} else {
-				if (max_working_cnt > 0) {
-					//USER already have one working value
-					break;
-				}
-			}
-		}
-
-		if (d > IO_DQS_EN_PHASE_MAX) {
-			//USER fiddle with FIFO
-			rw_mgr_incr_vfifo(grp, &v);
-		} else {
-			//USER found working solution!
-
-			d = min_working_d + (max_working_cnt - 1) / 2;
-
-			while (d > IO_DQS_EN_PHASE_MAX) {
-				d -= (IO_DQS_EN_PHASE_MAX + 1);
-			}
-
-			break;
-		}
-	}
-
-	if (i >= VFIFO_SIZE + 1) {
-		//USER cannot find working solution or cannot see edge of failing read
-
-		return 0;
-	}
-	//USER in the case the number of working steps is even, use 50ps taps to further center the window
-
-	if ((max_working_cnt & 1) == 0) {
-		delay_per_ptap_mid = IO_DELAY_PER_OPA_TAP / 2;
-
-		//USER increment in 50ps taps until we reach the required amount
-
-		for (i = 0, j = 0; i <= IO_DQS_EN_DELAY_MAX && j < delay_per_ptap_mid;
-		     i++, j += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) ;
-
-		scc_mgr_set_dqs_en_delay_all_ranks(grp, i - 1);
-	}
-
-	scc_mgr_set_dqs_en_phase_all_ranks(grp, d);
-
-	//USER push vfifo until we can successfully calibrate
-
-	for (i = 0; i < VFIFO_SIZE; i++) {
-		if (rw_mgr_mem_calibrate_read_test_all_ranks
-		    (grp, NUM_READ_PB_TESTS, PASS_ONE_BIT, &bit_chk, 0)) {
-			break;
-		}
-		//USER fiddle with FIFO
-		rw_mgr_incr_vfifo(grp, &v);
-	}
-
-	if (i >= VFIFO_SIZE) {
-		return 0;
-	}
-
-	return 1;
-}
-
-#endif
-
-// Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different dq_in_delay values
-static inline uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(uint32_t
-										      write_group,
-										      uint32_t
-										      read_group,
-										      uint32_t
-										      test_bgn)
-{
-	uint32_t found;
-	uint32_t i;
-	uint32_t p;
-	uint32_t d;
-	uint32_t r;
-
-	const uint32_t delay_step = IO_IO_IN_DELAY_MAX / (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
-
-	// try different dq_in_delays since the dq path is shorter than dqs
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-		select_shadow_regs_for_update(r, write_group, 1);
-		for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS;
-		     i++, p++, d += delay_step) {
-			DPRINT(1,
-			       "rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay: g=%lu/%lu r=%lu, i=%lu p=%lu d=%lu",
-			       write_group, read_group, r, i, p, d);
-			scc_mgr_set_dq_in_delay(write_group, p, d);
-			scc_mgr_load_dq(p);
-		}
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	}
-
-	found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
-
-	DPRINT(1,
-	       "rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay: g=%lu/%lu found=%lu; Reseting delay chain to zero",
-	       write_group, read_group, found);
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-		select_shadow_regs_for_update(r, write_group, 1);
-		for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
-			scc_mgr_set_dq_in_delay(write_group, p, 0);
-			scc_mgr_load_dq(p);
-		}
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	}
-
-	return found;
-}
-
-//USER per-bit deskew DQ and center
-
-#if NEWVERSION_RDDESKEW
-
-static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t write_group,
-						  uint32_t read_group, uint32_t test_bgn,
-						  uint32_t use_read_test, uint32_t update_fom)
-{
-	uint32_t i, p, d, min_index;
-	//USER Store these as signed since there are comparisons with signed numbers
-	t_btfld bit_chk;
-	t_btfld sticky_bit_chk;
-	int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
-	int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
-	int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
-	int32_t mid;
-	int32_t orig_mid_min, mid_min;
-	int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs, final_dqs_en;
-	int32_t dq_margin, dqs_margin;
-	uint32_t stop;
-
-	start_dqs = READ_SCC_DQS_IN_DELAY(read_group);
-	if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
-		start_dqs_en = READ_SCC_DQS_EN_DELAY(read_group);
-	}
-
-	select_curr_shadow_reg_using_rank(rank_bgn);
-
-	//USER per-bit deskew
-
-	//USER set the left and right edge of each bit to an illegal value
-	//USER use (IO_IO_IN_DELAY_MAX + 1) as an illegal value
-	sticky_bit_chk = 0;
-	for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
-		left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
-		right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
-	}
-
-	//USER Search for the left edge of the window for each bit
-	for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
-		scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-		//USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit
-		if (use_read_test) {
-			stop =
-			    !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group, NUM_READ_PB_TESTS,
-							    PASS_ONE_BIT, &bit_chk, 0, 0);
-		} else {
-			rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, PASS_ONE_BIT,
-							&bit_chk, 0);
-			bit_chk =
-			    bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
-					(read_group -
-					 (write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
-					  RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
-			stop = (bit_chk == 0);
-		}
-		sticky_bit_chk = sticky_bit_chk | bit_chk;
-		stop = stop && (sticky_bit_chk == param->read_correct_mask);
-		DPRINT(2, "vfifo_center(left): dtap=%lu => " BTFLD_FMT " == " BTFLD_FMT " && %lu",
-		       d, sticky_bit_chk, param->read_correct_mask, stop);
-
-		if (stop == 1) {
-			break;
-		} else {
-			for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
-				if (bit_chk & 1) {
-					//USER Remember a passing test as the left_edge
-					left_edge[i] = d;
-				} else {
-					//USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge
-					if (left_edge[i] == IO_IO_IN_DELAY_MAX + 1) {
-						right_edge[i] = -(d + 1);
-					}
-				}
-				DPRINT(2,
-				       "vfifo_center[l,d=%lu]: bit_chk_test=%d left_edge[%lu]: %ld right_edge[%lu]: %ld",
-				       d, (int)(bit_chk & 1), i, left_edge[i], i, right_edge[i]);
-				bit_chk = bit_chk >> 1;
-			}
-		}
-	}
-
-	//USER Reset DQ delay chains to 0
-	scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, 0);
-	sticky_bit_chk = 0;
-	for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
-
-		DPRINT(2, "vfifo_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i],
-		       i, right_edge[i]);
-
-		//USER Check for cases where we haven't found the left edge, which makes our assignment of the the
-		//USER right edge invalid.  Reset it to the illegal value.
-		if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1)
-		    && (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
-			right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
-			DPRINT(2, "vfifo_center: reset right_edge[%lu]: %ld", i, right_edge[i]);
-		}
-		//USER Reset sticky bit (except for bits where we have seen both the left and right edge)
-		sticky_bit_chk = sticky_bit_chk << 1;
-		if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1)
-		    && (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
-			sticky_bit_chk = sticky_bit_chk | 1;
-		}
-
-		if (i == 0) {
-			break;
-		}
-	}
-
-	//USER Search for the right edge of the window for each bit
-	for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
-		scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
-		if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
-			uint32_t delay = d + start_dqs_en;
-			if (delay > IO_DQS_EN_DELAY_MAX) {
-				delay = IO_DQS_EN_DELAY_MAX;
-			}
-			scc_mgr_set_dqs_en_delay(read_group, delay);
-		}
-		scc_mgr_load_dqs(read_group);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-		//USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit
-		if (use_read_test) {
-			stop =
-			    !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group, NUM_READ_PB_TESTS,
-							    PASS_ONE_BIT, &bit_chk, 0, 0);
-		} else {
-			rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, PASS_ONE_BIT,
-							&bit_chk, 0);
-			bit_chk =
-			    bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
-					(read_group -
-					 (write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
-					  RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
-			stop = (bit_chk == 0);
-		}
-		sticky_bit_chk = sticky_bit_chk | bit_chk;
-		stop = stop && (sticky_bit_chk == param->read_correct_mask);
-
-		DPRINT(2, "vfifo_center(right): dtap=%lu => " BTFLD_FMT " == " BTFLD_FMT " && %lu",
-		       d, sticky_bit_chk, param->read_correct_mask, stop);
-
-		if (stop == 1) {
-			break;
-		} else {
-			for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
-				if (bit_chk & 1) {
-					//USER Remember a passing test as the right_edge
-					right_edge[i] = d;
-				} else {
-					if (d != 0) {
-						//USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge
-						if (right_edge[i] == IO_IO_IN_DELAY_MAX + 1) {
-							left_edge[i] = -(d + 1);
-						}
-					} else {
-						//USER d = 0 failed, but it passed when testing the left edge, so it must be marginal, set it to -1
-						if (right_edge[i] == IO_IO_IN_DELAY_MAX + 1
-						    && left_edge[i] != IO_IO_IN_DELAY_MAX + 1) {
-							right_edge[i] = -1;
-						}
-						//USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge
-						else if (right_edge[i] == IO_IO_IN_DELAY_MAX + 1) {
-							left_edge[i] = -(d + 1);
-						}
-
-					}
-				}
-
-				DPRINT(2,
-				       "vfifo_center[r,d=%lu]: bit_chk_test=%d left_edge[%lu]: %ld right_edge[%lu]: %ld",
-				       d, (int)(bit_chk & 1), i, left_edge[i], i, right_edge[i]);
-				bit_chk = bit_chk >> 1;
-			}
-		}
-	}
-
-	// Store all observed margins
-
-	//USER Check that all bits have a window
-	for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
-		DPRINT(2, "vfifo_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i],
-		       i, right_edge[i]);
-		BFM_GBL_SET(dq_read_left_edge[read_group][i], left_edge[i]);
-		BFM_GBL_SET(dq_read_right_edge[read_group][i], right_edge[i]);
-		if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1)
-		    || (right_edge[i] == IO_IO_IN_DELAY_MAX + 1)) {
-
-			//USER Restore delay chain settings before letting the loop in
-			//USER rw_mgr_mem_calibrate_vfifo to retry different dqs/ck relationships
-			scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
-			if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
-				scc_mgr_set_dqs_en_delay(read_group, start_dqs_en);
-			}
-			scc_mgr_load_dqs(read_group);
-			IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-			DPRINT(1, "vfifo_center: failed to find edge [%lu]: %ld %ld", i,
-			       left_edge[i], right_edge[i]);
-			if (use_read_test) {
-				set_failing_group_stage(read_group * RW_MGR_MEM_DQ_PER_READ_DQS + i,
-							CAL_STAGE_VFIFO, CAL_SUBSTAGE_VFIFO_CENTER);
-			} else {
-				set_failing_group_stage(read_group * RW_MGR_MEM_DQ_PER_READ_DQS + i,
-							CAL_STAGE_VFIFO_AFTER_WRITES,
-							CAL_SUBSTAGE_VFIFO_CENTER);
-			}
-			return 0;
-		}
-	}
-
-	//USER Find middle of window for each DQ bit
-	mid_min = left_edge[0] - right_edge[0];
-	min_index = 0;
-	for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
-		mid = left_edge[i] - right_edge[i];
-		if (mid < mid_min) {
-			mid_min = mid;
-			min_index = i;
-		}
-	}
-
-	//USER  -mid_min/2 represents the amount that we need to move DQS.  If mid_min is odd and positive we'll need to add one to
-	//USER make sure the rounding in further calculations is correct (always bias to the right), so just add 1 for all positive values
-	if (mid_min > 0) {
-		mid_min++;
-	}
-	mid_min = mid_min / 2;
-
-	DPRINT(1, "vfifo_center: mid_min=%ld (index=%lu)", mid_min, min_index);
-
-	//USER Determine the amount we can change DQS (which is -mid_min)
-	orig_mid_min = mid_min;
-	new_dqs = start_dqs - mid_min;
-	if (new_dqs > IO_DQS_IN_DELAY_MAX) {
-		new_dqs = IO_DQS_IN_DELAY_MAX;
-	} else if (new_dqs < 0) {
-		new_dqs = 0;
-	}
-	mid_min = start_dqs - new_dqs;
-	DPRINT(1, "vfifo_center: new mid_min=%ld new_dqs=%ld", mid_min, new_dqs);
-
-	if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
-		if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX) {
-			mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
-		} else if (start_dqs_en - mid_min < 0) {
-			mid_min += start_dqs_en - mid_min;
-		}
-	}
-	new_dqs = start_dqs - mid_min;
-
-	DPRINT(1, "vfifo_center: start_dqs=%ld start_dqs_en=%ld new_dqs=%ld mid_min=%ld",
-	       start_dqs, IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1, new_dqs, mid_min);
-
-	//USER Initialize data for export structures
-	dqs_margin = IO_IO_IN_DELAY_MAX + 1;
-	dq_margin = IO_IO_IN_DELAY_MAX + 1;
-
-	//USER add delay to bring centre of all DQ windows to the same "level"
-	for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
-		//USER Use values before divide by 2 to reduce round off error
-		shift_dq =
-		    (left_edge[i] - right_edge[i] -
-		     (left_edge[min_index] - right_edge[min_index])) / 2 + (orig_mid_min - mid_min);
-
-		DPRINT(2, "vfifo_center: before: shift_dq[%lu]=%ld", i, shift_dq);
-
-		if (shift_dq + (int32_t) READ_SCC_DQ_IN_DELAY(p) > (int32_t) IO_IO_IN_DELAY_MAX) {
-			shift_dq = (int32_t) IO_IO_IN_DELAY_MAX - READ_SCC_DQ_IN_DELAY(i);
-		} else if (shift_dq + (int32_t) READ_SCC_DQ_IN_DELAY(p) < 0) {
-			shift_dq = -(int32_t) READ_SCC_DQ_IN_DELAY(p);
-		}
-		DPRINT(2, "vfifo_center: after: shift_dq[%lu]=%ld", i, shift_dq);
-		final_dq[i] = READ_SCC_DQ_IN_DELAY(p) + shift_dq;
-		scc_mgr_set_dq_in_delay(write_group, p, final_dq[i]);
-		scc_mgr_load_dq(p);
-
-		DPRINT(2, "vfifo_center: margin[%lu]=[%ld,%ld]", i,
-		       left_edge[i] - shift_dq + (-mid_min), right_edge[i] + shift_dq - (-mid_min));
-		//USER To determine values for export structures
-		if (left_edge[i] - shift_dq + (-mid_min) < dq_margin) {
-			dq_margin = left_edge[i] - shift_dq + (-mid_min);
-		}
-		if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin) {
-			dqs_margin = right_edge[i] + shift_dq - (-mid_min);
-		}
-	}
-
-	final_dqs = new_dqs;
-	if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
-		final_dqs_en = start_dqs_en - mid_min;
-	}
-	//USER Move DQS-en
-	if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
-		scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
-		scc_mgr_load_dqs(read_group);
-	}
-	//USER Move DQS
-	scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
-	scc_mgr_load_dqs(read_group);
-
-	if (update_fom) {
-		//USER Export values
-		gbl->fom_in +=
-		    (dq_margin +
-		     dqs_margin) / (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH);
-	}
-
-	DPRINT(2, "vfifo_center: dq_margin=%ld dqs_margin=%ld", dq_margin, dqs_margin);
-
-	//USER Do not remove this line as it makes sure all of our decisions have been applied
-	IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	return (dq_margin >= 0) && (dqs_margin >= 0);
-}
-
-#else
-
-static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t grp,
-						  uint32_t test_bgn, uint32_t use_read_test)
-{
-	uint32_t i, p, d;
-	uint32_t mid;
-	t_btfld bit_chk;
-	uint32_t max_working_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
-	uint32_t dq_margin, dqs_margin;
-	uint32_t start_dqs;
-
-	//USER per-bit deskew.
-	//USER start of the per-bit sweep with the minimum working delay setting for
-	//USER all bits.
-
-	for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
-		max_working_dq[i] = 0;
-	}
-
-	for (d = 1; d <= IO_IO_IN_DELAY_MAX; d++) {
-		scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-		if (!rw_mgr_mem_calibrate_read_test
-		    (rank_bgn, grp, NUM_READ_PB_TESTS, PASS_ONE_BIT, &bit_chk, 0, 0)) {
-			break;
-		} else {
-			for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
-				if (bit_chk & 1) {
-					max_working_dq[i] = d;
-				}
-				bit_chk = bit_chk >> 1;
-			}
-		}
-	}
-
-	//USER determine minimum working value for DQ
-
-	dq_margin = IO_IO_IN_DELAY_MAX;
-
-	for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
-		if (max_working_dq[i] < dq_margin) {
-			dq_margin = max_working_dq[i];
-		}
-	}
-
-	//USER add delay to bring all DQ windows to the same "level"
-
-	for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
-		if (max_working_dq[i] > dq_margin) {
-			scc_mgr_set_dq_in_delay(write_group, i, max_working_dq[i] - dq_margin);
-		} else {
-			scc_mgr_set_dq_in_delay(write_group, i, 0);
-		}
-
-		scc_mgr_load_dq(p, p);
-	}
-
-	//USER sweep DQS window, may potentially have more window due to per-bit-deskew that was done
-	//USER in the previous step.
-
-	start_dqs = READ_SCC_DQS_IN_DELAY(grp);
-
-	for (d = start_dqs + 1; d <= IO_DQS_IN_DELAY_MAX; d++) {
-		scc_mgr_set_dqs_bus_in_delay(grp, d);
-		scc_mgr_load_dqs(grp);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-		if (!rw_mgr_mem_calibrate_read_test
-		    (rank_bgn, grp, NUM_READ_TESTS, PASS_ALL_BITS, &bit_chk, 0, 0)) {
-			break;
-		}
-	}
-
-	scc_mgr_set_dqs_bus_in_delay(grp, start_dqs);
-
-	//USER margin on the DQS pin
-
-	dqs_margin = d - start_dqs - 1;
-
-	//USER find mid point, +1 so that we don't go crazy pushing DQ
-
-	mid = (dq_margin + dqs_margin + 1) / 2;
-
-	gbl->fom_in += dq_margin + dqs_margin;
-//      TCLRPT_SET(debug_summary_report->fom_in, debug_summary_report->fom_in + (dq_margin + dqs_margin));
-//      TCLRPT_SET(debug_cal_report->cal_status_per_group[grp].fom_in, (dq_margin + dqs_margin));
-
-	//USER center DQS ... if the headroom is setup properly we shouldn't need to
-
-	if (dqs_margin > mid) {
-		scc_mgr_set_dqs_bus_in_delay(grp, READ_SCC_DQS_IN_DELAY(grp) + dqs_margin - mid);
-
-		if (DDRX) {
-			uint32_t delay = READ_SCC_DQS_EN_DELAY(grp) + dqs_margin - mid;
-
-			if (delay > IO_DQS_EN_DELAY_MAX) {
-				delay = IO_DQS_EN_DELAY_MAX;
-			}
-
-			scc_mgr_set_dqs_en_delay(grp, delay);
-		}
-	}
-
-	scc_mgr_load_dqs(grp);
-
-	//USER center DQ
-
-	if (dq_margin > mid) {
-		for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
-			scc_mgr_set_dq_in_delay(write_group, i,
-						READ_SCC_DQ_IN_DELAY(i) + dq_margin - mid);
-			scc_mgr_load_dq(p, p);
-		}
-
-		dqs_margin += dq_margin - mid;
-		dq_margin -= dq_margin - mid;
-	}
-
-	IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-	return (dq_margin + dqs_margin) > 0;
-}
-
-#endif
-
-//USER calibrate the read valid prediction FIFO.
-//USER
-//USER  - read valid prediction will consist of finding a good DQS enable phase, DQS enable delay, DQS input phase, and DQS input delay.
-//USER  - we also do a per-bit deskew on the DQ lines.
-
-#if NEWVERSION_GW
-
-//USER VFIFO Calibration -- Full Calibration
-static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, uint32_t test_bgn)
-{
-	uint32_t p, d, rank_bgn, sr;
-	uint32_t dtaps_per_ptap;
-	uint32_t tmp_delay;
-	t_btfld bit_chk;
-	uint32_t grp_calibrated;
-	uint32_t write_group, write_test_bgn;
-	uint32_t failed_substage;
-	uint32_t dqs_in_dtaps, orig_start_dqs;
-
-	//USER update info for sims
-
-	reg_file_set_stage(CAL_STAGE_VFIFO);
-
-	if (DDRX) {
-		write_group = read_group;
-		write_test_bgn = test_bgn;
-	} else {
-		write_group =
-		    read_group / (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH);
-		write_test_bgn = read_group * RW_MGR_MEM_DQ_PER_READ_DQS;
-	}
-
-	// USER Determine number of delay taps for each phase tap
-	dtaps_per_ptap = 0;
-	tmp_delay = 0;
-	if (!QDRII) {
-		while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
-			dtaps_per_ptap++;
-			tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
-		}
-		dtaps_per_ptap--;
-		tmp_delay = 0;
-	}
-	//USER update info for sims
-
-	reg_file_set_group(read_group);
-
-	grp_calibrated = 0;
-
-	reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
-	failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
-
-	for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
-
-		if (DDRX || RLDRAMX) {
-			// In RLDRAMX we may be messing the delay of pins in the same write group but outside of
-			// the current read group, but that's ok because we haven't calibrated the output side yet.
-			if (d > 0) {
-				scc_mgr_apply_group_all_out_delay_add_all_ranks(write_group,
-										write_test_bgn, d);
-			}
-		}
-
-		for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; p++) {
-			//USER set a particular dqdqs phase
-			if (DDRX) {
-				scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
-			}
-			//USER Previous iteration may have failed as a result of ck/dqs or ck/dk violation,
-			//USER in which case the device may require special recovery.
-			if (DDRX || RLDRAMX) {
-				if (d != 0 || p != 0) {
-					recover_mem_device_after_ck_dqs_violation();
-				}
-			}
-
-			DPRINT(1, "calibrate_vfifo: g=%lu p=%lu d=%lu", read_group, p, d);
-			BFM_GBL_SET(gwrite_pos[read_group].p, p);
-			BFM_GBL_SET(gwrite_pos[read_group].d, d);
-
-			//USER Load up the patterns used by read calibration using current DQDQS phase
-
-			rw_mgr_mem_calibrate_read_load_patterns_all_ranks();
-
-			if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
-				if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
-				    (read_group, 1, &bit_chk)) {
-					DPRINT(1, "Guaranteed read test failed: g=%lu p=%lu d=%lu",
-					       read_group, p, d);
-					break;
-				}
-			}
-			// Loop over different DQS in delay chains for the purpose of DQS Enable calibration finding one bit working
-			orig_start_dqs = READ_SCC_DQS_IN_DELAY(read_group);
-			for (dqs_in_dtaps = orig_start_dqs;
-			     dqs_in_dtaps <= IO_DQS_IN_DELAY_MAX && grp_calibrated == 0;
-			     dqs_in_dtaps++) {
-
-				for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
-				     rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
-
-					if (!param->skip_shadow_regs[sr]) {
-
-						//USER Select shadow register set
-						select_shadow_regs_for_update(rank_bgn, read_group,
-									      1);
-
-						WRITE_SCC_DQS_IN_DELAY(read_group, dqs_in_dtaps);
-						scc_mgr_load_dqs(read_group);
-						IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-					}
-				}
-
-// case:56390
-				grp_calibrated = 1;
-				if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
-				    (write_group, read_group, test_bgn)) {
-					// USER Read per-bit deskew can be done on a per shadow register basis
-					for (rank_bgn = 0, sr = 0;
-					     rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
-					     rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
-						//USER Determine if this set of ranks should be skipped entirely
-						if (!param->skip_shadow_regs[sr]) {
-
-							//USER Select shadow register set
-							select_shadow_regs_for_update(rank_bgn,
-										      read_group,
-										      1);
-
-							// Before doing read deskew, set DQS in back to the reserve value
-							WRITE_SCC_DQS_IN_DELAY(read_group,
-									       orig_start_dqs);
-							scc_mgr_load_dqs(read_group);
-							IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-							// If doing read after write calibration, do not update FOM now - do it then
-							if (!rw_mgr_mem_calibrate_vfifo_center
-							    (rank_bgn, write_group, read_group,
-							     test_bgn, 1, 0)) {
-								grp_calibrated = 0;
-								failed_substage =
-								    CAL_SUBSTAGE_VFIFO_CENTER;
-							}
-						}
-					}
-				} else {
-					grp_calibrated = 0;
-					failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
-				}
-			}
-
-		}
-	}
-
-	if (grp_calibrated == 0) {
-		set_failing_group_stage(write_group, CAL_STAGE_VFIFO, failed_substage);
-
-		return 0;
-	}
-	//USER Reset the delay chains back to zero if they have moved > 1 (check for > 1 because loop will increase d even when pass in first case)
-	if (DDRX || RLDRAMII) {
-		if (d > 2) {
-			scc_mgr_zero_group(write_group, write_test_bgn, 1);
-		}
-	}
-
-	return 1;
-}
-
-#else
-
-//USER VFIFO Calibration -- Full Calibration
-static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t g, uint32_t test_bgn)
-{
-	uint32_t p, rank_bgn, sr;
-	uint32_t grp_calibrated;
-	uint32_t failed_substage;
-
-	//USER update info for sims
-
-	reg_file_set_stage(CAL_STAGE_VFIFO);
-
-	reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
-
-	failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
-
-	//USER update info for sims
-
-	reg_file_set_group(g);
-
-	grp_calibrated = 0;
-
-	for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; p++) {
-		//USER set a particular dqdqs phase
-		if (DDRX) {
-			scc_mgr_set_dqdqs_output_phase_all_ranks(g, p);
-		}
-		//USER Load up the patterns used by read calibration using current DQDQS phase
-
-		rw_mgr_mem_calibrate_read_load_patterns_all_ranks();
-		if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
-			if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
-			    (read_group, 1, &bit_chk)) {
-				break;
-			}
-		}
-
-		grp_calibrated = 1;
-		if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(g, g, test_bgn)) {
-			// USER Read per-bit deskew can be done on a per shadow register basis
-			for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
-			     rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
-
-				//USER Determine if this set of ranks should be skipped entirely
-				if (!param->skip_shadow_regs[sr]) {
-
-					//USER Select shadow register set
-					select_shadow_regs_for_update(rank_bgn, read_group, 1);
-
-					if (!rw_mgr_mem_calibrate_vfifo_center
-					    (rank_bgn, g, test_bgn, 1)) {
-						grp_calibrated = 0;
-						failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
-					}
-				}
-			}
-		} else {
-			grp_calibrated = 0;
-			failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
-		}
-	}
-
-	if (grp_calibrated == 0) {
-		set_failing_group_stage(g, CAL_STAGE_VFIFO, failed_substage);
-		return 0;
-	}
-
-	return 1;
-}
-
-#endif
-
-//USER VFIFO Calibration -- Read Deskew Calibration after write deskew
-static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group, uint32_t test_bgn)
-{
-	uint32_t rank_bgn, sr;
-	uint32_t grp_calibrated;
-	uint32_t write_group;
-
-	//USER update info for sims
-
-	reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
-	reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
-
-	if (DDRX) {
-		write_group = read_group;
-	} else {
-		write_group =
-		    read_group / (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH);
-	}
-
-	//USER update info for sims
-	reg_file_set_group(read_group);
-
-	grp_calibrated = 1;
-	// USER Read per-bit deskew can be done on a per shadow register basis
-	for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
-	     rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
-
-		//USER Determine if this set of ranks should be skipped entirely
-		if (!param->skip_shadow_regs[sr]) {
-
-			//USER Select shadow register set
-			select_shadow_regs_for_update(rank_bgn, read_group, 1);
-
-			// This is the last calibration round, update FOM here
-			if (!rw_mgr_mem_calibrate_vfifo_center
-			    (rank_bgn, write_group, read_group, test_bgn, 0, 1)) {
-				grp_calibrated = 0;
-			}
-		}
-	}
-
-	if (grp_calibrated == 0) {
-		set_failing_group_stage(write_group, CAL_STAGE_VFIFO_AFTER_WRITES,
-					CAL_SUBSTAGE_VFIFO_CENTER);
-		return 0;
-	}
-
-	return 1;
-}
-
-//USER Calibrate LFIFO to find smallest read latency
-
-static uint32_t rw_mgr_mem_calibrate_lfifo(void)
-{
-	uint32_t found_one;
-	t_btfld bit_chk;
-
-	//USER update info for sims
-
-	reg_file_set_stage(CAL_STAGE_LFIFO);
-	reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
-
-	//USER Load up the patterns used by read calibration for all ranks
-
-	rw_mgr_mem_calibrate_read_load_patterns_all_ranks();
-
-	found_one = 0;
-
-	do {
-		IOWR_32DIRECT(PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat);
-		DPRINT(2, "lfifo: read_lat=%lu", gbl->curr_read_lat);
-
-		if (!rw_mgr_mem_calibrate_read_test_all_ranks
-		    (0, NUM_READ_TESTS, PASS_ALL_BITS, &bit_chk, 1)) {
-			break;
-		}
-
-		found_one = 1;
-
-		//USER reduce read latency and see if things are working
-		//USER correctly
-
-		gbl->curr_read_lat--;
-	} while (gbl->curr_read_lat > 0);
-
-	//USER reset the fifos to get pointers to known state
-
-	IOWR_32DIRECT(PHY_MGR_CMD_FIFO_RESET, 0, 0);
-
-	if (found_one) {
-		//USER add a fudge factor to the read latency that was determined
-		gbl->curr_read_lat += 2;
-		IOWR_32DIRECT(PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat);
-
-		DPRINT(2, "lfifo: success: using read_lat=%lu", gbl->curr_read_lat);
-
-		return 1;
-	} else {
-		set_failing_group_stage(0xff, CAL_STAGE_LFIFO, CAL_SUBSTAGE_READ_LATENCY);
-
-		DPRINT(2, "lfifo: failed at initial read_lat=%lu", gbl->curr_read_lat);
-
-		return 0;
-	}
-}
-
-//USER issue write test command.
-//USER two variants are provided. one that just tests a write pattern and another that
-//USER tests datamask functionality.
-
-static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group, uint32_t test_dm)
-{
-	uint32_t mcc_instruction;
-	uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES)
-				     && ENABLE_SUPER_QUICK_CALIBRATION) || BFM_MODE;
-	uint32_t rw_wl_nop_cycles;
-
-	//USER Set counter and jump addresses for the right
-	//USER number of NOP cycles.
-	//USER The number of supported NOP cycles can range from -1 to infinity
-	//USER Three different cases are handled:
-	//USER
-	//USER 1. For a number of NOP cycles greater than 0, the RW Mgr looping
-	//USER    mechanism will be used to insert the right number of NOPs
-	//USER
-	//USER 2. For a number of NOP cycles equals to 0, the micro-instruction
-	//USER    issuing the write command will jump straight to the micro-instruction
-	//USER    that turns on DQS (for DDRx), or outputs write data (for RLD), skipping
-	//USER    the NOP micro-instruction all together
-	//USER
-	//USER 3. A number of NOP cycles equal to -1 indicates that DQS must be turned
-	//USER    on in the same micro-instruction that issues the write command. Then we need
-	//USER    to directly jump to the micro-instruction that sends out the data
-	//USER
-	//USER NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters (2 and 3). One
-	//USER       jump-counter (0) is used to perform multiple write-read operations.
-	//USER       one counter left to issue this command in "multiple-group" mode.
-
-	rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
-
-	if (rw_wl_nop_cycles == -1) {
-		//USER CNTR 2 - We want to execute the special write operation that
-		//USER turns on DQS right away and then skip directly to the instruction that
-		//USER sends out the data. We set the counter to a large number so that the
-		//USER jump is always taken
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, 0xFF);
-
-		//USER CNTR 3 - Not used
-		if (test_dm) {
-			mcc_instruction = __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
-			IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0,
-				      __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA);
-			IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP);
-		} else {
-			mcc_instruction = __RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
-			IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_LFSR_WR_RD_BANK_0_DATA);
-			IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_LFSR_WR_RD_BANK_0_NOP);
-		}
-
-	} else if (rw_wl_nop_cycles == 0) {
-		//USER CNTR 2 - We want to skip the NOP operation and go straight to
-		//USER the DQS enable instruction. We set the counter to a large number so that the
-		//USER jump is always taken
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, 0xFF);
-
-		//USER CNTR 3 - Not used
-		if (test_dm) {
-			mcc_instruction = __RW_MGR_LFSR_WR_RD_DM_BANK_0;
-			IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS);
-		} else {
-			mcc_instruction = __RW_MGR_LFSR_WR_RD_BANK_0;
-			IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_LFSR_WR_RD_BANK_0_DQS);
-		}
-
-	} else {
-		//USER CNTR 2 - In this case we want to execute the next instruction and NOT
-		//USER take the jump. So we set the counter to 0. The jump address doesn't count
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, 0x0);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, 0x0);
-
-		//USER CNTR 3 - Set the nop counter to the number of cycles we need to loop for, minus 1
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_3, 0, rw_wl_nop_cycles - 1);
-		if (test_dm) {
-			mcc_instruction = __RW_MGR_LFSR_WR_RD_DM_BANK_0;
-			IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP);
-		} else {
-			mcc_instruction = __RW_MGR_LFSR_WR_RD_BANK_0;
-			IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_LFSR_WR_RD_BANK_0_NOP);
-		}
-	}
-
-	IOWR_32DIRECT(RW_MGR_RESET_READ_DATAPATH, 0, 0);
-
-	if (quick_write_mode) {
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0x08);
-	} else {
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0x40);
-	}
-	IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, mcc_instruction);
-
-	//USER CNTR 1 - This is used to ensure enough time elapses for read data to come back.
-	IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, 0x30);
-
-	if (test_dm) {
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT);
-	} else {
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_LFSR_WR_RD_BANK_0_WAIT);
-	}
-
-	IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, (group << 2), mcc_instruction);
-
-}
-
-//USER Test writes, can check for a single bit pass or multiple bit pass
-
-static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, uint32_t write_group,
-						uint32_t use_dm, uint32_t all_correct,
-						t_btfld * bit_chk, uint32_t all_ranks)
-{
-	uint32_t r;
-	t_btfld correct_mask_vg;
-	t_btfld tmp_bit_chk;
-	uint32_t vg;
-	uint32_t rank_end =
-	    all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS : (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
-
-	*bit_chk = param->write_correct_mask;
-	correct_mask_vg = param->write_correct_mask_vg;
-
-	for (r = rank_bgn; r < rank_end; r++) {
-		if (param->skip_ranks[r]) {
-			//USER request to skip the rank
-
-			continue;
-		}
-		//USER set rank
-		set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
-
-		tmp_bit_chk = 0;
-		for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS - 1;; vg--) {
-
-			//USER reset the fifos to get pointers to known state
-			IOWR_32DIRECT(PHY_MGR_CMD_FIFO_RESET, 0, 0);
-
-			tmp_bit_chk =
-			    tmp_bit_chk << (RW_MGR_MEM_DQ_PER_WRITE_DQS /
-					    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
-			rw_mgr_mem_calibrate_write_test_issue(write_group *
-							      RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
-							      + vg, use_dm);
-
-			tmp_bit_chk =
-			    tmp_bit_chk | (correct_mask_vg & ~(IORD_32DIRECT(BASE_RW_MGR, 0)));
-			DPRINT(2,
-			       "write_test(%lu,%lu,%lu) :[%lu,%lu] " BTFLD_FMT " & ~%x => "
-			       BTFLD_FMT " => " BTFLD_FMT, write_group, use_dm, all_correct, r, vg,
-			       correct_mask_vg, IORD_32DIRECT(BASE_RW_MGR, 0),
-			       correct_mask_vg & ~IORD_32DIRECT(BASE_RW_MGR, 0), tmp_bit_chk);
-
-			if (vg == 0) {
-				break;
-			}
-		}
-		*bit_chk &= tmp_bit_chk;
-	}
-
-	if (all_correct) {
-		set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
-		DPRINT(2, "write_test(%lu,%lu,ALL) : " BTFLD_FMT " == " BTFLD_FMT " => %lu",
-		       write_group, use_dm, *bit_chk, param->write_correct_mask,
-		       (long unsigned int)(*bit_chk == param->write_correct_mask));
-		return (*bit_chk == param->write_correct_mask);
-	} else {
-		set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
-		DPRINT(2, "write_test(%lu,%lu,ONE) : " BTFLD_FMT " != " BTFLD_FMT " => %lu",
-		       write_group, use_dm, *bit_chk, (long unsigned int)0,
-		       (long unsigned int)(*bit_chk != 0));
-		return (*bit_chk != 0x00);
-	}
-}
-
-static inline uint32_t rw_mgr_mem_calibrate_write_test_all_ranks(uint32_t write_group,
-								 uint32_t use_dm,
-								 uint32_t all_correct,
-								 t_btfld * bit_chk)
-{
-	return rw_mgr_mem_calibrate_write_test(0, write_group, use_dm, all_correct, bit_chk, 1);
-}
-
-//USER level the write operations
-
-#if NEWVERSION_WL
-
-//USER Write Levelling -- Full Calibration
-static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn)
-{
-	uint32_t p, d;
-
-	uint32_t num_additional_fr_cycles = 0;
-
-	t_btfld bit_chk;
-	uint32_t work_bgn, work_end, work_mid;
-	uint32_t tmp_delay;
-	uint32_t found_begin;
-	uint32_t dtaps_per_ptap;
-
-	//USER update info for sims
-
-	reg_file_set_stage(CAL_STAGE_WLEVEL);
-	reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY);
-
-	//USER maximum phases for the sweep
-
-	dtaps_per_ptap = IORD_32DIRECT(REG_FILE_DTAPS_PER_PTAP, 0);
-
-	//USER starting phases
-
-	//USER update info for sims
-
-	reg_file_set_group(g);
-
-	//USER starting and end range where writes work
-
-	scc_mgr_spread_out2_delay_all_ranks(g, test_bgn);
-
-	work_bgn = 0;
-	work_end = 0;
-
-	//USER step 1: find first working phase, increment in ptaps, and then in dtaps if ptaps doesn't find a working phase
-	found_begin = 0;
-	tmp_delay = 0;
-	for (d = 0; d <= dtaps_per_ptap; d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP) {
-		scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, d);
-
-		work_bgn = tmp_delay;
-
-		for (p = 0;
-		     p <= IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles * IO_DLL_CHAIN_LENGTH;
-		     p++, work_bgn += IO_DELAY_PER_OPA_TAP) {
-			DPRINT(2, "wlevel: begin-1: p=%lu d=%lu", p, d);
-			scc_mgr_set_dqdqs_output_phase_all_ranks(g, p);
-
-			if (rw_mgr_mem_calibrate_write_test_all_ranks(g, 0, PASS_ONE_BIT, &bit_chk)) {
-				found_begin = 1;
-				break;
-			}
-		}
-
-		if (found_begin) {
-			break;
-		}
-	}
-
-	if (p > IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles * IO_DLL_CHAIN_LENGTH) {
-		//USER fail, cannot find first working phase
-
-		set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY);
-
-		return 0;
-	}
-
-	DPRINT(2, "wlevel: first valid p=%lu d=%lu", p, d);
-
-	reg_file_set_sub_stage(CAL_SUBSTAGE_LAST_WORKING_DELAY);
-
-	//USER If d is 0 then the working window covers a phase tap and we can follow the old procedure
-	//USER  otherwise, we've found the beginning, and we need to increment the dtaps until we find the end
-	if (d == 0) {
-		COV(WLEVEL_PHASE_PTAP_OVERLAP);
-		work_end = work_bgn + IO_DELAY_PER_OPA_TAP;
-
-		//USER step 2: if we have room, back off by one and increment in dtaps
-
-		if (p > 0) {
-			int found = 0;
-			scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1);
-
-			tmp_delay = work_bgn - IO_DELAY_PER_OPA_TAP;
-
-			for (d = 0; d <= IO_IO_OUT1_DELAY_MAX && tmp_delay < work_bgn;
-			     d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP) {
-				DPRINT(2, "wlevel: begin-2: p=%lu d=%lu", (p - 1), d);
-				scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, d);
-
-				if (rw_mgr_mem_calibrate_write_test_all_ranks
-				    (g, 0, PASS_ONE_BIT, &bit_chk)) {
-					found = 1;
-					work_bgn = tmp_delay;
-					break;
-				}
-			}
-
-			{
-				uint32_t d2;
-				uint32_t p2;
-				if (found) {
-					d2 = d;
-					p2 = p - 1;
-				} else {
-					d2 = 0;
-					p2 = p;
-				}
-
-				DPRINT(2, "wlevel: found begin-A: p=%lu d=%lu ps=%lu", p2, d2,
-				       work_bgn);
-
-				BFM_GBL_SET(dqs_wlevel_left_edge[g].p, p2);
-				BFM_GBL_SET(dqs_wlevel_left_edge[g].d, d2);
-				BFM_GBL_SET(dqs_wlevel_left_edge[g].ps, work_bgn);
-			}
-
-			scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, 0);
-		} else {
-			DPRINT(2, "wlevel: found begin-B: p=%lu d=%lu ps=%lu", p, d, work_bgn);
-
-			BFM_GBL_SET(dqs_wlevel_left_edge[g].p, p);
-			BFM_GBL_SET(dqs_wlevel_left_edge[g].d, d);
-			BFM_GBL_SET(dqs_wlevel_left_edge[g].ps, work_bgn);
-		}
-
-		//USER step 3: go forward from working phase to non working phase, increment in ptaps
-
-		for (p = p + 1;
-		     p <= IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles * IO_DLL_CHAIN_LENGTH;
-		     p++, work_end += IO_DELAY_PER_OPA_TAP) {
-			DPRINT(2, "wlevel: end-0: p=%lu d=%lu", p, (long unsigned int)0);
-			scc_mgr_set_dqdqs_output_phase_all_ranks(g, p);
-
-			if (!rw_mgr_mem_calibrate_write_test_all_ranks
-			    (g, 0, PASS_ONE_BIT, &bit_chk)) {
-				break;
-			}
-		}
-
-		//USER step 4: back off one from last, increment in dtaps
-		//USER The actual increment is done outside the if/else statement since it is shared with other code
-
-		p = p - 1;
-
-		scc_mgr_set_dqdqs_output_phase_all_ranks(g, p);
-
-		work_end -= IO_DELAY_PER_OPA_TAP;
-		d = 0;
-
-	} else {
-		//USER step 5: Window doesn't cover phase tap, just increment dtaps until failure
-		//USER The actual increment is done outside the if/else statement since it is shared with other code
-		COV(WLEVEL_PHASE_PTAP_NO_OVERLAP);
-		work_end = work_bgn;
-		DPRINT(2, "wlevel: found begin-C: p=%lu d=%lu ps=%lu", p, d, work_bgn);
-		BFM_GBL_SET(dqs_wlevel_left_edge[g].p, p);
-		BFM_GBL_SET(dqs_wlevel_left_edge[g].d, d);
-		BFM_GBL_SET(dqs_wlevel_left_edge[g].ps, work_bgn);
-
-	}
-
-	//USER The actual increment until failure
-	for (; d <= IO_IO_OUT1_DELAY_MAX; d++, work_end += IO_DELAY_PER_DCHAIN_TAP) {
-		DPRINT(2, "wlevel: end: p=%lu d=%lu", p, d);
-		scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, d);
-
-		if (!rw_mgr_mem_calibrate_write_test_all_ranks(g, 0, PASS_ONE_BIT, &bit_chk)) {
-			break;
-		}
-	}
-	scc_mgr_zero_group(g, test_bgn, 1);
-
-	work_end -= IO_DELAY_PER_DCHAIN_TAP;
-
-	if (work_end >= work_bgn) {
-		//USER we have a working range
-	} else {
-		//USER nil range
-
-		set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_LAST_WORKING_DELAY);
-
-		return 0;
-	}
-
-	DPRINT(2, "wlevel: found end: p=%lu d=%lu; range: [%lu,%lu]", p, d - 1, work_bgn, work_end);
-	BFM_GBL_SET(dqs_wlevel_right_edge[g].p, p);
-	BFM_GBL_SET(dqs_wlevel_right_edge[g].d, d - 1);
-	BFM_GBL_SET(dqs_wlevel_right_edge[g].ps, work_end);
-
-	//USER center
-
-	work_mid = (work_bgn + work_end) / 2;
-
-	DPRINT(2, "wlevel: work_mid=%ld", work_mid);
-
-	tmp_delay = 0;
-
-	for (p = 0;
-	     p <= IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles * IO_DLL_CHAIN_LENGTH
-	     && tmp_delay < work_mid; p++, tmp_delay += IO_DELAY_PER_OPA_TAP) ;
-
-	if (tmp_delay > work_mid) {
-		tmp_delay -= IO_DELAY_PER_OPA_TAP;
-		p--;
-	}
-
-	while (p > IO_DQDQS_OUT_PHASE_MAX) {
-		tmp_delay -= IO_DELAY_PER_OPA_TAP;
-		p--;
-	}
-
-	scc_mgr_set_dqdqs_output_phase_all_ranks(g, p);
-
-	DPRINT(2, "wlevel: p=%lu tmp_delay=%lu left=%lu", p, tmp_delay, work_mid - tmp_delay);
-
-	for (d = 0; d <= IO_IO_OUT1_DELAY_MAX && tmp_delay < work_mid;
-	     d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP) ;
-
-	if (tmp_delay > work_mid) {
-		tmp_delay -= IO_DELAY_PER_DCHAIN_TAP;
-		d--;
-	}
-
-	DPRINT(2, "wlevel: p=%lu d=%lu tmp_delay=%lu left=%lu", p, d, tmp_delay,
-	       work_mid - tmp_delay);
-
-	scc_mgr_apply_group_all_out_delay_add_all_ranks(g, test_bgn, d);
-
-	DPRINT(2, "wlevel: found middle: p=%lu d=%lu", p, d);
-	BFM_GBL_SET(dqs_wlevel_mid[g].p, p);
-	BFM_GBL_SET(dqs_wlevel_mid[g].d, d);
-	BFM_GBL_SET(dqs_wlevel_mid[g].ps, work_mid);
-
-	return 1;
-}
-
-#else
-
-//USER Write Levelling -- Full Calibration
-static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn)
-{
-	uint32_t p, d;
-	t_btfld bit_chk;
-	uint32_t work_bgn, work_end, work_mid;
-	uint32_t tmp_delay;
-
-	//USER update info for sims
-
-	reg_file_set_stage(CAL_STAGE_WLEVEL);
-	reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY);
-
-	//USER maximum phases for the sweep
-
-	//USER starting phases
-
-	//USER update info for sims
-
-	reg_file_set_group(g);
-
-	//USER starting and end range where writes work
-
-	work_bgn = 0;
-	work_end = 0;
-
-	//USER step 1: find first working phase, increment in ptaps
-
-	for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++, work_bgn += IO_DELAY_PER_OPA_TAP) {
-		scc_mgr_set_dqdqs_output_phase_all_ranks(g, p);
-
-		if (rw_mgr_mem_calibrate_write_test_all_ranks(g, 0, PASS_ONE_BIT, &bit_chk)) {
-			break;
-		}
-	}
-
-	if (p > IO_DQDQS_OUT_PHASE_MAX) {
-		//USER fail, cannot find first working phase
-
-		set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY);
-
-		return 0;
-	}
-
-	work_end = work_bgn + IO_DELAY_PER_OPA_TAP;
-
-	reg_file_set_sub_stage(CAL_SUBSTAGE_LAST_WORKING_DELAY);
-
-	//USER step 2: if we have room, back off by one and increment in dtaps
-
-	if (p > 0) {
-		scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1);
-
-		tmp_delay = work_bgn - IO_DELAY_PER_OPA_TAP;
-
-		for (d = 0; d <= IO_IO_OUT1_DELAY_MAX && tmp_delay < work_bgn;
-		     d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP) {
-			scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, d);
-
-			if (rw_mgr_mem_calibrate_write_test_all_ranks(g, 0, PASS_ONE_BIT, &bit_chk)) {
-				work_bgn = tmp_delay;
-				break;
-			}
-		}
-
-		scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, 0);
-	}
-	//USER step 3: go forward from working phase to non working phase, increment in ptaps
-
-	for (p = p + 1; p <= IO_DQDQS_OUT_PHASE_MAX; p++, work_end += IO_DELAY_PER_OPA_TAP) {
-		scc_mgr_set_dqdqs_output_phase_all_ranks(g, p);
-
-		if (!rw_mgr_mem_calibrate_write_test_all_ranks(g, 0, PASS_ONE_BIT, &bit_chk)) {
-			break;
-		}
-	}
-
-	//USER step 4: back off one from last, increment in dtaps
-
-	scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1);
-
-	work_end -= IO_DELAY_PER_OPA_TAP;
-
-	for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++, work_end += IO_DELAY_PER_DCHAIN_TAP) {
-		scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, d);
-
-		if (!rw_mgr_mem_calibrate_write_test_all_ranks(g, 0, PASS_ONE_BIT, &bit_chk)) {
-			break;
-		}
-	}
-
-	scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, 0);
-
-	if (work_end > work_bgn) {
-		//USER we have a working range
-	} else {
-		//USER nil range
-
-		set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_LAST_WORKING_DELAY);
-
-		return 0;
-	}
-
-	//USER center
-
-	work_mid = (work_bgn + work_end) / 2;
-
-	tmp_delay = 0;
-
-	for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && tmp_delay < work_mid;
-	     p++, tmp_delay += IO_DELAY_PER_OPA_TAP) ;
-
-	tmp_delay -= IO_DELAY_PER_OPA_TAP;
-
-	scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1);
-
-	for (d = 0; d <= IO_IO_OUT1_DELAY_MAX && tmp_delay < work_mid;
-	     d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP) ;
-
-	scc_mgr_apply_group_all_out_delay_add_all_ranks(g, test_bgn, d - 1);
-
-	return 1;
-}
-
-#endif
-
-//USER center all windows. do per-bit-deskew to possibly increase size of certain windows
-
-#if NEWVERSION_WRDESKEW
-
-static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t write_group,
-						   uint32_t test_bgn)
-{
-	uint32_t i, p, min_index;
-	int32_t d;
-	//USER Store these as signed since there are comparisons with signed numbers
-	t_btfld bit_chk;
-	t_btfld sticky_bit_chk;
-	int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
-	int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
-	int32_t mid;
-	int32_t mid_min, orig_mid_min;
-	int32_t new_dqs, start_dqs, shift_dq;
-	int32_t dq_margin, dqs_margin, dm_margin;
-	uint32_t stop;
-	int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
-	int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
-	int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
-	int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
-	int32_t win_best = 0;
-
-	dm_margin = 0;
-
-	start_dqs = READ_SCC_DQS_IO_OUT1_DELAY();
-
-	select_curr_shadow_reg_using_rank(rank_bgn);
-
-	//USER per-bit deskew
-
-	//USER set the left and right edge of each bit to an illegal value
-	//USER use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value
-	sticky_bit_chk = 0;
-	for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-		left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
-		right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
-	}
-
-	//USER Search for the left edge of the window for each bit
-	for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
-		scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-		//USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit
-		stop =
-		    !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, PASS_ONE_BIT,
-						     &bit_chk, 0);
-		sticky_bit_chk = sticky_bit_chk | bit_chk;
-		stop = stop && (sticky_bit_chk == param->write_correct_mask);
-		DPRINT(2,
-		       "write_center(left): dtap=%lu => " BTFLD_FMT " == " BTFLD_FMT
-		       " && %lu [bit_chk=" BTFLD_FMT "]", d, sticky_bit_chk,
-		       param->write_correct_mask, stop, bit_chk);
-
-		if (stop == 1) {
-			break;
-		} else {
-			for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-				if (bit_chk & 1) {
-					//USER Remember a passing test as the left_edge
-					left_edge[i] = d;
-				} else {
-					//USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge
-					if (left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) {
-						right_edge[i] = -(d + 1);
-					}
-				}
-				DPRINT(2,
-				       "write_center[l,d=%lu): bit_chk_test=%d left_edge[%lu]: %ld right_edge[%lu]: %ld",
-				       d, (int)(bit_chk & 1), i, left_edge[i], i, right_edge[i]);
-				bit_chk = bit_chk >> 1;
-			}
-		}
-	}
-
-	//USER Reset DQ delay chains to 0
-	scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0);
-	sticky_bit_chk = 0;
-	for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
-
-		DPRINT(2, "write_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i],
-		       i, right_edge[i]);
-
-		//USER Check for cases where we haven't found the left edge, which makes our assignment of the the
-		//USER right edge invalid.  Reset it to the illegal value.
-		if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)
-		    && (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
-			right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
-			DPRINT(2, "write_center: reset right_edge[%lu]: %ld", i, right_edge[i]);
-		}
-		//USER Reset sticky bit (except for bits where we have seen the left edge)
-		sticky_bit_chk = sticky_bit_chk << 1;
-		if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
-			sticky_bit_chk = sticky_bit_chk | 1;
-		}
-
-		if (i == 0) {
-			break;
-		}
-	}
-
-	//USER Search for the right edge of the window for each bit
-	for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
-		scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, d + start_dqs);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-		if (QDRII) {
-			rw_mgr_mem_dll_lock_wait();
-		}
-		//USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit
-		stop =
-		    !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, PASS_ONE_BIT,
-						     &bit_chk, 0);
-		if (stop) {
-			recover_mem_device_after_ck_dqs_violation();
-		}
-		sticky_bit_chk = sticky_bit_chk | bit_chk;
-		stop = stop && (sticky_bit_chk == param->write_correct_mask);
-
-		DPRINT(2, "write_center (right): dtap=%lu => " BTFLD_FMT " == " BTFLD_FMT " && %lu",
-		       d, sticky_bit_chk, param->write_correct_mask, stop);
-
-		if (stop == 1) {
-			if (d == 0) {
-				for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-					//USER d = 0 failed, but it passed when testing the left edge, so it must be marginal, set it to -1
-					if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1
-					    && left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1) {
-						right_edge[i] = -1;
-					}
-				}
-			}
-			break;
-		} else {
-			for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-				if (bit_chk & 1) {
-					//USER Remember a passing test as the right_edge
-					right_edge[i] = d;
-				} else {
-					if (d != 0) {
-						//USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge
-						if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) {
-							left_edge[i] = -(d + 1);
-						}
-					} else {
-						//USER d = 0 failed, but it passed when testing the left edge, so it must be marginal, set it to -1
-						if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1
-						    && left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1) {
-							right_edge[i] = -1;
-						}
-						//USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge
-						else if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) {
-							left_edge[i] = -(d + 1);
-						}
-					}
-				}
-				DPRINT(2,
-				       "write_center[r,d=%lu): bit_chk_test=%d left_edge[%lu]: %ld right_edge[%lu]: %ld",
-				       d, (int)(bit_chk & 1), i, left_edge[i], i, right_edge[i]);
-				bit_chk = bit_chk >> 1;
-			}
-		}
-	}
-
-	//USER Check that all bits have a window
-	for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-		DPRINT(2, "write_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i],
-		       i, right_edge[i]);
-		BFM_GBL_SET(dq_write_left_edge[write_group][i], left_edge[i]);
-		BFM_GBL_SET(dq_write_right_edge[write_group][i], right_edge[i]);
-		if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)
-		    || (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
-			set_failing_group_stage(test_bgn + i, CAL_STAGE_WRITES,
-						CAL_SUBSTAGE_WRITES_CENTER);
-			return 0;
-		}
-	}
-
-	//USER Find middle of window for each DQ bit
-	mid_min = left_edge[0] - right_edge[0];
-	min_index = 0;
-	for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-		mid = left_edge[i] - right_edge[i];
-		if (mid < mid_min) {
-			mid_min = mid;
-			min_index = i;
-		}
-	}
-
-	//USER  -mid_min/2 represents the amount that we need to move DQS.  If mid_min is odd and positive we'll need to add one to
-	//USER make sure the rounding in further calculations is correct (always bias to the right), so just add 1 for all positive values
-	if (mid_min > 0) {
-		mid_min++;
-	}
-	mid_min = mid_min / 2;
-
-	DPRINT(1, "write_center: mid_min=%ld", mid_min);
-
-	//USER Determine the amount we can change DQS (which is -mid_min)
-	orig_mid_min = mid_min;
-	new_dqs = start_dqs;
-	mid_min = 0;
-
-	DPRINT(1, "write_center: start_dqs=%ld new_dqs=%ld mid_min=%ld", start_dqs, new_dqs,
-	       mid_min);
-
-	//USER Initialize data for export structures
-	dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
-	dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
-
-	//USER add delay to bring centre of all DQ windows to the same "level"
-	for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
-		//USER Use values before divide by 2 to reduce round off error
-		shift_dq =
-		    (left_edge[i] - right_edge[i] -
-		     (left_edge[min_index] - right_edge[min_index])) / 2 + (orig_mid_min - mid_min);
-
-		DPRINT(2, "write_center: before: shift_dq[%lu]=%ld", i, shift_dq);
-
-		if (shift_dq + (int32_t) READ_SCC_DQ_OUT1_DELAY(i) > (int32_t) IO_IO_OUT1_DELAY_MAX) {
-			shift_dq = (int32_t) IO_IO_OUT1_DELAY_MAX - READ_SCC_DQ_OUT1_DELAY(i);
-		} else if (shift_dq + (int32_t) READ_SCC_DQ_OUT1_DELAY(i) < 0) {
-			shift_dq = -(int32_t) READ_SCC_DQ_OUT1_DELAY(i);
-		}
-		DPRINT(2, "write_center: after: shift_dq[%lu]=%ld", i, shift_dq);
-		scc_mgr_set_dq_out1_delay(write_group, i, READ_SCC_DQ_OUT1_DELAY(i) + shift_dq);
-		scc_mgr_load_dq(i);
-
-		DPRINT(2, "write_center: margin[%lu]=[%ld,%ld]", i,
-		       left_edge[i] - shift_dq + (-mid_min), right_edge[i] + shift_dq - (-mid_min));
-		//USER To determine values for export structures
-		if (left_edge[i] - shift_dq + (-mid_min) < dq_margin) {
-			dq_margin = left_edge[i] - shift_dq + (-mid_min);
-		}
-		if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin) {
-			dqs_margin = right_edge[i] + shift_dq - (-mid_min);
-		}
-	}
-
-	//USER Move DQS
-	if (QDRII) {
-		scc_mgr_set_group_dqs_io_and_oct_out1_gradual(write_group, new_dqs);
-	} else {
-		scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	}
-
-	DPRINT(2, "write_center: DM");
-
-	//USER set the left and right edge of each bit to an illegal value
-	//USER use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value
-	left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
-	right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
-
-	//USER Search for the/part of the window with DM shift
-	for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
-		scc_mgr_apply_group_dm_out1_delay(write_group, d);
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-		if (rw_mgr_mem_calibrate_write_test
-		    (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) {
-
-			//USE Set current end of the window
-			end_curr = -d;
-			//USER If a starting edge of our window has not been seen this is our current start of the DM window
-			if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1) {
-				bgn_curr = -d;
-			}
-			//USER If current window is bigger than best seen. Set best seen to be current window
-			if ((end_curr - bgn_curr + 1) > win_best) {
-				win_best = end_curr - bgn_curr + 1;
-				bgn_best = bgn_curr;
-				end_best = end_curr;
-			}
-		} else {
-			//USER We just saw a failing test. Reset temp edge
-			bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
-			end_curr = IO_IO_OUT1_DELAY_MAX + 1;
-		}
-
-	}
-
-	//USER Reset DM delay chains to 0
-	scc_mgr_apply_group_dm_out1_delay(write_group, 0);
-
-	//USER Check to see if the current window nudges up aganist 0 delay. If so we need to continue the search by shifting DQS otherwise DQS search begins as a new search
-	if (end_curr != 0) {
-		bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
-		end_curr = IO_IO_OUT1_DELAY_MAX + 1;
-	}
-	//USER Search for the/part of the window with DQS shifts
-	for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
-		// Note: This only shifts DQS, so are we limiting ourselve to
-		// width of DQ unnecessarily
-		scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, d + new_dqs);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-		if (rw_mgr_mem_calibrate_write_test
-		    (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) {
-
-			//USE Set current end of the window
-			end_curr = d;
-			//USER If a beginning edge of our window has not been seen this is our current begin of the DM window
-			if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1) {
-				bgn_curr = d;
-			}
-			//USER If current window is bigger than best seen. Set best seen to be current window
-			if ((end_curr - bgn_curr + 1) > win_best) {
-				win_best = end_curr - bgn_curr + 1;
-				bgn_best = bgn_curr;
-				end_best = end_curr;
-			}
-		} else {
-			//USER We just saw a failing test. Reset temp edge
-			recover_mem_device_after_ck_dqs_violation();
-			bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
-			end_curr = IO_IO_OUT1_DELAY_MAX + 1;
-
-			//USER Early exit optimization: if ther remaining delay chain space is less than already seen largest window we can exit
-			if ((win_best - 1) > (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
-				break;
-			}
-
-		}
-	}
-
-	//USER assign left and right edge for cal and reporting;
-	left_edge[0] = -1 * bgn_best;
-	right_edge[0] = end_best;
-
-	DPRINT(2, "dm_calib: left=%ld right=%ld", left_edge[0], right_edge[0]);
-	BFM_GBL_SET(dm_left_edge[write_group][0], left_edge[0]);
-	BFM_GBL_SET(dm_right_edge[write_group][0], right_edge[0]);
-
-	//USER Move DQS (back to orig)
-	scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
-
-	//USER Move DM
-
-	//USER Find middle of window for the DM bit
-	mid = (left_edge[0] - right_edge[0]) / 2;
-
-	//USER only move right, since we are not moving DQS/DQ
-	if (mid < 0) {
-		mid = 0;
-	}
-	//dm_marign should fail if we never find a window
-	if (win_best == 0) {
-		dm_margin = -1;
-	} else {
-		dm_margin = left_edge[0] - mid;
-	}
-
-	scc_mgr_apply_group_dm_out1_delay(write_group, mid);
-	IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-	DPRINT(2, "dm_calib: left=%ld right=%ld mid=%ld dm_margin=%ld",
-	       left_edge[0], right_edge[0], mid, dm_margin);
-
-	//USER Export values
-	gbl->fom_out += dq_margin + dqs_margin;
-
-	DPRINT(2, "write_center: dq_margin=%ld dqs_margin=%ld dm_margin=%ld", dq_margin, dqs_margin,
-	       dm_margin);
-
-	//USER Do not remove this line as it makes sure all of our decisions have been applied
-	IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
-}
-
-#else // !NEWVERSION_WRDESKEW
-
-static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t write_group,
-						   uint32_t test_bgn)
-{
-	uint32_t i, p, d;
-	uint32_t mid;
-	t_btfld bit_chk, sticky_bit_chk;
-	uint32_t max_working_dq[RW_MGR_MEM_DQ_PER_WRITE_DQS];
-	uint32_t max_working_dm[RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH];
-	uint32_t dq_margin, dqs_margin, dm_margin;
-	uint32_t start_dqs;
-	uint32_t stop;
-
-	//USER per-bit deskew
-
-	for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-		max_working_dq[i] = 0;
-	}
-
-	for (d = 1; d <= IO_IO_OUT1_DELAY_MAX; d++) {
-		scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-		if (!rw_mgr_mem_calibrate_write_test
-		    (rank_bgn, write_group, 0, PASS_ONE_BIT, &bit_chk, 0)) {
-			break;
-		} else {
-			for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-				if (bit_chk & 1) {
-					max_working_dq[i] = d;
-				}
-				bit_chk = bit_chk >> 1;
-			}
-		}
-	}
-
-	scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0);
-
-	//USER determine minimum of maximums
-
-	dq_margin = IO_IO_OUT1_DELAY_MAX;
-
-	for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
-		if (max_working_dq[i] < dq_margin) {
-			dq_margin = max_working_dq[i];
-		}
-	}
-
-	//USER add delay to center DQ windows
-
-	for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
-		if (max_working_dq[i] > dq_margin) {
-			scc_mgr_set_dq_out1_delay(write_group, i, max_working_dq[i] - dq_margin);
-		} else {
-			scc_mgr_set_dq_out1_delay(write_group, i, 0);
-		}
-
-		scc_mgr_load_dq(p, i);
-	}
-
-	//USER sweep DQS window, may potentially have more window due to per-bit-deskew
-
-	start_dqs = READ_SCC_DQS_IO_OUT1_DELAY();
-
-	for (d = start_dqs + 1; d <= IO_IO_OUT1_DELAY_MAX; d++) {
-		scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, d);
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-		if (QDRII) {
-			rw_mgr_mem_dll_lock_wait();
-		}
-
-		if (!rw_mgr_mem_calibrate_write_test
-		    (rank_bgn, write_group, 0, PASS_ALL_BITS, &bit_chk, 0)) {
-			break;
-		}
-	}
-
-	scc_mgr_set_dqs_out1_delay(write_group, start_dqs);
-	scc_mgr_set_oct_out1_delay(write_group, start_dqs);
-
-	dqs_margin = d - start_dqs - 1;
-
-	//USER time to center, +1 so that we don't go crazy centering DQ
-
-	mid = (dq_margin + dqs_margin + 1) / 2;
-
-	gbl->fom_out += dq_margin + dqs_margin;
-
-	scc_mgr_load_dqs_io();
-	scc_mgr_load_dqs_for_write_group(write_group);
-
-	//USER center dq
-
-	if (dq_margin > mid) {
-		for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
-			scc_mgr_set_dq_out1_delay(write_group, i,
-						  READ_SCC_DQ_OUT1_DELAY(i) + dq_margin - mid);
-			scc_mgr_load_dq(p, i);
-		}
-		dqs_margin += dq_margin - mid;
-		dq_margin -= dq_margin - mid;
-	}
-	//USER do dm centering
-
-	if (!RLDRAMX) {
-		dm_margin = IO_IO_OUT1_DELAY_MAX;
-
-		if (QDRII) {
-			sticky_bit_chk = 0;
-			for (i = 0; i < RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
-			     i++) {
-				max_working_dm[i] = 0;
-			}
-		}
-
-		for (d = 1; d <= IO_IO_OUT1_DELAY_MAX; d++) {
-			scc_mgr_apply_group_dm_out1_delay(write_group, d);
-			IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-			if (DDRX) {
-				if (rw_mgr_mem_calibrate_write_test
-				    (rank_bgn, write_group, 1, PASS_ALL_BITS, &bit_chk, 0)) {
-					max_working_dm[0] = d;
-				} else {
-					break;
-				}
-			} else {
-				stop =
-				    !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
-								     PASS_ALL_BITS, &bit_chk, 0);
-				sticky_bit_chk = sticky_bit_chk | bit_chk;
-				stop = stop && (sticky_bit_chk == param->read_correct_mask);
-
-				if (stop == 1) {
-					break;
-				} else {
-					for (i = 0;
-					     i <
-					     RW_MGR_MEM_DATA_MASK_WIDTH /
-					     RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
-						if ((bit_chk & param->dm_correct_mask) ==
-						    param->dm_correct_mask) {
-							max_working_dm[i] = d;
-						}
-						bit_chk =
-						    bit_chk >> (RW_MGR_MEM_DATA_WIDTH /
-								RW_MGR_MEM_DATA_MASK_WIDTH);
-					}
-				}
-			}
-		}
-
-		i = 0;
-		for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
-			if (max_working_dm[i] > mid) {
-				scc_mgr_set_dm_out1_delay(write_group, i, max_working_dm[i] - mid);
-			} else {
-				scc_mgr_set_dm_out1_delay(write_group, i, 0);
-			}
-
-			scc_mgr_load_dm(i);
-
-			if (max_working_dm[i] < dm_margin) {
-				dm_margin = max_working_dm[i];
-			}
-		}
-	} else {
-		dm_margin = 0;
-	}
-
-	IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-	return (dq_margin + dqs_margin) > 0;
-}
-
-#endif
-
-//USER calibrate the write operations
-
-static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g, uint32_t test_bgn)
-{
-
-	reg_file_set_stage(CAL_STAGE_WRITES);
-	reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
-
-	//USER starting phases
-
-	//USER update info for sims
-
-	reg_file_set_group(g);
-
-	if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
-		set_failing_group_stage(g, CAL_STAGE_WRITES, CAL_SUBSTAGE_WRITES_CENTER);
-		return 0;
-	}
-
-	return 1;
-}
-
-//USER precharge all banks and activate row 0 in bank "000..." and bank "111..."
-static void mem_precharge_and_activate(void)
-{
-	uint32_t r;
-
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
-		if (param->skip_ranks[r]) {
-			//USER request to skip the rank
-
-			continue;
-		}
-		//USER set rank
-		set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
-
-		//USER precharge all banks ...
-		IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0x0F);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT1);
-
-		IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, 0x0F);
-		IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT2);
-
-		//USER activate rows
-		IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ACTIVATE_0_AND_1);
-	}
-}
-
-//USER perform all refreshes necessary over all ranks
-
-//USER Configure various memory related parameters.
-
-static void mem_config(void)
-{
-	uint32_t rlat, wlat;
-	uint32_t rw_wl_nop_cycles;
-	uint32_t max_latency;
-
-	//USER read in write and read latency
-
-	wlat = IORD_32DIRECT(MEM_T_WL_ADD, 0);
-	wlat += IORD_32DIRECT(DATA_MGR_MEM_T_ADD, 0);	/* WL for hard phy does not include additive latency */
-
-	// YYONG: add addtional write latency to offset the address/command extra clock cycle
-	// YYONG: We change the AC mux setting causing AC to be delayed by one mem clock cycle
-	// YYONG: only do this for DDR3
-	wlat = wlat + 1;
-
-	rlat = IORD_32DIRECT(MEM_T_RL_ADD, 0);
-
-	if (QUARTER_RATE_MODE) {
-		//USER In Quarter-Rate the WL-to-nop-cycles works like this
-		//USER 0,1     -> 0
-		//USER 2,3,4,5 -> 1
-		//USER 6,7,8,9 -> 2
-		//USER etc...
-		rw_wl_nop_cycles = (wlat + 6) / 4 - 1;
-	} else if (HALF_RATE_MODE) {
-		//USER In Half-Rate the WL-to-nop-cycles works like this
-		//USER 0,1 -> -1
-		//USER 2,3 -> 0
-		//USER 4,5 -> 1
-		//USER etc...
-		if (wlat % 2) {
-			rw_wl_nop_cycles = ((wlat - 1) / 2) - 1;
-		} else {
-			rw_wl_nop_cycles = (wlat / 2) - 1;
-		}
-	} else {
-		rw_wl_nop_cycles = wlat - 2;
-	}
-	gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
-
-	//USER For AV/CV, lfifo is hardened and always runs at full rate
-	//USER so max latency in AFI clocks, used here, is correspondingly smaller
-	if (QUARTER_RATE_MODE) {
-		max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) / 4 - 1;
-	} else if (HALF_RATE_MODE) {
-		max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) / 2 - 1;
-	} else {
-		max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) / 1 - 1;
-	}
-	//USER configure for a burst length of 8
-
-	if (QUARTER_RATE_MODE) {
-		//USER write latency
-		wlat = (wlat + 5) / 4 + 1;
-
-		//USER set a pretty high read latency initially
-		gbl->curr_read_lat = (rlat + 1) / 4 + 8;
-	} else if (HALF_RATE_MODE) {
-		//USER write latency
-		wlat = (wlat - 1) / 2 + 1;
-
-		//USER set a pretty high read latency initially
-		gbl->curr_read_lat = (rlat + 1) / 2 + 8;
-	} else {
-		//USER write latency
-		// Adjust Write Latency for Hard PHY
-		wlat = wlat + 1;
-
-		//USER set a pretty high read latency initially
-		gbl->curr_read_lat = rlat + 16;
-	}
-
-	if (gbl->curr_read_lat > max_latency) {
-		gbl->curr_read_lat = max_latency;
-	}
-	IOWR_32DIRECT(PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat);
-
-	//USER advertise write latency
-	gbl->curr_write_lat = wlat;
-	IOWR_32DIRECT(PHY_MGR_AFI_WLAT, 0, wlat - 2);
-
-	//USER initialize bit slips
-
-	mem_precharge_and_activate();
-}
-
-//USER Set VFIFO and LFIFO to instant-on settings in skip calibration mode
-
-static void mem_skip_calibrate(void)
-{
-	uint32_t vfifo_offset;
-	uint32_t i, j, r;
-
-	// Need to update every shadow register set used by the interface
-	for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) {
-
-		// Strictly speaking this should be called once per group to make
-		// sure each group's delay chains are refreshed from the SCC register file,
-		// but since we're resetting all delay chains anyway, we can save some
-		// runtime by calling select_shadow_regs_for_update just once to switch rank.
-		select_shadow_regs_for_update(r, 0, 1);
-
-		//USER Set output phase alignment settings appropriate for skip calibration
-		for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
-
-			scc_mgr_set_dqs_en_phase(i, 0);
-			// Case:33398
-			//
-			// Write data arrives to the I/O two cycles before write latency is reached (720 deg).
-			//   -> due to bit-slip in a/c bus
-			//   -> to allow board skew where dqs is longer than ck
-			//      -> how often can this happen!?
-			//      -> can claim back some ptaps for high freq support if we can relax this, but i digress...
-			//
-			// The write_clk leads mem_ck by 90 deg
-			// The minimum ptap of the OPA is 180 deg
-			// Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
-			// The write_clk is always delayed by 2 ptaps
-			//
-			// Hence, to make DQS aligned to CK, we need to delay DQS by:
-			//    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
-			//
-			// Dividing the above by (360 / IO_DLL_CHAIN_LENGTH) gives us the number of ptaps, which simplies to:
-			//
-			//    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
-			scc_mgr_set_dqdqs_output_phase(i, (1.25 * IO_DLL_CHAIN_LENGTH - 2));
-		}
-
-		IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, 0xff);
-		IOWR_32DIRECT(SCC_MGR_DQS_IO_ENA, 0, 0xff);
-
-		for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
-			IOWR_32DIRECT(SCC_MGR_GROUP_COUNTER, 0, i);
-			IOWR_32DIRECT(SCC_MGR_DQ_ENA, 0, 0xff);
-			IOWR_32DIRECT(SCC_MGR_DM_ENA, 0, 0xff);
-		}
-
-		IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	}
-
-	// Compensate for simulation model behaviour
-	for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
-		scc_mgr_set_dqs_bus_in_delay(i, 10);
-		scc_mgr_load_dqs(i);
-	}
-	IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-
-	//ArriaV has hard FIFOs that can only be initialized by incrementing in sequencer
-	vfifo_offset = CALIB_VFIFO_OFFSET;
-	for (j = 0; j < vfifo_offset; j++) {
-		if (HARD_PHY) {
-			IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_HARD_PHY, 0, 0xff);
-		} else {
-			IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_FR, 0, 0xff);
-		}
-	}
-
-	IOWR_32DIRECT(PHY_MGR_CMD_FIFO_RESET, 0, 0);
-
-	// For ACV with hard lfifo, we get the skip-cal setting from generation-time constant
-	gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
-	IOWR_32DIRECT(PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat);
-}
-
-//USER Memory calibration entry point
-
-static uint32_t mem_calibrate(void)
-{
-	uint32_t i;
-	uint32_t rank_bgn, sr;
-	uint32_t write_group, write_test_bgn;
-	uint32_t read_group, read_test_bgn;
-	uint32_t run_groups, current_run;
-	uint32_t failing_groups = 0;
-	uint32_t group_failed = 0;
-	uint32_t sr_failed = 0;
-
-	// Initialize the data settings
-	DPRINT(1, "Preparing to init data");
-	DPRINT(1, "Init complete");
-
-	gbl->error_substage = CAL_SUBSTAGE_NIL;
-	gbl->error_stage = CAL_STAGE_NIL;
-	gbl->error_group = 0xff;
-	gbl->fom_in = 0;
-	gbl->fom_out = 0;
-
-	mem_config();
-
-	if (ARRIAV || CYCLONEV) {
-		uint32_t bypass_mode = (HARD_PHY) ? 0x1 : 0x0;
-		for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
-			IOWR_32DIRECT(SCC_MGR_GROUP_COUNTER, 0, i);
-			scc_set_bypass_mode(i, bypass_mode);
-		}
-	}
-
-	if (((DYNAMIC_CALIB_STEPS) & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
-		//USER Set VFIFO and LFIFO to instant-on settings in skip calibration mode
-
-		mem_skip_calibrate();
-	} else {
-		for (i = 0; i < NUM_CALIB_REPEAT; i++) {
-
-			//USER Zero all delay chain/phase settings for all groups and all shadow register sets
-			scc_mgr_zero_all();
-
-			run_groups = ~param->skip_groups;
-
-			for (write_group = 0, write_test_bgn = 0;
-			     write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
-			     write_group++, write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
-				// Initialized the group failure
-				group_failed = 0;
-
-				// Mark the group as being attempted for calibration
-
-				BFM_GBL_SET(vfifo_idx, 0);
-				current_run =
-				    run_groups & ((1 << RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
-				run_groups = run_groups >> RW_MGR_NUM_DQS_PER_WRITE_GROUP;
-
-				if (current_run == 0) {
-					continue;
-				}
-
-				IOWR_32DIRECT(SCC_MGR_GROUP_COUNTER, 0, write_group);
-				scc_mgr_zero_group(write_group, write_test_bgn, 0);
-
-				for (read_group =
-				     write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
-				     RW_MGR_MEM_IF_WRITE_DQS_WIDTH, read_test_bgn = 0;
-				     read_group <
-				     (write_group +
-				      1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
-				     RW_MGR_MEM_IF_WRITE_DQS_WIDTH && group_failed == 0;
-				     read_group++, read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
-
-					//USER Calibrate the VFIFO
-					if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_VFIFO)) {
-						if (!rw_mgr_mem_calibrate_vfifo
-						    (read_group, read_test_bgn)) {
-							group_failed = 1;
-
-							if (!
-							    (gbl->
-							     phy_debug_mode_flags &
-							     PHY_DEBUG_SWEEP_ALL_GROUPS)) {
-								return 0;
-							}
-						}
-					}
-				}
-
-				//USER level writes (or align DK with CK for RLDRAMX)
-				if (group_failed == 0) {
-					if ((DDRX || RLDRAMII) && !(ARRIAV || CYCLONEV)) {
-						if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_WLEVEL)) {
-							if (!rw_mgr_mem_calibrate_wlevel
-							    (write_group, write_test_bgn)) {
-								group_failed = 1;
-
-								if (!
-								    (gbl->
-								     phy_debug_mode_flags &
-								     PHY_DEBUG_SWEEP_ALL_GROUPS)) {
-									return 0;
-								}
-							}
-						}
-					}
-				}
-				//USER Calibrate the output side
-				if (group_failed == 0) {
-					for (rank_bgn = 0, sr = 0;
-					     rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
-					     rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
-						sr_failed = 0;
-						if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES)) {
-							if ((STATIC_CALIB_STEPS) &
-							    CALIB_SKIP_DELAY_SWEEPS) {
-								//USER not needed in quick mode!
-							} else {
-								//USER Determine if this set of ranks should be skipped entirely
-								if (!param->skip_shadow_regs[sr]) {
-
-									//USER Select shadow register set
-									select_shadow_regs_for_update
-									    (rank_bgn, write_group,
-									     1);
-
-									if (!rw_mgr_mem_calibrate_writes(rank_bgn, write_group, write_test_bgn)) {
-										sr_failed = 1;
-										if (!
-										    (gbl->
-										     phy_debug_mode_flags
-										     &
-										     PHY_DEBUG_SWEEP_ALL_GROUPS))
-										{
-											return 0;
-										}
-									}
-								}
-							}
-						}
-						if (sr_failed == 0) {
-						} else {
-							group_failed = 1;
-						}
-					}
-				}
-
-				if (group_failed == 0) {
-					for (read_group =
-					     write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
-					     RW_MGR_MEM_IF_WRITE_DQS_WIDTH, read_test_bgn = 0;
-					     read_group <
-					     (write_group +
-					      1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
-					     RW_MGR_MEM_IF_WRITE_DQS_WIDTH && group_failed == 0;
-					     read_group++, read_test_bgn +=
-					     RW_MGR_MEM_DQ_PER_READ_DQS) {
-
-						if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES)) {
-							if (!rw_mgr_mem_calibrate_vfifo_end
-							    (read_group, read_test_bgn)) {
-								group_failed = 1;
-
-								if (!
-								    (gbl->
-								     phy_debug_mode_flags &
-								     PHY_DEBUG_SWEEP_ALL_GROUPS)) {
-									return 0;
-								}
-							}
-						}
-					}
-				}
-
-				if (group_failed == 0) {
-
-#if STATIC_IN_RTL_SIM
-#else
-#endif
-				}
-
-				if (group_failed != 0) {
-					failing_groups++;
-				}
-
-			}
-
-			// USER If there are any failing groups then report the failure
-			if (failing_groups != 0) {
-				return 0;
-			}
-			//USER Calibrate the LFIFO
-			if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
-				//USER If we're skipping groups as part of debug, don't calibrate LFIFO
-				if (param->skip_groups == 0) {
-					if (!rw_mgr_mem_calibrate_lfifo()) {
-						return 0;
-					}
-				}
-			}
-		}
-	}
-
-	//USER Do not remove this line as it makes sure all of our decisions have been applied
-	IOWR_32DIRECT(SCC_MGR_UPD, 0, 0);
-	return 1;
-}
-
-static uint32_t run_mem_calibrate(void)
-{
-
-	uint32_t pass;
-	uint32_t debug_info;
-	uint32_t ctrlcfg = IORD_32DIRECT(CTRL_CONFIG_REG, 0);
-
-	// Initialize the debug status to show that calibration has started.
-	// This should occur before anything else
-	// Reset pass/fail status shown on afi_cal_success/fail
-	IOWR_32DIRECT(PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_RESET);
-	//stop tracking manger
-
-	IOWR_32DIRECT(CTRL_CONFIG_REG, 0, ctrlcfg & 0xFFBFFFFF);
-
-	initialize();
-
-	rw_mgr_mem_initialize();
-
-	pass = mem_calibrate();
-
-	mem_precharge_and_activate();
-
-	//pe_checkout_pattern();
-
-	IOWR_32DIRECT(PHY_MGR_CMD_FIFO_RESET, 0, 0);
-
-	if (pass) {
-#ifdef TEST_SIZE
-		if (!check_test_mem(0)) {
-			gbl->error_stage = 0x92;
-			gbl->error_group = 0x92;
-		}
-#endif
-	}
-
-	//USER Handoff
-
-	//USER Don't return control of the PHY back to AFI when in debug mode
-	if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
-		rw_mgr_mem_handoff();
-
-		// In Hard PHY this is a 2-bit control:
-		// 0: AFI Mux Select
-		// 1: DDIO Mux Select
-		IOWR_32DIRECT(PHY_MGR_MUX_SEL, 0, 0x2);
-	}
-	IOWR_32DIRECT(CTRL_CONFIG_REG, 0, ctrlcfg);
-
-	if (pass) {
-		IPRINT("CALIBRATION PASSED");
-
-		gbl->fom_in /= 2;
-		gbl->fom_out /= 2;
-
-		if (gbl->fom_in > 0xff) {
-			gbl->fom_in = 0xff;
-		}
-
-		if (gbl->fom_out > 0xff) {
-			gbl->fom_out = 0xff;
-		}
-
-		// Update the FOM in the register file
-		debug_info = gbl->fom_in;
-		debug_info |= gbl->fom_out << 8;
-		IOWR_32DIRECT(REG_FILE_FOM, 0, debug_info);
-
-		IOWR_32DIRECT(PHY_MGR_CAL_DEBUG_INFO, 0, debug_info);
-		IOWR_32DIRECT(PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_SUCCESS);
-
-	} else {
-
-		IPRINT("CALIBRATION FAILED");
-
-		debug_info = gbl->error_stage;
-		debug_info |= gbl->error_substage << 8;
-		debug_info |= gbl->error_group << 16;
-
-		IOWR_32DIRECT(REG_FILE_FAILING_STAGE, 0, debug_info);
-		IOWR_32DIRECT(PHY_MGR_CAL_DEBUG_INFO, 0, debug_info);
-		IOWR_32DIRECT(PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_FAIL);
-
-		// Update the failing group/stage in the register file
-		debug_info = gbl->error_stage;
-		debug_info |= gbl->error_substage << 8;
-		debug_info |= gbl->error_group << 16;
-		IOWR_32DIRECT(REG_FILE_FAILING_STAGE, 0, debug_info);
-
-	}
-
-	// Set the debug status to show that calibration has ended.
-	// This should occur after everything else
-	return pass;
-
-}
-
-static void hc_initialize_rom_data(void)
-{
-	uint32_t i;
-
-	for (i = 0; i < inst_rom_init_size; i++) {
-		uint32_t data = inst_rom_init[i];
-		IOWR_32DIRECT(RW_MGR_INST_ROM_WRITE, (i << 2), data);
-	}
-
-	for (i = 0; i < ac_rom_init_size; i++) {
-		uint32_t data = ac_rom_init[i];
-		IOWR_32DIRECT(RW_MGR_AC_ROM_WRITE, (i << 2), data);
-	}
-}
-
-static void initialize_reg_file(void)
-{
-	// Initialize the register file with the correct data
-	IOWR_32DIRECT(REG_FILE_SIGNATURE, 0, REG_FILE_INIT_SEQ_SIGNATURE);
-	IOWR_32DIRECT(REG_FILE_DEBUG_DATA_ADDR, 0, 0);
-	IOWR_32DIRECT(REG_FILE_CUR_STAGE, 0, 0);
-	IOWR_32DIRECT(REG_FILE_FOM, 0, 0);
-	IOWR_32DIRECT(REG_FILE_FAILING_STAGE, 0, 0);
-	IOWR_32DIRECT(REG_FILE_DEBUG1, 0, 0);
-	IOWR_32DIRECT(REG_FILE_DEBUG2, 0, 0);
-}
-
-static void initialize_hps_phy(void)
-{
-	// These may need to be included also:
-	// wrap_back_en (false)
-	// atpg_en (false)
-	// pipelineglobalenable (true)
-
-	uint32_t reg;
-	// Tracking also gets configured here because it's in the same register
-	uint32_t trk_sample_count = 7500;
-	uint32_t trk_long_idle_sample_count = (10 << 16) | 100;	// Format is number of outer loops in the 16 MSB, sample count in 16 LSB.
-
-	reg = 0;
-	reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
-	reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
-	reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
-	reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
-	reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
-	reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
-	// Fix for long latency VFIFO
-	// This field selects the intrinsic latency to RDATA_EN/FULL path. 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
-	reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
-	reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(trk_sample_count);
-	IOWR_32DIRECT(BASE_MMR, SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET, reg);
-
-	reg = 0;
-	reg |=
-	    SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(trk_sample_count >>
-								SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
-	reg |=
-	    SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(trk_long_idle_sample_count);
-	IOWR_32DIRECT(BASE_MMR, SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET, reg);
-
-	reg = 0;
-	reg |=
-	    SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(trk_long_idle_sample_count
-									>>
-									SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
-	IOWR_32DIRECT(BASE_MMR, SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET, reg);
-}
-
-static void initialize_tracking(void)
-{
-	uint32_t concatenated_longidle = 0x0;
-	uint32_t concatenated_delays = 0x0;
-	uint32_t concatenated_rw_addr = 0x0;
-	uint32_t concatenated_refresh = 0x0;
-	uint32_t dtaps_per_ptap;
-	uint32_t tmp_delay;
-
-	// compute usable version of value in case we skip full computation later
-	dtaps_per_ptap = 0;
-	tmp_delay = 0;
-	while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
-		dtaps_per_ptap++;
-		tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
-	}
-	dtaps_per_ptap--;
-
-	concatenated_longidle = concatenated_longidle ^ 10;	//longidle outer loop
-	concatenated_longidle = concatenated_longidle << 16;
-	concatenated_longidle = concatenated_longidle ^ 100;	//longidle sample count
-
-	concatenated_delays = concatenated_delays ^ 243;	// trfc, worst case of 933Mhz 4Gb
-	concatenated_delays = concatenated_delays << 8;
-	concatenated_delays = concatenated_delays ^ 14;	// trcd, worst case
-	concatenated_delays = concatenated_delays << 8;
-	concatenated_delays = concatenated_delays ^ 10;	// vfifo wait
-	concatenated_delays = concatenated_delays << 8;
-	concatenated_delays = concatenated_delays ^ 4;	// mux delay
-
-	concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_IDLE;
-	concatenated_rw_addr = concatenated_rw_addr << 8;
-	concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_ACTIVATE_1;
-	concatenated_rw_addr = concatenated_rw_addr << 8;
-	concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_SGLE_READ;
-	concatenated_rw_addr = concatenated_rw_addr << 8;
-	concatenated_rw_addr = concatenated_rw_addr ^ __RW_MGR_PRECHARGE_ALL;
-
-	concatenated_refresh = concatenated_refresh ^ __RW_MGR_REFRESH_ALL;
-	concatenated_refresh = concatenated_refresh << 24;
-	concatenated_refresh = concatenated_refresh ^ 1000;	// trefi
-
-	// Initialize the register file with the correct data
-	IOWR_32DIRECT(REG_FILE_DTAPS_PER_PTAP, 0, dtaps_per_ptap);
-	IOWR_32DIRECT(REG_FILE_TRK_SAMPLE_COUNT, 0, 7500);
-	IOWR_32DIRECT(REG_FILE_TRK_LONGIDLE, 0, concatenated_longidle);
-	IOWR_32DIRECT(REG_FILE_DELAYS, 0, concatenated_delays);
-	IOWR_32DIRECT(REG_FILE_TRK_RW_MGR_ADDR, 0, concatenated_rw_addr);
-	IOWR_32DIRECT(REG_FILE_TRK_READ_DQS_WIDTH, 0, RW_MGR_MEM_IF_READ_DQS_WIDTH);
-	IOWR_32DIRECT(REG_FILE_TRK_RFSH, 0, concatenated_refresh);
-}
-
-static int socfpga_mem_calibration(void)
-{
-	param_t my_param;
-	gbl_t my_gbl;
-	uint32_t pass;
-	uint32_t i;
-
-	param = &my_param;
-	gbl = &my_gbl;
-
-	// Initialize the debug mode flags
-	gbl->phy_debug_mode_flags = 0;
-	// Set the calibration enabled by default
-	gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
-	// Only enable margining by default if requested
-	// Only sweep all groups (regardless of fail state) by default if requested
-	//Set enabled read test by default
-
-	// Initialize the register file
-	initialize_reg_file();
-
-	// Initialize any PHY CSR
-	initialize_hps_phy();
-
-	scc_mgr_initialize();
-
-	initialize_tracking();
-
-	// Initialize the TCL report. This must occur before any printf
-	// but after the debug mode flags and register file
-
-	// USER Enable all ranks, groups
-	for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++) {
-		param->skip_ranks[i] = 0;
-	}
-	for (i = 0; i < NUM_SHADOW_REGS; ++i) {
-		param->skip_shadow_regs[i] = 0;
-	}
-	param->skip_groups = 0;
-
-	IPRINT("Preparing to start memory calibration");
-
-	DPRINT(1,
-	       "%s%s %s ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu dqs=%lu,%lu dq=%lu dm=%lu "
-	       "ptap_delay=%lu dtap_delay=%lu dtap_dqsen_delay=%lu, dll=%lu",
-	       RDIMM ? "r" : (LRDIMM ? "l" : ""),
-	       DDR2 ? "DDR2" : (DDR3 ? "DDR3"
-				: (QDRII ? "QDRII"
-				   : (RLDRAMII ? "RLDRAMII"
-				      : (RLDRAM3 ? "RLDRAM3" : "??PROTO??")))),
-	       FULL_RATE ? "FR" : (HALF_RATE ? "HR" : (QUARTER_RATE ? "QR" : "??RATE??")),
-	       (long unsigned int)RW_MGR_MEM_NUMBER_OF_RANKS,
-	       (long unsigned int)RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
-	       (long unsigned int)RW_MGR_MEM_DQ_PER_READ_DQS,
-	       (long unsigned int)RW_MGR_MEM_DQ_PER_WRITE_DQS,
-	       (long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
-	       (long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
-	       (long unsigned int)RW_MGR_MEM_IF_READ_DQS_WIDTH,
-	       (long unsigned int)RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
-	       (long unsigned int)RW_MGR_MEM_DATA_WIDTH,
-	       (long unsigned int)RW_MGR_MEM_DATA_MASK_WIDTH,
-	       (long unsigned int)IO_DELAY_PER_OPA_TAP, (long unsigned int)IO_DELAY_PER_DCHAIN_TAP,
-	       (long unsigned int)IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
-	       (long unsigned int)IO_DLL_CHAIN_LENGTH);
-	DPRINT(1,
-	       "max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu io_in_d=%lu io_out1_d=%lu io_out2_d=%lu"
-	       "dqs_in_reserve=%lu dqs_out_reserve=%lu", (long unsigned int)IO_DQS_EN_PHASE_MAX,
-	       (long unsigned int)IO_DQDQS_OUT_PHASE_MAX, (long unsigned int)IO_DQS_EN_DELAY_MAX,
-	       (long unsigned int)IO_DQS_IN_DELAY_MAX, (long unsigned int)IO_IO_IN_DELAY_MAX,
-	       (long unsigned int)IO_IO_OUT1_DELAY_MAX, (long unsigned int)IO_IO_OUT2_DELAY_MAX,
-	       (long unsigned int)IO_DQS_IN_RESERVE, (long unsigned int)IO_DQS_OUT_RESERVE);
-
-	hc_initialize_rom_data();
-
-	//USER update info for sims
-	reg_file_set_stage(CAL_STAGE_NIL);
-	reg_file_set_group(0);
-
-	// Load global needed for those actions that require
-	// some dynamic calibration support
-	dyn_calib_steps = STATIC_CALIB_STEPS;
-
-	// Load global to allow dynamic selection of delay loop settings
-	// based on calibration mode
-	if (!((DYNAMIC_CALIB_STEPS) & CALIB_SKIP_DELAY_LOOPS)) {
-		skip_delay_mask = 0xff;
-	} else {
-		skip_delay_mask = 0x0;
-	}
-
-#ifdef TEST_SIZE
-	if (!check_test_mem(1)) {
-		IOWR_32DIRECT(PHY_MGR_CAL_DEBUG_INFO, 0, 0x9090);
-		IOWR_32DIRECT(PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_FAIL);
-	}
-	write_test_mem();
-	if (!check_test_mem(0)) {
-		IOWR_32DIRECT(PHY_MGR_CAL_DEBUG_INFO, 0, 0x9191);
-		IOWR_32DIRECT(PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_FAIL);
-	}
-#endif
-
-	pass = run_mem_calibrate();
-
-	// EMPTY
-
-	return pass;
-}
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h
deleted file mode 100644
index d2da21d13f..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h
+++ /dev/null
@@ -1,447 +0,0 @@
-#ifndef _SEQUENCER_H_
-#define _SEQUENCER_H_
-
-/*
-* Copyright Altera Corporation (C) 2012-2014. All rights reserved
-*
-* SPDX-License-Identifier:  BSD-3-Clause
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*  * Redistributions of source code must retain the above copyright
-*  notice, this list of conditions and the following disclaimer.
-*  * Redistributions in binary form must reproduce the above copyright
-*  notice, this list of conditions and the following disclaimer in the
-*  documentation and/or other materials provided with the distribution.
-*  * Neither the name of Altera Corporation nor the
-*  names of its contributors may be used to endorse or promote products
-*  derived from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#define ALTERA_ASSERT(condition)
-#define ALTERA_INFO_ASSERT(condition,text)
-
-#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
-#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
-
-#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
-#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
-
-#define RW_MGR_RUN_SINGLE_GROUP BASE_RW_MGR
-#define RW_MGR_RUN_ALL_GROUPS BASE_RW_MGR + 0x0400
-
-#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020)
-
-#define DDR3_MR1_ODT_MASK  0xFFFFFD99
-#define DDR3_MR2_ODT_MASK  0xFFFFF9FF
-#define DDR3_AC_MIRR_MASK  0x020A8
-
-#define RW_MGR_LOAD_CNTR_0 BASE_RW_MGR + 0x0800
-#define RW_MGR_LOAD_CNTR_1 BASE_RW_MGR + 0x0804
-#define RW_MGR_LOAD_CNTR_2 BASE_RW_MGR + 0x0808
-#define RW_MGR_LOAD_CNTR_3 BASE_RW_MGR + 0x080C
-
-#define RW_MGR_LOAD_JUMP_ADD_0 BASE_RW_MGR + 0x0C00
-#define RW_MGR_LOAD_JUMP_ADD_1 BASE_RW_MGR + 0x0C04
-#define RW_MGR_LOAD_JUMP_ADD_2 BASE_RW_MGR + 0x0C08
-#define RW_MGR_LOAD_JUMP_ADD_3 BASE_RW_MGR + 0x0C0C
-
-#define RW_MGR_RESET_READ_DATAPATH BASE_RW_MGR + 0x1000
-#define RW_MGR_SOFT_RESET BASE_RW_MGR + 0x2000
-
-#define RW_MGR_SET_CS_AND_ODT_MASK BASE_RW_MGR + 0x1400
-#define RW_MGR_SET_ACTIVE_RANK BASE_RW_MGR + 0x2400
-
-#define RW_MGR_LOOPBACK_MODE BASE_RW_MGR + 0x0200
-
-#define RW_MGR_ENABLE_REFRESH BASE_RW_MGR + 0x3000
-
-#define RW_MGR_RANK_NONE 0xFF
-#define RW_MGR_RANK_ALL 0x00
-
-#define RW_MGR_ODT_MODE_OFF 0
-#define RW_MGR_ODT_MODE_READ_WRITE 1
-
-#define NUM_CALIB_REPEAT	1
-
-#define NUM_READ_TESTS			7
-#define NUM_READ_PB_TESTS		7
-#define NUM_WRITE_TESTS			15
-#define NUM_WRITE_PB_TESTS		31
-
-#define PASS_ALL_BITS			1
-#define PASS_ONE_BIT			0
-
-/* calibration stages */
-
-#define CAL_STAGE_NIL			0
-#define CAL_STAGE_VFIFO			1
-#define CAL_STAGE_WLEVEL		2
-#define CAL_STAGE_LFIFO			3
-#define CAL_STAGE_WRITES		4
-#define CAL_STAGE_FULLTEST		5
-#define CAL_STAGE_REFRESH		6
-#define CAL_STAGE_CAL_SKIPPED		7
-#define CAL_STAGE_CAL_ABORTED		8
-#define CAL_STAGE_VFIFO_AFTER_WRITES	9
-
-/* calibration substages */
-
-#define CAL_SUBSTAGE_NIL		0
-#define CAL_SUBSTAGE_GUARANTEED_READ	1
-#define CAL_SUBSTAGE_DQS_EN_PHASE	2
-#define CAL_SUBSTAGE_VFIFO_CENTER	3
-#define CAL_SUBSTAGE_WORKING_DELAY	1
-#define CAL_SUBSTAGE_LAST_WORKING_DELAY	2
-#define CAL_SUBSTAGE_WLEVEL_COPY	3
-#define CAL_SUBSTAGE_WRITES_CENTER	1
-#define CAL_SUBSTAGE_READ_LATENCY	1
-#define CAL_SUBSTAGE_REFRESH		1
-
-#define MAX_RANKS			(RW_MGR_MEM_NUMBER_OF_RANKS)
-#define MAX_DQS				(RW_MGR_MEM_IF_WRITE_DQS_WIDTH > RW_MGR_MEM_IF_READ_DQS_WIDTH ? RW_MGR_MEM_IF_WRITE_DQS_WIDTH : RW_MGR_MEM_IF_READ_DQS_WIDTH)
-#define MAX_DQ				(RW_MGR_MEM_DATA_WIDTH)
-#define MAX_DM				(RW_MGR_MEM_DATA_MASK_WIDTH)
-
-/* length of VFIFO, from SW_MACROS */
-#define VFIFO_SIZE			(READ_VALID_FIFO_SIZE)
-
-/* Memory for data transfer between TCL scripts and NIOS.
- *
- * - First word is a command request.
- * - The remaining words are part of the transfer.
- */
-
-/* Define the base address of each manager. */
-
-/* MarkW: how should these base addresses be done for A-V? */
-#define BASE_PTR_MGR 					SEQUENCER_PTR_MGR_INST_BASE
-#define BASE_PHY_MGR 					(0x00088000)
-#define BASE_RW_MGR 					(0x00090000)
-#define BASE_DATA_MGR 					(0x00098000)
-#define BASE_SCC_MGR					SEQUENCER_SCC_MGR_INST_BASE
-#define BASE_REG_FILE					SEQUENCER_REG_FILE_INST_BASE
-#define BASE_TIMER					SEQUENCER_TIMER_INST_BASE
-#define BASE_MMR                                        (0x000C0000)
-#define BASE_TRK_MGR					(0x000D0000)
-
-/* Register file addresses. */
-#define REG_FILE_SIGNATURE				(BASE_REG_FILE + 0x0000)
-#define REG_FILE_DEBUG_DATA_ADDR		(BASE_REG_FILE + 0x0004)
-#define REG_FILE_CUR_STAGE              (BASE_REG_FILE + 0x0008)
-#define REG_FILE_FOM                    (BASE_REG_FILE + 0x000C)
-#define REG_FILE_FAILING_STAGE          (BASE_REG_FILE + 0x0010)
-#define REG_FILE_DEBUG1                 (BASE_REG_FILE + 0x0014)
-#define REG_FILE_DEBUG2                 (BASE_REG_FILE + 0x0018)
-
-#define REG_FILE_DTAPS_PER_PTAP         (BASE_REG_FILE + 0x001C)
-#define REG_FILE_TRK_SAMPLE_COUNT       (BASE_REG_FILE + 0x0020)
-#define REG_FILE_TRK_LONGIDLE           (BASE_REG_FILE + 0x0024)
-#define REG_FILE_DELAYS                 (BASE_REG_FILE + 0x0028)
-#define REG_FILE_TRK_RW_MGR_ADDR        (BASE_REG_FILE + 0x002C)
-#define REG_FILE_TRK_READ_DQS_WIDTH     (BASE_REG_FILE + 0x0030)
-#define REG_FILE_TRK_RFSH               (BASE_REG_FILE + 0x0034)
-#define CTRL_CONFIG_REG			(BASE_MMR      + 0x0000)
-
-/* PHY manager configuration registers. */
-
-#define PHY_MGR_PHY_RLAT				(BASE_PHY_MGR + 0x4000)
-#define PHY_MGR_RESET_MEM_STBL			(BASE_PHY_MGR + 0x4004)
-#define PHY_MGR_MUX_SEL					(BASE_PHY_MGR + 0x4008)
-#define PHY_MGR_CAL_STATUS				(BASE_PHY_MGR + 0x400c)
-#define PHY_MGR_CAL_DEBUG_INFO			(BASE_PHY_MGR + 0x4010)
-#define PHY_MGR_VFIFO_RD_EN_OVRD		(BASE_PHY_MGR + 0x4014)
-#define PHY_MGR_AFI_WLAT				(BASE_PHY_MGR + 0x4018)
-#define PHY_MGR_AFI_RLAT				(BASE_PHY_MGR + 0x401c)
-
-#define PHY_MGR_CAL_RESET				(0)
-#define PHY_MGR_CAL_SUCCESS			(1)
-#define PHY_MGR_CAL_FAIL				(2)
-
-/* PHY manager command addresses. */
-
-#define PHY_MGR_CMD_INC_VFIFO_FR		(BASE_PHY_MGR + 0x0000)
-#define PHY_MGR_CMD_INC_VFIFO_HR		(BASE_PHY_MGR + 0x0004)
-#define PHY_MGR_CMD_INC_VFIFO_HARD_PHY	(BASE_PHY_MGR + 0x0004)
-#define PHY_MGR_CMD_FIFO_RESET			(BASE_PHY_MGR + 0x0008)
-#define PHY_MGR_CMD_INC_VFIFO_FR_HR		(BASE_PHY_MGR + 0x000C)
-#define PHY_MGR_CMD_INC_VFIFO_QR		(BASE_PHY_MGR + 0x0010)
-
-/* PHY manager parameters. */
-
-#define PHY_MGR_MAX_RLAT_WIDTH			(BASE_PHY_MGR + 0x0000)
-#define PHY_MGR_MAX_AFI_WLAT_WIDTH 		(BASE_PHY_MGR + 0x0004)
-#define PHY_MGR_MAX_AFI_RLAT_WIDTH 		(BASE_PHY_MGR + 0x0008)
-#define PHY_MGR_CALIB_SKIP_STEPS		(BASE_PHY_MGR + 0x000c)
-#define PHY_MGR_CALIB_VFIFO_OFFSET		(BASE_PHY_MGR + 0x0010)
-#define PHY_MGR_CALIB_LFIFO_OFFSET		(BASE_PHY_MGR + 0x0014)
-#define PHY_MGR_RDIMM					(BASE_PHY_MGR + 0x0018)
-#define PHY_MGR_MEM_T_WL				(BASE_PHY_MGR + 0x001c)
-#define PHY_MGR_MEM_T_RL				(BASE_PHY_MGR + 0x0020)
-
-/* Data Manager */
-#define DATA_MGR_DRAM_CFG				(BASE_DATA_MGR + 0x0000)
-#define DATA_MGR_MEM_T_WL				(BASE_DATA_MGR + 0x0004)
-#define DATA_MGR_MEM_T_ADD				(BASE_DATA_MGR + 0x0008)
-#define DATA_MGR_MEM_T_RL				(BASE_DATA_MGR + 0x000C)
-#define DATA_MGR_MEM_T_RFC				(BASE_DATA_MGR + 0x0010)
-#define DATA_MGR_MEM_T_REFI				(BASE_DATA_MGR + 0x0014)
-#define DATA_MGR_MEM_T_WR				(BASE_DATA_MGR + 0x0018)
-#define DATA_MGR_MEM_T_MRD				(BASE_DATA_MGR + 0x001C)
-#define DATA_MGR_COL_WIDTH				(BASE_DATA_MGR + 0x0020)
-#define DATA_MGR_ROW_WIDTH				(BASE_DATA_MGR + 0x0024)
-#define DATA_MGR_BANK_WIDTH				(BASE_DATA_MGR + 0x0028)
-#define DATA_MGR_CS_WIDTH				(BASE_DATA_MGR + 0x002C)
-#define DATA_MGR_ITF_WIDTH				(BASE_DATA_MGR + 0x0030)
-#define DATA_MGR_DVC_WIDTH				(BASE_DATA_MGR + 0x0034)
-
-#define MEM_T_WL_ADD DATA_MGR_MEM_T_WL
-#define MEM_T_RL_ADD DATA_MGR_MEM_T_RL
-
-#define CALIB_SKIP_DELAY_LOOPS			(1 << 0)
-#define CALIB_SKIP_ALL_BITS_CHK			(1 << 1)
-#define CALIB_SKIP_DELAY_SWEEPS			(1 << 2)
-#define CALIB_SKIP_VFIFO				(1 << 3)
-#define CALIB_SKIP_LFIFO				(1 << 4)
-#define CALIB_SKIP_WLEVEL				(1 << 5)
-#define CALIB_SKIP_WRITES				(1 << 6)
-#define CALIB_SKIP_FULL_TEST			(1 << 7)
-#define CALIB_SKIP_ALL					(CALIB_SKIP_VFIFO | CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
-#define CALIB_IN_RTL_SIM				(1 << 8)
-
-/* Scan chain manager command addresses */
-
-#define WRITE_SCC_DQS_IN_DELAY(group, delay)	IOWR_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2, delay)
-#define WRITE_SCC_DQS_EN_DELAY(group, delay)	IOWR_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2, (delay) + IO_DQS_EN_DELAY_OFFSET)
-#define WRITE_SCC_DQS_EN_PHASE(group, phase)	IOWR_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2, phase)
-#define WRITE_SCC_DQDQS_OUT_PHASE(group, phase)	IOWR_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2, phase)
-#define WRITE_SCC_OCT_OUT1_DELAY(group, delay)	IOWR_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, (group) << 2, delay)
-#define WRITE_SCC_OCT_OUT2_DELAY(group, delay)
-#define WRITE_SCC_DQS_BYPASS(group, bypass)
-
-#define WRITE_SCC_DQ_OUT1_DELAY(pin, delay)		IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2, delay)
-
-#define WRITE_SCC_DQ_OUT2_DELAY(pin, delay)
-
-#define WRITE_SCC_DQ_IN_DELAY(pin, delay)		IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2, delay)
-
-#define WRITE_SCC_DQ_BYPASS(pin, bypass)
-
-#define WRITE_SCC_RFIFO_MODE(pin, mode)
-
-#define WRITE_SCC_HHP_EXTRAS(value) 	    IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_EXTRAS_OFFSET, value)
-#define WRITE_SCC_HHP_DQSE_MAP(value) 	    IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_DQSE_MAP_OFFSET, value)
-
-#define WRITE_SCC_DQS_IO_OUT1_DELAY(delay)	IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
-
-#define WRITE_SCC_DQS_IO_OUT2_DELAY(delay)
-
-#define WRITE_SCC_DQS_IO_IN_DELAY(delay)	IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
-
-#define WRITE_SCC_DM_IO_OUT1_DELAY(pin, delay)	IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
-
-#define WRITE_SCC_DM_IO_OUT2_DELAY(pin, delay)
-
-#define WRITE_SCC_DM_IO_IN_DELAY(pin, delay)	IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
-
-#define WRITE_SCC_DM_BYPASS(pin, bypass)
-
-#define READ_SCC_DQS_IN_DELAY(group)	IORD_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2)
-#define READ_SCC_DQS_EN_DELAY(group)	(IORD_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2) - IO_DQS_EN_DELAY_OFFSET)
-#define READ_SCC_DQS_EN_PHASE(group)	IORD_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2)
-#define READ_SCC_DQDQS_OUT_PHASE(group)	IORD_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2)
-#define READ_SCC_OCT_OUT1_DELAY(group)	IORD_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, (group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) << 2)
-#define READ_SCC_OCT_OUT2_DELAY(group)	0
-#define READ_SCC_DQS_BYPASS(group) 		0
-#define READ_SCC_DQS_BYPASS(group) 		0
-
-#define READ_SCC_DQ_OUT1_DELAY(pin)		IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2)
-#define READ_SCC_DQ_OUT2_DELAY(pin)		0
-#define READ_SCC_DQ_IN_DELAY(pin)		IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2)
-#define READ_SCC_DQ_BYPASS(pin) 	    0
-#define READ_SCC_RFIFO_MODE(pin) 	    0
-
-#define READ_SCC_DQS_IO_OUT1_DELAY()	IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
-#define READ_SCC_DQS_IO_OUT2_DELAY()	0
-#define READ_SCC_DQS_IO_IN_DELAY()	IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
-
-#define READ_SCC_DM_IO_OUT1_DELAY(pin)	IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
-#define READ_SCC_DM_IO_OUT2_DELAY(pin)	0
-#define READ_SCC_DM_IO_IN_DELAY(pin)	IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
-#define READ_SCC_DM_BYPASS(pin) 	    0
-
-#define SCC_MGR_GROUP_COUNTER			(BASE_SCC_MGR + 0x0000)
-#define SCC_MGR_DQS_IN_DELAY			(BASE_SCC_MGR + 0x0100)
-#define SCC_MGR_DQS_EN_PHASE			(BASE_SCC_MGR + 0x0200)
-#define SCC_MGR_DQS_EN_DELAY			(BASE_SCC_MGR + 0x0300)
-#define SCC_MGR_DQDQS_OUT_PHASE			(BASE_SCC_MGR + 0x0400)
-#define SCC_MGR_OCT_OUT1_DELAY			(BASE_SCC_MGR + 0x0500)
-#define SCC_MGR_IO_OUT1_DELAY			(BASE_SCC_MGR + 0x0700)
-#define SCC_MGR_IO_IN_DELAY				(BASE_SCC_MGR + 0x0900)
-
-/* HHP-HPS-specific versions of some commands */
-#define SCC_MGR_DQS_EN_DELAY_GATE		(BASE_SCC_MGR + 0x0600)
-#define SCC_MGR_IO_OE_DELAY			(BASE_SCC_MGR + 0x0800)
-#define SCC_MGR_HHP_GLOBALS				(BASE_SCC_MGR + 0x0A00)
-#define SCC_MGR_HHP_RFILE				(BASE_SCC_MGR + 0x0B00)
-
-/* HHP-HPS-specific values */
-#define SCC_MGR_HHP_EXTRAS_OFFSET			0
-#define SCC_MGR_HHP_DQSE_MAP_OFFSET			1
-
-#define SCC_MGR_DQS_ENA					(BASE_SCC_MGR + 0x0E00)
-#define SCC_MGR_DQS_IO_ENA				(BASE_SCC_MGR + 0x0E04)
-#define SCC_MGR_DQ_ENA					(BASE_SCC_MGR + 0x0E08)
-#define SCC_MGR_DM_ENA					(BASE_SCC_MGR + 0x0E0C)
-#define SCC_MGR_UPD						(BASE_SCC_MGR + 0x0E20)
-#define SCC_MGR_ACTIVE_RANK				(BASE_SCC_MGR + 0x0E40)
-#define SCC_MGR_AFI_CAL_INIT			(BASE_SCC_MGR + 0x0D00)
-
-// PHY Debug mode flag constants
-#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
-#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
-#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
-#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
-#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
-#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
-
-// Init and Reset delay constants - Only use if defined by sequencer_defines.h,
-// otherwise, revert to defaults
-// Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 200.75us @ 266MHz
-#ifdef TINIT_CNTR0_VAL
-#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
-#else
-#define SEQ_TINIT_CNTR0_VAL 0
-#endif
-
-#ifdef TINIT_CNTR1_VAL
-#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
-#else
-#define SEQ_TINIT_CNTR1_VAL 202
-#endif
-
-#ifdef TINIT_CNTR2_VAL
-#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
-#else
-#define SEQ_TINIT_CNTR2_VAL 131
-#endif
-
-// Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 500.86us @ 266MHz
-#ifdef TRESET_CNTR0_VAL
-#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
-#else
-#define SEQ_TRESET_CNTR0_VAL 2
-#endif
-
-#ifdef TRESET_CNTR1_VAL
-#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
-#else
-#define SEQ_TRESET_CNTR1_VAL 252
-#endif
-
-#ifdef TRESET_CNTR2_VAL
-#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
-#else
-#define SEQ_TRESET_CNTR2_VAL 131
-#endif
-
-/* Bitfield type changes depending on protocol */
-typedef uint32_t t_btfld;
-
-#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
-#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
-
-static const uint32_t inst_rom_init_size;
-static const uint32_t inst_rom_init[];
-static const uint32_t ac_rom_init_size;
-static const uint32_t ac_rom_init[];
-
-/* parameter variable holder */
-
-typedef struct sequencer_param_type {
-	t_btfld dm_correct_mask;
-	t_btfld read_correct_mask;
-	t_btfld read_correct_mask_vg;
-	t_btfld write_correct_mask;
-	t_btfld write_correct_mask_vg;
-
-	/* set a particular entry to 1 if we need to skip a particular rank */
-
-	uint32_t skip_ranks[MAX_RANKS];
-
-	/* set a particular entry to 1 if we need to skip a particular group */
-
-	uint32_t skip_groups;
-
-	/* set a particular entry to 1 if the shadow register (which represents a set of ranks) needs to be skipped */
-
-	uint32_t skip_shadow_regs[NUM_SHADOW_REGS];
-
-} param_t;
-
-/* global variable holder */
-
-typedef struct gbl_type {
-
-	uint32_t phy_debug_mode_flags;
-
-	/* current read latency */
-
-	uint32_t curr_read_lat;
-
-	/* current write latency */
-
-	uint32_t curr_write_lat;
-
-	/* error code */
-
-	uint32_t error_substage;
-	uint32_t error_stage;
-	uint32_t error_group;
-
-	/* figure-of-merit in, figure-of-merit out */
-
-	uint32_t fom_in;
-	uint32_t fom_out;
-
-	//USER Number of RW Mgr NOP cycles between write command and write data
-	uint32_t rw_wl_nop_cycles;
-} gbl_t;
-
-// External global variables
-static gbl_t *gbl;
-static param_t *param;
-
-// External functions
-static uint32_t run_mem_calibrate(void);
-static void rw_mgr_mem_initialize(void);
-static void rw_mgr_mem_dll_lock_wait(void);
-static inline void scc_mgr_set_dq_in_delay(uint32_t write_group, uint32_t dq_in_group,
-					   uint32_t delay);
-static inline void scc_mgr_set_dq_out1_delay(uint32_t write_group, uint32_t dq_in_group,
-					     uint32_t delay);
-static inline void scc_mgr_set_dq_out2_delay(uint32_t write_group, uint32_t dq_in_group,
-					     uint32_t delay);
-static inline void scc_mgr_load_dq(uint32_t dq_in_group);
-static inline void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay);
-static inline void scc_mgr_load_dqs(uint32_t dqs);
-static void scc_mgr_set_group_dqs_io_and_oct_out1_gradual(uint32_t write_group, uint32_t delay);
-static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, uint32_t delay);
-static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, uint32_t phase);
-static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, uint32_t phase);
-static inline void scc_mgr_set_dm_out1_delay(uint32_t write_group, uint32_t dm, uint32_t delay);
-static inline void scc_mgr_set_dm_out2_delay(uint32_t write_group, uint32_t dm, uint32_t delay);
-static inline void scc_mgr_load_dm(uint32_t dm);
-int sdram_calibration(void);
-#endif
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
deleted file mode 100644
index 7cec60937b..0000000000
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef	_SYSTEM_MANAGER_H_
-#define	_SYSTEM_MANAGER_H_
-
-void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num);
-
-/* address */
-#define CONFIG_SYSMGR_ROMCODEGRP_CTRL	(CYCLONE5_SYSMGR_ADDRESS + 0xc0)
-
-/* FPGA interface group */
-#define SYSMGR_FPGAINTF_MODULE		(CYCLONE5_SYSMGR_ADDRESS + 0x28)
-/* EMAC interface selection */
-#define CONFIG_SYSMGR_EMAC_CTRL		(CYCLONE5_SYSMGR_ADDRESS + 0x60)
-
-#define ISWGRP_HANDOFF_AXIBRIDGE	SYSMGR_ISWGRP_HANDOFF0
-#define ISWGRP_HANDOFF_L3REMAP		SYSMGR_ISWGRP_HANDOFF1
-#define ISWGRP_HANDOFF_FPGAINTF		SYSMGR_ISWGRP_HANDOFF2
-#define ISWGRP_HANDOFF_FPGA2SDR		SYSMGR_ISWGRP_HANDOFF3
-
-/* pin mux */
-#define SYSMGR_PINMUXGRP		(CYCLONE5_SYSMGR_ADDRESS + 0x400)
-#define SYSMGR_PINMUXGRP_NANDUSEFPGA	(SYSMGR_PINMUXGRP + 0x2F0)
-#define SYSMGR_PINMUXGRP_EMAC1USEFPGA	(SYSMGR_PINMUXGRP + 0x2F8)
-#define SYSMGR_PINMUXGRP_SDMMCUSEFPGA	(SYSMGR_PINMUXGRP + 0x308)
-#define SYSMGR_PINMUXGRP_EMAC0USEFPGA	(SYSMGR_PINMUXGRP + 0x314)
-#define SYSMGR_PINMUXGRP_SPIM1USEFPGA	(SYSMGR_PINMUXGRP + 0x330)
-#define SYSMGR_PINMUXGRP_SPIM0USEFPGA	(SYSMGR_PINMUXGRP + 0x338)
-
-/* bit fields */
-#define CONFIG_SYSMGR_PINMUXGRP_OFFSET	(0x400)
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX		(1<<0)
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO		(1<<1)
-#define SYSMGR_ECC_OCRAM_EN		(1<<0)
-#define SYSMGR_ECC_OCRAM_SERR		(1<<3)
-#define SYSMGR_ECC_OCRAM_DERR		(1<<4)
-#define SYSMGR_FPGAINTF_USEFPGA		0x1
-#define SYSMGR_FPGAINTF_SPIM0		(1<<0)
-#define SYSMGR_FPGAINTF_SPIM1		(1<<1)
-#define SYSMGR_FPGAINTF_EMAC0		(1<<2)
-#define SYSMGR_FPGAINTF_EMAC1		(1<<3)
-#define SYSMGR_FPGAINTF_NAND		(1<<4)
-#define SYSMGR_FPGAINTF_SDMMC		(1<<5)
-
-#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/debug_ll.h b/arch/arm/mach-socfpga/include/mach/debug_ll.h
deleted file mode 100644
index 3264934e6d..0000000000
--- a/arch/arm/mach-socfpga/include/mach/debug_ll.h
+++ /dev/null
@@ -1,84 +0,0 @@
-#ifndef __MACH_DEBUG_LL_H__
-#define   __MACH_DEBUG_LL_H__
-
-#include <io.h>
-#include <errno.h>
-
-#ifdef CONFIG_DEBUG_LL
-#define UART_BASE	CONFIG_DEBUG_SOCFPGA_UART_PHYS_ADDR
-#endif
-
-#define LSR_THRE	0x20	/* Xmit holding register empty */
-#define LSR_TEMT	0x40
-
-#define LCR_BKSE	0x80	/* Bank select enable */
-#define LCRVAL		0x3
-#define MCRVAL		0x3
-#define FCRVAL		0xc1
-
-#define RBR		0x0
-#define DLL		0x0
-#define IER		0x4
-#define DLM		0x4
-#define FCR		0x8
-#define LCR		0xc
-#define MCR		0x10
-#define LSR		0x14
-#define MSR		0x18
-#define SCR		0x1c
-#define THR		0x30
-
-#ifdef CONFIG_DEBUG_LL
-static inline unsigned int ns16550_calc_divisor(unsigned int clk,
-					 unsigned int baudrate)
-{
-	return (clk / 16 / baudrate);
-}
-
-static inline void INIT_LL(void)
-{
-	unsigned int div = ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK,
-						115200);
-
-	writel(0x00, UART_BASE + IER);
-
-	writel(LCR_BKSE, UART_BASE + LCR);
-	writel(div & 0xff, UART_BASE + DLL);
-	writel((div >> 8) & 0xff, UART_BASE + DLM);
-	writel(LCRVAL, UART_BASE + LCR);
-
-	writel(MCRVAL, UART_BASE + MCR);
-	writel(FCRVAL, UART_BASE + FCR);
-}
-
-#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
-static inline void PUTC_LL(char c)
-{
-	/* Wait until there is space in the FIFO */
-	while ((readl(UART_BASE + LSR) & LSR_THRE) == 0);
-	/* Send the character */
-	writel(c, UART_BASE + THR);
-	/* Wait to make sure it hits the line, in case we die too soon. */
-	while ((readl(UART_BASE + LSR) & LSR_THRE) == 0);
-}
-#else
-static inline void PUTC_LL(char c)
-{
-	/* Wait until there is space in the FIFO */
-	while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
-	/* Send the character */
-	writeb(c, UART_BASE + THR);
-	/* Wait to make sure it hits the line, in case we die too soon. */
-	while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
-}
-#endif
-
-#else
-static inline unsigned int ns16550_calc_divisor(unsigned int clk,
-					 unsigned int baudrate) {
-	return -ENOSYS;
-}
-static inline void INIT_LL(void) {}
-static inline void PUTC_LL(char c) {}
-#endif
-#endif
diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h
deleted file mode 100644
index c8ee73fe2e..0000000000
--- a/arch/arm/mach-socfpga/include/mach/generic.h
+++ /dev/null
@@ -1,104 +0,0 @@
-#ifndef __MACH_SOCFPGA_GENERIC_H
-#define __MACH_SOCFPGA_GENERIC_H
-
-#include <linux/types.h>
-
-struct socfpga_cm_config;
-
-struct socfpga_io_config;
-
-struct arria10_mainpll_cfg;
-struct arria10_perpll_cfg;
-struct arria10_pinmux_cfg;
-
-void arria10_init(struct arria10_mainpll_cfg *mainpll,
-		  struct arria10_perpll_cfg *perpll, uint32_t *pinmux);
-void arria10_finish_io(struct arria10_mainpll_cfg *mainpll,
-		       struct arria10_perpll_cfg *perpll, uint32_t *pinmux);
-
-void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
-			   struct socfpga_io_config *io_config);
-
-#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
-void socfpga_cyclone5_mmc_init(void);
-void socfpga_cyclone5_uart_init(void);
-void socfpga_cyclone5_timer_init(void);
-void socfpga_cyclone5_qspi_init(void);
-#else
-static inline void socfpga_cyclone5_mmc_init(void)
-{
-	return;
-}
-
-static inline void socfpga_cyclone5_uart_init(void)
-{
-	return;
-}
-
-static inline void socfpga_cyclone5_timer_init(void)
-{
-	return;
-}
-
-static inline void socfpga_cyclone5_qspi_init(void)
-{
-	return;
-}
-#endif
-#if defined(CONFIG_ARCH_SOCFPGA_ARRIA10)
-void socfpga_arria10_mmc_init(void);
-void socfpga_arria10_timer_init(void);
-int arria10_prepare_mmc(int barebox, int bitstream);
-void arria10_start_image(int offset);
-int arria10_load_fpga(int offset, int size);
-int arria10_device_init(struct arria10_mainpll_cfg *mainpll,
-			struct arria10_perpll_cfg *perpll,
-			uint32_t *pinmux);
-enum bootsource arria10_get_bootsource(void);
-#else
-static inline void socfpga_arria10_mmc_init(void)
-{
-	return;
-}
-
-static inline void socfpga_arria10_timer_init(void)
-{
-	return;
-}
-static inline void arria10_prepare_mmc(int barebox, int bitstream)
-{
-	return;
-}
-static inline void arria10_start_image(int offset)
-{
-	return;
-}
-static inline int arria10_load_fpga(int offset, int size)
-{
-	return 0;
-}
-static inline int arria10_device_init(struct arria10_mainpll_cfg *mainpll,
-			struct arria10_perpll_cfg *perpll,
-			uint32_t *pinmux)
-{
-	return 0;
-}
-#endif
-
-static inline void __udelay(unsigned us)
-{
-	volatile unsigned int i;
-
-	for (i = 0; i < us * 3; i++);
-}
-
-struct socfpga_barebox_part {
-	unsigned int nor_offset;
-	unsigned int nor_size;
-	const char *mmc_disk;
-};
-
-/* Partition/device for xloader to load main bootloader from */
-extern const struct socfpga_barebox_part *barebox_part;
-
-#endif /* __MACH_SOCFPGA_GENERIC_H */
diff --git a/arch/arm/mach-socfpga/include/mach/lowlevel.h b/arch/arm/mach-socfpga/include/mach/lowlevel.h
deleted file mode 100644
index 8134a02357..0000000000
--- a/arch/arm/mach-socfpga/include/mach/lowlevel.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef __MACH_SOCFPGA_LOWLEVEL_H
-#define __MACH_SOCFPGA_LOWLEVEL_H
-
-#include <common.h>
-#include <linux/sizes.h>
-#include <io.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
-#include <mach/generic.h>
-#include <debug_ll.h>
-#include <asm/cache.h>
-#include <mach/cyclone5-sdram-config.h>
-#include <mach/pll_config.h>
-#include <mach/cyclone5-sequencer.c>
-
-static void __noreturn start_socfpga_c5_common(uint32_t size, void *fdt_blob)
-{
-	void *fdt;
-
-	arm_cpu_lowlevel_init();
-
-	fdt = fdt_blob + get_runtime_offset();
-
-	barebox_arm_entry(0x0, size, fdt);
-}
-
-#define SOCFPGA_C5_ENTRY(name, fdt_name, memory_size)			\
-	ENTRY_FUNCTION(name, r0, r1, r2)				\
-	{								\
-		extern char __dtb_##fdt_name##_start[];			\
-									\
-		start_socfpga_c5_common(memory_size, __dtb_##fdt_name##_start); \
-	}
-
-static noinline void start_socfpga_c5_xload_common(uint32_t size)
-{
-	struct socfpga_io_config io_config;
-	int ret;
-
-	arm_early_mmu_cache_invalidate();
-
-	relocate_to_current_adr();
-	setup_c();
-
-	io_config.pinmux = sys_mgr_init_table;
-	io_config.num_pin = ARRAY_SIZE(sys_mgr_init_table);
-	io_config.iocsr_emac_mixed2 = iocsr_scan_chain0_table;
-	io_config.iocsr_mixed1_flash = iocsr_scan_chain1_table;
-	io_config.iocsr_general = iocsr_scan_chain2_table;
-	io_config.iocsr_ddr = iocsr_scan_chain3_table;
-
-	socfpga_lowlevel_init(&cm_default_cfg, &io_config);
-
-	puts_ll("lowlevel init done\n");
-	puts_ll("SDRAM setup...\n");
-
-	socfpga_sdram_mmr_init();
-
-	puts_ll("SDRAM calibration...\n");
-
-	ret = socfpga_mem_calibration();
-	if (!ret)
-		hang();
-
-	puts_ll("done\n");
-
-	barebox_arm_entry(0x0, size, NULL);
-}
-
-#define SOCFPGA_C5_XLOAD_ENTRY(name, memory_size)				\
-	ENTRY_FUNCTION(name, r0, r1, r2)				\
-	{								\
-		arm_cpu_lowlevel_init();				\
-									\
-		arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K);		\
-									\
-		start_socfpga_c5_xload_common(memory_size);		\
-	}
-
-#endif
diff --git a/arch/arm/mach-socfpga/include/mach/nic301.h b/arch/arm/mach-socfpga/include/mach/nic301.h
deleted file mode 100644
index 54d96c6381..0000000000
--- a/arch/arm/mach-socfpga/include/mach/nic301.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef	_NIC301_H_
-#define	_NIC301_H_
-
-void nic301_slave_ns(void);
-
-#define L3REGS_SECGRP_LWHPS2FPGAREGS_ADDRESS 0x20
-#define L3REGS_SECGRP_HPS2FPGAREGS_ADDRESS 0x90
-#define L3REGS_SECGRP_ACP_ADDRESS 0x94
-#define L3REGS_SECGRP_ROM_ADDRESS 0x98
-#define L3REGS_SECGRP_OCRAM_ADDRESS 0x9c
-#define L3REGS_SECGRP_SDRDATA_ADDRESS 0xa0
-
-#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x00000010
-#define L3REGS_REMAP_HPS2FPGA_MASK 0x00000008
-#define L3REGS_REMAP_OCRAM_MASK 0x00000001
-
-#endif /* _NIC301_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/pll_config.h b/arch/arm/mach-socfpga/include/mach/pll_config.h
deleted file mode 100644
index d6fb60dd24..0000000000
--- a/arch/arm/mach-socfpga/include/mach/pll_config.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef _MACH_SOCFPGA_PRELOADER_PLL_CONFIG_H_
-#define _MACH_SOCFPGA_PRELOADER_PLL_CONFIG_H_
-
-#include <mach/cyclone5-clock-manager.h>
-
-static struct socfpga_cm_config cm_default_cfg = {
-	/* main group */
-	.main_vco_base = (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) |
-		CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER)),
-	.mpuclk = CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
-	.mainclk = CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
-	.dbgatclk = CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
-	.mainqspiclk = CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
-	.mainnandsdmmcclk = CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
-	.cfg2fuser0clk = CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
-	.maindiv = CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
-		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
-		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
-		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
-	.dbgdiv = CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
-		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
-	.tracediv = CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
-	.l4src = CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
-		CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
-	/* peripheral group */
-	.peri_vco_base = (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) |
-		CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) |
-		CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER)),
-	.emac0clk = CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
-	.emac1clk = CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
-	.perqspiclk = CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
-	.pernandsdmmcclk = CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
-	.perbaseclk = CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
-	.s2fuser1clk = CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
-	.perdiv = CLKMGR_PERPLLGRP_DIV_USBCLK_SET(CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
-		CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
-		CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
-		CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
-	.gpiodiv = CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
-	.persrc = CLKMGR_PERPLLGRP_SRC_QSPI_SET(CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
-		CLKMGR_PERPLLGRP_SRC_NAND_SET(CONFIG_HPS_PERPLLGRP_SRC_NAND) |
-		CLKMGR_PERPLLGRP_SRC_SDMMC_SET(CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
-	/* sdram pll group */
-	.sdram_vco_base = (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) |
-		CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) |
-		CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER)),
-	.ddrdqsclk = CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
-		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
-	.ddr2xdqsclk = CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
-		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
-	.ddrdqclk = CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
-		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
-	.s2fuser2clk = CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
-		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
-	/* undocumented alteragrp */
-	.alteragrp_mpu = CONFIG_HPS_ALTERAGRP_MPUCLK,
-	.alteregrp_main = CONFIG_HPS_ALTERAGRP_MAINCLK,
-};
-
-#endif /* _MACH_SOCFPGA_PRELOADER_PLL_CONFIG_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_io.h b/arch/arm/mach-socfpga/include/mach/sdram_io.h
deleted file mode 100644
index ef87bdaf63..0000000000
--- a/arch/arm/mach-socfpga/include/mach/sdram_io.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above copyright
- *      notice, this list of conditions and the following disclaimer in the
- *      documentation and/or other materials provided with the distribution.
- *    * Neither the name of Altera Corporation nor the
- *      names of its contributors may be used to endorse or promote products
- *      derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <mach/cyclone5-sdram.h>
-
-#define MGR_SELECT_MASK   0xf8000
-
-#define APB_BASE_SCC_MGR	SDR_PHYGRP_SCCGRP_ADDRESS
-#define APB_BASE_PHY_MGR	SDR_PHYGRP_PHYMGRGRP_ADDRESS
-#define APB_BASE_RW_MGR		SDR_PHYGRP_RWMGRGRP_ADDRESS
-#define APB_BASE_DATA_MGR	SDR_PHYGRP_DATAMGRGRP_ADDRESS
-#define APB_BASE_REG_FILE	SDR_PHYGRP_REGFILEGRP_ADDRESS
-#define APB_BASE_MMR		SDR_CTRLGRP_ADDRESS
-
-#define __AVL_TO_APB(ADDR) \
-	((((ADDR) & MGR_SELECT_MASK) == (BASE_PHY_MGR))  ? (APB_BASE_PHY_MGR)  | (((ADDR) >> (14-6)) & (0x1<<6))  | ((ADDR) & 0x3f) : \
-	 (((ADDR) & MGR_SELECT_MASK) == (BASE_RW_MGR))   ? (APB_BASE_RW_MGR)   | ((ADDR) & 0x1fff) : \
- 	 (((ADDR) & MGR_SELECT_MASK) == (BASE_DATA_MGR)) ? (APB_BASE_DATA_MGR) | ((ADDR) & 0x7ff) : \
-	 (((ADDR) & MGR_SELECT_MASK) == (BASE_SCC_MGR))  ? (APB_BASE_SCC_MGR)  | ((ADDR) & 0xfff) : \
-	 (((ADDR) & MGR_SELECT_MASK) == (BASE_REG_FILE)) ? (APB_BASE_REG_FILE) | ((ADDR) & 0x7ff) : \
-	 (((ADDR) & MGR_SELECT_MASK) == (BASE_MMR))      ? (APB_BASE_MMR)      | ((ADDR) & 0xfff) : \
-	 -1)
-
-#define IOWR_32DIRECT(BASE, OFFSET, DATA) \
-	write_register(HPS_SDR_BASE, __AVL_TO_APB((uint32_t)((BASE) + (OFFSET))), DATA)
-
-#define IORD_32DIRECT(BASE, OFFSET) \
-	read_register(HPS_SDR_BASE, __AVL_TO_APB((uint32_t)((BASE) + (OFFSET))))
-	#define write_register(BASE, OFFSET, DATA) \
-		writel(DATA, ((BASE) + (OFFSET)))
-	#define read_register(BASE, OFFSET) \
-		readl((BASE) + (OFFSET))
-	#define HPS_SDR_BASE 0xffc20000
diff --git a/arch/arm/mach-socfpga/include/mach/system.h b/arch/arm/mach-socfpga/include/mach/system.h
deleted file mode 100644
index 89527b2c2b..0000000000
--- a/arch/arm/mach-socfpga/include/mach/system.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
-* Copyright Altera Corporation (C) 2012-2014. All rights reserved
-*
-* SPDX-License-Identifier:  BSD-3-Clause
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*  * Redistributions of source code must retain the above copyright
-*  notice, this list of conditions and the following disclaimer.
-*  * Redistributions in binary form must reproduce the above copyright
-*  notice, this list of conditions and the following disclaimer in the
-*  documentation and/or other materials provided with the distribution.
-*  * Neither the name of Altera Corporation nor the
-*  names of its contributors may be used to endorse or promote products
-*  derived from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#define SEQUENCER_DATA_MGR_INST_BASE 0x60000
-#define SEQUENCER_PHY_MGR_INST_BASE 0x48000
-#define SEQUENCER_PTR_MGR_INST_BASE 0x40000
-#define SEQUENCER_RAM_BASE 0x20000
-#define SEQUENCER_ROM_BASE 0x10000
-#define SEQUENCER_RW_MGR_INST_BASE 0x50000
-#define SEQUENCER_SCC_MGR_INST_BASE 0x58000
-#define SEQUENCER_REG_FILE_INST_BASE 0x70000
-#define SEQUENCER_TIMER_INST_BASE 0x78000
diff --git a/arch/arm/mach-socfpga/include/mach/tclrpt.h b/arch/arm/mach-socfpga/include/mach/tclrpt.h
deleted file mode 100644
index 6b332c8754..0000000000
--- a/arch/arm/mach-socfpga/include/mach/tclrpt.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef TCLRPT_H_
-#define TCLRPT_H_
-/*
-* Copyright Altera Corporation (C) 2012-2014. All rights reserved
-*
-* SPDX-License-Identifier:  BSD-3-Clause
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*  * Redistributions of source code must retain the above copyright
-*  notice, this list of conditions and the following disclaimer.
-*  * Redistributions in binary form must reproduce the above copyright
-*  notice, this list of conditions and the following disclaimer in the
-*  documentation and/or other materials provided with the distribution.
-*  * Neither the name of Altera Corporation nor the
-*  names of its contributors may be used to endorse or promote products
-*  derived from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "cyclone5-sequencer.h"
-
-#define TCLRPT_SET(item, value)
-
-// None of the rest of the file should be referenced if ENABLE_TCL_DEBUG is not
-// set (although it's not a problem if it is, but this helps catch errors)
-
-#endif
diff --git a/arch/arm/mach-socfpga/nic301.c b/arch/arm/mach-socfpga/nic301.c
index 7069c6e5b9..9b33a19687 100644
--- a/arch/arm/mach-socfpga/nic301.c
+++ b/arch/arm/mach-socfpga/nic301.c
@@ -17,8 +17,8 @@
 
 #include <common.h>
 #include <io.h>
-#include <mach/nic301.h>
-#include <mach/cyclone5-regs.h>
+#include <mach/socfpga/nic301.h>
+#include <mach/socfpga/cyclone5-regs.h>
 
 /*
  * Convert all slave from secure to non secure
diff --git a/arch/arm/mach-socfpga/xload.c b/arch/arm/mach-socfpga/xload.c
index 5c611ac6e1..5ae4eeb331 100644
--- a/arch/arm/mach-socfpga/xload.c
+++ b/arch/arm/mach-socfpga/xload.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #include <bootsource.h>
 #include <bootstrap.h>
 #include <common.h>
@@ -14,9 +16,9 @@
 #include <linux/stat.h>
 #include <linux/clk.h>
 
-#include <mach/generic.h>
-#include <mach/cyclone5-system-manager.h>
-#include <mach/cyclone5-regs.h>
+#include <mach/socfpga/generic.h>
+#include <mach/socfpga/cyclone5-system-manager.h>
+#include <mach/socfpga/cyclone5-regs.h>
 
 static struct socfpga_barebox_part default_parts[] = {
 	{
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 95d3dc510d..524d282a1d 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -1,18 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_STM32MP
 
 config ARCH_NR_GPIO
 	int
 	default 416
 
+config ARCH_STM32MP13
+	select ARM_PSCI_CLIENT
+	bool
+
 config ARCH_STM32MP157
 	select ARM_PSCI_CLIENT
 	bool
 
+config MACH_STM32MP13XX_DK
+	select ARCH_STM32MP13
+	bool "STM32MP135F DK board"
+
 config MACH_STM32MP15XX_DKX
 	select ARCH_STM32MP157
 	bool "STM32MP157 DK1 and DK2 boards"
 	help
-	  builds a single barebox-stm32mp15xx-dkx.img that can be deployed
+	  builds a single barebox-stm32mp15xx-dkx.stm32 that can be deployed
 	  as SSBL on both the stm32mp157a-dk1 and stm32mp157c-dk2
 
 config MACH_LXA_MC1
@@ -27,8 +37,22 @@ config MACH_STM32MP15X_EV1
 	select ARCH_STM32MP157
 	bool "STM32MP15X-EV1 board"
 	help
-	  builds a single barebox-stm32mp15x-ev1.img that can be deployed
+	  builds a single barebox-stm32mp15x-ev1.stm32 that can be deployed
 	  as SSBL on any STM32MP15X-EVAL platform, like the
 	  STM32MP157C-EV1
 
+config MACH_PROTONIC_STM32MP1
+	select ARCH_STM32MP157
+	bool "Protonic PRTT1L family of boards"
+	help
+	  Builds all barebox-prtt1*.stm32 that can be deployed as SSBL
+	  on the respective PRTT1L family board
+
+config MACH_PHYTEC_PHYCORE_STM32MP1
+	select ARCH_STM32MP157
+	bool "phyCORE-STM32MP1"
+	help
+	  builds an additional barebox-phytec-phycore.stm32
+	  that can be deployed as SSBL on the phyCORE-STM32MP1
+
 endif
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index 8e14b22535..837449150c 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -1,3 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y := init.o
 obj-pbl-y := ddrctrl.o
+pbl-y := bl33-generic.o
 obj-$(CONFIG_BOOTM) += stm32image.o
+obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
diff --git a/arch/arm/mach-stm32mp/bbu.c b/arch/arm/mach-stm32mp/bbu.c
new file mode 100644
index 0000000000..5d6d61db7d
--- /dev/null
+++ b/arch/arm/mach-stm32mp/bbu.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#define pr_fmt(fmt) "stm32mp-bbu: " fmt
+#include <common.h>
+#include <malloc.h>
+#include <bbu.h>
+#include <filetype.h>
+#include <errno.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <linux/sizes.h>
+#include <linux/stat.h>
+#include <ioctl.h>
+#include <mach/stm32mp/bbu.h>
+#include <libfile.h>
+#include <linux/bitfield.h>
+
+#define STM32MP_BBU_IMAGE_HAVE_FSBL		BIT(0)
+#define STM32MP_BBU_IMAGE_HAVE_FIP		BIT(1)
+
+struct stm32mp_bbu_handler {
+	struct bbu_handler handler;
+	loff_t offset;
+};
+
+#define to_stm32mp_bbu_handler(h) container_of(h, struct stm32mp_bbu_handler, h)
+
+static int stm32mp_bbu_gpt_part_update(struct bbu_handler *handler,
+				       const struct bbu_data *data,
+				       const char *part, bool optional)
+{
+	struct bbu_data gpt_data = *data;
+	struct stat st;
+	int ret;
+
+	gpt_data.devicefile = basprintf("%s.%s", gpt_data.devicefile, part);
+	if (!gpt_data.devicefile)
+		return -ENOMEM;
+
+	pr_debug("Attempting %s update\n", gpt_data.devicefile);
+
+	ret = stat(gpt_data.devicefile, &st);
+	if (ret == -ENOENT) {
+		if (optional)
+			return 0;
+		pr_err("Partition %s does not exist\n", gpt_data.devicefile);
+	}
+	if (ret)
+		goto out;
+
+	ret = bbu_std_file_handler(handler, &gpt_data);
+out:
+	kfree_const(gpt_data.devicefile);
+	return ret;
+}
+
+static int stm32mp_bbu_mmc_update(struct bbu_handler *handler,
+				  struct bbu_data *data)
+{
+	struct stm32mp_bbu_handler *priv = to_stm32mp_bbu_handler(handler);
+	int fd, ret;
+	size_t image_len = data->len;
+	const void *buf = data->image;
+	struct stat st;
+
+	pr_debug("Attempting eMMC boot partition update\n");
+
+	ret = bbu_confirm(data);
+	if (ret)
+		return ret;
+
+	fd = open(data->devicefile, O_RDWR);
+	if (fd < 0)
+		return fd;
+
+	ret = fstat(fd, &st);
+	if (ret)
+		goto close;
+
+	if (st.st_size < priv->offset || image_len > st.st_size - priv->offset) {
+		ret = -ENOSPC;
+		goto close;
+	}
+
+	ret = pwrite_full(fd, buf, image_len, priv->offset);
+	if (ret < 0)
+		pr_err("writing to %s failed with %pe\n", data->devicefile, ERR_PTR(ret));
+
+close:
+	close(fd);
+
+	return ret < 0 ? ret : 0;
+}
+
+/*
+ * TF-A compiled with STM32_EMMC_BOOT will first check for FIP image
+ * at offset SZ_256K and then in GPT partition of that name.
+ */
+static int stm32mp_bbu_mmc_fip_handler(struct bbu_handler *handler,
+				       struct bbu_data *data)
+{
+	struct stm32mp_bbu_handler *priv = to_stm32mp_bbu_handler(handler);
+	enum filetype filetype;
+	int image_flags = 0, ret;
+	bool is_emmc = true;
+
+	filetype = file_detect_type(data->image, data->len);
+
+	switch (filetype) {
+	case filetype_stm32_image_fsbl_v1:
+		priv->offset = 0;
+		image_flags |= STM32MP_BBU_IMAGE_HAVE_FSBL;
+		if (data->len > SZ_256K)
+			image_flags |= STM32MP_BBU_IMAGE_HAVE_FIP;
+		break;
+	default:
+		if (!bbu_force(data, "incorrect image type. Expected: %s, got %s",
+				file_type_to_string(filetype_fip),
+				file_type_to_string(filetype)))
+			return -EINVAL;
+		/* If forced assume it's a SSBL */
+		filetype = filetype_fip;
+		fallthrough;
+	case filetype_fip:
+		priv->offset = SZ_256K;
+		image_flags |= STM32MP_BBU_IMAGE_HAVE_FIP;
+		break;
+	}
+
+	pr_debug("Handling %s\n", file_type_to_string(filetype));
+
+	handler->flags |= BBU_HANDLER_FLAG_MMC_BOOT_ACK;
+
+	ret = bbu_mmcboot_handler(handler, data, stm32mp_bbu_mmc_update);
+	if (ret == -ENOENT) {
+		pr_debug("Not an eMMC, falling back to GPT fsbl1 partition\n");
+		is_emmc = false;
+		ret = 0;
+	}
+	if (ret < 0) {
+		pr_debug("eMMC boot update failed: %pe\n", ERR_PTR(ret));
+		return ret;
+	}
+
+	if (!is_emmc && (image_flags & STM32MP_BBU_IMAGE_HAVE_FSBL)) {
+		struct bbu_data fsbl1_data = *data;
+
+		fsbl1_data.len = min_t(size_t, fsbl1_data.len, SZ_256K);
+
+		/*
+		 * BootROM tells TF-A which fsbl slot was booted in r0, but TF-A
+		 * doesn't yet propagate this to us, so for now always flash
+		 * fsbl1
+		 */
+		ret = stm32mp_bbu_gpt_part_update(handler, &fsbl1_data, "fsbl1", false);
+	}
+
+	if (ret == 0 && (image_flags & STM32MP_BBU_IMAGE_HAVE_FIP)) {
+		struct bbu_data fip_data = *data;
+
+		if (image_flags & STM32MP_BBU_IMAGE_HAVE_FSBL) {
+			fip_data.image += SZ_256K;
+			fip_data.len -= SZ_256K;
+		}
+
+		/* No fip GPT partition in eMMC user area is usually ok, as
+		 * that means TF-A is configured to load FIP from eMMC boot part
+		 */
+		ret = stm32mp_bbu_gpt_part_update(handler, &fip_data, "fip", is_emmc);
+	}
+
+	if (ret < 0)
+		pr_debug("eMMC user area update failed: %pe\n", ERR_PTR(ret));
+
+	return ret;
+}
+
+int stm32mp_bbu_mmc_fip_register(const char *name,
+				 const char *devicefile,
+				 unsigned long flags)
+{
+	struct stm32mp_bbu_handler *priv;
+	int ret;
+
+	priv = xzalloc(sizeof(*priv));
+
+	priv->handler.flags = flags;
+	priv->handler.devicefile = devicefile;
+	priv->handler.name = name;
+	priv->handler.handler = stm32mp_bbu_mmc_fip_handler;
+
+	ret = bbu_register_handler(&priv->handler);
+	if (ret)
+		free(priv);
+
+	return ret;
+}
diff --git a/arch/arm/mach-stm32mp/bl33-generic.c b/arch/arm/mach-stm32mp/bl33-generic.c
new file mode 100644
index 0000000000..dda0135a07
--- /dev/null
+++ b/arch/arm/mach-stm32mp/bl33-generic.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <mach/stm32mp/entry.h>
+#include <debug_ll.h>
+
+/*
+ * barebox-dt-2nd.img expects being loaded at an offset, so the
+ * stack can grow down from entry point. The STM32MP TF-A default
+ * is to not have an offset. This stm32mp specific entry points
+ * avoids this issue by setting up a 64 byte stack after end of
+ * barebox and by asking the memory controller about RAM size
+ * instead of parsing it out of the DT.
+ *
+ * When using OP-TEE, ensure CONFIG_OPTEE_SIZE is appopriately set.
+ */
+
+ENTRY_FUNCTION(start_stm32mp_bl33, r0, r1, r2)
+{
+	stm32mp_cpu_lowlevel_init();
+
+	putc_ll('>');
+
+	stm32mp1_barebox_entry((void *)r2);
+}
diff --git a/arch/arm/mach-stm32mp/ddrctrl.c b/arch/arm/mach-stm32mp/ddrctrl.c
index 646fe4401a..f198ee196c 100644
--- a/arch/arm/mach-stm32mp/ddrctrl.c
+++ b/arch/arm/mach-stm32mp/ddrctrl.c
@@ -5,10 +5,10 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/stm32.h>
-#include <mach/ddr_regs.h>
-#include <mach/entry.h>
-#include <mach/stm32.h>
+#include <mach/stm32mp/ddr_regs.h>
+#include <mach/stm32mp/entry.h>
+#include <mach/stm32mp/stm32.h>
+#include <mach/stm32mp/revision.h>
 #include <asm/barebox-arm.h>
 #include <asm/memory.h>
 #include <pbl.h>
@@ -24,12 +24,12 @@
 #define ADDRMAP2_COL_B5		GENMASK(27, 24)
 
 #define ADDRMAP3_COL_B6		GENMASK( 3,  0)
-#define ADDRMAP3_COL_B7		GENMASK(12,  8)
-#define ADDRMAP3_COL_B8		GENMASK(20, 16)
-#define ADDRMAP3_COL_B9		GENMASK(28, 24)
+#define ADDRMAP3_COL_B7		GENMASK(11,  8)
+#define ADDRMAP3_COL_B8		GENMASK(19, 16)
+#define ADDRMAP3_COL_B9		GENMASK(27, 24)
 
-#define ADDRMAP4_COL_B10	GENMASK( 4,  0)
-#define ADDRMAP4_COL_B11	GENMASK(12,  8)
+#define ADDRMAP4_COL_B10	GENMASK( 3,  0)
+#define ADDRMAP4_COL_B11	GENMASK(11,  8)
 
 #define ADDRMAP5_ROW_B0		GENMASK( 3,  0)
 #define ADDRMAP5_ROW_B1		GENMASK(11,  8)
@@ -62,7 +62,8 @@ enum ddrctrl_buswidth {
 };
 
 static unsigned long ddrctrl_addrmap_ramsize(struct stm32mp1_ddrctl __iomem *d,
-					     enum ddrctrl_buswidth buswidth)
+					     enum ddrctrl_buswidth buswidth,
+					     unsigned nb_bytes)
 {
 	unsigned banks = 3, cols = 12, rows = 16;
 	u32 reg;
@@ -99,53 +100,62 @@ static unsigned long ddrctrl_addrmap_ramsize(struct stm32mp1_ddrctl __iomem *d,
 	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B13)) rows--;
 	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B12)) rows--;
 
-	return memory_sdram_size(cols, rows, BIT(banks), 4 / BIT(buswidth));
+	return memory_sdram_size(cols, rows, BIT(banks),
+				 DIV_ROUND_UP(nb_bytes, BIT(buswidth)));
 }
 
-static inline unsigned ddrctrl_ramsize(void __iomem *base)
+static inline unsigned ddrctrl_ramsize(void __iomem *base, unsigned nb_bytes)
 {
 	struct stm32mp1_ddrctl __iomem *ddrctl = base;
 	unsigned buswidth = readl(&ddrctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
 	buswidth >>= DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT;
 
-	return ddrctrl_addrmap_ramsize(ddrctl, buswidth);
+	return ddrctrl_addrmap_ramsize(ddrctl, buswidth, nb_bytes);
 }
 
 static inline unsigned stm32mp1_ddrctrl_ramsize(void)
 {
-	return ddrctrl_ramsize(IOMEM(STM32_DDRCTL_BASE));
+	u32 nb_bytes = 4;
+
+	if (cpu_stm32_is_stm32mp13())
+		nb_bytes /= 2;
+
+	return ddrctrl_ramsize(IOMEM(STM32_DDRCTL_BASE), nb_bytes);
 }
 
-void __noreturn stm32mp1_barebox_entry(void *boarddata)
+void __noreturn __prereloc stm32mp1_barebox_entry(void *boarddata)
 {
 	barebox_arm_entry(STM32_DDR_BASE, stm32mp1_ddrctrl_ramsize(), boarddata);
 }
 
 
-static int stm32mp1_ddr_probe(struct device_d *dev)
+static int stm32mp1_ddr_probe(struct device *dev)
 {
 	struct resource *iores;
 	void __iomem *base;
+	unsigned long nb_bytes;
 
 	iores = dev_request_mem_resource(dev, 0);
 	if (IS_ERR(iores))
 		return PTR_ERR(iores);
 	base = IOMEM(iores->start);
 
-	arm_add_mem_device("ram0", STM32_DDR_BASE, ddrctrl_ramsize(base));
+	nb_bytes = (unsigned long)device_get_match_data(dev);
 
-	return 0;
+	return arm_add_mem_device("ram0", STM32_DDR_BASE,
+				  ddrctrl_ramsize(base, nb_bytes));
 }
 
 static __maybe_unused struct of_device_id stm32mp1_ddr_dt_ids[] = {
-	{ .compatible = "st,stm32mp1-ddr" },
+	{ .compatible = "st,stm32mp1-ddr", .data = (void *)4 },
+	{ .compatible = "st,stm32mp13-ddr", .data = (void *)2 },
 	{ /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, stm32mp1_ddr_dt_ids);
 
-static struct driver_d stm32mp1_ddr_driver = {
+static struct driver stm32mp1_ddr_driver = {
 	.name   = "stm32mp1-ddr",
 	.probe  = stm32mp1_ddr_probe,
 	.of_compatible = DRV_OF_COMPAT(stm32mp1_ddr_dt_ids),
 };
-
 mem_platform_driver(stm32mp1_ddr_driver);
diff --git a/arch/arm/mach-stm32mp/include/mach/bbu.h b/arch/arm/mach-stm32mp/include/mach/bbu.h
deleted file mode 100644
index 8b9504400e..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/bbu.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef MACH_STM32MP_BBU_H_
-#define MACH_STM32MP_BBU_H_
-
-#include <bbu.h>
-
-static inline int stm32mp_bbu_mmc_register_handler(const char *name,
-						   const char *devicefile,
-						   unsigned long flags)
-{
-	return bbu_register_std_file_update(name, flags, devicefile,
-					    filetype_stm32_image_v1);
-}
-
-#endif /* MACH_STM32MP_BBU_H_ */
diff --git a/arch/arm/mach-stm32mp/include/mach/bootsource.h b/arch/arm/mach-stm32mp/include/mach/bootsource.h
deleted file mode 100644
index 5750dc1448..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/bootsource.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-#ifndef __MACH_STM32_BOOTSOURCE_H__
-#define __MACH_STM32_BOOTSOURCE_H__
-
-enum stm32mp_boot_device {
-	STM32MP_BOOT_FLASH_SD		= 0x10, /* .. 0x13 */
-	STM32MP_BOOT_FLASH_EMMC		= 0x20, /* .. 0x23 */
-	STM32MP_BOOT_FLASH_NAND		= 0x30,
-	STM32MP_BOOT_FLASH_NAND_FMC	= 0x31,
-	STM32MP_BOOT_FLASH_NOR		= 0x40,
-	STM32MP_BOOT_FLASH_NOR_QSPI	= 0x41,
-	STM32MP_BOOT_SERIAL_UART	= 0x50, /* .. 0x58 */
-	STM32MP_BOOT_SERIAL_USB		= 0x60,
-	STM32MP_BOOT_SERIAL_USB_OTG	= 0x62,
-};
-
-#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h
deleted file mode 100644
index d3cb91b1fd..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/bsec.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef __MACH_STM32_BSEC_H__
-#define __MACH_STM32_BSEC_H__
-
-#include <mach/smc.h>
-
-/* Return status */
-enum bsec_smc {
-	BSEC_SMC_OK		= 0,
-	BSEC_SMC_ERROR		= -1,
-	BSEC_SMC_DISTURBED	= -2,
-	BSEC_SMC_INVALID_PARAM	= -3,
-	BSEC_SMC_PROG_FAIL	= -4,
-	BSEC_SMC_LOCK_FAIL	= -5,
-	BSEC_SMC_WRITE_FAIL	= -6,
-	BSEC_SMC_SHADOW_FAIL	= -7,
-	BSEC_SMC_TIMEOUT	= -8,
-};
-
-/* Service for BSEC */
-enum bsec_op {
-	BSEC_SMC_READ_SHADOW	= 1,
-	BSEC_SMC_PROG_OTP	= 2,
-	BSEC_SMC_WRITE_SHADOW	= 3,
-	BSEC_SMC_READ_OTP	= 4,
-	BSEC_SMC_READ_ALL	= 5,
-	BSEC_SMC_WRITE_ALL	= 6,
-};
-
-static inline enum bsec_smc bsec_read_field(unsigned field, unsigned *val)
-{
-	return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_READ_SHADOW,
-			   field, 0, val);
-}
-
-static inline enum bsec_smc bsec_write_field(unsigned field, unsigned val)
-{
-	return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_WRITE_SHADOW,
-			   field, val, NULL);
-}
-
-#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/ddr_regs.h b/arch/arm/mach-stm32mp/include/mach/ddr_regs.h
deleted file mode 100644
index 7d6a5b8be4..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/ddr_regs.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-#ifndef _STM32MP1_DDR_REGS_H
-#define _STM32MP1_DDR_REGS_H
-
-/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
-struct stm32mp1_ddrctl {
-	u32 mstr ;		/* 0x0 Master*/
-	u32 stat;		/* 0x4 Operating Mode Status*/
-	u8 reserved008[0x10 - 0x8];
-	u32 mrctrl0;		/* 0x10 Control 0.*/
-	u32 mrctrl1;		/* 0x14 Control 1*/
-	u32 mrstat;		/* 0x18 Status*/
-	u32 reserved01c;	/* 0x1c */
-	u32 derateen;		/* 0x20 Temperature Derate Enable*/
-	u32 derateint;		/* 0x24 Temperature Derate Interval*/
-	u8 reserved028[0x30 - 0x28];
-	u32 pwrctl;		/* 0x30 Low Power Control*/
-	u32 pwrtmg;		/* 0x34 Low Power Timing*/
-	u32 hwlpctl;		/* 0x38 Hardware Low Power Control*/
-	u8 reserved03c[0x50 - 0x3C];
-	u32 rfshctl0;		/* 0x50 Refresh Control 0*/
-	u32 reserved054;	/* 0x54 Refresh Control 1*/
-	u32 reserved058;	/* 0x58 Refresh Control 2*/
-	u32 reserved05C;
-	u32 rfshctl3;		/* 0x60 Refresh Control 0*/
-	u32 rfshtmg;		/* 0x64 Refresh Timing*/
-	u8 reserved068[0xc0 - 0x68];
-	u32 crcparctl0;		/* 0xc0 CRC Parity Control0*/
-	u32 reserved0c4;	/* 0xc4 CRC Parity Control1*/
-	u32 reserved0c8;	/* 0xc8 CRC Parity Control2*/
-	u32 crcparstat;		/* 0xcc CRC Parity Status*/
-	u32 init0;		/* 0xd0 SDRAM Initialization 0*/
-	u32 init1;		/* 0xd4 SDRAM Initialization 1*/
-	u32 init2;		/* 0xd8 SDRAM Initialization 2*/
-	u32 init3;		/* 0xdc SDRAM Initialization 3*/
-	u32 init4;		/* 0xe0 SDRAM Initialization 4*/
-	u32 init5;		/* 0xe4 SDRAM Initialization 5*/
-	u32 reserved0e8;
-	u32 reserved0ec;
-	u32 dimmctl;		/* 0xf0 DIMM Control*/
-	u8 reserved0f4[0x100 - 0xf4];
-	u32 dramtmg0;		/* 0x100 SDRAM Timing 0*/
-	u32 dramtmg1;		/* 0x104 SDRAM Timing 1*/
-	u32 dramtmg2;		/* 0x108 SDRAM Timing 2*/
-	u32 dramtmg3;		/* 0x10c SDRAM Timing 3*/
-	u32 dramtmg4;		/* 0x110 SDRAM Timing 4*/
-	u32 dramtmg5;		/* 0x114 SDRAM Timing 5*/
-	u32 dramtmg6;		/* 0x118 SDRAM Timing 6*/
-	u32 dramtmg7;		/* 0x11c SDRAM Timing 7*/
-	u32 dramtmg8;		/* 0x120 SDRAM Timing 8*/
-	u8 reserved124[0x138 - 0x124];
-	u32 dramtmg14;		/* 0x138 SDRAM Timing 14*/
-	u32 dramtmg15;		/* 0x13C SDRAM Timing 15*/
-	u8 reserved140[0x180 - 0x140];
-	u32 zqctl0;		/* 0x180 ZQ Control 0*/
-	u32 zqctl1;		/* 0x184 ZQ Control 1*/
-	u32 zqctl2;		/* 0x188 ZQ Control 2*/
-	u32 zqstat;		/* 0x18c ZQ Status*/
-	u32 dfitmg0;		/* 0x190 DFI Timing 0*/
-	u32 dfitmg1;		/* 0x194 DFI Timing 1*/
-	u32 dfilpcfg0;		/* 0x198 DFI Low Power Configuration 0*/
-	u32 reserved19c;
-	u32 dfiupd0;		/* 0x1a0 DFI Update 0*/
-	u32 dfiupd1;		/* 0x1a4 DFI Update 1*/
-	u32 dfiupd2;		/* 0x1a8 DFI Update 2*/
-	u32 reserved1ac;
-	u32 dfimisc;		/* 0x1b0 DFI Miscellaneous Control*/
-	u8 reserved1b4[0x1bc - 0x1b4];
-	u32 dfistat;		/* 0x1bc DFI Miscellaneous Control*/
-	u8 reserved1c0[0x1c4 - 0x1c0];
-	u32 dfiphymstr;		/* 0x1c4 DFI PHY Master interface*/
-	u8 reserved1c8[0x204 - 0x1c8];
-	u32 addrmap1;		/* 0x204 Address Map 1*/
-	u32 addrmap2;		/* 0x208 Address Map 2*/
-	u32 addrmap3;		/* 0x20c Address Map 3*/
-	u32 addrmap4;		/* 0x210 Address Map 4*/
-	u32 addrmap5;		/* 0x214 Address Map 5*/
-	u32 addrmap6;		/* 0x218 Address Map 6*/
-	u8 reserved21c[0x224 - 0x21c];
-	u32 addrmap9;		/* 0x224 Address Map 9*/
-	u32 addrmap10;		/* 0x228 Address Map 10*/
-	u32 addrmap11;		/* 0x22C Address Map 11*/
-	u8 reserved230[0x240 - 0x230];
-	u32 odtcfg;		/* 0x240 ODT Configuration*/
-	u32 odtmap;		/* 0x244 ODT/Rank Map*/
-	u8 reserved248[0x250 - 0x248];
-	u32 sched;		/* 0x250 Scheduler Control*/
-	u32 sched1;		/* 0x254 Scheduler Control 1*/
-	u32 reserved258;
-	u32 perfhpr1;		/* 0x25c High Priority Read CAM 1*/
-	u32 reserved260;
-	u32 perflpr1;		/* 0x264 Low Priority Read CAM 1*/
-	u32 reserved268;
-	u32 perfwr1;		/* 0x26c Write CAM 1*/
-	u8 reserved27c[0x300 - 0x270];
-	u32 dbg0;		/* 0x300 Debug 0*/
-	u32 dbg1;		/* 0x304 Debug 1*/
-	u32 dbgcam;		/* 0x308 CAM Debug*/
-	u32 dbgcmd;		/* 0x30c Command Debug*/
-	u32 dbgstat;		/* 0x310 Status Debug*/
-	u8 reserved314[0x320 - 0x314];
-	u32 swctl;		/* 0x320 Software Programming Control Enable*/
-	u32 swstat;		/* 0x324 Software Programming Control Status*/
-	u8 reserved328[0x36c - 0x328];
-	u32 poisoncfg;		/* 0x36c AXI Poison Configuration Register*/
-	u32 poisonstat;		/* 0x370 AXI Poison Status Register*/
-	u8 reserved374[0x3fc - 0x374];
-
-	/* Multi Port registers */
-	u32 pstat;		/* 0x3fc Port Status*/
-	u32 pccfg;		/* 0x400 Port Common Configuration*/
-
-	/* PORT 0 */
-	u32 pcfgr_0;		/* 0x404 Configuration Read*/
-	u32 pcfgw_0;		/* 0x408 Configuration Write*/
-	u8 reserved40c[0x490 - 0x40c];
-	u32 pctrl_0;		/* 0x490 Port Control Register */
-	u32 pcfgqos0_0;		/* 0x494 Read QoS Configuration 0*/
-	u32 pcfgqos1_0;		/* 0x498 Read QoS Configuration 1*/
-	u32 pcfgwqos0_0;	/* 0x49c Write QoS Configuration 0*/
-	u32 pcfgwqos1_0;	/* 0x4a0 Write QoS Configuration 1*/
-	u8 reserved4a4[0x4b4 - 0x4a4];
-
-	/* PORT 1 */
-	u32 pcfgr_1;		/* 0x4b4 Configuration Read*/
-	u32 pcfgw_1;		/* 0x4b8 Configuration Write*/
-	u8 reserved4bc[0x540 - 0x4bc];
-	u32 pctrl_1;		/* 0x540 Port 2 Control Register */
-	u32 pcfgqos0_1;		/* 0x544 Read QoS Configuration 0*/
-	u32 pcfgqos1_1;		/* 0x548 Read QoS Configuration 1*/
-	u32 pcfgwqos0_1;	/* 0x54c Write QoS Configuration 0*/
-	u32 pcfgwqos1_1;	/* 0x550 Write QoS Configuration 1*/
-};
-
-/* DDR Physical Interface Control (DDRPHYC) registers*/
-struct stm32mp1_ddrphy {
-	u32 ridr;		/* 0x00 R Revision Identification*/
-	u32 pir;		/* 0x04 R/W PHY Initialization*/
-	u32 pgcr;		/* 0x08 R/W PHY General Configuration*/
-	u32 pgsr;		/* 0x0C PHY General Status*/
-	u32 dllgcr;		/* 0x10 R/W DLL General Control*/
-	u32 acdllcr;		/* 0x14 R/W AC DLL Control*/
-	u32 ptr0;		/* 0x18 R/W PHY Timing 0*/
-	u32 ptr1;		/* 0x1C R/W PHY Timing 1*/
-	u32 ptr2;		/* 0x20 R/W PHY Timing 2*/
-	u32 aciocr;		/* 0x24 AC I/O Configuration*/
-	u32 dxccr;		/* 0x28 DATX8 Common Configuration*/
-	u32 dsgcr;		/* 0x2C DDR System General Configuration*/
-	u32 dcr;		/* 0x30 DRAM Configuration*/
-	u32 dtpr0;		/* 0x34 DRAM Timing Parameters0*/
-	u32 dtpr1;		/* 0x38 DRAM Timing Parameters1*/
-	u32 dtpr2;		/* 0x3C DRAM Timing Parameters2*/
-	u32 mr0;		/* 0x40 Mode 0*/
-	u32 mr1;		/* 0x44 Mode 1*/
-	u32 mr2;		/* 0x48 Mode 2*/
-	u32 mr3;		/* 0x4C Mode 3*/
-	u32 odtcr;		/* 0x50 ODT Configuration*/
-	u32 dtar;		/* 0x54 data training address*/
-	u32 dtdr0;		/* 0x58 */
-	u32 dtdr1;		/* 0x5c */
-	u8 res1[0x0c0 - 0x060];	/* 0x60 */
-	u32 dcuar;		/* 0xc0 Address*/
-	u32 dcudr;		/* 0xc4 DCU Data*/
-	u32 dcurr;		/* 0xc8 DCU Run*/
-	u32 dculr;		/* 0xcc DCU Loop*/
-	u32 dcugcr;		/* 0xd0 DCU General Configuration*/
-	u32 dcutpr;		/* 0xd4 DCU Timing Parameters */
-	u32 dcusr0;		/* 0xd8 DCU Status 0*/
-	u32 dcusr1;		/* 0xdc DCU Status 1*/
-	u8 res2[0x100 - 0xe0];	/* 0xe0 */
-	u32 bistrr;		/* 0x100 BIST Run*/
-	u32 bistmskr0;		/* 0x104 BIST Mask 0*/
-	u32 bistmskr1;		/* 0x108 BIST Mask 0*/
-	u32 bistwcr;		/* 0x10c BIST Word Count*/
-	u32 bistlsr;		/* 0x110 BIST LFSR Seed*/
-	u32 bistar0;		/* 0x114 BIST Address 0*/
-	u32 bistar1;		/* 0x118 BIST Address 1*/
-	u32 bistar2;		/* 0x11c BIST Address 2*/
-	u32 bistupdr;		/* 0x120 BIST User Data Pattern*/
-	u32 bistgsr;		/* 0x124 BIST General Status*/
-	u32 bistwer;		/* 0x128 BIST Word Error*/
-	u32 bistber0;		/* 0x12c BIST Bit Error 0*/
-	u32 bistber1;		/* 0x130 BIST Bit Error 1*/
-	u32 bistber2;		/* 0x134 BIST Bit Error 2*/
-	u32 bistwcsr;		/* 0x138 BIST Word Count Status*/
-	u32 bistfwr0;		/* 0x13c BIST Fail Word 0*/
-	u32 bistfwr1;		/* 0x140 BIST Fail Word 1*/
-	u8 res3[0x178 - 0x144];	/* 0x144 */
-	u32 gpr0;		/* 0x178 General Purpose 0 (GPR0)*/
-	u32 gpr1;		/* 0x17C General Purpose 1 (GPR1)*/
-	u32 zq0cr0;		/* 0x180 zq 0 control 0 */
-	u32 zq0cr1;		/* 0x184 zq 0 control 1 */
-	u32 zq0sr0;		/* 0x188 zq 0 status 0 */
-	u32 zq0sr1;		/* 0x18C zq 0 status 1 */
-	u8 res4[0x1C0 - 0x190];	/* 0x190 */
-	u32 dx0gcr;		/* 0x1c0 Byte lane 0 General Configuration*/
-	u32 dx0gsr0;		/* 0x1c4 Byte lane 0 General Status 0*/
-	u32 dx0gsr1;		/* 0x1c8 Byte lane 0 General Status 1*/
-	u32 dx0dllcr;		/* 0x1cc Byte lane 0 DLL Control*/
-	u32 dx0dqtr;		/* 0x1d0 Byte lane 0 DQ Timing*/
-	u32 dx0dqstr;		/* 0x1d4 Byte lane 0 DQS Timing*/
-	u8 res5[0x200 - 0x1d8];	/* 0x1d8 */
-	u32 dx1gcr;		/* 0x200 Byte lane 1 General Configuration*/
-	u32 dx1gsr0;		/* 0x204 Byte lane 1 General Status 0*/
-	u32 dx1gsr1;		/* 0x208 Byte lane 1 General Status 1*/
-	u32 dx1dllcr;		/* 0x20c Byte lane 1 DLL Control*/
-	u32 dx1dqtr;		/* 0x210 Byte lane 1 DQ Timing*/
-	u32 dx1dqstr;		/* 0x214 Byte lane 1 QS Timing*/
-	u8 res6[0x240 - 0x218];	/* 0x218 */
-	u32 dx2gcr;		/* 0x240 Byte lane 2 General Configuration*/
-	u32 dx2gsr0;		/* 0x244 Byte lane 2 General Status 0*/
-	u32 dx2gsr1;		/* 0x248 Byte lane 2 General Status 1*/
-	u32 dx2dllcr;		/* 0x24c Byte lane 2 DLL Control*/
-	u32 dx2dqtr;		/* 0x250 Byte lane 2 DQ Timing*/
-	u32 dx2dqstr;		/* 0x254 Byte lane 2 QS Timing*/
-	u8 res7[0x280 - 0x258];	/* 0x258 */
-	u32 dx3gcr;		/* 0x280 Byte lane 3 General Configuration*/
-	u32 dx3gsr0;		/* 0x284 Byte lane 3 General Status 0*/
-	u32 dx3gsr1;		/* 0x288 Byte lane 3 General Status 1*/
-	u32 dx3dllcr;		/* 0x28c Byte lane 3 DLL Control*/
-	u32 dx3dqtr;		/* 0x290 Byte lane 3 DQ Timing*/
-	u32 dx3dqstr;		/* 0x294 Byte lane 3 QS Timing*/
-};
-
-#define DXN(phy, offset, byte)	((u32)(phy) + (offset) + ((u32)(byte) * 0x40))
-#define DXNGCR(phy, byte)	DXN(phy, 0x1c0, byte)
-#define DXNDLLCR(phy, byte)	DXN(phy, 0x1cc, byte)
-#define DXNDQTR(phy, byte)	DXN(phy, 0x1d0, byte)
-#define DXNDQSTR(phy, byte)	DXN(phy, 0x1d4, byte)
-
-/* DDRCTRL REGISTERS */
-#define DDRCTRL_MSTR_DDR3			BIT(0)
-#define DDRCTRL_MSTR_LPDDR2			BIT(2)
-#define DDRCTRL_MSTR_LPDDR3			BIT(3)
-#define DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT	12
-#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK	GENMASK(13, 12)
-#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL	(0 << 12)
-#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF	(1 << 12)
-#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER	(2 << 12)
-#define DDRCTRL_MSTR_DLL_OFF_MODE		BIT(15)
-
-#define DDRCTRL_STAT_OPERATING_MODE_MASK	GENMASK(2, 0)
-#define DDRCTRL_STAT_OPERATING_MODE_NORMAL	1
-#define DDRCTRL_STAT_OPERATING_MODE_SR		3
-#define DDRCTRL_STAT_SELFREF_TYPE_MASK		GENMASK(5, 4)
-#define DDRCTRL_STAT_SELFREF_TYPE_ASR		(3 << 4)
-#define DDRCTRL_STAT_SELFREF_TYPE_SR		(2 << 4)
-
-#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE		0
-/* only one rank supported */
-#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT		4
-#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
-		(0x1 << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
-#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT		12
-#define DDRCTRL_MRCTRL0_MR_ADDR_MASK		GENMASK(15, 12)
-#define DDRCTRL_MRCTRL0_MR_WR			BIT(31)
-
-#define DDRCTRL_MRSTAT_MR_WR_BUSY		BIT(0)
-
-#define DDRCTRL_PWRCTL_POWERDOWN_EN		BIT(1)
-#define DDRCTRL_PWRCTL_SELFREF_SW		BIT(5)
-
-#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH	BIT(0)
-
-#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK	GENMASK(27, 16)
-#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT	16
-
-#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK	(0xC0000000)
-#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL	(BIT(30))
-
-#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN	BIT(0)
-
-#define DDRCTRL_DBG1_DIS_HIF			BIT(1)
-
-#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY	BIT(29)
-#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY	BIT(28)
-#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY		BIT(26)
-#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH		GENMASK(12, 8)
-#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH		GENMASK(4, 0)
-#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
-		(DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
-		 DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
-#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
-		(DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
-		 DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
-		 DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
-
-#define DDRCTRL_DBGCMD_RANK0_REFRESH		BIT(0)
-
-#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY	BIT(0)
-
-#define DDRCTRL_SWCTL_SW_DONE			BIT(0)
-
-#define DDRCTRL_SWSTAT_SW_DONE_ACK		BIT(0)
-
-#define DDRCTRL_PCTRL_N_PORT_EN			BIT(0)
-
-/* DDRPHYC registers */
-#define DDRPHYC_PIR_INIT			BIT(0)
-#define DDRPHYC_PIR_DLLSRST			BIT(1)
-#define DDRPHYC_PIR_DLLLOCK			BIT(2)
-#define DDRPHYC_PIR_ZCAL			BIT(3)
-#define DDRPHYC_PIR_ITMSRST			BIT(4)
-#define DDRPHYC_PIR_DRAMRST			BIT(5)
-#define DDRPHYC_PIR_DRAMINIT			BIT(6)
-#define DDRPHYC_PIR_QSTRN			BIT(7)
-#define DDRPHYC_PIR_ICPC			BIT(16)
-#define DDRPHYC_PIR_ZCALBYP			BIT(30)
-#define DDRPHYC_PIR_INITSTEPS_MASK		GENMASK(31, 7)
-
-#define DDRPHYC_PGCR_DFTCMP			BIT(2)
-#define DDRPHYC_PGCR_PDDISDX			BIT(24)
-#define DDRPHYC_PGCR_RFSHDT_MASK		GENMASK(28, 25)
-
-#define DDRPHYC_PGSR_IDONE			BIT(0)
-#define DDRPHYC_PGSR_DTERR			BIT(5)
-#define DDRPHYC_PGSR_DTIERR			BIT(6)
-#define DDRPHYC_PGSR_DFTERR			BIT(7)
-#define DDRPHYC_PGSR_RVERR			BIT(8)
-#define DDRPHYC_PGSR_RVEIRR			BIT(9)
-
-#define DDRPHYC_DLLGCR_BPS200			BIT(23)
-
-#define DDRPHYC_ACDLLCR_DLLDIS			BIT(31)
-
-#define DDRPHYC_ZQ0CRN_ZDATA_MASK		GENMASK(27, 0)
-#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT		0
-#define DDRPHYC_ZQ0CRN_ZDEN			BIT(28)
-
-#define DDRPHYC_DXNGCR_DXEN			BIT(0)
-
-#define DDRPHYC_DXNDLLCR_DLLSRST		BIT(30)
-#define DDRPHYC_DXNDLLCR_DLLDIS			BIT(31)
-#define DDRPHYC_DXNDLLCR_SDPHASE_MASK		GENMASK(17, 14)
-#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT		14
-
-#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit)	(4 * (bit))
-#define DDRPHYC_DXNDQTR_DQDLY_MASK		GENMASK(3, 0)
-#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK		GENMASK(1, 0)
-#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK		GENMASK(3, 2)
-
-#define DDRPHYC_DXNDQSTR_DQSDLY_MASK		GENMASK(22, 20)
-#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT		20
-#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK		GENMASK(25, 23)
-#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT		23
-#define DDRPHYC_DXNDQSTR_R0DGSL_MASK		GENMASK(2, 0)
-#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT		0
-#define DDRPHYC_DXNDQSTR_R0DGPS_MASK		GENMASK(13, 12)
-#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT		12
-
-#define DDRPHYC_BISTRR_BDXSEL_MASK		GENMASK(22, 19)
-#define DDRPHYC_BISTRR_BDXSEL_SHIFT		19
-
-#define DDRPHYC_BISTGSR_BDDONE			BIT(0)
-#define DDRPHYC_BISTGSR_BDXERR			BIT(2)
-
-#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT		16
-
-/* PWR registers */
-#define PWR_CR3					0x00C
-#define PWR_CR3_DDRSRDIS			BIT(11)
-#define PWR_CR3_DDRRETEN			BIT(12)
-
-#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/debug_ll.h b/arch/arm/mach-stm32mp/include/mach/debug_ll.h
deleted file mode 100644
index 99fedb91fe..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/debug_ll.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __MACH_STM32MP1_DEBUG_LL_H
-#define __MACH_STM32MP1_DEBUG_LL_H
-
-#include <io.h>
-#include <mach/stm32.h>
-
-#define DEBUG_LL_UART_ADDR	STM32_UART4_BASE
-
-#define CR1_OFFSET	0x00
-#define CR3_OFFSET	0x08
-#define BRR_OFFSET	0x0c
-#define ISR_OFFSET	0x1c
-#define ICR_OFFSET	0x20
-#define RDR_OFFSET	0x24
-#define TDR_OFFSET	0x28
-
-#define USART_ISR_TXE	BIT(7)
-
-static inline void PUTC_LL(int c)
-{
-	void __iomem *base = IOMEM(DEBUG_LL_UART_ADDR);
-
-	writel(c, base + TDR_OFFSET);
-
-	while ((readl(base + ISR_OFFSET) & USART_ISR_TXE) == 0);
-}
-
-#endif /* __MACH_STM32MP1_DEBUG_LL_H */
diff --git a/arch/arm/mach-stm32mp/include/mach/entry.h b/arch/arm/mach-stm32mp/include/mach/entry.h
deleted file mode 100644
index 92e15b5cf4..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/entry.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _STM32MP_MACH_ENTRY_H_
-#define _STM32MP_MACH_ENTRY_H_
-
-#include <linux/kernel.h>
-#include <asm/barebox-arm.h>
-
-static __always_inline void stm32mp_cpu_lowlevel_init(void)
-{
-	unsigned long stack_top;
-	arm_cpu_lowlevel_init();
-
-	stack_top = (unsigned long)__image_end + get_runtime_offset() + 64;
-	stack_top = ALIGN(stack_top, 16);
-	arm_setup_stack(stack_top);
-}
-
-void __noreturn stm32mp1_barebox_entry(void *boarddata);
-
-#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h
deleted file mode 100644
index 2ef8ef30c3..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/revision.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
- */
-
-#ifndef __MACH_CPUTYPE_H__
-#define __MACH_CPUTYPE_H__
-
-#include <mach/bsec.h>
-#include <asm/io.h>
-#include <mach/stm32.h>
-
-/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0)
- * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI
- * 153X: 2x Cortex-A7, Cortex-M4, CAN FD
- * 151X: 1x Cortex-A7, Cortex-M4
- * XXXA: Cortex-A7 @ 650 MHz
- * XXXC: Cortex-A7 @ 650 MHz + Secure Boot + HW Crypto
- * XXXD: Cortex-A7 @ 800 MHz
- * XXXF: Cortex-A7 @ 800 MHz + Secure Boot + HW Crypto
- */
-#define CPU_STM32MP157Cxx	0x05000000
-#define CPU_STM32MP157Axx	0x05000001
-#define CPU_STM32MP153Cxx	0x05000024
-#define CPU_STM32MP153Axx	0x05000025
-#define CPU_STM32MP151Cxx	0x0500002E
-#define CPU_STM32MP151Axx	0x0500002F
-#define CPU_STM32MP157Fxx	0x05000080
-#define CPU_STM32MP157Dxx	0x05000081
-#define CPU_STM32MP153Fxx	0x050000A4
-#define CPU_STM32MP153Dxx	0x050000A5
-#define CPU_STM32MP151Fxx	0x050000AE
-#define CPU_STM32MP151Dxx	0x050000AF
-
-/* silicon revisions */
-#define CPU_REV_A	0x1000
-#define CPU_REV_B	0x2000
-#define CPU_REV_Z	0x2001
-
-int stm32mp_silicon_revision(void);
-int stm32mp_cputype(void);
-int stm32mp_package(void);
-
-#define cpu_is_stm32mp157c() (stm32mp_cputype() == CPU_STM32MP157Cxx)
-#define cpu_is_stm32mp157a() (stm32mp_cputype() == CPU_STM32MP157Axx)
-#define cpu_is_stm32mp153c() (stm32mp_cputype() == CPU_STM32MP153Cxx)
-#define cpu_is_stm32mp153a() (stm32mp_cputype() == CPU_STM32MP153Axx)
-#define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx)
-#define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx)
-
-/* DBGMCU register */
-#define DBGMCU_APB4FZ1		(STM32_DBGMCU_BASE + 0x2C)
-#define DBGMCU_IDC		(STM32_DBGMCU_BASE + 0x00)
-#define DBGMCU_IDC_DEV_ID_MASK	GENMASK(11, 0)
-#define DBGMCU_IDC_DEV_ID_SHIFT	0
-#define DBGMCU_IDC_REV_ID_MASK	GENMASK(31, 16)
-#define DBGMCU_IDC_REV_ID_SHIFT	16
-
-#define RCC_DBGCFGR		(STM32_RCC_BASE + 0x080C)
-#define RCC_DBGCFGR_DBGCKEN	BIT(8)
-
-/* BSEC OTP index */
-#define BSEC_OTP_RPN	1
-#define BSEC_OTP_PKG	16
-
-/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
-#define RPN_SHIFT	0
-#define RPN_MASK	GENMASK(7, 0)
-
-static inline u32 stm32mp_read_idc(void)
-{
-	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
-	return readl(IOMEM(DBGMCU_IDC));
-}
-
-/* Get Device Part Number (RPN) from OTP */
-static inline int __stm32mp_get_cpu_rpn(u32 *rpn)
-{
-	int ret = bsec_read_field(BSEC_OTP_RPN, rpn);
-	if (ret)
-		return ret;
-
-	*rpn = (*rpn >> RPN_SHIFT) & RPN_MASK;
-	return 0;
-}
-
-static inline int __stm32mp_get_cpu_type(u32 *type)
-{
-	u32 id;
-	int ret = __stm32mp_get_cpu_rpn(type);
-	if (ret)
-		return ret;
-
-	id = (stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
-	*type |= id << 16;
-	return 0;
-}
-
-#endif /* __MACH_CPUTYPE_H__ */
diff --git a/arch/arm/mach-stm32mp/include/mach/smc.h b/arch/arm/mach-stm32mp/include/mach/smc.h
deleted file mode 100644
index 6b8e62bd53..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/smc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __MACH_STM32_SMC_H__
-#define __MACH_STM32_SMC_H__
-
-#include <linux/arm-smccc.h>
-
-/* Secure Service access from Non-secure */
-#define STM32_SMC_RCC                   0x82001000
-#define STM32_SMC_PWR                   0x82001001
-#define STM32_SMC_RTC                   0x82001002
-#define STM32_SMC_BSEC                  0x82001003
-
-/* Register access service use for RCC/RTC/PWR */
-#define STM32_SMC_REG_WRITE             0x1
-#define STM32_SMC_REG_SET               0x2
-#define STM32_SMC_REG_CLEAR             0x3
-
-static inline int stm32mp_smc(u32 svc, u8 op, u32 data1, u32 data2, u32 *val)
-{
-        struct arm_smccc_res res;
-
-        arm_smccc_smc(svc, op, data1, data2, 0, 0, 0, 0, &res);
-        if (val)
-                *val = res.a1;
-
-        return (int)res.a0;
-}
-
-#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
deleted file mode 100644
index adb898fa26..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-#ifndef _MACH_STM32_H_
-#define _MACH_STM32_H_
-
-/*
- * Peripheral memory map
- */
-#define STM32_RCC_BASE			0x50000000
-#define STM32_PWR_BASE			0x50001000
-#define STM32_DBGMCU_BASE		0x50081000
-#define STM32_DDRCTL_BASE		0x5A003000
-#define STM32_DDRPHY_BASE		0x5A004000
-#define STM32_BSEC_BASE			0x5C005000
-#define STM32_TZC_BASE			0x5C006000
-#define STM32_ETZPC_BASE		0x5C007000
-#define STM32_TAMP_BASE			0x5C00A000
-
-#define STM32_USART1_BASE		0x5C000000
-#define STM32_USART2_BASE		0x4000E000
-#define STM32_USART3_BASE		0x4000F000
-#define STM32_UART4_BASE		0x40010000
-#define STM32_UART5_BASE		0x40011000
-#define STM32_USART6_BASE		0x44003000
-#define STM32_UART7_BASE		0x40018000
-#define STM32_UART8_BASE		0x40019000
-
-#define STM32_SYSRAM_BASE		0x2FFC0000
-#define STM32_SYSRAM_SIZE		SZ_256K
-
-#define STM32_DDR_BASE			0xC0000000
-#define STM32_DDR_SIZE			SZ_1G
-
-#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index 01961ae456..2eb8b6beec 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -8,10 +8,10 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/stm32.h>
-#include <mach/bsec.h>
-#include <mach/revision.h>
-#include <mach/bootsource.h>
+#include <mach/stm32mp/stm32.h>
+#include <mach/stm32mp/bsec.h>
+#include <mach/stm32mp/revision.h>
+#include <mach/stm32mp/bootsource.h>
 #include <bootsource.h>
 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
 
@@ -42,12 +42,9 @@
 
 /* TAMP registers */
 #define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
-/* secure access */
-#define TAMP_BACKUP_MAGIC_NUMBER        TAMP_BACKUP_REGISTER(4)
-#define TAMP_BACKUP_BRANCH_ADDRESS      TAMP_BACKUP_REGISTER(5)
 /* non secure access */
-#define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
-#define TAMP_BOOTCOUNT                  TAMP_BACKUP_REGISTER(21)
+#define STM32MP13_TAMP_BOOT_CONTEXT     TAMP_BACKUP_REGISTER(30)
+#define STM32MP15_TAMP_BOOT_CONTEXT     TAMP_BACKUP_REGISTER(20)
 
 #define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
 #define TAMP_BOOT_MODE_SHIFT            8
@@ -60,9 +57,8 @@
 #define FIXUP_CPU_NUM(mask) ((mask) >> 16)
 #define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL)
 
-static void setup_boot_mode(void)
+static void setup_boot_mode(u32 boot_ctx)
 {
-	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
 	u32 boot_mode =
 		(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
 	int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
@@ -98,31 +94,7 @@ static void setup_boot_mode(void)
 	pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d\n",
 		 boot_ctx, boot_mode, instance);
 
-	bootsource_set(src);
-	bootsource_set_instance(instance);
-}
-
-static int __stm32mp_cputype;
-int stm32mp_cputype(void)
-{
-	return __stm32mp_cputype;
-}
-
-static int __stm32mp_silicon_revision;
-int stm32mp_silicon_revision(void)
-{
-	return __stm32mp_silicon_revision;
-}
-
-static int __stm32mp_package;
-int stm32mp_package(void)
-{
-	return __stm32mp_package;
-}
-
-static u32 get_cpu_revision(void)
-{
-	return (stm32mp_read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
+	bootsource_set_raw(src, instance);
 }
 
 static int get_cpu_package(u32 *pkg)
@@ -140,7 +112,7 @@ static int stm32mp15_fixup_cpus(struct device_node *root, void *_ctx)
 	unsigned long ctx = (unsigned long)_ctx;
 	struct device_node *cpus_node, *np, *tmp;
 
-	cpus_node = of_find_node_by_name(root, "cpus");
+	cpus_node = of_find_node_by_name_address(root, "cpus");
 	if (!cpus_node)
 		return 0;
 
@@ -182,127 +154,112 @@ static int stm32mp15_fixup_pkg(struct device_node *root, void *_pkg)
 	return fixup_pinctrl(root, "st,stm32mp157-z-pinctrl", pkg);
 }
 
-static int setup_cpu_type(void)
+static int stm32mp15_setup_cpu_type(void)
 {
-	const char *cputypestr, *cpupkgstr, *cpurevstr;
 	unsigned long cpufixupctx = 0, pkgfixupctx = 0;
-	u32 pkg;
-	int ret;
+	int cputype, package;
 
-	__stm32mp_get_cpu_type(&__stm32mp_cputype);
-	switch (__stm32mp_cputype) {
+	__stm32mp15_get_cpu_type(&cputype);
+	switch (cputype) {
 	case CPU_STM32MP157Fxx:
-		cputypestr = "157F";
 		cpufixupctx = FIXUP_CPU_MASK(2, 800);
 		break;
 	case CPU_STM32MP157Dxx:
-		cputypestr = "157D";
 		cpufixupctx = FIXUP_CPU_MASK(2, 800);
 		break;
 	case CPU_STM32MP157Cxx:
-		cputypestr = "157C";
 		cpufixupctx = FIXUP_CPU_MASK(2, 650);
 		break;
 	case CPU_STM32MP157Axx:
-		cputypestr = "157A";
 		cpufixupctx = FIXUP_CPU_MASK(2, 650);
 		break;
 	case CPU_STM32MP153Fxx:
-		cputypestr = "153F";
 		cpufixupctx = FIXUP_CPU_MASK(2, 800);
 		break;
 	case CPU_STM32MP153Dxx:
-		cputypestr = "153D";
 		cpufixupctx = FIXUP_CPU_MASK(2, 800);
 		break;
 	case CPU_STM32MP153Cxx:
-		cputypestr = "153C";
 		cpufixupctx = FIXUP_CPU_MASK(2, 650);
 		break;
 	case CPU_STM32MP153Axx:
-		cputypestr = "153A";
 		cpufixupctx = FIXUP_CPU_MASK(2, 650);
 		break;
 	case CPU_STM32MP151Cxx:
-		cputypestr = "151C";
 		cpufixupctx = FIXUP_CPU_MASK(1, 650);
 		break;
 	case CPU_STM32MP151Axx:
-		cputypestr = "151A";
 		cpufixupctx = FIXUP_CPU_MASK(1, 650);
 		break;
 	case CPU_STM32MP151Fxx:
-		cputypestr = "151F";
 		cpufixupctx = FIXUP_CPU_MASK(1, 800);
 		break;
 	case CPU_STM32MP151Dxx:
-		cputypestr = "151D";
 		cpufixupctx = FIXUP_CPU_MASK(1, 800);
 		break;
 	default:
-		cputypestr = "????";
 		break;
 	}
 
-	get_cpu_package(&__stm32mp_package );
-	switch (__stm32mp_package) {
+	get_cpu_package(&package);
+	switch (package) {
 	case PKG_AA_LBGA448:
-		cpupkgstr = "AA";
 		pkgfixupctx = STM32MP_PKG_AA;
 		break;
 	case PKG_AB_LBGA354:
-		cpupkgstr = "AB";
 		pkgfixupctx = STM32MP_PKG_AB;
 		break;
 	case PKG_AC_TFBGA361:
-		cpupkgstr = "AC";
 		pkgfixupctx = STM32MP_PKG_AC;
 		break;
 	case PKG_AD_TFBGA257:
-		cpupkgstr = "AD";
 		pkgfixupctx = STM32MP_PKG_AD;
 		break;
 	default:
-		cpupkgstr = "??";
 		break;
 	}
 
-	__stm32mp_silicon_revision = get_cpu_revision();
-	switch (__stm32mp_silicon_revision) {
-	case CPU_REV_A:
-		cpurevstr = "A";
-		break;
-	case CPU_REV_B:
-		cpurevstr = "B";
-		break;
-	case CPU_REV_Z:
-		cpurevstr = "Z";
-		break;
-	default:
-		cpurevstr = "?";
-	}
-
-	pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n",
-		 __stm32mp_cputype, pkg, __stm32mp_silicon_revision);
-	pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr);
-
-	if (cpufixupctx) {
-		ret = of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx);
-		if (ret)
-			return ret;
-	}
+	pr_debug("cputype = 0x%x, package = 0x%x\n", cputype, package);
 
+	if (cpufixupctx)
+		of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx);
 	if (pkgfixupctx)
-		return of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx);
+		of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx);
 
 	return 0;
 }
 
+static int __st32mp_soc;
+
+int stm32mp_soc(void)
+{
+	return __st32mp_soc;
+}
+
 static int stm32mp_init(void)
 {
-	setup_cpu_type();
-	setup_boot_mode();
+	u32 boot_ctx;
+
+	if (of_machine_is_compatible("st,stm32mp135"))
+		__st32mp_soc = 32135;
+	else if (of_machine_is_compatible("st,stm32mp151"))
+		__st32mp_soc = 32151;
+	else if (of_machine_is_compatible("st,stm32mp153"))
+		__st32mp_soc = 32153;
+	else if (of_machine_is_compatible("st,stm32mp157"))
+		__st32mp_soc = 32157;
+	else
+		return 0;
+
+	if (__st32mp_soc == 32135) {
+		boot_ctx = readl(STM32MP13_TAMP_BOOT_CONTEXT);
+	} else {
+		stm32mp15_setup_cpu_type();
+		boot_ctx = readl(STM32MP15_TAMP_BOOT_CONTEXT);
+	}
+
+	setup_boot_mode(boot_ctx);
 
 	return 0;
 }
-core_initcall(stm32mp_init);
+postcore_initcall(stm32mp_init);
diff --git a/arch/arm/mach-stm32mp/stm32image.c b/arch/arm/mach-stm32mp/stm32image.c
index 207df6894d..37d7c73120 100644
--- a/arch/arm/mach-stm32mp/stm32image.c
+++ b/arch/arm/mach-stm32mp/stm32image.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 #define pr_fmt(fmt) "stm32image: " fmt
 
 #include <bootm.h>
@@ -5,6 +7,7 @@
 #include <init.h>
 #include <memory.h>
 #include <linux/sizes.h>
+#include <mach/stm32mp/stm32.h>
 
 #define BAREBOX_STAGE2_OFFSET	256
 
@@ -38,11 +41,14 @@ static int do_bootm_stm32image(struct image_data *data)
 static struct image_handler image_handler_stm32_image_v1_handler = {
 	.name = "STM32 image (v1)",
 	.bootm = do_bootm_stm32image,
-	.filetype = filetype_stm32_image_v1,
+	.filetype = filetype_stm32_image_ssbl_v1,
 };
 
 static int stm32mp_register_stm32image_image_handler(void)
 {
+	if (!stm32mp_soc())
+		return 0;
+
 	return register_image_handler(&image_handler_stm32_image_v1_handler);
 }
 late_initcall(stm32mp_register_stm32image_image_handler);
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index f144d346b4..cc256f584a 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_TEGRA
 
 config ARCH_TEXT_BASE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 60aae41ea0..ddc029bda2 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
 CFLAGS_tegra_avp_init.pbl.o := -mcpu=arm7tdmi -march=armv4t
 lwl-y += tegra_avp_init.o
diff --git a/arch/arm/mach-tegra/include/mach/debug_ll.h b/arch/arm/mach-tegra/include/mach/debug_ll.h
deleted file mode 100644
index 86218df63e..0000000000
--- a/arch/arm/mach-tegra/include/mach/debug_ll.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-/** @file
- *  This File contains declaration for early output support
- */
-#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
-#define __INCLUDE_ARCH_DEBUG_LL_H__
-
-#include <asm/io.h>
-#include <mach/iomap.h>
-
-#define DEBUG_LL_UART_ADDR	TEGRA_UARTA_BASE
-#define DEBUG_LL_UART_RSHFT	2
-
-#define rbr		(0 << DEBUG_LL_UART_RSHFT)
-#define lsr		(5 << DEBUG_LL_UART_RSHFT)
-#define LSR_THRE	0x20	/* Xmit holding register empty */
-
-static inline void PUTC_LL(char ch)
-{
-	while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE))
-		;
-
-	__raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
-}
-
-#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
deleted file mode 100644
index bbe6ae6be6..0000000000
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/iomap.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *	Colin Cross <ccross@google.com>
- *	Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_IOMAP_H
-#define __MACH_TEGRA_IOMAP_H
-
-#include <linux/sizes.h>
-
-#define TEGRA_IRAM_BASE			0x40000000
-#define TEGRA_IRAM_SIZE			SZ_256K
-
-#define TEGRA_HOST1X_BASE		0x50000000
-#define TEGRA_HOST1X_SIZE		0x24000
-
-#define TEGRA_ARM_PERIF_BASE		0x50040000
-#define TEGRA_ARM_PERIF_SIZE		SZ_8K
-
-#define TEGRA_ARM_PL310_BASE		0x50043000
-#define TEGRA_ARM_PL310_SIZE		SZ_4K
-
-#define TEGRA_ARM_INT_DIST_BASE		0x50041000
-#define TEGRA_ARM_INT_DIST_SIZE		SZ_4K
-
-#define TEGRA_MPE_BASE			0x54040000
-#define TEGRA_MPE_SIZE			SZ_256K
-
-#define TEGRA_VI_BASE			0x54080000
-#define TEGRA_VI_SIZE			SZ_256K
-
-#define TEGRA_ISP_BASE			0x54100000
-#define TEGRA_ISP_SIZE			SZ_256K
-
-#define TEGRA_DISPLAY_BASE		0x54200000
-#define TEGRA_DISPLAY_SIZE		SZ_256K
-
-#define TEGRA_DISPLAY2_BASE		0x54240000
-#define TEGRA_DISPLAY2_SIZE		SZ_256K
-
-#define TEGRA_HDMI_BASE			0x54280000
-#define TEGRA_HDMI_SIZE			SZ_256K
-
-#define TEGRA_GART_BASE			0x58000000
-#define TEGRA_GART_SIZE			SZ_32M
-
-#define TEGRA_UP_TAG_BASE		0x60000000
-#define TEGRA_UP_TAG_SIZE		SZ_4K
-
-#define TEGRA_RES_SEMA_BASE		0x60001000
-#define TEGRA_RES_SEMA_SIZE		SZ_4K
-
-#define TEGRA_HDMI_BASE			0x54280000
-#define TEGRA_HDMI_SIZE			SZ_256K
-
-#define TEGRA_GART_BASE			0x58000000
-#define TEGRA_GART_SIZE			SZ_32M
-
-#define TEGRA_RES_SEMA_BASE		0x60001000
-#define TEGRA_RES_SEMA_SIZE		SZ_4K
-
-#define TEGRA_ARB_SEMA_BASE		0x60002000
-#define TEGRA_ARB_SEMA_SIZE		SZ_4K
-
-#define TEGRA_PRIMARY_ICTLR_BASE	0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE	64
-
-#define TEGRA_ARBGNT_ICTLR_BASE		0x60004040
-#define TEGRA_ARBGNT_ICTLR_SIZE		192
-
-#define TEGRA_SECONDARY_ICTLR_BASE	0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE	64
-
-#define TEGRA_TERTIARY_ICTLR_BASE	0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE	64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE	0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZE	64
-
-#define TEGRA_TMR1_BASE			0x60005000
-#define TEGRA_TMR1_SIZE			8
-
-#define TEGRA_TMR2_BASE			0x60005008
-#define TEGRA_TMR2_SIZE			8
-
-#define TEGRA_TMRUS_BASE		0x60005010
-#define TEGRA_TMRUS_SIZE		64
-
-#define TEGRA_TMR3_BASE			0x60005050
-#define TEGRA_TMR3_SIZE			8
-
-#define TEGRA_TMR4_BASE			0x60005058
-#define TEGRA_TMR4_SIZE			8
-
-#define TEGRA_CLK_RESET_BASE		0x60006000
-#define TEGRA_CLK_RESET_SIZE		SZ_4K
-
-#define TEGRA_FLOW_CTRL_BASE		0x60007000
-#define TEGRA_FLOW_CTRL_SIZE		20
-
-#define TEGRA_AHB_DMA_BASE		0x60008000
-#define TEGRA_AHB_DMA_SIZE		SZ_4K
-
-#define TEGRA_AHB_DMA_CH0_BASE		0x60009000
-#define TEGRA_AHB_DMA_CH0_SIZE		32
-
-#define TEGRA_APB_DMA_BASE		0x6000A000
-#define TEGRA_APB_DMA_SIZE		SZ_4K
-
-#define TEGRA_APB_DMA_CH0_BASE		0x6000B000
-#define TEGRA_APB_DMA_CH0_SIZE		32
-
-#define TEGRA_AHB_GIZMO_BASE		0x6000C004
-#define TEGRA_AHB_GIZMO_SIZE		0x10C
-
-#define TEGRA_STATMON_BASE		0x6000C400
-#define TEGRA_STATMON_SIZE		SZ_1K
-
-#define TEGRA_GPIO_BASE			0x6000D000
-#define TEGRA_GPIO_SIZE			SZ_4K
-
-#define TEGRA_EXCEPTION_VECTORS_BASE    0x6000F000
-#define TEGRA_EXCEPTION_VECTORS_SIZE    SZ_4K
-
-#define TEGRA_VDE_BASE		0x6001A000
-#define TEGRA_VDE_SIZE		(SZ_8K + SZ_4K - SZ_256)
-
-#define TEGRA_APB_MISC_BASE		0x70000000
-#define TEGRA_APB_MISC_SIZE		SZ_4K
-
-#define TEGRA_APB_MISC_DAS_BASE		0x70000c00
-#define TEGRA_APB_MISC_DAS_SIZE		SZ_128
-
-#define TEGRA_AC97_BASE			0x70002000
-#define TEGRA_AC97_SIZE			SZ_512
-
-#define TEGRA_SPDIF_BASE		0x70002400
-#define TEGRA_SPDIF_SIZE		SZ_512
-
-#define TEGRA_I2S1_BASE			0x70002800
-#define TEGRA_I2S1_SIZE			SZ_256
-
-#define TEGRA_I2S2_BASE			0x70002A00
-#define TEGRA_I2S2_SIZE			SZ_256
-
-#define TEGRA_UARTA_BASE		0x70006000
-#define TEGRA_UARTA_SIZE		64
-
-#define TEGRA_UARTB_BASE		0x70006040
-#define TEGRA_UARTB_SIZE		64
-
-#define TEGRA_UARTC_BASE		0x70006200
-#define TEGRA_UARTC_SIZE		SZ_256
-
-#define TEGRA_UARTD_BASE		0x70006300
-#define TEGRA_UARTD_SIZE		SZ_256
-
-#define TEGRA_UARTE_BASE		0x70006400
-#define TEGRA_UARTE_SIZE		SZ_256
-
-#define TEGRA_NAND_BASE			0x70008000
-#define TEGRA_NAND_SIZE			SZ_256
-
-#define TEGRA_HSMMC_BASE		0x70008500
-#define TEGRA_HSMMC_SIZE		SZ_256
-
-#define TEGRA_SNOR_BASE			0x70009000
-#define TEGRA_SNOR_SIZE			SZ_4K
-
-#define TEGRA_PWFM_BASE			0x7000A000
-#define TEGRA_PWFM_SIZE			SZ_256
-
-#define TEGRA_PWFM0_BASE		0x7000A000
-#define TEGRA_PWFM0_SIZE		4
-
-#define TEGRA_PWFM1_BASE		0x7000A010
-#define TEGRA_PWFM1_SIZE		4
-
-#define TEGRA_PWFM2_BASE		0x7000A020
-#define TEGRA_PWFM2_SIZE		4
-
-#define TEGRA_PWFM3_BASE		0x7000A030
-#define TEGRA_PWFM3_SIZE		4
-
-#define TEGRA_MIPI_BASE			0x7000B000
-#define TEGRA_MIPI_SIZE			SZ_256
-
-#define TEGRA_I2C_BASE			0x7000C000
-#define TEGRA_I2C_SIZE			SZ_256
-
-#define TEGRA_TWC_BASE			0x7000C100
-#define TEGRA_TWC_SIZE			SZ_256
-
-#define TEGRA_SPI_BASE			0x7000C380
-#define TEGRA_SPI_SIZE			48
-
-#define TEGRA_I2C2_BASE			0x7000C400
-#define TEGRA_I2C2_SIZE			SZ_256
-
-#define TEGRA_I2C3_BASE			0x7000C500
-#define TEGRA_I2C3_SIZE			SZ_256
-
-#define TEGRA_OWR_BASE			0x7000C600
-#define TEGRA_OWR_SIZE			80
-
-#define TEGRA_DVC_BASE			0x7000D000
-#define TEGRA_DVC_SIZE			SZ_512
-
-#define TEGRA_SPI1_BASE			0x7000D400
-#define TEGRA_SPI1_SIZE			SZ_512
-
-#define TEGRA_SPI2_BASE			0x7000D600
-#define TEGRA_SPI2_SIZE			SZ_512
-
-#define TEGRA_SPI3_BASE			0x7000D800
-#define TEGRA_SPI3_SIZE			SZ_512
-
-#define TEGRA_SPI4_BASE			0x7000DA00
-#define TEGRA_SPI4_SIZE			SZ_512
-
-#define TEGRA_RTC_BASE			0x7000E000
-#define TEGRA_RTC_SIZE			SZ_256
-
-#define TEGRA_KBC_BASE			0x7000E200
-#define TEGRA_KBC_SIZE			SZ_256
-
-#define TEGRA_PMC_BASE			0x7000E400
-#define TEGRA_PMC_SIZE			SZ_256
-
-#define TEGRA_MC_BASE			0x7000F000
-#define TEGRA_MC_SIZE			SZ_1K
-
-#define TEGRA_EMC_BASE			0x7000F400
-#define TEGRA_EMC_SIZE			SZ_1K
-
-#define TEGRA_FUSE_BASE			0x7000F800
-#define TEGRA_FUSE_SIZE			SZ_1K
-
-#define TEGRA_KFUSE_BASE		0x7000FC00
-#define TEGRA_KFUSE_SIZE		SZ_1K
-
-#define TEGRA_CSITE_BASE		0x70040000
-#define TEGRA_CSITE_SIZE		SZ_256K
-
-#define TEGRA_SYSCTR0_BASE		0x700F0000
-#define TEGRA_SYSCTR0_SIZE		SZ_64K
-
-#define TEGRA_USB_BASE			0xC5000000
-#define TEGRA_USB_SIZE			SZ_16K
-
-#define TEGRA_USB2_BASE			0xC5004000
-#define TEGRA_USB2_SIZE			SZ_16K
-
-#define TEGRA_USB3_BASE			0xC5008000
-#define TEGRA_USB3_SIZE			SZ_16K
-
-#define TEGRA_SDMMC1_BASE		0xC8000000
-#define TEGRA_SDMMC1_SIZE		SZ_512
-
-#define TEGRA_SDMMC2_BASE		0xC8000200
-#define TEGRA_SDMMC2_SIZE		SZ_512
-
-#define TEGRA_SDMMC3_BASE		0xC8000400
-#define TEGRA_SDMMC3_SIZE		SZ_512
-
-#define TEGRA_SDMMC4_BASE		0xC8000600
-#define TEGRA_SDMMC4_SIZE		SZ_512
-
-#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
-# define TEGRA_DEBUG_UART_BASE 0
-#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
-#endif
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
deleted file mode 100644
index 1deae4e565..0000000000
--- a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/compiler.h>
-#include "mach/tegra20-car.h"
-#include "mach/lowlevel.h"
-
-static __always_inline
-void tegra_dvc_init(void)
-{
-	int div;
-	u32 reg;
-
-	/* reset DVC controller and enable clock */
-	writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_SET);
-	reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
-	reg |= CRC_CLK_OUT_ENB_H_DVC;
-	writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
-
-	/* set DVC I2C clock source to CLK_M and aim for 100kHz I2C clock */
-	div = ((tegra_get_osc_clock() * 3) >> 22) - 1;
-	writel((div) | (3 << 30),
-	       TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_DVC);
-
-	/* clear DVC reset */
-	tegra_ll_delay_usec(3);
-	writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_CLR);
-}
-
-static __always_inline
-void tegra124_dvc_pinmux(void)
-{
-	u32 val;
-
-	/* disable tristate for pin PWR_I2C_SCL_PZ6 */
-	val = readl(TEGRA_APB_MISC_BASE + 0x32b4);
-	val &= ~(1 << 4);
-	writel(val, TEGRA_APB_MISC_BASE + 0x32b4);
-
-	/* disable tristate for pin PWR_I2C_SDA_PZ7 */
-	val = readl(TEGRA_APB_MISC_BASE + 0x32b8);
-	val &= ~(1 << 4);
-	writel(val, TEGRA_APB_MISC_BASE + 0x32b8);
-}
-
-#define TEGRA_I2C_CNFG		0x00
-#define TEGRA_I2C_CMD_ADDR0	0x04
-#define TEGRA_I2C_CMD_DATA1	0x0c
-#define TEGRA_I2C_SEND_2_BYTES	0x0a02
-
-static __always_inline
-void tegra_dvc_write_addr(u32 addr, u32 config)
-{
-	writel(addr, TEGRA_DVC_BASE + TEGRA_I2C_CMD_ADDR0);
-	writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
-}
-
-static __always_inline
-void tegra_dvc_write_data(u32 data, u32 config)
-{
-	writel(data, TEGRA_DVC_BASE + TEGRA_I2C_CMD_DATA1);
-	writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
-}
-
-static __always_inline
-void tegra30_tps65911_cpu_rail_enable(void)
-{
-	tegra_dvc_write_addr(0x5a, 2);
-	/* reg 28, 600mV + (35-3) * 12,5mV = 1,0V */
-	tegra_dvc_write_data(0x2328, TEGRA_I2C_SEND_2_BYTES);
-	tegra_ll_delay_usec(1000);
-	/* reg 27, VDDctrl enable */
-	tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES);
-	tegra_ll_delay_usec(10 * 1000);
-}
-
-static __always_inline
-void tegra30_tps62366a_ramp_vddcore(void)
-{
-	tegra_dvc_write_addr(0xc0, 2);
-	/* set VDDcore to 1,2V */
-	tegra_dvc_write_data(0x4601, TEGRA_I2C_SEND_2_BYTES);
-	tegra_ll_delay_usec(1000);
-}
-
-static __always_inline
-void tegra30_tps62361b_ramp_vddcore(void)
-{
-	tegra_dvc_write_addr(0xc0, 2);
-	/* set VDDcore to 1,2V */
-	tegra_dvc_write_data(0x4603, TEGRA_I2C_SEND_2_BYTES);
-	tegra_ll_delay_usec(1000);
-}
-
-static __always_inline
-void tegra124_as3722_enable_essential_rails(u32 sd0voltage)
-{
-	/*
-	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
-	 * First set VDD to 1.0V, then enable the VDD regulator.
-	 */
-	tegra_dvc_write_addr(0x80, 2);
-	tegra_dvc_write_data(sd0voltage | 0x00, TEGRA_I2C_SEND_2_BYTES);
-	tegra_ll_delay_usec(10 * 1000);
-
-	/*
-	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
-	 * First set VDD to 1.0V, then enable the VDD regulator.
-	 */
-	tegra_dvc_write_addr(0x80, 2);
-	tegra_dvc_write_data(0x2800 | 0x06, TEGRA_I2C_SEND_2_BYTES);
-	tegra_ll_delay_usec(10 * 1000);
-
-	/*
-	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
-	 * First set VDD to 1.2V, then enable the VDD regulator.
-	 */
-	tegra_dvc_write_addr(0x80, 2);
-	tegra_dvc_write_data(0x1000 | 0x12, TEGRA_I2C_SEND_2_BYTES);
-	tegra_ll_delay_usec(10 * 1000);
-
-	/*
-	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
-	 * First set it to bypass 3.3V straight thru, then enable the regulator
-	 *
-	 * NOTE: We do this early because doing it later seems to hose the CPU
-	 * power rail/partition startup. Need to debug.
-	 */
-	tegra_dvc_write_addr(0x80, 2);
-	tegra_dvc_write_data(0x3f00 | 0x16, TEGRA_I2C_SEND_2_BYTES);
-	tegra_ll_delay_usec(10 * 1000);
-}
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
deleted file mode 100644
index 31f99eb175..0000000000
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/**
- * @file
- * @brief Boot informations provided by the Tegra SoC and it's BootROM. All
- * accessor functions are a header only implementations, as they are meant to
- * be used by both the main CPU complex (ARMv7) and the AVP (ARMv4).
- */
-
-#ifndef __TEGRA_LOWLEVEL_H
-#define __TEGRA_LOWLEVEL_H
-
-#include <asm/barebox-arm.h>
-#include <linux/compiler.h>
-#include <linux/sizes.h>
-#include <io.h>
-#include <mach/iomap.h>
-
-/* Bootinfotable */
-
-/* location of the BCT in IRAM */
-#define NV_BIT_BCTPTR_T20	0x3c
-#define NV_BIT_BCTPTR_T114	0x4c
-
-/* ODM data */
-#define BCT_ODMDATA_OFFSET	12	/* offset from the _end_ of the BCT */
-
-#define T20_ODMDATA_RAMSIZE_SHIFT	28
-#define T20_ODMDATA_RAMSIZE_MASK	(3 << T20_ODMDATA_RAMSIZE_SHIFT)
-#define T30_ODMDATA_RAMSIZE_MASK	(0xf << T20_ODMDATA_RAMSIZE_SHIFT)
-#define T20_ODMDATA_UARTTYPE_SHIFT	18
-#define T20_ODMDATA_UARTTYPE_MASK	(3 << T20_ODMDATA_UARTTYPE_SHIFT)
-#define T20_ODMDATA_UARTID_SHIFT	15
-#define T20_ODMDATA_UARTID_MASK		(7 << T20_ODMDATA_UARTID_SHIFT)
-
-/* chip ID */
-#define APB_MISC_HIDREV			0x804
-#define HIDREV_CHIPID_SHIFT		8
-#define HIDREV_CHIPID_MASK		(0xff << HIDREV_CHIPID_SHIFT)
-
-enum tegra_chiptype {
-	TEGRA_UNK_REV = -1,
-	TEGRA20 = 0,
-	TEGRA30 = 1,
-	TEGRA114 = 2,
-	TEGRA124 = 3,
-};
-
-static __always_inline
-u32 tegra_read_chipid(void)
-{
-	return readl(TEGRA_APB_MISC_BASE + APB_MISC_HIDREV);
-}
-
-static __always_inline
-enum tegra_chiptype tegra_get_chiptype(void)
-{
-	u32 hidrev;
-
-	hidrev = readl(TEGRA_APB_MISC_BASE + APB_MISC_HIDREV);
-
-	switch ((hidrev & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT) {
-	case 0x20:
-		return TEGRA20;
-	case 0x30:
-		return TEGRA30;
-	case 0x40:
-		return TEGRA124;
-	default:
-		return TEGRA_UNK_REV;
-	}
-}
-
-static __always_inline
-u32 tegra_get_odmdata(void)
-{
-	u32 bctptr_offset, bctptr, odmdata_offset;
-	enum tegra_chiptype chiptype = tegra_get_chiptype();
-
-	switch(chiptype) {
-	case TEGRA20:
-		bctptr_offset = NV_BIT_BCTPTR_T20;
-		odmdata_offset = 4068;
-		break;
-	case TEGRA30:
-		bctptr_offset = NV_BIT_BCTPTR_T20;
-		odmdata_offset = 6116;
-		break;
-	case TEGRA114:
-		bctptr_offset = NV_BIT_BCTPTR_T114;
-		odmdata_offset = 1752;
-		break;
-	case TEGRA124:
-		bctptr_offset = NV_BIT_BCTPTR_T114;
-		odmdata_offset = 1704;
-		break;
-	default:
-		return 0;
-	}
-
-	bctptr = __raw_readl(TEGRA_IRAM_BASE + bctptr_offset);
-
-	return __raw_readl(bctptr + odmdata_offset);
-}
-
-static __always_inline
-int tegra_get_num_cores(void)
-{
-	switch (tegra_get_chiptype()) {
-	case TEGRA20:
-		return 2;
-	case TEGRA30:
-	case TEGRA124:
-		return 4;
-	default:
-		return 0;
-	}
-}
-
-/* Runtime data */
-static __always_inline
-int tegra_cpu_is_maincomplex(void)
-{
-	u32 tag0;
-
-	tag0 = readl(TEGRA_UP_TAG_BASE);
-
-	return (tag0 & 0xff) == 0x55;
-}
-
-static __always_inline
-uint32_t tegra20_get_ramsize(void)
-{
-	switch ((tegra_get_odmdata() & T20_ODMDATA_RAMSIZE_MASK) >>
-		T20_ODMDATA_RAMSIZE_SHIFT) {
-	case 1:
-		return SZ_256M;
-	default:
-	case 2:
-		return SZ_512M;
-	case 3:
-		return SZ_1G;
-	}
-}
-
-static __always_inline
-uint32_t tegra30_get_ramsize(void)
-{
-	switch ((tegra_get_odmdata() & T30_ODMDATA_RAMSIZE_MASK) >>
-			T20_ODMDATA_RAMSIZE_SHIFT) {
-	case 0:
-	case 1:
-	default:
-		return SZ_256M;
-	case 2:
-		return SZ_512M;
-	case 3:
-		return SZ_512M + SZ_256M;
-	case 4:
-		return SZ_1G;
-	case 8:
-		return SZ_2G - SZ_1M;
-	}
-}
-
-#define CRC_OSC_CTRL			0x050
-#define CRC_OSC_CTRL_OSC_FREQ_SHIFT	30
-#define CRC_OSC_CTRL_OSC_FREQ_MASK	(0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
-
-static __always_inline
-int tegra_get_osc_clock(void)
-{
-	u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL);
-
-	switch ((osc_ctrl & CRC_OSC_CTRL_OSC_FREQ_MASK) >>
-		CRC_OSC_CTRL_OSC_FREQ_SHIFT) {
-	case 0:
-		return 13000000;
-	case 1:
-		return 19200000;
-	case 2:
-		return 12000000;
-	case 3:
-		return 26000000;
-	default:
-		return 0;
-	}
-}
-
-#define TIMER_CNTR_1US	0x00
-#define TIMER_USEC_CFG	0x04
-
-static __always_inline
-void tegra_ll_delay_setup(void)
-{
-	u32 reg;
-
-	/*
-	 * calibrate timer to run at 1MHz
-	 * TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
-	 * representing the divisor and bits [8:15] representing the dividend
-	 * each in n+1 form.
-	 */
-	switch (tegra_get_osc_clock()) {
-	case 12000000:
-		reg = 0x000b;
-		break;
-	case 13000000:
-		reg = 0x000c;
-		break;
-	case 19200000:
-		reg = 0x045f;
-		break;
-	case 26000000:
-		reg = 0x0019;
-		break;
-	default:
-		reg = 0;
-		break;
-	}
-
-	writel(reg, TEGRA_TMRUS_BASE + TIMER_USEC_CFG);
-}
-
-static __always_inline
-void tegra_ll_delay_usec(int delay)
-{
-	int timeout = (int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) + delay;
-
-	while ((int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) - timeout < 0);
-}
-
-/* reset vector for the AVP, to be called from board reset vector */
-void tegra_avp_reset_vector(void);
-
-/* reset vector for the main CPU complex */
-void tegra_maincomplex_entry(char *fdt);
-
-static __always_inline
-void tegra_cpu_lowlevel_setup(char *fdt)
-{
-	uint32_t r;
-
-	/* set the cpu to SVC32 mode */
-	__asm__ __volatile__("mrs %0, cpsr":"=r"(r));
-	r &= ~0x1f;
-	r |= 0xd3;
-	__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
-
-	arm_setup_stack(TEGRA_IRAM_BASE + SZ_256K);
-
-	if (tegra_cpu_is_maincomplex())
-		tegra_maincomplex_entry(fdt + get_runtime_offset());
-
-	tegra_ll_delay_setup();
-}
-
-#endif /* __TEGRA_LOWLEVEL_H */
diff --git a/arch/arm/mach-tegra/include/mach/tegra-bbu.h b/arch/arm/mach-tegra/include/mach/tegra-bbu.h
deleted file mode 100644
index 32e2861ac6..0000000000
--- a/arch/arm/mach-tegra/include/mach/tegra-bbu.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2015 Lucas Stach <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <bbu.h>
-
-#ifdef CONFIG_BAREBOX_UPDATE
-int tegra_bbu_register_emmc_handler(const char *name, char *devicefile,
-				    unsigned long flags);
-#else
-static int tegra_bbu_register_emmc_handler(const char *name, char *devicefile,
-				    unsigned long flags)
-{
-	return 0;
-};
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra-powergate.h b/arch/arm/mach-tegra/include/mach/tegra-powergate.h
deleted file mode 100644
index e32250a7fa..0000000000
--- a/arch/arm/mach-tegra/include/mach/tegra-powergate.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2010 Google, Inc
- *
- * Author:
- *	Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_POWERGATE_H_
-#define _MACH_TEGRA_POWERGATE_H_
-
-struct clk;
-struct reset_control;
-
-#define TEGRA_POWERGATE_CPU	0
-#define TEGRA_POWERGATE_3D	1
-#define TEGRA_POWERGATE_VENC	2
-#define TEGRA_POWERGATE_PCIE	3
-#define TEGRA_POWERGATE_VDEC	4
-#define TEGRA_POWERGATE_L2	5
-#define TEGRA_POWERGATE_MPE	6
-#define TEGRA_POWERGATE_HEG	7
-#define TEGRA_POWERGATE_SATA	8
-#define TEGRA_POWERGATE_CPU1	9
-#define TEGRA_POWERGATE_CPU2	10
-#define TEGRA_POWERGATE_CPU3	11
-#define TEGRA_POWERGATE_CELP	12
-#define TEGRA_POWERGATE_3D1	13
-#define TEGRA_POWERGATE_CPU0	14
-#define TEGRA_POWERGATE_C0NC	15
-#define TEGRA_POWERGATE_C1NC	16
-#define TEGRA_POWERGATE_SOR	17
-#define TEGRA_POWERGATE_DIS	18
-#define TEGRA_POWERGATE_DISB	19
-#define TEGRA_POWERGATE_XUSBA	20
-#define TEGRA_POWERGATE_XUSBB	21
-#define TEGRA_POWERGATE_XUSBC	22
-#define TEGRA_POWERGATE_VIC	23
-#define TEGRA_POWERGATE_IRAM	24
-
-#define TEGRA_POWERGATE_3D0	TEGRA_POWERGATE_3D
-
-#define TEGRA_IO_RAIL_CSIA	0
-#define TEGRA_IO_RAIL_CSIB	1
-#define TEGRA_IO_RAIL_DSI	2
-#define TEGRA_IO_RAIL_MIPI_BIAS	3
-#define TEGRA_IO_RAIL_PEX_BIAS	4
-#define TEGRA_IO_RAIL_PEX_CLK1	5
-#define TEGRA_IO_RAIL_PEX_CLK2	6
-#define TEGRA_IO_RAIL_USB0	9
-#define TEGRA_IO_RAIL_USB1	10
-#define TEGRA_IO_RAIL_USB2	11
-#define TEGRA_IO_RAIL_USB_BIAS	12
-#define TEGRA_IO_RAIL_NAND	13
-#define TEGRA_IO_RAIL_UART	14
-#define TEGRA_IO_RAIL_BB	15
-#define TEGRA_IO_RAIL_AUDIO	17
-#define TEGRA_IO_RAIL_HSIC	19
-#define TEGRA_IO_RAIL_COMP	22
-#define TEGRA_IO_RAIL_HDMI	28
-#define TEGRA_IO_RAIL_PEX_CNTRL	32
-#define TEGRA_IO_RAIL_SDMMC1	33
-#define TEGRA_IO_RAIL_SDMMC3	34
-#define TEGRA_IO_RAIL_SDMMC4	35
-#define TEGRA_IO_RAIL_CAM	36
-#define TEGRA_IO_RAIL_RES	37
-#define TEGRA_IO_RAIL_HV	38
-#define TEGRA_IO_RAIL_DSIB	39
-#define TEGRA_IO_RAIL_DSIC	40
-#define TEGRA_IO_RAIL_DSID	41
-#define TEGRA_IO_RAIL_CSIE	44
-#define TEGRA_IO_RAIL_LVDS	57
-#define TEGRA_IO_RAIL_SYS_DDC	58
-
-int tegra_powergate_is_powered(int id);
-int tegra_powergate_power_on(int id);
-int tegra_powergate_power_off(int id);
-int tegra_powergate_remove_clamping(int id);
-
-/* Must be called with clk disabled, and returns with clk enabled */
-int tegra_powergate_sequence_power_up(int id, struct clk *clk,
-				      struct reset_control *rst);
-
-#endif /* _MACH_TEGRA_POWERGATE_H_ */
diff --git a/arch/arm/mach-tegra/include/mach/tegra114-sysctr.h b/arch/arm/mach-tegra/include/mach/tegra114-sysctr.h
deleted file mode 100644
index 45d17c4d97..0000000000
--- a/arch/arm/mach-tegra/include/mach/tegra114-sysctr.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Register definitions */
-#define TEGRA_SYSCTR0_CNTCR		0x00
-#define TEGRA_SYSCTR0_CNTCR_ENABLE	(1 << 0)
-#define TEGRA_SYSCTR0_CNTCR_HDBG	(1 << 1)
-
-#define TEGRA_SYSCTR0_CNTSR		0x04
-
-#define TEGRA_SYSCTR0_CNTCV0		0x08
-
-#define TEGRA_SYSCTR0_CNTCV1		0x0c
-
-#define TEGRA_SYSCTR0_CNTFID0		0x20
-
-#define TEGRA_SYSCTR0_CNTFID1		0x24
diff --git a/arch/arm/mach-tegra/include/mach/tegra124-car.h b/arch/arm/mach-tegra/include/mach/tegra124-car.h
deleted file mode 100644
index 1fb924d9f4..0000000000
--- a/arch/arm/mach-tegra/include/mach/tegra124-car.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Register definitions */
-#define CRC_PLLX_MISC_3			0x518
-#define CRC_PLLX_MISC_3_IDDQ		(1 << 3)
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h
deleted file mode 100644
index 5a35f21c1f..0000000000
--- a/arch/arm/mach-tegra/include/mach/tegra20-car.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Register definitions */
-#define CRC_CLK_OUT_ENB_L		0x010
-#define CRC_CLK_OUT_ENB_L_CACHE2	(1 << 31)
-#define CRC_CLK_OUT_ENB_L_VCP		(1 << 29)
-#define CRC_CLK_OUT_ENB_L_HOST1X	(1 << 28)
-#define CRC_CLK_OUT_ENB_L_DISP1		(1 << 27)
-#define CRC_CLK_OUT_ENB_L_DISP2		(1 << 26)
-#define CRC_CLK_OUT_ENB_L_IDE		(1 << 25)
-#define CRC_CLK_OUT_ENB_L_3D		(1 << 24)
-#define CRC_CLK_OUT_ENB_L_ISP		(1 << 23)
-#define CRC_CLK_OUT_ENB_L_USBD		(1 << 22)
-#define CRC_CLK_OUT_ENB_L_2D		(1 << 21)
-#define CRC_CLK_OUT_ENB_L_VI		(1 << 20)
-#define CRC_CLK_OUT_ENB_L_EPP		(1 << 19)
-#define CRC_CLK_OUT_ENB_L_I2S2		(1 << 18)
-#define CRC_CLK_OUT_ENB_L_PWM		(1 << 17)
-#define CRC_CLK_OUT_ENB_L_TWC		(1 << 16)
-#define CRC_CLK_OUT_ENB_L_SDMMC4	(1 << 15)
-#define CRC_CLK_OUT_ENB_L_SDMMC1	(1 << 14)
-#define CRC_CLK_OUT_ENB_L_NDFLASH	(1 << 13)
-#define CRC_CLK_OUT_ENB_L_I2C1		(1 << 12)
-#define CRC_CLK_OUT_ENB_L_I2S1		(1 << 11)
-#define CRC_CLK_OUT_ENB_L_SPDIF		(1 << 10)
-#define CRC_CLK_OUT_ENB_L_SDMMC2	(1 << 9)
-#define CRC_CLK_OUT_ENB_L_GPIO		(1 << 8)
-#define CRC_CLK_OUT_ENB_L_UART2		(1 << 7)
-#define CRC_CLK_OUT_ENB_L_UART1		(1 << 6)
-#define CRC_CLK_OUT_ENB_L_TMR		(1 << 5)
-#define CRC_CLK_OUT_ENB_L_RTC		(1 << 4)
-#define CRC_CLK_OUT_ENB_L_AC97		(1 << 3)
-#define CRC_CLK_OUT_ENB_L_CPU		(1 << 0)
-
-#define CRC_CLK_OUT_ENB_H		0x014
-#define CRC_CLK_OUT_ENB_H_DVC		(1 << 15)
-
-#define CRC_CLK_OUT_ENB_U		0x018
-
-#define CRC_CCLK_BURST_POLICY		0x020
-#define CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT	28
-#define CRC_CCLK_BURST_POLICY_SYS_STATE_FIQ	8
-#define CRC_CCLK_BURST_POLICY_SYS_STATE_IRQ	4
-#define CRC_CCLK_BURST_POLICY_SYS_STATE_RUN	2
-#define CRC_CCLK_BURST_POLICY_SYS_STATE_IDLE	1
-#define CRC_CCLK_BURST_POLICY_SYS_STATE_STDBY	0
-#define CRC_CCLK_BURST_POLICY_FIQ_SRC_SHIFT	12
-#define CRC_CCLK_BURST_POLICY_IRQ_SRC_SHIFT	8
-#define CRC_CCLK_BURST_POLICY_RUN_SRC_SHIFT	4
-#define CRC_CCLK_BURST_POLICY_IDLE_SRC_SHIFT	0
-#define CRC_CCLK_BURST_POLICY_SRC_CLKM		0
-#define CRC_CCLK_BURST_POLICY_SRC_PLLC_OUT0	1
-#define CRC_CCLK_BURST_POLICY_SRC_CLKS		2
-#define CRC_CCLK_BURST_POLICY_SRC_PLLM_OUT0	3
-#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT0	4
-#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT4	5
-#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT3	6
-#define CRC_CCLK_BURST_POLICY_SRC_CLKD		7
-#define CRC_CCLK_BURST_POLICY_SRC_PLLX_OUT0	8
-
-#define CRC_SUPER_CCLK_DIV		0x024
-#define CRC_SUPER_CDIV_ENB		(1 << 31)
-#define CRC_SUPER_CDIV_DIS_FROM_COP_FIQ	(1 << 27)
-#define CRC_SUPER_CDIV_DIS_FROM_CPU_FIQ	(1 << 26)
-#define CRC_SUPER_CDIV_DIS_FROM_COP_IRQ	(1 << 25)
-#define CRC_SUPER_CDIV_DIS_FROM_CPU_IRQ	(1 << 24)
-#define CRC_SUPER_CDIV_DIVIDEND_SHIFT	8
-#define CRC_SUPER_CDIV_DIVIDEND_MASK	(0xff << CRC_SUPER_CDIV_DIVIDEND_SHIFT)
-#define CRC_SUPER_CDIV_DIVISOR_SHIFT	0
-#define CRC_SUPER_CDIV_DIVISOR_MASK	(0xff << CRC_SUPER_CDIV_DIVISOR_SHIFT)
-
-#define CRC_SCLK_BURST_POLICY		0x028
-#define CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT	28
-#define CRC_SCLK_BURST_POLICY_SYS_STATE_FIQ	8
-#define CRC_SCLK_BURST_POLICY_SYS_STATE_IRQ	4
-#define CRC_SCLK_BURST_POLICY_SYS_STATE_RUN	2
-#define CRC_SCLK_BURST_POLICY_SYS_STATE_IDLE	1
-#define CRC_SCLK_BURST_POLICY_SYS_STATE_STDBY	0
-#define CRC_SCLK_BURST_POLICY_FIQ_SRC_SHIFT	12
-#define CRC_SCLK_BURST_POLICY_IRQ_SRC_SHIFT	8
-#define CRC_SCLK_BURST_POLICY_RUN_SRC_SHIFT	4
-#define CRC_SCLK_BURST_POLICY_IDLE_SRC_SHIFT	0
-#define CRC_SCLK_BURST_POLICY_SRC_CLKM		0
-#define CRC_SCLK_BURST_POLICY_SRC_PLLC_OUT1	1
-#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT4	2
-#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT3	3
-#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT2	4
-#define CRC_SCLK_BURST_POLICY_SRC_CLKD		5
-#define CRC_SCLK_BURST_POLICY_SRC_CLKS		6
-#define CRC_SCLK_BURST_POLICY_SRC_PLLM_OUT1	7
-
-#define CRC_SUPER_SCLK_DIV		0x02c
-#define CRC_SUPER_SDIV_ENB		(1 << 31)
-#define CRC_SUPER_SDIV_DIS_FROM_COP_FIQ	(1 << 27)
-#define CRC_SUPER_SDIV_DIS_FROM_CPU_FIQ	(1 << 26)
-#define CRC_SUPER_SDIV_DIS_FROM_COP_IRQ	(1 << 25)
-#define CRC_SUPER_SDIV_DIS_FROM_CPU_IRQ	(1 << 24)
-#define CRC_SUPER_SDIV_DIVIDEND_SHIFT	8
-#define CRC_SUPER_SDIV_DIVIDEND_MASK	(0xff << CRC_SUPER_SDIV_DIVIDEND_SHIFT)
-#define CRC_SUPER_SDIV_DIVISOR_SHIFT	0
-#define CRC_SUPER_SDIV_DIVISOR_MASK	(0xff << CRC_SUPER_SDIV_DIVISOR_SHIFT)
-
-#define CRC_CLK_SYSTEM_RATE		0x030
-#define CRC_CLK_SYSTEM_RATE_AHB_SHIFT	4
-#define CRC_CLK_SYSTEM_RATE_APB_SHIFT	0
-
-#define CRC_CLK_CPU_CMPLX		0x04c
-#define CRC_CLK_CPU_CMPLX_CPU3_CLK_STP	(1 << 11)
-#define CRC_CLK_CPU_CMPLX_CPU2_CLK_STP	(1 << 10)
-#define CRC_CLK_CPU_CMPLX_CPU1_CLK_STP	(1 << 9)
-#define CRC_CLK_CPU_CMPLX_CPU0_CLK_STP	(1 << 8)
-#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_SHIFT	0
-#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_4	3
-#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_3	2
-#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_2	1
-#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_1	0
-
-#define CRC_OSC_CTRL			0x050
-#define CRC_OSC_CTRL_OSC_FREQ_SHIFT	30
-#define CRC_OSC_CTRL_OSC_FREQ_MASK	(0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
-#define CRC_OSC_CTRL_PLL_REF_DIV_SHIFT	28
-#define CRC_OSC_CTRL_PLL_REF_DIV_MASK	(0x3 << CRC_OSC_CTRL_PLL_REF_DIV_SHIFT)
-
-#define CRC_PLL_BASE_LOCK		27
-#define CRC_PLLE_MISC_LOCK		11
-
-#define CRC_PLL_MISC_LOCK_ENABLE	18
-#define CRC_PLLDU_MISC_LOCK_ENABLE	22
-#define CRC_PLLE_MISC_LOCK_ENABLE	9
-
-#define CRC_PLLS_BASE			0x0f0
-#define CRC_PLLS_MISC			0x0f4
-
-#define CRC_PLLC_BASE			0x080
-#define CRC_PLLC_OUT			0x084
-#define CRC_PLLC_MISC			0x08c
-
-#define CRC_PLLM_BASE			0x090
-#define CRC_PLLM_OUT			0x094
-#define CRC_PLLM_MISC			0x09c
-
-#define CRC_PLLP_BASE			0x0a0
-#define CRC_PLLP_OUTA			0x0a4
-#define CRC_PLLP_OUTB			0x0a8
-#define CRC_PLLP_MISC			0x0ac
-
-#define CRC_PLLA_BASE			0x0b0
-#define CRC_PLLA_OUT			0x0b4
-#define CRC_PLLA_MISC			0x0bc
-
-#define CRC_PLLU_BASE			0x0c0
-#define CRC_PLLU_MISC			0x0cc
-
-#define CRC_PLLD_BASE			0x0d0
-#define CRC_PLLD_MISC			0x0dc
-
-#define CRC_PLLX_BASE			0x0e0
-#define CRC_PLLX_BASE_BYPASS		(1 << 31)
-#define CRC_PLLX_BASE_ENABLE		(1 << 30)
-#define CRC_PLLX_BASE_REF_DIS		(1 << 29)
-#define CRC_PLLX_BASE_LOCK		(1 << 27)
-#define CRC_PLLX_BASE_DIVP_SHIFT	20
-#define CRC_PLLX_BASE_DIVP_MASK		(0x7 << CRC_PLLX_BASE_DIVP_SHIFT)
-#define CRC_PLLX_BASE_DIVN_SHIFT	8
-#define CRC_PLLX_BASE_DIVN_MASK		(0x3ff << CRC_PLLX_BASE_DIVN_SHIFT)
-#define CRC_PLLX_BASE_DIVM_SHIFT	0
-#define CRC_PLLX_BASE_DIVM_MASK		(0xf << CRC_PLLX_BASE_DIVM_SHIFT)
-
-#define CRC_PLLX_MISC			0x0e4
-#define CRC_PLLX_MISC_SETUP_SHIFT	24
-#define CRC_PLLX_MISC_SETUP_MASK	(0xf << CRC_PLLX_MISC_SETUP_SHIFT)
-#define CRC_PLLX_MISC_PTS_SHIFT		22
-#define CRC_PLLX_MISC_PTS_MASK		(0x3 << CRC_PLLX_MISC_PTS_SHIFT)
-#define CRC_PLLX_MISC_DCCON		(1 << 20)
-#define CRC_PLLX_MISC_LOCK_ENABLE	(1 << 18)
-#define CRC_PLLX_MISC_LOCK_SEL_SHIFT	12
-#define CRC_PLLX_MISC_LOCK_SEL_MASK	(0x3f << CRC_PLLX_MISC_LOCK_SEL_SHIFT)
-#define CRC_PLLX_MISC_CPCON_SHIFT	8
-#define CRC_PLLX_MISC_CPCON_MASK	(0xf << CRC_PLLX_MISC_CPCON_SHIFT)
-#define CRC_PLLX_MISC_LFCON_SHIFT	4
-#define CRC_PLLX_MISC_LFCON_MASK	(0xf << CRC_PLLX_MISC_LFCON_SHIFT)
-#define CRC_PLLX_MISC_VCOCON_SHIFT	0
-#define CRC_PLLX_MISC_VCOCON_MASK	(0xf << CRC_PLLX_MISC_VCOCON_SHIFT)
-
-#define CRC_PLLE_BASE			0x0e8
-#define CRC_PLLE_MISC			0x0ec
-
-#define CRC_CLK_SOURCE_I2S1		0x100
-#define CRC_CLK_SOURCE_I2S2		0x104
-#define CRC_CLK_SOURCE_SPDIF_OUT	0x108
-#define CRC_CLK_SOURCE_SPDIF_IN		0x10c
-#define CRC_CLK_SOURCE_PWM		0x110
-#define CRC_CLK_SOURCE_SPI		0x114
-#define CRC_CLK_SOURCE_SBC1		0x134
-#define CRC_CLK_SOURCE_SBC2		0x118
-#define CRC_CLK_SOURCE_SBC3		0x11c
-#define CRC_CLK_SOURCE_SBC4		0x1b4
-#define CRC_CLK_SOURCE_XIO		0x120
-#define CRC_CLK_SOURCE_TWC		0x12c
-#define CRC_CLK_SOURCE_IDE		0x144
-#define CRC_CLK_SOURCE_NDFLASH		0x160
-#define CRC_CLK_SOURCE_VFIR		0x168
-#define CRC_CLK_SOURCE_SDMMC1		0x150
-#define CRC_CLK_SOURCE_SDMMC2		0x154
-#define CRC_CLK_SOURCE_SDMMC3		0x1bc
-#define CRC_CLK_SOURCE_SDMMC4		0x164
-#define CRC_CLK_SOURCE_CVE		0x140
-#define CRC_CLK_SOURCE_TVO		0x188
-#define CRC_CLK_SOURCE_TVDAC		0x194
-#define CRC_CLK_SOURCE_HDMI		0x18c
-#define CRC_CLK_SOURCE_DISP1		0x138
-#define CRC_CLK_SOURCE_DISP2		0x13c
-#define CRC_CLK_SOURCE_CSITE		0x1d4
-#define CRC_CLK_SOURCE_LA		0x1f8
-#define CRC_CLK_SOURCE_OWR		0x1cc
-#define CRC_CLK_SOURCE_NOR		0x1d0
-#define CRC_CLK_SOURCE_MIPI		0x174
-#define CRC_CLK_SOURCE_I2C1		0x124
-#define CRC_CLK_SOURCE_I2C2		0x198
-#define CRC_CLK_SOURCE_I2C3		0x1b8
-#define CRC_CLK_SOURCE_DVC		0x128
-#define CRC_CLK_SOURCE_UARTA		0x178
-#define CRC_CLK_SOURCE_UARTB		0x17c
-#define CRC_CLK_SOURCE_UARTC		0x1a0
-#define CRC_CLK_SOURCE_UARTD		0x1c0
-#define CRC_CLK_SOURCE_UARTE		0x1c4
-#define CRC_CLK_SOURCE_3D		0x158
-#define CRC_CLK_SOURCE_2D		0x15c
-#define CRC_CLK_SOURCE_MPE		0x170
-#define CRC_CLK_SOURCE_EPP		0x16c
-#define CRC_CLK_SOURCE_HOST1X		0x180
-#define CRC_CLK_SOURCE_VDE		0x1c8
-#define CRC_CLK_SOURCE_VI		0x148
-#define CRC_CLK_SOURCE_VI_SENSOR	0x1a8
-#define CRC_CLK_SOURCE_EMC		0x19c
-
-#define CRC_RST_DEV_L_SET		0x300
-#define CRC_RST_DEV_L_CACHE2		(1 << 31)
-#define CRC_RST_DEV_L_VCP		(1 << 29)
-#define CRC_RST_DEV_L_HOST1X		(1 << 28)
-#define CRC_RST_DEV_L_DISP1		(1 << 27)
-#define CRC_RST_DEV_L_DISP2		(1 << 26)
-#define CRC_RST_DEV_L_IDE		(1 << 25)
-#define CRC_RST_DEV_L_3D		(1 << 24)
-#define CRC_RST_DEV_L_ISP		(1 << 23)
-#define CRC_RST_DEV_L_USBD		(1 << 22)
-#define CRC_RST_DEV_L_2D		(1 << 21)
-#define CRC_RST_DEV_L_VI		(1 << 20)
-#define CRC_RST_DEV_L_EPP		(1 << 19)
-#define CRC_RST_DEV_L_I2S2		(1 << 18)
-#define CRC_RST_DEV_L_PWM		(1 << 17)
-#define CRC_RST_DEV_L_TWC		(1 << 16)
-#define CRC_RST_DEV_L_SDMMC4		(1 << 15)
-#define CRC_RST_DEV_L_SDMMC1		(1 << 14)
-#define CRC_RST_DEV_L_NDFLASH		(1 << 13)
-#define CRC_RST_DEV_L_I2C1		(1 << 12)
-#define CRC_RST_DEV_L_I2S1		(1 << 11)
-#define CRC_RST_DEV_L_SPDIF		(1 << 10)
-#define CRC_RST_DEV_L_SDMMC2		(1 << 9)
-#define CRC_RST_DEV_L_GPIO		(1 << 8)
-#define CRC_RST_DEV_L_UART2		(1 << 7)
-#define CRC_RST_DEV_L_UART1		(1 << 6)
-#define CRC_RST_DEV_L_TMR		(1 << 5)
-#define CRC_RST_DEV_L_AC97		(1 << 3)
-#define CRC_RST_DEV_L_SYS		(1 << 2)
-#define CRC_RST_DEV_L_COP		(1 << 1)
-#define CRC_RST_DEV_L_CPU		(1 << 0)
-
-#define CRC_RST_DEV_L_CLR		0x304
-
-#define CRC_RST_DEV_H_SET		0x308
-#define CRC_RST_DEV_H_DVC		(1 << 15)
-
-#define CRC_RST_DEV_H_CLR		0x30c
-
-#define CRC_RST_CPU_CMPLX_SET		0x340
-
-#define CRC_RST_CPU_CMPLX_CLR		0x344
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-pmc.h b/arch/arm/mach-tegra/include/mach/tegra20-pmc.h
deleted file mode 100644
index c379544755..0000000000
--- a/arch/arm/mach-tegra/include/mach/tegra20-pmc.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* register definitions */
-#define PMC_CNTRL			0x000
-#define PMC_CNTRL_FUSE_OVERRIDE		(1 << 18)
-#define PMC_CNTRL_INTR_POLARITY		(1 << 17)
-#define PMC_CNTRL_CPUPWRREQ_OE		(1 << 16)
-#define PMC_CNTRL_CPUPWRREQ_POLARITY	(1 << 15)
-#define PMC_CNTRL_SIDE_EFFECT_LP0	(1 << 14)
-#define PMC_CNTRL_AOINIT		(1 << 13)
-#define PMC_CNTRL_PWRGATE_DIS		(1 << 12)
-#define PMC_CNTRL_SYSCLK_OE		(1 << 11)
-#define PMC_CNTRL_SYSCLK_POLARITY	(1 << 10)
-#define PMC_CNTRL_PWRREQ_OE		(1 << 9)
-#define PMC_CNTRL_PWRREQ_POLARITY	(1 << 8)
-#define PMC_CNTRL_BLINK_EN		(1 << 7)
-#define PMC_CNTRL_GLITCHDET_DIS		(1 << 6)
-#define PMC_CNTRL_LATCHWAKE_EN		(1 << 5)
-#define PMC_CNTRL_MAIN_RST		(1 << 4)
-#define PMC_CNTRL_KBC_RST		(1 << 3)
-#define PMC_CNTRL_RTC_RST		(1 << 2)
-#define PMC_CNTRL_RTC_CLK_DIS		(1 << 1)
-#define PMC_CNTRL_KBC_CLK_DIS		(1 << 0)
-
-#define PMC_PWRGATE_TOGGLE		0x030
-#define PMC_PWRGATE_TOGGLE_PARTID_SHIFT	0
-#define PMC_PWRGATE_TOGGLE_PARTID_MASK	(0x3 << PMC_PWRGATE_TOGGLE_PARTID_SHIFT)
-#define PMC_PWRGATE_TOGGLE_PARTID_CPU	0
-#define PMC_PWRGATE_TOGGLE_PARTID_TD	1
-#define PMC_PWRGATE_TOGGLE_PARTID_VE	2
-#define PMC_PWRGATE_TOGGLE_PARTID_PCX	3
-#define PMC_PWRGATE_TOGGLE_PARTID_VDE	4
-#define PMC_PWRGATE_TOGGLE_PARTID_L2C	5
-#define PMC_PWRGATE_TOGGLE_PARTID_MPE	6
-#define PMC_PWRGATE_TOGGLE_START	(1 << 8)
-
-#define PMC_REMOVE_CLAMPING_CMD		0x034
-#define PMC_REMOVE_CLAMPING_CMD_MPE	(1 << 6)
-#define PMC_REMOVE_CLAMPING_CMD_L2C	(1 << 5)
-#define PMC_REMOVE_CLAMPING_CMD_PCX	(1 << 4)
-#define PMC_REMOVE_CLAMPING_CMD_VDE	(1 << 3)
-#define PMC_REMOVE_CLAMPING_CMD_VE	(1 << 2)
-#define PMC_REMOVE_CLAMPING_CMD_TD	(1 << 1)
-#define PMC_REMOVE_CLAMPING_CMD_CPU	(1 << 0)
-
-#define PMC_PWRGATE_STATUS		0x038
-#define PMC_PWRGATE_STATUS_MPE		(1 << 6)
-#define PMC_PWRGATE_STATUS_L2C		(1 << 5)
-#define PMC_PWRGATE_STATUS_VDE		(1 << 4)
-#define PMC_PWRGATE_STATUS_PCX		(1 << 3)
-#define PMC_PWRGATE_STATUS_VE		(1 << 2)
-#define PMC_PWRGATE_STATUS_TD		(1 << 1)
-#define PMC_PWRGATE_STATUS_CPU		(1 << 0)
-
-#define PMC_PARTID_CRAIL		0
-#define PMC_PARTID_CE0			14
-#define PMC_PARTID_C0NC			15
-
-#define PMC_SCRATCH(i)			(0x050 + 0x4*i)
-
-#define PMC_RST_STATUS			0x1b4
-#define PMC_RST_STATUS_RST_SRC_SHIFT	0
-#define PMC_RST_STATUS_RST_SRC_MASK	(0x7 << PMC_RST_STATUS_RST_SRC_SHIFT)
-#define PMC_RST_STATUS_RST_SRC_POR	0
-#define PMC_RST_STATUS_RST_SRC_WATCHDOG	1
-#define PMC_RST_STATUS_RST_SRC_SENSOR	2
-#define PMC_RST_STATUS_RST_SRC_SW_MAIN	3
-#define PMC_RST_STATUS_RST_SRC_LP0	4
diff --git a/arch/arm/mach-tegra/include/mach/tegra30-car.h b/arch/arm/mach-tegra/include/mach/tegra30-car.h
deleted file mode 100644
index 7fb2238dc9..0000000000
--- a/arch/arm/mach-tegra/include/mach/tegra30-car.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Register definitions */
-#define CRC_CLK_OUT_ENB_V		0x360
-#define CRC_CLK_OUT_ENB_V_MSELECT	(1 << 3)
-
-#define CRC_CLK_SOURCE_MSEL		0x3b4
-#define CRC_CLK_SOURCE_MSEL_SRC_SHIFT	30
-#define CRC_CLK_SOURCE_MSEL_SRC_PLLP	0
-#define CRC_CLK_SOURCE_MSEL_SRC_PLLC	1
-#define CRC_CLK_SOURCE_MSEL_SRC_PLLM	2
-#define CRC_CLK_SOURCE_MSEL_SRC_CLKM	3
-
-#define CRC_CLK_SOURCE_I2C4		0x3c4
-
-#define CRC_RST_DEV_V_SET		0x430
-#define CRC_RST_DEV_V_MSELECT		(1 << 3)
-
-#define CRC_RST_DEV_V_CLR		0x434
-
-#define CRC_CLK_OUT_ENB_V_SET		0x440
-
-#define CRC_PLLE_AUX			0x48c
diff --git a/arch/arm/mach-tegra/include/mach/tegra30-flow.h b/arch/arm/mach-tegra/include/mach/tegra30-flow.h
deleted file mode 100644
index 50a3030e5e..0000000000
--- a/arch/arm/mach-tegra/include/mach/tegra30-flow.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#define FLOW_HALT_CPU_EVENTS		0x000
-#define FLOW_MODE_NONE			0
-#define FLOW_MODE_STOP			2
-
-#define FLOW_CLUSTER_CONTROL		0x02c
-#define FLOW_CLUSTER_CONTROL_ACTIVE_G	(0 << 0)
-#define FLOW_CLUSTER_CONTROL_ACTIVE_LP	(1 << 0)
diff --git a/arch/arm/mach-tegra/tegra-bbu.c b/arch/arm/mach-tegra/tegra-bbu.c
index 089e6c736a..0a59da04db 100644
--- a/arch/arm/mach-tegra/tegra-bbu.c
+++ b/arch/arm/mach-tegra/tegra-bbu.c
@@ -17,7 +17,7 @@
 #include <common.h>
 #include <fcntl.h>
 #include <fs.h>
-#include <mach/tegra-bbu.h>
+#include <mach/tegra/tegra-bbu.h>
 #include <malloc.h>
 
 static int tegra_bbu_emmc_handler(struct bbu_handler *handler,
diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c
index a252c995ea..11fd8c28be 100644
--- a/arch/arm/mach-tegra/tegra20-pmc.c
+++ b/arch/arm/mach-tegra/tegra20-pmc.c
@@ -27,11 +27,11 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/reset.h>
-#include <mach/lowlevel.h>
-#include <mach/tegra-powergate.h>
+#include <mach/tegra/lowlevel.h>
+#include <mach/tegra/tegra-powergate.h>
 #include <reset_source.h>
 
-#include <mach/tegra20-pmc.h>
+#include <mach/tegra/tegra20-pmc.h>
 
 static void __iomem *pmc_base;
 static int tegra_num_powerdomains;
@@ -200,7 +200,7 @@ static void tegra20_pmc_detect_reset_cause(void)
 	}
 }
 
-static int tegra20_pmc_probe(struct device_d *dev)
+static int tegra20_pmc_probe(struct device *dev)
 {
 	struct resource *iores;
 	iores = dev_request_mem_resource(dev, 0);
@@ -237,8 +237,9 @@ static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
 		/* sentinel */
 	}
 };
+MODULE_DEVICE_TABLE(of, tegra20_pmc_dt_ids);
 
-static struct driver_d tegra20_pmc_driver = {
+static struct driver tegra20_pmc_driver = {
 	.probe	= tegra20_pmc_probe,
 	.name	= "tegra20-pmc",
 	.of_compatible = DRV_OF_COMPAT(tegra20_pmc_dt_ids),
diff --git a/arch/arm/mach-tegra/tegra20-timer.c b/arch/arm/mach-tegra/tegra20-timer.c
index 34d34f7723..e3cd216f30 100644
--- a/arch/arm/mach-tegra/tegra20-timer.c
+++ b/arch/arm/mach-tegra/tegra20-timer.c
@@ -25,7 +25,7 @@
 #include <io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <mach/lowlevel.h>
+#include <mach/tegra/lowlevel.h>
 
 /* register definitions */
 #define TIMERUS_CNTR_1US	0x10
@@ -41,9 +41,10 @@ static uint64_t tegra20_timer_cs_read(void)
 static struct clocksource cs = {
 	.read	= tegra20_timer_cs_read,
 	.mask	= CLOCKSOURCE_MASK(32),
+	.priority = 80,
 };
 
-static int tegra20_timer_probe(struct device_d *dev)
+static int tegra20_timer_probe(struct device *dev)
 {
 	struct resource *iores;
 	u32 reg;
@@ -97,8 +98,9 @@ static __maybe_unused struct of_device_id tegra20_timer_dt_ids[] = {
 		/* sentinel */
 	}
 };
+MODULE_DEVICE_TABLE(of, tegra20_timer_dt_ids);
 
-static struct driver_d tegra20_timer_driver = {
+static struct driver tegra20_timer_driver = {
 	.probe	= tegra20_timer_probe,
 	.name	= "tegra20-timer",
 	.of_compatible = DRV_OF_COMPAT(tegra20_timer_dt_ids),
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index 10c149a955..d27f775cf9 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -17,9 +17,9 @@
 #include <common.h>
 #include <init.h>
 #include <asm/memory.h>
-#include <mach/iomap.h>
-#include <mach/lowlevel.h>
-#include <mach/tegra114-sysctr.h>
+#include <mach/tegra/iomap.h>
+#include <mach/tegra/lowlevel.h>
+#include <mach/tegra/tegra114-sysctr.h>
 
 static int tegra20_mem_init(void)
 {
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 8a11e06c53..021bcb6d95 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -20,12 +20,12 @@
 #include <common.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/lowlevel.h>
-#include <mach/tegra20-car.h>
-#include <mach/tegra20-pmc.h>
-#include <mach/tegra30-car.h>
-#include <mach/tegra30-flow.h>
-#include <mach/tegra124-car.h>
+#include <mach/tegra/lowlevel.h>
+#include <mach/tegra/tegra20-car.h>
+#include <mach/tegra/tegra20-pmc.h>
+#include <mach/tegra/tegra30-car.h>
+#include <mach/tegra/tegra30-flow.h>
+#include <mach/tegra/tegra124-car.h>
 
 /* instruct the PMIC to enable the CPU power rail */
 static void enable_maincomplex_powerrail(void)
diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c b/arch/arm/mach-tegra/tegra_maincomplex_init.c
index 27bb3363a3..2a2272a99f 100644
--- a/arch/arm/mach-tegra/tegra_maincomplex_init.c
+++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c
@@ -19,9 +19,9 @@
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <asm/errata.h>
-#include <mach/lowlevel.h>
-#include <mach/tegra20-pmc.h>
-#include <mach/tegra20-car.h>
+#include <mach/tegra/lowlevel.h>
+#include <mach/tegra/tegra20-pmc.h>
+#include <mach/tegra/tegra20-car.h>
 
 void tegra_maincomplex_entry(char *fdt)
 {
diff --git a/arch/arm/mach-uemd/Kconfig b/arch/arm/mach-uemd/Kconfig
index 2bcdd320c9..7844b9c78f 100644
--- a/arch/arm/mach-uemd/Kconfig
+++ b/arch/arm/mach-uemd/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_UEMD
 
 config ARCH_TEXT_BASE
diff --git a/arch/arm/mach-uemd/Makefile b/arch/arm/mach-uemd/Makefile
index 16a218658a..1c2b374603 100644
--- a/arch/arm/mach-uemd/Makefile
+++ b/arch/arm/mach-uemd/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj- := __dummy__.o
diff --git a/arch/arm/mach-uemd/include/mach/debug_ll.h b/arch/arm/mach-uemd/include/mach/debug_ll.h
deleted file mode 100644
index a565b67275..0000000000
--- a/arch/arm/mach-uemd/include/mach/debug_ll.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-/** @file
- *  This File contains declaration for early output support
- */
-#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
-#define __INCLUDE_ARCH_DEBUG_LL_H__
-
-#include <asm/io.h>
-#include <mach/hardware.h>
-
-#define DEBUG_LL_UART_ADDR	UEMD_UART0_BASE
-#define DEBUG_LL_UART_RSHFT	2
-
-#define rbr		(0 << DEBUG_LL_UART_RSHFT)
-#define lsr		(5 << DEBUG_LL_UART_RSHFT)
-#define LSR_THRE	0x20	/* Xmit holding register empty */
-
-static inline void PUTC_LL(char ch)
-{
-	while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE))
-		;
-
-	__raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
-}
-
-#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-uemd/include/mach/hardware.h b/arch/arm/mach-uemd/include/mach/hardware.h
deleted file mode 100644
index 2311ebf1cd..0000000000
--- a/arch/arm/mach-uemd/include/mach/hardware.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define UEMD_EHCI_BASE	0x10040000
-#define UEMD_UART0_BASE	0x2002b000
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index 95172cff8c..89f50c270e 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 if ARCH_VERSATILE
 
@@ -8,21 +9,9 @@ config MACH_VERSATILEPB
 	bool
 	default y
 	select ARM_AMBA
-	select CLKDEV_LOOKUP
-
-choice
-	prompt "ARM Board type"
-
-config MACH_VERSATILEPB_926T
-	bool "ARM Versatile/PB (ARM926EJ-S)"
 	select CPU_ARM926T
-
-config MACH_VERSATILEPB_ARM1176
-	bool "ARM Versatile/PB (ARM1176)"
 	select CPU_ARM1176
 
-endchoice
-
 source "arch/arm/boards/versatile/Kconfig"
 
 endif
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index a8da54c27b..6a9630115f 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -1,2 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
 
 obj-y += core.o
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index eb94a07dc9..b0124b700c 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -35,144 +35,11 @@
 #include <linux/amba/bus.h>
 
 #include <io.h>
-#include <asm/hardware/arm_timer.h>
 #include <asm/armlinux.h>
 
-#include <mach/platform.h>
-#include <mach/init.h>
+#include <mach/versatile/platform.h>
 
-struct clk {
-	unsigned long rate;
-};
-
-static struct clk ref_clk_dummy;
-
-static struct clk ref_clk_24 = {
-	.rate = 24000000,
-};
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/* enable and disable do nothing */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_enable(struct clk *clk)
-{
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-/* 1Mhz / 256 */
-#define TIMER_FREQ (1000000/256)
-
-#define TIMER0_BASE (VERSATILE_TIMER0_1_BASE)
-#define TIMER1_BASE ((VERSATILE_TIMER0_1_BASE) + 0x20)
-#define TIMER2_BASE (VERSATILE_TIMER2_3_BASE)
-#define TIMER3_BASE ((VERSATILE_TIMER2_3_BASE) + 0x20)
-
-static uint64_t vpb_clocksource_read(void)
-{
-	return ~readl(TIMER0_BASE + TIMER_VALUE);
-}
-
-static struct clocksource vpb_cs = {
-	.read = vpb_clocksource_read,
-	.mask = CLOCKSOURCE_MASK(32),
-	.shift = 10,
-};
-
-/* From Linux v2.6.35
- * arch/arm/mach-versatile/core.c */
-static void versatile_timer_init (void)
-{
-	u32 val;
-
-	/*
-	 * set clock frequency:
-	 *      VERSATILE_REFCLK is 32KHz
-	 *      VERSATILE_TIMCLK is 1MHz
-	 */
-
-	val = readl(VERSATILE_SCTL_BASE);
-	val |= (VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel);
-	writel(val, VERSATILE_SCTL_BASE);
-
-	/*
-	 * Disable all timers, just to be sure.
-	 */
-
-	writel(0, TIMER0_BASE + TIMER_CTRL);
-	writel(0, TIMER1_BASE + TIMER_CTRL);
-	writel(0, TIMER2_BASE + TIMER_CTRL);
-	writel(0, TIMER3_BASE + TIMER_CTRL);
-
-	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_DIV256,
-					TIMER0_BASE + TIMER_CTRL);
-}
-
-static int vpb_clocksource_init(void)
-{
-	versatile_timer_init();
-	vpb_cs.mult = clocksource_hz2mult(TIMER_FREQ, vpb_cs.shift);
-
-	return init_clock(&vpb_cs);
-}
-
-core_initcall(vpb_clocksource_init);
-
-static struct clk_lookup clocks_lookups[] = {
-	CLKDEV_CON_ID("apb_pclk", &ref_clk_dummy),
-	CLKDEV_DEV_ID("uart-pl0110", &ref_clk_24),
-	CLKDEV_DEV_ID("uart-pl0111", &ref_clk_24),
-	CLKDEV_DEV_ID("uart-pl0112", &ref_clk_24),
-	CLKDEV_DEV_ID("uart-pl0113", &ref_clk_24),
-};
-
-static int versatile_clkdev_init(void)
-{
-	clkdev_add_table(clocks_lookups, ARRAY_SIZE(clocks_lookups));
-
-	return 0;
-}
-postcore_initcall(versatile_clkdev_init);
-
-void versatile_register_uart(unsigned id)
-{
-	resource_size_t start;
-
-	switch (id) {
-	case 0:
-		start = VERSATILE_UART0_BASE;
-		break;
-	case 1:
-		start = VERSATILE_UART1_BASE;
-		break;
-	case 2:
-		start = VERSATILE_UART2_BASE;
-		break;
-	case 3:
-		start = VERSATILE_UART3_BASE;
-		break;
-	default:
-		return;
-	}
-	amba_apb_device_add(NULL, "uart-pl011", id, start, 4096, NULL, 0);
-}
-
-static void versatile_reset_soc(struct restart_handler *rst)
+static void __noreturn versatile_reset_soc(struct restart_handler *rst)
 {
 	u32 val;
 
@@ -188,11 +55,11 @@ static void versatile_reset_soc(struct restart_handler *rst)
 
 static int versatile_init(void)
 {
-	amba_apb_device_add(NULL, "pl061_gpio", 0, 0x101e4000, 4096, NULL, 0);
-	amba_apb_device_add(NULL, "pl061_gpio", 1, 0x101e5000, 4096, NULL, 0);
-	amba_apb_device_add(NULL, "pl061_gpio", 2, 0x101e6000, 4096, NULL, 0);
-	amba_apb_device_add(NULL, "pl061_gpio", 3, 0x101e7000, 4096, NULL, 0);
+	if (!of_machine_is_compatible("arm,versatile-pb") &&
+	    !of_machine_is_compatible("arm,versatile-ab"))
+		return 0;
+
 	restart_handler_register_fn("soc", versatile_reset_soc);
 	return 0;
 }
-coredevice_initcall(versatile_init);
+core_initcall(versatile_init);
diff --git a/arch/arm/mach-versatile/include/mach/debug_ll.h b/arch/arm/mach-versatile/include/mach/debug_ll.h
deleted file mode 100644
index 073402c51a..0000000000
--- a/arch/arm/mach-versatile/include/mach/debug_ll.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2010 B Labs Ltd
- * Author: Alexey Zaytsev <alexey.zaytsev@gmail.com>
- *
- * barebox is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * barebox is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_DEBUG_LL_H__
-#define   __MACH_DEBUG_LL_H__
-
-#define DEBUG_LL_UART_ADDR 0x101F1000
-
-#include <debug_ll/pl011.h>
-
-#endif
diff --git a/arch/arm/mach-versatile/include/mach/init.h b/arch/arm/mach-versatile/include/mach/init.h
deleted file mode 100644
index acb0f660a2..0000000000
--- a/arch/arm/mach-versatile/include/mach/init.h
+++ /dev/null
@@ -1,7 +0,0 @@
-
-#ifndef __VERSATILE_INIT_H__
-#define __VERSATILE_INIT_H__
-
-void versatile_register_uart(unsigned id);
-
-#endif
diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h
deleted file mode 100644
index 6f4b00360f..0000000000
--- a/arch/arm/mach-versatile/include/mach/platform.h
+++ /dev/null
@@ -1,402 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* SPDX-FileCopyrightText: 2003 ARM Limited */
-
-/*
- * Borrowed from Linux v2.6.35
- * arch/arm/mach-versatile/include/mach/platform.h
- */
-
-#ifndef __address_h
-#define __address_h                     1
-
-/*
- * Memory definitions
- */
-#define VERSATILE_BOOT_ROM_LO          0x30000000		/* DoC Base (64Mb)...*/
-#define VERSATILE_BOOT_ROM_HI          0x30000000
-#define VERSATILE_BOOT_ROM_BASE        VERSATILE_BOOT_ROM_HI	 /*  Normal position */
-#define VERSATILE_BOOT_ROM_SIZE        SZ_64M
-
-#define VERSATILE_SSRAM_BASE           /* VERSATILE_SSMC_BASE ? */
-#define VERSATILE_SSRAM_SIZE           SZ_2M
-
-#define VERSATILE_FLASH_BASE           0x34000000
-#define VERSATILE_FLASH_SIZE           SZ_64M
-
-/*
- *  SDRAM
- */
-#define VERSATILE_SDRAM_BASE           0x00000000
-
-/*
- *  Logic expansion modules
- *
- */
-
-
-/* ------------------------------------------------------------------------
- *  Versatile Registers
- * ------------------------------------------------------------------------
- *
- */
-#define VERSATILE_SYS_ID_OFFSET               0x00
-#define VERSATILE_SYS_SW_OFFSET               0x04
-#define VERSATILE_SYS_LED_OFFSET              0x08
-#define VERSATILE_SYS_OSC0_OFFSET             0x0C
-
-#if defined(CONFIG_ARCH_VERSATILE_PB)
-#define VERSATILE_SYS_OSC1_OFFSET             0x10
-#define VERSATILE_SYS_OSC2_OFFSET             0x14
-#define VERSATILE_SYS_OSC3_OFFSET             0x18
-#define VERSATILE_SYS_OSC4_OFFSET             0x1C
-#elif defined(CONFIG_MACH_VERSATILE_AB)
-#define VERSATILE_SYS_OSC1_OFFSET             0x1C
-#endif
-
-#define VERSATILE_SYS_OSCCLCD_OFFSET          0x1c
-
-#define VERSATILE_SYS_LOCK_OFFSET             0x20
-#define VERSATILE_SYS_100HZ_OFFSET            0x24
-#define VERSATILE_SYS_CFGDATA1_OFFSET         0x28
-#define VERSATILE_SYS_CFGDATA2_OFFSET         0x2C
-#define VERSATILE_SYS_FLAGS_OFFSET            0x30
-#define VERSATILE_SYS_FLAGSSET_OFFSET         0x30
-#define VERSATILE_SYS_FLAGSCLR_OFFSET         0x34
-#define VERSATILE_SYS_NVFLAGS_OFFSET          0x38
-#define VERSATILE_SYS_NVFLAGSSET_OFFSET       0x38
-#define VERSATILE_SYS_NVFLAGSCLR_OFFSET       0x3C
-#define VERSATILE_SYS_RESETCTL_OFFSET         0x40
-#define VERSATILE_SYS_PCICTL_OFFSET           0x44
-#define VERSATILE_SYS_MCI_OFFSET              0x48
-#define VERSATILE_SYS_FLASH_OFFSET            0x4C
-#define VERSATILE_SYS_CLCD_OFFSET             0x50
-#define VERSATILE_SYS_CLCDSER_OFFSET          0x54
-#define VERSATILE_SYS_BOOTCS_OFFSET           0x58
-#define VERSATILE_SYS_24MHz_OFFSET            0x5C
-#define VERSATILE_SYS_MISC_OFFSET             0x60
-#define VERSATILE_SYS_TEST_OSC0_OFFSET        0x80
-#define VERSATILE_SYS_TEST_OSC1_OFFSET        0x84
-#define VERSATILE_SYS_TEST_OSC2_OFFSET        0x88
-#define VERSATILE_SYS_TEST_OSC3_OFFSET        0x8C
-#define VERSATILE_SYS_TEST_OSC4_OFFSET        0x90
-
-#define VERSATILE_SYS_BASE                    0x10000000
-#define VERSATILE_SYS_ID                      (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
-#define VERSATILE_SYS_SW                      (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
-#define VERSATILE_SYS_LED                     (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
-#define VERSATILE_SYS_OSC0                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
-#define VERSATILE_SYS_OSC1                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
-
-#if defined(CONFIG_ARCH_VERSATILE_PB)
-#define VERSATILE_SYS_OSC2                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
-#define VERSATILE_SYS_OSC3                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
-#define VERSATILE_SYS_OSC4                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
-#endif
-
-#define VERSATILE_SYS_LOCK                    (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
-#define VERSATILE_SYS_100HZ                   (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
-#define VERSATILE_SYS_CFGDATA1                (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
-#define VERSATILE_SYS_CFGDATA2                (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
-#define VERSATILE_SYS_FLAGS                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
-#define VERSATILE_SYS_FLAGSSET                (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
-#define VERSATILE_SYS_FLAGSCLR                (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
-#define VERSATILE_SYS_NVFLAGS                 (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
-#define VERSATILE_SYS_NVFLAGSSET              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
-#define VERSATILE_SYS_NVFLAGSCLR              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
-#define VERSATILE_SYS_RESETCTL                (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
-#define VERSATILE_SYS_PCICTL                  (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
-#define VERSATILE_SYS_MCI                     (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
-#define VERSATILE_SYS_FLASH                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
-#define VERSATILE_SYS_CLCD                    (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
-#define VERSATILE_SYS_CLCDSER                 (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
-#define VERSATILE_SYS_BOOTCS                  (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
-#define VERSATILE_SYS_24MHz                   (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
-#define VERSATILE_SYS_MISC                    (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
-#define VERSATILE_SYS_TEST_OSC0               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
-#define VERSATILE_SYS_TEST_OSC1               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
-#define VERSATILE_SYS_TEST_OSC2               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
-#define VERSATILE_SYS_TEST_OSC3               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
-#define VERSATILE_SYS_TEST_OSC4               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)
-
-/*
- * Values for VERSATILE_SYS_RESET_CTRL
- */
-#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR    0x01
-#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT   0x02
-#define VERSATILE_SYS_CTRL_RESET_DLLRESET     0x03
-#define VERSATILE_SYS_CTRL_RESET_PLLRESET     0x04
-#define VERSATILE_SYS_CTRL_RESET_POR          0x05
-#define VERSATILE_SYS_CTRL_RESET_DoC          0x06
-
-#define VERSATILE_SYS_CTRL_LED         (1 << 0)
-
-
-/* ------------------------------------------------------------------------
- *  Versatile control registers
- * ------------------------------------------------------------------------
- */
-
-/*
- * VERSATILE_IDFIELD
- *
- * 31:24 = manufacturer (0x41 = ARM)
- * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
- * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
- * 11:4  = build value
- * 3:0   = revision number (0x1 = rev B (AHB))
- */
-
-/*
- * VERSATILE_SYS_LOCK
- *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
- *     SYS_CLD, SYS_BOOTCS
- */
-#define VERSATILE_SYS_LOCK_LOCKED    (1 << 16)
-#define VERSATILE_SYS_LOCKVAL_MASK	0xFFFF		/* write 0xA05F to enable write access */
-
-/*
- * VERSATILE_SYS_FLASH
- */
-#define VERSATILE_FLASHPROG_FLVPPEN	(1 << 0)	/* Enable writing to flash */
-
-/*
- * VERSATILE_INTREG
- *     - used to acknowledge and control MMCI and UART interrupts
- */
-#define VERSATILE_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
-#define VERSATILE_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
-#define VERSATILE_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
-                                                /* write 1 to acknowledge and clear               */
-#define VERSATILE_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
-#define VERSATILE_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
-
-/*
- * VERSATILE peripheral addresses
- */
-#define VERSATILE_PCI_CORE_BASE        0x10001000	/* PCI core control */
-#define VERSATILE_I2C_BASE             0x10002000	/* I2C control */
-#define VERSATILE_SIC_BASE             0x10003000	/* Secondary interrupt controller */
-#define VERSATILE_AACI_BASE            0x10004000	/* Audio */
-#define VERSATILE_MMCI0_BASE           0x10005000	/* MMC interface */
-#define VERSATILE_KMI0_BASE            0x10006000	/* KMI interface */
-#define VERSATILE_KMI1_BASE            0x10007000	/* KMI 2nd interface */
-#define VERSATILE_CHAR_LCD_BASE        0x10008000	/* Character LCD */
-#define VERSATILE_UART3_BASE           0x10009000	/* UART 3 */
-#define VERSATILE_SCI1_BASE            0x1000A000
-#define VERSATILE_MMCI1_BASE           0x1000B000    /* MMC Interface */
-	/* 0x1000C000 - 0x1000CFFF = reserved */
-#define VERSATILE_ETH_BASE             0x10010000	/* Ethernet */
-#define VERSATILE_USB_BASE             0x10020000	/* USB */
-	/* 0x10030000 - 0x100FFFFF = reserved */
-#define VERSATILE_SMC_BASE             0x10100000	/* SMC */
-#define VERSATILE_MPMC_BASE            0x10110000	/* MPMC */
-#define VERSATILE_CLCD_BASE            0x10120000	/* CLCD */
-#define VERSATILE_DMAC_BASE            0x10130000	/* DMA controller */
-#define VERSATILE_VIC_BASE             0x10140000	/* Vectored interrupt controller */
-#define VERSATILE_PERIPH_BASE          0x10150000	/* off-chip peripherals alias from */
-                                                /* 0x10000000 - 0x100FFFFF */
-#define VERSATILE_AHBM_BASE            0x101D0000	/* AHB monitor */
-#define VERSATILE_SCTL_BASE            0x101E0000	/* System controller */
-#define VERSATILE_WATCHDOG_BASE        0x101E1000	/* Watchdog */
-#define VERSATILE_TIMER0_1_BASE        0x101E2000	/* Timer 0 and 1 */
-#define VERSATILE_TIMER2_3_BASE        0x101E3000	/* Timer 2 and 3 */
-#define VERSATILE_GPIO0_BASE           0x101E4000	/* GPIO port 0 */
-#define VERSATILE_GPIO1_BASE           0x101E5000	/* GPIO port 1 */
-#define VERSATILE_GPIO2_BASE           0x101E6000	/* GPIO port 2 */
-#define VERSATILE_GPIO3_BASE           0x101E7000	/* GPIO port 3 */
-#define VERSATILE_RTC_BASE             0x101E8000	/* Real Time Clock */
-	/* 0x101E9000 - reserved */
-#define VERSATILE_SCI_BASE             0x101F0000	/* Smart card controller */
-#define VERSATILE_UART0_BASE           0x101F1000	/* Uart 0 */
-#define VERSATILE_UART1_BASE           0x101F2000	/* Uart 1 */
-#define VERSATILE_UART2_BASE           0x101F3000	/* Uart 2 */
-#define VERSATILE_SSP_BASE             0x101F4000	/* Synchronous Serial Port */
-
-#define VERSATILE_SSMC_BASE            0x20000000	/* SSMC */
-#define VERSATILE_IB2_BASE             0x24000000	/* IB2 module */
-#define VERSATILE_MBX_BASE             0x40000000	/* MBX */
-
-/* PCI space */
-#define VERSATILE_PCI_BASE             0x41000000	/* PCI Interface */
-#define VERSATILE_PCI_CFG_BASE	       0x42000000
-#define VERSATILE_PCI_MEM_BASE0        0x44000000
-#define VERSATILE_PCI_MEM_BASE1        0x50000000
-#define VERSATILE_PCI_MEM_BASE2        0x60000000
-/* Sizes of above maps */
-#define VERSATILE_PCI_BASE_SIZE	       0x01000000
-#define VERSATILE_PCI_CFG_BASE_SIZE    0x02000000
-#define VERSATILE_PCI_MEM_BASE0_SIZE   0x0c000000	/* 32Mb */
-#define VERSATILE_PCI_MEM_BASE1_SIZE   0x10000000	/* 256Mb */
-#define VERSATILE_PCI_MEM_BASE2_SIZE   0x10000000	/* 256Mb */
-
-#define VERSATILE_SDRAM67_BASE         0x70000000	/* SDRAM banks 6 and 7 */
-#define VERSATILE_LT_BASE              0x80000000	/* Logic Tile expansion */
-
-/*
- * Disk on Chip
- */
-#define VERSATILE_DOC_BASE             0x2C000000
-#define VERSATILE_DOC_SIZE             (16 << 20)
-#define VERSATILE_DOC_PAGE_SIZE        512
-#define VERSATILE_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
-
-#define ERASE_UNIT_PAGES    32
-#define START_PAGE          0x80
-
-/*
- *  LED settings, bits [7:0]
- */
-#define VERSATILE_SYS_LED0             (1 << 0)
-#define VERSATILE_SYS_LED1             (1 << 1)
-#define VERSATILE_SYS_LED2             (1 << 2)
-#define VERSATILE_SYS_LED3             (1 << 3)
-#define VERSATILE_SYS_LED4             (1 << 4)
-#define VERSATILE_SYS_LED5             (1 << 5)
-#define VERSATILE_SYS_LED6             (1 << 6)
-#define VERSATILE_SYS_LED7             (1 << 7)
-
-#define ALL_LEDS                  0xFF
-
-#define LED_BANK                  VERSATILE_SYS_LED
-
-/*
- * Control registers
- */
-#define VERSATILE_IDFIELD_OFFSET	0x0	/* Versatile build information */
-#define VERSATILE_FLASHPROG_OFFSET	0x4	/* Flash devices */
-#define VERSATILE_INTREG_OFFSET		0x8	/* Interrupt control */
-#define VERSATILE_DECODE_OFFSET		0xC	/* Fitted logic modules */
-
-
-/* ------------------------------------------------------------------------
- *  Versatile Interrupt Controller - control registers
- * ------------------------------------------------------------------------
- *
- *  Offsets from interrupt controller base
- *
- *  System Controller interrupt controller base is
- *
- * 	VERSATILE_IC_BASE
- *
- *  Core Module interrupt controller base is
- *
- * 	VERSATILE_SYS_IC
- *
- */
-/* VIC definitions in include/asm-arm/hardware/vic.h */
-
-#define SIC_IRQ_STATUS                  0
-#define SIC_IRQ_RAW_STATUS              0x04
-#define SIC_IRQ_ENABLE                  0x08
-#define SIC_IRQ_ENABLE_SET              0x08
-#define SIC_IRQ_ENABLE_CLEAR            0x0C
-#define SIC_INT_SOFT_SET                0x10
-#define SIC_INT_SOFT_CLEAR              0x14
-#define SIC_INT_PIC_ENABLE              0x20	/* read status of pass through mask */
-#define SIC_INT_PIC_ENABLES             0x20	/* set interrupt pass through bits */
-#define SIC_INT_PIC_ENABLEC             0x24	/* Clear interrupt pass through bits */
-
-/* ------------------------------------------------------------------------
- *  Interrupts - bit assignment (primary)
- * ------------------------------------------------------------------------
- */
-
-#define INT_WDOGINT                     0	/* Watchdog timer */
-#define INT_SOFTINT                     1	/* Software interrupt */
-#define INT_COMMRx                      2	/* Debug Comm Rx interrupt */
-#define INT_COMMTx                      3	/* Debug Comm Tx interrupt */
-#define INT_TIMERINT0_1                 4	/* Timer 0 and 1 */
-#define INT_TIMERINT2_3                 5	/* Timer 2 and 3 */
-#define INT_GPIOINT0                    6	/* GPIO 0 */
-#define INT_GPIOINT1                    7	/* GPIO 1 */
-#define INT_GPIOINT2                    8	/* GPIO 2 */
-#define INT_GPIOINT3                    9	/* GPIO 3 */
-#define INT_RTCINT                      10	/* Real Time Clock */
-#define INT_SSPINT                      11	/* Synchronous Serial Port */
-#define INT_UARTINT0                    12	/* UART 0 on development chip */
-#define INT_UARTINT1                    13	/* UART 1 on development chip */
-#define INT_UARTINT2                    14	/* UART 2 on development chip */
-#define INT_SCIINT                      15	/* Smart Card Interface */
-#define INT_CLCDINT                     16	/* CLCD controller */
-#define INT_DMAINT                      17	/* DMA controller */
-#define INT_PWRFAILINT                  18	/* Power failure */
-#define INT_MBXINT                      19	/* Graphics processor */
-#define INT_GNDINT                      20	/* Reserved */
-	/* External interrupt signals from logic tiles or secondary controller */
-#define INT_VICSOURCE21                 21	/* Disk on Chip */
-#define INT_VICSOURCE22                 22	/* MCI0A */
-#define INT_VICSOURCE23                 23	/* MCI1A */
-#define INT_VICSOURCE24                 24	/* AACI */
-#define INT_VICSOURCE25                 25	/* Ethernet */
-#define INT_VICSOURCE26                 26	/* USB */
-#define INT_VICSOURCE27                 27	/* PCI 0 */
-#define INT_VICSOURCE28                 28	/* PCI 1 */
-#define INT_VICSOURCE29                 29	/* PCI 2 */
-#define INT_VICSOURCE30                 30	/* PCI 3 */
-#define INT_VICSOURCE31                 31	/* SIC source */
-
-#define VERSATILE_SC_VALID_INT               0x003FFFFF
-
-#define MAXIRQNUM                       31
-#define MAXFIQNUM                       31
-#define MAXSWINUM                       31
-
-/* ------------------------------------------------------------------------
- *  Interrupts - bit assignment (secondary)
- * ------------------------------------------------------------------------
- */
-#define SIC_INT_MMCI0B                  1	/* Multimedia Card 0B */
-#define SIC_INT_MMCI1B                  2	/* Multimedia Card 1B */
-#define SIC_INT_KMI0                    3	/* Keyboard/Mouse port 0 */
-#define SIC_INT_KMI1                    4	/* Keyboard/Mouse port 1 */
-#define SIC_INT_SCI3                    5	/* Smart Card interface */
-#define SIC_INT_UART3                   6	/* UART 3 empty or data available */
-#define SIC_INT_CLCD                    7	/* Character LCD */
-#define SIC_INT_TOUCH                   8	/* Touchscreen */
-#define SIC_INT_KEYPAD                  9	/* Key pressed on display keypad */
-	/* 10:20 - reserved */
-#define SIC_INT_DoC                     21	/* Disk on Chip memory controller */
-#define SIC_INT_MMCI0A                  22	/* MMC 0A */
-#define SIC_INT_MMCI1A                  23	/* MMC 1A */
-#define SIC_INT_AACI                    24	/* Audio Codec */
-#define SIC_INT_ETH                     25	/* Ethernet controller */
-#define SIC_INT_USB                     26	/* USB controller */
-#define SIC_INT_PCI0                    27
-#define SIC_INT_PCI1                    28
-#define SIC_INT_PCI2                    29
-#define SIC_INT_PCI3                    30
-
-
-/*
- * System controller bit assignment
- */
-#define VERSATILE_REFCLK	0
-#define VERSATILE_TIMCLK	1
-
-#define VERSATILE_TIMER1_EnSel	15
-#define VERSATILE_TIMER2_EnSel	17
-#define VERSATILE_TIMER3_EnSel	19
-#define VERSATILE_TIMER4_EnSel	21
-
-
-#define VERSATILE_CSR_BASE             0x10000000
-#define VERSATILE_CSR_SIZE             0x10000000
-
-#ifdef CONFIG_MACH_VERSATILE_AB
-/*
- * IB2 Versatile/AB expansion board definitions
- */
-#define VERSATILE_IB2_CAMERA_BANK	VERSATILE_IB2_BASE
-#define VERSATILE_IB2_KBD_DATAREG	(VERSATILE_IB2_BASE + 0x01000000)
-
-/* VICINTSOURCE27 */
-#define VERSATILE_IB2_INT_BASE		(VERSATILE_IB2_BASE + 0x02000000)
-#define VERSATILE_IB2_IER		(VERSATILE_IB2_INT_BASE + 0)
-#define VERSATILE_IB2_ISR		(VERSATILE_IB2_INT_BASE + 4)
-
-#define VERSATILE_IB2_CTL_BASE		(VERSATILE_IB2_BASE + 0x03000000)
-#define VERSATILE_IB2_CTRL		(VERSATILE_IB2_CTL_BASE + 0)
-#define VERSATILE_IB2_STAT		(VERSATILE_IB2_CTL_BASE + 4)
-#endif
-
-#endif
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index b72684caa7..1b89d0edf9 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_VEXPRESS
 
 config ARCH_TEXT_BASE
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 9a06e648a6..b52ba00f3c 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += v2m.o
 obj-y += reset.o
diff --git a/arch/arm/mach-vexpress/include/mach/debug_ll.h b/arch/arm/mach-vexpress/include/mach/debug_ll.h
deleted file mode 100644
index d59f68ea19..0000000000
--- a/arch/arm/mach-vexpress/include/mach/debug_ll.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2013 Jean-Christophe PLAGNIOL-VILLARD <plagniol@jcrosoft.com>
- *
- * GPLv2 only
- */
-
-#ifndef __MACH_DEBUG_LL_H__
-#define   __MACH_DEBUG_LL_H__
-
-#include <linux/amba/serial.h>
-#include <io.h>
-
-#define DEBUG_LL_PHYS_BASE		0x10000000
-#define DEBUG_LL_PHYS_BASE_RS1		0x1c000000
-
-#ifdef MP
-#define DEBUG_LL_UART_ADDR DEBUG_LL_PHYS_BASE
-#else
-#define DEBUG_LL_UART_ADDR DEBUG_LL_PHYS_BASE_RS1
-#endif
-
-#include <debug_ll/pl011.h>
-
-#endif
diff --git a/arch/arm/mach-vexpress/include/mach/devices.h b/arch/arm/mach-vexpress/include/mach/devices.h
deleted file mode 100644
index bef8c8b94f..0000000000
--- a/arch/arm/mach-vexpress/include/mach/devices.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
- *
- * GPLv2 only
- */
-
-#ifndef __ASM_ARCH_DEVICES_H__
-#define __ASM_ARCH_DEVICES_H__
-
-#include <linux/amba/mmci.h>
-
-void vexpress_a9_legacy_init(void);
-void vexpress_init(void);
-
-extern void *v2m_wdt_base;
-extern void *v2m_sysreg_base;
-
-#endif /* __ASM_ARCH_DEVICES_H__ */
diff --git a/arch/arm/mach-vexpress/reset.c b/arch/arm/mach-vexpress/reset.c
index 78e452936d..0d626db7d7 100644
--- a/arch/arm/mach-vexpress/reset.c
+++ b/arch/arm/mach-vexpress/reset.c
@@ -9,12 +9,12 @@
 #include <init.h>
 #include <restart.h>
 #include <linux/amba/sp805.h>
-
-#include <mach/devices.h>
+#include <mach/vexpress/vexpress.h>
+#include <mach/vexpress/devices.h>
 
 void __iomem *v2m_wdt_base;
 
-static void vexpress_reset_soc(struct restart_handler *rst)
+static void __noreturn vexpress_reset_soc(struct restart_handler *rst)
 {
 	writel(LOAD_MIN, v2m_wdt_base + WDTLOAD);
 	writeb(RESET_ENABLE, v2m_wdt_base + WDTCONTROL);
@@ -22,10 +22,9 @@ static void vexpress_reset_soc(struct restart_handler *rst)
 	hang();
 }
 
-static int restart_register_feature(void)
+void vexpress_restart_register_feature(void __iomem *base)
 {
-	restart_handler_register_fn("soc-wdt", vexpress_reset_soc);
+	v2m_wdt_base = base;
 
-	return 0;
+	restart_handler_register_fn("soc-wdt", vexpress_reset_soc);
 }
-coredevice_initcall(restart_register_feature);
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 3535262848..5c4c2478cf 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -5,17 +5,10 @@
  */
 
 #include <common.h>
-#include <init.h>
 #include <io.h>
-
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/amba/bus.h>
-
-#include <asm/hardware/arm_timer.h>
 #include <asm/hardware/sp810.h>
-
-#include <mach/devices.h>
+#include <mach/vexpress/devices.h>
+#include <mach/vexpress/vexpress.h>
 
 void __iomem *v2m_sysreg_base;
 
@@ -23,8 +16,7 @@ static void v2m_sysctl_init(void __iomem *base)
 {
 	u32 scctrl;
 
-	if (WARN_ON(!base))
-		return;
+	v2m_sysreg_base = base;
 
 	/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
 	scctrl = readl(base + SCCTRL);
@@ -35,14 +27,12 @@ static void v2m_sysctl_init(void __iomem *base)
 
 void vexpress_a9_legacy_init(void)
 {
-	v2m_wdt_base = IOMEM(0x1000f000);
-	v2m_sysreg_base = IOMEM(0x10001000);
 	v2m_sysctl_init(IOMEM(0x10001000));
+	vexpress_restart_register_feature(IOMEM(0x1000f000));
 }
 
 void vexpress_init(void)
 {
-	v2m_wdt_base = IOMEM(0x1c0f0000);
-	v2m_sysreg_base = IOMEM(0x1c020000);
 	v2m_sysctl_init(IOMEM(0x1c020000));
+	vexpress_restart_register_feature(IOMEM(0x1c0f0000));
 }
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 3e07633e5f..451a344b2e 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 if ARCH_ZYNQ
 
 config ARCH_TEXT_BASE
@@ -11,7 +13,6 @@ config ZYNQ_DEBUG_LL_UART_BASE
 config ARCH_ZYNQ7000
 	bool
 	select CPU_V7
-	select CLKDEV_LOOKUP
 	select COMMON_CLK
 	select COMMON_CLK_OF_PROVIDER
 	select ARM_SMP_TWD
@@ -27,6 +28,7 @@ menu "select Zynq boards to be built"
 
 config MACH_ZEDBOARD
 	bool "Avnet Zynq-7000 ZedBoard"
+	select ARM_USE_COMPRESSED_DTB
 	select ARCH_ZYNQ7000
 
 endmenu
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 06c2ce996c..d5e94859a6 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 obj-y += zynq.o bootm-zynqimg.o
 lwl-y += cpu_init.o
diff --git a/arch/arm/mach-zynq/cpu_init.c b/arch/arm/mach-zynq/cpu_init.c
index ca7c4b2979..7194c7e216 100644
--- a/arch/arm/mach-zynq/cpu_init.c
+++ b/arch/arm/mach-zynq/cpu_init.c
@@ -3,7 +3,7 @@
 #include <common.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/errata.h>
-#include <mach/init.h>
+#include <mach/zynq/init.h>
 
 void zynq_cpu_lowlevel_init(void)
 {
diff --git a/arch/arm/mach-zynq/include/mach/debug_ll.h b/arch/arm/mach-zynq/include/mach/debug_ll.h
deleted file mode 100644
index 6c20dd534d..0000000000
--- a/arch/arm/mach-zynq/include/mach/debug_ll.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * based on mach-imx/include/mach/debug_ll.h
- */
-
-#ifndef __MACH_DEBUG_LL_H__
-#define __MACH_DEBUG_LL_H__
-
-#include <io.h>
-#include <mach/zynq7000-regs.h>
-
-#ifndef CONFIG_ZYNQ_DEBUG_LL_UART_BASE
-#warning define ZYNQ_DEBUG_LL_UART_BASE properly for debug_ll
-#define ZYNQ_DEBUG_LL_UART_BASE ZYNQ_UART1_BASE_ADDR
-#else
-#define ZYNQ_DEBUG_LL_UART_BASE CONFIG_ZYNQ_DEBUG_LL_UART_BASE
-#endif
-
-#define ZYNQ_UART_RXTXFIFO	0x30
-#define ZYNQ_UART_CHANNEL_STS	0x2C
-
-#define ZYNQ_UART_STS_TFUL	(1 << 4)
-#define ZYNQ_UART_TXDIS		(1 << 5)
-
-static inline void PUTC_LL(int c)
-{
-	void __iomem *base = (void __iomem *)ZYNQ_DEBUG_LL_UART_BASE;
-
-	if (readl(base) & ZYNQ_UART_TXDIS)
-		return;
-
-	while ((readl(base + ZYNQ_UART_CHANNEL_STS) & ZYNQ_UART_STS_TFUL) != 0)
-		;
-
-	writel(c, base + ZYNQ_UART_RXTXFIFO);
-}
-
-#endif
diff --git a/arch/arm/mach-zynq/include/mach/init.h b/arch/arm/mach-zynq/include/mach/init.h
deleted file mode 100644
index c458f602e4..0000000000
--- a/arch/arm/mach-zynq/include/mach/init.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef __MACH_INIT_H
-#define __MACH_INIT_H
-
-void zynq_cpu_lowlevel_init(void);
-
-#endif
diff --git a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
deleted file mode 100644
index ba4b67f479..0000000000
--- a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __MACH_FLASH_HEADER_H
-#define __MACH_FLASH_HEADER_H
-
-#include <stdint.h>
-
-#define REGINIT_OFFSET			0x0a0
-#define IMAGE_OFFSET			0x8c0
-
-#define WIDTH_DETECTION_MAGIC	0xAA995566
-#define IMAGE_IDENTIFICATION	0x584C4E58	/* "XLNX" */
-
-struct zynq_flash_header {
-	uint32_t width_det;
-	uint32_t image_id;
-	uint32_t enc_stat;
-	uint32_t user;
-	uint32_t flash_offset;
-	uint32_t length;
-	uint32_t res0;
-	uint32_t start_of_exec;
-	uint32_t total_len;
-	uint32_t res1;
-	uint32_t checksum;
-	uint32_t res2;
-};
-
-#endif /* __MACH_FLASH_HEADER_H */
diff --git a/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h b/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h
deleted file mode 100644
index 4e24064746..0000000000
--- a/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (c) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#define ZYNQ_SLCR_LOCK			0xF8000004
-#define ZYNQ_SLCR_UNLOCK		0xF8000008
-#define ZYNQ_ARM_PLL_CTRL		0xF8000100
-#define ZYNQ_DDR_PLL_CTRL		0xF8000104
-#define ZYNQ_IO_PLL_CTRL		0xF8000108
-#define ZYNQ_PLL_STATUS			0xF800010C
-#define ZYNQ_ARM_PLL_CFG		0xF8000110
-#define ZYNQ_DDR_PLL_CFG		0xF8000114
-#define ZYNQ_IO_PLL_CFG			0xF8000118
-#define ZYNQ_ARM_CLK_CTRL		0xF8000120
-#define ZYNQ_DDR_CLK_CTRL		0xF8000124
-#define ZYNQ_DCI_CLK_CTRL		0xF8000128
-#define ZYNQ_APER_CLK_CTRL		0xF800012C
-#define ZYNQ_USB0_CLK_CTRL		0xF8000130
-#define ZYNQ_USB1_CLK_CTRL		0xF8000134
-#define ZYNQ_GEM0_RCLK_CTRL		0xF8000138
-#define ZYNQ_GEM1_RCLK_CTRL		0xF800013C
-#define ZYNQ_GEM0_CLK_CTRL		0xF8000140
-#define ZYNQ_GEM1_CLK_CTRL		0xF8000144
-#define ZYNQ_SMC_CLK_CTRL		0xF8000148
-#define ZYNQ_LQSPI_CLK_CTRL		0xF800014C
-#define ZYNQ_SDIO_CLK_CTRL		0xF8000150
-#define ZYNQ_UART_CLK_CTRL		0xF8000154
-#define ZYNQ_SPI_CLK_CTRL		0xF8000158
-#define ZYNQ_CAN_CLK_CTRL		0xF800015C
-#define ZYNQ_CAN_MIOCLK_CTRL	0xF8000160
-#define ZYNQ_DBG_CLK_CTRL		0xF8000164
-#define ZYNQ_PCAP_CLK_CTRL		0xF8000168
-#define ZYNQ_TOPSW_CLK_CTRL		0xF800016C
-#define ZYNQ_FPGA0_CLK_CTRL		0xF8000170
-#define ZYNQ_FPGA1_CLK_CTRL		0xF8000180
-#define ZYNQ_FPGA2_CLK_CTRL		0xF8000190
-#define ZYNQ_FPGA3_CLK_CTRL		0xF80001A0
-#define ZYNQ_CLK_621_TRUE		0xF80001C4
diff --git a/arch/arm/mach-zynq/include/mach/zynq7000-regs.h b/arch/arm/mach-zynq/include/mach/zynq7000-regs.h
deleted file mode 100644
index eeecfe1ded..0000000000
--- a/arch/arm/mach-zynq/include/mach/zynq7000-regs.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * (c) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#define ZYNQ_UART0_BASE_ADDR		0xE0000000
-#define ZYNQ_UART1_BASE_ADDR		0xE0001000
-#define ZYNQ_I2C0_BASE_ADDR		0xE0004000
-#define ZYNQ_I2C1_BASE_ADDR		0xE0005000
-#define ZYNQ_SPI0_BASE_ADDR		0xE0006000
-#define ZYNQ_SPI1_BASE_ADDR		0xE0007000
-#define ZYNQ_CAN0_BASE_ADDR		0xE0008000
-#define ZYNQ_CAN1_BASE_ADDR		0xE0009000
-#define ZYNQ_GPIO_BASE_ADDR		0xE000A000
-#define ZYNQ_GEM0_BASE_ADDR		0xE000B000
-
-#define ZYNQ_SLCR_BASE			0xF8000000
-#define ZYNQ_SLCR_SCL			(ZYNQ_SLCR_BASE + 0x000)
-#define ZYNQ_SLCR_LOCK			(ZYNQ_SLCR_BASE + 0x004)
-#define ZYNQ_SLCR_UNLOCK		(ZYNQ_SLCR_BASE + 0x008)
-#define ZYNQ_SLCR_LOCKSTA		(ZYNQ_SLCR_BASE + 0x00C)
-#define ZYNQ_CLOCK_CTRL_BASE		(ZYNQ_SLCR_BASE + 0x100)
-#define ZYNQ_ARM_PLL_CTRL		0x000
-#define ZYNQ_DDR_PLL_CTRL		0x004
-#define ZYNQ_IO_PLL_CTRL		0x008
-#define ZYNQ_PLL_STATUS			0x00C
-#define ZYNQ_ARM_PLL_CFG		0x010
-#define ZYNQ_DDR_PLL_CFG		0x014
-#define ZYNQ_IO_PLL_CFG			0x018
-#define ZYNQ_ARM_CLK_CTRL		0x020
-#define ZYNQ_DDR_CLK_CTRL		0x024
-#define ZYNQ_DCI_CLK_CTRL		0x028
-#define ZYNQ_APER_CLK_CTRL		0x02C
-#define ZYNQ_USB0_CLK_CTRL		0x030
-#define ZYNQ_USB1_CLK_CTRL		0x034
-#define ZYNQ_GEM0_RCLK_CTRL		0x038
-#define ZYNQ_GEM1_RCLK_CTRL		0x03C
-#define ZYNQ_GEM0_CLK_CTRL		0x040
-#define ZYNQ_GEM1_CLK_CTRL		0x044
-#define ZYNQ_SMC_CLK_CTRL		0x048
-#define ZYNQ_LQSPI_CLK_CTRL		0x04C
-#define ZYNQ_SDIO_CLK_CTRL		0x050
-#define ZYNQ_UART_CLK_CTRL		0x054
-#define ZYNQ_SPI_CLK_CTRL		0x058
-#define ZYNQ_CAN_CLK_CTRL		0x05C
-#define ZYNQ_CAN_MIOCLK_CTRL		0x060
-#define ZYNQ_DBG_CLK_CTRL		0x064
-#define ZYNQ_PCAP_CLK_CTRL		0x068
-#define ZYNQ_TOPSW_CLK_CTRL		0x06C
-#define ZYNQ_FPGA0_CLK_CTRL		0x070
-#define ZYNQ_FPGA1_CLK_CTRL		0x080
-#define ZYNQ_FPGA2_CLK_CTRL		0x090
-#define ZYNQ_FPGA3_CLK_CTRL		0x0A0
-#define ZYNQ_CLK_621_TRUE		0x0C4
-#define ZYNQ_RST_CTRL_BASE		(ZYNQ_SLCR_BASE + 0x200)
-#define ZYNQ_SLCR_BOOT_MODE		(ZYNQ_SLCR_BASE + 0x25C)
-#define ZYNQ_PSS_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x000)
-#define ZYNQ_DDR_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x004)
-#define ZYNQ_TOPSW_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x008)
-#define ZYNQ_DMAC_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x00C)
-#define ZYNQ_USB_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x010)
-#define ZYNQ_GEM_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x014)
-#define ZYNQ_SDIO_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x018)
-#define ZYNQ_SPI_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x01C)
-#define ZYNQ_CAN_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x020)
-#define ZYNQ_I2C_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x024)
-#define ZYNQ_UART_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x028)
-#define ZYNQ_GPIO_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x02C)
-#define ZYNQ_LQSPI_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x030)
-#define ZYNQ_SMC_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x034)
-#define ZYNQ_OCM_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x038)
-#define ZYNQ_DEVCI_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x03C)
-#define ZYNQ_FPGA_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x040)
-#define ZYNQ_A9_CPU_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x044)
-#define ZYNQ_RS_AWDT_CTRL		(ZYNQ_RST_CTRL_BASE + 0x04C)
-#define ZYNQ_REBOOT_STATUS		(ZYNQ_SLCR_BASE + 0x258)
-#define ZYNQ_BOOT_MODE			(ZYNQ_SLCR_BASE + 0x25C)
-#define ZYNQ_APU_CTRL			(ZYNQ_SLCR_BASE + 0x300)
-#define ZYNQ_WDT_CLK_SEL		(ZYNQ_SLCR_BASE + 0x304)
-#define ZYNQ_PSS_IDCODE			(ZYNQ_SLCR_BASE + 0x530)
-#define ZYNQ_DDR_URGENT			(ZYNQ_SLCR_BASE + 0x600)
-#define ZYNQ_DDR_CAL_START		(ZYNQ_SLCR_BASE + 0x60C)
-#define ZYNQ_DDR_REF_START		(ZYNQ_SLCR_BASE + 0x614)
-#define ZYNQ_DDR_CMD_STA		(ZYNQ_SLCR_BASE + 0x618)
-#define ZYNQ_DDR_URGENT_SEL		(ZYNQ_SLCR_BASE + 0x61C)
-#define ZYNQ_DDR_DFI_STATUS		(ZYNQ_SLCR_BASE + 0x620)
-#define ZYNQ_MIO_BASE			(ZYNQ_SLCR_BASE + 0x700)
-#define ZYNQ_MIO_LOOPBACK		(ZYNQ_MIO_BASE + 0x104)
-#define ZYNQ_MIO_MST_TRI0		(ZYNQ_MIO_BASE + 0x10C)
-#define ZYNQ_MIO_MST_TRI1		(ZYNQ_MIO_BASE + 0x110)
-#define ZYNQ_SD0_WP_SEL			(ZYNQ_SLCR_BASE + 0x830)
-#define ZYNQ_SD1_WP_SEL			(ZYNQ_SLCR_BASE + 0x834)
-#define ZYNQ_LVL_SHIFTR_EN		(ZYNQ_SLCR_BASE + 0x900)
-#define ZYNQ_OCM_CFG			(ZYNQ_SLCR_BASE + 0x910)
-#define ZYNQ_GPIOB_BASE			(ZYNQ_SLCR_BASE + 0xB00)
-#define ZYNQ_GPIOB_CTRL			(ZYNQ_GPIOB_BASE + 0x000)
-#define ZYNQ_GPIOB_CFG_CMOS18		(ZYNQ_GPIOB_BASE + 0x004)
-#define ZYNQ_GPIOB_CFG_CMOS25		(ZYNQ_GPIOB_BASE + 0x008)
-#define ZYNQ_GPIOB_CFG_CMOS33		(ZYNQ_GPIOB_BASE + 0x00C)
-#define ZYNQ_GPIOB_CFG_LVTTL		(ZYNQ_GPIOB_BASE + 0x010)
-#define ZYNQ_GPIOB_CFG_HSTL		(ZYNQ_GPIOB_BASE + 0x014)
-#define ZYNQ_GPIOB_DRV_BIAS_CTRL	(ZYNQ_GPIOB_BASE + 0x018)
-#define ZYNQ_DDRIOB_BASE		(ZYNQ_SLCR_BASE + 0xB40)
-#define ZYNQ_DDRIOB_ADDR0		(ZYNQ_DDRIOB_BASE + 0x000)
-#define ZYNQ_DDRIOB_ADDR1		(ZYNQ_DDRIOB_BASE + 0x004)
-#define ZYNQ_DDRIOB_DATA0		(ZYNQ_DDRIOB_BASE + 0x008)
-#define ZYNQ_DDRIOB_DATA1		(ZYNQ_DDRIOB_BASE + 0x00C)
-#define ZYNQ_DDRIOB_DIFF0		(ZYNQ_DDRIOB_BASE + 0x010)
-#define ZYNQ_DDRIOB_DIFF1		(ZYNQ_DDRIOB_BASE + 0x014)
-#define ZYNQ_DDRIOB_CLOCK		(ZYNQ_DDRIOB_BASE + 0x018)
-#define ZYNQ_DDRIOB_DRIVE_SLEW_ADDR	(ZYNQ_DDRIOB_BASE + 0x01C)
-#define ZYNQ_DDRIOB_DRIVE_SLEW_DATA	(ZYNQ_DDRIOB_BASE + 0x020)
-#define ZYNQ_DDRIOB_DRIVE_SLEW_DIFF	(ZYNQ_DDRIOB_BASE + 0x024)
-#define ZYNQ_DDRIOB_DRIVE_SLEW_CLOCK	(ZYNQ_DDRIOB_BASE + 0x028)
-#define ZYNQ_DDRIOB_DDR_CTRL		(ZYNQ_DDRIOB_BASE + 0x02C)
-#define ZYNQ_DDRIOB_DCI_CTRL		(ZYNQ_DDRIOB_BASE + 0x030)
-#define ZYNQ_DDRIOB_DCI_STATUS		(ZYNQ_DDRIOB_BASE + 0x034)
-
-#define ZYNQ_TTC0_BASE_ADDR		0xF8001000
-#define ZYNQ_TTC1_BASE_ADDR		0xF8002000
-
-#define ZYNQ_DDRC_BASE			0xF8006000
-
-#define CORTEXA9_SCU_TIMER_BASE_ADDR	0xF8F00600
diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c
index 806aeb9130..2d76a68a5e 100644
--- a/arch/arm/mach-zynq/zynq.c
+++ b/arch/arm/mach-zynq/zynq.c
@@ -18,7 +18,7 @@
 #include <common.h>
 #include <init.h>
 #include <io.h>
-#include <mach/zynq7000-regs.h>
+#include <mach/zynq/zynq7000-regs.h>
 #include <restart.h>
 
 static void __noreturn zynq_restart_soc(struct restart_handler *rst)
@@ -71,7 +71,7 @@ static int zynq_init(void)
 
 	restart_handler_register_fn("soc", zynq_restart_soc);
 
-	bootsource_set(zynq_bootsource_get());
+	bootsource_set_raw(zynq_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
 
 	return 0;
 }
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index c9dc71c9e7..23d04926e6 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -1,5 +1,14 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
-if ARCH_ZYNQMP
+
+menu "ZynqMP Features"
+	depends on ARCH_ZYNQMP
+
+config MACH_XILINX_ZCU102
+	bool "Xilinx Zynq UltraScale+ MPSoC ZCU102"
+	select ARM_USE_COMPRESSED_DTB
+	help
+	  Say Y here if you are using the Xilinx Zynq UltraScale+ MPSoC ZCU102
+	  evaluation board.
 
 config MACH_XILINX_ZCU104
 	bool "Xilinx Zynq UltraScale+ MPSoC ZCU104"
@@ -7,4 +16,10 @@ config MACH_XILINX_ZCU104
 	  Say Y here if you are using the Xilinx Zynq UltraScale+ MPSoC ZCU104
 	  evaluation board.
 
-endif
+config MACH_XILINX_ZCU106
+	bool "Xilinx Zynq UltraScale+ MPSoC ZCU106"
+	help
+	  Say Y here if you are using the Xilinx Zynq UltraScale+ MPSoC ZCU106
+	  evaluation board.
+
+endmenu
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index 021efc94af..e24a43c0d5 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -1,2 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 obj-y += firmware-zynqmp.o
+obj-y += zynqmp.o
+obj-$(CONFIG_BAREBOX_UPDATE) += zynqmp-bbu.o
diff --git a/arch/arm/mach-zynqmp/firmware-zynqmp.c b/arch/arm/mach-zynqmp/firmware-zynqmp.c
index c23b434031..039a46e767 100644
--- a/arch/arm/mach-zynqmp/firmware-zynqmp.c
+++ b/arch/arm/mach-zynqmp/firmware-zynqmp.c
@@ -14,9 +14,17 @@
 
 #include <common.h>
 #include <init.h>
+#include <driver.h>
+#include <param.h>
 #include <linux/arm-smccc.h>
 
-#include <mach/firmware-zynqmp.h>
+#include <mach/zynqmp/firmware-zynqmp.h>
+
+struct zynqmp_fw {
+	struct device *dev;
+	u32 ggs[4];
+	u32 pggs[4];
+};
 
 #define ZYNQMP_TZ_VERSION(MAJOR, MINOR)	((MAJOR << 16) | MINOR)
 
@@ -40,6 +48,7 @@ enum pm_ret_status {
 
 enum pm_api_id {
 	PM_GET_API_VERSION = 1,
+	PM_MMIO_WRITE = 19,
 	PM_FPGA_LOAD = 22,
 	PM_FPGA_GET_STATUS,
 	PM_IOCTL = 34,
@@ -504,6 +513,130 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2,
 }
 
 /**
+ * zynqmp_pm_set_sd_tapdelay() -  Set tap delay for the SD device
+ *
+ * @node_id:	Node ID of the device
+ * @type:	Type of tap delay to set (input/output)
+ * @value:	Value to set fot the tap delay
+ *
+ * This function sets input/output tap delay for the SD device.
+ *
+ * Return:	Returns status, either success or error+reason
+ */
+int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
+{
+	u32 reg = (type == PM_TAPDELAY_INPUT) ? SD_ITAPDLY : SD_OTAPDLYSEL;
+	u32 mask = (node_id == NODE_SD_0) ? GENMASK(15, 0) : GENMASK(31, 16);
+
+	if (value) {
+		return zynqmp_pm_invoke_fn(PM_IOCTL, node_id,
+					   IOCTL_SET_SD_TAPDELAY,
+					   type, value, NULL);
+	}
+
+	/*
+	 * Work around completely misdesigned firmware API on Xilinx ZynqMP.
+	 * The IOCTL_SET_SD_TAPDELAY firmware call allows the caller to only
+	 * ever set IOU_SLCR SD_ITAPDLY Register SD0_ITAPDLYENA/SD1_ITAPDLYENA
+	 * bits, but there is no matching call to clear those bits. If those
+	 * bits are not cleared, SDMMC tuning may fail.
+	 *
+	 * Luckily, there are PM_MMIO_READ/PM_MMIO_WRITE calls which seem to
+	 * allow complete unrestricted access to all address space, including
+	 * IOU_SLCR SD_ITAPDLY Register and all the other registers, access
+	 * to which was supposed to be protected by the current firmware API.
+	 *
+	 * Use PM_MMIO_READ/PM_MMIO_WRITE to re-implement the missing counter
+	 * part of IOCTL_SET_SD_TAPDELAY which clears SDx_ITAPDLYENA bits.
+	 */
+	return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, reg, mask, 0, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_set_sd_tapdelay);
+
+/**
+ * zynqmp_pm_sd_dll_reset() - Reset DLL logic
+ *
+ * @node_id:	Node ID of the device
+ * @type:	Reset type
+ *
+ * This function resets DLL logic for the SD device.
+ *
+ * Return:	Returns status, either success or error+reason
+ */
+int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
+{
+	return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SD_DLL_RESET,
+				   type, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset);
+
+/*
+ * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs)
+ * @index:	GGS register index
+ * @value:	Register value to be written
+ *
+ * This function writes value to GGS register.
+ *
+ * Return:      Returns status, either success or error+reason
+ */
+int zynqmp_pm_write_ggs(u32 index, u32 value)
+{
+	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_WRITE_GGS,
+				   index, value, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_write_ggs);
+
+/**
+ * zynqmp_pm_read_ggs() - PM API for reading global general storage (ggs)
+ * @index:	GGS register index
+ * @value:	Register value to be written
+ *
+ * This function returns GGS register value.
+ *
+ * Return:	Returns status, either success or error+reason
+ */
+int zynqmp_pm_read_ggs(u32 index, u32 *value)
+{
+	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_READ_GGS,
+				   index, 0, value);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_read_ggs);
+
+/**
+ * zynqmp_pm_write_pggs() - PM API for writing persistent global general
+ *			     storage (pggs)
+ * @index:	PGGS register index
+ * @value:	Register value to be written
+ *
+ * This function writes value to PGGS register.
+ *
+ * Return:	Returns status, either success or error+reason
+ */
+int zynqmp_pm_write_pggs(u32 index, u32 value)
+{
+	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_WRITE_PGGS, index, value,
+				   NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_write_pggs);
+
+/**
+ * zynqmp_pm_read_pggs() - PM API for reading persistent global general
+ *			     storage (pggs)
+ * @index:	PGGS register index
+ * @value:	Register value to be written
+ *
+ * This function returns PGGS register value.
+ *
+ * Return:	Returns status, either success or error+reason
+ */
+int zynqmp_pm_read_pggs(u32 index, u32 *value)
+{
+	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_READ_PGGS, index, 0,
+				   value);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
+
+/**
  * zynqmp_pm_fpga_load - Perform the fpga load
  * @address:	Address to write to
  * @size:	pl bitstream size
@@ -576,12 +709,59 @@ const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_get_eemi_ops);
 
+static bool parse_reg(const char *reg, unsigned *idx)
+{
+	bool pggs = reg[0] == 'p';
+	kstrtouint(reg + pggs + sizeof("ggs") - 1, 10, idx);
+	return pggs;
+}
 
-static int zynqmp_firmware_probe(struct device_d *dev)
+static int ggs_set(struct param_d *p, void *_val)
+{
+	u32 *val = _val;
+	unsigned idx;
+
+	if (parse_reg(p->name, &idx))
+		return zynqmp_pm_write_pggs(idx, *val);
+	else
+		return zynqmp_pm_write_ggs(idx, *val);
+}
+static int ggs_get(struct param_d *p, void *_val)
 {
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u32 *val = _val;
+	unsigned idx;
+	int ret;
+
+	if (parse_reg(p->name, &idx))
+		ret = zynqmp_pm_read_pggs(idx, ret_payload);
+	else
+		ret = zynqmp_pm_read_ggs(idx, ret_payload);
+
+	if (ret)
+		return ret;
+
+	*val = ret_payload[1];
+
+	return 0;
+}
+
+static inline void dev_add_param_ggs(struct zynqmp_fw *fw, const char *str, u32 *value)
+{
+	dev_add_param_uint32(fw->dev, str, ggs_set, ggs_get, value, "0x%x", value);
+}
+
+static int zynqmp_firmware_probe(struct device *dev)
+{
+
+	struct zynqmp_fw *fw;
 	int ret;
 
-	ret = get_set_conduit_method(dev->device_node);
+	fw = xzalloc(sizeof(*fw));
+
+	dev_add_alias(dev, "zynqmp_fw");
+
+	ret = get_set_conduit_method(dev->of_node);
 	if (ret)
 		goto out;
 
@@ -619,7 +799,19 @@ static int zynqmp_firmware_probe(struct device_d *dev)
 	dev_dbg(dev, "Trustzone version v%d.%d\n",
 			pm_tz_version >> 16, pm_tz_version & 0xFFFF);
 
-	of_platform_populate(dev->device_node, NULL, dev);
+	of_platform_populate(dev->of_node, NULL, dev);
+
+	fw->dev = dev;
+
+	dev_add_param_ggs(fw, "ggs0", &fw->ggs[0]);
+	dev_add_param_ggs(fw, "ggs1", &fw->ggs[1]);
+	dev_add_param_ggs(fw, "ggs2", &fw->ggs[2]);
+	dev_add_param_ggs(fw, "ggs3", &fw->ggs[3]);
+
+	dev_add_param_ggs(fw, "pggs0", &fw->pggs[0]);
+	dev_add_param_ggs(fw, "pggs1", &fw->pggs[1]);
+	dev_add_param_ggs(fw, "pggs2", &fw->pggs[2]);
+	dev_add_param_ggs(fw, "pggs3", &fw->pggs[3]);
 out:
 	if (ret)
 		do_fw_call = do_fw_call_fail;
@@ -630,8 +822,9 @@ static struct of_device_id zynqmp_firmware_id_table[] = {
 	{ .compatible = "xlnx,zynqmp-firmware", },
 	{}
 };
+MODULE_DEVICE_TABLE(of, zynqmp_firmware_id_table);
 
-static struct driver_d zynqmp_firmware_driver = {
+static struct driver zynqmp_firmware_driver = {
 	.name = "zynqmp_firmware",
 	.probe = zynqmp_firmware_probe,
 	.of_compatible = DRV_OF_COMPAT(zynqmp_firmware_id_table),
diff --git a/arch/arm/mach-zynqmp/include/mach/debug_ll.h b/arch/arm/mach-zynqmp/include/mach/debug_ll.h
deleted file mode 100644
index 67571fe2e1..0000000000
--- a/arch/arm/mach-zynqmp/include/mach/debug_ll.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __MACH_DEBUG_LL_H__
-#define __MACH_DEBUG_LL_H__
-
-#include <io.h>
-
-#define ZYNQMP_UART0_BASE		0xFF000000
-#define ZYNQMP_UART1_BASE		0xFF010000
-#define ZYNQMP_UART_BASE		ZYNQMP_UART0_BASE
-#define ZYNQMP_DEBUG_LL_UART_BASE	ZYNQMP_UART_BASE
-
-#define ZYNQMP_UART_RXTXFIFO	0x30
-#define ZYNQMP_UART_CHANNEL_STS	0x2C
-
-#define ZYNQMP_UART_STS_TFUL	(1 << 4)
-#define ZYNQMP_UART_TXDIS		(1 << 5)
-
-static inline void PUTC_LL(int c)
-{
-	void __iomem *base = (void __iomem *)ZYNQMP_DEBUG_LL_UART_BASE;
-
-	if (readl(base) & ZYNQMP_UART_TXDIS)
-		return;
-
-	while ((readl(base + ZYNQMP_UART_CHANNEL_STS) & ZYNQMP_UART_STS_TFUL) != 0)
-		;
-
-	writel(c, base + 0x30);
-}
-
-#endif
diff --git a/arch/arm/mach-zynqmp/include/mach/firmware-zynqmp.h b/arch/arm/mach-zynqmp/include/mach/firmware-zynqmp.h
deleted file mode 100644
index a04482237d..0000000000
--- a/arch/arm/mach-zynqmp/include/mach/firmware-zynqmp.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Xilinx Zynq MPSoC Firmware layer
- *
- * Copyright (c) 2018 Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
- *
- * based on Linux xlnx-zynqmp
- *
- *  Michal Simek <michal.simek@xilinx.com>
- *  Davorin Mista <davorin.mista@aggios.com>
- *  Jolly Shah <jollys@xilinx.com>
- *  Rajan Vaja <rajanv@xilinx.com>
- */
-
-#ifndef FIRMWARE_ZYNQMP_H_
-#define FIRMWARE_ZYNQMP_H_
-
-#define PAYLOAD_ARG_CNT			4
-
-#define ZYNQMP_PM_VERSION(MAJOR, MINOR)	((MAJOR << 16) | MINOR)
-
-#define ZYNQMP_FPGA_BIT_AUTH_DDR	BIT(1)
-#define ZYNQMP_FPGA_BIT_AUTH_OCM	BIT(2)
-#define ZYNQMP_FPGA_BIT_ENC_USR_KEY	BIT(3)
-#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY	BIT(4)
-#define ZYNQMP_FPGA_BIT_ONLY_BIN	BIT(5)
-
-#define ZYNQMP_PCAP_STATUS_FPGA_DONE	BIT(3)
-
-enum pm_ioctl_id {
-	IOCTL_SET_PLL_FRAC_MODE = 8,
-	IOCTL_GET_PLL_FRAC_MODE,
-	IOCTL_SET_PLL_FRAC_DATA,
-	IOCTL_GET_PLL_FRAC_DATA,
-};
-
-enum pm_query_id {
-	PM_QID_INVALID,
-	PM_QID_CLOCK_GET_NAME,
-	PM_QID_CLOCK_GET_TOPOLOGY,
-	PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
-	PM_QID_CLOCK_GET_PARENTS,
-	PM_QID_CLOCK_GET_ATTRIBUTES,
-	PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
-};
-
-/**
- * struct zynqmp_pm_query_data - PM query data
- * @qid:	query ID
- * @arg1:	Argument 1 of query data
- * @arg2:	Argument 2 of query data
- * @arg3:	Argument 3 of query data
- */
-struct zynqmp_pm_query_data {
-	u32 qid;
-	u32 arg1;
-	u32 arg2;
-	u32 arg3;
-};
-
-struct zynqmp_eemi_ops {
-	int (*get_api_version)(u32 *version);
-	int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
-	int (*clock_enable)(u32 clock_id);
-	int (*clock_disable)(u32 clock_id);
-	int (*clock_getstate)(u32 clock_id, u32 *state);
-	int (*clock_setdivider)(u32 clock_id, u32 divider);
-	int (*clock_getdivider)(u32 clock_id, u32 *divider);
-	int (*clock_setrate)(u32 clock_id, u64 rate);
-	int (*clock_getrate)(u32 clock_id, u64 *rate);
-	int (*clock_setparent)(u32 clock_id, u32 parent_id);
-	int (*clock_getparent)(u32 clock_id, u32 *parent_id);
-	int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
-	int (*fpga_getstatus)(u32 *status);
-	int (*fpga_load)(u64 address, u32 size, u32 flags);
-};
-
-const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
-
-#endif /* FIRMWARE_ZYNQMP_H_ */
diff --git a/arch/arm/mach-zynqmp/zynqmp-bbu.c b/arch/arm/mach-zynqmp/zynqmp-bbu.c
new file mode 100644
index 0000000000..3c5e2fe885
--- /dev/null
+++ b/arch/arm/mach-zynqmp/zynqmp-bbu.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Michael Tretter <m.tretter@pengutronix.de>
+ */
+
+#include <common.h>
+#include <mach/zynqmp/zynqmp-bbu.h>
+
+int zynqmp_bbu_register_handler(const char *name, char *devicefile,
+				unsigned long flags)
+{
+	return bbu_register_std_file_update(name, flags, devicefile,
+					    filetype_zynq_image);
+}
diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c
new file mode 100644
index 0000000000..f86bda1693
--- /dev/null
+++ b/arch/arm/mach-zynqmp/zynqmp.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Michael Tretter <m.tretter@pengutronix.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <linux/types.h>
+#include <bootsource.h>
+#include <reset_source.h>
+
+#define ZYNQMP_CRL_APB_BASE		0xff5e0000
+#define ZYNQMP_CRL_APB_BOOT_MODE_USER	(ZYNQMP_CRL_APB_BASE + 0x200)
+#define ZYNQMP_CRL_APB_RESET_REASON	(ZYNQMP_CRL_APB_BASE + 0x220)
+
+/* PSJTAG interface, PS dedicated pins. */
+#define ZYNQMP_CRL_APB_BOOT_MODE_PSJTAG        0x0
+/* SPI 24-bit addressing */
+#define ZYNQMP_CRL_APB_BOOT_MODE_QSPI24        0x1
+/* SPI 32-bit addressing */
+#define ZYNQMP_CRL_APB_BOOT_MODE_QSPI32        0x2
+/* SD 2.0 card @ controller 0 */
+#define ZYNQMP_CRL_APB_BOOT_MODE_SD0           0x3
+/* SPI NAND flash */
+#define ZYNQMP_CRL_APB_BOOT_MODE_NAND          0x4
+/* SD 2.0 card @ controller 1 */
+#define ZYNQMP_CRL_APB_BOOT_MODE_SD1           0x5
+/* eMMC @ controller 1 */
+#define ZYNQMP_CRL_APB_BOOT_MODE_EMMC          0x6
+/* USB 2.0 */
+#define ZYNQMP_CRL_APB_BOOT_MODE_USB           0x7
+/* PJTAG connection 0 option. */
+#define ZYNQMP_CRL_APB_BOOT_MODE_PJTAG0        0x8
+/* PJTAG connection 1 option. */
+#define ZYNQMP_CRL_APB_BOOT_MODE_PJTAG1        0x9
+/* SD 3.0 card (level-shifted) @ controller 1 */
+#define ZYNQMP_CRL_APB_BOOT_MODE_SD1LS         0xE
+
+/* External POR: The PS_POR_B reset signal pin was asserted. */
+#define ZYNQMP_CRL_APB_RESET_REASON_EXTERNAL   BIT(0)
+/* Internal POR: A system error triggered a POR reset. */
+#define ZYNQMP_CRL_APB_RESET_REASON_INTERNAL   BIT(1)
+/* Internal system reset; A system error triggered a system reset. */
+#define ZYNQMP_CRL_APB_RESET_REASON_PMU        BIT(2)
+/* PS-only reset: Write to PMU_GLOBAL.GLOBAL_RESET [PS_ONLY_RST]. */
+#define ZYNQMP_CRL_APB_RESET_REASON_PSONLY     BIT(3)
+/* External system reset: The PS_SRST_B reset signal pin was asserted. */
+#define ZYNQMP_CRL_APB_RESET_REASON_SRST       BIT(4)
+/* Software system reset: Write to RESET_CTRL [soft_reset]. */
+#define ZYNQMP_CRL_APB_RESET_REASON_SOFT       BIT(5)
+/* Software debugger reset: Write to BLOCKONLY_RST [debug_only]. */
+#define ZYNQMP_CRL_APB_RESET_REASON_DEBUG_SYS  BIT(6)
+
+static void zynqmp_get_bootsource(enum bootsource *src, int *instance)
+{
+	u32 v;
+
+	if (!src || !instance)
+		return;
+
+	v = readl(ZYNQMP_CRL_APB_BOOT_MODE_USER);
+	v &= 0x0F;
+
+	/* cf. Table 11-1 "Boot Modes" in UG1085 Zynq UltraScale+ Device TRM */
+	switch (v) {
+	case ZYNQMP_CRL_APB_BOOT_MODE_PSJTAG:
+	case ZYNQMP_CRL_APB_BOOT_MODE_PJTAG0:
+	case ZYNQMP_CRL_APB_BOOT_MODE_PJTAG1:
+		*src = BOOTSOURCE_JTAG;
+		*instance = 0;
+		break;
+
+	case ZYNQMP_CRL_APB_BOOT_MODE_QSPI24:
+	case ZYNQMP_CRL_APB_BOOT_MODE_QSPI32:
+		*src = BOOTSOURCE_SPI;
+		*instance = 0;
+		break;
+
+	case ZYNQMP_CRL_APB_BOOT_MODE_SD0:
+		*src = BOOTSOURCE_MMC;
+		*instance = 0;
+		break;
+
+	case ZYNQMP_CRL_APB_BOOT_MODE_NAND:
+		*src = BOOTSOURCE_SPI_NAND;
+		*instance = 0;
+		break;
+
+	case ZYNQMP_CRL_APB_BOOT_MODE_SD1:
+	case ZYNQMP_CRL_APB_BOOT_MODE_EMMC:
+	case ZYNQMP_CRL_APB_BOOT_MODE_SD1LS:
+		*src = BOOTSOURCE_MMC;
+		*instance = 1;
+		break;
+
+	case ZYNQMP_CRL_APB_BOOT_MODE_USB:
+		*src = BOOTSOURCE_USB;
+		*instance = 0;
+		break;
+
+	default:
+		*src = BOOTSOURCE_UNKNOWN;
+		*instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+		break;
+	}
+}
+
+struct zynqmp_reset_reason {
+	u32 mask;
+	enum reset_src_type type;
+};
+
+static const struct zynqmp_reset_reason reset_reasons[] = {
+	{ ZYNQMP_CRL_APB_RESET_REASON_DEBUG_SYS,	RESET_JTAG },
+	{ ZYNQMP_CRL_APB_RESET_REASON_SOFT,		RESET_RST },
+	{ ZYNQMP_CRL_APB_RESET_REASON_SRST,		RESET_POR },
+	{ ZYNQMP_CRL_APB_RESET_REASON_PSONLY,		RESET_POR },
+	{ ZYNQMP_CRL_APB_RESET_REASON_PMU,		RESET_POR },
+	{ ZYNQMP_CRL_APB_RESET_REASON_INTERNAL,		RESET_POR },
+	{ ZYNQMP_CRL_APB_RESET_REASON_EXTERNAL,		RESET_POR },
+	{ /* sentinel */ }
+};
+
+static enum reset_src_type zynqmp_get_reset_src(void)
+{
+	enum reset_src_type type = RESET_UKWN;
+	unsigned int i;
+	u32 val;
+
+	val = readl(ZYNQMP_CRL_APB_RESET_REASON);
+
+	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
+		if (val & reset_reasons[i].mask) {
+			type = reset_reasons[i].type;
+			break;
+		}
+	}
+
+	pr_info("ZynqMP reset reason %s (ZYNQMP_CRL_APB_RESET_REASON: 0x%08x)\n",
+		reset_source_to_string(type), val);
+
+	return type;
+}
+
+static int zynqmp_init(void)
+{
+	enum bootsource boot_src;
+	int boot_instance;
+
+	if (!of_machine_is_compatible("xlnx,zynqmp"))
+		return 0;
+
+	zynqmp_get_bootsource(&boot_src, &boot_instance);
+	bootsource_set_raw(boot_src, boot_instance);
+
+	reset_source_set(zynqmp_get_reset_src());
+
+	return 0;
+}
+postcore_initcall(zynqmp_init);
diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
deleted file mode 100644
index bff825e58a..0000000000
--- a/arch/arm/tools/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# linux/arch/arm/tools/Makefile
-#
-# Copyright (C) 2001 Russell King
-#
-
-include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
-	$(Q)$(kecho) '  Generating $@'
-	$(Q)mkdir -p $(dir $@)
-	$(Q)$(AWK) -f $^ > $@
diff --git a/arch/arm/tools/gen-mach-types b/arch/arm/tools/gen-mach-types
deleted file mode 100644
index 04fef71d7b..0000000000
--- a/arch/arm/tools/gen-mach-types
+++ /dev/null
@@ -1,72 +0,0 @@
-#!/bin/awk
-#
-# Awk script to generate include/generated/mach-types.h
-#
-BEGIN	{ nr = 0 }
-/^#/	{ next }
-/^[ 	]*$/ { next }
-
-NF == 4 {
-	  machine_is[nr] = "machine_is_"$1;
-	  config[nr] = "CONFIG_"$2;
-	  mach_type[nr] = "MACH_TYPE_"$3;
-	  num[nr] = $4; nr++
-	}
-
-NF == 3 {
-	  machine_is[nr] = "machine_is_"$1;
-	  config[nr] = "CONFIG_"$2;
-	  mach_type[nr] = "MACH_TYPE_"$3;
-	  num[nr] = ""; nr++
-	}
-
-
-END	{
-	  printf("/*\n");
-	  printf(" * This was automagically generated from %s!\n", FILENAME);
-	  printf(" * Do NOT edit\n");
-	  printf(" */\n\n");
-	  printf("#ifndef __ASM_ARM_MACH_TYPE_H\n");
-	  printf("#define __ASM_ARM_MACH_TYPE_H\n\n");
-	  printf("#ifndef __ASSEMBLY__\n");
-	  printf("/* The type of machine we're running on */\n");
-	  printf("extern unsigned int __machine_arch_type;\n");
-	  printf("#endif\n\n");
-
-	  printf("/* see arch/arm/kernel/arch.c for a description of these */\n");
-	  for (i = 0; i < nr; i++)
-	    if (num[i] ~ /..*/)
-	      printf("#define %-30s %d\n", mach_type[i], num[i]);
-
-	  printf("\n");
-
-	  for (i = 0; i < nr; i++)
-	    if (num[i] ~ /..*/) {
-	      printf("#ifdef %s\n", config[i]);
-	      printf("# ifdef machine_arch_type\n");
-	      printf("#  undef machine_arch_type\n");
-	      printf("#  define machine_arch_type\t__machine_arch_type\n");
-	      printf("# else\n");
-	      printf("#  define machine_arch_type\t%s\n", mach_type[i]);
-	      printf("# endif\n");
-	      printf("# define %s()\t(machine_arch_type == %s)\n", machine_is[i], mach_type[i]);
-	      printf("#else\n");
-	      printf("# define %s()\t(0)\n", machine_is[i]);
-	      printf("#endif\n\n");
-	    }
-
-	  printf("/*\n * These have not yet been registered\n */\n");
-	  for (i = 0; i < nr; i++)
-	    if (num[i] !~ /..*/)
-	      printf("/* #define %-30s <<not registered>> */\n", mach_type[i]);
-
-	  for (i = 0; i < nr; i++)
-	    if (num[i] !~ /..*/) {
-	      printf("#define %s()\t(0)\n", machine_is[i]);
-	    }
-
-	  printf("\n#ifndef machine_arch_type\n");
-	  printf("#define machine_arch_type\t__machine_arch_type\n");
-	  printf("#endif\n\n");
-	  printf("#endif\n");
-	}
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
deleted file mode 100644
index 01bc7aa20a..0000000000
--- a/arch/arm/tools/mach-types
+++ /dev/null
@@ -1,4725 +0,0 @@
-# Database of machine macros and numbers
-#
-# This file is linux/arch/arm/tools/mach-types
-#
-# Up to date versions of this file can be obtained from:
-#
-#   http://www.arm.linux.org.uk/developer/machines/download.php
-#
-# Please do not send patches to this file; it is automatically generated!
-# To add an entry into this database, please see Documentation/arm/README,
-# or visit:
-#
-#   http://www.arm.linux.org.uk/developer/machines/?action=new
-#
-# Last update: Wed Sep 25 08:48:26 2013
-#
-# machine_is_xxx	CONFIG_xxxx		MACH_TYPE_xxx		number
-#
-ebsa110			ARCH_EBSA110		EBSA110			0
-riscpc			ARCH_RPC		RISCPC			1
-nexuspci		ARCH_NEXUSPCI		NEXUSPCI		3
-ebsa285			ARCH_EBSA285		EBSA285			4
-netwinder		ARCH_NETWINDER		NETWINDER		5
-cats			ARCH_CATS		CATS			6
-tbox			ARCH_TBOX		TBOX			7
-co285			ARCH_CO285		CO285			8
-clps7110		ARCH_CLPS7110		CLPS7110		9
-archimedes		ARCH_ARC		ARCHIMEDES		10
-a5k			ARCH_A5K		A5K			11
-etoile			ARCH_ETOILE		ETOILE			12
-lacie_nas		ARCH_LACIE_NAS		LACIE_NAS		13
-clps7500		ARCH_CLPS7500		CLPS7500		14
-shark			ARCH_SHARK		SHARK			15
-brutus			SA1100_BRUTUS		BRUTUS			16
-personal_server		ARCH_PERSONAL_SERVER	PERSONAL_SERVER		17
-itsy			SA1100_ITSY		ITSY			18
-l7200			ARCH_L7200		L7200			19
-pleb			SA1100_PLEB		PLEB			20
-integrator		ARCH_INTEGRATOR		INTEGRATOR		21
-h3600			SA1100_H3600		H3600			22
-ixp1200			ARCH_IXP1200		IXP1200			23
-p720t			ARCH_P720T		P720T			24
-assabet			SA1100_ASSABET		ASSABET			25
-victor			SA1100_VICTOR		VICTOR			26
-lart			SA1100_LART		LART			27
-ranger			SA1100_RANGER		RANGER			28
-graphicsclient		SA1100_GRAPHICSCLIENT	GRAPHICSCLIENT		29
-xp860			SA1100_XP860		XP860			30
-cerf			SA1100_CERF		CERF			31
-nanoengine		SA1100_NANOENGINE	NANOENGINE		32
-fpic			SA1100_FPIC		FPIC			33
-extenex1		SA1100_EXTENEX1		EXTENEX1		34
-sherman			SA1100_SHERMAN		SHERMAN			35
-accelent_sa		SA1100_ACCELENT		ACCELENT_SA		36
-accelent_l7200		ARCH_L7200_ACCELENT	ACCELENT_L7200		37
-netport			SA1100_NETPORT		NETPORT			38
-pangolin		SA1100_PANGOLIN		PANGOLIN		39
-yopy			SA1100_YOPY		YOPY			40
-coolidge		SA1100_COOLIDGE		COOLIDGE		41
-huw_webpanel		SA1100_HUW_WEBPANEL	HUW_WEBPANEL		42
-spotme			ARCH_SPOTME		SPOTME			43
-freebird		ARCH_FREEBIRD		FREEBIRD		44
-ti925			ARCH_TI925		TI925			45
-riscstation		ARCH_RISCSTATION	RISCSTATION		46
-cavy			SA1100_CAVY		CAVY			47
-jornada720		SA1100_JORNADA720	JORNADA720		48
-omnimeter		SA1100_OMNIMETER	OMNIMETER		49
-edb7211			ARCH_EDB7211		EDB7211			50
-citygo			SA1100_CITYGO		CITYGO			51
-pfs168			SA1100_PFS168		PFS168			52
-spot			SA1100_SPOT		SPOT			53
-flexanet		SA1100_FLEXANET		FLEXANET		54
-webpal			ARCH_WEBPAL		WEBPAL			55
-linpda			SA1100_LINPDA		LINPDA			56
-anakin			ARCH_ANAKIN		ANAKIN			57
-mvi			SA1100_MVI		MVI			58
-jupiter			SA1100_JUPITER		JUPITER			59
-psionw			ARCH_PSIONW		PSIONW			60
-aln			SA1100_ALN		ALN			61
-epxa			ARCH_CAMELOT		CAMELOT			62
-gds2200			SA1100_GDS2200		GDS2200			63
-netbook			SA1100_PSION_SERIES7	PSION_SERIES7		64
-xfile			SA1100_XFILE		XFILE			65
-accelent_ep9312		ARCH_ACCELENT_EP9312	ACCELENT_EP9312		66
-ic200			ARCH_IC200		IC200			67
-creditlart		SA1100_CREDITLART	CREDITLART		68
-htm			SA1100_HTM		HTM			69
-iq80310			ARCH_IQ80310		IQ80310			70
-freebot			SA1100_FREEBOT		FREEBOT			71
-entel			ARCH_ENTEL		ENTEL			72
-enp3510			ARCH_ENP3510		ENP3510			73
-trizeps			SA1100_TRIZEPS		TRIZEPS			74
-nesa			SA1100_NESA		NESA			75
-venus			ARCH_VENUS		VENUS			76
-tardis			ARCH_TARDIS		TARDIS			77
-mercury			ARCH_MERCURY		MERCURY			78
-empeg			SA1100_EMPEG		EMPEG			79
-adi_evb			ARCH_I80200FCC		I80200FCC		80
-itt_cpb			SA1100_ITT_CPB		ITT_CPB			81
-svc			SA1100_SVC		SVC			82
-alpha2			SA1100_ALPHA2		ALPHA2			84
-alpha1			SA1100_ALPHA1		ALPHA1			85
-netarm			ARCH_NETARM		NETARM			86
-simpad			SA1100_SIMPAD		SIMPAD			87
-pda1			ARCH_PDA1		PDA1			88
-lubbock			ARCH_LUBBOCK		LUBBOCK			89
-aniko			ARCH_ANIKO		ANIKO			90
-clep7212		ARCH_CLEP7212		CLEP7212		91
-cs89712			ARCH_CS89712		CS89712			92
-weararm			SA1100_WEARARM		WEARARM			93
-possio_px		SA1100_POSSIO_PX	POSSIO_PX		94
-sidearm			SA1100_SIDEARM		SIDEARM			95
-stork			SA1100_STORK		STORK			96
-shannon			SA1100_SHANNON		SHANNON			97
-ace			ARCH_ACE		ACE			98
-ballyarm		SA1100_BALLYARM		BALLYARM		99
-simputer		SA1100_SIMPUTER		SIMPUTER		100
-nexterm			SA1100_NEXTERM		NEXTERM			101
-sa1100_elf		SA1100_SA1100_ELF	SA1100_ELF		102
-gator			SA1100_GATOR		GATOR			103
-granite			ARCH_GRANITE		GRANITE			104
-consus			SA1100_CONSUS		CONSUS			105
-aaed2000		ARCH_AAED2000		AAED2000		106
-cdb89712		ARCH_CDB89712		CDB89712		107
-graphicsmaster		SA1100_GRAPHICSMASTER	GRAPHICSMASTER		108
-adsbitsy		SA1100_ADSBITSY		ADSBITSY		109
-pxa_idp			ARCH_PXA_IDP		PXA_IDP			110
-plce			ARCH_PLCE		PLCE			111
-pt_system3		SA1100_PT_SYSTEM3	PT_SYSTEM3		112
-murphy			ARCH_MEDALB		MEDALB			113
-eagle			ARCH_EAGLE		EAGLE			114
-dsc21			ARCH_DSC21		DSC21			115
-dsc24			ARCH_DSC24		DSC24			116
-ti5472			ARCH_TI5472		TI5472			117
-autcpu12		ARCH_AUTCPU12		AUTCPU12		118
-uengine			ARCH_UENGINE		UENGINE			119
-bluestem		SA1100_BLUESTEM		BLUESTEM		120
-xingu8			ARCH_XINGU8		XINGU8			121
-bushstb			ARCH_BUSHSTB		BUSHSTB			122
-epsilon1		SA1100_EPSILON1		EPSILON1		123
-balloon			SA1100_BALLOON		BALLOON			124
-puppy			ARCH_PUPPY		PUPPY			125
-elroy			SA1100_ELROY		ELROY			126
-gms720			ARCH_GMS720		GMS720			127
-s24x			ARCH_S24X		S24X			128
-jtel_clep7312		ARCH_JTEL_CLEP7312	JTEL_CLEP7312		129
-cx821xx			ARCH_CX821XX		CX821XX			130
-edb7312			ARCH_EDB7312		EDB7312			131
-bsa1110			SA1100_BSA1110		BSA1110			132
-powerpin		ARCH_POWERPIN		POWERPIN		133
-openarm			ARCH_OPENARM		OPENARM			134
-whitechapel		SA1100_WHITECHAPEL	WHITECHAPEL		135
-h3100			SA1100_H3100		H3100			136
-h3800			SA1100_H3800		H3800			137
-blue_v1			ARCH_BLUE_V1		BLUE_V1			138
-pxa_cerf		ARCH_PXA_CERF		PXA_CERF		139
-arm7tevb		ARCH_ARM7TEVB		ARM7TEVB		140
-d7400			SA1100_D7400		D7400			141
-piranha			ARCH_PIRANHA		PIRANHA			142
-sbcamelot		SA1100_SBCAMELOT	SBCAMELOT		143
-kings			SA1100_KINGS		KINGS			144
-smdk2400		ARCH_SMDK2400		SMDK2400		145
-collie			SA1100_COLLIE		COLLIE			146
-idr			ARCH_IDR		IDR			147
-badge4			SA1100_BADGE4		BADGE4			148
-webnet			ARCH_WEBNET		WEBNET			149
-d7300			SA1100_D7300		D7300			150
-cep			SA1100_CEP		CEP			151
-fortunet		ARCH_FORTUNET		FORTUNET		152
-vc547x			ARCH_VC547X		VC547X			153
-filewalker		SA1100_FILEWALKER	FILEWALKER		154
-netgateway		SA1100_NETGATEWAY	NETGATEWAY		155
-symbol2800		SA1100_SYMBOL2800	SYMBOL2800		156
-suns			SA1100_SUNS		SUNS			157
-frodo			SA1100_FRODO		FRODO			158
-ms301			SA1100_MACH_TYTE_MS301	MACH_TYTE_MS301		159
-mx1ads			ARCH_MX1ADS		MX1ADS			160
-h7201			ARCH_H7201		H7201			161
-h7202			ARCH_H7202		H7202			162
-amico			ARCH_AMICO		AMICO			163
-iam			SA1100_IAM		IAM			164
-tt530			SA1100_TT530		TT530			165
-sam2400			ARCH_SAM2400		SAM2400			166
-jornada56x		SA1100_JORNADA56X	JORNADA56X		167
-active			SA1100_ACTIVE		ACTIVE			168
-iq80321			ARCH_IQ80321		IQ80321			169
-wid			SA1100_WID		WID			170
-sabinal			ARCH_SABINAL		SABINAL			171
-ixp425_matacumbe	ARCH_IXP425_MATACUMBE	IXP425_MATACUMBE	172
-miniprint		SA1100_MINIPRINT	MINIPRINT		173
-adm510x			ARCH_ADM510X		ADM510X			174
-svs200			SA1100_SVS200		SVS200			175
-atg_tcu			ARCH_ATG_TCU		ATG_TCU			176
-jornada820		SA1100_JORNADA820	JORNADA820		177
-s3c44b0			ARCH_S3C44B0		S3C44B0			178
-margis2			ARCH_MARGIS2		MARGIS2			179
-ks8695			ARCH_KS8695		KS8695			180
-brh			ARCH_BRH		BRH			181
-s3c2410			ARCH_S3C2410		S3C2410			182
-possio_px30		ARCH_POSSIO_PX30	POSSIO_PX30		183
-s3c2800			ARCH_S3C2800		S3C2800			184
-fleetwood		SA1100_FLEETWOOD	FLEETWOOD		185
-omaha			ARCH_OMAHA		OMAHA			186
-ta7			ARCH_TA7		TA7			187
-nova			SA1100_NOVA		NOVA			188
-hmk			ARCH_HMK		HMK			189
-karo			ARCH_KARO		KARO			190
-fester			SA1100_FESTER		FESTER			191
-gpi			ARCH_GPI		GPI			192
-smdk2410		ARCH_SMDK2410		SMDK2410		193
-i519			ARCH_I519		I519			194
-nexio			SA1100_NEXIO		NEXIO			195
-bitbox			SA1100_BITBOX		BITBOX			196
-g200			SA1100_G200		G200			197
-gill			SA1100_GILL		GILL			198
-pxa_mercury		ARCH_PXA_MERCURY	PXA_MERCURY		199
-ceiva			ARCH_CEIVA		CEIVA			200
-fret			SA1100_FRET		FRET			201
-emailphone		SA1100_EMAILPHONE	EMAILPHONE		202
-h3900			ARCH_H3900		H3900			203
-pxa1			ARCH_PXA1		PXA1			204
-koan369			SA1100_KOAN369		KOAN369			205
-cogent			ARCH_COGENT		COGENT			206
-esl_simputer		ARCH_ESL_SIMPUTER	ESL_SIMPUTER		207
-esl_simputer_clr	ARCH_ESL_SIMPUTER_CLR	ESL_SIMPUTER_CLR	208
-esl_simputer_bw		ARCH_ESL_SIMPUTER_BW	ESL_SIMPUTER_BW		209
-hhp_cradle		ARCH_HHP_CRADLE		HHP_CRADLE		210
-he500			ARCH_HE500		HE500			211
-inhandelf2		SA1100_INHANDELF2	INHANDELF2		212
-inhandftip		SA1100_INHANDFTIP	INHANDFTIP		213
-dnp1110			SA1100_DNP1110		DNP1110			214
-pnp1110			SA1100_PNP1110		PNP1110			215
-csb226			ARCH_CSB226		CSB226			216
-arnold			SA1100_ARNOLD		ARNOLD			217
-voiceblue		MACH_VOICEBLUE		VOICEBLUE		218
-jz8028			ARCH_JZ8028		JZ8028			219
-h5400			ARCH_H5400		H5400			220
-forte			SA1100_FORTE		FORTE			221
-acam			SA1100_ACAM		ACAM			222
-abox			SA1100_ABOX		ABOX			223
-atmel			ARCH_ATMEL		ATMEL			224
-sitsang			ARCH_SITSANG		SITSANG			225
-cpu1110lcdnet		SA1100_CPU1110LCDNET	CPU1110LCDNET		226
-mpl_vcma9		ARCH_MPL_VCMA9		MPL_VCMA9		227
-opus_a1			ARCH_OPUS_A1		OPUS_A1			228
-daytona			ARCH_DAYTONA		DAYTONA			229
-killbear		SA1100_KILLBEAR		KILLBEAR		230
-yoho			ARCH_YOHO		YOHO			231
-jasper			ARCH_JASPER		JASPER			232
-dsc25			ARCH_DSC25		DSC25			233
-omap_innovator		MACH_OMAP_INNOVATOR	OMAP_INNOVATOR		234
-mnci			ARCH_RAMSES		RAMSES			235
-s28x			ARCH_S28X		S28X			236
-mport3			ARCH_MPORT3		MPORT3			237
-pxa_eagle250		ARCH_PXA_EAGLE250	PXA_EAGLE250		238
-pdb			ARCH_PDB		PDB			239
-blue_2g			SA1100_BLUE_2G		BLUE_2G			240
-bluearch		SA1100_BLUEARCH		BLUEARCH		241
-ixdp2400		ARCH_IXDP2400		IXDP2400		242
-ixdp2800		ARCH_IXDP2800		IXDP2800		243
-explorer		SA1100_EXPLORER		EXPLORER		244
-ixdp425			ARCH_IXDP425		IXDP425			245
-chimp			ARCH_CHIMP		CHIMP			246
-stork_nest		ARCH_STORK_NEST		STORK_NEST		247
-stork_egg		ARCH_STORK_EGG		STORK_EGG		248
-wismo			SA1100_WISMO		WISMO			249
-ezlinx			ARCH_EZLINX		EZLINX			250
-at91rm9200		ARCH_AT91RM9200		AT91RM9200		251
-adtech_orion		ARCH_ADTECH_ORION	ADTECH_ORION		252
-neptune			ARCH_NEPTUNE		NEPTUNE			253
-hackkit			SA1100_HACKKIT		HACKKIT			254
-pxa_wins30		ARCH_PXA_WINS30		PXA_WINS30		255
-lavinna			SA1100_LAVINNA		LAVINNA			256
-pxa_uengine		ARCH_PXA_UENGINE	PXA_UENGINE		257
-innokom			ARCH_INNOKOM		INNOKOM			258
-bms			ARCH_BMS		BMS			259
-ixcdp1100		ARCH_IXCDP1100		IXCDP1100		260
-prpmc1100		ARCH_PRPMC1100		PRPMC1100		261
-at91rm9200dk		ARCH_AT91RM9200DK	AT91RM9200DK		262
-armstick		ARCH_ARMSTICK		ARMSTICK		263
-armonie			ARCH_ARMONIE		ARMONIE			264
-mport1			ARCH_MPORT1		MPORT1			265
-s3c5410			ARCH_S3C5410		S3C5410			266
-zcp320a			ARCH_ZCP320A		ZCP320A			267
-i_box			ARCH_I_BOX		I_BOX			268
-stlc1502		ARCH_STLC1502		STLC1502		269
-siren			ARCH_SIREN		SIREN			270
-greenlake		ARCH_GREENLAKE		GREENLAKE		271
-argus			ARCH_ARGUS		ARGUS			272
-combadge		SA1100_COMBADGE		COMBADGE		273
-rokepxa			ARCH_ROKEPXA		ROKEPXA			274
-cintegrator		ARCH_CINTEGRATOR	CINTEGRATOR		275
-guidea07		ARCH_GUIDEA07		GUIDEA07		276
-tat257			ARCH_TAT257		TAT257			277
-igp2425			ARCH_IGP2425		IGP2425			278
-bluegrama		ARCH_BLUEGRAMMA		BLUEGRAMMA		279
-ipod			ARCH_IPOD		IPOD			280
-adsbitsyx		ARCH_ADSBITSYX		ADSBITSYX		281
-trizeps2		ARCH_TRIZEPS2		TRIZEPS2		282
-viper			ARCH_VIPER		VIPER			283
-adsbitsyplus		SA1100_ADSBITSYPLUS	ADSBITSYPLUS		284
-adsagc			SA1100_ADSAGC		ADSAGC			285
-stp7312			ARCH_STP7312		STP7312			286
-nx_phnx			MACH_NX_PHNX		NX_PHNX			287
-wep_ep250		ARCH_WEP_EP250		WEP_EP250		288
-inhandelf3		ARCH_INHANDELF3		INHANDELF3		289
-adi_coyote		ARCH_ADI_COYOTE		ADI_COYOTE		290
-iyonix			ARCH_IYONIX		IYONIX			291
-damicam1		ARCH_DAMICAM_SA1110	DAMICAM_SA1110		292
-meg03			ARCH_MEG03		MEG03			293
-pxa_whitechapel		ARCH_PXA_WHITECHAPEL	PXA_WHITECHAPEL		294
-nwsc			ARCH_NWSC		NWSC			295
-nwlarm			ARCH_NWLARM		NWLARM			296
-ixp425_mguard		ARCH_IXP425_MGUARD	IXP425_MGUARD		297
-pxa_netdcu4		ARCH_PXA_NETDCU4	PXA_NETDCU4		298
-ixdp2401		ARCH_IXDP2401		IXDP2401		299
-ixdp2801		ARCH_IXDP2801		IXDP2801		300
-zodiac			ARCH_ZODIAC		ZODIAC			301
-armmodul		ARCH_ARMMODUL		ARMMODUL		302
-ketop			SA1100_KETOP		KETOP			303
-av7200			ARCH_AV7200		AV7200			304
-arch_ti925		ARCH_ARCH_TI925		ARCH_TI925		305
-acq200			ARCH_ACQ200		ACQ200			306
-pt_dafit		SA1100_PT_DAFIT		PT_DAFIT		307
-ihba			ARCH_IHBA		IHBA			308
-quinque			ARCH_QUINQUE		QUINQUE			309
-nimbraone		ARCH_NIMBRAONE		NIMBRAONE		310
-nimbra29x		ARCH_NIMBRA29X		NIMBRA29X		311
-nimbra210		ARCH_NIMBRA210		NIMBRA210		312
-hhp_d95xx		ARCH_HHP_D95XX		HHP_D95XX		313
-labarm			ARCH_LABARM		LABARM			314
-m825xx			ARCH_M825XX		M825XX			315
-m7100			SA1100_M7100		M7100			316
-nipc2			ARCH_NIPC2		NIPC2			317
-fu7202			ARCH_FU7202		FU7202			318
-adsagx			ARCH_ADSAGX		ADSAGX			319
-pxa_pooh		ARCH_PXA_POOH		PXA_POOH		320
-bandon			ARCH_BANDON		BANDON			321
-pcm7210			ARCH_PCM7210		PCM7210			322
-nms9200			ARCH_NMS9200		NMS9200			323
-logodl			ARCH_LOGODL		LOGODL			324
-m7140			SA1100_M7140		M7140			325
-korebot			ARCH_KOREBOT		KOREBOT			326
-iq31244			ARCH_IQ31244		IQ31244			327
-koan393			SA1100_KOAN393		KOAN393			328
-inhandftip3		ARCH_INHANDFTIP3	INHANDFTIP3		329
-gonzo			ARCH_GONZO		GONZO			330
-bast			ARCH_BAST		BAST			331
-scanpass		ARCH_SCANPASS		SCANPASS		332
-ep7312_pooh		ARCH_EP7312_POOH	EP7312_POOH		333
-ta7s			ARCH_TA7S		TA7S			334
-ta7v			ARCH_TA7V		TA7V			335
-icarus			SA1100_ICARUS		ICARUS			336
-h1900			ARCH_H1900		H1900			337
-gemini			SA1100_GEMINI		GEMINI			338
-axim			ARCH_AXIM		AXIM			339
-audiotron		ARCH_AUDIOTRON		AUDIOTRON		340
-h2200			ARCH_H2200		H2200			341
-loox600			ARCH_LOOX600		LOOX600			342
-niop			ARCH_NIOP		NIOP			343
-dm310			ARCH_DM310		DM310			344
-seedpxa_c2		ARCH_SEEDPXA_C2		SEEDPXA_C2		345
-ixp4xx_mguardpci	ARCH_IXP4XX_MGUARD_PCI	IXP4XX_MGUARD_PCI	346
-h1940			ARCH_H1940		H1940			347
-scorpio			ARCH_SCORPIO		SCORPIO			348
-viva			ARCH_VIVA		VIVA			349
-pxa_xcard		ARCH_PXA_XCARD		PXA_XCARD		350
-csb335			ARCH_CSB335		CSB335			351
-ixrd425			ARCH_IXRD425		IXRD425			352
-iq80315			ARCH_IQ80315		IQ80315			353
-nmp7312			ARCH_NMP7312		NMP7312			354
-cx861xx			ARCH_CX861XX		CX861XX			355
-enp2611			ARCH_ENP2611		ENP2611			356
-xda			SA1100_XDA		XDA			357
-csir_ims		ARCH_CSIR_IMS		CSIR_IMS		358
-ixp421_dnaeeth		ARCH_IXP421_DNAEETH	IXP421_DNAEETH		359
-pocketserv9200		ARCH_POCKETSERV9200	POCKETSERV9200		360
-toto			ARCH_TOTO		TOTO			361
-s3c2440			ARCH_S3C2440		S3C2440			362
-ks8695p			ARCH_KS8695P		KS8695P			363
-se4000			ARCH_SE4000		SE4000			364
-quadriceps		ARCH_QUADRICEPS		QUADRICEPS		365
-bronco			ARCH_BRONCO		BRONCO			366
-esl_wireless_tab	ARCH_ESL_WIRELESS_TAB	ESL_WIRELESS_TAB	367
-esl_sofcomp		ARCH_ESL_SOFCOMP	ESL_SOFCOMP		368
-s5c7375			ARCH_S5C7375		S5C7375			369
-spearhead		ARCH_SPEARHEAD		SPEARHEAD		370
-pantera			ARCH_PANTERA		PANTERA			371
-prayoglite		ARCH_PRAYOGLITE		PRAYOGLITE		372
-gumstix			ARCH_GUMSTIX		GUMSTIX			373
-rcube			ARCH_RCUBE		RCUBE			374
-rea_olv			ARCH_REA_OLV		REA_OLV			375
-pxa_iphone		ARCH_PXA_IPHONE		PXA_IPHONE		376
-s3c3410			ARCH_S3C3410		S3C3410			377
-espd_4510b		ARCH_ESPD_4510B		ESPD_4510B		378
-mp1x			ARCH_MP1X		MP1X			379
-at91rm9200tb		ARCH_AT91RM9200TB	AT91RM9200TB		380
-adsvgx			ARCH_ADSVGX		ADSVGX			381
-omap_h2			MACH_OMAP_H2		OMAP_H2			382
-pelee			ARCH_PELEE		PELEE			383
-e740			MACH_E740		E740			384
-iq80331			ARCH_IQ80331		IQ80331			385
-versatile_pb		ARCH_VERSATILE_PB	VERSATILE_PB		387
-kev7a400		MACH_KEV7A400		KEV7A400		388
-lpd7a400		MACH_LPD7A400		LPD7A400		389
-lpd7a404		MACH_LPD7A404		LPD7A404		390
-fujitsu_camelot		ARCH_FUJITSU_CAMELOT	FUJITSU_CAMELOT		391
-janus2m			ARCH_JANUS2M		JANUS2M			392
-embtf			MACH_EMBTF		EMBTF			393
-hpm			MACH_HPM		HPM			394
-smdk2410tk		MACH_SMDK2410TK		SMDK2410TK		395
-smdk2410aj		MACH_SMDK2410AJ		SMDK2410AJ		396
-streetracer		MACH_STREETRACER	STREETRACER		397
-eframe			MACH_EFRAME		EFRAME			398
-csb337			MACH_CSB337		CSB337			399
-pxa_lark		MACH_PXA_LARK		PXA_LARK		400
-pxa_pnp2110		MACH_PNP2110		PNP2110			401
-tcc72x			MACH_TCC72X		TCC72X			402
-altair			MACH_ALTAIR		ALTAIR			403
-kc3			MACH_KC3		KC3			404
-sinteftd		MACH_SINTEFTD		SINTEFTD		405
-mainstone		MACH_MAINSTONE		MAINSTONE		406
-aday4x			MACH_ADAY4X		ADAY4X			407
-lite300			MACH_LITE300		LITE300			408
-s5c7376			MACH_S5C7376		S5C7376			409
-mt02			MACH_MT02		MT02			410
-mport3s			MACH_MPORT3S		MPORT3S			411
-ra_alpha		MACH_RA_ALPHA		RA_ALPHA		412
-xcep			MACH_XCEP		XCEP			413
-arcom_vulcan		MACH_ARCOM_VULCAN	ARCOM_VULCAN		414
-stargate		MACH_STARGATE		STARGATE		415
-armadilloj		MACH_ARMADILLOJ		ARMADILLOJ		416
-elroy_jack		MACH_ELROY_JACK		ELROY_JACK		417
-backend			MACH_BACKEND		BACKEND			418
-s5linbox		MACH_S5LINBOX		S5LINBOX		419
-nomadik			MACH_NOMADIK		NOMADIK			420
-ia_cpu_9200		MACH_IA_CPU_9200	IA_CPU_9200		421
-at91_bja1		MACH_AT91_BJA1		AT91_BJA1		422
-corgi			MACH_CORGI		CORGI			423
-poodle			MACH_POODLE		POODLE			424
-ten			MACH_TEN		TEN			425
-roverp5p		MACH_ROVERP5P		ROVERP5P		426
-sc2700			MACH_SC2700		SC2700			427
-ex_eagle		MACH_EX_EAGLE		EX_EAGLE		428
-nx_pxa12		MACH_NX_PXA12		NX_PXA12		429
-nx_pxa5			MACH_NX_PXA5		NX_PXA5			430
-blackboard2		MACH_BLACKBOARD2	BLACKBOARD2		431
-i819			MACH_I819		I819			432
-ixmb995e		MACH_IXMB995E		IXMB995E		433
-skyrider		MACH_SKYRIDER		SKYRIDER		434
-skyhawk			MACH_SKYHAWK		SKYHAWK			435
-enterprise		MACH_ENTERPRISE		ENTERPRISE		436
-dep2410			MACH_DEP2410		DEP2410			437
-armcore			MACH_ARMCORE		ARMCORE			438
-hobbit			MACH_HOBBIT		HOBBIT			439
-h7210			MACH_H7210		H7210			440
-pxa_netdcu5		MACH_PXA_NETDCU5	PXA_NETDCU5		441
-acc			MACH_ACC		ACC			442
-esl_sarva		MACH_ESL_SARVA		ESL_SARVA		443
-xm250			MACH_XM250		XM250			444
-t6tc1xb			MACH_T6TC1XB		T6TC1XB			445
-ess710			MACH_ESS710		ESS710			446
-mx31ads			MACH_MX31ADS		MX31ADS			447
-himalaya		MACH_HIMALAYA		HIMALAYA		448
-bolfenk			MACH_BOLFENK		BOLFENK			449
-at91rm9200kr		MACH_AT91RM9200KR	AT91RM9200KR		450
-edb9312			MACH_EDB9312		EDB9312			451
-omap_generic		MACH_OMAP_GENERIC	OMAP_GENERIC		452
-aximx3			MACH_AXIMX3		AXIMX3			453
-eb67xdip		MACH_EB67XDIP		EB67XDIP		454
-webtxs			MACH_WEBTXS		WEBTXS			455
-hawk			MACH_HAWK		HAWK			456
-ccat91sbc001		MACH_CCAT91SBC001	CCAT91SBC001		457
-expresso		MACH_EXPRESSO		EXPRESSO		458
-h4000			MACH_H4000		H4000			459
-dino			MACH_DINO		DINO			460
-ml675k			MACH_ML675K		ML675K			461
-edb9301			MACH_EDB9301		EDB9301			462
-edb9315			MACH_EDB9315		EDB9315			463
-reciva_tt		MACH_RECIVA_TT		RECIVA_TT		464
-cstcb01			MACH_CSTCB01		CSTCB01			465
-cstcb1			MACH_CSTCB1		CSTCB1			466
-shadwell		MACH_SHADWELL		SHADWELL		467
-goepel263		MACH_GOEPEL263		GOEPEL263		468
-acq100			MACH_ACQ100		ACQ100			469
-mx1fs2			MACH_MX1FS2		MX1FS2			470
-hiptop_g1		MACH_HIPTOP_G1		HIPTOP_G1		471
-sparky			MACH_SPARKY		SPARKY			472
-ns9750			MACH_NS9750		NS9750			473
-phoenix			MACH_PHOENIX		PHOENIX			474
-vr1000			MACH_VR1000		VR1000			475
-deisterpxa		MACH_DEISTERPXA		DEISTERPXA		476
-bcm1160			MACH_BCM1160		BCM1160			477
-pcm022			MACH_PCM022		PCM022			478
-adsgcx			MACH_ADSGCX		ADSGCX			479
-dreadnaught		MACH_DREADNAUGHT	DREADNAUGHT		480
-dm320			MACH_DM320		DM320			481
-markov			MACH_MARKOV		MARKOV			482
-cos7a400		MACH_COS7A400		COS7A400		483
-milano			MACH_MILANO		MILANO			484
-ue9328			MACH_UE9328		UE9328			485
-uex255			MACH_UEX255		UEX255			486
-ue2410			MACH_UE2410		UE2410			487
-a620			MACH_A620		A620			488
-ocelot			MACH_OCELOT		OCELOT			489
-cheetah			MACH_CHEETAH		CHEETAH			490
-omap_perseus2		MACH_OMAP_PERSEUS2	OMAP_PERSEUS2		491
-zvue			MACH_ZVUE		ZVUE			492
-roverp1			MACH_ROVERP1		ROVERP1			493
-asidial2		MACH_ASIDIAL2		ASIDIAL2		494
-s3c24a0			MACH_S3C24A0		S3C24A0			495
-e800			MACH_E800		E800			496
-e750			MACH_E750		E750			497
-s3c5500			MACH_S3C5500		S3C5500			498
-smdk5500		MACH_SMDK5500		SMDK5500		499
-signalsync		MACH_SIGNALSYNC		SIGNALSYNC		500
-nbc			MACH_NBC		NBC			501
-kodiak			MACH_KODIAK		KODIAK			502
-netbookpro		MACH_NETBOOKPRO		NETBOOKPRO		503
-hw90200			MACH_HW90200		HW90200			504
-condor			MACH_CONDOR		CONDOR			505
-cup			MACH_CUP		CUP			506
-kite			MACH_KITE		KITE			507
-scb9328			MACH_SCB9328		SCB9328			508
-omap_h3			MACH_OMAP_H3		OMAP_H3			509
-omap_h4			MACH_OMAP_H4		OMAP_H4			510
-n10			MACH_N10		N10			511
-montejade		MACH_MONTAJADE		MONTAJADE		512
-sg560			MACH_SG560		SG560			513
-dp1000			MACH_DP1000		DP1000			514
-omap_osk		MACH_OMAP_OSK		OMAP_OSK		515
-rg100v3			MACH_RG100V3		RG100V3			516
-mx2ads			MACH_MX2ADS		MX2ADS			517
-pxa_kilo		MACH_PXA_KILO		PXA_KILO		518
-ixp4xx_eagle		MACH_IXP4XX_EAGLE	IXP4XX_EAGLE		519
-tosa			MACH_TOSA		TOSA			520
-mb2520f			MACH_MB2520F		MB2520F			521
-emc1000			MACH_EMC1000		EMC1000			522
-tidsc25			MACH_TIDSC25		TIDSC25			523
-akcpmxl			MACH_AKCPMXL		AKCPMXL			524
-av3xx			MACH_AV3XX		AV3XX			525
-avila			MACH_AVILA		AVILA			526
-pxa_mpm10		MACH_PXA_MPM10		PXA_MPM10		527
-pxa_kyanite		MACH_PXA_KYANITE	PXA_KYANITE		528
-sgold			MACH_SGOLD		SGOLD			529
-oscar			MACH_OSCAR		OSCAR			530
-epxa4usb2		MACH_EPXA4USB2		EPXA4USB2		531
-xsengine		MACH_XSENGINE		XSENGINE		532
-ip600			MACH_IP600		IP600			533
-mcan2			MACH_MCAN2		MCAN2			534
-ddi_blueridge		MACH_DDI_BLUERIDGE	DDI_BLUERIDGE		535
-skyminder		MACH_SKYMINDER		SKYMINDER		536
-lpd79520		MACH_LPD79520		LPD79520		537
-edb9302			MACH_EDB9302		EDB9302			538
-hw90340			MACH_HW90340		HW90340			539
-cip_box			MACH_CIP_BOX		CIP_BOX			540
-ivpn			MACH_IVPN		IVPN			541
-rsoc2			MACH_RSOC2		RSOC2			542
-husky			MACH_HUSKY		HUSKY			543
-boxer			MACH_BOXER		BOXER			544
-shepherd		MACH_SHEPHERD		SHEPHERD		545
-aml42800aa		MACH_AML42800AA		AML42800AA		546
-lpc2294			MACH_LPC2294		LPC2294			548
-switchgrass		MACH_SWITCHGRASS	SWITCHGRASS		549
-ens_cmu			MACH_ENS_CMU		ENS_CMU			550
-mm6_sdb			MACH_MM6_SDB		MM6_SDB			551
-saturn			MACH_SATURN		SATURN			552
-i30030evb		MACH_I30030EVB		I30030EVB		553
-mxc27530evb		MACH_MXC27530EVB	MXC27530EVB		554
-smdk2800		MACH_SMDK2800		SMDK2800		555
-mtwilson		MACH_MTWILSON		MTWILSON		556
-ziti			MACH_ZITI		ZITI			557
-grandfather		MACH_GRANDFATHER	GRANDFATHER		558
-tengine			MACH_TENGINE		TENGINE			559
-s3c2460			MACH_S3C2460		S3C2460			560
-pdm			MACH_PDM		PDM			561
-h4700			MACH_H4700		H4700			562
-h6300			MACH_H6300		H6300			563
-rz1700			MACH_RZ1700		RZ1700			564
-a716			MACH_A716		A716			565
-estk2440a		MACH_ESTK2440A		ESTK2440A		566
-atwixp425		MACH_ATWIXP425		ATWIXP425		567
-csb336			MACH_CSB336		CSB336			568
-rirm2			MACH_RIRM2		RIRM2			569
-cx23518			MACH_CX23518		CX23518			570
-cx2351x			MACH_CX2351X		CX2351X			571
-computime		MACH_COMPUTIME		COMPUTIME		572
-izarus			MACH_IZARUS		IZARUS			573
-pxa_rts			MACH_RTS		RTS			574
-se5100			MACH_SE5100		SE5100			575
-s3c2510			MACH_S3C2510		S3C2510			576
-csb437tl		MACH_CSB437TL		CSB437TL		577
-slauson			MACH_SLAUSON		SLAUSON			578
-pearlriver		MACH_PEARLRIVER		PEARLRIVER		579
-tdc_p210		MACH_TDC_P210		TDC_P210		580
-sg580			MACH_SG580		SG580			581
-wrsbcarm7		MACH_WRSBCARM7		WRSBCARM7		582
-ipd			MACH_IPD		IPD			583
-pxa_dnp2110		MACH_PXA_DNP2110	PXA_DNP2110		584
-xaeniax			MACH_XAENIAX		XAENIAX			585
-somn4250		MACH_SOMN4250		SOMN4250		586
-pleb2			MACH_PLEB2		PLEB2			587
-cornwallis		MACH_CORNWALLIS		CORNWALLIS		588
-gurney_drv		MACH_GURNEY_DRV		GURNEY_DRV		589
-chaffee			MACH_CHAFFEE		CHAFFEE			590
-rms101			MACH_RMS101		RMS101			591
-rx3715			MACH_RX3715		RX3715			592
-swift			MACH_SWIFT		SWIFT			593
-roverp7			MACH_ROVERP7		ROVERP7			594
-pr818s			MACH_PR818S		PR818S			595
-trxpro			MACH_TRXPRO		TRXPRO			596
-nslu2			MACH_NSLU2		NSLU2			597
-e400			MACH_E400		E400			598
-trab			MACH_TRAB		TRAB			599
-cmc_pu2			MACH_CMC_PU2		CMC_PU2			600
-fulcrum			MACH_FULCRUM		FULCRUM			601
-netgate42x		MACH_NETGATE42X		NETGATE42X		602
-str710			MACH_STR710		STR710			603
-ixdpg425		MACH_IXDPG425		IXDPG425		604
-tomtomgo		MACH_TOMTOMGO		TOMTOMGO		605
-versatile_ab		MACH_VERSATILE_AB	VERSATILE_AB		606
-edb9307			MACH_EDB9307		EDB9307			607
-sg565			MACH_SG565		SG565			608
-lpd79524		MACH_LPD79524		LPD79524		609
-lpd79525		MACH_LPD79525		LPD79525		610
-rms100			MACH_RMS100		RMS100			611
-kb9200			MACH_KB9200		KB9200			612
-sx1			MACH_SX1		SX1			613
-hms39c7092		MACH_HMS39C7092		HMS39C7092		614
-armadillo		MACH_ARMADILLO		ARMADILLO		615
-ipcu			MACH_IPCU		IPCU			616
-loox720			MACH_LOOX720		LOOX720			617
-ixdp465			MACH_IXDP465		IXDP465			618
-ixdp2351		MACH_IXDP2351		IXDP2351		619
-adsvix			MACH_ADSVIX		ADSVIX			620
-dm270			MACH_DM270		DM270			621
-socltplus		MACH_SOCLTPLUS		SOCLTPLUS		622
-ecia			MACH_ECIA		ECIA			623
-cm4008			MACH_CM4008		CM4008			624
-p2001			MACH_P2001		P2001			625
-twister			MACH_TWISTER		TWISTER			626
-mudshark		MACH_MUDSHARK		MUDSHARK		627
-hb2			MACH_HB2		HB2			628
-iq80332			MACH_IQ80332		IQ80332			629
-sendt			MACH_SENDT		SENDT			630
-mx2jazz			MACH_MX2JAZZ		MX2JAZZ			631
-multiio			MACH_MULTIIO		MULTIIO			632
-hrdisplay		MACH_HRDISPLAY		HRDISPLAY		633
-mxc27530ads		MACH_MXC27530ADS	MXC27530ADS		634
-trizeps3		MACH_TRIZEPS3		TRIZEPS3		635
-zefeerdza		MACH_ZEFEERDZA		ZEFEERDZA		636
-zefeerdzb		MACH_ZEFEERDZB		ZEFEERDZB		637
-zefeerdzg		MACH_ZEFEERDZG		ZEFEERDZG		638
-zefeerdzn		MACH_ZEFEERDZN		ZEFEERDZN		639
-zefeerdzq		MACH_ZEFEERDZQ		ZEFEERDZQ		640
-gtwx5715		MACH_GTWX5715		GTWX5715		641
-astro_jack		MACH_ASTRO_JACK		ASTRO_JACK		643
-tip03			MACH_TIP03		TIP03			644
-a9200ec			MACH_A9200EC		A9200EC			645
-pnx0105			MACH_PNX0105		PNX0105			646
-adcpoecpu		MACH_ADCPOECPU		ADCPOECPU		647
-csb637			MACH_CSB637		CSB637			648
-mb9200			MACH_MB9200		MB9200			650
-kulun			MACH_KULUN		KULUN			651
-snapper			MACH_SNAPPER		SNAPPER			652
-optima			MACH_OPTIMA		OPTIMA			653
-dlhsbc			MACH_DLHSBC		DLHSBC			654
-x30			MACH_X30		X30			655
-n30			MACH_N30		N30			656
-manga_ks8695		MACH_MANGA_KS8695	MANGA_KS8695		657
-ajax			MACH_AJAX		AJAX			658
-nec_mp900		MACH_NEC_MP900		NEC_MP900		659
-vvtk1000		MACH_VVTK1000		VVTK1000		661
-kafa			MACH_KAFA		KAFA			662
-vvtk3000		MACH_VVTK3000		VVTK3000		663
-pimx1			MACH_PIMX1		PIMX1			664
-ollie			MACH_OLLIE		OLLIE			665
-skymax			MACH_SKYMAX		SKYMAX			666
-jazz			MACH_JAZZ		JAZZ			667
-tel_t3			MACH_TEL_T3		TEL_T3			668
-aisino_fcr255		MACH_AISINO_FCR255	AISINO_FCR255		669
-btweb			MACH_BTWEB		BTWEB			670
-dbg_lh79520		MACH_DBG_LH79520	DBG_LH79520		671
-cm41xx			MACH_CM41XX		CM41XX			672
-ts72xx			MACH_TS72XX		TS72XX			673
-nggpxa			MACH_NGGPXA		NGGPXA			674
-csb535			MACH_CSB535		CSB535			675
-csb536			MACH_CSB536		CSB536			676
-pxa_trakpod		MACH_PXA_TRAKPOD	PXA_TRAKPOD		677
-praxis			MACH_PRAXIS		PRAXIS			678
-lh75411			MACH_LH75411		LH75411			679
-otom			MACH_OTOM		OTOM			680
-nexcoder_2440		MACH_NEXCODER_2440	NEXCODER_2440		681
-loox410			MACH_LOOX410		LOOX410			682
-westlake		MACH_WESTLAKE		WESTLAKE		683
-nsb			MACH_NSB		NSB			684
-esl_sarva_stn		MACH_ESL_SARVA_STN	ESL_SARVA_STN		685
-esl_sarva_tft		MACH_ESL_SARVA_TFT	ESL_SARVA_TFT		686
-esl_sarva_iad		MACH_ESL_SARVA_IAD	ESL_SARVA_IAD		687
-esl_sarva_acc		MACH_ESL_SARVA_ACC	ESL_SARVA_ACC		688
-typhoon			MACH_TYPHOON		TYPHOON			689
-cnav			MACH_CNAV		CNAV			690
-a730			MACH_A730		A730			691
-netstar			MACH_NETSTAR		NETSTAR			692
-supercon		MACH_PHASEFALE_SUPERCON	PHASEFALE_SUPERCON	693
-shiva1100		MACH_SHIVA1100		SHIVA1100		694
-etexsc			MACH_ETEXSC		ETEXSC			695
-ixdpg465		MACH_IXDPG465		IXDPG465		696
-a9m2410			MACH_A9M2410		A9M2410			697
-a9m2440			MACH_A9M2440		A9M2440			698
-a9m9750			MACH_A9M9750		A9M9750			699
-a9m9360			MACH_A9M9360		A9M9360			700
-unc90			MACH_UNC90		UNC90			701
-eco920			MACH_ECO920		ECO920			702
-satview			MACH_SATVIEW		SATVIEW			703
-roadrunner		MACH_ROADRUNNER		ROADRUNNER		704
-at91rm9200ek		MACH_AT91RM9200EK	AT91RM9200EK		705
-gp32			MACH_GP32		GP32			706
-gem			MACH_GEM		GEM			707
-i858			MACH_I858		I858			708
-hx2750			MACH_HX2750		HX2750			709
-mxc91131evb		MACH_MXC91131EVB	MXC91131EVB		710
-p700			MACH_P700		P700			711
-cpe			MACH_CPE		CPE			712
-spitz			MACH_SPITZ		SPITZ			713
-nimbra340		MACH_NIMBRA340		NIMBRA340		714
-lpc22xx			MACH_LPC22XX		LPC22XX			715
-omap_comet3		MACH_COMET3		COMET3			716
-omap_comet4		MACH_COMET4		COMET4			717
-csb625			MACH_CSB625		CSB625			718
-fortunet2		MACH_FORTUNET2		FORTUNET2		719
-s5h2200			MACH_S5H2200		S5H2200			720
-optorm920		MACH_OPTORM920		OPTORM920		721
-adsbitsyxb		MACH_ADSBITSYXB		ADSBITSYXB		722
-adssphere		MACH_ADSSPHERE		ADSSPHERE		723
-adsportal		MACH_ADSPORTAL		ADSPORTAL		724
-ln2410sbc		MACH_LN2410SBC		LN2410SBC		725
-cb3rufc			MACH_CB3RUFC		CB3RUFC			726
-mp2usb			MACH_MP2USB		MP2USB			727
-ntnp425c		MACH_NTNP425C		NTNP425C		728
-colibri			MACH_COLIBRI		COLIBRI			729
-pcm7220			MACH_PCM7220		PCM7220			730
-gateway7001		MACH_GATEWAY7001	GATEWAY7001		731
-pcm027			MACH_PCM027		PCM027			732
-cmpxa			MACH_CMPXA		CMPXA			733
-anubis			MACH_ANUBIS		ANUBIS			734
-ite8152			MACH_ITE8152		ITE8152			735
-lpc3xxx			MACH_LPC3XXX		LPC3XXX			736
-puppeteer		MACH_PUPPETEER		PUPPETEER		737
-e570			MACH_E570		E570			739
-x50			MACH_X50		X50			740
-recon			MACH_RECON		RECON			741
-xboardgp8		MACH_XBOARDGP8		XBOARDGP8		742
-fpic2			MACH_FPIC2		FPIC2			743
-akita			MACH_AKITA		AKITA			744
-a81			MACH_A81		A81			745
-svm_sc25x		MACH_SVM_SC25X		SVM_SC25X		746
-vt020			MACH_VADATECH020	VADATECH020		747
-tli			MACH_TLI		TLI			748
-edb9315lc		MACH_EDB9315LC		EDB9315LC		749
-passec			MACH_PASSEC		PASSEC			750
-ds_tiger		MACH_DS_TIGER		DS_TIGER		751
-e310			MACH_E310		E310			752
-e330			MACH_E330		E330			753
-rt3000			MACH_RT3000		RT3000			754
-nokia770		MACH_NOKIA770		NOKIA770		755
-pnx0106			MACH_PNX0106		PNX0106			756
-hx21xx			MACH_HX21XX		HX21XX			757
-faraday			MACH_FARADAY		FARADAY			758
-sbc9312			MACH_SBC9312		SBC9312			759
-batman			MACH_BATMAN		BATMAN			760
-jpd201			MACH_JPD201		JPD201			761
-mipsa			MACH_MIPSA		MIPSA			762
-kacom			MACH_KACOM		KACOM			763
-swarcocpu		MACH_SWARCOCPU		SWARCOCPU		764
-swarcodsl		MACH_SWARCODSL		SWARCODSL		765
-blueangel		MACH_BLUEANGEL		BLUEANGEL		766
-hairygrama		MACH_HAIRYGRAMA		HAIRYGRAMA		767
-banff			MACH_BANFF		BANFF			768
-carmeva			MACH_CARMEVA		CARMEVA			769
-sam255			MACH_SAM255		SAM255			770
-ppm10			MACH_PPM10		PPM10			771
-edb9315a		MACH_EDB9315A		EDB9315A		772
-sunset			MACH_SUNSET		SUNSET			773
-stargate2		MACH_STARGATE2		STARGATE2		774
-intelmote2		MACH_INTELMOTE2		INTELMOTE2		775
-trizeps4		MACH_TRIZEPS4		TRIZEPS4		776
-mainstone2		MACH_MAINSTONE2		MAINSTONE2		777
-ez_ixp42x		MACH_EZ_IXP42X		EZ_IXP42X		778
-tapwave_zodiac		MACH_TAPWAVE_ZODIAC	TAPWAVE_ZODIAC		779
-universalmeter		MACH_UNIVERSALMETER	UNIVERSALMETER		780
-hicoarm9		MACH_HICOARM9		HICOARM9		781
-pnx4008			MACH_PNX4008		PNX4008			782
-kws6000			MACH_KWS6000		KWS6000			783
-portux920t		MACH_PORTUX920T		PORTUX920T		784
-ez_x5			MACH_EZ_X5		EZ_X5			785
-omap_rudolph		MACH_OMAP_RUDOLPH	OMAP_RUDOLPH		786
-cpuat91			MACH_CPUAT91		CPUAT91			787
-rea9200			MACH_REA9200		REA9200			788
-acts_pune_sa1110	MACH_ACTS_PUNE_SA1110	ACTS_PUNE_SA1110	789
-ixp425			MACH_IXP425		IXP425			790
-i30030ads		MACH_I30030ADS		I30030ADS		791
-perch			MACH_PERCH		PERCH			792
-eis05r1			MACH_EIS05R1		EIS05R1			793
-pepperpad		MACH_PEPPERPAD		PEPPERPAD		794
-sb3010			MACH_SB3010		SB3010			795
-rm9200			MACH_RM9200		RM9200			796
-dma03			MACH_DMA03		DMA03			797
-road_s101		MACH_ROAD_S101		ROAD_S101		798
-iq81340sc		MACH_IQ81340SC		IQ81340SC		799
-iq_nextgen_b		MACH_IQ_NEXTGEN_B	IQ_NEXTGEN_B		800
-iq81340mc		MACH_IQ81340MC		IQ81340MC		801
-iq_nextgen_d		MACH_IQ_NEXTGEN_D	IQ_NEXTGEN_D		802
-iq_nextgen_e		MACH_IQ_NEXTGEN_E	IQ_NEXTGEN_E		803
-mallow_at91		MACH_MALLOW_AT91	MALLOW_AT91		804
-cybertracker_i		MACH_CYBERTRACKER_I	CYBERTRACKER_I		805
-gesbc931x		MACH_GESBC931X		GESBC931X		806
-centipad		MACH_CENTIPAD		CENTIPAD		807
-armsoc			MACH_ARMSOC		ARMSOC			808
-se4200			MACH_SE4200		SE4200			809
-ems197a			MACH_EMS197A		EMS197A			810
-micro9			MACH_MICRO9		MICRO9			811
-micro9l			MACH_MICRO9L		MICRO9L			812
-uc5471dsp		MACH_UC5471DSP		UC5471DSP		813
-sj5471eng		MACH_SJ5471ENG		SJ5471ENG		814
-none			MACH_CMPXA26X		CMPXA26X		815
-nc1			MACH_NC			NC			816
-omap_palmte		MACH_OMAP_PALMTE	OMAP_PALMTE		817
-ajax52x			MACH_AJAX52X		AJAX52X			818
-siriustar		MACH_SIRIUSTAR		SIRIUSTAR		819
-iodata_hdlg		MACH_IODATA_HDLG	IODATA_HDLG		820
-at91rm9200utl		MACH_AT91RM9200UTL	AT91RM9200UTL		821
-biosafe			MACH_BIOSAFE		BIOSAFE			822
-mp1000			MACH_MP1000		MP1000			823
-parsy			MACH_PARSY		PARSY			824
-ccxp270			MACH_CCXP		CCXP			825
-omap_gsample		MACH_OMAP_GSAMPLE	OMAP_GSAMPLE		826
-realview_eb		MACH_REALVIEW_EB	REALVIEW_EB		827
-samoa			MACH_SAMOA		SAMOA			828
-palmt3			MACH_PALMT3		PALMT3			829
-i878			MACH_I878		I878			830
-borzoi			MACH_BORZOI		BORZOI			831
-gecko			MACH_GECKO		GECKO			832
-ds101			MACH_DS101		DS101			833
-omap_palmtt2		MACH_OMAP_PALMTT2	OMAP_PALMTT2		834
-palmld			MACH_PALMLD		PALMLD			835
-cc9c			MACH_CC9C		CC9C			836
-sbc1670			MACH_SBC1670		SBC1670			837
-ixdp28x5		MACH_IXDP28X5		IXDP28X5		838
-omap_palmtt		MACH_OMAP_PALMTT	OMAP_PALMTT		839
-ml696k			MACH_ML696K		ML696K			840
-arcom_zeus		MACH_ARCOM_ZEUS		ARCOM_ZEUS		841
-osiris			MACH_OSIRIS		OSIRIS			842
-maestro			MACH_MAESTRO		MAESTRO			843
-palmte2			MACH_PALMTE2		PALMTE2			844
-ixbbm			MACH_IXBBM		IXBBM			845
-mx27ads			MACH_MX27ADS		MX27ADS			846
-ax8004			MACH_AX8004		AX8004			847
-at91sam9261ek		MACH_AT91SAM9261EK	AT91SAM9261EK		848
-loft			MACH_LOFT		LOFT			849
-magpie			MACH_MAGPIE		MAGPIE			850
-mx21ads			MACH_MX21ADS		MX21ADS			851
-mb87m3400		MACH_MB87M3400		MB87M3400		852
-mguard_delta		MACH_MGUARD_DELTA	MGUARD_DELTA		853
-davinci_dvdp		MACH_DAVINCI_DVDP	DAVINCI_DVDP		854
-htcuniversal		MACH_HTCUNIVERSAL	HTCUNIVERSAL		855
-tpad			MACH_TPAD		TPAD			856
-roverp3			MACH_ROVERP3		ROVERP3			857
-jornada928		MACH_JORNADA928		JORNADA928		858
-mv88fxx81		MACH_MV88FXX81		MV88FXX81		859
-stmp36xx		MACH_STMP36XX		STMP36XX		860
-sxni79524		MACH_SXNI79524		SXNI79524		861
-ams_delta		MACH_AMS_DELTA		AMS_DELTA		862
-uranium			MACH_URANIUM		URANIUM			863
-ucon			MACH_UCON		UCON			864
-nas100d			MACH_NAS100D		NAS100D			865
-l083			MACH_L083_1000		L083_1000		866
-ezx			MACH_EZX		EZX			867
-pnx5220			MACH_PNX5220		PNX5220			868
-butte			MACH_BUTTE		BUTTE			869
-srm2			MACH_SRM2		SRM2			870
-dsbr			MACH_DSBR		DSBR			871
-crystalball		MACH_CRYSTALBALL	CRYSTALBALL		872
-tinypxa27x		MACH_TINYPXA27X		TINYPXA27X		873
-herbie			MACH_HERBIE		HERBIE			874
-magician		MACH_MAGICIAN		MAGICIAN		875
-cm4002			MACH_CM4002		CM4002			876
-b4			MACH_B4			B4			877
-maui			MACH_MAUI		MAUI			878
-cybertracker_g		MACH_CYBERTRACKER_G	CYBERTRACKER_G		879
-nxdkn			MACH_NXDKN		NXDKN			880
-mio8390			MACH_MIO8390		MIO8390			881
-omi_board		MACH_OMI_BOARD		OMI_BOARD		882
-mx21civ			MACH_MX21CIV		MX21CIV			883
-mahi_cdac		MACH_MAHI_CDAC		MAHI_CDAC		884
-palmtx			MACH_PALMTX		PALMTX			885
-s3c2413			MACH_S3C2413		S3C2413			887
-samsys_ep0		MACH_SAMSYS_EP0		SAMSYS_EP0		888
-wg302v1			MACH_WG302V1		WG302V1			889
-wg302v2			MACH_WG302V2		WG302V2			890
-eb42x			MACH_EB42X		EB42X			891
-iq331es			MACH_IQ331ES		IQ331ES			892
-cosydsp			MACH_COSYDSP		COSYDSP			893
-uplat7d_proto		MACH_UPLAT7D		UPLAT7D			894
-ptdavinci		MACH_PTDAVINCI		PTDAVINCI		895
-mbus			MACH_MBUS		MBUS			896
-nadia2vb		MACH_NADIA2VB		NADIA2VB		897
-r1000			MACH_R1000		R1000			898
-hw90250			MACH_HW90250		HW90250			899
-omap_2430sdp		MACH_OMAP_2430SDP	OMAP_2430SDP		900
-davinci_evm		MACH_DAVINCI_EVM	DAVINCI_EVM		901
-omap_tornado		MACH_OMAP_TORNADO	OMAP_TORNADO		902
-olocreek		MACH_OLOCREEK		OLOCREEK		903
-palmz72			MACH_PALMZ72		PALMZ72			904
-nxdb500			MACH_NXDB500		NXDB500			905
-apf9328			MACH_APF9328		APF9328			906
-omap_wipoq		MACH_OMAP_WIPOQ		OMAP_WIPOQ		907
-omap_twip		MACH_OMAP_TWIP		OMAP_TWIP		908
-treo650			MACH_TREO650		TREO650			909
-acumen			MACH_ACUMEN		ACUMEN			910
-xp100			MACH_XP100		XP100			911
-fs2410			MACH_FS2410		FS2410			912
-pxa270_cerf		MACH_PXA270_CERF	PXA270_CERF		913
-sq2ftlpalm		MACH_SQ2FTLPALM		SQ2FTLPALM		914
-bsemserver		MACH_BSEMSERVER		BSEMSERVER		915
-netclient		MACH_NETCLIENT		NETCLIENT		916
-palmt5			MACH_PALMT5		PALMT5			917
-palmtc			MACH_PALMTC		PALMTC			918
-omap_apollon		MACH_OMAP_APOLLON	OMAP_APOLLON		919
-mxc30030evb		MACH_MXC30030EVB	MXC30030EVB		920
-rea_cpu2		MACH_REA_2D		REA_2D			921
-eti3e524		MACH_TI3E524		TI3E524			922
-ateb9200		MACH_ATEB9200		ATEB9200		923
-auckland		MACH_AUCKLAND		AUCKLAND		924
-ak3220m			MACH_AK3320M		AK3320M			925
-duramax			MACH_DURAMAX		DURAMAX			926
-n35			MACH_N35		N35			927
-pronghorn		MACH_PRONGHORN		PRONGHORN		928
-fundy			MACH_FUNDY		FUNDY			929
-logicpd_pxa270		MACH_LOGICPD_PXA270	LOGICPD_PXA270		930
-cpu777			MACH_CPU777		CPU777			931
-simicon9201		MACH_SIMICON9201	SIMICON9201		932
-leap2_hpm		MACH_LEAP2_HPM		LEAP2_HPM		933
-cm922txa10		MACH_CM922TXA10		CM922TXA10		934
-sandgate		MACH_PXA		PXA			935
-sandgate2		MACH_SANDGATE2		SANDGATE2		936
-sandgate2g		MACH_SANDGATE2G		SANDGATE2G		937
-sandgate2p		MACH_SANDGATE2P		SANDGATE2P		938
-fred_jack		MACH_FRED_JACK		FRED_JACK		939
-ttg_color1		MACH_TTG_COLOR1		TTG_COLOR1		940
-nxeb500hmi		MACH_NXEB500HMI		NXEB500HMI		941
-netdcu8			MACH_NETDCU8		NETDCU8			942
-ng_fvx538		MACH_NG_FVX538		NG_FVX538		944
-ng_fvs338		MACH_NG_FVS338		NG_FVS338		945
-pnx4103			MACH_PNX4103		PNX4103			946
-hesdb			MACH_HESDB		HESDB			947
-xsilo			MACH_XSILO		XSILO			948
-espresso		MACH_ESPRESSO		ESPRESSO		949
-emlc			MACH_EMLC		EMLC			950
-sisteron		MACH_SISTERON		SISTERON		951
-rx1950			MACH_RX1950		RX1950			952
-tsc_venus		MACH_TSC_VENUS		TSC_VENUS		953
-ds101j			MACH_DS101J		DS101J			954
-mxc30030ads		MACH_MXC30030ADS	MXC30030ADS		955
-fujitsu_wimaxsoc	MACH_FUJITSU_WIMAXSOC	FUJITSU_WIMAXSOC	956
-dualpcmodem		MACH_DUALPCMODEM	DUALPCMODEM		957
-gesbc9312		MACH_GESBC9312		GESBC9312		958
-htcapache		MACH_HTCAPACHE		HTCAPACHE		959
-ixdp435			MACH_IXDP435		IXDP435			960
-catprovt100		MACH_CATPROVT100	CATPROVT100		961
-picotux1xx		MACH_PICOTUX1XX		PICOTUX1XX		962
-picotux2xx		MACH_PICOTUX2XX		PICOTUX2XX		963
-dsmg600			MACH_DSMG600		DSMG600			964
-empc2			MACH_EMPC2		EMPC2			965
-ventura			MACH_VENTURA		VENTURA			966
-phidget_sbc		MACH_PHIDGET_SBC	PHIDGET_SBC		967
-ij3k			MACH_IJ3K		IJ3K			968
-pisgah			MACH_PISGAH		PISGAH			969
-omap_fsample		MACH_OMAP_FSAMPLE	OMAP_FSAMPLE		970
-sg720			MACH_SG720		SG720			971
-redfox			MACH_REDFOX		REDFOX			972
-mysh_ep9315_1		MACH_MYSH_EP9315_1	MYSH_EP9315_1		973
-tpf106			MACH_TPF106		TPF106			974
-at91rm9200kg		MACH_AT91RM9200KG	AT91RM9200KG		975
-rcmt2			MACH_SLEDB		SLEDB			976
-ontrack			MACH_ONTRACK		ONTRACK			977
-pm1200			MACH_PM1200		PM1200			978
-ess24562		MACH_ESS24XXX		ESS24XXX		979
-coremp7			MACH_COREMP7		COREMP7			980
-nexcoder_6446		MACH_NEXCODER_6446	NEXCODER_6446		981
-stvc8380		MACH_STVC8380		STVC8380		982
-teklynx			MACH_TEKLYNX		TEKLYNX			983
-carbonado		MACH_CARBONADO		CARBONADO		984
-sysmos_mp730		MACH_SYSMOS_MP730	SYSMOS_MP730		985
-snapper_cl15		MACH_SNAPPER_CL15	SNAPPER_CL15		986
-pgigim			MACH_PGIGIM		PGIGIM			987
-ptx9160p2		MACH_PTX9160P2		PTX9160P2		988
-dcore1			MACH_DCORE1		DCORE1			989
-victorpxa		MACH_VICTORPXA		VICTORPXA		990
-mx2dtb			MACH_MX2DTB		MX2DTB			991
-pxa_irex_er0100		MACH_PXA_IREX_ER0100	PXA_IREX_ER0100		992
-omap_palmz71		MACH_OMAP_PALMZ71	OMAP_PALMZ71		993
-bartec_deg		MACH_BARTEC_DEG		BARTEC_DEG		994
-hw50251			MACH_HW50251		HW50251			995
-ibox			MACH_IBOX		IBOX			996
-atlaslh7a404		MACH_ATLASLH7A404	ATLASLH7A404		997
-pt2026			MACH_PT2026		PT2026			998
-htcalpine		MACH_HTCALPINE		HTCALPINE		999
-bartec_vtu		MACH_BARTEC_VTU		BARTEC_VTU		1000
-vcoreii			MACH_VCOREII		VCOREII			1001
-pdnb3			MACH_PDNB3		PDNB3			1002
-htcbeetles		MACH_HTCBEETLES		HTCBEETLES		1003
-s3c6400			MACH_S3C6400		S3C6400			1004
-s3c2443			MACH_S3C2443		S3C2443			1005
-omap_ldk		MACH_OMAP_LDK		OMAP_LDK		1006
-smdk2460		MACH_SMDK2460		SMDK2460		1007
-smdk2440		MACH_SMDK2440		SMDK2440		1008
-smdk2412		MACH_SMDK2412		SMDK2412		1009
-webbox			MACH_WEBBOX		WEBBOX			1010
-cwwndp			MACH_CWWNDP		CWWNDP			1011
-i839			MACH_DRAGON		DRAGON			1012
-opendo_cpu_board	MACH_OPENDO_CPU_BOARD	OPENDO_CPU_BOARD	1013
-ccm2200			MACH_CCM2200		CCM2200			1014
-etwarm			MACH_ETWARM		ETWARM			1015
-m93030			MACH_M93030		M93030			1016
-cc7u			MACH_CC7U		CC7U			1017
-mtt_ranger		MACH_MTT_RANGER		MTT_RANGER		1018
-nexus			MACH_NEXUS		NEXUS			1019
-desman			MACH_DESMAN		DESMAN			1020
-bkde303			MACH_BKDE303		BKDE303			1021
-smdk2413		MACH_SMDK2413		SMDK2413		1022
-aml_m7200		MACH_AML_M7200		AML_M7200		1023
-aml_m5900		MACH_AML_M5900		AML_M5900		1024
-sg640			MACH_SG640		SG640			1025
-edg79524		MACH_EDG79524		EDG79524		1026
-ai2410			MACH_AI2410		AI2410			1027
-ixp465			MACH_IXP465		IXP465			1028
-balloon3		MACH_BALLOON3		BALLOON3		1029
-heins			MACH_HEINS		HEINS			1030
-mpluseva		MACH_MPLUSEVA		MPLUSEVA		1031
-rt042			MACH_RT042		RT042			1032
-cwiem			MACH_CWIEM		CWIEM			1033
-cm_x270			MACH_CM_X270		CM_X270			1034
-cm_x255			MACH_CM_X255		CM_X255			1035
-esh_at91		MACH_ESH_AT91		ESH_AT91		1036
-sandgate3		MACH_SANDGATE3		SANDGATE3		1037
-primo			MACH_PRIMO		PRIMO			1038
-gemstone		MACH_GEMSTONE		GEMSTONE		1039
-pronghorn_metro		MACH_PRONGHORNMETRO	PRONGHORNMETRO		1040
-sidewinder		MACH_SIDEWINDER		SIDEWINDER		1041
-picomod1		MACH_PICOMOD1		PICOMOD1		1042
-sg590			MACH_SG590		SG590			1043
-akai9307		MACH_AKAI9307		AKAI9307		1044
-fontaine		MACH_FONTAINE		FONTAINE		1045
-wombat			MACH_WOMBAT		WOMBAT			1046
-acq300			MACH_ACQ300		ACQ300			1047
-mod272			MACH_MOD_270		MOD_270			1048
-vmc_vc0820		MACH_VC0820		VC0820			1049
-ani_aim			MACH_ANI_AIM		ANI_AIM			1050
-jellyfish		MACH_JELLYFISH		JELLYFISH		1051
-amanita			MACH_AMANITA		AMANITA			1052
-vlink			MACH_VLINK		VLINK			1053
-dexflex			MACH_DEXFLEX		DEXFLEX			1054
-eigen_ttq		MACH_EIGEN_TTQ		EIGEN_TTQ		1055
-arcom_titan		MACH_ARCOM_TITAN	ARCOM_TITAN		1056
-tabla			MACH_TABLA		TABLA			1057
-mdirac3			MACH_MDIRAC3		MDIRAC3			1058
-mrhfbp2			MACH_MRHFBP2		MRHFBP2			1059
-at91rm9200rb		MACH_AT91RM9200RB	AT91RM9200RB		1060
-ani_apm			MACH_ANI_APM		ANI_APM			1061
-ella1			MACH_ELLA1		ELLA1			1062
-inhand_pxa27x		MACH_INHAND_PXA27X	INHAND_PXA27X		1063
-inhand_pxa25x		MACH_INHAND_PXA25X	INHAND_PXA25X		1064
-empos_xm		MACH_EMPOS_XM		EMPOS_XM		1065
-empos			MACH_EMPOS		EMPOS			1066
-empos_tiny		MACH_EMPOS_TINY		EMPOS_TINY		1067
-empos_sm		MACH_EMPOS_SM		EMPOS_SM		1068
-egret			MACH_EGRET		EGRET			1069
-ostrich			MACH_OSTRICH		OSTRICH			1070
-n50			MACH_N50		N50			1071
-ecbat91			MACH_ECBAT91		ECBAT91			1072
-stareast		MACH_STAREAST		STAREAST		1073
-dspg_dw			MACH_DSPG_DW		DSPG_DW			1074
-onearm			MACH_ONEARM		ONEARM			1075
-mrg110_6		MACH_MRG110_6		MRG110_6		1076
-wrt300nv2		MACH_WRT300NV2		WRT300NV2		1077
-xm_bulverde		MACH_XM_BULVERDE	XM_BULVERDE		1078
-msm6100			MACH_MSM6100		MSM6100			1079
-eti_b1			MACH_ETI_B1		ETI_B1			1080
-za9l_series		MACH_ZILOG_ZA9L		ZILOG_ZA9L		1081
-bit2440			MACH_BIT2440		BIT2440			1082
-nbi			MACH_NBI		NBI			1083
-smdk2443		MACH_SMDK2443		SMDK2443		1084
-vdavinci		MACH_VDAVINCI		VDAVINCI		1085
-atc6			MACH_ATC6		ATC6			1086
-multmdw			MACH_MULTMDW		MULTMDW			1087
-mba2440			MACH_MBA2440		MBA2440			1088
-ecsd			MACH_ECSD		ECSD			1089
-palmz31			MACH_PALMZ31		PALMZ31			1090
-fsg			MACH_FSG		FSG			1091
-razor101		MACH_RAZOR101		RAZOR101		1092
-opera_tdm		MACH_OPERA_TDM		OPERA_TDM		1093
-comcerto		MACH_COMCERTO		COMCERTO		1094
-tb0319			MACH_TB0319		TB0319			1095
-kws8000			MACH_KWS8000		KWS8000			1096
-b2			MACH_B2			B2			1097
-lcl54			MACH_LCL54		LCL54			1098
-at91sam9260ek		MACH_AT91SAM9260EK	AT91SAM9260EK		1099
-glantank		MACH_GLANTANK		GLANTANK		1100
-n2100			MACH_N2100		N2100			1101
-n4100			MACH_N4100		N4100			1102
-rsc4			MACH_VERTICAL_RSC4	VERTICAL_RSC4		1103
-sg8100			MACH_SG8100		SG8100			1104
-im42xx			MACH_IM42XX		IM42XX			1105
-ftxx			MACH_FTXX		FTXX			1106
-lwfusion		MACH_LWFUSION		LWFUSION		1107
-qt2410			MACH_QT2410		QT2410			1108
-kixrp435		MACH_KIXRP435		KIXRP435		1109
-ccw9c			MACH_CCW9C		CCW9C			1110
-dabhs			MACH_DABHS		DABHS			1111
-gzmx			MACH_GZMX		GZMX			1112
-ipnw100ap		MACH_IPNW100AP		IPNW100AP		1113
-cc9p9360dev		MACH_CC9P9360DEV	CC9P9360DEV		1114
-cc9p9750dev		MACH_CC9P9750DEV	CC9P9750DEV		1115
-cc9p9360val		MACH_CC9P9360VAL	CC9P9360VAL		1116
-cc9p9750val		MACH_CC9P9750VAL	CC9P9750VAL		1117
-nx70v			MACH_NX70V		NX70V			1118
-at91rm9200df		MACH_AT91RM9200DF	AT91RM9200DF		1119
-se_pilot2		MACH_SE_PILOT2		SE_PILOT2		1120
-mtcn_t800		MACH_MTCN_T800		MTCN_T800		1121
-vcmx212			MACH_VCMX212		VCMX212			1122
-lynx			MACH_LYNX		LYNX			1123
-at91sam9260id		MACH_AT91SAM9260ID	AT91SAM9260ID		1124
-hw86052			MACH_HW86052		HW86052			1125
-pilz_pmi3		MACH_PILZ_PMI3		PILZ_PMI3		1126
-edb9302a		MACH_EDB9302A		EDB9302A		1127
-edb9307a		MACH_EDB9307A		EDB9307A		1128
-ct_dfs			MACH_CT_DFS		CT_DFS			1129
-pilz_pmi4		MACH_PILZ_PMI4		PILZ_PMI4		1130
-xceednp_ixp		MACH_XCEEDNP_IXP	XCEEDNP_IXP		1131
-smdk2442b		MACH_SMDK2442B		SMDK2442B		1132
-xnode			MACH_XNODE		XNODE			1133
-aidx270			MACH_AIDX270		AIDX270			1134
-rema			MACH_REMA		REMA			1135
-bps1000			MACH_BPS1000		BPS1000			1136
-hw90350			MACH_HW90350		HW90350			1137
-omap_3430sdp		MACH_OMAP_3430SDP	OMAP_3430SDP		1138
-bluetouch		MACH_BLUETOUCH		BLUETOUCH		1139
-vstms			MACH_VSTMS		VSTMS			1140
-xsbase270		MACH_XSBASE270		XSBASE270		1141
-at91sam9260ek_cn	MACH_AT91SAM9260EK_CN	AT91SAM9260EK_CN	1142
-adsturboxb		MACH_ADSTURBOXB		ADSTURBOXB		1143
-oti4110			MACH_OTI4110		OTI4110			1144
-hme_pxa			MACH_HME_PXA		HME_PXA			1145
-deisterdca		MACH_DEISTERDCA		DEISTERDCA		1146
-ces_ssem2		MACH_CES_SSEM2		CES_SSEM2		1147
-ces_mtr			MACH_CES_MTR		CES_MTR			1148
-tds_avng_sbc		MACH_TDS_AVNG_SBC	TDS_AVNG_SBC		1149
-everest			MACH_EVEREST		EVEREST			1150
-pnx4010			MACH_PNX4010		PNX4010			1151
-oxnas			MACH_OXNAS		OXNAS			1152
-fiori			MACH_FIORI		FIORI			1153
-ml1200			MACH_ML1200		ML1200			1154
-pecos			MACH_PECOS		PECOS			1155
-nb2xxx			MACH_NB2XXX		NB2XXX			1156
-hw6900			MACH_HW6900		HW6900			1157
-cdcs_quoll		MACH_CDCS_QUOLL		CDCS_QUOLL		1158
-quicksilver		MACH_QUICKSILVER	QUICKSILVER		1159
-uplat926		MACH_UPLAT926		UPLAT926		1160
-dep2410_dep2410		MACH_DEP2410_THOMAS	DEP2410_THOMAS		1161
-dtk2410			MACH_DTK2410		DTK2410			1162
-chili			MACH_CHILI		CHILI			1163
-demeter			MACH_DEMETER		DEMETER			1164
-dionysus		MACH_DIONYSUS		DIONYSUS		1165
-as352x			MACH_AS352X		AS352X			1166
-service			MACH_SERVICE		SERVICE			1167
-cs_e9301		MACH_CS_E9301		CS_E9301		1168
-micro9m			MACH_MICRO9M		MICRO9M			1169
-ia_mospck		MACH_IA_MOSPCK		IA_MOSPCK		1170
-ql201b			MACH_QL201B		QL201B			1171
-bbm			MACH_BBM		BBM			1174
-exxx			MACH_EXXX		EXXX			1175
-wma11b			MACH_WMA11B		WMA11B			1176
-pelco_atlas		MACH_PELCO_ATLAS	PELCO_ATLAS		1177
-g500			MACH_G500		G500			1178
-bug			MACH_BUG		BUG			1179
-mx33ads			MACH_MX33ADS		MX33ADS			1180
-chub			MACH_CHUB		CHUB			1181
-neo1973_gta01		MACH_NEO1973_GTA01	NEO1973_GTA01		1182
-w90n740			MACH_W90N740		W90N740			1183
-medallion_sa2410	MACH_MEDALLION_SA2410	MEDALLION_SA2410	1184
-ia_cpu_9200_2		MACH_IA_CPU_9200_2	IA_CPU_9200_2		1185
-dimmrm9200		MACH_DIMMRM9200		DIMMRM9200		1186
-pm9261			MACH_PM9261		PM9261			1187
-ml7304			MACH_ML7304		ML7304			1189
-ucp250			MACH_UCP250		UCP250			1190
-intboard		MACH_INTBOARD		INTBOARD		1191
-gulfstream		MACH_GULFSTREAM		GULFSTREAM		1192
-labquest		MACH_LABQUEST		LABQUEST		1193
-vcmx313			MACH_VCMX313		VCMX313			1194
-urg200			MACH_URG200		URG200			1195
-cpux255lcdnet		MACH_CPUX255LCDNET	CPUX255LCDNET		1196
-netdcu9			MACH_NETDCU9		NETDCU9			1197
-netdcu10		MACH_NETDCU10		NETDCU10		1198
-dspg_dga		MACH_DSPG_DGA		DSPG_DGA		1199
-dspg_dvw		MACH_DSPG_DVW		DSPG_DVW		1200
-solos			MACH_SOLOS		SOLOS			1201
-at91sam9263ek		MACH_AT91SAM9263EK	AT91SAM9263EK		1202
-osstbox			MACH_OSSTBOX		OSSTBOX			1203
-kbat9261		MACH_KBAT9261		KBAT9261		1204
-ct1100			MACH_CT1100		CT1100			1205
-akcppxa			MACH_AKCPPXA		AKCPPXA			1206
-ochaya1020		MACH_OCHAYA1020		OCHAYA1020		1207
-hitrack			MACH_HITRACK		HITRACK			1208
-syme1			MACH_SYME1		SYME1			1209
-syhl1			MACH_SYHL1		SYHL1			1210
-empca400		MACH_EMPCA400		EMPCA400		1211
-em7210			MACH_EM7210		EM7210			1212
-htchermes		MACH_HTCHERMES		HTCHERMES		1213
-eti_c1			MACH_ETI_C1		ETI_C1			1214
-ac100			MACH_AC100		AC100			1216
-sneetch			MACH_SNEETCH		SNEETCH			1217
-studentmate		MACH_STUDENTMATE	STUDENTMATE		1218
-zir2410			MACH_ZIR2410		ZIR2410			1219
-zir2413			MACH_ZIR2413		ZIR2413			1220
-dlonip3			MACH_DLONIP3		DLONIP3			1221
-instream		MACH_INSTREAM		INSTREAM		1222
-ambarella		MACH_AMBARELLA		AMBARELLA		1223
-nevis			MACH_NEVIS		NEVIS			1224
-htc_trinity		MACH_HTC_TRINITY	HTC_TRINITY		1225
-ql202b			MACH_QL202B		QL202B			1226
-vpac270			MACH_VPAC270		VPAC270			1227
-rd129			MACH_RD129		RD129			1228
-htcwizard		MACH_HTCWIZARD		HTCWIZARD		1229
-treo680			MACH_TREO680		TREO680			1230
-tecon_tmezon		MACH_TECON_TMEZON	TECON_TMEZON		1231
-zylonite		MACH_ZYLONITE		ZYLONITE		1233
-gene1270		MACH_GENE1270		GENE1270		1234
-zir2412			MACH_ZIR2412		ZIR2412			1235
-mx31lite		MACH_MX31LITE		MX31LITE		1236
-t700wx			MACH_T700WX		T700WX			1237
-vf100			MACH_VF100		VF100			1238
-nsb2			MACH_NSB2		NSB2			1239
-nxhmi_bb		MACH_NXHMI_BB		NXHMI_BB		1240
-nxhmi_re		MACH_NXHMI_RE		NXHMI_RE		1241
-n4100pro		MACH_N4100PRO		N4100PRO		1242
-sam9260			MACH_SAM9260		SAM9260			1243
-omap_treo600		MACH_OMAP_TREO600	OMAP_TREO600		1244
-indy2410		MACH_INDY2410		INDY2410		1245
-nelt_a			MACH_NELT_A		NELT_A			1246
-n311			MACH_N311		N311			1248
-at91sam9260vgk		MACH_AT91SAM9260VGK	AT91SAM9260VGK		1249
-at91leppe		MACH_AT91LEPPE		AT91LEPPE		1250
-at91lepccn		MACH_AT91LEPCCN		AT91LEPCCN		1251
-apc7100			MACH_APC7100		APC7100			1252
-stargazer		MACH_STARGAZER		STARGAZER		1253
-sonata			MACH_SONATA		SONATA			1254
-schmoogie		MACH_SCHMOOGIE		SCHMOOGIE		1255
-aztool			MACH_AZTOOL		AZTOOL			1256
-mioa701			MACH_MIOA701		MIOA701			1257
-sxni9260		MACH_SXNI9260		SXNI9260		1258
-mxc27520evb		MACH_MXC27520EVB	MXC27520EVB		1259
-armadillo5x0		MACH_ARMADILLO5X0	ARMADILLO5X0		1260
-mb9260			MACH_MB9260		MB9260			1261
-mb9263			MACH_MB9263		MB9263			1262
-ipac9302		MACH_IPAC9302		IPAC9302		1263
-cc9p9360js		MACH_CC9P9360JS		CC9P9360JS		1264
-gallium			MACH_GALLIUM		GALLIUM			1265
-msc2410			MACH_MSC2410		MSC2410			1266
-ghi270			MACH_GHI270		GHI270			1267
-davinci_leonardo	MACH_DAVINCI_LEONARDO	DAVINCI_LEONARDO	1268
-oiab			MACH_OIAB		OIAB			1269
-smdk6400		MACH_SMDK6400		SMDK6400		1270
-nokia_n800		MACH_NOKIA_N800		NOKIA_N800		1271
-greenphone		MACH_GREENPHONE		GREENPHONE		1272
-compex42x		MACH_COMPEXWP18		COMPEXWP18		1273
-xmate			MACH_XMATE		XMATE			1274
-energizer		MACH_ENERGIZER		ENERGIZER		1275
-ime1			MACH_IME1		IME1			1276
-sweda_tms		MACH_SWEDATMS		SWEDATMS		1277
-ntnp435c		MACH_NTNP435C		NTNP435C		1278
-spectro2		MACH_SPECTRO2		SPECTRO2		1279
-h6039			MACH_H6039		H6039			1280
-ep80219			MACH_EP80219		EP80219			1281
-samoa_ii		MACH_SAMOA_II		SAMOA_II		1282
-cwmxl			MACH_CWMXL		CWMXL			1283
-as9200			MACH_AS9200		AS9200			1284
-sfx1149			MACH_SFX1149		SFX1149			1285
-navi010			MACH_NAVI010		NAVI010			1286
-multmdp			MACH_MULTMDP		MULTMDP			1287
-scb9520			MACH_SCB9520		SCB9520			1288
-htcathena		MACH_HTCATHENA		HTCATHENA		1289
-xp179			MACH_XP179		XP179			1290
-h4300			MACH_H4300		H4300			1291
-goramo_mlr		MACH_GORAMO_MLR		GORAMO_MLR		1292
-mxc30020evb		MACH_MXC30020EVB	MXC30020EVB		1293
-adsbitsyg5		MACH_ADSBITSYG5		ADSBITSYG5		1294
-adsportalplus		MACH_ADSPORTALPLUS	ADSPORTALPLUS		1295
-mmsp2plus		MACH_MMSP2PLUS		MMSP2PLUS		1296
-em_x270			MACH_EM_X270		EM_X270			1297
-tpp302			MACH_TPP302		TPP302			1298
-tpp104			MACH_TPM104		TPM104			1299
-tpm102			MACH_TPM102		TPM102			1300
-tpm109			MACH_TPM109		TPM109			1301
-fbxo1			MACH_FBXO1		FBXO1			1302
-hxd8			MACH_HXD8		HXD8			1303
-neo1973_gta02		MACH_NEO1973_GTA02	NEO1973_GTA02		1304
-emtest			MACH_EMTEST		EMTEST			1305
-ad6900			MACH_AD6900		AD6900			1306
-europa			MACH_EUROPA		EUROPA			1307
-metroconnect		MACH_METROCONNECT	METROCONNECT		1308
-ez_s2410		MACH_EZ_S2410		EZ_S2410		1309
-ez_s2440		MACH_EZ_S2440		EZ_S2440		1310
-ez_ep9312		MACH_EZ_EP9312		EZ_EP9312		1311
-ez_ep9315		MACH_EZ_EP9315		EZ_EP9315		1312
-ez_x7			MACH_EZ_X7		EZ_X7			1313
-godotdb			MACH_GODOTDB		GODOTDB			1314
-mistral			MACH_MISTRAL		MISTRAL			1315
-msm			MACH_MSM		MSM			1316
-ct5910			MACH_CT5910		CT5910			1317
-ct5912			MACH_CT5912		CT5912			1318
-argonst_mp		MACH_HYNET_INE		HYNET_INE		1319
-hynet_app		MACH_HYNET_APP		HYNET_APP		1320
-msm7200			MACH_MSM7200		MSM7200			1321
-msm7600			MACH_MSM7600		MSM7600			1322
-ceb255			MACH_CEB255		CEB255			1323
-ciel			MACH_CIEL		CIEL			1324
-slm5650			MACH_SLM5650		SLM5650			1325
-at91sam9rlek		MACH_AT91SAM9RLEK	AT91SAM9RLEK		1326
-comtech_router		MACH_COMTECH_ROUTER	COMTECH_ROUTER		1327
-sbc2410x		MACH_SBC2410X		SBC2410X		1328
-at4x0bd			MACH_AT4X0BD		AT4X0BD			1329
-cbifr			MACH_CBIFR		CBIFR			1330
-arcom_quantum		MACH_ARCOM_QUANTUM	ARCOM_QUANTUM		1331
-matrix520		MACH_MATRIX520		MATRIX520		1332
-matrix510		MACH_MATRIX510		MATRIX510		1333
-matrix500		MACH_MATRIX500		MATRIX500		1334
-m501			MACH_M501		M501			1335
-aaeon1270		MACH_AAEON1270		AAEON1270		1336
-matrix500ev		MACH_MATRIX500EV	MATRIX500EV		1337
-pac500			MACH_PAC500		PAC500			1338
-pnx8181			MACH_PNX8181		PNX8181			1339
-colibri320		MACH_COLIBRI320		COLIBRI320		1340
-aztoolbb		MACH_AZTOOLBB		AZTOOLBB		1341
-aztoolg2		MACH_AZTOOLG2		AZTOOLG2		1342
-dvlhost			MACH_DVLHOST		DVLHOST			1343
-zir9200			MACH_ZIR9200		ZIR9200			1344
-zir9260			MACH_ZIR9260		ZIR9260			1345
-cocopah			MACH_COCOPAH		COCOPAH			1346
-nds			MACH_NDS		NDS			1347
-rosencrantz		MACH_ROSENCRANTZ	ROSENCRANTZ		1348
-fttx_odsc		MACH_FTTX_ODSC		FTTX_ODSC		1349
-classe_r6904		MACH_CLASSE_R6904	CLASSE_R6904		1350
-cam60			MACH_CAM60		CAM60			1351
-mxc30031ads		MACH_MXC30031ADS	MXC30031ADS		1352
-datacall		MACH_DATACALL		DATACALL		1353
-at91eb01		MACH_AT91EB01		AT91EB01		1354
-rty			MACH_RTY		RTY			1355
-dwl2100			MACH_DWL2100		DWL2100			1356
-vinsi			MACH_VINSI		VINSI			1357
-db88f5281		MACH_DB88F5281		DB88F5281		1358
-csb726			MACH_CSB726		CSB726			1359
-tik27			MACH_TIK27		TIK27			1360
-mx_uc7420		MACH_MX_UC7420		MX_UC7420		1361
-rirm3			MACH_RIRM3		RIRM3			1362
-pelco_odyssey		MACH_PELCO_ODYSSEY	PELCO_ODYSSEY		1363
-adx_abox		MACH_ADX_ABOX		ADX_ABOX		1365
-adx_tpid		MACH_ADX_TPID		ADX_TPID		1366
-minicheck		MACH_MINICHECK		MINICHECK		1367
-idam			MACH_IDAM		IDAM			1368
-mario_mx		MACH_MARIO_MX		MARIO_MX		1369
-vi1888			MACH_VI1888		VI1888			1370
-zr4230			MACH_ZR4230		ZR4230			1371
-t1_ix_blue		MACH_T1_IX_BLUE		T1_IX_BLUE		1372
-syhq2			MACH_SYHQ2		SYHQ2			1373
-computime_r3		MACH_COMPUTIME_R3	COMPUTIME_R3		1374
-oratis			MACH_ORATIS		ORATIS			1375
-mikko			MACH_MIKKO		MIKKO			1376
-holon			MACH_HOLON		HOLON			1377
-olip8			MACH_OLIP8		OLIP8			1378
-ghi270hg		MACH_GHI270HG		GHI270HG		1379
-davinci_dm6467_evm	MACH_DAVINCI_DM6467_EVM	DAVINCI_DM6467_EVM	1380
-davinci_dm355_evm	MACH_DAVINCI_DM355_EVM	DAVINCI_DM355_EVM	1381
-blackriver		MACH_BLACKRIVER		BLACKRIVER		1383
-sandgate_wp		MACH_SANDGATEWP		SANDGATEWP		1384
-cdotbwsg		MACH_CDOTBWSG		CDOTBWSG		1385
-quark963		MACH_QUARK963		QUARK963		1386
-csb735			MACH_CSB735		CSB735			1387
-littleton		MACH_LITTLETON		LITTLETON		1388
-mio_p550		MACH_MIO_P550		MIO_P550		1389
-motion2440		MACH_MOTION2440		MOTION2440		1390
-imm500			MACH_IMM500		IMM500			1391
-homematic		MACH_HOMEMATIC		HOMEMATIC		1392
-ermine			MACH_ERMINE		ERMINE			1393
-kb9202b			MACH_KB9202B		KB9202B			1394
-hs1xx			MACH_HS1XX		HS1XX			1395
-studentmate2440		MACH_STUDENTMATE2440	STUDENTMATE2440		1396
-arvoo_l1_z1		MACH_ARVOO_L1_Z1	ARVOO_L1_Z1		1397
-dep2410k		MACH_DEP2410K		DEP2410K		1398
-xxsvideo		MACH_XXSVIDEO		XXSVIDEO		1399
-im4004			MACH_IM4004		IM4004			1400
-ochaya1050		MACH_OCHAYA1050		OCHAYA1050		1401
-lep9261			MACH_LEP9261		LEP9261			1402
-svenmeb			MACH_SVENMEB		SVENMEB			1403
-fortunet2ne		MACH_FORTUNET2NE	FORTUNET2NE		1404
-nxhx			MACH_NXHX		NXHX			1406
-realview_pb11mp		MACH_REALVIEW_PB11MP	REALVIEW_PB11MP		1407
-ids500			MACH_IDS500		IDS500			1408
-ors_n725		MACH_ORS_N725		ORS_N725		1409
-hsdarm			MACH_HSDARM		HSDARM			1410
-sha_pon003		MACH_SHA_PON003		SHA_PON003		1411
-sha_pon004		MACH_SHA_PON004		SHA_PON004		1412
-sha_pon007		MACH_SHA_PON007		SHA_PON007		1413
-sha_pon011		MACH_SHA_PON011		SHA_PON011		1414
-h6042			MACH_H6042		H6042			1415
-h6043			MACH_H6043		H6043			1416
-looxc550		MACH_LOOXC550		LOOXC550		1417
-cnty_titan		MACH_CNTY_TITAN		CNTY_TITAN		1418
-app3xx			MACH_APP3XX		APP3XX			1419
-sideoatsgrama		MACH_SIDEOATSGRAMA	SIDEOATSGRAMA		1420
-treo700p		MACH_TREO700P		TREO700P		1421
-treo700w		MACH_TREO700W		TREO700W		1422
-treo750			MACH_TREO750		TREO750			1423
-treo755p		MACH_TREO755P		TREO755P		1424
-ezreganut9200		MACH_EZREGANUT9200	EZREGANUT9200		1425
-sarge			MACH_SARGE		SARGE			1426
-a696			MACH_A696		A696			1427
-turtle1916		MACH_TURTLE		TURTLE			1428
-mx27_3ds		MACH_MX27_3DS		MX27_3DS		1430
-bishop			MACH_BISHOP		BISHOP			1431
-pxx			MACH_PXX		PXX			1432
-redwood			MACH_REDWOOD		REDWOOD			1433
-omap_2430dlp		MACH_OMAP_2430DLP	OMAP_2430DLP		1436
-omap_2430osk		MACH_OMAP_2430OSK	OMAP_2430OSK		1437
-sardine			MACH_SARDINE		SARDINE			1438
-halibut			MACH_HALIBUT		HALIBUT			1439
-trout			MACH_TROUT		TROUT			1440
-goldfish		MACH_GOLDFISH		GOLDFISH		1441
-gesbc2440		MACH_GESBC2440		GESBC2440		1442
-nomad			MACH_NOMAD		NOMAD			1443
-rosalind		MACH_ROSALIND		ROSALIND		1444
-cc9p9215		MACH_CC9P9215		CC9P9215		1445
-cc9p9210		MACH_CC9P9210		CC9P9210		1446
-cc9p9215js		MACH_CC9P9215JS		CC9P9215JS		1447
-cc9p9210js		MACH_CC9P9210JS		CC9P9210JS		1448
-nasffe			MACH_NASFFE		NASFFE			1449
-tn2x0bd			MACH_TN2X0BD		TN2X0BD			1450
-gwmpxa			MACH_GWMPXA		GWMPXA			1451
-exyplus			MACH_EXYPLUS		EXYPLUS			1452
-jadoo21			MACH_JADOO21		JADOO21			1453
-looxn560		MACH_LOOXN560		LOOXN560		1454
-bonsai			MACH_BONSAI		BONSAI			1455
-adsmilgato		MACH_ADSMILGATO		ADSMILGATO		1456
-gba			MACH_GBA		GBA			1457
-h6044			MACH_H6044		H6044			1458
-app			MACH_APP		APP			1459
-tct_hammer		MACH_TCT_HAMMER		TCT_HAMMER		1460
-herald			MACH_HERALD		HERALD			1461
-artemis			MACH_ARTEMIS		ARTEMIS			1462
-htctitan		MACH_HTCTITAN		HTCTITAN		1463
-qranium			MACH_QRANIUM		QRANIUM			1464
-adx_wsc2		MACH_ADX_WSC2		ADX_WSC2		1465
-adx_medcom		MACH_ADX_MEDCOM		ADX_MEDCOM		1466
-bboard			MACH_BBOARD		BBOARD			1467
-cambria			MACH_CAMBRIA		CAMBRIA			1468
-mt7xxx			MACH_MT7XXX		MT7XXX			1469
-matrix512		MACH_MATRIX512		MATRIX512		1470
-matrix522		MACH_MATRIX522		MATRIX522		1471
-ipac5010		MACH_IPAC5010		IPAC5010		1472
-sakura			MACH_SAKURA		SAKURA			1473
-grocx			MACH_GROCX		GROCX			1474
-pm9263			MACH_PM9263		PM9263			1475
-sim_one			MACH_SIM_ONE		SIM_ONE			1476
-acq132			MACH_ACQ132		ACQ132			1477
-datr			MACH_DATR		DATR			1478
-actux1			MACH_ACTUX1		ACTUX1			1479
-actux2			MACH_ACTUX2		ACTUX2			1480
-actux3			MACH_ACTUX3		ACTUX3			1481
-flexit			MACH_FLEXIT		FLEXIT			1482
-bh2x0bd			MACH_BH2X0BD		BH2X0BD			1483
-atb2002			MACH_ATB2002		ATB2002			1484
-xenon			MACH_XENON		XENON			1485
-fm607			MACH_FM607		FM607			1486
-matrix514		MACH_MATRIX514		MATRIX514		1487
-matrix524		MACH_MATRIX524		MATRIX524		1488
-inpod			MACH_INPOD		INPOD			1489
-jive			MACH_JIVE		JIVE			1490
-tll_mx21		MACH_TLL_MX21		TLL_MX21		1491
-sbc2800			MACH_SBC2800		SBC2800			1492
-cc7ucamry		MACH_CC7UCAMRY		CC7UCAMRY		1493
-ubisys_p9_sc15		MACH_UBISYS_P9_SC15	UBISYS_P9_SC15		1494
-ubisys_p9_ssc2d10	MACH_UBISYS_P9_SSC2D10	UBISYS_P9_SSC2D10	1495
-ubisys_p9_rcu3		MACH_UBISYS_P9_RCU3	UBISYS_P9_RCU3		1496
-aml_m8000		MACH_AML_M8000		AML_M8000		1497
-snapper_270		MACH_SNAPPER_270	SNAPPER_270		1498
-omap_bbx		MACH_OMAP_BBX		OMAP_BBX		1499
-ucn2410			MACH_UCN2410		UCN2410			1500
-sam9_l9260		MACH_SAM9_L9260		SAM9_L9260		1501
-eti_c2			MACH_ETI_C2		ETI_C2			1502
-avalanche		MACH_AVALANCHE		AVALANCHE		1503
-realview_pb1176		MACH_REALVIEW_PB1176	REALVIEW_PB1176		1504
-dp1500			MACH_DP1500		DP1500			1505
-apple_iphone		MACH_APPLE_IPHONE	APPLE_IPHONE		1506
-yl9200			MACH_YL9200		YL9200			1507
-rd88f5182		MACH_RD88F5182		RD88F5182		1508
-kurobox_pro		MACH_KUROBOX_PRO	KUROBOX_PRO		1509
-se_poet			MACH_SE_POET		SE_POET			1510
-mx31_3ds		MACH_MX31_3DS		MX31_3DS		1511
-r270			MACH_R270		R270			1512
-armour21		MACH_ARMOUR21		ARMOUR21		1513
-dt2			MACH_DT2		DT2			1514
-vt4			MACH_VT4		VT4			1515
-tyco320			MACH_TYCO320		TYCO320			1516
-adma			MACH_ADMA		ADMA			1517
-wp188			MACH_WP188		WP188			1518
-corsica			MACH_CORSICA		CORSICA			1519
-bigeye			MACH_BIGEYE		BIGEYE			1520
-tll5000			MACH_TLL5000		TLL5000			1522
-bebot			MACH_BEBOT		BEBOT			1523
-qong			MACH_QONG		QONG			1524
-tcompact		MACH_TCOMPACT		TCOMPACT		1525
-puma5			MACH_PUMA5		PUMA5			1526
-elara			MACH_ELARA		ELARA			1527
-ellington		MACH_ELLINGTON		ELLINGTON		1528
-xda_atom		MACH_XDA_ATOM		XDA_ATOM		1529
-energizer2		MACH_ENERGIZER2		ENERGIZER2		1530
-odin			MACH_ODIN		ODIN			1531
-actux4			MACH_ACTUX4		ACTUX4			1532
-esl_omap		MACH_ESL_OMAP		ESL_OMAP		1533
-omap2evm		MACH_OMAP2EVM		OMAP2EVM		1534
-omap3evm		MACH_OMAP3EVM		OMAP3EVM		1535
-adx_pcu57		MACH_ADX_PCU57		ADX_PCU57		1536
-monaco			MACH_MONACO		MONACO			1537
-levante			MACH_LEVANTE		LEVANTE			1538
-tmxipx425		MACH_TMXIPX425		TMXIPX425		1539
-leep			MACH_LEEP		LEEP			1540
-raad			MACH_RAAD		RAAD			1541
-dns323			MACH_DNS323		DNS323			1542
-ap1000			MACH_AP1000		AP1000			1543
-a9sam6432		MACH_A9SAM6432		A9SAM6432		1544
-shiny			MACH_SHINY		SHINY			1545
-omap3_beagle		MACH_OMAP3_BEAGLE	OMAP3_BEAGLE		1546
-csr_bdb2		MACH_CSR_BDB2		CSR_BDB2		1547
-nokia_n810		MACH_NOKIA_N810		NOKIA_N810		1548
-c270			MACH_C270		C270			1549
-sentry			MACH_SENTRY		SENTRY			1550
-pcm038			MACH_PCM038		PCM038			1551
-anc300			MACH_ANC300		ANC300			1552
-htckaiser		MACH_HTCKAISER		HTCKAISER		1553
-sbat100			MACH_SBAT100		SBAT100			1554
-modunorm		MACH_MODUNORM		MODUNORM		1555
-pelos_twarm		MACH_PELOS_TWARM	PELOS_TWARM		1556
-flank			MACH_FLANK		FLANK			1557
-sirloin			MACH_SIRLOIN		SIRLOIN			1558
-brisket			MACH_BRISKET		BRISKET			1559
-chuck			MACH_CHUCK		CHUCK			1560
-otter			MACH_OTTER		OTTER			1561
-davinci_ldk		MACH_DAVINCI_LDK	DAVINCI_LDK		1562
-phreedom		MACH_PHREEDOM		PHREEDOM		1563
-sg310			MACH_SG310		SG310			1564
-ts209			MACH_TS209		TS209			1565
-at91cap9adk		MACH_AT91CAP9ADK	AT91CAP9ADK		1566
-tion9315		MACH_TION9315		TION9315		1567
-mast			MACH_MAST		MAST			1568
-pfw			MACH_PFW		PFW			1569
-yl_p2440		MACH_YL_P2440		YL_P2440		1570
-zsbc32			MACH_ZSBC32		ZSBC32			1571
-omap_pace2		MACH_OMAP_PACE2		OMAP_PACE2		1572
-imx_pace2		MACH_IMX_PACE2		IMX_PACE2		1573
-mx31moboard		MACH_MX31MOBOARD	MX31MOBOARD		1574
-mx37_3ds		MACH_MX37_3DS		MX37_3DS		1575
-rcc			MACH_RCC		RCC			1576
-dmp			MACH_ARM9		ARM9			1577
-vision_ep9307		MACH_VISION_EP9307	VISION_EP9307		1578
-scly1000		MACH_SCLY1000		SCLY1000		1579
-fontel_ep		MACH_FONTEL_EP		FONTEL_EP		1580
-voiceblue3g		MACH_VOICEBLUE3G	VOICEBLUE3G		1581
-tt9200			MACH_TT9200		TT9200			1582
-digi2410		MACH_DIGI2410		DIGI2410		1583
-terastation_pro2	MACH_TERASTATION_PRO2	TERASTATION_PRO2	1584
-linkstation_pro		MACH_LINKSTATION_PRO	LINKSTATION_PRO		1585
-motorola_a780		MACH_MOTOROLA_A780	MOTOROLA_A780		1587
-motorola_e6		MACH_MOTOROLA_E6	MOTOROLA_E6		1588
-motorola_e2		MACH_MOTOROLA_E2	MOTOROLA_E2		1589
-motorola_e680		MACH_MOTOROLA_E680	MOTOROLA_E680		1590
-ur2410			MACH_UR2410		UR2410			1591
-tas9261			MACH_TAS9261		TAS9261			1592
-davinci_hermes_hd	MACH_HERMES_HD		HERMES_HD		1593
-davinci_perseo_hd	MACH_PERSEO_HD		PERSEO_HD		1594
-stargazer2		MACH_STARGAZER2		STARGAZER2		1595
-e350			MACH_E350		E350			1596
-wpcm450			MACH_WPCM450		WPCM450			1597
-cartesio		MACH_CARTESIO		CARTESIO		1598
-toybox			MACH_TOYBOX		TOYBOX			1599
-tx27			MACH_TX27		TX27			1600
-ts409			MACH_TS409		TS409			1601
-p300			MACH_P300		P300			1602
-xdacomet		MACH_XDACOMET		XDACOMET		1603
-dexflex2		MACH_DEXFLEX2		DEXFLEX2		1604
-ow			MACH_OW			OW			1605
-armebs3			MACH_ARMEBS3		ARMEBS3			1606
-u3			MACH_U3			U3			1607
-smdk2450		MACH_SMDK2450		SMDK2450		1608
-rsi_ews			MACH_RSI_EWS		RSI_EWS			1609
-tnb			MACH_TNB		TNB			1610
-toepath			MACH_TOEPATH		TOEPATH			1611
-kb9263			MACH_KB9263		KB9263			1612
-mt7108			MACH_MT7108		MT7108			1613
-smtr2440		MACH_SMTR2440		SMTR2440		1614
-manao			MACH_MANAO		MANAO			1615
-cm_x300			MACH_CM_X300		CM_X300			1616
-gulfstream_kp		MACH_GULFSTREAM_KP	GULFSTREAM_KP		1617
-lanreadyfn522		MACH_LANREADYFN522	LANREADYFN522		1618
-arma37			MACH_ARMA37		ARMA37			1619
-mendel			MACH_MENDEL		MENDEL			1620
-pelco_iliad		MACH_PELCO_ILIAD	PELCO_ILIAD		1621
-unit2p			MACH_UNIT2P		UNIT2P			1622
-inc20otter		MACH_INC20OTTER		INC20OTTER		1623
-at91sam9g20ek		MACH_AT91SAM9G20EK	AT91SAM9G20EK		1624
-sc_ge2			MACH_STORCENTER		STORCENTER		1625
-smdk6410		MACH_SMDK6410		SMDK6410		1626
-u300			MACH_U300		U300			1627
-u500			MACH_U500		U500			1628
-ds9260			MACH_DS9260		DS9260			1629
-riverrock		MACH_RIVERROCK		RIVERROCK		1630
-scibath			MACH_SCIBATH		SCIBATH			1631
-at91sam7se		MACH_AT91SAM7SE512EK	AT91SAM7SE512EK		1632
-wrt350n_v2		MACH_WRT350N_V2		WRT350N_V2		1633
-multimedia		MACH_MULTIMEDIA		MULTIMEDIA		1634
-marvin			MACH_MARVIN		MARVIN			1635
-x500			MACH_X500		X500			1636
-awlug4lcu		MACH_AWLUG4LCU		AWLUG4LCU		1637
-palermoc		MACH_PALERMOC		PALERMOC		1638
-omap_ldp		MACH_OMAP_LDP		OMAP_LDP		1639
-ip500			MACH_IP500		IP500			1640
-ase2			MACH_ASE2		ASE2			1642
-mx35evb			MACH_MX35EVB		MX35EVB			1643
-aml_m8050		MACH_AML_M8050		AML_M8050		1644
-mx35_3ds		MACH_MX35_3DS		MX35_3DS		1645
-mars			MACH_MARS		MARS			1646
-neuros_osd2		MACH_NEUROS_OSD2	NEUROS_OSD2		1647
-badger			MACH_BADGER		BADGER			1648
-trizeps4wl		MACH_TRIZEPS4WL		TRIZEPS4WL		1649
-trizeps5		MACH_TRIZEPS5		TRIZEPS5		1650
-marlin			MACH_MARLIN		MARLIN			1651
-ts78xx			MACH_TS78XX		TS78XX			1652
-hpipaq214		MACH_HPIPAQ214		HPIPAQ214		1653
-at572d940dcm		MACH_AT572D940DCM	AT572D940DCM		1654
-ne1board		MACH_NE1BOARD		NE1BOARD		1655
-zante			MACH_ZANTE		ZANTE			1656
-sffsdr			MACH_SFFSDR		SFFSDR			1657
-tw2662			MACH_TW2662		TW2662			1658
-vf10xx			MACH_VF10XX		VF10XX			1659
-zoran43xx		MACH_ZORAN43XX		ZORAN43XX		1660
-sonix926		MACH_SONIX926		SONIX926		1661
-celestialsemi		MACH_CELESTIALSEMI	CELESTIALSEMI		1662
-cc9m2443js		MACH_CC9M2443JS		CC9M2443JS		1663
-tw5334			MACH_TW5334		TW5334			1664
-omap_htcartemis		MACH_HTCARTEMIS		HTCARTEMIS		1665
-nal_hlite		MACH_NAL_HLITE		NAL_HLITE		1666
-htcvogue		MACH_HTCVOGUE		HTCVOGUE		1667
-smartweb		MACH_SMARTWEB		SMARTWEB		1668
-mv86xx			MACH_MV86XX		MV86XX			1669
-mv87xx			MACH_MV87XX		MV87XX			1670
-songyoungho		MACH_SONGYOUNGHO	SONGYOUNGHO		1671
-younghotema		MACH_YOUNGHOTEMA	YOUNGHOTEMA		1672
-pcm037			MACH_PCM037		PCM037			1673
-mmvp			MACH_MMVP		MMVP			1674
-mmap			MACH_MMAP		MMAP			1675
-ptid2410		MACH_PTID2410		PTID2410		1676
-james_926		MACH_JAMES_926		JAMES_926		1677
-fm6000			MACH_FM6000		FM6000			1678
-db88f6281_bp		MACH_DB88F6281_BP	DB88F6281_BP		1680
-rd88f6192_nas		MACH_RD88F6192_NAS	RD88F6192_NAS		1681
-rd88f6281		MACH_RD88F6281		RD88F6281		1682
-db78x00_bp		MACH_DB78X00_BP		DB78X00_BP		1683
-smdk2416		MACH_SMDK2416		SMDK2416		1685
-oce_spider_si		MACH_OCE_SPIDER_SI	OCE_SPIDER_SI		1686
-oce_spider_sk		MACH_OCE_SPIDER_SK	OCE_SPIDER_SK		1687
-rovern6			MACH_ROVERN6		ROVERN6			1688
-pelco_evolution		MACH_PELCO_EVOLUTION	PELCO_EVOLUTION		1689
-wbd111			MACH_WBD111		WBD111			1690
-elaracpe		MACH_ELARACPE		ELARACPE		1691
-mabv3			MACH_MABV3		MABV3			1692
-mv2120			MACH_MV2120		MV2120			1693
-csb737			MACH_CSB737		CSB737			1695
-mx51_3ds		MACH_MX51_3DS		MX51_3DS		1696
-g900			MACH_G900		G900			1697
-apf27			MACH_APF27		APF27			1698
-ggus2000		MACH_GGUS2000		GGUS2000		1699
-omap_2430_mimic		MACH_OMAP_2430_MIMIC	OMAP_2430_MIMIC		1700
-imx27lite		MACH_IMX27LITE		IMX27LITE		1701
-almex			MACH_ALMEX		ALMEX			1702
-control			MACH_CONTROL		CONTROL			1703
-mba2410			MACH_MBA2410		MBA2410			1704
-volcano			MACH_VOLCANO		VOLCANO			1705
-zenith			MACH_ZENITH		ZENITH			1706
-muchip			MACH_MUCHIP		MUCHIP			1707
-magellan		MACH_MAGELLAN		MAGELLAN		1708
-usb_a9260		MACH_USB_A9260		USB_A9260		1709
-usb_a9263		MACH_USB_A9263		USB_A9263		1710
-qil_a9260		MACH_QIL_A9260		QIL_A9260		1711
-cme9210			MACH_CME9210		CME9210			1712
-hczh4			MACH_HCZH4		HCZH4			1713
-spearbasic		MACH_SPEARBASIC		SPEARBASIC		1714
-dep2440			MACH_DEP2440		DEP2440			1715
-hdl_gxr			MACH_HDL_GXR		HDL_GXR			1716
-hdl_gt			MACH_HDL_GT		HDL_GT			1717
-hdl_4g			MACH_HDL_4G		HDL_4G			1718
-s3c6000			MACH_S3C6000		S3C6000			1719
-mmsp2_mdk		MACH_MMSP2_MDK		MMSP2_MDK		1720
-mpx220			MACH_MPX220		MPX220			1721
-kzm_arm11_01		MACH_KZM_ARM11_01	KZM_ARM11_01		1722
-htc_polaris		MACH_HTC_POLARIS	HTC_POLARIS		1723
-htc_kaiser		MACH_HTC_KAISER		HTC_KAISER		1724
-lg_ks20			MACH_LG_KS20		LG_KS20			1725
-hhgps			MACH_HHGPS		HHGPS			1726
-nokia_n810_wimax	MACH_NOKIA_N810_WIMAX	NOKIA_N810_WIMAX	1727
-insight			MACH_INSIGHT		INSIGHT			1728
-sapphire		MACH_SAPPHIRE		SAPPHIRE		1729
-csb637xo		MACH_CSB637XO		CSB637XO		1730
-evisiong		MACH_EVISIONG		EVISIONG		1731
-stmp37xx		MACH_STMP37XX		STMP37XX		1732
-stmp378x		MACH_STMP378X		STMP378X		1733
-tnt			MACH_TNT		TNT			1734
-tbxt			MACH_TBXT		TBXT			1735
-playmate		MACH_PLAYMATE		PLAYMATE		1736
-pns10			MACH_PNS10		PNS10			1737
-eznavi			MACH_EZNAVI		EZNAVI			1738
-ps4000			MACH_PS4000		PS4000			1739
-ezx_a780		MACH_EZX_A780		EZX_A780		1740
-ezx_e680		MACH_EZX_E680		EZX_E680		1741
-ezx_a1200		MACH_EZX_A1200		EZX_A1200		1742
-ezx_e6			MACH_EZX_E6		EZX_E6			1743
-ezx_e2			MACH_EZX_E2		EZX_E2			1744
-ezx_a910		MACH_EZX_A910		EZX_A910		1745
-cwmx31			MACH_CWMX31		CWMX31			1746
-sl2312			MACH_SL2312		SL2312			1747
-blenny			MACH_BLENNY		BLENNY			1748
-ds107			MACH_DS107		DS107			1749
-dsx07			MACH_DSX07		DSX07			1750
-picocom1		MACH_PICOCOM1		PICOCOM1		1751
-lynx_wolverine		MACH_LYNX_WOLVERINE	LYNX_WOLVERINE		1752
-ubisys_p9_sc19		MACH_UBISYS_P9_SC19	UBISYS_P9_SC19		1753
-kratos_low		MACH_KRATOS_LOW		KRATOS_LOW		1754
-m700			MACH_M700		M700			1755
-edmini_v2		MACH_EDMINI_V2		EDMINI_V2		1756
-zipit2			MACH_ZIPIT2		ZIPIT2			1757
-hslfemtocell		MACH_HSLFEMTOCELL	HSLFEMTOCELL		1758
-daintree_at91		MACH_DAINTREE_AT91	DAINTREE_AT91		1759
-sg560usb		MACH_SG560USB		SG560USB		1760
-omap3_pandora		MACH_OMAP3_PANDORA	OMAP3_PANDORA		1761
-usr8200			MACH_USR8200		USR8200			1762
-s1s65k			MACH_S1S65K		S1S65K			1763
-s2s65a			MACH_S2S65A		S2S65A			1764
-icore			MACH_ICORE		ICORE			1765
-mss2			MACH_MSS2		MSS2			1766
-belmont			MACH_BELMONT		BELMONT			1767
-asusp525		MACH_ASUSP525		ASUSP525		1768
-lb88rc8480		MACH_LB88RC8480		LB88RC8480		1769
-hipxa			MACH_HIPXA		HIPXA			1770
-mx25_3ds		MACH_MX25_3DS		MX25_3DS		1771
-m800			MACH_M800		M800			1772
-omap3530_lv_som		MACH_OMAP3530_LV_SOM	OMAP3530_LV_SOM		1773
-prima_evb		MACH_PRIMA_EVB		PRIMA_EVB		1774
-mx31bt1			MACH_MX31BT1		MX31BT1			1775
-atlas4_evb		MACH_ATLAS4_EVB		ATLAS4_EVB		1776
-mx31cicada		MACH_MX31CICADA		MX31CICADA		1777
-mi424wr			MACH_MI424WR		MI424WR			1778
-axs_ultrax		MACH_AXS_ULTRAX		AXS_ULTRAX		1779
-at572d940deb		MACH_AT572D940DEB	AT572D940DEB		1780
-davinci_da830_evm	MACH_DAVINCI_DA830_EVM	DAVINCI_DA830_EVM	1781
-ep9302			MACH_EP9302		EP9302			1782
-at572d940hfek		MACH_AT572D940HFEB	AT572D940HFEB		1783
-cybook3			MACH_CYBOOK3		CYBOOK3			1784
-wdg002			MACH_WDG002		WDG002			1785
-sg560adsl		MACH_SG560ADSL		SG560ADSL		1786
-nextio_n2800_ica	MACH_NEXTIO_N2800_ICA	NEXTIO_N2800_ICA	1787
-dove_db			MACH_DOVE_DB		DOVE_DB			1788
-vandihud		MACH_VANDIHUD		VANDIHUD		1790
-magx_e8			MACH_MAGX_E8		MAGX_E8			1791
-magx_z6			MACH_MAGX_Z6		MAGX_Z6			1792
-magx_v8			MACH_MAGX_V8		MAGX_V8			1793
-magx_u9			MACH_MAGX_U9		MAGX_U9			1794
-toughcf08		MACH_TOUGHCF08		TOUGHCF08		1795
-zw4400			MACH_ZW4400		ZW4400			1796
-marat91			MACH_MARAT91		MARAT91			1797
-overo			MACH_OVERO		OVERO			1798
-at2440evb		MACH_AT2440EVB		AT2440EVB		1799
-neocore926		MACH_NEOCORE926		NEOCORE926		1800
-wnr854t			MACH_WNR854T		WNR854T			1801
-imx27			MACH_IMX27		IMX27			1802
-moose_db		MACH_MOOSE_DB		MOOSE_DB		1803
-fab4			MACH_FAB4		FAB4			1804
-htcdiamond		MACH_HTCDIAMOND		HTCDIAMOND		1805
-fiona			MACH_FIONA		FIONA			1806
-mxc30030_x		MACH_MXC30030_X		MXC30030_X		1807
-bmp1000			MACH_BMP1000		BMP1000			1808
-logi9200		MACH_LOGI9200		LOGI9200		1809
-tqma31			MACH_TQMA31		TQMA31			1810
-ccw9p9215js		MACH_CCW9P9215JS	CCW9P9215JS		1811
-rd88f5181l_ge		MACH_RD88F5181L_GE	RD88F5181L_GE		1812
-sifmain			MACH_SIFMAIN		SIFMAIN			1813
-sam9_l9261		MACH_SAM9_L9261		SAM9_L9261		1814
-cc9m2443		MACH_CC9M2443		CC9M2443		1815
-xaria300		MACH_XARIA300		XARIA300		1816
-it9200			MACH_IT9200		IT9200			1817
-rd88f5181l_fxo		MACH_RD88F5181L_FXO	RD88F5181L_FXO		1818
-kriss_sensor		MACH_KRISS_SENSOR	KRISS_SENSOR		1819
-pilz_pmi5		MACH_PILZ_PMI5		PILZ_PMI5		1820
-jade			MACH_JADE		JADE			1821
-ks8695_softplc		MACH_KS8695_SOFTPLC	KS8695_SOFTPLC		1822
-gprisc3			MACH_GPRISC3		GPRISC3			1823
-stamp9g20		MACH_STAMP9G20		STAMP9G20		1824
-smdk6430		MACH_SMDK6430		SMDK6430		1825
-smdkc100		MACH_SMDKC100		SMDKC100		1826
-tavorevb		MACH_TAVOREVB		TAVOREVB		1827
-saar			MACH_SAAR		SAAR			1828
-deister_eyecam		MACH_DEISTER_EYECAM	DEISTER_EYECAM		1829
-at91sam9m10g45ek	MACH_AT91SAM9M10G45EK	AT91SAM9M10G45EK	1830
-linkstation_produo	MACH_LINKSTATION_PRODUO	LINKSTATION_PRODUO	1831
-hit_b0			MACH_HIT_B0		HIT_B0			1832
-adx_rmu			MACH_ADX_RMU		ADX_RMU			1833
-xg_cpe_main		MACH_XG_CPE_MAIN	XG_CPE_MAIN		1834
-edb9407a		MACH_EDB9407A		EDB9407A		1835
-dtb9608			MACH_DTB9608		DTB9608			1836
-em104v1			MACH_EM104V1		EM104V1			1837
-demo			MACH_DEMO		DEMO			1838
-logi9260		MACH_LOGI9260		LOGI9260		1839
-mx31_exm32		MACH_MX31_EXM32		MX31_EXM32		1840
-usb_a9g20		MACH_USB_A9G20		USB_A9G20		1841
-picproje2008		MACH_PICPROJE2008	PICPROJE2008		1842
-cs_e9315		MACH_CS_E9315		CS_E9315		1843
-qil_a9g20		MACH_QIL_A9G20		QIL_A9G20		1844
-sha_pon020		MACH_SHA_PON020		SHA_PON020		1845
-nad			MACH_NAD		NAD			1846
-sbc35_a9260		MACH_SBC35_A9260	SBC35_A9260		1847
-sbc35_a9g20		MACH_SBC35_A9G20	SBC35_A9G20		1848
-davinci_beginning	MACH_DAVINCI_BEGINNING	DAVINCI_BEGINNING	1849
-uwc			MACH_UWC		UWC			1850
-mxlads			MACH_MXLADS		MXLADS			1851
-htcnike			MACH_HTCNIKE		HTCNIKE			1852
-deister_pxa270		MACH_DEISTER_PXA270	DEISTER_PXA270		1853
-cme9210js		MACH_CME9210JS		CME9210JS		1854
-cc9p9360		MACH_CC9P9360		CC9P9360		1855
-mocha			MACH_MOCHA		MOCHA			1856
-wapd170ag		MACH_WAPD170AG		WAPD170AG		1857
-linkstation_mini	MACH_LINKSTATION_MINI	LINKSTATION_MINI	1858
-afeb9260		MACH_AFEB9260		AFEB9260		1859
-w90x900			MACH_W90X900		W90X900			1860
-w90x700			MACH_W90X700		W90X700			1861
-kt300ip			MACH_KT300IP		KT300IP			1862
-kt300ip_g20		MACH_KT300IP_G20	KT300IP_G20		1863
-srcm			MACH_SRCM		SRCM			1864
-wlnx_9260		MACH_WLNX_9260		WLNX_9260		1865
-openmoko_gta03		MACH_OPENMOKO_GTA03	OPENMOKO_GTA03		1866
-osprey2			MACH_OSPREY2		OSPREY2			1867
-kbio9260		MACH_KBIO9260		KBIO9260		1868
-ginza			MACH_GINZA		GINZA			1869
-a636n			MACH_A636N		A636N			1870
-imx27ipcam		MACH_IMX27IPCAM		IMX27IPCAM		1871
-nemoc			MACH_NEMOC		NEMOC			1872
-geneva			MACH_GENEVA		GENEVA			1873
-htcpharos		MACH_HTCPHAROS		HTCPHAROS		1874
-neonc			MACH_NEONC		NEONC			1875
-nas7100			MACH_NAS7100		NAS7100			1876
-teuphone		MACH_TEUPHONE		TEUPHONE		1877
-annax_eth2		MACH_ANNAX_ETH2		ANNAX_ETH2		1878
-csb733			MACH_CSB733		CSB733			1879
-bk3			MACH_BK3		BK3			1880
-omap_em32		MACH_OMAP_EM32		OMAP_EM32		1881
-et9261cp		MACH_ET9261CP		ET9261CP		1882
-jasperc			MACH_JASPERC		JASPERC			1883
-issi_arm9		MACH_ISSI_ARM9		ISSI_ARM9		1884
-ued			MACH_UED		UED			1885
-esiblade		MACH_ESIBLADE		ESIBLADE		1886
-eye02			MACH_EYE02		EYE02			1887
-imx27kbd		MACH_IMX27KBD		IMX27KBD		1888
-kixvp435		MACH_KIXVP435		KIXVP435		1890
-kixnp435		MACH_KIXNP435		KIXNP435		1891
-africa			MACH_AFRICA		AFRICA			1892
-nh233			MACH_NH233		NH233			1893
-rd88f6183ap_ge		MACH_RD88F6183AP_GE	RD88F6183AP_GE		1894
-bcm4760			MACH_BCM4760		BCM4760			1895
-eddy_v2			MACH_EDDY_V2		EDDY_V2			1896
-realview_pba8		MACH_REALVIEW_PBA8	REALVIEW_PBA8		1897
-hid_a7			MACH_HID_A7		HID_A7			1898
-hero			MACH_HERO		HERO			1899
-omap_poseidon		MACH_OMAP_POSEIDON	OMAP_POSEIDON		1900
-realview_pbx		MACH_REALVIEW_PBX	REALVIEW_PBX		1901
-micro9s			MACH_MICRO9S		MICRO9S			1902
-mako			MACH_MAKO		MAKO			1903
-xdaflame		MACH_XDAFLAME		XDAFLAME		1904
-phidget_sbc2		MACH_PHIDGET_SBC2	PHIDGET_SBC2		1905
-limestone		MACH_LIMESTONE		LIMESTONE		1906
-iprobe_c32		MACH_IPROBE_C32		IPROBE_C32		1907
-rut100			MACH_RUT100		RUT100			1908
-asusp535		MACH_ASUSP535		ASUSP535		1909
-htcraphael		MACH_HTCRAPHAEL		HTCRAPHAEL		1910
-sygdg1			MACH_SYGDG1		SYGDG1			1911
-sygdg2			MACH_SYGDG2		SYGDG2			1912
-seoul			MACH_SEOUL		SEOUL			1913
-salerno			MACH_SALERNO		SALERNO			1914
-ucn_s3c64xx		MACH_UCN_S3C64XX	UCN_S3C64XX		1915
-msm7201a		MACH_MSM7201A		MSM7201A		1916
-lpr1			MACH_LPR1		LPR1			1917
-armadillo500fx		MACH_ARMADILLO500FX	ARMADILLO500FX		1918
-g3evm			MACH_G3EVM		G3EVM			1919
-z3_dm355		MACH_Z3_DM355		Z3_DM355		1920
-w90p910evb		MACH_W90P910EVB		W90P910EVB		1921
-w90p920evb		MACH_W90P920EVB		W90P920EVB		1922
-w90p950evb		MACH_W90P950EVB		W90P950EVB		1923
-w90n960evb		MACH_W90N960EVB		W90N960EVB		1924
-camhd			MACH_CAMHD		CAMHD			1925
-mvc100			MACH_MVC100		MVC100			1926
-electrum_200		MACH_ELECTRUM_200	ELECTRUM_200		1927
-htcjade			MACH_HTCJADE		HTCJADE			1928
-memphis			MACH_MEMPHIS		MEMPHIS			1929
-imx27sbc		MACH_IMX27SBC		IMX27SBC		1930
-lextar			MACH_LEXTAR		LEXTAR			1931
-mv88f6281gtw_ge		MACH_MV88F6281GTW_GE	MV88F6281GTW_GE		1932
-ncp			MACH_NCP		NCP			1933
-z32an_series		MACH_Z32AN		Z32AN			1934
-tmq_capd		MACH_TMQ_CAPD		TMQ_CAPD		1935
-omap3_wl		MACH_OMAP3_WL		OMAP3_WL		1936
-chumby			MACH_CHUMBY		CHUMBY			1937
-atsarm9			MACH_ATSARM9		ATSARM9			1938
-davinci_dm365_evm	MACH_DAVINCI_DM365_EVM	DAVINCI_DM365_EVM	1939
-bahamas			MACH_BAHAMAS		BAHAMAS			1940
-das			MACH_DAS		DAS			1941
-minidas			MACH_MINIDAS		MINIDAS			1942
-vk1000			MACH_VK1000		VK1000			1943
-centro			MACH_CENTRO		CENTRO			1944
-ctera_2bay		MACH_CTERA_2BAY		CTERA_2BAY		1945
-edgeconnect		MACH_EDGECONNECT	EDGECONNECT		1946
-nd27000			MACH_ND27000		ND27000			1947
-cobra			MACH_GEMALTO_COBRA	GEMALTO_COBRA		1948
-ingelabs_comet		MACH_INGELABS_COMET	INGELABS_COMET		1949
-pollux_wiz		MACH_POLLUX_WIZ		POLLUX_WIZ		1950
-blackstone		MACH_BLACKSTONE		BLACKSTONE		1951
-topaz			MACH_TOPAZ		TOPAZ			1952
-aixle			MACH_AIXLE		AIXLE			1953
-mw998			MACH_MW998		MW998			1954
-nokia_rx51		MACH_NOKIA_RX51		NOKIA_RX51		1955
-vsc5605ev		MACH_VSC5605EV		VSC5605EV		1956
-nt98700dk		MACH_NT98700DK		NT98700DK		1957
-icontact		MACH_ICONTACT		ICONTACT		1958
-swarco_frcpu		MACH_SWARCO_FRCPU	SWARCO_FRCPU		1959
-swarco_scpu		MACH_SWARCO_SCPU	SWARCO_SCPU		1960
-bbox_p16		MACH_BBOX_P16		BBOX_P16		1961
-bstd			MACH_BSTD		BSTD			1962
-sbc2440ii		MACH_SBC2440II		SBC2440II		1963
-pcm034			MACH_PCM034		PCM034			1964
-neso			MACH_NESO		NESO			1965
-wlnx_9g20		MACH_WLNX_9G20		WLNX_9G20		1966
-omap_zoom2		MACH_OMAP_ZOOM2		OMAP_ZOOM2		1967
-totemnova		MACH_TOTEMNOVA		TOTEMNOVA		1968
-c5000			MACH_C5000		C5000			1969
-unipo_at91sam9263	MACH_UNIPO_AT91SAM9263	UNIPO_AT91SAM9263	1970
-ethernut5		MACH_ETHERNUT5		ETHERNUT5		1971
-arm11			MACH_ARM11		ARM11			1972
-cpuat9260		MACH_CPUAT9260		CPUAT9260		1973
-cpupxa255		MACH_CPUPXA255		CPUPXA255		1974
-eukrea_cpuimx27		MACH_EUKREA_CPUIMX27	EUKREA_CPUIMX27		1975
-cheflux			MACH_CHEFLUX		CHEFLUX			1976
-eb_cpux9k2		MACH_EB_CPUX9K2		EB_CPUX9K2		1977
-opcotec			MACH_OPCOTEC		OPCOTEC			1978
-yt			MACH_YT			YT			1979
-motoq			MACH_MOTOQ		MOTOQ			1980
-bsb1			MACH_BSB1		BSB1			1981
-acs5k			MACH_ACS5K		ACS5K			1982
-milan			MACH_MILAN		MILAN			1983
-quartzv2		MACH_QUARTZV2		QUARTZV2		1984
-rsvp			MACH_RSVP		RSVP			1985
-rmp200			MACH_RMP200		RMP200			1986
-snapper_9260		MACH_SNAPPER_9260	SNAPPER_9260		1987
-dsm320			MACH_DSM320		DSM320			1988
-adsgcm			MACH_ADSGCM		ADSGCM			1989
-ase2_400		MACH_ASE2_400		ASE2_400		1990
-pizza			MACH_PIZZA		PIZZA			1991
-spot_ngpl		MACH_SPOT_NGPL		SPOT_NGPL		1992
-armata			MACH_ARMATA		ARMATA			1993
-exeda			MACH_EXEDA		EXEDA			1994
-mx31sf005		MACH_MX31SF005		MX31SF005		1995
-f5d8231_4_v2		MACH_F5D8231_4_V2	F5D8231_4_V2		1996
-q2440			MACH_Q2440		Q2440			1997
-qq2440			MACH_QQ2440		QQ2440			1998
-mini2440		MACH_MINI2440		MINI2440		1999
-colibri300		MACH_COLIBRI300		COLIBRI300		2000
-jades			MACH_JADES		JADES			2001
-spark			MACH_SPARK		SPARK			2002
-benzina			MACH_BENZINA		BENZINA			2003
-blaze			MACH_BLAZE		BLAZE			2004
-linkstation_ls_hgl	MACH_LINKSTATION_LS_HGL	LINKSTATION_LS_HGL	2005
-htckovsky		MACH_HTCKOVSKY		HTCKOVSKY		2006
-sony_prs505		MACH_SONY_PRS505	SONY_PRS505		2007
-hanlin_v3		MACH_HANLIN_V3		HANLIN_V3		2008
-sapphira		MACH_SAPPHIRA		SAPPHIRA		2009
-dack_sda_01		MACH_DACK_SDA_01	DACK_SDA_01		2010
-armbox			MACH_ARMBOX		ARMBOX			2011
-harris_rvp		MACH_HARRIS_RVP		HARRIS_RVP		2012
-ribaldo			MACH_RIBALDO		RIBALDO			2013
-agora			MACH_AGORA		AGORA			2014
-omap3_mini		MACH_OMAP3_MINI		OMAP3_MINI		2015
-a9sam6432_b		MACH_A9SAM6432_B	A9SAM6432_B		2016
-usg2410			MACH_USG2410		USG2410			2017
-pc72052_i10_revb	MACH_PC72052_I10_REVB	PC72052_I10_REVB	2018
-mx35_exm32		MACH_MX35_EXM32		MX35_EXM32		2019
-topas910		MACH_TOPAS910		TOPAS910		2020
-hyena			MACH_HYENA		HYENA			2021
-pospax			MACH_POSPAX		POSPAX			2022
-hdl_gx			MACH_HDL_GX		HDL_GX			2023
-ctera_4bay		MACH_CTERA_4BAY		CTERA_4BAY		2024
-ctera_plug_c		MACH_CTERA_PLUG_C	CTERA_PLUG_C		2025
-crwea_plug_i		MACH_CRWEA_PLUG_I	CRWEA_PLUG_I		2026
-egauge2			MACH_EGAUGE2		EGAUGE2			2027
-didj			MACH_DIDJ		DIDJ			2028
-m_s3c2443		MACH_MEISTER		MEISTER			2029
-htcblackstone		MACH_HTCBLACKSTONE	HTCBLACKSTONE		2030
-cpuat9g20		MACH_CPUAT9G20		CPUAT9G20		2031
-smdk6440		MACH_SMDK6440		SMDK6440		2032
-omap_35xx_mvp		MACH_OMAP_35XX_MVP	OMAP_35XX_MVP		2033
-ctera_plug_i		MACH_CTERA_PLUG_I	CTERA_PLUG_I		2034
-pvg610_100		MACH_PVG610		PVG610			2035
-hprw6815		MACH_HPRW6815		HPRW6815		2036
-omap3_oswald		MACH_OMAP3_OSWALD	OMAP3_OSWALD		2037
-nas4220b		MACH_NAS4220B		NAS4220B		2038
-htcraphael_cdma		MACH_HTCRAPHAEL_CDMA	HTCRAPHAEL_CDMA		2039
-htcdiamond_cdma		MACH_HTCDIAMOND_CDMA	HTCDIAMOND_CDMA		2040
-scaler			MACH_SCALER		SCALER			2041
-zylonite2		MACH_ZYLONITE2		ZYLONITE2		2042
-aspenite		MACH_ASPENITE		ASPENITE		2043
-teton			MACH_TETON		TETON			2044
-ttc_dkb			MACH_TTC_DKB		TTC_DKB			2045
-bishop2			MACH_BISHOP2		BISHOP2			2046
-ippv5			MACH_IPPV5		IPPV5			2047
-farm926			MACH_FARM926		FARM926			2048
-mmccpu			MACH_MMCCPU		MMCCPU			2049
-sgmsfl			MACH_SGMSFL		SGMSFL			2050
-tt8000			MACH_TT8000		TT8000			2051
-zrn4300lp		MACH_ZRN4300LP		ZRN4300LP		2052
-mptc			MACH_MPTC		MPTC			2053
-h6051			MACH_H6051		H6051			2054
-pvg610_101		MACH_PVG610_101		PVG610_101		2055
-stamp9261_pc_evb	MACH_STAMP9261_PC_EVB	STAMP9261_PC_EVB	2056
-pelco_odysseus		MACH_PELCO_ODYSSEUS	PELCO_ODYSSEUS		2057
-tny_a9260		MACH_TNY_A9260		TNY_A9260		2058
-tny_a9g20		MACH_TNY_A9G20		TNY_A9G20		2059
-aesop_mp2530f		MACH_AESOP_MP2530F	AESOP_MP2530F		2060
-dx900			MACH_DX900		DX900			2061
-cpodc2			MACH_CPODC2		CPODC2			2062
-tilt_8925		MACH_TILT_8925		TILT_8925		2063
-davinci_dm357_evm	MACH_DAVINCI_DM357_EVM	DAVINCI_DM357_EVM	2064
-swordfish		MACH_SWORDFISH		SWORDFISH		2065
-corvus			MACH_CORVUS		CORVUS			2066
-taurus			MACH_TAURUS		TAURUS			2067
-axm			MACH_AXM		AXM			2068
-axc			MACH_AXC		AXC			2069
-baby			MACH_BABY		BABY			2070
-mp200			MACH_MP200		MP200			2071
-pcm043			MACH_PCM043		PCM043			2072
-hanlin_v3c		MACH_HANLIN_V3C		HANLIN_V3C		2073
-kbk9g20			MACH_KBK9G20		KBK9G20			2074
-adsturbog5		MACH_ADSTURBOG5		ADSTURBOG5		2075
-avenger_lite1		MACH_AVENGER_LITE1	AVENGER_LITE1		2076
-suc82x			MACH_SUC		SUC			2077
-at91sam7s256		MACH_AT91SAM7S256	AT91SAM7S256		2078
-mendoza			MACH_MENDOZA		MENDOZA			2079
-kira			MACH_KIRA		KIRA			2080
-mx1hbm			MACH_MX1HBM		MX1HBM			2081
-quatro43xx		MACH_QUATRO43XX		QUATRO43XX		2082
-quatro4230		MACH_QUATRO4230		QUATRO4230		2083
-nsb400			MACH_NSB400		NSB400			2084
-drp255			MACH_DRP255		DRP255			2085
-thoth			MACH_THOTH		THOTH			2086
-firestone		MACH_FIRESTONE		FIRESTONE		2087
-asusp750		MACH_ASUSP750		ASUSP750		2088
-ctera_dl		MACH_CTERA_DL		CTERA_DL		2089
-socr			MACH_SOCR		SOCR			2090
-htcoxygen		MACH_HTCOXYGEN		HTCOXYGEN		2091
-heroc			MACH_HEROC		HEROC			2092
-zeno6800		MACH_ZENO6800		ZENO6800		2093
-sc2mcs			MACH_SC2MCS		SC2MCS			2094
-gene100			MACH_GENE100		GENE100			2095
-as353x			MACH_AS353X		AS353X			2096
-sheevaplug		MACH_SHEEVAPLUG		SHEEVAPLUG		2097
-at91sam9g20		MACH_AT91SAM9G20	AT91SAM9G20		2098
-mv88f6192gtw_fe		MACH_MV88F6192GTW_FE	MV88F6192GTW_FE		2099
-cc9200			MACH_CC9200		CC9200			2100
-sm9200			MACH_SM9200		SM9200			2101
-tp9200			MACH_TP9200		TP9200			2102
-snapperdv		MACH_SNAPPERDV		SNAPPERDV		2103
-avengers_lite		MACH_AVENGERS_LITE	AVENGERS_LITE		2104
-avengers_lite1		MACH_AVENGERS_LITE1	AVENGERS_LITE1		2105
-omap3axon		MACH_OMAP3AXON		OMAP3AXON		2106
-ma8xx			MACH_MA8XX		MA8XX			2107
-mp201ek			MACH_MP201EK		MP201EK			2108
-davinci_tux		MACH_DAVINCI_TUX	DAVINCI_TUX		2109
-mpa1600			MACH_MPA1600		MPA1600			2110
-pelco_troy		MACH_PELCO_TROY		PELCO_TROY		2111
-nsb667			MACH_NSB667		NSB667			2112
-rovers5_4mpix		MACH_ROVERS5_4MPIX	ROVERS5_4MPIX		2113
-twocom			MACH_TWOCOM		TWOCOM			2114
-ubisys_p9_rcu3r2	MACH_UBISYS_P9_RCU3R2	UBISYS_P9_RCU3R2	2115
-hero_espresso		MACH_HERO_ESPRESSO	HERO_ESPRESSO		2116
-afeusb			MACH_AFEUSB		AFEUSB			2117
-t830			MACH_T830		T830			2118
-spd8020_cc		MACH_SPD8020_CC		SPD8020_CC		2119
-om_3d7k			MACH_OM_3D7K		OM_3D7K			2120
-picocom2		MACH_PICOCOM2		PICOCOM2		2121
-uwg4mx27		MACH_UWG4MX27		UWG4MX27		2122
-uwg4mx31		MACH_UWG4MX31		UWG4MX31		2123
-cherry			MACH_CHERRY		CHERRY			2124
-mx51_babbage		MACH_MX51_BABBAGE	MX51_BABBAGE		2125
-s3c2440turkiye		MACH_S3C2440TURKIYE	S3C2440TURKIYE		2126
-tx37			MACH_TX37		TX37			2127
-sbc2800_9g20		MACH_SBC2800_9G20	SBC2800_9G20		2128
-benzglb			MACH_BENZGLB		BENZGLB			2129
-benztd			MACH_BENZTD		BENZTD			2130
-cartesio_plus		MACH_CARTESIO_PLUS	CARTESIO_PLUS		2131
-solrad_g20		MACH_SOLRAD_G20		SOLRAD_G20		2132
-mx27wallace		MACH_MX27WALLACE	MX27WALLACE		2133
-fmzwebmodul		MACH_FMZWEBMODUL	FMZWEBMODUL		2134
-rd78x00_masa		MACH_RD78X00_MASA	RD78X00_MASA		2135
-smallogger		MACH_SMALLOGGER		SMALLOGGER		2136
-ccw9p9215		MACH_CCW9P9215		CCW9P9215		2137
-dm355_leopard		MACH_DM355_LEOPARD	DM355_LEOPARD		2138
-ts219			MACH_TS219		TS219			2139
-tny_a9263		MACH_TNY_A9263		TNY_A9263		2140
-apollo			MACH_APOLLO		APOLLO			2141
-at91cap9stk		MACH_AT91CAP9STK	AT91CAP9STK		2142
-spc300			MACH_SPC300		SPC300			2143
-eko			MACH_EKO		EKO			2144
-ccw9m2443		MACH_CCW9M2443		CCW9M2443		2145
-ccw9m2443js		MACH_CCW9M2443JS	CCW9M2443JS		2146
-m2m_router_device	MACH_M2M_ROUTER_DEVICE	M2M_ROUTER_DEVICE	2147
-str9104nas		MACH_STAR9104NAS	STAR9104NAS		2148
-pca100			MACH_PCA100		PCA100			2149
-z3_dm365_mod_01		MACH_Z3_DM365_MOD_01	Z3_DM365_MOD_01		2150
-hipox			MACH_HIPOX		HIPOX			2151
-omap3_piteds		MACH_OMAP3_PITEDS	OMAP3_PITEDS		2152
-bm150r			MACH_BM150R		BM150R			2153
-tbone			MACH_TBONE		TBONE			2154
-merlin			MACH_MERLIN		MERLIN			2155
-falcon			MACH_FALCON		FALCON			2156
-davinci_da850_evm	MACH_DAVINCI_DA850_EVM	DAVINCI_DA850_EVM	2157
-s5p6440			MACH_S5P6440		S5P6440			2158
-at91sam9g10ek		MACH_AT91SAM9G10EK	AT91SAM9G10EK		2159
-omap_4430sdp		MACH_OMAP_4430SDP	OMAP_4430SDP		2160
-lpc313x			MACH_LPC313X		LPC313X			2161
-magx_zn5		MACH_MAGX_ZN5		MAGX_ZN5		2162
-magx_em30		MACH_MAGX_EM30		MAGX_EM30		2163
-magx_ve66		MACH_MAGX_VE66		MAGX_VE66		2164
-meesc			MACH_MEESC		MEESC			2165
-otc570			MACH_OTC570		OTC570			2166
-bcu2412			MACH_BCU2412		BCU2412			2167
-beacon			MACH_BEACON		BEACON			2168
-actia_tgw		MACH_ACTIA_TGW		ACTIA_TGW		2169
-e4430			MACH_E4430		E4430			2170
-ql300			MACH_QL300		QL300			2171
-btmavb101		MACH_BTMAVB101		BTMAVB101		2172
-btmawb101		MACH_BTMAWB101		BTMAWB101		2173
-sq201			MACH_SQ201		SQ201			2174
-quatro45xx		MACH_QUATRO45XX		QUATRO45XX		2175
-openpad			MACH_OPENPAD		OPENPAD			2176
-tx25			MACH_TX25		TX25			2177
-omap3_torpedo		MACH_OMAP3_TORPEDO	OMAP3_TORPEDO		2178
-htcraphael_k		MACH_HTCRAPHAEL_K	HTCRAPHAEL_K		2179
-lal43			MACH_LAL43		LAL43			2181
-htcraphael_cdma500	MACH_HTCRAPHAEL_CDMA500	HTCRAPHAEL_CDMA500	2182
-anw6410			MACH_ANW6410		ANW6410			2183
-htcprophet		MACH_HTCPROPHET		HTCPROPHET		2185
-cfa_10022		MACH_CFA_10022		CFA_10022		2186
-imx27_visstrim_m10	MACH_IMX27_VISSTRIM_M10	IMX27_VISSTRIM_M10	2187
-px2imx27		MACH_PX2IMX27		PX2IMX27		2188
-stm3210e_eval		MACH_STM3210E_EVAL	STM3210E_EVAL		2189
-dvs10			MACH_DVS10		DVS10			2190
-portuxg20		MACH_PORTUXG20		PORTUXG20		2191
-arm_spv			MACH_ARM_SPV		ARM_SPV			2192
-smdkc110		MACH_SMDKC110		SMDKC110		2193
-cabespresso		MACH_CABESPRESSO	CABESPRESSO		2194
-hmc800			MACH_HMC800		HMC800			2195
-sholes			MACH_SHOLES		SHOLES			2196
-btmxc31			MACH_BTMXC31		BTMXC31			2197
-dt501			MACH_DT501		DT501			2198
-ktx			MACH_KTX		KTX			2199
-omap3517evm		MACH_OMAP3517EVM	OMAP3517EVM		2200
-netspace_v2		MACH_NETSPACE_V2	NETSPACE_V2		2201
-netspace_max_v2		MACH_NETSPACE_MAX_V2	NETSPACE_MAX_V2		2202
-d2net_v2		MACH_D2NET_V2		D2NET_V2		2203
-net2big_v2		MACH_NET2BIG_V2		NET2BIG_V2		2204
-net4big_v2		MACH_NET4BIG_V2		NET4BIG_V2		2205
-net5big_v2		MACH_NET5BIG_V2		NET5BIG_V2		2206
-endb2443		MACH_ENDB2443		ENDB2443		2207
-inetspace_v2		MACH_INETSPACE_V2	INETSPACE_V2		2208
-tros			MACH_TROS		TROS			2209
-pelco_homer		MACH_PELCO_HOMER	PELCO_HOMER		2210
-ofsp8			MACH_OFSP8		OFSP8			2211
-at91sam9g45ekes		MACH_AT91SAM9G45EKES	AT91SAM9G45EKES		2212
-guf_cupid		MACH_GUF_CUPID		GUF_CUPID		2213
-eab1r			MACH_EAB1R		EAB1R			2214
-desirec			MACH_DESIREC		DESIREC			2215
-cordoba			MACH_CORDOBA		CORDOBA			2216
-irvine			MACH_IRVINE		IRVINE			2217
-sff772			MACH_SFF772		SFF772			2218
-pelco_milano		MACH_PELCO_MILANO	PELCO_MILANO		2219
-pc7302			MACH_PC7302		PC7302			2220
-bip6000			MACH_BIP6000		BIP6000			2221
-silvermoon		MACH_SILVERMOON		SILVERMOON		2222
-vc0830			MACH_VC0830		VC0830			2223
-dt430			MACH_DT430		DT430			2224
-ji42pf			MACH_JI42PF		JI42PF			2225
-gnet_ksm		MACH_GNET_KSM		GNET_KSM		2226
-gnet_sgm		MACH_GNET_SGM		GNET_SGM		2227
-gnet_sgr		MACH_GNET_SGR		GNET_SGR		2228
-omap3_icetekevm		MACH_OMAP3_ICETEKEVM	OMAP3_ICETEKEVM		2229
-pnp			MACH_PNP		PNP			2230
-ctera_2bay_k		MACH_CTERA_2BAY_K	CTERA_2BAY_K		2231
-ctera_2bay_u		MACH_CTERA_2BAY_U	CTERA_2BAY_U		2232
-sas_c			MACH_SAS_C		SAS_C			2233
-vma2315			MACH_VMA2315		VMA2315			2234
-vcs			MACH_VCS		VCS			2235
-spear600		MACH_SPEAR600		SPEAR600		2236
-spear300		MACH_SPEAR300		SPEAR300		2237
-spear1300		MACH_SPEAR1300		SPEAR1300		2238
-lilly1131		MACH_LILLY1131		LILLY1131		2239
-arvoo_ax301		MACH_ARVOO_AX301	ARVOO_AX301		2240
-mapphone		MACH_MAPPHONE		MAPPHONE		2241
-legend			MACH_LEGEND		LEGEND			2242
-salsa			MACH_SALSA		SALSA			2243
-lounge			MACH_LOUNGE		LOUNGE			2244
-vision			MACH_VISION		VISION			2245
-vmb20			MACH_VMB20		VMB20			2246
-hy2410			MACH_HY2410		HY2410			2247
-hy9315			MACH_HY9315		HY9315			2248
-bullwinkle		MACH_BULLWINKLE		BULLWINKLE		2249
-arm_ultimator2		MACH_ARM_ULTIMATOR2	ARM_ULTIMATOR2		2250
-vs_v210			MACH_VS_V210		VS_V210			2252
-vs_v212			MACH_VS_V212		VS_V212			2253
-hmt			MACH_HMT		HMT			2254
-km_kirkwood		MACH_KM_KIRKWOOD	KM_KIRKWOOD		2255
-vesper			MACH_VESPER		VESPER			2256
-str9			MACH_STR9		STR9			2257
-omap3_wl_ff		MACH_OMAP3_WL_FF	OMAP3_WL_FF		2258
-simcom			MACH_SIMCOM		SIMCOM			2259
-mcwebio			MACH_MCWEBIO		MCWEBIO			2260
-omap3_phrazer		MACH_OMAP3_PHRAZER	OMAP3_PHRAZER		2261
-darwin			MACH_DARWIN		DARWIN			2262
-oratiscomu		MACH_ORATISCOMU		ORATISCOMU		2263
-rtsbc20			MACH_RTSBC20		RTSBC20			2264
-sgh_i780		MACH_I780		I780			2265
-gemini324		MACH_GEMINI324		GEMINI324		2266
-oratislan		MACH_ORATISLAN		ORATISLAN		2267
-oratisalog		MACH_ORATISALOG		ORATISALOG		2268
-oratismadi		MACH_ORATISMADI		ORATISMADI		2269
-oratisot16		MACH_ORATISOT16		ORATISOT16		2270
-oratisdesk		MACH_ORATISDESK		ORATISDESK		2271
-vexpress		MACH_VEXPRESS		VEXPRESS		2272
-sintexo			MACH_SINTEXO		SINTEXO			2273
-cm3389			MACH_CM3389		CM3389			2274
-omap3_cio		MACH_OMAP3_CIO		OMAP3_CIO		2275
-sgh_i900		MACH_SGH_I900		SGH_I900		2276
-bst100			MACH_BST100		BST100			2277
-passion			MACH_PASSION		PASSION			2278
-indesign_at91sam	MACH_INDESIGN_AT91SAM	INDESIGN_AT91SAM	2279
-c4_badger		MACH_C4_BADGER		C4_BADGER		2280
-c4_viper		MACH_C4_VIPER		C4_VIPER		2281
-d2net			MACH_D2NET		D2NET			2282
-bigdisk			MACH_BIGDISK		BIGDISK			2283
-notalvision		MACH_NOTALVISION	NOTALVISION		2284
-omap3_kboc		MACH_OMAP3_KBOC		OMAP3_KBOC		2285
-cyclone			MACH_CYCLONE		CYCLONE			2286
-ninja			MACH_NINJA		NINJA			2287
-at91sam9g20ek_2mmc	MACH_AT91SAM9G20EK_2MMC	AT91SAM9G20EK_2MMC	2288
-bcmring			MACH_BCMRING		BCMRING			2289
-resol_dl2		MACH_RESOL_DL2		RESOL_DL2		2290
-ifosw			MACH_IFOSW		IFOSW			2291
-htcrhodium		MACH_HTCRHODIUM		HTCRHODIUM		2292
-htctopaz		MACH_HTCTOPAZ		HTCTOPAZ		2293
-matrix504		MACH_MATRIX504		MATRIX504		2294
-mrfsa			MACH_MRFSA		MRFSA			2295
-sc_p270			MACH_SC_P270		SC_P270			2296
-atlas5_evb		MACH_ATLAS5_EVB		ATLAS5_EVB		2297
-pelco_lobox		MACH_PELCO_LOBOX	PELCO_LOBOX		2298
-dilax_pcu200		MACH_DILAX_PCU200	DILAX_PCU200		2299
-leonardo		MACH_LEONARDO		LEONARDO		2300
-zoran_approach7		MACH_ZORAN_APPROACH7	ZORAN_APPROACH7		2301
-dp6xx			MACH_DP6XX		DP6XX			2302
-bcm2153_vesper		MACH_BCM2153_VESPER	BCM2153_VESPER		2303
-mahimahi		MACH_MAHIMAHI		MAHIMAHI		2304
-clickc			MACH_CLICKC		CLICKC			2305
-zb_gateway		MACH_ZB_GATEWAY		ZB_GATEWAY		2306
-tazcard			MACH_TAZCARD		TAZCARD			2307
-tazdev			MACH_TAZDEV		TAZDEV			2308
-annax_cb_arm		MACH_ANNAX_CB_ARM	ANNAX_CB_ARM		2309
-annax_dm3		MACH_ANNAX_DM3		ANNAX_DM3		2310
-cerebric		MACH_CEREBRIC		CEREBRIC		2311
-orca			MACH_ORCA		ORCA			2312
-pc9260			MACH_PC9260		PC9260			2313
-ems285a			MACH_EMS285A		EMS285A			2314
-gec2410			MACH_GEC2410		GEC2410			2315
-gec2440			MACH_GEC2440		GEC2440			2316
-mw903			MACH_ARCH_MW903		ARCH_MW903		2317
-mw2440			MACH_MW2440		MW2440			2318
-ecac2378		MACH_ECAC2378		ECAC2378		2319
-tazkiosk		MACH_TAZKIOSK		TAZKIOSK		2320
-whiterabbit_mch		MACH_WHITERABBIT_MCH	WHITERABBIT_MCH		2321
-sbox9263		MACH_SBOX9263		SBOX9263		2322
-smdk6442		MACH_SMDK6442		SMDK6442		2324
-openrd_base		MACH_OPENRD_BASE	OPENRD_BASE		2325
-incredible		MACH_INCREDIBLE		INCREDIBLE		2326
-incrediblec		MACH_INCREDIBLEC	INCREDIBLEC		2327
-heroct			MACH_HEROCT		HEROCT			2328
-mmnet1000		MACH_MMNET1000		MMNET1000		2329
-devkit8000		MACH_DEVKIT8000		DEVKIT8000		2330
-devkit9000		MACH_DEVKIT9000		DEVKIT9000		2331
-mx31txtr		MACH_MX31TXTR		MX31TXTR		2332
-u380			MACH_U380		U380			2333
-oamp3_hualu		MACH_HUALU_BOARD	HUALU_BOARD		2334
-npcmx50			MACH_NPCMX50		NPCMX50			2335
-mx51_efikamx		MACH_MX51_EFIKAMX	MX51_EFIKAMX		2336
-mx51_lange52		MACH_MX51_LANGE52	MX51_LANGE52		2337
-riom			MACH_RIOM		RIOM			2338
-comcas			MACH_COMCAS		COMCAS			2339
-wsi_mx27		MACH_WSI_MX27		WSI_MX27		2340
-cm_t35			MACH_CM_T35		CM_T35			2341
-net2big			MACH_NET2BIG		NET2BIG			2342
-motorola_a1600		MACH_MOTOROLA_A1600	MOTOROLA_A1600		2343
-igep0020		MACH_IGEP0020		IGEP0020		2344
-igep0010		MACH_IGEP0010		IGEP0010		2345
-mv6281gtwge2		MACH_MV6281GTWGE2	MV6281GTWGE2		2346
-scat100			MACH_SCAT100		SCAT100			2347
-sanmina			MACH_SANMINA		SANMINA			2348
-momento			MACH_MOMENTO		MOMENTO			2349
-nuc9xx			MACH_NUC9XX		NUC9XX			2350
-nuc910evb		MACH_NUC910EVB		NUC910EVB		2351
-nuc920evb		MACH_NUC920EVB		NUC920EVB		2352
-nuc950evb		MACH_NUC950EVB		NUC950EVB		2353
-nuc945evb		MACH_NUC945EVB		NUC945EVB		2354
-nuc960evb		MACH_NUC960EVB		NUC960EVB		2355
-nuc932evb		MACH_NUC932EVB		NUC932EVB		2356
-nuc900			MACH_NUC900		NUC900			2357
-sd1soc			MACH_SD1SOC		SD1SOC			2358
-ln2440bc		MACH_LN2440BC		LN2440BC		2359
-rsbc			MACH_RSBC		RSBC			2360
-openrd_client		MACH_OPENRD_CLIENT	OPENRD_CLIENT		2361
-hpipaq11x		MACH_HPIPAQ11X		HPIPAQ11X		2362
-wayland			MACH_WAYLAND		WAYLAND			2363
-acnbsx102		MACH_ACNBSX102		ACNBSX102		2364
-hwat91			MACH_HWAT91		HWAT91			2365
-at91sam9263cs		MACH_AT91SAM9263CS	AT91SAM9263CS		2366
-csb732			MACH_CSB732		CSB732			2367
-u8500			MACH_U8500		U8500			2368
-huqiu			MACH_HUQIU		HUQIU			2369
-mx51_efikasb		MACH_MX51_EFIKASB	MX51_EFIKASB		2370
-pmt1g			MACH_PMT1G		PMT1G			2371
-htcelf			MACH_HTCELF		HTCELF			2372
-armadillo420		MACH_ARMADILLO420	ARMADILLO420		2373
-armadillo440		MACH_ARMADILLO440	ARMADILLO440		2374
-u_chip_dual_arm		MACH_U_CHIP_DUAL_ARM	U_CHIP_DUAL_ARM		2375
-csr_bdb3		MACH_CSR_BDB3		CSR_BDB3		2376
-dolby_cat1018		MACH_DOLBY_CAT1018	DOLBY_CAT1018		2377
-hy9307			MACH_HY9307		HY9307			2378
-aspire_easystore	MACH_A_ES		A_ES			2379
-davinci_irif		MACH_DAVINCI_IRIF	DAVINCI_IRIF		2380
-agama9263		MACH_AGAMA9263		AGAMA9263		2381
-marvell_jasper		MACH_MARVELL_JASPER	MARVELL_JASPER		2382
-flint			MACH_FLINT		FLINT			2383
-tavorevb3		MACH_TAVOREVB3		TAVOREVB3		2384
-sch_m490		MACH_SCH_M490		SCH_M490		2386
-rbl01			MACH_RBL01		RBL01			2387
-omnifi			MACH_OMNIFI		OMNIFI			2388
-otavalo			MACH_OTAVALO		OTAVALO			2389
-htc_excalibur_s620	MACH_HTC_EXCALIBUR_S620	HTC_EXCALIBUR_S620	2391
-htc_opal		MACH_HTC_OPAL		HTC_OPAL		2392
-touchbook		MACH_TOUCHBOOK		TOUCHBOOK		2393
-latte			MACH_LATTE		LATTE			2394
-xa200			MACH_XA200		XA200			2395
-nimrod			MACH_NIMROD		NIMROD			2396
-cc9p9215_3g		MACH_CC9P9215_3G	CC9P9215_3G		2397
-cc9p9215_3gjs		MACH_CC9P9215_3GJS	CC9P9215_3GJS		2398
-tk71			MACH_TK71		TK71			2399
-comham3525		MACH_COMHAM3525		COMHAM3525		2400
-mx31erebus		MACH_MX31EREBUS		MX31EREBUS		2401
-mcardmx27		MACH_MCARDMX27		MCARDMX27		2402
-paradise		MACH_PARADISE		PARADISE		2403
-tide			MACH_TIDE		TIDE			2404
-wzl2440			MACH_WZL2440		WZL2440			2405
-sdrdemo			MACH_SDRDEMO		SDRDEMO			2406
-ethercan2		MACH_ETHERCAN2		ETHERCAN2		2407
-ecmimg20		MACH_ECMIMG20		ECMIMG20		2408
-omap_dragon		MACH_OMAP_DRAGON	OMAP_DRAGON		2409
-halo			MACH_HALO		HALO			2410
-huangshan		MACH_HUANGSHAN		HUANGSHAN		2411
-vl_ma2sc		MACH_VL_MA2SC		VL_MA2SC		2412
-raumfeld_rc		MACH_RAUMFELD_RC	RAUMFELD_RC		2413
-raumfeld_connector	MACH_RAUMFELD_CONNECTOR	RAUMFELD_CONNECTOR	2414
-raumfeld_speaker	MACH_RAUMFELD_SPEAKER	RAUMFELD_SPEAKER	2415
-multibus_master		MACH_MULTIBUS_MASTER	MULTIBUS_MASTER		2416
-multibus_pbk		MACH_MULTIBUS_PBK	MULTIBUS_PBK		2417
-tnetv107x		MACH_TNETV107X		TNETV107X		2418
-snake			MACH_SNAKE		SNAKE			2419
-cwmx27			MACH_CWMX27		CWMX27			2420
-sch_m480		MACH_SCH_M480		SCH_M480		2421
-platypus		MACH_PLATYPUS		PLATYPUS		2422
-pss2			MACH_PSS2		PSS2			2423
-davinci_apm150		MACH_DAVINCI_APM150	DAVINCI_APM150		2424
-str9100			MACH_STR9100		STR9100			2425
-net5big			MACH_NET5BIG		NET5BIG			2426
-seabed9263		MACH_SEABED9263		SEABED9263		2427
-mx51_m2id		MACH_MX51_M2ID		MX51_M2ID		2428
-octvocplus_eb		MACH_OCTVOCPLUS_EB	OCTVOCPLUS_EB		2429
-klk_firefox		MACH_KLK_FIREFOX	KLK_FIREFOX		2430
-klk_wirma_module	MACH_KLK_WIRMA_MODULE	KLK_WIRMA_MODULE	2431
-klk_wirma_mmi		MACH_KLK_WIRMA_MMI	KLK_WIRMA_MMI		2432
-supersonic		MACH_SUPERSONIC		SUPERSONIC		2433
-liberty			MACH_LIBERTY		LIBERTY			2434
-mh355			MACH_MH355		MH355			2435
-pc7802			MACH_PC7802		PC7802			2436
-gnet_sgc		MACH_GNET_SGC		GNET_SGC		2437
-einstein15		MACH_EINSTEIN15		EINSTEIN15		2438
-cmpd			MACH_CMPD		CMPD			2439
-davinci_hase1		MACH_DAVINCI_HASE1	DAVINCI_HASE1		2440
-lgeincitephone		MACH_LGEINCITEPHONE	LGEINCITEPHONE		2441
-ea313x			MACH_EA313X		EA313X			2442
-fwbd_39064		MACH_FWBD_39064		FWBD_39064		2443
-fwbd_390128		MACH_FWBD_390128	FWBD_390128		2444
-pelco_moe		MACH_PELCO_MOE		PELCO_MOE		2445
-minimix27		MACH_MINIMIX27		MINIMIX27		2446
-omap3_thunder		MACH_OMAP3_THUNDER	OMAP3_THUNDER		2447
-passionc		MACH_PASSIONC		PASSIONC		2448
-mx27amata		MACH_MX27AMATA		MX27AMATA		2449
-bgat1			MACH_BGAT1		BGAT1			2450
-buzz			MACH_BUZZ		BUZZ			2451
-mb9g20			MACH_MB9G20		MB9G20			2452
-yushan			MACH_YUSHAN		YUSHAN			2453
-lizard			MACH_LIZARD		LIZARD			2454
-omap3polycom		MACH_OMAP3POLYCOM	OMAP3POLYCOM		2455
-smdkv210		MACH_SMDKV210		SMDKV210		2456
-bravo			MACH_BRAVO		BRAVO			2457
-siogentoo1		MACH_SIOGENTOO1		SIOGENTOO1		2458
-siogentoo2		MACH_SIOGENTOO2		SIOGENTOO2		2459
-sm3k			MACH_SM3K		SM3K			2460
-acer_tempo_f900		MACH_ACER_TEMPO_F900	ACER_TEMPO_F900		2461
-glittertind		MACH_GLITTERTIND	GLITTERTIND		2463
-omap_zoom3		MACH_OMAP_ZOOM3		OMAP_ZOOM3		2464
-omap_3630sdp		MACH_OMAP_3630SDP	OMAP_3630SDP		2465
-cybook2440		MACH_CYBOOK2440		CYBOOK2440		2466
-torino_s		MACH_TORINO_S		TORINO_S		2467
-havana			MACH_HAVANA		HAVANA			2468
-beaumont_11		MACH_BEAUMONT_11	BEAUMONT_11		2469
-vanguard		MACH_VANGUARD		VANGUARD		2470
-s5pc110_draco		MACH_S5PC110_DRACO	S5PC110_DRACO		2471
-cartesio_two		MACH_CARTESIO_TWO	CARTESIO_TWO		2472
-aster			MACH_ASTER		ASTER			2473
-voguesv210		MACH_VOGUESV210		VOGUESV210		2474
-acm500x			MACH_ACM500X		ACM500X			2475
-km9260			MACH_KM9260		KM9260			2476
-nideflexg1		MACH_NIDEFLEXG1		NIDEFLEXG1		2477
-ctera_plug_io		MACH_CTERA_PLUG_IO	CTERA_PLUG_IO		2478
-smartq7			MACH_SMARTQ7		SMARTQ7			2479
-at91sam9g10ek2		MACH_AT91SAM9G10EK2	AT91SAM9G10EK2		2480
-asusp527		MACH_ASUSP527		ASUSP527		2481
-at91sam9g20mpm2		MACH_AT91SAM9G20MPM2	AT91SAM9G20MPM2		2482
-topasa900		MACH_TOPASA900		TOPASA900		2483
-electrum_100		MACH_ELECTRUM_100	ELECTRUM_100		2484
-mx51grb			MACH_MX51GRB		MX51GRB			2485
-xea300			MACH_XEA300		XEA300			2486
-htcstartrek		MACH_HTCSTARTREK	HTCSTARTREK		2487
-lima			MACH_LIMA		LIMA			2488
-csb740			MACH_CSB740		CSB740			2489
-usb_s8815		MACH_USB_S8815		USB_S8815		2490
-watson_efm_plugin	MACH_WATSON_EFM_PLUGIN	WATSON_EFM_PLUGIN	2491
-milkyway		MACH_MILKYWAY		MILKYWAY		2492
-g4evm			MACH_G4EVM		G4EVM			2493
-picomod6		MACH_PICOMOD6		PICOMOD6		2494
-omapl138_hawkboard	MACH_OMAPL138_HAWKBOARD	OMAPL138_HAWKBOARD	2495
-ip6000			MACH_IP6000		IP6000			2496
-ip6010			MACH_IP6010		IP6010			2497
-utm400			MACH_UTM400		UTM400			2498
-omap3_zybex		MACH_OMAP3_ZYBEX	OMAP3_ZYBEX		2499
-wireless_space		MACH_WIRELESS_SPACE	WIRELESS_SPACE		2500
-sx560			MACH_SX560		SX560			2501
-ts41x			MACH_TS41X		TS41X			2502
-elphel10373		MACH_ELPHEL10373	ELPHEL10373		2503
-rhobot			MACH_RHOBOT		RHOBOT			2504
-mx51_refresh		MACH_MX51_REFRESH	MX51_REFRESH		2505
-ls9260			MACH_LS9260		LS9260			2506
-shank			MACH_SHANK		SHANK			2507
-qsd8x50_st1		MACH_QSD8X50_ST1	QSD8X50_ST1		2508
-at91sam9m10ekes		MACH_AT91SAM9M10EKES	AT91SAM9M10EKES		2509
-hiram			MACH_HIRAM		HIRAM			2510
-phy3250			MACH_PHY3250		PHY3250			2511
-ea3250			MACH_EA3250		EA3250			2512
-fdi3250			MACH_FDI3250		FDI3250			2513
-at91sam9263nit		MACH_AT91SAM9263NIT	AT91SAM9263NIT		2515
-ccmx51			MACH_CCMX51		CCMX51			2516
-ccmx51js		MACH_CCMX51JS		CCMX51JS		2517
-ccwmx51			MACH_CCWMX51		CCWMX51			2518
-ccwmx51js		MACH_CCWMX51JS		CCWMX51JS		2519
-mini6410		MACH_MINI6410		MINI6410		2520
-tiny6410		MACH_TINY6410		TINY6410		2521
-nano6410		MACH_NANO6410		NANO6410		2522
-at572d940hfnldb		MACH_AT572D940HFNLDB	AT572D940HFNLDB		2523
-htcleo			MACH_HTCLEO		HTCLEO			2524
-avp13			MACH_AVP13		AVP13			2525
-xxsvideod		MACH_XXSVIDEOD		XXSVIDEOD		2526
-vpnext			MACH_VPNEXT		VPNEXT			2527
-swarco_itc3		MACH_SWARCO_ITC3	SWARCO_ITC3		2528
-tx51			MACH_TX51		TX51			2529
-dolby_cat1021		MACH_DOLBY_CAT1021	DOLBY_CAT1021		2530
-mx28evk			MACH_MX28EVK		MX28EVK			2531
-phoenix260		MACH_PHOENIX260		PHOENIX260		2532
-uvaca_stork		MACH_UVACA_STORK	UVACA_STORK		2533
-smartq5			MACH_SMARTQ5		SMARTQ5			2534
-all3078			MACH_ALL3078		ALL3078			2535
-ctera_2bay_ds		MACH_CTERA_2BAY_DS	CTERA_2BAY_DS		2536
-siogentoo3		MACH_SIOGENTOO3		SIOGENTOO3		2537
-epb5000			MACH_EPB5000		EPB5000			2538
-hy9263			MACH_HY9263		HY9263			2539
-acer_tempo_m900		MACH_ACER_TEMPO_M900	ACER_TEMPO_M900		2540
-acer_tempo_dx650	MACH_ACER_TEMPO_DX900	ACER_TEMPO_DX900	2541
-acer_tempo_x960		MACH_ACER_TEMPO_X960	ACER_TEMPO_X960		2542
-acer_eten_v900		MACH_ACER_ETEN_V900	ACER_ETEN_V900		2543
-acer_eten_x900		MACH_ACER_ETEN_X900	ACER_ETEN_X900		2544
-bonnell			MACH_BONNELL		BONNELL			2545
-oht_mx27		MACH_OHT_MX27		OHT_MX27		2546
-htcquartz		MACH_HTCQUARTZ		HTCQUARTZ		2547
-davinci_dm6467tevm	MACH_DAVINCI_DM6467TEVM	DAVINCI_DM6467TEVM	2548
-c3ax03			MACH_C3AX03		C3AX03			2549
-mxt_td60		MACH_MXT_TD60		MXT_TD60		2550
-esyx			MACH_ESYX		ESYX			2551
-dove_db2		MACH_DOVE_DB2		DOVE_DB2		2552
-bulldog			MACH_BULLDOG		BULLDOG			2553
-derell_me2000		MACH_DERELL_ME2000	DERELL_ME2000		2554
-bcmring_base		MACH_BCMRING_BASE	BCMRING_BASE		2555
-bcmring_evm		MACH_BCMRING_EVM	BCMRING_EVM		2556
-bcmring_evm_jazz	MACH_BCMRING_EVM_JAZZ	BCMRING_EVM_JAZZ	2557
-bcmring_sp		MACH_BCMRING_SP		BCMRING_SP		2558
-bcmring_sv		MACH_BCMRING_SV		BCMRING_SV		2559
-bcmring_sv_jazz		MACH_BCMRING_SV_JAZZ	BCMRING_SV_JAZZ		2560
-bcmring_tablet		MACH_BCMRING_TABLET	BCMRING_TABLET		2561
-bcmring_vp		MACH_BCMRING_VP		BCMRING_VP		2562
-bcmring_evm_seikor	MACH_BCMRING_EVM_SEIKOR	BCMRING_EVM_SEIKOR	2563
-bcmring_sp_wqvga	MACH_BCMRING_SP_WQVGA	BCMRING_SP_WQVGA	2564
-bcmring_custom		MACH_BCMRING_CUSTOM	BCMRING_CUSTOM		2565
-acer_s200		MACH_ACER_S200		ACER_S200		2566
-bt270			MACH_BT270		BT270			2567
-iseo			MACH_ISEO		ISEO			2568
-cezanne			MACH_CEZANNE		CEZANNE			2569
-lucca			MACH_LUCCA		LUCCA			2570
-supersmart		MACH_SUPERSMART		SUPERSMART		2571
-arm11_board		MACH_CS_MISANO		CS_MISANO		2572
-magnolia2		MACH_MAGNOLIA2		MAGNOLIA2		2573
-emxx			MACH_EMXX		EMXX			2574
-outlaw			MACH_OUTLAW		OUTLAW			2575
-riot_bei2		MACH_RIOT_BEI2		RIOT_BEI2		2576
-riot_gx2		MACH_RIOT_VOX		RIOT_VOX		2577
-riot_x37		MACH_RIOT_X37		RIOT_X37		2578
-mega25mx		MACH_MEGA25MX		MEGA25MX		2579
-benzina2		MACH_BENZINA2		BENZINA2		2580
-ignite			MACH_IGNITE		IGNITE			2581
-foggia			MACH_FOGGIA		FOGGIA			2582
-arezzo			MACH_AREZZO		AREZZO			2583
-leica_skywalker		MACH_LEICA_SKYWALKER	LEICA_SKYWALKER		2584
-jacinto2_jamr		MACH_JACINTO2_JAMR	JACINTO2_JAMR		2585
-gts_nova		MACH_GTS_NOVA		GTS_NOVA		2586
-p3600			MACH_P3600		P3600			2587
-dlt2			MACH_DLT2		DLT2			2588
-df3120			MACH_DF3120		DF3120			2589
-ecucore_9g20		MACH_ECUCORE_9G20	ECUCORE_9G20		2590
-nautel_am35xx		MACH_NAUTEL_LPC3240	NAUTEL_LPC3240		2591
-glacier			MACH_GLACIER		GLACIER			2592
-phrazer_bulldog		MACH_PHRAZER_BULLDOG	PHRAZER_BULLDOG		2593
-omap3_bulldog		MACH_OMAP3_BULLDOG	OMAP3_BULLDOG		2594
-pca101			MACH_PCA101		PCA101			2595
-buzzc			MACH_BUZZC		BUZZC			2596
-sasie2			MACH_SASIE2		SASIE2			2597
-smartmeter_dl		MACH_SMARTMETER_DL	SMARTMETER_DL		2599
-wzl6410			MACH_WZL6410		WZL6410			2600
-wzl6410m		MACH_WZL6410M		WZL6410M		2601
-wzl6410f		MACH_WZL6410F		WZL6410F		2602
-wzl6410i		MACH_WZL6410I		WZL6410I		2603
-spacecom1		MACH_SPACECOM1		SPACECOM1		2604
-pingu920		MACH_PINGU920		PINGU920		2605
-bravoc			MACH_BRAVOC		BRAVOC			2606
-vdssw			MACH_VDSSW		VDSSW			2608
-romulus			MACH_ROMULUS		ROMULUS			2609
-omap_magic		MACH_OMAP_MAGIC		OMAP_MAGIC		2610
-eltd100			MACH_ELTD100		ELTD100			2611
-capc7117		MACH_CAPC7117		CAPC7117		2612
-swan			MACH_SWAN		SWAN			2613
-veu			MACH_VEU		VEU			2614
-rm2			MACH_RM2		RM2			2615
-tt2100			MACH_TT2100		TT2100			2616
-venice			MACH_VENICE		VENICE			2617
-pc7323			MACH_PC7323		PC7323			2618
-masp			MACH_MASP		MASP			2619
-fujitsu_tvstbsoc0	MACH_FUJITSU_TVSTBSOC	FUJITSU_TVSTBSOC	2620
-fujitsu_tvstbsoc1	MACH_FUJITSU_TVSTBSOC1	FUJITSU_TVSTBSOC1	2621
-lexikon			MACH_LEXIKON		LEXIKON			2622
-mini2440v2		MACH_MINI2440V2		MINI2440V2		2623
-icontrol		MACH_ICONTROL		ICONTROL		2624
-gplugd			MACH_GPLUGD		GPLUGD			2625
-qsd8x50a_st1_1		MACH_QSD8X50A_ST1_1	QSD8X50A_ST1_1		2626
-qsd8x50a_st1_5		MACH_QSD8X50A_ST1_5	QSD8X50A_ST1_5		2627
-bee			MACH_BEE		BEE			2628
-mx23evk			MACH_MX23EVK		MX23EVK			2629
-ap4evb			MACH_AP4EVB		AP4EVB			2630
-stockholm		MACH_STOCKHOLM		STOCKHOLM		2631
-lpc_h3131		MACH_LPC_H3131		LPC_H3131		2632
-stingray		MACH_STINGRAY		STINGRAY		2633
-kraken			MACH_KRAKEN		KRAKEN			2634
-gw2388			MACH_GW2388		GW2388			2635
-jadecpu			MACH_JADECPU		JADECPU			2636
-carlisle		MACH_CARLISLE		CARLISLE		2637
-lux_sf9			MACH_LUX_SF9		LUX_SF9			2638
-nemid_tb		MACH_NEMID_TB		NEMID_TB		2639
-terrier			MACH_TERRIER		TERRIER			2640
-turbot			MACH_TURBOT		TURBOT			2641
-sanddab			MACH_SANDDAB		SANDDAB			2642
-mx35_cicada		MACH_MX35_CICADA	MX35_CICADA		2643
-ghi2703d		MACH_GHI2703D		GHI2703D		2644
-lux_sfx9		MACH_LUX_SFX9		LUX_SFX9		2645
-lux_sf9g		MACH_LUX_SF9G		LUX_SF9G		2646
-lux_edk9		MACH_LUX_EDK9		LUX_EDK9		2647
-hw90240			MACH_HW90240		HW90240			2648
-dm365_leopard		MACH_DM365_LEOPARD	DM365_LEOPARD		2649
-mityomapl138		MACH_MITYOMAPL138	MITYOMAPL138		2650
-scat110			MACH_SCAT110		SCAT110			2651
-acer_a1			MACH_ACER_A1		ACER_A1			2652
-cmcontrol		MACH_CMCONTROL		CMCONTROL		2653
-pelco_lamar		MACH_PELCO_LAMAR	PELCO_LAMAR		2654
-rfp43			MACH_RFP43		RFP43			2655
-sk86r0301		MACH_SK86R0301		SK86R0301		2656
-ctpxa			MACH_CTPXA		CTPXA			2657
-epb_arm9_a		MACH_EPB_ARM9_A		EPB_ARM9_A		2658
-guruplug		MACH_GURUPLUG		GURUPLUG		2659
-spear310		MACH_SPEAR310		SPEAR310		2660
-spear320		MACH_SPEAR320		SPEAR320		2661
-robotx			MACH_ROBOTX		ROBOTX			2662
-lsxhl			MACH_LSXHL		LSXHL			2663
-smartlite		MACH_SMARTLITE		SMARTLITE		2664
-cws2			MACH_CWS2		CWS2			2665
-m619			MACH_M619		M619			2666
-smartview		MACH_SMARTVIEW		SMARTVIEW		2667
-lsa_salsa		MACH_LSA_SALSA		LSA_SALSA		2668
-kizbox			MACH_KIZBOX		KIZBOX			2669
-htccharmer		MACH_HTCCHARMER		HTCCHARMER		2670
-guf_neso_lt		MACH_GUF_NESO_LT	GUF_NESO_LT		2671
-pm9g45			MACH_PM9G45		PM9G45			2672
-htcpanther		MACH_HTCPANTHER		HTCPANTHER		2673
-htcpanther_cdma		MACH_HTCPANTHER_CDMA	HTCPANTHER_CDMA		2674
-reb01			MACH_REB01		REB01			2675
-aquila			MACH_AQUILA		AQUILA			2676
-spark_sls_hw2		MACH_SPARK_SLS_HW2	SPARK_SLS_HW2		2677
-esata_sheevaplug	MACH_ESATA_SHEEVAPLUG	ESATA_SHEEVAPLUG	2678
-msm7x30_surf		MACH_MSM7X30_SURF	MSM7X30_SURF		2679
-micro2440		MACH_MICRO2440		MICRO2440		2680
-am2440			MACH_AM2440		AM2440			2681
-tq2440			MACH_TQ2440		TQ2440			2682
-ea2478devkit		MACH_EA2478DEVKIT	EA2478DEVKIT		2683
-ak880x			MACH_AK880X		AK880X			2684
-cobra3530		MACH_COBRA3530		COBRA3530		2685
-pmppb			MACH_PMPPB		PMPPB			2686
-u6715			MACH_U6715		U6715			2687
-axar1500_sender		MACH_AXAR1500_SENDER	AXAR1500_SENDER		2688
-g30_dvb			MACH_G30_DVB		G30_DVB			2689
-vc088x			MACH_VC088X		VC088X			2690
-mioa702			MACH_MIOA702		MIOA702			2691
-hpmin			MACH_HPMIN		HPMIN			2692
-ak880xak		MACH_AK880XAK		AK880XAK		2693
-arm926tomap850		MACH_ARM926TOMAP850	ARM926TOMAP850		2694
-lkevm			MACH_LKEVM		LKEVM			2695
-mw6410			MACH_MW6410		MW6410			2696
-terastation_wxl		MACH_TERASTATION_WXL	TERASTATION_WXL		2697
-cpu8000e		MACH_CPU8000E		CPU8000E		2698
-tokyo			MACH_TOKYO		TOKYO			2700
-msm7201a_surf		MACH_MSM7201A_SURF	MSM7201A_SURF		2701
-msm7201a_ffa		MACH_MSM7201A_FFA	MSM7201A_FFA		2702
-msm7x25_surf		MACH_MSM7X25_SURF	MSM7X25_SURF		2703
-msm7x25_ffa		MACH_MSM7X25_FFA	MSM7X25_FFA		2704
-msm7x27_surf		MACH_MSM7X27_SURF	MSM7X27_SURF		2705
-msm7x27_ffa		MACH_MSM7X27_FFA	MSM7X27_FFA		2706
-msm7x30_ffa		MACH_MSM7X30_FFA	MSM7X30_FFA		2707
-qsd8x50_surf		MACH_QSD8X50_SURF	QSD8X50_SURF		2708
-qsd8x50_comet		MACH_QSD8X50_COMET	QSD8X50_COMET		2709
-qsd8x50_ffa		MACH_QSD8X50_FFA	QSD8X50_FFA		2710
-qsd8x50a_surf		MACH_QSD8X50A_SURF	QSD8X50A_SURF		2711
-qsd8x50a_ffa		MACH_QSD8X50A_FFA	QSD8X50A_FFA		2712
-adx_xgcp10		MACH_ADX_XGCP10		ADX_XGCP10		2713
-mcgwumts2a		MACH_MCGWUMTS2A		MCGWUMTS2A		2714
-mobikt			MACH_MOBIKT		MOBIKT			2715
-mx53_evk		MACH_MX53_EVK		MX53_EVK		2716
-igep0030		MACH_IGEP0030		IGEP0030		2717
-axell_h40_h50_ctrl	MACH_AXELL_H40_H50_CTRL	AXELL_H40_H50_CTRL	2718
-dtcommod		MACH_DTCOMMOD		DTCOMMOD		2719
-gould			MACH_GOULD		GOULD			2720
-siberia			MACH_SIBERIA		SIBERIA			2721
-sbc3530			MACH_SBC3530		SBC3530			2722
-qarm			MACH_QARM		QARM			2723
-mips			MACH_MIPS		MIPS			2724
-mx27grb			MACH_MX27GRB		MX27GRB			2725
-sbc8100			MACH_SBC8100		SBC8100			2726
-saarb			MACH_SAARB		SAARB			2727
-omap3mini		MACH_OMAP3MINI		OMAP3MINI		2728
-cnmbook7se		MACH_CNMBOOK7SE		CNMBOOK7SE		2729
-catan			MACH_CATAN		CATAN			2730
-harmony			MACH_HARMONY		HARMONY			2731
-tonga			MACH_TONGA		TONGA			2732
-cybook_orizon		MACH_CYBOOK_ORIZON	CYBOOK_ORIZON		2733
-htcrhodiumcdma		MACH_HTCRHODIUMCDMA	HTCRHODIUMCDMA		2734
-epc_g45			MACH_EPC_G45		EPC_G45			2735
-epc_lpc3250		MACH_EPC_LPC3250	EPC_LPC3250		2736
-mxc91341evb		MACH_MXC91341EVB	MXC91341EVB		2737
-rtw1000			MACH_RTW1000		RTW1000			2738
-bobcat			MACH_BOBCAT		BOBCAT			2739
-trizeps6		MACH_TRIZEPS6		TRIZEPS6		2740
-msm7x30_fluid		MACH_MSM7X30_FLUID	MSM7X30_FLUID		2741
-nedap9263		MACH_NEDAP9263		NEDAP9263		2742
-netgear_ms2110		MACH_NETGEAR_MS2110	NETGEAR_MS2110		2743
-bmx			MACH_BMX		BMX			2744
-netstream		MACH_NETSTREAM		NETSTREAM		2745
-vpnext_rcu		MACH_VPNEXT_RCU		VPNEXT_RCU		2746
-vpnext_mpu		MACH_VPNEXT_MPU		VPNEXT_MPU		2747
-bcmring_tablet_v1	MACH_BCMRING_TABLET_V1	BCMRING_TABLET_V1	2748
-sgarm10			MACH_SGARM10		SGARM10			2749
-cm_t3517		MACH_CM_T3517		CM_T3517		2750
-dig297			MACH_OMAP3_CPS		OMAP3_CPS		2751
-axar1500_receiver	MACH_AXAR1500_RECEIVER	AXAR1500_RECEIVER	2752
-wbd222			MACH_WBD222		WBD222			2753
-mt65xx			MACH_MT65XX		MT65XX			2754
-msm8x60_surf		MACH_MSM8X60_SURF	MSM8X60_SURF		2755
-msm8x60_sim		MACH_MSM8X60_SIM	MSM8X60_SIM		2756
-tcc8000_sdk		MACH_TCC8000_SDK	TCC8000_SDK		2758
-nanos			MACH_NANOS		NANOS			2759
-stamp9g10		MACH_STAMP9G10		STAMP9G10		2760
-stamp9g45		MACH_STAMP9G45		STAMP9G45		2761
-h6053			MACH_H6053		H6053			2762
-smint01			MACH_SMINT01		SMINT01			2763
-prtlvt2			MACH_PRTLVT2		PRTLVT2			2764
-ap420			MACH_AP420		AP420			2765
-davinci_dm365_fc	MACH_DAVINCI_DM365_FC	DAVINCI_DM365_FC	2767
-msm8x55_surf		MACH_MSM8X55_SURF	MSM8X55_SURF		2768
-msm8x55_ffa		MACH_MSM8X55_FFA	MSM8X55_FFA		2769
-esl_vamana		MACH_ESL_VAMANA		ESL_VAMANA		2770
-sbc35			MACH_SBC35		SBC35			2771
-mpx6446			MACH_MPX6446		MPX6446			2772
-oreo_controller		MACH_OREO_CONTROLLER	OREO_CONTROLLER		2773
-kopin_models		MACH_KOPIN_MODELS	KOPIN_MODELS		2774
-ttc_vision2		MACH_TTC_VISION2	TTC_VISION2		2775
-cns3420vb		MACH_CNS3420VB		CNS3420VB		2776
-lpc_evo			MACH_LPC2		LPC2			2777
-olympus			MACH_OLYMPUS		OLYMPUS			2778
-vortex			MACH_VORTEX		VORTEX			2779
-s5pc200			MACH_S5PC200		S5PC200			2780
-ecucore_9263		MACH_ECUCORE_9263	ECUCORE_9263		2781
-smdkc200		MACH_SMDKC200		SMDKC200		2782
-emsiso_sx27		MACH_EMSISO_SX27	EMSISO_SX27		2783
-apx_som9g45_ek		MACH_APX_SOM9G45_EK	APX_SOM9G45_EK		2784
-songshan		MACH_SONGSHAN		SONGSHAN		2785
-tianshan		MACH_TIANSHAN		TIANSHAN		2786
-vpx500			MACH_VPX500		VPX500			2787
-am3517sam		MACH_AM3517SAM		AM3517SAM		2788
-skat91_sim508		MACH_SKAT91_SIM508	SKAT91_SIM508		2789
-skat91_s3e		MACH_SKAT91_S3E		SKAT91_S3E		2790
-omap4_panda		MACH_OMAP4_PANDA	OMAP4_PANDA		2791
-df7220			MACH_DF7220		DF7220			2792
-nemini			MACH_NEMINI		NEMINI			2793
-t8200			MACH_T8200		T8200			2794
-apf51			MACH_APF51		APF51			2795
-dr_rc_unit		MACH_DR_RC_UNIT		DR_RC_UNIT		2796
-bordeaux		MACH_BORDEAUX		BORDEAUX		2797
-catania_b		MACH_CATANIA_B		CATANIA_B		2798
-mx51_ocean		MACH_MX51_OCEAN		MX51_OCEAN		2799
-ti8168evm		MACH_TI8168EVM		TI8168EVM		2800
-neocoreomap		MACH_NEOCOREOMAP	NEOCOREOMAP		2801
-withings_wbp		MACH_WITHINGS_WBP	WITHINGS_WBP		2802
-dbps			MACH_DBPS		DBPS			2803
-pcbfp0001		MACH_PCBFP0001		PCBFP0001		2805
-speedy			MACH_SPEEDY		SPEEDY			2806
-chrysaor		MACH_CHRYSAOR		CHRYSAOR		2807
-tango			MACH_TANGO		TANGO			2808
-synology_dsx11		MACH_SYNOLOGY_DSX11	SYNOLOGY_DSX11		2809
-hanlin_v3ext		MACH_HANLIN_V3EXT	HANLIN_V3EXT		2810
-hanlin_v5		MACH_HANLIN_V5		HANLIN_V5		2811
-hanlin_v3plus		MACH_HANLIN_V3PLUS	HANLIN_V3PLUS		2812
-iriver_story		MACH_IRIVER_STORY	IRIVER_STORY		2813
-irex_iliad		MACH_IREX_ILIAD		IREX_ILIAD		2814
-irex_dr1000		MACH_IREX_DR1000	IREX_DR1000		2815
-teton_bga		MACH_TETON_BGA		TETON_BGA		2816
-snapper9g45		MACH_SNAPPER9G45	SNAPPER9G45		2817
-tam3517			MACH_TAM3517		TAM3517			2818
-pdc100			MACH_PDC100		PDC100			2819
-eukrea_cpuimx25sd	MACH_EUKREA_CPUIMX25SD	EUKREA_CPUIMX25SD	2820
-eukrea_cpuimx35sd	MACH_EUKREA_CPUIMX35SD	EUKREA_CPUIMX35SD	2821
-eukrea_cpuimx51sd	MACH_EUKREA_CPUIMX51SD	EUKREA_CPUIMX51SD	2822
-eukrea_cpuimx51		MACH_EUKREA_CPUIMX51	EUKREA_CPUIMX51		2823
-p565			MACH_P565		P565			2824
-acer_a4			MACH_ACER_A4		ACER_A4			2825
-davinci_dm368_bip	MACH_DAVINCI_DM368_BIP	DAVINCI_DM368_BIP	2826
-eshare			MACH_ESHARE		ESHARE			2827
-wlbargn			MACH_WLBARGN		WLBARGN			2829
-bm170			MACH_BM170		BM170			2830
-netspace_mini_v2	MACH_NETSPACE_MINI_V2	NETSPACE_MINI_V2	2831
-netspace_plug_v2	MACH_NETSPACE_PLUG_V2	NETSPACE_PLUG_V2	2832
-siemens_l1		MACH_SIEMENS_L1		SIEMENS_L1		2833
-elv_lcu1		MACH_ELV_LCU1		ELV_LCU1		2834
-mcu1			MACH_MCU1		MCU1			2835
-omap3_tao3530		MACH_OMAP3_TAO3530	OMAP3_TAO3530		2836
-omap3_pcutouch		MACH_OMAP3_PCUTOUCH	OMAP3_PCUTOUCH		2837
-smdkc210		MACH_SMDKC210		SMDKC210		2838
-omap3_braillo		MACH_OMAP3_BRAILLO	OMAP3_BRAILLO		2839
-spyplug			MACH_SPYPLUG		SPYPLUG			2840
-ginger			MACH_GINGER		GINGER			2841
-tny_t3530		MACH_TNY_T3530		TNY_T3530		2842
-pcaal1			MACH_PCAAL1		PCAAL1			2843
-spade			MACH_SPADE		SPADE			2844
-mxc25_topaz		MACH_MXC25_TOPAZ	MXC25_TOPAZ		2845
-t5325			MACH_T5325		T5325			2846
-gw2361			MACH_GW2361		GW2361			2847
-elog			MACH_ELOG		ELOG			2848
-income			MACH_INCOME		INCOME			2849
-bcm589x			MACH_BCM589X		BCM589X			2850
-etna			MACH_ETNA		ETNA			2851
-hawks			MACH_HAWKS		HAWKS			2852
-meson			MACH_MESON		MESON			2853
-xsbase255		MACH_XSBASE255		XSBASE255		2854
-pvm2030			MACH_PVM2030		PVM2030			2855
-mioa502			MACH_MIOA502		MIOA502			2856
-vvbox_sdorig2		MACH_VVBOX_SDORIG2	VVBOX_SDORIG2		2857
-vvbox_sdlite2		MACH_VVBOX_SDLITE2	VVBOX_SDLITE2		2858
-vvbox_sdpro4		MACH_VVBOX_SDPRO4	VVBOX_SDPRO4		2859
-htc_spv_m700		MACH_HTC_SPV_M700	HTC_SPV_M700		2860
-mx257sx			MACH_MX257SX		MX257SX			2861
-goni			MACH_GONI		GONI			2862
-msm8x55_svlte_ffa	MACH_MSM8X55_SVLTE_FFA	MSM8X55_SVLTE_FFA	2863
-msm8x55_svlte_surf	MACH_MSM8X55_SVLTE_SURF	MSM8X55_SVLTE_SURF	2864
-quickstep		MACH_QUICKSTEP		QUICKSTEP		2865
-dmw96			MACH_DMW96		DMW96			2866
-hammerhead		MACH_HAMMERHEAD		HAMMERHEAD		2867
-trident			MACH_TRIDENT		TRIDENT			2868
-lightning		MACH_LIGHTNING		LIGHTNING		2869
-iconnect		MACH_ICONNECT		ICONNECT		2870
-autobot			MACH_AUTOBOT		AUTOBOT			2871
-coconut			MACH_COCONUT		COCONUT			2872
-durian			MACH_DURIAN		DURIAN			2873
-cayenne			MACH_CAYENNE		CAYENNE			2874
-fuji			MACH_FUJI		FUJI			2875
-synology_6282		MACH_SYNOLOGY_6282	SYNOLOGY_6282		2876
-em1sy			MACH_EM1SY		EM1SY			2877
-m502			MACH_M502		M502			2878
-matrix518		MACH_MATRIX518		MATRIX518		2879
-tiny_gurnard		MACH_TINY_GURNARD	TINY_GURNARD		2880
-spear1310		MACH_SPEAR1310		SPEAR1310		2881
-bv07			MACH_BV07		BV07			2882
-mxt_td61		MACH_MXT_TD61		MXT_TD61		2883
-openrd_ultimate		MACH_OPENRD_ULTIMATE	OPENRD_ULTIMATE		2884
-devixp			MACH_DEVIXP		DEVIXP			2885
-miccpt			MACH_MICCPT		MICCPT			2886
-mic256			MACH_MIC256		MIC256			2887
-as1167			MACH_AS1167		AS1167			2888
-omap3_ibiza		MACH_OMAP3_IBIZA	OMAP3_IBIZA		2889
-u5500			MACH_U5500		U5500			2890
-davinci_picto		MACH_DAVINCI_PICTO	DAVINCI_PICTO		2891
-mecha			MACH_MECHA		MECHA			2892
-bubba3			MACH_BUBBA3		BUBBA3			2893
-pupitre			MACH_PUPITRE		PUPITRE			2894
-tegra_vogue		MACH_TEGRA_VOGUE	TEGRA_VOGUE		2896
-tegra_e1165		MACH_TEGRA_E1165	TEGRA_E1165		2897
-simplenet		MACH_SIMPLENET		SIMPLENET		2898
-ec4350tbm		MACH_EC4350TBM		EC4350TBM		2899
-pec_tc			MACH_PEC_TC		PEC_TC			2900
-pec_hc2			MACH_PEC_HC2		PEC_HC2			2901
-esl_mobilis_a		MACH_ESL_MOBILIS_A	ESL_MOBILIS_A		2902
-esl_mobilis_b		MACH_ESL_MOBILIS_B	ESL_MOBILIS_B		2903
-esl_wave_a		MACH_ESL_WAVE_A		ESL_WAVE_A		2904
-esl_wave_b		MACH_ESL_WAVE_B		ESL_WAVE_B		2905
-unisense_mmm		MACH_UNISENSE_MMM	UNISENSE_MMM		2906
-blueshark		MACH_BLUESHARK		BLUESHARK		2907
-e10			MACH_E10		E10			2908
-app3k_robin		MACH_APP3K_ROBIN	APP3K_ROBIN		2909
-pov15hd			MACH_POV15HD		POV15HD			2910
-stella			MACH_STELLA		STELLA			2911
-linkstation_lschl	MACH_LINKSTATION_LSCHL	LINKSTATION_LSCHL	2913
-netwalker		MACH_NETWALKER		NETWALKER		2914
-acsx106			MACH_ACSX106		ACSX106			2915
-atlas5_c1		MACH_ATLAS5_C1		ATLAS5_C1		2916
-nsb3ast			MACH_NSB3AST		NSB3AST			2917
-gnet_slc		MACH_GNET_SLC		GNET_SLC		2918
-af4000			MACH_AF4000		AF4000			2919
-ark9431			MACH_ARK9431		ARK9431			2920
-fs_s5pc100		MACH_FS_S5PC100		FS_S5PC100		2921
-omap3505nova8		MACH_OMAP3505NOVA8	OMAP3505NOVA8		2922
-omap3621_edp1		MACH_OMAP3621_EDP1	OMAP3621_EDP1		2923
-oratisaes		MACH_ORATISAES		ORATISAES		2924
-smdkv310		MACH_SMDKV310		SMDKV310		2925
-siemens_l0		MACH_SIEMENS_L0		SIEMENS_L0		2926
-ventana			MACH_VENTANA		VENTANA			2927
-wm8505_7in_netbook	MACH_WM8505_7IN_NETBOOK	WM8505_7IN_NETBOOK	2928
-ec4350sdb		MACH_EC4350SDB		EC4350SDB		2929
-mimas			MACH_MIMAS		MIMAS			2930
-titan			MACH_TITAN		TITAN			2931
-craneboard		MACH_CRANEBOARD		CRANEBOARD		2932
-es2440			MACH_ES2440		ES2440			2933
-najay_a9263		MACH_NAJAY_A9263	NAJAY_A9263		2934
-htctornado		MACH_HTCTORNADO		HTCTORNADO		2935
-dimm_mx257		MACH_DIMM_MX257		DIMM_MX257		2936
-jigen301		MACH_JIGEN		JIGEN			2937
-smdk6450		MACH_SMDK6450		SMDK6450		2938
-meno_qng		MACH_MENO_QNG		MENO_QNG		2939
-ns2416			MACH_NS2416		NS2416			2940
-rpc353			MACH_RPC353		RPC353			2941
-tq6410			MACH_TQ6410		TQ6410			2942
-sky6410			MACH_SKY6410		SKY6410			2943
-dynasty			MACH_DYNASTY		DYNASTY			2944
-vivo			MACH_VIVO		VIVO			2945
-bury_bl7582		MACH_BURY_BL7582	BURY_BL7582		2946
-bury_bps5270		MACH_BURY_BPS5270	BURY_BPS5270		2947
-basi			MACH_BASI		BASI			2948
-tn200			MACH_TN200		TN200			2949
-c2mmi			MACH_C2MMI		C2MMI			2950
-meson_6236m		MACH_MESON_6236M	MESON_6236M		2951
-meson_8626m		MACH_MESON_8626M	MESON_8626M		2952
-tube			MACH_TUBE		TUBE			2953
-messina			MACH_MESSINA		MESSINA			2954
-mx50_arm2		MACH_MX50_ARM2		MX50_ARM2		2955
-cetus9263		MACH_CETUS9263		CETUS9263		2956
-brownstone		MACH_BROWNSTONE		BROWNSTONE		2957
-vmx25			MACH_VMX25		VMX25			2958
-vmx51			MACH_VMX51		VMX51			2959
-abacus			MACH_ABACUS		ABACUS			2960
-cm4745			MACH_CM4745		CM4745			2961
-oratislink		MACH_ORATISLINK		ORATISLINK		2962
-davinci_dm365_dvr	MACH_DAVINCI_DM365_DVR	DAVINCI_DM365_DVR	2963
-netviz			MACH_NETVIZ		NETVIZ			2964
-flexibity		MACH_FLEXIBITY		FLEXIBITY		2965
-wlan_computer		MACH_WLAN_COMPUTER	WLAN_COMPUTER		2966
-lpc24xx			MACH_LPC24XX		LPC24XX			2967
-spica			MACH_SPICA		SPICA			2968
-gpsdisplay		MACH_GPSDISPLAY		GPSDISPLAY		2969
-bipnet			MACH_BIPNET		BIPNET			2970
-overo_ctu_inertial	MACH_OVERO_CTU_INERTIAL	OVERO_CTU_INERTIAL	2971
-davinci_dm355_mmm	MACH_DAVINCI_DM355_MMM	DAVINCI_DM355_MMM	2972
-pc9260_v2		MACH_PC9260_V2		PC9260_V2		2973
-ptx7545			MACH_PTX7545		PTX7545			2974
-tm_efdc			MACH_TM_EFDC		TM_EFDC			2975
-omap3_waldo1		MACH_OMAP3_WALDO1	OMAP3_WALDO1		2977
-flyer			MACH_FLYER		FLYER			2978
-tornado3240		MACH_TORNADO3240	TORNADO3240		2979
-soli_01			MACH_SOLI_01		SOLI_01			2980
-omapl138_europalc	MACH_OMAPL138_EUROPALC	OMAPL138_EUROPALC	2981
-helios_v1		MACH_HELIOS_V1		HELIOS_V1		2982
-netspace_lite_v2	MACH_NETSPACE_LITE_V2	NETSPACE_LITE_V2	2983
-ssc			MACH_SSC		SSC			2984
-premierwave_en		MACH_PREMIERWAVE_EN	PREMIERWAVE_EN		2985
-wasabi			MACH_WASABI		WASABI			2986
-mx50_rdp		MACH_MX50_RDP		MX50_RDP		2988
-universal_c210		MACH_UNIVERSAL_C210	UNIVERSAL_C210		2989
-real6410		MACH_REAL6410		REAL6410		2990
-spx_sakura		MACH_SPX_SAKURA		SPX_SAKURA		2991
-ij3k_2440		MACH_IJ3K_2440		IJ3K_2440		2992
-omap3_bc10		MACH_OMAP3_BC10		OMAP3_BC10		2993
-thebe			MACH_THEBE		THEBE			2994
-rv082			MACH_RV082		RV082			2995
-armlguest		MACH_ARMLGUEST		ARMLGUEST		2996
-tjinc1000		MACH_TJINC1000		TJINC1000		2997
-dockstar		MACH_DOCKSTAR		DOCKSTAR		2998
-ax8008			MACH_AX8008		AX8008			2999
-gnet_sgce		MACH_GNET_SGCE		GNET_SGCE		3000
-pxwnas_500_1000		MACH_PXWNAS_500_1000	PXWNAS_500_1000		3001
-ea20			MACH_EA20		EA20			3002
-awm2			MACH_AWM2		AWM2			3003
-ti8148evm		MACH_TI8148EVM		TI8148EVM		3004
-seaboard		MACH_SEABOARD		SEABOARD		3005
-linkstation_chlv2	MACH_LINKSTATION_CHLV2	LINKSTATION_CHLV2	3006
-tera_pro2_rack		MACH_TERA_PRO2_RACK	TERA_PRO2_RACK		3007
-rubys			MACH_RUBYS		RUBYS			3008
-aquarius		MACH_AQUARIUS		AQUARIUS		3009
-mx53_ard		MACH_MX53_ARD		MX53_ARD		3010
-mx53_smd		MACH_MX53_SMD		MX53_SMD		3011
-lswxl			MACH_LSWXL		LSWXL			3012
-dove_avng_v3		MACH_DOVE_AVNG_V3	DOVE_AVNG_V3		3013
-sdi_ess_9263		MACH_SDI_ESS_9263	SDI_ESS_9263		3014
-jocpu550		MACH_JOCPU550		JOCPU550		3015
-msm8x60_rumi3		MACH_MSM8X60_RUMI3	MSM8X60_RUMI3		3016
-msm8x60_ffa		MACH_MSM8X60_FFA	MSM8X60_FFA		3017
-yanomami		MACH_YANOMAMI		YANOMAMI		3018
-gta04			MACH_GTA04		GTA04			3019
-cm_a510			MACH_CM_A510		CM_A510			3020
-omap3_rfs200		MACH_OMAP3_RFS200	OMAP3_RFS200		3021
-kx33xx			MACH_KX33XX		KX33XX			3022
-ptx7510			MACH_PTX7510		PTX7510			3023
-top9000			MACH_TOP9000		TOP9000			3024
-teenote			MACH_TEENOTE		TEENOTE			3025
-ts3			MACH_TS3		TS3			3026
-a0			MACH_A0			A0			3027
-fsm9xxx_surf		MACH_FSM9XXX_SURF	FSM9XXX_SURF		3028
-fsm9xxx_ffa		MACH_FSM9XXX_FFA	FSM9XXX_FFA		3029
-frrhwcdma60w		MACH_FRRHWCDMA60W	FRRHWCDMA60W		3030
-remus			MACH_REMUS		REMUS			3031
-at91cap7xdk		MACH_AT91CAP7XDK	AT91CAP7XDK		3032
-at91cap7stk		MACH_AT91CAP7STK	AT91CAP7STK		3033
-kt_sbc_sam9_1		MACH_KT_SBC_SAM9_1	KT_SBC_SAM9_1		3034
-armada_xp_db		MACH_ARMADA_XP_DB	ARMADA_XP_DB		3036
-spdm			MACH_SPDM		SPDM			3037
-gtib			MACH_GTIB		GTIB			3038
-dgm3240			MACH_DGM3240		DGM3240			3039
-iv_atlas_i_lpe		MACH_ATLAS_I_LPE	ATLAS_I_LPE		3040
-htcmega			MACH_HTCMEGA		HTCMEGA			3041
-tricorder		MACH_TRICORDER		TRICORDER		3042
-tx28			MACH_TX28		TX28			3043
-bstbrd			MACH_BSTBRD		BSTBRD			3044
-pwb3090			MACH_PWB3090		PWB3090			3045
-idea6410		MACH_IDEA6410		IDEA6410		3046
-qbc9263			MACH_QBC9263		QBC9263			3047
-borabora		MACH_BORABORA		BORABORA		3048
-valdez			MACH_VALDEZ		VALDEZ			3049
-ls9g20			MACH_LS9G20		LS9G20			3050
-mios_v1			MACH_MIOS_V1		MIOS_V1			3051
-s5pc110_crespo		MACH_S5PC110_CRESPO	S5PC110_CRESPO		3052
-controltek9g20		MACH_CONTROLTEK9G20	CONTROLTEK9G20		3053
-tin307			MACH_TIN307		TIN307			3054
-tin510			MACH_TIN510		TIN510			3055
-ep3505			MACH_EP3517		EP3517			3056
-bluecheese		MACH_BLUECHEESE		BLUECHEESE		3057
-tem3x30			MACH_TEM3X30		TEM3X30			3058
-harvest_desoto		MACH_HARVEST_DESOTO	HARVEST_DESOTO		3059
-msm8x60_qrdc		MACH_MSM8X60_QRDC	MSM8X60_QRDC		3060
-spear900		MACH_SPEAR900		SPEAR900		3061
-pcontrol_g20		MACH_PCONTROL_G20	PCONTROL_G20		3062
-rdstor			MACH_RDSTOR		RDSTOR			3063
-usdloader		MACH_USDLOADER		USDLOADER		3064
-tsoploader		MACH_TSOPLOADER		TSOPLOADER		3065
-kronos			MACH_KRONOS		KRONOS			3066
-ffcore			MACH_FFCORE		FFCORE			3067
-mone			MACH_MONE		MONE			3068
-unit2s			MACH_UNIT2S		UNIT2S			3069
-acer_a5			MACH_ACER_A5		ACER_A5			3070
-etherpro_isp		MACH_ETHERPRO_ISP	ETHERPRO_ISP		3071
-stretchs7000		MACH_STRETCHS7000	STRETCHS7000		3072
-p87_smartsim		MACH_P87_SMARTSIM	P87_SMARTSIM		3073
-tulip			MACH_TULIP		TULIP			3074
-sunflower		MACH_SUNFLOWER		SUNFLOWER		3075
-rib			MACH_RIB		RIB			3076
-clod			MACH_CLOD		CLOD			3077
-rump			MACH_RUMP		RUMP			3078
-tenderloin		MACH_TENDERLOIN		TENDERLOIN		3079
-shortloin		MACH_SHORTLOIN		SHORTLOIN		3080
-antares			MACH_ANTARES		ANTARES			3082
-wb40n			MACH_WB40N		WB40N			3083
-herring			MACH_HERRING		HERRING			3084
-naxy400			MACH_NAXY400		NAXY400			3085
-naxy1200		MACH_NAXY1200		NAXY1200		3086
-vpr200			MACH_VPR200		VPR200			3087
-bug20			MACH_BUG20		BUG20			3088
-goflexnet		MACH_GOFLEXNET		GOFLEXNET		3089
-torbreck		MACH_TORBRECK		TORBRECK		3090
-saarb_mg1		MACH_SAARB_MG1		SAARB_MG1		3091
-callisto		MACH_CALLISTO		CALLISTO		3092
-multhsu			MACH_MULTHSU		MULTHSU			3093
-saluda			MACH_SALUDA		SALUDA			3094
-pemp_omap3_apollo	MACH_PEMP_OMAP3_APOLLO	PEMP_OMAP3_APOLLO	3095
-vc0718			MACH_VC0718		VC0718			3096
-mvblx			MACH_MVBLX		MVBLX			3097
-inhand_apeiron		MACH_INHAND_APEIRON	INHAND_APEIRON		3098
-inhand_fury		MACH_INHAND_FURY	INHAND_FURY		3099
-inhand_siren		MACH_INHAND_SIREN	INHAND_SIREN		3100
-hdnvp			MACH_HDNVP		HDNVP			3101
-softwinner		MACH_SOFTWINNER		SOFTWINNER		3102
-prima2_evb		MACH_PRIMA2_EVB		PRIMA2_EVB		3103
-nas6210			MACH_NAS6210		NAS6210			3104
-unisdev			MACH_UNISDEV		UNISDEV			3105
-sbca11			MACH_SBCA11		SBCA11			3106
-saga			MACH_SAGA		SAGA			3107
-ns_k330			MACH_NS_K330		NS_K330			3108
-tanna			MACH_TANNA		TANNA			3109
-imate8502		MACH_IMATE8502		IMATE8502		3110
-aspen			MACH_ASPEN		ASPEN			3111
-daintree_cwac		MACH_DAINTREE_CWAC	DAINTREE_CWAC		3112
-zmx25			MACH_ZMX25		ZMX25			3113
-maple1			MACH_MAPLE1		MAPLE1			3114
-qsd8x72_surf		MACH_QSD8X72_SURF	QSD8X72_SURF		3115
-qsd8x72_ffa		MACH_QSD8X72_FFA	QSD8X72_FFA		3116
-abilene			MACH_ABILENE		ABILENE			3117
-eigen_ttr		MACH_EIGEN_TTR		EIGEN_TTR		3118
-iomega_ix2_200		MACH_IOMEGA_IX2_200	IOMEGA_IX2_200		3119
-coretec_vcx7400		MACH_CORETEC_VCX7400	CORETEC_VCX7400		3120
-santiago		MACH_SANTIAGO		SANTIAGO		3121
-mx257sol		MACH_MX257SOL		MX257SOL		3122
-strasbourg		MACH_STRASBOURG		STRASBOURG		3123
-msm8x60_fluid		MACH_MSM8X60_FLUID	MSM8X60_FLUID		3124
-smartqv5		MACH_SMARTQV5		SMARTQV5		3125
-smartqv3		MACH_SMARTQV3		SMARTQV3		3126
-smartqv7		MACH_SMARTQV7		SMARTQV7		3127
-paz00			MACH_PAZ00		PAZ00			3128
-acmenetusfoxg20		MACH_ACMENETUSFOXG20	ACMENETUSFOXG20		3129
-fwbd_0404		MACH_FWBD_0404		FWBD_0404		3131
-hdgu			MACH_HDGU		HDGU			3132
-pyramid			MACH_PYRAMID		PYRAMID			3133
-epiphan			MACH_EPIPHAN		EPIPHAN			3134
-omap_bender		MACH_OMAP_BENDER	OMAP_BENDER		3135
-gurnard			MACH_GURNARD		GURNARD			3136
-gtl_it5100		MACH_GTL_IT5100		GTL_IT5100		3137
-bcm2708			MACH_BCM2708		BCM2708			3138
-mx51_ggc		MACH_MX51_GGC		MX51_GGC		3139
-sharespace		MACH_SHARESPACE		SHARESPACE		3140
-haba_knx_explorer	MACH_HABA_KNX_EXPLORER	HABA_KNX_EXPLORER	3141
-simtec_kirkmod		MACH_SIMTEC_KIRKMOD	SIMTEC_KIRKMOD		3142
-crux			MACH_CRUX		CRUX			3143
-mx51_bravo		MACH_MX51_BRAVO		MX51_BRAVO		3144
-charon			MACH_CHARON		CHARON			3145
-picocom3		MACH_PICOCOM3		PICOCOM3		3146
-picocom4		MACH_PICOCOM4		PICOCOM4		3147
-serrano			MACH_SERRANO		SERRANO			3148
-doubleshot		MACH_DOUBLESHOT		DOUBLESHOT		3149
-evsy			MACH_EVSY		EVSY			3150
-huashan			MACH_HUASHAN		HUASHAN			3151
-lausanne		MACH_LAUSANNE		LAUSANNE		3152
-emerald			MACH_EMERALD		EMERALD			3153
-tqma35			MACH_TQMA35		TQMA35			3154
-marvel			MACH_MARVEL		MARVEL			3155
-manuae			MACH_MANUAE		MANUAE			3156
-chacha			MACH_CHACHA		CHACHA			3157
-lemon			MACH_LEMON		LEMON			3158
-csc			MACH_CSC		CSC			3159
-gira_knxip_router	MACH_GIRA_KNXIP_ROUTER	GIRA_KNXIP_ROUTER	3160
-t20			MACH_T20		T20			3161
-hdmini			MACH_HDMINI		HDMINI			3162
-sciphone_g2		MACH_SCIPHONE_G2	SCIPHONE_G2		3163
-express			MACH_EXPRESS		EXPRESS			3164
-express_kt		MACH_EXPRESS_KT		EXPRESS_KT		3165
-maximasp		MACH_MAXIMASP		MAXIMASP		3166
-nitrogen_imx51		MACH_NITROGEN_IMX51	NITROGEN_IMX51		3167
-nitrogen_imx53		MACH_NITROGEN_IMX53	NITROGEN_IMX53		3168
-sunfire			MACH_SUNFIRE		SUNFIRE			3169
-arowana			MACH_AROWANA		AROWANA			3170
-tegra_daytona		MACH_TEGRA_DAYTONA	TEGRA_DAYTONA		3171
-tegra_swordfish		MACH_TEGRA_SWORDFISH	TEGRA_SWORDFISH		3172
-edison			MACH_EDISON		EDISON			3173
-svp8500v1		MACH_SVP8500V1		SVP8500V1		3174
-svp8500v2		MACH_SVP8500V2		SVP8500V2		3175
-svp5500			MACH_SVP5500		SVP5500			3176
-b5500			MACH_B5500		B5500			3177
-s5500			MACH_S5500		S5500			3178
-icon			MACH_ICON		ICON			3179
-elephant		MACH_ELEPHANT		ELEPHANT		3180
-shooter			MACH_SHOOTER		SHOOTER			3182
-spade_lte		MACH_SPADE_LTE		SPADE_LTE		3183
-philhwani		MACH_PHILHWANI		PHILHWANI		3184
-gsncomm			MACH_GSNCOMM		GSNCOMM			3185
-strasbourg_a2		MACH_STRASBOURG_A2	STRASBOURG_A2		3186
-mmm			MACH_MMM		MMM			3187
-davinci_dm365_bv	MACH_DAVINCI_DM365_BV	DAVINCI_DM365_BV	3188
-ag5evm			MACH_AG5EVM		AG5EVM			3189
-sc575plc		MACH_SC575PLC		SC575PLC		3190
-sc575hmi		MACH_SC575IPC		SC575IPC		3191
-omap3_tdm3730		MACH_OMAP3_TDM3730	OMAP3_TDM3730		3192
-top9000_eval		MACH_TOP9000_EVAL	TOP9000_EVAL		3194
-top9000_su		MACH_TOP9000_SU		TOP9000_SU		3195
-utm300			MACH_UTM300		UTM300			3196
-tsunagi			MACH_TSUNAGI		TSUNAGI			3197
-ts75xx			MACH_TS75XX		TS75XX			3198
-ts47xx			MACH_TS47XX		TS47XX			3200
-da850_k5		MACH_DA850_K5		DA850_K5		3201
-ax502			MACH_AX502		AX502			3202
-igep0032		MACH_IGEP0032		IGEP0032		3203
-antero			MACH_ANTERO		ANTERO			3204
-synergy			MACH_SYNERGY		SYNERGY			3205
-ics_if_voip		MACH_ICS_IF_VOIP	ICS_IF_VOIP		3206
-wlf_cragg_6410		MACH_WLF_CRAGG_6410	WLF_CRAGG_6410		3207
-punica			MACH_PUNICA		PUNICA			3208
-trimslice		MACH_TRIMSLICE		TRIMSLICE		3209
-mx27_wmultra		MACH_MX27_WMULTRA	MX27_WMULTRA		3210
-mackerel		MACH_MACKEREL		MACKEREL		3211
-fa9x27			MACH_FA9X27		FA9X27			3213
-ns2816tb		MACH_NS2816TB		NS2816TB		3214
-ns2816_ntpad		MACH_NS2816_NTPAD	NS2816_NTPAD		3215
-ns2816_ntnb		MACH_NS2816_NTNB	NS2816_NTNB		3216
-kaen			MACH_KAEN		KAEN			3217
-nv1000			MACH_NV1000		NV1000			3218
-nuc950ts		MACH_NUC950TS		NUC950TS		3219
-nokia_rm680		MACH_NOKIA_RM680	NOKIA_RM680		3220
-ast2200			MACH_AST2200		AST2200			3221
-lead			MACH_LEAD		LEAD			3222
-unino1			MACH_UNINO1		UNINO1			3223
-greeco			MACH_GREECO		GREECO			3224
-verdi			MACH_VERDI		VERDI			3225
-dm6446_adbox		MACH_DM6446_ADBOX	DM6446_ADBOX		3226
-quad_salsa		MACH_QUAD_SALSA		QUAD_SALSA		3227
-abb_gma_1_1		MACH_ABB_GMA_1_1	ABB_GMA_1_1		3228
-svcid			MACH_SVCID		SVCID			3229
-msm8960_sim		MACH_MSM8960_SIM	MSM8960_SIM		3230
-msm8960_rumi3		MACH_MSM8960_RUMI3	MSM8960_RUMI3		3231
-icon_g			MACH_ICON_G		ICON_G			3232
-mb3			MACH_MB3		MB3			3233
-gsia18s			MACH_GSIA18S		GSIA18S			3234
-pivicc			MACH_PIVICC		PIVICC			3235
-pcm048			MACH_PCM048		PCM048			3236
-dds			MACH_DDS		DDS			3237
-chalten_xa1		MACH_CHALTEN_XA1	CHALTEN_XA1		3238
-ts48xx			MACH_TS48XX		TS48XX			3239
-tonga2_tfttimer		MACH_TONGA2_TFTTIMER	TONGA2_TFTTIMER		3240
-whistler		MACH_WHISTLER		WHISTLER		3241
-asl_phoenix		MACH_ASL_PHOENIX	ASL_PHOENIX		3242
-at91sam9263otlite	MACH_AT91SAM9263OTLITE	AT91SAM9263OTLITE	3243
-ddplug			MACH_DDPLUG		DDPLUG			3244
-d2plug			MACH_D2PLUG		D2PLUG			3245
-kzm9d			MACH_KZM9D		KZM9D			3246
-verdi_lte		MACH_VERDI_LTE		VERDI_LTE		3247
-nanozoom		MACH_NANOZOOM		NANOZOOM		3248
-dm3730_som_lv		MACH_DM3730_SOM_LV	DM3730_SOM_LV		3249
-dm3730_torpedo		MACH_DM3730_TORPEDO	DM3730_TORPEDO		3250
-anchovy			MACH_ANCHOVY		ANCHOVY			3251
-re2rev20		MACH_RE2REV20		RE2REV20		3253
-re2rev21		MACH_RE2REV21		RE2REV21		3254
-cns21xx			MACH_CNS21XX		CNS21XX			3255
-rider			MACH_RIDER		RIDER			3257
-nsk330			MACH_NSK330		NSK330			3258
-cns2133evb		MACH_CNS2133EVB		CNS2133EVB		3259
-z3_816x_mod		MACH_Z3_816X_MOD	Z3_816X_MOD		3260
-z3_814x_mod		MACH_Z3_814X_MOD	Z3_814X_MOD		3261
-beect			MACH_BEECT		BEECT			3262
-dma_thunderbug		MACH_DMA_THUNDERBUG	DMA_THUNDERBUG		3263
-omn_at91sam9g20		MACH_OMN_AT91SAM9G20	OMN_AT91SAM9G20		3264
-mx25_e2s_uc		MACH_MX25_E2S_UC	MX25_E2S_UC		3265
-mione			MACH_MIONE		MIONE			3266
-top9000_tcu		MACH_TOP9000_TCU	TOP9000_TCU		3267
-top9000_bsl		MACH_TOP9000_BSL	TOP9000_BSL		3268
-kingdom			MACH_KINGDOM		KINGDOM			3269
-armadillo460		MACH_ARMADILLO460	ARMADILLO460		3270
-lq2			MACH_LQ2		LQ2			3271
-sweda_tms2		MACH_SWEDA_TMS2		SWEDA_TMS2		3272
-mx53_loco		MACH_MX53_LOCO		MX53_LOCO		3273
-acer_a8			MACH_ACER_A8		ACER_A8			3275
-acer_gauguin		MACH_ACER_GAUGUIN	ACER_GAUGUIN		3276
-guppy			MACH_GUPPY		GUPPY			3277
-mx61_ard		MACH_MX61_ARD		MX61_ARD		3278
-tx53			MACH_TX53		TX53			3279
-omapl138_case_a3	MACH_OMAPL138_CASE_A3	OMAPL138_CASE_A3	3280
-uemd			MACH_UEMD		UEMD			3281
-ccwmx51mut		MACH_CCWMX51MUT		CCWMX51MUT		3282
-rockhopper		MACH_ROCKHOPPER		ROCKHOPPER		3283
-encore			MACH_ENCORE		ENCORE			3284
-hkdkc100		MACH_HKDKC100		HKDKC100		3285
-ts42xx			MACH_TS42XX		TS42XX			3286
-aebl			MACH_AEBL		AEBL			3287
-wario			MACH_WARIO		WARIO			3288
-gfs_spm			MACH_GFS_SPM		GFS_SPM			3289
-cm_t3730		MACH_CM_T3730		CM_T3730		3290
-isc3			MACH_ISC3		ISC3			3291
-rascal			MACH_RASCAL		RASCAL			3292
-hrefv60			MACH_HREFV60		HREFV60			3293
-tpt_2_0			MACH_TPT_2_0		TPT_2_0			3294
-pydtd			MACH_PYRAMID_TD		PYRAMID_TD		3295
-splendor		MACH_SPLENDOR		SPLENDOR		3296
-guf_vincell		MACH_GUF_PLANET		GUF_PLANET		3297
-msm8x60_qt		MACH_MSM8X60_QT		MSM8X60_QT		3298
-htc_hd_mini		MACH_HTC_HD_MINI	HTC_HD_MINI		3299
-athene			MACH_ATHENE		ATHENE			3300
-deep_r_ek_1		MACH_DEEP_R_EK_1	DEEP_R_EK_1		3301
-vivow_ct		MACH_VIVOW_CT		VIVOW_CT		3302
-nery_1000		MACH_NERY_1000		NERY_1000		3303
-rfl109145_ssrv		MACH_RFL109145_SSRV	RFL109145_SSRV		3304
-nmh			MACH_NMH		NMH			3305
-wn802t			MACH_WN802T		WN802T			3306
-dragonet		MACH_DRAGONET		DRAGONET		3307
-geneva_b4		MACH_GENEVA_B		GENEVA_B		3308
-at91sam9263desk16l	MACH_AT91SAM9263DESK16L	AT91SAM9263DESK16L	3309
-bcmhana_sv		MACH_BCMHANA_SV		BCMHANA_SV		3310
-bcmhana_tablet		MACH_BCMHANA_TABLET	BCMHANA_TABLET		3311
-koi			MACH_KOI		KOI			3312
-ts4800			MACH_TS4800		TS4800			3313
-tqma9263		MACH_TQMA9263		TQMA9263		3314
-holiday			MACH_HOLIDAY		HOLIDAY			3315
-dma_6410		MACH_DMA6410		DMA6410			3316
-pcats_overlay		MACH_PCATS_OVERLAY	PCATS_OVERLAY		3317
-hwgw6410		MACH_HWGW6410		HWGW6410		3318
-shenzhou		MACH_SHENZHOU		SHENZHOU		3319
-cwme9210		MACH_CWME9210		CWME9210		3320
-cwme9210js		MACH_CWME9210JS		CWME9210JS		3321
-pgs_v1			MACH_PGS_SITARA		PGS_SITARA		3322
-colibri_t20		MACH_COLIBRI_TEGRA2	COLIBRI_TEGRA2		3323
-w21			MACH_W21		W21			3324
-polysat1		MACH_POLYSAT1		POLYSAT1		3325
-dataway			MACH_DATAWAY		DATAWAY			3326
-cobral138		MACH_COBRAL138		COBRAL138		3327
-roverpcs8		MACH_ROVERPCS8		ROVERPCS8		3328
-marvelc			MACH_MARVELC		MARVELC			3329
-navefihid		MACH_NAVEFIHID		NAVEFIHID		3330
-dm365_cv100		MACH_DM365_CV100	DM365_CV100		3331
-able			MACH_ABLE		ABLE			3332
-legacy			MACH_LEGACY		LEGACY			3333
-icong			MACH_ICONG		ICONG			3334
-rover_g8		MACH_ROVER_G8		ROVER_G8		3335
-t5388p			MACH_T5388P		T5388P			3336
-dingo			MACH_DINGO		DINGO			3337
-goflexhome		MACH_GOFLEXHOME		GOFLEXHOME		3338
-lanreadyfn511		MACH_LANREADYFN511	LANREADYFN511		3340
-omap3_baia		MACH_OMAP3_BAIA		OMAP3_BAIA		3341
-omap3smartdisplay	MACH_OMAP3SMARTDISPLAY	OMAP3SMARTDISPLAY	3342
-xilinx			MACH_XILINX		XILINX			3343
-a2f			MACH_A2F		A2F			3344
-sky25			MACH_SKY25		SKY25			3345
-ccmx53			MACH_CCMX53		CCMX53			3346
-ccmx53js		MACH_CCMX53JS		CCMX53JS		3347
-ccwmx53			MACH_CCWMX53		CCWMX53			3348
-ccwmx53js		MACH_CCWMX53JS		CCWMX53JS		3349
-frisms			MACH_FRISMS		FRISMS			3350
-msm7x27a_ffa		MACH_MSM7X27A_FFA	MSM7X27A_FFA		3351
-msm7x27a_surf		MACH_MSM7X27A_SURF	MSM7X27A_SURF		3352
-msm7x27a_rumi3		MACH_MSM7X27A_RUMI3	MSM7X27A_RUMI3		3353
-dimmsam9g20		MACH_DIMMSAM9G20	DIMMSAM9G20		3354
-dimm_imx28		MACH_DIMM_IMX28		DIMM_IMX28		3355
-amk_a4			MACH_AMK_A4		AMK_A4			3356
-gnet_sgme		MACH_GNET_SGME		GNET_SGME		3357
-shooter_u		MACH_SHOOTER_U		SHOOTER_U		3358
-vmx53			MACH_VMX53		VMX53			3359
-rhino			MACH_RHINO		RHINO			3360
-armlex4210		MACH_ARMLEX4210		ARMLEX4210		3361
-swarcoextmodem		MACH_SWARCOEXTMODEM	SWARCOEXTMODEM		3362
-snowball		MACH_SNOWBALL		SNOWBALL		3363
-pcm049			MACH_PCM049		PCM049			3364
-vigor			MACH_VIGOR		VIGOR			3365
-oslo_amundsen		MACH_OSLO_AMUNDSEN	OSLO_AMUNDSEN		3366
-gsl_diamond		MACH_GSL_DIAMOND	GSL_DIAMOND		3367
-cv2201			MACH_CV2201		CV2201			3368
-cv2202			MACH_CV2202		CV2202			3369
-cv2203			MACH_CV2203		CV2203			3370
-vit_ibox		MACH_VIT_IBOX		VIT_IBOX		3371
-dm6441_esp		MACH_DM6441_ESP		DM6441_ESP		3372
-at91sam9x5ek		MACH_AT91SAM9X5EK	AT91SAM9X5EK		3373
-libra			MACH_LIBRA		LIBRA			3374
-easycrrh		MACH_EASYCRRH		EASYCRRH		3375
-tripel			MACH_TRIPEL		TRIPEL			3376
-endian_mini		MACH_ENDIAN_MINI	ENDIAN_MINI		3377
-xilinx_ep107		MACH_XILINX_EP107	XILINX_EP107		3378
-nuri			MACH_NURI		NURI			3379
-janus			MACH_JANUS		JANUS			3380
-ddnas			MACH_DDNAS		DDNAS			3381
-tag			MACH_TAG		TAG			3382
-tagw			MACH_TAGW		TAGW			3383
-nitrogen_vm_imx51	MACH_NITROGEN_VM_IMX51	NITROGEN_VM_IMX51	3384
-viprinet		MACH_VIPRINET		VIPRINET		3385
-bockw			MACH_BOCKW		BOCKW			3386
-eva2000			MACH_EVA2000		EVA2000			3387
-steelyard		MACH_STEELYARD		STEELYARD		3388
-ea2468devkit		MACH_LPC2468OEM		LPC2468OEM		3389
-sdh001			MACH_MACH_SDH001	MACH_SDH001		3390
-fe2478mblox		MACH_LPC2478MICROBLOX	LPC2478MICROBLOX	3391
-nsslsboard		MACH_NSSLSBOARD		NSSLSBOARD		3392
-geneva_b5		MACH_GENEVA_B5		GENEVA_B5		3393
-spear1340		MACH_SPEAR1340		SPEAR1340		3394
-rexmas			MACH_REXMAS		REXMAS			3395
-msm8960_cdp		MACH_MSM8960_CDP	MSM8960_CDP		3396
-msm8960_mtp		MACH_MSM8960_MDP	MSM8960_MDP		3397
-msm8960_fluid		MACH_MSM8960_FLUID	MSM8960_FLUID		3398
-msm8960_apq		MACH_MSM8960_APQ	MSM8960_APQ		3399
-helios_v2		MACH_HELIOS_V2		HELIOS_V2		3400
-mif10p			MACH_MIF10P		MIF10P			3401
-iam28			MACH_IAM28		IAM28			3402
-picasso			MACH_PICASSO		PICASSO			3403
-mr301a			MACH_MR301A		MR301A			3404
-notle			MACH_NOTLE		NOTLE			3405
-eelx2			MACH_EELX2		EELX2			3406
-moon			MACH_MOON		MOON			3407
-ruby			MACH_RUBY		RUBY			3408
-goldengate		MACH_GOLDENGATE		GOLDENGATE		3409
-ctbu_gen2		MACH_CTBU_GEN2		CTBU_GEN2		3410
-kmp_am17_01		MACH_KMP_AM17_01	KMP_AM17_01		3411
-wtplug			MACH_WTPLUG		WTPLUG			3412
-mx27su2			MACH_MX27SU2		MX27SU2			3413
-nb31			MACH_NB31		NB31			3414
-hjsdu			MACH_HJSDU		HJSDU			3415
-td3_rev1		MACH_TD3_REV1		TD3_REV1		3416
-eag_ci4000		MACH_EAG_CI4000		EAG_CI4000		3417
-net5big_nand_v2		MACH_NET5BIG_NAND_V2	NET5BIG_NAND_V2		3418
-cpx2			MACH_CPX2		CPX2			3419
-net2big_nand_v2		MACH_NET2BIG_NAND_V2	NET2BIG_NAND_V2		3420
-ecuv5			MACH_ECUV5		ECUV5			3421
-hsgx6d			MACH_HSGX6D		HSGX6D			3422
-dawad7			MACH_DAWAD7		DAWAD7			3423
-sam9repeater		MACH_SAM9REPEATER	SAM9REPEATER		3424
-gt_i5700		MACH_GT_I5700		GT_I5700		3425
-ctera_plug_c2		MACH_CTERA_PLUG_C2	CTERA_PLUG_C2		3426
-marvelct		MACH_MARVELCT		MARVELCT		3427
-ag11005			MACH_AG11005		AG11005			3428
-omap_tabletblaze	MACH_OMAP_BLAZE		OMAP_BLAZE		3429
-vangogh			MACH_VANGOGH		VANGOGH			3430
-matrix505		MACH_MATRIX505		MATRIX505		3431
-oce_nigma		MACH_OCE_NIGMA		OCE_NIGMA		3432
-t55			MACH_T55		T55			3433
-bio3k			MACH_BIO3K		BIO3K			3434
-expressct		MACH_EXPRESSCT		EXPRESSCT		3435
-cardhu			MACH_CARDHU		CARDHU			3436
-aruba			MACH_ARUBA		ARUBA			3437
-bonaire			MACH_BONAIRE		BONAIRE			3438
-nuc700evb		MACH_NUC700EVB		NUC700EVB		3439
-nuc710evb		MACH_NUC710EVB		NUC710EVB		3440
-nuc740evb		MACH_NUC740EVB		NUC740EVB		3441
-nuc745evb		MACH_NUC745EVB		NUC745EVB		3442
-transcede		MACH_TRANSCEDE		TRANSCEDE		3443
-mora			MACH_MORA		MORA			3444
-nda_evm			MACH_NDA_EVM		NDA_EVM			3445
-timu			MACH_TIMU		TIMU			3446
-expressh		MACH_EXPRESSH		EXPRESSH		3447
-veridis_a300		MACH_VERIDIS_A300	VERIDIS_A300		3448
-dm368_leopard		MACH_DM368_LEOPARD	DM368_LEOPARD		3449
-omap_mcop		MACH_OMAP_MCOP		OMAP_MCOP		3450
-tritip			MACH_TRITIP		TRITIP			3451
-sm1k			MACH_SM1K		SM1K			3452
-monch			MACH_MONCH		MONCH			3453
-curacao			MACH_CURACAO		CURACAO			3454
-origen			MACH_ORIGEN		ORIGEN			3455
-epc10			MACH_EPC10		EPC10			3456
-sgh_i740		MACH_SGH_I740		SGH_I740		3457
-tuna			MACH_TUNA		TUNA			3458
-mx51_tulip		MACH_MX51_TULIP		MX51_TULIP		3459
-mx51_aster7		MACH_MX51_ASTER7	MX51_ASTER7		3460
-acro37xbrd		MACH_ACRO37XBRD		ACRO37XBRD		3461
-elke			MACH_ELKE		ELKE			3462
-sbc6000x		MACH_SBC6000X		SBC6000X		3463
-r1801e			MACH_R1801E		R1801E			3464
-h1600			MACH_H1600		H1600			3465
-mini210			MACH_MINI210		MINI210			3466
-mini8168		MACH_MINI8168		MINI8168		3467
-pc7308			MACH_PC7308		PC7308			3468
-ge863_pro3_evk		MACH_GE863		GE863			3469
-kmm2m01			MACH_KMM2M01		KMM2M01			3470
-mx51erebus		MACH_MX51EREBUS		MX51EREBUS		3471
-wm8650refboard		MACH_WM8650REFBOARD	WM8650REFBOARD		3472
-tuxrail			MACH_TUXRAIL		TUXRAIL			3473
-arthur			MACH_ARTHUR		ARTHUR			3474
-doorboy			MACH_DOORBOY		DOORBOY			3475
-xarina			MACH_XARINA		XARINA			3476
-roverx7			MACH_ROVERX7		ROVERX7			3477
-sdvr			MACH_SDVR		SDVR			3478
-acer_maya		MACH_ACER_MAYA		ACER_MAYA		3479
-pico			MACH_PICO		PICO			3480
-cwmx233			MACH_CWMX233		CWMX233			3481
-cwam1808		MACH_CWAM1808		CWAM1808		3482
-cwdm365			MACH_CWDM365		CWDM365			3483
-mx51_moray		MACH_MX51_MORAY		MX51_MORAY		3484
-thales_cbc		MACH_THALES_CBC		THALES_CBC		3485
-bluepoint		MACH_BLUEPOINT		BLUEPOINT		3486
-dir665			MACH_DIR665		DIR665			3487
-acmerover1		MACH_ACMEROVER1		ACMEROVER1		3488
-shooter_ct		MACH_SHOOTER_CT		SHOOTER_CT		3489
-bliss			MACH_BLISS		BLISS			3490
-blissc			MACH_BLISSC		BLISSC			3491
-thales_adc		MACH_THALES_ADC		THALES_ADC		3492
-ubisys_p9d_evp		MACH_UBISYS_P9D_EVP	UBISYS_P9D_EVP		3493
-atdgp318		MACH_ATDGP318		ATDGP318		3494
-dma210u			MACH_DMA210U		DMA210U			3495
-em_t3			MACH_EM_T3		EM_T3			3496
-htx3250			MACH_HTX3250		HTX3250			3497
-g50			MACH_G50		G50			3498
-eco5			MACH_ECO5		ECO5			3499
-wintergrasp		MACH_WINTERGRASP	WINTERGRASP		3500
-puro			MACH_PURO		PURO			3501
-shooter_k		MACH_SHOOTER_K		SHOOTER_K		3502
-nspire			MACH_NSPIRE		NSPIRE			3503
-mickxx			MACH_MICKXX		MICKXX			3504
-lxmb			MACH_LXMB		LXMB			3505
-tmdxscbp6618x		MACH_TMDXSCBP6616X	TMDXSCBP6616X		3506
-adam			MACH_ADAM		ADAM			3507
-b1004			MACH_B1004		B1004			3508
-oboea			MACH_OBOEA		OBOEA			3509
-a1015			MACH_A1015		A1015			3510
-robin_vbdt30		MACH_ROBIN_VBDT30	ROBIN_VBDT30		3511
-tegra_enterprise	MACH_TEGRA_ENTERPRISE	TEGRA_ENTERPRISE	3512
-rfl108200_mk10		MACH_RFL108200_MK10	RFL108200_MK10		3513
-rfl108300_mk16		MACH_RFL108300_MK16	RFL108300_MK16		3514
-rover_v7		MACH_ROVER_V7		ROVER_V7		3515
-miphone			MACH_MIPHONE		MIPHONE			3516
-femtobts		MACH_FEMTOBTS		FEMTOBTS		3517
-monopoli		MACH_MONOPOLI		MONOPOLI		3518
-boss			MACH_BOSS		BOSS			3519
-davinci_dm368_vtam	MACH_DAVINCI_DM368_VTAM	DAVINCI_DM368_VTAM	3520
-clcon			MACH_CLCON		CLCON			3521
-nokia_rm696		MACH_NOKIA_RM696	NOKIA_RM696		3522
-tahiti			MACH_TAHITI		TAHITI			3523
-fighter			MACH_FIGHTER		FIGHTER			3524
-sgh_i710		MACH_SGH_I710		SGH_I710		3525
-integreproscb		MACH_INTEGREPROSCB	INTEGREPROSCB		3526
-monza			MACH_MONZA		MONZA			3527
-calimain		MACH_CALIMAIN		CALIMAIN		3528
-mx6q_sabreauto		MACH_MX6Q_SABREAUTO	MX6Q_SABREAUTO		3529
-gma01x			MACH_GMA01X		GMA01X			3530
-sbc51			MACH_SBC51		SBC51			3531
-fit			MACH_FIT		FIT			3532
-steelhead		MACH_STEELHEAD		STEELHEAD		3533
-panther			MACH_PANTHER		PANTHER			3534
-msm8960_liquid		MACH_MSM8960_LIQUID	MSM8960_LIQUID		3535
-lexikonct		MACH_LEXIKONCT		LEXIKONCT		3536
-ns2816_stb		MACH_NS2816_STB		NS2816_STB		3537
-sei_mm2_lpc3250		MACH_SEI_MM2_LPC3250	SEI_MM2_LPC3250		3538
-cmimx53			MACH_CMIMX53		CMIMX53			3539
-sandwich		MACH_SANDWICH		SANDWICH		3540
-chief			MACH_CHIEF		CHIEF			3541
-pogo_e02		MACH_POGO_E02		POGO_E02		3542
-mikrap_x168		MACH_MIKRAP_X168	MIKRAP_X168		3543
-htcmozart		MACH_HTCMOZART		HTCMOZART		3544
-htcgold			MACH_HTCGOLD		HTCGOLD			3545
-mt72xx			MACH_MT72XX		MT72XX			3546
-mx51_ivy		MACH_MX51_IVY		MX51_IVY		3547
-mx51_lvd		MACH_MX51_LVD		MX51_LVD		3548
-omap3_wiser2		MACH_OMAP3_WISER2	OMAP3_WISER2		3549
-dreamplug		MACH_DREAMPLUG		DREAMPLUG		3550
-cobas_c_111		MACH_COBAS_C_111	COBAS_C_111		3551
-cobas_u_411		MACH_COBAS_U_411	COBAS_U_411		3552
-hssd			MACH_HSSD		HSSD			3553
-iom35x			MACH_IOM35X		IOM35X			3554
-psom_omap		MACH_PSOM_OMAP		PSOM_OMAP		3555
-iphone_2g		MACH_IPHONE_2G		IPHONE_2G		3556
-iphone_3g		MACH_IPHONE_3G		IPHONE_3G		3557
-ipod_touch_1g		MACH_IPOD_TOUCH_1G	IPOD_TOUCH_1G		3558
-pharos_tpc		MACH_PHAROS_TPC		PHAROS_TPC		3559
-mx53_hydra		MACH_MX53_HYDRA		MX53_HYDRA		3560
-ns2816_dev_board	MACH_NS2816_DEV_BOARD	NS2816_DEV_BOARD	3561
-iphone_3gs		MACH_IPHONE_3GS		IPHONE_3GS		3562
-iphone_4		MACH_IPHONE_4		IPHONE_4		3563
-ipod_touch_4g		MACH_IPOD_TOUCH_4G	IPOD_TOUCH_4G		3564
-dragon_e1100		MACH_DRAGON_E1100	DRAGON_E1100		3565
-topside			MACH_TOPSIDE		TOPSIDE			3566
-irisiii			MACH_IRISIII		IRISIII			3567
-deto_macarm9		MACH_DETO_MACARM9	DETO_MACARM9		3568
-eti_d1			MACH_ETI_D1		ETI_D1			3569
-som3530sdk		MACH_SOM3530SDK		SOM3530SDK		3570
-oc_engine		MACH_OC_ENGINE		OC_ENGINE		3571
-apq8064_sim		MACH_APQ8064_SIM	APQ8064_SIM		3572
-alps			MACH_ALPS		ALPS			3575
-tny_t3730		MACH_TNY_T3730		TNY_T3730		3576
-geryon_nfe		MACH_GERYON_NFE		GERYON_NFE		3577
-ns2816_ref_board	MACH_NS2816_REF_BOARD	NS2816_REF_BOARD	3578
-silverstone		MACH_SILVERSTONE	SILVERSTONE		3579
-mtt2440			MACH_MTT2440		MTT2440			3580
-ynicdb			MACH_YNICDB		YNICDB			3581
-bct			MACH_BCT		BCT			3582
-tuscan			MACH_TUSCAN		TUSCAN			3583
-xbt_sam9g45		MACH_XBT_SAM9G45	XBT_SAM9G45		3584
-enbw_cmc		MACH_ENBW_CMC		ENBW_CMC		3585
-msm8x60_dragon		MACH_APQ8060_DRAGON	APQ8060_DRAGON		3586
-ch104mx257		MACH_CH104MX257		CH104MX257		3587
-openpri			MACH_OPENPRI		OPENPRI			3588
-am335xevm		MACH_AM335XEVM		AM335XEVM		3589
-picodmb			MACH_PICODMB		PICODMB			3590
-waluigi			MACH_WALUIGI		WALUIGI			3591
-punicag7		MACH_PUNICAG7		PUNICAG7		3592
-ipad_1g			MACH_IPAD_1G		IPAD_1G			3593
-appletv_2g		MACH_APPLETV_2G		APPLETV_2G		3594
-mach_ecog45		MACH_MACH_ECOG45	MACH_ECOG45		3595
-ait_cam_enc_4xx		MACH_AIT_CAM_ENC_4XX	AIT_CAM_ENC_4XX		3596
-runnymede		MACH_RUNNYMEDE		RUNNYMEDE		3597
-play			MACH_PLAY		PLAY			3598
-hw90260			MACH_HW90260		HW90260			3599
-tagh			MACH_TAGH		TAGH			3600
-filbert			MACH_FILBERT		FILBERT			3601
-getinge_netcomv3	MACH_GETINGE_NETCOMV3	GETINGE_NETCOMV3	3602
-cw20			MACH_CW20		CW20			3603
-cinema			MACH_CINEMA		CINEMA			3604
-cinema_tea		MACH_CINEMA_TEA		CINEMA_TEA		3605
-cinema_coffee		MACH_CINEMA_COFFEE	CINEMA_COFFEE		3606
-cinema_juice		MACH_CINEMA_JUICE	CINEMA_JUICE		3607
-linux_pad		MACH_THEPAD		THEPAD			3608
-mx53_mirage2		MACH_MX53_MIRAGE2	MX53_MIRAGE2		3609
-mx53_efikasb		MACH_MX53_EFIKASB	MX53_EFIKASB		3610
-stm_b2000		MACH_STM_B2000		STM_B2000		3612
-m28evk			MACH_M28EVK		M28EVK			3613
-pda			MACH_PDA		PDA			3614
-meraki_mr58		MACH_MERAKI_MR58	MERAKI_MR58		3615
-kota2			MACH_KOTA2		KOTA2			3616
-letcool			MACH_LETCOOL		LETCOOL			3617
-mx27iat			MACH_MX27IAT		MX27IAT			3618
-apollo_td		MACH_APOLLO_TD		APOLLO_TD		3619
-arena			MACH_ARENA		ARENA			3620
-gsngateway		MACH_GSNGATEWAY		GSNGATEWAY		3621
-lf2000			MACH_LF2000		LF2000			3622
-bonito			MACH_BONITO		BONITO			3623
-asymptote		MACH_ASYMPTOTE		ASYMPTOTE		3624
-bst2brd			MACH_BST2BRD		BST2BRD			3625
-tx335s			MACH_TX335S		TX335S			3626
-pelco_tesla		MACH_PELCO_TESLA	PELCO_TESLA		3627
-rrhtestplat		MACH_RRHTESTPLAT	RRHTESTPLAT		3628
-vidtonic_pro		MACH_VIDTONIC_PRO	VIDTONIC_PRO		3629
-pl_apollo		MACH_PL_APOLLO		PL_APOLLO		3630
-pl_phoenix		MACH_PL_PHOENIX		PL_PHOENIX		3631
-m28cu3			MACH_M28CU3		M28CU3			3632
-vvbox_hd		MACH_VVBOX_HD		VVBOX_HD		3633
-coreware_sam9260_	MACH_COREWARE_SAM9260_	COREWARE_SAM9260_	3634
-marmaduke		MACH_MARMADUKE		MARMADUKE		3635
-amg_xlcore_camera	MACH_AMG_XLCORE_CAMERA	AMG_XLCORE_CAMERA	3636
-omap3_egf		MACH_OMAP3_EGF		OMAP3_EGF		3637
-smdk4212		MACH_SMDK4212		SMDK4212		3638
-dnp9200			MACH_DNP9200		DNP9200			3639
-tf101			MACH_TF101		TF101			3640
-omap3silvio		MACH_OMAP3SILVIO	OMAP3SILVIO		3641
-picasso2		MACH_PICASSO2		PICASSO2		3642
-vangogh2		MACH_VANGOGH2		VANGOGH2		3643
-olpc_xo_1_75		MACH_OLPC_XO_1_75	OLPC_XO_1_75		3644
-gx400			MACH_GX400		GX400			3645
-gs300			MACH_GS300		GS300			3646
-acer_a9			MACH_ACER_A9		ACER_A9			3647
-vivow_evm		MACH_VIVOW_EVM		VIVOW_EVM		3648
-veloce_cxq		MACH_VELOCE_CXQ		VELOCE_CXQ		3649
-veloce_cxm		MACH_VELOCE_CXM		VELOCE_CXM		3650
-p1852			MACH_P1852		P1852			3651
-naxy100			MACH_NAXY100		NAXY100			3652
-taishan			MACH_TAISHAN		TAISHAN			3653
-touchlink		MACH_TOUCHLINK		TOUCHLINK		3654
-stm32f103ze		MACH_STM32F103ZE	STM32F103ZE		3655
-mcx			MACH_MCX		MCX			3656
-stm_nmhdk_fli7610	MACH_STM_NMHDK_FLI7610	STM_NMHDK_FLI7610	3657
-top28x			MACH_TOP28X		TOP28X			3658
-okl4vp_microvisor	MACH_OKL4VP_MICROVISOR	OKL4VP_MICROVISOR	3659
-pop			MACH_POP		POP			3660
-layer			MACH_LAYER		LAYER			3661
-trondheim		MACH_TRONDHEIM		TRONDHEIM		3662
-eva			MACH_EVA		EVA			3663
-trust_taurus		MACH_TRUST_TAURUS	TRUST_TAURUS		3664
-ns2816_huashan		MACH_NS2816_HUASHAN	NS2816_HUASHAN		3665
-ns2816_yangcheng	MACH_NS2816_YANGCHENG	NS2816_YANGCHENG	3666
-p852			MACH_P852		P852			3667
-flea3			MACH_FLEA3		FLEA3			3668
-bowfin			MACH_BOWFIN		BOWFIN			3669
-mv88de3100		MACH_MV88DE3100		MV88DE3100		3670
-pia_am35x		MACH_PIA_AM35X		PIA_AM35X		3671
-cedar			MACH_CEDAR		CEDAR			3672
-picasso_e		MACH_PICASSO_E		PICASSO_E		3673
-samsung_e60		MACH_SAMSUNG_E60	SAMSUNG_E60		3674
-msm9615_cdp		MACH_MDM9615		MDM9615			3675
-sdvr_mini		MACH_SDVR_MINI		SDVR_MINI		3676
-omap3_ij3k		MACH_OMAP3_IJ3K		OMAP3_IJ3K		3677
-modasmc1		MACH_MODASMC1		MODASMC1		3678
-apq8064_rumi3		MACH_APQ8064_RUMI3	APQ8064_RUMI3		3679
-matrix506		MACH_MATRIX506		MATRIX506		3680
-msm9615_mtp		MACH_MSM9615_MTP	MSM9615_MTP		3681
-dm36x_spawndc		MACH_DM36X_SPAWNDC	DM36X_SPAWNDC		3682
-sff792			MACH_SFF792		SFF792			3683
-am335xiaevm		MACH_AM335XIAEVM	AM335XIAEVM		3684
-g3c2440			MACH_G3C2440		G3C2440			3685
-tion270			MACH_TION270		TION270			3686
-w22q7arm02		MACH_W22Q7ARM02		W22Q7ARM02		3687
-omap_cat		MACH_OMAP_CAT		OMAP_CAT		3688
-at91sam9n12ek		MACH_AT91SAM9N12EK	AT91SAM9N12EK		3689
-morrison		MACH_MORRISON		MORRISON		3690
-svdu			MACH_SVDU		SVDU			3691
-lpp01			MACH_LPP01		LPP01			3692
-ubc283			MACH_UBC283		UBC283			3693
-zeppelin		MACH_ZEPPELIN		ZEPPELIN		3694
-motus			MACH_MOTUS		MOTUS			3695
-neomainboard		MACH_NEOMAINBOARD	NEOMAINBOARD		3696
-devkit3250		MACH_DEVKIT3250		DEVKIT3250		3697
-devkit7000		MACH_DEVKIT7000		DEVKIT7000		3698
-fmc_uic			MACH_FMC_UIC		FMC_UIC			3699
-fmc_dcm			MACH_FMC_DCM		FMC_DCM			3700
-batwm			MACH_BATWM		BATWM			3701
-atlas6cb		MACH_ATLAS6CB		ATLAS6CB		3702
-quattro_f		MACH_QUATTROF		QUATTROF		3703
-quattro_u		MACH_QUATTROU		QUATTROU		3704
-blue			MACH_BLUE		BLUE			3705
-colorado		MACH_COLORADO		COLORADO		3706
-popc			MACH_POPC		POPC			3707
-promwad_jade		MACH_PROMWAD_JADE	PROMWAD_JADE		3708
-amp			MACH_AMP		AMP			3709
-gnet_amp		MACH_GNET_AMP		GNET_AMP		3710
-toques			MACH_TOQUES		TOQUES			3711
-apx4devkit		MACH_APX4DEVKIT		APX4DEVKIT		3712
-dct_storm		MACH_DCT_STORM		DCT_STORM		3713
-dm8168z3		MACH_Z3			Z3			3714
-owl			MACH_OWL		OWL			3715
-cogent_csb1741		MACH_COGENT_CSB1741	COGENT_CSB1741		3716
-omap3_kiko		MACH_OMAP3		OMAP3			3717
-adillustra610		MACH_ADILLUSTRA610	ADILLUSTRA610		3718
-ecafe_na04		MACH_ECAFE_NA04		ECAFE_NA04		3719
-popct			MACH_POPCT		POPCT			3720
-omap3_helena		MACH_OMAP3_HELENA	OMAP3_HELENA		3721
-ach			MACH_ACH		ACH			3722
-module_dtb		MACH_MODULE_DTB		MODULE_DTB		3723
-ratebox			MACH_RACKBOX		RACKBOX			3724
-oslo_elisabeth		MACH_OSLO_ELISABETH	OSLO_ELISABETH		3725
-tt01			MACH_TT01		TT01			3726
-msm8930_cdp		MACH_MSM8930_CDP	MSM8930_CDP		3727
-msm8930_mtp		MACH_MSM8930_MTP	MSM8930_MTP		3728
-msm8930_fluid		MACH_MSM8930_FLUID	MSM8930_FLUID		3729
-ltu11			MACH_LTU11		LTU11			3730
-am1808_spawnco		MACH_AM1808_SPAWNCO	AM1808_SPAWNCO		3731
-flx6410			MACH_FLX6410		FLX6410			3732
-mx6q_qsb		MACH_MX6Q_QSB		MX6Q_QSB		3733
-mx53_plt424		MACH_MX53_PLT424	MX53_PLT424		3734
-jasmine			MACH_JASMINE		JASMINE			3735
-l138_owlboard_plus	MACH_L138_OWLBOARD_PLUS	L138_OWLBOARD_PLUS	3736
-wr21			MACH_WR21		WR21			3737
-peaboy			MACH_PEABOY		PEABOY			3739
-mx28_plato		MACH_MX28_PLATO		MX28_PLATO		3740
-kacom2			MACH_KACOM2		KACOM2			3741
-slco			MACH_SLCO		SLCO			3742
-imx51pico		MACH_IMX51PICO		IMX51PICO		3743
-glink1			MACH_GLINK1		GLINK1			3744
-diamond			MACH_DIAMOND		DIAMOND			3745
-d9000			MACH_D9000		D9000			3746
-w5300e01		MACH_W5300E01		W5300E01		3747
-im6000			MACH_IM6000		IM6000			3748
-mx51_fred51		MACH_MX51_FRED51	MX51_FRED51		3749
-stm32f2			MACH_STM32F2		STM32F2			3750
-ville			MACH_VILLE		VILLE			3751
-ptip_murnau		MACH_PTIP_MURNAU	PTIP_MURNAU		3752
-ptip_classic		MACH_PTIP_CLASSIC	PTIP_CLASSIC		3753
-mx53grb			MACH_MX53GRB		MX53GRB			3754
-gagarin			MACH_GAGARIN		GAGARIN			3755
-msm7627a_qrd1		MACH_MSM7X27A_QRD1	MSM7X27A_QRD1		3756
-nas2big			MACH_NAS2BIG		NAS2BIG			3757
-superfemto		MACH_SUPERFEMTO		SUPERFEMTO		3758
-teufel			MACH_TEUFEL		TEUFEL			3759
-dinara			MACH_DINARA		DINARA			3760
-vanquish		MACH_VANQUISH		VANQUISH		3761
-zipabox1		MACH_ZIPABOX1		ZIPABOX1		3762
-u9540			MACH_U9540		U9540			3763
-jet			MACH_JET		JET			3764
-smdk4412		MACH_SMDK4412		SMDK4412		3765
-elite			MACH_ELITE		ELITE			3766
-spear320_hmi		MACH_SPEAR320_HMI	SPEAR320_HMI		3767
-ontario			MACH_ONTARIO		ONTARIO			3768
-mx6q_sabrelite		MACH_MX6Q_SABRELITE	MX6Q_SABRELITE		3769
-vc200			MACH_VC200		VC200			3770
-msm7625a_ffa		MACH_MSM7625A_FFA	MSM7625A_FFA		3771
-msm7625a_surf		MACH_MSM7625A_SURF	MSM7625A_SURF		3772
-benthossbp		MACH_BENTHOSSBP		BENTHOSSBP		3773
-smdk5210		MACH_SMDK5210		SMDK5210		3774
-empq2300		MACH_EMPQ2300		EMPQ2300		3775
-minipos			MACH_MINIPOS		MINIPOS			3776
-omap5_sevm		MACH_OMAP5_SEVM		OMAP5_SEVM		3777
-shelter			MACH_SHELTER		SHELTER			3778
-omap3_devkit8500	MACH_OMAP3_DEVKIT8500	OMAP3_DEVKIT8500	3779
-edgetd			MACH_EDGETD		EDGETD			3780
-copperyard		MACH_COPPERYARD		COPPERYARD		3781
-edge_test		MACH_EDGE		EDGE			3782
-edge_u			MACH_EDGE_U		EDGE_U			3783
-edge_td			MACH_EDGE_TD		EDGE_TD			3784
-wdss			MACH_WDSS		WDSS			3785
-dl_pb25			MACH_DL_PB25		DL_PB25			3786
-dss11			MACH_DSS11		DSS11			3787
-cpa			MACH_CPA		CPA			3788
-aptp2000		MACH_APTP2000		APTP2000		3789
-marzen			MACH_MARZEN		MARZEN			3790
-st_turbine		MACH_ST_TURBINE		ST_TURBINE		3791
-gtl_it3300		MACH_GTL_IT3300		GTL_IT3300		3792
-mx6_mule		MACH_MX6_MULE		MX6_MULE		3793
-v7pxa_dt		MACH_V7PXA_DT		V7PXA_DT		3794
-v7mmp_dt		MACH_V7MMP_DT		V7MMP_DT		3795
-dragon7			MACH_DRAGON7		DRAGON7			3796
-krome			MACH_KROME		KROME			3797
-oratisdante		MACH_ORATISDANTE	ORATISDANTE		3798
-fathom			MACH_FATHOM		FATHOM			3799
-dns325			MACH_DNS325		DNS325			3800
-sarnen			MACH_SARNEN		SARNEN			3801
-ubisys_g1		MACH_UBISYS_G1		UBISYS_G1		3802
-mx53_pf1		MACH_MX53_PF1		MX53_PF1		3803
-asanti			MACH_ASANTI		ASANTI			3804
-volta			MACH_VOLTA		VOLTA			3805
-potenza			MACH_S5P6450		S5P6450			3806
-knight			MACH_KNIGHT		KNIGHT			3807
-beaglebone		MACH_BEAGLEBONE		BEAGLEBONE		3808
-becker			MACH_BECKER		BECKER			3809
-fc360			MACH_FC360		FC360			3810
-pmi2_xls		MACH_PMI2_XLS		PMI2_XLS		3811
-taranto			MACH_TARANTO		TARANTO			3812
-plutux			MACH_PLUTUX		PLUTUX			3813
-ipmp_medcom		MACH_IPMP_MEDCOM	IPMP_MEDCOM		3814
-absolut			MACH_ABSOLUT		ABSOLUT			3815
-awpb3			MACH_AWPB3		AWPB3			3816
-nfp32xx_dt		MACH_NFP32XX_DT		NFP32XX_DT		3817
-dl_pb53			MACH_DL_PB53		DL_PB53			3818
-acu_ii			MACH_ACU_II		ACU_II			3819
-avalon			MACH_AVALON		AVALON			3820
-sphinx			MACH_SPHINX		SPHINX			3821
-titan_t			MACH_TITAN_T		TITAN_T			3822
-harvest_boris		MACH_HARVEST_BORIS	HARVEST_BORIS		3823
-mach_msm7x30_m3s	MACH_MACH_MSM7X30_M3S	MACH_MSM7X30_M3S	3824
-smdk5250		MACH_SMDK5250		SMDK5250		3825
-imxt_lite		MACH_IMXT_LITE		IMXT_LITE		3826
-imxt_std		MACH_IMXT_STD		IMXT_STD		3827
-imxt_log		MACH_IMXT_LOG		IMXT_LOG		3828
-imxt_nav		MACH_IMXT_NAV		IMXT_NAV		3829
-imxt_full		MACH_IMXT_FULL		IMXT_FULL		3830
-ag09015			MACH_AG09015		AG09015			3831
-am3517_mt_ventoux	MACH_AM3517_MT_VENTOUX	AM3517_MT_VENTOUX	3832
-dp1arm9			MACH_DP1ARM9		DP1ARM9			3833
-picasso_m		MACH_PICASSO_M		PICASSO_M		3834
-video_gadget		MACH_VIDEO_GADGET	VIDEO_GADGET		3835
-mtt_om3x		MACH_MTT_OM3X		MTT_OM3X		3836
-mx6q_arm2		MACH_MX6Q_ARM2		MX6Q_ARM2		3837
-picosam9g45		MACH_PICOSAM9G45	PICOSAM9G45		3838
-vpm_dm365		MACH_VPM_DM365		VPM_DM365		3839
-bonfire			MACH_BONFIRE		BONFIRE			3840
-mt2p2d			MACH_MT2P2D		MT2P2D			3841
-sigpda01		MACH_SIGPDA01		SIGPDA01		3842
-cn27			MACH_CN27		CN27			3843
-mx25_cwtap		MACH_MX25_CWTAP		MX25_CWTAP		3844
-apf28			MACH_APF28		APF28			3845
-pelco_maxwell		MACH_PELCO_MAXWELL	PELCO_MAXWELL		3846
-ge_phoenix		MACH_GE_PHOENIX		GE_PHOENIX		3847
-empc_a500		MACH_EMPC_A500		EMPC_A500		3848
-ims_arm9		MACH_IMS_ARM9		IMS_ARM9		3849
-mini2416		MACH_MINI2416		MINI2416		3850
-mini2450		MACH_MINI2450		MINI2450		3851
-mini310			MACH_MINI310		MINI310			3852
-spear_hurricane		MACH_SPEAR_HURRICANE	SPEAR_HURRICANE		3853
-mt7208			MACH_MT7208		MT7208			3854
-lpc178x			MACH_LPC178X		LPC178X			3855
-farleys			MACH_FARLEYS		FARLEYS			3856
-efm32gg_dk3750		MACH_EFM32GG_DK3750	EFM32GG_DK3750		3857
-zeus_board		MACH_ZEUS_BOARD		ZEUS_BOARD		3858
-cc51			MACH_CC51		CC51			3859
-cottoncandy		MACH_FXI_C210		FXI_C210		3860
-msm8627_cdp		MACH_MSM8627_CDP	MSM8627_CDP		3861
-msm8627_mtp		MACH_MSM8627_MTP	MSM8627_MTP		3862
-armadillo800eva		MACH_ARMADILLO800EVA	ARMADILLO800EVA		3863
-primou			MACH_PRIMOU		PRIMOU			3864
-primoc			MACH_PRIMOC		PRIMOC			3865
-primoct			MACH_PRIMOCT		PRIMOCT			3866
-a9500			MACH_A9500		A9500			3867
-pue_td			MACH_PULSE_TD		PULSE_TD		3868
-pluto			MACH_PLUTO		PLUTO			3869
-acfx100			MACH_ACFX100		ACFX100			3870
-msm8625_rumi3		MACH_MSM8625_RUMI3	MSM8625_RUMI3		3871
-valente			MACH_VALENTE		VALENTE			3872
-crfs_rfeye		MACH_CRFS_RFEYE		CRFS_RFEYE		3873
-rfeye			MACH_RFEYE		RFEYE			3874
-phidget_sbc3		MACH_PHIDGET_SBC3	PHIDGET_SBC3		3875
-tcw_mika		MACH_TCW_MIKA		TCW_MIKA		3876
-imx28_egf		MACH_IMX28_EGF		IMX28_EGF		3877
-valente_wx		MACH_VALENTE_WX		VALENTE_WX		3878
-huangshans		MACH_HUANGSHANS		HUANGSHANS		3879
-bosphorus1		MACH_BOSPHORUS1		BOSPHORUS1		3880
-prima			MACH_PRIMA		PRIMA			3881
-meson3_skt		MACH_M3_SKT		M3_SKT			3882
-meson3_ref		MACH_M3_REF		M3_REF			3883
-evita_ulk		MACH_EVITA_ULK		EVITA_ULK		3884
-merisc600		MACH_MERISC600		MERISC600		3885
-dolak			MACH_DOLAK		DOLAK			3886
-sbc53			MACH_SBC53		SBC53			3887
-elite_ulk		MACH_ELITE_ULK		ELITE_ULK		3888
-pov2			MACH_POV2		POV2			3889
-ipod_touch_2g		MACH_IPOD_TOUCH_2G	IPOD_TOUCH_2G		3890
-da850_pqab		MACH_DA850_PQAB		DA850_PQAB		3891
-fermi			MACH_FERMI		FERMI			3892
-ccardwmx28		MACH_CCARDWMX28		CCARDWMX28		3893
-ccardmx28		MACH_CCARDMX28		CCARDMX28		3894
-fs20_fcm2050		MACH_FS20_FCM2050	FS20_FCM2050		3895
-kinetis			MACH_KINETIS		KINETIS			3896
-kai			MACH_KAI		KAI			3897
-bcthb2			MACH_BCTHB2		BCTHB2			3898
-inels3_cu		MACH_INELS3_CU		INELS3_CU		3899
-da850_juniper		MACH_JUNIPER		JUNIPER			3900
-da850_apollo		MACH_DA850_APOLLO	DA850_APOLLO		3901
-tracnas			MACH_TRACNAS		TRACNAS			3902
-mityarm335x		MACH_MITYARM335X	MITYARM335X		3903
-xcgz7x			MACH_XCGZ7X		XCGZ7X			3904
-cubox			MACH_CUBOX		CUBOX			3905
-terminator		MACH_TERMINATOR		TERMINATOR		3906
-eye03			MACH_EYE03		EYE03			3907
-kota3			MACH_KOTA3		KOTA3			3908
-mx53_nitrogen_k		MACH_MX5		MX5			3909
-pscpe			MACH_PSCPE		PSCPE			3910
-akt1100			MACH_AKT1100		AKT1100			3911
-pcaaxl2			MACH_PCAAXL2		PCAAXL2			3912
-primodd_ct		MACH_PRIMODD_CT		PRIMODD_CT		3913
-nsbc			MACH_NSBC		NSBC			3914
-meson2_skt		MACH_MESON2_SKT		MESON2_SKT		3915
-meson2_ref		MACH_MESON2_REF		MESON2_REF		3916
-ccardwmx28js		MACH_CCARDWMX28JS	CCARDWMX28JS		3917
-ccardmx28js		MACH_CCARDMX28JS	CCARDMX28JS		3918
-indico			MACH_INDICO		INDICO			3919
-msm8960dt		MACH_MSM8960DT		MSM8960DT		3920
-primods			MACH_PRIMODS		PRIMODS			3921
-beluga_m1388		MACH_BELUGA_M1388	BELUGA_M1388		3922
-primotd			MACH_PRIMOTD		PRIMOTD			3923
-varan_master		MACH_VARAN_MASTER	VARAN_MASTER		3924
-primodd			MACH_PRIMODD		PRIMODD			3925
-jetduo			MACH_JETDUO		JETDUO			3926
-mx53_umobo		MACH_MX53_UMOBO		MX53_UMOBO		3927
-trats			MACH_TRATS		TRATS			3928
-starcraft		MACH_STARCRAFT		STARCRAFT		3929
-qseven_tegra2		MACH_QSEVEN_TEGRA2	QSEVEN_TEGRA2		3930
-lichee_sun4i_devbd	MACH_LICHEE_SUN4I_DEVBD	LICHEE_SUN4I_DEVBD	3931
-movenow			MACH_MOVENOW		MOVENOW			3932
-golf_u			MACH_GOLF_U		GOLF_U			3933
-msm7627a_evb		MACH_MSM7627A_EVB	MSM7627A_EVB		3934
-rambo			MACH_RAMBO		RAMBO			3935
-golfu			MACH_GOLFU		GOLFU			3936
-mango310		MACH_MANGO310		MANGO310		3937
-dns343			MACH_DNS343		DNS343			3938
-var_som_om44		MACH_VAR_SOM_OM44	VAR_SOM_OM44		3939
-naon			MACH_NAON		NAON			3940
-vp4000			MACH_VP4000		VP4000			3941
-impcard			MACH_IMPCARD		IMPCARD			3942
-smoovcam		MACH_SMOOVCAM		SMOOVCAM		3943
-cobham3725		MACH_COBHAM3725		COBHAM3725		3944
-cobham3730		MACH_COBHAM3730		COBHAM3730		3945
-cobham3703		MACH_COBHAM3703		COBHAM3703		3946
-quetzal			MACH_QUETZAL		QUETZAL			3947
-apq8064_cdp		MACH_APQ8064_CDP	APQ8064_CDP		3948
-apq8064_mtp		MACH_APQ8064_MTP	APQ8064_MTP		3949
-apq8064_fluid		MACH_APQ8064_FLUID	APQ8064_FLUID		3950
-apq8064_liquid		MACH_APQ8064_LIQUID	APQ8064_LIQUID		3951
-mango210		MACH_MANGO210		MANGO210		3952
-mango100		MACH_MANGO100		MANGO100		3953
-mango24			MACH_MANGO24		MANGO24			3954
-mango64			MACH_MANGO64		MANGO64			3955
-nsa320			MACH_NSA320		NSA320			3956
-elv_ccu2		MACH_ELV_CCU2		ELV_CCU2		3957
-triton_x00		MACH_TRITON_X00		TRITON_X00		3958
-triton_1500_2000	MACH_TRITON_1500_2000	TRITON_1500_2000	3959
-pogoplugv4		MACH_POGOPLUGV4		POGOPLUGV4		3960
-venus_cl		MACH_VENUS_CL		VENUS_CL		3961
-vulcano_g20		MACH_VULCANO_G20	VULCANO_G20		3962
-sgs_i9100		MACH_SGS_I9100		SGS_I9100		3963
-stsv2			MACH_STSV2		STSV2			3964
-csb1724			MACH_CSB1724		CSB1724			3965
-omapl138_lcdk		MACH_OMAPL138_LCDK	OMAPL138_LCDK		3966
-jel_dd			MACH_JEWEL_DD		JEWEL_DD		3967
-pvd_mx25		MACH_PVD_MX25		PVD_MX25		3968
-meson6_skt		MACH_MESON6_SKT		MESON6_SKT		3969
-meson6_ref		MACH_MESON6_REF		MESON6_REF		3970
-pxm			MACH_PXM		PXM			3971
-stuttgart		MACH_S3			S3			3972
-pogoplugv3		MACH_POGOPLUGV3		POGOPLUGV3		3973
-mlp89626		MACH_MLP89626		MLP89626		3974
-iomegahmndce		MACH_IOMEGAHMNDCE	IOMEGAHMNDCE		3975
-pogoplugv3pci		MACH_POGOPLUGV3PCI	POGOPLUGV3PCI		3976
-bntv250			MACH_BNTV250		BNTV250			3977
-mx53_qseven		MACH_MX53_QSEVEN	MX53_QSEVEN		3978
-gtl_it1100		MACH_GTL_IT1100		GTL_IT1100		3979
-mx6q_sabresd		MACH_MX6Q_SABRESD	MX6Q_SABRESD		3980
-mt4			MACH_MT4		MT4			3981
-jumbo_d			MACH_JUMBO_D		JUMBO_D			3982
-jumbo_i			MACH_JUMBO_I		JUMBO_I			3983
-fs20_dmp		MACH_FS20_DMP		FS20_DMP		3984
-dns320			MACH_DNS320		DNS320			3985
-mx28bacos		MACH_MX28BACOS		MX28BACOS		3986
-tl80			MACH_TL80		TL80			3987
-polatis_nic_1001	MACH_POLATIS_NIC_1001	POLATIS_NIC_1001	3988
-tely			MACH_TELY		TELY			3989
-u8520			MACH_U8520		U8520			3990
-manta			MACH_MANTA		MANTA			3991
-spear1340_lcad		MACH_SPEAR_EM_S900	SPEAR_EM_S900		3992
-mpq8064_cdp		MACH_MPQ8064_CDP	MPQ8064_CDP		3993
-mpq8064_hrd		MACH_MPQ8064_STB	MPQ8064_STB		3994
-mpq8064_dtv		MACH_MPQ8064_DTV	MPQ8064_DTV		3995
-dm368som		MACH_DM368SOM		DM368SOM		3996
-gprisb2			MACH_GPRISB2		GPRISB2			3997
-chammid			MACH_CHAMMID		CHAMMID			3998
-seoul2			MACH_SEOUL2		SEOUL2			3999
-omap4_nooktablet	MACH_OMAP4_NOOKTABLET	OMAP4_NOOKTABLET	4000
-aalto			MACH_AALTO		AALTO			4001
-metro			MACH_METRO		METRO			4002
-cydm3730		MACH_CYDM3730		CYDM3730		4003
-tqma53			MACH_TQMA53		TQMA53			4004
-msm7627a_qrd3		MACH_MSM7627A_QRD3	MSM7627A_QRD3		4005
-mx28_canby		MACH_MX28_CANBY		MX28_CANBY		4006
-tiger			MACH_TIGER		TIGER			4007
-pcats_9307_type_a	MACH_PCATS_9307_TYPE_A	PCATS_9307_TYPE_A	4008
-pcats_9307_type_o	MACH_PCATS_9307_TYPE_O	PCATS_9307_TYPE_O	4009
-pcats_9307_type_r	MACH_PCATS_9307_TYPE_R	PCATS_9307_TYPE_R	4010
-streamplug		MACH_STREAMPLUG		STREAMPLUG		4011
-icechicken_dev		MACH_ICECHICKEN_DEV	ICECHICKEN_DEV		4012
-hedgehog		MACH_HEDGEHOG		HEDGEHOG		4013
-yusend_obc		MACH_YUSEND_OBC		YUSEND_OBC		4014
-imxninja		MACH_IMXNINJA		IMXNINJA		4015
-omap4_jarod		MACH_OMAP4_JAROD	OMAP4_JAROD		4016
-eco5_pk			MACH_ECO5_PK		ECO5_PK			4017
-qj2440			MACH_QJ2440		QJ2440			4018
-mx6q_mercury		MACH_MX6Q_MERCURY	MX6Q_MERCURY		4019
-cm6810			MACH_CM6810		CM6810			4020
-omap4_torpedo		MACH_OMAP4_TORPEDO	OMAP4_TORPEDO		4021
-nsa310			MACH_NSA310		NSA310			4022
-tmx536			MACH_TMX536		TMX536			4023
-ktt20			MACH_KTT20		KTT20			4024
-dragonix		MACH_DRAGONIX		DRAGONIX		4025
-lungching		MACH_LUNGCHING		LUNGCHING		4026
-bulogics		MACH_BULOGICS		BULOGICS		4027
-mx535_sx		MACH_MX535_SX		MX535_SX		4028
-ngui3250		MACH_NGUI3250		NGUI3250		4029
-salutec_dac		MACH_SALUTEC_DAC	SALUTEC_DAC		4030
-loco			MACH_LOCO		LOCO			4031
-ctera_plug_usi		MACH_CTERA_PLUG_USI	CTERA_PLUG_USI		4032
-scepter			MACH_SCEPTER		SCEPTER			4033
-sga			MACH_SGA		SGA			4034
-p_81_j5			MACH_P_81_J5		P_81_J5			4035
-p_81_o4			MACH_P_81_O4		P_81_O4			4036
-msm8625_surf		MACH_MSM8625_SURF	MSM8625_SURF		4037
-carallon_shark		MACH_CARALLON_SHARK	CARALLON_SHARK		4038
-lsgc_icam		MACH_LSGCICAM		LSGCICAM		4039
-ordog			MACH_ORDOG		ORDOG			4040
-puente_io		MACH_PUENTE_IO		PUENTE_IO		4041
-msm8625_evb		MACH_MSM8625_EVB	MSM8625_EVB		4042
-ev_am1707		MACH_EV_AM1707		EV_AM1707		4043
-ev_am1707e2		MACH_EV_AM1707E2	EV_AM1707E2		4044
-ev_am3517e2		MACH_EV_AM3517E2	EV_AM3517E2		4045
-calabria		MACH_CALABRIA		CALABRIA		4046
-ev_imx287		MACH_EV_IMX287		EV_IMX287		4047
-erau			MACH_ERAU		ERAU			4048
-sichuan			MACH_SICHUAN		SICHUAN			4049
-sopdm			MACH_WIRMA3		WIRMA3			4050
-davinci_da850		MACH_DAVINCI_DA850	DAVINCI_DA850		4051
-omap138_trunarc		MACH_OMAP138_TRUNARC	OMAP138_TRUNARC		4052
-bcm4761			MACH_BCM4761		BCM4761			4053
-picasso_e2		MACH_PICASSO_E2		PICASSO_E2		4054
-picasso_mf		MACH_PICASSO_MF		PICASSO_MF		4055
-miro			MACH_MIRO		MIRO			4056
-at91sam9g20ewon3	MACH_AT91SAM9G20EWON3	AT91SAM9G20EWON3	4057
-yoyo			MACH_YOYO		YOYO			4058
-windjkl			MACH_WINDJKL		WINDJKL			4059
-monarudo		MACH_MONARUDO		MONARUDO		4060
-batan			MACH_BATAN		BATAN			4061
-tadao			MACH_TADAO		TADAO			4062
-baso			MACH_BASO		BASO			4063
-mahon			MACH_MAHON		MAHON			4064
-villec2			MACH_VILLEC2		VILLEC2			4065
-asi1230			MACH_ASI1230		ASI1230			4066
-alaska			MACH_ALASKA		ALASKA			4067
-swarco_shdsl2		MACH_SWARCO_SHDSL2	SWARCO_SHDSL2		4068
-oxrtu			MACH_OXRTU		OXRTU			4069
-omap5_panda		MACH_OMAP5_PANDA	OMAP5_PANDA		4070
-imx286			MACH_MX28XDI		MX28XDI			4071
-c8000			MACH_C8000		C8000			4072
-bje_display3_5		MACH_BJE_DISPLAY3_5	BJE_DISPLAY3_5		4073
-picomod7		MACH_PICOMOD7		PICOMOD7		4074
-picocom5		MACH_PICOCOM5		PICOCOM5		4075
-qblissa8		MACH_QBLISSA8		QBLISSA8		4076
-armstonea8		MACH_ARMSTONEA8		ARMSTONEA8		4077
-netdcu14		MACH_NETDCU14		NETDCU14		4078
-at91sam9x5_epiphan	MACH_AT91SAM9X5_EPIPHAN	AT91SAM9X5_EPIPHAN	4079
-p2u			MACH_P2U		P2U			4080
-doris			MACH_DORIS		DORIS			4081
-j49			MACH_J49		J49			4082
-vdss2e			MACH_VDSS2E		VDSS2E			4083
-vc300			MACH_VC300		VC300			4084
-ns115_pad_test		MACH_NS115_PAD_TEST	NS115_PAD_TEST		4085
-ns115_pad_ref		MACH_NS115_PAD_REF	NS115_PAD_REF		4086
-ns115_phone_test	MACH_NS115_PHONE_TEST	NS115_PHONE_TEST	4087
-ns115_phone_ref		MACH_NS115_PHONE_REF	NS115_PHONE_REF		4088
-golfc			MACH_GOLFC		GOLFC			4089
-xerox_olympus		MACH_XEROX_OLYMPUS	XEROX_OLYMPUS		4090
-mx6sl_arm2		MACH_MX6SL_ARM2		MX6SL_ARM2		4091
-csb1701_csb1726		MACH_CSB1701_CSB1726	CSB1701_CSB1726		4092
-at91sam9xeek		MACH_AT91SAM9XEEK	AT91SAM9XEEK		4093
-ebv210			MACH_EBV210		EBV210			4094
-msm7627a_qrd7		MACH_MSM7627A_QRD7	MSM7627A_QRD7		4095
-svthin			MACH_SVTHIN		SVTHIN			4096
-duovero			MACH_DUOVERO		DUOVERO			4097
-chupacabra		MACH_CHUPACABRA		CHUPACABRA		4098
-scorpion		MACH_SCORPION		SCORPION		4099
-davinci_he_hmi10	MACH_DAVINCI_HE_HMI10	DAVINCI_HE_HMI10	4100
-topkick			MACH_TOPKICK		TOPKICK			4101
-m3_auguestrush		MACH_M3_AUGUESTRUSH	M3_AUGUESTRUSH		4102
-ipc335x			MACH_IPC335X		IPC335X			4103
-sun4i			MACH_SUN4I		SUN4I			4104
-imx233_olinuxino	MACH_IMX233_OLINUXINO	IMX233_OLINUXINO	4105
-k2_wl			MACH_K2_WL		K2_WL			4106
-k2_ul			MACH_K2_UL		K2_UL			4107
-k2_cl			MACH_K2_CL		K2_CL			4108
-minbari_w		MACH_MINBARI_W		MINBARI_W		4109
-minbari_m		MACH_MINBARI_M		MINBARI_M		4110
-k035			MACH_K035		K035			4111
-ariel			MACH_ARIEL		ARIEL			4112
-arielsaarc		MACH_ARIELSAARC		ARIELSAARC		4113
-arieldkb		MACH_ARIELDKB		ARIELDKB		4114
-armadillo810		MACH_ARMADILLO810	ARMADILLO810		4115
-tam335x			MACH_TAM335X		TAM335X			4116
-grouper			MACH_GROUPER		GROUPER			4117
-mpcsa21_9g20		MACH_MPCSA21_9G20	MPCSA21_9G20		4118
-m6u_cpu			MACH_M6U_CPU		M6U_CPU			4119
-davinci_dp7		MACH_DAVINCI_DP10	DAVINCI_DP10		4120
-ginkgo			MACH_GINKGO		GINKGO			4121
-cgt_qmx6		MACH_CGT_QMX6		CGT_QMX6		4122
-profpga			MACH_PROFPGA		PROFPGA			4123
-acfx100oc		MACH_ACFX100OC		ACFX100OC		4124
-acfx100nb		MACH_ACFX100NB		ACFX100NB		4125
-capricorn		MACH_CAPRICORN		CAPRICORN		4126
-pisces			MACH_PISCES		PISCES			4127
-aries			MACH_ARIES		ARIES			4128
-cancer			MACH_CANCER		CANCER			4129
-leo			MACH_LEO		LEO			4130
-virgo			MACH_VIRGO		VIRGO			4131
-sagittarius		MACH_SAGITTARIUS	SAGITTARIUS		4132
-devil			MACH_DEVIL		DEVIL			4133
-ballantines		MACH_BALLANTINES	BALLANTINES		4134
-omap3_procerusvpu	MACH_OMAP3_PROCERUSVPU	OMAP3_PROCERUSVPU	4135
-my27			MACH_MY27		MY27			4136
-sun6i			MACH_SUN6I		SUN6I			4137
-sun5i			MACH_SUN5I		SUN5I			4138
-mx512_mx		MACH_MX512_MX		MX512_MX		4139
-kzm9g			MACH_KZM9G		KZM9G			4140
-vdstbn			MACH_VDSTBN		VDSTBN			4141
-cfa10036		MACH_CFA10036		CFA10036		4142
-cfa10049		MACH_CFA10049		CFA10049		4143
-pcm051			MACH_PCM051		PCM051			4144
-vybrid_vf7xx		MACH_VYBRID_VF7XX	VYBRID_VF7XX		4145
-vybrid_vf6xx		MACH_VYBRID_VF6XX	VYBRID_VF6XX		4146
-vybrid_vf5xx		MACH_VYBRID_VF5XX	VYBRID_VF5XX		4147
-vybrid_vf4xx		MACH_VYBRID_VF4XX	VYBRID_VF4XX		4148
-aria_g25		MACH_ARIA_G25		ARIA_G25		4149
-bcm21553		MACH_BCM21553		BCM21553		4150
-smdk5410		MACH_SMDK5410		SMDK5410		4151
-lpc18xx			MACH_LPC18XX		LPC18XX			4152
-oratisparty		MACH_ORATISPARTY	ORATISPARTY		4153
-qseven			MACH_QSEVEN		QSEVEN			4154
-gmv_generic		MACH_GMV_GENERIC	GMV_GENERIC		4155
-th_link_eth		MACH_TH_LINK_ETH	TH_LINK_ETH		4156
-tn_muninn		MACH_TN_MUNINN		TN_MUNINN		4157
-rampage			MACH_RAMPAGE		RAMPAGE			4158
-visstrim_mv10		MACH_VISSTRIM_MV10	VISSTRIM_MV10		4159
-monacotdu		MACH_MONACO_TDU		MONACO_TDU		4160
-monacoul		MACH_MONACO_UL		MONACO_UL		4161
-enrc2u			MACH_ENRC2_U		ENRC2_U			4162
-evitareul		MACH_EVITA_UL		EVITA_UL		4163
-mx28_wilma		MACH_MX28_WILMA		MX28_WILMA		4164
-monacou			MACH_MONACO_U		MONACO_U		4165
-msm8625_ffa		MACH_MSM8625_FFA	MSM8625_FFA		4166
-vpu101			MACH_VPU101		VPU101			4167
-operaul			MACH_OPERA_UL		OPERA_UL		4168
-baileys			MACH_BAILEYS		BAILEYS			4169
-cloudbox		MACH_FAMILYBOX		FAMILYBOX		4170
-ensemble_mx35		MACH_ENSEMBLE_MX35	ENSEMBLE_MX35		4171
-sc_sps_1		MACH_SC_SPS_1		SC_SPS_1		4172
-ucsimply_sam9260	MACH_UCSIMPLY_SAM9260	UCSIMPLY_SAM9260	4173
-unicorn			MACH_UNICORN		UNICORN			4174
-m9g45a			MACH_M9G45A		M9G45A			4175
-mtwebif			MACH_MTWEBIF		MTWEBIF			4176
-playstone		MACH_PLAYSTONE		PLAYSTONE		4177
-chelsea			MACH_CHELSEA		CHELSEA			4178
-bayern			MACH_BAYERN		BAYERN			4179
-mitwo			MACH_MITWO		MITWO			4180
-mx25_noah		MACH_MX25_NOAH		MX25_NOAH		4181
-stm_b2020		MACH_STM_B2020		STM_B2020		4182
-annax_src		MACH_ANNAX_SRC		ANNAX_SRC		4183
-ionics_stratus		MACH_IONICS_STRATUS	IONICS_STRATUS		4184
-hugo			MACH_HUGO		HUGO			4185
-em300			MACH_EM300		EM300			4186
-mmp3_qseven		MACH_MMP3_QSEVEN	MMP3_QSEVEN		4187
-bosphorus2		MACH_BOSPHORUS2		BOSPHORUS2		4188
-tt2200			MACH_TT2200		TT2200			4189
-ocelot3			MACH_OCELOT3		OCELOT3			4190
-tek_cobra		MACH_TEK_COBRA		TEK_COBRA		4191
-protou			MACH_PROTOU		PROTOU			4192
-msm8625_evt		MACH_MSM8625_EVT	MSM8625_EVT		4193
-mx53_sellwood		MACH_MX53_SELLWOOD	MX53_SELLWOOD		4194
-somiq_am35		MACH_SOMIQ_AM35		SOMIQ_AM35		4195
-somiq_am37		MACH_SOMIQ_AM37		SOMIQ_AM37		4196
-k2_plc_cl		MACH_K2_PLC_CL		K2_PLC_CL		4197
-tc2			MACH_TC2		TC2			4198
-dulex_j			MACH_DULEX_J		DULEX_J			4199
-stm_b2044		MACH_STM_B2044		STM_B2044		4200
-deluxe_j		MACH_DELUXE_J		DELUXE_J		4201
-mango2443		MACH_MANGO2443		MANGO2443		4202
-cp2dcg			MACH_CP2DCG		CP2DCG			4203
-cp2dtg			MACH_CP2DTG		CP2DTG			4204
-cp2dug			MACH_CP2DUG		CP2DUG			4205
-var_som_am33		MACH_VAR_SOM_AM33	VAR_SOM_AM33		4206
-pepper			MACH_PEPPER		PEPPER			4207
-mango2450		MACH_MANGO2450		MANGO2450		4208
-valente_wx_c9		MACH_VALENTE_WX_C9	VALENTE_WX_C9		4209
-minitv			MACH_MINITV		MINITV			4210
-u8540			MACH_U8540		U8540			4211
-iv_atlas_i_z7e		MACH_IV_ATLAS_I_Z7E	IV_ATLAS_I_Z7E		4212
-mx53_csb1733		MACH_COGENT_CSB1733	COGENT_CSB1733		4213
-mach_type_sky		MACH_MACH_TYPE_SKY	MACH_TYPE_SKY		4214
-bluesky			MACH_BLUESKY		BLUESKY			4215
-ngrouter		MACH_NGROUTER		NGROUTER		4216
-mx53_denetim		MACH_MX53_DENETIM	MX53_DENETIM		4217
-opal			MACH_OPAL		OPAL			4218
-gnet_us3gref		MACH_GNET_US3GREF	GNET_US3GREF		4219
-gnet_nc3g		MACH_GNET_NC3G		GNET_NC3G		4220
-gnet_ge3g		MACH_GNET_GE3G		GNET_GE3G		4221
-adp2			MACH_ADP2		ADP2			4222
-tqma28			MACH_TQMA28		TQMA28			4223
-kacom3			MACH_KACOM3		KACOM3			4224
-rrhdemo			MACH_RRHDEMO		RRHDEMO			4225
-protodug		MACH_PROTODUG		PROTODUG		4226
-lago			MACH_LAGO		LAGO			4227
-ktt30			MACH_KTT30		KTT30			4228
-ts43xx			MACH_TS43XX		TS43XX			4229
-mx6q_denso		MACH_MX6Q_DENSO		MX6Q_DENSO		4230
-comsat_gsmumts8		MACH_COMSAT_GSMUMTS8	COMSAT_GSMUMTS8		4231
-dreamx			MACH_DREAMX		DREAMX			4232
-thunderstonem		MACH_THUNDERSTONEM	THUNDERSTONEM		4233
-yoyopad			MACH_YOYOPAD		YOYOPAD			4234
-yoyopatient		MACH_YOYOPATIENT	YOYOPATIENT		4235
-a10l			MACH_A10L		A10L			4236
-mq60			MACH_MQ60		MQ60			4237
-linkstation_lsql	MACH_LINKSTATION_LSQL	LINKSTATION_LSQL	4238
-am3703gateway		MACH_AM3703GATEWAY	AM3703GATEWAY		4239
-accipiter		MACH_ACCIPITER		ACCIPITER		4240
-e1853			MACH_P1853		P1853			4241
-magnidug		MACH_MAGNIDUG		MAGNIDUG		4242
-hydra			MACH_HYDRA		HYDRA			4243
-sun3i			MACH_SUN3I		SUN3I			4244
-stm_b2078		MACH_STM_B2078		STM_B2078		4245
-at91sam9263deskv2	MACH_AT91SAM9263DESKV2	AT91SAM9263DESKV2	4246
-deluxe_r		MACH_DELUXE_R		DELUXE_R		4247
-p_98_v			MACH_P_98_V		P_98_V			4248
-p_98_c			MACH_P_98_C		P_98_C			4249
-davinci_am18xx_omn	MACH_DAVINCI_AM18XX_OMN	DAVINCI_AM18XX_OMN	4250
-socfpga_cyclone5	MACH_SOCFPGA_CYCLONE5	SOCFPGA_CYCLONE5	4251
-cabatuin		MACH_CABATUIN		CABATUIN		4252
-yoyopad_ft		MACH_YOYOPAD_FT		YOYOPAD_FT		4253
-dan2400evb		MACH_DAN2400EVB		DAN2400EVB		4254
-dan3400evb		MACH_DAN3400EVB		DAN3400EVB		4255
-edm_sf_imx6		MACH_EDM_SF_IMX6	EDM_SF_IMX6		4256
-edm_cf_imx6		MACH_EDM_CF_IMX6	EDM_CF_IMX6		4257
-vpos3xx			MACH_VPOS3XX		VPOS3XX			4258
-vulcano_9x5		MACH_VULCANO_9X5	VULCANO_9X5		4259
-spmp8000		MACH_SPMP8000		SPMP8000		4260
-catalina		MACH_CATALINA		CATALINA		4261
-rd88f5181l_fe		MACH_RD88F5181L_FE	RD88F5181L_FE		4262
-mx535_mx		MACH_MX535_MX		MX535_MX		4263
-armadillo840		MACH_ARMADILLO840	ARMADILLO840		4264
-spc9000baseboard	MACH_SPC9000BASEBOARD	SPC9000BASEBOARD	4265
-iris			MACH_IRIS		IRIS			4266
-protodcg		MACH_PROTODCG		PROTODCG		4267
-palmtree		MACH_PALMTREE		PALMTREE		4268
-novena			MACH_NOVENA		NOVENA			4269
-ma_um			MACH_MA_UM		MA_UM			4270
-ma_am			MACH_MA_AM		MA_AM			4271
-ems348			MACH_EMS348		EMS348			4272
-cm_fx6			MACH_CM_FX6		CM_FX6			4273
-arndale			MACH_ARNDALE		ARNDALE			4274
-q5xr5			MACH_Q5XR5		Q5XR5			4275
-willow			MACH_WILLOW		WILLOW			4276
-omap3621_odyv3		MACH_OMAP3621_ODYV3	OMAP3621_ODYV3		4277
-omapl138_presonus	MACH_OMAPL138_PRESONUS	OMAPL138_PRESONUS	4278
-dvf99			MACH_DVF99		DVF99			4279
-impression_j		MACH_IMPRESSION_J	IMPRESSION_J		4280
-qblissa9		MACH_QBLISSA9		QBLISSA9		4281
-robin_heliview10	MACH_ROBIN_HELIVIEW10	ROBIN_HELIVIEW10	4282
-sun7i			MACH_SUN7I		SUN7I			4283
-mx6q_hdmidongle		MACH_MX6Q_HDMIDONGLE	MX6Q_HDMIDONGLE		4284
-mx6_sid2		MACH_MX6_SID2		MX6_SID2		4285
-helios_v3		MACH_HELIOS_V3		HELIOS_V3		4286
-helios_v4		MACH_HELIOS_V4		HELIOS_V4		4287
-q7_imx6			MACH_Q7_IMX6		Q7_IMX6			4288
-odroidx			MACH_ODROIDX		ODROIDX			4289
-robpro			MACH_ROBPRO		ROBPRO			4290
-research59if_mk1	MACH_RESEARCH59IF_MK1	RESEARCH59IF_MK1	4291
-bobsleigh		MACH_BOBSLEIGH		BOBSLEIGH		4292
-dcshgwt3		MACH_DCSHGWT3		DCSHGWT3		4293
-gld1018			MACH_GLD1018		GLD1018			4294
-ev10			MACH_EV10		EV10			4295
-nitrogen6x		MACH_NITROGEN6X		NITROGEN6X		4296
-p_107_bb		MACH_P_107_BB		P_107_BB		4297
-evita_utl		MACH_EVITA_UTL		EVITA_UTL		4298
-falconwing		MACH_FALCONWING		FALCONWING		4299
-dct3			MACH_DCT3		DCT3			4300
-cpx2e_cell		MACH_CPX2E_CELL		CPX2E_CELL		4301
-amiro			MACH_AMIRO		AMIRO			4302
-mx6q_brassboard		MACH_MX6Q_BRASSBOARD	MX6Q_BRASSBOARD		4303
-dalmore			MACH_DALMORE		DALMORE			4304
-omap3_portal7cp		MACH_OMAP3_PORTAL7CP	OMAP3_PORTAL7CP		4305
-tegra_pluto		MACH_TEGRA_PLUTO	TEGRA_PLUTO		4306
-mx6sl_evk		MACH_MX6SL_EVK		MX6SL_EVK		4307
-m7			MACH_M7			M7			4308
-pxm2			MACH_PXM2		PXM2			4309
-haba_knx_lite		MACH_HABA_KNX_LITE	HABA_KNX_LITE		4310
-tai			MACH_TAI		TAI			4311
-prototd			MACH_PROTOTD		PROTOTD			4312
-dst_tonto		MACH_DST_TONTO		DST_TONTO		4313
-draco			MACH_DRACO		DRACO			4314
-dxr2			MACH_DXR2		DXR2			4315
-rut			MACH_RUT		RUT			4316
-am180x_wsc		MACH_AM180X_WSC		AM180X_WSC		4317
-deluxe_u		MACH_DELUXE_U		DELUXE_U		4318
-deluxe_ul		MACH_DELUXE_UL		DELUXE_UL		4319
-at91sam9260medths	MACH_AT91SAM9260MEDTHS	AT91SAM9260MEDTHS	4320
-matrix516		MACH_MATRIX516		MATRIX516		4321
-vid401x			MACH_VID401X		VID401X			4322
-helios_v5		MACH_HELIOS_V5		HELIOS_V5		4323
-playpaq2		MACH_PLAYPAQ2		PLAYPAQ2		4324
-igam			MACH_IGAM		IGAM			4325
-amico_i			MACH_AMICO_I		AMICO_I			4326
-amico_e			MACH_AMICO_E		AMICO_E			4327
-sentient_mm3_ck		MACH_SENTIENT_MM3_CK	SENTIENT_MM3_CK		4328
-smx6			MACH_SMX6		SMX6			4329
-pango			MACH_PANGO		PANGO			4330
-ns115_stick		MACH_NS115_STICK	NS115_STICK		4331
-bctrm3			MACH_BCTRM3		BCTRM3			4332
-doctorws		MACH_DOCTORWS		DOCTORWS		4333
-m2601			MACH_M2601		M2601			4334
-gco_mgmtt		MACH_GRIDCO_TRINITY	GRIDCO_TRINITY		4335
-pc73032			MACH_PC3032		PC3032			4336
-vgg1111			MACH_VGG1111		VGG1111			4337
-countach		MACH_COUNTACH		COUNTACH		4338
-visstrim_sm20		MACH_VISSTRIM_SM20	VISSTRIM_SM20		4339
-a639			MACH_A639		A639			4340
-spacemonkey		MACH_SPACEMONKEY	SPACEMONKEY		4341
-zpdu_stamp		MACH_ZPDU_STAMP		ZPDU_STAMP		4342
-htc_g7_clone		MACH_HTC_G7_CLONE	HTC_G7_CLONE		4343
-ft2080_corvus		MACH_FT2080_CORVUS	FT2080_CORVUS		4344
-fisland			MACH_FISLAND		FISLAND			4345
-zpdu			MACH_ZPDU		ZPDU			4346
-urt			MACH_URT		URT			4347
-conti_ovip		MACH_CONTI_OVIP		CONTI_OVIP		4348
-omapl138_nagra		MACH_OMAPL138_NAGRA	OMAPL138_NAGRA		4349
-da850_at3kp1		MACH_DA850_AT3KP1	DA850_AT3KP1		4350
-da850_at3kp2		MACH_DA850_AT3KP2	DA850_AT3KP2		4351
-surma			MACH_SURMA		SURMA			4352
-stm_b2092		MACH_STM_B2092		STM_B2092		4353
-mx535_ycr		MACH_MX535_YCR		MX535_YCR		4354
-m7_wl			MACH_M7_WL		M7_WL			4355
-m7_u			MACH_M7_U		M7_U			4356
-omap3_stndt_evm		MACH_OMAP3_STNDT_EVM	OMAP3_STNDT_EVM		4357
-m7_wlv			MACH_M7_WLV		M7_WLV			4358
-xam3517			MACH_XAM3517		XAM3517			4359
-a220			MACH_A220		A220			4360
-aclima_odie		MACH_ACLIMA_ODIE	ACLIMA_ODIE		4361
-vibble			MACH_VIBBLE		VIBBLE			4362
-k2_u			MACH_K2_U		K2_U			4363
-mx53_egf		MACH_MX53_EGF		MX53_EGF		4364
-novpek_imx53		MACH_NOVPEK_IMX53	NOVPEK_IMX53		4365
-novpek_imx6x		MACH_NOVPEK_IMX6X	NOVPEK_IMX6X		4366
-mx25_smartbox		MACH_MX25_SMARTBOX	MX25_SMARTBOX		4367
-eicg6410		MACH_EICG6410		EICG6410		4368
-picasso_e3		MACH_PICASSO_E3		PICASSO_E3		4369
-motonavigator		MACH_MOTONAVIGATOR	MOTONAVIGATOR		4370
-varioconnect2		MACH_VARIOCONNECT2	VARIOCONNECT2		4371
-deluxe_tw		MACH_DELUXE_TW		DELUXE_TW		4372
-kore3			MACH_KORE3		KORE3			4374
-mx6s_drs		MACH_MX6S_DRS		MX6S_DRS		4375
-cmimx6			MACH_CMIMX6		CMIMX6			4376
-roth			MACH_ROTH		ROTH			4377
-eq4ux			MACH_EQ4UX		EQ4UX			4378
-x1plus			MACH_X1PLUS		X1PLUS			4379
-modimx27		MACH_MODIMX27		MODIMX27		4380
-videon_hduac		MACH_VIDEON_HDUAC	VIDEON_HDUAC		4381
-blackbird		MACH_BLACKBIRD		BLACKBIRD		4382
-runmaster		MACH_RUNMASTER		RUNMASTER		4383
-ceres			MACH_CERES		CERES			4384
-nad435			MACH_NAD435		NAD435			4385
-ns115_proto_type	MACH_NS115_PROTO_TYPE	NS115_PROTO_TYPE	4386
-fs20_vcc		MACH_FS20_VCC		FS20_VCC		4387
-meson6tv_ref		MACH_MESON6TV		MESON6TV		4388
-meson6tv_skt		MACH_MESON6TV_SKT	MESON6TV_SKT		4389
-keystone		MACH_KEYSTONE		KEYSTONE		4390
-pcm052			MACH_PCM052		PCM052			4391
-rainbowg15_q7		MACH_TYPE		TYPE			4392
-qrd_skud_prime		MACH_QRD_SKUD_PRIME	QRD_SKUD_PRIME		4393
-mx6_rainbow		MACH_RAINBOWG15		RAINBOWG15		4394
-guf_santaro		MACH_GUF_SANTARO	GUF_SANTARO		4395
-sheepshead		MACH_SHEEPSHEAD		SHEEPSHEAD		4396
-mx6_iwg15m_mxm		MACH_MX6_IWG15M_MXM	MX6_IWG15M_MXM		4397
-mx6_iwg15m_q7		MACH_MX6_IWG15M_Q7	MX6_IWG15M_Q7		4398
-at91sam9263if8mic	MACH_AT91SAM9263IF8MIC	AT91SAM9263IF8MIC	4399
-ex			MACH_EXCEL		EXCEL			4400
-marcopolo		MACH_MARCOPOLO		MARCOPOLO		4401
-mx535_sdcr		MACH_MX535_SDCR		MX535_SDCR		4402
-mx53_csb2733		MACH_MX53_CSB2733	MX53_CSB2733		4403
-diva			MACH_DIVA		DIVA			4404
-ncr_7744		MACH_NCR_7744		NCR_7744		4405
-macallan		MACH_MACALLAN		MACALLAN		4406
-wnr3500			MACH_WNR3500		WNR3500			4407
-pgavrf			MACH_PGAVRF		PGAVRF			4408
-helios_v6		MACH_HELIOS_V6		HELIOS_V6		4409
-lcct			MACH_LCCT		LCCT			4410
-csndug			MACH_CSNDUG		CSNDUG			4411
-wandboard_imx6		MACH_WANDBOARD_IMX6	WANDBOARD_IMX6		4412
-omap4_jet		MACH_OMAP4_JET		OMAP4_JET		4413
-tegra_roth		MACH_TEGRA_ROTH		TEGRA_ROTH		4414
-m7dcg			MACH_M7DCG		M7DCG			4415
-m7dug			MACH_M7DUG		M7DUG			4416
-m7dtg			MACH_M7DTG		M7DTG			4417
-ap42x			MACH_AP42X		AP42X			4418
-var_som_mx6		MACH_VAR_SOM_MX6	VAR_SOM_MX6		4419
-pdlu			MACH_PDLU		PDLU			4420
-hydrogen		MACH_HYDROGEN		HYDROGEN		4421
-npa211e			MACH_NPA211E		NPA211E			4422
-arcadia			MACH_ARCADIA		ARCADIA			4423
-arcadia_l		MACH_ARCADIA_L		ARCADIA_L		4424
-msm8930dt		MACH_MSM8930DT		MSM8930DT		4425
-ktam3874		MACH_KTAM3874		KTAM3874		4426
-cec4			MACH_CEC4		CEC4			4427
-ape6evm			MACH_APE6EVM		APE6EVM			4428
-tx6			MACH_TX6		TX6			4429
-owen_som		MACH_OWENSOM		OWENSOM			4430
-cfa10037		MACH_CFA10037		CFA10037		4431
-nbrd_voip		MACH_NATEKS_VOIP	NATEKS_VOIP		4432
-ezp1000			MACH_EZP1000		EZP1000			4433
-wgr826v			MACH_WGR826V		WGR826V			4434
-exuma			MACH_EXUMA		EXUMA			4435
-fregate			MACH_FREGATE		FREGATE			4436
-osirisimx508		MACH_OSIRISIMX508	OSIRISIMX508		4437
-st_exigo		MACH_ST_EXIGO		ST_EXIGO		4438
-pismo			MACH_PISMO		PISMO			4439
-atc7			MACH_ATC7		ATC7			4440
-nspireclp		MACH_NSPIRECLP		NSPIRECLP		4441
-nspiretp		MACH_NSPIRETP		NSPIRETP		4442
-nspirecx		MACH_NSPIRECX		NSPIRECX		4443
-maya			MACH_MAYA		MAYA			4444
-wecct			MACH_WECCT		WECCT			4445
-m2s			MACH_M2S		M2S			4446
-msm8625q_evbd		MACH_MSM8625Q_EVBD	MSM8625Q_EVBD		4447
-tiny210			MACH_TINY210		TINY210			4448
-g3			MACH_G3			G3			4449
-hurricane		MACH_HURRICANE		HURRICANE		4450
-mx6_pod			MACH_MX6_POD		MX6_POD			4451
-elondcn			MACH_ELONDCN		ELONDCN			4452
-cwmx535			MACH_CWMX535		CWMX535			4453
-m7_wlj			MACH_M7_WLJ		M7_WLJ			4454
-qsp_arm			MACH_QSP_ARM		QSP_ARM			4455
-msm8625q_skud		MACH_MSM8625Q_SKUD	MSM8625Q_SKUD		4456
-htcmondrian		MACH_HTCMONDRIAN	HTCMONDRIAN		4457
-watson_ead		MACH_WATSON_EAD		WATSON_EAD		4458
-mitwoa			MACH_MITWOA		MITWOA			4459
-omap3_wolverine		MACH_OMAP3_WOLVERINE	OMAP3_WOLVERINE		4460
-mapletree		MACH_MAPLETREE		MAPLETREE		4461
-msm8625_fih_sae		MACH_MSM8625_FIH_SAE	MSM8625_FIH_SAE		4462
-epc35			MACH_EPC35		EPC35			4463
-smartrtu		MACH_SMARTRTU		SMARTRTU		4464
-rcm101			MACH_RCM101		RCM101			4465
-amx_imx53_mxx		MACH_AMX_IMX53_MXX	AMX_IMX53_MXX		4466
-crius			MACH_CP3DCG		CP3DCG			4467
-themis			MACH_CP3DTG		CP3DTG			4468
-uranus			MACH_CP3DUG		CP3DUG			4469
-acer_a12		MACH_ACER_A12		ACER_A12		4470
-sbc6x			MACH_SBC6X		SBC6X			4471
-u2			MACH_U2			U2			4472
-smdk4270		MACH_SMDK4270		SMDK4270		4473
-priscillag		MACH_PRISCILLAG		PRISCILLAG		4474
-priscillac		MACH_PRISCILLAC		PRISCILLAC		4475
-priscilla		MACH_PRISCILLA		PRISCILLA		4476
-innova_shpu_v2		MACH_INNOVA_SHPU_V2	INNOVA_SHPU_V2		4477
-auriga			MACH_M7CDTU		M7CDTU			4478
-mach_type_dep2410	MACH_MACH_TYPE_DEP2410	MACH_TYPE_DEP2410	4479
-bctre3			MACH_BCTRE3		BCTRE3			4480
-omap_m100		MACH_OMAP_M100		OMAP_M100		4481
-flo			MACH_FLO		FLO			4482
-nanobone		MACH_NANOBONE		NANOBONE		4483
-stm_b2105		MACH_STM_B2105		STM_B2105		4484
-omap4_bsc_bap_v3	MACH_OMAP4_BSC_BAP_V3	OMAP4_BSC_BAP_V3	4485
-ss1pam			MACH_SS1PAM		SS1PAM			4486
-caelum			MACH_DLXP_WL		DLXP_WL			4487
-primominiu		MACH_PRIMOMINIU		PRIMOMINIU		4488
-mrt_35hd_dualnas_e	MACH_MRT_35HD_DUALNAS_E	MRT_35HD_DUALNAS_E	4489
-kiwi			MACH_KIWI		KIWI			4490
-hw90496			MACH_HW90496		HW90496			4491
-mep2440			MACH_MEP2440		MEP2440			4492
-colibri_t30		MACH_COLIBRI_T30	COLIBRI_T30		4493
-cwv1			MACH_CWV1		CWV1			4494
-nsa325			MACH_NSA325		NSA325			4495
-camelopardalis		MACH_DLXP_UL		DLXP_UL			4496
-dpxmtc			MACH_DPXMTC		DPXMTC			4497
-tt_stuttgart		MACH_TT_STUTTGART	TT_STUTTGART		4498
-miranda_apcii		MACH_MIRANDA_APCII	MIRANDA_APCII		4499
-mx6q_moderox		MACH_MX6Q_MODEROX	MX6Q_MODEROX		4500
-mudskipper		MACH_MUDSKIPPER		MUDSKIPPER		4501
-urania			MACH_URANIA		URANIA			4502
-stm_b2112		MACH_STM_B2112		STM_B2112		4503
-ara			MACH_GTOU		GTOU			4504
-mx6q_ats_phoenix	MACH_MX6Q_ATS_PHOENIX	MX6Q_ATS_PHOENIX	4505
-stm_b2116		MACH_STM_B2116		STM_B2116		4506
-mythology		MACH_MYTHOLOGY		MYTHOLOGY		4507
-fc360v1			MACH_FC360V1		FC360V1			4508
-gps_sensor		MACH_GPS_SENSOR		GPS_SENSOR		4509
-gazelle			MACH_GAZELLE		GAZELLE			4510
-mpq8064_dma		MACH_MPQ8064_DMA	MPQ8064_DMA		4511
-wems_asd01		MACH_WEMS_ASD01		WEMS_ASD01		4512
-apalis_t30		MACH_APALIS_T30		APALIS_T30		4513
-mx6q_sbc35_c398		MACH_MX6Q_QSBC35_C398	MX6Q_QSBC35_C398	4514
-armstonea9		MACH_ARMSTONEA9		ARMSTONEA9		4515
-omap_blazetablet	MACH_OMAP_BLAZETABLET	OMAP_BLAZETABLET	4516
-ar6mxq			MACH_AR6MXQ		AR6MXQ			4517
-ar6mxs			MACH_AR6MXS		AR6MXS			4518
-deto_mx6apos		MACH_DETO_APOS_MX6	DETO_APOS_MX6		4519
-gwventana		MACH_GWVENTANA		GWVENTANA		4520
-igep0033		MACH_IGEP0033		IGEP0033		4521
-antlia			MACH_RACA		RACA			4522
-apus			MACH_APPLESODA		APPLESODA		4523
-h52c1_concerto		MACH_H52C1_CONCERTO	H52C1_CONCERTO		4524
-fcmbrd			MACH_FCMBRD		FCMBRD			4525
-pcaaxs1			MACH_PCAAXS1		PCAAXS1			4526
-ls_orca			MACH_LS_ORCA		LS_ORCA			4527
-pcm051lb		MACH_PCM051LB		PCM051LB		4528
-mx6s_lp507_gvci		MACH_MX6S_LP507_GVCI	MX6S_LP507_GVCI		4529
-dido			MACH_DIDO		DIDO			4530
-swarco_itc3_9g20	MACH_SWARCO_ITC3_9G20	SWARCO_ITC3_9G20	4531
-robo_roady		MACH_ROBO_ROADY		ROBO_ROADY		4532
-rskrza1			MACH_RSKRZA1		RSKRZA1			4533
-swarco_sid		MACH_SWARCO_SID		SWARCO_SID		4534
-mx6_iwg15s_sbc		MACH_MX6_IWG15S_SBC	MX6_IWG15S_SBC		4535
-mx6q_camaro		MACH_MX6Q_CAMARO	MX6Q_CAMARO		4536
-hb6mxs			MACH_HB6MXS		HB6MXS			4537
-lager			MACH_LAGER		LAGER			4538
-lp8x4x			MACH_LP8X4X		LP8X4X			4539
-tegratab7		MACH_TEGRATAB7		TEGRATAB7		4540
-andromeda		MACH_ANDROMEDA		ANDROMEDA		4541
-bootes			MACH_BOOTES		BOOTES			4542
-nethmi			MACH_NETHMI		NETHMI			4543
-tegratab		MACH_TEGRATAB		TEGRATAB		4544
-som5_evb		MACH_SOM5_EVB		SOM5_EVB		4545
-venaticorum		MACH_VENATICORUM	VENATICORUM		4546
-stm_b2110		MACH_STM_B2110		STM_B2110		4547
-elux_hathor		MACH_ELUX_HATHOR	ELUX_HATHOR		4548
-helios_v7		MACH_HELIOS_V7		HELIOS_V7		4549
-xc10v1			MACH_XC10V1		XC10V1			4550
-cp2u			MACH_CP2U		CP2U			4551
-iap_f			MACH_IAP_F		IAP_F			4552
-iap_g			MACH_IAP_G		IAP_G			4553
-aae			MACH_AAE		AAE			4554
-pegasus			MACH_PEGASUS		PEGASUS			4555
-cygnus			MACH_CYGNUS		CYGNUS			4556
-centaurus		MACH_CENTAURUS		CENTAURUS		4557
-msm8930_qrd8930		MACH_MSM8930_QRD8930	MSM8930_QRD8930		4558
-quby_tim		MACH_QUBY_TIM		QUBY_TIM		4559
-zedi3250a		MACH_ZEDI3250A		ZEDI3250A		4560
-grus			MACH_GRUS		GRUS			4561
-apollo3			MACH_APOLLO3		APOLLO3			4562
-cowon_r7		MACH_COWON_R7		COWON_R7		4563
-tonga3			MACH_TONGA3		TONGA3			4564
-p535			MACH_P535		P535			4565
-sa3874i			MACH_SA3874I		SA3874I			4566
-mx6_navico_com		MACH_MX6_NAVICO_COM	MX6_NAVICO_COM		4567
-proxmobil2		MACH_PROXMOBIL2		PROXMOBIL2		4568
-ubinux1			MACH_UBINUX1		UBINUX1			4569
-istos			MACH_ISTOS		ISTOS			4570
-benvolio4		MACH_BENVOLIO4		BENVOLIO4		4571
-eco5_bx2		MACH_ECO5_BX2		ECO5_BX2		4572
-eukrea_cpuimx28sd	MACH_EUKREA_CPUIMX28SD	EUKREA_CPUIMX28SD	4573
-domotab			MACH_DOMOTAB		DOMOTAB			4574
-pfla03			MACH_PFLA03		PFLA03			4575
-et_cpu_301_16		MACH_ET_CPU_301_16	ET_CPU_301_16		4576
-skywalker		MACH_SKYWALKER		SKYWALKER		4577
-scorpius		MACH_SCORPIUS		SCORPIUS		4578
-capricornus		MACH_CAPRICORNUS	CAPRICORNUS		4579
-lyra			MACH_LYRA		LYRA			4580
-gatero			MACH_GATERO		GATERO			4581
-gatero01		MACH_GATERO01		GATERO01		4582
-z4dtg			MACH_Z4DTG		Z4DTG			4583
-lupus			MACH_LUPUS		LUPUS			4584
-leap101			MACH_LEAP101		LEAP101			4585
-cm_t335			MACH_CM_T335		CM_T335			4586
-pna			MACH_PNA		PNA			4587
-ecoforest_cpu2013	MACH_ECOFOREST_CPU2013	ECOFOREST_CPU2013	4588
-apq8064_dma		MACH_APQ8064_DMA	APQ8064_DMA		4589
-mx53_armour		MACH_MX53_ARMOUR	MX53_ARMOUR		4590
-eurofunk_aepl3		MACH_EUROFUNK_AEPL3	EUROFUNK_AEPL3		4591
-eurofunk_mhls3		MACH_EUROFUNK_MHLS3	EUROFUNK_MHLS3		4592
-eurofunk_e1if		MACH_EUROFUNK_E1IF	EUROFUNK_E1IF		4593
-lepus			MACH_LEPUS		LEPUS			4594
-bora			MACH_BORA		BORA			4595
-ads4011			MACH_ADS4011		ADS4011			4596
-beaver			MACH_BEAVER		BEAVER			4597
-imx233_iungo		MACH_IMX233_IUNGO	IMX233_IUNGO		4598
-cepheus			MACH_CEPHEUS		CEPHEUS			4599
-cetus			MACH_CETUS		CETUS			4600
-chamaeleon		MACH_CHAMAELEON		CHAMAELEON		4601
-ardbeg			MACH_ARDBEG		ARDBEG			4602
-ixora			MACH_IXORA		IXORA			4603
-juglans			MACH_JUGLANS		JUGLANS			4604
-canismajor		MACH_CANISMAJOR		CANISMAJOR		4605
-at91sam9263mib		MACH_AT91SAM9263MIB	AT91SAM9263MIB		4606
-cosino_9g35		MACH_COSINO_9G35	COSINO_9G35		4607
-tiny4412		MACH_TINY4412		TINY4412		4608
-balloon4		MACH_BALLOON4		BALLOON4		4609
-pgg			MACH_PGG		PGG			4610
-xxsq701			MACH_XXSQ701		XXSQ701			4611
-mx6_navico_rdr		MACH_MX6_NAVICO_RDR	MX6_NAVICO_RDR		4612
-phantom			MACH_PHANTOM		PHANTOM			4613
-canisminorh		MACH_CANISMINORH	CANISMINORH		4614
-carina			MACH_CARINA		CARINA			4615
-e1859			MACH_E1859		E1859			4616
-armstonea5		MACH_ARMSTONEA5		ARMSTONEA5		4617
-picocoma5		MACH_PICOCOMA5		PICOCOMA5		4618
-netdcua5		MACH_NETDCUA5		NETDCUA5		4619
-molly			MACH_MOLLY		MOLLY			4620
-maserati		MACH_MASERATI		MASERATI		4621
-mx53_idebx		MACH_MX53_IDEBX		MX53_IDEBX		4622
-mx53_c2cb		MACH_MX53_C2CB		MX53_C2CB		4623
-mipsee			MACH_MIPSEE		MIPSEE			4624
-seeklop			MACH_SEEKLOP		SEEKLOP			4625
-audisee			MACH_AUDISEE		AUDISEE			4626
-tx48			MACH_TX48		TX48			4627
-tl7689_pad_aurora	MACH_TL7689_PAD_REF	TL7689_PAD_REF		4628
-tl7689_pad_test		MACH_TL7689_PAD_TEST	TL7689_PAD_TEST		4629
-tl7689_phone_ref	MACH_TL7689_PHONE_REF	TL7689_PHONE_REF	4630
-tl7689_phone_test	MACH_TL7689_PHONE_TEST	TL7689_PHONE_TEST	4631
-swarco_scc_wks		MACH_SWARCO_SCC_WKS	SWARCO_SCC_WKS		4632
-accordo2		MACH_ACCORDO2		ACCORDO2		4633
-trizeps7		MACH_TRIZEPS7		TRIZEPS7		4634
-f100			MACH_F100		F100			4635
-armadillo410		MACH_ARMADILLO410	ARMADILLO410		4636
-tiny2416		MACH_TINY2416		TINY2416		4637
-tiny2451		MACH_TINY2451		TINY2451		4638
-mini2451		MACH_MINI2451		MINI2451		4639
-tiny5250		MACH_TINY5250		TINY5250		4640
-tiny3358		MACH_TINY3358		TINY3358		4641
-cassiopeia		MACH_T6_UL		T6_UL			4642
-columba			MACH_T6_U		T6_U			4643
-delphinus		MACH_T6_ULA		T6_ULA			4644
-crater			MACH_T6_WL		T6_WL			4645
-eridanus		MACH_T6_WHL		T6_WHL			4646
-circinus		MACH_CIRCINUS		CIRCINUS		4647
-socpk255		MACH_SOCPK255		SOCPK255		4648
-socprv270		MACH_SOCPRV270		SOCPRV270		4649
-socprc270		MACH_SOCPRC270		SOCPRC270		4650
-induses			MACH_MACH_CP5DTU	MACH_CP5DTU		4651
-hercules		MACH_CP5DTU		CP5DTU			4652
-horologium		MACH_CP5DUG		CP5DUG			4653
-hydrus			MACH_CP5DWG		CP5DWG			4654
-am335x_egf		MACH_AM335X_EGF		AM335X_EGF		4655
-azm9g45			MACH_AZM9G45		AZM9G45			4656
-azm335x			MACH_AZM335X		AZM335X			4657
-lynbrd			MACH_LYNBRD		LYNBRD			4658
-am35x_egf		MACH_AM35X_EGF		AM35X_EGF		4659
-sevulcan		MACH_SEVULCAN		SEVULCAN		4660
-ax8008m			MACH_AX8008M		AX8008M			4661
-ax8008mr		MACH_AX8008MR		AX8008MR		4662
-xynix			MACH_XYNIX		XYNIX			4663
-omap3621_odyv4		MACH_OMAP3621_ODYV4	OMAP3621_ODYV4		4664
-mx6_cameronet		MACH_MX6_CAMERONET	MX6_CAMERONET		4665
-omap4_dart		MACH_OMAP4_DART		OMAP4_DART		4666
-mx6q_enzo		MACH_MX6Q_ENZO		MX6Q_ENZO		4667
-ev_imx287micro		MACH_EV_IMX287MICRO	EV_IMX287MICRO		4668
-ev_imx287mini		MACH_EV_IMX287MINI	EV_IMX287MINI		4669
-mx53_cec2		MACH_MX53_CEC2		MX53_CEC2		4670
-helios_v8		MACH_HELIOS_V8		HELIOS_V8		4671
-helios_v9		MACH_HELIOS_V9		HELIOS_V9		4672
-cognac			MACH_COGNAC		COGNAC			4673
-zest			MACH_ZEST		ZEST			4674
-gc3			MACH_GC3		GC3			4675
-dad_media		MACH_DAD_MEDIA		DAD_MEDIA		4676
-htouch			MACH_HTOUCH		HTOUCH			4677
-spt7500baseboard	MACH_SPT7500BASEBOARD	SPT7500BASEBOARD	4678
-omap4_dart_evm		MACH_OMAP4_DART_EVM	OMAP4_DART_EVM		4679
-mx53_tlv		MACH_MX53_TLV		MX53_TLV		4680
-pdak2h			MACH_PDAK2H		PDAK2H			4681
-matrix513		MACH_MATRIX513		MATRIX513		4682
-livebox01		MACH_LIVEBOX01		LIVEBOX01		4683
-cevrza1l		MACH_CEVRZA1L		CEVRZA1L		4684
-b1010			MACH_B1010		B1010			4685
-fwtmk1			MACH_FWTMK1		FWTMK1			4686
-grenada			MACH_GRENADA		GRENADA			4687
-hassel			MACH_HASSEL		HASSEL			4688
-odroidxu		MACH_ODROIDXU		ODROIDXU		4689
-odroidu2		MACH_ODROIDU2		ODROIDU2		4690
-naiad			MACH_NAIAD		NAIAD			4691
-harrier			MACH_HARRIER		HARRIER			4692
-pcl052			MACH_PCL052		PCL052			4693
-libra2404		MACH_LIBRA2404		LIBRA2404		4694
-mx6_lemonboard		MACH_MX6_LEMONBOARD	MX6_LEMONBOARD		4695
-mx6_atlas		MACH_MX6_ATLAS		MX6_ATLAS		4696
-elecsys_z2		MACH_ELECSYS_Z2		ELECSYS_Z2		4697
-elecsys_z4		MACH_ELECSYS_Z4		ELECSYS_Z4		4698
-ipq806x_db149		MACH_IPQ806X_DB149	IPQ806X_DB149		4699
-pulsar			MACH_PULSAR		PULSAR			4700
-scalancem		MACH_SCALANCEM		SCALANCEM		4701
-na11			MACH_NA11		NA11			4702
-ipq806x_db147		MACH_IPQ806X_DB147	IPQ806X_DB147		4703
-ipq806x_ap148		MACH_IPQ806X_AP148	IPQ806X_AP148		4704
-amltd_imx6		MACH_AMLTD_IMX6		AMLTD_IMX6		4705
-pia_am335x		MACH_PIA_AM335X		PIA_AM335X		4706
-blade			MACH_BLADE		BLADE			4707
-matisse			MACH_MATISSE		MATISSE			4708
-ikebana			MACH_IKEBANA		IKEBANA			4709
-lf3000			MACH_LF3000		LF3000			4710
-carallon_stingray	MACH_CARALLON_STINGRAY	CARALLON_STINGRAY	4711
-mensa			MACH_MENSA		MENSA			4712
-ces_coreboard		MACH_CES_COREBOARD	CES_COREBOARD		4713
-vybrid_iwg16m_umxm	MACH_VYBRID_IWG16M_UMXM	VYBRID_IWG16M_UMXM	4714
-loki			MACH_LOKI		LOKI			4715
-pcm053			MACH_PCM053		PCM053			4716
-smm200			MACH_SMM200		SMM200			4717
-m507			MACH_M507		M507			4718
-orsoc_armsoc_8695	MACH_ORSOC_ARMSOC_8695	ORSOC_ARMSOC_8695	4719
-am335x_zy		MACH_AM335X_ZY		AM335X_ZY		4720
-arrakis			MACH_ARRAKIS		ARRAKIS			4721
-sxlt			MACH_SXLT		SXLT			4722
-ylcm			MACH_YLCM		YLCM			4723
-eagle6d			MACH_EAGLE6D		EAGLE6D			4724
-lcu1			MACH_LCU1		LCU1			4725
-mx6dl_iwg15m_q7		MACH_MX6DL_IWG15M_Q7	MX6DL_IWG15M_Q7		4726
-sbc_phyflex_am335	MACH_SBCPHYFLEXAM335	SBCPHYFLEXAM335		4727
-sbc_phycard_am335	MACH_SBCPHYCARDAM335	SBCPHYCARDAM335		4728
-sbc_phyflex_imx6	MACH_SBCPHYFLEXIMX6	SBCPHYFLEXIMX6		4729
-homeserverstick		MACH_HOMESERVERSTICK	HOMESERVERSTICK		4730
-ecxec			MACH_ECXEC		ECXEC			4731
-hh300			MACH_HH300		HH300			4732
-cpuca8			MACH_CPUCA8		CPUCA8			4733
-a0057_lsembeddedpc	MACH_A0057_LSEMBEDDEDPC	A0057_LSEMBEDDEDPC	4734
-iproc			MACH_IPROC		IPROC			4735
-nemesis_nfe		MACH_NEMESIS_NFE	NEMESIS_NFE		4736
-mabv3x25		MACH_MABV3X25		MABV3X25		4737
-octant			MACH_OCTANT		OCTANT			4738
-msm7x27_thunder		MACH_MSM7X27_THUNDER	MSM7X27_THUNDER		4739
-maxim			MACH_MAXIM		MAXIM			4740
-telematicctrlunit	MACH_TELEMATICCTRLUNIT	TELEMATICCTRLUNIT	4741
-mx6q_jcdbox		MACH_MX6Q_JCDBOX	MX6Q_JCDBOX		4742
-ckb_1808		MACH_CKB_1808		CKB_1808		4743
-ckb_3352		MACH_CKB_3352		CKB_3352		4744
-hikirk			MACH_HIKIRK		HIKIRK			4745
-dns320l			MACH_DNS320L		DNS320L			4746
-stm_b2120		MACH_STM_B2120		STM_B2120		4747
-stm_b2089		MACH_STM_B2089		STM_B2089		4748
-colibri_vf50		MACH_COLIBRI_VF50	COLIBRI_VF50		4749
-colibri_vf61		MACH_COLIBRI_VF61	COLIBRI_VF61		4750
-synergy2		MACH_SYNERGY2		SYNERGY2		4751
-pcm051_hmi		MACH_PCM051_HMI		PCM051_HMI		4752
-tek2			MACH_TEK2		TEK2			4753
-duckbill		MACH_DUCKBILL		DUCKBILL		4754
-mx50_seismic		MACH_MX50_SEISMIC	MX50_SEISMIC		4755
-twoface			MACH_TWOFACE		TWOFACE			4756
-t10			MACH_T10		T10			4757
-lib1313			MACH_LIB1313		LIB1313			4758
-himx			MACH_HIMX		HIMX			4759
-vcm30_t30		MACH_VCM30_T30		VCM30_T30		4760
-cornerview		MACH_CORNERVIEW		CORNERVIEW		4761
-p01600			MACH_P01600		P01600			4762
-axel			MACH_AXEL		AXEL			4763
-imx6_andy		MACH_IMX6_ANDY		IMX6_ANDY		4764
-nsa220			MACH_NSA220		NSA220			4765
-ti8168hsc1		MACH_TI8168HSC1		TI8168HSC1		4766
-dory			MACH_DORY		DORY			4767
-ecv4			MACH_ECV4		ECV4			4768
-webbg3flight		MACH_WEBBG3FLIGHT	WEBBG3FLIGHT		4769
-sbc_phycore_am335x	MACH_SBC_PHYCORE_AM335X	SBC_PHYCORE_AM335X	4770
-tsc			MACH_TSC		TSC			4771