diff options
Diffstat (limited to 'arch/arm')
67 files changed, 1878 insertions, 2758 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5db67b9db8..2d55bc69a3 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -246,7 +246,6 @@ barebox.imximg: $(KBUILD_BINARY) FORCE boarddir = $(srctree)/arch/arm/boards imxcfg-$(CONFIG_MACH_FREESCALE_MX53_SMD) += $(boarddir)/freescale-mx53-smd/flash-header.imxcfg -imxcfg-$(CONFIG_MACH_CCMX51) += $(boarddir)/ccxmx51/flash-header.imxcfg imxcfg-$(CONFIG_MACH_TX51) += $(boarddir)/karo-tx51/flash-header-karo-tx51.imxcfg imxcfg-$(CONFIG_MACH_GUF_VINCELL) += $(boarddir)/guf-vincell/flash-header.imxcfg imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += $(boarddir)/eukrea_cpuimx51/flash-header.imxcfg diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 3bf176b14d..b546274244 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -157,3 +157,4 @@ obj-$(CONFIG_MACH_ZII_RDU1) += zii-imx51-rdu1/ obj-$(CONFIG_MACH_ZII_RDU2) += zii-imx6q-rdu2/ obj-$(CONFIG_MACH_ZII_VF610_DEV) += zii-vf610-dev/ obj-$(CONFIG_MACH_ZII_IMX7D_RPU2) += zii-imx7d-rpu2/ +obj-$(CONFIG_MACH_WAGO_PFC_AM35XX) += wago-pfc-am35xx/ diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile index 66083a239e..d4d5e76395 100644 --- a/arch/arm/boards/at91sam9263ek/Makefile +++ b/arch/arm/boards/at91sam9263ek/Makefile @@ -1,7 +1,7 @@ ifeq ($(CONFIG_OFDEVICE),) obj-y += init.o endif -obj-$(CONFIG_OF_DEVICE) += of_init.o +obj-$(CONFIG_OFDEVICE) += of_init.o lwl-y += lowlevel_init.o diff --git a/arch/arm/boards/ccxmx51/Makefile b/arch/arm/boards/ccxmx51/Makefile index 6ba98b12de..50cf929c5d 100644 --- a/arch/arm/boards/ccxmx51/Makefile +++ b/arch/arm/boards/ccxmx51/Makefile @@ -1,3 +1,3 @@ obj-y += ccxmx51.o -lwl-y += lowlevel.o -obj-$(CONFIG_MACH_CCMX51_BASEBOARD) += ccxmx51js.o +lwl-y += lowlevel.o +bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-ccxmx51 diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c index 71a51e1927..13fba51fec 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51.c +++ b/arch/arm/boards/ccxmx51/ccxmx51.c @@ -1,477 +1,279 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2009-2010 Digi International, Inc. * Copyright (C) 2007 Sascha Hauer, Pengutronix * (c) 2011 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * + * Modified for barebox by Alexander Shiyan <shc_work@mail.ru> */ #include <common.h> -#include <net.h> +#include <envfs.h> #include <init.h> -#include <environment.h> -#include <mach/imx51-regs.h> -#include <platform_data/eth-fec.h> +#include <net.h> +#include <notifier.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <fs.h> -#include <fcntl.h> #include <linux/sizes.h> -#include <nand.h> -#include <notifier.h> -#include <spi/spi.h> #include <mfd/mc13xxx.h> -#include <asm/io.h> -#include <mach/imx-nand.h> -#include <mach/spi.h> -#include <mach/generic.h> -#include <mach/iomux-mx51.h> -#include <mach/devices-imx51.h> +#include <mfd/mc13892.h> + +#include <mach/bbu.h> +#include <mach/esdctl.h> #include <mach/iim.h> -#include <mach/clock-imx51_53.h> #include <mach/imx5.h> +#include <mach/imx51-regs.h> #include <mach/revision.h> -#include <mach/esdctl.h> - -#include "ccxmx51.h" - -static struct ccxmx51_ident ccxmx51_ids[] = { -/* 0x00 */ { "Unknown", 0, 0, 0, 0, 0 }, -/* 0x01 */ { "Not supported", 0, 0, 0, 0, 0 }, -/* 0x02 */ { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 1 }, -/* 0x03 */ { "i.MX515@800MHz, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 0 }, -/* 0x04 */ { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 1 }, -/* 0x05 */ { "i.MX515@600MHz, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 0 }, -/* 0x06 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 }, -/* 0x07 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 }, -/* 0x08 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_256M, 0, 1, 0, 1 }, -/* 0x09 */ { "i.MX515@800MHz, PHY, Accel", SZ_256M, 0, 1, 0, 0 }, -/* 0x0a */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_256M, 1, 1, 0, 1 }, -/* 0x0b */ { "i.MX515@600MHz, PHY, Accel", SZ_256M, 1, 1, 0, 0 }, -/* 0x0c */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_128M, 0, 1, 0, 1 }, -/* 0x0d */ { "i.MX512@800MHz", SZ_128M, 0, 0, 0, 0 }, -/* 0x0e */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 }, -/* 0x0f */ { "i.MX515@600MHz, PHY, Accel", SZ_128M, 1, 1, 0, 0 }, -/* 0x10 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_128M, 1, 1, 0, 1 }, -/* 0x11 */ { "i.MX515@800MHz, PHY, Accel", SZ_128M, 0, 1, 0, 0 }, -/* 0x12 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_512M, 1, 1, 0, 1 }, -/* 0x13 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 }, -}; - -struct ccxmx51_ident *ccxmx51_id; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 7, -}; -static iomux_v3_cfg_t ccxmx51_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - /* UART3 */ - MX51_PAD_UART3_RXD__UART3_RXD, - MX51_PAD_UART3_TXD__UART3_TXD, - /* I2C2 */ - MX51_PAD_GPIO1_2__I2C2_SCL, - MX51_PAD_GPIO1_3__I2C2_SDA, - /* eCSPI1 */ - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_CSPI1_RDY__ECSPI1_RDY, - MX51_PAD_CSPI1_SS0__ECSPI1_SS0, - MX51_PAD_CSPI1_SS1__ECSPI1_SS1, - /* FEC */ - MX51_PAD_DISP2_DAT14__FEC_RDATA0, - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1, - MX51_PAD_DI_GP4__FEC_RDATA2, - MX51_PAD_DISP2_DAT0__FEC_RDATA3, - MX51_PAD_DISP2_DAT15__FEC_TDATA0, - MX51_PAD_DISP2_DAT6__FEC_TDATA1, - MX51_PAD_DISP2_DAT7__FEC_TDATA2, - MX51_PAD_DISP2_DAT8__FEC_TDATA3, - MX51_PAD_DISP2_DAT9__FEC_TX_EN, - MX51_PAD_DISP2_DAT10__FEC_COL, - MX51_PAD_DISP2_DAT11__FEC_RX_CLK, - MX51_PAD_DISP2_DAT12__FEC_RX_DV, - MX51_PAD_DISP2_DAT13__FEC_TX_CLK, - MX51_PAD_DI2_PIN2__FEC_MDC, - MX51_PAD_DI2_PIN4__FEC_CRS, - MX51_PAD_DI2_PIN3__FEC_MDIO, - MX51_PAD_DI_GP3__FEC_TX_ER, - MX51_PAD_DISP2_DAT1__FEC_RX_ER, - /* WEIM */ - MX51_PAD_EIM_DA0__EIM_DA0, - MX51_PAD_EIM_DA1__EIM_DA1, - MX51_PAD_EIM_DA2__EIM_DA2, - MX51_PAD_EIM_DA3__EIM_DA3, - MX51_PAD_EIM_DA4__EIM_DA4, - MX51_PAD_EIM_DA5__EIM_DA5, - MX51_PAD_EIM_DA6__EIM_DA6, - MX51_PAD_EIM_DA7__EIM_DA7, - MX51_PAD_EIM_D16__EIM_D16, - MX51_PAD_EIM_D17__EIM_D17, - MX51_PAD_EIM_D18__EIM_D18, - MX51_PAD_EIM_D19__EIM_D19, - MX51_PAD_EIM_D20__EIM_D20, - MX51_PAD_EIM_D21__EIM_D21, - MX51_PAD_EIM_D22__EIM_D22, - MX51_PAD_EIM_D23__EIM_D23, - MX51_PAD_EIM_D24__EIM_D24, - MX51_PAD_EIM_D25__EIM_D25, - MX51_PAD_EIM_D26__EIM_D26, - MX51_PAD_EIM_D27__EIM_D27, - MX51_PAD_EIM_D28__EIM_D28, - MX51_PAD_EIM_D29__EIM_D29, - MX51_PAD_EIM_D30__EIM_D30, - MX51_PAD_EIM_D31__EIM_D31, - MX51_PAD_EIM_OE__EIM_OE, - MX51_PAD_EIM_CS5__EIM_CS5, - /* NAND */ - MX51_PAD_NANDF_D0__NANDF_D0, - MX51_PAD_NANDF_D1__NANDF_D1, - MX51_PAD_NANDF_D2__NANDF_D2, - MX51_PAD_NANDF_D3__NANDF_D3, - MX51_PAD_NANDF_D4__NANDF_D4, - MX51_PAD_NANDF_D5__NANDF_D5, - MX51_PAD_NANDF_D6__NANDF_D6, - MX51_PAD_NANDF_D7__NANDF_D7, - MX51_PAD_NANDF_ALE__NANDF_ALE, - MX51_PAD_NANDF_CLE__NANDF_CLE, - MX51_PAD_NANDF_RE_B__NANDF_RE_B, - MX51_PAD_NANDF_WE_B__NANDF_WE_B, - MX51_PAD_NANDF_WP_B__NANDF_WP_B, - MX51_PAD_NANDF_CS0__NANDF_CS0, - MX51_PAD_NANDF_RB0__NANDF_RB0, - /* LAN9221 IRQ (GPIO1.9) */ - MX51_PAD_GPIO1_9__GPIO1_9, - /* MC13892 IRQ (GPIO1.5) */ - MX51_PAD_GPIO1_5__GPIO1_5, - /* MMA7455LR IRQ1 (GPIO1.7) */ - MX51_PAD_GPIO1_7__GPIO1_7, - /* MMA7455LR IRQ2 (GPIO1.6) */ - MX51_PAD_GPIO1_6__GPIO1_6, - /* User GPIOs */ - MX51_PAD_GPIO1_0__GPIO1_0, - MX51_PAD_GPIO1_1__GPIO1_1, - MX51_PAD_GPIO1_8__GPIO1_8, - MX51_PAD_DI1_PIN11__GPIO3_0, - MX51_PAD_DI1_PIN12__GPIO3_1, - MX51_PAD_DI1_PIN13__GPIO3_2, - MX51_PAD_DI1_D0_CS__GPIO3_3, - MX51_PAD_DI1_D1_CS__GPIO3_4, - MX51_PAD_DISPB2_SER_DIN__GPIO3_5, - MX51_PAD_DISPB2_SER_DIO__GPIO3_6, - MX51_PAD_DISPB2_SER_CLK__GPIO3_7, - MX51_PAD_DISPB2_SER_RS__GPIO3_8, - MX51_PAD_NANDF_RB1__GPIO3_9, - MX51_PAD_NANDF_RB2__GPIO3_10, - MX51_PAD_NANDF_RB3__GPIO3_11, - MX51_PAD_CSI1_D8__GPIO3_12, - MX51_PAD_CSI1_D9__GPIO3_13, - MX51_PAD_NANDF_CS1__GPIO3_17, - MX51_PAD_NANDF_CS2__GPIO3_18, - MX51_PAD_NANDF_CS3__GPIO3_19, - MX51_PAD_NANDF_CS4__GPIO3_20, - MX51_PAD_NANDF_CS5__GPIO3_21, - MX51_PAD_NANDF_CS6__GPIO3_22, +static const struct ccxmx_ident { + char *id_string; + unsigned int mem_sz; + unsigned int cpu_mhz; + unsigned char eth0:1; + unsigned char eth1:1; + unsigned char wless:1; + unsigned char accel:1; +} *ccxmx_id, ccxmx51_ids[] = { + [0x00] = { NULL /* Unknown */, 0, 0, 0, 0, 0, 0 }, + [0x01] = { NULL /* Not supported */, 0, 0, 0, 0, 0, 0 }, + [0x02] = { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 800, 1, 1, 1, 1 }, + [0x03] = { "i.MX515@800MHz, PHY, Ext. Eth, Accel", SZ_512M, 800, 1, 1, 0, 1 }, + [0x04] = { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 600, 1, 1, 1, 1 }, + [0x05] = { "i.MX515@600MHz, PHY, Ext. Eth, Accel", SZ_512M, 600, 1, 1, 0, 1 }, + [0x06] = { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 800, 1, 0, 1, 1 }, + [0x07] = { "i.MX515@800MHz, PHY, Accel", SZ_512M, 800, 1, 0, 0, 1 }, + [0x08] = { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_256M, 800, 1, 0, 1, 1 }, + [0x09] = { "i.MX515@800MHz, PHY, Accel", SZ_256M, 800, 1, 0, 0, 1 }, + [0x0a] = { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_256M, 600, 1, 0, 1, 1 }, + [0x0b] = { "i.MX515@600MHz, PHY, Accel", SZ_256M, 600, 1, 0, 0, 1 }, + [0x0c] = { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_128M, 800, 1, 0, 1, 1 }, + [0x0d] = { "i.MX512@800MHz", SZ_128M, 800, 0, 0, 0, 0 }, + [0x0e] = { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 800, 1, 0, 1, 1 }, + [0x0f] = { "i.MX515@600MHz, PHY, Accel", SZ_128M, 600, 1, 0, 0, 1 }, + [0x10] = { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_128M, 600, 1, 0, 1, 1 }, + [0x11] = { "i.MX515@800MHz, PHY, Accel", SZ_128M, 800, 1, 0, 0, 1 }, + [0x12] = { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_512M, 600, 1, 0, 1, 1 }, + [0x13] = { "i.MX515@800MHz, PHY, Accel", SZ_512M, 800, 1, 0, 0, 1 }, }; -#define CCXMX51_ECSPI1_CS0 IMX_GPIO_NR(4, 24) -#define CCXMX51_ECSPI1_CS1 IMX_GPIO_NR(4, 25) +static u32 boardserial; -static int ecspi_0_cs[] = { CCXMX51_ECSPI1_CS0, CCXMX51_ECSPI1_CS1, }; - -static struct spi_imx_master ecspi_0_data = { - .chipselect = ecspi_0_cs, - .num_chipselect = ARRAY_SIZE(ecspi_0_cs), -}; - -static const struct spi_board_info ccxmx51_spi_board_info[] = { - { - .name = "mc13892", - .bus_num = 0, - .chip_select = 0, - }, -}; - -static struct imxusb_platformdata ccxmx51_otg_pdata = { - .flags = MXC_EHCI_MODE_UTMI_16_BIT | MXC_EHCI_POWER_PINS_ENABLED, - .mode = IMX_USB_MODE_HOST, -}; - -static int ccxmx51_power_init(void) +static void ccxmx51_power_init(struct mc13xxx *mc13xxx) { - struct mc13xxx *mc13xxx_dev; u32 val; - mc13xxx_dev = mc13xxx_get(); - if (!mc13xxx_dev) - return -ENODEV; - - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_MISC, &val); - /* Reset devices by clearing GP01-GPO4 */ - val &= ~((1 << 21) | (3 << 12) | (3 << 10) | (3 << 8) | (3 << 6)); - /* Switching off the PWGT1SPIEN */ - val |= (1 << 15); - /* Switching on the PWGT2SPIEN */ - val &= ~(1 << 16); - /* Enable short circuit protection */ - val |= (1 << 0); - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_MISC, val); - - /* Allow charger to charge (4.2V and 560mA) */ - val = 0x238033; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_CHARGE, val); - - if (imx_silicon_revision() < IMX_CHIP_REV_3_0) { - /* Set core voltage (SW1) to 1.1V */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_0, &val); - val &= ~0x00001f; - val |= 0x000014; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_0, val); - - /* Setup VCC (SW2) to 1.25 */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_1, &val); - val &= ~0x00001f; - val |= 0x00001a; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_1, val); - - /* Setup 1V2_DIG1 (SW3) to 1.25 */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_2, &val); - val &= ~0x00001f; - val |= 0x00001a; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_2, val); - } else { - /* Setup VCC (SW2) to 1.225 */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_1, &val); - val &= ~0x00001f; - val |= 0x000019; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_1, val); - - /* Setup 1V2_DIG1 (SW3) to 1.2 */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_2, &val); - val &= ~0x00001f; - val |= 0x000018; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_2, val); - } - - if (mc13xxx_revision(mc13xxx_dev) <= MC13892_REVISION_2_0) { - /* Set switchers in PWM mode for Atlas 2.0 and lower */ - /* Setup the switcher mode for SW1 & SW2*/ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_4, &val); - val &= ~0x003c0f; - val |= 0x001405; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_5, &val); - val &= ~0x000f0f; - val |= 0x000505; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_5, val); - } else { - /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ - /* Setup the switcher mode for SW1 & SW2*/ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_4, &val); - val &= ~0x003c0f; - val |= 0x002008; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_5, &val); - val &= ~0x000f0f; - val |= 0x000808; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_5, val); - } - - /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SETTING_1, &val); - val &= ~0x0001fc; - val |= 0x0001f4; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SETTING_1, val); + /* Clear GP01-GPO4, enable short circuit protection, PWGT1SPIEN off */ + val = MC13892_POWER_MISC_REGSCPEN | MC13892_POWER_MISC_PWGT1SPIEN; + val |= MC13892_POWER_MISC_GPO4ADIN; + mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val); + + /* Set ICHRG in externally powered mode, 4.2V, Disable thermistor */ + mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0xa3827b); + + /* Set core voltage (SW1) to 1.1V NORMAL, 1.05V STANDBY */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val); + val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE1_SHIFT); + val |= MC13892_SWx_SWx_1_100V << MC13892_SWMODE1_SHIFT; + val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE2_SHIFT); + val |= MC13892_SWx_SWx_1_050V << MC13892_SWMODE2_SHIFT; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val); + + /* Setup VCC (SW2) to 1.225 NORMAL, 1.175V STANDBY */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val); + val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE1_SHIFT); + val |= MC13892_SWx_SWx_1_225V << MC13892_SWMODE1_SHIFT; + val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE2_SHIFT); + val |= MC13892_SWx_SWx_1_175V << MC13892_SWMODE2_SHIFT; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.2 NORMAL, 1.15V STANDBY */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val); + val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE1_SHIFT); + val |= MC13892_SWx_SWx_1_200V << MC13892_SWMODE1_SHIFT; + val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE2_SHIFT); + val |= MC13892_SWx_SWx_1_150V << MC13892_SWMODE2_SHIFT; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); + + /* Set SW1-SW4 switcher in Auto in NORMAL & STANDBY mode */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); + val &= ~(MC13892_SWMODE_MASK << MC13892_SWMODE1_SHIFT); + val |= MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE1_SHIFT; + val &= ~(MC13892_SWMODE_MASK << MC13892_SWMODE2_SHIFT); + val |= MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE2_SHIFT; + /* Disable current limit */ + val |= 1 << 22; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val); + + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val); + val &= ~(MC13892_SWMODE_MASK << MC13892_SWMODE3_SHIFT); + val |= MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE3_SHIFT; + val &= ~(MC13892_SWMODE_MASK << MC13892_SWMODE4_SHIFT); + val |= MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE4_SHIFT; + /* Enable SWBST */ + val |= 1 << 20; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val); + + /* Set VVIDEO=2.775V, VAUDIO=3V, VSD=3.15V */ + val = MC13892_SETTING_1_VVIDEO_2_775 | MC13892_SETTING_1_VAUDIO_3_0; + val |= MC13892_SETTING_1_VSD_3_15; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val); /* Configure VGEN3 and VCAM regulators to use external PNP */ - val = 0x000208; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_MODE_1, val); + val = MC13892_MODE_1_VGEN3CONFIG | MC13892_MODE_1_VCAMCONFIG; + mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); udelay(200); - /* Set VGEN3 to 1.8V */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SETTING_0, &val); - val &= ~(1 << 14); - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SETTING_0, val); + /* Set VGEN2=3.15V, VGEN3=1.8V, VDIG=1.25V, VCAM=2.75V */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val); + val &= ~(MC13892_SETTING_0_VGEN2_MASK | MC13892_SETTING_0_VGEN3_MASK); + val |= MC13892_SETTING_0_VGEN2_3_15 | MC13892_SETTING_0_VGEN3_1_8; + val &= ~(MC13892_SETTING_0_VDIG_MASK | MC13892_SETTING_0_VCAM_MASK); + val |= MC13892_SETTING_0_VDIG_1_25 | MC13892_SETTING_0_VCAM_2_75; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val); - /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ - val = 0x049249; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_MODE_1, val); + /* Enable OTG function */ + mc13xxx_reg_write(mc13xxx, MC13892_REG_USB1, 0x409); - /* Enable USB1 charger */ - val = 0x000409; - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_USB1, val); - - /* Set VCOIN to 3.0V and Enable It */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_CTL0, &val); + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = MC13892_MODE_1_VGEN3EN | MC13892_MODE_1_VGEN3CONFIG; + val |= MC13892_MODE_1_VCAMEN | MC13892_MODE_1_VCAMCONFIG; + val |= MC13892_MODE_1_VVIDEOEN | MC13892_MODE_1_VAUDIOEN; + val |= MC13892_MODE_1_VSDEN; + mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); + + /* Set VCOIN=3.0V, Keeps VSRTC and CLK32KMCU */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_CTL0, &val); val &= ~(7 << 20); - val |= (4 << 20) | (1 << 23); - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_CTL0, val); - /* Keeps VSRTC and CLK32KMCU */ - val |= (1 << 4); - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_CTL0, val); - - /* De-assert reset of external devices on GP01, GPO2, GPO3 and GPO4 */ - mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_MISC, &val); + val |= (1 << 4) | (4 << 20) | (1 << 23); + mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_CTL0, val); + + /* De-assert reset of external devices on GP01-GPO4 */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val); /* GPO1 - External */ /* GP02 - LAN9221 Power */ /* GP03 - FEC Reset */ /* GP04 - Wireless Power */ - if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X) && ccxmx51_id->eth1) { - val |= (1 << 8); - mdelay(50); + if (ccxmx_id->eth1) { + val |= MC13892_POWER_MISC_GPO2EN; + mdelay(100); } - if (IS_ENABLED(CONFIG_DRIVER_NET_FEC_IMX) && ccxmx51_id->eth0) - val |= (1 << 10); - if (ccxmx51_id->wless) - val |= (1 << 12); - mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_MISC, val); + if (ccxmx_id->eth0) + val |= MC13892_POWER_MISC_GPO3EN; + if (ccxmx_id->wless) + val |= MC13892_POWER_MISC_GPO4EN; + mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val); udelay(100); - return 0; + console_flush(); + imx51_init_lowlevel(ccxmx_id->cpu_mhz); + clock_notifier_call_chain(); + + printf("MC13892 PMIC initialized.\n"); } -/* - * On this board the SDRAM is always configured for 512Mib. The real - * size is determined by the board id read from the IIM module. - */ -static int ccxmx51_sdram_fixup(void) +static void ccxmx51_disable_device(struct device_node *root, const char *label) { - imx_esdctl_disable(); + struct device_node *np = of_find_node_by_name(root, label); + if (np) + of_device_disable(np); +} + +static int ccxmx51_board_fixup(struct device_node *root, void *unused) +{ + char *serial; + + if (!ccxmx_id->accel) + ccxmx51_disable_device(root, "mma7455l@1d"); + + if (!ccxmx_id->eth0) + ccxmx51_disable_device(root, "ethernet@83fec000"); + + if (!ccxmx_id->eth1) + ccxmx51_disable_device(root, "lan9221@5,0"); + + if (!ccxmx_id->wless) + ccxmx51_disable_device(root, "esdhc@70008000"); + + serial = basprintf("%08x%08x", 0, boardserial); + of_set_property(root, "serial-number", serial, strlen(serial) + 1, 1); + free(serial); return 0; } -postcore_initcall(ccxmx51_sdram_fixup); -static int ccxmx51_memory_init(void) +static __init int ccxmx51_is_compatible(void) { + return of_machine_is_compatible("digi,connectcore-ccxmx51-som"); +} + +static __init int ccxmx51_sdram_fixup(void) +{ + if (!ccxmx51_is_compatible()) + return 0; + arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, SZ_128M); + /* + * On this board the SDRAM is always configured for 512Mib. The real + * size is determined by the board id read from the IIM module. + */ + imx_esdctl_disable(); + + of_register_fixup(ccxmx51_board_fixup, NULL); + return 0; } -mem_initcall(ccxmx51_memory_init); +postcore_initcall(ccxmx51_sdram_fixup); -static int ccxmx51_devices_init(void) +static __init int ccxmx51_init(void) { + char manloc = 'N'; u8 hwid[6]; - int pwr; - char manloc; - - if ((imx_iim_read(1, 9, hwid, sizeof(hwid)) != sizeof(hwid)) || (hwid[0] < 0x02) || (hwid[0] >= ARRAY_SIZE(ccxmx51_ids))) - memset(hwid, 0x00, sizeof(hwid)); - - ccxmx51_id = &ccxmx51_ids[hwid[0]]; - printf("Module Variant: %s (0x%02x)\n", ccxmx51_id->id_string, hwid[0]); - - if (hwid[0]) { - printf("Module HW Rev : %02x\n", hwid[1] + 1); - switch (hwid[2] & 0xc0) { - case 0x00: - manloc = 'B'; - break; - case 0x40: - manloc = 'W'; - break; - case 0x80: - manloc = 'S'; - break; - default: - manloc = 'N'; - break; - } - printf("Module Serial : %c%d\n", manloc, ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]); - if ((ccxmx51_id->mem_sz - SZ_128M) > 0) - arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M, ccxmx51_id->mem_sz - SZ_128M); - } else - return -ENOSYS; - - imx51_add_uart1(); - imx51_add_uart2(); - - spi_register_board_info(ccxmx51_spi_board_info, ARRAY_SIZE(ccxmx51_spi_board_info)); - imx51_add_spi0(&ecspi_0_data); - - pwr = ccxmx51_power_init(); - console_flush(); - imx51_init_lowlevel((ccxmx51_id->industrial || pwr) ? 600 : 800); - clock_notifier_call_chain(); - if (pwr) - printf("Could not setup PMIC. Clocks not adjusted.\n"); - imx51_add_i2c1(NULL); + if (!ccxmx51_is_compatible()) + return 0; - imx51_add_nand(&nand_info); - devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", 0x80000, 0x40000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - if (IS_ENABLED(CONFIG_DRIVER_NET_FEC_IMX) && ccxmx51_id->eth0 && !pwr) { - eth_register_ethaddr(0, hwid); - imx51_add_fec(&fec_info); + if ((imx_iim_read(1, 9, hwid, sizeof(hwid)) != sizeof(hwid)) || + (hwid[0] < 0x02) || (hwid[0] >= ARRAY_SIZE(ccxmx51_ids))) { + printf("Unknown board variant (0x%02x). System halted.\n", hwid[0]); + hang(); } - if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X) && ccxmx51_id->eth1 && !pwr) { - /* Configure the WEIM CS5 timming, bus width, etc */ - /* 16 bit on DATA[31..16], not multiplexed, async */ - writel(0x00420081, MX51_WEIM_BASE_ADDR + WEIM_CSxGCR1(5)); - /* ADH has not effect on non muxed bus */ - writel(0, MX51_WEIM_BASE_ADDR + WEIM_CSxGCR2(5)); - /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ - writel(0x32260000, MX51_WEIM_BASE_ADDR + WEIM_CSxRCR1(5)); - /* APR=0 */ - writel(0, MX51_WEIM_BASE_ADDR + WEIM_CSxRCR2(5)); - /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0 */ - writel(0x72080f00, MX51_WEIM_BASE_ADDR + WEIM_CSxWCR1(5)); - - /* LAN9221 network controller */ - add_generic_device("smc911x", 1, NULL, MX51_CS5_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); + ccxmx_id = &ccxmx51_ids[hwid[0]]; + + switch (hwid[2] & 0xc0) { + case 0x00: + manloc = 'B'; + break; + case 0x40: + manloc = 'W'; + break; + case 0x80: + manloc = 'S'; + break; + default: + break; } - imx51_add_usbotg(&ccxmx51_otg_pdata); + eth_register_ethaddr(0, hwid); - armlinux_set_architecture(ccxmx51_id->wless ? MACH_TYPE_CCWMX51 : MACH_TYPE_CCMX51); + boardserial = ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]; - return 0; -} -device_initcall(ccxmx51_devices_init); + printf("Module Variant: %s (0x%02x)\n", ccxmx_id->id_string, hwid[0]); + printf("Module HW Rev : %02x\n", hwid[1] + 1); + printf("Module Serial : %c%d\n", manloc, boardserial); -static int ccxmx51_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(ccxmx51_pads, ARRAY_SIZE(ccxmx51_pads)); + if ((ccxmx_id->mem_sz - SZ_128M) > 0) + arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M, + ccxmx_id->mem_sz - SZ_128M); + + mc13xxx_register_init_callback(ccxmx51_power_init); - barebox_set_model("Digi ConnectCore i.MX51"); - barebox_set_hostname("ccmx51"); + imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", + BBU_HANDLER_FLAG_DEFAULT); - imx51_add_uart0(); + if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT)) + defaultenv_append_directory(defaultenv_ccxmx51); return 0; } -console_initcall(ccxmx51_console_init); +fs_initcall(ccxmx51_init); diff --git a/arch/arm/boards/ccxmx51/ccxmx51.h b/arch/arm/boards/ccxmx51/ccxmx51.h deleted file mode 100644 index 3feacac034..0000000000 --- a/arch/arm/boards/ccxmx51/ccxmx51.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2010 Digi International Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef _CCXMX51_H_ -#define _CCXMX51_H_ - -struct ccxmx51_hwid { - u8 variant; - u8 version; - u32 sn; - char mloc; -}; - -struct ccxmx51_ident { - const char *id_string; - const int mem_sz; - const char industrial; - const char eth0; - const char eth1; - const char wless; -}; - -extern struct ccxmx51_ident *ccxmx51_id; - -#endif /* _CCXMX51_H_ */ diff --git a/arch/arm/boards/ccxmx51/ccxmx51js.c b/arch/arm/boards/ccxmx51/ccxmx51js.c deleted file mode 100644 index 7f068e239a..0000000000 --- a/arch/arm/boards/ccxmx51/ccxmx51js.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <io.h> -#include <init.h> -#include <gpio.h> -#include <mci.h> -#include <asm/armlinux.h> -#include <mach/generic.h> -#include <mach/imx51-regs.h> -#include <mach/iomux-mx51.h> -#include <mach/devices-imx51.h> -#include <generated/mach-types.h> - -#include "ccxmx51.h" - -#define CCXMX51JS_USBH1_RESET IMX_GPIO_NR(3, 8) -#define CCXMX51JS_SD3_WP IMX_GPIO_NR(3, 17) - -static iomux_v3_cfg_t ccxmx51js_pads[] = { - /* SD1 */ - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - /* SD3 */ - MX51_PAD_NANDF_CS7__SD3_CLK, - MX51_PAD_NANDF_RDY_INT__SD3_CMD, - MX51_PAD_NANDF_D8__SD3_DATA0, - MX51_PAD_NANDF_D9__SD3_DATA1, - MX51_PAD_NANDF_D10__SD3_DATA2, - MX51_PAD_NANDF_D11__SD3_DATA3, - MX51_PAD_NANDF_D12__SD3_DAT4, - MX51_PAD_NANDF_D13__SD3_DAT5, - MX51_PAD_NANDF_D14__SD3_DAT6, - MX51_PAD_NANDF_D15__SD3_DAT7, - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_STP__USBH1_STP, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, -}; - -static struct esdhc_platform_data sdhc1_pdata = { - .cd_type = ESDHC_CD_NONE, - .wp_type = ESDHC_WP_NONE, - .caps = MMC_CAP_4_BIT_DATA, -}; - -static struct esdhc_platform_data sdhc3_pdata = { - .cd_type = ESDHC_CD_NONE, - .wp_type = ESDHC_WP_GPIO, - .wp_gpio = CCXMX51JS_SD3_WP, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, -}; - -static struct imxusb_platformdata ccxmx51js_usbhost1_pdata = { - .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_ITC_NO_THRESHOLD, - .mode = IMX_USB_MODE_HOST, -}; - -static int ccxmx51js_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(ccxmx51js_pads, ARRAY_SIZE(ccxmx51js_pads)); - - if (IS_ENABLED(CONFIG_MCI_IMX_ESDHC)) { - imx51_add_mmc0(&sdhc1_pdata); - imx51_add_mmc2(&sdhc3_pdata); - } - - gpio_direction_output(CCXMX51JS_USBH1_RESET, 0); - mdelay(10); - gpio_set_value(CCXMX51JS_USBH1_RESET, 1); - mdelay(10); - imx51_add_usbh1(&ccxmx51js_usbhost1_pdata); - - armlinux_set_architecture(ccxmx51_id->wless ? MACH_TYPE_CCWMX51JS : MACH_TYPE_CCMX51JS); - - return 0; -} - -late_initcall(ccxmx51js_init); diff --git a/arch/arm/boards/ccxmx51/env/boot/nand b/arch/arm/boards/ccxmx51/defaultenv-ccxmx51/boot/nand index d53f07ec5d..d53f07ec5d 100644 --- a/arch/arm/boards/ccxmx51/env/boot/nand +++ b/arch/arm/boards/ccxmx51/defaultenv-ccxmx51/boot/nand diff --git a/arch/arm/boards/ccxmx51/env/nv/boot.default b/arch/arm/boards/ccxmx51/defaultenv-ccxmx51/nv/boot.default index 026a25cc7e..026a25cc7e 100644 --- a/arch/arm/boards/ccxmx51/env/nv/boot.default +++ b/arch/arm/boards/ccxmx51/defaultenv-ccxmx51/nv/boot.default diff --git a/arch/arm/boards/ccxmx51/env/init/mtdparts-nand b/arch/arm/boards/ccxmx51/env/init/mtdparts-nand deleted file mode 100644 index 27ed38a888..0000000000 --- a/arch/arm/boards/ccxmx51/env/init/mtdparts-nand +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="512k(barebox)ro,256k(bareboxenv),3328k(kernel),-(root)" -kernelname="mxc_nand" - -mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/ccxmx51/env/nv/autoboot_timeout b/arch/arm/boards/ccxmx51/env/nv/autoboot_timeout deleted file mode 100644 index 0cfbf08886..0000000000 --- a/arch/arm/boards/ccxmx51/env/nv/autoboot_timeout +++ /dev/null @@ -1 +0,0 @@ -2 diff --git a/arch/arm/boards/ccxmx51/lowlevel.c b/arch/arm/boards/ccxmx51/lowlevel.c index 2b3dc42e87..462c22e284 100644 --- a/arch/arm/boards/ccxmx51/lowlevel.c +++ b/arch/arm/boards/ccxmx51/lowlevel.c @@ -1,3 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Author: Alexander Shiyan <shc_work@mail.ru> */ + #include <common.h> #include <mach/esdctl.h> #include <mach/generic.h> @@ -5,8 +8,16 @@ #include <asm/barebox-arm-head.h> #include <mach/imx51-regs.h> -void __naked barebox_arm_reset_vector(void) +ENTRY_FUNCTION(start_ccxmx51, r0, r1, r2) { + extern char __dtb_imx51_ccxmx51_start[]; + void *fdt; + imx5_cpu_lowlevel_init(); - barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, NULL); + + arm_setup_stack(0x20000000 - 16); + + fdt = __dtb_imx51_ccxmx51_start + get_runtime_offset(); + + barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, fdt); } diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c index 584ecdcab2..641fa15021 100644 --- a/arch/arm/boards/clep7212/clep7212.c +++ b/arch/arm/boards/clep7212/clep7212.c @@ -37,7 +37,7 @@ static int clps711x_devices_init(void) add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_io, SZ_32M, IORESOURCE_MEM); - devfs_add_partition("nor0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED, + devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); devfs_add_partition("nor0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED, "env0"); diff --git a/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor b/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor index 39777f95f2..e2e518ca66 100644 --- a/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor +++ b/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor @@ -1,6 +1,6 @@ #!/bin/sh -mtdparts="256k(boot),256k(env),3584k(kernel),-(root)" +mtdparts="512k(boot),256k(env),3584k(kernel),-(root)" kernelname="physmap-flash.0" mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c index d7c5681dbc..ec41eb8c11 100644 --- a/arch/arm/boards/efika-mx-smartbook/board.c +++ b/arch/arm/boards/efika-mx-smartbook/board.c @@ -79,7 +79,7 @@ static void efikamx_power_init(struct mc13xxx *mc) /* power up the system first */ mc13xxx_reg_write(mc, MC13892_REG_POWER_MISC, - MC13892_POWER_MISC_PWUP); + MC13892_POWER_MISC_GPO4ADIN); /* Set core voltage to 1.1V */ mc13xxx_reg_read(mc, MC13892_REG_SW_0, &val); diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c index e1132e0b54..1e96c0893f 100644 --- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c @@ -15,11 +15,30 @@ #include <mach/esdctl.h> #include <mach/imx-nand.h> -#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) +enum { + PHYCARD_MICRON_64MB, + PHYCARD_MICRON_128MB, +}; -static void sdram_init(void) +#define ESDCTL0_VAL_64MB (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL9) +#define ESDCFG0_VAL_64MB 0x00696429 +#define ESDCTL0_VAL_128MB (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) +#define ESDCFG0_VAL_128MB 0x006ac73a + +static void sdram_init(int sdram) { int i; + unsigned esdcfg, esdctl; + + if (sdram == PHYCARD_MICRON_64MB) { + esdcfg = ESDCFG0_VAL_64MB; + esdctl = ESDCTL0_VAL_64MB; + } else if (sdram == PHYCARD_MICRON_128MB) { + esdcfg = ESDCFG0_VAL_128MB; + esdctl = ESDCTL0_VAL_128MB; + } else { + hang(); + } /* * DDR on CSD0 @@ -36,29 +55,29 @@ static void sdram_init(void) /* Initial reset */ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(esdcfg, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); /* precharge CSD0 all banks */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + writel(esdctl | ESDCTL0_SMODE_PRECHARGE, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writel(0x00000000, 0xa0000f00); /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + writel(esdctl | ESDCTL0_SMODE_AUTO_REFRESH, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); for (i = 0; i < 8; i++) writel(0, 0xa0000f00); - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + writel(esdctl | ESDCTL0_SMODE_LOAD_MODE, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, 0xa0000033); writeb(0xff, 0xa1000000); - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + writel(esdctl | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); } -void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt) +void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram) { unsigned long r; @@ -96,14 +115,25 @@ void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt) MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL | MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR); - sdram_init(); + sdram_init(sdram); imx27_barebox_boot_nand_external(fdt); } extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[]; -ENTRY_FUNCTION(start_phytec_phycard_imx27, r0, r1, r2) +ENTRY_FUNCTION(start_phytec_phycard_imx27_64mb, r0, r1, r2) +{ + void *fdt; + + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12); + + fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); + + phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_64MB); +} + +ENTRY_FUNCTION(start_phytec_phycard_imx27_128mb, r0, r1, r2) { void *fdt; @@ -111,5 +141,5 @@ ENTRY_FUNCTION(start_phytec_phycard_imx27, r0, r1, r2) fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); - phytec_phycard_imx27_common_init(fdt); + phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_128MB); } diff --git a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/init/bootsource b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/init/bootsource index 61a0879bfb..75b5619218 100644 --- a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/init/bootsource +++ b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/init/bootsource @@ -11,13 +11,13 @@ else fi if [ $bootsource = mmc -a $bootsource_instance = 1 ]; then - global.boot.default="emmc mmc spi net" + global.boot.default="bootchooser emmc mmc spi net" elif [ $bootsource = mmc -a $bootsource_instance = 0 ]; then global.boot.default="mmc $nvmem spi net" elif [ $bootsource = nand ]; then - global.boot.default="nand spi mmc net" + global.boot.default="bootchooser nand spi mmc net" elif [ $bootsource = spi ]; then - global.boot.default="spi $nvmem mmc net" + global.boot.default="spi bootchooser $nvmem mmc net" elif [ $bootsource = net ]; then - global.boot.default="net $nvmem spi mmc" + global.boot.default="net bootchooser $nvmem spi mmc" fi diff --git a/arch/arm/boards/vscom-baltos/board.c b/arch/arm/boards/vscom-baltos/board.c index 39f40a6061..c64864d432 100644 --- a/arch/arm/boards/vscom-baltos/board.c +++ b/arch/arm/boards/vscom-baltos/board.c @@ -68,6 +68,9 @@ static int baltos_read_eeprom(void) int rc; unsigned char mac_addr[6]; + if (!of_machine_is_compatible("vscom,onrisc")) + return 0; + rc = read_file_2("/dev/eeprom0", &size, (void *)&buf, diff --git a/arch/arm/boards/wago-pfc-am35xx/Makefile b/arch/arm/boards/wago-pfc-am35xx/Makefile new file mode 100644 index 0000000000..7bd3009f31 --- /dev/null +++ b/arch/arm/boards/wago-pfc-am35xx/Makefile @@ -0,0 +1,6 @@ +lwl-y += lowlevel.o +ifdef CONFIG_OMAP_BUILD_IFT +obj-y += board-mlo.o +else +obj-y += board.o +endif diff --git a/arch/arm/boards/wago-pfc-am35xx/board-mlo.c b/arch/arm/boards/wago-pfc-am35xx/board-mlo.c new file mode 100644 index 0000000000..7925c71a4b --- /dev/null +++ b/arch/arm/boards/wago-pfc-am35xx/board-mlo.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com> + * Author: Heinrich Toews <heinrich.toews@wago.com> + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <linux/sizes.h> +#include <mach/omap3-silicon.h> +#include <mach/gpmc.h> +#include <mach/gpmc_nand.h> +#include <errno.h> +#include <mach/omap3-devices.h> +#include <mach/generic.h> + +/* map first four erase blocks */ +static struct omap_barebox_part pfc200_mlo_part = { + /* start of boot0..boot3 (stage2 bootcode), + * we have 4x partitions + */ + .nand_offset = 4 * SZ_128K, + .nand_size = 4 * SZ_128K, +}; + +/** + * @brief Initialize the serial port to be used as console. + * + * @return result of device registration + */ +static int pfc200_init_console(void) +{ + barebox_set_model("Wago PFC200 MLO Stage #1"); + barebox_set_hostname("pfc200-mlo"); + + omap3_add_uart3(); + + return 0; +} +console_initcall(pfc200_init_console); + +static int pfc200_mem_init(void) +{ + omap_add_ram0(SZ_256M); + + return 0; +} +mem_initcall(pfc200_mem_init); + +static struct gpmc_nand_platform_data nand_plat = { + .cs = 0, + .device_width = 8, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW_ROMCODE, + .nand_cfg = &omap3_nand_cfg, +}; + +static int pfc200_init_devices(void) +{ +#ifdef CONFIG_OMAP_GPMC + /* + * WP is made high and WAIT1 active Low + */ + gpmc_generic_init(0x10); +#endif + omap_add_gpmc_nand_device(&nand_plat); + omap_set_barebox_part(&pfc200_mlo_part); + + omap3_add_mmc1(NULL); + + return 0; +} +device_initcall(pfc200_init_devices); diff --git a/arch/arm/boards/wago-pfc-am35xx/board.c b/arch/arm/boards/wago-pfc-am35xx/board.c new file mode 100644 index 0000000000..2bad40912d --- /dev/null +++ b/arch/arm/boards/wago-pfc-am35xx/board.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com> + * Author: Heinrich Toews <heinrich.toews@wago.com> + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <gpio.h> +#include <linux/sizes.h> +#include <linux/err.h> +#include <asm/memory.h> +#include <mach/generic.h> + +static int pfc200_mem_init(void) +{ + if (!of_machine_is_compatible("ti,pfc200")) + return 0; + + arm_add_mem_device("ram0", 0x80000000, SZ_256M); + return 0; +} +mem_initcall(pfc200_mem_init); + +#define GPIO_KSZ886x_RESET 136 + +static int pfc200_devices_init(void) +{ + if (!of_machine_is_compatible("ti,pfc200")) + return 0; + + gpio_direction_output(GPIO_KSZ886x_RESET, 1); + + omap_set_bootmmc_devname("mmc0"); + + return 0; +} +coredevice_initcall(pfc200_devices_init); diff --git a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c new file mode 100644 index 0000000000..7da8fd0331 --- /dev/null +++ b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com> + * Author: Heinrich Toews <heinrich.toews@wago.com> + */ + +#include <common.h> +#include <init.h> +#include <linux/sizes.h> +#include <io.h> +#include <linux/string.h> +#include <debug_ll.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/generic.h> +#include <mach/sdrc.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> +#include <mach/wdt.h> +#include <mach/omap3-mux.h> +#include <mach/omap3-silicon.h> +#include <mach/omap3-generic.h> +#include <mach/omap3-clock.h> +#include <mach/control.h> +#include <asm/common.h> +#include <asm-generic/memory_layout.h> + +#include <mach/emif4.h> + +static void mux_config(void) +{ + /* SDRC */ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)); + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)); + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)); + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)); + MUX_VAL(CP(SDRC_CKE0), (M0)); + MUX_VAL(CP(SDRC_CKE1), (M0)); + /* sdrc_strben_dly0 */ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)); + /*sdrc_strben_dly1*/ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)); + + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/ + /* - ETH_nRESET*/ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); + + /* MMC */ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)); + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)); + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)); + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)); + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)); + + /* MMC GPIOs */ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M4)); /* McBSP2_FSX -> SD-MMC1-CD (GPIO_116) */ + MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTU | DIS | M4)); /* McBSP2_CLKX -> SD-MMC1-EN (GPIO_117) */ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M4)); /* McBSP2_DR -> SD-MMC1-WP (GPIO_118) */ + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | DIS | M4)); /* MMC2_DAT7 -> SD-MMC1-RW (GPIO_139) */ + + /* UART1 */ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /* M4, GPIO_149 */ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); + + MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTU | DIS | M4)); /* MCSPI1_CS2 -> SEL_RS232/485_GPIO176 (GPIO_176) */ + + /* UART2 */ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); + + /* WATCHDOG */ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)); /* Trigger Event <1,6s */ + MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)); /* Enable */ + + /* I2C1: PMIC */ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M4)); /* SYS_nIRQ -> PMIC_nINT1 (GPIO_0) */ + + /* I2C2: RTC, EEPROM */ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /* RTC_EEPROM_SCL2 */ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /* RTC_EEPROM_SDA2 */ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)); /* HDQ_SIO -> WD_nWP GPIO_170 */ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4)); /* SYS_CLKREQ -> RTC_nINT (GPIO_1) */ + + /* GPIO_BANK3: operating mode switch and reset all pushbutton */ + MUX_VAL(CP(DSS_DATA20), (IEN | PTU | EN | M4)); // DSS_DATA20 -> BAS_RUN /* GPIO 90 */ (sync, changed) + MUX_VAL(CP(DSS_DATA21), (IEN | PTU | EN | M4)); // DSS_DATA21 -> BAS_STOP /* GPIO 91 */ (sync, changed) + MUX_VAL(CP(DSS_DATA22), (IEN | PTU | EN | M4)); // DSS_DATA22 -> BAS_RESET /* GPIO 92 */ (sync, changed) + MUX_VAL(CP(DSS_DATA23), (IEN | PTU | EN | M4)); // DSS_DATA23 -> RESET_ALL /* GPIO 93 */ (sync, changed) + MUX_VAL(CP(CCDC_PCLK) , (IEN | PTU | EN | M4)); // CCDC_PCLK -> System Reset /* GPIO 94 */ (sync, changed) Reserved for later use! + + /* *********** ADDED FOR JTAG DEBUGGING ************* */ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)); +} + +static noinline void pfc200_board_init(void) +{ + int in_sdram = omap3_running_in_sdram(); + u32 r0; + + if (IS_ENABLED(CONFIG_DEBUG_LL)) { + am33xx_uart_soft_reset(IOMEM(OMAP3_UART3_BASE)); + omap_uart_lowlevel_init(IOMEM(OMAP3_UART3_BASE)); + putc_ll('>'); + } + + omap3_core_init(); + + mux_config(); + +#define CONTROL_DEVCONF3 0x48002584 + /* activate DDR2 CPU Termination */ + r0 = readl(CONTROL_DEVCONF3); + writel(r0 | 0x2, CONTROL_DEVCONF3); + + /* Dont reconfigure SDRAM while running in SDRAM */ + if (!in_sdram) + am35xx_emif4_init(); + + barebox_arm_entry(0x80000000, SZ_256M, NULL); +} + +ENTRY_FUNCTION(start_am35xx_pfc_750_820x_sram, bootinfo, r1, r2) +{ + omap3_save_bootinfo((void *)bootinfo); + + arm_cpu_lowlevel_init(); + + omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); + + relocate_to_current_adr(); + setup_c(); + + pfc200_board_init(); +} + +extern char __dtb_am35xx_pfc_750_820x_start[]; + +ENTRY_FUNCTION(start_am35xx_pfc_750_820x_sdram, r0, r1, r2) +{ + void *fdt = __dtb_am35xx_pfc_750_820x_start; + + fdt += get_runtime_offset(); + + barebox_arm_entry(0x80000000, SZ_256M, fdt); +} diff --git a/arch/arm/boards/zii-imx6q-rdu2/Makefile b/arch/arm/boards/zii-imx6q-rdu2/Makefile index c6285362f2..10dfba3a3c 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/Makefile +++ b/arch/arm/boards/zii-imx6q-rdu2/Makefile @@ -1,3 +1,3 @@ -obj-y += board.o +obj-y += board.o switch-cmd.o lwl-y += lowlevel.o bbenv-y += defaultenv-rdu2 diff --git a/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c b/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c new file mode 100644 index 0000000000..bdba46fb36 --- /dev/null +++ b/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2018 Zodiac Inflight Innovation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <common.h> +#include <command.h> +#include <i2c/i2c.h> + +static int do_rave_switch_reset(int argc, char *argv[]) +{ + struct i2c_client client; + u8 reg; + + if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && + !of_machine_is_compatible("zii,imx6qp-zii-rdu2")) + return -ENODEV; + + client.adapter = i2c_get_adapter(1); + if (!client.adapter) + return -ENODEV; + + /* address of the switch watchdog microcontroller */ + client.addr = 0x38; + reg = 0x78; + /* set switch reset time to 100ms */ + i2c_write_reg(&client, 0x0a, ®, 1); + /* reset the switch */ + reg = 0x01; + i2c_write_reg(&client, 0x0d, ®, 1); + /* issue dummy command to work around firmware bug */ + i2c_read_reg(&client, 0x01, ®, 1); + + return 0; +} + +BAREBOX_CMD_START(rave_reset_switch) + .cmd = do_rave_switch_reset, + BAREBOX_CMD_DESC("reset ethernet switch on RDU2") + BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP) +BAREBOX_CMD_END diff --git a/arch/arm/configs/am35xx_pfc200_xload_defconfig b/arch/arm/configs/am35xx_pfc200_xload_defconfig new file mode 100644 index 0000000000..da55382f05 --- /dev/null +++ b/arch/arm/configs/am35xx_pfc200_xload_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARCH_OMAP=y +CONFIG_OMAP_BUILD_IFT=y +CONFIG_OMAP_MULTI_BOARDS=y +CONFIG_MACH_WAGO_PFC_AM35XX=y +CONFIG_THUMB2_BAREBOX=y +# CONFIG_ARM_EXCEPTIONS is not set +# CONFIG_MEMINFO is not set +CONFIG_MMU=y +# CONFIG_MMU_EARLY is not set +CONFIG_STACK_SIZE=0xc00 +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_DUMMY=y +CONFIG_RELOCATABLE=y +CONFIG_PROMPT="X-load pfc200>" +CONFIG_SHELL_NONE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_SIMPLE=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_WRITE is not set +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_SOFT is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +# CONFIG_NAND_INFO is not set +# CONFIG_NAND_BBT is not set +CONFIG_NAND_OMAP_GPMC=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +# CONFIG_MCI_WRITE is not set +CONFIG_MCI_MMC_BOOT_PARTITIONS=y +CONFIG_MCI_OMAP_HSMMC=y +# CONFIG_FS_RAMFS is not set +# CONFIG_FS_DEVFS is not set +CONFIG_FS_FAT=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/ccmx51_defconfig b/arch/arm/configs/ccmx51_defconfig deleted file mode 100644 index c16f73f7b1..0000000000 --- a/arch/arm/configs/ccmx51_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_MACH_CCMX51=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x2000000 -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_BOOTM_SHOW_TYPE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/ccxmx51/env" -CONFIG_LONGHELP=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_ARM_MMUINFO=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GO=y -CONFIG_CMD_RESET=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_CLK=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_NANDTEST=y -CONFIG_CMD_SPI=y -CONFIG_CMD_OFTREE=y -CONFIG_NET=y -CONFIG_DRIVER_NET_FEC_IMX=y -CONFIG_DRIVER_NET_SMC911X=y -CONFIG_I2C=y -CONFIG_I2C_IMX=y -CONFIG_MTD=y -CONFIG_NAND=y -CONFIG_NAND_IMX=y -CONFIG_USB_HOST=y -CONFIG_USB_IMX_CHIPIDEA=y -CONFIG_USB_EHCI=y -CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y -CONFIG_MCI=y -CONFIG_MCI_IMX_ESDHC=y -CONFIG_FS_CRAMFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/efika-mx-smartbook_defconfig b/arch/arm/configs/efika-mx-smartbook_defconfig deleted file mode 100644 index a988a0c54d..0000000000 --- a/arch/arm/configs/efika-mx-smartbook_defconfig +++ /dev/null @@ -1,106 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_IMX_MULTI_BOARDS=y -CONFIG_MACH_EFIKA_MX_SMARTBOOK=y -CONFIG_IMX_IIM=y -CONFIG_IMX_IIM_FUSE_BLOW=y -CONFIG_THUMB2_BAREBOX=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x2000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_BOOTM_SHOW_TYPE=y -CONFIG_BOOTM_VERBOSE=y -CONFIG_BOOTM_INITRD=y -CONFIG_BOOTM_OFTREE=y -CONFIG_BOOTM_OFTREE_UIMAGE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/efika-mx-smartbook/env/" -CONFIG_RESET_SOURCE=y -CONFIG_LONGHELP=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_ARM_MMUINFO=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_GO=y -CONFIG_CMD_RESET=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_LN=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_PING=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_LED=y -CONFIG_CMD_SPI=y -CONFIG_CMD_LED_TRIGGER=y -CONFIG_CMD_WD=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIME=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_NET_NETCONSOLE=y -CONFIG_NET_RESOLV=y -CONFIG_OFDEVICE=y -CONFIG_NET_USB=y -CONFIG_NET_USB_ASIX=y -CONFIG_NET_USB_SMSC95XX=y -CONFIG_I2C=y -CONFIG_I2C_IMX=y -CONFIG_MTD=y -CONFIG_MTD_M25P80=y -CONFIG_DRIVER_CFI=y -CONFIG_CFI_BUFFER_WRITE=y -CONFIG_DISK_INTF_PLATFORM_IDE=y -CONFIG_DISK_PATA_IMX=y -CONFIG_USB_HOST=y -CONFIG_USB_IMX_CHIPIDEA=y -CONFIG_USB_EHCI=y -CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_IMX_ESDHC=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_LED_TRIGGERS=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_IMX=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 64b202b9dc..2068a6cee4 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -1,6 +1,7 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y CONFIG_MACH_KINDLE_MX50=y +CONFIG_MACH_CCMX51=y CONFIG_MACH_EFIKA_MX_SMARTBOOK=y CONFIG_MACH_EMBEDSKY_E9=y CONFIG_MACH_FREESCALE_MX51_PDK=y @@ -41,7 +42,6 @@ CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y CONFIG_MACH_FREESCALE_MX7_SABRESD=y CONFIG_MACH_NXP_IMX6ULL_EVK=y CONFIG_MACH_GRINN_LITEBOARD=y -CONFIG_IMX_IIM=y CONFIG_IMX_IIM_FUSE_BLOW=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y diff --git a/arch/arm/configs/am335x_defconfig b/arch/arm/configs/omap_defconfig index 09dde908a3..128027a640 100644 --- a/arch/arm/configs/am335x_defconfig +++ b/arch/arm/configs/omap_defconfig @@ -4,14 +4,16 @@ CONFIG_BAREBOX_UPDATE_AM33XX_NAND=y CONFIG_BAREBOX_UPDATE_AM33XX_EMMC=y CONFIG_OMAP_MULTI_BOARDS=y CONFIG_MACH_AFI_GF=y +CONFIG_MACH_BEAGLE=y CONFIG_MACH_BEAGLEBONE=y CONFIG_MACH_PHYTEC_SOM_AM335X=y +CONFIG_MACH_VSCOM_BALTOS=y +CONFIG_MACH_WAGO_PFC_AM35XX=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_BOARD_APPEND_ATAG=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y CONFIG_MMU=y -CONFIG_TEXT_BASE=0x0 CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y @@ -30,6 +32,7 @@ CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_STATE=y +CONFIG_BOOTCHOOSER=y CONFIG_RESET_SOURCE=y CONFIG_DEBUG_INFO=y CONFIG_LONGHELP=y @@ -90,6 +93,7 @@ CONFIG_CMD_OF_FIXUP_STATUS=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y CONFIG_CMD_STATE=y +CONFIG_CMD_BOOTCHOOSER=y CONFIG_NET=y CONFIG_NET_NFS=y CONFIG_NET_NETCONSOLE=y @@ -98,6 +102,7 @@ CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y CONFIG_DRIVER_NET_CPSW=y +CONFIG_DRIVER_NET_DAVINCI_EMAC=y CONFIG_MICREL_PHY=y CONFIG_SMSC_PHY=y CONFIG_NET_USB=y diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c index 48a8086456..25ef0d3d82 100644 --- a/arch/arm/cpu/start-pbl.c +++ b/arch/arm/cpu/start-pbl.c @@ -31,9 +31,13 @@ #include <asm/mmu.h> #include <asm/unaligned.h> +#include "entry.h" + unsigned long free_mem_ptr; unsigned long free_mem_end_ptr; +void pbl_start(void); + /* * First instructions in the pbl image */ diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile index 372bf8d699..fda4eeafec 100644 --- a/arch/arm/crypto/Makefile +++ b/arch/arm/crypto/Makefile @@ -13,5 +13,3 @@ quiet_cmd_perl = PERL $@ $(src)/sha256-core.S_shipped: $(src)/sha256-armv4.pl $(call cmd,perl) - -.PRECIOUS: $(obj)/sha256-core.S diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c08b35a101..9c657ded35 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -21,6 +21,7 @@ pbl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o pbl-dtb-$(CONFIG_MACH_TX53) += imx53-tx53-xx30.dtb.o imx53-tx53-1011.dtb.o +pbl-dtb-$(CONFIG_MACH_CCMX51) += imx51-ccxmx51.dtb.o pbl-dtb-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o @@ -122,5 +123,6 @@ pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o +pbl-dtb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo diff --git a/arch/arm/dts/am335x-phytec-state.dtsi b/arch/arm/dts/am335x-phytec-state.dtsi index 6bca597159..1f61cf5a2e 100644 --- a/arch/arm/dts/am335x-phytec-state.dtsi +++ b/arch/arm/dts/am335x-phytec-state.dtsi @@ -15,13 +15,14 @@ / { aliases { am335x_phytec_mac_state = &am335x_phytec_mac_state; + state = &am335x_phytec_boot_state; }; am335x_phytec_mac_state: am335x_phytec_mac_state { magic = <0x3f45620e>; compatible = "barebox,state"; backend-type = "raw"; - backend = <&backend_state_eeprom>; + backend = <&backend_state_mac_eeprom>; backend-stridesize = <40>; keep-previous-content; @@ -37,6 +38,54 @@ }; }; + + am335x_phytec_boot_state: am335x_phytec_boot_state { + magic = <0x883b86a6>; + compatible = "barebox,state"; + backend-type = "raw"; + backend = <&backend_state_update_eeprom>; + backend-stridesize = <54>; + keep-previous-content; + + #address-cells = <1>; + #size-cells = <1>; + bootstate { + #address-cells = <1>; + #size-cells = <1>; + last_chosen { + reg = <0x0 0x4>; + type = "uint32"; + }; + system0 { + #address-cells = <1>; + #size-cells = <1>; + remaining_attempts { + reg = <0x4 0x4>; + type = "uint32"; + default = <3>; + }; + priority { + reg = <0x8 0x4>; + type = "uint32"; + default = <21>; + }; + }; + system1 { + #address-cells = <1>; + #size-cells = <1>; + remaining_attempts { + reg = <0x10 0x4>; + type = "uint32"; + default = <3>; + }; + priority { + reg = <0x14 0x4>; + type = "uint32"; + default = <20>; + }; + }; + }; + }; }; &eeprom { @@ -45,9 +94,13 @@ compatible = "fixed-partitions"; #size-cells = <1>; #address-cells = <1>; - backend_state_eeprom: state@0 { - reg = <0x000 0x120>; + backend_state_mac_eeprom: state@0 { + reg = <0x000 0x100>; label = "state-eeprom"; }; + backend_state_update_eeprom: state@100 { + reg = <0x100 0x150>; + label = "update-eeprom"; + }; }; }; diff --git a/arch/arm/dts/am33xx-clocks-strip.dtsi b/arch/arm/dts/am33xx-clocks-strip.dtsi index 92906deafe..706e1c9712 100644 --- a/arch/arm/dts/am33xx-clocks-strip.dtsi +++ b/arch/arm/dts/am33xx-clocks-strip.dtsi @@ -22,7 +22,6 @@ /delete-node/ &ehrpwm2_tbclk; /delete-node/ &clk_32768_ck; /delete-node/ &clk_rc32k_ck; -/delete-node/ &tclkin_ck; /delete-node/ &dpll_core_m6_ck; /delete-node/ &dpll_mpu_m2_ck; /delete-node/ &dpll_ddr_ck; @@ -40,7 +39,6 @@ /delete-node/ &pruss_ocp_gclk; /delete-node/ &mmu_fck; /delete-node/ &timer1_fck; -/delete-node/ &timer2_fck; /delete-node/ &timer3_fck; /delete-node/ &timer4_fck; /delete-node/ &timer5_fck; diff --git a/arch/arm/dts/am33xx-strip.dtsi b/arch/arm/dts/am33xx-strip.dtsi index 0c9d852630..b776c9cee7 100644 --- a/arch/arm/dts/am33xx-strip.dtsi +++ b/arch/arm/dts/am33xx-strip.dtsi @@ -27,7 +27,6 @@ /delete-node/ &dcan1; /delete-node/ &mailbox; /delete-node/ &timer1; -/delete-node/ &timer2; /delete-node/ &timer3; /delete-node/ &timer4; /delete-node/ &timer5; diff --git a/arch/arm/dts/am35xx-pfc-750_820x.dts b/arch/arm/dts/am35xx-pfc-750_820x.dts new file mode 100644 index 0000000000..707778dfac --- /dev/null +++ b/arch/arm/dts/am35xx-pfc-750_820x.dts @@ -0,0 +1,487 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * Copyright (C) 2014 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com> + * Author: Heinrich Toews <heinrich.toews@wago.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include <arm/am3517.dtsi> + +/ { + model = "Wago PFC200 (AM3505)"; + compatible = "ti,pfc200", "ti,am3517", "ti,omap3"; + + chosen { + stdout-path = &uart3; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vmmc_fixed: vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + aliases { + serial3 = &uart3; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + u1-green@0 { + label = "u1-green"; + gpios = <&gpio3 22 0>; + linux,default-trigger = "none"; + }; + + u1-red@1 { + label = "u1-red"; + gpios = <&gpio3 23 0>; + linux,default-trigger = "none"; + }; + + u2-green@2 { + label = "u2-green"; + gpios = <&gpio3 18 0>; + linux,default-trigger = "none"; + }; + + u2-red@3 { + label = "u2-red"; + gpios = <&gpio3 19 0>; + linux,default-trigger = "none"; + }; + + u3-green@4 { + label = "u3-green"; + gpios = <&gpio3 14 0>; + linux,default-trigger = "none"; + }; + + u3-red@5 { + label = "u3-red"; + gpios = <&gpio3 15 0>; + linux,default-trigger = "none"; + }; + + u4-green@6 { + label = "u4-green"; + gpios = <&gpio3 10 0>; + linux,default-trigger = "none"; + }; + + u4-red@7 { + label = "u4-red"; + gpios = <&gpio3 11 0>; + linux,default-trigger = "none"; + }; + + dia-green@8 { + label = "dia-green"; + gpios = <&gpio3 6 0>; + linux,default-trigger = "none"; + }; + + dia-red@9 { + label = "dia-red"; + gpios = <&gpio3 7 0>; + linux,default-trigger = "none"; + }; + + bf-green@10 { + label = "bf-green"; + gpios = <&gpio3 2 0>; + linux,default-trigger = "none"; + }; + + bf-red@11 { + label = "bf-red"; + gpios = <&gpio3 3 0>; + linux,default-trigger = "none"; + }; + + sys-green@12 { + label = "sys-green"; + gpios = <&gpio3 4 0>; + linux,default-trigger = "none"; + }; + + sys-red@13 { + label = "sys-red"; + gpios = <&gpio3 5 0>; + linux,default-trigger = "none"; + }; + + + run-green@14 { + label = "run-green"; + gpios = <&gpio3 8 0>; + linux,default-trigger = "none"; + }; + + run-red@15 { + label = "run-red"; + gpios = <&gpio3 9 0>; + linux,default-trigger = "none"; + }; + + + io-green@16 { + label = "io-green"; + gpios = <&gpio3 12 0>; + linux,default-trigger = "none"; + }; + + io-red@17 { + label = "io-red"; + gpios = <&gpio3 13 0>; + linux,default-trigger = "none"; + }; + + + ms-green@18 { + label = "ms-green"; + gpios = <&gpio3 16 0>; + linux,default-trigger = "none"; + }; + + ms-red@19 { + label = "ms-red"; + gpios = <&gpio3 17 0>; + linux,default-trigger = "none"; + }; + + + ns-green@20 { + label = "ns-green"; + gpios = <&gpio3 20 0>; + linux,default-trigger = "none"; + }; + + ns-red@21 { + label = "ns-red"; + gpios = <&gpio3 21 0>; + linux,default-trigger = "none"; + }; + + + can-green@22 { + label = "can-green"; + gpios = <&gpio3 24 0>; + linux,default-trigger = "none"; + }; + + can-red@23 { + label = "can-red"; + gpios = <&gpio3 25 0>; + linux,default-trigger = "none"; + }; + + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&davinci_emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; + status = "okay"; + phy-mode = "rmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&davinci_mdio { + status = "okay"; + reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc_fixed>; + bus-width = <4>; + cd-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO 116 */ + cd-inverted; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&bas_pins>; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x150 (PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ + 0x14e (PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ + 0x152 (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + 0x14c (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + 0x1a2 (PIN_OUTPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176: sel_rs232/485_gpio176 */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x14a (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x18a (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + 0x18e (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl.i2c2_scl */ + 0x190 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda.i2c2_sda */ + 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170: wd_nwp */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ + 0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + 0x116 (PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + 0x118 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + 0x11a (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + 0x11c (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + 0x11e (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + emac_pins: pinmux_emac_pins { + pinctrl-single,pins = < + 0x1ce (PIN_INPUT | MUX_MODE0) /* rmii_mdio_data.rmii_mdio_data */ + 0x1d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* rmii_mdio_clk.rmii_mdio_clk */ + 0x1d2 (PIN_INPUT | MUX_MODE0) /* rmii_rxd0.rmii_rxd0 */ + 0x1d4 (PIN_INPUT | MUX_MODE0) /* rmii_rxd1.rmii_rxd1 */ + 0x1d6 (PIN_INPUT | MUX_MODE0) /* rmii_crs_dv.rmii_crs_dv */ + 0x1d8 (PIN_INPUT | MUX_MODE0) /* rmii_rxer.rmii_rxer */ + 0x1da (PIN_OUTPUT_PULLUP | MUX_MODE0) /* rmii_txd0.rmii_txd0 */ + 0x1dc (PIN_INPUT | MUX_MODE0) /* rmii_txd1.rmii_txd1 */ + 0x1de (PIN_INPUT | MUX_MODE0) /* rmii_txen.rmii_txen */ + 0x1e0 (PIN_INPUT | MUX_MODE0) /* rmii_50mhz_clk.rmii_50mhz_clk */ + 0x134 (PIN_OUTPUT | MUX_MODE4) /* mmc2_dat4.gpio_136: nrst_switch */ + >; + }; + + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + 0x0a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_pclk.gpio_66: led_1_1_green */ + 0x0a6 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_hsync.gpio_67: led_1_1_red */ + 0x0a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_vsync.gpio_68: led_1_2_green */ + 0x0aa (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_acbias.gpio_69: led_1_2_red */ + + 0x0ac (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data0.gpio_70: led_2_1_green */ + 0x0ae (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data1.gpio_71: led_2_1_red */ + 0x0b0 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data2.gpio_72: led_2_2_green */ + 0x0b2 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data3.gpio_73: led_2_2_red */ + + 0x0b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data4.gpio_74: led_3_1_green */ + 0x0b6 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data5.gpio_75: led_3_1_red */ + 0x0b8 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data6.gpio_76: led_3_2_green */ + 0x0ba (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data7.gpio_77: led_3_2_red */ + + 0x0bc (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data8.gpio_78: led_4_1_green */ + 0x0be (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data9.gpio_79: led_4_1_red */ + 0x0c0 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data10.gpio_80: led_4_2_green */ + 0x0c2 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data11.gpio_81: led_4_2_red */ + + 0x0c4 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data12.gpio_82: led_5_1_green */ + 0x0c6 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data13.gpio_83: led_5_1_red */ + 0x0c8 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data14.gpio_84: led_5_2_green */ + 0x0ca (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data15.gpio_85: led_5_2_red */ + + 0x0cc (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data16.gpio_86: led_6_1_green */ + 0x0ce (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data17.gpio_87: led_6_1_red */ + 0x0d0 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data18.gpio_88: led_6_2_green */ + 0x0d2 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* dss_data19.gpio_89: led_6_2_red */ + >; + }; + + bas_pins: pinmux_bas_pins { + pinctrl-single,pins = < + 0x0d4 (PIN_INPUT_PULLUP | MUX_MODE4) /* dss_data20.gpio_90: bas_run */ + 0x0d6 (PIN_INPUT_PULLUP | MUX_MODE4) /* dss_data21.gpio_91: bas_stop */ + 0x0d8 (PIN_INPUT_PULLUP | MUX_MODE4) /* dss_data22.gpio_92: bas_reset */ + 0x0da (PIN_INPUT_PULLUP | MUX_MODE4) /* dss_data23.gpio_93: reset_all */ + >; + }; + + gpmc_pins: pinmux_gpmc_pins { + pinctrl-single,pins = < + 0x04a (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ + 0x04c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ + 0x04e (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ + 0x050 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a4.gpmc_a4 */ + 0x052 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a5.gpmc_a5 */ + 0x054 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a6.gpmc_a6 */ + 0x056 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a7.gpmc_a7 */ + 0x058 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a8.gpmc_a8 */ + 0x05a (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a9.gpmc_a9 */ + 0x05c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_a10.gpmc_a10 */ + + 0x06c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ + 0x06e (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ + 0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ + 0x072 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ + 0x074 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ + 0x076 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ + 0x078 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ + 0x07a (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ + + 0x07e (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_ncs0.gpmc_ncs0 */ + 0x080 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ + 0x082 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_ncs2.gpmc_ncs2 */ + 0x08c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_clk.gpmc_clk */ + + 0x090 (PIN_OUTPUT | MUX_MODE0) /* gpmc_nadv_ale.gpmc_nadv_ale */ + 0x092 (PIN_OUTPUT | MUX_MODE0) /* gpmc_noe.gpmc_noe */ + 0x094 (PIN_OUTPUT | MUX_MODE0) /* gpmc_nwe */ + + 0x096 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_nbe0_cle.gpmc_nbe0_cle */ + + 0x098 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_nbe1.gpmc_nbe1 */ + 0x09a (PIN_INPUT | MUX_MODE0) /* gpmc_nwp.gpmc_nwp */ + + 0x09c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x09e (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait1.gpmc_wait1 */ + 0x0a0 (PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait2.gpio_64 */ + 0x0a2 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait3.gpmc_wait3 */ + >; + }; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gpmc_pins>; + num-cs = <2>; + num-waitpins = <1>; + ranges = < + 0 0 0x08000000 0x01000000 /* CS0: NAND */ + >; + + nand: nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <36>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <24>; + gpmc,adv-wr-off-ns = <36>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <30>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <48>; + gpmc,access-ns = <54>; + gpmc,rd-cycle-ns = <72>; + gpmc,wr-cycle-ns = <72>; + + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + + gpmc,wr-access-ns = <30>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/include/ "am3xxx-pfc-nandparts.dtsi" diff --git a/arch/arm/dts/am3xxx-pfc-nandparts.dtsi b/arch/arm/dts/am3xxx-pfc-nandparts.dtsi new file mode 100644 index 0000000000..65dd56b815 --- /dev/null +++ b/arch/arm/dts/am3xxx-pfc-nandparts.dtsi @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * Copyright (C) 2015 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com> + * Author: Oleg Karfich <oleg.karfich@wago.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&nand { + /* 4 x 128k MLOs */ + partition@0 { + label = "mlo0"; + reg = <0x0 0x20000>; + }; + + partition@20000 { + label = "mlo1"; + reg = <0x20000 0x20000>; + }; + + partition@40000 { + label = "mlo2"; + reg = <0x40000 0x20000>; + }; + + partition@60000 { + label = "mlo3"; + reg = <0x60000 0x20000>; + }; + + /* 16 x 128k: 4 x stage2 (4x128k) */ + partition@80000 { + label = "boot0"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "boot1"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "boot2"; + reg = <0x180000 0x80000>; + }; + + partition@200000 { + label = "boot3"; + reg = <0x200000 0x80000>; + }; + + partition@280000 { + label = "ubidata"; + /* + * Size 0x0 extends partition to + * end of nand flash. + */ + reg = <0x280000 0x0>; + }; +}; diff --git a/arch/arm/dts/imx51-ccxmx51.dts b/arch/arm/dts/imx51-ccxmx51.dts new file mode 100644 index 0000000000..efe5dbf631 --- /dev/null +++ b/arch/arm/dts/imx51-ccxmx51.dts @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Author: Alexander Shiyan <shc_work@mail.ru> */ + +#include <arm/imx51-digi-connectcore-jsk.dts> + +/ { + chosen { + stdout-path = &uart1; + + environment { + compatible = "barebox,environment"; + device-path = &nfc, "partname:env"; + }; + }; +}; + +&iim { + barebox,provide-mac-address = <&fec 1 9>; +}; + +&nfc { + partition@0 { + label = "boot"; + reg = <0x00000 0x80000>; + }; + + partition@80000 { + label = "env"; + reg = <0x80000 0x40000>; + }; + + partition@c0000 { + label = "kernel"; + reg = <0xc0000 0x340000>; + }; + + partition@400000 { + label = "root"; + reg = <0x400000 0>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi index 53fdb722d0..5c43b16ab1 100644 --- a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi @@ -32,6 +32,9 @@ reg = <0x0 0xe0000>; }; + /delete-node/ partition@c0000; + /delete-node/ partition@c2000; + partition@e0000 { label = "barebox-environment"; reg = <0xe0000 0x20000>; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi index d829fdd6fb..398546d7b9 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -49,7 +49,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; nand-on-flash-bbt; - fsl,no-blockmark-swap; status = "disabled"; #address-cells = <1>; diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts index 56a35173a0..9593c555f9 100644 --- a/arch/arm/dts/imx8mq-evk.dts +++ b/arch/arm/dts/imx8mq-evk.dts @@ -6,16 +6,11 @@ /dts-v1/; +#include <arm64/freescale/imx8mq-evk.dts> #include "imx8mq.dtsi" -#include "imx8mq-ddrc.dtsi" / { - model = "NXP i.MX8MQ EVK"; - compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; - chosen { - stdout-path = &uart1; - environment-emmc { compatible = "barebox,environment"; device-path = &usdhc1, "partname:barebox-environment"; @@ -27,168 +22,9 @@ status = "disabled"; }; }; - - reg_usdhc2_vmmc: regulator-vsd-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&dcss { - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1_mdc>, <&pinctrl_fec1_mdio>, - <&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>, - <&pinctrl_fec1_phy_reset>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - status ="okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <975000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1675000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1625000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3625000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -&ocotp { - barebox,provide-mac-address = <&fec1 0x640>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&usb_dwc3_1 { - status = "okay"; - dr_mode = "host"; }; &usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1_cd_reset>, <&pinctrl_usdhc1_clk_strobe>, - <&pinctrl_usdhc1_data>; - pinctrl-1 = <&pinctrl_usdhc1_cd_reset>, - <&pinctrl_usdhc1_clk_strobe_100mhz>, - <&pinctrl_usdhc1_data_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_cd_reset>, - <&pinctrl_usdhc1_clk_strobe_200mhz>, - <&pinctrl_usdhc1_data_200mhz>; - vqmmc-supply = <&sw4_reg>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - #address-cells = <1>; #size-cells = <1>; @@ -204,17 +40,6 @@ }; &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk>, - <&pinctrl_usdhc2_data>; - pinctrl-1 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_100mhz>, - <&pinctrl_usdhc2_data_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_200mhz>, - <&pinctrl_usdhc2_data_200mhz>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; - #address-cells = <1>; #size-cells = <1>; @@ -229,250 +54,6 @@ }; }; -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1_mdc: fec1mdcgrp { - pinmux = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC>; - drive-strength = <3>; - slew-rate = <0>; - }; - - pinctrl_fec1_mdio: fec1mdiogrp { - pinmux = <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO>; - drive-strength = <3>; - slew-rate = <0>; - drive-open-drain; - }; - - pinctrl_fec1_phy_reset: fec1phyresetgrp { - pinmux = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9>; - drive-strength = <1>; - slew-rate = <0>; - }; - - pinctrl_fec1_data_tx: fec1datatxgrp { - pinmux = < - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL - >; - drive-strength = <7>; - slew-rate = <3>; - }; - - pinctrl_fec1_data_rx: fec1datarxgrp { - pinmux = < - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL - >; - drive-strength = <1>; - slew-rate = <2>; - input-schmitt-enable; - }; - - pinctrl_i2c1: i2c1grp { - pinmux = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA - >; - drive-strength = <7>; - slew-rate = <0>; - drive-open-drain; - input-enable; - }; - - pinctrl_reg_usdhc2: regusdhc2grpgpio { - pinmux = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19>; - drive-strength = <1>; - slew-rate = <0>; - bias-pull-up; - }; - - pinctrl_uart1: uart1grp { - pinmux = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX - >; - drive-strength = <1>; - slew-rate = <0>; - bias-pull-up; - }; - - pinctrl_usdhc1_cd_reset: usdhc1cdgrp { - pinmux = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B - >; - drive-strength = <1>; - slew-rate = <0>; - bias-pull-up; - }; - - pinctrl_usdhc1_clk_strobe: usdhc1clkgrp { - pinmux = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE - >; - drive-strength = <3>; - slew-rate = <0>; - }; - - pinctrl_usdhc1_data: usdhc1datagrp { - pinmux = < - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 - >; - drive-strength = <3>; - slew-rate = <0>; - bias-pull-up; - input-schmitt-enable; - }; - - pinctrl_usdhc1_clk_strobe_100mhz: usdhc1clk100grp { - pinmux = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE - >; - drive-strength = <3>; - slew-rate = <0>; - }; - - pinctrl_usdhc1_data_100mhz: usdhc1data100grp { - pinmux = < - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 - >; - drive-strength = <5>; - slew-rate = <1>; - bias-pull-up; - input-schmitt-enable; - }; - - pinctrl_usdhc1_clk_strobe_200mhz: usdhc1clk200grp { - pinmux = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE - >; - drive-strength = <7>; - slew-rate = <3>; - }; - - pinctrl_usdhc1_data_200mhz: usdhc1data200grp { - pinmux = < - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 - >; - drive-strength = <7>; - slew-rate = <3>; - bias-pull-up; - input-schmitt-enable; - }; - - pinctrl_usdhc2_vselect: usdhc2vselectgrp { - pinmux = <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT>; - drive-strength = <1>; - slew-rate = <0>; - bias-pull-up; - }; - - pinctrl_usdhc2_clk: usdhc2clkgrp { - pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>; - drive-strength = <3>; - slew-rate = <0>; - }; - - pinctrl_usdhc2_data: usdhc2datagrp { - pinmux = < - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 - >; - drive-strength = <3>; - slew-rate = <0>; - bias-pull-up; - input-schmitt-enable; - }; - - pinctrl_usdhc2_clk_100mhz: usdhc2clk100grp { - pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>; - drive-strength = <5>; - slew-rate = <1>; - }; - - pinctrl_usdhc2_data_100mhz: usdhc2data100grp { - pinmux = < - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 - >; - drive-strength = <5>; - slew-rate = <1>; - bias-pull-up; - input-schmitt-enable; - }; - - pinctrl_usdhc2_clk_200mhz: usdhc2clk200grp { - pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>; - drive-strength = <7>; - slew-rate = <3>; - }; - - pinctrl_usdhc2_data_200mhz: usdhc2data200grp { - pinmux = < - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 - >; - drive-strength = <7>; - slew-rate = <3>; - bias-pull-up; - input-schmitt-enable; - }; - - pinctrl_wdog: wdoggrp { - pinmux = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B>; - drive-strength = <6>; - slew-rate = <0>; - bias-pull-up; - }; -}; +&ocotp { + barebox,provide-mac-address = <&fec1 0x640>; +};
\ No newline at end of file diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h deleted file mode 100644 index b94b02080a..0000000000 --- a/arch/arm/dts/imx8mq-pinfunc.h +++ /dev/null @@ -1,623 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DTS_IMX8MQ_PINFUNC_H -#define __DTS_IMX8MQ_PINFUNC_H - -/* - * The pin function ID is a tuple of - * <mux_reg conf_reg input_reg mux_mode input_val> - */ - -#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 - -#endif /* __DTS_IMX8MQ_PINFUNC_H */ diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index f89bee200e..1ddb51f898 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -4,31 +4,10 @@ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> */ -#include <dt-bindings/clock/imx8mq-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> -#include "imx8mq-pinfunc.h" - -/* first 128 KiB of memory are owned by ATF */ -/memreserve/ 0x40000000 0x00020000; / { - /* This should really be the GPC, but we need a driver for this first */ - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -36,186 +15,40 @@ gpio4 = &gpio5; mmc0 = &usdhc1; mmc1 = &usdhc2; + spi0 = &ecspi1; }; - ckil: clk-ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc_25m: clk-osc-25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "osc_25m"; - }; - - osc_27m: clk-osc-27m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "osc_27m"; - }; - - clk_ext1: clk-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clk-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clk-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clk-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - #cooling-cells = <2>; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ - interrupt-parent = <&gic>; - arm,no-tick-in-suspend; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&dcss_disp0>; - }; - - peripherals@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - - bus@30000000 { /* AIPS1 */ - compatible = "fsl,imx8mq-aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30000000 0x30000000 0x400000>; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; - gpio4: gpio@30230000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; }; - gpio5: gpio@30240000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; }; + }; + }; + soc@0 { + bus@30000000 { tmu: tmu@30260000 { compatible = "fsl,imx8mq-tmu"; reg = <0x30260000 0x10000>; @@ -223,158 +56,61 @@ little-endian; fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; fsl,tmu-calibration = <0x00000000 0x00000023 - 0x00000001 0x00000029 - 0x00000002 0x0000002f - 0x00000003 0x00000035 - 0x00000004 0x0000003d - 0x00000005 0x00000043 - 0x00000006 0x0000004b - 0x00000007 0x00000051 - 0x00000008 0x00000057 - 0x00000009 0x0000005f - 0x0000000a 0x00000067 - 0x0000000b 0x0000006f - - 0x00010000 0x0000001b - 0x00010001 0x00000023 - 0x00010002 0x0000002b - 0x00010003 0x00000033 - 0x00010004 0x0000003b - 0x00010005 0x00000043 - 0x00010006 0x0000004b - 0x00010007 0x00000055 - 0x00010008 0x0000005d - 0x00010009 0x00000067 - 0x0001000a 0x00000070 - - 0x00020000 0x00000017 - 0x00020001 0x00000023 - 0x00020002 0x0000002d - 0x00020003 0x00000037 - 0x00020004 0x00000041 - 0x00020005 0x0000004b - 0x00020006 0x00000057 - 0x00020007 0x00000063 - 0x00020008 0x0000006f - - 0x00030000 0x00000015 - 0x00030001 0x00000021 - 0x00030002 0x0000002d - 0x00030003 0x00000039 - 0x00030004 0x00000045 - 0x00030005 0x00000053 - 0x00030006 0x0000005f - 0x00030007 0x00000071>; + 0x00000001 0x00000029 + 0x00000002 0x0000002f + 0x00000003 0x00000035 + 0x00000004 0x0000003d + 0x00000005 0x00000043 + 0x00000006 0x0000004b + 0x00000007 0x00000051 + 0x00000008 0x00000057 + 0x00000009 0x0000005f + 0x0000000a 0x00000067 + 0x0000000b 0x0000006f + + 0x00010000 0x0000001b + 0x00010001 0x00000023 + 0x00010002 0x0000002b + 0x00010003 0x00000033 + 0x00010004 0x0000003b + 0x00010005 0x00000043 + 0x00010006 0x0000004b + 0x00010007 0x00000055 + 0x00010008 0x0000005d + 0x00010009 0x00000067 + 0x0001000a 0x00000070 + + 0x00020000 0x00000017 + 0x00020001 0x00000023 + 0x00020002 0x0000002d + 0x00020003 0x00000037 + 0x00020004 0x00000041 + 0x00020005 0x0000004b + 0x00020006 0x00000057 + 0x00020007 0x00000063 + 0x00020008 0x0000006f + + 0x00030000 0x00000015 + 0x00030001 0x00000021 + 0x00030002 0x0000002d + 0x00030003 0x00000039 + 0x00030004 0x00000045 + 0x00030005 0x00000053 + 0x00030006 0x0000005f + 0x00030007 0x00000071>; #thermal-sensor-cells = <0>; }; - thermal-zones { - /* cpu thermal */ - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu>; - - trips { - cpu_alert0: trip0 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit0: trip1 { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - iomuxc: iomuxc@30330000 { - compatible = "fsl,imx8mq-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mq-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - ocotp: ocotp@30350000 { compatible = "fsl,imx8mq-ocotp"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; }; - - anatop: anatop@30360000 { - compatible = "fsl,imx8mq-anatop", "syscon"; - reg = <0x30360000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mq-ccm"; - reg = <0x30380000 0x10000>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - clocks = <&ckil>, <&osc_25m>, <&osc_27m>, - <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "ckil", "osc_25m", "osc_27m", - "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; - status = "disabled"; - }; }; - bus@30400000 { /* AIPS2 */ - compatible = "fsl,imx8mq-aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30400000 0x30400000 0x400000>; - }; - - bus@30800000 { /* AIPS3 */ - compatible = "fsl,imx8mq-aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>; - + bus@30800000 { ecspi1: ecspi@30820000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; reg = <0x30820000 0x10000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, @@ -382,370 +118,30 @@ clock-names = "ipg", "per"; status = "disabled"; }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, - <&clk IMX8MQ_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, - <&clk IMX8MQ_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, - <&clk IMX8MQ_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, - <&clk IMX8MQ_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - usdhc1: usdhc@30b40000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_DUMMY>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, - <&clk IMX8MQ_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@30b50000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_DUMMY>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, - <&clk IMX8MQ_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET_TIMER_DIV>, - <&clk IMX8MQ_CLK_ENET_REF_DIV>, - <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - }; - - bus@32c00000 { /* AIPS4 */ - compatible = "fsl,imx8mq-aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x32c00000 0x32c00000 0x400000>; - - hdmi: hdmi@32c00000 { - compatible = "fsl,imx8mq-hdmi"; - reg = <0x32c00000 0x33800>, /* HDP registers */ - <0x32e40000 0x40000>; /* HDP SEC register */ - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "plug_in", "plug_out"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - hdmi_disp: endpoint { - remote-endpoint = <&dcss_disp0_hdmi>; - }; - }; - }; - - dcss: dcss@32e00000 { - compatible = "nxp,imx8mq-dcss"; - reg = <0x32e00000 0x30000>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, - <4 IRQ_TYPE_LEVEL_HIGH>, - <5 IRQ_TYPE_LEVEL_HIGH>, - <6 IRQ_TYPE_LEVEL_HIGH>, - <8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dpr_dc_ch0", - "dpr_dc_ch1", - "dpr_dc_ch2", - "ctx_ld", - "dtg_prg1"; - interrupt-parent = <&irqsteer_dcss>; - clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, - <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, - <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, - <&clk IMX8MQ_CLK_DC_PIXEL_DIV>, - <&clk IMX8MQ_CLK_DISP_DTRC_DIV>; - clock-names = "apb", "axi", "rtrm", - "pixel", "dtrc"; - assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>, - <&clk IMX8MQ_CLK_DISP_AXI_SRC>, - <&clk IMX8MQ_CLK_DISP_RTRM_SRC>, - <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>; - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_SYS1_PLL_800M>; - assigned-clock-rates = <594000000>, - <800000000>, - <400000000>, - <400000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dcss_disp0: port@0 { - reg = <0>; - dcss_disp0_hdmi: hdmi-endpoint { - remote-endpoint = <&hdmi_disp>; - }; - }; - }; - - irqsteer_dcss: interrupt-controller@32e2d000 { - compatible = "nxp,imx-irqsteer"; - reg = <0x32e2d000 0x1000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; - clock-names = "ipg"; - nxp,channel = <2>; - nxp,endian = <1>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - gpu: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x40000>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI_DIV>, - <&clk IMX8MQ_CLK_GPU_AHB_DIV>; - clock-names = "core", "shader", "bus", "reg"; - - assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, - <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, - <&clk IMX8MQ_CLK_GPU_AXI_SRC>, - <&clk IMX8MQ_CLK_GPU_AHB_SRC>; - assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>; - assigned-clock-rates = <800000000>, <800000000>, - <800000000>, <800000000>; - //power-domains = <&gpu_pd>; - }; - - usb3_0: usb0@38100000 { - compatible = "fsl,imx8mq-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x38100000 0x38100000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>, - <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - status = "disabled"; - - usb_dwc3_0: dwc3@38100000 { - compatible = "snps,dwc3"; - reg = <0x38100000 0x10000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb3_phy0 0>, <&usb3_phy0 1>; - phy-names = "usb2-phy", "usb3-phy"; - //power-domains = <&usb_otg1_pd>; - snps,power-down-scale = <2>; - usb3-resume-missing-cas; - status = "disabled"; - }; - }; - - usb3_phy0: phy@381f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x381f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; - clock-names = "usb_phy_root_clk"; - #phy-cells = <1>; - - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - }; - - usb3_1: usb1@38200000 { - compatible = "fsl,imx8mq-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x38200000 0x38200000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; - clock-names = "usb2_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>, - <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - status = "disabled"; - - usb_dwc3_1: dwc3@38200000 { - compatible = "snps,dwc3"; - reg = <0x38200000 0x10000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb3_phy1 0>, <&usb3_phy1 1>; - phy-names = "usb2-phy", "usb3-phy"; - //power-domains = <&usb_otg2_pd>; - snps,power-down-scale = <2>; - usb3-resume-missing-cas; - status = "disabled"; - }; - }; - - usb3_phy1: phy@382f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x382f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; - clock-names = "usb_phy_root_clk"; - #phy-cells = <1>; - - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>, /* GICR */ - <0x31000000 0x2000>, /* GICC */ - <0x31010000 0x2000>, /* GICV */ - <0x31020000 0x2000>; /* GICH */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; }; }; }; - +&A53_0 { + #cooling-cells = <2>; +}; &clk { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_SRC>, - <&clk IMX8MQ_CLK_USDHC1_DIV>, - <&clk IMX8MQ_CLK_USDHC2_SRC>, - <&clk IMX8MQ_CLK_USDHC2_DIV>, - <&clk IMX8MQ_CLK_ENET_AXI_SRC>, - <&clk IMX8MQ_CLK_ENET_TIMER_SRC>, - <&clk IMX8MQ_CLK_ENET_REF_SRC>, - <&clk IMX8MQ_CLK_ENET_TIMER_DIV>; - + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>, + <&clk IMX8MQ_CLK_USDHC2>, + <&clk IMX8MQ_CLK_ENET_AXI>, + <&clk IMX8MQ_CLK_ENET_TIMER>, + <&clk IMX8MQ_CLK_ENET_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_400M>, - <0>, <&clk IMX8MQ_SYS1_PLL_400M>, - <0>, <&clk IMX8MQ_SYS1_PLL_266M>, <&clk IMX8MQ_SYS2_PLL_100M>, - <&clk IMX8MQ_SYS2_PLL_125M>, - <0>; + <&clk IMX8MQ_SYS2_PLL_125M>; - assigned-clock-rates = <400000000>, - <200000000>, - <400000000>, + assigned-clock-rates = <200000000>, <200000000>, <266000000>, - <0>, - <125000000>, - <25000000>; + <25000000>, + <125000000>; }; - diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index b4021b5038..63975071f1 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -40,7 +40,7 @@ static void __iomem *st = IOMEM(AT91RM9200_BASE_ST); * the updates as seen by the CPU don't seem to be strictly monotonic. * Waiting until we read the same value twice avoids glitching. */ -uint64_t at91rm9200_clocksource_read(void) +static uint64_t at91rm9200_clocksource_read(void) { unsigned long x1, x2; diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index a67345f05d..c7e4962a93 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -396,6 +396,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) } else { /* MCI1 */ start = AT91SAM9263_BASE_MCI1; + /* CLK */ + at91_set_A_periph(AT91_PIN_PA6, 0); + if (data->slot_b) { /* CMD */ at91_set_A_periph(AT91_PIN_PA21, 1); diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 9d2e3a3acc..d2691acae3 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -22,6 +22,7 @@ #include <mach/hardware.h> #include <mach/at91_pmc.h> #include <mach/cpu.h> +#include <mach/board.h> #include "clock.h" #include "generic.h" diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index 0f2c269732..886f81e9ad 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -64,6 +64,8 @@ struct atmel_nand_data { u8 cle; /* address line number connected to CLE */ u8 bus_width_16; /* buswidth is 16 bit */ u8 ecc_mode; /* NAND_ECC_* */ + u8 ecc_strength; /* number of bits to correct per ECC step */ + u8 ecc_size_shift; /* data bytes covered by a single ECC step.*/ u8 on_flash_bbt; /* Use flash based bbt */ u8 has_pmecc; /* Use PMECC */ u8 bus_on_d0; diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index adc614c42c..cb79eb26b8 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -15,6 +15,7 @@ #include <mach/cpu.h> #include <mach/at91_dbgu.h> #include <mach/at91_rstc.h> +#include <mach/board.h> #include "generic.h" @@ -24,17 +25,6 @@ void __initdata (*at91_boot_soc)(void); struct at91_socinfo at91_soc_initdata; EXPORT_SYMBOL(at91_soc_initdata); -void __init at91rm9200_set_type(int type) -{ - if (type == ARCH_REVISON_9200_PQFP) - at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP; - else - at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; - - pr_info("AT91: filled in soc subtype: %s\n", - at91_get_soc_subtype(&at91_soc_initdata)); -} - static void __init soc_detect(u32 dbgu_base) { u32 cidr, socid; diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index 0853ce2e62..c00514e86d 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -24,7 +24,7 @@ endmenu config ARCH_TEXT_BASE hex - default 0xc0780000 if MACH_CLEP7212 + default 0xc0740000 if MACH_CLEP7212 config BAREBOX_MAX_IMAGE_SIZE hex diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index d9b60053db..44ca27096b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -26,7 +26,6 @@ config ARCH_TEXT_BASE default 0x93d00000 if MACH_TX25 default 0x7ff00000 if MACH_TQMA53 default 0x97f00000 if MACH_TX51 - default 0x97f00000 if MACH_CCMX51 default 0x4fc00000 if MACH_SABRELITE default 0x8fe00000 if MACH_TX53 default 0x97f00000 if MACH_EFIKA_MX_SMARTBOOK @@ -246,6 +245,18 @@ config MACH_KINDLE_MX50 Kindle Model No. D01100 (Kindle Wi-Fi), D01200 (Kindle Touch) or EY21 (Kindle Paperwhite). +config MACH_CCMX51 + bool "ConnectCore i.MX51" + select ARCH_IMX51 + select IMX_IIM + select SPI + select DRIVER_SPI_IMX + select MFD_MC13XXX + select RELOCATABLE + help + Say Y here if you are using Digi ConnectCore (W)i-i.MX51 + equipped with a Freescale i.MX51 Processor + config MACH_EFIKA_MX_SMARTBOOK bool "Efika MX smartbook" select ARCH_IMX51 @@ -622,25 +633,6 @@ config MACH_TX51 help Say Y here if you are using the Ka-Ro tx51 board -config MACH_CCMX51 - bool "ConnectCore i.MX51" - select ARCH_IMX51 - select IMX_IIM - select SPI - select DRIVER_SPI_IMX - select MFD_MC13XXX - help - Say Y here if you are using Digi ConnectCore (W)i-i.MX51 - equipped with a Freescale i.MX51 Processor - -config MACH_CCMX51_BASEBOARD - bool "Digi development board for CCMX51 module" - depends on MACH_CCMX51 - default y - help - This adds board specific devices that can be found on Digi - evaluation board for CCMX51 module. - # ---------------------------------------------------------- comment "i.MX53 Boards" diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c index ca11e83456..ff2a828c7d 100644 --- a/arch/arm/mach-imx/imx7.c +++ b/arch/arm/mach-imx/imx7.c @@ -26,6 +26,7 @@ void imx7_init_lowlevel(void) { void __iomem *aips1 = IOMEM(MX7_AIPS1_CONFIG_BASE_ADDR); void __iomem *aips2 = IOMEM(MX7_AIPS2_CONFIG_BASE_ADDR); + void __iomem *aips3 = IOMEM(MX7_AIPS3_CONFIG_BASE_ADDR); /* * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -46,6 +47,14 @@ void imx7_init_lowlevel(void) writel(0, aips2 + 0x48); writel(0, aips2 + 0x4c); writel(0, aips2 + 0x50); + + writel(0x77777777, aips3); + writel(0x77777777, aips3 + 0x4); + writel(0, aips3 + 0x40); + writel(0, aips3 + 0x44); + writel(0, aips3 + 0x48); + writel(0, aips3 + 0x4c); + writel(0, aips3 + 0x50); } #define SC_CNTCR 0x0 diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index c451cf0d47..e793175f38 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -26,7 +26,7 @@ config ARCH_OMAP3 bool select CPU_V7 select GENERIC_GPIO - select OMAP_CLOCK_SOURCE_S32K + select CLOCKSOURCE_TI_32K help Say Y here if you are using Texas Instrument's OMAP343x based platform @@ -34,7 +34,7 @@ config ARCH_OMAP4 bool select CPU_V7 select GENERIC_GPIO - select OMAP_CLOCK_SOURCE_S32K + select CLOCKSOURCE_TI_32K help Say Y here if you are using Texas Instrument's OMAP4 based platform @@ -43,17 +43,16 @@ config ARCH_AM33XX select CPU_V7 select GENERIC_GPIO select OFTREE - select OMAP_CLOCK_SOURCE_DMTIMER + select CLOCKSOURCE_TI_DM select ARM_USE_COMPRESSED_DTB help Say Y here if you are using Texas Instrument's AM33xx based platform -# Blind enable all possible clocks.. think twice before you do this. -config OMAP_CLOCK_SOURCE_S32K - bool - -config OMAP_CLOCK_SOURCE_DMTIMER +config ARCH_AM35XX bool + select ARCH_OMAP3 + help + Say Y here if you are using Texas Instrument's AM35XX based platform config OMAP_GPMC prompt "Support for GPMC configuration" @@ -184,6 +183,15 @@ config MACH_VSCOM_BALTOS help Say Y here if you are using a am335x based VScom Baltos devices +config MACH_WAGO_PFC_AM35XX + bool "Wago PFC200 Fieldbus Controller" + select ARCH_AM35XX + select HAVE_DEFAULT_ENVIRONMENT_NEW + select HAVE_PBL_MULTI_IMAGES + select HAVE_CONFIGURABLE_MEMORY_LAYOUT + help + Say Y here if you are using a the AM3505 based PFC200 controller + endif source arch/arm/boards/phytec-som-am335x/Kconfig diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile index a84e94ed7d..36b2aa090e 100644 --- a/arch/arm/mach-omap/Makefile +++ b/arch/arm/mach-omap/Makefile @@ -17,13 +17,12 @@ # obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o pbl-$(CONFIG_ARCH_OMAP) += syslib.o -obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o -obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER) += dmtimer.o obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o -obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o +obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o +obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o am35xx_emif4.o obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o obj-$(CONFIG_ARCH_OMAP3) += omap3_clock.o pbl-$(CONFIG_ARCH_OMAP3) += omap3_clock.o diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 513746248e..fe3c4a8b17 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -256,36 +256,12 @@ int am33xx_init(void) int am33xx_devices_init(void) { - return am33xx_gpio_init(); -} - -/* UART Defines */ -#define UART_SYSCFG_OFFSET 0x54 -#define UART_SYSSTS_OFFSET 0x58 - -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_RESET (0x1 << 1) -#define UART_SMART_IDLE_EN (0x1 << 0x3) - -void am33xx_uart_soft_reset(void __iomem *uart_base) -{ - int reg; - - reg = readl(uart_base + UART_SYSCFG_OFFSET); - reg |= UART_RESET; - writel(reg, (uart_base + UART_SYSCFG_OFFSET)); - - while ((readl(uart_base + UART_SYSSTS_OFFSET) & - UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - reg = readl((uart_base + UART_SYSCFG_OFFSET)); - reg |= UART_SMART_IDLE_EN; - writel(reg, (uart_base + UART_SYSCFG_OFFSET)); + am33xx_gpio_init(); + add_generic_device("omap-dmtimer", 0, NULL, AM33XX_DMTIMER2_BASE, 0x400, + IORESOURCE_MEM, NULL); + return 0; } - #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) #define VTP_CTRL_START_EN (0x1) diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c new file mode 100644 index 0000000000..38fc0f02d2 --- /dev/null +++ b/arch/arm/mach-omap/am35xx_emif4.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author : + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * Based on mem.c and sdrc.c + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <io.h> +#include <mach/emif4.h> +#include <mach/omap3-silicon.h> + +/* + * do_pac200_emif4_init - + * - Init the emif4 module for DDR access + * - Early init routines, called from flash or SRAM. + */ +void am35xx_emif4_init(void) +{ + unsigned int regval; + struct emif4 *emif4_base = IOMEM(OMAP3_SDRC_BASE); + + /* Set the DDR PHY parameters in PHY ctrl registers */ + regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | + EMIF4_DDR1_EXT_STRB_DIS); + writel(regval, &emif4_base->ddr_phyctrl1); + writel(regval, &emif4_base->ddr_phyctrl1_shdw); + writel(0, &emif4_base->ddr_phyctrl2); + + /* Reset the DDR PHY and wait till completed */ + regval = readl(&emif4_base->sdram_iodft_tlgc); + regval |= (1 << 10); + writel(regval, &emif4_base->sdram_iodft_tlgc); + + /* Wait till that bit clears*/ + while ((readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)) == 0x1); + + /* Re-verify the DDR PHY status*/ + while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0); + + regval |= (1 << 0); + writel(regval, &emif4_base->sdram_iodft_tlgc); + + /* Set SDR timing registers */ + regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | + EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS | + EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD | + EMIF4_TIM1_T_RP); + writel(regval, &emif4_base->sdram_time1); + writel(regval, &emif4_base->sdram_time1_shdw); + + regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP | + EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR | + EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP); + writel(regval, &emif4_base->sdram_time2); + writel(regval, &emif4_base->sdram_time2_shdw); + + regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC); + writel(regval, &emif4_base->sdram_time3); + writel(regval, &emif4_base->sdram_time3_shdw); + + /* Set the PWR control register */ + regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE | + EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE); + writel(regval, &emif4_base->sdram_pwr_mgmt); + writel(regval, &emif4_base->sdram_pwr_mgmt_shdw); + + /* Set the DDR refresh rate control register */ + regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS); + writel(regval, &emif4_base->sdram_refresh_ctrl); + writel(regval, &emif4_base->sdram_refresh_ctrl_shdw); + + /* set the SDRAM configuration register */ + regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK | + EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE | + EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD | + EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL | + EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM | + EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP); + writel(regval, &emif4_base->sdram_config); +} diff --git a/arch/arm/mach-omap/am3xxx.c b/arch/arm/mach-omap/am3xxx.c new file mode 100644 index 0000000000..75965a8e0e --- /dev/null +++ b/arch/arm/mach-omap/am3xxx.c @@ -0,0 +1,32 @@ +#include <common.h> +#include <io.h> +#include <mach/am3xxx-silicon.h> + +/* UART Defines */ +#define UART_SYSCFG_OFFSET 0x54 +#define UART_SYSSTS_OFFSET 0x58 + +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_RESET (0x1 << 1) +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +void am3xxx_uart_soft_reset(void __iomem *uart_base) +{ + int reg; + + reg = readl(uart_base + UART_SYSCFG_OFFSET); + reg |= UART_RESET; + writel(reg, (uart_base + UART_SYSCFG_OFFSET)); + + while ((readl(uart_base + UART_SYSSTS_OFFSET) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + reg = readl((uart_base + UART_SYSCFG_OFFSET)); + reg |= UART_SMART_IDLE_EN; + writel(reg, (uart_base + UART_SYSCFG_OFFSET)); +} + +void am33xx_uart_soft_reset(void __iomem *uart_base) + __alias(am3xxx_uart_soft_reset);
\ No newline at end of file diff --git a/arch/arm/mach-omap/dmtimer.c b/arch/arm/mach-omap/dmtimer.c deleted file mode 100644 index e223b8cc8f..0000000000 --- a/arch/arm/mach-omap/dmtimer.c +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file - * @brief Support DMTimer counter - * - * FileName: arch/arm/mach-omap/dmtimer.c - */ -/* - * This File is based on arch/arm/mach-omap/s32k_clksource.c - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * (C) Copyright 2012 Phytec Messtechnik GmbH - * Author: Teresa Gámez <t.gamez@phytec.de> - * (C) Copyright 2015 Phytec Messtechnik GmbH - * Author: Daniel Schultz <d.schultz@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <clock.h> -#include <init.h> -#include <io.h> -#include <mach/am33xx-silicon.h> -#include <mach/am33xx-clock.h> - -#include <stdio.h> - -#define CLK_RC32K 32768 - -#define TIDR 0x0 -#define TIOCP_CFG 0x10 -#define IRQ_EOI 0x20 -#define IRQSTATUS_RAW 0x24 -#define IRQSTATUS 0x28 -#define IRQSTATUS_SET 0x2c -#define IRQSTATUS_CLR 0x30 -#define IRQWAKEEN 0x34 -#define TCLR 0x38 -#define TCRR 0x3C -#define TLDR 0x40 -#define TTGR 0x44 -#define TWPS 0x48 -#define TMAR 0x4C -#define TCAR1 0x50 -#define TSICR 0x54 -#define TCAR2 0x58 - -static void *base = (void *)AM33XX_DMTIMER2_BASE; - -/** - * @brief Provide a simple counter read - * - * @return DMTimer counter - */ -static uint64_t dmtimer_read(void) -{ - return readl(base + TCRR); -} - -static struct clocksource dmtimer_cs = { - .read = dmtimer_read, - .mask = CLOCKSOURCE_MASK(32), - .shift = 10, -}; - -/** - * @brief Initialize the Clock - * - * Enable dmtimer. - * - * @return result of @ref init_clock - */ -static int dmtimer_init(void) -{ - u64 clk_speed; - - clk_speed = am33xx_get_osc_clock(); - clk_speed *= 1000; - dmtimer_cs.mult = clocksource_hz2mult(clk_speed, dmtimer_cs.shift); - - /* Enable counter */ - writel(0x3, base + TCLR); - - return init_clock(&dmtimer_cs); -} - -/* Run me at boot time */ -core_initcall(dmtimer_init); diff --git a/arch/arm/mach-omap/include/mach/am3xxx-silicon.h b/arch/arm/mach-omap/include/mach/am3xxx-silicon.h new file mode 100644 index 0000000000..c5f73ad457 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/am3xxx-silicon.h @@ -0,0 +1,6 @@ +#ifndef __ASM_ARCH_AM33XX_H +#define __ASM_ARCH_AM33XX_H + +void am3xxx_uart_soft_reset(void __iomem *uart_base); + +#endif /* __ASM_ARCH_AM33XX_H */
\ No newline at end of file diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h new file mode 100644 index 0000000000..1f9c2938a1 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/emif4.h @@ -0,0 +1,105 @@ +/* + * Auther: + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ + +/* + * Configuration values + */ +#define EMIF4_TIM1_T_RP (0x3 << 25) +#define EMIF4_TIM1_T_RCD (0x3 << 21) +#define EMIF4_TIM1_T_WR (0x3 << 17) +#define EMIF4_TIM1_T_RAS (0x7 << 12) /* 8->7 */ +#define EMIF4_TIM1_T_RC (0xA << 6) +#define EMIF4_TIM1_T_RRD (0x2 << 3) +#define EMIF4_TIM1_T_WTR (0x2) + +#define EMIF4_TIM2_T_XP (0x2 << 28) +#define EMIF4_TIM2_T_ODT (0x0 << 25) /* 2? */ +#define EMIF4_TIM2_T_XSNR (0x1C << 16) +#define EMIF4_TIM2_T_XSRD (0xC8 << 6) +#define EMIF4_TIM2_T_RTP (0x1 << 3) +#define EMIF4_TIM2_T_CKE (0x2) + +#define EMIF4_TIM3_T_RFC (0x15 << 4) /* 25->15 */ +#define EMIF4_TIM3_T_RAS_MAX (0xf) /* 7->f */ + +#define EMIF4_PWR_IDLE_MODE (0x2 << 30) +#define EMIF4_PWR_DPD_DIS (0x0 << 10) +#define EMIF4_PWR_DPD_EN (0x1 << 10) +#define EMIF4_PWR_LP_MODE (0x0 << 8) +#define EMIF4_PWR_PM_TIM (0x0) + +#define EMIF4_INITREF_DIS (0x0 << 31) +#define EMIF4_REFRESH_RATE (0x257) /* 50f->257 */ + +#define EMIF4_CFG_SDRAM_TYP (0x2 << 29) +#define EMIF4_CFG_IBANK_POS (0x0 << 27) +#define EMIF4_CFG_DDR_TERM (0x3 << 24) /* --> 0x3 */ +#define EMIF4_CFG_DDR2_DDQS (0x1 << 23) +#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20) +#define EMIF4_CFG_SDR_DRV (0x0 << 18) +#define EMIF4_CFG_NARROW_MD (0x0 << 14) +#define EMIF4_CFG_CL (0x5 << 10) +#define EMIF4_CFG_ROWSIZE (0x0 << 7) /* --> 0x4: a0..a12 */ +#define EMIF4_CFG_IBANK (0x3 << 4) +#define EMIF4_CFG_EBANK (0x0 << 3) +#define EMIF4_CFG_PGSIZE (0x2) /* 10 columns */ + +/* + * EMIF4 PHY Control 1 register configuration + */ +#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7) +#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7) +#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6) +#define EMIF4_DDR1_PWRDN_EN (0x1 << 6) +#define EMIF4_DDR1_READ_LAT (0x6 << 0) + +struct emif4 { + unsigned int emif_mod_id_rev; + unsigned int sdram_sts; + unsigned int sdram_config; + unsigned int res1; + unsigned int sdram_refresh_ctrl; + unsigned int sdram_refresh_ctrl_shdw; + unsigned int sdram_time1; + unsigned int sdram_time1_shdw; + unsigned int sdram_time2; + unsigned int sdram_time2_shdw; + unsigned int sdram_time3; + unsigned int sdram_time3_shdw; + unsigned char res2[8]; + unsigned int sdram_pwr_mgmt; + unsigned int sdram_pwr_mgmt_shdw; + unsigned char res3[32]; + unsigned int sdram_iodft_tlgc; + unsigned char res4[128]; + unsigned int ddr_phyctrl1; + unsigned int ddr_phyctrl1_shdw; + unsigned int ddr_phyctrl2; +}; + +void am35xx_emif4_init(void); + +#endif /* endif _EMIF_H_ */ diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h index 7c52da754f..849964ab3e 100644 --- a/arch/arm/mach-omap/include/mach/omap3-clock.h +++ b/arch/arm/mach-omap/include/mach/omap3-clock.h @@ -64,6 +64,8 @@ #define CM_CLKSEL_CAM 0X0f40 #define CM_FCLKEN_PER 0X1000 #define CM_ICLKEN_PER 0X1010 +#define CM_IDLEST_PER 0X1020 +#define CM_AUTOIDLE_PER 0X1030 #define CM_CLKSEL_PER 0X1040 #define CM_CLKSEL1_EMU 0X1140 #define CM_FCLKEN_USBH 0x1400 diff --git a/arch/arm/mach-omap/include/mach/omap3-mux.h b/arch/arm/mach-omap/include/mach/omap3-mux.h index d6fb9c393c..a679e25567 100644 --- a/arch/arm/mach-omap/include/mach/omap3-mux.h +++ b/arch/arm/mach-omap/include/mach/omap3-mux.h @@ -413,4 +413,51 @@ #define CONTROL_PADCONF_SDRC_CKE0 0x0262 #define CONTROL_PADCONF_SDRC_CKE1 0x0264 -#endif /* _ASM_ARCH_OMAP3_MUX_H_ */ +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 + +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 + +/* AM/DM37xx specific */ +#define CONTROL_PADCONF_GPIO127 0x0A54 +#define CONTROL_PADCONF_GPIO126 0x0A56 +#define CONTROL_PADCONF_GPIO128 0x0A58 +#define CONTROL_PADCONF_GPIO129 0x0A5A + +#endif diff --git a/arch/arm/mach-omap/include/mach/omap4-generic.h b/arch/arm/mach-omap/include/mach/omap4-generic.h index 7ec41d880b..c1d0a3c900 100644 --- a/arch/arm/mach-omap/include/mach/omap4-generic.h +++ b/arch/arm/mach-omap/include/mach/omap4-generic.h @@ -1,6 +1,7 @@ #ifndef __MACH_OMAP4_GENERIC_H #define __MACH_OMAP4_GENERIC_H +#include <linux/sizes.h> #include <mach/generic.h> #include <mach/omap4-silicon.h> diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h index e36f49df8a..57bfb3c680 100644 --- a/arch/arm/mach-omap/include/mach/sys_info.h +++ b/arch/arm/mach-omap/include/mach/sys_info.h @@ -43,6 +43,7 @@ #define CPU_3350 0x3350 #define CPU_3430 0x3430 #define CPU_3630 0x3630 +#define CPU_AM35XX 0x3500 /** * Define CPU revisions @@ -84,6 +85,7 @@ #define OMAP_HAWKEYE_34XX 0xB7AE /* OMAP34xx */ #define OMAP_HAWKEYE_36XX 0xB891 /* OMAP36xx */ #define OMAP_HAWKEYE_335X 0xB944 /* AM335x */ +#define OMAP_HAWKEYE_AM35XX 0xb868 /* AM35xx */ /** These are implemented by the System specific code in omapX-generic.c */ u32 get_cpu_type(void); diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c index 6700f56f39..03b866c28e 100644 --- a/arch/arm/mach-omap/omap3_clock.c +++ b/arch/arm/mach-omap/omap3_clock.c @@ -290,7 +290,7 @@ static struct dpll_param mpu_dpll_param_34x_es1[] = { static struct dpll_param mpu_dpll_param_34x_es2[] = { {.m = 0x0FA, .n = 0x05, .fsel = 0x07, .m2 = 0x01, }, /* 12 MHz */ - {.m = 0x1F4, .n = 0x0C, .fsel = 0x03, .m2 = 0x01, }, /* 13 MHz */ + {.m = 0x258, .n = 0x0C, .fsel = 0x03, .m2 = 0x01, }, /* 13 MHz */ {.m = 0x271, .n = 0x17, .fsel = 0x03, .m2 = 0x01, }, /* 19.2 MHz */ {.m = 0x0FA, .n = 0x0C, .fsel = 0x07, .m2 = 0x01, }, /* 26 MHz */ {.m = 0x271, .n = 0x2F, .fsel = 0x03, .m2 = 0x01, }, /* 38.4 MHz */ @@ -617,11 +617,12 @@ void prcm_init(void) sr32(OMAP3_CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS); wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_PLL_MPU), LDELAY); - if (cpu_type == CPU_3430) { + if (cpu_type == CPU_3430 || cpu_type == CPU_AM35XX) { init_core_dpll_34x(cpu_rev, clk_index); init_per_dpll_34x(cpu_rev, clk_index); init_mpu_dpll_34x(cpu_rev, clk_index); - init_iva_dpll_34x(cpu_rev, clk_index); + if (cpu_type != CPU_AM35XX) + init_iva_dpll_34x(cpu_rev, clk_index); } else if (cpu_type == CPU_3630) { init_core_dpll_36x(cpu_rev, clk_index); @@ -676,7 +677,12 @@ static void per_clocks_enable(void) #define ICK_CAM_ON 0x00000001 #define FCK_PER_ON 0x0003ffff #define ICK_PER_ON 0x0003ffff - sr32(OMAP3_CM_REG(FCLKEN_IVA2), 0, 32, FCK_IVA2_ON); + + if (get_cpu_type() != CPU_AM35XX) { + sr32(OMAP3_CM_REG(FCLKEN_IVA2), 0, 32, FCK_IVA2_ON); + sr32(OMAP3_CM_REG(FCLKEN_CAM), 0, 32, FCK_CAM_ON); + sr32(OMAP3_CM_REG(ICLKEN_CAM), 0, 32, ICK_CAM_ON); + } sr32(OMAP3_CM_REG(FCLKEN1_CORE), 0, 32, FCK_CORE1_ON); sr32(OMAP3_CM_REG(ICLKEN1_CORE), 0, 32, ICK_CORE1_ON); sr32(OMAP3_CM_REG(ICLKEN2_CORE), 0, 32, ICK_CORE2_ON); @@ -684,8 +690,6 @@ static void per_clocks_enable(void) sr32(OMAP3_CM_REG(ICLKEN_WKUP), 0, 32, ICK_WKUP_ON); sr32(OMAP3_CM_REG(FCLKEN_DSS), 0, 32, FCK_DSS_ON); sr32(OMAP3_CM_REG(ICLKEN_DSS), 0, 32, ICK_DSS_ON); - sr32(OMAP3_CM_REG(FCLKEN_CAM), 0, 32, FCK_CAM_ON); - sr32(OMAP3_CM_REG(ICLKEN_CAM), 0, 32, ICK_CAM_ON); sr32(OMAP3_CM_REG(FCLKEN_PER), 0, 32, FCK_PER_ON); sr32(OMAP3_CM_REG(ICLKEN_PER), 0, 32, ICK_PER_ON); diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c index 5327bad1aa..cff4a4fb11 100644 --- a/arch/arm/mach-omap/omap3_generic.c +++ b/arch/arm/mach-omap/omap3_generic.c @@ -43,6 +43,8 @@ #include <mach/wdt.h> #include <mach/sys_info.h> #include <mach/syslib.h> +#include <mach/omap3-generic.h> +#include <reset_source.h> /** * @brief Reset the CPU @@ -77,6 +79,9 @@ u32 get_cpu_type(void) if (hawkeye == OMAP_HAWKEYE_34XX) return CPU_3430; + if (hawkeye == OMAP_HAWKEYE_AM35XX) + return CPU_AM35XX; + if (hawkeye == OMAP_HAWKEYE_36XX) return CPU_3630; @@ -486,12 +491,60 @@ static int omap3_bootsource(void) return 0; } +#define OMAP3_PRM_RSTST_OFF 0x8 +#define OMAP3_REG_PRM_RSTST (OMAP3_PRM_REG(RSTCTRL) + OMAP3_PRM_RSTST_OFF) + +#define OMAP3_ICECRUSHER_RST BIT(10) +#define OMAP3_ICEPICK_RST BIT(9) +#define OMAP3_EXTERNAL_WARM_RST BIT(6) +#define OMAP3_SECURE_WD_RST BIT(5) +#define OMAP3_MPU_WD_RST BIT(4) +#define OMAP3_SECURITY_VIOL_RST BIT(3) +#define OMAP3_GLOBAL_SW_RST BIT(1) +#define OMAP3_GLOBAL_COLD_RST BIT(0) + +static void omap3_detect_reset_reason(void) +{ + uint32_t val = 0; + + val = readl(OMAP3_REG_PRM_RSTST); + /* clear OMAP3_PRM_RSTST - must be cleared by software */ + writel(val, OMAP3_REG_PRM_RSTST); + + switch (val) { + case OMAP3_ICECRUSHER_RST: + case OMAP3_ICEPICK_RST: + reset_source_set(RESET_JTAG); + break; + case OMAP3_EXTERNAL_WARM_RST: + reset_source_set(RESET_EXT); + break; + case OMAP3_SECURE_WD_RST: + case OMAP3_MPU_WD_RST: + case OMAP3_SECURITY_VIOL_RST: + reset_source_set(RESET_WDG); + break; + case OMAP3_GLOBAL_SW_RST: + reset_source_set(RESET_RST); + break; + case OMAP3_GLOBAL_COLD_RST: + reset_source_set(RESET_POR); + break; + default: + reset_source_set(RESET_UKWN); + break; + } +} + int omap3_init(void) { omap_gpmc_base = (void *)OMAP3_GPMC_BASE; restart_handler_register_fn(omap3_restart_soc); + if (IS_ENABLED(CONFIG_RESET_SOURCE)) + omap3_detect_reset_reason(); + return omap3_bootsource(); } @@ -532,6 +585,9 @@ static int omap3_gpio_init(void) int omap3_devices_init(void) { - return omap3_gpio_init(); + omap3_gpio_init(); + add_generic_device("omap-32ktimer", 0, NULL, OMAP3_32KTIMER_BASE, 0x400, + IORESOURCE_MEM, NULL); + return 0; } #endif diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index a3f370df8f..1f71153848 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -10,6 +10,7 @@ #include <mach/generic.h> #include <mach/gpmc.h> #include <mach/omap4_rom_usb.h> +#include <mach/omap4-generic.h> /* * The following several lines are taken from U-Boot to support @@ -179,7 +180,7 @@ static inline void delay(unsigned long loops) "bne 1b" : "=r" (loops) : "0"(loops)); } -int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs) +static int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs) { /* * set SDRAM CONFIG register @@ -684,5 +685,8 @@ static int omap4_gpio_init(void) int omap4_devices_init(void) { - return omap4_gpio_init(); + omap4_gpio_init(); + add_generic_device("omap-32ktimer", 0, NULL, OMAP44XX_32KTIMER_BASE, 0x400, + IORESOURCE_MEM, NULL); + return 0; } diff --git a/arch/arm/mach-omap/s32k_clksource.c b/arch/arm/mach-omap/s32k_clksource.c deleted file mode 100644 index 7def8b1807..0000000000 --- a/arch/arm/mach-omap/s32k_clksource.c +++ /dev/null @@ -1,85 +0,0 @@ -/** - * @file - * @brief Provide @ref clocksource functionality for OMAP - * - * @ref clocksource provides a neat architecture. all we do is - * To loop in with Sync 32Khz clock ticking away at 32768hz on OMAP. - * Sync 32Khz clock is an always ON clock. - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <clock.h> -#include <init.h> -#include <io.h> -#include <mach/omap3-silicon.h> -#include <mach/omap4-silicon.h> -#include <mach/clocks.h> -#include <mach/timers.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> - -/** Sync 32Khz Timer registers */ -#define S32K_CR 0x10 -#define S32K_FREQUENCY 32768 - -static void __iomem *timerbase; - -/** - * @brief Provide a simple clock read - * - * Nothing is simpler.. read direct from clock and provide it - * to the caller. - * - * @return S32K clock counter - */ -static uint64_t s32k_clocksource_read(void) -{ - return readl(timerbase + S32K_CR); -} - -/* A bit obvious isn't it? */ -static struct clocksource s32k_cs = { - .read = s32k_clocksource_read, - .mask = CLOCKSOURCE_MASK(32), - .shift = 10, -}; - -/** - * @brief Initialize the Clock - * - * There is nothing to do on OMAP as SYNC32K clock is - * always on, and we do a simple data structure initialization. - * 32K clock gives 32768 ticks a seconds - * - * @return result of @ref init_clock - */ -static int s32k_clocksource_init(void) -{ - if (IS_ENABLED(CONFIG_ARCH_OMAP3)) - timerbase = (void *)OMAP3_32KTIMER_BASE; - else if (IS_ENABLED(CONFIG_ARCH_OMAP4)) - timerbase = (void *)OMAP44XX_32KTIMER_BASE; - else - BUG(); - - s32k_cs.mult = clocksource_hz2mult(S32K_FREQUENCY, s32k_cs.shift); - - return init_clock(&s32k_cs); -} - -/* Run me at boot time */ -core_initcall(s32k_clocksource_init); |