diff options
Diffstat (limited to 'arch/arm')
44 files changed, 240 insertions, 306 deletions
diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c index d27d9e4ddf..ad47ee2558 100644 --- a/arch/arm/boards/guf-vincell/board.c +++ b/arch/arm/boards/guf-vincell/board.c @@ -40,6 +40,9 @@ static void vincell_fec_reset(void) static int vincell_devices_init(void) { + if (!of_machine_is_compatible("guf,imx53-vincell")) + return 0; + writel(0, MX53_M4IF_BASE_ADDR + 0xc); clk_set_rate(clk_lookup("emi_slow_podf"), 133333334); diff --git a/arch/arm/boards/phytec-phycore-pxa270/board.c b/arch/arm/boards/phytec-phycore-pxa270/board.c index 833c4c81e4..1424c9c937 100644 --- a/arch/arm/boards/phytec-phycore-pxa270/board.c +++ b/arch/arm/boards/phytec-phycore-pxa270/board.c @@ -26,7 +26,7 @@ #include <partition.h> #include <linux/sizes.h> -#include <plat/gpio.h> +#include <gpio.h> #include <mach/mfp-pxa27x.h> #include <mach/pxa-regs.h> #include <mach/pxafb.h> diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c index 5f65261a9f..d3100c88b3 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/board.c +++ b/arch/arm/boards/phytec-phyflex-imx6/board.c @@ -16,6 +16,7 @@ * Foundation. * */ +#define pr_fmt(fmt) "phyFLEX-i.MX6: " fmt #include <malloc.h> #include <envfs.h> @@ -27,12 +28,16 @@ #include <of.h> #include <mach/bbu.h> #include <fec.h> +#include <globalvar.h> #include <linux/micrel_phy.h> #include <mach/iomux-mx6.h> #include <mach/imx6.h> +#define PHYFLEX_MODULE_REV_1 0x1 +#define PHYFLEX_MODULE_REV_2 0x2 + #define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \ MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS @@ -64,10 +69,24 @@ static void phyflex_err006282_workaround(void) gpio_direction_input(MX6_PHYFLEX_ERR006282); } +static unsigned int pfla02_module_revision; + +static unsigned int get_module_rev(void) +{ + unsigned int val = 0; + + val = gpio_get_value(IMX_GPIO_NR(2, 12)); + val |= (gpio_get_value(IMX_GPIO_NR(2, 13)) << 1); + val |= (gpio_get_value(IMX_GPIO_NR(2, 14)) << 2); + val |= (gpio_get_value(IMX_GPIO_NR(2, 15)) << 3); + + return 16 - val; +} + static int phytec_pfla02_init(void) { int ret; - char *environment_path; + char *environment_path, *envdev; if (!of_machine_is_compatible("phytec,imx6q-pfla02") && !of_machine_is_compatible("phytec,imx6dl-pfla02") && @@ -78,17 +97,25 @@ static int phytec_pfla02_init(void) imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + pfla02_module_revision = get_module_rev(); + globalvar_add_simple_int("board.revision", &pfla02_module_revision, "%u"); + + pr_info("Module Revision: %u\n", pfla02_module_revision); + switch (bootsource_get()) { case BOOTSOURCE_MMC: environment_path = asprintf("/chosen/environment-sd%d", bootsource_get_instance() + 1); + envdev = "MMC"; break; case BOOTSOURCE_NAND: environment_path = asprintf("/chosen/environment-nand"); + envdev = "NAND flash"; break; default: case BOOTSOURCE_SPI: environment_path = asprintf("/chosen/environment-spinor"); + envdev = "SPI NOR flash"; break; } @@ -99,6 +126,8 @@ static int phytec_pfla02_init(void) free(environment_path); + pr_notice("Using environment in %s\n", envdev); + return 0; } device_initcall(phytec_pfla02_init); diff --git a/arch/arm/boards/zylonite/board.c b/arch/arm/boards/zylonite/board.c index dabc6ffb0b..2caadbcecc 100644 --- a/arch/arm/boards/zylonite/board.c +++ b/arch/arm/boards/zylonite/board.c @@ -28,6 +28,7 @@ #include <net/smc91111.h> #include <platform_data/mtd-nand-mrvl.h> #include <pwm.h> +#include <linux/sizes.h> #include <mach/devices.h> #include <mach/mfp-pxa3xx.h> @@ -66,6 +67,8 @@ static int zylonite_devices_init(void) &smsc91x_pdata); add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL, 0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata); + devfs_add_partition("nand0", SZ_1M, SZ_256K, DEVFS_PARTITION_FIXED, + "env0"); return 0; } device_initcall(zylonite_devices_init); diff --git a/arch/arm/boards/zylonite/env/bin/init b/arch/arm/boards/zylonite/env/bin/init deleted file mode 100644 index a6bc087b22..0000000000 --- a/arch/arm/boards/zylonite/env/bin/init +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config -addpart /dev/nand0 $mtdparts -usbserial -s "Zylonite usb gadget" - -# Phase1: check for MTD override -mtd_env_override -if [ $? = 0 ]; then - echo "Switching to custom environment" - /env/init - exit -fi - -# Phase2: initiate network -dhcp -H zylonite - -# Phase3: activate netconsole, broadcast everywhere -netconsole.ip=255.255.255.255 -netconsole.active=ioe -netconsole.port=6666 - diff --git a/arch/arm/boards/zylonite/env/bin/mtd_env_override b/arch/arm/boards/zylonite/env/bin/mtd_env_override deleted file mode 100644 index 6ea253a4f0..0000000000 --- a/arch/arm/boards/zylonite/env/bin/mtd_env_override +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -loadenv /dev/nand0.barebox-env -exit $? diff --git a/arch/arm/boards/zylonite/env/boot/nand-ubi b/arch/arm/boards/zylonite/env/boot/nand-ubi new file mode 100644 index 0000000000..2231738224 --- /dev/null +++ b/arch/arm/boards/zylonite/env/boot/nand-ubi @@ -0,0 +1,5 @@ +#!/bin/sh + +global.bootm.image="/dev/nand0.kernel" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:linux_root ubi.mtd=nand.root rootfstype=ubifs" diff --git a/arch/arm/boards/zylonite/env/config b/arch/arm/boards/zylonite/env/config deleted file mode 100644 index ee66e37cc3..0000000000 --- a/arch/arm/boards/zylonite/env/config +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -autoboot_timeout=3 - -mtdparts="128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)" -bootargs="$bootargs mtdparts=pxa3xx_nand-0:$mtdparts ubi.mtd=5 rootfstype=ubifs root=ubi0:root ro ram=64M console=ttyS0,115200" diff --git a/arch/arm/boards/zylonite/env/init/mtdparts-nand b/arch/arm/boards/zylonite/env/init/mtdparts-nand new file mode 100644 index 0000000000..9db4652c40 --- /dev/null +++ b/arch/arm/boards/zylonite/env/init/mtdparts-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)" +kernelname="pxa3xx_nand-0" + +mtdparts-add -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/zylonite/env/nv/hostname b/arch/arm/boards/zylonite/env/nv/hostname new file mode 100644 index 0000000000..6e6d865eda --- /dev/null +++ b/arch/arm/boards/zylonite/env/nv/hostname @@ -0,0 +1 @@ +zylonite diff --git a/arch/arm/boards/zylonite/env/nv/linux.bootargs.base b/arch/arm/boards/zylonite/env/nv/linux.bootargs.base new file mode 100644 index 0000000000..317f8b16a1 --- /dev/null +++ b/arch/arm/boards/zylonite/env/nv/linux.bootargs.base @@ -0,0 +1 @@ +ram=64M diff --git a/arch/arm/boards/zylonite/env/nv/linux.bootargs.console b/arch/arm/boards/zylonite/env/nv/linux.bootargs.console new file mode 100644 index 0000000000..476b1fbe49 --- /dev/null +++ b/arch/arm/boards/zylonite/env/nv/linux.bootargs.console @@ -0,0 +1 @@ +console=ttyS0,115200 diff --git a/arch/arm/configs/zylonite310_defconfig b/arch/arm/configs/zylonite310_defconfig index fa6587c0ee..ffe3215354 100644 --- a/arch/arm/configs/zylonite310_defconfig +++ b/arch/arm/configs/zylonite310_defconfig @@ -8,17 +8,17 @@ CONFIG_ARM_UNWIND=y # CONFIG_BANNER is not set CONFIG_MMU=y CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000 -CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_MALLOC_SIZE=0x800000 CONFIG_EXPERIMENTAL=y CONFIG_MODULES=y CONFIG_KALLSYMS=y CONFIG_PROMPT="zylonite-barebox:" -CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/zylonite/env" CONFIG_RESET_SOURCE=y CONFIG_DEFAULT_LOGLEVEL=8 @@ -27,8 +27,6 @@ CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y CONFIG_CMD_MEMINFO=y -CONFIG_FLEXIBLE_BOOTARGS=y -CONFIG_CMD_BOOT=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y CONFIG_CMD_BOOTM_INITRD=y @@ -40,26 +38,20 @@ CONFIG_CMD_LOADY=y CONFIG_CMD_RESET=y CONFIG_CMD_SAVES=y CONFIG_CMD_PARTITION=y -CONFIG_CMD_AUTOMOUNT=y CONFIG_CMD_UBIFORMAT=y CONFIG_CMD_EXPORT=y -CONFIG_CMD_GLOBAL=y CONFIG_CMD_LOADENV=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_SAVEENV=y -CONFIG_CMD_BASENAME=y CONFIG_CMD_CMP=y -CONFIG_CMD_DIRNAME=y CONFIG_CMD_FILETYPE=y CONFIG_CMD_LN=y -CONFIG_CMD_READLINK=y CONFIG_CMD_UNCOMPRESS=y CONFIG_CMD_LET=y CONFIG_CMD_MSLEEP=y CONFIG_CMD_SLEEP=y CONFIG_CMD_DHCP=y CONFIG_CMD_HOST=y -CONFIG_NET_CMD_IFUP=y CONFIG_CMD_MIITOOL=y CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c index 2be562d7de..428dd93249 100644 --- a/arch/arm/cpu/cache-l2x0.c +++ b/arch/arm/cpu/cache-l2x0.c @@ -1,3 +1,5 @@ +#define pr_fmt(fmt) "l2x0: " fmt + #include <common.h> #include <init.h> #include <io.h> @@ -7,6 +9,7 @@ #define CACHE_LINE_SIZE 32 static void __iomem *l2x0_base; +static uint32_t l2x0_way_mask; /* Bitmask of active ways */ static inline void cache_wait(void __iomem *reg, unsigned long mask) { @@ -50,8 +53,8 @@ static inline void l2x0_flush_line(unsigned long addr) static inline void l2x0_inv_all(void) { /* invalidate all ways */ - writel(0xff, l2x0_base + L2X0_INV_WAY); - cache_wait(l2x0_base + L2X0_INV_WAY, 0xff); + writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); + cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); cache_sync(); } @@ -112,6 +115,13 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) cache_sync(); } +static void l2x0_flush_all(void) +{ + writel(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); + cache_wait(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); + cache_sync(); +} + static void l2x0_disable(void) { writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY); @@ -122,9 +132,37 @@ static void l2x0_disable(void) void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) { __u32 aux; + __u32 cache_id; + int ways; + const char *type; l2x0_base = base; + cache_id = readl(l2x0_base + L2X0_CACHE_ID); + aux = readl(l2x0_base + L2X0_AUX_CTRL); + + /* Determine the number of ways */ + switch (cache_id & L2X0_CACHE_ID_PART_MASK) { + case L2X0_CACHE_ID_PART_L310: + if (aux & (1 << 16)) + ways = 16; + else + ways = 8; + type = "L310"; + break; + case L2X0_CACHE_ID_PART_L210: + ways = (aux >> 13) & 0xf; + type = "L210"; + break; + default: + /* Assume unknown chips have 8 ways */ + ways = 8; + type = "L2x0 series"; + break; + } + + l2x0_way_mask = (1 << ways) - 1; + /* * Check if l2x0 controller is already enabled. * If you are booting from non-secure mode @@ -149,5 +187,9 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.clean_range = l2x0_clean_range; outer_cache.flush_range = l2x0_flush_range; outer_cache.disable = l2x0_disable; -} + outer_cache.flush_all = l2x0_flush_all; + pr_debug("%s cache controller enabled\n", type); + pr_debug("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", + ways, cache_id, aux); +} diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c index 7b161d59d6..27ead1c177 100644 --- a/arch/arm/cpu/cache.c +++ b/arch/arm/cpu/cache.c @@ -71,6 +71,8 @@ void __mmu_cache_flush(void) { if (cache_fns) cache_fns->mmu_cache_flush(); + if (outer_cache.flush_all) + outer_cache.flush_all(); } int arm_set_cache_functions(void) diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c index 5e708023e4..ff8f43d175 100644 --- a/arch/arm/cpu/cpu.c +++ b/arch/arm/cpu/cpu.c @@ -79,10 +79,9 @@ struct outer_cache_fns outer_cache; */ void mmu_disable(void) { + __mmu_cache_flush(); if (outer_cache.disable) outer_cache.disable(); - - __mmu_cache_flush(); __mmu_cache_off(); } diff --git a/arch/arm/cpu/exceptions.S b/arch/arm/cpu/exceptions.S index f17f1e11e4..eda0d6ab8d 100644 --- a/arch/arm/cpu/exceptions.S +++ b/arch/arm/cpu/exceptions.S @@ -220,9 +220,9 @@ _fiq: .word fiq .align 4 .global arm_ignore_data_abort arm_ignore_data_abort: -.word arm_ignore_data_abort /* When != 0 data aborts are ignored */ +.word 0 /* When != 0 data aborts are ignored */ .global arm_data_abort_occurred arm_data_abort_occurred: -.word arm_data_abort_occurred /* set != 0 by the data abort handler */ +.word 0 /* set != 0 by the data abort handler */ abort_stack: .space 8 diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index 37bfa058a5..7b185d713b 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -66,6 +66,7 @@ static inline void tlb_invalidate(void) } #define PTE_FLAGS_CACHED_V7 (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE) +#define PTE_FLAGS_WC_V7 PTE_EXT_TEX(1) #define PTE_FLAGS_UNCACHED_V7 (0) #define PTE_FLAGS_CACHED_V4 (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE) #define PTE_FLAGS_UNCACHED_V4 PTE_SMALL_AP_UNO_SRW @@ -75,6 +76,7 @@ static inline void tlb_invalidate(void) * This will be determined at runtime. */ static uint32_t pte_flags_cached; +static uint32_t pte_flags_wc; static uint32_t pte_flags_uncached; #define PTE_MASK ((1 << 12) - 1) @@ -159,9 +161,9 @@ static u32 *find_pte(unsigned long adr) static void dma_flush_range(unsigned long start, unsigned long end) { + __dma_flush_range(start, end); if (outer_cache.flush_range) outer_cache.flush_range(start, end); - __dma_flush_range(start, end); } static void dma_inv_range(unsigned long start, unsigned long end) @@ -325,9 +327,11 @@ static int mmu_init(void) if (cpu_architecture() >= CPU_ARCH_ARMv7) { pte_flags_cached = PTE_FLAGS_CACHED_V7; + pte_flags_wc = PTE_FLAGS_WC_V7; pte_flags_uncached = PTE_FLAGS_UNCACHED_V7; } else { pte_flags_cached = PTE_FLAGS_CACHED_V4; + pte_flags_wc = PTE_FLAGS_UNCACHED_V4; pte_flags_uncached = PTE_FLAGS_UNCACHED_V4; } @@ -408,6 +412,22 @@ void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle) return ret; } +void *dma_alloc_writecombine(size_t size, dma_addr_t *dma_handle) +{ + void *ret; + + size = PAGE_ALIGN(size); + ret = xmemalign(PAGE_SIZE, size); + if (dma_handle) + *dma_handle = (dma_addr_t)ret; + + dma_inv_range((unsigned long)ret, (unsigned long)ret + size); + + remap_range(ret, size, pte_flags_wc); + + return ret; +} + unsigned long virt_to_phys(volatile void *virt) { return (unsigned long)virt; diff --git a/arch/arm/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/dts/imx27-phytec-phycore-rdk.dts index 9d216afa3a..f602045c7e 100644 --- a/arch/arm/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/dts/imx27-phytec-phycore-rdk.dts @@ -10,13 +10,13 @@ environment-nor { compatible = "barebox,environment"; - device-path = &nor, "partname:env"; + device-path = &environment_nor; status = "disabled"; }; environment-nand { compatible = "barebox,environment"; - device-path = &nfc, "partname:env"; + device-path = &environment_nand; status = "disabled"; }; }; @@ -32,7 +32,7 @@ reg = <0x00000000 0x00080000>; }; - partition@1 { + environment_nand: partition@1 { label = "env"; reg = <0x00080000 0x00020000>; }; @@ -54,7 +54,7 @@ reg = <0x00000000 0x00080000>; }; - partition@1 { + environment_nor: partition@1 { label = "env"; reg = <0x00080000 0x00020000>; }; diff --git a/arch/arm/dts/imx51-babbage.dts b/arch/arm/dts/imx51-babbage.dts index 909774bd52..f8402ca8fa 100644 --- a/arch/arm/dts/imx51-babbage.dts +++ b/arch/arm/dts/imx51-babbage.dts @@ -18,7 +18,7 @@ environment@0 { compatible = "barebox,environment"; - device-path = &esdhc1, "partname:barebox-environment"; + device-path = &environment_esdhc1; }; }; }; @@ -27,7 +27,7 @@ #address-cells = <1>; #size-cells = <1>; - partition@0 { + environment_esdhc1: partition@0 { label = "barebox-environment"; reg = <0x80000 0x20000>; }; diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi index 4007a092a8..bf634e49d4 100644 --- a/arch/arm/dts/imx53-qsb-common.dtsi +++ b/arch/arm/dts/imx53-qsb-common.dtsi @@ -16,7 +16,7 @@ environment@0 { compatible = "barebox,environment"; - device-path = &esdhc1, "partname:barebox-environment"; + device-path = &bareboxenv; }; }; }; @@ -25,7 +25,7 @@ #address-cells = <1>; #size-cells = <1>; - partition@0 { + bareboxenv: partition@0 { label = "barebox-environment"; reg = <0x80000 0x20000>; }; diff --git a/arch/arm/dts/imx6dl-eltec-hipercam.dts b/arch/arm/dts/imx6dl-eltec-hipercam.dts index 737752f0b1..166f8f1244 100644 --- a/arch/arm/dts/imx6dl-eltec-hipercam.dts +++ b/arch/arm/dts/imx6dl-eltec-hipercam.dts @@ -15,7 +15,7 @@ environment@0 { compatible = "barebox,environment"; - device-path = &norflash0, "partname:bareboxenv"; + device-path = &environment_nor0; }; }; }; @@ -39,7 +39,7 @@ reg = <0x0 0xc0000>; }; - partition@1 { + environment_nor0: partition@1 { label = "bareboxenv"; reg = <0xc0000 0x8000>; }; diff --git a/arch/arm/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi index 0f801aebc9..47154d5d9f 100644 --- a/arch/arm/dts/imx6dl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi @@ -16,7 +16,3 @@ model = "Phytec phyFLEX-i.MX6 Dual Lite"; compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; }; - -&ecspi3 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx6q-phytec-pbab01.dts b/arch/arm/dts/imx6q-phytec-pbab01.dts index 580338dff8..2f816dd1ac 100644 --- a/arch/arm/dts/imx6q-phytec-pbab01.dts +++ b/arch/arm/dts/imx6q-phytec-pbab01.dts @@ -16,8 +16,4 @@ / { model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; compatible = "phytec,imx6x-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; - - chosen { - linux,stdout-path = &uart4; - }; }; diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi index 6435ab791d..97cf78a73c 100644 --- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi +++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi @@ -19,13 +19,13 @@ chosen { environment-sd { compatible = "barebox,environment"; - device-path = &usdhc3, "partname:barebox-environment"; + device-path = &environment_usdhc3; status = "disabled"; }; environment-nand { compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; + device-path = &environment_nand; status = "disabled"; }; }; @@ -139,7 +139,7 @@ reg = <0x0 0x400000>; }; - partition@1 { + environment_nand: partition@1 { label = "barebox-environment"; reg = <0x400000 0x20000>; }; @@ -183,7 +183,7 @@ label = "barebox"; reg = <0x0 0x80000>; }; - partition@1 { + environment_usdhc3: partition@1 { label = "barebox-environment"; reg = <0x80000 0x80000>; }; diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi index b1172dc095..48f1da3cad 100644 --- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6q-phytec-pfla02.dtsi @@ -17,7 +17,3 @@ model = "Phytec phyFLEX-i.MX6 Quad"; compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; }; - -&ecspi3 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts index 71ca855251..1f92c15242 100644 --- a/arch/arm/dts/imx6q-sabresd.dts +++ b/arch/arm/dts/imx6q-sabresd.dts @@ -25,7 +25,7 @@ environment@0 { compatible = "barebox,environment"; - device-path = &usdhc3, "partname:barebox-environment"; + device-path = &environment_usdhc3; }; }; }; diff --git a/arch/arm/dts/imx6q-var-custom.dts b/arch/arm/dts/imx6q-var-custom.dts index 795114d841..ef6981e3bc 100644 --- a/arch/arm/dts/imx6q-var-custom.dts +++ b/arch/arm/dts/imx6q-var-custom.dts @@ -30,7 +30,7 @@ environment@0 { compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; + device-path = &environment_nand; }; }; diff --git a/arch/arm/dts/imx6q-var-som.dtsi b/arch/arm/dts/imx6q-var-som.dtsi index 792691191e..d005f319d6 100644 --- a/arch/arm/dts/imx6q-var-som.dtsi +++ b/arch/arm/dts/imx6q-var-som.dtsi @@ -42,7 +42,7 @@ reg = <0x0 0x200000>; }; - partition@1 { + environment_nand: partition@1 { label = "barebox-environment"; reg = <0x200000 0x20000>; }; diff --git a/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi index 157e130ff1..86ab991c91 100644 --- a/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi @@ -9,22 +9,8 @@ * http://www.gnu.org/copyleft/gpl.html */ -&fec { - status = "okay"; -}; +#include <arm/imx6qdl-phytec-pbab01.dtsi> &uart1 { status = "okay"; }; - -&uart4 { - status = "okay"; -}; - -&usdhc2 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index 5ac0ef9431..b79ce2c0f9 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -9,7 +9,14 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include <arm/imx6qdl-phytec-pfla02.dtsi> + / { + memory { + /* let barebox fill the memory node */ + reg = <0 0>; + }; + chosen { environment-nand { compatible = "barebox,environment"; @@ -50,17 +57,7 @@ }; &ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "disabled"; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 24 0>; - - flash: m25p80@0 { - compatible = "m25p80"; - spi-max-frequency = <20000000>; - reg = <0>; - + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -87,12 +84,7 @@ }; &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 0>; - status = "disabled"; mdio { #address-cells = <1>; @@ -108,10 +100,6 @@ }; &gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; #address-cells = <1>; #size-cells = <1>; @@ -143,44 +131,20 @@ &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - ecspi3 { - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - >; - }; - }; + pinctrl-0 = <&pinctrl_hog>, <&pinctrl_rev>; - enet { - pinctrl_enet: enetgrp { + imx6q-phytec-pfla02 { + pinctrl_rev: revgrp { fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x80000000 + MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x80000000 + MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x80000000 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000 >; }; - }; - gpmi-nand { - pinctrl_gpmi_nand: gpmi-nand { + pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 @@ -204,79 +168,13 @@ >; }; }; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 - >; - }; - }; - - uart4 { - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - }; - - usdhc2 { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - }; - - usdhc3 { - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - >; - }; - }; }; &ocotp { barebox,provide-mac-address = <&fec 0x620>; }; -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 0>; - wp-gpios = <&gpio1 2 0>; - status = "disabled"; -}; - &usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio1 27 0>; - wp-gpios = <&gpio1 29 0>; - status = "disabled"; - #address-cells = <1>; #size-cells = <1>; @@ -284,6 +182,7 @@ label = "barebox"; reg = <0x0 0x80000>; }; + partition@1 { label = "barebox-environment"; reg = <0x80000 0x80000>; diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi index 54201bdb7e..32318cf389 100644 --- a/arch/arm/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi @@ -34,7 +34,7 @@ reg = <0x0 0x80000>; }; - partition@1 { + environment_usdhc3: partition@1 { label = "barebox-environment"; reg = <0x80000 0x80000>; }; diff --git a/arch/arm/dts/imx6s-riotboard.dts b/arch/arm/dts/imx6s-riotboard.dts index 117c00a575..a522dd9934 100644 --- a/arch/arm/dts/imx6s-riotboard.dts +++ b/arch/arm/dts/imx6s-riotboard.dts @@ -17,7 +17,7 @@ environment@0 { compatible = "barebox,environment"; - device-path = &usdhc4, "partname:barebox-environment"; + device-path = &environment_usdhc4; }; }; @@ -232,7 +232,7 @@ reg = <0x0 0x80000>; }; - partition@1 { + environment_usdhc4: partition@1 { label = "barebox-environment"; reg = <0x80000 0x80000>; }; diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h deleted file mode 100644 index b3c1efe739..0000000000 --- a/arch/arm/include/asm/gpio.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _ARCH_ARM_GPIO_H -#define _ARCH_ARM_GPIO_H - -#ifndef CONFIG_GPIOLIB -#include <mach/gpio.h> -#else -#include <asm-generic/gpio.h> -#endif - -#endif /* _ARCH_ARM_GPIO_H */ diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index 97bb0dbeb6..3b19e9ef3c 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h @@ -67,6 +67,7 @@ struct outer_cache_fns { void (*inv_range)(unsigned long, unsigned long); void (*clean_range)(unsigned long, unsigned long); void (*flush_range)(unsigned long, unsigned long); + void (*flush_all)(void); void (*disable)(void); }; diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 4e9d6865ab..bdc0cb6879 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -7,8 +7,6 @@ #ifndef __AT91_GPIO_H__ #define __AT91_GPIO_H__ -#include <asm-generic/gpio.h> - #define MAX_NB_GPIO_PER_BANK 32 static inline unsigned pin_to_bank(unsigned pin) diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-ep93xx/include/mach/gpio.h deleted file mode 100644 index 306ab4c9f2..0000000000 --- a/arch/arm/mach-ep93xx/include/mach/gpio.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/gpio.h> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 0de2d3e153..f2dc52d518 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -175,15 +175,18 @@ config ARCH_IMX53 config ARCH_IMX6 bool + select ARCH_HAS_L2X0 select ARCH_HAS_FEC_IMX select CPU_V7 select PINCTRL_IMX_IOMUX_V3 + select OFTREE select COMMON_CLK_OF_PROVIDER select HW_HAS_PCI config ARCH_IMX6SX bool select ARCH_IMX6 + select OFTREE select COMMON_CLK_OF_PROVIDER config IMX_MULTI_BOARDS diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 7508964bf5..ceabe19dc2 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -22,6 +22,7 @@ #include <mach/imx6-anadig.h> #include <mach/imx6-regs.h> #include <mach/generic.h> +#include <asm/mmu.h> #define SI_REV 0x260 @@ -193,3 +194,37 @@ int imx6_devices_init(void) return 0; } + +#define L310_PREFETCH_CTRL 0xF60 + +static int imx6_mmu_init(void) +{ + void __iomem *l2x0_base = IOMEM(0x00a02000); + u32 val; + + if (!cpu_is_mx6()) + return 0; + + /* Configure the L2 PREFETCH and POWER registers */ + val = readl(l2x0_base + L310_PREFETCH_CTRL); + val |= 0x70800000; + + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + if (cpu_is_mx6q()) + val &= ~(1 << 30 | 1 << 23); + + writel(val, l2x0_base + L310_PREFETCH_CTRL); + + l2x0_init(l2x0_base, 0x0, ~0UL); + + return 0; +} +postmmu_initcall(imx6_mmu_init); diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h deleted file mode 100644 index 8643c98d5a..0000000000 --- a/arch/arm/mach-mxs/include/mach/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2010 Juergen Beisert - Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_MACH_GPIO_H -#define __ASM_MACH_GPIO_H - -#include <asm-generic/gpio.h> - -#endif /* __ASM_MACH_GPIO_H */ diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c index 4e98493e73..7dd6ac0648 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/mach-pxa/gpio.c @@ -66,3 +66,35 @@ int __init pxa_init_gpio(int start, int end) return 0; } + +int gpio_get_value(unsigned gpio) +{ + return GPLR(gpio) & GPIO_bit(gpio); +} + +void gpio_set_value(unsigned gpio, int value) +{ + if (value) + GPSR(gpio) = GPIO_bit(gpio); + else + GPCR(gpio) = GPIO_bit(gpio); +} + +int gpio_direction_input(unsigned gpio) +{ + if (__gpio_is_inverted(gpio)) + GPDR(gpio) |= GPIO_bit(gpio); + else + GPDR(gpio) &= ~GPIO_bit(gpio); + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); + if (__gpio_is_inverted(gpio)) + GPDR(gpio) &= ~GPIO_bit(gpio); + else + GPDR(gpio) |= GPIO_bit(gpio); + return 0; +} diff --git a/arch/arm/mach-pxa/include/plat/gpio.h b/arch/arm/mach-pxa/include/plat/gpio.h index 4c7b5266fb..35f90715e0 100644 --- a/arch/arm/mach-pxa/include/plat/gpio.h +++ b/arch/arm/mach-pxa/include/plat/gpio.h @@ -31,38 +31,6 @@ #define GFER_OFFSET 0x3C #define GEDR_OFFSET 0x48 -static inline int gpio_get_value(unsigned gpio) -{ - return GPLR(gpio) & GPIO_bit(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - if (value) - GPSR(gpio) = GPIO_bit(gpio); - else - GPCR(gpio) = GPIO_bit(gpio); -} - -static inline int gpio_direction_input(unsigned gpio) -{ - if (__gpio_is_inverted(gpio)) - GPDR(gpio) |= GPIO_bit(gpio); - else - GPDR(gpio) &= ~GPIO_bit(gpio); - return 0; -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - gpio_set_value(gpio, value); - if (__gpio_is_inverted(gpio)) - GPDR(gpio) &= ~GPIO_bit(gpio); - else - GPDR(gpio) |= GPIO_bit(gpio); - return 0; -} - /* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). * Those cases currently cause holes in the GPIO number space, the * actual number of the last GPIO is recorded by 'pxa_last_gpio'. diff --git a/arch/arm/mach-samsung/gpio-s3c24x0.c b/arch/arm/mach-samsung/gpio-s3c24x0.c index f62588f0e7..58ca284eab 100644 --- a/arch/arm/mach-samsung/gpio-s3c24x0.c +++ b/arch/arm/mach-samsung/gpio-s3c24x0.c @@ -15,7 +15,7 @@ #include <errno.h> #include <io.h> #include <mach/s3c-iomap.h> -#include <mach/gpio.h> +#include <gpio.h> #include <mach/s3c24xx-gpio.h> #include <mach/iomux.h> diff --git a/arch/arm/mach-samsung/include/mach/gpio.h b/arch/arm/mach-samsung/include/mach/gpio.h deleted file mode 100644 index 39206676f8..0000000000 --- a/arch/arm/mach-samsung/include/mach/gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_MACH_GPIO_H -#define __ASM_MACH_GPIO_H - -#include <asm-generic/gpio.h> - -#endif /* __ASM_MACH_GPIO_H */ |