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-rw-r--r--arch/arm/boards/microchip-ksz9477-evb/lowlevel.c33
-rw-r--r--arch/arm/boards/skov-imx6/version.c88
-rw-r--r--arch/arm/boards/skov-imx6/version.h6
-rw-r--r--arch/arm/dts/imx6qdl-phytec-pfla02.dtsi2
-rw-r--r--arch/arm/mach-at91/Kconfig2
-rw-r--r--arch/arm/mach-at91/Makefile1
-rw-r--r--arch/arm/mach-at91/boot_test_cmd.c3
-rw-r--r--arch/arm/mach-at91/ddramc.c8
-rw-r--r--arch/arm/mach-at91/include/mach/ddramc.h1
-rw-r--r--arch/arm/mach-at91/include/mach/sama5_bootsource.h3
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h88
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3_ll.h24
-rw-r--r--arch/arm/mach-at91/include/mach/xload.h4
-rw-r--r--arch/arm/mach-at91/sama5d3_ll.c34
-rw-r--r--arch/arm/mach-at91/xload-mmc.c51
-rw-r--r--arch/arm/mach-imx/imx.c4
16 files changed, 335 insertions, 17 deletions
diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
index 30a5760da6..93ae481975 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
+++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
@@ -8,20 +8,16 @@
#include <init.h>
#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
-#include <mach/at91_pmc_ll.h>
-
-#include <mach/hardware.h>
-#include <mach/iomux.h>
#include <debug_ll.h>
-#include <mach/at91_dbgu.h>
+#include <mach/barebox-arm.h>
+#include <mach/iomux.h>
+#include <mach/sama5d3.h>
+#include <mach/sama5d3-xplained-ddramc.h>
+#include <mach/xload.h>
/* PCK = 528MHz, MCK = 132MHz */
#define MASTER_CLOCK 132000000
-#define sama5d3_pmc_enable_periph_clock(clk) \
- at91_pmc_enable_periph_clock(IOMEM(SAMA5D3_BASE_PMC), clk)
-
static void dbgu_init(void)
{
void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
@@ -36,14 +32,27 @@ static void dbgu_init(void)
putc_ll('>');
}
+SAMA5_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071_xload_mmc, r4)
+{
+ sama5d3_lowlevel_init();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ sama5d3_udelay_init(MASTER_CLOCK);
+ sama5d3_xplained_ddrconf();
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ dbgu_init();
+
+ sama5d3_atmci_start_image(0, MASTER_CLOCK, 0);
+}
+
extern char __dtb_z_at91_microchip_ksz9477_evb_start[];
-ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
+SAMA5_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r4)
{
void *fdt;
- arm_cpu_lowlevel_init();
-
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE);
if (IS_ENABLED(CONFIG_DEBUG_LL))
diff --git a/arch/arm/boards/skov-imx6/version.c b/arch/arm/boards/skov-imx6/version.c
new file mode 100644
index 0000000000..5a6a0625ca
--- /dev/null
+++ b/arch/arm/boards/skov-imx6/version.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#define pr_fmt(fmt) "skov-imx6: " fmt
+
+#include <common.h>
+#include <mach/iomux-mx6.h>
+#include <mach/imx-gpio.h>
+#include <mach/imx6.h>
+
+#include "version.h"
+
+#define V_PAD_CTRL MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \
+ MX6_PAD_CTL_SPEED_LOW
+
+unsigned skov_imx6_get_version(void)
+{
+ void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+ void __iomem *gpiobase = IOMEM(MX6_GPIO2_BASE_ADDR);
+ unsigned reg;
+ unsigned var = 0;
+ int cpu_type = __imx6_cpu_type();
+
+ /* mux pins as GPIOs */
+ switch (cpu_type) {
+ case IMX6_CPUTYPE_IMX6S:
+ case IMX6_CPUTYPE_IMX6DL:
+ writel(0x05, iomuxbase + 0x348); /* VERSION_0, GPIO2/10 */
+ writel(V_PAD_CTRL, iomuxbase + 0x730);
+ writel(0x05, iomuxbase + 0x35c); /* VERSION_1, GPIO2/15 */
+ writel(V_PAD_CTRL, iomuxbase + 0x744);
+ writel(0x05, iomuxbase + 0x340); /* VERSION_2, GPIO2/8 */
+ writel(V_PAD_CTRL, iomuxbase + 0x728);
+ writel(0x05, iomuxbase + 0x344); /* VERSION_3, GPIO2/9 */
+ writel(V_PAD_CTRL, iomuxbase + 0x72C);
+ writel(0x05, iomuxbase + 0x350); /* VERSION_4, GPIO2/12 */
+ writel(V_PAD_CTRL, iomuxbase + 0x738);
+ writel(0x05, iomuxbase + 0x358); /* VERSION_5, GPIO2/14 */
+ writel(V_PAD_CTRL, iomuxbase + 0x740);
+ writel(0x05, iomuxbase + 0x34c); /* VERSION_6, GPIO2/11 */
+ writel(V_PAD_CTRL, iomuxbase + 0x734);
+ writel(0x05, iomuxbase + 0x354); /* VERSION_7, GPIO2/13 */
+ writel(V_PAD_CTRL, iomuxbase + 0x73C);
+ break;
+ case IMX6_CPUTYPE_IMX6D:
+ case IMX6_CPUTYPE_IMX6Q:
+ writel(0x05, iomuxbase + 0x324); /* VERSION_0, GPIO2/10 */
+ writel(V_PAD_CTRL, iomuxbase + 0x70c);
+ writel(0x05, iomuxbase + 0x338); /* VERSION_1, GPIO2/15 */
+ writel(V_PAD_CTRL, iomuxbase + 0x720);
+ writel(0x05, iomuxbase + 0x31c); /* VERSION_2, GPIO2/8 */
+ writel(V_PAD_CTRL, iomuxbase + 0x704);
+ writel(0x05, iomuxbase + 0x320); /* VERSION_3, GPIO2/9 */
+ writel(V_PAD_CTRL, iomuxbase + 0x708);
+ writel(0x05, iomuxbase + 0x32c); /* VERSION_4, GPIO2/12 */
+ writel(V_PAD_CTRL, iomuxbase + 0x714);
+ writel(0x05, iomuxbase + 0x334); /* VERSION_5, GPIO2/14 */
+ writel(V_PAD_CTRL, iomuxbase + 0x71c);
+ writel(0x05, iomuxbase + 0x328); /* VERSION_6, GPIO2/11 */
+ writel(V_PAD_CTRL, iomuxbase + 0x710);
+ writel(0x05, iomuxbase + 0x330); /* VERSION_7, GPIO2/13 */
+ writel(V_PAD_CTRL, iomuxbase + 0x718);
+ break;
+ default:
+ pr_err("Invalid SoC! i.MX6S/DL or i.MX6Q expected (found %d)\n", cpu_type);
+ return -1;
+ }
+
+ imx6_gpio_direction_input(gpiobase, 13);
+ imx6_gpio_direction_input(gpiobase, 11);
+ imx6_gpio_direction_input(gpiobase, 14);
+ imx6_gpio_direction_input(gpiobase, 12);
+ imx6_gpio_direction_input(gpiobase, 9);
+ imx6_gpio_direction_input(gpiobase, 8);
+ imx6_gpio_direction_input(gpiobase, 15);
+ imx6_gpio_direction_input(gpiobase, 10);
+
+ reg = readl(gpiobase + 0x00);
+ var |= imx6_gpio_val(gpiobase, 13) << 7;
+ var |= imx6_gpio_val(gpiobase, 11) << 6;
+ var |= imx6_gpio_val(gpiobase, 14) << 5;
+ var |= imx6_gpio_val(gpiobase, 12) << 4;
+ var |= imx6_gpio_val(gpiobase, 9) << 3;
+ var |= imx6_gpio_val(gpiobase, 8) << 2;
+ var |= imx6_gpio_val(gpiobase, 15) << 1;
+ var |= imx6_gpio_val(gpiobase, 10) << 0;
+
+ return (~var) & 0xff;
+}
diff --git a/arch/arm/boards/skov-imx6/version.h b/arch/arm/boards/skov-imx6/version.h
new file mode 100644
index 0000000000..008410490b
--- /dev/null
+++ b/arch/arm/boards/skov-imx6/version.h
@@ -0,0 +1,6 @@
+#ifndef __SKOV_VERSION_H
+#define __SKOV_VERSION_H
+
+unsigned skov_imx6_get_version(void);
+
+#endif /* __SKOV_VERSION_H */
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index e1aa3183b3..0653fcc3c3 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -115,7 +115,7 @@
&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>, <&pinctrl_rev>;
+ pinctrl-0 = <&pinctrl_rev>;
imx6q-phytec-pfla02 {
pinctrl_rev: revgrp {
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 810c00d495..28a82c1a93 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -45,6 +45,7 @@ config HAVE_AT91_DDRAMC
config AT91_MCI_PBL
bool
+ depends on MCI_ATMEL_PBL
depends on MCI_ATMEL_SDHCI_PBL
default y
@@ -610,6 +611,7 @@ config MACH_MICROCHIP_KSZ9477_EVB
bool "Microchip EVB-KSZ9477 Evaluation Kit"
select SOC_SAMA5D3
select OFDEVICE
+ select MCI_ATMEL_PBL
select COMMON_CLK_OF_PROVIDER
help
Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 9cfba28fa0..c895af7a2f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o sama5d3_devices.o
endif
lwl-$(CONFIG_SOC_SAMA5D2) += sama5d2_ll.o
obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
+lwl-$(CONFIG_SOC_SAMA5D3) += sama5d3_ll.o
obj-$(CONFIG_SOC_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o
obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o
obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o
diff --git a/arch/arm/mach-at91/boot_test_cmd.c b/arch/arm/mach-at91/boot_test_cmd.c
index 4fd1998ad0..7bb40f2e40 100644
--- a/arch/arm/mach-at91/boot_test_cmd.c
+++ b/arch/arm/mach-at91/boot_test_cmd.c
@@ -24,7 +24,6 @@ static int do_at91_boot_test(int argc, char *argv[])
int ret = 1;
char *sram = "/dev/sram0";
u32 read_size, write_size;
- u32 tmp = 0;
while ((opt = getopt(argc, argv, "j:s:")) > 0) {
switch (opt) {
@@ -64,7 +63,7 @@ static int do_at91_boot_test(int argc, char *argv[])
}
while (write_size) {
- tmp = write(fd, buf, write_size);
+ int tmp = write(fd, buf, write_size);
if (tmp < 0) {
perror("write");
goto err_open;
diff --git a/arch/arm/mach-at91/ddramc.c b/arch/arm/mach-at91/ddramc.c
index c3ef6b0090..0aece5345f 100644
--- a/arch/arm/mach-at91/ddramc.c
+++ b/arch/arm/mach-at91/ddramc.c
@@ -26,6 +26,14 @@ void __noreturn sama5d2_barebox_entry(unsigned int r4, void *boarddata)
boarddata);
}
+void __noreturn sama5d3_barebox_entry(unsigned int r4, void *boarddata)
+{
+ __sama5d3_stashed_bootrom_r4 = r4;
+
+ barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(),
+ boarddata);
+}
+
static int sama5_ddr_probe(struct device_d *dev)
{
struct resource *iores;
diff --git a/arch/arm/mach-at91/include/mach/ddramc.h b/arch/arm/mach-at91/include/mach/ddramc.h
index 5d6f3a70b7..7daef17636 100644
--- a/arch/arm/mach-at91/include/mach/ddramc.h
+++ b/arch/arm/mach-at91/include/mach/ddramc.h
@@ -33,5 +33,6 @@ void at91_lpddr1_sdram_initialize(void __iomem *base_address,
const struct at91_ddramc_register *ddramc_config);
void __noreturn sama5d2_barebox_entry(unsigned int r4, void *boarddata);
+void __noreturn sama5d3_barebox_entry(unsigned int r4, void *boarddata);
#endif /* #ifndef __DDRAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/sama5_bootsource.h b/arch/arm/mach-at91/include/mach/sama5_bootsource.h
index 8355c2eeb6..931e1f29c8 100644
--- a/arch/arm/mach-at91/include/mach/sama5_bootsource.h
+++ b/arch/arm/mach-at91/include/mach/sama5_bootsource.h
@@ -46,6 +46,9 @@ static inline int sama5_bootsource_instance(u32 reg)
#define __sama5d2_stashed_bootrom_r4 \
(*(volatile u32 *)(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE - 0x4))
+#define __sama5d3_stashed_bootrom_r4 \
+ (*(volatile u32 *)(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 0x4))
+
static inline void __noreturn sama5_boot_xload(void __noreturn (*bb)(void), u32 r4)
{
asm volatile("mov r4, %0" : : "r"(r4) : );
diff --git a/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h b/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h
new file mode 100644
index 0000000000..6f829282c6
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: BSD-1-Clause
+ *
+ * Copyright (C) 2014, Atmel Corporation
+ *
+ * SAMA5D27 System-in-Package DDRAMC configuration
+ */
+
+#include <mach/at91_ddrsdrc.h>
+#include <mach/ddramc.h>
+#include <mach/sama5d3_ll.h>
+
+static inline void sama5d3_xplained_ddrconf(void)
+{
+ const struct at91_ddramc_register conf = {
+ .mdr = AT91_DDRC2_DBW_32_BITS | AT91_DDRC2_MD_DDR2_SDRAM,
+
+ .cr = AT91_DDRC2_NC_DDR10_SDR9
+ | AT91_DDRC2_NR_13
+ | AT91_DDRC2_CAS_3
+ | AT91_DDRC2_DISABLE_RESET_DLL
+ | AT91_DDRC2_ENABLE_DLL
+ | AT91_DDRC2_ENRDM_ENABLE
+ | AT91_DDRC2_NB_BANKS_8
+ | AT91_DDRC2_NDQS_DISABLED
+ | AT91_DDRC2_DECOD_INTERLEAVED
+ | AT91_DDRC2_UNAL_SUPPORTED,
+
+ /*
+ * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
+ * With a 133 MHz frequency, the refresh timer count register must to be
+ * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
+ * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
+ */
+ .rtr = 0x40F, /* Refresh timer: 7.812us */
+
+ /* One clock cycle @ 133 MHz = 7.5 ns */
+ .t0pr = AT91_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
+ | AT91_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
+ | AT91_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
+ | AT91_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
+ | AT91_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
+ | AT91_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
+ | AT91_DDRC2_TWTR_(2) /* 2 clock cycles min */
+ | AT91_DDRC2_TMRD_(2), /* 2 clock cycles */
+
+ .t1pr = AT91_DDRC2_TXP_(2) /* 2 clock cycles */
+ | AT91_DDRC2_TXSRD_(200) /* 200 clock cycles */
+ | AT91_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns */
+ | AT91_DDRC2_TRFC_(17), /* 17 * 7.5 = 127.5 ns */
+
+ .t2pr = AT91_DDRC2_TFAW_(6) /* 6 * 7.5 = 45 ns */
+ | AT91_DDRC2_TRTP_(2) /* 2 clock cycles min */
+ | AT91_DDRC2_TRPA_(2) /* 2 * 7.5 = 15 ns */
+ | AT91_DDRC2_TXARDS_(8) /* = TXARD */
+ | AT91_DDRC2_TXARD_(8), /* MR12 = 1 */
+ };
+ u32 reg;
+
+ /* enable ddr2 clock */
+ sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_MPDDRC);
+ at91_pmc_enable_system_clock(IOMEM(SAMA5D3_BASE_PMC), AT91CAP9_PMC_DDR);
+
+
+ /* Init the special register for sama5d3x */
+ /* MPDDRC DLL Slave Offset Register: DDR2 configuration */
+ reg = AT91_MPDDRC_S0OFF_1
+ | AT91_MPDDRC_S2OFF_1
+ | AT91_MPDDRC_S3OFF_1;
+ writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_DLL_SOR);
+
+ /* MPDDRC DLL Master Offset Register */
+ /* write master + clk90 offset */
+ reg = AT91_MPDDRC_MOFF_7
+ | AT91_MPDDRC_CLK90OFF_31
+ | AT91_MPDDRC_SELOFF_ENABLED | AT91_MPDDRC_KEY;
+ writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_DLL_MOR);
+
+ /* MPDDRC I/O Calibration Register */
+ /* DDR2 RZQ = 50 Ohm */
+ /* TZQIO = 4 */
+ reg = AT91_MPDDRC_RDIV_DDR2_RZQ_50
+ | AT91_MPDDRC_TZQIO_4;
+ writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_IO_CALIBR);
+
+ /* DDRAM2 Controller initialize */
+ at91_ddram_initialize(IOMEM(SAMA5D3_BASE_MPDDRC), IOMEM(SAMA5_DDRCS),
+ &conf);
+}
diff --git a/arch/arm/mach-at91/include/mach/sama5d3_ll.h b/arch/arm/mach-at91/include/mach/sama5d3_ll.h
new file mode 100644
index 0000000000..b5b6b5d820
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d3_ll.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __SAMA5D3_LL_H__
+#define __SAMA5D3_LL_H__
+
+#include <mach/at91_pmc_ll.h>
+#include <mach/debug_ll.h>
+#include <mach/early_udelay.h>
+
+void sama5d3_lowlevel_init(void);
+
+static inline void sama5d3_pmc_enable_periph_clock(int clk)
+{
+ at91_pmc_enable_periph_clock(IOMEM(SAMA5D3_BASE_PMC), clk);
+}
+
+/* requires relocation */
+static inline void sama5d3_udelay_init(unsigned int msc)
+{
+ early_udelay_init(IOMEM(SAMA5D3_BASE_PMC), IOMEM(SAMA5D3_BASE_PIT),
+ SAMA5D3_ID_PIT, msc, AT91_PMC_LL_SAMA5D3);
+}
+
+#endif /* __SAMA5D3_LL_H__ */
diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h
index 338577c221..bbc70af210 100644
--- a/arch/arm/mach-at91/include/mach/xload.h
+++ b/arch/arm/mach-at91/include/mach/xload.h
@@ -5,7 +5,11 @@
#include <pbl.h>
void __noreturn sama5d2_sdhci_start_image(u32 r4);
+void __noreturn sama5d3_atmci_start_image(u32 r4, unsigned int clock,
+ unsigned int slot);
int at91_sdhci_bio_init(struct pbl_bio *bio, void __iomem *base);
+int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
+ unsigned int clock, unsigned int slot);
#endif /* __MACH_XLOAD_H */
diff --git a/arch/arm/mach-at91/sama5d3_ll.c b/arch/arm/mach-at91/sama5d3_ll.c
new file mode 100644
index 0000000000..4650593699
--- /dev/null
+++ b/arch/arm/mach-at91/sama5d3_ll.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
+// SPDX-FileCopyrightText: 2017, Microchip Corporation
+
+#include <mach/at91_wdt.h>
+#include <mach/barebox-arm.h>
+#include <mach/sama5d3_ll.h>
+
+void sama5d3_lowlevel_init(void)
+{
+ arm_cpu_lowlevel_init();
+
+ at91_wdt_disable(IOMEM(SAMA5D3_BASE_WDT));
+ at91_pmc_init(IOMEM(SAMA5D3_BASE_PMC), AT91_PMC_LL_SAMA5D3);
+
+ /* At this stage the main oscillator
+ * is supposed to be enabled PCK = MCK = MOSC
+ */
+
+ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
+ at91_pmc_cfg_plla(IOMEM(SAMA5D3_BASE_PMC), AT91_PMC3_MUL_(43)
+ | AT91_PMC_OUT_0 | AT91_PMC_PLLCOUNT
+ | AT91_PMC_DIV_BYPASS, AT91_PMC_LL_SAMA5D3);
+
+ /* Initialize PLLA charge pump */
+ at91_pmc_init_pll(IOMEM(SAMA5D3_BASE_PMC), AT91_PMC_IPLLA_3);
+
+ /* Switch PCK/MCK on Main clock output */
+ at91_pmc_cfg_mck(IOMEM(SAMA5D3_BASE_PMC), AT91SAM9_PMC_MDIV_4
+ | AT91_PMC_CSS_MAIN, AT91_PMC_LL_SAMA5D3);
+
+ /* Switch PCK/MCK on PLLA output */
+ at91_pmc_cfg_mck(IOMEM(SAMA5D3_BASE_PMC), AT91SAM9_PMC_MDIV_4
+ | AT91_PMC_CSS_PLLA, AT91_PMC_LL_SAMA5D3);
+}
diff --git a/arch/arm/mach-at91/xload-mmc.c b/arch/arm/mach-at91/xload-mmc.c
index e9edeccb7f..8d4f653d1e 100644
--- a/arch/arm/mach-at91/xload-mmc.c
+++ b/arch/arm/mach-at91/xload-mmc.c
@@ -3,6 +3,7 @@
#include <mach/sama5_bootsource.h>
#include <mach/hardware.h>
#include <mach/sama5d2_ll.h>
+#include <mach/sama5d3_ll.h>
#include <mach/gpio.h>
#include <linux/sizes.h>
#include <asm/cache.h>
@@ -82,3 +83,53 @@ void __noreturn sama5d2_sdhci_start_image(u32 r4)
out_panic:
panic("FAT chainloading failed\n");
}
+
+static const struct atmci_instance {
+ void __iomem *base;
+ unsigned id;
+ u8 periph;
+ s8 pins[15];
+} sama5d3_atmci_instances[] = {
+ [0] = {
+ .base = IOMEM(SAMA5D3_BASE_HSMCI0),
+ .id = SAMA5D3_ID_HSMCI0,
+ .periph = AT91_MUX_PERIPH_A,
+ .pins = {
+ AT91_PIN_PD0, AT91_PIN_PD1, AT91_PIN_PD2, AT91_PIN_PD3,
+ AT91_PIN_PD4, AT91_PIN_PD5, AT91_PIN_PD6, AT91_PIN_PD7,
+ AT91_PIN_PD8, AT91_PIN_PD9, -1 }
+ },
+};
+
+void __noreturn sama5d3_atmci_start_image(u32 boot_src, unsigned int clock,
+ unsigned int slot)
+{
+ void *buf = (void *)SAMA5_DDRCS;
+ const struct atmci_instance *instance;
+ struct pbl_bio bio;
+ const s8 *pin;
+ int ret;
+
+ ret = sama5_bootsource_instance(boot_src);
+ if (ret > ARRAY_SIZE(sama5d3_atmci_instances) - 1)
+ panic("Couldn't determine boot MCI instance\n");
+
+ instance = &sama5d3_atmci_instances[boot_src];
+
+ sama5d3_pmc_enable_periph_clock(SAMA5D2_ID_PIOD);
+ for (pin = instance->pins; *pin >= 0; pin++) {
+ at91_mux_pio3_pin(IOMEM(SAMA5D3_BASE_PIOD),
+ pin_to_mask(*pin), instance->periph, 0);
+ }
+
+ sama5d3_pmc_enable_periph_clock(instance->id);
+
+ ret = at91_mci_bio_init(&bio, instance->base, clock, slot);
+ if (ret)
+ goto out_panic;
+
+ at91_fat_start_image(&bio, buf, SZ_16M, boot_src);
+
+out_panic:
+ panic("FAT chainloading failed\n");
+}
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 3d8c55c54e..bd7e9ac423 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -209,6 +209,6 @@ void imx_set_reset_reason(void __iomem *srsr,
reset_source_set_prinst(type, RESET_SOURCE_DEFAULT_PRIORITY, instance);
- pr_info("i.MX reset reason %s (SRSR: 0x%08x)\n",
- reset_source_to_string(type), reg);
+ pr_debug("i.MX reset reason %s (SRSR: 0x%08x)\n",
+ reset_source_to_string(type), reg);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 13:08:42 +0000