diff options
Diffstat (limited to 'arch/arm')
76 files changed, 1342 insertions, 1479 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f4213f48f4..59fce0c601 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -68,9 +68,13 @@ config ARCH_CLPS711X select CLKDEV_LOOKUP select CLOCKSOURCE_CLPS711X select COMMON_CLK + select COMMON_CLK_OF_PROVIDER select CPU_32v4T select GPIOLIB + select HAS_DEBUG_LL + select HAVE_PBL_MULTI_IMAGES select MFD_SYSCON + select RELOCATABLE config ARCH_DAVINCI bool "TI Davinci" diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index d303999614..3ccde26f1b 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -192,3 +192,4 @@ obj-$(CONFIG_MACH_SKOV_ARM9CPU) += skov-arm9cpu/ obj-$(CONFIG_MACH_RK3568_EVB) += rockchip-rk3568-evb/ obj-$(CONFIG_MACH_RK3568_BPI_R2PRO) += rockchip-rk3568-bpi-r2pro/ obj-$(CONFIG_MACH_PINE64_QUARTZ64) += pine64-quartz64/ +obj-$(CONFIG_MACH_RADXA_ROCK3) += radxa-rock3/ diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c index de40f6c5af..7c94b19c9f 100644 --- a/arch/arm/boards/afi-gf/lowlevel.c +++ b/arch/arm/boards/afi-gf/lowlevel.c @@ -10,11 +10,12 @@ #include <mach/am33xx-generic.h> #include <mach/am33xx-silicon.h> #include <mach/am33xx-clock.h> +#include <mach/emif4.h> +#include <mach/generic.h> #include <mach/sdrc.h> #include <mach/sys_info.h> #include <mach/syslib.h> #include <mach/am33xx-mux.h> -#include <mach/wdt.h> #include <debug_ll.h> /* AM335X EMIF Register values */ @@ -130,34 +131,35 @@ static void board_config_vtp(void) static void board_config_emif_ddr(void) { + const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE); u32 i; /*Program EMIF0 CFG Registers*/ - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); - __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); - __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); - __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); - __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); - __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); - __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); - - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); - - __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + __raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1); + __raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW); + __raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_2); + __raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1); + __raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW); + __raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2); + __raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW); + __raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3); + __raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW); + + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG); + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2); + + __raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL); + __raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); for (i = 0; i < 5000; i++) { } - __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + __raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL); + __raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG); + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2); } static void board_config_ddr(void) @@ -209,13 +211,7 @@ static noinline int gf_sram_init(void) fdt = __dtb_z_am335x_afi_gf_start; - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); - __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); /* Setup the PLLs and the clocks for the peripherals */ am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_200); diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c index 544e396e03..ebec4b5419 100644 --- a/arch/arm/boards/beaglebone/lowlevel.c +++ b/arch/arm/boards/beaglebone/lowlevel.c @@ -15,7 +15,6 @@ #include <mach/syslib.h> #include <mach/am33xx-mux.h> #include <mach/am33xx-generic.h> -#include <mach/wdt.h> #include "beaglebone.h" @@ -118,13 +117,7 @@ static noinline int beaglebone_sram_init(void) else sdram_size = SZ_256M; - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); - __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); /* Setup the PLLs and the clocks for the peripherals */ if (is_beaglebone_black()) { diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile index 096120e567..85d92c8a7f 100644 --- a/arch/arm/boards/clep7212/Makefile +++ b/arch/arm/boards/clep7212/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += clep7212.o +obj-y += board.o lwl-y += lowlevel.o -bbenv-y += defaultenv-clep7212 +bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-clep7212 diff --git a/arch/arm/boards/clep7212/board.c b/arch/arm/boards/clep7212/board.c new file mode 100644 index 0000000000..b3983f2f49 --- /dev/null +++ b/arch/arm/boards/clep7212/board.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> + +#include <envfs.h> +#include <init.h> +#include <of.h> + +static __init int clep7212_init(void) +{ + if (of_machine_is_compatible("cirrus,clep7212")) + defaultenv_append_directory(defaultenv_clep7212); + + return 0; +} +device_initcall(clep7212_init); diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c deleted file mode 100644 index 3b497a6bd2..0000000000 --- a/arch/arm/boards/clep7212/clep7212.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2012 Alexander Shiyan <shc_work@mail.ru> - -#include <common.h> -#include <driver.h> -#include <envfs.h> -#include <init.h> -#include <partition.h> -#include <io.h> -#include <linux/sizes.h> -#include <asm/armlinux.h> -#include <asm/mmu.h> -#include <generated/mach-types.h> - -#include <mach/clps711x.h> -#include <mach/devices.h> - -static int clps711x_devices_init(void) -{ - u32 serial_h = 0, serial_l = readl(UNIQID); - void *cfi_io; - - /* Setup Chipselects */ - clps711x_setup_memcfg(0, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_16); - clps711x_setup_memcfg(1, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_8); - clps711x_setup_memcfg(2, MEMCFG_WAITSTATE_8_3 | MEMCFG_BUS_WIDTH_16 | - MEMCFG_CLKENB); - clps711x_setup_memcfg(3, MEMCFG_WAITSTATE_7_1 | MEMCFG_BUS_WIDTH_32); - - cfi_io = map_io_sections(CS0_BASE, (void *)0x90000000, SZ_32M); - add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_io, SZ_32M, - IORESOURCE_MEM); - - devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, - "self0"); - devfs_add_partition("nor0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED, - "env0"); - - armlinux_set_architecture(MACH_TYPE_CLEP7212); - armlinux_set_serial(((u64)serial_h << 32) | serial_l); - - defaultenv_append_directory(defaultenv_clep7212); - - return 0; -} -device_initcall(clps711x_devices_init); - -static int clps711x_console_init(void) -{ - barebox_set_model("Cirrus Logic CLEP7212"); - barebox_set_hostname("clep7212"); - - clps711x_add_uart(0); - - return 0; -} -console_initcall(clps711x_console_init); diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c index 41827dfa16..09f2762fac 100644 --- a/arch/arm/boards/clep7212/lowlevel.c +++ b/arch/arm/boards/clep7212/lowlevel.c @@ -1,22 +1,21 @@ // SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2012 Alexander Shiyan <shc_work@mail.ru> +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> #include <common.h> -#include <init.h> - -#include <asm/barebox-arm-head.h> - +#include <asm/barebox-arm.h> +#include <linux/sizes.h> #include <mach/clps711x.h> -#ifdef CONFIG_CLPS711X_RAISE_CPUFREQ -# define CLPS711X_CPU_PLL_MULT 50 -#else -# define CLPS711X_CPU_PLL_MULT 40 -#endif +extern char __dtb_ep7212_clep7212_start[]; -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +ENTRY_FUNCTION_WITHSTACK(start_ep7212_clep7212, + CS6_BASE + 48 * SZ_1K, r0, r1, r2) { + void *fdt; + arm_cpu_lowlevel_init(); - clps711x_barebox_entry(CLPS711X_CPU_PLL_MULT, NULL); + fdt = __dtb_ep7212_clep7212_start; + + clps711x_start(fdt + get_runtime_offset()); } diff --git a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c index 14100747e0..350576fa52 100644 --- a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c +++ b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c @@ -25,7 +25,6 @@ #include <mach/clock.h> #include <mach/mci.h> #include <mach/iomux.h> -#include <generated/mach-types.h> static struct mxs_mci_platform_data mci_pdata = { .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED, diff --git a/arch/arm/boards/kindle-mx50/board.c b/arch/arm/boards/kindle-mx50/board.c index 8fc5af8320..4cfd68a258 100644 --- a/arch/arm/boards/kindle-mx50/board.c +++ b/arch/arm/boards/kindle-mx50/board.c @@ -84,10 +84,9 @@ static char *mac; static void kindle_rev_init(void) { int ret; - size_t size; void *buf; const char userdata[] = "/dev/mmc2.boot0.userdata"; - ret = read_file_2(userdata, &size, &buf, 128); + ret = read_file_2(userdata, NULL, &buf, 128); if (ret && ret != -EFBIG) { pr_err("Could not read board info from %s\n", userdata); return; diff --git a/arch/arm/boards/myirtech-x335x/lowlevel.c b/arch/arm/boards/myirtech-x335x/lowlevel.c index e867a0be7d..c394253320 100644 --- a/arch/arm/boards/myirtech-x335x/lowlevel.c +++ b/arch/arm/boards/myirtech-x335x/lowlevel.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> */ +#include <common.h> #include <io.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> @@ -13,7 +14,6 @@ #include <mach/generic.h> #include <mach/sdrc.h> #include <mach/sys_info.h> -#include <mach/wdt.h> #define AM335X_ZCZ_1000 0x1c2f @@ -41,12 +41,13 @@ static const struct am33xx_cmd_control ddr3_cmd_ctrl = { /* CPU module contains 512MB (2*256MB) DDR3 SDRAM (2*128MB compatible), * so we configure EMIF for 512MB then detect real size of memory. */ -static const struct am33xx_emif_regs ddr3_regs = { +static struct am33xx_emif_regs ddr3_regs = { .emif_read_latency = 0x00100007, .emif_tim1 = 0x0aaad4db, .emif_tim2 = 0x266b7fda, .emif_tim3 = 0x501f867f, .zq_config = 0x50074be4, + /* MT41K256M8DA */ .sdram_config = 0x61c05332, .sdram_config2 = 0x00, .sdram_ref_ctrl = 0xc30, @@ -68,13 +69,7 @@ ENTRY_FUNCTION(start_am33xx_myirtech_sram, bootinfo, r1, r2) fdt = __dtb_z_am335x_myirtech_myd_start; - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); - __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); mpupll = MPUPLL_M_800; if (am33xx_get_cpu_rev() == AM335X_ES2_1) { @@ -87,6 +82,12 @@ ENTRY_FUNCTION(start_am33xx_myirtech_sram, bootinfo, r1, r2) am335x_sdram_init(0x18b, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data); + if (get_ram_size((void *)AM33XX_DRAM_ADDR_SPACE_START, SZ_512M) < SZ_512M) { + /* MT41K128M8DA */ + ddr3_regs.sdram_config = 0x61c04ab2; + am335x_sdram_init(0x18b, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data); + } + if (IS_ENABLED(CONFIG_DEBUG_LL)) { am33xx_uart_soft_reset(IOMEM(AM33XX_UART0_BASE)); am33xx_enable_uart0_pin_mux(); @@ -94,22 +95,16 @@ ENTRY_FUNCTION(start_am33xx_myirtech_sram, bootinfo, r1, r2) putc_ll('>'); } - barebox_arm_entry(AM33XX_DRAM_ADDR_SPACE_START, SZ_256M, fdt); + am335x_barebox_entry(fdt); } ENTRY_FUNCTION(start_am33xx_myirtech_sdram, r0, r1, r2) { void *fdt; - u32 sdram_size; fdt = __dtb_z_am335x_myirtech_myd_start; fdt += get_runtime_offset(); - /* Detect 256M/512M module variant */ - __raw_writel(SZ_512M, AM33XX_DRAM_ADDR_SPACE_START + SZ_256M); - __raw_writel(SZ_256M, AM33XX_DRAM_ADDR_SPACE_START + 0); - sdram_size = __raw_readl(AM33XX_DRAM_ADDR_SPACE_START + SZ_256M); - - barebox_arm_entry(AM33XX_DRAM_ADDR_SPACE_START, sdram_size, fdt); + am335x_barebox_entry(fdt); } diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c index c28107cb17..8d88bfe8c2 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/board.c +++ b/arch/arm/boards/nxp-imx8mq-evk/board.c @@ -40,7 +40,7 @@ static int nxp_imx8mq_evk_init(void) barebox_set_hostname("imx8mq-evk"); flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; - imx8m_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0.barebox", flags); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", flags); flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0; imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", flags); diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c index 39addea973..b1f752c4cb 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c +++ b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c @@ -81,6 +81,7 @@ void ddr_init(void) reg32_write(0x3d400200,0x15); reg32_write(0x3d40020c,0x0); reg32_write(0x3d400210,0x1f1f); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0x48080707); @@ -222,4 +223,4 @@ void ddr_init(void) /* enable DDR auto-refresh mode */ tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; reg32_write(DDRC_RFSHCTL3(0), tmp); -}
\ No newline at end of file +} diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c index bffb3ad880..8e506bc4ed 100644 --- a/arch/arm/boards/phytec-som-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c @@ -15,7 +15,6 @@ #include <mach/syslib.h> #include <mach/am33xx-mux.h> #include <mach/am33xx-generic.h> -#include <mach/wdt.h> #include <debug_ll.h> #include "ram-timings.h" @@ -136,15 +135,7 @@ static noinline void physom_board_init(void *fdt, int sdram, int module_family) struct am335x_sdram_timings *timing = NULL; u32 ramsize; - /* - * WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); - - writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400); diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr_init.c b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c index aa327d3fb0..c6812e3efa 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddr_init.c +++ b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c @@ -84,6 +84,7 @@ void ddr_init(void) reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0xf070707); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d402020,0x1); reg32_write(0x3d402024,0x518b00); reg32_write(0x3d402050,0x20d040); diff --git a/arch/arm/boards/protonic-imx6/board.c b/arch/arm/boards/protonic-imx6/board.c index cdbb8debe6..a0dec5b1e2 100644 --- a/arch/arm/boards/protonic-imx6/board.c +++ b/arch/arm/boards/protonic-imx6/board.c @@ -4,14 +4,18 @@ // SPDX-FileCopyrightText: 2020 Oleksij Rempel, Pengutronix #include <bbu.h> +#include <boot.h> +#include <bootm.h> #include <common.h> #include <deep-probe.h> #include <environment.h> #include <fcntl.h> +#include <globalvar.h> #include <gpio.h> #include <i2c/i2c.h> #include <mach/bbu.h> #include <mach/imx6.h> +#include <mach/ocotp-fusemap.h> #include <mfd/imx6q-iomuxc-gpr.h> #include <mfd/syscon.h> #include <net.h> @@ -21,7 +25,6 @@ #include <sys/stat.h> #include <unistd.h> #include <usb/usb.h> -#include <work.h> #define GPIO_HW_REV_ID {\ {IMX_GPIO_NR(2, 8), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "rev_id0"}, \ @@ -86,10 +89,8 @@ struct prt_imx6_priv { unsigned int hw_id; unsigned int hw_rev; const char *name; - unsigned int usb_delay; unsigned int no_usb_check; - struct work_queue wq; - struct work_struct work; + char *ocotp_serial; }; struct prti6q_rfid_contents { @@ -212,12 +213,11 @@ static int prt_imx6_set_mac(struct prt_imx6_priv *priv, return 0; } -static int prt_imx6_set_serial(struct prt_imx6_priv *priv, - struct prti6q_rfid_contents *rfid) +static int prt_imx6_set_serial(struct prt_imx6_priv *priv, char *serial) { - rfid->serial[9] = 0; /* Failsafe */ - dev_info(priv->dev, "Serial number: %s\n", rfid->serial); - barebox_set_serial_number(rfid->serial); + serial[9] = 0; /* Failsafe */ + dev_info(priv->dev, "Serial number: %s\n", serial); + barebox_set_serial_number(serial); return 0; } @@ -241,14 +241,58 @@ static int prt_imx6_read_i2c_mac_serial(struct prt_imx6_priv *priv) if (ret) return ret; - ret = prt_imx6_set_serial(priv, &rfid); + ret = prt_imx6_set_serial(priv, rfid.serial); if (ret) return ret; return 0; } -static int prt_imx6_usb_mount(struct prt_imx6_priv *priv, char **usbdisk) +#define PRT_IMX6_GP1_FMT_DEC BIT(31) + +static int prt_imx6_read_ocotp_serial(struct prt_imx6_priv *priv) +{ + int ret; + unsigned val; + + ret = imx_ocotp_read_field(OCOTP_GP1, &val); + if (ret) { + dev_err(priv->dev, "Failed to read ocotp serial (%i)\n", ret); + return ret; + } + + if (!(val & PRT_IMX6_GP1_FMT_DEC)) + return -EINVAL; + val &= PRT_IMX6_GP1_FMT_DEC - 1; + + priv->ocotp_serial = xasprintf("%u", val); + + return prt_imx6_set_serial(priv, priv->ocotp_serial); +} + +static int prt_imx6_set_ocotp_serial(struct param_d *param, void *driver_priv) +{ + struct prt_imx6_priv *priv = driver_priv; + int ret; + unsigned val; + + ret = kstrtouint(priv->ocotp_serial, 10, &val); + if (ret) + return ret; + + if (val & PRT_IMX6_GP1_FMT_DEC) + return -ERANGE; + val |= PRT_IMX6_GP1_FMT_DEC; + + ret = imx_ocotp_write_field(OCOTP_GP1, val); + if (ret) + return ret; + + barebox_set_serial_number(priv->ocotp_serial); + return 0; +} + +static int prt_imx6_usb_mount(struct prt_imx6_priv *priv) { struct device_d *dev = priv->dev; const char *path; @@ -267,8 +311,6 @@ static int prt_imx6_usb_mount(struct prt_imx6_priv *priv, char **usbdisk) ret = mount(path, NULL, "usb", NULL); if (ret) goto exit_usb_mount; - - *usbdisk = strdup("disk0.0"); return 0; } @@ -278,8 +320,6 @@ static int prt_imx6_usb_mount(struct prt_imx6_priv *priv, char **usbdisk) ret = mount(path, NULL, "usb", NULL); if (ret) goto exit_usb_mount; - - *usbdisk = strdup("disk0"); return 0; } @@ -290,25 +330,21 @@ exit_usb_mount: #define OTG_PORTSC1 (MX6_OTG_BASE_ADDR+0x184) -static void prt_imx6_check_usb_boot_do_work(struct work_struct *w) +static int prt_imx6_usb_boot(struct bootentry *entry, int verbose, int dryrun) { - struct prt_imx6_priv *priv = container_of(w, struct prt_imx6_priv, work); + struct prt_imx6_priv *priv = prt_priv; struct device_d *dev = priv->dev; - char *second_word, *bootsrc, *usbdisk; + char *second_word; char buf[sizeof("vicut1q recovery")] = {}; - unsigned int v; + struct bootm_data bootm_data = {}; ssize_t size; int fd, ret; - v = readl(OTG_PORTSC1); - if ((v & 0x0c00) == 0) /* LS == SE0 ==> nothing connected */ - return; - usb_rescan(); - ret = prt_imx6_usb_mount(priv, &usbdisk); + ret = prt_imx6_usb_mount(priv); if (ret) - return; + return ret; fd = open("/usb/boot_target", O_RDONLY); if (fd < 0) { @@ -347,37 +383,91 @@ static void prt_imx6_check_usb_boot_do_work(struct work_struct *w) goto exit_usb_boot; } + bootm_data_init_defaults(&bootm_data); + second_word++; if (strncmp(second_word, "usb", 3) == 0) { - bootsrc = "usb"; + dev_info(dev, "Booting from USB drive\n"); + bootm_data.os_file = "/usb/linuximage.fit"; } else if (strncmp(second_word, "recovery", 8) == 0) { - bootsrc = "recovery"; + dev_info(dev, "Booting internal recovery OS\n"); + bootm_data.os_file = "/dev/mmc2.5"; } else { dev_err(dev, "Unknown boot target!\n"); ret = -ENODEV; goto exit_usb_boot; } - dev_info(dev, "detected valid usb boot target file, overwriting boot to: %s\n", bootsrc); - ret = setenv("global.boot.default", bootsrc); + ret = globalvar_add_simple("linux.bootargs.root", + "root=/dev/ram rw rootwait ramdisk_size=196608"); if (ret) goto exit_usb_boot; - free(usbdisk); - return; + if (verbose) + bootm_data.verbose = verbose; + if (dryrun) + bootm_data.dryrun = dryrun; + + ret = bootm_boot(&bootm_data); + if (ret) + goto exit_usb_boot; + + return 0; exit_usb_boot: dev_err(dev, "Failed to run usb boot: %s\n", strerror(-ret)); - free(usbdisk); - return; + return ret; +} + +static void prt_imx6_bootentry_release(struct bootentry *entry) +{ + free(entry); +} + +static int prt_imx6_bootentry_create(struct bootentries *bootentries, const char *name) +{ + struct bootentry *entry; + + entry = xzalloc(sizeof(*entry)); + if (!entry) + return -ENOMEM; + + entry->me.type = MENU_ENTRY_NORMAL; + entry->release = prt_imx6_bootentry_release; + entry->boot = prt_imx6_usb_boot; + entry->title = xstrdup(name); + entry->description = xstrdup("Boot FIT image of a USB drive"); + bootentries_add_entry(bootentries, entry); + + return 0; +} + +static int prt_imx6_bootentry_provider(struct bootentries *bootentries, + const char *name) +{ + int found = 0; + unsigned int v; + + if (strncmp(name, "prt-usb", 7)) + return found; + + v = readl(OTG_PORTSC1); + if ((v & 0x0c00) == 0) /* No usb device detected */ + return found; + + if (!prt_imx6_bootentry_create(bootentries, name)) + found = 1; + + return found; } static int prt_imx6_env_init(struct prt_imx6_priv *priv) { const struct prt_machine_data *dcfg = priv->dcfg; struct device_d *dev = priv->dev; - char *delay, *bootsrc; + char *delay, *bootsrc, *boot_targets; + unsigned int autoboot_timeout; int ret; ret = setenv("global.linux.bootargs.base", "consoleblank=0 vt.color=0x00"); @@ -388,13 +478,14 @@ static int prt_imx6_env_init(struct prt_imx6_priv *priv) set_autoboot_state(AUTOBOOT_BOOT); } else { if (dcfg->flags & PRT_IMX6_USB_LONG_DELAY) - priv->usb_delay = 4; + autoboot_timeout = 4; else - priv->usb_delay = 1; + autoboot_timeout = 1; /* the usb_delay value is used for poller_call_async() */ - delay = basprintf("%d", priv->usb_delay); + delay = basprintf("%d", autoboot_timeout); ret = setenv("global.autoboot_timeout", delay); + free(delay); if (ret) goto exit_env_init; } @@ -404,7 +495,13 @@ static int prt_imx6_env_init(struct prt_imx6_priv *priv) else bootsrc = "mmc2"; - ret = setenv("global.boot.default", bootsrc); + if (!priv->no_usb_check) + boot_targets = xasprintf("prt-usb %s", bootsrc); + else + boot_targets = xstrdup(bootsrc); + + ret = setenv("global.boot.default", boot_targets); + free(boot_targets); if (ret) goto exit_env_init; @@ -462,6 +559,8 @@ exit_bbu: static int prt_imx6_devices_init(void) { struct prt_imx6_priv *priv = prt_priv; + struct device_d *ocotp_dev; + struct param_d *p; if (!priv) return 0; @@ -471,17 +570,26 @@ static int prt_imx6_devices_init(void) prt_imx6_bbu(priv); - prt_imx6_read_i2c_mac_serial(priv); - - prt_imx6_env_init(priv); + /* + * Read serial number from fuses. On success we'll assume the imx_ocotp + * driver takes care of providing the mac address if needed. On + * failure we'll fallback to reading and setting serial and mac from an + * attached RFID eeprom. + */ + if (prt_imx6_read_ocotp_serial(priv) != 0) + prt_imx6_read_i2c_mac_serial(priv); - if (!priv->no_usb_check) { - priv->wq.fn = prt_imx6_check_usb_boot_do_work; + bootentry_register_provider(prt_imx6_bootentry_provider); - wq_register(&priv->wq); + prt_imx6_env_init(priv); - wq_queue_delayed_work(&priv->wq, &priv->work, - priv->usb_delay * SECOND); + ocotp_dev = get_device_by_name("ocotp0"); + if (ocotp_dev) { + p = dev_add_param_string(ocotp_dev, "serial_number", + prt_imx6_set_ocotp_serial, NULL, + &priv->ocotp_serial, priv); + if (IS_ERR(p)) + return PTR_ERR(p); } return 0; @@ -680,24 +788,22 @@ static int prt_imx6_rfid_fixup(struct prt_imx6_priv *priv, } i2c_node = of_find_node_by_alias(root, alias); + kfree(alias); if (!i2c_node) { dev_err(priv->dev, "Unsupported i2c adapter\n"); - ret = -ENODEV; - goto free_alias; + return -ENODEV; } eeprom_node_name = basprintf("/eeprom@%x", dcfg->i2c_addr); if (!eeprom_node_name) { - ret = -ENOMEM; - goto free_alias; + return -ENOMEM; } node = of_create_node(i2c_node, eeprom_node_name); if (!node) { dev_err(priv->dev, "Failed to create node %s\n", eeprom_node_name); - ret = -ENOMEM; - goto free_eeprom; + return -ENOMEM; } ret = of_property_write_string(node, "compatible", "atmel,24c256"); @@ -721,8 +827,6 @@ static int prt_imx6_rfid_fixup(struct prt_imx6_priv *priv, return 0; free_eeprom: kfree(eeprom_node_name); -free_alias: - kfree(alias); exit_error: dev_err(priv->dev, "Failed to apply fixup: %pe\n", ERR_PTR(ret)); return ret; diff --git a/arch/arm/boards/radxa-rock3/.gitignore b/arch/arm/boards/radxa-rock3/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/radxa-rock3/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/radxa-rock3/Makefile b/arch/arm/boards/radxa-rock3/Makefile new file mode 100644 index 0000000000..b37b6c870b --- /dev/null +++ b/arch/arm/boards/radxa-rock3/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/radxa-rock3/board.c b/arch/arm/boards/radxa-rock3/board.c new file mode 100644 index 0000000000..aef5ec5df6 --- /dev/null +++ b/arch/arm/boards/radxa-rock3/board.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/bbu.h> + +struct rock3_model { + const char *name; + const char *shortname; +}; + +static int rock3_probe(struct device_d *dev) +{ + enum bootsource bootsource = bootsource_get(); + int instance = bootsource_get_instance(); + const struct rock3_model *model; + + model = device_get_match_data(dev); + + barebox_set_model(model->name); + barebox_set_hostname(model->shortname); + + if (bootsource == BOOTSOURCE_MMC && instance == 1) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, + "/dev/mmc1"); + + return 0; +} + +static const struct rock3_model rock3a = { + .name = "Radxa ROCK3 Model A", + .shortname = "rock3a", +}; + +static const struct of_device_id rock3_of_match[] = { + { + .compatible = "radxa,rock3a", + .data = &rock3a, + }, + { /* sentinel */ }, +}; + +static struct driver_d rock3_board_driver = { + .name = "board-rock3", + .probe = rock3_probe, + .of_compatible = rock3_of_match, +}; +coredevice_platform_driver(rock3_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(rock3_of_match); diff --git a/arch/arm/boards/radxa-rock3/lowlevel.c b/arch/arm/boards/radxa-rock3/lowlevel.c new file mode 100644 index 0000000000..00a68889cd --- /dev/null +++ b/arch/arm/boards/radxa-rock3/lowlevel.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <common.h> +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/hardware.h> +#include <mach/atf.h> +#include <debug_ll.h> +#include <mach/rockchip.h> + +extern char __dtb_rk3568_rock_3a_start[]; + +static noinline void rk3568_start(void *fdt) +{ + /* + * Image execution starts at 0x0, but this is used for ATF and + * OP-TEE later, so move away from here. + */ + if (current_el() == 3) + relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + /* + * Enable vccio4 1.8V and vccio6 1.8V + * Needed for GMAC to work. + */ + writel(RK_SETBITS(0x50), 0xfdc20140); + + if (current_el() == 3) { + rk3568_lowlevel_init(); + rk3568_atf_load_bl31(fdt); + /* not reached */ + } + + barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM, fdt); +} + +ENTRY_FUNCTION(start_rock3a, r0, r1, r2) +{ + rk3568_start(__dtb_rk3568_rock_3a_start); +} diff --git a/arch/arm/boards/rockchip-rk3568-evb/board.c b/arch/arm/boards/rockchip-rk3568-evb/board.c index 09385bea29..a466d385a2 100644 --- a/arch/arm/boards/rockchip-rk3568-evb/board.c +++ b/arch/arm/boards/rockchip-rk3568-evb/board.c @@ -28,8 +28,9 @@ static int rk3568_evb_probe(struct device_d *dev) else of_device_enable_path("/chosen/environment-emmc"); - rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/emmc"); - rk3568_bbu_mmc_register("sd", 0, "/dev/sd"); + rk3568_bbu_mmc_register("sd", 0, "/dev/mmc0"); + rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, + "/dev/mmc1"); return 0; } diff --git a/arch/arm/boards/vscom-baltos/board.c b/arch/arm/boards/vscom-baltos/board.c index 59782d2990..83c7dbc8b0 100644 --- a/arch/arm/boards/vscom-baltos/board.c +++ b/arch/arm/boards/vscom-baltos/board.c @@ -85,7 +85,6 @@ static uint8_t get_dip_switch(uint16_t id, uint32_t rev) static int baltos_read_eeprom(void) { struct bsp_vs_hwparam hw_param; - size_t size; char *buf, var_buf[32]; int rc; unsigned char mac_addr[6]; @@ -95,7 +94,7 @@ static int baltos_read_eeprom(void) return 0; rc = read_file_2("/dev/eeprom0", - &size, + NULL, (void *)&buf, sizeof(hw_param)); if (rc && rc != -EFBIG) diff --git a/arch/arm/boards/vscom-baltos/lowlevel.c b/arch/arm/boards/vscom-baltos/lowlevel.c index 7da2f92efb..2fa8a0fdc3 100644 --- a/arch/arm/boards/vscom-baltos/lowlevel.c +++ b/arch/arm/boards/vscom-baltos/lowlevel.c @@ -16,7 +16,6 @@ #include <mach/syslib.h> #include <mach/am33xx-mux.h> #include <mach/am33xx-generic.h> -#include <mach/wdt.h> static const struct am33xx_ddr_data ddr3_data = { .rd_slave_ratio0 = 0x38, @@ -86,13 +85,7 @@ static noinline void baltos_sram_init(void) fdt = __dtb_z_am335x_baltos_minimal_start; - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); - __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); /* Setup the PLLs and the clocks for the peripherals */ am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400); diff --git a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c index 7da8fd0331..9018bedf22 100644 --- a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c +++ b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c @@ -16,7 +16,6 @@ #include <mach/sdrc.h> #include <mach/sys_info.h> #include <mach/syslib.h> -#include <mach/wdt.h> #include <mach/omap3-mux.h> #include <mach/omap3-silicon.h> #include <mach/omap3-generic.h> @@ -200,7 +199,7 @@ static noinline void pfc200_board_init(void) /* Dont reconfigure SDRAM while running in SDRAM */ if (!in_sdram) - am35xx_emif4_init(); + am35xx_emif4_init(IOMEM(OMAP3_SDRC_BASE)); barebox_arm_entry(0x80000000, SZ_256M, NULL); } diff --git a/arch/arm/boards/zii-imx51-rdu1/board.c b/arch/arm/boards/zii-imx51-rdu1/board.c index 42c99ecc1e..0b5271b8de 100644 --- a/arch/arm/boards/zii-imx51-rdu1/board.c +++ b/arch/arm/boards/zii-imx51-rdu1/board.c @@ -27,8 +27,6 @@ #include <linux/sizes.h> #include <linux/nvmem-consumer.h> -#include <envfs.h> - static int zii_rdu1_init(void) { const char *hostname; diff --git a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c index 7a955193fd..902d0ee3cd 100644 --- a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c +++ b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c @@ -81,6 +81,7 @@ void ddr_init(void) reg32_write(0x3d400200,0x17); reg32_write(0x3d40020c,0x0); reg32_write(0x3d400210,0x1f1f); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0x7070707); @@ -222,4 +223,4 @@ void ddr_init(void) /* enable DDR auto-refresh mode */ tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; reg32_write(DDRC_RFSHCTL3(0), tmp); -}
\ No newline at end of file +} diff --git a/arch/arm/configs/at91sam9n12ek_defconfig b/arch/arm/configs/at91sam9n12ek_defconfig index b7c3a4b1f4..ce97ad62dc 100644 --- a/arch/arm/configs/at91sam9n12ek_defconfig +++ b/arch/arm/configs/at91sam9n12ek_defconfig @@ -4,12 +4,12 @@ CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_PBL_IMAGE=y +CONFIG_IMAGE_COMPRESSION_XZKERN=y CONFIG_MMU=y CONFIG_MALLOC_SIZE=0xa00000 CONFIG_EXPERIMENTAL=y CONFIG_MALLOC_TLSF=y CONFIG_PROMPT="9G20-EK:" -CONFIG_GLOB=y CONFIG_PROMPT_HUSH_PS2="y" CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y @@ -60,9 +60,6 @@ CONFIG_MTD=y # CONFIG_MTD_OOB_DEVICE is not set CONFIG_MTD_M25P80=y CONFIG_NAND=y -# CONFIG_NAND_ECC_SOFT is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -# CONFIG_NAND_ECC_HW_NONE is not set CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL_PMECC=y CONFIG_USB_GADGET=y diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig index d9eab565b9..684ae79e22 100644 --- a/arch/arm/configs/clps711x_defconfig +++ b/arch/arm/configs/clps711x_defconfig @@ -1,8 +1,8 @@ CONFIG_ARCH_CLPS711X=y +CONFIG_CLPS711X_RAISE_CPUFREQ=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y # CONFIG_MEMINFO is not set -CONFIG_PBL_IMAGE=y CONFIG_MMU=y CONFIG_EXPERIMENTAL=y CONFIG_BAUDRATE=57600 @@ -28,6 +28,8 @@ CONFIG_CMD_TIMEOUT=y CONFIG_CMD_CRC=y CONFIG_CMD_CRC_CMP=y CONFIG_CMD_FLASH=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y # CONFIG_SPI is not set CONFIG_MTD=y CONFIG_DRIVER_CFI=y @@ -36,6 +38,7 @@ CONFIG_DRIVER_CFI=y CONFIG_DISK=y CONFIG_DISK_WRITE=y CONFIG_DISK_INTF_PLATFORM_IDE=y +# CONFIG_PINCTRL is not set CONFIG_FS_CRAMFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/rockchip_v8_defconfig b/arch/arm/configs/rockchip_v8_defconfig index 79d51234cc..7fba31ddc3 100644 --- a/arch/arm/configs/rockchip_v8_defconfig +++ b/arch/arm/configs/rockchip_v8_defconfig @@ -2,6 +2,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_MACH_RK3568_EVB=y CONFIG_MACH_RK3568_BPI_R2PRO=y CONFIG_MACH_PINE64_QUARTZ64=y +CONFIG_MACH_RADXA_ROCK3=y CONFIG_BOARD_ARM_GENERIC_DT=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_PSCI_CLIENT=y @@ -89,6 +90,7 @@ CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_NET_DESIGNWARE_EQOS=y CONFIG_DRIVER_NET_DESIGNWARE_ROCKCHIP=y +CONFIG_REALTEK_PHY=y CONFIG_SMSC_PHY=y CONFIG_NET_USB=y CONFIG_NET_USB_ASIX=y diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c index a08fc253ef..aea50e80d1 100644 --- a/arch/arm/cpu/cpuinfo.c +++ b/arch/arm/cpu/cpuinfo.c @@ -27,6 +27,7 @@ #define ARM_CPU_PART_CORTEX_A15 0xC0F0 #define ARM_CPU_PART_CORTEX_A53 0xD030 #define ARM_CPU_PART_CORTEX_A57 0xD070 +#define ARM_CPU_PART_CORTEX_A72 0xD080 static void decode_cache(unsigned long size) { @@ -191,7 +192,7 @@ static int do_cpuinfo(int argc, char *argv[]) if (cpu_arch >= CPU_ARCH_ARMv7) { unsigned int major, minor; - char *part; + const char *part = NULL; major = (mainid >> 20) & 0xf; minor = mainid & 0xf; switch (mainid & 0xfff0) { @@ -216,12 +217,23 @@ static int do_cpuinfo(int argc, char *argv[]) case ARM_CPU_PART_CORTEX_A57: part = "Cortex-A57"; break; + case ARM_CPU_PART_CORTEX_A72: + part = "Cortex-A72"; + break; default: - part = "unknown"; + printf("core: unknown (0x%08lx) r%up%u\n", + mainid, major, minor); + break; } - printf("core: %s r%up%u\n", part, major, minor); + + if (part) + printf("core: %s r%up%u\n", part, major, minor); } +#ifdef CONFIG_CPU_64v8 + printf("exception level: %u\n", current_el()); +#endif + if (cache & (1 << 24)) { /* separate I/D cache */ printf("I-cache: "); diff --git a/arch/arm/cpu/mmu-common.c b/arch/arm/cpu/mmu-common.c index 2ef1fa231f..488a189f1c 100644 --- a/arch/arm/cpu/mmu-common.c +++ b/arch/arm/cpu/mmu-common.c @@ -9,6 +9,7 @@ #include <dma.h> #include <mmu.h> #include <asm/system.h> +#include <asm/barebox-arm.h> #include <memory.h> #include "mmu.h" @@ -58,14 +59,24 @@ void dma_free_coherent(void *mem, dma_addr_t dma_handle, size_t size) static int mmu_init(void) { - if (list_empty(&memory_banks)) + if (list_empty(&memory_banks)) { + resource_size_t start; + int ret; + /* * If you see this it means you have no memory registered. * This can be done either with arm_add_mem_device() in an * initcall prior to mmu_initcall or via devicetree in the * memory node. */ - panic("MMU: No memory bank found! Cannot continue\n"); + pr_emerg("No memory bank registered. Limping along with initial memory\n"); + + start = arm_mem_membase_get(); + ret = barebox_add_memory_bank("initmem", start, + arm_mem_endmem_get() - start); + if (ret) + panic(""); + } __mmu_init(get_cr() & CR_M); diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c index c61db66865..14cc310312 100644 --- a/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c @@ -28,6 +28,7 @@ unsigned long arm_stack_top; static unsigned long arm_barebox_size; static unsigned long arm_endmem; +static unsigned long arm_membase; static void *barebox_boarddata; static unsigned long barebox_boarddata_size; @@ -114,6 +115,12 @@ unsigned long arm_mem_endmem_get(void) } EXPORT_SYMBOL_GPL(arm_mem_endmem_get); +unsigned long arm_mem_membase_get(void) +{ + return arm_membase; +} +EXPORT_SYMBOL_GPL(arm_mem_membase_get); + static int barebox_memory_areas_init(void) { if(barebox_boarddata) @@ -148,6 +155,7 @@ __noreturn __no_sanitize_address void barebox_non_pbl_start(unsigned long membas pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize); + arm_membase = membase; arm_endmem = endmem; arm_stack_top = arm_mem_stack_top(membase, endmem); arm_barebox_size = barebox_size; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2c21410498..0c7e43e226 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -8,6 +8,7 @@ lwl-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o lwl-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o lwl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o lwl-$(CONFIG_MACH_CANON_A1100) += canon-a1100.dtb.o +lwl-$(CONFIG_MACH_CLEP7212) += ep7212-clep7212.dtb.o lwl-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o lwl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o lwl-$(CONFIG_MACH_DUCKBILL) += imx28-duckbill.dtb.o @@ -104,6 +105,7 @@ lwl-$(CONFIG_MACH_PROTONIC_STM32MP1) += \ stm32mp151-prtt1c.dtb.o \ stm32mp151-prtt1s.dtb.o lwl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o +lwl-$(CONFIG_MACH_RADXA_ROCK3) += rk3568-rock-3a.dtb.o lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o lwl-$(CONFIG_MACH_RK3568_EVB) += rk3568-evb1-v10.dtb.o diff --git a/arch/arm/dts/am335x-myirtech-myd.dts b/arch/arm/dts/am335x-myirtech-myd.dts index 6ec65e533d..1ea0f2a440 100644 --- a/arch/arm/dts/am335x-myirtech-myd.dts +++ b/arch/arm/dts/am335x-myirtech-myd.dts @@ -6,6 +6,13 @@ #include <arm/am335x-myirtech-myd.dts> / { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + }; + chosen { environment { compatible = "barebox,environment"; diff --git a/arch/arm/dts/ep7212-clep7212.dts b/arch/arm/dts/ep7212-clep7212.dts new file mode 100644 index 0000000000..84c5e79548 --- /dev/null +++ b/arch/arm/dts/ep7212-clep7212.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Author: Alexander Shiyan <shc_work@mail.ru> */ + +#include <arm/ep7211.dtsi> + +/ { + model = "Cirrus Logic EP7212"; + compatible = "cirrus,clep7212", "cirrus,ep7212", "cirrus,ep7209"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x02000000>; + }; + + chosen { + stdout-path = &uart1; + + environment { + compatible = "barebox,environment"; + device-path = &flash, "partname:env"; + }; + }; +}; + +&bus { + /* Setup Memory Timings */ + /* CS0 = WAITSTATE_6_1 | BUS_WIDTH_16 */ + /* CS1 = WAITSTATE_6_1 | BUS_WIDTH_8 */ + /* CS2 = WAITSTATE_8_3 | BUS_WIDTH_16 | CLKENB */ + /* CS3 = WAITSTATE_7_1 | BUS_WIDTH_32 */ + barebox,ep7209-memcfg1 = <0x25802b28>; + + flash: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000 0x80000>; + }; + + partition@80000 { + label = "env"; + reg = <0x80000 0x40000>; + }; + + partition@c0000 { + label = "kernel"; + reg = <0xc0000 0x340000>; + }; + + partition@400000 { + label = "root"; + reg = <0x400000 0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/dts/imx6q-dmo-edmqmx6.dts index 2b9097c482..fcf8ad8993 100644 --- a/arch/arm/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/dts/imx6q-dmo-edmqmx6.dts @@ -37,29 +37,18 @@ }; }; -&ecspi5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi_5_1>; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio1 12 0>; - status = "okay"; - - flash: m25p80@0 { - compatible = "m25p80"; - spi-max-frequency = <40000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; +&flash { + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; - }; + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; }; }; @@ -71,17 +60,6 @@ >; }; }; - - ecspi5 { - pinctrl_ecspi_5_1: ecspi5rp-1 { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 - >; - }; - }; }; &i2c2 { diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts index 304f150307..6c06ad7e47 100644 --- a/arch/arm/dts/imx8mm-evk.dts +++ b/arch/arm/dts/imx8mm-evk.dts @@ -24,8 +24,8 @@ }; }; -&fec1 { - phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +®_usdhc2_vmmc { + off-on-delay-us = <20000>; }; &usdhc2 { diff --git a/arch/arm/dts/imx8mq-ddrc.dtsi b/arch/arm/dts/imx8mq-ddrc.dtsi index 1df39151a1..6961477eef 100644 --- a/arch/arm/dts/imx8mq-ddrc.dtsi +++ b/arch/arm/dts/imx8mq-ddrc.dtsi @@ -8,3 +8,7 @@ /delete-node/ memory@40000000; }; +&ddrc { + status = "okay"; +}; + diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts index 5a65324b3c..deb31abe54 100644 --- a/arch/arm/dts/imx8mq-mnt-reform2.dts +++ b/arch/arm/dts/imx8mq-mnt-reform2.dts @@ -6,17 +6,12 @@ /dts-v1/; -#include <arm64/freescale/imx8mq.dtsi> +#include <arm64/freescale/imx8mq-mnt-reform2.dts> #include "imx8mq.dtsi" #include "imx8mq-ddrc.dtsi" / { - model = "MNT Reform2"; - compatible = "mntre,reform2", "fsl,imx8mq"; - chosen { - stdout-path = &uart1; - environment-emmc { compatible = "barebox,environment"; device-path = &usdhc1, "partname:barebox-environment"; @@ -29,86 +24,13 @@ status = "disabled"; }; }; - - pcie1_refclk: pcie1-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - interrupts = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - }; }; &ocotp { barebox,provide-mac-address = <&fec1 0x640>; }; -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1>; - reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - &usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-mmc-hs400; - non-removable; - no-sd; - no-sdio; - status = "okay"; - #address-cells = <1>; #size-cells = <1>; @@ -124,14 +46,6 @@ }; &usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - status = "okay"; - #address-cells = <1>; #size-cells = <1>; @@ -145,79 +59,3 @@ reg = <0xe0000 0x20000>; }; }; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1 - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1 - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x1 - >; - }; - - pinctrl_pcie1: pcie1grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x03 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc - >; - }; - - pinctrl_wdog: wdog1grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts index df5633978d..d2c1fc89a8 100644 --- a/arch/arm/dts/rk3568-evb1-v10.dts +++ b/arch/arm/dts/rk3568-evb1-v10.dts @@ -5,22 +5,11 @@ */ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include "rk3568.dtsi" -/ { - model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; - compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; - - aliases { - emmc = &sdhci; - sd = &sdmmc0; - }; +#include <arm64/rockchip/rk3568-evb1-v10.dts> +/ { chosen: chosen { - stdout-path = "serial2:1500000n8"; - environment-sd { compatible = "barebox,environment"; device-path = &environment_sd; @@ -38,437 +27,10 @@ device_type = "memory"; reg = <0x0 0x00a00000 0x0 0x7f600000>; }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc3v3_lcd0_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_lcd1_n: vcc3v3-lcd1-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd1_n"; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - regulator-name = "vcc5v0_otg"; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - }; -}; - -&gmac0 { - phy-mode = "rgmii"; - clock_in_out = "output"; - - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x3c>; - rx_delay = <0x2f>; - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&gmac1 { - phy-mode = "rgmii"; - clock_in_out = "output"; - - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - - tx_delay = <0x4f>; - rx_delay = <0x26>; - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default", "pmic-sleep", - "pmic-power-off", "pmic-reset"; - pinctrl-0 = <&pmic_int>; - pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; - pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; - pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; - - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - //fb-inner-reg-idxs = <2>; - /* 1: rst regs (default in codes), 0: rst the pmic */ - pmic-reset-func = <0>; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - - pwrkey { - status = "okay"; - }; - - pinctrl_rk8xx: pinctrl_rk8xx { - gpio-controller; - #gpio-cells = <2>; - - rk817_slppin_null: rk817_slppin_null { - pins = "gpio_slp"; - function = "pin_fun0"; - }; - - rk817_slppin_slp: rk817_slppin_slp { - pins = "gpio_slp"; - function = "pin_fun1"; - }; - - rk817_slppin_pwrdn: rk817_slppin_pwrdn { - pins = "gpio_slp"; - function = "pin_fun2"; - }; - - rk817_slppin_rst: rk817_slppin_rst { - pins = "gpio_slp"; - function = "pin_fun3"; - }; - }; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_logic"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_npu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_image"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda_0v9"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_acodec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_1v8"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_image"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_3v3"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&mdio0 { - rgmii_phy0: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reg = <0x0>; - }; -}; - -&mdio1 { - rgmii_phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reg = <0x0>; - }; -}; - -&pinctrl { - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - soc_slppin_gpio: soc_slppin_gpio { - rockchip,pins = - <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; - }; - - soc_slppin_slp: soc_slppin_slp { - rockchip,pins = - <0 RK_PA2 1 &pcfg_pull_none>; - }; - - soc_slppin_rst: soc_slppin_rst { - rockchip,pins = - <0 RK_PA2 2 &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; }; &sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; no-sd; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; partitions { compatible = "fixed-partitions"; @@ -483,18 +45,6 @@ }; &sdmmc0 { - max-frequency = <150000000>; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - status = "okay"; - partitions { compatible = "fixed-partitions"; #address-cells = <2>; @@ -506,68 +56,3 @@ }; }; }; - -&uart2 { - status = "okay"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy0_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&combphy0_us { - status = "okay"; -}; - -&combphy1_usq { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts new file mode 100644 index 0000000000..44d4fc9686 --- /dev/null +++ b/arch/arm/dts/rk3568-rock-3a.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <arm64/rockchip/rk3568-rock-3a.dts> + +/ { + chosen: chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &environment_sd; + status = "disabled"; + }; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &environment_emmc; + status = "disabled"; + }; + }; + + memory@a00000 { + device_type = "memory"; + reg = <0x0 0x00a00000 0x0 0x7f600000>; + }; +}; + +&sdhci { + no-sd; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + environment_emmc: partition@408000 { + label = "barebox-environment"; + reg = <0x0 0x408000 0x0 0x8000>; + }; + }; +}; + +&sdmmc0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + environment_sd: partition@408000 { + label = "barebox-environment"; + reg = <0x0 0x408000 0x0 0x8000>; + }; + }; +}; diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h index 15b3b6c444..8240cce9bf 100644 --- a/arch/arm/include/asm/barebox-arm.h +++ b/arch/arm/include/asm/barebox-arm.h @@ -84,6 +84,7 @@ static inline void boarddata_create(void *adr, u32 machine) u32 barebox_arm_machine(void); unsigned long arm_mem_ramoops_get(void); +unsigned long arm_mem_membase_get(void); unsigned long arm_mem_endmem_get(void); struct barebox_arm_boarddata *barebox_arm_get_boarddata(void); diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index 52cf8468c0..6cf6bc37a2 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -16,7 +16,6 @@ menu "CLPS711X specific settings" config CLPS711X_RAISE_CPUFREQ bool "Raise CPU frequency to 90 MHz" - depends on MACH_CLEP7212 help Raise CPU frequency to 90 MHz. This operation can be performed only for devices which allow to operate at 90 MHz. @@ -24,12 +23,4 @@ config CLPS711X_RAISE_CPUFREQ endmenu -config ARCH_TEXT_BASE - hex - default 0xc0740000 if MACH_CLEP7212 - -config BAREBOX_MAX_IMAGE_SIZE - hex - default 0x00080000 if MACH_CLEP7212 - endif diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile index 4d5950d9b5..871c5f7e9c 100644 --- a/arch/arm/mach-clps711x/Makefile +++ b/arch/arm/mach-clps711x/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += clock.o devices.o reset.o +obj-y += clock.o common.o lwl-y += lowlevel.o diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c index 2c5137c582..8674b8c801 100644 --- a/arch/arm/mach-clps711x/clock.c +++ b/arch/arm/mach-clps711x/clock.c @@ -1,11 +1,5 @@ -/* - * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> #include <common.h> #include <init.h> @@ -21,13 +15,15 @@ #define CLPS711X_EXT_FREQ 13000000 static struct clk *clks[CLPS711X_CLK_MAX]; +static struct clk_onecell_data clk_data; -static struct clk_div_table tdiv_tbl[] = { +static const struct clk_div_table tdiv_tbl[] = { { .val = 0, .div = 256, }, { .val = 1, .div = 1, }, + { } }; -static __init int clps711x_clk_init(void) +static int clps711x_clk_probe(struct device_d *dev) { unsigned int f_cpu, f_bus, f_uart, f_timer_ref, pll; u32 tmp; @@ -50,7 +46,7 @@ static __init int clps711x_clk_init(void) f_bus = 36864000 / 2; } - f_uart = f_bus / 10; + f_uart = DIV_ROUND_CLOSEST(f_bus, 10); if (tmp & SYSFLG2_CKMODE) { tmp = readw(SYSCON2); @@ -72,23 +68,25 @@ static __init int clps711x_clk_init(void) clks[CLPS711X_CLK_UART] = clk_fixed("uart", f_uart); clks[CLPS711X_CLK_TIMERREF] = clk_fixed("timer_ref", f_timer_ref); clks[CLPS711X_CLK_TIMER1] = clk_divider_table("timer1", "timer_ref", 0, - IOMEM(SYSCON1), 5, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl)); + IOMEM(SYSCON1), 5, 1, tdiv_tbl, 0); clks[CLPS711X_CLK_TIMER2] = clk_divider_table("timer2", "timer_ref", 0, - IOMEM(SYSCON1), 7, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl)); + IOMEM(SYSCON1), 7, 1, tdiv_tbl, 0); - clkdev_add_physbase(clks[CLPS711X_CLK_UART], UARTDR1, NULL); - clkdev_add_physbase(clks[CLPS711X_CLK_UART], UARTDR2, NULL); - clkdev_add_physbase(clks[CLPS711X_CLK_TIMER2], TC2D, NULL); + clk_data.clks = clks; + clk_data.clk_num = CLPS711X_CLK_MAX; + of_clk_add_provider(dev->device_node, of_clk_src_onecell_get, &clk_data); return 0; } -postcore_initcall(clps711x_clk_init); -static __init int clps711x_core_init(void) -{ - add_generic_device("clps711x-cs", DEVICE_ID_SINGLE, NULL, - TC2D, SZ_2, IORESOURCE_MEM, NULL); +static const struct of_device_id __maybe_unused clps711x_clk_dt_ids[] = { + { .compatible = "cirrus,ep7209-clk", }, + { } +}; - return 0; -} -coredevice_initcall(clps711x_core_init); +static struct driver_d clps711x_clk_driver = { + .probe = clps711x_clk_probe, + .name = "clps711x-clk", + .of_compatible = DRV_OF_COMPAT(clps711x_clk_dt_ids), +}; +postcore_platform_driver(clps711x_clk_driver); diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c new file mode 100644 index 0000000000..c0b817872d --- /dev/null +++ b/arch/arm/mach-clps711x/common.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> + +#include <common.h> +#include <driver.h> +#include <restart.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <mach/clps711x.h> + +#define CLPS711X_MAP_ADDR 0x90000000 + +static u32 remap_size = 0; + +static void __noreturn clps711x_restart(struct restart_handler *rst) +{ + shutdown_barebox(); + + asm("mov pc, #0"); + + hang(); +} + +static __init int is_clps711x_compatible(void) +{ + return of_machine_is_compatible("cirrus,ep7209"); +} + +static __init int clps711x_init(void) +{ + char *serial; + + if (!is_clps711x_compatible()) + return 0; + + restart_handler_register_fn("vector", clps711x_restart); + + serial = basprintf("%08x%08x", 0, readl(UNIQID)); + + barebox_set_serial_number(serial); + + free(serial); + + return 0; +} +postcore_initcall(clps711x_init); + +static int __init clps711x_bus_map(void) +{ + if (is_clps711x_compatible() && remap_size) + map_io_sections(0, (void *)CLPS711X_MAP_ADDR, remap_size); + + return 0; +} +postmmu_initcall(clps711x_bus_map); + +/* Scan for devices that start at zero address and maps them + * to a different unused address. + * To start the kernel, a fixup is used that rewrites the address + * of the patched device to its original state. + */ + +static void clps711x_bus_patch(struct device_node *node, + u32 compare, u32 change) +{ + const __be32 *ranges; + int rsize; + + ranges = of_get_property(node, "ranges", &rsize); + + if (ranges) { + int banks = rsize / (sizeof(u32) * 4); + __be32 *fixed, *fixedptr; + + fixed = xmalloc(rsize); + fixedptr = fixed; + + while (banks--) { + u32 bank, cell, addr, size; + + bank = be32_to_cpu(*ranges++); + cell = be32_to_cpu(*ranges++); + addr = be32_to_cpu(*ranges++); + size = be32_to_cpu(*ranges++); + + if (addr == compare) { + addr = change; + remap_size = size; + } + + *fixedptr++ = cpu_to_be32(bank); + *fixedptr++ = cpu_to_be32(cell); + *fixedptr++ = cpu_to_be32(addr); + *fixedptr++ = cpu_to_be32(size); + } + + of_set_property(node, "ranges", fixed, rsize, 0); + + free(fixed); + } +} + +static int clps711x_bus_fixup(struct device_node *root, void *context) +{ + struct device_node *node = context; + + if (remap_size) + clps711x_bus_patch(node, CLPS711X_MAP_ADDR, 0); + + return 0; +} + +static int clps711x_bus_probe(struct device_d *dev) +{ + u32 mcfg; + + /* Setup bus timings */ + if (!of_property_read_u32(dev->device_node, + "barebox,ep7209-memcfg1", &mcfg)) + writel(mcfg, MEMCFG1); + if (!of_property_read_u32(dev->device_node, + "barebox,ep7209-memcfg2", &mcfg)) + writel(mcfg, MEMCFG2); + + clps711x_bus_patch(dev->device_node, 0, CLPS711X_MAP_ADDR); + + of_platform_populate(dev->device_node, NULL, dev); + + of_register_fixup(clps711x_bus_fixup, dev->device_node); + + return 0; +} + +static const struct of_device_id __maybe_unused clps711x_bus_dt_ids[] = { + { .compatible = "cirrus,ep7209-bus", }, + { } +}; + +static struct driver_d clps711x_bus_driver = { + .name = "clps711x-bus", + .probe = clps711x_bus_probe, + .of_compatible = DRV_OF_COMPAT(clps711x_bus_dt_ids), +}; + +static int __init clps711x_bus_init(void) +{ + return platform_driver_register(&clps711x_bus_driver); +} +core_initcall(clps711x_bus_init); diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index 957b2b8477..9aef7f3fd3 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -1,13 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Hardware definitions for Cirrus Logic CLPS711X - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * Copyright (C) 2012-2022 Alexander Shiyan <shc_work@mail.ru> */ #ifndef __MACH_CLPS711X_H @@ -159,6 +153,10 @@ #define SYSCON2_CLKENSL (1 << 13) #define SYSCON2_BUZFREQ (1 << 14) +#define SYSCON_UARTEN (1 << 8) +#define SYSFLG_UBUSY (1 << 11) +#define SYSFLG_UTXFF (1 << 23) + #define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8) #define SYNCIO_SMCKEN (1 << 13) #define SYNCIO_TXFRMEN (1 << 14) @@ -247,6 +245,16 @@ #define MEMCFG_WAITSTATE_2_0 (14 << 2) #define MEMCFG_WAITSTATE_1_0 (15 << 2) -void clps711x_barebox_entry(u32, void *); +#define UBRLCR_BREAK (1 << 12) +#define UBRLCR_PRTEN (1 << 13) +#define UBRLCR_EVENPRT (1 << 14) +#define UBRLCR_XSTOP (1 << 15) +#define UBRLCR_FIFOEN (1 << 16) +#define UBRLCR_WRDLEN5 (0 << 17) +#define UBRLCR_WRDLEN6 (1 << 17) +#define UBRLCR_WRDLEN7 (2 << 17) +#define UBRLCR_WRDLEN8 (3 << 17) + +void clps711x_start(void *); #endif diff --git a/arch/arm/mach-clps711x/include/mach/debug_ll.h b/arch/arm/mach-clps711x/include/mach/debug_ll.h new file mode 100644 index 0000000000..342bb7628a --- /dev/null +++ b/arch/arm/mach-clps711x/include/mach/debug_ll.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> + +#ifndef __MACH_DEBUG_LL_H__ +#define __MACH_DEBUG_LL_H__ + +#include <asm/io.h> +#include <mach/clps711x.h> + +static inline void PUTC_LL(char c) +{ + do { + } while (readl(SYSFLG1) & SYSFLG_UTXFF); + + writew(c, UARTDR1); + + do { + } while (readl(SYSFLG1) & SYSFLG_UBUSY); +} + +#endif diff --git a/arch/arm/mach-clps711x/include/mach/devices.h b/arch/arm/mach-clps711x/include/mach/devices.h deleted file mode 100644 index 77c43be25c..0000000000 --- a/arch/arm/mach-clps711x/include/mach/devices.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_DEVICES_H -#define __MACH_DEVICES_H - -void clps711x_setup_memcfg(int bank, u32 val); -void clps711x_add_uart(unsigned int id); - -#endif diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c index 35b8b35e87..608f0778d7 100644 --- a/arch/arm/mach-clps711x/lowlevel.c +++ b/arch/arm/mach-clps711x/lowlevel.c @@ -1,25 +1,31 @@ -/* - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> +#include <asm/io.h> +#include <asm/barebox-arm.h> #include <common.h> -#include <init.h> +#include <debug_ll.h> #include <linux/sizes.h> +#include <mach/clps711x.h> -#include <asm/io.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> +#define DEBUG_LL_BAUDRATE (57600) -#include <mach/clps711x.h> +static inline void setup_uart(const u32 bus_speed) +{ + u32 baud_base = DIV_ROUND_CLOSEST(bus_speed, 10); + u32 baud_divisor = + DIV_ROUND_CLOSEST(baud_base, DEBUG_LL_BAUDRATE * 16) - 1; + + writel(baud_divisor | UBRLCR_FIFOEN | UBRLCR_WRDLEN8, UBRLCR1); + writel(0, STFCLR); + writel(SYSCON_UARTEN, SYSCON1); -void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data) + putc_ll('>'); +} + +void clps711x_start(void *fdt) { - u32 cpu, bus; + u32 bus, pll; /* Check if we running from external 13 MHz clock */ if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) { @@ -27,24 +33,17 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data) writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3); asm("nop"); - /* Check valid multiplier, default to 74 MHz */ - if ((pllmult < 20) || (pllmult > 50)) - pllmult = 40; + if (IS_ENABLED(CONFIG_CLPS711X_RAISE_CPUFREQ)) { + /* Setup PLL to 92160000 Hz */ + writel(50 << 24, PLLW); + asm("nop"); + } - /* Setup PLL */ - writel(pllmult << 24, PLLW); - asm("nop"); - - /* Check for old CPUs without PLL */ - if ((readl(PLLR) >> 24) != pllmult) - cpu = 73728000; - else - cpu = pllmult * 3686400; - - if (cpu >= 36864000) - bus = cpu / 2; + pll = readl(PLLR) >> 24; + if (pll) + bus = (pll * 3686400) / 4; else - bus = 36864000 / 2; + bus = 73728000 / 4; } else { bus = 13000000; /* Setup bus wait state scaling factor to 1 */ @@ -52,6 +51,13 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data) asm("nop"); } + + /* Disable UART, IrDa, LCD */ + writel(0, SYSCON1); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(bus); + /* CLKEN select, SDRAM width=32 */ writel(SYSCON2_CLKENSL, SYSCON2); @@ -62,12 +68,10 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data) /* Setup Refresh Rate (64ms 8K Blocks) */ writel((64 * bus) / (8192 * 1000), SDRFPR); - /* Disable UART, IrDa, LCD */ - writel(0, SYSCON1); /* Disable PWM */ writew(0, PMPCON); /* Disable LED flasher */ writew(0, LEDFLSH); - barebox_arm_entry(SDRAM0_BASE, SZ_8M, data); + barebox_arm_entry(SDRAM0_BASE, SZ_8M, fdt); } diff --git a/arch/arm/mach-clps711x/reset.c b/arch/arm/mach-clps711x/reset.c deleted file mode 100644 index 90ddb8f5d2..0000000000 --- a/arch/arm/mach-clps711x/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <common.h> -#include <init.h> -#include <restart.h> - -static void __noreturn clps711x_restart_soc(struct restart_handler *rst) -{ - shutdown_barebox(); - - asm("mov pc, #0"); - - hang(); -} - -static int restart_register_feature(void) -{ - restart_handler_register_fn("vector", clps711x_restart_soc); - - return 0; -} -coredevice_initcall(restart_register_feature); diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index 63afdf1ef4..16a377341c 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -285,6 +285,8 @@ void imx53_get_boot_source(enum bootsource *src, int *instance) default: if (imx53_bootsource_nand(cfg1)) *src = BOOTSOURCE_NAND; + else + *src = BOOTSOURCE_UNKNOWN; break; } @@ -464,6 +466,8 @@ void imx6_get_boot_source(enum bootsource *src, int *instance) default: if (imx53_bootsource_nand(bootmode)) *src = BOOTSOURCE_NAND; + else + *src = BOOTSOURCE_UNKNOWN; break; } } @@ -522,10 +526,12 @@ static void __imx7_get_boot_source(enum bootsource *src, int *instance, case 5: *src = BOOTSOURCE_NOR; break; - case 15: + case 14: /* observed on i.MX8MP for USB "serial" booting */ + case 15: /* observed on i.MX8MM for USB "serial" booting */ *src = BOOTSOURCE_SERIAL; break; default: + *src = BOOTSOURCE_UNKNOWN; break; } } @@ -629,6 +635,8 @@ void vf610_get_boot_source(enum bootsource *src, int *instance) default: if (imx53_bootsource_nand(sbmr1)) *src = BOOTSOURCE_NAND; + else + *src = BOOTSOURCE_UNKNOWN; break; } } diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index 559692c765..ea36215419 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -10,7 +10,6 @@ #include <mach/imx7-regs.h> #include <mach/imx8mq-regs.h> #include <mach/imx8m-ccm-regs.h> -#include <common.h> #include <io.h> #include <asm/syscounter.h> #include <asm/system.h> diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index b070ebc62a..a55ee06b83 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -317,6 +317,7 @@ static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) #define DDRC_ADDRMAP0_CS_BIT0 GENMASK(4, 0) #define DDRC_MSTR 0x0000 +#define DDRC_MSTR_DDR4 BIT(4) #define DDRC_MSTR_LPDDR4 BIT(5) #define DDRC_MSTR_DATA_BUS_WIDTH GENMASK(13, 12) #define DDRC_MSTR_ACTIVE_RANKS GENMASK(27, 24) @@ -370,9 +371,8 @@ static resource_size_t imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[DDRC_ADDRMAP_LENGTH], u8 col_max, const u8 col_b[], unsigned int col_b_num, u8 row_max, const u8 row_b[], unsigned int row_b_num, - bool reduced_adress_space, bool is_imx8) + bool reduced_adress_space, unsigned int mstr) { - const u32 mstr = readl(ddrc + DDRC_MSTR); unsigned int banks, ranks, columns, rows, active_ranks, width; resource_size_t size; @@ -393,11 +393,13 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[DDRC_ADDRMAP_LENGTH], BUG(); } - /* Bus width in bytes, 0 means half byte or 4-bit mode */ - if (is_imx8 && !(mstr & DDRC_MSTR_LPDDR4)) - width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1; - else - width = 4; + /* + * mstr is ignored for some SoCs/RAM types and may yield wrong + * results when used for calculation. Callers of this function + * are expected to fix it up as necessary. + * Bus width in bytes, 0 means half byte or 4-bit mode + */ + width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1; switch (FIELD_GET(DDRC_MSTR_DATA_BUS_WIDTH, mstr)) { case 0b00: /* Full DQ bus */ @@ -423,7 +425,12 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[DDRC_ADDRMAP_LENGTH], if (FIELD_GET(DDRC_ADDRMAP1_BANK_B2, addrmap[1]) != 0b11111) banks++; - if (addrmap[8]) { + if (mstr & DDRC_MSTR_DDR4) { + /* FIXME: DDR register spreasheet claims this to be + * 6-bit and 63 meaning bank group address bit 0 is 0, + * but reference manual claims 5-bit without 'neutral' value + * See MX8M_Mini_DDR4_RPA_v17, MX8M_Nano_DDR4_RPA_v8 + */ if (FIELD_GET(DDRC_ADDRMAP8_BG_B0, addrmap[8]) != 0b11111) banks++; if (FIELD_GET(DDRC_ADDRMAP8_BG_B1, addrmap[8]) != 0b111111) @@ -446,7 +453,13 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[DDRC_ADDRMAP_LENGTH], return reduced_adress_space ? size * 3 / 4 : size; } -static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) +static void imx_ddrc_set_mstr_device_config(u32 *mstr, unsigned bits) +{ + *mstr &= ~DDRC_MSTR_DEVICE_CONFIG; + *mstr |= FIELD_PREP(DDRC_MSTR_DEVICE_CONFIG, fls(bits / 8)); +} + +static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc, unsigned buswidth) { const u32 addrmap[DDRC_ADDRMAP_LENGTH] = { readl(ddrc + DDRC_ADDRMAP(0)), @@ -485,17 +498,28 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) }; const bool reduced_adress_space = FIELD_GET(DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB, addrmap[6]); + u32 mstr = readl(ddrc + DDRC_MSTR); + + /* Device config is ignored and taken as 32-bit for LPDDR4 */ + if (mstr & DDRC_MSTR_LPDDR4) + imx_ddrc_set_mstr_device_config(&mstr, buswidth); return imx_ddrc_sdram_size(ddrc, addrmap, 12, ARRAY_AND_SIZE(col_b), 18, ARRAY_AND_SIZE(row_b), - reduced_adress_space, true); + reduced_adress_space, mstr); } static int imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) { return arm_add_mem_device("ram0", data->base0, - imx8m_ddrc_sdram_size(mmdcbase)); + imx8m_ddrc_sdram_size(mmdcbase, 32)); +} + +static int imx8mn_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ + return arm_add_mem_device("ram0", data->base0, + imx8m_ddrc_sdram_size(mmdcbase, 16)); } static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) @@ -527,11 +551,15 @@ static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) }; const bool reduced_adress_space = FIELD_GET(DDRC_ADDRMAP6_LPDDR3_6GB_12GB, addrmap[6]); + u32 mstr = readl(ddrc + DDRC_MSTR); + + /* Device config is unused on i.MX7, so rewrite it as 32-bit wide */ + imx_ddrc_set_mstr_device_config(&mstr, 32); return imx_ddrc_sdram_size(ddrc, addrmap, 11, ARRAY_AND_SIZE(col_b), 15, ARRAY_AND_SIZE(row_b), - reduced_adress_space, false); + reduced_adress_space, mstr); } static int imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) @@ -629,6 +657,11 @@ static __maybe_unused struct imx_esdctl_data imx8mq_data = { .add_mem = imx8m_ddrc_add_mem, }; +static __maybe_unused struct imx_esdctl_data imx8mn_data = { + .base0 = MX8M_DDR_CSD1_BASE_ADDR, + .add_mem = imx8mn_ddrc_add_mem, +}; + static __maybe_unused struct imx_esdctl_data imx7d_data = { .base0 = MX7_DDR_BASE_ADDR, .add_mem = imx7d_ddrc_add_mem, @@ -703,7 +736,7 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = { .data = &imx8mq_data }, { .compatible = "fsl,imx8mn-ddrc", - .data = &imx8mq_data + .data = &imx8mn_data }, { .compatible = "fsl,imx8mq-ddrc", .data = &imx8mq_data @@ -890,11 +923,11 @@ void __noreturn vf610_barebox_entry(void *boarddata) boarddata); } -static void __noreturn imx8m_barebox_entry(void *boarddata) +static void __noreturn imx8m_barebox_entry(void *boarddata, unsigned buswidth) { resource_size_t size; - size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR)); + size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR), buswidth); /* * We artificially limit detected memory size to force malloc * pool placement to be within 4GiB address space, so as to @@ -910,22 +943,22 @@ static void __noreturn imx8m_barebox_entry(void *boarddata) void __noreturn imx8mm_barebox_entry(void *boarddata) { - imx8m_barebox_entry(boarddata); + imx8m_barebox_entry(boarddata, 32); } void __noreturn imx8mn_barebox_entry(void *boarddata) { - imx8m_barebox_entry(boarddata); + imx8m_barebox_entry(boarddata, 16); } void __noreturn imx8mp_barebox_entry(void *boarddata) { - imx8m_barebox_entry(boarddata); + imx8m_barebox_entry(boarddata, 32); } void __noreturn imx8mq_barebox_entry(void *boarddata) { - imx8m_barebox_entry(boarddata); + imx8m_barebox_entry(boarddata, 32); } void __noreturn imx7d_barebox_entry(void *boarddata) diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index 64d4d77ff5..3b0c587cc5 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -422,54 +422,12 @@ static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data) static int imx_bbu_internal_mmcboot_update(struct bbu_handler *handler, struct bbu_data *data) { - struct bbu_data _data = *data; int ret; - char *bootpartvar; - const char *bootpart; - char *devicefile; - const char *devname = devpath_to_name(data->devicefile); - ret = device_detect_by_name(devname); - if (ret) { - pr_err("Couldn't detect device '%s'\n", devname); - return ret; - } - - ret = asprintf(&bootpartvar, "%s.boot", devname); - if (ret < 0) - return ret; - - bootpart = getenv(bootpartvar); - if (!bootpart) { - pr_err("Couldn't read the value of '%s'\n", bootpartvar); - ret = -ENOENT; - goto free_bootpartvar; - } - - if (!strcmp(bootpart, "boot0")) { - bootpart = "boot1"; - } else { - bootpart = "boot0"; - } - - ret = asprintf(&devicefile, "/dev/%s.%s", devname, bootpart); - if (ret < 0) - goto free_bootpartvar; - - _data.devicefile = devicefile; - - ret = imx_bbu_update(handler, &_data); - if (ret) - goto free_devicefile; - - /* on success switch boot source */ - ret = setenv(bootpartvar, bootpart); - -free_devicefile: - free(devicefile); + ret = bbu_mmcboot_handler(handler, data, imx_bbu_update); -free_bootpartvar: - free(bootpartvar); + if (ret == -ENOENT) + pr_err("Couldn't read the value of .boot parameter\n"); return ret; } diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 6b7cdac541..8b275bd6f6 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -13,7 +13,6 @@ #include <mach/ocotp.h> #include <mach/imx8mp-regs.h> #include <mach/imx8mq-regs.h> -#include <mach/imx8m-ccm-regs.h> #include <soc/imx8m/clk-early.h> #include <linux/iopoll.h> diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile index e81284ec3b..6b42196b23 100644 --- a/arch/arm/mach-omap/Makefile +++ b/arch/arm/mach-omap/Makefile @@ -16,13 +16,13 @@ # # obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o -pbl-$(CONFIG_ARCH_OMAP) += syslib.o +pbl-$(CONFIG_ARCH_OMAP) += syslib.o omap_generic.o obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o -obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o -obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o am35xx_emif4.o +obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o emif4.o +obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o emif4.o obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o obj-$(CONFIG_ARCH_OMAP3) += omap3_clock.o pbl-$(CONFIG_ARCH_OMAP3) += omap3_clock.o diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 3c5cdf065c..bfe5b3dc73 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -23,6 +23,7 @@ #include <asm/barebox-arm.h> #include <mach/am33xx-silicon.h> #include <mach/am33xx-clock.h> +#include <mach/emif4.h> #include <mach/generic.h> #include <mach/sys_info.h> #include <mach/am33xx-generic.h> @@ -307,18 +308,20 @@ void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl) void am33xx_config_sdram(const struct am33xx_emif_regs *regs) { - writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); - writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); - writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); - writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); - writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); - writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); - writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); - writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); - writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); + const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE); + + writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1); + writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW); + writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_2); + writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1); + writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW); + writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2); + writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW); + writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3); + writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW); if (regs->ocp_config) - writel(regs->ocp_config, AM33XX_EMIF4_0_REG(OCP_CONFIG)); + writel(regs->ocp_config, emif4 + EMIF4_OCP_CONFIG); if (regs->zq_config) { /* @@ -326,75 +329,23 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs) * about 570us for a delay, which will be long enough * to configure things. */ - writel(0x2800, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - writel(regs->zq_config, AM33XX_EMIF4_0_REG(ZQ_CONFIG)); + writel(0x2800, emif4 + EMIF4_SDRAM_REF_CTRL); + writel(regs->zq_config, emif4 + EMIF4_ZQ_CONFIG); writel(regs->sdram_config, CM_EMIF_SDRAM_CONFIG); - writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - writel(regs->sdram_ref_ctrl, - AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - writel(regs->sdram_ref_ctrl, - AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); - + writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG); + writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL); + writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); } - writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); - writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); -} - -/** - * am335x_sdram_size - read back SDRAM size from sdram_config register - * - * @return: The SDRAM size - */ -unsigned long am335x_sdram_size(void) -{ - int rows, cols, width, banks; - unsigned long size; - uint32_t sdram_config = readl(CM_EMIF_SDRAM_CONFIG); - - rows = ((sdram_config >> 7) & 0x7) + 9; - cols = (sdram_config & 0x7) + 8; - - switch ((sdram_config >> 14) & 0x3) { - case 0: - width = 4; - break; - case 1: - width = 2; - break; - default: - return 0; - } - - switch ((sdram_config >> 4) & 0x7) { - case 0: - banks = 1; - break; - case 1: - banks = 2; - break; - case 2: - banks = 4; - break; - case 3: - banks = 8; - break; - default: - return 0; - } - - size = (1 << rows) * (1 << cols) * banks * width; - - debug("%s: sdram_config: 0x%08x cols: %2d rows: %2d width: %2d banks: %2d size: 0x%08lx\n", - __func__, sdram_config, cols, rows, width, banks, size); - - return size; + writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL); + writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); + writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG); } void __noreturn am335x_barebox_entry(void *boarddata) { - barebox_arm_entry(0x80000000, am335x_sdram_size(), boarddata); + barebox_arm_entry(0x80000000, + emif4_sdram_size(IOMEM(AM33XX_EMIF4_BASE)), boarddata); } void am33xx_config_io_ctrl(int ioctrl) diff --git a/arch/arm/mach-omap/am33xx_scrm.c b/arch/arm/mach-omap/am33xx_scrm.c index 0f13a9deb6..e10e80ce31 100644 --- a/arch/arm/mach-omap/am33xx_scrm.c +++ b/arch/arm/mach-omap/am33xx_scrm.c @@ -21,10 +21,12 @@ #include <asm/barebox-arm.h> #include <asm/memory.h> #include <mach/am33xx-silicon.h> +#include <mach/emif4.h> static int am33xx_scrm_probe(struct device_d *dev) { - return arm_add_mem_device("ram0", 0x80000000, am335x_sdram_size()); + return arm_add_mem_device("ram0", 0x80000000, + emif4_sdram_size(IOMEM(AM33XX_EMIF4_BASE))); } static __maybe_unused struct of_device_id am33xx_scrm_dt_ids[] = { diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c deleted file mode 100644 index 678a338fd6..0000000000 --- a/arch/arm/mach-omap/am35xx_emif4.c +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Author : - * Vaibhav Hiremath <hvaibhav@ti.com> - * - * Based on mem.c and sdrc.c - * - * Copyright (C) 2010 - * Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include <common.h> -#include <io.h> -#include <mach/emif4.h> -#include <mach/omap3-silicon.h> - -/* - * do_pac200_emif4_init - - * - Init the emif4 module for DDR access - * - Early init routines, called from flash or SRAM. - */ -void am35xx_emif4_init(void) -{ - unsigned int regval; - struct emif4 *emif4_base = IOMEM(OMAP3_SDRC_BASE); - - /* Set the DDR PHY parameters in PHY ctrl registers */ - regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | - EMIF4_DDR1_EXT_STRB_DIS); - writel(regval, &emif4_base->ddr_phyctrl1); - writel(regval, &emif4_base->ddr_phyctrl1_shdw); - writel(0, &emif4_base->ddr_phyctrl2); - - /* Reset the DDR PHY and wait till completed */ - regval = readl(&emif4_base->sdram_iodft_tlgc); - regval |= (1 << 10); - writel(regval, &emif4_base->sdram_iodft_tlgc); - - /* Wait till that bit clears*/ - while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)); - - /* Re-verify the DDR PHY status*/ - while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0); - - regval |= (1 << 0); - writel(regval, &emif4_base->sdram_iodft_tlgc); - - /* Set SDR timing registers */ - regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | - EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS | - EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD | - EMIF4_TIM1_T_RP); - writel(regval, &emif4_base->sdram_time1); - writel(regval, &emif4_base->sdram_time1_shdw); - - regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP | - EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR | - EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP); - writel(regval, &emif4_base->sdram_time2); - writel(regval, &emif4_base->sdram_time2_shdw); - - regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC); - writel(regval, &emif4_base->sdram_time3); - writel(regval, &emif4_base->sdram_time3_shdw); - - /* Set the PWR control register */ - regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE | - EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE); - writel(regval, &emif4_base->sdram_pwr_mgmt); - writel(regval, &emif4_base->sdram_pwr_mgmt_shdw); - - /* Set the DDR refresh rate control register */ - regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS); - writel(regval, &emif4_base->sdram_refresh_ctrl); - writel(regval, &emif4_base->sdram_refresh_ctrl_shdw); - - /* set the SDRAM configuration register */ - regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK | - EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE | - EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD | - EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL | - EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM | - EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP); - writel(regval, &emif4_base->sdram_config); -} diff --git a/arch/arm/mach-omap/emif4.c b/arch/arm/mach-omap/emif4.c new file mode 100644 index 0000000000..b5a53e8c63 --- /dev/null +++ b/arch/arm/mach-omap/emif4.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author : + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * Based on mem.c and sdrc.c + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <io.h> +#include <mach/emif4.h> + +/* + * AM35xx configuration values + */ +#define EMIF4_TIM1_T_RP (0x3 << 25) +#define EMIF4_TIM1_T_RCD (0x3 << 21) +#define EMIF4_TIM1_T_WR (0x3 << 17) +#define EMIF4_TIM1_T_RAS (0x7 << 12) +#define EMIF4_TIM1_T_RC (0xa << 6) +#define EMIF4_TIM1_T_RRD (0x2 << 3) +#define EMIF4_TIM1_T_WTR (0x2) + +#define EMIF4_TIM2_T_XP (0x2 << 28) +#define EMIF4_TIM2_T_ODT (0x0 << 25) +#define EMIF4_TIM2_T_XSNR (0x1c << 16) +#define EMIF4_TIM2_T_XSRD (0xc8 << 6) +#define EMIF4_TIM2_T_RTP (0x1 << 3) +#define EMIF4_TIM2_T_CKE (0x2) + +#define EMIF4_TIM3_T_RFC (0x15 << 4) +#define EMIF4_TIM3_T_RAS_MAX (0xf) + +#define EMIF4_PWR_IDLE_MODE (0x2 << 30) +#define EMIF4_PWR_DPD_DIS (0x0 << 10) +#define EMIF4_PWR_DPD_EN (0x1 << 10) +#define EMIF4_PWR_LP_MODE (0x0 << 8) +#define EMIF4_PWR_PM_TIM (0x0) + +#define EMIF4_INITREF_DIS (0x0 << 31) +#define EMIF4_REFRESH_RATE (0x257) + +#define EMIF4_CFG_SDRAM_TYP (0x2 << 29) +#define EMIF4_CFG_IBANK_POS (0x0 << 27) +#define EMIF4_CFG_DDR_TERM (0x3 << 24) +#define EMIF4_CFG_DDR2_DDQS (0x1 << 23) +#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20) +#define EMIF4_CFG_SDR_DRV (0x0 << 18) +#define EMIF4_CFG_NARROW_MD (0x0 << 14) +#define EMIF4_CFG_CL (0x5 << 10) +#define EMIF4_CFG_ROWSIZE (0x0 << 7) +#define EMIF4_CFG_IBANK (0x3 << 4) +#define EMIF4_CFG_EBANK (0x0 << 3) +#define EMIF4_CFG_PGSIZE (0x2) + +/* + * EMIF4 PHY Control 1 register configuration + */ +#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7) +#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7) +#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6) +#define EMIF4_DDR1_PWRDN_EN (0x1 << 6) +#define EMIF4_DDR1_READ_LAT (0x6 << 0) + +/** + * emif4_sdram_size - read back SDRAM size from sdram_config register + * + * @return: The SDRAM size + */ +unsigned long emif4_sdram_size(const void __iomem *emif4) +{ + uint32_t sdram_config = readl(emif4 + EMIF4_SDRAM_CONFIG); + int rows, cols, width, banks; + unsigned long size; + + rows = ((sdram_config >> 7) & 0x7) + 9; + cols = (sdram_config & 0x7) + 8; + + switch ((sdram_config >> 14) & 0x3) { + case 0: + width = 4; + break; + case 1: + width = 2; + break; + default: + return 0; + } + + switch ((sdram_config >> 4) & 0x7) { + case 0: + banks = 1; + break; + case 1: + banks = 2; + break; + case 2: + banks = 4; + break; + case 3: + banks = 8; + break; + default: + return 0; + } + + size = (1 << rows) * (1 << cols) * banks * width; + + debug("SDRAM_CONFIG: 0x%08x, cols: %2d, rows: %2d, width: %2d, banks: %2d, size: 0x%08lx\n", + sdram_config, cols, rows, width, banks, size); + + return size; +} + +/* + * - Init the emif4 module for DDR access + * - Early init routines, called from flash or SRAM. + */ +void am35xx_emif4_init(const void __iomem *emif4) +{ + unsigned int regval; + + /* Set the DDR PHY parameters in PHY ctrl registers */ + regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | + EMIF4_DDR1_EXT_STRB_DIS); + writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1); + writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW); + writel(0, emif4 + EMIF4_DDR_PHY_CTRL_2); + + /* Reset the DDR PHY and wait till completed */ + regval = readl(emif4 + EMIF4_IODFT_TLGC); + regval |= (1 << 10); + writel(regval, emif4 + EMIF4_IODFT_TLGC); + + /* Wait till that bit clears*/ + while (readl(emif4 + EMIF4_IODFT_TLGC) & (1 << 10)); + + /* Re-verify the DDR PHY status*/ + while ((readl(emif4 + EMIF4_STATUS) & (1 << 2)) == 0x0); + + regval |= (1 << 0); + writel(regval, emif4 + EMIF4_IODFT_TLGC); + + /* Set SDR timing registers */ + regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | + EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS | + EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD | + EMIF4_TIM1_T_RP); + writel(regval, emif4 + EMIF4_SDRAM_TIM_1); + writel(regval, emif4 + EMIF4_SDRAM_TIM_1_SHADOW); + + regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP | + EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR | + EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP); + writel(regval, emif4 + EMIF4_SDRAM_TIM_2); + writel(regval, emif4 + EMIF4_SDRAM_TIM_2_SHADOW); + + regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC); + writel(regval, emif4 + EMIF4_SDRAM_TIM_3); + writel(regval, emif4 + EMIF4_SDRAM_TIM_3_SHADOW); + + /* Set the PWR control register */ + regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE | + EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE); + writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL); + writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL_SHADOW); + + /* Set the DDR refresh rate control register */ + regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS); + writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL); + writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); + + /* set the SDRAM configuration register */ + regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK | + EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE | + EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD | + EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL | + EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM | + EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP); + writel(regval, emif4 + EMIF4_SDRAM_CONFIG); +} diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index 0467dac03b..74b0b7638e 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -37,9 +37,6 @@ #define AM33XX_GPIO2_BASE (AM33XX_L4_PER_BASE + 0x1AC000 + 0x100) #define AM33XX_GPIO3_BASE (AM33XX_L4_PER_BASE + 0x1AE000 + 0x100) -/* EMFI Registers */ -#define AM33XX_EMFI0_BASE 0x4C000000 - #define AM33XX_DRAM_ADDR_SPACE_START 0x80000000 #define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000 @@ -83,8 +80,8 @@ #define AM33XX_WDT_BASE 0x44E35000 /* EMIF Base address */ -#define AM33XX_EMIF4_0_CFG_BASE 0x4C000000 -#define AM33XX_EMIF4_1_CFG_BASE 0x4D000000 +#define AM33XX_EMIF4_BASE 0x4c000000 + #define AM33XX_DMM_BASE 0x4E000000 #define AM335X_CPSW_BASE 0x4A100000 @@ -97,30 +94,6 @@ #define AM33XX_DMM_LISA_MAP__3 (AM33XX_DMM_BASE + 0x4C) #define AM33XX_DMM_PAT_BASE_ADDR (AM33XX_DMM_BASE + 0x460) -#define AM33XX_EMIF4_0_REG(REGNAME) (AM33XX_EMIF4_0_CFG_BASE + EMIF4_##REGNAME) -#define AM33XX_EMIF4_1_REG(REGNAME) (AM33XX_EMIF4_1_CFG_BASE + EMIF4_##REGNAME) - -#define EMIF4_MOD_ID_REV 0x0 -#define EMIF4_SDRAM_STATUS 0x04 -#define EMIF4_SDRAM_CONFIG 0x08 -#define EMIF4_SDRAM_CONFIG2 0x0C -#define EMIF4_SDRAM_REF_CTRL 0x10 -#define EMIF4_SDRAM_REF_CTRL_SHADOW 0x14 -#define EMIF4_SDRAM_TIM_1 0x18 -#define EMIF4_SDRAM_TIM_1_SHADOW 0x1C -#define EMIF4_SDRAM_TIM_2 0x20 -#define EMIF4_SDRAM_TIM_2_SHADOW 0x24 -#define EMIF4_SDRAM_TIM_3 0x28 -#define EMIF4_SDRAM_TIM_3_SHADOW 0x2C -#define EMIF0_SDRAM_MGMT_CTRL 0x38 -#define EMIF0_SDRAM_MGMT_CTRL_SHD 0x3C -#define EMIF4_OCP_CONFIG 0x54 -#define EMIF4_ZQ_CONFIG 0xC8 -#define EMIF4_DDR_PHY_CTRL_1 0xE4 -#define EMIF4_DDR_PHY_CTRL_1_SHADOW 0xE8 -#define EMIF4_DDR_PHY_CTRL_2 0xEC -#define EMIF4_IODFT_TLGC 0x60 - #define AM33XX_VTP0_CTRL_REG 0x44E10E0C #define AM33XX_VTP1_CTRL_REG 0x48140E10 @@ -247,7 +220,6 @@ void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr); void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl, const struct am33xx_emif_regs *emif_regs, const struct am33xx_ddr_data *ddr_data); -unsigned long am335x_sdram_size(void); void am335x_barebox_entry(void *boarddata); #endif diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h index 1f9c2938a1..00702e60e8 100644 --- a/arch/arm/mach-omap/include/mach/emif4.h +++ b/arch/arm/mach-omap/include/mach/emif4.h @@ -24,82 +24,29 @@ #ifndef _EMIF_H_ #define _EMIF_H_ -/* - * Configuration values - */ -#define EMIF4_TIM1_T_RP (0x3 << 25) -#define EMIF4_TIM1_T_RCD (0x3 << 21) -#define EMIF4_TIM1_T_WR (0x3 << 17) -#define EMIF4_TIM1_T_RAS (0x7 << 12) /* 8->7 */ -#define EMIF4_TIM1_T_RC (0xA << 6) -#define EMIF4_TIM1_T_RRD (0x2 << 3) -#define EMIF4_TIM1_T_WTR (0x2) - -#define EMIF4_TIM2_T_XP (0x2 << 28) -#define EMIF4_TIM2_T_ODT (0x0 << 25) /* 2? */ -#define EMIF4_TIM2_T_XSNR (0x1C << 16) -#define EMIF4_TIM2_T_XSRD (0xC8 << 6) -#define EMIF4_TIM2_T_RTP (0x1 << 3) -#define EMIF4_TIM2_T_CKE (0x2) - -#define EMIF4_TIM3_T_RFC (0x15 << 4) /* 25->15 */ -#define EMIF4_TIM3_T_RAS_MAX (0xf) /* 7->f */ - -#define EMIF4_PWR_IDLE_MODE (0x2 << 30) -#define EMIF4_PWR_DPD_DIS (0x0 << 10) -#define EMIF4_PWR_DPD_EN (0x1 << 10) -#define EMIF4_PWR_LP_MODE (0x0 << 8) -#define EMIF4_PWR_PM_TIM (0x0) - -#define EMIF4_INITREF_DIS (0x0 << 31) -#define EMIF4_REFRESH_RATE (0x257) /* 50f->257 */ - -#define EMIF4_CFG_SDRAM_TYP (0x2 << 29) -#define EMIF4_CFG_IBANK_POS (0x0 << 27) -#define EMIF4_CFG_DDR_TERM (0x3 << 24) /* --> 0x3 */ -#define EMIF4_CFG_DDR2_DDQS (0x1 << 23) -#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20) -#define EMIF4_CFG_SDR_DRV (0x0 << 18) -#define EMIF4_CFG_NARROW_MD (0x0 << 14) -#define EMIF4_CFG_CL (0x5 << 10) -#define EMIF4_CFG_ROWSIZE (0x0 << 7) /* --> 0x4: a0..a12 */ -#define EMIF4_CFG_IBANK (0x3 << 4) -#define EMIF4_CFG_EBANK (0x0 << 3) -#define EMIF4_CFG_PGSIZE (0x2) /* 10 columns */ - -/* - * EMIF4 PHY Control 1 register configuration - */ -#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7) -#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7) -#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6) -#define EMIF4_DDR1_PWRDN_EN (0x1 << 6) -#define EMIF4_DDR1_READ_LAT (0x6 << 0) - -struct emif4 { - unsigned int emif_mod_id_rev; - unsigned int sdram_sts; - unsigned int sdram_config; - unsigned int res1; - unsigned int sdram_refresh_ctrl; - unsigned int sdram_refresh_ctrl_shdw; - unsigned int sdram_time1; - unsigned int sdram_time1_shdw; - unsigned int sdram_time2; - unsigned int sdram_time2_shdw; - unsigned int sdram_time3; - unsigned int sdram_time3_shdw; - unsigned char res2[8]; - unsigned int sdram_pwr_mgmt; - unsigned int sdram_pwr_mgmt_shdw; - unsigned char res3[32]; - unsigned int sdram_iodft_tlgc; - unsigned char res4[128]; - unsigned int ddr_phyctrl1; - unsigned int ddr_phyctrl1_shdw; - unsigned int ddr_phyctrl2; -}; - -void am35xx_emif4_init(void); +#define EMIF4_MOD_ID_REV 0x0 +#define EMIF4_STATUS 0x04 +#define EMIF4_SDRAM_CONFIG 0x08 +#define EMIF4_SDRAM_CONFIG2 0x0c +#define EMIF4_SDRAM_REF_CTRL 0x10 +#define EMIF4_SDRAM_REF_CTRL_SHADOW 0x14 +#define EMIF4_SDRAM_TIM_1 0x18 +#define EMIF4_SDRAM_TIM_1_SHADOW 0x1c +#define EMIF4_SDRAM_TIM_2 0x20 +#define EMIF4_SDRAM_TIM_2_SHADOW 0x24 +#define EMIF4_SDRAM_TIM_3 0x28 +#define EMIF4_SDRAM_TIM_3_SHADOW 0x2c +#define EMIF4_POWER_MANAGEMENT_CTRL 0x38 +#define EMIF4_POWER_MANAGEMENT_CTRL_SHADOW 0x3c +#define EMIF4_OCP_CONFIG 0x54 +#define EMIF4_ZQ_CONFIG 0xc8 +#define EMIF4_DDR_PHY_CTRL_1 0xe4 +#define EMIF4_DDR_PHY_CTRL_1_SHADOW 0xe8 +#define EMIF4_DDR_PHY_CTRL_2 0xec +#define EMIF4_IODFT_TLGC 0x60 + +unsigned long emif4_sdram_size(const void __iomem *emif4); + +void am35xx_emif4_init(const void __iomem *emif4); #endif /* endif _EMIF_H_ */ diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h index fa391c8d48..8b2b7a4f0c 100644 --- a/arch/arm/mach-omap/include/mach/generic.h +++ b/arch/arm/mach-omap/include/mach/generic.h @@ -79,6 +79,8 @@ static inline int omap_set_mmc_dev(const char *mmcdev) void __noreturn omap_start_barebox(void *barebox); +void omap_watchdog_disable(const void __iomem *wdt); + void omap_set_bootmmc_devname(const char *devname); const char *omap_get_bootmmc_devname(void); diff --git a/arch/arm/mach-omap/include/mach/wdt.h b/arch/arm/mach-omap/include/mach/wdt.h deleted file mode 100644 index 9a5288d386..0000000000 --- a/arch/arm/mach-omap/include/mach/wdt.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file - * @brief This file contains the Watchdog timer specific register definitions - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_OMAP_WDT_H -#define __ASM_ARCH_OMAP_WDT_H - -/** Watchdog Register defines */ -#define OMAP3_WDT_REG(REGNAME) (OMAP3_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME) -#define AM33XX_WDT_REG(REGNAME) (AM33XX_WDT_BASE + OMAP_WDT_##REGNAME) - -#define OMAP_WDT_WIDR (0x000) -#define OMAP_WDT_SYSCONFIG (0x010) -#define OMAP_WDT_WD_SYSSTATUS (0x014) -#define OMAP_WDT_WISR (0x018) -#define OMAP_WDT_WIER (0x01C) -#define OMAP_WDT_WCLR (0x024) -#define OMAP_WDT_WCRR (0x028) -#define OMAP_WDT_WLDR (0x02C) -#define OMAP_WDT_WTGR (0x030) -#define OMAP_WDT_WWPS (0x034) -#define OMAP_WDT_WSPR (0x048) - -/* Unlock Code for Watchdog timer to disable the same */ -#define WDT_DISABLE_CODE1 0xAAAA -#define WDT_DISABLE_CODE2 0x5555 - -#endif /* __ASM_ARCH_OMAP_WDT_H */ diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c index 3f6a346277..69f2d51a62 100644 --- a/arch/arm/mach-omap/omap3_generic.c +++ b/arch/arm/mach-omap/omap3_generic.c @@ -40,7 +40,6 @@ #include <mach/omap3-smx.h> #include <mach/clocks.h> #include <mach/omap3-clock.h> -#include <mach/wdt.h> #include <mach/sys_info.h> #include <mach/syslib.h> #include <mach/omap3-generic.h> @@ -379,19 +378,10 @@ static void secureworld_exit(void) */ static void watchdog_init(void) { - int pending = 1; - sr32(OMAP3_CM_REG(FCLKEN_WKUP), 5, 1, 1); sr32(OMAP3_CM_REG(ICLKEN_WKUP), 5, 1, 1); - wait_on_value((0x1 << 5), 0x20, OMAP3_CM_REG(IDLEST_WKUP), 5); - - writel(WDT_DISABLE_CODE1, OMAP3_WDT_REG(WSPR)); - - do { - pending = readl(OMAP3_WDT_REG(WWPS)); - } while (pending); - writel(WDT_DISABLE_CODE2, OMAP3_WDT_REG(WSPR)); + omap_watchdog_disable(IOMEM(OMAP3_MPU_WDTIMER_BASE)); } /** diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index 406b686318..6d165b7f68 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -65,18 +65,6 @@ void omap4_set_warmboot_order(u32 *device_list) writel(OMAP44XX_SAR_CH_START, OMAP44XX_SAR_CH_ADDRESS); } -#define WATCHDOG_WSPR 0x48 -#define WATCHDOG_WWPS 0x34 - -static void wait_for_command_complete(void) -{ - int pending = 1; - - do { - pending = readl(OMAP44XX_WDT2_BASE + WATCHDOG_WWPS); - } while (pending); -} - /* EMIF */ #define EMIF_MOD_ID_REV 0x0000 #define EMIF_STATUS 0x0004 @@ -463,14 +451,8 @@ unsigned int omap4_revision(void) */ static int watchdog_init(void) { - void __iomem *wd2_base = (void *)OMAP44XX_WDT2_BASE; - - if (!cpu_is_omap4()) - return 0; - - writel(WD_UNLOCK1, wd2_base + WATCHDOG_WSPR); - wait_for_command_complete(); - writel(WD_UNLOCK2, wd2_base + WATCHDOG_WSPR); + if (cpu_is_omap4()) + omap_watchdog_disable(IOMEM(OMAP44XX_WDT2_BASE)); return 0; } diff --git a/arch/arm/mach-omap/omap_generic.c b/arch/arm/mach-omap/omap_generic.c index a1c0aeb595..6bb26a6ef0 100644 --- a/arch/arm/mach-omap/omap_generic.c +++ b/arch/arm/mach-omap/omap_generic.c @@ -70,6 +70,24 @@ void __noreturn omap_start_barebox(void *barebox) hang(); } +#define OMAP_WDT_WWPS 0x34 +#define OMAP_WDT_WSPR 0x48 +#define WDT_DISABLE_CODE1 0xaaaa +#define WDT_DISABLE_CODE2 0x5555 + +void omap_watchdog_disable(const void __iomem *wdt) +{ + /* WDT is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + __raw_writel(WDT_DISABLE_CODE1, wdt + OMAP_WDT_WSPR); + + do { + } while (__raw_readl(wdt + OMAP_WDT_WWPS)); + + __raw_writel(WDT_DISABLE_CODE2, wdt + OMAP_WDT_WSPR); +} + #ifdef CONFIG_BOOTM static int do_bootm_omap_barebox(struct image_data *data) { diff --git a/arch/arm/mach-omap/syslib.c b/arch/arm/mach-omap/syslib.c index 42da348c5a..488f0ab859 100644 --- a/arch/arm/mach-omap/syslib.c +++ b/arch/arm/mach-omap/syslib.c @@ -52,19 +52,16 @@ void sdelay(unsigned long loops) * @param[in] read_addr address to read from * @param[in] bound max iterations * - * @return 1 if match_value is found, else if bound iterations reached, + * @return non zero if match_value is found, else if bound iterations reached, * returns 0 */ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) { - u32 i = 0, val; do { - ++i; - val = readl(read_addr) & read_bit_mask; + u32 val = readl(read_addr) & read_bit_mask; if (val == match_value) - return 1; - if (i == bound) - return 0; - } while (1); -} + break; + } while (--bound); + return bound; +} diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c index 6d3704b8cf..6a02e2b589 100644 --- a/arch/arm/mach-omap/xload.c +++ b/arch/arm/mach-omap/xload.c @@ -115,7 +115,6 @@ static void *omap_xload_boot_mmc(void) { int ret; void *buf; - int len; const char *diskdev; char *partname; @@ -137,9 +136,9 @@ static void *omap_xload_boot_mmc(void) free(partname); - buf = read_file("/barebox.bin", &len); + buf = read_file("/barebox.bin", NULL); if (!buf) - buf = read_file("/boot/barebox.bin", &len); + buf = read_file("/boot/barebox.bin", NULL); if (!buf) { printf("could not read barebox.bin from sd card\n"); return NULL; @@ -156,7 +155,6 @@ static void *omap_xload_boot_spi(struct omap_barebox_part *part) static void *omap4_xload_boot_usb(void){ int ret; void *buf; - int len; ret = mount("omap4_usbboot", "omap4_usbbootfs", "/", NULL); if (ret) { @@ -164,7 +162,7 @@ static void *omap4_xload_boot_usb(void){ return NULL; } - buf = read_file("/barebox.bin", &len); + buf = read_file("/barebox.bin", NULL); if (!buf) printf("could not read barebox.bin from omap4_usbbootfs\n"); @@ -175,7 +173,6 @@ static void *omap_serial_boot(void){ struct console_device *cdev; int ret; void *buf; - int len; int fd; /* need temporary place to store file */ @@ -203,7 +200,7 @@ static void *omap_serial_boot(void){ return NULL; } - buf = read_file("/barebox.bin", &len); + buf = read_file("/barebox.bin", NULL); if (!buf) printf("could not read barebox.bin from serial\n"); @@ -216,7 +213,6 @@ static void *am33xx_net_boot(void) { void *buf = NULL; int err; - int len; struct dhcp_req_param dhcp_param; const char *bootfile; IPaddr_t ip; @@ -276,7 +272,7 @@ static void *am33xx_net_boot(void) file = basprintf("%s/%s", TFTP_MOUNT, bootfile); - buf = read_file(file, &len); + buf = read_file(file, NULL); if (!buf) printf("could not read %s.\n", bootfile); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index df9e59790a..1f3ba706ee 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -80,6 +80,12 @@ config MACH_PINE64_QUARTZ64 help Say Y here if you are using a Pine64 Quartz64 +config MACH_RADXA_ROCK3 + select ARCH_RK3568 + bool "Radxa ROCK3" + help + Say Y here if you are using a Radxa ROCK3 + comment "select board features:" config ARCH_RK3399_OPTEE diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index 86c13b8fca..837449150c 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -4,3 +4,4 @@ obj-y := init.o obj-pbl-y := ddrctrl.o pbl-y := bl33-generic.o obj-$(CONFIG_BOOTM) += stm32image.o +obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o diff --git a/arch/arm/mach-stm32mp/bbu.c b/arch/arm/mach-stm32mp/bbu.c new file mode 100644 index 0000000000..545965198f --- /dev/null +++ b/arch/arm/mach-stm32mp/bbu.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#define pr_fmt(fmt) "stm32mp-bbu: " fmt +#include <common.h> +#include <malloc.h> +#include <bbu.h> +#include <filetype.h> +#include <errno.h> +#include <fs.h> +#include <fcntl.h> +#include <linux/sizes.h> +#include <linux/stat.h> +#include <ioctl.h> +#include <mach/bbu.h> +#include <libfile.h> +#include <linux/bitfield.h> + +#define STM32MP_BBU_IMAGE_HAVE_FSBL BIT(0) +#define STM32MP_BBU_IMAGE_HAVE_FIP BIT(1) + +struct stm32mp_bbu_handler { + struct bbu_handler handler; + loff_t offset; +}; + +#define to_stm32mp_bbu_handler(h) container_of(h, struct stm32mp_bbu_handler, h) + +static int stm32mp_bbu_gpt_part_update(struct bbu_handler *handler, + const struct bbu_data *data, + const char *part, bool optional) +{ + struct bbu_data gpt_data = *data; + struct stat st; + int ret; + + gpt_data.devicefile = basprintf("%s.%s", gpt_data.devicefile, part); + if (!gpt_data.devicefile) + return -ENOMEM; + + pr_debug("Attempting %s update\n", gpt_data.devicefile); + + ret = stat(gpt_data.devicefile, &st); + if (ret == -ENOENT) { + if (optional) + return 0; + pr_err("Partition %s does not exist\n", gpt_data.devicefile); + } + if (ret) + goto out; + + ret = bbu_std_file_handler(handler, &gpt_data); +out: + kfree_const(gpt_data.devicefile); + return ret; +} + +static int stm32mp_bbu_mmc_update(struct bbu_handler *handler, + struct bbu_data *data) +{ + struct stm32mp_bbu_handler *priv = to_stm32mp_bbu_handler(handler); + int fd, ret; + size_t image_len = data->len; + const void *buf = data->image; + struct stat st; + + pr_debug("Attempting eMMC boot partition update\n"); + + ret = bbu_confirm(data); + if (ret) + return ret; + + fd = open(data->devicefile, O_RDWR); + if (fd < 0) + return fd; + + ret = fstat(fd, &st); + if (ret) + goto close; + + if (st.st_size < priv->offset || image_len > st.st_size - priv->offset) { + ret = -ENOSPC; + goto close; + } + + ret = pwrite_full(fd, buf, image_len, priv->offset); + if (ret < 0) + pr_err("writing to %s failed with %pe\n", data->devicefile, ERR_PTR(ret)); + +close: + close(fd); + + return ret < 0 ? ret : 0; +} + +/* + * TF-A compiled with STM32_EMMC_BOOT will first check for FIP image + * at offset SZ_256K and then in GPT partition of that name. + */ +static int stm32mp_bbu_mmc_fip_handler(struct bbu_handler *handler, + struct bbu_data *data) +{ + struct stm32mp_bbu_handler *priv = to_stm32mp_bbu_handler(handler); + enum filetype filetype; + int image_flags = 0, ret; + bool is_emmc = true; + + filetype = file_detect_type(data->image, data->len); + + switch (filetype) { + case filetype_stm32_image_fsbl_v1: + priv->offset = 0; + image_flags |= STM32MP_BBU_IMAGE_HAVE_FSBL; + if (data->len > SZ_256K) + image_flags |= STM32MP_BBU_IMAGE_HAVE_FIP; + break; + default: + if (!bbu_force(data, "incorrect image type. Expected: %s, got %s", + file_type_to_string(filetype_fip), + file_type_to_string(filetype))) + return -EINVAL; + /* If forced assume it's a SSBL */ + filetype = filetype_fip; + fallthrough; + case filetype_fip: + priv->offset = SZ_256K; + image_flags |= STM32MP_BBU_IMAGE_HAVE_FIP; + break; + } + + pr_debug("Handling %s\n", file_type_to_string(filetype)); + + data->flags |= BBU_FLAG_MMC_BOOT_ACK; + + ret = bbu_mmcboot_handler(handler, data, stm32mp_bbu_mmc_update); + if (ret == -ENOENT) { + pr_debug("Not an eMMC, falling back to GPT fsbl1 partition\n"); + is_emmc = false; + ret = 0; + } + if (ret < 0) { + pr_debug("eMMC boot update failed: %pe\n", ERR_PTR(ret)); + return ret; + } + + if (!is_emmc && (image_flags & STM32MP_BBU_IMAGE_HAVE_FSBL)) { + struct bbu_data fsbl1_data = *data; + + fsbl1_data.len = min_t(size_t, fsbl1_data.len, SZ_256K); + + /* + * BootROM tells TF-A which fsbl slot was booted in r0, but TF-A + * doesn't yet propagate this to us, so for now always flash + * fsbl1 + */ + ret = stm32mp_bbu_gpt_part_update(handler, &fsbl1_data, "fsbl1", false); + } + + if (ret == 0 && (image_flags & STM32MP_BBU_IMAGE_HAVE_FIP)) { + struct bbu_data fip_data = *data; + + if (image_flags & STM32MP_BBU_IMAGE_HAVE_FSBL) { + fip_data.image += SZ_256K; + fip_data.len -= SZ_256K; + } + + /* No fip GPT partition in eMMC user area is usually ok, as + * that means TF-A is configured to load FIP from eMMC boot part + */ + ret = stm32mp_bbu_gpt_part_update(handler, &fip_data, "fip", is_emmc); + } + + if (ret < 0) + pr_debug("eMMC user area update failed: %pe\n", ERR_PTR(ret)); + + return ret; +} + +int stm32mp_bbu_mmc_fip_register(const char *name, + const char *devicefile, + unsigned long flags) +{ + struct stm32mp_bbu_handler *priv; + int ret; + + priv = xzalloc(sizeof(*priv)); + + priv->handler.flags = flags; + priv->handler.devicefile = devicefile; + priv->handler.name = name; + priv->handler.handler = stm32mp_bbu_mmc_fip_handler; + + ret = bbu_register_handler(&priv->handler); + if (ret) + free(priv); + + return ret; +} diff --git a/arch/arm/mach-stm32mp/ddrctrl.c b/arch/arm/mach-stm32mp/ddrctrl.c index ed211cf58e..31bddba764 100644 --- a/arch/arm/mach-stm32mp/ddrctrl.c +++ b/arch/arm/mach-stm32mp/ddrctrl.c @@ -5,7 +5,6 @@ #include <common.h> #include <init.h> -#include <mach/stm32.h> #include <mach/ddr_regs.h> #include <mach/entry.h> #include <mach/stm32.h> diff --git a/arch/arm/mach-stm32mp/include/mach/bbu.h b/arch/arm/mach-stm32mp/include/mach/bbu.h index d49fb045ea..b469cdeb7c 100644 --- a/arch/arm/mach-stm32mp/include/mach/bbu.h +++ b/arch/arm/mach-stm32mp/include/mach/bbu.h @@ -10,7 +10,23 @@ static inline int stm32mp_bbu_mmc_register_handler(const char *name, unsigned long flags) { return bbu_register_std_file_update(name, flags, devicefile, - filetype_stm32_image_v1); + filetype_stm32_image_ssbl_v1); } +#ifdef CONFIG_BAREBOX_UPDATE + +int stm32mp_bbu_mmc_fip_register(const char *name, const char *devicefile, + unsigned long flags); + +#else + +static inline int stm32mp_bbu_mmc_fip_register(const char *name, + const char *devicefile, + unsigned long flags) +{ + return -ENOSYS; +} + +#endif + #endif /* MACH_STM32MP_BBU_H_ */ diff --git a/arch/arm/mach-stm32mp/stm32image.c b/arch/arm/mach-stm32mp/stm32image.c index caff68651c..7867418e6c 100644 --- a/arch/arm/mach-stm32mp/stm32image.c +++ b/arch/arm/mach-stm32mp/stm32image.c @@ -40,7 +40,7 @@ static int do_bootm_stm32image(struct image_data *data) static struct image_handler image_handler_stm32_image_v1_handler = { .name = "STM32 image (v1)", .bootm = do_bootm_stm32image, - .filetype = filetype_stm32_image_v1, + .filetype = filetype_stm32_image_ssbl_v1, }; static int stm32mp_register_stm32image_image_handler(void) |