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-rw-r--r--arch/blackfin/cpu-bf561/init_sdram.S53
1 files changed, 52 insertions, 1 deletions
diff --git a/arch/blackfin/cpu-bf561/init_sdram.S b/arch/blackfin/cpu-bf561/init_sdram.S
index f16bb28bad..84fda76bcd 100644
--- a/arch/blackfin/cpu-bf561/init_sdram.S
+++ b/arch/blackfin/cpu-bf561/init_sdram.S
@@ -27,7 +27,7 @@ init_sdram:
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
+ r0 = 0x640(Z);
w[p0] = r0.l;
ssync;
@@ -41,6 +41,44 @@ init_sdram:
[P2] = R0;
SSYNC;
+ /* Make sure PLL wakeup is enabled as BOOT ROM seems to disable
+ * it. (R7 and R6 used to store original value!)
+ */
+ p0.h = hi(SIC_IWR);
+ p0.l = lo(SIC_IWR);
+ r7 = [p0];
+ r0 = 1;
+ [p0] = r0;
+#ifdef SICA_IWR1
+ p0.h = hi(SICA_IWR1);
+ p0.l = lo(SICA_IWR1);
+ r6 = [p0];
+ r0 = 0;
+ [p0] = r0;
+#endif
+ ssync;
+
+#ifdef CONFIG_VSEL
+ /*
+ *
+ * Set Voltage Regulator.
+ */
+
+ p2.h = hi(VR_CTL);
+ p2.l = lo(VR_CTL);
+ r0 = w[p2];
+ r1 = ~0xf0;
+ r0 = r0 & r1;
+ r1 = CONFIG_VSEL & 0x0f;
+ r1 = r1 << 4;
+ r0 = r0 | r1;
+ cli r2;
+ ssync;
+ w[p2] = r0.l;
+ idle;
+ sti r2;
+#endif
+
/*
* Set PLL_CTL with the value that we calculate in R0
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
@@ -159,6 +197,19 @@ skip:
SSYNC;
nop;
+ /*
+ * Restore wakeup
+ */
+ p0.h = hi(SIC_IWR);
+ p0.l = lo(SIC_IWR);
+ [p0] = r7;
+#ifdef SICA_IWR1
+ p0.h = hi(SICA_IWR1);
+ p0.l = lo(SICA_IWR1);
+ [p0] = r6;
+#endif
+ ssync;
+
(P5:0) = [SP++];
(R7:0) = [SP++];
RETS = [SP++];