diff options
Diffstat (limited to 'arch/mips/lib/c-r4k.c')
| -rw-r--r-- | arch/mips/lib/c-r4k.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c index ba77d18e7c..150205840d 100644 --- a/arch/mips/lib/c-r4k.c +++ b/arch/mips/lib/c-r4k.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/io.h> #include <asm/mipsregs.h> +#include <asm/cache.h> #include <asm/cacheops.h> #include <asm/cpu.h> #include <asm/cpu-info.h> @@ -47,6 +48,29 @@ static inline void blast_##pfx##cache##_range(unsigned long start, \ __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D) __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D) +void flush_cache_all(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned long lsize; + unsigned long addr; + unsigned long aend; + unsigned int icache_size, dcache_size; + + dcache_size = c->dcache.waysize * c->dcache.ways; + lsize = c->dcache.linesz; + aend = (KSEG0 + dcache_size - 1) & ~(lsize - 1); + for (addr = KSEG0; addr <= aend; addr += lsize) + cache_op(Index_Writeback_Inv_D, addr); + + icache_size = c->icache.waysize * c->icache.ways; + lsize = c->icache.linesz; + aend = (KSEG0 + icache_size - 1) & ~(lsize - 1); + for (addr = KSEG0; addr <= aend; addr += lsize) + cache_op(Index_Invalidate_I, addr); + + /* secondatory cache skipped */ +} + void dma_flush_range(unsigned long start, unsigned long end) { blast_dcache_range(start, end); |