diff options
Diffstat (limited to 'arch/ppc/boards')
47 files changed, 0 insertions, 2772 deletions
diff --git a/arch/ppc/boards/.gitignore b/arch/ppc/boards/.gitignore deleted file mode 100644 index d1165788c9..0000000000 --- a/arch/ppc/boards/.gitignore +++ /dev/null @@ -1 +0,0 @@ -barebox.lds diff --git a/arch/ppc/boards/freescale-p1010rdb/Makefile b/arch/ppc/boards/freescale-p1010rdb/Makefile deleted file mode 100644 index a7b64eef4d..0000000000 --- a/arch/ppc/boards/freescale-p1010rdb/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -obj-y += p1010rdb.o -obj-y += law.o -obj-y += tlb.o -obj-y += ddr.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-freescale-p1010rdb diff --git a/arch/ppc/boards/freescale-p1010rdb/config.h b/arch/ppc/boards/freescale-p1010rdb/config.h deleted file mode 100644 index 4f67183507..0000000000 --- a/arch/ppc/boards/freescale-p1010rdb/config.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CFG_SYS_CLK_FREQ 66666666 -#define CFG_DDR_CLK_FREQ 66666666 - -#define CFG_CHIP_SELECTS_PER_CTRL 1 - -/* - * Memory map - * - * 0x0000_0000 0x3fff_ffff DDR 1G cacheable - * - * Localbus non-cacheable - * 0xee0_0000 0xefff_ffff FLASH 32M non-cacheable - * 0xffb0_0000 0xffb0_0fff PIXIS 4K Cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_CCSRBAR_DEFAULT 0xff700000 -#define CFG_CCSRBAR 0xffe00000 -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR -#define CFG_IMMR CFG_CCSRBAR - -#define CFG_INIT_RAM_ADDR 0xffd00000 -#define CFG_INIT_RAM_SIZE 0x00004000 -#define CFG_INIT_BI_SIZE 0x00000100 -#define CFG_INIT_SP_OFFSET (CFG_INIT_RAM_SIZE - CFG_INIT_BI_SIZE) - -#define CFG_BOOT_BLOCK 0xe0000000 -#define CFG_BOOT_BLOCK_PHYS CFG_BOOT_BLOCK -#define CFG_FLASH_BASE 0xee000000 -#define CFG_FLASH_BASE_PHYS CFG_FLASH_BASE -#define CFG_CPLD_BASE 0xffb00000 -#define CFG_CPLD_BASE_PHYS CFG_CPLD_BASE - -#define CFG_IFC_CSPR0 (CSPR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | CSPR_MSEL_NOR | \ - CSPR_V) -#define CFG_IFC_CSOR0 CSOR_NOR_ADM_SHIFT(7) -#define CFG_IFC_AMASK0 IFC_AMASK(32*1024*1024) - -#endif /* __CONFIG_H */ diff --git a/arch/ppc/boards/freescale-p1010rdb/ddr.c b/arch/ppc/boards/freescale-p1010rdb/ddr.c deleted file mode 100644 index 18069f4df1..0000000000 --- a/arch/ppc/boards/freescale-p1010rdb/ddr.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> - * Timur Tabi <timur@freescale.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <init.h> -#include <mach/fsl_i2c.h> -#include <mach/immap_85xx.h> -#include <mach/clock.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/fsl_lbc.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_ddr_dimm_params.h> -#include "p1010rdb.h" - -static const u8 spd_addr = 0x52; - -int fsl_ddr_board_info(struct ddr_board_info_s *info) -{ - p1010rdb_early_init(); - - info->fsl_ddr_ver = 0; - info->ddr_base = IOMEM(MPC85xx_DDR_ADDR); - /* Actual number of chip select used */ - info->cs_per_ctrl = CFG_CHIP_SELECTS_PER_CTRL; - info->dimm_slots_per_ctrl = 1; - info->i2c_bus = 1; - info->i2c_slave = 0x7f; - info->i2c_speed = 400000; - info->i2c_base = IOMEM(I2C2_BASE_ADDR); - info->spd_i2c_addr = &spd_addr; - - return 0; -} - -void fsl_ddr_board_options(struct memctl_options_s *popts, - struct dimm_params_s *pdimm) -{ - popts->cs_local_opts[0].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[0].odt_wr_cfg = FSL_DDR_ODT_CS; - popts->cs_local_opts[0].odt_rtt_norm = DDR3_RTT_40_OHM; - popts->cs_local_opts[0].odt_rtt_wr = DDR3_RTT_OFF; - - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - popts->dll_rst_dis = 1; -} diff --git a/arch/ppc/boards/freescale-p1010rdb/defaultenv-freescale-p1010rdb/bin/init b/arch/ppc/boards/freescale-p1010rdb/defaultenv-freescale-p1010rdb/bin/init deleted file mode 100644 index c0e04c1f2d..0000000000 --- a/arch/ppc/boards/freescale-p1010rdb/defaultenv-freescale-p1010rdb/bin/init +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -source /env/config diff --git a/arch/ppc/boards/freescale-p1010rdb/defaultenv-freescale-p1010rdb/config b/arch/ppc/boards/freescale-p1010rdb/defaultenv-freescale-p1010rdb/config deleted file mode 100644 index bffd86882e..0000000000 --- a/arch/ppc/boards/freescale-p1010rdb/defaultenv-freescale-p1010rdb/config +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -export bootargs="root=/dev/nfs rw ip=bootp console=ttyS0,115200"
\ No newline at end of file diff --git a/arch/ppc/boards/freescale-p1010rdb/law.c b/arch/ppc/boards/freescale-p1010rdb/law.c deleted file mode 100644 index 6edfbc2fb8..0000000000 --- a/arch/ppc/boards/freescale-p1010rdb/law.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <asm/fsl_law.h> - -struct law_entry law_table[] = { - FSL_SET_LAW(CFG_BOOT_BLOCK_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), - FSL_SET_LAW(CFG_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/arch/ppc/boards/freescale-p1010rdb/p1010rdb.c b/arch/ppc/boards/freescale-p1010rdb/p1010rdb.c deleted file mode 100644 index b163327597..0000000000 --- a/arch/ppc/boards/freescale-p1010rdb/p1010rdb.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright 2014 GE Intelligent Platforms, Inc. - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <platform_data/serial-ns16550.h> -#include <net.h> -#include <types.h> -#include <i2c/i2c.h> -#include <gpio.h> -#include <envfs.h> -#include <partition.h> -#include <memory.h> -#include <asm/cache.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_law.h> -#include <asm/fsl_ifc.h> -#include <mach/mpc85xx.h> -#include <mach/mmu.h> -#include <mach/immap_85xx.h> -#include <mach/gianfar.h> -#include <mach/clock.h> -#include <mach/early_udelay.h> -#include <of.h> - -static struct gfar_info_struct gfar_info[] = { - { - .phyaddr = 1, - .tbiana = 0, - .tbicr = 0, - .mdiobus_tbi = 0, - }, - { - .phyaddr = 0, - .tbiana = 0x1a0, - .tbicr = 0x9140, - .mdiobus_tbi = 1, - }, - { - .phyaddr = 2, - .tbiana = 0x1a0, - .tbicr = 0x9140, - .mdiobus_tbi = 2, - }, -}; - -struct i2c_platform_data i2cplat[] = { - { .bitrate = 400000, }, - { .bitrate = 400000, }, -}; - -void p1010rdb_early_init(void) -{ - void __iomem *ifc = IFC_BASE_ADDR; - void __iomem *gur = IOMEM(MPC85xx_GUTS_ADDR); - - /* Clock configuration to access CPLD using IFC(GPCM) */ - setbits_be32(ifc + FSL_IFC_GCR_OFFSET, - 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - - /* Erratum A003549 */ - setbits_be32(gur + MPC85xx_GUTS_PMUXCR_OFFSET, - MPC85xx_PMUXCR_LCLK_IFC_CS3); - - /* Update CS0 timings to access boot flash */ - set_ifc_ftim(IFC_CS0, IFC_FTIM0, FTIM0_NOR_TACSE(0x4) | - FTIM0_NOR_TEADC(0x5) | FTIM0_NOR_TEAHC(0x5)); - set_ifc_ftim(IFC_CS0, IFC_FTIM1, FTIM1_NOR_TACO(0x1e) | - FTIM1_NOR_TRAD_NOR(0x0f)); - set_ifc_ftim(IFC_CS0, IFC_FTIM2, FTIM2_NOR_TCS(0x4) | - FTIM2_NOR_TCH(0x4) | FTIM2_NOR_TWP(0x1c)); - set_ifc_ftim(IFC_CS0, IFC_FTIM3, 0); - - /* Map the CPLD */ - set_ifc_cspr(IFC_CS3, CSPR_PHYS_ADDR(CFG_CPLD_BASE_PHYS) | - CSPR_PORT_SIZE_8 | CSPR_MSEL_GPCM | CSPR_V); - set_ifc_csor(IFC_CS3, 0); - set_ifc_amask(IFC_CS3, IFC_AMASK(64*1024)); - set_ifc_ftim(IFC_CS3, IFC_FTIM0, FTIM0_GPCM_TACSE(0xe) | - FTIM0_GPCM_TEADC(0x0e) | FTIM0_GPCM_TEAHC(0x0e)); - set_ifc_ftim(IFC_CS3, IFC_FTIM1, FTIM1_GPCM_TACO(0x1e) | - FTIM1_GPCM_TRAD(0x0f)); - set_ifc_ftim(IFC_CS3, IFC_FTIM2, FTIM2_GPCM_TCS(0xe) | - FTIM2_GPCM_TCH(0) | FTIM2_GPCM_TWP(0x1f)); - set_ifc_ftim(IFC_CS3, IFC_FTIM3, 0); - - /* PCIe reset through GPIO 4 */ - gpio_direction_output(4, 1); -} - -static void board_eth_init(void) -{ - fsl_eth_init(1, &gfar_info[0]); - fsl_eth_init(2, &gfar_info[1]); - fsl_eth_init(3, &gfar_info[2]); -} - -static int p1010rdb_devices_init(void) -{ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 32 << 20, 0); - devfs_add_partition("nor0", 0x1f80000, 0x80000, DEVFS_PARTITION_FIXED, - "self0"); - devfs_add_partition("nor0", 0x1f60000, 0x10000, DEVFS_PARTITION_FIXED, - "env0"); - add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, 0x100, - IORESOURCE_MEM, &i2cplat[0]); - add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, 0x100, - IORESOURCE_MEM, &i2cplat[1]); - board_eth_init(); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_freescale_p1010rdb); - - return 0; -} - -device_initcall(p1010rdb_devices_init); - -static struct NS16550_plat serial_plat = { - .clock = 0, - .shift = 0, -}; - -static int p1010rdb_console_init(void) -{ - barebox_set_model("Freescale P1010RDB"); - barebox_set_hostname("p1010rdb"); - - serial_plat.clock = fsl_get_bus_freq(0); - add_ns16550_device(1, CFG_IMMR + 0x4500, 16, - IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat); - return 0; -} - -console_initcall(p1010rdb_console_init); - -static int p1010rdb_mem_init(void) -{ - barebox_add_memory_bank("ram0", 0x0, fsl_get_effective_memsize()); - return 0; -} - -mem_initcall(p1010rdb_mem_init); - -static int p1010rdb_board_init_r(void) -{ - const uint32_t flashbase = CFG_BOOT_BLOCK; - const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1); - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash */ - e500_disable_tlb(flash_esel); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - e500_set_tlb(1, flashbase, CFG_BOOT_BLOCK_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - fsl_l2_cache_init(); - - return 0; -} - -core_initcall(p1010rdb_board_init_r); - -static int fdt_board_setup(struct device_node *blob, void *unused) -{ - struct device_node *node; - - node = of_find_compatible_node(blob, NULL, "fsl,esdhc"); - if (node) - of_delete_node(node); - - node = of_find_compatible_node(blob, NULL, "fsl,starlite-tdm"); - if (node) - of_delete_node(node); - - node = of_find_compatible_node(blob, NULL, "fsl,p1010-flexcan"); - if (node) - of_delete_node(node); - - node = of_find_compatible_node(blob, NULL, "fsl,p1010-flexcan"); - if (node) - of_delete_node(node); - - return 0; -} - -static int of_register_p1010rdb_fixup(void) -{ - return of_register_fixup(fdt_board_setup, NULL); -} -late_initcall(of_register_p1010rdb_fixup); diff --git a/arch/ppc/boards/freescale-p1010rdb/p1010rdb.h b/arch/ppc/boards/freescale-p1010rdb/p1010rdb.h deleted file mode 100644 index f325ff48fd..0000000000 --- a/arch/ppc/boards/freescale-p1010rdb/p1010rdb.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2014 GE Intelligent Platforms, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -void p1010rdb_early_init(void); diff --git a/arch/ppc/boards/freescale-p1010rdb/tlb.c b/arch/ppc/boards/freescale-p1010rdb/tlb.c deleted file mode 100644 index 23ef0f2ade..0000000000 --- a/arch/ppc/boards/freescale-p1010rdb/tlb.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <mach/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (4 * 1024), - CFG_INIT_RAM_ADDR + (4 * 1024), - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (8 * 1024), - CFG_INIT_RAM_ADDR + (8 * 1024), - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (12 * 1024), - CFG_INIT_RAM_ADDR + (12 * 1024), - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - FSL_SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - FSL_SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* W**G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - FSL_SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK_PHYS, - MAS3_SX | MAS3_SR, MAS2_M | MAS2_W | MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - FSL_SET_TLB_ENTRY(1, CFG_CPLD_BASE, CFG_CPLD_BASE_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 6, BOOKE_PAGESZ_128K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/arch/ppc/boards/freescale-p1022ds/Makefile b/arch/ppc/boards/freescale-p1022ds/Makefile deleted file mode 100644 index 48867fa851..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -obj-y += p1022ds.o -obj-y += law.o -obj-y += tlb.o -obj-y += ddr.o -obj-y += ics307_clk.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-freescale-p1022ds diff --git a/arch/ppc/boards/freescale-p1022ds/config.h b/arch/ppc/boards/freescale-p1022ds/config.h deleted file mode 100644 index 666b9ff987..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/config.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -extern unsigned long ics307_clk_freq(unsigned int reg); -#endif -#define CFG_SYS_CLK_FREQ ics307_clk_freq(25) -#define CFG_DDR_CLK_FREQ ics307_clk_freq(28) - -#define CFG_CHIP_SELECTS_PER_CTRL 2 - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR 2G cacheable - * - * Localbus non-cacheable - * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xffdf_0000 0xffdf_0fff PIXIS 4K Cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_CCSRBAR_DEFAULT 0xff700000 -#define CFG_CCSRBAR 0xffe00000 -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR -#define CFG_IMMR CFG_CCSRBAR - -#define CFG_INIT_RAM_ADDR 0xffd00000 -#define CFG_INIT_RAM_SIZE 0x00004000 -#define CFG_INIT_BI_SIZE 0x00000100 -#define CFG_INIT_SP_OFFSET (CFG_INIT_RAM_SIZE - CFG_INIT_BI_SIZE) - -#define CFG_BOOT_BLOCK 0xe0000000 -#define CFG_BOOT_BLOCK_PHYS CFG_BOOT_BLOCK -#define CFG_FLASH_BASE 0xe8000000 -#define CFG_FLASH_BASE_PHYS CFG_FLASH_BASE -#define CFG_PIXIS_BASE 0xffdf0000 -#define CFG_PIXIS_BASE_PHYS CFG_PIXIS_BASE - -#endif /* __CONFIG_H */ diff --git a/arch/ppc/boards/freescale-p1022ds/ddr.c b/arch/ppc/boards/freescale-p1022ds/ddr.c deleted file mode 100644 index 1944518c79..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/ddr.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> - * Timur Tabi <timur@freescale.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <init.h> -#include <mach/fsl_i2c.h> -#include <mach/immap_85xx.h> -#include <mach/clock.h> -#include <asm/io.h> -#include <asm/fsl_lbc.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_ddr_dimm_params.h> -#include "p1022ds.h" - -static const u8 spd_addr = 0x51; - -int fsl_ddr_board_info(struct ddr_board_info_s *info) -{ - /* - * Early mapping is needed to access the clock - * parameters in the FPGA. - */ - p1022ds_lbc_early_init(); - - info->fsl_ddr_ver = 0; - info->ddr_base = IOMEM(MPC85xx_DDR_ADDR); - /* Actual number of chip select used */ - info->cs_per_ctrl = CFG_CHIP_SELECTS_PER_CTRL; - info->dimm_slots_per_ctrl = 1; - info->i2c_bus = 1; - info->i2c_slave = 0x7f; - info->i2c_speed = 400000; - info->i2c_base = IOMEM(I2C2_BASE_ADDR); - info->spd_i2c_addr = &spd_addr; - - return 0; -} - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; /* Range: 0-8 */ - u32 cpo; /* Range: 2-31 */ - u32 write_data_delay; /* Range: 0-6 */ - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters dimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - { 1, 549, 5, 31, 3, 0 }, - { 1, 850, 5, 31, 5, 0 }, - { 2, 549, 5, 31, 3, 0 }, - { 2, 850, 5, 31, 5, 0 }, - { } -}; - -void fsl_ddr_board_options(struct memctl_options_s *popts, - struct dimm_params_s *pdimm) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - unsigned long ddr_freq; - uint32_t i; - - for (i = 0; i < popts->board_info->cs_per_ctrl; i++) { - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 1; - popts->cs_local_opts[i].odt_rtt_wr = DDR3_RTT_OFF; - } - popts->cs_local_opts[0].odt_rtt_norm = DDR3_RTT_40_OHM; - popts->cs_local_opts[1].odt_rtt_norm = DDR3_RTT_OFF; - - pbsp = dimm0; - - ddr_freq = fsl_get_ddr_freq(0) / 1000000; - /* - * To have optimal parameters specific to the board, do a fine - * adjustment of DDR parameters depending on the DDR data rate. - */ - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - /* Use highest parameters if none were found */ - if (pbsp_highest) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2t; - } - -found: - popts->half_strength_driver_enable = 1; - - /* Per AN4039, enable ZQ calibration. */ - popts->zq_en = 1; - - popts->auto_self_refresh_en = 1; - popts->sr_it = 0xb; - - popts->dll_rst_dis = 1; -} diff --git a/arch/ppc/boards/freescale-p1022ds/defaultenv-freescale-p1022ds/bin/init b/arch/ppc/boards/freescale-p1022ds/defaultenv-freescale-p1022ds/bin/init deleted file mode 100644 index c0e04c1f2d..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/defaultenv-freescale-p1022ds/bin/init +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -source /env/config diff --git a/arch/ppc/boards/freescale-p1022ds/defaultenv-freescale-p1022ds/config b/arch/ppc/boards/freescale-p1022ds/defaultenv-freescale-p1022ds/config deleted file mode 100644 index bffd86882e..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/defaultenv-freescale-p1022ds/config +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -export bootargs="root=/dev/nfs rw ip=bootp console=ttyS0,115200"
\ No newline at end of file diff --git a/arch/ppc/boards/freescale-p1022ds/ics307_clk.c b/arch/ppc/boards/freescale-p1022ds/ics307_clk.c deleted file mode 100644 index f7c5bbde99..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/ics307_clk.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> - -/* decode S[0-2] to Output Divider (OD) */ -static u8 ics307_s_to_od[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* Calculate frequency being generated by ICS307-02 clock chip. */ -unsigned long ics307_clk_freq(unsigned int reg) -{ - const unsigned long input_freq = 33333000; - void __iomem *fpga_base = IOMEM(CFG_PIXIS_BASE); - unsigned char cw0, cw1, cw2; - unsigned long vdw, rdw, od, freq; - - cw0 = in_8(fpga_base + reg); - cw1 = in_8(fpga_base + reg + 1); - cw2 = in_8(fpga_base + reg + 2); - vdw = ((cw1 << 1) & 0x1fe) + ((cw2 >> 7) & 1); - rdw = cw2 & 0x7f; - od = ics307_s_to_od[cw0 & 0x7]; - /* - * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD) - * - * cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for crystal - */ - freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od); - - return freq; -} diff --git a/arch/ppc/boards/freescale-p1022ds/law.c b/arch/ppc/boards/freescale-p1022ds/law.c deleted file mode 100644 index 167937a05a..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/law.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <asm/fsl_law.h> - -struct law_entry law_table[] = { - FSL_SET_LAW(CFG_BOOT_BLOCK_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - FSL_SET_LAW(CFG_PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/arch/ppc/boards/freescale-p1022ds/p1022ds.c b/arch/ppc/boards/freescale-p1022ds/p1022ds.c deleted file mode 100644 index d80c234ea9..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/p1022ds.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright 2014 GE Intelligent Platforms, Inc. - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <platform_data/serial-ns16550.h> -#include <net.h> -#include <types.h> -#include <i2c/i2c.h> -#include <partition.h> -#include <memory.h> -#include <envfs.h> -#include <asm/cache.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_law.h> -#include <mach/mpc85xx.h> -#include <mach/mmu.h> -#include <mach/immap_85xx.h> -#include <mach/gianfar.h> -#include <mach/clock.h> -#include <mach/early_udelay.h> - -/* Define attributes for eTSEC1 and eTSEC2 */ -static struct gfar_info_struct gfar_info[] = { - { - .phyaddr = 1, - .tbiana = 0, - .tbicr = 0, - .mdiobus_tbi = 0, - }, - { - .phyaddr = 2, - .tbiana = 0, - .tbicr = 0, - .mdiobus_tbi = 0, - }, -}; - -struct i2c_platform_data i2cplat[] = { - { .bitrate = 400000, }, - { .bitrate = 400000, }, -}; - -void p1022ds_lbc_early_init(void) -{ - void __iomem *gur = IOMEM(MPC85xx_GUTS_ADDR); - void __iomem *lbc = LBC_BASE_ADDR; - - /* Set the local bus monitor timeout value to the maximum */ - clrsetbits_be32(lbc + FSL_LBC_LBCR_OFFSET, 0xff0f, 0xf); - /* Set the pin muxing to enable ETSEC2. */ - clrbits_be32(gur + MPC85xx_GUTS_PMUXCR2_OFFSET, 0x001f8000); - /* Set pmuxcr to allow both i2c1 and i2c2 */ - setbits_be32(gur + MPC85xx_GUTS_PMUXCR_OFFSET, 0x1000); - - /* Map the boot flash and FPGA */ - fsl_set_lbc_br(0, BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | BR_PS_16 | BR_V); - fsl_set_lbc_or(0, 0xf8000ff7); - fsl_set_lbc_br(2, BR_PHYS_ADDR(CFG_PIXIS_BASE_PHYS) | BR_PS_8 | BR_V); - fsl_set_lbc_or(2, 0xffff8ff7); -} - -static void board_eth_init(void) -{ - struct i2c_adapter *adapter; - struct i2c_client client; - char mac[6]; - int ret, ix; - - adapter = i2c_get_adapter(1); - client.addr = 0x57; - client.adapter = adapter; - - for (ix = 0; ix < 2; ix++) { - int mac_offset; - - mac_offset = 0x42 + (sizeof(mac) * ix); - ret = i2c_read_reg(&client, mac_offset, mac, sizeof(mac)); - if (ret != sizeof(mac)) - pr_err("Fail to retrieve MAC address\n"); - else - eth_register_ethaddr(ix, mac); - } - - fsl_eth_init(1, &gfar_info[0]); - fsl_eth_init(2, &gfar_info[1]); -} - -static int p1022ds_devices_init(void) -{ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 128 << 20, 0); - devfs_add_partition("nor0", 0x7f80000, 0x80000, DEVFS_PARTITION_FIXED, - "self0"); - devfs_add_partition("nor0", 0x7f00000, 0x10000, DEVFS_PARTITION_FIXED, - "env0"); - add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, 0x100, - IORESOURCE_MEM, &i2cplat[0]); - add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, 0x100, - IORESOURCE_MEM, &i2cplat[1]); - - board_eth_init(); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_freescale_p1022ds); - - return 0; -} - -device_initcall(p1022ds_devices_init); - -static struct NS16550_plat serial_plat = { - .clock = 0, - .shift = 0, -}; - -static int p1022ds_console_init(void) -{ - barebox_set_model("Freescale P1022DS"); - barebox_set_hostname("p1022ds"); - - serial_plat.clock = fsl_get_bus_freq(0); - add_ns16550_device(DEVICE_ID_DYNAMIC, CFG_IMMR + 0x4500, 16, - IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat); - return 0; -} - -console_initcall(p1022ds_console_init); - -static int p1022ds_mem_init(void) -{ - barebox_add_memory_bank("ram0", 0x0, fsl_get_effective_memsize()); - return 0; -} - -mem_initcall(p1022ds_mem_init); - -static int p1022ds_board_init_r(void) -{ - void __iomem *fpga = IOMEM(CFG_PIXIS_BASE); - const uint32_t flashbase = CFG_BOOT_BLOCK; - const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1); - - /* Enable SPI */ - out_8(fpga + 8, (in_8(fpga + 8) & ~(0xc0)) | (0x80)); - - /* Map the NAND flash */ - fsl_set_lbc_br(1, BR_PHYS_ADDR(0xff800000) | BR_PS_8 | - (2 << BR_DECC_SHIFT) | BR_MS_FCM | BR_V); - fsl_set_lbc_or(1, 0xffff8796); - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash */ - e500_disable_tlb(flash_esel); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - e500_set_tlb(1, flashbase, CFG_BOOT_BLOCK_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - fsl_l2_cache_init(); - - return 0; -} - -core_initcall(p1022ds_board_init_r); diff --git a/arch/ppc/boards/freescale-p1022ds/p1022ds.h b/arch/ppc/boards/freescale-p1022ds/p1022ds.h deleted file mode 100644 index cbc2aca644..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/p1022ds.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2014 GE Intelligent Platforms, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -void p1022ds_lbc_early_init(void); diff --git a/arch/ppc/boards/freescale-p1022ds/tlb.c b/arch/ppc/boards/freescale-p1022ds/tlb.c deleted file mode 100644 index 86ab43aec0..0000000000 --- a/arch/ppc/boards/freescale-p1022ds/tlb.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <mach/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (4 * 1024), - CFG_INIT_RAM_ADDR + (4 * 1024), - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (8 * 1024), - CFG_INIT_RAM_ADDR + (8 * 1024), - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (12 * 1024), - CFG_INIT_RAM_ADDR + (12 * 1024), - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - FSL_SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - FSL_SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - FSL_SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK_PHYS, - MAS3_SX | MAS3_SR, MAS2_M | MAS2_W | MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - FSL_SET_TLB_ENTRY(1, CFG_PIXIS_BASE, CFG_PIXIS_BASE_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 7, BOOKE_PAGESZ_4K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/arch/ppc/boards/freescale-p2020rdb/Makefile b/arch/ppc/boards/freescale-p2020rdb/Makefile deleted file mode 100644 index b2497f695c..0000000000 --- a/arch/ppc/boards/freescale-p2020rdb/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -obj-y += p2020rdb.o -obj-y += law.o -obj-y += tlb.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-freescale-p2020rdb diff --git a/arch/ppc/boards/freescale-p2020rdb/config.h b/arch/ppc/boards/freescale-p2020rdb/config.h deleted file mode 100644 index e607ee7b46..0000000000 --- a/arch/ppc/boards/freescale-p2020rdb/config.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright 2012 GE Intelligent Platforms, Inc. - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -/* - * P2020RDB board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CFG_SYS_CLK_FREQ get_board_sys_clk(0) -#define CFG_DDR_CLK_FREQ 66666666 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 - -#define CFG_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR - -#define CFG_IMMR CFG_CCSRBAR - -/* DDR Setup */ - -#define CFG_CHIP_SELECTS_PER_CTRL 1 - -#define CFG_SDRAM_BASE 0x00000000 - -/* These timings are adjusted for a 667Mhz clock. */ -#define CFG_SYS_DDR_CS0_BNDS 0x0000003f /* 1GB */ -#define CFG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CFG_SYS_DDR_TIMING_3 0x00030000 -#define CFG_SYS_DDR_TIMING_0 0x55770802 -#define CFG_SYS_DDR_TIMING_1 0x5f599543 -#define CFG_SYS_DDR_TIMING_2 0x0fa074d1 - -#define CFG_SYS_DDR_CONTROL 0xc3000000 -#define CFG_SYS_DDR_CONTROL2 0x24401000 -#define CFG_SYS_DDR_MODE_1 0x00040852 -#define CFG_SYS_DDR_MODE_2 0x00000000 -#define CFG_SYS_MD_CNTL 0x00000000 -#define CFG_SYS_DDR_INTERVAL 0x0a280100 - -#define CFG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CFG_SYS_DDR_CLK_CTRL 0x03000000 - -/* - * Memory map - * - * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen - * - * Localbus non-cacheable - * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - */ - -/* - * Local Bus Definitions - */ -#define CFG_FLASH_BASE 0xef000000 -#define CFG_FLASH_BASE_PHYS CFG_FLASH_BASE - -#define CFG_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -/* Leave 256 bytes for global data */ -#define CFG_INIT_SP_OFFSET (0x00004000 - 256) - -#endif /* __CONFIG_H */ diff --git a/arch/ppc/boards/freescale-p2020rdb/defaultenv-freescale-p2020rdb/bin/init b/arch/ppc/boards/freescale-p2020rdb/defaultenv-freescale-p2020rdb/bin/init deleted file mode 100644 index 4d7b03e26d..0000000000 --- a/arch/ppc/boards/freescale-p2020rdb/defaultenv-freescale-p2020rdb/bin/init +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -source /env/config
\ No newline at end of file diff --git a/arch/ppc/boards/freescale-p2020rdb/defaultenv-freescale-p2020rdb/config b/arch/ppc/boards/freescale-p2020rdb/defaultenv-freescale-p2020rdb/config deleted file mode 100644 index 23e0ba2a5d..0000000000 --- a/arch/ppc/boards/freescale-p2020rdb/defaultenv-freescale-p2020rdb/config +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -export bootargs="root=/dev/nfs rw ip=bootp"
\ No newline at end of file diff --git a/arch/ppc/boards/freescale-p2020rdb/law.c b/arch/ppc/boards/freescale-p2020rdb/law.c deleted file mode 100644 index 420a69eeec..0000000000 --- a/arch/ppc/boards/freescale-p2020rdb/law.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - FSL_SET_LAW(CFG_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c deleted file mode 100644 index 555976578e..0000000000 --- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright 2012 GE Intelligent Platforms, Inc. - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <platform_data/serial-ns16550.h> -#include <types.h> -#include <i2c/i2c.h> -#include <partition.h> -#include <memory.h> -#include <envfs.h> -#include <asm/cache.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_law.h> -#include <mach/mpc85xx.h> -#include <mach/mmu.h> -#include <mach/immap_85xx.h> -#include <mach/gianfar.h> -#include <mach/clock.h> -#include <mach/early_udelay.h> - -#define VSC7385_RST_SET 0x00080000 -#define SLIC_RST_SET 0x00040000 -#define SGMII_PHY_RST_SET 0x00020000 -#define PCIE_RST_SET 0x00010000 -#define RGMII_PHY_RST_SET 0x02000000 - -#define USB_RST_CLR 0x04000000 - -#define GPIO_DIR 0x060f0000 - -#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \ - SGMII_PHY_RST_SET | PCIE_RST_SET | \ - RGMII_PHY_RST_SET) - -#define SYSCLK_MASK 0x00200000 -#define BOARDREV_MASK 0x10100000 -#define BOARDREV_B 0x10100000 -#define BOARDREV_C 0x00100000 -#define BOARDREV_D 0x00000000 - -#define SYSCLK_66 66666666 -#define SYSCLK_50 50000000 -#define SYSCLK_100 100000000 - -/* Define attributes for eTSEC2 and eTSEC3 */ -static struct gfar_info_struct gfar_info[] = { - { - .phyaddr = 0, - .tbiana = 0x1a0, - .tbicr = 0x9140, - .mdiobus_tbi = 1, - }, - { - .phyaddr = 1, - .tbiana = 0, - .tbicr = 0, - .mdiobus_tbi = 2, - }, -}; - -/* I2C busses. */ -struct i2c_platform_data i2cplat = { - .bitrate = 400000, -}; - -static int devices_init(void) -{ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 16 << 20, 0); - devfs_add_partition("nor0", 0xf60000, 0x8000, DEVFS_PARTITION_FIXED, - "env0"); - devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED, - "self0"); - add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, - 0x100, IORESOURCE_MEM, &i2cplat); - add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, - 0x100, IORESOURCE_MEM, &i2cplat); - - fsl_eth_init(2, &gfar_info[0]); - fsl_eth_init(3, &gfar_info[1]); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_freescale_p2020rdb); - - return 0; -} - -device_initcall(devices_init); - -static struct NS16550_plat serial_plat = { - .clock = 0, - .shift = 0, -}; - -static int p2020_console_init(void) -{ - barebox_set_model("Freescale P2020RDB"); - barebox_set_hostname("p2020rdb"); - - serial_plat.clock = fsl_get_bus_freq(0); - - add_ns16550_device(DEVICE_ID_DYNAMIC, 0xffe04500, 16, - IORESOURCE_MEM | IORESOURCE_MEM_8BIT, - &serial_plat); - return 0; -} - -console_initcall(p2020_console_init); - -static int mem_init(void) -{ - barebox_add_memory_bank("ram0", 0x0, 1024 << 20); - - return 0; -} -mem_initcall(mem_init); - -/* - * fixed_sdram: fixed sdram settings. - */ -phys_size_t fixed_sdram(void) -{ - void __iomem *regs = (void __iomem *)(MPC85xx_DDR_ADDR); - int sdram_cfg = (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR2); - phys_size_t dram_size; - - /* If already enabled (running from RAM), get out */ - if (in_be32(regs + DDR_OFF(SDRAM_CFG)) & SDRAM_CFG_MEM_EN) - return fsl_get_effective_memsize(); - - out_be32(regs + DDR_OFF(CS0_BNDS), CFG_SYS_DDR_CS0_BNDS); - out_be32(regs + DDR_OFF(CS0_CONFIG), CFG_SYS_DDR_CS0_CONFIG); - out_be32(regs + DDR_OFF(TIMING_CFG_3), CFG_SYS_DDR_TIMING_3); - out_be32(regs + DDR_OFF(TIMING_CFG_0), CFG_SYS_DDR_TIMING_0); - out_be32(regs + DDR_OFF(TIMING_CFG_1), CFG_SYS_DDR_TIMING_1); - out_be32(regs + DDR_OFF(TIMING_CFG_2), CFG_SYS_DDR_TIMING_2); - out_be32(regs + DDR_OFF(SDRAM_CFG_2), CFG_SYS_DDR_CONTROL2); - out_be32(regs + DDR_OFF(SDRAM_MODE), CFG_SYS_DDR_MODE_1); - out_be32(regs + DDR_OFF(SDRAM_MODE_2), CFG_SYS_DDR_MODE_2); - out_be32(regs + DDR_OFF(SDRAM_MD_CNTL), CFG_SYS_MD_CNTL); - /* Basic refresh rate (7.8us),high temp is 3.9us */ - out_be32(regs + DDR_OFF(SDRAM_INTERVAL), - CFG_SYS_DDR_INTERVAL); - out_be32(regs + DDR_OFF(SDRAM_DATA_INIT), - CFG_SYS_DDR_DATA_INIT); - out_be32(regs + DDR_OFF(SDRAM_CLK_CNTL), - CFG_SYS_DDR_CLK_CTRL); - - out_be32(regs + DDR_OFF(SDRAM_INIT_ADDR), 0); - out_be32(regs + DDR_OFF(SDRAM_INIT_ADDR_EXT), 0); - /* - * Wait 200us for the DDR clock to stabilize. - */ - early_udelay(200); - asm volatile ("sync;isync"); - - out_be32(regs + DDR_OFF(SDRAM_CFG), sdram_cfg); - - dram_size = fsl_get_effective_memsize(); - if (fsl_set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR) < 0) - return 0; - - return dram_size; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - u32 val_gpdat, sysclk_gpio, board_rev_gpio; - void __iomem *gpio_regs = (void __iomem *)MPC85xx_GPIO_ADDR; - - val_gpdat = in_be32(gpio_regs + MPC85xx_GPIO_GPDAT); - sysclk_gpio = val_gpdat & SYSCLK_MASK; - board_rev_gpio = val_gpdat & BOARDREV_MASK; - - if (board_rev_gpio == BOARDREV_C) { - if (sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - } else if (board_rev_gpio == BOARDREV_B) { - if (sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_50; - } else if (board_rev_gpio == BOARDREV_D) { - if (sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - } - return 0; -} - -static void checkboard(void) -{ - u32 val_gpdat, board_rev_gpio; - void __iomem *gpio_regs = (void __iomem *)MPC85xx_GPIO_ADDR; - - val_gpdat = in_be32(gpio_regs + MPC85xx_GPIO_GPDAT); - board_rev_gpio = val_gpdat & BOARDREV_MASK; - - if ((board_rev_gpio != BOARDREV_C) && (board_rev_gpio != BOARDREV_B) && - (board_rev_gpio != BOARDREV_D)) - panic("Unexpected Board REV %x detected!!\n", board_rev_gpio); - - setbits_be32((gpio_regs + MPC85xx_GPIO_GPDIR), GPIO_DIR); - - /* - * Bringing the following peripherals out of reset via GPIOs - * 0 = reset and 1 = out of reset - * GPIO12 - Reset to Ethernet Switch - * GPIO13 - Reset to SLIC/SLAC devices - * GPIO14 - Reset to SGMII_PHY_N - * GPIO15 - Reset to PCIe slots - * GPIO6 - Reset to RGMII PHY - * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset - */ - clrsetbits_be32((gpio_regs + MPC85xx_GPIO_GPDAT), USB_RST_CLR, - BOARD_PERI_RST_SET); -} - -static int board_init_r(void) -{ - const unsigned int flashbase = CFG_FLASH_BASE; - const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1); - - checkboard(); - - /* Map the whole boot flash */ - fsl_set_lbc_br(0, BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | BR_PS_16 | BR_V); - fsl_set_lbc_or(0, 0xff000ff7); - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash */ - e500_disable_tlb(flash_esel); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - e500_set_tlb(1, flashbase, CFG_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_16M, 1); - - fsl_l2_cache_init(); - - return 0; -} -core_initcall(board_init_r); diff --git a/arch/ppc/boards/freescale-p2020rdb/tlb.c b/arch/ppc/boards/freescale-p2020rdb/tlb.c deleted file mode 100644 index 9853673ff2..0000000000 --- a/arch/ppc/boards/freescale-p2020rdb/tlb.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <mach/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (4 * 1024), - CFG_INIT_RAM_ADDR + (4 * 1024), - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (8 * 1024), - CFG_INIT_RAM_ADDR + (8 * 1024), - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (12 * 1024), - CFG_INIT_RAM_ADDR + (12 * 1024), - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - FSL_SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - FSL_SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - FSL_SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_16M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/arch/ppc/boards/owc-da923rc/Makefile b/arch/ppc/boards/owc-da923rc/Makefile deleted file mode 100644 index 4cf6c5cf3c..0000000000 --- a/arch/ppc/boards/owc-da923rc/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -obj-y += da923rc.o -obj-y += tlb.o -obj-y += law.o -obj-y += ddr.o -obj-y += nand.o -obj-y += product_data.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-owc-da923rc diff --git a/arch/ppc/boards/owc-da923rc/config.h b/arch/ppc/boards/owc-da923rc/config.h deleted file mode 100644 index 3895324e95..0000000000 --- a/arch/ppc/boards/owc-da923rc/config.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2013 GE Intelligent Platforms, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * DA923RC board configuration file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CFG_SYS_CLK_FREQ 66666666 - -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CFG_CHIP_SELECTS_PER_CTRL 1 - -/* - * Memory map - * - * 0x0000_0000 0x1fff_ffff DDR 512MB Cacheable - * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable - * 0xf400_0000 0xf400_3fff L1 for stack 4K Cacheable TLB0 - * - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_CCSRBAR_DEFAULT 0xff700000 -#define CFG_CCSRBAR 0xe0000000 -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR -#define CFG_IMMR CFG_CCSRBAR - -/* Initial memory for global storage and stack. */ -#define CFG_INIT_RAM_ADDR 0xf4000000 -#define CFG_INIT_RAM_SIZE 0x00004000 -#define CFG_INIT_BI_SIZE 0x100 -#define CFG_INIT_SP_OFFSET (CFG_INIT_RAM_SIZE - CFG_INIT_BI_SIZE) - -#define BOOT_BLOCK 0xfc000000 - -#define BOARD_TYPE_UNKNOWN -1 -#define BOARD_TYPE_NONE 0 -#define BOARD_TYPE_DA923 1 -#define BOARD_TYPE_GBX460 2 - -#endif /* __CONFIG_H */ diff --git a/arch/ppc/boards/owc-da923rc/da923rc.c b/arch/ppc/boards/owc-da923rc/da923rc.c deleted file mode 100644 index 2665a15091..0000000000 --- a/arch/ppc/boards/owc-da923rc/da923rc.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright 2013 GE Intelligent Platforms, Inc. - * Copyright 2019 Abaco Systems, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Abaco Systems DA923RC/GBX460 board support. - */ - -#include <common.h> -#include <console.h> -#include <init.h> -#include <memory.h> -#include <driver.h> -#include <asm/io.h> -#include <net.h> -#include <gpio.h> -#include <envfs.h> -#include <platform_data/serial-ns16550.h> -#include <partition.h> -#include <environment.h> -#include <i2c/i2c.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/cache.h> -#include <mach/mmu.h> -#include <mach/mpc85xx.h> -#include <mach/immap_85xx.h> -#include <mach/gianfar.h> -#include <mach/gpio.h> -#include <mach/clock.h> -#include <mach/fsl_i2c.h> -#include "product_data.h" - -static struct gfar_info_struct gfar_info[] = { - { - .phyaddr = 7, - .tbiana = 0, - .tbicr = 0, - .mdiobus_tbi = 0, - }, -}; - -struct i2c_platform_data i2cplat[] = { - { - .bitrate = 400000, - }, - { - .bitrate = 400000, - }, -}; - -static struct board_info binfo; - -static int board_eth_init(void) -{ - void __iomem *gur = IOMEM(MPC85xx_GUTS_ADDR); - struct owc_product_data product; - int st; - - /* Toggle eth0 reset pin */ - gpio_set_value(4, 0); - udelay(5); - gpio_set_value(4, 1); - - /* Disable eTSEC3 */ - out_be32(gur + MPC85xx_DEVDISR_OFFSET, - in_be32(gur + MPC85xx_DEVDISR_OFFSET) & - ~MPC85xx_DEVDISR_TSEC3); - - st = owc_get_product_data(&product); - if (((product.v2.mac.count > 0) && (product.v2.mac.count <= MAX_MAC)) - && (st == 0)) - eth_register_ethaddr(0, (const char *)&product.v2.mac.mac[0]); - - fsl_eth_init(1, &gfar_info[0]); - - return 0; -} - -static int da923rc_devices_init(void) -{ - add_cfi_flash_device(0, 0xfe000000, 32 << 20, 0); - devfs_add_partition("nor0", 0x0, 0x8000, DEVFS_PARTITION_FIXED, "env0"); - devfs_add_partition("nor0", 0x1f80000, 8 << 16, DEVFS_PARTITION_FIXED, - "self0"); - add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, 0x100, - IORESOURCE_MEM, &i2cplat[0]); - add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, 0x100, - IORESOURCE_MEM, &i2cplat[1]); - - board_eth_init(); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_owc_da923rc); - - return 0; -} - -device_initcall(da923rc_devices_init); - -static struct NS16550_plat serial_plat = { - .clock = 0, - .shift = 0, -}; - -static int da923rc_console_init(void) -{ - if (binfo.bid == BOARD_TYPE_DA923) - barebox_set_model("DA923RC"); - else if (binfo.bid == BOARD_TYPE_GBX460) - barebox_set_model("GBX460"); - else - barebox_set_model("unknown"); - - serial_plat.clock = fsl_get_bus_freq(0); - add_ns16550_device(1, CFG_CCSRBAR + 0x4600, 16, - IORESOURCE_MEM | IORESOURCE_MEM_8BIT, - &serial_plat); - return 0; -} - -console_initcall(da923rc_console_init); - -static int da923rc_mem_init(void) -{ - barebox_add_memory_bank("ram0", 0x0, fsl_get_effective_memsize()); - return 0; -} - -mem_initcall(da923rc_mem_init); - -static int da923rc_board_init_r(void) -{ - void __iomem *lbc = LBC_BASE_ADDR; - void __iomem *ecm = IOMEM(MPC85xx_ECM_ADDR); - void __iomem *pci = IOMEM(PCI1_BASE_ADDR); - const unsigned int flashbase = (BOOT_BLOCK + 0x2000000); - uint8_t flash_esel; - - da923rc_boardinfo_get(&binfo); - - flush_dcache(); - invalidate_icache(); - - /* Clear LBC error interrupts */ - out_be32(lbc + FSL_LBC_LTESR_OFFSET, 0xffffffff); - /* Enable LBC error interrupts */ - out_be32(lbc + FSL_LBC_LTEIR_OFFSET, 0xffffffff); - /* Clear ecm errors */ - out_be32(ecm + MPC85xx_ECM_EEDR_OFFSET, 0xffffffff); - /* Enable ecm errors */ - out_be32(ecm + MPC85xx_ECM_EEER_OFFSET, 0xffffffff); - - /* Re-map boot flash */ - fsl_set_lbc_br(0, BR_PHYS_ADDR(0xfe000000) | BR_PS_16 | BR_V); - fsl_set_lbc_or(0, 0xfe006e21); - - /* Invalidate TLB entry for boot block */ - flash_esel = e500_find_tlb_idx((void *)flashbase, 1); - e500_disable_tlb(flash_esel); - flash_esel = e500_find_tlb_idx((void *)(flashbase + 0x1000000), 1); - e500_disable_tlb(flash_esel); - - /* Boot block back to cache inhibited. */ - e500_set_tlb(1, BOOT_BLOCK + (2 * 0x1000000), - BOOT_BLOCK + (2 * 0x1000000), - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G | MAS2_M, - 0, 2, BOOKE_PAGESZ_16M, 1); - e500_set_tlb(1, BOOT_BLOCK + (3 * 0x1000000), - BOOT_BLOCK + (3 * 0x1000000), - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G | MAS2_M, - 0, 3, BOOKE_PAGESZ_16M, 1); - - fsl_l2_cache_init(); - - fsl_enable_gpiout(); - /* Enable NOR low voltage programming (gpio 2) and write (gpio 3). */ - gpio_set_value(2, 1); - gpio_set_value(3, 1); - - /* Enable write to NAND flash */ - if (binfo.bid == BOARD_TYPE_GBX460) { - /* Map CPLD */ - fsl_set_lbc_br(3, BR_PHYS_ADDR(0xfc010000) | BR_PS_16 | BR_V); - fsl_set_lbc_or(3, 0xffffe001); - /* Enable all reset */ - out_be16(IOMEM(0xfc010044), 0xffff); - gpio_set_value(6, 1); - } - - /* Board reset and PHY reset. Disable CS3. */ - if (binfo.bid == BOARD_TYPE_DA923) { - gpio_set_value(0, 0); - gpio_set_value(1, 1); - /* De-assert Board reset */ - udelay(1000); - gpio_set_value(0, 1); - } - - /* Enable PCI error reporting */ - out_be32(pci + 0xe00, 0x80000040); - out_be32(pci + 0xe08, 0x6bf); - out_be32(pci + 0xe0c, 0xbb1fa001); - /* 32-bytes cacheline size */ - out_be32(pci, 0x8000000c); - out_le32(pci + 4, 0x00008008); - - return 0; -} - -postcore_initcall(da923rc_board_init_r); diff --git a/arch/ppc/boards/owc-da923rc/ddr.c b/arch/ppc/boards/owc-da923rc/ddr.c deleted file mode 100644 index fc0c50cdcd..0000000000 --- a/arch/ppc/boards/owc-da923rc/ddr.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright 2013 GE Intelligent Platforms, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Board specific DDR tuning. - */ - -#include <common.h> -#include <mach/fsl_i2c.h> -#include <mach/immap_85xx.h> -#include <mach/clock.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_ddr_dimm_params.h> -#include "product_data.h" - -static struct board_info *binfo = - (struct board_info *)(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_SIZE - - sizeof(struct board_info)); - -static u8 spd_addr = 0x50; - -static int da923rc_boardinfo_init(void) -{ - void __iomem *i2c = IOMEM(I2C1_BASE_ADDR); - uint8_t id; - int ret; - - memset(binfo, 0, sizeof(struct board_info)); - - binfo->bid = BOARD_TYPE_UNKNOWN; - /* Read made from flash, use the DDR I2C API. */ - fsl_i2c_init(i2c, 400000, 0x7f); - /* Read board id from offset 0. */ - ret = fsl_i2c_read(i2c, 0x3b, 0, 1, &id, sizeof(uint8_t)); - fsl_i2c_stop(i2c); - - if (ret == 0) { - /* - * Board ID: - * 0-2 Hardware board - * revision - * 3-5 Board ID - * 000b/010b/100b - DA923, 001 - GBX460 - * 6-7 Undefined 00 - */ - binfo->rev = id & 7; - id &= 0x38; - id >>= 3; - switch (id) { - case 0: - case 2: - case 4: - binfo->bid = BOARD_TYPE_DA923; - break; - case 1: - binfo->bid = BOARD_TYPE_GBX460; - break; - default: - binfo->bid = BOARD_TYPE_NONE; - } - } - - return ret; -} - -void da923rc_boardinfo_get(struct board_info *bi) -{ - memcpy(bi, binfo, sizeof(struct board_info)); -} - -void fsl_ddr_board_info(struct ddr_board_info_s *info) -{ - info->fsl_ddr_ver = 0; - info->ddr_base = IOMEM(MPC85xx_DDR_ADDR); - /* Actual number of chip select used */ - info->cs_per_ctrl = 1; - info->dimm_slots_per_ctrl = 1; - info->i2c_bus = 0; - info->i2c_slave = 0x7f; - info->i2c_speed = 400000; - info->i2c_base = IOMEM(I2C1_BASE_ADDR); - info->spd_i2c_addr = &spd_addr; -} - -void fsl_ddr_board_options(struct memctl_options_s *popts, - struct dimm_params_s *pdimm) -{ - da923rc_boardinfo_init(); - - /* - * Clock adjustment in 1/8-cycle - * 0 = Clock is launched aligned with address/command - * ... - * 6 = 3/4 cycle late - * 7 = 7/8 cycle late - * 8 = 1 cycle late - */ - popts->clk_adjust = 8; - - /* - * /MCAS-to-preamble override. Defines the number of DRAM cycles - * between when a read is issued and when the corresponding DQS - * preamble is valid for the memory controller. - * - * Factors to consider for CPO: - * - frequency - * - ddr type - */ - popts->cpo_override = 9; - - /* - * Write command to write data strobe timing adjustment. - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing disabled. */ - popts->twoT_en = 0; - if (pdimm->registered_dimm != 0) - hang(); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - - /* Enable additive latency override. */ - popts->additive_latency_override = 1; - popts->additive_latency_override_value = 1; - - /* 50000ps is valid for a 16-bit wide data bus */ - popts->tFAW_window_four_activates_ps = 50000; - - /* Allow ECC */ - popts->ECC_mode = 1; - popts->data_init = 0; - - /* DLL reset disable */ - popts->dll_rst_dis = 1; - - /* Powerdown timings in number of tCK. */ - popts->txard = 2; - popts->txp = 2; - popts->taxpd = 8; - - /* Load mode timing in number of tCK. */ - popts->tmrd = 2; - - /* Assert ODT only during writes to CSn */ - popts->cs_local_opts[0].odt_wr_cfg = FSL_DDR_ODT_CS; -} diff --git a/arch/ppc/boards/owc-da923rc/defaultenv-owc-da923rc/bin/boot b/arch/ppc/boards/owc-da923rc/defaultenv-owc-da923rc/bin/boot deleted file mode 100644 index ce7da18e63..0000000000 --- a/arch/ppc/boards/owc-da923rc/defaultenv-owc-da923rc/bin/boot +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/sh -#Load the firmware images from the NOR UBIFS file system and boot - -readlink /mnt/active symlink - -bootargs="ubi.mtd=nand root=ubi0:fs-active rootfstype=ubifs rw panic=25" -cp /mnt/$symlink/uImage / -cp /mnt/$symlink/dtb / -bootm -o /dtb /uImage
\ No newline at end of file diff --git a/arch/ppc/boards/owc-da923rc/defaultenv-owc-da923rc/bin/init b/arch/ppc/boards/owc-da923rc/defaultenv-owc-da923rc/bin/init deleted file mode 100644 index 80cc2cffb3..0000000000 --- a/arch/ppc/boards/owc-da923rc/defaultenv-owc-da923rc/bin/init +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh -export PATH=/env/bin - -source /env/config - -#Define a 26MB partition in flash starting at offset 0x20000 -addpart -n /dev/nor0 0x1a00000@0x20000(boot) -ubiattach /dev/boot - -if [ $? -ne 0 ]; then - echo "Fail to attach UBI device" - exit 1; -fi - -mkdir /mnt -mount -t ubifs /dev/ubi0.boot /mnt - -echo -echo -n "Hit ctrl-c to stop autoboot: " -timeout -c 5 - -if [ $? -ne 0 ]; then - exit 0 -fi - -boot diff --git a/arch/ppc/boards/owc-da923rc/defaultenv-owc-da923rc/config b/arch/ppc/boards/owc-da923rc/defaultenv-owc-da923rc/config deleted file mode 100644 index 79e2606a71..0000000000 --- a/arch/ppc/boards/owc-da923rc/defaultenv-owc-da923rc/config +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh -export bootargs="root=/dev/nfs rw ip=bootp" -eth0.ipaddr=192.168.0.136 -eth0.serverip=192.168.0.102 diff --git a/arch/ppc/boards/owc-da923rc/law.c b/arch/ppc/boards/owc-da923rc/law.c deleted file mode 100644 index 3d32c7e677..0000000000 --- a/arch/ppc/boards/owc-da923rc/law.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2013 GE Intelligent Platforms, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <asm/fsl_law.h> - -struct law_entry law_table[] = { - FSL_SET_LAW(0xf8000000, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - FSL_SET_LAW(0xc0000000, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - FSL_SET_LAW(0xe1000000, LAW_SIZE_64K, LAW_TRGT_IF_PCI), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/arch/ppc/boards/owc-da923rc/nand.c b/arch/ppc/boards/owc-da923rc/nand.c deleted file mode 100644 index 550d790570..0000000000 --- a/arch/ppc/boards/owc-da923rc/nand.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright 2013 GE Intelligent Platforms, Inc - * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> - * (C) Copyright 2006 - * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * This code only cares about setting up the UPM state machine for Linux - * to use the NAND. - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> -#include <asm/fsl_lbc.h> -#include <mach/immap_85xx.h> - -/* NAND UPM tables for a 25Mhz bus frequency. */ -static const u32 upm_patt_25[] = { - /* Single read data */ - 0xcff02c30, 0x0ff02c30, 0x0ff02c34, 0x0ff32c30, - 0xfff32c31, 0xfff32c30, 0xfffffc30, 0xfffffc30, - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - 0xcfaf2c30, 0x0faf2c30, 0x0faf2c30, 0x0fff2c34, - 0xfffffc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - 0xcfa3ec30, 0x0fa3ec30, 0x0fa3ec30, 0x0ff3ec34, - 0xfff3ec31, 0xfffffc30, 0xfffffc30, 0xfffffc30, - /* UPM Write Single RAM array entry -> NAND Write Data */ - 0x0ff32c30, 0x0fa32c30, 0x0fa32c34, 0x0ff32c30, - 0xfff32c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, - /* Default */ - 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, - 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, - 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, - 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, - 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -static void upm_write(uint8_t addr, uint32_t val) -{ - void __iomem *lbc = LBC_BASE_ADDR; - - out_be32(lbc + FSL_LBC_MDR_OFFSET, val); - clrsetbits_be32(lbc + FSL_LBC_MAMR_OFFSET, MxMR_MAD_MSK, - MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); - - /* dummy access to perform write */ - out_8(IOMEM(0xfc000000), 0); - clrbits_be32(lbc + FSL_LBC_MAMR_OFFSET, MxMR_OP_WARR); -} - -static int board_nand_init(void) -{ - void __iomem *mxmr = IOMEM(LBC_BASE_ADDR + FSL_LBC_MAMR_OFFSET); - int j; - - /* Base register CS2: - * - 0xfc000000 - * - 8-bit data width - * - UPMA - */ - fsl_set_lbc_br(2, BR_PHYS_ADDR(0xfc000000) | BR_PS_8 | BR_MS_UPMA | - BR_V); - - /* - * Otions register: - * - 32KB window. - * - Buffer control disabled. - * - External address latch delay. - */ - fsl_set_lbc_or(2, 0xffffe001); - - for (j = 0; j < 64; j++) - upm_write(j, upm_patt_25[j]); - - out_be32(mxmr, MxMR_OP_NORM | MxMR_GPL_x4DIS); - - return 0; -} - -device_initcall(board_nand_init); diff --git a/arch/ppc/boards/owc-da923rc/product_data.c b/arch/ppc/boards/owc-da923rc/product_data.c deleted file mode 100644 index 5135afdd2a..0000000000 --- a/arch/ppc/boards/owc-da923rc/product_data.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright 2013 GE Intelligent Platforms Inc. - * Copyright 2019 Abaco Systems Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Retrieve and check the product data. - */ - -#include <common.h> -#include <crc.h> -#include <i2c/i2c.h> -#include <mach/immap_85xx.h> -#include <mach/fsl_i2c.h> -#include "product_data.h" - -static int owc_pd_header_check(unsigned short header) -{ - if (header != 0xa5a5) - return -1; - else - return 0; -} - -static int owc_is_data_valid(struct owc_product_data *v) -{ - int crc, ret = 0; - const unsigned char *p = (const unsigned char *)v; - - if (owc_pd_header_check(v->v1.pdh.tag)) - return -1; - - switch (v->v1.pdh.version) { - case PDVERSION_V1: - case PDVERSION_V1bis: - crc = crc32(0, p, sizeof(struct product_data_v1) - 4); - if (crc != v->v1.crc32) - ret = -1; - break; - case PDVERSION_V2: - crc = crc32(0, p, sizeof(struct product_data_v2) - 4); - if (crc != v->v2.crc32) - ret = -1; - break; - default: - ret = -1; - } - - return ret; -} - -int owc_get_product_data(struct owc_product_data *productp) -{ - struct i2c_adapter *adapter; - struct i2c_client client; - unsigned int width = 0; - int ret; - - adapter = i2c_get_adapter(0); - client.addr = 0x51; - client.adapter = adapter; - ret = i2c_read_reg(&client, 0, (uint8_t *) productp, - sizeof(unsigned short)); - - /* If there is no valid header, it may be a 16-bit eeprom. */ - if (owc_pd_header_check(productp->v1.pdh.tag)) - width = I2C_ADDR_16_BIT; - - ret = i2c_read_reg(&client, width, (uint8_t *) productp, - sizeof(struct owc_product_data)); - - if (ret == sizeof(struct owc_product_data)) - ret = owc_is_data_valid(productp); - - return ret; -} diff --git a/arch/ppc/boards/owc-da923rc/product_data.h b/arch/ppc/boards/owc-da923rc/product_data.h deleted file mode 100644 index cbbb8d377f..0000000000 --- a/arch/ppc/boards/owc-da923rc/product_data.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2013 GE Intelligent Platforms, Inc. - * Copyright 2019 Abaco Systems, Inc. - * - * The product data structure and function prototypes. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -struct board_info { - uint32_t bid; - uint32_t rev; -}; - -#define MAX_MAC 8 -enum product_data_version { - PDVERSION_V1 = 1, - PDVERSION_V1bis = 0x10, - PDVERSION_V2 = 2, - PDVERSION_MAX = PDVERSION_V2, -}; - -struct __attribute__ ((__packed__)) product_data_header { - unsigned short tag; - unsigned char version; - unsigned short len; -}; - -struct __attribute__ ((__packed__)) mac { - unsigned char count; - unsigned char mac[MAX_MAC][6]; -}; - -struct __attribute__ ((__packed__)) product_data_v1 { - struct product_data_header pdh; - struct mac mac; - int crc32; -}; - -struct __attribute__ ((__packed__)) product_data_v2 { - struct product_data_header pdh; - struct mac mac; - char sn[8]; - int crc32; -}; - -struct __attribute__ ((__packed__)) owc_product_data { - union { - struct product_data_v1 v1; - struct product_data_v2 v2; - }; -}; - -extern int owc_get_product_data(struct owc_product_data *productp); -extern void da923rc_boardinfo_get(struct board_info *bi); diff --git a/arch/ppc/boards/owc-da923rc/tlb.c b/arch/ppc/boards/owc-da923rc/tlb.c deleted file mode 100644 index 889e2743b7..0000000000 --- a/arch/ppc/boards/owc-da923rc/tlb.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright 2013 GE Intelligent Platforms, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <mach/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (4 * 1024), - CFG_INIT_RAM_ADDR + (4 * 1024), - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (8 * 1024), - CFG_INIT_RAM_ADDR + (8 * 1024), - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (12 * 1024), - CFG_INIT_RAM_ADDR + (12 * 1024), - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - /* - * TLB 0/1: 2x16M Cache inhibited, guarded - * CPLD and NAND in cache-inhibited area. - */ - FSL_SET_TLB_ENTRY(1, BOOT_BLOCK, BOOT_BLOCK, - MAS3_SX | MAS3_SW | MAS3_SR, - MAS2_W | MAS2_I | MAS2_G | MAS2_M, - 0, 0, BOOKE_PAGESZ_16M, 1), - FSL_SET_TLB_ENTRY(1, BOOT_BLOCK + 0x1000000, - BOOT_BLOCK + 0x1000000, - MAS3_SX | MAS3_SW | MAS3_SR, - MAS2_W | MAS2_I | MAS2_G | MAS2_M, - 0, 1, BOOKE_PAGESZ_16M, 1), - /* - * The boot flash is mapped with the cache enabled. - * TLB 2/3: 2x16M Cacheable Write-through, guarded - */ - FSL_SET_TLB_ENTRY(1, BOOT_BLOCK + (2 * 0x1000000), - BOOT_BLOCK + (2 * 0x1000000), - MAS3_SX | MAS3_SW | MAS3_SR, - MAS2_W | MAS2_G | MAS2_M, - 0, 2, BOOKE_PAGESZ_16M, 1), - FSL_SET_TLB_ENTRY(1, BOOT_BLOCK + (3 * 0x1000000), - BOOT_BLOCK + (3 * 0x1000000), - MAS3_SX | MAS3_SW | MAS3_SR, - MAS2_W | MAS2_G | MAS2_M, - 0, 3, BOOKE_PAGESZ_16M, 1), - - FSL_SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, - MAS2_I | MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/arch/ppc/boards/pcm030/Makefile b/arch/ppc/boards/pcm030/Makefile deleted file mode 100644 index 4e5dc4f57b..0000000000 --- a/arch/ppc/boards/pcm030/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += pcm030.o eeprom.o -extra-y += barebox.lds diff --git a/arch/ppc/boards/pcm030/barebox.lds.S b/arch/ppc/boards/pcm030/barebox.lds.S deleted file mode 100644 index 6c91ed6256..0000000000 --- a/arch/ppc/boards/pcm030/barebox.lds.S +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <asm-generic/barebox.lds.h> - -OUTPUT_ARCH("powerpc") -ENTRY(_start) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - . = TEXT_BASE; - - .text : - { - _text = .; - _stext = .; - arch/ppc/mach-mpc5xxx/start.o (.text) - *(.text*) - *(.got1*) - . = ALIGN(16); - *(.rodata*) - *(.rodata1*) - *(.rodata.str1.4) - RO_DATA_SECTION - } - - /* Read-only sections, merged into text segment: */ -/* - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } -*/ - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _etext = .; - PROVIDE (erotext = .); - _sdata = .; - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - - .data : - { - *(.data*) - *(.data1*) - *(.sdata*) - *(.sdata2*) - *(.dynamic*) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __init_size = __init_end - _start; - - __bss_start = .; - .bss : - { - *(.sbss*) *(.scommon*) - *(.dynbss*) - *(.bss*) - *(COMMON) - } - __bss_stop = .; - _end = . ; - PROVIDE (end = .); -} diff --git a/arch/ppc/boards/pcm030/config.h b/arch/ppc/boards/pcm030/config.h deleted file mode 100644 index 3fe1f286d9..0000000000 --- a/arch/ppc/boards/pcm030/config.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messatechnik GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <mach/mpc5xxx.h> - -#define CFG_MPC5XXX_CLKIN 33333000 /* ... running at 33.333MHz */ - -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#endif /* __CONFIG_H */ diff --git a/arch/ppc/boards/pcm030/eeprom.c b/arch/ppc/boards/pcm030/eeprom.c deleted file mode 100644 index aa00f361cd..0000000000 --- a/arch/ppc/boards/pcm030/eeprom.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (C) 2015 Juergen Borleis <kernel@pengutronix.de> - * - * Based on code from: - * Copyright (C) 2013 Jan Luebbe <j.luebbe@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <common.h> -#include <errno.h> -#include <fcntl.h> -#include <fs.h> -#include <globalvar.h> -#include <xfuncs.h> -#include <init.h> -#include <net.h> - -#define PCM030_EEPROM_DEVICE "/dev/eeprom0" - -/* - * The first 2048 bytes contain the U-Boot environment shipped with the boards. - * After that an area begins where some board specific and partially unique data - * is stored. All of this data is plain test, string delimiter is the semicolon. - * the last string terminates with a '\0'. - * One example found in the 'product' area: PCM-030-02REI;017822;0050C2875974\0 - * The first string seems to be the product type, the second string some kind - * of serial number and the last string the boards unique MAC. - */ -struct pcm030_eeprom { - char env[0x800]; /* u-boot environment */ - char product[0x80]; /* <product>;<serno>;<mac>\0 */ -} __attribute__((packed)); - -static void pcm030_read_factory_data(const struct pcm030_eeprom *buf) -{ - unsigned u, l; - char *board, *serial; - char *full_mac = "xx:xx:xx:xx:xx:xx"; - u8 enetaddr[6]; - - u = 0; - - for (l = 0; (l + u) < sizeof(buf->product); l++) { - if (buf->product[u + l] != ';') - continue; - board = xstrndup(&buf->product[u], l); - u += l + 1; - globalvar_add_simple("model.type", board); - free(board); - } - - for (l = 0; (l + u) < sizeof(buf->product); l++) { - if (buf->product[u + l] != ';') - continue; - serial = xstrndup(&buf->product[u], l); - u += l + 1; - globalvar_add_simple("model.serial", serial); - free(serial); - } - - /* for the MAC do a simple duck test */ - if (buf->product[u] != ';' && buf->product[u + 12] == '\0') { - full_mac[0] = buf->product[u + 0]; - full_mac[1] = buf->product[u + 1]; - full_mac[3] = buf->product[u + 2]; - full_mac[4] = buf->product[u + 3]; - full_mac[6] = buf->product[u + 4]; - full_mac[7] = buf->product[u + 5]; - full_mac[9] = buf->product[u + 6]; - full_mac[10] = buf->product[u + 7]; - full_mac[12] = buf->product[u + 8]; - full_mac[13] = buf->product[u + 9]; - full_mac[15] = buf->product[u + 10]; - full_mac[16] = buf->product[u + 11]; - string_to_ethaddr(full_mac, enetaddr); - eth_register_ethaddr(0, enetaddr); - return; - } - - printf("EEPROM contains no ethernet MAC\n"); -} - -static int pcm030_eeprom_read(void) -{ - int fd, ret; - struct pcm030_eeprom *buf; - - fd = open(PCM030_EEPROM_DEVICE, O_RDONLY); - if (fd < 0) { - perror("failed to open " PCM030_EEPROM_DEVICE); - return fd; - } - - buf = xmalloc(sizeof(struct pcm030_eeprom)); - - ret = pread(fd, buf, sizeof(struct pcm030_eeprom), 0); - if (ret < sizeof(struct pcm030_eeprom)) { - perror("failed to read " PCM030_EEPROM_DEVICE); - goto out; - } - - pcm030_read_factory_data(buf); - ret = 0; -out: - free(buf); - close(fd); - - return ret; -} -late_initcall(pcm030_eeprom_read); diff --git a/arch/ppc/boards/pcm030/env/init/mtdparts-nor b/arch/ppc/boards/pcm030/env/init/mtdparts-nor deleted file mode 100644 index 44c07ead21..0000000000 --- a/arch/ppc/boards/pcm030/env/init/mtdparts-nor +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="512k(nor0.bareboxlow),4M(nor0.kernel),512k(nor0.oftree),26M(nor0.root),512k(nor0.barebox),512k(nor0.bareboxenv)" -kernelname="physmap-flash.0" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/ppc/boards/pcm030/env/nv/linux.bootargs.console b/arch/ppc/boards/pcm030/env/nv/linux.bootargs.console deleted file mode 100644 index 31ce0e71eb..0000000000 --- a/arch/ppc/boards/pcm030/env/nv/linux.bootargs.console +++ /dev/null @@ -1 +0,0 @@ -console=ttyPSC0,115200 diff --git a/arch/ppc/boards/pcm030/mt46v32m16-75.h b/arch/ppc/boards/pcm030/mt46v32m16-75.h deleted file mode 100644 index 60ea09eebc..0000000000 --- a/arch/ppc/boards/pcm030/mt46v32m16-75.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * Eric Schumann, Phytec Messtechnik - * adapted for mt46v32m16-75 DDR-RAM - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x715f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 - - -/* Settings for XLB = 99 MHz */ -/* -#define SDRAM_MODE 0x008D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714b0f00 -#define SDRAM_CONFIG1 0x63611730 -#define SDRAM_CONFIG2 0x47670000 -*/ - -#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */ diff --git a/arch/ppc/boards/pcm030/pcm030.c b/arch/ppc/boards/pcm030/pcm030.c deleted file mode 100644 index 05c1ce9ca8..0000000000 --- a/arch/ppc/boards/pcm030/pcm030.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messtechnik GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <driver.h> -#include <init.h> -#include <platform_data/eth-fec.h> -#include <types.h> -#include <partition.h> -#include <memory.h> -#include <linux/sizes.h> -#include <linux/stat.h> -#include <asm/io.h> -#include <fs.h> -#include <i2c/i2c.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, -}; - -static struct i2c_board_info pcm030_i2c_devices[] = { - { I2C_BOARD_INFO("pcf8563", 0x51), }, - { I2C_BOARD_INFO("24c32", 0x52), }, -}; - -struct i2c_platform_data pcm030_i2c_plat = { - .bitrate = 100000, -}; - -static int devices_init (void) -{ - struct stat s; - int ret; - - /* - * Flash can be 16MB or 32MB, setup for the last 32MB no matter - * what we find later. - */ - mpc5200_setup_cs(MPC5200_BOOTCS, 0xfe000000, SZ_32M, 0x0008fd00); - add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xfe000000, 32 * 1024 * 1024, 0); - - add_generic_device("fec_mpc5xxx", DEVICE_ID_DYNAMIC, NULL, MPC5XXX_FEC, 0x200, - IORESOURCE_MEM, &fec_info); - i2c_register_board_info(0, pcm030_i2c_devices, ARRAY_SIZE(pcm030_i2c_devices)); - add_generic_device("i2c-fsl", DEVICE_ID_DYNAMIC, NULL, MPC5XXX_I2C2, 0x100, - IORESOURCE_MEM, &pcm030_i2c_plat); - - ret = stat("/dev/nor0", &s); - if (ret) - return 0; - - devfs_add_partition("nor0", s.st_size - SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", s.st_size - SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env0"); - - return 0; -} - -device_initcall(devices_init); - -static int console_init(void) -{ - barebox_set_model("Phytec phyCORE MPC5200 tiny"); - barebox_set_hostname("mpc5200"); - - add_generic_device("mpc5xxx_serial", DEVICE_ID_DYNAMIC, NULL, MPC5XXX_PSC3, 0x200, - IORESOURCE_MEM, NULL); - add_generic_device("mpc5xxx_serial", DEVICE_ID_DYNAMIC, NULL, MPC5XXX_PSC6, 0x200, - IORESOURCE_MEM, NULL); - return 0; -} - -console_initcall(console_init); - -static int mem_init(void) -{ - unsigned long sdramsize; - - sdramsize = mpc5200_get_sdram_size(0) + mpc5200_get_sdram_size(1); - - barebox_add_memory_bank("ram0", 0x0, sdramsize); - - return 0; -} -mem_initcall(mem_init); - -#include "mt46v32m16-75.h" - -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} - -void initdram (int board_type) -{ - ulong dramsize = 0; - - ulong test1, test2; - - /* Setup pin multiplexing */ - - /* PSC6=UART, PSC3=UART ; Ether=100MBit with MD */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = 0x00559c10; - *(vu_long *)MPC5XXX_CS_BURST = 0x00000000; - *(vu_long *)MPC5XXX_CS_DEADCYCLE = 0x33333333; - - /* - * Make USB work due to the special base crystal frequency: - * 33,3330MHz * 16 = 533,328MHz main clock, but should be 528 MHz Clock - */ - out_be32((void *)MPC5XXX_CDM_48_FDC, 0x00015555); - - mpc5200_setup_bus_clocks(1, 4); - - if (get_pc() > SZ_128M) { - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR && SDRAM_TAPDELAY - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((ulong *)0, 0x10000000); - sdram_start(1); - test2 = get_ram_size((ulong *)0, 0x10000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - } -} |