diff options
Diffstat (limited to 'arch/riscv')
37 files changed, 459 insertions, 493 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1190cd4272..8f2cd089a2 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,12 +8,12 @@ config RISCV select OFDEVICE select COMMON_CLK select COMMON_CLK_OF_PROVIDER - select CLKDEV_LOOKUP select HAS_DMA + select ARCH_DMA_DEFAULT_COHERENT select HAVE_PBL_IMAGE select HAVE_PBL_MULTI_IMAGES select HAVE_IMAGE_COMPRESSION - select HAS_ARCH_SJLJ + select ARCH_HAS_SJLJ select HAS_KALLSYMS select RISCV_TIMER if RISCV_SBI select HW_HAS_PCI diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 828b65a0c1..cef9cd5230 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -5,7 +5,7 @@ menu "SoC selection" config SOC_ERIZO bool "Erizo SoC" depends on ARCH_RV32I - select HAS_ASM_DEBUG_LL + select HAS_DEBUG_LL select HAS_NMON select USE_COMPRESSED_DTB select RISCV_M_MODE @@ -20,7 +20,7 @@ config SOC_VIRT select RISCV_S_MODE select BOARD_RISCV_GENERIC_DT select HAS_CACHE - select HAS_ASM_DEBUG_LL + select HAS_DEBUG_LL help Generates an image tht can be be booted by QEMU. The image is called barebox-dt-2nd.img @@ -38,6 +38,7 @@ config BOARD_RISCV_VIRT config BOARD_RISCVEMU depends on SOC_VIRT bool "TinyEMU Virt Machine (riscvemu)" + select OF_OVERLAY default y help TinyEMU's Virt machine differs from QEMU in poweroff and restart @@ -55,7 +56,7 @@ config SOC_SIFIVE select CLK_SIFIVE_PRCI select RISCV_TIMER select HAS_MACB - select HAS_ASM_DEBUG_LL + select HAS_DEBUG_LL help This enables support for SiFive SoC platform hardware. @@ -72,7 +73,7 @@ config SOC_STARFIVE bool "StarFive SoCs" select ARCH_HAS_RESET_CONTROLLER select RISCV_S_MODE - select HAS_ASM_DEBUG_LL + select HAS_DEBUG_LL select HAS_NMON help This enables support for SiFive SoC platform hardware. @@ -87,6 +88,7 @@ config SOC_STARFIVE_JH7100 bool select SOC_STARFIVE_JH71XX select SIFIVE_L2 + select OF_DMA_COHERENCY help Unlike JH7110 and later, CPU on the JH7100 are not cache-coherent with respect to DMA masters like GMAC and DW MMC controller. @@ -110,6 +112,22 @@ config BOARD_BEAGLEV_BETA endif +config SOC_ALLWINNER_SUN20I + bool "Allwinner Sun20i SoCs" + depends on ARCH_RV64I + select HAS_DEBUG_LL + select HAS_CACHE + +if SOC_ALLWINNER_SUN20I + +config BOARD_ALLWINNER_D1 + bool "Allwinner D1 Nezha" + select RISCV_S_MODE + select RISCV_M_MODE + def_bool y + +endif + comment "CPU features" config SIFIVE_L2 @@ -119,7 +137,7 @@ config SIFIVE_L2 config SOC_LITEX bool "LiteX SoCs" depends on ARCH_RV32I - select HAS_ASM_DEBUG_LL + select HAS_DEBUG_LL select HAS_NMON select USE_COMPRESSED_DTB select RISCV_TIMER diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 6fbf1d4ddd..71ca82fe8d 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -1,25 +1,34 @@ # SPDX-License-Identifier: GPL-2.0-only -KBUILD_DEFCONFIG := virt64_defconfig +KBUILD_DEFCONFIG := rv64i_defconfig KBUILD_CPPFLAGS += -fno-strict-aliasing ifeq ($(CONFIG_ARCH_RV32I),y) - riscv-cflags-y += -march=rv32im -mabi=ilp32 + KBUILD_CPPFLAGS += -mabi=ilp32 riscv-ldflags-y += -melf32lriscv else - riscv-cflags-y += -march=rv64im -mabi=lp64 + KBUILD_CPPFLAGS += -mabi=lp64 riscv-ldflags-y += -melf64lriscv endif -riscv-cflags-y += -Wstrict-prototypes -mcmodel=medany -fpic -riscv-ldflags-y += -pie -static +# ISA string setting +riscv-march-$(CONFIG_ARCH_RV32I) := rv32im +riscv-march-$(CONFIG_ARCH_RV64I) := rv64im -PBL_CPPFLAGS += $(riscv-cflags-y) -LDFLAGS_pbl += $(riscv-ldflags-y) +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei -cflags-y += $(riscv-cflags-y) +KBUILD_CPPFLAGS += -march=$(riscv-march-y) +KBUILD_CFLAGS += -mno-save-restore +KBUILD_CFLAGS += -fno-asynchronous-unwind-tables -fno-unwind-tables +KBUILD_CFLAGS += $(call cc-option,-mstrict-align) +KBUILD_CPPFLAGS += -Wstrict-prototypes -mcmodel=medany -fpic +riscv-ldflags-y += -pie -static +LDFLAGS_pbl += $(riscv-ldflags-y) LDFLAGS_barebox += $(riscv-ldflags-y) ifndef CONFIG_MODULES @@ -29,6 +38,7 @@ LDFLAGS_barebox += -static --gc-sections endif KBUILD_BINARY := barebox.bin +KBUILD_IMAGE := $(KBUILD_BINARY) archprepare: maketools @@ -41,11 +51,6 @@ common-y += arch/riscv/boot/ common-$(CONFIG_OFTREE) += arch/riscv/dts/ -KBUILD_CPPFLAGS += $(cflags-y) -KBUILD_CFLAGS += $(cflags-y) - lds-y := arch/riscv/lib/barebox.lds CLEAN_FILES += arch/riscv/lib/barebox.lds - -KBUILD_IMAGE := $(KBUILD_BINARY) diff --git a/arch/riscv/boards/Makefile b/arch/riscv/boards/Makefile index 3b763ff308..df16d38496 100644 --- a/arch/riscv/boards/Makefile +++ b/arch/riscv/boards/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_BOARD_ALLWINNER_D1) += allwinner-d1/ obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo/ obj-$(CONFIG_BOARD_HIFIVE) += hifive/ obj-$(CONFIG_BOARD_BEAGLEV) += beaglev/ diff --git a/arch/riscv/boards/allwinner-d1/Makefile b/arch/riscv/boards/allwinner-d1/Makefile new file mode 100644 index 0000000000..3d217ffe0b --- /dev/null +++ b/arch/riscv/boards/allwinner-d1/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +pbl-y += lowlevel.o diff --git a/arch/riscv/boards/allwinner-d1/lowlevel.c b/arch/riscv/boards/allwinner-d1/lowlevel.c new file mode 100644 index 0000000000..2b07a81edb --- /dev/null +++ b/arch/riscv/boards/allwinner-d1/lowlevel.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <debug_ll.h> +#include <asm/barebox-riscv.h> + +#define DRAM_BASE 0x40000000 + +ENTRY_FUNCTION(start_allwinner_d1, a0, a1, a2) +{ + barebox_riscv_supervisor_entry(DRAM_BASE, SZ_1G, a0, (void *)a1); +} diff --git a/arch/riscv/boards/beaglev/board.c b/arch/riscv/boards/beaglev/board.c index 110754ea95..d466eef7f1 100644 --- a/arch/riscv/boards/beaglev/board.c +++ b/arch/riscv/boards/beaglev/board.c @@ -8,7 +8,7 @@ #include <bbu.h> #include <envfs.h> -static int beaglev_probe(struct device_d *dev) +static int beaglev_probe(struct device *dev) { barebox_set_hostname("beaglev-starlight"); @@ -21,8 +21,9 @@ static const struct of_device_id beaglev_of_match[] = { { .compatible = "beagle,beaglev-starlight-jh7100" }, { /* sentinel */ }, }; +MODULE_DEVICE_TABLE(of, beaglev_of_match); -static struct driver_d beaglev_board_driver = { +static struct driver beaglev_board_driver = { .name = "board-beaglev", .probe = beaglev_probe, .of_compatible = beaglev_of_match, diff --git a/arch/riscv/boards/riscvemu/Makefile b/arch/riscv/boards/riscvemu/Makefile index 56949c2357..baada2136e 100644 --- a/arch/riscv/boards/riscvemu/Makefile +++ b/arch/riscv/boards/riscvemu/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += board.o -obj-y += overlay-of-sram.dtb.o +obj-y += riscvemu-sram.dtbo.o bbenv-$(CONFIG_CMD_TUTORIAL) += defaultenv-riscvemu + +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z +clean-files += *.dtbo *.dtbo.S .*.dtso diff --git a/arch/riscv/boards/riscvemu/board.c b/arch/riscv/boards/riscvemu/board.c index d9c7bd77b8..afd6608ac5 100644 --- a/arch/riscv/boards/riscvemu/board.c +++ b/arch/riscv/boards/riscvemu/board.c @@ -33,17 +33,17 @@ static void __noreturn riscvemu_restart(struct restart_handler *rst) priv->restart(riscv_hartid(), barebox_riscv_boot_dtb()); } -extern char __dtb_overlay_of_sram_start[]; +extern char __dtbo_riscvemu_sram_start[]; -static int riscvemu_probe(struct device_d *dev) +static int riscvemu_probe(struct device *dev) { struct device_node *of_chosen; struct device_node *overlay; struct riscvemu_priv *priv; u64 start; - overlay = of_unflatten_dtb(__dtb_overlay_of_sram_start, INT_MAX); - of_overlay_apply_tree(dev->device_node, overlay); + overlay = of_unflatten_dtb(__dtbo_riscvemu_sram_start, INT_MAX); + of_overlay_apply_tree(dev->of_node, overlay); /* of_probe() will happen later at of_populate_initcall */ if (IS_ENABLED(CONFIG_CMD_TUTORIAL)) @@ -69,7 +69,7 @@ static const struct of_device_id riscvemu_of_match[] = { }; BAREBOX_DEEP_PROBE_ENABLE(riscvemu_of_match); -static struct driver_d riscvemu_board_driver = { +static struct driver riscvemu_board_driver = { .name = "board-riscvemu", .probe = riscvemu_probe, .of_compatible = riscvemu_of_match, diff --git a/arch/riscv/boards/riscvemu/overlay-of-sram.dts b/arch/riscv/boards/riscvemu/overlay-of-sram.dts deleted file mode 100644 index 506d45bde9..0000000000 --- a/arch/riscv/boards/riscvemu/overlay-of-sram.dts +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/dts-v1/; -/plugin/; - -/ { - fragment@0 { - target-path = "/soc"; - __overlay__ { - #address-cells = <2>; - #size-cells = <2>; - sram@0 { - compatible = "mtd-ram"; - reg = <0 0x1000 0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootrom"; - reg = <0x0 0x40>; - }; - - partition@40 { - label = "fdt"; - reg = <0x40 0x1fc0>; - }; - - environment_sram: partition@3000 { - label = "barebox-environment"; - reg = <0x3000 0xb000>; - }; - - backend_state_sram: partition@e000 { - label = "barebox-state"; - reg = <0xe000 0x1000>; - }; - }; - }; - }; - }; - - fragment@2 { - target-path = "/chosen"; - __overlay__ { - environment { - compatible = "barebox,environment"; - device-path = "/soc/sram@0/partitions/partition@3000"; - }; - }; - }; - - fragment@3 { - target-path = "/"; - __overlay__ { - aliases { - state = "/state"; - }; - - state { - #address-cells = <1>; - #size-cells = <1>; - compatible = "barebox,state"; - magic = <0x290cf8c6>; - backend-type = "raw"; - backend = <&backend_state_sram>; - backend-stridesize = <64>; - - bootstate { - #address-cells = <1>; - #size-cells = <1>; - - system0 { - #address-cells = <1>; - #size-cells = <1>; - - remaining_attempts@0 { - reg = <0x0 0x4>; - type = "uint32"; - default = <3>; - }; - - priority@4 { - reg = <0x4 0x4>; - type = "uint32"; - default = <20>; - }; - }; - - system1 { - #address-cells = <1>; - #size-cells = <1>; - - remaining_attempts@8 { - reg = <0x8 0x4>; - type = "uint32"; - default = <3>; - }; - - priority@c { - reg = <0xc 0x4>; - type = "uint32"; - default = <21>; - }; - }; - - last_chosen@10 { - reg = <0x10 0x4>; - type = "uint32"; - }; - }; - }; - }; - }; - - fragment@4 { - target-path = "/htif"; - #address-cells = <2>; - #size-cells = <2>; - - __overlay__ { - reg = <0 0x40008000 0 0x8>; - }; - }; -}; diff --git a/arch/riscv/boards/riscvemu/riscvemu-sram.dtso b/arch/riscv/boards/riscvemu/riscvemu-sram.dtso new file mode 100644 index 0000000000..395fde84c1 --- /dev/null +++ b/arch/riscv/boards/riscvemu/riscvemu-sram.dtso @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/dts-v1/; +/plugin/; + +&{/soc} { + #address-cells = <2>; + #size-cells = <2>; + sram@1000 { + compatible = "mtd-ram"; + reg = <0 0x1000 0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootrom"; + reg = <0x0 0x40>; + }; + + partition@40 { + label = "fdt"; + reg = <0x40 0x1fc0>; + }; + + environment_sram: partition@3000 { + label = "barebox-environment"; + reg = <0x3000 0xb000>; + }; + + backend_state_sram: partition@e000 { + label = "barebox-state"; + reg = <0xe000 0x1000>; + }; + }; + }; +}; + +&{/chosen} { + environment { + compatible = "barebox,environment"; + device-path = "/soc/sram@1000/partitions/partition@3000"; + }; +}; + +&{/} { + aliases { + state = "/state"; + }; + + state { + #address-cells = <1>; + #size-cells = <1>; + compatible = "barebox,state"; + magic = <0x290cf8c6>; + backend-type = "raw"; + backend = <&backend_state_sram>; + backend-stridesize = <64>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@4 { + reg = <0x4 0x4>; + type = "uint32"; + default = <20>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@8 { + reg = <0x8 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@c { + reg = <0xc 0x4>; + type = "uint32"; + default = <21>; + }; + }; + + last_chosen@10 { + reg = <0x10 0x4>; + type = "uint32"; + }; + }; + }; +}; + +&{/htif} { + reg = <0 0x40008000 0 0x8>; +}; diff --git a/arch/riscv/boot/board-dt-2nd.c b/arch/riscv/boot/board-dt-2nd.c index 8b78e1b11d..f1479d8346 100644 --- a/arch/riscv/boot/board-dt-2nd.c +++ b/arch/riscv/boot/board-dt-2nd.c @@ -50,6 +50,12 @@ static void noinline __noreturn start_dt_2nd_nonnaked(unsigned long hartid, if (!fdt) hang(); + /* + * We need to call this here, as a multiplatform build + * depends on querying mode for riscv_vendor_id() + */ + riscv_set_flags(RISCV_S_MODE); + relocate_to_current_adr(); setup_c(); diff --git a/arch/riscv/boot/entry.c b/arch/riscv/boot/entry.c index e4a5c2208d..f5a536fc78 100644 --- a/arch/riscv/boot/entry.c +++ b/arch/riscv/boot/entry.c @@ -25,6 +25,7 @@ void __noreturn __naked barebox_riscv_entry(unsigned long membase, { unsigned long stack_top = riscv_mem_stack_top(membase, membase + memsize); asm volatile ("move sp, %0" : : "r"(stack_top)); - barebox_pbl_start(membase, memsize, boarddata, flags); + riscv_set_flags(flags); + barebox_pbl_start(membase, memsize, boarddata); } diff --git a/arch/riscv/boot/entry.h b/arch/riscv/boot/entry.h index fb4af5eae5..b3a24d2783 100644 --- a/arch/riscv/boot/entry.h +++ b/arch/riscv/boot/entry.h @@ -6,12 +6,10 @@ void __noreturn barebox_non_pbl_start(unsigned long membase, unsigned long memsize, - void *boarddata, - unsigned flags); + void *boarddata); void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize, - void *boarddata, - unsigned flags); + void *boarddata); #endif diff --git a/arch/riscv/boot/start.c b/arch/riscv/boot/start.c index 8b4c8bb2f0..92991d0f6a 100644 --- a/arch/riscv/boot/start.c +++ b/arch/riscv/boot/start.c @@ -3,6 +3,10 @@ #define pr_fmt(fmt) "start.c: " fmt +#ifdef CONFIG_DEBUG_INITCALLS +#define DEBUG +#endif + #include <common.h> #include <init.h> #include <linux/sizes.h> @@ -27,7 +31,6 @@ static unsigned long riscv_barebox_size; static unsigned long riscv_endmem; static void *barebox_boarddata; static unsigned long barebox_boarddata_size; -unsigned barebox_riscv_pbl_flags; void *barebox_riscv_boot_dtb(void) { @@ -108,7 +111,7 @@ device_initcall(barebox_memory_areas_init); */ __noreturn __no_sanitize_address __section(.text_entry) void barebox_non_pbl_start(unsigned long membase, unsigned long memsize, - void *boarddata, unsigned flags) + void *boarddata) { unsigned long endmem = membase + memsize; unsigned long malloc_start, malloc_end; @@ -121,7 +124,7 @@ void barebox_non_pbl_start(unsigned long membase, unsigned long memsize, barrier(); - irq_init_vector(__riscv_mode(flags)); + irq_init_vector(riscv_mode()); pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize); @@ -171,20 +174,18 @@ void barebox_non_pbl_start(unsigned long membase, unsigned long memsize, mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1); - barebox_riscv_pbl_flags = flags; - pr_debug("starting barebox...\n"); start_barebox(); } -void start(unsigned long membase, unsigned long memsize, void *boarddata, unsigned flags); +void start(unsigned long membase, unsigned long memsize, void *boarddata); /* * First function in the uncompressed image. We get here from * the pbl. The stack already has been set up by the pbl. */ void __no_sanitize_address __section(.text_entry) start(unsigned long membase, - unsigned long memsize, void *boarddata, unsigned flags) + unsigned long memsize, void *boarddata) { - barebox_non_pbl_start(membase, memsize, boarddata, flags); + barebox_non_pbl_start(membase, memsize, boarddata); } diff --git a/arch/riscv/boot/uncompress.c b/arch/riscv/boot/uncompress.c index 4ed9b4d371..84142acf9c 100644 --- a/arch/riscv/boot/uncompress.c +++ b/arch/riscv/boot/uncompress.c @@ -24,20 +24,20 @@ unsigned long free_mem_ptr; unsigned long free_mem_end_ptr; void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize, - void *fdt, unsigned flags) + void *fdt) { uint32_t pg_len, uncompressed_len; - void __noreturn (*barebox)(unsigned long, unsigned long, void *, unsigned); + void __noreturn (*barebox)(unsigned long, unsigned long, void *); unsigned long endmem = membase + memsize; unsigned long barebox_base; void *pg_start, *pg_end; unsigned long pc = get_pc(); - irq_init_vector(__riscv_mode(flags)); + irq_init_vector(riscv_mode()); /* piggy data is not relocated, so determine the bounds now */ - pg_start = input_data + get_runtime_offset(); - pg_end = input_data_end + get_runtime_offset(); + pg_start = runtime_address(input_data); + pg_end = runtime_address(input_data_end); pg_len = pg_end - pg_start; uncompressed_len = input_data_len(); @@ -72,5 +72,5 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize, pr_debug("jumping to uncompressed image at 0x%p. dtb=0x%p\n", barebox, fdt); - barebox(membase, memsize, fdt, flags); + barebox(membase, memsize, fdt); } diff --git a/arch/riscv/configs/virt64_defconfig b/arch/riscv/configs/rv64i_defconfig index c2edd2dc28..53c367c5e4 100644 --- a/arch/riscv/configs/virt64_defconfig +++ b/arch/riscv/configs/rv64i_defconfig @@ -1,5 +1,13 @@ CONFIG_ARCH_RV64I=y +CONFIG_SOC_ALLWINNER_SUN20I=y +CONFIG_SOC_SIFIVE=y +CONFIG_SOC_STARFIVE=y CONFIG_SOC_VIRT=y +CONFIG_BOARD_ALLWINNER_D1=y +CONFIG_BOARD_BEAGLEV=y +CONFIG_BOARD_BEAGLEV_BETA=y +CONFIG_BOARD_HIFIVE=y +CONFIG_BOARD_RISCV_GENERIC_DT=y CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y CONFIG_STACK_SIZE=0x20000 CONFIG_MALLOC_SIZE=0x0 @@ -13,6 +21,7 @@ CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y CONFIG_BOOTM_VERBOSE=y CONFIG_BOOTM_INITRD=y +CONFIG_SYSTEM_PARTITIONS=y CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_ALL=y CONFIG_CONSOLE_ALLOW_COLOR=y @@ -47,9 +56,11 @@ CONFIG_CMD_LN=y CONFIG_CMD_MD5SUM=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_UNCOMPRESS=y CONFIG_CMD_MSLEEP=y CONFIG_CMD_SLEEP=y CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y CONFIG_CMD_PING=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_EDIT=y @@ -66,6 +77,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y +CONFIG_CMD_WD=y CONFIG_CMD_2048=y CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_OF_DIFF=y @@ -86,12 +98,21 @@ CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_OF_BAREBOX_ENV_IN_FS=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_VIRTIO_CONSOLE=y +CONFIG_SERIAL_SIFIVE=y +CONFIG_DRIVER_NET_MACB=y +CONFIG_DRIVER_NET_DESIGNWARE=y +CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y +CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE=y CONFIG_DRIVER_NET_VIRTIO=y +CONFIG_MICREL_PHY=y +CONFIG_SPI_MEM=y CONFIG_DRIVER_SPI_GPIO=y +CONFIG_SPI_SIFIVE=y CONFIG_I2C=y CONFIG_I2C_GPIO=y CONFIG_MTD=y # CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_RAW_DEVICE=y CONFIG_MTD_CONCAT=y CONFIG_MTD_M25P80=y CONFIG_MTD_MTDRAM=y @@ -104,21 +125,42 @@ CONFIG_VIDEO=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_DRIVER_VIDEO_BOCHS_PCI=y CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y +CONFIG_MCI=y +CONFIG_MCI_SPI=y +CONFIG_MCI_DW=y CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 CONFIG_STATE_DRV=y CONFIG_EEPROM_AT24=y CONFIG_VIRTIO_INPUT=y +CONFIG_SRAM=y +CONFIG_STARFIVE_PWRSEQ=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y +CONFIG_WATCHDOG=y +CONFIG_STARFIVE_WDT=y CONFIG_HWRNG=y CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_GPIO_SIFIVE=y +CONFIG_HW_RANDOM_STARFIVE=y CONFIG_GPIO_GENERIC_PLATFORM=y -# CONFIG_PINCTRL is not set +CONFIG_GPIO_STARFIVE=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_NVMEM=y +CONFIG_NVMEM_RMEM=y +CONFIG_STARFIVE_OTP=y CONFIG_PCI_ECAM_GENERIC=y CONFIG_BLK_DEV_NVME=y CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_NVMEM_REBOOT_MODE=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_POWER_RESET_HTIF_POWEROFF=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_VIRTIO_MMIO=y +# CONFIG_VIRTIO_MENU is not set CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y CONFIG_FS_NFS=y diff --git a/arch/riscv/configs/sifive_defconfig b/arch/riscv/configs/sifive_defconfig deleted file mode 100644 index 6ebe6eaf37..0000000000 --- a/arch/riscv/configs/sifive_defconfig +++ /dev/null @@ -1,129 +0,0 @@ -CONFIG_ARCH_RV64I=y -CONFIG_SOC_SIFIVE=y -CONFIG_BOARD_HIFIVE=y -CONFIG_BOARD_RISCV_GENERIC_DT=y -CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_STACK_SIZE=0x20000 -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y -CONFIG_PANIC_HANG=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_CONSOLE_ALLOW_COLOR=y -CONFIG_PBL_CONSOLE=y -CONFIG_PARTITION_DISK_EFI=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_STATE=y -CONFIG_STATE_CRYPTO=y -CONFIG_BOOTCHOOSER=y -CONFIG_RESET_SOURCE=y -CONFIG_MACHINE_ID=y -CONFIG_CMD_DMESG=y -CONFIG_LONGHELP=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_IMD=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_POLLER=y -CONFIG_CMD_SLICE=y -CONFIG_CMD_GO=y -CONFIG_CMD_LOADY=y -CONFIG_CMD_RESET=y -CONFIG_CMD_BOOTCHOOSER=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_CMP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_LN=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_SHA1SUM=y -CONFIG_CMD_SHA256SUM=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_PING=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_FBTEST=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MM=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_POWEROFF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_2048=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_OF_DIFF=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_DISPLAY_TIMINGS=y -CONFIG_CMD_OF_FIXUP_STATUS=y -CONFIG_CMD_OF_OVERLAY=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_DHRYSTONE=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_NET_FASTBOOT=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_SERIAL_SIFIVE=y -CONFIG_DRIVER_NET_MACB=y -CONFIG_DRIVER_SPI_GPIO=y -CONFIG_SPI_SIFIVE=y -CONFIG_I2C=y -CONFIG_I2C_GPIO=y -CONFIG_MTD=y -CONFIG_MTD_RAW_DEVICE=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_M25P80=y -CONFIG_DRIVER_CFI=y -CONFIG_DRIVER_CFI_BANK_WIDTH_8=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIDEO=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y -CONFIG_MCI=y -CONFIG_MCI_SPI=y -CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 -CONFIG_EEPROM_AT24=y -CONFIG_HWRNG=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_GPIO_SIFIVE=y -# CONFIG_PINCTRL is not set -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_VIRTIO_MMIO=y -CONFIG_FS_EXT4=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_FS_UIMAGEFS=y -CONFIG_FS_PSTORE=y -CONFIG_FS_SQUASHFS=y -CONFIG_ZLIB=y -CONFIG_BZLIB=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y -CONFIG_XZ_DECOMPRESS=y -CONFIG_BASE64=y -CONFIG_DIGEST_CRC32_GENERIC=y -CONFIG_IMD_TARGET=y -CONFIG_BAREBOXENV_TARGET=y -CONFIG_BAREBOXCRC32_TARGET=y diff --git a/arch/riscv/configs/starfive_defconfig b/arch/riscv/configs/starfive_defconfig deleted file mode 100644 index c4df2256f5..0000000000 --- a/arch/riscv/configs/starfive_defconfig +++ /dev/null @@ -1,131 +0,0 @@ -CONFIG_ARCH_RV64I=y -CONFIG_SOC_STARFIVE=y -CONFIG_BOARD_BEAGLEV=y -CONFIG_BOARD_BEAGLEV_BETA=y -CONFIG_BOARD_RISCV_GENERIC_DT=y -CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_STACK_SIZE=0x20000 -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y -CONFIG_PANIC_HANG=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_BOOTM_INITRD=y -CONFIG_SYSTEM_PARTITIONS=y -CONFIG_IMD_TARGET=y -CONFIG_CONSOLE_ALLOW_COLOR=y -CONFIG_PBL_CONSOLE=y -CONFIG_PARTITION_DISK_EFI=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_BAREBOXENV_TARGET=y -CONFIG_BAREBOXCRC32_TARGET=y -CONFIG_STATE=y -CONFIG_STATE_CRYPTO=y -CONFIG_BOOTCHOOSER=y -CONFIG_RESET_SOURCE=y -CONFIG_MACHINE_ID=y -CONFIG_CMD_DMESG=y -CONFIG_LONGHELP=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_IMD=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_POLLER=y -CONFIG_CMD_SLICE=y -CONFIG_CMD_GO=y -CONFIG_CMD_LOADY=y -CONFIG_CMD_RESET=y -CONFIG_CMD_BOOTCHOOSER=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_CMP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_LN=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_SHA1SUM=y -CONFIG_CMD_SHA256SUM=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MM=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_POWEROFF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_WD=y -CONFIG_CMD_2048=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_OF_DIFF=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_DISPLAY_TIMINGS=y -CONFIG_CMD_OF_FIXUP_STATUS=y -CONFIG_CMD_OF_OVERLAY=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_DHRYSTONE=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_DRIVER_NET_DESIGNWARE=y -CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y -CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE=y -CONFIG_MICREL_PHY=y -CONFIG_SPI_MEM=y -CONFIG_DRIVER_SPI_GPIO=y -CONFIG_MCI=y -CONFIG_MCI_DW=y -CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 -CONFIG_SRAM=y -CONFIG_STARFIVE_PWRSEQ=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_LED_GPIO_OF=y -CONFIG_LED_TRIGGERS=y -CONFIG_WATCHDOG=y -CONFIG_STARFIVE_WDT=y -CONFIG_HWRNG=y -CONFIG_HW_RANDOM_STARFIVE=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_STARFIVE=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_NVMEM=y -CONFIG_NVMEM_RMEM=y -CONFIG_STARFIVE_OTP=y -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_NVMEM_REBOOT_MODE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_GPIO_RESTART=y -# CONFIG_VIRTIO_MENU is not set -CONFIG_FS_EXT4=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_FS_UIMAGEFS=y -CONFIG_FS_PSTORE=y -CONFIG_FS_SQUASHFS=y -CONFIG_ZLIB=y -CONFIG_BZLIB=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y -CONFIG_XZ_DECOMPRESS=y -CONFIG_BASE64=y -CONFIG_DIGEST_CRC32_GENERIC=y diff --git a/arch/riscv/cpu/core.c b/arch/riscv/cpu/core.c index c075301b1b..38aa402758 100644 --- a/arch/riscv/cpu/core.c +++ b/arch/riscv/cpu/core.c @@ -32,8 +32,8 @@ static int riscv_request_stack(void) } coredevice_initcall(riscv_request_stack); -static struct device_d timer_dev; -static struct device_d serial_sbi_dev; +static struct device timer_dev; +static struct device serial_sbi_dev; static s64 hartid; @@ -60,14 +60,14 @@ static int riscv_fixup_cpus(struct device_node *root, void *context) return 0; } -static int riscv_probe(struct device_d *parent) +static int riscv_probe(struct device *parent) { int ret; /* Each hart has a timer, but we only need one */ if (IS_ENABLED(CONFIG_RISCV_TIMER) && !timer_dev.parent) { timer_dev.id = DEVICE_ID_SINGLE; - timer_dev.device_node = parent->device_node; + timer_dev.of_node = parent->of_node; timer_dev.parent = parent; dev_set_name(&timer_dev, "riscv-timer"); @@ -78,7 +78,7 @@ static int riscv_probe(struct device_d *parent) if (IS_ENABLED(CONFIG_SERIAL_SBI) && !serial_sbi_dev.parent) { serial_sbi_dev.id = DEVICE_ID_SINGLE; - serial_sbi_dev.device_node = 0; + serial_sbi_dev.of_node = 0; serial_sbi_dev.parent = parent; dev_set_name(&serial_sbi_dev, "riscv-serial-sbi"); @@ -98,8 +98,9 @@ static struct of_device_id riscv_dt_ids[] = { { .compatible = "riscv", }, { /* sentinel */ }, }; +MODULE_DEVICE_TABLE(of, riscv_dt_ids); -static struct driver_d riscv_driver = { +static struct driver riscv_driver = { .name = "riscv", .probe = riscv_probe, .of_compatible = riscv_dt_ids, diff --git a/arch/riscv/cpu/dma.c b/arch/riscv/cpu/dma.c index 5a4d714e5e..511170aaa4 100644 --- a/arch/riscv/cpu/dma.c +++ b/arch/riscv/cpu/dma.c @@ -52,23 +52,24 @@ void dma_set_ops(const struct dma_ops *ops) dma_ops = ops; } -void dma_sync_single_for_cpu(dma_addr_t address, size_t size, enum dma_data_direction dir) +void arch_sync_dma_for_cpu(void *vaddr, size_t size, + enum dma_data_direction dir) { - /* - * FIXME: This function needs a device argument to support non 1:1 mappings - */ + unsigned long start = (unsigned long)vaddr; + unsigned long end = start + size; + if (dir != DMA_TO_DEVICE) - dma_ops->inv_range(address, address + size); + dma_ops->inv_range(start, end); } -void dma_sync_single_for_device(dma_addr_t address, size_t size, enum dma_data_direction dir) +void arch_sync_dma_for_device(void *vaddr, size_t size, + enum dma_data_direction dir) { - /* - * FIXME: This function needs a device argument to support non 1:1 mappings - */ + unsigned long start = (unsigned long)vaddr; + unsigned long end = start + size; if (dir == DMA_FROM_DEVICE) - dma_ops->inv_range(address, address + size); + dma_ops->inv_range(start, end); else - dma_ops->flush_range(address, address + size); + dma_ops->flush_range(start, end); } diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 17d7d249e4..a3c8fbd9d0 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -10,4 +10,4 @@ pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \ pbl-$(CONFIG_BOARD_BEAGLEV) += jh7100-beaglev-starlight.dtb.o pbl-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux.dtb.o -clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts index 65694bfd24..3b82c16ff0 100644 --- a/arch/riscv/dts/hifive-unleashed-a00.dts +++ b/arch/riscv/dts/hifive-unleashed-a00.dts @@ -1,3 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 OR X11 */ #include <riscv/sifive/hifive-unleashed-a00.dts> + +/* probing on QEMU v5.2.0 triggers load access fault @0x10040014 */ +&qspi0 { status = "disabled"; }; +&qspi2 { status = "disabled"; }; diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts index b8793e9105..24a4c798a9 100644 --- a/arch/riscv/dts/hifive-unmatched-a00.dts +++ b/arch/riscv/dts/hifive-unmatched-a00.dts @@ -1,3 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 OR X11 */ #include <riscv/sifive/hifive-unmatched-a00.dts> + +/* probing on QEMU v5.2.0 triggers load access fault @0x10040014 */ +&qspi0 { status = "disabled"; }; +&qspi1 { status = "disabled"; }; +&spi0 { status = "disabled"; }; diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi index e3990582af..b11801553b 100644 --- a/arch/riscv/dts/jh7100.dtsi +++ b/arch/riscv/dts/jh7100.dtsi @@ -212,6 +212,7 @@ #clock-cells = <1>; compatible = "simple-bus"; ranges; + dma-noncoherent; intram0: sram@18000000 { compatible = "mmio-sram"; diff --git a/arch/riscv/include/asm/barebox.lds.h b/arch/riscv/include/asm/barebox.lds.h new file mode 100644 index 0000000000..0fa05df6ff --- /dev/null +++ b/arch/riscv/include/asm/barebox.lds.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BAREBOX_OUTPUT_ARCH "riscv" +#ifdef CONFIG_64BIT +#define BAREBOX_OUTPUT_FORMAT "elf64-littleriscv" +#else +#define BAREBOX_OUTPUT_FORMAT "elf32-littleriscv" +#endif + +#include <asm-generic/barebox.lds.h> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9a0b9326b2..c787f89001 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -6,10 +6,29 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#include <asm/vendorid_list.h> + +static inline void thead_local_flush_icache_all(void) +{ + /* + * According [1] "13.3 Example of cache settings" + * [1]: https://github.com/T-head-Semi/openc906/blob/main/ \ + * doc/openc906%20datasheet.pd + */ + __asm__ volatile (".long 0x0100000b" ::: "memory"); /* th.icache.iall */ + __asm__ volatile (".long 0x01b0000b" ::: "memory"); /* th.sync.is */ +} + static inline void local_flush_icache_all(void) { -#ifdef HAS_CACHE - asm volatile ("fence.i" ::: "memory"); +#ifdef CONFIG_HAS_CACHE + switch(riscv_vendor_id()) { + case THEAD_VENDOR_ID: + thead_local_flush_icache_all(); + break; + default: + __asm__ volatile ("fence.i" ::: "memory"); + } #endif } diff --git a/arch/riscv/include/asm/debug_ll.h b/arch/riscv/include/asm/debug_ll.h index de9bc5f5fd..34294b09dd 100644 --- a/arch/riscv/include/asm/debug_ll.h +++ b/arch/riscv/include/asm/debug_ll.h @@ -29,6 +29,11 @@ #define DEBUG_LL_UART_CLK (58982400 / 16) #define DEBUG_LL_UART_SHIFT 0 #define DEBUG_LL_UART_IOSIZE8 +#elif defined CONFIG_DEBUG_SUN20I +#define DEBUG_LL_UART_ADDR 0x2500000 +#define DEBUG_LL_UART_CLK (24000000 / 16) +#define DEBUG_LL_UART_SHIFT 2 +#define DEBUG_LL_UART_IOSIZE32 #endif #define DEBUG_LL_UART_BPS CONFIG_BAUDRATE diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h index 6673648bcd..cea039cc5e 100644 --- a/arch/riscv/include/asm/sections.h +++ b/arch/riscv/include/asm/sections.h @@ -6,6 +6,7 @@ #include <asm-generic/sections.h> #include <linux/types.h> #include <asm/unaligned.h> +#include <asm/reloc.h> extern char __rel_dyn_start[]; extern char __rel_dyn_end[]; @@ -19,7 +20,7 @@ unsigned long get_runtime_offset(void); static inline unsigned int input_data_len(void) { - return get_unaligned((const u32 *)(input_data_end + get_runtime_offset() - 4)); + return get_unaligned((const u32 *)runtime_address(input_data_end) - 1); } #endif diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h index adf856f9e9..f0b6bf2945 100644 --- a/arch/riscv/include/asm/system.h +++ b/arch/riscv/include/asm/system.h @@ -5,6 +5,8 @@ #ifndef __ASSEMBLY__ +#include <asm/sbi.h> + #define RISCV_MODE_MASK 0x3 enum riscv_mode { RISCV_U_MODE = 0, @@ -13,7 +15,39 @@ enum riscv_mode { RISCV_M_MODE = 3, }; -static inline enum riscv_mode __riscv_mode(u32 flags) +static inline void riscv_set_flags(unsigned flags) +{ + switch (flags & RISCV_MODE_MASK) { + case RISCV_S_MODE: + __asm__ volatile("csrw sscratch, %0" : : "r"(flags)); + break; + case RISCV_M_MODE: + __asm__ volatile("csrw mscratch, %0" : : "r"(flags)); + break; + default: + /* Other modes are not implemented yet */ + break; + } +} + +static inline u32 riscv_get_flags(void) +{ + u32 flags = 0; + + if (IS_ENABLED(CONFIG_RISCV_S_MODE)) + __asm__ volatile("csrr %0, sscratch" : "=r"(flags)); + + /* + * Since we always set the scratch register on the very beginning, a + * empty flags indicates that we are running in M-mode. + */ + if (!flags) + __asm__ volatile("csrr %0, mscratch" : "=r"(flags)); + + return flags; +} + +static inline enum riscv_mode riscv_mode(void) { /* allow non-LTO builds to discard code for unused modes */ if (!IS_ENABLED(CONFIG_RISCV_MULTI_MODE)) { @@ -23,14 +57,14 @@ static inline enum riscv_mode __riscv_mode(u32 flags) return RISCV_S_MODE; } - return flags & RISCV_MODE_MASK; + return riscv_get_flags() & RISCV_MODE_MASK; } -static inline long __riscv_hartid(u32 flags) +static inline long riscv_hartid(void) { long hartid = -1; - switch (__riscv_mode(flags)) { + switch (riscv_mode()) { case RISCV_S_MODE: __asm__ volatile("mv %0, tp\n" : "=r"(hartid) :); break; @@ -42,19 +76,29 @@ static inline long __riscv_hartid(u32 flags) return hartid; } -#ifndef __PBL__ -extern unsigned barebox_riscv_pbl_flags; - -static inline enum riscv_mode riscv_mode(void) +static inline long riscv_vendor_id(void) { - return __riscv_mode(barebox_riscv_pbl_flags); -} + struct sbiret ret; + long id; -static inline long riscv_hartid(void) -{ - return __riscv_hartid(barebox_riscv_pbl_flags); + switch (riscv_mode()) { + case RISCV_M_MODE: + __asm__ volatile("csrr %0, mvendorid\n" : "=r"(id)); + return id; + case RISCV_S_MODE: + /* + * We need to use the sbi_ecall() since it can be that we got + * called without a working stack + */ + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, + 0, 0, 0, 0, 0, 0); + if (!ret.error) + return ret.value; + return -1; + default: + return -1; + } } -#endif #endif diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h new file mode 100644 index 0000000000..cb89af3f07 --- /dev/null +++ b/arch/riscv/include/asm/vendorid_list.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 SiFive + */ +#ifndef ASM_VENDOR_LIST_H +#define ASM_VENDOR_LIST_H + +#define SIFIVE_VENDOR_ID 0x489 +#define THEAD_VENDOR_ID 0x5b7 + +#endif diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h new file mode 100644 index 0000000000..74f077d38f --- /dev/null +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2012 Regents of the University of California + * + * Derived from arch/x86/include/asm/word-at-a-time.h + */ + +#ifndef _ASM_RISCV_WORD_AT_A_TIME_H +#define _ASM_RISCV_WORD_AT_A_TIME_H + + +#include <linux/kernel.h> +#include <linux/bitops.h> + +struct word_at_a_time { + const unsigned long one_bits, high_bits; +}; + +#define WORD_AT_A_TIME_CONSTANTS { REPEAT_BYTE(0x01), REPEAT_BYTE(0x80) } + +static inline unsigned long has_zero(unsigned long val, + unsigned long *bits, const struct word_at_a_time *c) +{ + unsigned long mask = ((val - c->one_bits) & ~val) & c->high_bits; + *bits = mask; + return mask; +} + +static inline unsigned long prep_zero_mask(unsigned long val, + unsigned long bits, const struct word_at_a_time *c) +{ + return bits; +} + +static inline unsigned long create_zero_mask(unsigned long bits) +{ + bits = (bits - 1) & ~bits; + return bits >> 7; +} + +static inline unsigned long find_zero(unsigned long mask) +{ + return fls64(mask) >> 3; +} + +/* The mask we created is directly usable as a bytemask */ +#define zero_bytemask(mask) (mask) + +#endif /* _ASM_RISCV_WORD_AT_A_TIME_H */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index f3db5320f7..6932480800 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -4,7 +4,7 @@ extra-y += barebox.lds obj-y += dtb.o obj-pbl-y += sections.o setupc.o reloc.o sections.o runtime-offset.o -obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o longjmp.o +obj-$(CONFIG_ARCH_HAS_SJLJ) += setjmp.o longjmp.o obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o obj-$(CONFIG_RISCV_SBI) += sbi.o obj-$(CONFIG_CMD_RISCV_CPUINFO) += cpuinfo.o diff --git a/arch/riscv/lib/barebox.lds.S b/arch/riscv/lib/barebox.lds.S index 7856b57a52..101615ab05 100644 --- a/arch/riscv/lib/barebox.lds.S +++ b/arch/riscv/lib/barebox.lds.S @@ -11,15 +11,11 @@ * */ -#include <asm-generic/barebox.lds.h> +#include <asm/barebox.lds.h> -OUTPUT_ARCH(riscv) +OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH) ENTRY(start) -#ifdef CONFIG_64BIT -OUTPUT_FORMAT("elf64-littleriscv") -#else -OUTPUT_FORMAT("elf32-littleriscv") -#endif +OUTPUT_FORMAT(BAREBOX_OUTPUT_FORMAT) SECTIONS { . = 0x0; diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 6984f282be..a6655b8aaf 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -36,6 +36,12 @@ static struct image_handler riscv_linux_handler = { .filetype = filetype_riscv_linux_image, }; +static struct image_handler riscv_linux_efi_handler = { + .name = "RISC-V Linux/EFI image", + .bootm = do_bootm_linux, + .filetype = filetype_riscv_efi_linux_image, +}; + static struct image_handler riscv_fit_handler = { .name = "FIT image", .bootm = do_bootm_linux, @@ -51,6 +57,7 @@ static struct image_handler riscv_barebox_handler = { static int riscv_register_image_handler(void) { register_image_handler(&riscv_linux_handler); + register_image_handler(&riscv_linux_efi_handler); register_image_handler(&riscv_barebox_handler); if (IS_ENABLED(CONFIG_FITIMAGE)) diff --git a/arch/riscv/lib/pbl.lds.S b/arch/riscv/lib/pbl.lds.S index e238b2bfd3..0fe7dfda8e 100644 --- a/arch/riscv/lib/pbl.lds.S +++ b/arch/riscv/lib/pbl.lds.S @@ -2,15 +2,11 @@ /* SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */ #include <linux/sizes.h> -#include <asm-generic/barebox.lds.h> +#include <asm/barebox.lds.h> #include <asm-generic/memory_layout.h> -OUTPUT_ARCH(riscv) -#ifdef CONFIG_64BIT -OUTPUT_FORMAT("elf64-littleriscv") -#else -OUTPUT_FORMAT("elf32-littleriscv") -#endif +OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH) +OUTPUT_FORMAT(BAREBOX_OUTPUT_FORMAT) SECTIONS { . = 0x0; @@ -74,8 +70,6 @@ SECTIONS .piggydata : { *(.piggydata) } - __piggydata_end = .; - .image_end : { KEEP(*(.__image_end)) } pbl_image_size = .; diff --git a/arch/riscv/lib/reloc.c b/arch/riscv/lib/reloc.c index da53c50448..0c1ec8b488 100644 --- a/arch/riscv/lib/reloc.c +++ b/arch/riscv/lib/reloc.c @@ -42,9 +42,13 @@ void relocate_to_current_adr(void) if (!offset) return; - dstart = __rel_dyn_start + offset; - dend = __rel_dyn_end + offset; - dynsym = (void *)__dynsym_start + offset; + /* + * We have yet to relocate, so using runtime_address + * to compute the relocated address + */ + dstart = runtime_address(__rel_dyn_start); + dend = runtime_address(__rel_dyn_end); + dynsym = runtime_address(__dynsym_start); for (rela = dstart; (void *)rela < dend; rela++) { unsigned long *fixup; @@ -66,7 +70,7 @@ void relocate_to_current_adr(void) putc_ll(' '); puthex_ll(rela->r_addend); putc_ll('\n'); - panic(""); + __hang(); } } |