diff options
Diffstat (limited to 'arch')
316 files changed, 17760 insertions, 40 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ac8459c7d7..8b4d64c268 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -118,7 +118,7 @@ maketools: PHONY += maketools ifneq ($(board-y),) -BOARD := board/$(board-y)/ +BOARD := arch/arm/boards/$(board-y)/ else BOARD := endif diff --git a/arch/arm/boards/a9m2410/Makefile b/arch/arm/boards/a9m2410/Makefile new file mode 100644 index 0000000000..63026f08b2 --- /dev/null +++ b/arch/arm/boards/a9m2410/Makefile @@ -0,0 +1,3 @@ + +obj-y += lowlevel_init.o +obj-y += a9m2410.o diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c new file mode 100644 index 0000000000..f327f82b7f --- /dev/null +++ b/arch/arm/boards/a9m2410/a9m2410.c @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2009 Juergen Beisert, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/** + * @file + * @brief a9m2410 Specific Board Initialization routines + * + */ + +#include <common.h> +#include <driver.h> +#include <init.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <partition.h> +#include <nand.h> +#include <asm/io.h> +#include <mach/s3c24x0-iomap.h> +#include <mach/s3c24x0-nand.h> + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "ram", + .map_base = CS6_BASE, + .platform_data = &ram_pdata, +}; + +// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, +static struct s3c24x0_nand_platform_data nand_info = { + .nand_timing = CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1) +}; + +static struct device_d nand_dev = { + .name = "s3c24x0_nand", + .map_base = S3C24X0_NAND_BASE, + .platform_data = &nand_info, +}; + +/* + * SMSC 91C111 network controller on the baseboard + * connected to CS line 1 and interrupt line + * GPIO3, data width is 32 bit + */ +static struct device_d network_dev = { + .name = "smc91c111", + .map_base = CS1_BASE + 0x300, + .size = 16, +}; + +static int a9m2410_devices_init(void) +{ + uint32_t reg; + + /* + * detect the current memory size + * Note: On this card the second SDRAM page is not used + */ + reg = readl(BANKSIZE); + + switch (reg &= 0x7) { + case 0: + sdram_dev.size = 32 * 1024 * 1024; + break; + case 1: + sdram_dev.size = 64 * 1024 * 1024; + break; + case 2: + sdram_dev.size = 128 * 1024 * 1024; + break; + case 4: + sdram_dev.size = 2 * 1024 * 1024; + break; + case 5: + sdram_dev.size = 4 * 1024 * 1024; + break; + case 6: + sdram_dev.size = 8 * 1024 * 1024; + break; + case 7: + sdram_dev.size = 16 * 1024 * 1024; + break; + } + + /* ---------- configure the GPIOs ------------- */ + writel(0x007FFFFF, GPACON); + writel(0x00000000, GPCCON); + writel(0x00000000, GPCUP); + writel(0x00000000, GPDCON); + writel(0x00000000, GPDUP); + writel(0xAAAAAAAA, GPECON); + writel(0x0000E03F, GPEUP); + writel(0x00000000, GPBCON); /* all inputs */ + writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */ + writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */ + writel(0x000000FF, GPFUP); + writel(readl(GPGDAT) | 0x0010, GPGDAT); /* switch off LCD backlight */ + writel(0xFF00A938, GPGCON); /* switch off USB device */ + writel(0x0000F000, GPGUP); + writel(readl(GPHDAT) | 0x100, GPHDAT); /* switch BOOTINT/GPIO_ON# to high */ + writel(0x000007FF, GPHUP); + writel(0x0029FAAA, GPHCON); + /* + * USB port1 normal, USB port0 normal, USB1 pads for device + * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1, + * 2nd SDRAM bank off (only bank 1 is used) + */ + writel(0x40140, MISCCR); + + /* ----------- configure the access to the outer space ---------- */ + reg = readl(BWSCON); + + /* CS#1 to access the network controller */ + reg &= ~0xf0; + reg |= 0xe0; + writel(0x1350, BANKCON1); + + /* CS#2 to the dual 16550 UART */ + reg &= ~0xf00; + reg |= 0x400; + writel(0x0d50, BANKCON2); + + writel(reg, BWSCON); + + /* release the reset signal to the network and UART device */ + reg = readl(MISCCR); + reg |= 0x10000; + writel(reg, MISCCR); + + /* ----------- the devices the boot loader should work with -------- */ + register_device(&nand_dev); + register_device(&sdram_dev); + register_device(&network_dev); + +#ifdef CONFIG_NAND + /* ----------- add some vital partitions -------- */ + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); +#endif + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100); + armlinux_set_architecture(MACH_TYPE_A9M2410); + + return 0; +} + +device_initcall(a9m2410_devices_init); + +#ifdef CONFIG_S3C24XX_NAND_BOOT +void __bare_init nand_boot(void) +{ + s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512); +} +#endif + +static struct device_d a9m2410_serial_device = { + .name = "s3c24x0_serial", + .map_base = UART1_BASE, + .size = UART1_SIZE, +}; + +static int a9m2410_console_init(void) +{ + register_device(&a9m2410_serial_device); + return 0; +} + +console_initcall(a9m2410_console_init); + +/** @page a9m2410 DIGI's a9m2410 + +This CPU card is based on a Samsung S3C2410 CPU. The card is shipped with: + +- S3C2410\@200 MHz (ARM920T/ARMv4T) +- 12MHz crystal reference +- SDRAM 32 MiB + - Samsung K4M563233E-EE1H + - 2M x 32Bit x 4 Banks Mobile SDRAM + - 90 pin FBGA + - CL3\@133MHz, CL2\@100MHz (CAS/RAS delay 19ns) + - four banks + - 32 bit data bits + - row address size is 11 + - Row cycle time: 69ns + - collumn address size is 9 bits + - Extended temperature range (-25°C...85°C) + - 64ms refresh period (4k) +- NAND Flash 32 MiB + - Samsung KM29U256T + - 32MiB 3,3V 8-bit + - ID: 0xEC, 0x75, 0x??, 0xBD + - 30ns/40ns/20ns +- I2C interface, 100KHz and 400KHz + - Real Time Clock + - Dallas DS1337 + - address 0x68 + - EEPROM + - ST M24LC64 + - address 0x50 + - 16bit addressing +- LCD interface +- Touch Screen interface +- Camera interface +- I2S interface +- AC97 Audio-CODEC interface +- SD card interface +- 3 serial RS232 interfaces +- Host and device USB interface, USB1.1 compliant +- Ethernet interface + - 10Mbps, Cirrus Logic, CS8900A (on the CPU card) or + - 10/100Mbps, SMSC 91C111 (on the baseboard) +- SPI interface +- JTAG interface + +How to get the binary image: + +Using the default configuration: + +@code +make ARCH=arm a9m2410_defconfig +@endcode + +Build the binary image: + +@code +make ARCH=arm CROSS_COMPILE=armv4compiler +@endcode + +@note replace the armv4compiler with your ARM v4 cross compiler. +*/ diff --git a/arch/arm/boards/a9m2410/config.h b/arch/arm/boards/a9m2410/config.h new file mode 100644 index 0000000000..87b05fc55d --- /dev/null +++ b/arch/arm/boards/a9m2410/config.h @@ -0,0 +1,122 @@ +/** + * @file + * @brief Global defintions for the ARM S3C2410 based a9m2410 CPU card + */ +/* This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/** + * The external clock reference is a 12.0MHz crystal + */ +#define S3C24XX_CLOCK_REFERENCE 12000000 + +/** + * Define the main clock configuration to be used in register CLKDIVN + * + * We must limit the frequency of the connected SDRAMs with the clock ratio + * setup to 1:2:4. This will result into FCLK:HCLK:PCLK = 200Mhz:100MHz:50MHz + */ +#define BOARD_SPECIFIC_CLKDIVN 0x003 + +/** + * Define the MPLL configuration to be used in register MPLLCON + * + * We want the MPLL to run at 202.80MHz + */ +#define BOARD_SPECIFIC_MPLL ((0xA1 << 12) + (3 << 4) + 1) + +/** + * Define the UPLL configuration to be used in register UPLLCON + * + * We want the UPLL to run at 48.0MHz + */ +#define BOARD_SPECIFIC_UPLL ((0x78 << 12) + (2 << 4) + 3) + +/* + * SDRAM configuration for Samsung K4M563233E + * - 2M x 32Bit x 4 Banks Mobile SDRAM + * - 90 pin FBGA + * - CL2@100MHz + */ +/* + * SDRAM uses 32bit width + */ +#define BOARD_SPECIFIC_BWSCON ((0x02 << 24) + (0x02 << 28)) +/* + * 32MiB SDRAM in bank6 + * - MT = 11 (= sync dram type) + * - Trcd = 00 (= CL2) + * - SCAN = 01 (= 9 bit collumns) + */ +#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + 0x1) +/* + * No memory in bank7 + */ +#define BOARD_SPECIFIC_BANKCON7 ((0x3 << 15) + (0x0 << 2) + 0x1) +/* + * SDRAM refresh settings + * - REFEN = 1 (= refresh enabled) + * - TREFMD = 0 (= auto refresh) + * - Trp = 00 (= 2 RAS precharge clocks) + * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) + * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489 + */ +#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489) +/* + * SDRAM banksize + * - BURST_EN = 1 (= burst mode enabled) + * - SCKE_EN = 1 (= SDRAM SCKE enabled) + * - SCLK_EN = 1 (= clock active only during accesses) + * - BK67MAP = 000 (= 32MiB) + */ +#define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (0 << 4) + 0) +/* + * SDRAM mode register bank6 + * CL = 010 (= 2 clocks) + */ +#define BOARD_SPECIFIC_MRSRB6 (0x2 << 4) +/* + * SDRAM mode register bank7 + * CL = 010 (= 2 clocks) + */ +#define BOARD_SPECIFIC_MRSRB7 (0x2 << 4) + +/* + * Flash access timings + * Tacls = 0ns (but 20ns data setup time) + * Twrph0 = 25ns (write) 35ns (read) + * Twrph1 = 10ns (10ns data hold time) + * Read cycle time = 50ns + * + * Assumed HCLK is 100MHz + * Tacls = 1 (-> 20ns) + * Twrph0 = 3 (-> 40ns) + * Twrph1 = 1 (-> 20ns) + * Cycle time = 80ns + */ +#define A9M2410_TACLS 1 +#define A9M2410_TWRPH0 3 +#define A9M2410_TWRPH1 1 + +/* needed in the generic NAND boot code only */ +#ifdef CONFIG_S3C24XX_NAND_BOOT +# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1) +#endif + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/a9m2410/env/bin/_update b/arch/arm/boards/a9m2410/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/a9m2410/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/a9m2410/env/bin/boot b/arch/arm/boards/a9m2410/env/bin/boot new file mode 100644 index 0000000000..59fa60e4e9 --- /dev/null +++ b/arch/arm/boards/a9m2410/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\"" + +if [ x$kernel = xnet ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/a9m2410/env/bin/hush_hack b/arch/arm/boards/a9m2410/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/a9m2410/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/a9m2410/env/bin/init b/arch/arm/boards/a9m2410/env/bin/init new file mode 100644 index 0000000000..5ae44dd455 --- /dev/null +++ b/arch/arm/boards/a9m2410/env/bin/init @@ -0,0 +1,34 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type update_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/a9m2410/env/bin/update_kernel b/arch/arm/boards/a9m2410/env/bin/update_kernel new file mode 100644 index 0000000000..c43a55785b --- /dev/null +++ b/arch/arm/boards/a9m2410/env/bin/update_kernel @@ -0,0 +1,13 @@ +#!/bin/sh + +. /env/config + +part=/dev/nand0.kernel.bb + +if [ x$1 = x ]; then + image=$uimage +else + image=$1 +fi + +. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2410/env/bin/update_root b/arch/arm/boards/a9m2410/env/bin/update_root new file mode 100644 index 0000000000..34139e5dce --- /dev/null +++ b/arch/arm/boards/a9m2410/env/bin/update_root @@ -0,0 +1,11 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = x ]; then + image=$jffs2 +else + image=$1 +fi + +. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2410/env/config b/arch/arm/boards/a9m2410/env/config new file mode 100644 index 0000000000..79150ce017 --- /dev/null +++ b/arch/arm/boards/a9m2410/env/config @@ -0,0 +1,26 @@ +#!/bin/sh + +# can be either 'net' or 'nand'' +kernel=net +root=net + +uimage=uImage-a9m2410 +jffs2=root-a9m2410.jffs2 + +autoboot_timeout=3 + +nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2410/root" +bootargs="console=ttySAC0,38400" + +nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" +rootpart_nand="/dev/mtdblock3" + +# use 'dhcp' to do dhcp in barebox and in kernel +#ip=dhcp + +# or set your networking parameters here +eth0.ipaddr=192.168.42.31 +eth0.netmask=255.255.0.0 +eth0.gateway=192.168.23.1 +eth0.serverip=192.168.23.2 +eth0.ethaddr=00:04:f3:00:06:35 diff --git a/arch/arm/boards/a9m2410/lowlevel_init.S b/arch/arm/boards/a9m2410/lowlevel_init.S new file mode 100644 index 0000000000..461b93c3f1 --- /dev/null +++ b/arch/arm/boards/a9m2410/lowlevel_init.S @@ -0,0 +1,37 @@ +/* + * + */ + +#include <config.h> +#include <mach/s3c24x0-iomap.h> + + .section ".text_bare_init.board_init_lowlevel","ax" + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr /* save the link register */ + + bl s3c24x0_disable_wd + + /* skip everything here if we are already running from SDRAM */ + cmp pc, #S3C24X0_SDRAM_BASE + blo 1f + cmp pc, #S3C24X0_SDRAM_END + bhs 1f + + mov pc, r10 + +/* we are running from NOR or NAND/SRAM memory. Do further initialisation */ +1: + bl s3c24x0_pll_init + + bl s3c24x0_sdram_init + +#ifdef CONFIG_S3C24XX_NAND_BOOT + mov lr, r10 /* restore the link register */ +/* up to here we are running from the internal SRAM area */ + b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */ +#else + mov pc, r10 +#endif diff --git a/arch/arm/boards/a9m2440/Makefile b/arch/arm/boards/a9m2440/Makefile new file mode 100644 index 0000000000..779e83dc03 --- /dev/null +++ b/arch/arm/boards/a9m2440/Makefile @@ -0,0 +1,4 @@ + +obj-y += lowlevel_init.o +obj-y += a9m2440.o +obj-$(CONFIG_MACH_A9M2410DEV) += a9m2410dev.o diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c new file mode 100644 index 0000000000..1220bd9777 --- /dev/null +++ b/arch/arm/boards/a9m2440/a9m2410dev.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2009 Juergen Beisert + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/** + * @file + * @brief a9m2410dev Baseboad specific initialization routines + * + */ + +#include <common.h> +#include <driver.h> +#include <init.h> +#include <asm/io.h> +#include <mach/s3c24x0-iomap.h> + +/** + * Initialize the CPU to be able to work with the a9m2410dev evaluation board + */ +int a9m2410dev_devices_init(void) +{ + unsigned int reg; + + /* ---------- configure the GPIOs ------------- */ + writel(0x007FFFFF, GPACON); + writel(0x00000000, GPCCON); + writel(0x00000000, GPCUP); + writel(0x00000000, GPDCON); + writel(0x00000000, GPDUP); + writel(0xAAAAAAAA, GPECON); + writel(0x0000E03F, GPEUP); + writel(0x00000000, GPBCON); /* all inputs */ + writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */ + writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */ + writel(0x000000FF, GPFUP); + writel(readl(GPGDAT) | 0x1010, GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */ + writel(0x0100A93A, GPGCON); /* switch on USB device */ + writel(0x0000F000, GPGUP); + writel(0x0029FAAA, GPHCON); + + writel((1 << 12) | (0 << 11), GPJDAT); + writel(0x0016aaaa, GPJCON); + writel(~((0<<12)| (1<<11)), GPJUP); + + writel((0 << 12) | (0 << 11), GPJDAT); + writel(0x0016aaaa, GPJCON); + writel(0x00001fff, GPJUP); + + writel(0x00000000, DSC0); + writel(0x00000000, DSC1); + + /* + * USB port1 normal, USB port0 normal, USB1 pads for device + * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1, + */ + writel((readl(MISCCR) & ~0xFFFF) | 0x0140, MISCCR); + + /* ----------- configure the access to the outer space ---------- */ + reg = readl(BWSCON); + + /* CS#1 to access the network controller */ + reg &= ~0xf0; + reg |= 0xe0; + writel(0x1350, BANKCON1); + + /* CS#2 to the dual 16550 UART */ + reg &= ~0xf00; + reg |= 0x400; + writel(0x0d50, BANKCON2); + + writel(reg, BWSCON); + + /* release the reset signal to the network and UART device */ + reg = readl(MISCCR); + reg |= 0x10000; + writel(reg, MISCCR); + + return 0; +} diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c new file mode 100644 index 0000000000..2567f5ed13 --- /dev/null +++ b/arch/arm/boards/a9m2440/a9m2440.c @@ -0,0 +1,271 @@ +/* + * Copyright (C) 2009 Juergen Beisert, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/** + * @file + * @brief a9m2440 Specific Board Initialization routines + * + */ + +#include <common.h> +#include <driver.h> +#include <init.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <partition.h> +#include <nand.h> +#include <asm/io.h> +#include <mach/s3c24x0-iomap.h> +#include <mach/s3c24x0-nand.h> +#include <mach/s3c24xx-generic.h> + +#include "baseboards.h" + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = CS6_BASE, + .platform_data = &ram_pdata, +}; + +static struct s3c24x0_nand_platform_data nand_info = { + .nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1) +}; + +static struct device_d nand_dev = { + .name = "s3c24x0_nand", + .map_base = S3C24X0_NAND_BASE, + .platform_data = &nand_info, +}; + +/* + * cs8900 network controller onboard + * Connected to CS line 5 + A24 and interrupt line EINT9, + * data width is 16 bit + */ +static struct device_d network_dev = { + .name = "cs8900", + .map_base = CS5_BASE + (1 << 24) + 0x300, + .size = 16, +}; + +static int a9m2440_check_for_ram(uint32_t addr) +{ + uint32_t tmp1, tmp2; + int rc = 0; + + tmp1 = readl(addr); + tmp2 = readl(addr + sizeof(uint32_t)); + + writel(0xaaaaaaaa, addr); + writel(0x55555555, addr + sizeof(uint32_t)); + if ((readl(addr) != 0xaaaaaaaa) || (readl(addr + sizeof(uint32_t)) != 0x55555555)) + rc = 1; /* seems no RAM */ + + writel(0x55555555, addr); + writel(0xaaaaaaaa, addr + sizeof(uint32_t)); + if ((readl(addr) != 0x55555555) || (readl(addr + sizeof(uint32_t)) != 0xaaaaaaaa)) + rc = 1; /* seems no RAM */ + + writel(tmp1, addr); + writel(tmp2, addr + sizeof(uint32_t)); + + return rc; +} + +static void a9m2440_disable_second_sdram_bank(void) +{ + writel(readl(BANKCON7) & ~(0x3 << 15),BANKCON7); + writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable clock */ +} + +static int a9m2440_devices_init(void) +{ + uint32_t reg; + + /* + * The special SDRAM setup code for this machine will always enable + * both SDRAM banks. But the second SDRAM device may not exists! + * So we must check here, if the second bank is populated to get the + * correct RAM size. + */ + switch (readl(BANKSIZE) & 0x7) { + case 0: + if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 32 * 1024 * 1024)) + a9m2440_disable_second_sdram_bank(); + break; + case 1: + if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 64 * 1024 * 1024)) + a9m2440_disable_second_sdram_bank(); + break; + case 2: + if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 128 * 1024 * 1024)) + a9m2440_disable_second_sdram_bank(); + break; + case 4: + case 5: + case 6: /* not supported on this machine */ + break; + default: + if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 16 * 1024 * 1024)) + a9m2440_disable_second_sdram_bank(); + break; + } + + sdram_dev.size = s3c24x0_get_memory_size(); + + /* ----------- configure the access to the outer space ---------- */ + reg = readl(BWSCON); + + /* CS#5 to access the network controller */ + reg &= ~0x00f00000; + reg |= 0x00d00000; /* 16 bit */ + writel(0x1f4c, BANKCON5); + + writel(reg, BWSCON); + +#ifdef CONFIG_MACH_A9M2410DEV + a9m2410dev_devices_init(); +#endif + + /* release the reset signal to external devices */ + reg = readl(MISCCR); + reg |= 0x10000; + writel(reg, MISCCR); + + /* ----------- the devices the boot loader should work with -------- */ + register_device(&nand_dev); + register_device(&sdram_dev); + register_device(&network_dev); + +#ifdef CONFIG_NAND + /* ----------- add some vital partitions -------- */ + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); +#endif + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100); + armlinux_set_architecture(MACH_TYPE_A9M2440); + + return 0; +} + +device_initcall(a9m2440_devices_init); + +#ifdef CONFIG_S3C24XX_NAND_BOOT +void __bare_init nand_boot(void) +{ + s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512); +} +#endif + +static struct device_d a9m2440_serial_device = { + .name = "s3c24x0_serial", + .map_base = UART1_BASE, + .size = UART1_SIZE, +}; + +static int a9m2440_console_init(void) +{ + register_device(&a9m2440_serial_device); + return 0; +} + +console_initcall(a9m2440_console_init); + +/** @page a9m2440 DIGI's a9m2440 + +This CPU card is based on a Samsung S3C2440 CPU. The card is shipped with: + +- S3C2440\@400 MHz or 533 MHz (ARM920T/ARMv4T) +- 16.9344 MHz crystal reference +- SDRAM 32/64/128 MiB + - Samsung K4M563233E-EE1H (one or two devices for 32 MiB or 64 MiB) + - 2M x 32bit x 4 Banks Mobile SDRAM + - CL2\@100 MHz (CAS/RAS delay 19ns) + - 105 MHz max + - collumn address size is 9 bits + - Row cycle time: 69ns + - Samsung K4M513233C-DG75 (one or two devices for 64 MiB or 128 MiB) + - 4M x 32bit x 4 Banks Mobile SDRAM + - CL2\@100MHz (CAS/RAS delay 18ns) + - 111 MHz max + - collumn address size is 9 bits + - Row cycle time: 63ns + - 64ms refresh period (4k) + - 90 pin FBGA + - 32 bit data bits + - Extended temperature range (-25°C...85°C) +- NAND Flash 32/64/128 MiB + - Samsung KM29U512T (NAND01GW3A0AN6) + - 64 MiB 3,3V 8-bit + - ID: 0xEC, 0x76, 0x??, 0xBD + - Samsung KM29U256T + - 32 MiB 3,3V 8-bit + - ID: 0xEC, 0x75, 0x??, 0xBD + - ST Micro + - 128 MiB 3,3V 8-bit + - ID: 0x20, 0x79 + - 30ns/40ns/20ns +- I2C interface, 100 KHz and 400 KHz + - Real Time Clock + - Dallas DS1337 + - address 0x68 + - EEPROM + - ST M24LC64 + - address 0x50 + - 16bit addressing +- LCD interface +- Touch Screen interface +- Camera interface +- I2S interface +- AC97 Audio-CODEC interface +- SD card interface +- 3 serial RS232 interfaces +- Host and device USB interface, USB1.1 compliant +- Ethernet interface + - 10Mbps, Cirrus Logic, CS8900A (on the CPU card) +- SPI interface +- JTAG interface + +How to get the binary image: + +Using the default configuration: + +@code +make ARCH=arm a9m2440_defconfig +@endcode + +Build the binary image: + +@code +make ARCH=arm CROSS_COMPILE=armv4compiler +@endcode + +@note replace the armv4compiler with your ARM v4 cross compiler. + +*/ diff --git a/arch/arm/boards/a9m2440/baseboards.h b/arch/arm/boards/a9m2440/baseboards.h new file mode 100644 index 0000000000..ec80312b69 --- /dev/null +++ b/arch/arm/boards/a9m2440/baseboards.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2009 Juergen Beisert + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifdef CONFIG_MACH_A9M2410DEV +extern int a9m2410dev_devices_init(void); +#endif diff --git a/arch/arm/boards/a9m2440/config.h b/arch/arm/boards/a9m2440/config.h new file mode 100644 index 0000000000..43cb6ab934 --- /dev/null +++ b/arch/arm/boards/a9m2440/config.h @@ -0,0 +1,73 @@ +/** + * @file + * @brief Global defintions for the ARM S3C2440 based a9m2440 CPU card + */ +/* This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/** + * The external clock reference is a 16.9344 MHz crystal + */ +#define S3C24XX_CLOCK_REFERENCE 16934400 + +/** + * Define the main clock configuration to be used in register CLKDIVN + * + * We must limit the frequency of the connected SDRAMs with the clock ratio + * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 400Mhz:100MHz:50MHz + */ +#define BOARD_SPECIFIC_CLKDIVN 0x05 + +/** + * Define the MPLL configuration to be used in register MPLLCON + * + * We want the MPLL to run at 399.65 MHz + */ +#define BOARD_SPECIFIC_MPLL ((0x6e << 12) + (3 << 4) + 1) + +/** + * Define the UPLL configuration to be used in register UPLLCON + * + * We want the UPLL to run at 47.98 MHz + */ +#define BOARD_SPECIFIC_UPLL ((0x3c << 12) + (4 << 4) + 2) + +/* + * Flash access timings + * Tacls = 0ns (but 20ns data setup time) + * Twrph0 = 25ns (write) 35ns (read) + * Twrph1 = 10ns (10ns data hold time) + * Read cycle time = 50ns + * + * Assumed HCLK is 100MHz + * Tacls = 1 (-> 20ns) + * Twrph0 = 3 (-> 40ns) + * Twrph1 = 1 (-> 20ns) + * Cycle time = 80ns + */ +#define A9M2440_TACLS 1 +#define A9M2440_TWRPH0 3 +#define A9M2440_TWRPH1 1 + +/* needed in the generic NAND boot code only */ +#ifdef CONFIG_S3C24XX_NAND_BOOT +# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1) +#endif + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/a9m2440/env/bin/_update b/arch/arm/boards/a9m2440/env/bin/_update new file mode 100644 index 0000000000..b10682ece4 --- /dev/null +++ b/arch/arm/boards/a9m2440/env/bin/_update @@ -0,0 +1,34 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/a9m2440/env/bin/boot b/arch/arm/boards/a9m2440/env/bin/boot new file mode 100644 index 0000000000..86e22cf9ff --- /dev/null +++ b/arch/arm/boards/a9m2440/env/bin/boot @@ -0,0 +1,40 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +fi +if [ x$root = xnet ]; then + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" + if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" + else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +fi + +bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\"" + +bootargs="$bootargs cs89x0_media=rj45 cs89x0_mac=$eth0.ethaddr" + +if [ x$kernel = xnet ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/a9m2440/env/bin/hush_hack b/arch/arm/boards/a9m2440/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/a9m2440/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/a9m2440/env/bin/init b/arch/arm/boards/a9m2440/env/bin/init new file mode 100644 index 0000000000..5ae44dd455 --- /dev/null +++ b/arch/arm/boards/a9m2440/env/bin/init @@ -0,0 +1,34 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type update_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/a9m2440/env/bin/update_kernel b/arch/arm/boards/a9m2440/env/bin/update_kernel new file mode 100644 index 0000000000..c43a55785b --- /dev/null +++ b/arch/arm/boards/a9m2440/env/bin/update_kernel @@ -0,0 +1,13 @@ +#!/bin/sh + +. /env/config + +part=/dev/nand0.kernel.bb + +if [ x$1 = x ]; then + image=$uimage +else + image=$1 +fi + +. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2440/env/bin/update_root b/arch/arm/boards/a9m2440/env/bin/update_root new file mode 100644 index 0000000000..46cbca5beb --- /dev/null +++ b/arch/arm/boards/a9m2440/env/bin/update_root @@ -0,0 +1,13 @@ +#!/bin/sh + +. /env/config + +part=/dev/nand0.root.bb + +if [ x$1 = x ]; then + image=$jffs2 +else + image=$1 +fi + +. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2440/env/config b/arch/arm/boards/a9m2440/env/config new file mode 100644 index 0000000000..936c35f9a9 --- /dev/null +++ b/arch/arm/boards/a9m2440/env/config @@ -0,0 +1,26 @@ +#!/bin/sh + +# can be either 'net' or 'nand'' +kernel=net +root=net + +uimage=uImage-a9m2440 +jffs2=root-a9m2440.jffs2 + +autoboot_timeout=3 + +nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2440/root" +bootargs="console=ttySAC0,38400" + +nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" +rootpart_nand="/dev/mtdblock3" + +# use 'dhcp' to do dhcp in barebox and in kernel +#ip=dhcp + +# or set your networking parameters here +eth0.ipaddr=192.168.42.32 +eth0.netmask=255.255.0.0 +eth0.gateway=192.168.23.1 +eth0.serverip=192.168.23.2 +eth0.ethaddr=00:04:f3:00:06:35 diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S new file mode 100644 index 0000000000..4b5c596076 --- /dev/null +++ b/arch/arm/boards/a9m2440/lowlevel_init.S @@ -0,0 +1,240 @@ +/* + * + */ + +#include <config.h> +#include <mach/s3c24x0-iomap.h> + + .section ".text_bare_init.board_init_lowlevel","ax" + +/* + * To be able to setup the SDRAM interface correctly, we need some + * external information about the connected SDRAM devices. + * + * When we set GPH8, we can read at GPB: + * Bit 0..1: Memory device size -> 00=16M, 01=64M, 10=32M, 11=128M + * Bit 2: CL setting + * + * Some remarks: The CL setting seems useless. It always signals a CL3 + * requirement, but the SDRAM types I found on the cards are supporting + * CL2 @ 100 MHz. But also these SDRAM types are only support 105 MHz max. + * So, we never need CL3 because we can't run the CPU at 533 MHz (which + * implies an 133 MHz SDRAM clock). + * All devices are connected via 32 bit databus + * + * Note: I was able to check the 32 MiB and 64 MiB configuration only. I didn't + * had access to a 16 MiB nor 128 MiB config. + * + */ + +sdram_init: + /* + * Read the configuration. After reset until any GPIO port is + * configured yet, these pins show external settings, to detect + * the SDRAM size. + */ + ldr r1, =GPBDAT + ldr r4, [r1] + and r4, r4, #0x3 + + ldr r1, =S3C24X0_MEMCTL_BASE + /* configure both SDRAM areas with 32 bit data bus width */ + ldr r0, =((0x2 << 24) + (0x2 << 28)) + str r0, [r1], #0x1c /* post add register offset for bank6 */ + + /* + * With the configuration we simply need to calculate an offset into + * our table with the predefined SDRAM settings + */ + adr r0, SDRAMDATA + mov r2, #6*4 /* # of bytes per table entry */ + mul r3, r4, r2 + add r0, r0, r3 /* start address of the entry */ + + /* + * store the table entry data into the registers + */ +1: + ldr r3, [r0], #4 + str r3, [r1], #4 + subs r2, r2, #4 + bne 1b + +/* TODO: Check if the second bank is populated, and switch it off if not */ + + mov pc, lr + +/* + * we need 4 sets of memory settings per main CPU clock speed + * + * 400MHz main speed: + * - 16 MiB in the first bank, maybe 16 MiB in the second bank (untested!) + * - 32 MiB in the first bank, maybe 32 MiB in the second bank (CL=2) + * - 64 MiB in the first bank, maybe 64 MiB in the second bank (CL=2) + * - 128 MiB in the first bank, maybe 128 MiB in the second bank (untested!) + * + * Note: SDRAM clock runs at 100MHz + */ + +SDRAMDATA: +/* --------------------------- 16 MiB @ 100MHz --------------------------- */ + /* + * - MT = 11 (= sync dram type) + * - Trcd = 01 (= CL3) + * - SCAN = 00 (= 8 bit collumns) + */ + .word ((0x3 << 15) + (0x1 << 2) + (0x0)) + .word ((0x3 << 15) + (0x1 << 2) + (0x0)) + /* + * SDRAM refresh settings + * - REFEN = 1 (= refresh enabled) + * - TREFMD = 0 (= auto refresh) + * - Trp = 00 (= 2 RAS precharge clocks) + * - Tsrc = 11 (= 7 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) + * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = FIXME + */ + .word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x3 << 18) + 468) + /* + * SDRAM banksize + * - BURST_EN = 0 (= burst mode disabled) + * - SCKE_EN = 1 (= SDRAM SCKE enabled) + * - SCLK_EN = 1 (= clock active only during accesses) + * - BK67MAP = 010 (= 128MiB) FIXME????? + */ + .word ((0 << 7) + (1 << 5) + (1 << 4) + 2) + /* + * SDRAM mode register + * CL = 010 (= 2 clocks) + */ + .word (0x2 << 4) + .word (0x2 << 4) + +/* ------------- one or two banks with 64 MiB @ 100MHz -------------------- */ + + /* + * - MT = 11 (= sync dram type) + * - Trcd = 00 (= CL2) + * - SCAN = 01 (= 9 bit collumns) + */ + .word ((0x3 << 15) + (0x0 << 2) + (0x1)) + .word ((0x3 << 15) + (0x0 << 2) + (0x1)) + /* + * SDRAM refresh settings + * - REFEN = 1 (= refresh enabled) + * - TREFMD = 0 (= auto refresh) + * - Trp = 00 (= 2 RAS precharge clocks) + * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) + * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489 + */ + .word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489) + /* + * SDRAM banksize + * - BURST_EN = 1 (= burst mode enabled) + * - SCKE_EN = 1 (= SDRAM SCKE enabled) + * - SCLK_EN = 1 (= clock active only during accesses) + * - BK67MAP = 001 (= 64 MiB) + */ + .word ((1 << 7) + (1 << 5) + (1 << 4) + 1) + /* + * SDRAM mode register + * CL = 010 (= 2 clocks) + */ + .word (0x2 << 4) + .word (0x2 << 4) + +/* ------------- one or two banks with 32 MiB @ 100MHz -------------------- */ + + /* + * - MT = 11 (= sync dram type) + * - Trcd = 00 (= CL2) + * - SCAN = 01 (= 9 bit collumns) + */ + .word ((0x3 << 15) + (0x0 << 2) + (0x1)) + .word ((0x3 << 15) + (0x0 << 2) + (0x1)) + /* + * SDRAM refresh settings + * - REFEN = 1 (= refresh enabled) + * - TREFMD = 0 (= auto refresh) + * - Trp = 00 (= 2 RAS precharge clocks) + * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) + * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489 + */ + .word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489) + /* + * SDRAM banksize + * - BURST_EN = 1 (= burst mode enabled) + * - SCKE_EN = 1 (= SDRAM SCKE enabled) + * - SCLK_EN = 1 (= clock active only during accesses) + * - BK67MAP = 000 (= 32 MiB) + */ + .word ((1 << 7) + (1 << 5) + (1 << 4) + 0) + /* + * SDRAM mode register + * CL = 010 (= 2 clocks) + */ + .word (0x2 << 4) + .word (0x2 << 4) + +/* ------------ one or two banks with 128 MiB @ 100MHz -------------------- */ + + /* + * - MT = 11 (= sync dram type) + * - Trcd = 00 (= CL2) + * - SCAN = 01 (= 9 bit collumns) + */ + .word ((0x3 << 15) + (0x0 << 2) + (0x1)) + .word ((0x3 << 15) + (0x0 << 2) + (0x1)) + /* + * SDRAM refresh settings + * - REFEN = 1 (= refresh enabled) + * - TREFMD = 0 (= auto refresh) + * - Trp = 00 (= 2 RAS precharge clocks) + * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) + * - Refrsh = 2^11 + 1 - 100 * 7.5 = 2049 - FIXME = 1259 + */ + .word ((0x1 << 23) + (0x0 << 22) + (0x1 << 20) + (0x3 << 18) + 1259) + /* + * SDRAM banksize + * - BURST_EN = 0 (= burst mode disabled) + * - SCKE_EN = 1 (= SDRAM SCKE enabled) + * - SCLK_EN = 1 (= clock active only during accesses) + * - BK67MAP = 010 (= 128MiB) + */ + .word (0x32) + /* + * SDRAM mode register + * CL = 010 (= 2 clocks) + */ + .word (0x2 << 4) + .word (0x2 << 4) + +/* ------------------------------------------------------------------------ */ + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr /* save the link register */ + + bl s3c24x0_disable_wd + + /* skip everything here if we are already running from SDRAM */ + cmp pc, #S3C24X0_SDRAM_BASE + blo 1f + cmp pc, #S3C24X0_SDRAM_END + bhs 1f + + mov pc, r10 + +/* we are running from NOR or NAND/SRAM memory. Do further initialisation */ +1: + bl s3c24x0_pll_init + + bl sdram_init + +#ifdef CONFIG_S3C24XX_NAND_BOOT + mov lr, r10 /* restore the link register */ +/* up to here we are running from the internal SRAM area */ + b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */ +#else + mov pc, r10 +#endif diff --git a/arch/arm/boards/at91sam9260ek/Makefile b/arch/arm/boards/at91sam9260ek/Makefile new file mode 100644 index 0000000000..73ef72e210 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel_init.o +obj-y += init.o diff --git a/arch/arm/boards/at91sam9260ek/config.h b/arch/arm/boards/at91sam9260ek/config.h new file mode 100644 index 0000000000..afd8563212 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/at91sam9260ek/env/bin/_update b/arch/arm/boards/at91sam9260ek/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/at91sam9260ek/env/bin/boot b/arch/arm/boards/at91sam9260ek/env/bin/boot new file mode 100644 index 0000000000..ed6f11a108 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xflash ]; then + root=flash + kernel=flash +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xflash ]; then + bootargs="$bootargs root=$rootpart rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=192.168.23.111:$nfsroot" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage + bootm uImage +else + bootm /dev/nor0.kernel +fi + diff --git a/arch/arm/boards/at91sam9260ek/env/bin/init b/arch/arm/boards/at91sam9260ek/env/bin/init new file mode 100644 index 0000000000..b8d8399842 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/env/bin/init @@ -0,0 +1,19 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type udate_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot
\ No newline at end of file diff --git a/arch/arm/boards/at91sam9260ek/env/bin/pcidmaloop b/arch/arm/boards/at91sam9260ek/env/bin/pcidmaloop new file mode 100644 index 0000000000..24e76cbed7 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/env/bin/pcidmaloop @@ -0,0 +1,14 @@ +pci stat +pci stat -c +while true; do + pci readm 32 0xA1000000 32 -s + pci readm 32 0xA2000000 256 -s + pci dmatx 2000 a2000100 128 -s + pci writem 32 0xa2000100 0x12345678 4 -s + pci readm 32 0xA3000000 256 -s + pci dmatx 2000 a3000040 128 -s + pci writem 32 0xa3000100 0x12345678 4 -s + pci readm 32 0xA4000000 16 -s + pci dmatx 2000 a4000080 4 -s + pci writem 32 0xa4000080 0x12345678 4 -s +done diff --git a/arch/arm/boards/at91sam9260ek/env/bin/pciloop b/arch/arm/boards/at91sam9260ek/env/bin/pciloop new file mode 100644 index 0000000000..4a804f9f31 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/env/bin/pciloop @@ -0,0 +1,13 @@ +pci stat +pci stat -c +while true; do + pci readm 32 0xA1000000 32 -s + pci readm 32 0xA2000000 256 -s + pci writem 32 0xa2000100 0x12345678 4 -s + pci readm 32 0xA3000000 256 -s + pci writem 32 0xa3000100 0x12345678 4 -s + pci readm 32 0xA4000000 16 -s + pci writem 32 0xa4000080 0x12345678 4 -s + +# pci dmatx 2000 a3000040 128 -s +done diff --git a/arch/arm/boards/at91sam9260ek/env/bin/update_kernel b/arch/arm/boards/at91sam9260ek/env/bin/update_kernel new file mode 100644 index 0000000000..1ad95fc5d6 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/env/bin/update_kernel @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$uimage +part=/dev/nor0.kernel + +. /env/bin/_update $1 diff --git a/arch/arm/boards/at91sam9260ek/env/bin/update_root b/arch/arm/boards/at91sam9260ek/env/bin/update_root new file mode 100644 index 0000000000..b757a5b922 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/env/bin/update_root @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +part=/dev/nor0.root + +. /env/bin/_update $1 diff --git a/arch/arm/boards/at91sam9260ek/env/config b/arch/arm/boards/at91sam9260ek/env/config new file mode 100644 index 0000000000..71d6f88cfe --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/env/config @@ -0,0 +1,20 @@ +#!/bin/sh + +# can be either 'net' or 'flash' +kernel=net +root=net + +# use 'dhcp' todo dhcp in barebox and in kernel +ip=dhcp + +# +# setup default ethernet address +# +eth0.serverip=192.168.23.108 + +uimage=uImage-at91sam9260ek + +autoboot_timeout=3 + +nfsroot="/home/jbe/pengutronix/bsp/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root,v3" +bootargs="console=ttyS0,115200 rw init=/bin/sh" diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c new file mode 100644 index 0000000000..9fd75256c6 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/init.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <fec.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <linux/mtd/nand.h> +#include <mach/board.h> +#include <mach/at91sam9_smc.h> +#include <mach/sam9_smc.h> +#include <gpio.h> +#include <mach/io.h> +#include <mach/at91_pmc.h> +#include <mach/at91_rstc.h> + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, +/* .det_pin = ... not connected */ + .ecc_base = (void __iomem *)(AT91_BASE_SYS + AT91_ECC), + .ecc_mode = NAND_ECC_HW, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + +static struct sam9_smc_config ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 2, +}; + +static void ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct at91_ether_platform_data macb_pdata = { + .flags = AT91SAM_ETHER_RMII, + .phy_addr = 0, +}; + +static void at91sam9260ek_phy_reset(void) +{ + unsigned long rstc; + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + + at91_set_gpio_input(AT91_PIN_PA14, 0); + at91_set_gpio_input(AT91_PIN_PA15, 0); + at91_set_gpio_input(AT91_PIN_PA17, 0); + at91_set_gpio_input(AT91_PIN_PA25, 0); + at91_set_gpio_input(AT91_PIN_PA26, 0); + at91_set_gpio_input(AT91_PIN_PA28, 0); + + rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0d << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (rstc) | + AT91_RSTC_URSTEN); +} + +static int at91sam9260ek_devices_init(void) +{ + ek_add_device_nand(); + at91sam9260ek_phy_reset(); + at91_add_device_eth(&macb_pdata); + + at91_add_device_sdram(64 * 1024 * 1024); + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + armlinux_set_architecture(MACH_TYPE_AT91SAM9260EK); + + devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + return 0; +} + +device_initcall(at91sam9260ek_devices_init); + +static int at91sam9260ek_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} + +console_initcall(at91sam9260ek_console_init); diff --git a/arch/arm/boards/at91sam9260ek/lowlevel_init.S b/arch/arm/boards/at91sam9260ek/lowlevel_init.S new file mode 100644 index 0000000000..4961682322 --- /dev/null +++ b/arch/arm/boards/at91sam9260ek/lowlevel_init.S @@ -0,0 +1,26 @@ +/* + * Board specific setup info + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl board_init_lowlevel +board_init_lowlevel: + mov pc, lr diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/at91sam9263ek/config.h b/arch/arm/boards/at91sam9263ek/config.h new file mode 100644 index 0000000000..9cc8af2e1d --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/config.h @@ -0,0 +1,110 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ + +#define MASTER_PLL_MUL 171 +#define MASTER_PLL_DIV 14 + +/* clocks */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + AT91_PMC_PLLCOUNT | /* PLL Counter */ \ + (2 << 28) | /* PLL Clock Frequency Range */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ + AT91_MATRIX_EBI0_CS1A_SDRAMC) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 0 +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (1 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (1 << 28)) /* Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/at91sam9263ek/env/bin/_update b/arch/arm/boards/at91sam9263ek/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/at91sam9263ek/env/bin/boot b/arch/arm/boards/at91sam9263ek/env/bin/boot new file mode 100644 index 0000000000..533dea7618 --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/env/bin/boot @@ -0,0 +1,47 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$1 = xnor ]; then + root=nor + kernel=nor +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +elif [ x$root = xnor ]; then + bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +elif [ $kernel = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/at91sam9263ek/env/bin/hush_hack b/arch/arm/boards/at91sam9263ek/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/at91sam9263ek/env/bin/init b/arch/arm/boards/at91sam9263ek/env/bin/init new file mode 100644 index 0000000000..eaa298d651 --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/env/bin/init @@ -0,0 +1,38 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nor [<imagename>] to update kernel into flash" + echo "type update_root nor [<imagename>] to update rootfs into flash" + echo "type update_barebox_xmodem nor to update barebox into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/at91sam9263ek/env/bin/update_barebox_xmodem b/arch/arm/boards/at91sam9263ek/env/bin/update_barebox_xmodem new file mode 100644 index 0000000000..39818b585c --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/env/bin/update_barebox_xmodem @@ -0,0 +1,26 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + part=/dev/nand0.barebox +elif [ x$1 = xnor ]; then + part=/dev/nor0.barebox +else + echo "usage: $0 nor|nand" + exit 1 +fi + +loadb -f barebox.bin -c + +unprotect $part +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing barebox.bin to $part" +echo +cp barebox.bin $part +crc32 -f barebox.bin +crc32 -f $part diff --git a/arch/arm/boards/at91sam9263ek/env/bin/update_kernel b/arch/arm/boards/at91sam9263ek/env/bin/update_kernel new file mode 100644 index 0000000000..05c822d860 --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/at91sam9263ek/env/bin/update_root b/arch/arm/boards/at91sam9263ek/env/bin/update_root new file mode 100644 index 0000000000..a75137237b --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/at91sam9263ek/env/config b/arch/arm/boards/at91sam9263ek/env/config new file mode 100644 index 0000000000..4b322ad4df --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/env/config @@ -0,0 +1,28 @@ +#!/bin/sh + +# can be either 'net', 'nor' or 'nand'' +kernel=net +root=net + +uimage=uImage +jffs2=root.jffs2 + +autoboot_timeout=3 + +nfsroot="" +bootargs="console=ttyS0,115200" + +nor_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +rootpart_nor="/dev/mtdblock3" + +#nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +#rootpart_nand="/dev/mtdblock7" + +# use 'dhcp' to do dhcp in barebox and in kernel +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=192.168.23.1 diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c new file mode 100644 index 0000000000..21803ca3b5 --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/init.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <linux/mtd/nand.h> +#include <mach/at91_pmc.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> +#include <mach/at91sam9_smc.h> +#include <mach/sam9_smc.h> + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, +/* .det_pin = ... not connected */ + .ecc_base = (void __iomem *)(AT91_BASE_SYS + AT91_ECC0), + .ecc_mode = NAND_ECC_HW, + .rdy_pin = AT91_PIN_PA22, + .enable_pin = AT91_PIN_PD15, +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + +static struct sam9_smc_config ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 2, +}; + +static void ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = AT91_CHIPSELECT_0, + .size = 8 * 1024 * 1024, +}; + +static struct at91_ether_platform_data macb_pdata = { + .flags = AT91SAM_ETHER_RMII, + .phy_addr = 0, +}; + +static int at91sam9263ek_devices_init(void) +{ + /* + * PB27 enables the 50MHz oscillator for Ethernet PHY + * 1 - enable + * 0 - disable + */ + at91_set_gpio_output(AT91_PIN_PB27, 1); + at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + + at91_add_device_sdram(64 * 1024 * 1024); + ek_add_device_nand(); + at91_add_device_eth(&macb_pdata); + register_device(&cfi_dev); + +#if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD) + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self"); + devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); +#elif defined(CONFIG_NAND_ATMEL) + devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); +#endif + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + armlinux_set_architecture(MACH_TYPE_AT91SAM9263EK); + + return 0; +} + +device_initcall(at91sam9263ek_devices_init); + +static int at91sam9263ek_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} + +console_initcall(at91sam9263ek_console_init); diff --git a/arch/arm/boards/edb93xx/Makefile b/arch/arm/boards/edb93xx/Makefile new file mode 100644 index 0000000000..e19cd7b4c2 --- /dev/null +++ b/arch/arm/boards/edb93xx/Makefile @@ -0,0 +1,2 @@ + +obj-y += edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o diff --git a/arch/arm/boards/edb93xx/config.h b/arch/arm/boards/edb93xx/config.h new file mode 100644 index 0000000000..6ae9a40e19 --- /dev/null +++ b/arch/arm/boards/edb93xx/config.h @@ -0,0 +1,4 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/edb93xx/early_udelay.h b/arch/arm/boards/edb93xx/early_udelay.h new file mode 100644 index 0000000000..185283d98d --- /dev/null +++ b/arch/arm/boards/edb93xx/early_udelay.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* delay execution before timers are initialized */ +static inline void early_udelay(uint32_t usecs) +{ + /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ + register uint32_t loops = usecs * (1000 / 20); + + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c new file mode 100644 index 0000000000..b0078a5227 --- /dev/null +++ b/arch/arm/boards/edb93xx/edb93xx.c @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <driver.h> +#include <environment.h> +#include <fs.h> +#include <init.h> +#include <partition.h> +#include <asm/armlinux.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <mach/ep93xx-regs.h> +#include "edb93xx.h" + +#define DEVCFG_U1EN (1 << 18) + +/* + * Up to 32MiB NOR type flash, connected to + * CS line 6, data width is 16 bit + */ +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0x60000000, + .size = EDB93XX_CFI_FLASH_SIZE, +}; + +static struct memory_platform_data ram_dev_pdata0 = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram0_dev = { + .name = "mem", + .map_base = CONFIG_EP93XX_SDRAM_BANK0_BASE, + .size = CONFIG_EP93XX_SDRAM_BANK0_SIZE, + .platform_data = &ram_dev_pdata0, +}; + +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2) +static struct memory_platform_data ram_dev_pdata1 = { + .name = "ram1", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram1_dev = { + .name = "mem", + .map_base = CONFIG_EP93XX_SDRAM_BANK1_BASE, + .size = CONFIG_EP93XX_SDRAM_BANK1_SIZE, + .platform_data = &ram_dev_pdata1, +}; +#endif + +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3) +static struct memory_platform_data ram_dev_pdata2 = { + .name = "ram2", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram2_dev = { + .name = "mem", + .map_base = CONFIG_EP93XX_SDRAM_BANK2_BASE, + .size = CONFIG_EP93XX_SDRAM_BANK2_SIZE, + .platform_data = &ram_dev_pdata2, +}; +#endif + +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4) +static struct memory_platform_data ram_dev_pdata3 = { + .name = "ram3", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram3_dev = { + .name = "mem", + .map_base = CONFIG_EP93XX_SDRAM_BANK3_BASE, + .size = CONFIG_EP93XX_SDRAM_BANK3_SIZE, + .platform_data = &ram_dev_pdata3, +}; +#endif + +static struct device_d eth_dev = { + .name = "ep93xx_eth", +}; + +static int ep93xx_devices_init(void) +{ + register_device(&cfi_dev); + + /* + * Create partitions that should be + * not touched by any regular user + */ + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); + + protect_file("/dev/env0", 1); + + register_device(&sdram0_dev); +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2) + register_device(&sdram1_dev); +#endif +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3) + register_device(&sdram2_dev); +#endif +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4) + register_device(&sdram3_dev); +#endif + + armlinux_add_dram(&sdram0_dev); +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2) + armlinux_add_dram(&sdram1_dev); +#endif +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3) + armlinux_add_dram(&sdram2_dev); +#endif +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4) + armlinux_add_dram(&sdram3_dev); +#endif + + register_device(ð_dev); + + armlinux_set_bootparams((void *)CONFIG_EP93XX_SDRAM_BANK0_BASE + 0x100); + + armlinux_set_architecture(MACH_TYPE); + + return 0; +} + +device_initcall(ep93xx_devices_init); + +static struct device_d edb93xx_serial_device = { + .name = "pl010_serial", + .map_base = UART1_BASE, + .size = 4096, +}; + +static int edb93xx_console_init(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + /* + * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of + * 14.7456/2 MHz + */ + uint32_t value = readl(&syscon->pwrcnt); + value |= SYSCON_PWRCNT_UART_BAUD; + writel(value, &syscon->pwrcnt); + + /* Enable UART1 */ + value = readl(&syscon->devicecfg); + value |= DEVCFG_U1EN; + writel(0xAA, &syscon->sysswlock); + writel(value, &syscon->devicecfg); + + register_device(&edb93xx_serial_device); + + return 0; +} + +console_initcall(edb93xx_console_init); diff --git a/arch/arm/boards/edb93xx/edb93xx.dox b/arch/arm/boards/edb93xx/edb93xx.dox new file mode 100644 index 0000000000..3964d55367 --- /dev/null +++ b/arch/arm/boards/edb93xx/edb93xx.dox @@ -0,0 +1,108 @@ +/** @page edb9301 Cirrus Logic EDB9301 + +This boards is based on a Cirrus Logic EP9301 CPU. The board is shipped with: + +- 16MiB NOR type Flash Memory +- 32MiB synchronous dynamic RAM on CS3 +- 128kiB serial EEPROM +- MII 10/100 Ethernet PHY +- Stereo audio codec + +*/ + +/** @page edb9302 Cirrus Logic EDB9302 + +This board is based on a Cirrus Logic EP9302 CPU. The board is shipped with: + +- 16MiB NOR type Flash Memory +- 32MiB synchronous dynamic RAM on CS3 +- 128kiB serial EEPROM +- MII 10/100 Ethernet PHY +- Stereo audio codec + +*/ + +/** @page edb9302a Cirrus Logic EDB9302A + +This board is based on a Cirrus Logic EP9302 CPU. The board is shipped with: + +- 16MiB NOR type Flash Memory +- 32MiB synchronous dynamic RAM on CS0 +- 512kiB serial EEPROM +- MII 10/100 Ethernet PHY +- Stereo audio codec + +*/ + +/** @page edb9307 Cirrus Logic EDB9307 + +This board is based on a Cirrus Logic EP9307 CPU. The board is shipped with: + +- 32MiB NOR type Flash Memory +- 64MiB synchronous dynamic RAM on CS3 +- 512kiB asynchronous SRAM +- 128kiB serial EEPROM +- MII 10/100 Ethernet PHY +- Stereo audio codec +- Real-Time Clock +- IR receiver + +*/ + +/** @page edb9307a Cirrus Logic EDB9307A + +This board is based on a Cirrus Logic EP9307 CPU. The board is shipped with: + +- 32MiB NOR type Flash Memory +- 64MiB synchronous dynamic RAM on CS0 +- 512kiB serial EEPROM +- MII 10/100 Ethernet PHY +- Stereo audio codec +- Real-Time Clock +- IR receiver + +*/ + +/** @page edb9312 Cirrus Logic EDB9312 + +This board is based on a Cirrus Logic EP9312 CPU. The board is shipped with: + +- 32MiB NOR type Flash Memory +- 64MiB synchronous dynamic RAM on CS3 +- 512kiB asynchronous SRAM +- 128kiB serial EEPROM +- MII 10/100 Ethernet PHY +- Stereo audio codec +- Real-Time Clock +- IR receiver + +*/ + +/** @page edb9315 Cirrus Logic EDB9315 + +This board is based on a Cirrus Logic EP9315 CPU. The board is shipped with: + +- 32MiB NOR type Flash Memory +- 64MiB synchronous dynamic RAM on CS3 +- 512kiB asynchronous SRAM +- 128kiB serial EEPROM +- MII 10/100 Ethernet PHY +- Stereo audio codec +- Real-Time Clock +- IR receiver + +*/ + +/** @page edb9315a Cirrus Logic EDB9315A + +This board is based on a Cirrus Logic EP9315 CPU. The board is shipped with: + +- 32MiB NOR type Flash Memory +- 64MiB synchronous dynamic RAM on CS0 +- 128kiB serial EEPROM +- MII 10/100 Ethernet PHY +- Stereo audio codec +- Real-Time Clock +- IR receiver + +*/
\ No newline at end of file diff --git a/arch/arm/boards/edb93xx/edb93xx.h b/arch/arm/boards/edb93xx/edb93xx.h new file mode 100644 index 0000000000..5e5c6f518c --- /dev/null +++ b/arch/arm/boards/edb93xx/edb93xx.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_MACH_EDB9301) +#define MACH_TYPE MACH_TYPE_EDB9301 +#elif defined(CONFIG_MACH_EDB9302) +#define MACH_TYPE MACH_TYPE_EDB9302 +#elif defined(CONFIG_MACH_EDB9302A) +#define MACH_TYPE MACH_TYPE_EDB9302A +#elif defined(CONFIG_MACH_EDB9307) +#define MACH_TYPE MACH_TYPE_EDB9307 +#elif defined(CONFIG_MACH_EDB9307A) +#define MACH_TYPE MACH_TYPE_EDB9307A +#elif defined(CONFIG_MACH_EDB9312) +#define MACH_TYPE MACH_TYPE_EDB9312 +#elif defined(CONFIG_MACH_EDB9315) +#define MACH_TYPE MACH_TYPE_EDB9315 +#elif defined(CONFIG_MACH_EDB9315A) +#define MACH_TYPE MACH_TYPE_EDB9315A +#endif + +#if defined(CONFIG_MACH_EDB9301) || defined(CONFIG_MACH_EDB9302) || \ + defined(CONFIG_MACH_EDB9302A) +#define EDB93XX_CFI_FLASH_SIZE (16 * 1024 * 1024) +#elif defined(CONFIG_MACH_EDB9307) || defined(CONFIG_MACH_EDB9307A) || \ + defined(CONFIG_MACH_EDB9312) || defined(CONFIG_MACH_EDB9315) || \ + defined(CONFIG_MACH_EDB9315A) +#define EDB93XX_CFI_FLASH_SIZE (32 * 1024 * 1024) +#endif diff --git a/arch/arm/boards/edb93xx/env/bin/boot b/arch/arm/boards/edb93xx/env/bin/boot new file mode 100644 index 0000000000..143f3d018d --- /dev/null +++ b/arch/arm/boards/edb93xx/env/bin/boot @@ -0,0 +1,48 @@ +#!/bin/sh + +. /env/config + +if [ x${rootfs_boot_media} = xflash ]; +then + rootfs_img=/dev/nor0.rootfs_${active_cfg} + + if [ x${active_cfg} = x1 ]; + then + rootfs_blkdev=/dev/mtdblock4 + cfg_1_ro="ro" + cfg_2_ro="" + else + rootfs_blkdev=/dev/mtdblock6 + cfg_1_ro="" + cfg_2_ro="ro" + fi + + bootargs_rootfs="root=${rootfs_blkdev} rootfstype=squashfs ro" +elif [ x${rootfs_boot_media} = xnet ]; +then + bootargs_rootfs="root=/dev/nfs nfsroot=${eth0.serverip}:/srv/nfs/${board},v3,nolock,tcp ip=${eth0.ipaddr}" +else + echo "ERROR: \$rootfs_boot_media invalid: ${rootfs_boot_media}" + exit 1 +fi + +if [ x${kernel_boot_media} = xflash ]; +then + kernel_img=/dev/nor0.kernel_${active_cfg} +elif [ x${kernel_boot_media} = xnet ]; +then + cd / + tftp ${board}/kernel.img || exit 1 + kernel_img=/kernel.img +else + echo "ERROR: \$kernel_boot_media invalid: ${kernel_boot_media}" + exit 1 +fi + +source /env/bin/set_nor_parts + +bootargs_mtd="mtdparts=physmap-flash.0:${nor_parts}" + +bootargs="${bootargs_common} ${bootargs_mtd} ${bootargs_rootfs}" + +bootm ${kernel_img}
\ No newline at end of file diff --git a/arch/arm/boards/edb93xx/env/bin/flash_partition b/arch/arm/boards/edb93xx/env/bin/flash_partition new file mode 100644 index 0000000000..ded40aa8a3 --- /dev/null +++ b/arch/arm/boards/edb93xx/env/bin/flash_partition @@ -0,0 +1,22 @@ +#!/bin/sh + +if [ $# != 2 ]; +then + echo "Usage: $0 <image> <partition>" + exit 1 +fi + +image=$1 +partition=$2 + +echo "Unlocking ${partition}" +unprotect ${partition} + +echo "Erasing ${partition}" +erase ${partition} + +echo "Flashing ${image} to ${partition}" +cp ${image} ${partition} + +echo "Locking ${partition}" +protect ${partition} diff --git a/arch/arm/boards/edb93xx/env/bin/init b/arch/arm/boards/edb93xx/env/bin/init new file mode 100644 index 0000000000..c6b5aed271 --- /dev/null +++ b/arch/arm/boards/edb93xx/env/bin/init @@ -0,0 +1,19 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +# add partitions to barebox +. /env/bin/set_nor_parts +addpart /dev/nor0 ${nor_parts} + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + exit +fi + +boot
\ No newline at end of file diff --git a/arch/arm/boards/edb93xx/env/bin/set_nor_parts b/arch/arm/boards/edb93xx/env/bin/set_nor_parts new file mode 100644 index 0000000000..38321fa8cc --- /dev/null +++ b/arch/arm/boards/edb93xx/env/bin/set_nor_parts @@ -0,0 +1,3 @@ +#!/bin/sh + +nor_parts="256k(barebox)ro,128k(env_boot),128k(env_boot.bak),1664k(kernel_1)${cfg_1_ro},6144k(rootfs_1)${cfg_1_ro},1664k(kernel_2)${cfg_2_ro},6144k(rootfs_2)${cfg_2_ro},128k(cfg_app),128k(cfg_app.bak)"
\ No newline at end of file diff --git a/arch/arm/boards/edb93xx/env/bin/update_kernel b/arch/arm/boards/edb93xx/env/bin/update_kernel new file mode 100644 index 0000000000..3e4b9b0b8e --- /dev/null +++ b/arch/arm/boards/edb93xx/env/bin/update_kernel @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +if [ $# != 1 ]; +then + echo "Usage: $0 <1/2>" + exit 1 +fi + +partition=/dev/nor0.kernel_$1 + +cd / +tftp ${board}/kernel.img || exit 1 + +flash_partition kernel.img ${partition} diff --git a/arch/arm/boards/edb93xx/env/bin/update_rootfs b/arch/arm/boards/edb93xx/env/bin/update_rootfs new file mode 100644 index 0000000000..52a3699fd0 --- /dev/null +++ b/arch/arm/boards/edb93xx/env/bin/update_rootfs @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +if [ $# != 1 ]; +then + echo "Usage: $0 <1/2>" + exit 1 +fi + +partition=/dev/nor0.rootfs_$1 + +cd / +tftp ${board}/rootfs.img || exit 1 + +flash_partition rootfs.img ${partition} diff --git a/arch/arm/boards/edb93xx/env/config b/arch/arm/boards/edb93xx/env/config new file mode 100644 index 0000000000..47ab209d82 --- /dev/null +++ b/arch/arm/boards/edb93xx/env/config @@ -0,0 +1,16 @@ +#!/bin/sh + +eth0.ipaddr=192.168.0.50 +eth0.netmask=255.255.0.0 +eth0.serverip=192.168.0.8 +eth0.ethaddr=80:81:82:83:84:85 + +board=edb9301 +autoboot_timeout=3 +active_cfg=1 +bootargs_common="console=ttyAM0,115200" + +# valid media: flash/net +kernel_boot_media=flash +rootfs_boot_media=flash + diff --git a/arch/arm/boards/edb93xx/flash_cfg.c b/arch/arm/boards/edb93xx/flash_cfg.c new file mode 100644 index 0000000000..91a6a4ea96 --- /dev/null +++ b/arch/arm/boards/edb93xx/flash_cfg.c @@ -0,0 +1,38 @@ +/* + * Flash setup for Cirrus edb93xx boards + * + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mach/ep93xx-regs.h> +#include <asm/io.h> + +#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ + SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ + 1 << SMC_BCR_MW_SHIFT) + +void flash_cfg(void) +{ + struct smc_regs *smc = (struct smc_regs *)SMC_BASE; + + writel(SMC_BCR6_VALUE, &smc->bcr6); +} diff --git a/arch/arm/boards/edb93xx/pll_cfg.c b/arch/arm/boards/edb93xx/pll_cfg.c new file mode 100644 index 0000000000..a687af0a01 --- /dev/null +++ b/arch/arm/boards/edb93xx/pll_cfg.c @@ -0,0 +1,58 @@ +/* + * PLL setup for Cirrus edb93xx boards + * + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + * + * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "pll_cfg.h" +#include "early_udelay.h" + +void pll_cfg(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + + /* setup PLL1 */ + writel(CLKSET1_VAL, &syscon->clkset1); + + /* + * flush the pipeline + * writing to CLKSET1 causes the EP93xx to enter standby for between + * 8 ms to 16 ms, until PLL1 stabilizes + */ + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + + /* setup PLL2 */ + writel(CLKSET2_VAL, &syscon->clkset2); + + /* + * the user's guide recommends to wait at least 1 ms for PLL2 to + * stabilize + */ + early_udelay(1000); +} diff --git a/arch/arm/boards/edb93xx/pll_cfg.h b/arch/arm/boards/edb93xx/pll_cfg.h new file mode 100644 index 0000000000..503507aa17 --- /dev/null +++ b/arch/arm/boards/edb93xx/pll_cfg.h @@ -0,0 +1,72 @@ +/* + * PLL register values for Cirrus edb93xx boards + * + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <mach/ep93xx-regs.h> + +#if defined(CONFIG_MACH_EDB9301) +/* + * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2 + * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000, + * pll1_x2: 331776000.000000, pll1_out: 331776000.000000 + */ +#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ + 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ + SYSCON_CLKSET1_NBYP1 | \ + 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) +#elif defined(CONFIG_MACH_EDB9302) || defined(CONFIG_MACH_EDB9302A) || \ + defined(CONFIG_MACH_EDB9307) || defined(CONFIG_MACH_EDB9307A) || \ + defined CONFIG_MACH_EDB9312 || defined(CONFIG_MACH_EDB9315) ||\ + defined(CONFIG_MACH_EDB9315A) +/* + * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2 + * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000, + * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000 + */ +#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ + 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ + SYSCON_CLKSET1_NBYP1 | \ + 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) +#else +#error "Undefined board" +#endif + +/* + * usb_div: 4, nbyp2: 1, pll2_en: 1 + * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, + * pll2_x2: 384000000.000000, pll2_out: 192000000.000000 + */ +#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \ + SYSCON_CLKSET2_PLL2_EN | \ + SYSCON_CLKSET2_NBYP2 | \ + 3 << SYSCON_CLKSET2_USB_DIV_SHIFT) diff --git a/arch/arm/boards/edb93xx/sdram_cfg.c b/arch/arm/boards/edb93xx/sdram_cfg.c new file mode 100644 index 0000000000..3d4fe08e19 --- /dev/null +++ b/arch/arm/boards/edb93xx/sdram_cfg.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + * + * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "sdram_cfg.h" +#include "early_udelay.h" + +#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \ + (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL)) + +#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \ + (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0 + +static void precharge_all_banks(void); +static void setup_refresh_timer(void); +static void program_mode_registers(void); + +void sdram_cfg(void) +{ + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG); + + /* Issue continous NOP commands */ + writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); + + early_udelay(200); + + precharge_all_banks(); + + setup_refresh_timer(); + + program_mode_registers(); + + /* Select normal operation mode */ + writel(GLCONFIG_CKE, &sdram->glconfig); +} + +static void precharge_all_banks(void) +{ + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + /* Issue PRECHARGE ALL commands */ + writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig); + + /* + * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always + * issued. + * + * Cirrus proposes a workaround which consists in performing a read from + * each bank to force the precharge. This causes some boards to hang. + * Writing to the SDRAM banks instead of reading has the same + * side-effect (the SDRAM controller issues the necessary precharges), + * but is known to work on all supported boards + */ + + PRECHARGE_BANK(0); + +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2) + PRECHARGE_BANK(1); +#endif + +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3) + PRECHARGE_BANK(2); +#endif + +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4) + PRECHARGE_BANK(3); +#endif +} + +static void setup_refresh_timer(void) +{ + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + /* Load refresh timer with 10 to issue refresh every 10 cycles */ + writel(0x0a, &sdram->refrshtimr); + + /* + * Wait at least 80 clock cycles to provide 8 refresh cycles + * to all SDRAMs + */ + early_udelay(1); + + /* + * Program refresh timer with normal value + * We need 8192 refresh cycles every 64ms + * at 15ns (HCLK >= 66MHz) per cycle: + * 64ms / 8192 = 7.8125us + * 7.8125us / 15ns = 520 (0x208) + */ + /* + * TODO: redboot uses 0x1e0 for the slowest possible device + * but i don't understand how this value is calculated + */ + writel(0x208, &sdram->refrshtimr); +} + +static void program_mode_registers(void) +{ + struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; + + /* Select mode register update mode */ + writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); + + PROGRAM_MODE_REG(0); + +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2) + PROGRAM_MODE_REG(1); +#endif + +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3) + PROGRAM_MODE_REG(2); +#endif + +#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4) + PROGRAM_MODE_REG(3); +#endif +} diff --git a/arch/arm/boards/edb93xx/sdram_cfg.h b/arch/arm/boards/edb93xx/sdram_cfg.h new file mode 100644 index 0000000000..c57b76ef18 --- /dev/null +++ b/arch/arm/boards/edb93xx/sdram_cfg.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + * + * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <mach/ep93xx-regs.h> + +#define SDRAM_BASE_ADDR CONFIG_EP93XX_SDRAM_BANK0_BASE + +#ifdef CONFIG_EP93XX_SDCE0_PHYS_OFFSET +#define SDRAM_DEVCFG_REG devcfg0 +#elif defined(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) +#define SDRAM_DEVCFG_REG devcfg3 +#else +#error "SDRAM bank configuration" +#endif + +#if defined(CONFIG_MACH_EDB9301) || defined(CONFIG_MACH_EDB9302) ||\ + defined(CONFIG_MACH_EDB9302A) +/* + * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM + * + * CLK cycle time min: + * @ CAS latency = 3: 7.5ns + * @ CAS latency = 2: 10ns + * We're running at 66MHz (EDB9301) / 100Mhz (EDB9302(a)) external + * bus speed (HCLK), with a cycle time of 15ns / 10ns, so it's safe + * to use CAS latency = 2 + * + * RAS-to-CAS delay min: + * 20ns + * At 15ns/10ns cycle time, we use RAS-to-CAS delay = 2 + * + * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear + * as four blocks of 8MB size, instead of eight blocks of 4MB size: + * + * EDB9301/EDB9302: + * + * 0x00000000 - 0x007fffff + * 0x01000000 - 0x017fffff + * 0x04000000 - 0x047fffff + * 0x05000000 - 0x057fffff + * + * + * EDB9302a: + * + * 0xc0000000 - 0xc07fffff + * 0xc1000000 - 0xc17fffff + * 0xc4000000 - 0xc47fffff + * 0xc5000000 - 0xc57fffff + * + * BANKCOUNT = 1: This is a device with four banks + */ + +#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ + SDRAM_DEVCFG_SROMLL | \ + SDRAM_DEVCFG_CASLAT_2 | \ + SDRAM_DEVCFG_RASTOCAS_2 | \ + SDRAM_DEVCFG_EXTBUSWIDTH) + +/* + * 16 bit ext. bus + * + * A[22:09] is output as SYA[13:0] + * CAS latency: 2 + * Burst type: sequential + * Burst length: 8 (required for 16 bit ext. bus) + * SYA[13:0] = 0x0023 + */ +#define SDRAM_MODE_REG_VAL 0x4600 + +#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */ +#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */ +#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */ +#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */ + +#elif defined(CONFIG_MACH_EDB9307) || defined(CONFIG_MACH_EDB9307A) ||\ + defined CONFIG_MACH_EDB9312 || defined(CONFIG_MACH_EDB9315) ||\ + defined(CONFIG_MACH_EDB9315A) +/* + * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM + * + * CLK cycle time min: + * @ CAS latency = 3: 7.5ns + * @ CAS latency = 2: 10ns + * We're running at 100MHz (10ns cycle time) external bus speed (HCLK), + * so it's safe to use CAS latency = 2 + * + * RAS-to-CAS delay min: + * 20ns + * At 10ns cycle time, we use RAS-to-CAS delay = 2 + * + * EDB9307, EDB9312, EDB9315: + * + * 0x00000000 - 0x01ffffff + * 0x04000000 - 0x05ffffff + * + * + * EDB9307a, EDB9315a: + * + * 0xc0000000 - 0xc1ffffff + * 0xc4000000 - 0xc5ffffff + */ + +#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ + SDRAM_DEVCFG_SROMLL | \ + SDRAM_DEVCFG_CASLAT_2 | \ + SDRAM_DEVCFG_RASTOCAS_2) + +/* + * 32 bit ext. bus + * + * A[23:10] is output as SYA[13:0] + * CAS latency: 2 + * Burst type: sequential + * Burst length: 4 + * SYA[13:0] = 0x0022 + */ +#define SDRAM_MODE_REG_VAL 0x8800 + +#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */ +#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */ +#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */ +#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */ +#endif diff --git a/arch/arm/boards/eukrea_cpuimx25/Makefile b/arch/arm/boards/eukrea_cpuimx25/Makefile new file mode 100644 index 0000000000..406c6f32f7 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/Makefile @@ -0,0 +1,24 @@ +# +# (C) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y += lowlevel.o +obj-y += eukrea_cpuimx25.o diff --git a/arch/arm/boards/eukrea_cpuimx25/config.h b/arch/arm/boards/eukrea_cpuimx25/config.h new file mode 100644 index 0000000000..efff909eed --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/config.h @@ -0,0 +1,27 @@ +/* + * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX25_HCLK_FREQ 24000000 + +#endif + +/* nothing to do here yet */ diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/_update b/arch/arm/boards/eukrea_cpuimx25/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/boot b/arch/arm/boards/eukrea_cpuimx25/env/bin/boot new file mode 100644 index 0000000000..2d9b3af01c --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/boot @@ -0,0 +1,53 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xjffS2 ]; then + root=jffs2 + kernel=nand +fi + +if [ x$1 = xubifs ]; then + root=ubifs + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + if [ x$ip = xoff ]; then + bootargs="$bootargs ip=off" + else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +fi + +if [ x$root = xjffs2 ]; then + bootargs="$bootargs root=/dev/mtdblock$rootpartnum_nand rootfstype=jffs2" +fi + +if [ x$root = xubifs ]; then + bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum_nand rootfstype=ubifs" +fi + +if [ x$root = xnet ]; then + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/hush_hack b/arch/arm/boards/eukrea_cpuimx25/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/init b/arch/arm/boards/eukrea_cpuimx25/env/bin/init new file mode 100644 index 0000000000..335d7ae579 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/init @@ -0,0 +1,41 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -f /env/logo.bmp ]; then + bmp /env/logo.bmp +elif [ -f /env/logo.bmp.lzo ]; then + unlzo /env/logo.bmp.lzo /logo.bmp + bmp /logo.bmp +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" + saveenv +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type update_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/update_kernel b/arch/arm/boards/eukrea_cpuimx25/env/bin/update_kernel new file mode 100644 index 0000000000..c2d2cc3fa9 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/update_kernel @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$uimage +part=/dev/nand0.kernel.bb + +. /env/bin/_update $1 diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/update_root b/arch/arm/boards/eukrea_cpuimx25/env/bin/update_root new file mode 100644 index 0000000000..dd89a5afad --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/update_root @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$rootfs +part=/dev/nand0.root.bb + +. /env/bin/_update $1 diff --git a/arch/arm/boards/eukrea_cpuimx25/env/config b/arch/arm/boards/eukrea_cpuimx25/env/config new file mode 100644 index 0000000000..9217ca17be --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/env/config @@ -0,0 +1,27 @@ +#!/bin/sh + +# can be either 'net' or 'jffs2' or 'ubifs' +kernel=nand +root=ubifs + +basedir=cpuimx25 +uimage=$basedir/uImage +rootfs=$basedir/rootfs + +autoboot_timeout=1 + +nfsroot="" +bootargs="console=ttymxc0,115200" + +nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)" +rootpartnum_nand=3 +ubiroot="eukrea-cpuimx25-rootfs" + +# use 'dhcp' to do dhcp in barebox and in kernel +ip=off + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c new file mode 100644 index 0000000000..caeb46e872 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c @@ -0,0 +1,273 @@ +/* + * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <asm/armlinux.h> +#include <mach/gpio.h> +#include <asm/io.h> +#include <asm/mmu.h> + +#include <partition.h> +#include <asm/mach-types.h> +#include <mach/imx-nand.h> +#include <mach/imxfb.h> +#include <fec.h> +#include <nand.h> +#include <mach/imx-flash-header.h> +#include <mach/iomux-mx25.h> + +extern unsigned long _stext; + +void __naked __flash_header_start go(void) +{ + __asm__ __volatile__("b exception_vectors\n"); +} + +struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = { + { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, }, + { .ptr_type = 1, .addr = 0x80000400, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, }, + { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000000, .val = 0xff, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, }, + { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, +}; + +struct imx_flash_header __flash_header_0x400 eukrea_cpuimx25_header = { + .app_code_jump_vector = TEXT_BASE + 0x2000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = TEXT_BASE + 0x400 + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = TEXT_BASE + 0x400 + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = TEXT_BASE, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof(dcd_entry), +}; + +extern unsigned long __bss_start; + +unsigned long __image_len_0x400 barebox_len = 0x40000; + +static struct fec_platform_data fec_info = { + .xcv_type = RMII, + .phy_addr = 1, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = IMX_FEC_BASE, + .platform_data = &fec_info, +}; + +static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram0_dev = { + .name = "mem", + .map_base = IMX_SDRAM_CS0, + .size = 64 * 1024 * 1024, + .platform_data = &sdram_pdata, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = IMX_NFC_BASE, + .platform_data = &nand_info, +}; + +static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "CMO-QVGA", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .hsync_len = 30, + .left_margin = 38, + .right_margin = 20, + .vsync_len = 3, + .upper_margin = 15, + .lower_margin = 4, + }, + .pcr = 0xCAD08B80, + .bpp = 16, +}; + +static struct imx_fb_platform_data eukrea_cpuimx25_fb_data = { + .mode = &imxfb_mode, + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x80040060, +}; + + +static struct device_d imxfb_dev = { + .name = "imxfb", + .map_base = 0x53fbc000, + .size = 0x1000, + .platform_data = &eukrea_cpuimx25_fb_data, +}; + +#ifdef CONFIG_MMU +static void eukrea_cpuimx25_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + + mmu_enable(); +} +#else +static void eukrea_cpuimx25_mmu_init(void) +{ +} +#endif + +static struct pad_desc eukrea_cpuimx25_pads[] = { + MX25_PAD_FEC_MDC__MDC, + MX25_PAD_FEC_MDIO__MDIO, + MX25_PAD_FEC_RDATA0__RDATA0, + MX25_PAD_FEC_RDATA1__RDATA1, + MX25_PAD_FEC_RX_DV__RX_DV, + MX25_PAD_FEC_TDATA0__TDATA0, + MX25_PAD_FEC_TDATA1__TDATA1, + MX25_PAD_FEC_TX_CLK__TX_CLK, + MX25_PAD_FEC_TX_EN__TX_EN, + /* UART1 */ + MX25_PAD_UART1_RXD__RXD_MUX, + MX25_PAD_UART1_TXD__TXD_MUX, + MX25_PAD_UART1_RTS__RTS, + MX25_PAD_UART1_CTS__CTS, + /* LCDC */ + MX25_PAD_LD0__LCDC_LD0, + MX25_PAD_LD1__LCDC_LD1, + MX25_PAD_LD2__LCDC_LD2, + MX25_PAD_LD3__LCDC_LD3, + MX25_PAD_LD4__LCDC_LD4, + MX25_PAD_LD5__LCDC_LD5, + MX25_PAD_LD6__LCDC_LD6, + MX25_PAD_LD7__LCDC_LD7, + MX25_PAD_LD8__LCDC_LD8, + MX25_PAD_LD9__LCDC_LD9, + MX25_PAD_LD10__LCDC_LD10, + MX25_PAD_LD11__LCDC_LD11, + MX25_PAD_LD12__LCDC_LD12, + MX25_PAD_LD13__LCDC_LD13, + MX25_PAD_LD14__LCDC_LD14, + MX25_PAD_LD15__LCDC_LD15, + MX25_PAD_GPIO_E__LCDC_LD16, + MX25_PAD_GPIO_F__LCDC_LD17, + MX25_PAD_LSCLK__LCDC_LSCLK, + MX25_PAD_OE_ACD__LCDC_OE_ACD, + MX25_PAD_VSYNC__LCDC_VSYN, + MX25_PAD_HSYNC__LCDC_HSYN, + /* BACKLIGHT CONTROL */ + MX25_PAD_PWM__GPIO26, +}; + +static int eukrea_cpuimx25_devices_init(void) +{ + eukrea_cpuimx25_mmu_init(); + + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads, + ARRAY_SIZE(eukrea_cpuimx25_pads)); + register_device(&fec_dev); + + nand_info.width = 1; + register_device(&nand_dev); + + devfs_add_partition("nand0", 0x00000, 0x40000, + PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, + PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + register_device(&sdram0_dev); + + /* enable LCD */ + gpio_direction_output(26, 1); + gpio_set_value(26, 1); + + register_device(&imxfb_dev); + + armlinux_add_dram(&sdram0_dev); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX25); + + return 0; +} + +device_initcall(eukrea_cpuimx25_devices_init); + +static struct device_d eukrea_cpuimx25_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 16 * 1024, +}; + +static int eukrea_cpuimx25_console_init(void) +{ + writel(0x03010101, IMX_CCM_BASE + CCM_PCDR3); + register_device(&eukrea_cpuimx25_serial_device); + return 0; +} + +console_initcall(eukrea_cpuimx25_console_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif + +static int eukrea_cpuimx25_core_setup(void) +{ + writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2); + return 0; + +} +core_initcall(eukrea_cpuimx25_core_setup); diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c new file mode 100644 index 0000000000..b9d3ce57bb --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -0,0 +1,130 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <init.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <mach/esdctl.h> +#include <asm/cache-l2x0.h> +#include <asm/io.h> +#include <mach/imx-nand.h> +#include <asm/barebox-arm.h> +#include <asm-generic/memory_layout.h> +#include <asm/system.h> + +static void __bare_init __naked insdram(void) +{ + uint32_t r; + + /* setup a stack to be able to call imx_nand_load_image() */ + r = STACK_BASE + STACK_SIZE - 12; + __asm__ __volatile__("mov sp, %0" : : "r"(r)); + + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); + + board_init_lowlevel_return(); +} + +#define MX25_CCM_MCR 0x64 +#define MX25_CCM_CGR0 0x0c +#define MX25_CCM_CGR1 0x10 +#define MX25_CCM_CGR2 0x14 + +void __bare_init __naked board_init_lowlevel(void) +{ + uint32_t r; + unsigned int *trg, *src; + int i; + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good. + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, 0x43f00000); + writel(0x77777777, 0x43f00004); + writel(0x77777777, 0x53f00000); + writel(0x77777777, 0x53f00004); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup + * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB + */ + writel(0x00002143, 0x43f04000); + writel(0x00002143, 0x43f04100); + writel(0x00002143, 0x43f04200); + writel(0x00002143, 0x43f04300); + writel(0x00002143, 0x43f04400); + /* SGPCR - always park on last master */ + writel(0x10, 0x43f04010); + writel(0x10, 0x43f04110); + writel(0x10, 0x43f04210); + writel(0x10, 0x43f04310); + writel(0x10, 0x43f04410); + /* MGPCR - restore default values */ + writel(0x0, 0x43f04800); + writel(0x0, 0x43f04900); + writel(0x0, 0x43f04a00); + writel(0x0, 0x43f04b00); + writel(0x0, 0x43f04c00); + + /* Configure M3IF registers + * M3IF Control Register (M3IFCTL) for MX25 + * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 + * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 + * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 + * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 + * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000 + * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000 + * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 + * ---------- + * 0x00000001 + */ + writel(0x1, 0xb8003000); + + /* enable all the clocks */ + writel(0x038A81A2, IMX_CCM_BASE + MX25_CCM_CGR0); + writel(0x24788F00, IMX_CCM_BASE + MX25_CCM_CGR1); + writel(0x00004438, IMX_CCM_BASE + MX25_CCM_CGR2); + writel(0x00, IMX_CCM_BASE + MX25_CCM_MCR); + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x1000) + board_init_lowlevel_return(); + + src = (unsigned int *)IMX_NFC_BASE; + trg = (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ + for (i = 0; i < 0x1000 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ + r = (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} diff --git a/arch/arm/boards/eukrea_cpuimx27/Makefile b/arch/arm/boards/eukrea_cpuimx27/Makefile new file mode 100644 index 0000000000..5d958fa9aa --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/Makefile @@ -0,0 +1,3 @@ + +obj-y += lowlevel_init.o +obj-y += eukrea_cpuimx27.o diff --git a/arch/arm/boards/eukrea_cpuimx27/config.h b/arch/arm/boards/eukrea_cpuimx27/config.h new file mode 100644 index 0000000000..ec6f2123bf --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/config.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Global defintions for the ARM Eukrea cpuimx27 board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/_update b/arch/arm/boards/eukrea_cpuimx27/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot new file mode 100644 index 0000000000..7272e56763 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot @@ -0,0 +1,51 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$1 = xnor ]; then + root=nor + kernel=nor +fi + +if [ x$root = xnet ]; then + if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" + else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +else + bootargs="$bootargs ip=off" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +elif [ x$root = xnor ]; then + bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +elif [ $kernel = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/hush_hack b/arch/arm/boards/eukrea_cpuimx27/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/init b/arch/arm/boards/eukrea_cpuimx27/env/bin/init new file mode 100644 index 0000000000..3bfd194913 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/init @@ -0,0 +1,37 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nand|nor [<imagename>] to update kernel into flash" + echo "type update_root nand|nor [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel new file mode 100644 index 0000000000..05c822d860 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root new file mode 100644 index 0000000000..eaf36ebcea --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/eukrea_cpuimx27/env/config b/arch/arm/boards/eukrea_cpuimx27/env/config new file mode 100644 index 0000000000..505ada39c7 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/config @@ -0,0 +1,31 @@ +#!/bin/sh + +# can be either 'net', 'nor' or 'nand'' +kernel=nor +root=nor + +uimage=mx27/uImage +jffs2=mx27/rootfs.jffs2 + +autoboot_timeout=1 + +# DVI-SVGA DVI-VGA CMO-QVGA +video="CMO-QVGA" +bootargs="console=ttymxc0,115200 fec_mac=$eth0.ethaddr video=mxcfb:$video" + +nor_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)" +rootpart_nor="/dev/mtdblock3" + +nand_parts="-(nand)" +rootpart_nand="" + +nfsroot="" + +# use 'dhcp' to do dhcp in barebox and in kernel +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c new file mode 100644 index 0000000000..1937d21c85 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -0,0 +1,370 @@ +/* + * Copyright (C) 2009 Eric Benard, Eukrea Electromatique + * Based on pcm038.c which is : + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <errno.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <fec.h> +#include <notifier.h> +#include <mach/gpio.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <mach/pmic.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <nand.h> +#include <command.h> +#include <asm/io.h> +#include <mach/imx-nand.h> +#include <mach/imx-pll.h> +#include <mach/imxfb.h> +#include <ns16550.h> +#include <asm/mmu.h> +#include <i2c/i2c.h> +#include <i2c/lp3972.h> +#include <mach/iomux-mx27.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0xC0000000, + .size = 32 * 1024 * 1024, +}; +#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB +static struct device_d cfi_dev1 = { + .name = "cfi_flash", + .map_base = 0xC2000000, + .size = 32 * 1024 * 1024, +}; +#endif + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB +#define SDRAM0 256 +#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB +#define SDRAM0 128 +#endif + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0xa0000000, + .size = SDRAM0 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 1, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = 0x1002b000, + .platform_data = &fec_info, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = 0xd8000000, + .platform_data = &nand_info, +}; + +#ifdef CONFIG_DRIVER_SERIAL_NS16550 +unsigned int quad_uart_read(unsigned long base, unsigned char reg_idx) +{ + unsigned int reg_addr = (unsigned int)base; + reg_addr += reg_idx << 1; + return 0xff & readw(reg_addr); +} +EXPORT_SYMBOL(quad_uart_read); + +void quad_uart_write(unsigned int val, unsigned long base, + unsigned char reg_idx) +{ + unsigned int reg_addr = (unsigned int)base; + reg_addr += reg_idx << 1; + writew(0xff & val, reg_addr); +} +EXPORT_SYMBOL(quad_uart_write); + +static struct NS16550_plat quad_uart_serial_plat = { + .clock = 14745600, + .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR, + .reg_read = quad_uart_read, + .reg_write = quad_uart_write, +}; + +#ifdef CONFIG_EUKREA_CPUIMX27_QUART1 +#define QUART_OFFSET 0x200000 +#elif defined CONFIG_EUKREA_CPUIMX27_QUART2 +#define QUART_OFFSET 0x400000 +#elif defined CONFIG_EUKREA_CPUIMX27_QUART3 +#define QUART_OFFSET 0x800000 +#elif defined CONFIG_EUKREA_CPUIMX27_QUART4 +#define QUART_OFFSET 0x1000000 +#endif + +static struct device_d quad_uart_serial_device = { + .name = "serial_ns16550", + .map_base = IMX_CS3_BASE + QUART_OFFSET, + .size = 0xF, + .platform_data = (void *)&quad_uart_serial_plat, +}; +#endif + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("lp3972", 0x34), + }, +}; + +static struct device_d i2c_dev = { + .name = "i2c-imx", + .map_base = IMX_I2C1_BASE, +}; + +#ifdef CONFIG_MMU +static void eukrea_cpuimx27_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + mmu_enable(); +} +#else +static void eukrea_cpuimx27_mmu_init(void) +{ +} +#endif + +#ifdef CONFIG_DRIVER_VIDEO_IMX +static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "CMO-QVGA", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = 156000, + .hsync_len = 30, + .left_margin = 38, + .right_margin = 20, + .vsync_len = 3, + .upper_margin = 15, + .lower_margin = 4, + }, + .pcr = 0xFAD08B80, + .bpp = 16,}; + +static struct imx_fb_platform_data eukrea_cpuimx27_fb_data = { + .mode = &imxfb_mode, + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; + +static struct device_d imxfb_dev = { + .name = "imxfb", + .map_base = 0x10021000, + .size = 0x1000, + .platform_data = &eukrea_cpuimx27_fb_data, +}; +#endif + +static int eukrea_cpuimx27_devices_init(void) +{ + char *envdev = "no"; + int i; + + unsigned int mode[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + PD17_PF_I2C_DATA, + PD18_PF_I2C_CLK, +#ifdef CONFIG_DRIVER_SERIAL_IMX + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, +#endif +#ifdef CONFIG_DRIVER_VIDEO_IMX + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA31_PF_OE_ACD, + GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT, +#endif + }; + + eukrea_cpuimx27_mmu_init(); + + /* configure 16 bit nor flash on cs0 */ + CS0U = 0x00008F03; + CS0L = 0xA0330D01; + CS0A = 0x002208C0; + + /* initialize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + register_device(&cfi_dev); +#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB + register_device(&cfi_dev1); +#endif + register_device(&nand_dev); + register_device(&sdram_dev); + + PCCR0 |= PCCR0_I2C1_EN; + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + register_device(&i2c_dev); + + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + envdev = "NOR"; + + printf("Using environment in %s Flash\n", envdev); + +#ifdef CONFIG_DRIVER_VIDEO_IMX + register_device(&imxfb_dev); + gpio_direction_output(GPIO_PORTE | 5, 0); + gpio_set_value(GPIO_PORTE | 5, 1); +#endif + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0xa0000100); + armlinux_set_architecture(MACH_TYPE_CPUIMX27); + + return 0; +} + +device_initcall(eukrea_cpuimx27_devices_init); + +#ifdef CONFIG_DRIVER_SERIAL_IMX +static struct device_d eukrea_cpuimx27_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; +#endif + +static int eukrea_cpuimx27_console_init(void) +{ +#ifdef CONFIG_DRIVER_SERIAL_IMX + register_device(&eukrea_cpuimx27_serial_device); +#endif + /* configure 8 bit UART on cs3 */ + FMCR &= ~0x2; + CS3U = 0x0000D603; + CS3L = 0x0D1D0D01; + CS3A = 0x00D20000; +#ifdef CONFIG_DRIVER_SERIAL_NS16550 + register_device(&quad_uart_serial_device); +#endif + return 0; +} + +console_initcall(eukrea_cpuimx27_console_init); + +static int eukrea_cpuimx27_late_init(void) +{ +#ifdef CONFIG_DRIVER_I2C_LP3972 + struct i2c_client *client; + u8 reg[1]; +#endif + console_flush(); + register_device(&fec_dev); + +#ifdef CONFIG_DRIVER_I2C_LP3972 + client = lp3972_get_client(); + if (!client) + return -ENODEV; + reg[0] = 0xa0; + i2c_write_reg(client, 0x39, reg, sizeof(reg)); +#endif + return 0; +} + +late_initcall(eukrea_cpuimx27_late_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif + diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox new file mode 100644 index 0000000000..6c2bfede22 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox @@ -0,0 +1,11 @@ +/** @page eukrea_cpuimx27 Eukrea's CPUIMX27 + +This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with: + +- up to 64MiB NOR type Flash Memory +- up to 256MiB synchronous dynamic RAM +- up to 512MiB NAND type Flash Memory +- MII 10/100 ethernet PHY +- optional 16554 Quad UART on CS3 + +*/ diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S new file mode 100644 index 0000000000..5295a8a227 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -0,0 +1,141 @@ +#include <config.h> +#include <mach/imx-regs.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB +#define ROWS0 ESDCTL_ROW14 +#define CFG0 0x0029572D +#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB +#define ROWS0 ESDCTL_ROW13 +#define CFG0 0x00095728 +#endif + +#define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10) + +.macro sdram_init + /* + * DDR on CSD0 + */ + writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */ + + writel(0x55555555, DSCR(3)) /* Set the driving strength */ + writel(0x55555555, DSCR(5)) + writel(0x55555555, DSCR(6)) + writel(0x00005005, DSCR(7)) + writel(0x15555555, DSCR(8)) + + writel(0x00000004, ESDMISC) /* Initial reset */ + writel(CFG0, ESDCFG0) + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */ + writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0) + + ldr r0, =0xa0000f00 + mov r1, #0 + mov r2, #8 +1: + str r1, [r0] + subs r2, #1 + bne 1b + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0) + ldr r0, =0xA0000033 + mov r1, #0xda + strb r1, [r0] +#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB + ldr r0, =0xA2000000 +#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB + ldr r0, =0xA1000000 +#endif + mov r1, #0xff + strb r1, [r0] + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0) +.endm + + .section ".text_bare_init","ax" + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr + + /* ahb lite ip interface */ + writel(0x20040304, AIPI1_PSR0) + writel(0xDFFBFCFB, AIPI1_PSR1) + writel(0x00000000, AIPI2_PSR0) + writel(0xFFFFFFFF, AIPI2_PSR1) + + /* disable mpll/spll */ + ldr r0, =CSCR + ldr r1, [r0] + bic r1, r1, #0x03 + str r1, [r0] + + /* + * pll clock initialization - see section 3.4.3 of the i.MX27 manual + */ + writel(0x00331C23, MPCTL0) /* MPLL = 399 MHz */ + writel(0x040C2403, SPCTL0) /* SPLL = 240 MHz */ + writel(0x33F38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + + /* add some delay here */ + mov r1, #0x1000 +1: subs r1, r1, #0x1 + bne 1b + + /* clock gating enable */ + writel(0x00050f08, GPCR) + + /* peripheral clock divider */ + writel(0x130400c3, PCDR0) /* FIXME */ + writel(0x09030208, PCDR1) /* PERDIV1=08 @133 MHz */ + /* PERDIV1=04 @266 MHz */ + + /* skip sdram initialization if we run from ram */ + cmp pc, #0xa0000000 + bls 1f + cmp pc, #0xc0000000 + bhi 1f + + mov pc,r10 +1: + sdram_init + +#ifdef CONFIG_NAND_IMX_BOOT + ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */ + + ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ + ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + + /* skip NAND boot if not running from NFC space */ + cmp pc, r0 + bls ret + cmp pc, r2 + bhi ret + + /* Move ourselves out of NFC SRAM */ + ldr r1, =TEXT_BASE + +copy_loop: + ldmia r0!, {r3-r9} /* copy from source address [r0] */ + stmia r1!, {r3-r9} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + ldr pc, =1f /* Jump to SDRAM */ +1: + bl nand_boot /* Load barebox from NAND Flash */ + + ldr r1, =IMX_NFC_BASE - TEXT_BASE + sub r10, r10, r1 /* adjust return address from NFC SRAM */ + /* to SDRAM */ + +#endif /* CONFIG_NAND_IMX_BOOT */ + +ret: + mov pc,r10 diff --git a/arch/arm/boards/eukrea_cpuimx35/Makefile b/arch/arm/boards/eukrea_cpuimx35/Makefile new file mode 100644 index 0000000000..32ffe42cb1 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/Makefile @@ -0,0 +1,25 @@ +# +# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y += lowlevel.o +obj-y += eukrea_cpuimx35.o +obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o diff --git a/arch/arm/boards/eukrea_cpuimx35/config.h b/arch/arm/boards/eukrea_cpuimx35/config.h new file mode 100644 index 0000000000..bfd3b3964e --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/config.h @@ -0,0 +1,23 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX35_HCLK_FREQ 24000000 + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/_update b/arch/arm/boards/eukrea_cpuimx35/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/boot b/arch/arm/boards/eukrea_cpuimx35/env/bin/boot new file mode 100644 index 0000000000..fca5b8cc19 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/boot @@ -0,0 +1,52 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xjffS2 ]; then + root=jffs2 + kernel=nand +fi + +if [ x$1 = xubifs ]; then + root=ubifs + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + if [ x$ip = xoff ]; then + bootargs="$bootargs ip=off" + else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +fi + +if [ x$root = xjffs2 ]; then + bootargs="$bootargs root=/dev/mtdblock$rootpartnum_nand rootfstype=jffs2" +fi + +if [ x$root = xubifs ]; then + bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum_nand rootfstype=ubifs" +fi + +if [ x$root = xnet ]; then + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nand0.kernel.bb +fi diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/hush_hack b/arch/arm/boards/eukrea_cpuimx35/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/init b/arch/arm/boards/eukrea_cpuimx35/env/bin/init new file mode 100644 index 0000000000..49e54c5fdd --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/init @@ -0,0 +1,41 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -f /env/logo.bmp ]; then + bmp /env/logo.bmp +elif [ -f /env/logo.bmp.lzo ]; then + unlzo /env/logo.bmp.lzo /logo.bmp + bmp /logo.bmp +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" + saveenv +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type update_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/update_kernel b/arch/arm/boards/eukrea_cpuimx35/env/bin/update_kernel new file mode 100644 index 0000000000..c2d2cc3fa9 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/update_kernel @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$uimage +part=/dev/nand0.kernel.bb + +. /env/bin/_update $1 diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/update_root b/arch/arm/boards/eukrea_cpuimx35/env/bin/update_root new file mode 100644 index 0000000000..dd89a5afad --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/update_root @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$rootfs +part=/dev/nand0.root.bb + +. /env/bin/_update $1 diff --git a/arch/arm/boards/eukrea_cpuimx35/env/config b/arch/arm/boards/eukrea_cpuimx35/env/config new file mode 100644 index 0000000000..df2079fa58 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/env/config @@ -0,0 +1,27 @@ +#!/bin/sh + +# can be either 'net' or 'nand'' +kernel=nand +root=ubifs + +basedir=cpuimx35 +uimage=$basedir/uImage +rootfs=$basedir/rootfs + +autoboot_timeout=1 + +nfsroot="" +bootargs="console=ttymxc0,115200" + +nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)" +rootpartnum_nand=3 +ubiroot="eukrea-cpuimx35-rootfs" + +# use 'dhcp' to do dhcp in barebox and in kernel +ip=off + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c new file mode 100644 index 0000000000..7f1c782f1e --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -0,0 +1,343 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * 2009 Marc Kleine-Budde, Pengutronix + * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from: + * + * * mx35_3stack.c - board file for uboot-v1 + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <errno.h> +#include <fcntl.h> +#include <fec.h> +#include <fs.h> +#include <init.h> +#include <nand.h> +#include <net.h> +#include <partition.h> + +#include <asm/armlinux.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/mmu.h> + +#include <mach/gpio.h> +#include <mach/imx-nand.h> +#include <mach/imx-regs.h> +#include <mach/iomux-mx35.h> +#include <mach/iomux-v3.h> +#include <mach/pmic.h> +#include <mach/imx-ipu-fb.h> +#include <mach/imx-pll.h> + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 0x1F, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = IMX_FEC_BASE, + .platform_data = &fec_info, +}; + +static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = IMX_SDRAM_CS0, + .size = 128 * 1024 * 1024, + .platform_data = &sdram_pdata, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = IMX_NFC_BASE, + .platform_data = &nand_info, +}; + +static struct fb_videomode imxfb_mode = { + .name = "CMO_QVGA", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(7000), + .left_margin = 68, + .right_margin = 20, + .upper_margin = 15, + .lower_margin = 4, + .hsync_len = 30, + .vsync_len = 3, + .sync = FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct imx_ipu_fb_platform_data ipu_fb_data = { + .mode = &imxfb_mode, + .bpp = 16, +}; + +static struct device_d imxfb_dev = { + .name = "imx-ipu-fb", + .map_base = 0x53fc0000, + .size = 0x1000, + .platform_data = &ipu_fb_data, +}; + +#ifdef CONFIG_MMU +static int eukrea_cpuimx35_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + mmu_enable(); + +#ifdef CONFIG_CACHE_L2X0 + l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); +#endif + return 0; +} +postcore_initcall(eukrea_cpuimx35_mmu_init); +#endif + +static int eukrea_cpuimx35_devices_init(void) +{ + register_device(&nand_dev); + + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + register_device(&fec_dev); + + register_device(&sdram_dev); + register_device(&imxfb_dev); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35); + + return 0; +} + +device_initcall(eukrea_cpuimx35_devices_init); + +static int eukrea_cpuimx35_enable_display(void) +{ + gpio_direction_output(1, 1); + gpio_direction_output(0, 0); + return 0; +} + +late_initcall(eukrea_cpuimx35_enable_display); + +static struct device_d eukrea_cpuimx35_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static struct pad_desc eukrea_cpuimx35_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + + MX35_PAD_RXD1__UART1_RXD_MUX, + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RTS1__UART1_RTS, + MX35_PAD_CTS1__UART1_CTS, +}; + +static int eukrea_cpuimx35_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, + ARRAY_SIZE(eukrea_cpuimx35_pads)); + + register_device(&eukrea_cpuimx35_serial_device); + return 0; +} + +console_initcall(eukrea_cpuimx35_console_init); + +static int eukrea_cpuimx35_core_init(void) +{ + u32 reg; + + /* enable clock for I2C1 and FEC */ + reg = readl(IMX_CCM_BASE + CCM_CGR1); + reg |= 0x3 << CCM_CGR1_FEC_SHIFT; + reg = writel(reg, IMX_CCM_BASE + CCM_CGR1); + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, IMX_AIPS1_BASE); + writel(0x77777777, IMX_AIPS1_BASE + 0x4); + writel(0x77777777, IMX_AIPS2_BASE); + writel(0x77777777, IMX_AIPS2_BASE + 0x4); + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + writel(0x0, IMX_AIPS1_BASE + 0x40); + writel(0x0, IMX_AIPS1_BASE + 0x44); + writel(0x0, IMX_AIPS1_BASE + 0x48); + writel(0x0, IMX_AIPS1_BASE + 0x4C); + reg = readl(IMX_AIPS1_BASE + 0x50); + reg &= 0x00FFFFFF; + writel(reg, IMX_AIPS1_BASE + 0x50); + + writel(0x0, IMX_AIPS2_BASE + 0x40); + writel(0x0, IMX_AIPS2_BASE + 0x44); + writel(0x0, IMX_AIPS2_BASE + 0x48); + writel(0x0, IMX_AIPS2_BASE + 0x4C); + reg = readl(IMX_AIPS2_BASE + 0x50); + reg &= 0x00FFFFFF; + writel(reg, IMX_AIPS2_BASE + 0x50); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup */ + + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_PARAM1 0x00302154 + writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + + /* SGPCR - always park on last master */ + writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ + writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ + writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ + writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ + writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + + /* MGPCR - restore default values */ + writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ + writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ + writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ + writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ + writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ + writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + writel(0x40, IMX_M3IF_BASE); + + return 0; +} + +core_initcall(eukrea_cpuimx35_core_init); + +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) + +static int do_cpufreq(struct command *cmdtp, int argc, char *argv[]) +{ + unsigned long freq; + + if (argc != 2) + return COMMAND_ERROR_USAGE; + + freq = simple_strtoul(argv[1], NULL, 0); + + switch (freq) { + case 399: + writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); + break; + case 532: + writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + break; + default: + return COMMAND_ERROR_USAGE; + } + + printf("Switched CPU frequency to %dMHz\n", freq); + + return 0; +} + +static const __maybe_unused char cmd_cpufreq_help[] = +"Usage: cpufreq 399|532\n" +"\n" +"Set CPU frequency to <freq> MHz\n"; + +BAREBOX_CMD_START(cpufreq) + .cmd = do_cpufreq, + .usage = "adjust CPU frequency", + BAREBOX_CMD_HELP(cmd_cpufreq_help) +BAREBOX_CMD_END diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.dox b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.dox new file mode 100644 index 0000000000..cbdf69db35 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.dox @@ -0,0 +1,4 @@ +/** @page eukrea_cpuimx35 Eukrea's CPUIMX35 + + +*/ diff --git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c new file mode 100644 index 0000000000..a0ccf5c8f7 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c @@ -0,0 +1,60 @@ +#include <common.h> +#include <mach/imx-flash-header.h> + +extern unsigned long _stext; + +void __naked __flash_header_start go(void) +{ + __asm__ __volatile__("b exception_vectors\n"); +} + +struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = { + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, }, + { .ptr_type = 1, .addr = 0x80000400, .val = 0x12345678, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, }, + { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, }, + { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82220080, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82228080, }, + { .ptr_type = 4, .addr = 0xB8001020, .val = 0x80000028, }, + { .ptr_type = 4, .addr = 0xB8001024, .val = 0x80000028, }, + { .ptr_type = 4, .addr = 0xB8001028, .val = 0x80000028, }, + { .ptr_type = 4, .addr = 0xB800102c, .val = 0x80000028, }, + { .ptr_type = 4, .addr = 0xB8001030, .val = 0x80000028, }, +}; + +#define APP_DEST 0x80000000 + +struct imx_flash_header __flash_header_0x400 flash_header = { + .app_code_jump_vector = APP_DEST + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = APP_DEST, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof (dcd_entry), +}; + +unsigned long __image_len_0x400 barebox_len = 0x40000; + diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c new file mode 100644 index 0000000000..44f3cf0725 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -0,0 +1,218 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <init.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <mach/esdctl.h> +#include <asm/cache-l2x0.h> +#include <asm/io.h> +#include <mach/imx-nand.h> +#include <asm/barebox-arm.h> +#include <asm-generic/memory_layout.h> +#include <asm/system.h> + +/* Assuming 24MHz input clock */ +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) +#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) + +#ifdef CONFIG_NAND_IMX_BOOT +static void __bare_init __naked insdram(void) +{ + uint32_t r; + + /* Speed up NAND controller by adjusting the NFC divider */ + r = readl(IMX_CCM_BASE + CCM_PDR4); + r &= ~(0xf << 28); + r |= 0x1 << 28; + writel(r, IMX_CCM_BASE + CCM_PDR4); + + /* setup a stack to be able to call imx_nand_load_image() */ + r = STACK_BASE + STACK_SIZE - 12; + __asm__ __volatile__("mov sp, %0" : : "r"(r)); + + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); + + board_init_lowlevel_return(); +} +#endif + +void __bare_init __naked board_init_lowlevel(void) +{ + uint32_t r, s; + unsigned long ccm_base = IMX_CCM_BASE; + unsigned long iomuxc_base = IMX_IOMUXC_BASE; +#ifdef CONFIG_NAND_IMX_BOOT + unsigned int *trg, *src; + int i; +#endif + + r = get_cr(); + r |= CR_Z; /* Flow prediction (Z) */ + r |= CR_U; /* unaligned accesses */ + r |= CR_FI; /* Low Int Latency */ + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s)); + s |= 0x7; + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s)); + + set_cr(r); + + r = 0; + __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); + + /* + * Branch predicition is now enabled. Flush the BTAC to ensure a valid + * starting point. Don't flush BTAC while it is disabled to avoid + * ARM1136 erratum 408023. + */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r)); + + /* invalidate I cache and D cache */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r)); + + /* invalidate TLBs */ + __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r)); + + /* Drain the write buffer */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r)); + + /* Also setup the Peripheral Port Remap register inside the core */ + r = 0x40000015; /* start from AIPS 2GB region */ + __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); + + /* + * End of ARM1136 init + */ + + writel(0x003F4208, ccm_base + CCM_CCMR); + + /* Set MPLL , arm clock and ahb clock*/ + writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL); + + writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); + writel(0x00001000, ccm_base + CCM_PDR0); + + r = readl(ccm_base + CCM_CGR0); + r |= 0x00300000; + writel(r, ccm_base + CCM_CGR0); + + r = readl(ccm_base + CCM_CGR1); + r |= 0x00000C00; + r |= 0x00000003; + writel(r, ccm_base + CCM_CGR1); + + r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL); + r |= 0x1000; + writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0x80000000 && r < 0x90000000) + board_init_lowlevel_return(); + + /* Set DDR Type to SDRAM, drive strength workaround * + * 0x00000000 MDDR * + * 0x00000800 3,3V SDRAM */ + + r = 0x00000800; + writel(r, iomuxc_base + 0x794); + writel(r, iomuxc_base + 0x798); + writel(r, iomuxc_base + 0x79c); + writel(r, iomuxc_base + 0x7a0); + writel(r, iomuxc_base + 0x7a4); + + /* MDDR init, enable mDDR*/ + writel(0x00000304, ESDMISC); /* was 0x00000004 */ + + /* set timing paramters */ + writel(0x00255417, ESDCFG0); + /* select Precharge-All mode */ + writel(0x92220000, ESDCTL0); + /* Precharge-All */ + writel(0x12345678, IMX_SDRAM_CS0 + 0x400); + + /* select Load-Mode-Register mode */ + writel(0xB8001000, ESDCTL0); + /* Load reg EMR2 */ + writeb(0xda, 0x84000000); + /* Load reg EMR3 */ + writeb(0xda, 0x86000000); + /* Load reg EMR1 -- enable DLL */ + writeb(0xda, 0x82000400); + /* Load reg MR -- reset DLL */ + writeb(0xda, 0x80000333); + + /* select Precharge-All mode */ + writel(0x92220000, ESDCTL0); + /* Precharge-All */ + writel(0x12345678, IMX_SDRAM_CS0 + 0x400); + + /* select Manual-Refresh mode */ + writel(0xA2220000, ESDCTL0); + /* Manual-Refresh 2 times */ + writel(0x87654321, IMX_SDRAM_CS0); + writel(0x87654321, IMX_SDRAM_CS0); + + /* select Load-Mode-Register mode */ + writel(0xB2220000, ESDCTL0); + /* Load reg MR -- CL3, BL8, end DLL reset */ + writeb(0xda, 0x80000233); + /* Load reg EMR1 -- OCD default */ + writeb(0xda, 0x82000780); + /* Load reg EMR1 -- OCD exit */ + writeb(0xda, 0x82000400); + + /* select normal-operation mode + * DSIZ32-bit, BL8, COL10-bit, ROW13-bit + * disable PWT & PRCT + * disable Auto-Refresh */ + writel(0x82220080, ESDCTL0); + + /* enable Auto-Refresh */ + writel(0x82228080, ESDCTL0); + /* enable Auto-Refresh */ + writel(0x00002000, ESDCTL1); + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)IMX_NFC_BASE; + trg = (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ + for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ + r = (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} + diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c new file mode 100644 index 0000000000..a77a02d498 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c @@ -0,0 +1,354 @@ +/* + * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <asm/armlinux.h> +#include <mach/gpio.h> +#include <asm/io.h> +#include <partition.h> +#include <asm/mach-types.h> +#include <mach/imx-nand.h> +#include <fec.h> +#include <nand.h> +#include <mach/imx-flash-header.h> +#include <mach/iomux-mx25.h> +#include <linux/err.h> +#include <i2c/i2c.h> +#include <i2c/mc34704.h> + +extern unsigned long _stext; + +void __naked __flash_header_start go(void) +{ + __asm__ __volatile__("b exception_vectors\n"); +} + +struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = { + { .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, }, + { .ptr_type = 4, .addr = 0xb8002054, .val = 0x22252521, }, + { .ptr_type = 4, .addr = 0xb8002058, .val = 0x22220a00, }, +#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2 + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, + { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000304, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, + { .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, + { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x83000000, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x80000333, .val = 0xda, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, + { .ptr_type = 4, .addr = 0x80000400, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2210000, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, + { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000780, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, +#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR + { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, }, + { .ptr_type = 1, .addr = 0x80000400, .val = 0x21, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, }, + { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000000, .val = 0xff, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216880, }, + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, }, +#else +#error "Unsupported SDRAM type" +#endif + { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, +}; + +#define APP_DEST 0x80000000 + +struct imx_flash_header __flash_header_0x400 mx25_3ds_header = { + .app_code_jump_vector = APP_DEST + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = APP_DEST, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof (dcd_entry), +}; + +extern unsigned long __bss_start; + +unsigned long __image_len_0x400 barebox_len = 0x40000; + +static struct fec_platform_data fec_info = { + .xcv_type = RMII, + .phy_addr = 1, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = IMX_FEC_BASE, + .platform_data = &fec_info, +}; + +static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram0_dev = { + .name = "mem", + .map_base = IMX_SDRAM_CS0, +#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2 + .size = 64 * 1024 * 1024, +#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR + .size = 128 * 1024 * 1024, +#else +#error "Unsupported SDRAM type" +#endif + .platform_data = &sdram_pdata, +}; + +static struct memory_platform_data sram_pdata = { + .name = "sram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sram0_dev = { + .name = "mem", + .map_base = 0x78000000, + .size = 128 * 1024, + .platform_data = &sram_pdata, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = IMX_NFC_BASE, + .platform_data = &nand_info, +}; + +#ifdef CONFIG_USB +static void imx25_usb_init(void) +{ + unsigned int tmp; + + /* Host 2 */ + tmp = readl(IMX_OTG_BASE + 0x600); + tmp &= ~(3 << 21); + tmp |= (2 << 21) | (1 << 4) | (1 << 5); + writel(tmp, IMX_OTG_BASE + 0x600); + + tmp = readl(IMX_OTG_BASE + 0x584); + tmp |= 3 << 30; + writel(tmp, IMX_OTG_BASE + 0x584); + + /* Set to Host mode */ + tmp = readl(IMX_OTG_BASE + 0x5a8); + writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8); +} + +static struct device_d usbh2_dev = { + .name = "ehci", + .map_base = IMX_OTG_BASE + 0x400, + .size = 0x200, +}; +#endif + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("mc34704", 0x54), + }, +}; + +static struct device_d i2c_dev = { + .name = "i2c-imx", + .map_base = IMX_I2C1_BASE, +}; + +static int imx25_3ds_pmic_init(void) +{ + struct mc34704 *pmic; + + pmic = mc34704_get(); + if (pmic == NULL) + return -EIO; + + return mc34704_reg_write(pmic, 0x2, 0x9); +} + +static int imx25_3ds_fec_init(void) +{ + int ret; + + ret = imx25_3ds_pmic_init(); + if (ret < 0) + return ret; + + /* + * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. + * Assert FEC_RESET_B, then power up the PHY by asserting + * FEC_ENABLE, at the same time lifting FEC_RESET_B. + * + * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17 + * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12 + */ + writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */ + writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */ + +#define FEC_ENABLE_GPIO 35 +#define FEC_RESET_B_GPIO 104 + + /* make the pins output */ + gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */ + gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */ + udelay(2); + + /* turn on power & lift reset */ + gpio_set_value(FEC_ENABLE_GPIO, 1); + gpio_set_value(FEC_RESET_B_GPIO, 1); + + return 0; +} +late_initcall(imx25_3ds_fec_init); + +static int imx25_devices_init(void) +{ +#ifdef CONFIG_USB + /* USB does not work yet. Don't know why. Maybe + * the CPLD has to be initialized. + */ + imx25_usb_init(); + register_device(&usbh2_dev); +#endif + + register_device(&fec_dev); + + if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14)) + nand_info.width = 2; + + register_device(&nand_dev); + + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + register_device(&sdram0_dev); + register_device(&sram0_dev); + + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + register_device(&i2c_dev); + + armlinux_add_dram(&sdram0_dev); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_MX25_3DS); + + return 0; +} + +device_initcall(imx25_devices_init); + +static struct device_d imx25_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 16 * 1024, +}; + +static struct pad_desc imx25_pads[] = { + MX25_PAD_FEC_MDC__MDC, + MX25_PAD_FEC_MDIO__MDIO, + MX25_PAD_FEC_RDATA0__RDATA0, + MX25_PAD_FEC_RDATA1__RDATA1, + MX25_PAD_FEC_RX_DV__RX_DV, + MX25_PAD_FEC_TDATA0__TDATA0, + MX25_PAD_FEC_TDATA1__TDATA1, + MX25_PAD_FEC_TX_CLK__TX_CLK, + MX25_PAD_FEC_TX_EN__TX_EN, + MX25_PAD_POWER_FAIL__POWER_FAIL_INT, + MX25_PAD_A17__GPIO3, + MX25_PAD_D12__GPIO8, + /* UART1 */ + MX25_PAD_UART1_RXD__RXD_MUX, + MX25_PAD_UART1_TXD__TXD_MUX, + MX25_PAD_UART1_RTS__RTS, + MX25_PAD_UART1_CTS__CTS, + /* USBH2 */ + MX25_PAD_D9__USBH2_PWR, + MX25_PAD_D8__USBH2_OC, + MX25_PAD_LD0__USBH2_CLK, + MX25_PAD_LD1__USBH2_DIR, + MX25_PAD_LD2__USBH2_STP, + MX25_PAD_LD3__USBH2_NXT, + MX25_PAD_LD4__USBH2_DATA0, + MX25_PAD_LD5__USBH2_DATA1, + MX25_PAD_LD6__USBH2_DATA2, + MX25_PAD_LD7__USBH2_DATA3, + MX25_PAD_HSYNC__USBH2_DATA4, + MX25_PAD_VSYNC__USBH2_DATA5, + MX25_PAD_LSCLK__USBH2_DATA6, + MX25_PAD_OE_ACD__USBH2_DATA7, + /* i2c */ + MX25_PAD_I2C1_CLK__SCL, + MX25_PAD_I2C1_DAT__SDA, +}; + +static int imx25_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads)); + + writel(0x03010101, 0x53f80024); + + register_device(&imx25_serial_device); + return 0; +} + +console_initcall(imx25_console_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif + +static int imx25_core_setup(void) +{ + writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2); + return 0; + +} +core_initcall(imx25_core_setup); + diff --git a/arch/arm/boards/freescale-mx25-3-stack/Makefile b/arch/arm/boards/freescale-mx25-3-stack/Makefile new file mode 100644 index 0000000000..ab853e0d6b --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/Makefile @@ -0,0 +1,24 @@ +# +# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y += lowlevel_init.o +obj-y += 3stack.o diff --git a/arch/arm/boards/freescale-mx25-3-stack/config.h b/arch/arm/boards/freescale-mx25-3-stack/config.h new file mode 100644 index 0000000000..f35e8a0557 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/config.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Definitions related to passing arguments to kernel. + */ + +#define CONFIG_MX25_HCLK_FREQ 24000000 + +#endif + +/* nothing to do here yet */ diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/_update b/arch/arm/boards/freescale-mx25-3-stack/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/boot b/arch/arm/boards/freescale-mx25-3-stack/env/bin/boot new file mode 100644 index 0000000000..7bbff2d1f6 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/boot @@ -0,0 +1,47 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$1 = xnor ]; then + root=nor + kernel=nor +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +elif [ x$root = xnor ]; then + bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +elif [ $kernel = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/hush_hack b/arch/arm/boards/freescale-mx25-3-stack/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/init b/arch/arm/boards/freescale-mx25-3-stack/env/bin/init new file mode 100644 index 0000000000..0600b9e661 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/init @@ -0,0 +1,30 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nand|nor [<imagename>] to update kernel into flash" + echo "type update_root nand|nor [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_kernel b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_kernel new file mode 100644 index 0000000000..05c822d860 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_root b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_root new file mode 100644 index 0000000000..eaf36ebcea --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/config b/arch/arm/boards/freescale-mx25-3-stack/env/config new file mode 100644 index 0000000000..a5e492e339 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/config @@ -0,0 +1,29 @@ +#!/bin/sh + +# can be either 'net', 'nor' or 'nand'' +kernel=net +root=net + +uimage=uImage-pcm043 +jffs2=root-pcm043.jffs2 + +autoboot_timeout=3 + +nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root" +bootargs="console=ttymxc0,115200" + +nor_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),-(root)" +rootpart_nor="/dev/mtdblock3" + +nand_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),108416k(root),-(kernel1)" +rootpart_nand="/dev/mtdblock7" + +# use 'dhcp' to do dhcp in barebox and in kernel +#ip=dhcp + +# or set your networking parameters here +eth0.ipaddr=192.168.3.11 +eth0.netmask=255.255.255.0 +#eth0.gateway=a.b.c.d +eth0.serverip=192.168.3.10 +eth0.ethaddr=00:50:c2:8c:e6:0e diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S new file mode 100644 index 0000000000..73bb14723e --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S @@ -0,0 +1,253 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <mach/esdctl.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define writeb(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + strb r1, [r0]; + +/* Assuming 24MHz input clock */ +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 (IMX_PLL_PD(1) | IMX_PLL_MFD(0) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) +#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) + +.section ".text_bare_init","ax" + +ARM_PPMRR: .word 0x40000015 +L2CACHE_PARAM: .word 0x00030024 +CCM_CCMR_W: .word 0x003F4208 +CCM_PDR0_W: .word 0x00801000 +MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 +MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 +PPCTL_PARAM_W: .word PPCTL_PARAM_300 +CCM_BASE_ADDR_W: .word IMX_CCM_BASE + +.globl board_init_lowlevel +board_init_lowlevel: + mov r10, lr + +#define MX25_CCM_MCR 0x64 + + ldr r0, CCM_BASE_ADDR_W + /* default CLKO to 1/32 of the ARM core */ + ldr r1, [r0, #MX25_CCM_MCR] + bic r1, r1, #0x00F00000 + bic r1, r1, #0x7F000000 + mov r2, #0x5F000000 + add r2, r2, #0x00200000 + orr r1, r1, r2 + str r1, [r0, #MX25_CCM_MCR] + + /* enable all the clocks */ + writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0) + writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1) + writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2) + writel(0x0000FEFF, IMX_CCM_BASE + MX25_CCM_MCR) + + /* Skip SDRAM initialization if we run from RAM */ + cmp pc, #0x80000000 + bls 1f + cmp pc, #0x90000000 + bhi 1f + + mov pc, lr + +1: + ldr r0, ESDCTL_BASE_W + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + mov r12, #0x00 + mov r2, #0x1 /* mDDR */ + mov r1, #IMX_SDRAM_CS0 + bl setup_sdram_bank +// cmp r3, #0x0 +// orreq r12, r12, #1 +// eorne r2, r2, #0x1 +// blne setup_sdram_bank + + ldr r3, ESDCTL_DELAY5 + str r3, [r0, #0x30] + +#ifdef CONFIG_NAND_IMX_BOOT + ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */ + + ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ + ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + + /* skip NAND boot if not running from NFC space */ + cmp pc, r0 + bls ret + cmp pc, r2 + bhi ret + + /* Move ourselves out of NFC SRAM */ + ldr r1, =TEXT_BASE + +copy_loop: + ldmia r0!, {r3-r9} /* copy from source address [r0] */ + stmia r1!, {r3-r9} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + ldr pc, =1f /* Jump to SDRAM */ +1: + bl nand_boot /* Load barebox from NAND Flash */ + + ldr r1, =IMX_NFC_BASE - TEXT_BASE + sub r10, r10, r1 /* adjust return address from NFC SRAM */ + /* to SDRAM */ + +#endif /* CONFIG_NAND_IMX_BOOT */ + +ret: + mov pc, r10 + +/* + * r0: control base, r1: ram bank base + * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working + */ +setup_sdram_bank: + mov r3, #0xE /* 0xA + 0x4 */ + tst r2, #0x1 + orreq r3, r3, #0x300 /* DDR2 */ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: adr r4, ESDCTL_CONFIG + tst r2, #0x1 + ldreq r3, [r4, #0x0] + ldrne r3, [r4, #0x4] + cmp r1, #IMX_SDRAM_CS1 + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, RAM_PARAM1_MDDR + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #IMX_SDRAM_CS1 + ldr r3, ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, RAM_PARAM4_MDDR + strb r3, [r1, r4] + ldr r4, RAM_PARAM5_MDDR + strb r3, [r1, r4] + ldr r4, RAM_PARAM3_MDDR + strb r3, [r1, r4] + ldr r4, RAM_PARAM2_MDDR + strb r3, [r1, r4] + + ldr r3, ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, RAM_PARAM1_MDDR + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #IMX_SDRAM_CS1 + ldr r3, ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + adr r4, RAM_PARAM6_MDDR + tst r2, #0x1 + ldreq r4, [r4, #0x0] + ldrne r4, [r4, #0x4] + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, RAM_PARAM7_MDDR + streqb r3, [r1, r4] + adr r4, RAM_PARAM3_MDDR + ldreq r4, [r4, #0x0] + ldrne r4, [r4, #0x4] + strb r3, [r1, r4] + + cmp r1, #IMX_SDRAM_CS1 + ldr r3, ESDCTL_0x82226080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr + +RAM_PARAM1_MDDR: .word 0x00000400 +RAM_PARAM2_MDDR: .word 0x00000333 +RAM_PARAM3_MDDR: .word 0x02000400 + .word 0x02000000 +RAM_PARAM4_MDDR: .word 0x04000000 +RAM_PARAM5_MDDR: .word 0x06000000 +RAM_PARAM6_MDDR: .word 0x00000233 + .word 0x00000033 +RAM_PARAM7_MDDR: .word 0x02000780 +ESDCTL_0x92220000: .word 0x92210000 +ESDCTL_0xA2220000: .word 0xA2210000 +ESDCTL_0xB2220000: .word 0xB2210000 +ESDCTL_0x82226080: .word 0x82216080 +ESDCTL_CONFIG: .word 0x007FFC3F + .word 0x007FFC3F +ESDCTL_DELAY5: .word 0x00F49F00 +ESDCTL_BASE_W: .word IMX_ESD_BASE + diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c new file mode 100644 index 0000000000..9a66976f9d --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c @@ -0,0 +1,498 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * 2009 Marc Kleine-Budde, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from: + * + * * mx35_3stack.c - board file for uboot-v1 + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + */ + +#include <common.h> +#include <environment.h> +#include <errno.h> +#include <fcntl.h> +#include <fec.h> +#include <fs.h> +#include <init.h> +#include <nand.h> +#include <net.h> +#include <partition.h> + +#include <asm/armlinux.h> +#include <asm/io.h> +#include <asm/mach-types.h> + +#include <mach/gpio.h> +#include <mach/imx-nand.h> +#include <mach/imx-regs.h> +#include <mach/iomux-mx35.h> +#include <mach/iomux-v3.h> +#include <mach/pmic.h> +#include <mach/imx-ipu-fb.h> +#include <mach/generic.h> + +#include <i2c/i2c.h> +#include <i2c/mc13892.h> +#include <i2c/mc9sdz60.h> + + +/* Board rev for the PDK 3stack */ +#define MX35PDK_BOARD_REV_1 0 +#define MX35PDK_BOARD_REV_2 1 + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = IMX_CS0_BASE, + .size = 64 * 1024 * 1024, +}; + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 0x1F, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = IMX_FEC_BASE, + .platform_data = &fec_info, +}; + +static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = IMX_SDRAM_CS0, + .size = 128 * 1024 * 1024, + .platform_data = &sdram_pdata, +}; + +struct imx_nand_platform_data nand_info = { + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = IMX_NFC_BASE, + .platform_data = &nand_info, +}; + +static struct device_d smc911x_dev = { + .name = "smc911x", + .map_base = IMX_CS5_BASE, + .size = IMX_CS5_RANGE, +}; + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("mc13892", 0x08), + }, { + I2C_BOARD_INFO("mc9sdz60", 0x69), + }, +}; + +static struct device_d i2c_dev = { + .name = "i2c-imx", + .map_base = IMX_I2C1_BASE, +}; + +/* + * Generic display, shipped with the PDK + */ +static struct fb_videomode CTP_CLAA070LC0ACW = { + /* 800x480 @ 60 Hz */ + .name = "CTP-CLAA070LC0ACW", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(27000), + .left_margin = 50, + .right_margin = 50, /* whole line should have 900 clocks */ + .upper_margin = 10, + .lower_margin = 10, /* whole frame should have 500 lines */ + .hsync_len = 1, /* note: DE only display */ + .vsync_len = 1, /* note: DE only display */ + .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct imx_ipu_fb_platform_data ipu_fb_data = { + .mode = &CTP_CLAA070LC0ACW, + .bpp = 16, +}; + +static struct device_d imxfb_dev = { + .name = "imx-ipu-fb", + .map_base = 0x53fc0000, + .size = 0x1000, + .platform_data = &ipu_fb_data, +}; + +/* + * Revision to be passed to kernel. The kernel provided + * by freescale relies on this. + * + * C --> CPU type + * S --> Silicon revision + * B --> Board rev + * + * 31 20 16 12 8 4 0 + * | Cmaj | Cmin | B | Smaj | Smin| + * + * e.g 0x00035120 --> i.MX35, Cpu silicon rev 2.0, Board rev 2 +*/ +static unsigned int imx35_3ds_system_rev = 0x00035000; + +static void set_silicon_rev( int rev) +{ + imx35_3ds_system_rev = imx35_3ds_system_rev | (rev & 0xFF); +} + +static void set_board_rev(int rev) +{ + imx35_3ds_system_rev = (imx35_3ds_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8; +} + + +static int f3s_devices_init(void) +{ + uint32_t reg; + + /* CS0: Nor Flash */ + writel(0x0000cf03, CSCR_U(0)); + writel(0x10000d03, CSCR_L(0)); + writel(0x00720900, CSCR_A(0)); + + reg = readl(IMX_CCM_BASE + CCM_RCSR); + /* some fuses provide us vital information about connected hardware */ + if (reg & 0x20000000) + nand_info.width = 2; /* 16 bit */ + else + nand_info.width = 1; /* 8 bit */ + + /* + * This platform supports NOR and NAND + */ + register_device(&nand_dev); + register_device(&cfi_dev); + + switch ((reg >> 25) & 0x3) { + case 0x01: /* NAND is the source */ + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + break; + + case 0x00: /* NOR is the source */ + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 0x80000, PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + break; + } + + set_silicon_rev(imx_silicon_revision()); + + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + register_device(&i2c_dev); + + register_device(&fec_dev); + register_device(&smc911x_dev); + + register_device(&sdram_dev); + register_device(&imxfb_dev); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_MX35_3DS); + + return 0; +} + +device_initcall(f3s_devices_init); + +static int f3s_enable_display(void) +{ + /* Enable power to the LCD. (bit 6 hi.) */ + mc9sdz60_set_bits(mc9sdz60_get(), MC9SDZ60_REG_GPIO_1, 0x40, 0x40); + + return 0; +} + +late_initcall(f3s_enable_display); + +static struct device_d f3s_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static struct pad_desc f3s_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + + MX35_PAD_RXD1__UART1_RXD_MUX, + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RTS1__UART1_RTS, + MX35_PAD_CTS1__UART1_CTS, + + MX35_PAD_I2C1_CLK__I2C1_SCL, + MX35_PAD_I2C1_DAT__I2C1_SDA, + + MX35_PAD_WDOG_RST__GPIO1_6, + MX35_PAD_COMPARE__GPIO1_5, + + /* Display */ + MX35_PAD_LD0__IPU_DISPB_DAT_0, + MX35_PAD_LD1__IPU_DISPB_DAT_1, + MX35_PAD_LD2__IPU_DISPB_DAT_2, + MX35_PAD_LD3__IPU_DISPB_DAT_3, + MX35_PAD_LD4__IPU_DISPB_DAT_4, + MX35_PAD_LD5__IPU_DISPB_DAT_5, + MX35_PAD_LD6__IPU_DISPB_DAT_6, + MX35_PAD_LD7__IPU_DISPB_DAT_7, + MX35_PAD_LD8__IPU_DISPB_DAT_8, + MX35_PAD_LD9__IPU_DISPB_DAT_9, + MX35_PAD_LD10__IPU_DISPB_DAT_10, + MX35_PAD_LD11__IPU_DISPB_DAT_11, + MX35_PAD_LD12__IPU_DISPB_DAT_12, + MX35_PAD_LD13__IPU_DISPB_DAT_13, + MX35_PAD_LD14__IPU_DISPB_DAT_14, + MX35_PAD_LD15__IPU_DISPB_DAT_15, + MX35_PAD_LD16__IPU_DISPB_DAT_16, + MX35_PAD_LD17__IPU_DISPB_DAT_17, + MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, + MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, + MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, + MX35_PAD_CONTRAST__IPU_DISPB_CONTR, + MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, + MX35_PAD_D3_REV__IPU_DISPB_D3_REV, + MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, +}; + +static int f3s_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); + + register_device(&f3s_serial_device); + return 0; +} + +console_initcall(f3s_console_init); + +static int f3s_core_init(void) +{ + u32 reg; + + writel(0x0000D843, CSCR_U(5)); /* CS5: smc9117 */ + writel(0x22252521, CSCR_L(5)); + writel(0x22220A00, CSCR_A(5)); + + /* enable clock for I2C1 and FEC */ + reg = readl(IMX_CCM_BASE + CCM_CGR1); + reg |= 0x3 << CCM_CGR1_FEC_SHIFT; + reg |= 0x3 << CCM_CGR1_I2C1_SHIFT; + reg = writel(reg, IMX_CCM_BASE + CCM_CGR1); + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, IMX_AIPS1_BASE); + writel(0x77777777, IMX_AIPS1_BASE + 0x4); + writel(0x77777777, IMX_AIPS2_BASE); + writel(0x77777777, IMX_AIPS2_BASE + 0x4); + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + writel(0x0, IMX_AIPS1_BASE + 0x40); + writel(0x0, IMX_AIPS1_BASE + 0x44); + writel(0x0, IMX_AIPS1_BASE + 0x48); + writel(0x0, IMX_AIPS1_BASE + 0x4C); + reg = readl(IMX_AIPS1_BASE + 0x50); + reg &= 0x00FFFFFF; + writel(reg, IMX_AIPS1_BASE + 0x50); + + writel(0x0, IMX_AIPS2_BASE + 0x40); + writel(0x0, IMX_AIPS2_BASE + 0x44); + writel(0x0, IMX_AIPS2_BASE + 0x48); + writel(0x0, IMX_AIPS2_BASE + 0x4C); + reg = readl(IMX_AIPS2_BASE + 0x50); + reg &= 0x00FFFFFF; + writel(reg, IMX_AIPS2_BASE + 0x50); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup */ + + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_PARAM1 0x00302154 + writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + + /* SGPCR - always park on last master */ + writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ + writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ + writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ + writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ + writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + + /* MGPCR - restore default values */ + writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ + writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ + writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ + writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ + writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ + writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + + return 0; +} + +core_initcall(f3s_core_init); + +static int f3s_get_rev(struct mc13892 *mc13892) +{ + u32 rev; + int err; + + err = mc13892_reg_read(mc13892, MC13892_REG_IDENTIFICATION, &rev); + if (err) + return err; + + dev_info(&mc13892->client->dev, "revision: 0x%x\n", rev); + if (rev == 0x00ffffff) + return -ENODEV; + + return ((rev >> 6) & 0x7) ? MX35PDK_BOARD_REV_2 : MX35PDK_BOARD_REV_1; +} + +static int f3s_pmic_init_v2(struct mc13892 *mc13892) +{ + int err = 0; + + /* COMPARE pin (GPIO1_5) as output and set high */ + gpio_direction_output( 32*0 + 5 , 1); + + err |= mc13892_set_bits(mc13892, MC13892_REG_SETTING_0, 0x03, 0x03); + err |= mc13892_set_bits(mc13892, MC13892_REG_MODE_0, 0x01, 0x01); + if (err) + dev_err(&mc13892->client->dev, + "Init sequence failed, the system might not be working!\n"); + + return err; +} + +static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60) +{ + int err = 0; + + err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_1, 0x04, 0x04); + + err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x00); + mdelay(200); + err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x80); + + if (err) + dev_err(&mc9sdz60->client->dev, + "Init sequence failed, the system might not be working!\n"); + + return err; +} + +static int f3s_pmic_init(void) +{ + struct mc13892 *mc13892; + struct mc9sdz60 *mc9sdz60; + int rev; + + mc13892 = mc13892_get(); + if (!mc13892) { + printf("FAILED to get mc13892 handle!\n"); + return 0; + } + + rev = f3s_get_rev(mc13892); + switch (rev) { + case MX35PDK_BOARD_REV_1: + break; + case MX35PDK_BOARD_REV_2: + f3s_pmic_init_v2(mc13892); + break; + default: + printf("FAILED to identify board revision!\n"); + return 0; + } + + set_board_rev(rev); + printf("i.MX35 PDK CPU board version %d.\n", rev ); + + mc9sdz60 = mc9sdz60_get(); + if (!mc9sdz60) { + printf("FAILED to get mc9sdz60 handle!\n"); + return 0; + } + + f3s_pmic_init_all(mc9sdz60); + + armlinux_set_revision(imx35_3ds_system_rev); + + return 0; +} + +late_initcall(f3s_pmic_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + /* + * The driver is able to detect NAND's pagesize by CPU internal + * fuses or external pull ups. But not the blocksize... + */ + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.dox b/arch/arm/boards/freescale-mx35-3-stack/3stack.dox new file mode 100644 index 0000000000..15c5b6e1ff --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.dox @@ -0,0 +1,4 @@ +/** @page the3stack Freescale MX35 3-Stack Board + + +*/ diff --git a/arch/arm/boards/freescale-mx35-3-stack/Makefile b/arch/arm/boards/freescale-mx35-3-stack/Makefile new file mode 100644 index 0000000000..a8ea4a3d66 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/Makefile @@ -0,0 +1,4 @@ + +obj-y += lowlevel_init.o +obj-y += 3stack.o +obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o diff --git a/arch/arm/boards/freescale-mx35-3-stack/board-mx35_3stack.h b/arch/arm/boards/freescale-mx35-3-stack/board-mx35_3stack.h new file mode 100644 index 0000000000..c18066ad9c --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/board-mx35_3stack.h @@ -0,0 +1,107 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * (C) Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BOARD_MX35_3STACK_H +#define __BOARD_MX35_3STACK_H + +#define UNALIGNED_ACCESS_ENABLE +#define LOW_INT_LATENCY_ENABLE +#define BRANCH_PREDICTION_ENABLE + +#define L2CC_AUX_CTL_CONFIG 0x00030024 + +#define AIPS_MPR_CONFIG 0x77777777 +#define AIPS_OPACR_CONFIG 0x00000000 + +/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_MPR_CONFIG 0x00302154 +/* SGPCR - always park on last master */ +#define MAX_SGPCR_CONFIG 0x00000010 +/* MGPCR - restore default values */ +#define MAX_MGPCR_CONFIG 0x00000000 + +/* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ +#define M3IF_CONFIG 0x00000040 + +#define DBG_BASE_ADDR WEIM_CTRL_CS5 +#define DBG_CSCR_U_CONFIG 0x0000D843 +#define DBG_CSCR_L_CONFIG 0x22252521 +#define DBG_CSCR_A_CONFIG 0x22220A00 + +#define CCM_CCMR_CONFIG 0x003F4208 +#define CCM_PDR0_CONFIG 0x00821000 + +#define PLL_BRM_OFFSET 31 +#define PLL_PD_OFFSET 26 +#define PLL_MFD_OFFSET 16 +#define PLL_MFI_OFFSET 10 + +#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) +#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) +#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) +#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) +#define _PLL_MFN(x) (x) +#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ + (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ + _PLL_MFN(mfn)) + +#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) + +/*MEMORY SETING*/ +#define ESDCTL_0x92220000 0x92220000 +#define ESDCTL_0xA2220000 0xA2220000 +#define ESDCTL_0xB2220000 0xB2220000 +#define ESDCTL_0x82228080 0x82228080 + +#define ESDCTL_PRECHARGE 0x00000400 + +#define ESDCTL_MDDR_CONFIG 0x007FFC3F +#define ESDCTL_MDDR_MR 0x00000033 +#define ESDCTL_MDDR_EMR 0x02000000 + +#define ESDCTL_DDR2_CONFIG 0x007FFC3F +#define ESDCTL_DDR2_EMR2 0x04000000 +#define ESDCTL_DDR2_EMR3 0x06000000 +#define ESDCTL_DDR2_EN_DLL 0x02000400 +#define ESDCTL_DDR2_RESET_DLL 0x00000333 +#define ESDCTL_DDR2_MR 0x00000233 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 + +#define ESDCTL_DELAY_LINE5 0x00F49F00 +#endif /* __BOARD_MX35_3STACK_H */ diff --git a/arch/arm/boards/freescale-mx35-3-stack/config.h b/arch/arm/boards/freescale-mx35-3-stack/config.h new file mode 100644 index 0000000000..c724a57bd0 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/config.h @@ -0,0 +1,28 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Global defintions for the Freescale i.MX35 3-stack board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX35_HCLK_FREQ 24000000 + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/freescale-mx35-3-stack/env/bin/_update b/arch/arm/boards/freescale-mx35-3-stack/env/bin/_update new file mode 100644 index 0000000000..ddd6b84f72 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/env/bin/_update @@ -0,0 +1,39 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "Server did not reply! Update aborted." + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +echo +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part + +protect $part diff --git a/arch/arm/boards/freescale-mx35-3-stack/env/bin/boot b/arch/arm/boards/freescale-mx35-3-stack/env/bin/boot new file mode 100644 index 0000000000..fb2fe614d4 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/env/bin/boot @@ -0,0 +1,57 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + rootfs_loc=nand + kernel_loc=nand +elif [ x$1 = xnor ]; then + rootfs_loc=nor + kernel_loc=nor +elif [ x$1 = xnet ]; then + rootfs_loc=net + kernel_loc=net +fi + + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +elif [ x$ip != xno ]; then + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + + +if [ $rootfs_loc != net ]; then + if [ x$rootfs_loc = xnand ]; then + rootfs_mtdblock=$rootfs_mtdblock_nand + else + rootfs_mtdblock=$rootfs_mtdblock_nor + fi + + + if [ $rootfs_type = ubifs ]; then + bootargs="$bootargs root=ubi0:root ubi.mtd=$rootfs_mtdblock" + else + bootargs="$bootargs root=/dev/mtdblock$rootfs_mtdblock" + fi + + bootargs="$bootargs rootfstype=$rootfs_type" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + + +bootargs="$bootargs mtdparts=\"physmap-flash.0:$nor_parts;mxc_nand:$nand_parts\"" + +if [ $kernel_loc = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $kernel uImage || exit 1 + bootm uImage +elif [ $kernel_loc = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/freescale-mx35-3-stack/env/bin/hush_hack b/arch/arm/boards/freescale-mx35-3-stack/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/freescale-mx35-3-stack/env/bin/init b/arch/arm/boards/freescale-mx35-3-stack/env/bin/init new file mode 100644 index 0000000000..c982f22a86 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/env/bin/init @@ -0,0 +1,38 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" + saveenv +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nand|nor [<imagename>] to update kernel into flash" + echo "type update_rootfs nand|nor [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/freescale-mx35-3-stack/env/bin/update_kernel b/arch/arm/boards/freescale-mx35-3-stack/env/bin/update_kernel new file mode 100644 index 0000000000..63ad11aaed --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config +image=$kernel + +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/freescale-mx35-3-stack/env/bin/update_rootfs b/arch/arm/boards/freescale-mx35-3-stack/env/bin/update_rootfs new file mode 100644 index 0000000000..53dd2ca575 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/env/bin/update_rootfs @@ -0,0 +1,20 @@ +#!/bin/sh + +. /env/config + +if [ $rootfs_type = ubifs ]; then + image=${rootfs}.ubi +else + image=${rootfs}.$rootfs_type +fi + +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/freescale-mx35-3-stack/env/config b/arch/arm/boards/freescale-mx35-3-stack/env/config new file mode 100644 index 0000000000..51195f7404 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/env/config @@ -0,0 +1,35 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'no' if you don't want to pass the ip from barebox to the kernel +#ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net', 'nor' or 'nand'' +kernel_loc=nand +rootfs_loc=nand + +# can be either 'jffs2', or 'ubifs' +rootfs_type=ubifs + +kernel=uImage-mx35-3-stack +rootfs=root-mx35-3-stack +envimage=u-boot-v2-environment-mx35-3-stack + +autoboot_timeout=3 + +nfsroot="/path/to/nfs/root" +bootargs="console=ttymxc0,115200" + +bootargs="$bootargs video=mx3fb:CTP-CLAA070LC0ACW" + +nor_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nor=3 + +nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nand=7 diff --git a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c new file mode 100644 index 0000000000..171c499a6d --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c @@ -0,0 +1,49 @@ +#include <common.h> +#include <mach/imx-flash-header.h> + +extern unsigned long _stext; + +void __naked __flash_header_start go(void) +{ + __asm__ __volatile__("b exception_vectors\n"); +} + +struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = { + { .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, }, + { .ptr_type = 4, .addr = 0xB8002054, .val = 0x22252521, }, + { .ptr_type = 4, .addr = 0xB8002058, .val = 0x22220a00, }, + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, }, + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000030C, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, }, + { .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, }, + { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x82000780, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x82000400, .val = 0xda, }, + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82226080, }, + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, }, + { .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, }, + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, }, + { .ptr_type = 4, .addr = 0xB8001008, .val = 0x00002000, }, +}; + +#define APP_DEST 0x80000000 + +struct imx_flash_header __flash_header_0x400 flash_header = { + .app_code_jump_vector = APP_DEST + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = APP_DEST, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof (dcd_entry), +}; + +unsigned long __image_len_0x400 barebox_len = 0x40000; + diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S new file mode 100644 index 0000000000..1680579b51 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S @@ -0,0 +1,283 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <mach/esdctl.h> +#include <asm/cache-l2x0.h> +#include "board-mx35_3stack.h" + +#define CSD0_BASE_ADDR 0x80000000 +#define ESDCTL_BASE_ADDR 0xB8001000 +#define CSD1_BASE_ADDR 0x90000000 + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define writeb(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + strb r1, [r0]; + +/* Assuming 24MHz input clock */ +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) +#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) + + .section ".text_bare_init","ax" + +ARM_PPMRR: .word 0x40000015 +L2CACHE_PARAM: .word 0x00030024 +CCM_CCMR_W: .word 0x003F4208 +CCM_PDR0_W: .word 0x00001000 +MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 +MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 +PPCTL_PARAM_W: .word PPCTL_PARAM_300 +CCM_BASE_ADDR_W: .word IMX_CCM_BASE + +.globl board_init_lowlevel +board_init_lowlevel: + mov r10, lr + + mrc 15, 0, r1, c1, c0, 0 + + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 + + orr r1, r1, #(1 << 11) /* Flow prediction (Z) */ + orr r1, r1, #(1 << 22) /* unaligned accesses */ + orr r1, r1, #(1 << 21) /* Low Int Latency */ + + mcr 15, 0, r1, c1, c0, 0 + + mov r0, #0 + mcr 15, 0, r0, c15, c2, 4 + + /* + * Branch predicition is now enabled. Flush the BTAC to ensure a valid + * starting point. Don't flush BTAC while it is disabled to avoid + * ARM1136 erratum 408023. + */ + mov r0, #0 + mcr p15, 0, r0, c7, c5, 6 /* flush entire BTAC */ + + mov r0, #0 + mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + +/* + * End of ARM1136 init + */ + ldr r0, CCM_BASE_ADDR_W + + ldr r2, CCM_CCMR_W + str r2, [r0, #CCM_CCMR] + + ldr r3, MPCTL_PARAM_532_W /* consumer path*/ + + /* Set MPLL, arm clock and ahb clock */ + str r3, [r0, #CCM_MPCTL] + + ldr r1, PPCTL_PARAM_W + str r1, [r0, #CCM_PPCTL] + + ldr r1, CCM_PDR0_W + str r1, [r0, #CCM_PDR0] + + ldr r1, [r0, #CCM_CGR0] + orr r1, r1, #0x00300000 + str r1, [r0, #CCM_CGR0] + + ldr r1, [r0, #CCM_CGR1] + orr r1, r1, #0x00000C00 + orr r1, r1, #0x00000003 + str r1, [r0, #CCM_CGR1] + + /* Skip SDRAM initialization if we run from RAM */ + cmp pc, #0x80000000 + bls 1f + cmp pc, #0x90000000 + bhi 1f + + mov pc, r10 + +1: + ldr r0, =ESDCTL_BASE_ADDR + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + /* ip(r12) has used to save lr register in upper calling */ + mov fp, lr + + mov r5, #0x00 + mov r2, #0x00 + mov r1, #CSD0_BASE_ADDR + bl setup_sdram_bank + cmp r3, #0x0 + orreq r5, r5, #1 + eorne r2, r2, #0x1 + blne setup_sdram_bank + + mov lr, fp + + ldr r3, =ESDCTL_DELAY_LINE5 + str r3, [r0, #0x30] + +#ifdef CONFIG_NAND_IMX_BOOT + ldr sp, =TEXT_BASE - 4 /* Setup a temporary stack in SDRAM */ + + ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ + ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */ + + /* skip NAND boot if not running from NFC space */ + cmp pc, r0 + blo ret + cmp pc, r2 + bhs ret + + /* Move ourselves out of NFC SRAM */ + ldr r1, =TEXT_BASE + +copy_loop: + ldmia r0!, {r3-r9} /* copy from source address [r0] */ + stmia r1!, {r3-r9} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + ldr pc, =1f /* Jump to SDRAM */ +1: + bl nand_boot /* Load barebox from NAND Flash */ + + /* rebase the return address */ + ldr r1, =IMX_NFC_BASE - TEXT_BASE + sub r10, r10, r1 /* adjust return address from NFC SRAM */ +ret: +#endif /* CONFIG_NAND_IMX_BOOT */ + + mov pc, r10 + +/* + * r0: ESDCTL control base, r1: sdram slot base + * r2: DDR type (0: DDR2, 1: MDDR) r3, r4: working base + */ +setup_sdram_bank: + mov r3, #0xE /* 0xA + 0x4 */ + tst r2, #0x1 + orreq r3, r3, #0x300 /* DDR2 */ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: tst r2, #0x1 + ldreq r3, =ESDCTL_DDR2_CONFIG + ldrne r3, =ESDCTL_MDDR_CONFIG + cmp r1, #CSD1_BASE_ADDR + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_DDR2_EMR2 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EMR3 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EN_DLL + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_RESET_DLL + strb r3, [r1, r4] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + tst r2, #0x1 + ldreq r4, =ESDCTL_DDR2_MR + ldrne r4, =ESDCTL_MDDR_MR + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT + streqb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_EN_DLL + ldrne r4, =ESDCTL_MDDR_EMR + strb r3, [r1, r4] + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0x82228080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr diff --git a/arch/arm/boards/guf-neso/Makefile b/arch/arm/boards/guf-neso/Makefile new file mode 100644 index 0000000000..2b6eb02595 --- /dev/null +++ b/arch/arm/boards/guf-neso/Makefile @@ -0,0 +1,5 @@ + +obj-y += lowlevel.o +obj-y += board.o +obj-y += pll_init.o + diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c new file mode 100644 index 0000000000..2f53d34556 --- /dev/null +++ b/arch/arm/boards/guf-neso/board.c @@ -0,0 +1,401 @@ +/* + * Copyright (C) 2010 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <fec.h> +#include <notifier.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <nand.h> +#include <command.h> +#include <spi/spi.h> +#include <usb/isp1504.h> + +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> + +#include <mach/gpio.h> +#include <mach/spi.h> +#include <mach/imx-regs.h> +#include <mach/iomux-mx27.h> +#include <mach/imx-nand.h> +#include <mach/imx-pll.h> +#include <mach/imxfb.h> + +/* two pins are controlling the CS signals to the USB phys */ +#define USBH2_PHY_CS_GPIO (GPIO_PORTF + 20) +#define OTG_PHY_CS_GPIO (GPIO_PORTF + 19) + +/* two pins are controlling the display and its backlight */ +#define LCD_POWER_GPIO (GPIO_PORTF + 18) +#define BACKLIGHT_POWER_GPIO (GPIO_PORTE + 5) + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0xa0000000, + .size = 128 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 31, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = 0x1002b000, + .platform_data = &fec_info, +}; + +static struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = 0xd8000000, + .platform_data = &nand_info, +}; + +static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "CPT CLAA070LC0JCT", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(27000), + .hsync_len = 1, /* DE only sync */ + .left_margin = 50, + .right_margin = 50, + .vsync_len = 1, /* DE only sync */ + .upper_margin = 10, + .lower_margin = 10, + }, + /* + * - TFT style panel + * - clk enabled while idle + * - clock inverted + * - data not inverted + * - data enable high active + */ + .pcr = PCR_TFT | + PCR_COLOR | + PCR_PBSIZ_8 | + PCR_BPIX_16 | + PCR_CLKPOL | + PCR_SCLK_SEL | + PCR_LPPOL | + PCR_FLMPOL, + .bpp = 16, /* TODO 32 bit does not work: The 'green' component is lacking in this mode */ +}; + +static void neso_fb_enable(int enable) +{ + gpio_direction_output(LCD_POWER_GPIO, enable); + gpio_direction_output(BACKLIGHT_POWER_GPIO, enable); +} + +static struct imx_fb_platform_data neso_fb_data = { + .mode = &imxfb_mode, + .pwmr = 0x00000000, /* doesn't matter */ + .lscr1 = 0x00120300, /* doesn't matter */ + /* dynamic mode -> using the reset values (as recommended in the datasheet) */ + .dmacr = (0 << 31) | (4 << 16) | 96, + .enable = neso_fb_enable, + .framebuffer_ovl = (void *)0xa7f00000, +}; + +static struct device_d imxfb_dev = { + .name = "imxfb", + .map_base = 0x10021000, + .size = 0x1000, + .platform_data = &neso_fb_data, +}; + +#ifdef CONFIG_USB + +static struct device_d usbh2_dev = { + .name = "ehci", + .map_base = IMX_OTG_BASE + 0x400, + .size = 0x200, +}; + +static void neso_usbh_init(void) +{ + uint32_t temp; + + temp = readl(IMX_OTG_BASE + 0x600); + temp &= ~((3 << 21) | 1); + temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20) | (1<<11); + writel(temp, IMX_OTG_BASE + 0x600); + + temp = readl(IMX_OTG_BASE + 0x584); + temp &= ~(3 << 30); + temp |= 2 << 30; + writel(temp, IMX_OTG_BASE + 0x584); + + mdelay(10); + + gpio_set_value(USBH2_PHY_CS_GPIO, 0); + mdelay(10); + isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x570), 1); +} +#endif + +#ifdef CONFIG_MMU +static void neso_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + mmu_enable(); +} +#else +static void neso_mmu_init(void) +{ +} +#endif + +static int neso_devices_init(void) +{ + int i; + + unsigned int mode[] = { + /* UART1 */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + /* FEC */ + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + + /* SSI1 connected in AC97 style */ + PC20_PF_SSI1_FS, + PC21_PF_SSI1_RXD, + PC22_PF_SSI1_TXD, + PC23_PF_SSI1_CLK, + + /* LED 1 */ + (GPIO_PORTB | 15 | GPIO_GPIO | GPIO_OUT), + /* LED 2 */ + (GPIO_PORTB | 16 | GPIO_GPIO | GPIO_OUT), + /* CTOUCH reset */ + (GPIO_PORTB | 17 | GPIO_GPIO | GPIO_OUT), + /* CTOUCH IRQ */ + (GPIO_PORTB | 14 | GPIO_GPIO | GPIO_IN), + /* RTC IRQ */ + (GPIO_PORTF | 14 | GPIO_GPIO | GPIO_IN), + /* SD change card detection */ + (GPIO_PORTF | 17 | GPIO_GPIO | GPIO_IN), + /* SDHC1*/ + PE18_PF_SD1_D0, + PE19_PF_SD1_D1, + PE20_PF_SD1_D2, + PE21_PF_SD1_D3, + PE22_PF_SD1_CMD, + PE23_PF_SD1_CLK, + /* I2C1 */ + PD17_PF_I2C_DATA, + PD18_PF_I2C_CLK, + /* I2C2, for CTOUCH */ + PC5_PF_I2C2_SDA, + PC6_PF_I2C2_SCL, + + /* Connected to: Both USB phys and ethernet phy FIXME 1 = RESET? */ + PE17_PF_RESET_OUT, + + /* USB host */ + (USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT), + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD22_AF_USBH2_DATA0, + PD24_AF_USBH2_DATA1, + PD23_AF_USBH2_DATA2, + PD20_AF_USBH2_DATA3, + PD19_AF_USBH2_DATA4, + PD26_AF_USBH2_DATA5, + PD21_AF_USBH2_DATA6, + PA2_PF_USBH2_DATA7, + + /* USB OTG */ + (OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT), + PE24_PF_USBOTG_CLK, + PE2_PF_USBOTG_DIR, + PE0_PF_USBOTG_NXT, + PE1_PF_USBOTG_STP, + PC9_PF_USBOTG_DATA0, + PC11_PF_USBOTG_DATA1, + PC10_PF_USBOTG_DATA2, + PC13_PF_USBOTG_DATA3, + PC12_PF_USBOTG_DATA4, + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PE25_PF_USBOTG_DATA7, + + /* Display signals */ + (LCD_POWER_GPIO | GPIO_GPIO | GPIO_OUT), /* LCD power: 1 = LCD on */ + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA31_PF_OE_ACD, /* DE */ + + /* Backlight PWM (Use as gpio) */ + (BACKLIGHT_POWER_GPIO | GPIO_GPIO | GPIO_OUT), + }; + + /* reset the chip select lines to the USB/OTG phys to avoid any hang */ + gpio_direction_output(OTG_PHY_CS_GPIO, 1); + gpio_direction_output(USBH2_PHY_CS_GPIO, 1); + + + neso_mmu_init(); + + /* initialize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + register_device(&nand_dev); + register_device(&sdram_dev); + register_device(&imxfb_dev); + +#ifdef CONFIG_USB + neso_usbh_init(); + register_device(&usbh2_dev); +#endif + + register_device(&fec_dev); + + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0xa0000100); + armlinux_set_architecture(MACH_TYPE_NESO); + + return 0; +} + +device_initcall(neso_devices_init); + +static struct device_d neso_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static int neso_console_init(void) +{ + register_device(&neso_serial_device); + + return 0; +} + +console_initcall(neso_console_init); + +extern void *neso_pll_init, *neso_pll_init_end; + +static int neso_pll(void) +{ + void *vram = (void *)0xffff4c00; + void (*pllfunc)(void) = vram; + + printf("initialising PLLs\n"); + + memcpy(vram, &neso_pll_init, 0x100); + + console_flush(); + + pllfunc(); + + /* clock gating enable */ + GPCR = 0x00050f08; + + PCDR0 = 0x130410c3; + PCDR1 = 0x09030911; + + /* Clocks have changed. Notify clients */ + clock_notifier_call_chain(); + + return 0; +} + +late_initcall(neso_pll); + diff --git a/arch/arm/boards/guf-neso/config.h b/arch/arm/boards/guf-neso/config.h new file mode 100644 index 0000000000..c2f5e7cc58 --- /dev/null +++ b/arch/arm/boards/guf-neso/config.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Global defintions for the ARM i.MX27 based pcm038 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/guf-neso/env/config b/arch/arm/boards/guf-neso/env/config new file mode 100644 index 0000000000..6327e69217 --- /dev/null +++ b/arch/arm/boards/guf-neso/env/config @@ -0,0 +1,53 @@ +#!/bin/sh + +machine=guf-neso +eth0.serverip= +user= + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net', 'nor' or 'nand' +kernel_loc=net +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root-$machine.$rootfs_type + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +kernelimage_type=zimage +kernelimage=zImage-$machine +#kernelimage_type=uimage +#kernelimage=uImage-$machine +#kernelimage_type=raw +#kernelimage=Image-$machine +#kernelimage_type=raw_lzo +#kernelimage=Image-$machine.lzo + +if [ -n $user ]; then + kernelimage="$user"-"$kernelimage" + nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine" + rootfsimage="$user"-"$rootfsimage" +else + nfsroot="$eth0.serverip:/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttymxc0,115200" + +nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nand=3 + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c new file mode 100644 index 0000000000..0c376f2fae --- /dev/null +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -0,0 +1,117 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <init.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <mach/esdctl.h> +#include <asm/cache-l2x0.h> +#include <asm/io.h> +#include <mach/imx-nand.h> +#include <asm/barebox-arm.h> +#include <asm/system.h> +#include <asm-generic/memory_layout.h> + +static void __bare_init __naked insdram(void) +{ + uint32_t r; + + PCCR1 |= PCCR1_NFC_BAUDEN; + + /* setup a stack to be able to call imx_nand_load_image() */ + r = STACK_BASE + STACK_SIZE - 12; + __asm__ __volatile__("mov sp, %0" : : "r"(r)); + + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); + + board_init_lowlevel_return(); +} + +#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) + +void __bare_init __naked board_init_lowlevel(void) +{ + uint32_t r; + int i; + unsigned int *trg, *src; + + /* ahb lite ip interface */ + AIPI1_PSR0 = 0x20040304; + AIPI1_PSR1 = 0xDFFBFCFB; + AIPI2_PSR0 = 0x00000000; + AIPI2_PSR1 = 0xFFFFFFFF; + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0xa0000000 && r < 0xb0000000) + board_init_lowlevel_return(); + + /* + * DDR on CSD0 + */ + writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */ + + DSCR(3) = 0x55555555; /* Set the driving strength */ + DSCR(5) = 0x55555555; + DSCR(6) = 0x55555555; + DSCR(7) = 0x00005005; + DSCR(8) = 0x15555555; + + writel(0x00000004, ESDMISC); /* Initial reset */ + writel(0x006ac73a, ESDCFG0); + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */ + writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); + + for (i = 0; i < 8; i++) + writel(0, 0xa0000f00); + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); + + writeb(0xda, 0xa0000033); + writeb(0xff, 0xa1000000); + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0); + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)IMX_NFC_BASE; + trg = (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ + for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ + r = (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} + diff --git a/arch/arm/boards/guf-neso/pll_init.S b/arch/arm/boards/guf-neso/pll_init.S new file mode 100644 index 0000000000..87e5312fb4 --- /dev/null +++ b/arch/arm/boards/guf-neso/pll_init.S @@ -0,0 +1,48 @@ +#include <config.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <linux/linkage.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define CSCR_VAL CSCR_USB_DIV(3) | \ + CSCR_SD_CNT(3) | \ + CSCR_MSHC_SEL | \ + CSCR_H264_SEL | \ + CSCR_SSI1_SEL | \ + CSCR_SSI2_SEL | \ + CSCR_MCU_SEL | \ + CSCR_ARM_SRC_MPLL | \ + CSCR_SP_SEL | \ + CSCR_ARM_DIV(0) | \ + CSCR_FPM_EN | \ + CSCR_SPEN | \ + CSCR_MPEN | \ + CSCR_AHB_DIV(1) + +ENTRY(neso_pll_init) + + writel(IMX_PLL_PD(0) | + IMX_PLL_MFD(51) | + IMX_PLL_MFI(7) | + IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */ + + writel(IMX_PLL_PD(1) | + IMX_PLL_MFD(12) | + IMX_PLL_MFI(9) | + IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ + + writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + + ldr r2, =16000 +1: + subs r2, r2, #1 + nop + bcs 1b + + mov pc, lr +ENDPROC(neso_pll_init) + diff --git a/arch/arm/boards/imx21ads/Makefile b/arch/arm/boards/imx21ads/Makefile new file mode 100644 index 0000000000..7993fdef8a --- /dev/null +++ b/arch/arm/boards/imx21ads/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel_init.o +obj-y += imx21ads.o diff --git a/arch/arm/boards/imx21ads/config.h b/arch/arm/boards/imx21ads/config.h new file mode 100644 index 0000000000..edfb29ffb0 --- /dev/null +++ b/arch/arm/boards/imx21ads/config.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Global defintions for the ARM i.MX21 based imx21ads + **/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/imx21ads/env/bin/init b/arch/arm/boards/imx21ads/env/bin/init new file mode 100644 index 0000000000..224a6b40be --- /dev/null +++ b/arch/arm/boards/imx21ads/env/bin/init @@ -0,0 +1 @@ +# Dummy Init environment script diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c new file mode 100644 index 0000000000..5e88af4fd8 --- /dev/null +++ b/arch/arm/boards/imx21ads/imx21ads.c @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2009 Ivo Clarysse + * + * Based on imx27ads.c, + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <asm/armlinux.h> +#include <asm/io.h> +#include <mach/gpio.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/mach-types.h> +#include <mach/imx-nand.h> +#include <mach/imxfb.h> +#include <mach/iomux-mx21.h> + +#define MX21ADS_IO_REG 0xCC800000 +#define MX21ADS_IO_LCDON (1 << 9) + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0xC8000000, + .size = 32 * 1024 * 1024, +}; + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0xc0000000, + .size = 64 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = 0xDF003000, + .platform_data = &nand_info, +}; + +static struct device_d cs8900_dev = { + .name = "cs8900", + .map_base = IMX_CS1_BASE, + // IRQ is connected to UART3_RTS +}; + +/* Sharp LQ035Q7DB02 QVGA display */ +static struct imx_fb_videomode imx_fb_modedata = { + .mode = { + .name = "Sharp-LQ035Q7", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 188679, + .left_margin = 6, + .right_margin = 16, + .upper_margin = 8, + .lower_margin = 10, + .hsync_len = 2, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, + .pcr = 0xfb108bc7, + .bpp = 16, +}; + +static struct imx_fb_platform_data imx_fb_data = { + .mode = &imx_fb_modedata, + .cmap_greyscale = 0, + .cmap_inverse = 0, + .cmap_static = 0, + .pwmr = 0x00a903ff, + .lscr1 = 0x00120300, + .dmacr = 0x00020008, +}; + +static struct device_d imxfb_dev = { + .name = "imxfb", + .map_base = 0x10021000, + .size = 0x1000, + .platform_data = &imx_fb_data, +}; + +static int imx21ads_timing_init(void) +{ + u32 temp; + + /* Configure External Interface Module */ + /* CS0: burst flash */ + CS0U = 0x00003E00; + CS0L = 0x00000E01; + + /* CS1: Ethernet controller, external UART, memory-mapped I/O (16-bit) */ + CS1U = 0x00002000; + CS1L = 0x11118501; + + /* CS2: disable (not available, since CSD0 in use) */ + CS2U = 0x0; + CS2L = 0x0; + + /* CS3: disable */ + CS3U = 0x0; + CS3L = 0x0; + /* CS4: disable */ + CS4U = 0x0; + CS4L = 0x0; + /* CS5: disable */ + CS5U = 0x0; + CS5L = 0x0; + + temp = PCDR0; + temp &= ~0xF000; + temp |= 0xA000; /* Set NFC divider; 0xA yields 24.18MHz */ + PCDR0 = temp; + + return 0; +} + +core_initcall(imx21ads_timing_init); + +static int mx21ads_devices_init(void) +{ + int i; + unsigned int mode[] = { + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA24_PF_REV, + PA25_PF_CLS, + PA26_PF_PS, + PA27_PF_SPL_SPR, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA30_PF_CONTRAST, + PA31_PF_OE_ACD, + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + }; + + /* initizalize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + register_device(&cfi_dev); + register_device(&sdram_dev); + register_device(&nand_dev); + register_device(&cs8900_dev); + register_device(&imxfb_dev); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0xc0000100); + armlinux_set_architecture(MACH_TYPE_MX21ADS); + + return 0; +} + +device_initcall(mx21ads_devices_init); + +static int mx21ads_enable_display(void) +{ + u16 tmp; + + tmp = readw(MX21ADS_IO_REG); + tmp |= MX21ADS_IO_LCDON; + writew(tmp, MX21ADS_IO_REG); + return 0; +} + +late_initcall(mx21ads_enable_display); + +static struct device_d mx21ads_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static int mx21ads_console_init(void) +{ + register_device(&mx21ads_serial_device); + return 0; +} + +console_initcall(mx21ads_console_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + PCCR0 |= PCCR0_NFC_EN; + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif + diff --git a/arch/arm/boards/imx21ads/imx21ads.dox b/arch/arm/boards/imx21ads/imx21ads.dox new file mode 100644 index 0000000000..9f11ffaa6e --- /dev/null +++ b/arch/arm/boards/imx21ads/imx21ads.dox @@ -0,0 +1,5 @@ +/** @page imx21ads Freescale i.MX21ads + +This is the Freescale evaluation board for the i.MX21 Processor + +*/ diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S new file mode 100644 index 0000000000..607da27476 --- /dev/null +++ b/arch/arm/boards/imx21ads/lowlevel_init.S @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2010 Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <mach/imx-regs.h> + + .section ".text_bare_init","ax" + +.globl board_init_lowlevel +board_init_lowlevel: + +/* Save lr, because it is overwritten by the calls to mem_delay. */ + mov r10, lr + +/* + * Initialize the AHB-Lite IP Interface (AIPI) module (to enable access to + * on chip peripherals) as described in section 7.2 of rev3 of the i.MX21 + * reference manual. + */ + ldr r0, =AIPI1_PSR0 + ldr r1, =0x00040304 + str r1, [r0] + ldr r0, =AIPI1_PSR1 + ldr r1, =0xfffbfcfb + str r1, [r0] + + ldr r0, =AIPI2_PSR0 + ldr r1, =0x3ffc0000 + str r1, [r0] + ldr r0, =AIPI2_PSR1 + ldr r1, =0xffffffff + str r1, [r0] + +/* + * Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable + * the clock to peripherals. + */ + ldr r0, =CSCR + ldr r1, =0x17180607 + str r1, [r0] + + ldr r0, =PCCR1 + ldr r1, =0x0e000000 + str r1, [r0] + + +/* + * SDRAM and SDRAM controller configuration + */ + + /* + * CSD1 not required, because the MX21ADS board only contains 64Mbyte. + * CS3 can therefore be made available. + */ + ldr r0, =FMCR + ldr r1, =0xffffffc9 + str r1, [r0] + + /* Skip SDRAM initialization if we run from RAM */ + cmp pc, #0xc0000000 + bls 1f + cmp pc, #0xc8000000 + bhi 1f + + mov pc, r10 +1: + + /* Precharge */ + ldr r0, =SDCTL0 + ldr r1, =0x92120300 + str r1, [r0] + ldr r2, =0xc0200000 + ldr r1, [r2] + + bl mem_delay + + /* Auto refresh */ + ldr r1, =0xa2120300 + str r1, [r0] + ldr r2, =0xc0000000 + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + + /* Set mode register */ + ldr r1, =0xB2120300 + str r1, [r0] + ldr r1, =0xC0119800 + ldr r2, [r1] + + bl mem_delay + + /* Back to Normal Mode */ + ldr r1, =0x8212F339 + str r1, [r0] + + /* Set NFC_CLK to 24MHz */ + ldr r0, =PCDR0 + ldr r1, =0x6419a007 + str r1, [r0] + +#ifdef CONFIG_NAND_IMX_BOOT + ldr sp, =TEXT_BASE - 4 /* Setup a temporary stack in SDRAM */ + + ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ + ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */ + + /* skip NAND boot if not running from NFC space */ + cmp pc, r0 + bls ret + cmp pc, r2 + bhi ret + + /* Move ourselves out of NFC SRAM */ + ldr r1, =TEXT_BASE + +copy_loop: + ldmia r0!, {r3-r9} /* copy from source address [r0] */ + stmia r1!, {r3-r9} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + ldr pc, =1f /* Jump to SDRAM */ +1: + bl nand_boot /* Load barebox from NAND Flash */ + + ldr r1, =IMX_NFC_BASE - TEXT_BASE + sub r10, r10, r1 /* adjust return address from NFC */ + /* SRAM to SDRAM */ +#endif /* CONFIG_NAND_IMX_BOOT */ + +ret: + mov pc, r10 + +/* + * spin for a while. we need to wait at least 200 usecs. + */ +mem_delay: + mov r4, #0x4000 +spin: subs r4, r4, #1 + bne spin + mov pc, lr + diff --git a/arch/arm/boards/imx27ads/Makefile b/arch/arm/boards/imx27ads/Makefile new file mode 100644 index 0000000000..bdc905f0ef --- /dev/null +++ b/arch/arm/boards/imx27ads/Makefile @@ -0,0 +1,3 @@ + +obj-y += lowlevel_init.o +obj-y += imx27ads.o diff --git a/arch/arm/boards/imx27ads/config.h b/arch/arm/boards/imx27ads/config.h new file mode 100644 index 0000000000..b54a3c53d4 --- /dev/null +++ b/arch/arm/boards/imx27ads/config.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Global defintions for the Freescale imx27ads ARM board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/imx27ads/env/bin/_update b/arch/arm/boards/imx27ads/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/imx27ads/env/bin/boot b/arch/arm/boards/imx27ads/env/bin/boot new file mode 100644 index 0000000000..3859dc113b --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xflash ]; then + root=flash + kernel=flash +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xflash ]; then + bootargs="$bootargs root=$rootpart rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nor0.kernel +fi + diff --git a/arch/arm/boards/imx27ads/env/bin/init b/arch/arm/boards/imx27ads/env/bin/init new file mode 100644 index 0000000000..48e2139f7d --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/init @@ -0,0 +1,20 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +addpart /dev/nor0 $mtdparts + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type udate_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot
\ No newline at end of file diff --git a/arch/arm/boards/imx27ads/env/bin/update_kernel b/arch/arm/boards/imx27ads/env/bin/update_kernel new file mode 100644 index 0000000000..1ad95fc5d6 --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/update_kernel @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$uimage +part=/dev/nor0.kernel + +. /env/bin/_update $1 diff --git a/arch/arm/boards/imx27ads/env/bin/update_root b/arch/arm/boards/imx27ads/env/bin/update_root new file mode 100644 index 0000000000..b757a5b922 --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/update_root @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +part=/dev/nor0.root + +. /env/bin/_update $1 diff --git a/arch/arm/boards/imx27ads/env/config b/arch/arm/boards/imx27ads/env/config new file mode 100644 index 0000000000..f18a86b7c1 --- /dev/null +++ b/arch/arm/boards/imx27ads/env/config @@ -0,0 +1,25 @@ +#!/bin/sh + +# can be either 'net' or 'flash' +kernel=net +root=net + +# use 'dhcp' todo dhcp in barebox and in kernel +ip=dhcp + +eth0.ipaddr=192.168.23.164 +eth0.netmask=255.255.255.0 +eth0.gateway=192.168.23.2 +eth0.serverip=192.168.23.2 + +uimage=uImage-mx27ads +jffs2=root-mx27ads.jffs2 + +autoboot_timeout=3 + +nfsroot="/tmp/imx27ads" +bootargs="console=ttymxc0,115200" + +mtdparts="128k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" +rootpart="/dev/mtdblock3" + diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c new file mode 100644 index 0000000000..6f31520ffa --- /dev/null +++ b/arch/arm/boards/imx27ads/imx27ads.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <asm/armlinux.h> +#include <asm/io.h> +#include <fec.h> +#include <mach/gpio.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/mach-types.h> +#include <mach/iomux-mx27.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0xC0000000, + .size = 32 * 1024 * 1024, +}; + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0xa0000000, + .size = 128 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 1, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = 0x1002b000, + .platform_data = &fec_info, +}; + +static int imx27ads_timing_init(void) +{ + /* configure cpld on cs4 */ + CS4U = 0x0000DCF6; + CS4L = 0x444A4541; + CS4A = 0x44443302; + + /* configure synchronous mode for + * 16 bit nor flash on cs0 */ + CS0U = 0x0000CC03; + CS0L = 0xa0330D01; + CS0A = 0x00220800; + + writew(0x00f0, 0xc0000000); + writew(0x00aa, 0xc0000aaa); + writew(0x0055, 0xc0000554); + writew(0x00d0, 0xc0000aaa); + writew(0x66ca, 0xc0000aaa); + writew(0x00f0, 0xc0000000); + + CS0U = 0x23524E80; + CS0L = 0x10000D03; + CS0A = 0x00720900; + + /* Select FEC data through data path */ + writew(0x0020, IMX_CS4_BASE + 0x10); + + /* Enable CPLD FEC data path */ + writew(0x0010, IMX_CS4_BASE + 0x14); + + return 0; +} + +core_initcall(imx27ads_timing_init); + +static int mx27ads_devices_init(void) +{ + int i; + unsigned int mode[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + }; + + /* initizalize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + register_device(&cfi_dev); + register_device(&sdram_dev); + register_device(&fec_dev); + + devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0xa0000100); + armlinux_set_architecture(MACH_TYPE_MX27ADS); + + return 0; +} + +device_initcall(mx27ads_devices_init); + +static struct device_d mx27ads_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static int mx27ads_console_init(void) +{ + register_device(&mx27ads_serial_device); + return 0; +} + +console_initcall(mx27ads_console_init); + diff --git a/arch/arm/boards/imx27ads/imx27ads.dox b/arch/arm/boards/imx27ads/imx27ads.dox new file mode 100644 index 0000000000..e14d8e3fab --- /dev/null +++ b/arch/arm/boards/imx27ads/imx27ads.dox @@ -0,0 +1,5 @@ +/** @page imx27ads Freescale i.MX27ads + +This is the Freescale evaluation board for the i.MX27 Processor + +*/ diff --git a/arch/arm/boards/imx27ads/lowlevel_init.S b/arch/arm/boards/imx27ads/lowlevel_init.S new file mode 100644 index 0000000000..df12aead00 --- /dev/null +++ b/arch/arm/boards/imx27ads/lowlevel_init.S @@ -0,0 +1,172 @@ +/* + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia + * Applications Processor Reference Manual, Rev. 0.2". + * + */ + +#include <config.h> +#include <mach/imx-regs.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0)) + +.macro sdram_init_sha + /* + * DDR on CSD0 + */ + writel(0x00000008, 0xD8001010) + writel(0x55555555, 0x10027828) + writel(0x55555555, 0x10027830) + writel(0x55555555, 0x10027834) + writel(0x00005005, 0x10027838) + writel(0x15555555, 0x1002783C) + writel(0x00000004, 0xD8001010) + writel(0x006ac73a, 0xD8001004) + writel(0x92100000, 0xD8001000) + writel(0x00000000, 0xA0000F00) + writel(0xA2100000, 0xD8001000) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0xA2200000, 0xD8001000) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0xb2100000, 0xD8001000) + ldr r0, =0xA0000033 + mov r1, #0xda + strb r1, [r0] + ldr r0, =0xA1000000 + mov r1, #0xff + strb r1, [r0] + writel(0x82226080, 0xD8001000) +.endm + +.macro sdram_init_mx27_manual + /* + * sdram init sequence, as defined in 18.5.4 of the i.MX27 reference manual + */ +1: + ldr r2, =ESD_ESDCTL0 /* base address of registers */ + ldr r3, =PRE_ALL_CMD /* SMODE=001 */ + str r3,(r2,#0x0) /* put CSD0 in precharge command mode */ + ldr r4, =SDRAM_CSD0 /* CSD0 precharge address (A10=1) */ + str r1,(r4,#0x0) /* precharge CSD0 all banks */ + ldr r3, =AUTO_REF_CMD /* SMODE=010 */ + str r3,(r2,#0x0) /* put array 0 in auto-refresh mode */ + ldr r4, =SDRAM_CSD0_BASE /* CSD0 base address */ + ldr r6,=0x7 /* load loop counter */ +1: ldr r5,(r4,#0x0) /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 /* decrease counter value */ + bne 1b + ldr r3, =SET_MODE_REG_CMD /* SMODE=011 */ + str r3,(r2,#0x0) /* setup CSD0 for mode register write */ + ldr r3, =MODE_REG_VAL0 /* array 0 mode register value */ + ldrb r5,(r3,#0x0) /* New mode register value on address bus */ + ldr r3, =NORMAL_MODE /* SMODE=000 */ + str r3,(r2,#0x0) /* setup CSD0 for normal operation */ + +ESD_ESDCTL0 .long 0xD8001000 // system/external device dependent data +SDRAM_CSD0 .long 0x00000000 // system/external device dependent data +SDRAM_CSD0_BASE .long 0x00000000 // system/external device dependent data +PRE_ALL_CMD .long 0x00000000 // system/external device dependent data (SMODE=001) +AUTO_REF_CMD .long 0x00000000 // system/external device dependent data (SMODE=010) +SET_MODE_REG_CMD .long 0x00000000 // system/external device dependent data (SMODE=011) +MODE_REG_VAL0 .long 0x00000000 // system/external device dependent data +NORMAL_MODE .long 0x00000000 // system/external device dependent data (SMODE=000) +.endm + +.macro sdram_init_barebox + /* configure 16 bit nor flash on cs0 */ + writel(0x0000CC03, 0xd8002000) + writel(0xa0330D01, 0xd8002004) + writel(0x00220800, 0xd8002008) + + /* ddr on csd0 - initial reset */ + writel(0x00000008, 0xD8001010) + + /* configure ddr on csd0 - wait 5000 cycles */ + writel(0x00000004, 0xD8001010) + writel(0x006ac73a, 0xD8001004) + writel(0x92100000, 0xD8001000) + writel(0x12344321, 0xA0000f00) + writel(0xa2100000, 0xD8001000) + writel(0x12344321, 0xA0000000) + writel(0x12344321, 0xA0000000) + writel(0xb2100000, 0xD8001000) + ldr r0, =0xA0000033 + mov r1, #0xda + strb r1, [r0] + ldr r0, =0xA1000000 + mov r1, #0xff + strb r1, [r0] + writel(0x82226080, 0xD8001000) + writel(0xDEADBEEF, 0xA0000000) + writel(0x0000000c, 0xD8001010) +.endm + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr + + /* ahb lite ip interface */ + writel(0x20040304, AIPI1_PSR0) + writel(0xDFFBFCFB, AIPI1_PSR1) + writel(0x00000000, AIPI2_PSR0) + writel(0xFFFFFFFF, AIPI2_PSR1) + + /* disable mpll/spll */ + ldr r0, =CSCR + ldr r1, [r0] + bic r1, r1, #0x03 + str r1, [r0] + + /* + * pll clock initialization - see section 3.4.3 of the i.MX27 manual + * + * FIXME: Using the 399*2 MHz values from table 3-8 doens't work + * with 1.2 V core voltage! Find out if this is + * documented somewhere. + */ + writel(0x00191403, MPCTL0) /* MPLL = 199.5*2 MHz */ + writel(0x040C2403, SPCTL0) /* SPLL = FIXME (needs review) */ + + /* + * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz + * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz + * System clock (HCLK) = 133 MHz + */ + writel(0x33F30307 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + + /* add some delay here */ + mov r1, #0x1000 +1: subs r1, r1, #0x1 + bne 1b + + /* clock gating enable */ + writel(0x00050f08, GPCR) + + /* peripheral clock divider */ + writel(0x23C8F403, PCDR0) /* FIXME */ + writel(0x09030913, PCDR1) /* PERDIV1=08 @133 MHz */ + /* PERDIV1=04 @266 MHz * + * / + /* skip sdram initialization if we run from ram */ + cmp pc, #0xa0000000 + bls 1f + cmp pc, #0xc0000000 + bhi 1f + + mov pc,r10 +1: + sdram_init_sha + + mov pc,r10 + diff --git a/arch/arm/boards/mmccpu/Makefile b/arch/arm/boards/mmccpu/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/mmccpu/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/mmccpu/config.h b/arch/arm/boards/mmccpu/config.h new file mode 100644 index 0000000000..1133b8f040 --- /dev/null +++ b/arch/arm/boards/mmccpu/config.h @@ -0,0 +1,141 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MASTER_CLOCK 99532800 /* peripheral = main / 2 */ + +/* values */ +#define MASTER_PLL_MUL 54 +#define MASTER_PLL_DIV 4 + +/* clocks */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + AT91_PMC_PLLCOUNT | /* PLL Counter */ \ + (2 << 28) | /* PLL Clock Frequency Range */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | \ + AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 0 +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x13c +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* tWR - Write Recovery Delay */ \ + (8 << 12) | /* tRC - Row Cycle Delay */ \ + (2 << 16) | /* tRP - Row Precharge Delay */ \ + (2 << 20) | /* tRCD - Row to Column Delay */ \ + (5 << 24) | /* tRAS - Active to Precharge Delay */ \ + (12 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 780 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup CS0 (NOR Flash) - 16-bit */ +#if 1 +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \ + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \ + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) +#elif 0 /* slow setup */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \ + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \ + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(1)) +#else /* RONETIX' original values */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) +#endif + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/mmccpu/env/bin/_update b/arch/arm/boards/mmccpu/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/mmccpu/env/bin/boot b/arch/arm/boards/mmccpu/env/bin/boot new file mode 100644 index 0000000000..533dea7618 --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/boot @@ -0,0 +1,47 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$1 = xnor ]; then + root=nor + kernel=nor +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +elif [ x$root = xnor ]; then + bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +elif [ $kernel = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/mmccpu/env/bin/hush_hack b/arch/arm/boards/mmccpu/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/mmccpu/env/bin/init b/arch/arm/boards/mmccpu/env/bin/init new file mode 100644 index 0000000000..ac84bd596f --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/init @@ -0,0 +1,37 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nor [<imagename>] to update kernel into flash" + echo "type update_root nor [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/mmccpu/env/bin/update_kernel b/arch/arm/boards/mmccpu/env/bin/update_kernel new file mode 100644 index 0000000000..05c822d860 --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/mmccpu/env/bin/update_root b/arch/arm/boards/mmccpu/env/bin/update_root new file mode 100644 index 0000000000..a75137237b --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/mmccpu/env/config b/arch/arm/boards/mmccpu/env/config new file mode 100644 index 0000000000..5367cd9f56 --- /dev/null +++ b/arch/arm/boards/mmccpu/env/config @@ -0,0 +1,30 @@ +#!/bin/sh + +# can be either 'net', 'nor' or 'nand'' +kernel=nor +root=nor + +uimage=uImage-mmccpu +jffs2=root-mmccpu.jffs2 + +autoboot_timeout=3 + +nfsroot="/home/kschwinne/src/pengutronix/OSELAS.BSP-Bucyrus-Grabowski-trunk/platform-Bucyrus-mmccpu/root" + +bootargs="console=ttyS0,115200 mmccpu=p299" + +#nor_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" +nor_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),10240k(root),10240k(rootbu),-(data)" +rootpart_nor="/dev/mtdblock3" + +#nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +#rootpart_nand="/dev/mtdblock7" + +# use 'dhcp' to do dhcp in barebox and in kernel +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d diff --git a/arch/arm/boards/mmccpu/init.c b/arch/arm/boards/mmccpu/init.c new file mode 100644 index 0000000000..e010a83104 --- /dev/null +++ b/arch/arm/boards/mmccpu/init.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <fec.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <linux/mtd/nand.h> +#include <mach/at91_pmc.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = AT91_CHIPSELECT_0, + .size = 0, /* zero means autodetect size */ +}; + +static struct at91_ether_platform_data macb_pdata = { + .flags = AT91SAM_ETHER_MII | AT91SAM_ETHER_FORCE_LINK, + .phy_addr = 4, +}; + +static int mmccpu_devices_init(void) +{ + /* + * PB27 enables the 50MHz oscillator for Ethernet PHY + * 1 - enable + * 0 - disable + */ + at91_set_gpio_output(AT91_PIN_PB27, 1); + at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + + at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_eth(&macb_pdata); + register_device(&cfi_dev); + + devfs_add_partition("nor0", 0x00000, 256 * 1024, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 128 * 1024, PARTITION_FIXED, "env0"); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + armlinux_set_architecture(MACH_TYPE_MMCCPU); + + return 0; +} + +device_initcall(mmccpu_devices_init); + +static int mmccpu_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} + +console_initcall(mmccpu_console_init); diff --git a/arch/arm/boards/netx/Makefile b/arch/arm/boards/netx/Makefile new file mode 100644 index 0000000000..8b33fec316 --- /dev/null +++ b/arch/arm/boards/netx/Makefile @@ -0,0 +1,2 @@ +obj-y += netx.o platform.o + diff --git a/arch/arm/boards/netx/config.h b/arch/arm/boards/netx/config.h new file mode 100644 index 0000000000..ca15136817 --- /dev/null +++ b/arch/arm/boards/netx/config.h @@ -0,0 +1,4 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/netx/netx.c b/arch/arm/boards/netx/netx.c new file mode 100644 index 0000000000..d6bfcca54d --- /dev/null +++ b/arch/arm/boards/netx/netx.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/netx-regs.h> +#include <partition.h> +#include <asm/armlinux.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/mach-types.h> +#include <mach/netx-eth.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0xC0000000, + .size = 32 * 1024 * 1024, +}; + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0x80000000, + .size = 64 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +struct netx_eth_platform_data eth0_data = { + .xcno = 0, +}; + +static struct device_d netx_eth_dev0 = { + .name = "netx-eth", + .platform_data = ð0_data, +}; + +struct netx_eth_platform_data eth1_data = { + .xcno = 1, +}; + +static struct device_d netx_eth_dev1 = { + .name = "netx-eth", + .platform_data = ð1_data, +}; + +static int netx_devices_init(void) { + register_device(&cfi_dev); + register_device(&sdram_dev); + register_device(&netx_eth_dev0); + register_device(&netx_eth_dev1); + + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); + + /* Do not overwrite primary env for now */ + devfs_add_partition("nor0", 0xc0000, 0x80000, PARTITION_FIXED, "env0"); + + protect_file("/dev/env0", 1); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_NXDB500); + + return 0; +} + +device_initcall(netx_devices_init); + +static struct device_d netx_serial_device = { + .name = "netx_serial", + .map_base = NETX_PA_UART0, + .size = 0x40, +}; + +static int netx_console_init(void) +{ + /* configure gpio for serial */ + *(volatile unsigned long *)(0x00100800) = 2; + *(volatile unsigned long *)(0x00100804) = 2; + *(volatile unsigned long *)(0x00100808) = 2; + *(volatile unsigned long *)(0x0010080c) = 2; + + register_device(&netx_serial_device); + return 0; +} + +console_initcall(netx_console_init); + diff --git a/arch/arm/boards/netx/netx.dox b/arch/arm/boards/netx/netx.dox new file mode 100644 index 0000000000..e22c5e8554 --- /dev/null +++ b/arch/arm/boards/netx/netx.dox @@ -0,0 +1,9 @@ +/** @page netx Hilscher's NetX card family + +This CPU card is based on a Hilscher's NetX ARM CPU. The card is shipped +in various incarnations: + +Specific to this CPU is, it does not require any setup code to bring the +SDRAM up and working. This is done in a pre bootloader. + +*/
\ No newline at end of file diff --git a/arch/arm/boards/netx/platform.S b/arch/arm/boards/netx/platform.S new file mode 100644 index 0000000000..4961682322 --- /dev/null +++ b/arch/arm/boards/netx/platform.S @@ -0,0 +1,26 @@ +/* + * Board specific setup info + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl board_init_lowlevel +board_init_lowlevel: + mov pc, lr diff --git a/arch/arm/boards/omap/Kconfig b/arch/arm/boards/omap/Kconfig new file mode 100644 index 0000000000..d612064710 --- /dev/null +++ b/arch/arm/boards/omap/Kconfig @@ -0,0 +1,93 @@ +# OMAP based Board Specific Configuration file +# +# (C) Copyright 2008 +# OMAP Architecture specific features +# Texas Instruments, <www.ti.com> +# Nishanth Menon <x0nishan@ti.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +config ARCH_TEXT_BASE + hex + default 0x80e80000 if MACH_OMAP343xSDP + default 0x80e80000 if MACH_BEAGLE + +menu "OMAP Platform Features" + +config BOARDINFO + default "Texas Instrument's SDP343x" if MACH_OMAP343xSDP + default "Texas Instrument's Beagle" if MACH_BEAGLE + default "Texas Instrument's OMAP3EVM" if MACH_OMAP3EVM + +choice + prompt "Select OMAP platform" + +config MACH_OMAP343xSDP + bool "Texas Instrument's SDP343x" + select MACH_HAS_LOWLEVEL_INIT + select OMAP_CLOCK_ALL + select HAS_OMAP_NAND + help + Say Y here if you are using SDP343x platform + +config MACH_BEAGLE + bool "Texas Instrument's Beagle Board" + select MACH_HAS_LOWLEVEL_INIT + select OMAP_CLOCK_ALL + select HAS_OMAP_NAND + help + Say Y here if you are using Beagle Board + +config MACH_OMAP3EVM + bool "Texas Instrument's OMAP3 EVM" + select MACH_HAS_LOWLEVEL_INIT + select OMAP_CLOCK_ALL + select HAS_OMAP_NAND + help + Say Y here if you are using OMAP3EVM + +endchoice + +if MACH_OMAP3EVM + choice + prompt "Select UART" + + config OMAP3EVM_UART1 + bool "Use UART1" + depends on MACH_OMAP3EVM + help + Say Y here if you would like to use UART1 as console. + + config OMAP3EVM_UART3 + bool "Use UART3" + depends on MACH_OMAP3EVM + help + Say Y here if you would like to use UART3 as console. + endchoice +endif + +config MACH_OMAP_ADVANCED_MUX + bool "Enable advanced pin muxing" + depends on MACH_OMAP343xSDP + default n + help + Say Y here if you would like to have complete pin muxing to be + done at boot time + +config HAS_OMAP_NAND + bool + +endmenu diff --git a/arch/arm/boards/omap/Makefile b/arch/arm/boards/omap/Makefile new file mode 100644 index 0000000000..1e74e241b4 --- /dev/null +++ b/arch/arm/boards/omap/Makefile @@ -0,0 +1,28 @@ +# OMAP Board Specific Makefile +# +# (C) Copyright 2008 +# OMAP Architecture specific features +# Texas Instruments, <www.ti.com> +# Nishanth Menon <x0nishan@ti.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += platform.o +obj-$(CONFIG_MACH_OMAP343xSDP) += board-sdp343x.o +obj-$(CONFIG_MACH_BEAGLE) += board-beagle.o +obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o +obj-y += devices-gpmc-nand.o + diff --git a/arch/arm/boards/omap/board-beagle.c b/arch/arm/boards/omap/board-beagle.c new file mode 100644 index 0000000000..a4cbf313b8 --- /dev/null +++ b/arch/arm/boards/omap/board-beagle.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Raghavendra KH <r-khandenahally@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Beagle Specific Board Initialization routines + */ + +/** + * @page ti_beagle Texas Instruments Beagle Board + * + * FileName: arch/arm/boards/omap/board-beagle.c + * + * Beagle Board from Texas Instruments as described here: + * http://www.beagleboard.org + * + * This board is based on OMAP3530. + * More on OMAP3530 (including documentation can be found here): + * http://focus.ti.com/docs/prod/folders/print/omap3530.html + * + * This file provides initialization in two stages: + * @li boot time initialization - do basics required to get SDRAM working. + * This is run from SRAM - so no case constructs and global vars can be used. + * @li run time initialization - this is for the rest of the initializations + * such as flash, uart etc. + * + * Boot time initialization includes: + * @li SDRAM initialization. + * @li Pin Muxing relevant for Beagle. + * + * Run time initialization includes + * @li serial @ref serial_ns16550.c driver device definition + * + * Originally from arch/arm/boards/omap/board-sdp343x.c + */ + +#include <common.h> +#include <console.h> +#include <init.h> +#include <driver.h> +#include <asm/io.h> +#include <ns16550.h> +#include <asm/armlinux.h> +#include <mach/silicon.h> +#include <mach/sdrc.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> +#include <mach/control.h> +#include <mach/omap3-mux.h> +#include <mach/gpmc.h> +#include "board.h" + +/******************** Board Boot Time *******************/ + +/** + * @brief Do the SDRC initialization for 128Meg Micron DDR for CS0 + * + * @return void + */ +static void sdrc_init(void) +{ + /* SDRAM software reset */ + /* No idle ack and RESET enable */ + writel(0x1A, SDRC_REG(SYSCONFIG)); + sdelay(100); + /* No idle ack and RESET disable */ + writel(0x18, SDRC_REG(SYSCONFIG)); + + /* SDRC Sharing register */ + /* 32-bit SDRAM on data lane [31:0] - CS0 */ + /* pin tri-stated = 1 */ + writel(0x00000100, SDRC_REG(SHARING)); + + /* ----- SDRC Registers Configuration --------- */ + /* SDRC_MCFG0 register */ + writel(0x02584099, SDRC_REG(MCFG_0)); + + /* SDRC_RFR_CTRL0 register */ + writel(0x54601, SDRC_REG(RFR_CTRL_0)); + + /* SDRC_ACTIM_CTRLA0 register */ + writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0)); + + /* SDRC_ACTIM_CTRLB0 register */ + writel(0x12214, SDRC_REG(ACTIM_CTRLB_0)); + + /* Disble Power Down of CKE due to 1 CKE on combo part */ + writel(0x00000081, SDRC_REG(POWER)); + + /* SDRC_MANUAL command register */ + /* NOP command */ + writel(0x00000000, SDRC_REG(MANUAL_0)); + /* Precharge command */ + writel(0x00000001, SDRC_REG(MANUAL_0)); + /* Auto-refresh command */ + writel(0x00000002, SDRC_REG(MANUAL_0)); + /* Auto-refresh command */ + writel(0x00000002, SDRC_REG(MANUAL_0)); + + /* SDRC MR0 register Burst length=4 */ + writel(0x00000032, SDRC_REG(MR_0)); + + /* SDRC DLLA control register */ + writel(0x0000000A, SDRC_REG(DLLA_CTRL)); + + return; +} + +/** + * @brief Do the pin muxing required for Board operation. + * We enable ONLY the pins we require to set. OMAP provides pins which do not + * have alternate modes. Such pins done need to be set. + * + * See @ref MUX_VAL for description of the muxing mode. + * + * @return void + */ +static void mux_config(void) +{ + /* SDRC_D0 - SDRC_D31 default mux mode is mode0 */ + + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); + + /* D0-D7 default mux mode is mode0 */ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); + /* GPMC_NADV_ALE default mux mode is mode0 */ + /* GPMC_NOE default mux mode is mode0 */ + /* GPMC_NWE default mux mode is mode0 */ + /* GPMC_NBE0_CLE default mux mode is mode0 */ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); + /* GPMC_WAIT0 default mux mode is mode0 */ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); + + /* SERIAL INTERFACE */ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); + /* I2C1_SCL default mux mode is mode0 */ + /* I2C1_SDA default mux mode is mode0 */ +} + +/** + * @brief The basic entry point for board initialization. + * + * This is called as part of machine init (after arch init). + * This is again called with stack in SRAM, so not too many + * constructs possible here. + * + * @return void + */ +void board_init(void) +{ + int in_sdram = running_in_sdram(); + + mux_config(); + /* Dont reconfigure SDRAM while running in SDRAM! */ + if (!in_sdram) + sdrc_init(); +} + +/******************** Board Run Time *******************/ + +#ifdef CONFIG_DRIVER_SERIAL_NS16550 + +static struct NS16550_plat serial_plat = { + .clock = 48000000, /* 48MHz (APLL96/2) */ + .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR, + .reg_read = omap_uart_read, + .reg_write = omap_uart_write, +}; + +static struct device_d beagle_serial_device = { + .name = "serial_ns16550", + .map_base = OMAP_UART3_BASE, + .size = 1024, + .platform_data = (void *)&serial_plat, +}; + +/** + * @brief UART serial port initialization - remember to enable COM clocks in + * arch + * + * @return result of device registration + */ +static int beagle_console_init(void) +{ + /* Register the serial port */ + return register_device(&beagle_serial_device); +} +console_initcall(beagle_console_init); +#endif /* CONFIG_DRIVER_SERIAL_NS16550 */ + +static struct memory_platform_data sram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0x80000000, + .size = 128 * 1024 * 1024, + .platform_data = &sram_pdata, +}; + +static int beagle_devices_init(void) +{ + int ret; + + ret = register_device(&sdram_dev); + if (ret) + goto failed; + +#ifdef CONFIG_GPMC + /* WP is made high and WAIT1 active Low */ + gpmc_generic_init(0x10); +#endif + gpmc_generic_nand_devices_init(0, 16, 1); + + armlinux_add_dram(&sdram_dev); +failed: + return ret; +} +device_initcall(beagle_devices_init); diff --git a/arch/arm/boards/omap/board-omap3evm.c b/arch/arm/boards/omap/board-omap3evm.c new file mode 100644 index 0000000000..619ea94485 --- /dev/null +++ b/arch/arm/boards/omap/board-omap3evm.c @@ -0,0 +1,275 @@ +/** + * @file + * @brief Board Initialization routines for OMAP3EVM. + * + * FileName: arch/arm/boards/omap/board-omap3evm.c + * + * This board is based on OMAP3530. + * More on OMAP3530 (including documentation can be found here): + * http://focus.ti.com/docs/prod/folders/print/omap3530.html + * + * This file provides initialization in two stages: + * @li Boot time initialization - just get SDRAM working. + * This is run from SRAM - so no case constructs and global vars can be used. + * @li Run time initialization - this is for the rest of the initializations + * such as flash, uart etc. + * + * Boot time initialization includes: + * @li SDRAM initialization. + * @li Pin Muxing relevant for the EVM. + * + * Run time initialization includes + * @li serial @ref serial_ns16550.c driver device definition + * + * Originally from arch/arm/boards/omap/board-beagle.c + */ + +/* + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * Sanjeev Premi <premi@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <console.h> +#include <init.h> +#include <driver.h> +#include <asm/io.h> +#include <ns16550.h> +#include <asm/armlinux.h> +#include <mach/silicon.h> +#include <mach/sdrc.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> +#include <mach/control.h> +#include <mach/omap3-mux.h> +#include <mach/gpmc.h> +#include "board.h" + + +/* + * Boot-time initialization(s) + */ + +/** + * @brief Initialize the SDRC module + * + * @return void + */ +static void sdrc_init(void) +{ + /* SDRAM software reset */ + /* No idle ack and RESET enable */ + writel(0x1A, SDRC_REG(SYSCONFIG)); + sdelay(100); + /* No idle ack and RESET disable */ + writel(0x18, SDRC_REG(SYSCONFIG)); + + /* SDRC Sharing register */ + /* 32-bit SDRAM on data lane [31:0] - CS0 */ + /* pin tri-stated = 1 */ + writel(0x00000100, SDRC_REG(SHARING)); + + /* ----- SDRC Registers Configuration --------- */ + /* SDRC_MCFG0 register */ + writel(0x02584099, SDRC_REG(MCFG_0)); + + /* SDRC_RFR_CTRL0 register */ + writel(0x54601, SDRC_REG(RFR_CTRL_0)); + + /* SDRC_ACTIM_CTRLA0 register */ + writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0)); + + /* SDRC_ACTIM_CTRLB0 register */ + writel(0x12214, SDRC_REG(ACTIM_CTRLB_0)); + + /* Disble Power Down of CKE due to 1 CKE on combo part */ + writel(0x00000081, SDRC_REG(POWER)); + + /* SDRC_MANUAL command register */ + /* NOP command */ + writel(0x00000000, SDRC_REG(MANUAL_0)); + /* Precharge command */ + writel(0x00000001, SDRC_REG(MANUAL_0)); + /* Auto-refresh command */ + writel(0x00000002, SDRC_REG(MANUAL_0)); + /* Auto-refresh command */ + writel(0x00000002, SDRC_REG(MANUAL_0)); + + /* SDRC MR0 register Burst length=4 */ + writel(0x00000032, SDRC_REG(MR_0)); + + /* SDRC DLLA control register */ + writel(0x0000000A, SDRC_REG(DLLA_CTRL)); + + return; +} + +/** + * @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3 + * do not have alternate modes. We don't program these pins. + * + * See @ref MUX_VAL for description of the muxing mode. + * + * @return void + */ +static void mux_config(void) +{ + /* + * SDRC + * - SDRC_D0-SDRC_D31: Default MUX mode is mode0. + */ + + /* + * GPMC + * - GPMC_D0-GPMC_D7: Default MUX mode is mode0. + * - GPMC_NADV_ALE: Default MUX mode is mode0. + * - GPMC_NOE: Default MUX mode is mode0. + * - GPMC_NWE: Default MUX mode is mode0. + * - GPMC_WAIT0: Default MUX mode is mode0. + */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); + + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); + + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); + + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); + + /* + * Serial Interface + */ +#if defined(CONFIG_OMAP3EVM_UART1) + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); +#elif defined(CONFIG_OMAP3EVM_UART3) + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); +#endif +} + +/** + * @brief The basic entry point for board initialization. + * + * This is called as part of machine init (after arch init). + * This is again called with stack in SRAM, so not too many + * constructs possible here. + * + * @return void + */ +void board_init(void) +{ + int in_sdram = running_in_sdram(); + + mux_config(); + /* Dont reconfigure SDRAM while running in SDRAM! */ + if (!in_sdram) + sdrc_init(); +} + +/* + * Run-time initialization(s) + */ + +#ifdef CONFIG_DRIVER_SERIAL_NS16550 + +static struct NS16550_plat serial_plat = { + .clock = 48000000, /* 48MHz (APLL96/2) */ + .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR, + .reg_read = omap_uart_read, + .reg_write = omap_uart_write, +}; + +static struct device_d omap3evm_serial_device = { + .name = "serial_ns16550", +#if defined(CONFIG_OMAP3EVM_UART1) + .map_base = OMAP_UART1_BASE, +#elif defined(CONFIG_OMAP3EVM_UART3) + .map_base = OMAP_UART3_BASE, +#endif + .size = 1024, + .platform_data = (void *)&serial_plat, +}; + +/** + * @brief Initialize the serial port to be used as console. + * + * @return result of device registration + */ +static int omap3evm_init_console(void) +{ + return register_device(&omap3evm_serial_device); +} +console_initcall(omap3evm_init_console); +#endif /* CONFIG_DRIVER_SERIAL_NS16550 */ + +static struct memory_platform_data sram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0x80000000, + .size = 128 * 1024 * 1024, + .platform_data = &sram_pdata, +}; + +static int omap3evm_init_devices(void) +{ + int ret; + + ret = register_device(&sdram_dev); + if (ret) + goto failed; + +#ifdef CONFIG_GPMC + /* + * WP is made high and WAIT1 active Low + */ + gpmc_generic_init(0x10); +#endif + + armlinux_add_dram(&sdram_dev); + +failed: + return ret; +} +device_initcall(omap3evm_init_devices); diff --git a/arch/arm/boards/omap/board-sdp343x.c b/arch/arm/boards/omap/board-sdp343x.c new file mode 100644 index 0000000000..32d1a4235c --- /dev/null +++ b/arch/arm/boards/omap/board-sdp343x.c @@ -0,0 +1,672 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief SDP3430 Specific Board Initialization routines + */ + +/** + * @page ti_SDP3430 Texas Instruments SDP3430 + * + * FileName: arch/arm/boards/omap/board-sdp343x.c + * + * SDP3430 from Texas Instruments as described here: + * http://www.ti.com/omap3430_devplatform + * This file provides initialization in two stages: + * @li boot time initialization - do basics required to get SDRAM working. + * This is run from SRAM - so no case constructs and global vars can be used. + * @li run time initialization - this is for the rest of the initializations + * such as flash, uart etc. + * + * Boot time initialization includes: + * @li SDRAM initialization. + * @li Pin Muxing relevant for SDP3430. + * + * Run time initialization includes + * @li serial @ref serial_ns16550.c driver device definition + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ + +#include <common.h> +#include <console.h> +#include <init.h> +#include <driver.h> +#include <asm/io.h> +#include <ns16550.h> +#include <asm/armlinux.h> +#include <mach/silicon.h> +#include <mach/sdrc.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> +#include <mach/control.h> +#include <mach/omap3-mux.h> +#include <mach/gpmc.h> +#include "board.h" + +/******************** Board Boot Time *******************/ +static void sdrc_init(void); +static void mux_config(void); + +/** + * @brief The basic entry point for board initialization. + * + * This is called as part of machine init (after arch init). + * This is again called with stack in SRAM, so not too many + * constructs possible here. + * + * @return void + */ +void board_init(void) +{ + int in_sdram = running_in_sdram(); + mux_config(); + if (!in_sdram) + sdrc_init(); +} + +/** + * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0 + * + * @return void + */ +static void sdrc_init(void) +{ + /* Issue SDRC Soft reset */ + writel(0x12, SDRC_REG(SYSCONFIG)); + /* Wait until Reset complete */ + while ((readl(SDRC_REG(STATUS)) & 0x1) == 0); + /* SDRC to normal mode */ + writel(0x10, SDRC_REG(SYSCONFIG)); + /* SDRC Sharing register */ + /* 32-bit SDRAM on data lane [31:0] - CS0 */ + /* pin tri-stated = 1 */ + writel(0x00000100, SDRC_REG(SHARING)); + + /* ----- SDRC_REG(CS0 Configuration --------- */ + /* SDRC_REG(MCFG0 register */ + writel(0x02584019, SDRC_REG(MCFG_0)); + + /* SDRC_REG(RFR_CTRL0 register */ + writel(0x0003DE01, SDRC_REG(RFR_CTRL_0)); + + /* SDRC_REG(ACTIM_CTRLA0 register */ + writel(0X5A9A4486, SDRC_REG(ACTIM_CTRLA_0)); + + /* SDRC_REG(ACTIM_CTRLB0 register */ + writel(0x00000010, SDRC_REG(ACTIM_CTRLB_0)); + + /* Disble Power Down of CKE cuz of 1 CKE on combo part */ + writel(0x00000081, SDRC_REG(POWER)); + + /* SDRC_REG(Manual command register */ + /* NOP command */ + writel(0x00000000, SDRC_REG(MANUAL_0)); + /* Precharge command */ + writel(0x00000001, SDRC_REG(MANUAL_0)); + /* Auto-refresh command */ + writel(0x00000002, SDRC_REG(MANUAL_0)); + /* Auto-refresh command */ + writel(0x00000002, SDRC_REG(MANUAL_0)); + + /* SDRC MR0 register */ + /* CAS latency = 3 */ + /* Write Burst = Read Burst */ + /* Serial Mode */ + writel(0x00000032, SDRC_REG(MR_0)); /* Burst length =4 */ + + /* SDRC DLLA control register */ + /* Enable DLL A */ + writel(0x0000000A, SDRC_REG(DLLA_CTRL)); + + /* wait until DLL is locked */ + while ((readl(SDRC_REG(DLLA_STATUS)) & 0x4) == 0); + return; +} + +/** + * @brief Do the pin muxing required for Board operation. + * + * See @ref MUX_VAL for description of the muxing mode. Since some versions + * of Linux depend on all pin muxing being done at barebox level, we may need to + * enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing. + * + * @return void + */ +static void mux_config(void) +{ + /* Essential MUX Settings */ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /* SDRC_D0 */ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /* SDRC_D1 */ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /* SDRC_D2 */ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /* SDRC_D3 */ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /* SDRC_D4 */ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /* SDRC_D5 */ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /* SDRC_D6 */ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /* SDRC_D7 */ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /* SDRC_D8 */ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /* SDRC_D9 */ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /* SDRC_D10 */ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /* SDRC_D11 */ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /* SDRC_D12 */ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /* SDRC_D13 */ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /* SDRC_D14 */ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /* SDRC_D15 */ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /* SDRC_D16 */ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /* SDRC_D17 */ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /* SDRC_D18 */ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /* SDRC_D19 */ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /* SDRC_D20 */ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /* SDRC_D21 */ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /* SDRC_D22 */ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /* SDRC_D23 */ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /* SDRC_D24 */ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /* SDRC_D25 */ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /* SDRC_D26 */ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /* SDRC_D27 */ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /* SDRC_D28 */ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /* SDRC_D29 */ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /* SDRC_D30 */ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /* SDRC_D31 */ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /* SDRC_CLK */ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /* SDRC_DQS0 */ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /* SDRC_DQS1 */ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /* SDRC_DQS2 */ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /* SDRC_DQS3 */ + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); /* GPMC_A1 */ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); /* GPMC_A2 */ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); /* GPMC_A3 */ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); /* GPMC_A4 */ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); /* GPMC_A5 */ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); /* GPMC_A6 */ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); /* GPMC_A7 */ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); /* GPMC_A8 */ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); /* GPMC_A9 */ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); /* GPMC_A10 */ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)); /* GPMC_D0 */ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)); /* GPMC_D1 */ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)); /* GPMC_D2 */ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)); /* GPMC_D3 */ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)); /* GPMC_D4 */ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)); /* GPMC_D5 */ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)); /* GPMC_D6 */ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)); /* GPMC_D7 */ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); /* GPMC_D8 */ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); /* GPMC_D9 */ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); /* GPMC_D10 */ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); /* GPMC_D11 */ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); /* GPMC_D12 */ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); /* GPMC_D13 */ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); /* GPMC_D14 */ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); /* GPMC_D15 */ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /* GPMC_NCS0 */ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /* GPMC_NCS1 */ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /* GPMC_NCS2 */ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /* GPMC_NCS3 */ + /* GPIO_55 - FLASH_DIS */ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)); + /* GPIO_56 - TORCH_EN */ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)); + /* GPIO_57 - AGPS SLP */ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4)); + /* GPMC_58 - WLAN_IRQ */ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)); + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); /* GPMC_CLK */ + /* GPMC_NADV_ALE */ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /* GPMC_NOE */ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /* GPMC_NWE */ + /* GPMC_NBE0_CLE */ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4)); /* GPIO_61 -BT_SHUTDN */ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /* GPMC_NWP */ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /* GPMC_WAIT0 */ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /* GPMC_WAIT1 */ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /* GPIO_64 */ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /* GPIO_65 */ + + /* SERIAL INTERFACE */ + /* UART3_CTS_RCTX */ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); + /* UART3_RTS_SD */ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); + /* UART3_RX_IRRX */ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); + /* UART3_TX_IRTX */ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); + /* HSUSB0_CLK */ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); + /* HSUSB0_STP */ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); + /* HSUSB0_DIR */ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); + /* HSUSB0_NXT */ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); + /* HSUSB0_DATA0 */ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); + /* HSUSB0_DATA1 */ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); + /* HSUSB0_DATA2 */ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); + /* HSUSB0_DATA3 */ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); + /* HSUSB0_DATA4 */ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); + /* HSUSB0_DATA5 */ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); + /* HSUSB0_DATA6 */ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); + /* HSUSB0_DATA7 */ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /* I2C1_SCL */ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /* I2C1_SDA */ +#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX + /* DSS */ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /* DSS_PCLK */ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /* DSS_HSYNC */ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /* DSS_VSYNC */ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /* DSS_ACBIAS */ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /* DSS_DATA0 */ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /* DSS_DATA1 */ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /* DSS_DATA2 */ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /* DSS_DATA3 */ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /* DSS_DATA4 */ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /* DSS_DATA5 */ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /* DSS_DATA6 */ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /* DSS_DATA7 */ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /* DSS_DATA8 */ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /* DSS_DATA9 */ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /* DSS_DATA10 */ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /* DSS_DATA11 */ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /* DSS_DATA12 */ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /* DSS_DATA13 */ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /* DSS_DATA14 */ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /* DSS_DATA15 */ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /* DSS_DATA16 */ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /* DSS_DATA17 */ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /* DSS_DATA18 */ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /* DSS_DATA19 */ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /* DSS_DATA20 */ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /* DSS_DATA21 */ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /* DSS_DATA22 */ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /* DSS_DATA23 */ + /* CAMERA */ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /* CAM_HS */ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /* CAM_VS */ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /* CAM_XCLKA */ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /* CAM_PCLK */ + /* GPIO_98 - CAM_RESET */ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /* CAM_D0 */ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /* CAM_D1 */ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /* CAM_D2 */ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /* CAM_D3 */ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /* CAM_D4 */ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /* CAM_D5 */ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /* CAM_D6 */ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /* CAM_D7 */ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /* CAM_D8 */ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /* CAM_D9 */ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /* CAM_D10 */ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /* CAM_D11 */ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /* CAM_XCLKB */ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /* GPIO_167 */ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /* CAM_STROBE */ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /* CSI2_DX0 */ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /* CSI2_DY0 */ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /* CSI2_DX1 */ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /* CSI2_DY1 */ + /* AUDIO INTERFACE */ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /* MCBSP2_FSX */ + /* MCBSP2_CLKX */ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /* MCBSP2_DR */ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /* MCBSP2_DX */ + /* EXPANSION CARD */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /* MMC1_CLK */ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /* MMC1_CMD */ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /* MMC1_DAT0 */ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /* MMC1_DAT1 */ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /* MMC1_DAT2 */ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /* MMC1_DAT3 */ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /* MMC1_DAT4 */ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /* MMC1_DAT5 */ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /* MMC1_DAT6 */ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /* MMC1_DAT7 */ + /* WIRELESS LAN */ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /* MMC2_CLK */ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /* MMC2_CMD */ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /* MMC2_DAT0 */ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /* MMC2_DAT1 */ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /* MMC2_DAT2 */ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /* MMC2_DAT3 */ + /* MMC2_DIR_DAT0 */ + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)); + /* MMC2_DIR_DAT1 */ + MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)); + /* MMC2_DIR_CMD */ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)); + /* MMC2_CLKIN */ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)); + /* BLUETOOTH */ + /* MCBSP3_DX */ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); + /* MCBSP3_DR */ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); + /* MCBSP3_CLKX */ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); + /* MCBSP3_FSX */ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /* UART2_CTS */ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /* UART2_RTS */ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /* UART2_TX */ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /* UART2_RX */ + /* MODEM INTERFACE */ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /* UART1_TX */ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /* UART1_RTS */ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /* UART1_CTS */ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /* UART1_RX */ + /* SSI1_DAT_RX */ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)); + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)); /* SSI1_FLAG_RX */ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)); /* SSI1_RDY_RX */ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)); /* SSI1_WAKE */ + /* MCBSP1_CLKR */ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); + /* GPIO_157 - BT_WKUP */ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)); + /* MCBSP1_DX */ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /* MCBSP1_DR */ + /* MCBSP_CLKS */ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); + /* MCBSP1_FSX */ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); + /* MCBSP1_CLKX */ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); + /* SERIAL INTERFACE */ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /* I2C2_SCL */ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /* I2C2_SDA */ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /* I2C3_SCL */ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /* I2C3_SDA */ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /* I2C4_SCL */ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /* I2C4_SDA */ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /* HDQ_SIO */ + /* MCSPI1_CLK */ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); + /* MCSPI1_SIMO */ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); + /* MCSPI1_SOMI */ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); + /* MCSPI1_CS0 */ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); + /* MCSPI1_CS1 */ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)); + /* GPIO_176-NOR_DPD */ + MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)); + /* MCSPI1_CS3 */ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); + /* MCSPI2_CLK */ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); + /* MCSPI2_SIMO */ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); + /* MCSPI2_SOMI */ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); + /* MCSPI2_CS0 */ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); + /* MCSPI2_CS1 */ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); + + /* CONTROL AND DEBUG */ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /* SYS_32K */ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /* SYS_CLKREQ */ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /* SYS_NIRQ */ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /* GPIO_2 - PEN_IRQ */ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /* GPIO_3 */ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /* GPIO_4 - MMC1_WP */ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /* GPIO_5 - LCD_ENVDD */ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /* GPIO_6 - LAN_INTR0 */ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /* GPIO_7 - MMC2_WP */ + /* GPIO_8-LCD_ENBKL */ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)); + /* SYS_OFF_MODE */ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); + /* SYS_CLKOUT1 */ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)); /* GPIO_186 */ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /* JTAG_NTRST */ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /* JTAG_TCK */ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /* JTAG_TMS */ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /* JTAG_TDI */ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /* JTAG_EMU0 */ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /* JTAG_EMU1 */ + /* HSUSB1_TLL_STP */ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); + /* HSUSB1_TLL_CLK */ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); + /* HSUSB1_TLL_DATA0 */ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1)); + /* MCSPI3_CS0 */ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1)); + /* HSUSB1_TLL_DATA2 */ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1)); + /* HSUSB1_TLL_DATA7 */ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1)); + /* HSUSB1_TLL_DATA4 */ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB1_TLL_DATA5 */ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB1_TLL_DATA6 */ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB1_TLL_DATA3 */ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB1_TLL_DIR */ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB1_TLL_NXT */ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB2_TLL_CLK */ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB2_TLL_STP */ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB2_TLL_DIR */ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB2_TLL_NXT */ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB2_TLL_DATA0 */ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); + /* HSUSB2_TLL_DATA1 */ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); + + /* DIE TO DIE */ + MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)); /* D2D_MCAD0 */ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /* D2D_MCAD1 */ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /* D2D_MCAD2 */ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /* D2D_MCAD3 */ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /* D2D_MCAD4 */ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /* D2D_MCAD5 */ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /* D2D_MCAD6 */ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /* D2D_MCAD7 */ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /* D2D_MCAD8 */ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /* D2D_MCAD9 */ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /* D2D_MCAD10 */ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /* D2D_MCAD11 */ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /* D2D_MCAD12 */ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /* D2D_MCAD13 */ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /* D2D_MCAD14 */ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /* D2D_MCAD15 */ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /* D2D_MCAD16 */ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /* D2D_MCAD17 */ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /* D2D_MCAD18 */ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /* D2D_MCAD19 */ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /* D2D_MCAD20 */ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /* D2D_MCAD21 */ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /* D2D_MCAD22 */ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /* D2D_MCAD23 */ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /* D2D_MCAD24 */ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /* D2D_MCAD25 */ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /* D2D_MCAD26 */ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /* D2D_MCAD27 */ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /* D2D_MCAD28 */ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /* D2D_MCAD29 */ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /* D2D_MCAD30 */ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /* D2D_MCAD31 */ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /* D2D_MCAD32 */ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /* D2D_MCAD33 */ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /* D2D_MCAD34 */ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /* D2D_MCAD35 */ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /* D2D_MCAD36 */ + /* D2D_CLK26MI */ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); + /* D2D_NRESPWRON */ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); + /* D2D_NRESWARM */ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); + /* D2D_ARM9NIRQ */ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); + /* D2D_UMA2P6FIQ */ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); + /* D2D_SPINT */ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); + /* D2D_FRINT */ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); + /* D2D_DMAREQ0 */ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); + /* D2D_DMAREQ1 */ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); + /* D2D_DMAREQ2 */ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); + /* D2D_DMAREQ3 */ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); + /* D2D_N3GTRST */ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); + /* D2D_N3GTDI */ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); + /* D2D_N3GTDO */ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); + /* D2D_N3GTMS */ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); + /* D2D_N3GTCK */ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); + /* D2D_N3GRTCK */ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); + /* D2D_MSTDBY */ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); + /* D2D_SWAKEUP */ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); + /* D2D_IDLEREQ */ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); + /* D2D_IDLEACK */ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); + /* D2D_MWRITE */ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); + /* D2D_SWRITE */ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); + /* D2D_MREAD */ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); + /* D2D_SREAD */ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); + /* D2D_MBUSFLAG */ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); + /* D2D_SBUSFLAG */ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); + /* SDRC_CKE0 */ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); + /* SDRC_CKE1 NOT USED */ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); +#endif /* CONFIG_MACH_OMAP_ADVANCED_MUX */ +} + +/******************** Board Run Time *******************/ + +/*-----------------------CONSOLE Devices -----------------------------------*/ + +#ifdef CONFIG_DRIVER_SERIAL_NS16550 + +static struct NS16550_plat serial_plat = { + .clock = 48000000, /* 48MHz (APLL96/2) */ + .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR, + .reg_read = omap_uart_read, + .reg_write = omap_uart_write, +}; + +static struct device_d sdp3430_serial_device = { + .name = "serial_ns16550", + .map_base = OMAP_UART3_BASE, + .size = 1024, + .platform_data = (void *)&serial_plat, +}; + +/** + * @brief UART serial port initialization - remember to enable COM clocks in arch + * + * @return result of device registration + */ +static int sdp3430_console_init(void) +{ + /* Register the serial port */ + return register_device(&sdp3430_serial_device); +} + +console_initcall(sdp3430_console_init); +#endif /* CONFIG_DRIVER_SERIAL_NS16550 */ + +/*------------------------- FLASH Devices -----------------------------------*/ +static int sdp3430_flash_init(void) +{ +#ifdef CONFIG_GPMC + /* WP is made high and WAIT1 active Low */ + gpmc_generic_init(0x10); +#endif + return 0; +} + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +struct device_d sdram_dev = { + .name = "mem", + .map_base = 0x80000000, + .size = 128 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +/*-----------------------Generic Devices Initialization ---------------------*/ + +static int sdp3430_devices_init(void) +{ + int ret; + ret = register_device(&sdram_dev); + if (ret) + goto failed; + ret = sdp3430_flash_init(); + if (ret) + goto failed; + + armlinux_add_dram(&sdram_dev); +failed: + return ret; +} + +device_initcall(sdp3430_devices_init); diff --git a/arch/arm/boards/omap/board.h b/arch/arm/boards/omap/board.h new file mode 100644 index 0000000000..cf231a208e --- /dev/null +++ b/arch/arm/boards/omap/board.h @@ -0,0 +1,35 @@ +/** + * @file + * @brief exported generic APIs which various board files implement + * + * FileName: arch/arm/boards/omap/board.h + * + * This file will not contain any board specific implementations. + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Raghavendra KH <r-khandenahally@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __BOARD_OMAP_H_ +#define __BOARD_OMAP_H_ + +/** Generic Board initialization called from platform.S */ +void board_init(void); + +#endif /* __BOARD_OMAP_H_ */ diff --git a/arch/arm/boards/omap/config.h b/arch/arm/boards/omap/config.h new file mode 100644 index 0000000000..29d2ee2317 --- /dev/null +++ b/arch/arm/boards/omap/config.h @@ -0,0 +1,33 @@ +/** + * @file + * @brief provide a wrapper for standard malloc and stack size defines + * + * FileName: arch/arm/boards/omap/config.h + * + * Standard defines should be configurable for us to move Stack and malloc + * areas around this defines some basics for that + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MACH_OMAP_CONFIG_H +#define __MACH_OMAP_CONFIG_H + +#endif /* __MACH_OMAP_CONFIG_H */ diff --git a/arch/arm/boards/omap/devices-gpmc-nand.c b/arch/arm/boards/omap/devices-gpmc-nand.c new file mode 100644 index 0000000000..ac23e9d036 --- /dev/null +++ b/arch/arm/boards/omap/devices-gpmc-nand.c @@ -0,0 +1,101 @@ +/** + * @file + * @brief GPMC specific NAND devices + * + * FileName: arch/arm/boards/omap/devices-gpmc-nand.c + * + * GPMC NAND Devices such as those from Micron, Samsung are listed here + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <console.h> +#include <init.h> +#include <driver.h> +#include <clock.h> +#include <asm/io.h> + +#include <mach/silicon.h> +#include <mach/gpmc.h> +#include <mach/gpmc_nand.h> + +#define GPMC_CONF1_VALx8 0x00000800 +#define GPMC_CONF1_VALx16 0x00001800 +/* Set up the generic params */ + +/** GPMC timing for our nand device */ +static struct gpmc_config nand_cfg = { + .cfg = { + 0, /*CONF1 */ + 0x00141400, /*CONF2 */ + 0x00141400, /*CONF3 */ + 0x0F010F01, /*CONF4 */ + 0x010C1414, /*CONF5 */ +#ifdef CONFIG_ARCH_OMAP3 + /* Additional bits in OMAP3 */ + 0x1F040000 | +#endif + 0x00000A80, /*CONF6 */ + }, + + /* Nand: dont care about base address */ + .base = 0x28000000, + /* GPMC address map as small as possible */ + .size = GPMC_SIZE_16M, +}; + +/** NAND platform specific settings settings */ +static struct gpmc_nand_platform_data nand_plat = { + .cs = 0, + .max_timeout = MSECOND, + .wait_mon_pin = 0, + .priv = (void *)&nand_cfg, +}; + +/** NAND device definition */ +static struct device_d gpmc_generic_nand_nand_device = { + .name = "gpmc_nand", + .map_base = OMAP_GPMC_BASE, + .size = 1024 * 4, /* GPMC size */ + .platform_data = (void *)&nand_plat, +}; + +/** + * @brief gpmc_generic_nand_devices_init - init generic nand device + * + * @return success/fail based on device funtion + */ +int gpmc_generic_nand_devices_init(int cs, int width, int hwecc) +{ + nand_plat.cs = cs; + + if (width == 16) + nand_cfg.cfg[0] = GPMC_CONF1_VALx16; + else + nand_cfg.cfg[0] = GPMC_CONF1_VALx8; + + nand_plat.device_width = width; + nand_plat.plat_options = hwecc ? NAND_HWECC_ENABLE : 0; + + /* Configure GPMC CS before register */ + gpmc_cs_config(nand_plat.cs, &nand_cfg); + return register_device(&gpmc_generic_nand_nand_device); +} diff --git a/arch/arm/boards/omap/env/bin/init b/arch/arm/boards/omap/env/bin/init new file mode 100644 index 0000000000..224a6b40be --- /dev/null +++ b/arch/arm/boards/omap/env/bin/init @@ -0,0 +1 @@ +# Dummy Init environment script diff --git a/arch/arm/boards/omap/platform.S b/arch/arm/boards/omap/platform.S new file mode 100644 index 0000000000..77b7eed906 --- /dev/null +++ b/arch/arm/boards/omap/platform.S @@ -0,0 +1,65 @@ +/** + * @file + * @brief Wrapper to call board level initialization routine + * + * FileName: arch/arm/boards/omap/platform.S + * + * board_init_lowlevel is defined here. This calls board_init which + * is linked to the binary - the board_init only has a SRAM stack. + * so it needs to be careful about the usage of global variables + * and the likes. Enabled only if CONFIG_MACH_DO_LOWLEVEL_INIT is + * defined + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <mach/silicon.h> + +#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT +/** + * @fn void board_init_lowlevel(void) + * + * @brief This provides a assembly wrapper setting up SRAM before calling + * board_init + * + * @return void + */ +.globl board_init_lowlevel +board_init_lowlevel: + /* Setup a temporary stack so that we can call C functions + * Yes. this might have been already done by arch code. + * No harm in being a bit redundant to avoid future complications + */ + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + str lr, [sp] /* stash current link register */ + mov ip, lr /* save link reg across call */ + /* Do the pin muxes, sdram init etc..board-xxx.c */ + bl board_init + ldr lr, [sp] /* restore current link register */ + ldr ip, [sp] /* restore save ip */ + /* back to arch calling code */ + mov pc, lr +SRAM_STACK: + .word OMAP_SRAM_STACK + +#endif /* CONFIG_MACH_DO_LOWLEVEL_INIT */ diff --git a/arch/arm/boards/pcm037/Makefile b/arch/arm/boards/pcm037/Makefile new file mode 100644 index 0000000000..7d36b77df0 --- /dev/null +++ b/arch/arm/boards/pcm037/Makefile @@ -0,0 +1,24 @@ +# +# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y += lowlevel_init.o +obj-y += pcm037.o diff --git a/arch/arm/boards/pcm037/config.h b/arch/arm/boards/pcm037/config.h new file mode 100644 index 0000000000..5495d0309c --- /dev/null +++ b/arch/arm/boards/pcm037/config.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Definitions related to passing arguments to kernel. + */ + +/* #define CONFIG_SYSPLL_CLK_FREQ 26000000 */ + +/* FIXME */ +#define CONFIG_MX31_HCLK_FREQ 26000000 +#define CONFIG_MX31_CLK32 32000 + +#endif + +/* nothing to do here yet */ diff --git a/arch/arm/boards/pcm037/env/config b/arch/arm/boards/pcm037/env/config new file mode 100644 index 0000000000..bf15620057 --- /dev/null +++ b/arch/arm/boards/pcm037/env/config @@ -0,0 +1,56 @@ +#!/bin/sh + +machine=pcm037 +eth0.serverip= +user= + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net', 'nor' or 'nand' +kernel_loc=net +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root-$machine.$rootfs_type + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +kernelimage_type=zimage +kernelimage=zImage-$machine +#kernelimage_type=uimage +#kernelimage=uImage-$machine +#kernelimage_type=raw +#kernelimage=Image-$machine +#kernelimage_type=raw_lzo +#kernelimage=Image-$machine.lzo + +if [ -n $user ]; then + kernelimage="$user"-"$kernelimage" + nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine" + rootfsimage="$user"-"$rootfsimage" +else + nfsroot="$eth0.serverip:/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttymxc0,115200" + +nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nor=3 + +nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nand=7 + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S new file mode 100644 index 0000000000..8988db23a2 --- /dev/null +++ b/arch/arm/boards/pcm037/lowlevel_init.S @@ -0,0 +1,167 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define writeb(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + strb r1, [r0]; + +.macro DELAY loops + ldr r2, =\loops +1: + subs r2, r2, #1 + nop + bcs 1b +.endm + + .section ".text_bare_init","ax" + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr + writel(IPU_CONF_DI_EN, IPU_CONF) + writel(0x074B0BF5, IMX_CCM_BASE + CCM_CCMR) + + DELAY 0x40000 + + writel(0x074B0BF5 | CCMR_MPE, IMX_CCM_BASE + CCM_CCMR) + writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, IMX_CCM_BASE + CCM_CCMR) + + writel(PDR0_CSI_PODF(0xff1) | \ + PDR0_PER_PODF(7) | \ + PDR0_HSP_PODF(3) | \ + PDR0_NFC_PODF(5) | \ + PDR0_IPG_PODF(1) | \ + PDR0_MAX_PODF(3) | \ + PDR0_MCU_PODF(0), \ + IMX_CCM_BASE + CCM_PDR0) + + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), IMX_CCM_BASE + CCM_MPCTL) + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), IMX_CCM_BASE + CCM_SPCTL) + + /* Configure IOMUXC + * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) + * (behaviour copied by sha, source unknown) + */ + mov r1, #0; + ldr r0, =0x43FAC26C + str r1, [r0], #4 + str r1, [r0], #4 + str r1, [r0], #0x10 + + ldr r2, =0x43FAC2DC +clear_iomux: + str r1, [r0], #4 + cmp r0, r2 + bls clear_iomux + writel(0x1000, 0x43FAC27C )/* CS2 CSD0) */ + + /* Skip SDRAM initialization if we run from RAM */ + cmp pc, #0x80000000 + blo 1f + cmp pc, #0x90000000 + bhs 1f + + mov pc, r10 +1: + +#if defined CONFIG_PCM037_SDRAM_BANK0_128MB +#define ROWS0 ESDCTL0_ROW13 +#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB +#define ROWS0 ESDCTL0_ROW14 +#endif + writel(0x00000004, ESDMISC) + writel(0x006ac73a, ESDCFG0) + writel(0x90100000 | ROWS0, ESDCTL0) + writel(0x12344321, IMX_SDRAM_CS0 + 0xf00) + writel(0xa0100000 | ROWS0, ESDCTL0) + writel(0x12344321, IMX_SDRAM_CS0) + writel(0x12344321, IMX_SDRAM_CS0) + writel(0xb0100000 | ROWS0, ESDCTL0) + writeb(0xda, IMX_SDRAM_CS0 + 0x33) + writeb(0xff, IMX_SDRAM_CS0 + 0x01000000) + writel(0x80226080 | ROWS0, ESDCTL0) + writel(0xDEADBEEF, IMX_SDRAM_CS0) + writel(0x0000000c, ESDMISC) + +#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE +#if defined CONFIG_PCM037_SDRAM_BANK1_128MB +#define ROWS1 ESDCTL0_ROW13 +#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB +#define ROWS1 ESDCTL0_ROW14 +#endif + writel(0x006ac73a, ESDCFG1) + writel(0x90100000 | ROWS1, ESDCTL1) + writel(0x12344321, IMX_SDRAM_CS1 + 0xf00) + writel(0xa0100000 | ROWS1, ESDCTL1) + writel(0x12344321, IMX_SDRAM_CS1) + writel(0x12344321, IMX_SDRAM_CS1) + writel(0xb0100000 | ROWS1, ESDCTL1) + writeb(0xda, IMX_SDRAM_CS1 + 0x33) + writeb(0xff, IMX_SDRAM_CS1 + 0x01000000) + writel(0x80226080 | ROWS1, ESDCTL1) + writel(0xDEADBEEF, IMX_SDRAM_CS1) + writel(0x0000000c, ESDMISC) +#endif + +#ifdef CONFIG_NAND_IMX_BOOT + ldr sp, =0x80f00000 /* Setup a temporary stack in SDRAM */ + + ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ + ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + + /* skip NAND boot if not running from NFC space */ + cmp pc, r0 + blo ret + cmp pc, r2 + bhs ret + + /* Move ourselves out of NFC SRAM */ + ldr r1, =TEXT_BASE + +copy_loop: + ldmia r0!, {r3-r9} /* copy from source address [r0] */ + stmia r1!, {r3-r9} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + ldr pc, =1f /* Jump to SDRAM */ +1: + bl nand_boot /* Load barebox from NAND Flash */ + + ldr r1, =IMX_NFC_BASE - TEXT_BASE + sub r10, r10, r1 /* adjust return address from NFC SRAM */ +ret: +#endif /* CONFIG_NAND_IMX_BOOT */ + + mov pc, r10 + diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c new file mode 100644 index 0000000000..2e6968b844 --- /dev/null +++ b/arch/arm/boards/pcm037/pcm037.c @@ -0,0 +1,340 @@ +/* + * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Board support for Phytec's, i.MX31 based CPU card, called: PCM037 + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <fs.h> +#include <environment.h> +#include <usb/isp1504.h> +#include <mach/imx-regs.h> +#include <mach/iomux-mx31.h> +#include <asm/armlinux.h> +#include <mach/gpio.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <partition.h> +#include <asm/mach-types.h> +#include <mach/imx-nand.h> + + +/* + * Up to 32MiB NOR type flash, connected to + * CS line 0, data width is 16 bit + */ +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = IMX_CS0_BASE, + .size = 32 * 1024 * 1024, /* area size */ +}; + +/* + * up to 2MiB static RAM type memory, connected + * to CS4, data width is 16 bit + */ +static struct memory_platform_data sram_dev_pdata0 = { + .name = "sram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sram_dev = { + .name = "mem", + .map_base = IMX_CS4_BASE, + .size = IMX_CS4_RANGE, /* area size */ + .platform_data = &sram_dev_pdata0, +}; + +/* + * SMSC 9217 network controller + * connected to CS line 1 and interrupt line + * GPIO3, data width is 16 bit + */ +static struct device_d network_dev = { + .name = "smc911x", + .map_base = IMX_CS1_BASE, + .size = IMX_CS1_RANGE, /* area size */ +}; + +#if defined CONFIG_PCM037_SDRAM_BANK0_128MB +#define SDRAM0 128 +#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB +#define SDRAM0 256 +#endif + +static struct memory_platform_data ram_dev_pdata0 = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram0_dev = { + .name = "mem", + .map_base = IMX_SDRAM_CS0, + .size = SDRAM0 * 1024 * 1024, /* fix size */ + .platform_data = &ram_dev_pdata0, +}; + +#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE + +#if defined CONFIG_PCM037_SDRAM_BANK1_128MB +#define SDRAM1 128 +#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB +#define SDRAM1 256 +#endif + +static struct memory_platform_data ram_dev_pdata1 = { + .name = "ram1", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram1_dev = { + .name = "mem", + .map_base = IMX_SDRAM_CS1, + .size = SDRAM1 * 1024 * 1024, /* fix size */ + .platform_data = &ram_dev_pdata1, +}; +#endif + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = 0xB8000000, + .platform_data = &nand_info, +}; + +#ifdef CONFIG_USB +static struct device_d usbotg_dev = { + .name = "ehci", + .map_base = IMX_OTG_BASE, + .size = 0x200, +}; + +static struct device_d usbh2_dev = { + .name = "ehci", + .map_base = IMX_OTG_BASE + 0x400, + .size = 0x200, +}; + +static void pcm037_usb_init(void) +{ + u32 tmp; + + /* enable clock */ + tmp = readl(0x53f80000); + tmp |= (1 << 9); + writel(tmp, 0x53f80000); + + /* Host 1 */ + tmp = readl(IMX_OTG_BASE + 0x600); + tmp &= ~((3 << 21) | 1); + tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20); + writel(tmp, IMX_OTG_BASE + 0x600); + + tmp = readl(IMX_OTG_BASE + 0x184); + tmp &= ~(3 << 30); + tmp |= 2 << 30; + writel(tmp, IMX_OTG_BASE + 0x184); + + imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0); + imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1); + imx_iomux_mode(MX31_PIN_USBOTG_DATA2__USBOTG_DATA2); + imx_iomux_mode(MX31_PIN_USBOTG_DATA3__USBOTG_DATA3); + imx_iomux_mode(MX31_PIN_USBOTG_DATA4__USBOTG_DATA4); + imx_iomux_mode(MX31_PIN_USBOTG_DATA5__USBOTG_DATA5); + imx_iomux_mode(MX31_PIN_USBOTG_DATA6__USBOTG_DATA6); + imx_iomux_mode(MX31_PIN_USBOTG_DATA7__USBOTG_DATA7); + imx_iomux_mode(MX31_PIN_USBOTG_CLK__USBOTG_CLK); + imx_iomux_mode(MX31_PIN_USBOTG_DIR__USBOTG_DIR); + imx_iomux_mode(MX31_PIN_USBOTG_NXT__USBOTG_NXT); + imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP); + + mdelay(50); + isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x170), 1); + + /* Host 2 */ + tmp = readl(IOMUXC_BASE + 0x8); + tmp |= 1 << 11; + writel(tmp, IOMUXC_BASE + 0x8); + + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)); + +#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); + imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); + imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); + imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); + imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ + imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ + imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ + imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ + imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ + imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ + imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ + imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ + + tmp = readl(IMX_OTG_BASE + 0x600); + tmp &= ~((3 << 21) | 1); + tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); + writel(tmp, IMX_OTG_BASE + 0x600); + + tmp = readl(IMX_OTG_BASE + 0x584); + tmp &= ~(3 << 30); + tmp |= 2 << 30; + writel(tmp, IMX_OTG_BASE + 0x584); + + mdelay(50); + isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x570), 1); + + /* Set to Host mode */ + tmp = readl(IMX_OTG_BASE + 0x1a8); + writel(tmp | 0x3, IMX_OTG_BASE + 0x1a8); + +} +#endif + +#ifdef CONFIG_MMU +static void pcm037_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + mmu_enable(); + +#ifdef CONFIG_CACHE_L2X0 + l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); +#endif +} +#else +static void pcm037_mmu_init(void) +{ +} +#endif + +static int imx31_devices_init(void) +{ + pcm037_mmu_init(); + + __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ + __REG(CSCR_L(0)) = 0x10000d03; + __REG(CSCR_A(0)) = 0x00720900; + + __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ + __REG(CSCR_L(1)) = 0x444a4541; + __REG(CSCR_A(1)) = 0x44443302; + + __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ + __REG(CSCR_L(4)) = 0x22252521; + __REG(CSCR_A(4)) = 0x22220a00; + + __REG(CSCR_U(5)) = 0x0000DCF6; /* CS5: SJA1000 */ + __REG(CSCR_L(5)) = 0x444A0301; + __REG(CSCR_A(5)) = 0x44443302; + + register_device(&cfi_dev); + + /* + * Create partitions that should be + * not touched by any regular user + */ + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); /* ourself */ + devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); /* environment */ + + protect_file("/dev/env0", 1); + + register_device(&sram_dev); + register_device(&nand_dev); + register_device(&network_dev); + + register_device(&sdram0_dev); +#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE + register_device(&sdram1_dev); +#endif +#ifdef CONFIG_USB + pcm037_usb_init(); + register_device(&usbotg_dev); + register_device(&usbh2_dev); +#endif + + armlinux_add_dram(&sdram0_dev); +#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE + armlinux_add_dram(&sdram1_dev); +#endif + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_PCM037); + + return 0; +} + +device_initcall(imx31_devices_init); + +static struct device_d imx31_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 16 * 1024, +}; + +static int imx31_console_init(void) +{ + /* init gpios for serial port */ + imx_iomux_mode(MX31_PIN_RXD1__RXD1); + imx_iomux_mode(MX31_PIN_TXD1__TXD1); + imx_iomux_mode(MX31_PIN_CTS1__CTS1); + imx_iomux_mode(MX31_PIN_RTS1__RTS1); + + register_device(&imx31_serial_device); + return 0; +} + +console_initcall(imx31_console_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif diff --git a/arch/arm/boards/pcm037/pcm037.dox b/arch/arm/boards/pcm037/pcm037.dox new file mode 100644 index 0000000000..b2afdd6acd --- /dev/null +++ b/arch/arm/boards/pcm037/pcm037.dox @@ -0,0 +1,11 @@ +/** @page pcm037 Phytec's phyCORE-i.MX31 + +This CPU card is based on a Freescale i.MX31 CPU. The card is shipped with: + +- up to 64MiB NOR type Flash Memory +- up to 2MiB static RAM +- 64MiB NAND type Flash Memory +- SMSC 9217 network controller +- 128MiB synchronous dynamic RAM + +*/ diff --git a/arch/arm/boards/pcm038/Makefile b/arch/arm/boards/pcm038/Makefile new file mode 100644 index 0000000000..a681ddafb9 --- /dev/null +++ b/arch/arm/boards/pcm038/Makefile @@ -0,0 +1,3 @@ + +obj-y += lowlevel.o pll_init.o +obj-y += pcm038.o diff --git a/arch/arm/boards/pcm038/config.h b/arch/arm/boards/pcm038/config.h new file mode 100644 index 0000000000..c2f5e7cc58 --- /dev/null +++ b/arch/arm/boards/pcm038/config.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Global defintions for the ARM i.MX27 based pcm038 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/pcm038/env/config b/arch/arm/boards/pcm038/env/config new file mode 100644 index 0000000000..a8be5c924d --- /dev/null +++ b/arch/arm/boards/pcm038/env/config @@ -0,0 +1,56 @@ +#!/bin/sh + +machine=pcm038 +eth0.serverip= +user= + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net', 'nor' or 'nand' +kernel_loc=net +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root-$machine.$rootfs_type + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +kernelimage_type=zimage +kernelimage=zImage-$machine +#kernelimage_type=uimage +#kernelimage=uImage-$machine +#kernelimage_type=raw +#kernelimage=Image-$machine +#kernelimage_type=raw_lzo +#kernelimage=Image-$machine.lzo + +if [ -n $user ]; then + kernelimage="$user"-"$kernelimage" + nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine" + rootfsimage="$user"-"$rootfsimage" +else + nfsroot="$eth0.serverip:/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttymxc0,115200" + +nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nor=3 + +nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nand=7 + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c new file mode 100644 index 0000000000..0c376f2fae --- /dev/null +++ b/arch/arm/boards/pcm038/lowlevel.c @@ -0,0 +1,117 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <init.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <mach/esdctl.h> +#include <asm/cache-l2x0.h> +#include <asm/io.h> +#include <mach/imx-nand.h> +#include <asm/barebox-arm.h> +#include <asm/system.h> +#include <asm-generic/memory_layout.h> + +static void __bare_init __naked insdram(void) +{ + uint32_t r; + + PCCR1 |= PCCR1_NFC_BAUDEN; + + /* setup a stack to be able to call imx_nand_load_image() */ + r = STACK_BASE + STACK_SIZE - 12; + __asm__ __volatile__("mov sp, %0" : : "r"(r)); + + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); + + board_init_lowlevel_return(); +} + +#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) + +void __bare_init __naked board_init_lowlevel(void) +{ + uint32_t r; + int i; + unsigned int *trg, *src; + + /* ahb lite ip interface */ + AIPI1_PSR0 = 0x20040304; + AIPI1_PSR1 = 0xDFFBFCFB; + AIPI2_PSR0 = 0x00000000; + AIPI2_PSR1 = 0xFFFFFFFF; + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0xa0000000 && r < 0xb0000000) + board_init_lowlevel_return(); + + /* + * DDR on CSD0 + */ + writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */ + + DSCR(3) = 0x55555555; /* Set the driving strength */ + DSCR(5) = 0x55555555; + DSCR(6) = 0x55555555; + DSCR(7) = 0x00005005; + DSCR(8) = 0x15555555; + + writel(0x00000004, ESDMISC); /* Initial reset */ + writel(0x006ac73a, ESDCFG0); + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */ + writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); + + for (i = 0; i < 8; i++) + writel(0, 0xa0000f00); + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); + + writeb(0xda, 0xa0000033); + writeb(0xff, 0xa1000000); + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0); + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)IMX_NFC_BASE; + trg = (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ + for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ + r = (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} + diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c new file mode 100644 index 0000000000..03794fc13d --- /dev/null +++ b/arch/arm/boards/pcm038/pcm038.c @@ -0,0 +1,423 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <fec.h> +#include <notifier.h> +#include <mach/gpio.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <mach/pmic.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <nand.h> +#include <command.h> +#include <spi/spi.h> +#include <asm/io.h> +#include <mach/imx-nand.h> +#include <mach/imx-pll.h> +#include <mach/imxfb.h> +#include <asm/mmu.h> +#include <usb/isp1504.h> +#include <mach/spi.h> +#include <mach/iomux-mx27.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0xC0000000, + .size = 32 * 1024 * 1024, +}; + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0xa0000000, + .size = 128 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +static struct memory_platform_data sram_pdata = { + .name = "sram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sram_dev = { + .name = "mem", + .map_base = 0xc8000000, + .size = 512 * 1024, /* Can be up to 2MiB */ + .platform_data = &sram_pdata, +}; + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 1, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = 0x1002b000, + .platform_data = &fec_info, +}; + +static int pcm038_spi_cs[] = {GPIO_PORTD + 28}; + +static struct spi_imx_master pcm038_spi_0_data = { + .chipselect = pcm038_spi_cs, + .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), +}; + +static struct device_d spi_dev = { + .name = "imx_spi", + .map_base = 0x1000e000, + .platform_data = &pcm038_spi_0_data, +}; + +static struct spi_board_info pcm038_spi_board_info[] = { + { + .name = "mc13783", + .max_speed_hz = 3000000, + .bus_num = 0, + .chip_select = 0, + } +}; + +static struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = 0xd8000000, + .platform_data = &nand_info, +}; + +static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "Sharp-LQ035Q7", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 188679, /* in ps (5.3MHz) */ + .hsync_len = 7, + .left_margin = 5, + .right_margin = 16, + .vsync_len = 1, + .upper_margin = 7, + .lower_margin = 9, + }, + /* + * - HSYNC active high + * - VSYNC active high + * - clk notenabled while idle + * - clock not inverted + * - data not inverted + * - data enable low active + * - enable sharp mode + */ + .pcr = 0xF00080C0, + .bpp = 16, +}; + +static struct imx_fb_platform_data pcm038_fb_data = { + .mode = &imxfb_mode, + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; + +static struct device_d imxfb_dev = { + .name = "imxfb", + .map_base = 0x10021000, + .size = 0x1000, + .platform_data = &pcm038_fb_data, +}; + +#ifdef CONFIG_USB +static struct device_d usbh2_dev = { + .name = "ehci", + .map_base = IMX_OTG_BASE + 0x400, + .size = 0x200, +}; + +static void pcm038_usbh_init(void) +{ + uint32_t temp; + + temp = readl(IMX_OTG_BASE + 0x600); + temp &= ~((3 << 21) | 1); + temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); + writel(temp, IMX_OTG_BASE + 0x600); + + temp = readl(IMX_OTG_BASE + 0x584); + temp &= ~(3 << 30); + temp |= 2 << 30; + writel(temp, IMX_OTG_BASE + 0x584); + + mdelay(10); + + isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x570), 1); +} +#endif + +#ifdef CONFIG_MMU +static void pcm038_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + mmu_enable(); +} +#else +static void pcm038_mmu_init(void) +{ +} +#endif + +static int pcm038_devices_init(void) +{ + int i; + char *envdev; + + unsigned int mode[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + PD25_PF_CSPI1_RDY, + GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT, + PD29_PF_CSPI1_SCLK, + PD30_PF_CSPI1_MISO, + PD31_PF_CSPI1_MOSI, + /* display */ + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA24_PF_REV, + PA25_PF_CLS, + PA26_PF_PS, + PA27_PF_SPL_SPR, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA30_PF_CONTRAST, + PA31_PF_OE_ACD, + /* USB host 2 */ + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, + }; + + pcm038_mmu_init(); + + /* configure 16 bit nor flash on cs0 */ + CS0U = 0x0000CC03; + CS0L = 0xa0330D01; + CS0A = 0x00220800; + + /* configure SRAM on cs1 */ + CS1U = 0x0000d843; + CS1L = 0x22252521; + CS1A = 0x22220a00; + + /* configure SJA1000 on cs4 */ + CS4U = 0x0000DCF6; + CS4L = 0x444A0301; + CS4A = 0x44443302; + + /* initizalize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + PCCR0 |= PCCR0_CSPI1_EN; + PCCR1 |= PCCR1_PERCLK2_EN; + + gpio_direction_output(GPIO_PORTD | 28, 0); + gpio_set_value(GPIO_PORTD | 28, 0); + spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); + register_device(&spi_dev); + + register_device(&cfi_dev); + register_device(&nand_dev); + register_device(&sdram_dev); + register_device(&sram_dev); + register_device(&imxfb_dev); + +#ifdef CONFIG_USB + pcm038_usbh_init(); + register_device(&usbh2_dev); +#endif + + /* Register the fec device after the PLL re-initialisation + * as the fec depends on the (now higher) ipg clock + */ + register_device(&fec_dev); + + switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) { + case GPCR_BOOT_8BIT_NAND_2k: + case GPCR_BOOT_16BIT_NAND_2k: + case GPCR_BOOT_16BIT_NAND_512: + case GPCR_BOOT_8BIT_NAND_512: + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + envdev = "NAND"; + break; + default: + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + + envdev = "NOR"; + } + + printf("Using environment in %s Flash\n", envdev); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0xa0000100); + armlinux_set_architecture(MACH_TYPE_PCM038); + + return 0; +} + +device_initcall(pcm038_devices_init); + +static struct device_d pcm038_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static int pcm038_console_init(void) +{ + /* bring PLLs to reset default */ + MPCTL0 = 0x00211803; + SPCTL0 = 0x1002700c; + CSCR = 0x33fc1307; + + register_device(&pcm038_serial_device); + + return 0; +} + +console_initcall(pcm038_console_init); + +extern void *pcm038_pll_init, *pcm038_pll_init_end; + +static int pcm038_power_init(void) +{ + int ret; + void *vram = 0xffff4c00; + void (*pllfunc)(void) = vram; + + printf("initialising PLLs: 0x%p 0x%p\n", &pcm038_pll_init); + + memcpy(vram, &pcm038_pll_init, 0x100); + + console_flush(); + + ret = pmic_power(); + if (ret) { + printf("Failed to initialize PMIC. Will continue with low CPU speed\n"); + return 0; + } + + /* wait for good power level */ + udelay(100000); + + pllfunc(); + + /* clock gating enable */ + GPCR = 0x00050f08; + + PCDR0 = 0x130410c3; + PCDR1 = 0x09030911; + + /* Clocks have changed. Notify clients */ + clock_notifier_call_chain(); + + return 0; +} + +late_initcall(pcm038_power_init); + diff --git a/arch/arm/boards/pcm038/pcm038.dox b/arch/arm/boards/pcm038/pcm038.dox new file mode 100644 index 0000000000..9b17674a21 --- /dev/null +++ b/arch/arm/boards/pcm038/pcm038.dox @@ -0,0 +1,8 @@ +/** @page pcm038 Phytec's phyCORE-i.MX27 + +This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with: + +- up to 32MiB NOR type Flash Memory +- 32MiB synchronous dynamic RAM + +*/ diff --git a/arch/arm/boards/pcm038/pll_init.S b/arch/arm/boards/pcm038/pll_init.S new file mode 100644 index 0000000000..0c1ff13415 --- /dev/null +++ b/arch/arm/boards/pcm038/pll_init.S @@ -0,0 +1,48 @@ +#include <config.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <linux/linkage.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define CSCR_VAL CSCR_USB_DIV(3) | \ + CSCR_SD_CNT(3) | \ + CSCR_MSHC_SEL | \ + CSCR_H264_SEL | \ + CSCR_SSI1_SEL | \ + CSCR_SSI2_SEL | \ + CSCR_MCU_SEL | \ + CSCR_ARM_SRC_MPLL | \ + CSCR_SP_SEL | \ + CSCR_ARM_DIV(0) | \ + CSCR_FPM_EN | \ + CSCR_SPEN | \ + CSCR_MPEN | \ + CSCR_AHB_DIV(1) + +ENTRY(pcm038_pll_init) + + writel(IMX_PLL_PD(0) | + IMX_PLL_MFD(51) | + IMX_PLL_MFI(7) | + IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */ + + writel(IMX_PLL_PD(1) | + IMX_PLL_MFD(12) | + IMX_PLL_MFI(9) | + IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ + + writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + + ldr r2, =16000 +1: + subs r2, r2, #1 + nop + bcs 1b + + mov pc, lr +ENDPROC(pcm038_pll_init) + diff --git a/arch/arm/boards/pcm043/Makefile b/arch/arm/boards/pcm043/Makefile new file mode 100644 index 0000000000..6753bbe81a --- /dev/null +++ b/arch/arm/boards/pcm043/Makefile @@ -0,0 +1,24 @@ +# +# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y += lowlevel.o +obj-y += pcm043.o diff --git a/arch/arm/boards/pcm043/config.h b/arch/arm/boards/pcm043/config.h new file mode 100644 index 0000000000..0e3b175a62 --- /dev/null +++ b/arch/arm/boards/pcm043/config.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Definitions related to passing arguments to kernel. + */ + +#define CONFIG_MX35_HCLK_FREQ 24000000 + +#endif + +/* nothing to do here yet */ diff --git a/arch/arm/boards/pcm043/env/config b/arch/arm/boards/pcm043/env/config new file mode 100644 index 0000000000..212b6a9cd8 --- /dev/null +++ b/arch/arm/boards/pcm043/env/config @@ -0,0 +1,58 @@ +#!/bin/sh + +machine=pcm043 +eth0.serverip= +user= + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net', 'nor' or 'nand' +kernel_loc=net +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root-$machine.$rootfs_type + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +kernelimage_type=zimage +kernelimage=zImage-$machine +#kernelimage_type=uimage +#kernelimage=uImage-$machine +#kernelimage_type=raw +#kernelimage=Image-$machine +#kernelimage_type=raw_lzo +#kernelimage=Image-$machine.lzo + +if [ -n $user ]; then + kernelimage="$user"-"$kernelimage" + nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine" + rootfsimage="$user"-"$rootfsimage" +else + nfsroot="$eth0.serverip:/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttymxc0,115200" + +bootargs="$bootargs video=mx3fb:CTP-CLAA070LC0ACW" + +nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nor=3 + +nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nand=7 + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c new file mode 100644 index 0000000000..9eff5a6713 --- /dev/null +++ b/arch/arm/boards/pcm043/lowlevel.c @@ -0,0 +1,214 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <init.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <mach/esdctl.h> +#include <asm/cache-l2x0.h> +#include <asm/io.h> +#include <mach/imx-nand.h> +#include <asm/barebox-arm.h> +#include <asm-generic/memory_layout.h> +#include <asm/system.h> + +/* Assuming 24MHz input clock */ +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) +#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) + +static void __bare_init __naked insdram(void) +{ + uint32_t r; + + /* Speed up NAND controller by adjusting the NFC divider */ + r = readl(IMX_CCM_BASE + CCM_PDR4); + r &= ~(0xf << 28); + r |= 0x1 << 28; + writel(r, IMX_CCM_BASE + CCM_PDR4); + + /* setup a stack to be able to call imx_nand_load_image() */ + r = STACK_BASE + STACK_SIZE - 12; + __asm__ __volatile__("mov sp, %0" : : "r"(r)); + + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); + + board_init_lowlevel_return(); +} + +void __bare_init __naked board_init_lowlevel(void) +{ + uint32_t r, s; + unsigned long ccm_base = IMX_CCM_BASE; + unsigned long iomuxc_base = IMX_IOMUXC_BASE; + unsigned int *trg, *src; + int i; + + r = get_cr(); + r |= CR_Z; /* Flow prediction (Z) */ + r |= CR_U; /* unaligned accesses */ + r |= CR_FI; /* Low Int Latency */ + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s)); + s |= 0x7; + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s)); + + set_cr(r); + + r = 0; + __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); + + /* + * Branch predicition is now enabled. Flush the BTAC to ensure a valid + * starting point. Don't flush BTAC while it is disabled to avoid + * ARM1136 erratum 408023. + */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r)); + + /* invalidate I cache and D cache */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r)); + + /* invalidate TLBs */ + __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r)); + + /* Drain the write buffer */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r)); + + /* Also setup the Peripheral Port Remap register inside the core */ + r = 0x40000015; /* start from AIPS 2GB region */ + __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); + + /* + * End of ARM1136 init + */ + + writel(0x003F4208, ccm_base + CCM_CCMR); + + /* Set MPLL , arm clock and ahb clock*/ + writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL); + + writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); + writel(0x00001000, ccm_base + CCM_PDR0); + + r = readl(ccm_base + CCM_CGR0); + r |= 0x00300000; + writel(r, ccm_base + CCM_CGR0); + + r = readl(ccm_base + CCM_CGR1); + r |= 0x00000C00; + r |= 0x00000003; + writel(r, ccm_base + CCM_CGR1); + + r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL); + r |= 0x1000; + writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0x80000000 && r < 0x90000000) + board_init_lowlevel_return(); + + /* Set DDR Type to SDRAM, drive strength workaround * + * 0x00000000 MDDR * + * 0x00000800 3,3V SDRAM */ + + r = 0x00000800; + writel(r, iomuxc_base + 0x794); + writel(r, iomuxc_base + 0x798); + writel(r, iomuxc_base + 0x79c); + writel(r, iomuxc_base + 0x7a0); + writel(r, iomuxc_base + 0x7a4); + + /* MDDR init, enable mDDR*/ + writel(0x00000304, ESDMISC); /* was 0x00000004 */ + + /* set timing paramters */ + writel(0x00255417, ESDCFG0); + /* select Precharge-All mode */ + writel(0x92220000, ESDCTL0); + /* Precharge-All */ + writel(0x12345678, IMX_SDRAM_CS0 + 0x400); + + /* select Load-Mode-Register mode */ + writel(0xB8001000, ESDCTL0); + /* Load reg EMR2 */ + writeb(0xda, 0x84000000); + /* Load reg EMR3 */ + writeb(0xda, 0x86000000); + /* Load reg EMR1 -- enable DLL */ + writeb(0xda, 0x82000400); + /* Load reg MR -- reset DLL */ + writeb(0xda, 0x80000333); + + /* select Precharge-All mode */ + writel(0x92220000, ESDCTL0); + /* Precharge-All */ + writel(0x12345678, IMX_SDRAM_CS0 + 0x400); + + /* select Manual-Refresh mode */ + writel(0xA2220000, ESDCTL0); + /* Manual-Refresh 2 times */ + writel(0x87654321, IMX_SDRAM_CS0); + writel(0x87654321, IMX_SDRAM_CS0); + + /* select Load-Mode-Register mode */ + writel(0xB2220000, ESDCTL0); + /* Load reg MR -- CL3, BL8, end DLL reset */ + writeb(0xda, 0x80000233); + /* Load reg EMR1 -- OCD default */ + writeb(0xda, 0x82000780); + /* Load reg EMR1 -- OCD exit */ + writeb(0xda, 0x82000400); + + /* select normal-operation mode + * DSIZ32-bit, BL8, COL10-bit, ROW13-bit + * disable PWT & PRCT + * disable Auto-Refresh */ + writel(0x82220080, ESDCTL0); + + /* enable Auto-Refresh */ + writel(0x82228080, ESDCTL0); + /* enable Auto-Refresh */ + writel(0x00002000, ESDCTL1); + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)IMX_NFC_BASE; + trg = (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ + for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ + r = (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} + diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c new file mode 100644 index 0000000000..dd178ed787 --- /dev/null +++ b/arch/arm/boards/pcm043/pcm043.c @@ -0,0 +1,392 @@ +/* + * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Board support for Phytec's, i.MX35 based CPU card, called: PCM043 + */ + +#include <common.h> +#include <command.h> +#include <init.h> +#include <driver.h> +#include <environment.h> +#include <fs.h> +#include <mach/imx-regs.h> +#include <asm/armlinux.h> +#include <mach/gpio.h> +#include <asm/io.h> +#include <partition.h> +#include <nand.h> +#include <asm/mach-types.h> +#include <mach/imx-nand.h> +#include <fec.h> +#include <fb.h> +#include <asm/mmu.h> +#include <mach/imx-ipu-fb.h> +#include <mach/imx-pll.h> +#include <mach/iomux-mx35.h> + +#define CYG_MACRO_START +#define CYG_MACRO_END +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) + +/* + * Up to 32MiB NOR type flash, connected to + * CS line 0, data width is 16 bit + */ +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = IMX_CS0_BASE, + .size = 32 * 1024 * 1024, /* area size */ +}; + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = IMX_FEC_BASE, + .platform_data = &fec_info, +}; + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram0_dev = { + .name = "mem", + .map_base = IMX_SDRAM_CS0, + .size = 128 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = IMX_NFC_BASE, + .platform_data = &nand_info, +}; + +#ifdef CONFIG_PCM043_DISPLAY_SHARP +static const struct fb_videomode pcm043_fb_mode = { + /* 240x320 @ 60 Hz */ + .name = "Sharp-LQ035Q7", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 185925, + .left_margin = 9, + .right_margin = 16, + .upper_margin = 7, + .lower_margin = 9, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; +#else +static const struct fb_videomode pcm043_fb_mode = { + /* 240x320 @ 60 Hz */ + .name = "TX090", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 38255, + .left_margin = 144, + .right_margin = 0, + .upper_margin = 7, + .lower_margin = 40, + .hsync_len = 96, + .vsync_len = 1, + .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; +#endif + +static struct imx_ipu_fb_platform_data ipu_fb_data = { + .mode = &pcm043_fb_mode, + .bpp = 16, +}; + +static struct device_d imx_ipu_fb_dev = { + .name = "imx-ipu-fb", + .map_base = 0x53fc0000, + .size = 0x1000, + .platform_data = &ipu_fb_data, +}; + +#ifdef CONFIG_MMU +static int pcm043_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + + mmu_enable(); + +#ifdef CONFIG_CACHE_L2X0 + l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); +#endif + return 0; +} +postcore_initcall(pcm043_mmu_init); +#endif + +static int imx35_devices_init(void) +{ + uint32_t reg; + + /* CS0: Nor Flash */ + writel(0x0000cf03, CSCR_U(0)); + writel(0x10000d03, CSCR_L(0)); + writel(0x00720900, CSCR_A(0)); + + reg = readl(IMX_CCM_BASE + CCM_RCSR); + /* some fuses provide us vital information about connected hardware */ + if (reg & 0x20000000) + nand_info.width = 2; /* 16 bit */ + else + nand_info.width = 1; /* 8 bit */ + + register_device(&fec_dev); + /* + * This platform supports NOR and NAND + */ + register_device(&nand_dev); + register_device(&cfi_dev); + + if ((reg & 0xc00) == 0x800) { /* reset mode: external boot */ + switch ( (reg >> 25) & 0x3) { + case 0x01: /* NAND is the source */ + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + break; + + case 0x00: /* NOR is the source */ + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); /* ourself */ + devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); /* environment */ + protect_file("/dev/env0", 1); + break; + } + } + + register_device(&sdram0_dev); + register_device(&imx_ipu_fb_dev); + + armlinux_add_dram(&sdram0_dev); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_PCM043); + + return 0; +} + +device_initcall(imx35_devices_init); + +static struct device_d imx35_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 16 * 1024, +}; + +static struct pad_desc pcm043_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + MX35_PAD_RXD1__UART1_RXD_MUX, + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RTS1__UART1_RTS, + MX35_PAD_CTS1__UART1_CTS, + MX35_PAD_I2C1_CLK__I2C1_SCL, + MX35_PAD_I2C1_DAT__I2C1_SDA +}; + +static int imx35_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); + + register_device(&imx35_serial_device); + return 0; +} + +console_initcall(imx35_console_init); + +static int pcm043_core_setup(void) +{ + u32 tmp; + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, IMX_AIPS1_BASE); + writel(0x77777777, IMX_AIPS1_BASE + 0x4); + writel(0x77777777, IMX_AIPS2_BASE); + writel(0x77777777, IMX_AIPS2_BASE + 0x4); + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + writel(0x0, IMX_AIPS1_BASE + 0x40); + writel(0x0, IMX_AIPS1_BASE + 0x44); + writel(0x0, IMX_AIPS1_BASE + 0x48); + writel(0x0, IMX_AIPS1_BASE + 0x4C); + tmp = readl(IMX_AIPS1_BASE + 0x50); + tmp &= 0x00FFFFFF; + writel(tmp, IMX_AIPS1_BASE + 0x50); + + writel(0x0, IMX_AIPS2_BASE + 0x40); + writel(0x0, IMX_AIPS2_BASE + 0x44); + writel(0x0, IMX_AIPS2_BASE + 0x48); + writel(0x0, IMX_AIPS2_BASE + 0x4C); + tmp = readl(IMX_AIPS2_BASE + 0x50); + tmp &= 0x00FFFFFF; + writel(tmp, IMX_AIPS2_BASE + 0x50); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup */ + + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_PARAM1 0x00302154 + writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ + writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + + /* SGPCR - always park on last master */ + writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ + writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ + writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ + writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ + writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + + /* MGPCR - restore default values */ + writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ + writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ + writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ + writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ + writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ + writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + + writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */ + writel(0x444A4541, CSCR_L(0)); + writel(0x44443302, CSCR_A(0)); + + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + writel(0x40, IMX_M3IF_BASE); + + return 0; +} + +core_initcall(pcm043_core_setup); + +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) + +static int do_cpufreq(struct command *cmdtp, int argc, char *argv[]) +{ + unsigned long freq; + + if (argc != 2) + return COMMAND_ERROR_USAGE; + + freq = simple_strtoul(argv[1], NULL, 0); + + switch (freq) { + case 399: + writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); + break; + case 532: + writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + break; + default: + return COMMAND_ERROR_USAGE; + } + + printf("Switched CPU frequency to %dMHz\n", freq); + + return 0; +} + +static const __maybe_unused char cmd_cpufreq_help[] = +"Usage: cpufreq 399|532\n" +"\n" +"Set CPU frequency to <freq> MHz\n"; + +BAREBOX_CMD_START(cpufreq) + .cmd = do_cpufreq, + .usage = "adjust CPU frequency", + BAREBOX_CMD_HELP(cmd_cpufreq_help) +BAREBOX_CMD_END + diff --git a/arch/arm/boards/pcm043/pcm043.dox b/arch/arm/boards/pcm043/pcm043.dox new file mode 100644 index 0000000000..c6715fffcf --- /dev/null +++ b/arch/arm/boards/pcm043/pcm043.dox @@ -0,0 +1,28 @@ +/** @page pcm043 Phytec's phyCORE-i.MX35 + +This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with: + + +FIXME: +- up to 64 MiB NOR type Flash Memory +- up to 2 MiB static RAM +- 1 GiB or 2 GiB NAND type Flash Memory + - Micron NAND 1 GiB 3,3V 8-bit + - 256 kiB block size + - ? kiB page size + - Manufacturer ID: 0x2c + - Device ID: 0xd3 + - Samsung K9K8G08, 1 GiB + - 128 kiB block size + - 2 kiB page size + - Manufacturer ID: ? + - Device ID: ? + - ST NAND08G, 1 GiB + - 128 kiB block size + - 2 kiB page size + - Manufacturer ID: ? + - Device ID: ? +- 128MiB synchronous dynamic RAM + + +*/ diff --git a/arch/arm/boards/phycard-i.MX27/Makefile b/arch/arm/boards/phycard-i.MX27/Makefile new file mode 100644 index 0000000000..fd52350fbb --- /dev/null +++ b/arch/arm/boards/phycard-i.MX27/Makefile @@ -0,0 +1,3 @@ + +obj-y += lowlevel_init.o +obj-y += pca100.o diff --git a/arch/arm/boards/phycard-i.MX27/config.h b/arch/arm/boards/phycard-i.MX27/config.h new file mode 100644 index 0000000000..c2f5e7cc58 --- /dev/null +++ b/arch/arm/boards/phycard-i.MX27/config.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Global defintions for the ARM i.MX27 based pcm038 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config new file mode 100644 index 0000000000..d0670dec2c --- /dev/null +++ b/arch/arm/boards/phycard-i.MX27/env/config @@ -0,0 +1,54 @@ +#!/bin/sh + +machine=pca100 +eth0.serverip= +user= + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net', 'nor' or 'nand' +kernel_loc=net +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root-$machine.$rootfs_type + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +kernelimage_type=zimage +kernelimage=zImage-$machine +#kernelimage_type=uimage +#kernelimage=uImage-$machine +#kernelimage_type=raw +#kernelimage=Image-$machine +#kernelimage_type=raw_lzo +#kernelimage=Image-$machine.lzo + +if [ -n $user ]; then + kernelimage="$user"-"$kernelimage" + nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine" + rootfsimage="$user"-"$rootfsimage" +else + nfsroot="$eth0.serverip:/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttymxc0,115200" + +nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" +rootfs_mtdblock_nand=7 + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + + diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S new file mode 100644 index 0000000000..9349581165 --- /dev/null +++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S @@ -0,0 +1,129 @@ +/* + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia + * Applications Processor Reference Manual, Rev. 0.2". + * + */ + +#include <config.h> +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + + +#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) + +.macro sdram_init + /* + * DDR on CSD0 + */ + writel(0x00000008, ESDMISC) /* Enable DDR SDRAM operation */ + + writel(0x55555555, DSCR(3)) /* Set the driving strength */ + writel(0x55555555, DSCR(5)) + writel(0x55555555, DSCR(6)) + writel(0x00005005, DSCR(7)) + writel(0x15555555, DSCR(8)) + + writel(0x00000004, ESDMISC) /* Initial reset */ + writel(0x006ac73a, ESDCFG0) + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */ + writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0) + + ldr r0, =0xa0000f00 + mov r1, #0 + mov r2, #8 +1: + str r1, [r0] + subs r2, #1 + bne 1b + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0) + ldr r0, =0xA0000033 + mov r1, #0xda + strb r1, [r0] + ldr r0, =0xA1000000 + mov r1, #0xff + strb r1, [r0] + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0) +.endm + + .section ".text_bare_init","ax" + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr + + /* ahb lite ip interface */ + writel(0x20040304, AIPI1_PSR0) + writel(0xDFFBFCFB, AIPI1_PSR1) + writel(0x00000000, AIPI2_PSR0) + writel(0xFFFFFFFF, AIPI2_PSR1) + + /* skip sdram initialization if we run from ram */ + cmp pc, #0xa0000000 + bls 1f + cmp pc, #0xc0000000 + bhi 1f + + mov pc,r10 + +1: + writel(IMX_PLL_PD(0) | + IMX_PLL_MFD(51) | + IMX_PLL_MFI(7) | + IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */ + + writel(IMX_PLL_PD(1) | + IMX_PLL_MFD(12) | + IMX_PLL_MFI(9) | + IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ + + writel(CSCR_MPLL_RESTART | CSCR_SPLL_RESTART | CSCR_ARM_SRC_MPLL | + CSCR_MCU_SEL | CSCR_SP_SEL | CSCR_FPM_EN | CSCR_MPEN | + CSCR_SPEN | CSCR_ARM_DIV(0) | CSCR_AHB_DIV(1) | CSCR_USB_DIV(3) | + CSCR_SD_CNT(3) | CSCR_SSI2_SEL | CSCR_SSI1_SEL | CSCR_H264_SEL | + CSCR_MSHC_SEL, CSCR) + + sdram_init + +#ifdef CONFIG_NAND_IMX_BOOT + ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */ + + ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ + ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + + /* skip NAND boot if not running from NFC space */ + cmp pc, r0 + bls ret + cmp pc, r2 + bhi ret + + /* Move ourselves out of NFC SRAM */ + ldr r1, =TEXT_BASE + +copy_loop: + ldmia r0!, {r3-r9} /* copy from source address [r0] */ + stmia r1!, {r3-r9} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + ldr pc, =1f /* Jump to SDRAM */ +1: + bl nand_boot /* Load barebox from NAND Flash */ + + ldr r1, =IMX_NFC_BASE - TEXT_BASE + sub r10, r10, r1 /* adjust return address from NFC SRAM */ + /* to SDRAM */ + +#endif /* CONFIG_NAND_IMX_BOOT */ + +ret: + mov pc,r10 + diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c new file mode 100644 index 0000000000..ce59960e22 --- /dev/null +++ b/arch/arm/boards/phycard-i.MX27/pca100.c @@ -0,0 +1,239 @@ + /* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <fec.h> +#include <mach/gpio.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <nand.h> +#include <spi/spi.h> +#include <asm/io.h> +#include <mach/imx-nand.h> +#include <mach/imx-pll.h> +#include <gpio.h> +#include <asm/mmu.h> +#include <usb/isp1504.h> +#include <mach/iomux-mx27.h> + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0xa0000000, + .size = 128 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 1, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = 0x1002b000, + .platform_data = &fec_info, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = 0xd8000000, + .platform_data = &nand_info, +}; + +#ifdef CONFIG_USB +static struct device_d usbh2_dev = { + .name = "ehci", + .map_base = IMX_OTG_BASE + 0x400, + .size = 0x200, +}; + +static void pca100_usbh_init(void) +{ + uint32_t temp; + + temp = readl(IMX_OTG_BASE + 0x600); + temp &= ~((3 << 21) | 1); + temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20); + writel(temp, IMX_OTG_BASE + 0x600); + + temp = readl(IMX_OTG_BASE + 0x584); + temp &= ~(3 << 30); + temp |= 2 << 30; + writel(temp, IMX_OTG_BASE + 0x584); + + mdelay(10); + + gpio_direction_output(GPIO_PORTB + 24, 0); + + mdelay(10); + + isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x570), 1); +} +#endif + +#ifdef CONFIG_MMU +static void pca100_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + mmu_enable(); +} +#else +static void pca100_mmu_init(void) +{ +} +#endif + +static int pca100_devices_init(void) +{ + int i; + struct device_d *nand; + + unsigned int mode[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + PD25_PF_CSPI1_RDY, + PD26_PF_CSPI1_SS2, + PD27_PF_CSPI1_SS1, + PD28_PF_CSPI1_SS0, + PD29_PF_CSPI1_SCLK, + PD30_PF_CSPI1_MISO, + PD31_PF_CSPI1_MOSI, + /* USB host 2 */ + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, + }; + + /* disable the usb phys */ + imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN); + gpio_direction_output(GPIO_PORTB + 23, 1); + imx_gpio_mode((GPIO_PORTB | 24) | GPIO_GPIO | GPIO_IN); + gpio_direction_output(GPIO_PORTB + 24, 1); + + /* initizalize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + register_device(&nand_dev); + register_device(&sdram_dev); + register_device(&fec_dev); + + PCCR1 |= PCCR1_PERCLK2_EN; + +#ifdef CONFIG_USB + pca100_usbh_init(); + register_device(&usbh2_dev); +#endif + + nand = get_device_by_name("nand0"); + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0xa0000100); + armlinux_set_architecture(2149); + + return 0; +} + +device_initcall(pca100_devices_init); + +static struct device_d pca100_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static int pca100_console_init(void) +{ + pca100_mmu_init(); + register_device(&pca100_serial_device); + return 0; +} + +console_initcall(pca100_console_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif + diff --git a/arch/arm/boards/phycard-i.MX27/pca100.dox b/arch/arm/boards/phycard-i.MX27/pca100.dox new file mode 100644 index 0000000000..9b17674a21 --- /dev/null +++ b/arch/arm/boards/phycard-i.MX27/pca100.dox @@ -0,0 +1,8 @@ +/** @page pcm038 Phytec's phyCORE-i.MX27 + +This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with: + +- up to 32MiB NOR type Flash Memory +- 32MiB synchronous dynamic RAM + +*/ diff --git a/arch/arm/boards/pm9263/Makefile b/arch/arm/boards/pm9263/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/pm9263/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/pm9263/config.h b/arch/arm/boards/pm9263/config.h new file mode 100644 index 0000000000..9a9c5cdcb7 --- /dev/null +++ b/arch/arm/boards/pm9263/config.h @@ -0,0 +1,126 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */ + +#define MASTER_PLL_DIV 6 +#define MASTER_PLL_MUL 65 +#define MAIN_PLL_DIV 2 /* 2 or 4 */ + +/* clocks */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + AT91_PMC_PLLCOUNT | /* PLL Counter */ \ + (2 << 28) | /* PLL Clock Frequency Range */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +#if (MAIN_PLL_DIV == 2) +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +#else +/* PCK/4 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91RM9200_PMC_MDIV_3 | \ + AT91_PMC_PDIV_1) +/* PCK/4 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91RM9200_PMC_MDIV_3 | \ + AT91_PMC_PDIV_1) +#endif +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ + AT91_MATRIX_EBI0_CS1A_SDRAMC) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 0 +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* tWR - Write Recovery Delay */ \ + (7 << 12) | /* tRC - Row Cycle Delay */ \ + (2 << 16) | /* tRP - Row Precharge Delay */ \ + (2 << 20) | /* tRCD - Row to Column Delay */ \ + (5 << 24) | /* tRAS - Active to Precharge Delay */ \ + (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) + + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/pm9263/env/bin/_update b/arch/arm/boards/pm9263/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/pm9263/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/pm9263/env/bin/boot b/arch/arm/boards/pm9263/env/bin/boot new file mode 100644 index 0000000000..533dea7618 --- /dev/null +++ b/arch/arm/boards/pm9263/env/bin/boot @@ -0,0 +1,47 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$1 = xnor ]; then + root=nor + kernel=nor +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +elif [ x$root = xnor ]; then + bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +elif [ $kernel = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/pm9263/env/bin/hush_hack b/arch/arm/boards/pm9263/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/pm9263/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/pm9263/env/bin/init b/arch/arm/boards/pm9263/env/bin/init new file mode 100644 index 0000000000..02f5cd415b --- /dev/null +++ b/arch/arm/boards/pm9263/env/bin/init @@ -0,0 +1,37 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nor [<imagename>] to update kernel into flash" + echo "type update_root nor [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/pm9263/env/bin/update_kernel b/arch/arm/boards/pm9263/env/bin/update_kernel new file mode 100644 index 0000000000..05c822d860 --- /dev/null +++ b/arch/arm/boards/pm9263/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/pm9263/env/bin/update_root b/arch/arm/boards/pm9263/env/bin/update_root new file mode 100644 index 0000000000..a75137237b --- /dev/null +++ b/arch/arm/boards/pm9263/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/pm9263/env/config b/arch/arm/boards/pm9263/env/config new file mode 100644 index 0000000000..75132911c4 --- /dev/null +++ b/arch/arm/boards/pm9263/env/config @@ -0,0 +1,28 @@ +#!/bin/sh + +# can be either 'net', 'nor' or 'nand'' +kernel=net +root=net + +uimage=uImage-PM9263 +jffs2=root-PM9263.jffs2 + +autoboot_timeout=3 + +nfsroot="/ptx/work/octopus/mkl/bucyrus/OSELAS.BSP-Bucyrus-Grabowski-trunk/platform-Ronetix-PM9263/root" +bootargs="console=ttyS0,115200" + +nor_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +rootpart_nor="/dev/mtdblock3" + +#nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +#rootpart_nand="/dev/mtdblock7" + +# use 'dhcp' to do dhcp in barebox and in kernel +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +eth0.serverip=192.168.23.1 diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c new file mode 100644 index 0000000000..88b91eafa9 --- /dev/null +++ b/arch/arm/boards/pm9263/init.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <fec.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <linux/mtd/nand.h> +#include <mach/at91_pmc.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> +#include <mach/at91sam9_smc.h> +#include <mach/sam9_smc.h> + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, +/* .det_pin = ... not connected */ + .ecc_base = (void __iomem *)(AT91_BASE_SYS + AT91_ECC0), + .ecc_mode = NAND_ECC_HW, + .rdy_pin = AT91_PIN_PB30, + .enable_pin = AT91_PIN_PD15, +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + +static struct sam9_smc_config pm_nand_smc_config = { + .ncs_read_setup = 1, + .nrd_setup = 1, + .ncs_write_setup = 1, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 2, +}; + +static void pm_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + pm_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + pm_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &pm_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = AT91_CHIPSELECT_0, + .size = 4 * 1024 * 1024, +}; + +static struct at91_ether_platform_data macb_pdata = { + .flags = AT91SAM_ETHER_RMII, + .phy_addr = 0, +}; + +static int pm9263_devices_init(void) +{ + /* + * PB27 enables the 50MHz oscillator for Ethernet PHY + * 1 - enable + * 0 - disable + */ + at91_set_gpio_output(AT91_PIN_PB27, 1); + at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + + at91_add_device_sdram(64 * 1024 * 1024); + pm_add_device_nand(); + at91_add_device_eth(&macb_pdata); + register_device(&cfi_dev); + + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0"); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + armlinux_set_architecture(MACH_TYPE_PM9263); + + return 0; +} + +device_initcall(pm9263_devices_init); + +static int pm9263_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} + +console_initcall(pm9263_console_init); diff --git a/arch/arm/boards/scb9328/Makefile b/arch/arm/boards/scb9328/Makefile new file mode 100644 index 0000000000..db6fd7ec37 --- /dev/null +++ b/arch/arm/boards/scb9328/Makefile @@ -0,0 +1,3 @@ + +obj-y += lowlevel_init.o +obj-y += scb9328.o diff --git a/arch/arm/boards/scb9328/config.h b/arch/arm/boards/scb9328/config.h new file mode 100644 index 0000000000..cc22b7ae72 --- /dev/null +++ b/arch/arm/boards/scb9328/config.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli <peposh@etc.sk>, 2003. + * + * 2003/13/06 Initial MP10 Support copied from wepep250 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYSPLL_CLK_FREQ 16000000 + +#endif /* __CONFIG_H */ + diff --git a/arch/arm/boards/scb9328/env/bin/init b/arch/arm/boards/scb9328/env/bin/init new file mode 100644 index 0000000000..416669f851 --- /dev/null +++ b/arch/arm/boards/scb9328/env/bin/init @@ -0,0 +1,3 @@ + +echo running init + diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S new file mode 100644 index 0000000000..5b024286bb --- /dev/null +++ b/arch/arm/boards/scb9328/lowlevel_init.S @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + * 02111-1307, USA. + * + */ + +#include <mach/imx-regs.h> + +#define CPU200 + +#ifdef CPU200 +#define CFG_MPCTL0_VAL 0x00321431 +#else +#define CFG_MPCTL0_VAL 0x040e200e +#endif + +#define BUS72 + +#ifdef BUS72 +#define CFG_SPCTL0_VAL 0x04002400 +#endif + +#ifdef BUS96 +#define CFG_SPCTL0_VAL 0x04001800 +#endif + +#ifdef BUS64 +#define CFG_SPCTL0_VAL 0x08001800 +#endif + +/* Das ist der BCLK Divider, der aus der System PLL + BCLK und HCLK erzeugt: + 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 + 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 + 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 + 0x2f001003 : 192MHz/5=38,4MHz + 0x2f000003 : 64MHz/1 + Bit 22: SPLL Restart + Bit 21: MPLL Restart */ + +#ifdef BUS64 +#define CFG_CSCR_VAL 0x2f030003 +#endif + +#ifdef BUS72 +#define CFG_CSCR_VAL 0x2f030403 +#endif +/* Bit[0:3] contain PERCLK1DIV for UART 1 + 0x000b00b ->b<- -> 192MHz/12=16MHz + 0x000b00b ->8<- -> 144MHz/09=16MHz + 0x000b00b ->3<- -> 64MHz/4=16MHz */ + +#ifdef BUS96 +#define CFG_PCDR_VAL 0x000b00b5 +#endif + +#ifdef BUS64 +#define CFG_PCDR_VAL 0x000b00b3 +#endif + +#ifdef BUS72 +#define CFG_PCDR_VAL 0x000b00b8 +#endif + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr + + /* Change PERCLK1DIV to 14 ie 14+1 */ + writel(CFG_PCDR_VAL, PCDR) + + /* set MCU PLL Control Register 0 */ + writel(CFG_MPCTL0_VAL, MPCTL0) + + /* set mpll restart bit */ + ldr r0, =CSCR + ldr r1, [r0] + orr r1,r1,#(1<<21) + str r1, [r0] + + mov r2,#0x10 +1: + mov r3,#0x2000 +2: + subs r3,r3,#1 + bne 2b + + subs r2,r2,#1 + bne 1b + + /* set System PLL Control Register 0 */ + writel(CFG_SPCTL0_VAL, SPCTL0) + + /* set spll restart bit */ + ldr r0, =CSCR + ldr r1, [r0] + orr r1,r1,#(1<<22) + str r1, [r0] + + mov r2,#0x10 +1: + mov r3,#0x2000 +2: + subs r3,r3,#1 + bne 2b + + subs r2,r2,#1 + bne 1b + + writel(CFG_CSCR_VAL, CSCR) + +/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon + *this..... + * + * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 + * register 1, this stops it using the output of the PLL and thus runs at the + * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never + * use the value set in the CM_OSC registers...regardless of what you set it + * too! Thus, although i thought i was running at 140MHz, i'm actually running + * at 40!.. + + * Slapping this into my bootloader does the trick... + + * MRC p15,0,r0,c1,c0,0 ; read core configuration register + * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode + * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration + * register + */ + MRC p15,0,r0,c1,c0,0 + ORR r0,r0,#0xC0000000 + MCR p15,0,r0,c1,c0,0 + + /* Skip SDRAM initialization if we run from RAM */ + cmp pc, #0x08000000 + bls 1f + cmp pc, #0x09000000 + bhi 1f + + mov pc,r10 + +1: + +/* SDRAM Setup */ + + writel(0x910a8200, SDCTL0) /* Precharge cmd, CAS = 2 */ + writel(0x0, 0x08200000) /* Issue Precharge all Command */ + writel(0xa10a8200, SDCTL0) /* Autorefresh cmd, CAS = 2 */ + + ldr r0, =0x08000000 + ldr r1, =0x0 /* Issue AutoRefresh Command */ + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + + writel(0xb10a8300, SDCTL0) + writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */ + writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */ + + mov pc,r10 diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c new file mode 100644 index 0000000000..e781393eae --- /dev/null +++ b/arch/arm/boards/scb9328/scb9328.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <asm/mach-types.h> +#include <mach/imx-regs.h> +#include <asm/armlinux.h> +#include <mach/gpio.h> +#include <asm/io.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <dm9000.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + + .map_base = 0x10000000, + .size = 16 * 1024 * 1024, +}; + +static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0x08000000, + .size = 16 * 1024 * 1024, + .platform_data = &sdram_pdata, +}; + +static struct dm9000_platform_data dm9000_data = { + .iobase = 0x16000000, + .iodata = 0x16000004, + .buswidth = DM9000_WIDTH_16, +}; + +static struct device_d dm9000_dev = { + .name = "dm9000", + .map_base = 0x16000000, + .size = 8, + .platform_data = &dm9000_data, +}; + +static int scb9328_devices_init(void) { + + imx_gpio_mode(PA23_PF_CS5); + +/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ + FMCR = 0x1; + + CS0U = 0x000F2000; + CS0L = 0x11110d01; + + CS1U = 0x000F0a00; + CS1L = 0x11110601; + CS2U = 0x0; + CS2L = 0x0; + CS3U = 0x000FFFFF; + CS3L = 0x00000303; + CS4U = 0x000F0a00; + CS4L = 0x11110301; + CS5U = 0x00008400; + CS5L = 0x00000D03; + + register_device(&cfi_dev); + register_device(&sdram_dev); + register_device(&dm9000_dev); + + devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0x08000100); + armlinux_set_architecture(MACH_TYPE_SCB9328); + + return 0; +} + +device_initcall(scb9328_devices_init); + +static struct device_d scb9328_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static int scb9328_console_init(void) +{ + /* init gpios for serial port */ + imx_gpio_mode(PC11_PF_UART1_TXD); + imx_gpio_mode(PC12_PF_UART1_RXD); + + register_device(&scb9328_serial_device); + return 0; +} + +console_initcall(scb9328_console_init); + diff --git a/arch/arm/boards/scb9328/scb9328.dox b/arch/arm/boards/scb9328/scb9328.dox new file mode 100644 index 0000000000..75bc7c8c1a --- /dev/null +++ b/arch/arm/boards/scb9328/scb9328.dox @@ -0,0 +1,9 @@ +/** @page scb9328 Synertronixx's scb9328 + +This CPU card is based on a Freescale i.MX1 CPU. The card is shipped with: + +- up to 16MiB NOR type Flash Memory +- 16MiB synchronous dynamic RAM +- DM9000 network controller + +*/ diff --git a/arch/arm/configs/a9m2410_defconfig b/arch/arm/configs/a9m2410_defconfig index 9429a3763d..9e888fc6b9 100644 --- a/arch/arm/configs/a9m2410_defconfig +++ b/arch/arm/configs/a9m2410_defconfig @@ -100,7 +100,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/a9m2410/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/a9m2410/env" # # Debugging diff --git a/arch/arm/configs/a9m2440_defconfig b/arch/arm/configs/a9m2440_defconfig index 1fcabbb62e..f69dcfd76a 100644 --- a/arch/arm/configs/a9m2440_defconfig +++ b/arch/arm/configs/a9m2440_defconfig @@ -101,7 +101,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/a9m2440/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/a9m2440/env" # # Debugging diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig index 61df756932..b40485b46f 100644 --- a/arch/arm/configs/at91sam9260ek_defconfig +++ b/arch/arm/configs/at91sam9260ek_defconfig @@ -89,7 +89,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/at91sam9260ek/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9260ek/env" # # Debugging diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig index eb47856b05..d423c2fdfd 100644 --- a/arch/arm/configs/at91sam9263ek_defconfig +++ b/arch/arm/configs/at91sam9263ek_defconfig @@ -93,7 +93,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/at91sam9263ek/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9263ek/env" # # Debugging diff --git a/arch/arm/configs/edb93xx_defconfig b/arch/arm/configs/edb93xx_defconfig index d6b4b19f14..d8fe23f70f 100644 --- a/arch/arm/configs/edb93xx_defconfig +++ b/arch/arm/configs/edb93xx_defconfig @@ -103,7 +103,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/edb93xx/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/edb93xx/env" # # Debugging diff --git a/arch/arm/configs/eukrea_cpuimx25_defconfig b/arch/arm/configs/eukrea_cpuimx25_defconfig index 574d32292d..88f61c7826 100644 --- a/arch/arm/configs/eukrea_cpuimx25_defconfig +++ b/arch/arm/configs/eukrea_cpuimx25_defconfig @@ -108,7 +108,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/eukrea_cpuimx25/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx25/env" # # Debugging diff --git a/arch/arm/configs/eukrea_cpuimx27_defconfig b/arch/arm/configs/eukrea_cpuimx27_defconfig index a1cf1adb74..c7f6b78db0 100644 --- a/arch/arm/configs/eukrea_cpuimx27_defconfig +++ b/arch/arm/configs/eukrea_cpuimx27_defconfig @@ -118,7 +118,7 @@ CONFIG_CONSOLE_ACTIVATE_ALL=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/eukrea_cpuimx27/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx27/env" # # Debugging diff --git a/arch/arm/configs/freescale_mx25_3stack_defconfig b/arch/arm/configs/freescale_mx25_3stack_defconfig index d308e5bf01..fd7dd4273c 100644 --- a/arch/arm/configs/freescale_mx25_3stack_defconfig +++ b/arch/arm/configs/freescale_mx25_3stack_defconfig @@ -106,7 +106,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/freescale-mx25-3-stack/env/" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx25-3-stack/env/" # # Debugging diff --git a/arch/arm/configs/freescale_mx35_3stack_defconfig b/arch/arm/configs/freescale_mx35_3stack_defconfig index 17a2fdc6d9..4321fbce09 100644 --- a/arch/arm/configs/freescale_mx35_3stack_defconfig +++ b/arch/arm/configs/freescale_mx35_3stack_defconfig @@ -105,7 +105,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/freescale-mx35-3-stack/env/" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx35-3-stack/env/" # # Debugging diff --git a/arch/arm/configs/mmccpu_defconfig b/arch/arm/configs/mmccpu_defconfig index 2b80a30a59..a8c41e7878 100644 --- a/arch/arm/configs/mmccpu_defconfig +++ b/arch/arm/configs/mmccpu_defconfig @@ -93,7 +93,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/mmccpu/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/mmccpu/env" # # Debugging diff --git a/arch/arm/configs/mx21ads_defconfig b/arch/arm/configs/mx21ads_defconfig index 99a87143ec..99b5ed6aa4 100644 --- a/arch/arm/configs/mx21ads_defconfig +++ b/arch/arm/configs/mx21ads_defconfig @@ -104,7 +104,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/imx21ads/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/imx21ads/env" # # Debugging diff --git a/arch/arm/configs/mx27ads_defconfig b/arch/arm/configs/mx27ads_defconfig index 71880c0b76..a1bf3f9412 100644 --- a/arch/arm/configs/mx27ads_defconfig +++ b/arch/arm/configs/mx27ads_defconfig @@ -108,7 +108,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/imx27ads/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/imx27ads/env" # # Debugging diff --git a/arch/arm/configs/pca100_defconfig b/arch/arm/configs/pca100_defconfig index 52a5d93bb5..62beefab32 100644 --- a/arch/arm/configs/pca100_defconfig +++ b/arch/arm/configs/pca100_defconfig @@ -110,7 +110,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv board/phycard-i.MX27/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/phycard-i.MX27/env" # # Debugging diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig index 9353d0e546..9337f8579b 100644 --- a/arch/arm/configs/pcm037_defconfig +++ b/arch/arm/configs/pcm037_defconfig @@ -106,7 +106,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv board/pcm037/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/pcm037/env" # # Debugging diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig index a80089cd4f..65ecb0763d 100644 --- a/arch/arm/configs/pcm038_defconfig +++ b/arch/arm/configs/pcm038_defconfig @@ -110,7 +110,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv board/pcm038/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/pcm038/env" # # Debugging diff --git a/arch/arm/configs/pcm043_defconfig b/arch/arm/configs/pcm043_defconfig index 72a8a4291f..482e580dad 100644 --- a/arch/arm/configs/pcm043_defconfig +++ b/arch/arm/configs/pcm043_defconfig @@ -109,7 +109,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv board/pcm043/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/pcm043/env" # # Debugging diff --git a/arch/arm/configs/pm9263_defconfig b/arch/arm/configs/pm9263_defconfig index cde5cbe66e..d5ee46a6f2 100644 --- a/arch/arm/configs/pm9263_defconfig +++ b/arch/arm/configs/pm9263_defconfig @@ -93,7 +93,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/pm9263/env/" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pm9263/env/" # # Debugging diff --git a/arch/arm/configs/scb9328_defconfig b/arch/arm/configs/scb9328_defconfig index 6638234be3..7dc56dd855 100644 --- a/arch/arm/configs/scb9328_defconfig +++ b/arch/arm/configs/scb9328_defconfig @@ -105,7 +105,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set # CONFIG_PARTITION is not set CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/scb9328/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/scb9328/env" # # Debugging diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h index 5f0bb73413..7bb1af1606 100644 --- a/arch/arm/include/asm/barebox-arm.h +++ b/arch/arm/include/asm/barebox-arm.h @@ -32,7 +32,7 @@ /* cpu/.../cpu.c */ int cleanup_before_linux(void); -/* board/.../... */ +/* arch/<arch>board(s)/.../... */ int board_init(void); int dram_init (void); diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index e5230802ec..158639ec59 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -83,6 +83,6 @@ config GPMC NAND, OneNAND etc. # Get the board specific configurations -source board/omap/Kconfig +source arch/arm/boards/omap/Kconfig endmenu diff --git a/arch/arm/mach-omap/arch-omap.dox b/arch/arm/mach-omap/arch-omap.dox index 01e45f291e..df16b7be96 100644 --- a/arch/arm/mach-omap/arch-omap.dox +++ b/arch/arm/mach-omap/arch-omap.dox @@ -39,7 +39,7 @@ Motivation for code organization is driven from: Code is Organized into three main directories: @li arch/arm/mach-omap -contains files for ALL peripherals which are present on board with very few exceptions. We will come to these exceptions in later sections. @li include/asm-arm/arch-omap - contains files for ALL OMAP on-silicon peripherals. No Board specific files here please! -@li board/omap - contains files for ALL boards using OMAP processors. +@li arch/arm/boards/omap - contains files for ALL boards using OMAP processors. @section mach_omap arch/arm/mach-omap directory guidelines It is rather simple: All common peripherals should be isolated as separate driver libraries as far as possible. Exceptions such as clock configuration code may be isolated by the following naming convention: omapX_function_name.[cS], where X belongs to the OMAP variant. The exception is for devices who have existing code locations - potentially drivers/i2c/busses and the like. @@ -52,7 +52,7 @@ All OMAP common headers are located here. Where we have to incorporate a OMAP va include/asm-arm/arch-omap/silicon.h contains includes for omapX-silicon.h which defines the base addresses for the peripherals on that platform. the usual convention is to use #define OMAP_SOMETHING_BASE to allow re-use. -@section board_omap board/omap directory guidelines +@section board_omap arch/arm/boards/omap directory guidelines All Board specific files go here. In u-boot, we always had to use common config file which is shared by other drivers to get serial, ethernet baseaddress etc.. we can easily use the device_d structure to handle it with @a barebox. This is more like programming for Linux kernel - it is pretty easy. Each specific board file has board-XYZ.c and potentially and equivalent h file. @@ -66,7 +66,7 @@ The responsibility of arch_init_lowlevel and related calls is to setup OMAP. No Once this is past, the code returns back to arm common code (cpu/start-arm.S). Here Instruction and Data caches are disabled. The execution proceeds to normal board initialization. @section board_boot The board boot path -If the proper CONFIG_MACH_DO_LOWLEVEL_INIT flag is setup, board_init_lowlevel is called. This again would call a common file board/omap/platform.S which setups a temporary SRAM stack and bumps the control to board_init. +If the proper CONFIG_MACH_DO_LOWLEVEL_INIT flag is setup, board_init_lowlevel is called. This again would call a common file arch/arm/boards/omap/platform.S which setups a temporary SRAM stack and bumps the control to board_init. Every Board in OMAP platform can potentially define a board_init and enable defconfig in arch/arm/configs directory. The responsibility here is to setup OMAP for board configurations - this includes SDRAM configuration and pin muxing configuration. Once this is complete, @a barebox boot process proceeds by calling init functions and finally entering shell prompt @@ -87,7 +87,7 @@ static int my_board_devices_init(void) { device_initcall(my_board_devices_init); @endcode -You may probably be interested in calling console_initcall to get a console.. Modify board/omap/Kconfig to add your OMAP board, create a defconfig, do a make C=2 to enable sparse warnings, you can potentially have a binary done in no time! if you remember to put doxygen comments in your code, you can do a make docs and get the documentation done too.. +You may probably be interested in calling console_initcall to get a console.. Modify arch/arm/boards/omap/Kconfig to add your OMAP board, create a defconfig, do a make C=2 to enable sparse warnings, you can potentially have a binary done in no time! if you remember to put doxygen comments in your code, you can do a make docs and get the documentation done too.. */ diff --git a/arch/arm/mach-s3c24xx/generic.c b/arch/arm/mach-s3c24xx/generic.c index 372904f89d..46b5c50d5b 100644 --- a/arch/arm/mach-s3c24xx/generic.c +++ b/arch/arm/mach-s3c24xx/generic.c @@ -244,8 +244,8 @@ EXPORT_SYMBOL(reset_cpu); @section s3c24xx_boards Boards using S3C24xx Processors -@li @subpage board/a9m2410/a9m2410.c -@li @subpage board/a9m2440/a9m2440.c +@li @subpage arch/arm/boards/a9m2410/a9m2410.c +@li @subpage arch/arm/boards/a9m2440/a9m2440.c @section s3c24xx_arch Documentation for S3C24xx Architectures Files diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index dbb90814f9..902268da70 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -22,7 +22,7 @@ PHONY += maketools ifneq ($(board-y),) -BOARD := board/$(board-y)/ +BOARD := arch/blackfin/boards/$(board-y)/ else BOARD := endif diff --git a/arch/blackfin/boards/ipe337/Makefile b/arch/blackfin/boards/ipe337/Makefile new file mode 100644 index 0000000000..172dfb688c --- /dev/null +++ b/arch/blackfin/boards/ipe337/Makefile @@ -0,0 +1,4 @@ +obj-y += ipe337.o +obj-y += cmd_alternate.o + +extra-y += barebox.lds diff --git a/arch/blackfin/boards/ipe337/barebox.lds.S b/arch/blackfin/boards/ipe337/barebox.lds.S new file mode 100644 index 0000000000..4299b8208b --- /dev/null +++ b/arch/blackfin/boards/ipe337/barebox.lds.S @@ -0,0 +1,87 @@ +/* + * barebox - barebox.lds.S + * + * Copyright (c) 2005-2007 Analog Device Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm-generic/barebox.lds.h> + +OUTPUT_ARCH("bfin") +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +/* +MEMORY +{ + ram : ORIGIN = (0x2000000), LENGTH = (256 * 1024) + l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000 + l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000 +} +*/ + +SECTIONS +{ + . = TEXT_BASE; + + . = ALIGN(4); + .text : + { + __stext = .; + __text = .; + _text = .; + *(.text_entry) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + __etext = .; /* End of text and rodata section */ + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + ___barebox_cmd_start = .; + .barebox_cmd : { BAREBOX_CMDS } + ___barebox_cmd_end = .; + + ___barebox_initcalls_start = .; + .barebox_initcalls : { INITCALLS } + ___barebox_initcalls_end = .; + + ___usymtab_start = .; + __usymtab : { BAREBOX_SYMS } + ___usymtab_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} + diff --git a/arch/blackfin/boards/ipe337/cmd_alternate.c b/arch/blackfin/boards/ipe337/cmd_alternate.c new file mode 100644 index 0000000000..2883c77d32 --- /dev/null +++ b/arch/blackfin/boards/ipe337/cmd_alternate.c @@ -0,0 +1,56 @@ +#include <common.h> +#include <command.h> +#include <linux/stat.h> +#include <malloc.h> +#include <fs.h> + +#define MAGIC 0x19691228 + +static int do_alternate(struct command *cmdtp, int argc, char *argv[]) +{ + void *buf; + size_t size; + ulong *ptr, val = 0, bitcount = 0; + + if (argc != 2) + return COMMAND_ERROR_USAGE; + + buf = read_file(argv[1], &size); + if (!buf) + return 1; + + ptr = buf; + if ((*ptr) != MAGIC) { + printf("Wrong magic! Expected 0x%08x, got 0x%08x.\n", MAGIC, *ptr); + return 1; + } + + ptr++; + + while ((ulong)ptr <= (ulong)buf + size && !(val = *ptr++)) + bitcount += 32; + + if (val) { + do { + if (val & 1) + break; + bitcount++; + } while (val >>= 1); + } + + printf("Bitcount : %d\n", bitcount); + + free(buf); + return (bitcount & 1) ? 3 : 2; +} + +static const __maybe_unused char cmd_alternate_help[] = +"Usage: alternate <file>" +"\n"; + +BAREBOX_CMD_START(alternate) + .cmd = do_alternate, + .usage = "count zero bits in a file", + BAREBOX_CMD_HELP(cmd_alternate_help) +BAREBOX_CMD_END + diff --git a/arch/blackfin/boards/ipe337/config.h b/arch/blackfin/boards/ipe337/config.h new file mode 100644 index 0000000000..aa25d0792d --- /dev/null +++ b/arch/blackfin/boards/ipe337/config.h @@ -0,0 +1,46 @@ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Clock settings + */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#if defined(CONFIG_MACH_IPE337_V1) +#define CONFIG_CLKIN_HZ 25000000 +#elif defined(CONFIG_MACH_IPE337_V2) +#define CONFIG_CLKIN_HZ 40000000 +#else +#error "Unknown IPE337 revision" +#endif + +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 10 /* POR default */ +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 /* POR default */ +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 /* POR default */ + +/* Frequencies selected: 400MHz CCLK / 80MHz SCLK ^= 12.5ns cycle time*/ + +#define AMGCTLVAL 0x1F + +/* no need for speed, currently, leave at defaults */ +#define AMBCTL0VAL 0xFFC2FFC2 +#define AMBCTL1VAL 0xFFC2FFC2 + +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ + +#endif /* __CONFIG_H */ diff --git a/arch/blackfin/boards/ipe337/env/bin/_alternate b/arch/blackfin/boards/ipe337/env/bin/_alternate new file mode 100644 index 0000000000..10ae2134c0 --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/_alternate @@ -0,0 +1,9 @@ +#!/bin/sh + +. /env/config + +alternate $ageing +if [ $? -lt 2 ]; then + echo "Error when accesing ageing-partition!" + exit 1 +fi diff --git a/arch/blackfin/boards/ipe337/env/bin/_update b/arch/blackfin/boards/ipe337/env/bin/_update new file mode 100644 index 0000000000..5419ece6a7 --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/_update @@ -0,0 +1,37 @@ +#!/bin/sh + +if [ $# = 1 ]; then + image=$1 +fi + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "Erasing partition $part" +erase $part + +echo +echo "Flashing $image to $part" +tftp $image $part + +protect $part diff --git a/arch/blackfin/boards/ipe337/env/bin/boot b/arch/blackfin/boards/ipe337/env/bin/boot new file mode 100644 index 0000000000..62807d211f --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/boot @@ -0,0 +1,54 @@ +#!/bin/sh + +. /env/config + +alternate $ageing +ret=$? + +if [ $ret = 0 ]; then + echo "Error when accesing ageing-partition!" + exit 1 +elif [ $ret = 2 ]; then + act_kernel=/dev/nor0.kernel0 + act_rootfs=/dev/mtdblock5 +else + act_kernel=/dev/nor0.kernel1 + act_rootfs=/dev/mtdblock6 +fi +echo "-> Active kernel: $act_kernel" +echo "-> Active system: $act_rootfs" +echo + +if [ x$1 = xflash ]; then + root=flash + kernel=flash +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xflash ]; then + bootargs="$bootargs root=$act_rootfs rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm $act_kernel +fi diff --git a/arch/blackfin/boards/ipe337/env/bin/init b/arch/blackfin/boards/ipe337/env/bin/init new file mode 100644 index 0000000000..e864dc5a42 --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/init @@ -0,0 +1,24 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +addpart /dev/nor0 $mtdparts + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "Type update_kernel [<imagename>] to update kernel into flash." + echo "Type update_system [<imagename>] to update rootfs into flash." + echo "Type update_application [<imagename>] to update applications into flash." + echo "Type update_persistent [<imagename>] to update persistent into flash." + echo "Type update_bareboxenv [<imagename>] to update bareboxenv into flash (use with care!)." + echo "Type reset_ageing to initialize the ageing partittion (use with care!)." + echo + exit +fi + +boot diff --git a/arch/blackfin/boards/ipe337/env/bin/magic.bin b/arch/blackfin/boards/ipe337/env/bin/magic.bin new file mode 100644 index 0000000000..f8bff393cf --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/magic.bin @@ -0,0 +1 @@ +(i
\ No newline at end of file diff --git a/arch/blackfin/boards/ipe337/env/bin/reset_ageing b/arch/blackfin/boards/ipe337/env/bin/reset_ageing new file mode 100644 index 0000000000..2c95ae762e --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/reset_ageing @@ -0,0 +1,27 @@ +#!/bin/sh + +. /env/config + +image=/env/bin/magic.bin +part=$ageing + +if [ \! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +unprotect $part + +echo +echo "Erasing partition $part" +erase $part + +echo +echo "Creating magic" +cp $image $part + +echo +echo "Testing partition" +. /env/bin/_alternate + +protect $part diff --git a/arch/blackfin/boards/ipe337/env/bin/update_application b/arch/blackfin/boards/ipe337/env/bin/update_application new file mode 100644 index 0000000000..46ad210e36 --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/update_application @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$appimage +part=/dev/nor0.application + +. /env/bin/_update $1 diff --git a/arch/blackfin/boards/ipe337/env/bin/update_bareboxenv b/arch/blackfin/boards/ipe337/env/bin/update_bareboxenv new file mode 100644 index 0000000000..b0a32c626b --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/update_bareboxenv @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$envimage +part=/dev/nor0.bareboxenv + +. /env/bin/_update $1 diff --git a/arch/blackfin/boards/ipe337/env/bin/update_kernel b/arch/blackfin/boards/ipe337/env/bin/update_kernel new file mode 100644 index 0000000000..d5c210eb2b --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/update_kernel @@ -0,0 +1,19 @@ +#!/bin/sh + +. /env/config + +image=$uimage + +alternate $ageing +ret=$? + +if [ $ret = 0 ]; then + echo "Error when accesing ageing-partition!" + exit 1 +elif [ $ret = 2 ]; then + part=/dev/nor0.kernel0 +else + part=/dev/nor0.kernel1 +fi + +. /env/bin/_update $1 diff --git a/arch/blackfin/boards/ipe337/env/bin/update_persistent b/arch/blackfin/boards/ipe337/env/bin/update_persistent new file mode 100644 index 0000000000..a869b2218d --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/update_persistent @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$perimage +part=/dev/nor0.persistent + +. /env/bin/_update $1 diff --git a/arch/blackfin/boards/ipe337/env/bin/update_system b/arch/blackfin/boards/ipe337/env/bin/update_system new file mode 100644 index 0000000000..598fc10e81 --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/bin/update_system @@ -0,0 +1,19 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 + +alternate $ageing +ret=$? + +if [ $ret = 0 ]; then + echo "Error when accesing ageing-partition!" + exit 1 +elif [ $ret = 2 ]; then + part=/dev/nor0.system0 +else + part=/dev/nor0.system1 +fi + +. /env/bin/_update $1 diff --git a/arch/blackfin/boards/ipe337/env/config b/arch/blackfin/boards/ipe337/env/config new file mode 100644 index 0000000000..7c5ee76e30 --- /dev/null +++ b/arch/blackfin/boards/ipe337/env/config @@ -0,0 +1,27 @@ +#!/bin/sh + +# can be either 'net' or 'flash' +kernel=net +root=net + +# use 'dhcp' todo dhcp in barebox and in kernel +#ip=dhcp + +eth0.ipaddr=192.168.23.164 +eth0.netmask=255.255.255.0 +eth0.gateway=192.168.23.2 +eth0.serverip=192.168.23.2 + +uimage=uImage-bfin +jffs2=root-bfin.jffs2 +appimage=apps-bfin +perimage=pers-bfin +envimage=uEnv-bfin + +autoboot_timeout=1 + +nfsroot="/ptx/work/octopus/wsa/svn/OSELAS.BSP-Pipetronix-ipe337-trunk/root" +bootargs="console=ttyBF0,115200" + +mtdparts="128k(barebox)ro,128k(bareboxenv),128k(ageing),1280k(kernel0),1280k(kernel1),8704k(system0),8704k(system1),8320k(application),4096k(persistent)" +ageing=/dev/nor0.ageing diff --git a/arch/blackfin/boards/ipe337/ipe337.c b/arch/blackfin/boards/ipe337/ipe337.c new file mode 100644 index 0000000000..269e7743fc --- /dev/null +++ b/arch/blackfin/boards/ipe337/ipe337.c @@ -0,0 +1,68 @@ +#include <common.h> +#include <init.h> +#include <driver.h> +#include <asm/cpu/cdefBF561.h> +#include <partition.h> +#include <fs.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0x20000000, + .size = 32 * 1024 * 1024, +}; + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0x0, + .size = 128 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +static struct device_d smc911x_dev = { + .name = "smc911x", + .map_base = 0x24000000, + .size = 4096, +}; + +static int ipe337_devices_init(void) { + register_device(&cfi_dev); + register_device(&sdram_dev); + + /* Reset smc911x */ + *pFIO0_DIR = (1<<12); + *pFIO0_FLAG_C = (1<<12); + mdelay(100); + *pFIO0_FLAG_S = (1<<12); + + register_device(&smc911x_dev); + + devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0"); + + protect_file("/dev/env0", 1); + + return 0; +} + +device_initcall(ipe337_devices_init); + +static struct device_d blackfin_serial_device = { + .name = "blackfin_serial", + .map_base = 0, + .size = 4096, +}; + +static int blackfin_console_init(void) +{ + register_device(&blackfin_serial_device); + + return 0; +} + +console_initcall(blackfin_console_init); + diff --git a/arch/blackfin/boards/ipe337/ipe337.dox b/arch/blackfin/boards/ipe337/ipe337.dox new file mode 100644 index 0000000000..4d7925af94 --- /dev/null +++ b/arch/blackfin/boards/ipe337/ipe337.dox @@ -0,0 +1,10 @@ +/** @page ipe337 ipe337 + +This CPU card is based on an Analog Device Blackfin CPU. The card is shipped +with: + +- 32MiB NOR type Flash Memory +- 128MiB synchronous dynamic RAM +- SMSC9xxx network controller + +*/
\ No newline at end of file diff --git a/arch/blackfin/configs/ipe337_defconfig b/arch/blackfin/configs/ipe337_defconfig index fd4ff66456..33fd2fcde8 100644 --- a/arch/blackfin/configs/ipe337_defconfig +++ b/arch/blackfin/configs/ipe337_defconfig @@ -55,7 +55,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/ipe337/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/blackin/boards/ipe337/env" # # Debugging diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index f377325add..ec70028a16 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -63,7 +63,7 @@ PHONY += maketools ifneq ($(board-y),) -BOARD := board/$(board-y)/ +BOARD := arch/m68k/boards/$(board-y)/ else BOARD := endif diff --git a/arch/m68k/boards/kp_ukd_r1_num/Makefile b/arch/m68k/boards/kp_ukd_r1_num/Makefile new file mode 100644 index 0000000000..65f2a02fca --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/Makefile @@ -0,0 +1,31 @@ +# +# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> +# See file CREDITS for list of people who contributed to this project. +# +# This file is part of barebox. +# +# barebox is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# barebox is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with barebox. If not, see <http://www.gnu.org/licenses/>. +# + +# The build system allows to split everything into distinct files covering an +# separate issue. Use that! + +# Board specific callbacks and initialisations + +obj-y += lowlevel_init.o +obj-y += highlevel_init.o +obj-y += kp_ukd_r1_num.o + +obj-y += pci-stubs.o + diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update b/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot b/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot new file mode 100644 index 0000000000..c9fcbac620 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xflash ]; then + root=flash + kernel=flash +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xflash ]; then + bootargs="$bootargs root=$rootpart rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nor0.kernel +fi + diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/init b/arch/m68k/boards/kp_ukd_r1_num/env/bin/init new file mode 100644 index 0000000000..48e2139f7d --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/init @@ -0,0 +1,20 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +addpart /dev/nor0 $mtdparts + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type udate_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot
\ No newline at end of file diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop new file mode 100644 index 0000000000..24e76cbed7 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop @@ -0,0 +1,14 @@ +pci stat +pci stat -c +while true; do + pci readm 32 0xA1000000 32 -s + pci readm 32 0xA2000000 256 -s + pci dmatx 2000 a2000100 128 -s + pci writem 32 0xa2000100 0x12345678 4 -s + pci readm 32 0xA3000000 256 -s + pci dmatx 2000 a3000040 128 -s + pci writem 32 0xa3000100 0x12345678 4 -s + pci readm 32 0xA4000000 16 -s + pci dmatx 2000 a4000080 4 -s + pci writem 32 0xa4000080 0x12345678 4 -s +done diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop new file mode 100644 index 0000000000..4a804f9f31 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop @@ -0,0 +1,13 @@ +pci stat +pci stat -c +while true; do + pci readm 32 0xA1000000 32 -s + pci readm 32 0xA2000000 256 -s + pci writem 32 0xa2000100 0x12345678 4 -s + pci readm 32 0xA3000000 256 -s + pci writem 32 0xa3000100 0x12345678 4 -s + pci readm 32 0xA4000000 16 -s + pci writem 32 0xa4000080 0x12345678 4 -s + +# pci dmatx 2000 a3000040 128 -s +done diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel new file mode 100644 index 0000000000..1ad95fc5d6 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$uimage +part=/dev/nor0.kernel + +. /env/bin/_update $1 diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root new file mode 100644 index 0000000000..b757a5b922 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +part=/dev/nor0.root + +. /env/bin/_update $1 diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/config b/arch/m68k/boards/kp_ukd_r1_num/env/config new file mode 100644 index 0000000000..14958ba1df --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/env/config @@ -0,0 +1,32 @@ +#!/bin/sh + +# can be either 'net' or 'flash' +kernel=net +root=net + +# use 'dhcp' todo dhcp in barebox and in kernel +ip=dhcp + +# +# setup default ethernet address +# +eth0.ipaddr=192.168.0.99 +eth0.netmask=255.255.255.0 +eth0.gateway=192.168.0.110 +eth0.serverip=192.168.0.110 + +uimage=uImage-mcf5475 +jffs2=root-mcf5475-ptx.jffs2 + +autoboot_timeout=3 + +#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs" +nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3" +bootargs="console=ttyS0 rw initcall_debug debug" + +# +# setup the partitions in the main flash +# +mtdparts=512k(self),256k(env),3M(kernel),-(root) +rootpart="/dev/mtdblock3" + diff --git a/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c b/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c new file mode 100644 index 0000000000..3a88cd68c7 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c @@ -0,0 +1,124 @@ +/* + * (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> + * See file CREDITS for list of people who contributed to this project. + * + * This file is part of barebox. + * + * barebox is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * barebox is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with barebox. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @file + * @brief This file contains high-level init functions. + * + */ +#include <common.h> +#include <reloc.h> +#include <config.h> +#include <mach/mcf54xx-regs.h> + +static void board_gpio_init(void) +{ + /* + * Enable Ethernet signals so that, if a cable is plugged into + * the ports, the lines won't be floating and potentially cause + * erroneous transmissions + */ + MCF_GPIO_PAR_FECI2CIRQ = 0 + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; +} + + +static void board_psc_init(void) +{ +#if (CFG_EARLY_UART_PORT == 0) + MCF_GPIO_PAR_PSC0 = (0 +#ifdef HARDWARE_FLOW_CONTROL + | MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS + | MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS +#endif + | MCF_GPIO_PAR_PSC0_PAR_TXD0 + | MCF_GPIO_PAR_PSC0_PAR_RXD0); +#elif (CFG_EARLY_UART_PORT == 1) + MCF_GPIO_PAR_PSC1 = (0 +#ifdef HARDWARE_FLOW_CONTROL + | MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS + | MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS +#endif + | MCF_GPIO_PAR_PSC1_PAR_TXD1 + | MCF_GPIO_PAR_PSC1_PAR_RXD1); +#elif (CFG_EARLY_UART_PORT == 2) + MCF_GPIO_PAR_PSC2 = (0 +#ifdef HARDWARE_FLOW_CONTROL + | MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS + | MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS +#endif + | MCF_GPIO_PAR_PSC2_PAR_TXD2 + | MCF_GPIO_PAR_PSC2_PAR_RXD2); +#elif (CFG_EARLY_UART_PORT == 3) + MCF_GPIO_PAR_PSC3 = (0 +#ifdef HARDWARE_FLOW_CONTROL + | MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS + | MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS +#endif + | MCF_GPIO_PAR_PSC3_PAR_TXD3 + | MCF_GPIO_PAR_PSC3_PAR_RXD3); +#else +#error "Invalid CFG_EARLY_UART_PORT setting" +#endif + + /* Put PSC in UART mode */ + MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART; + + /* Call generic UART initialization */ +// mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud()); +} + + +/** Do board specific early init + * + * @note We run at link address now, you can now call other code + */ +void board_init_highlevel(void) +{ + /* Initialize platform specific GPIOs */ + board_gpio_init(); + + /* Init UART GPIOs and Modes */ + board_psc_init(); + + /* Setup the early init data */ +#ifdef CONFIG_HAS_EARLY_INIT + early_init(); +#endif + /* Configure the early debug output facility */ +#ifdef CONFIG_DEBUG_LL + early_debug_init(); +#endif +} + +/** Provide address of early debug low-level output + * + * @todo Should return real address for UART register map. + */ +void *get_early_console_base(const char *name) +{ + return (void*)1 + CFG_EARLY_UART_PORT; +} diff --git a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c new file mode 100644 index 0000000000..9bf1713cc4 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c @@ -0,0 +1,153 @@ +/* + * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> + * See file CREDITS for list of people who contributed to this project. + * + * This file is part of barebox. + * + * barebox is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * barebox is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with barebox. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <fec.h> +#include <environment.h> +#include <mach/mcf54xx-regs.h> +//#include <mach/gpio.h> +#include <mach/clocks.h> +#include <asm/io.h> +#include <partition.h> + +/* + * Return board clock in MHz FIXME move to clocks file + */ +ulong mcfv4e_get_bus_clk(void) +{ + return CFG_SYSTEM_CORE_CLOCK; +} +/* + * Up to 64MiB NOR type flash, connected to + * CS line 0, data width is 32 bit + */ +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = CFG_FLASH_ADDRESS, + .size = CFG_FLASH_SIZE, +}; + +/* + * up to 2MiB static RAM type memory, connected + * to CS4, data width is 16 bit + */ +//static struct device_d sram_dev = { +// .name = "sram", +//FIXME .map_base = IMX_CS4_BASE, +//FIXME .size = IMX_CS4_RANGE, /* area size */ +//}; + +/* + * ?MiB NAND type flash, data width 8 bit + */ +//static struct device_d nand_dev = { +// .name = "cfi_flash_nand", +// .map_base = 0xfc000000, /* FIXME */ +// .size = 32 * 1024 * 1024, /* FIXME */ +//}; + + +/* + * Build in FastEthernetControllers (FECs) + */ +static struct fec_platform_data fec_info = { + .xcv_type = MII100, +}; + +static struct device_d network_dev0 = { + .name = "fec_mcf54xx", + .map_base = MCF_FEC_ADDR(0), + .size = MCF_FEC_SIZE(0), /* area size */ + .platform_data = &fec_info, +}; +static struct device_d network_dev1 = { + .name = "fec_mcf54xx", + .map_base = MCF_FEC_ADDR(1), + .size = MCF_FEC_SIZE(1), /* area size */ + .platform_data = &fec_info, +}; + +/* + * 128MiB of SDRAM, data width is 32 bit + */ +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = CFG_SDRAM_ADDRESS, + .size = CFG_SDRAM_SIZE, + .platform_data = &ram_pdata, +}; + +static int mcfv4e_devices_init(void) +{ + printf("Setting up board devices...\n"); + + /* setup pins for I2C2 (for EEPROM, RTC) */ +//FIXME imx_gpio_mode(MUX_CSPI2_MOSI_I2C2_SCL); +//FIXME imx_gpio_mode(MUX_CSPI2_MISO_I2C2_SCL); + + register_device(&cfi_dev); + + /* + * Create partitions that should be + * not touched by any regular user + */ + devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0"); /* ourself */ + devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0"); /* environment */ + protect_file("/dev/env0", 1); + + //register_device(&sram_dev); + //register_device(&nand_dev); + + register_device(&network_dev0); + //register_device(&network_dev1); + + register_device(&sdram_dev); + + return 0; +} + +device_initcall(mcfv4e_devices_init); + +static struct device_d mcfv4e_serial_device = { + .name = "mcfv4e_serial", + .map_base = 1+CFG_EARLY_UART_PORT, + .size = 16 * 1024, +}; + +static int mcfv4e_console_init(void) +{ + /* init gpios for serial port */ + + /* Already set in lowlevel_init.c */ + + register_device(&mcfv4e_serial_device); + return 0; +} + +console_initcall(mcfv4e_console_init); + diff --git a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox new file mode 100644 index 0000000000..ca0fcbcf39 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox @@ -0,0 +1,13 @@ +/** @page kp_ukd_r1 konzeptpark MCB2 Prototype Board + +This target is based on a PhyTec PhyCore MCF54x5 NUM CPU. The card is shipped with: + +- up to 64MiB NOR type Flash Memory +- 128MiB synchronous dynamic RAM +- PCI USB 2.0 Host +- PCCard Controller +- MiniPCI Parallel +- MiniPCIe (USB lane only) +- ... + +*/ diff --git a/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c b/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c new file mode 100644 index 0000000000..b3de505c24 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c @@ -0,0 +1,183 @@ +/* + * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> + * See file CREDITS for list of people who contributed to this project. + * + * This file is part of barebox. + * + * barebox is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * barebox is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with barebox. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @file + * @brief This file contains ... + * + */ +#include <common.h> +#include <config.h> +#include <mach/mcf54xx-regs.h> + +/** Initialize board specific very early inits + * + * @note This code is not allowed to call other code - just init + * your Chipselects and SDRAM stuff here! + */ +void board_init_lowlevel(void) +{ + /* + * The phyCORE-MCF548x has a 32MB or 64MB boot flash. + * The is a CF Card and ControlRegs on CS1 and CS2 + */ + + /* Setup SysGlue Chip-Select */ + MCF_FBCS_CSAR5 = MCF_FBCS_CSAR_BA(CFG_SYSGLUE_ADDRESS); + + MCF_FBCS_CSCR5 = (MCF_FBCS_CSCR_PS_32 + | MCF_FBCS_CSCR_AA + | MCF_FBCS_CSCR_ASET(1) + | MCF_FBCS_CSCR_WS(CFG_SYSGLUE_WAIT_STATES)); + + MCF_FBCS_CSMR5 = (MCF_FBCS_CSMR_BAM_16M + | MCF_FBCS_CSMR_V); + + /* Setup boot flash chip-select */ + MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS); + + MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32 + | MCF_FBCS_CSCR_AA + | MCF_FBCS_CSCR_ASET(1) + | MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES)); + + MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M + | MCF_FBCS_CSMR_V); + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) + { + /* + * Basic configuration and initialization + */ + // 0x000002AA + MCF_SDRAMC_SDRAMDS = (0 + | MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + | MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + | MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + | MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + | MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + ); + + // 0x0000001A + MCF_SDRAMC_CS0CFG = (0 + | MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS) + | MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE) + ); + + MCF_SDRAMC_CS1CFG = 0; + MCF_SDRAMC_CS2CFG = 0; + MCF_SDRAMC_CS3CFG = 0; + + // 0x73611730 + MCF_SDRAMC_SDCFG1 = (0 + | MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5)) + | MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1)) + | MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2)) + | MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) + | MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) + | MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) + | MCF_SDRAMC_SDCFG1_WTLAT(3) + ); + + // 0x46770000 + MCF_SDRAMC_SDCFG2 = (0 + | MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2) + | MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR) + | MCF_SDRAMC_SDCFG2_BRD2WT(7) + | MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1) + ); + + /* + * Precharge and enable write to SDMR + */ + // 0xE10B0002 + MCF_SDRAMC_SDCR = (0 + | MCF_SDRAMC_SDCR_MODE_EN + | MCF_SDRAMC_SDCR_CKE + | MCF_SDRAMC_SDCR_DDR + | MCF_SDRAMC_SDCR_MUX(1) // 13 x 10 x 2 ==> MUX=1 + | MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5)) + | MCF_SDRAMC_SDCR_IPALL + ); + + /* + * Write extended mode register + */ + // 0x40010000 + MCF_SDRAMC_SDMR = (0 + | MCF_SDRAMC_SDMR_BNKAD_LEMR + | MCF_SDRAMC_SDMR_AD(0x0) + | MCF_SDRAMC_SDMR_CMD + ); + + /* + * Write mode register and reset DLL + */ + // 0x048d0000 + MCF_SDRAMC_SDMR = (0 + | MCF_SDRAMC_SDMR_BNKAD_LMR + | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD) + | MCF_SDRAMC_SDMR_CMD + ); + + /* + * Execute a PALL command + */ + // 0xE10B0002 + MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; + + /* + * Perform two REF cycles + */ + // 0xE10B0004 + MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; + MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; + + /* + * Write mode register and clear reset DLL + */ + // 0x008D0000 + MCF_SDRAMC_SDMR = (0 + | MCF_SDRAMC_SDMR_BNKAD_LMR + | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD) + | MCF_SDRAMC_SDMR_CMD + ); + + /* + * Enable auto refresh and lock SDMR + */ + // 0x610B0000 + MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; + + // 0x710B0F00 + MCF_SDRAMC_SDCR |= (0 + | MCF_SDRAMC_SDCR_REF + | MCF_SDRAMC_SDCR_DQS_OE(0xF) + ); + } +} + +/** @file + * + * Target specific early chipselect and SDRAM init. + */ diff --git a/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c b/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c new file mode 100644 index 0000000000..b7ab7c7d72 --- /dev/null +++ b/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c @@ -0,0 +1,41 @@ +/* + * (C) 2007,2008 Carsten Schlote <schlote@vahanus.net> + * See file CREDITS for list of people who contributed to this project. + * + * This file is part of barebox. + * + * barebox is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * barebox is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with barebox. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @file + * @brief This file contains callbacks for the PCI subsystem + * + */ +#include <common.h> +#include <config.h> + + +/** Returns mapping from PCI slot to CPU irq for the target board + * @return Coldfire IRQ vector number, or -1 for no irq + */ +int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin) +{ + int rc = -1; + switch (slot) + { + case 16 : break; + case 17 ... 21 : rc = 64 + 7; break; // Eport IRQ7 + } + return rc; +} diff --git a/arch/m68k/boards/phycore_mcf54xx/Makefile b/arch/m68k/boards/phycore_mcf54xx/Makefile new file mode 100644 index 0000000000..054123fe75 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/Makefile @@ -0,0 +1,31 @@ +# +# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> +# See file CREDITS for list of people who contributed to this project. +# +# This file is part of barebox. +# +# barebox is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# barebox is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with barebox. If not, see <http://www.gnu.org/licenses/>. +# + +# The build system allows to split everything into distinct files covering an +# separate issue. Use that! + +# Board specific callbacks and initialisations + +obj-y += lowlevel_init.o +obj-y += highlevel_init.o +obj-y += phyCore_MCF54xx.o + +obj-y += pci-stubs.o + diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/_update b/arch/m68k/boards/phycore_mcf54xx/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/boot b/arch/m68k/boards/phycore_mcf54xx/env/bin/boot new file mode 100644 index 0000000000..c9fcbac620 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xflash ]; then + root=flash + kernel=flash +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xflash ]; then + bootargs="$bootargs root=$rootpart rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nor0.kernel +fi + diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/init b/arch/m68k/boards/phycore_mcf54xx/env/bin/init new file mode 100644 index 0000000000..48e2139f7d --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/init @@ -0,0 +1,20 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +addpart /dev/nor0 $mtdparts + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type udate_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot
\ No newline at end of file diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop b/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop new file mode 100644 index 0000000000..24e76cbed7 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop @@ -0,0 +1,14 @@ +pci stat +pci stat -c +while true; do + pci readm 32 0xA1000000 32 -s + pci readm 32 0xA2000000 256 -s + pci dmatx 2000 a2000100 128 -s + pci writem 32 0xa2000100 0x12345678 4 -s + pci readm 32 0xA3000000 256 -s + pci dmatx 2000 a3000040 128 -s + pci writem 32 0xa3000100 0x12345678 4 -s + pci readm 32 0xA4000000 16 -s + pci dmatx 2000 a4000080 4 -s + pci writem 32 0xa4000080 0x12345678 4 -s +done diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop b/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop new file mode 100644 index 0000000000..4a804f9f31 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop @@ -0,0 +1,13 @@ +pci stat +pci stat -c +while true; do + pci readm 32 0xA1000000 32 -s + pci readm 32 0xA2000000 256 -s + pci writem 32 0xa2000100 0x12345678 4 -s + pci readm 32 0xA3000000 256 -s + pci writem 32 0xa3000100 0x12345678 4 -s + pci readm 32 0xA4000000 16 -s + pci writem 32 0xa4000080 0x12345678 4 -s + +# pci dmatx 2000 a3000040 128 -s +done diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel new file mode 100644 index 0000000000..1ad95fc5d6 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$uimage +part=/dev/nor0.kernel + +. /env/bin/_update $1 diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root new file mode 100644 index 0000000000..b757a5b922 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +part=/dev/nor0.root + +. /env/bin/_update $1 diff --git a/arch/m68k/boards/phycore_mcf54xx/env/config b/arch/m68k/boards/phycore_mcf54xx/env/config new file mode 100644 index 0000000000..58550625d2 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/env/config @@ -0,0 +1,32 @@ +#!/bin/sh + +# can be either 'net' or 'flash' +kernel=net +root=net + +# use 'dhcp' todo dhcp in barebox and in kernel +ip=dhcp + +# +# setup default ethernet address +# +eth0.ipaddr=192.168.0.99 +eth0.netmask=255.255.255.0 +eth0.gateway=192.168.0.110 +eth0.serverip=192.168.0.110 + +uimage=uImage-mcf5485 +jffs2=root-mcf5485-ptx.jffs2 + +autoboot_timeout=3 + +#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs" +nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3" +bootargs="console=ttyS0 rw initcall_debug debug" + +# +# setup the partitions in the main flash +# +mtdparts=512k(self),256k(env),3M(kernel),-(root) +rootpart="/dev/mtdblock3" + diff --git a/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c b/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c new file mode 100644 index 0000000000..3a88cd68c7 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c @@ -0,0 +1,124 @@ +/* + * (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> + * See file CREDITS for list of people who contributed to this project. + * + * This file is part of barebox. + * + * barebox is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * barebox is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with barebox. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @file + * @brief This file contains high-level init functions. + * + */ +#include <common.h> +#include <reloc.h> +#include <config.h> +#include <mach/mcf54xx-regs.h> + +static void board_gpio_init(void) +{ + /* + * Enable Ethernet signals so that, if a cable is plugged into + * the ports, the lines won't be floating and potentially cause + * erroneous transmissions + */ + MCF_GPIO_PAR_FECI2CIRQ = 0 + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII + | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; +} + + +static void board_psc_init(void) +{ +#if (CFG_EARLY_UART_PORT == 0) + MCF_GPIO_PAR_PSC0 = (0 +#ifdef HARDWARE_FLOW_CONTROL + | MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS + | MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS +#endif + | MCF_GPIO_PAR_PSC0_PAR_TXD0 + | MCF_GPIO_PAR_PSC0_PAR_RXD0); +#elif (CFG_EARLY_UART_PORT == 1) + MCF_GPIO_PAR_PSC1 = (0 +#ifdef HARDWARE_FLOW_CONTROL + | MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS + | MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS +#endif + | MCF_GPIO_PAR_PSC1_PAR_TXD1 + | MCF_GPIO_PAR_PSC1_PAR_RXD1); +#elif (CFG_EARLY_UART_PORT == 2) + MCF_GPIO_PAR_PSC2 = (0 +#ifdef HARDWARE_FLOW_CONTROL + | MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS + | MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS +#endif + | MCF_GPIO_PAR_PSC2_PAR_TXD2 + | MCF_GPIO_PAR_PSC2_PAR_RXD2); +#elif (CFG_EARLY_UART_PORT == 3) + MCF_GPIO_PAR_PSC3 = (0 +#ifdef HARDWARE_FLOW_CONTROL + | MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS + | MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS +#endif + | MCF_GPIO_PAR_PSC3_PAR_TXD3 + | MCF_GPIO_PAR_PSC3_PAR_RXD3); +#else +#error "Invalid CFG_EARLY_UART_PORT setting" +#endif + + /* Put PSC in UART mode */ + MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART; + + /* Call generic UART initialization */ +// mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud()); +} + + +/** Do board specific early init + * + * @note We run at link address now, you can now call other code + */ +void board_init_highlevel(void) +{ + /* Initialize platform specific GPIOs */ + board_gpio_init(); + + /* Init UART GPIOs and Modes */ + board_psc_init(); + + /* Setup the early init data */ +#ifdef CONFIG_HAS_EARLY_INIT + early_init(); +#endif + /* Configure the early debug output facility */ +#ifdef CONFIG_DEBUG_LL + early_debug_init(); +#endif +} + +/** Provide address of early debug low-level output + * + * @todo Should return real address for UART register map. + */ +void *get_early_console_base(const char *name) +{ + return (void*)1 + CFG_EARLY_UART_PORT; +} diff --git a/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c b/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c new file mode 100644 index 0000000000..2837e3ed67 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c @@ -0,0 +1,194 @@ +/* + * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> + * See file CREDITS for list of people who contributed to this project. + * + * This file is part of barebox. + * + * barebox is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * barebox is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with barebox. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @file + * @brief This file contains ... + * + */ +#include <common.h> +#include <config.h> +#include <mach/mcf54xx-regs.h> + +/** Initialize board specific very early inits + * + * @note This code is not allowed to call other code - just init + * your Chipselects and SDRAM stuff here! + */ +void board_init_lowlevel(void) +{ + /* + * The phyCORE-MCF548x has a 32MB or 64MB boot flash. + * The is a CF Card and ControlRegs on CS1 and CS2 + */ + + /* Setup SysGlue Chip-Select for user IOs */ + MCF_FBCS_CSAR2 = MCF_FBCS_CSAR_BA(CFG_XPLD_ADDRESS); + + MCF_FBCS_CSCR2 = (MCF_FBCS_CSCR_PS_16 + | MCF_FBCS_CSCR_AA + | MCF_FBCS_CSCR_ASET(1) + | MCF_FBCS_CSCR_WS(CFG_XPLD_WAIT_STATES)); + + MCF_FBCS_CSMR2 = (MCF_FBCS_CSMR_BAM_16M + | MCF_FBCS_CSMR_V); + + /* Setup SysGlue Chip-Select for CFCARD */ + MCF_FBCS_CSAR1 = MCF_FBCS_CSAR_BA(CFG_CFCARD_ADDRESS); + + MCF_FBCS_CSCR1 = (MCF_FBCS_CSCR_PS_16 + | MCF_FBCS_CSCR_AA + | MCF_FBCS_CSCR_ASET(1) + | MCF_FBCS_CSCR_WS(CFG_CFCARD_WAIT_STATES)); + + MCF_FBCS_CSMR1 = (MCF_FBCS_CSMR_BAM_16M + | MCF_FBCS_CSMR_V); + + /* Setup boot flash chip-select */ + MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS); + + MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32 + | MCF_FBCS_CSCR_AA + | MCF_FBCS_CSCR_ASET(1) + | MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES)); + + MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M + | MCF_FBCS_CSMR_V); + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) + { + /* + * Basic configuration and initialization + */ + // 0x000002AA + MCF_SDRAMC_SDRAMDS = (0 + | MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + | MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + | MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + | MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + | MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) + ); + + // 0x0000001A + MCF_SDRAMC_CS0CFG = (0 + | MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS) + | MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE) + ); + + MCF_SDRAMC_CS1CFG = 0; + MCF_SDRAMC_CS2CFG = 0; + MCF_SDRAMC_CS3CFG = 0; + + // 0x73611730 + MCF_SDRAMC_SDCFG1 = (0 + | MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5)) + | MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1)) + | MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2)) + | MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) + | MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) + | MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) + | MCF_SDRAMC_SDCFG1_WTLAT(3) + ); + + // 0x46770000 + MCF_SDRAMC_SDCFG2 = (0 + | MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2) + | MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR) + | MCF_SDRAMC_SDCFG2_BRD2WT(7) + | MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1) + ); + + /* + * Precharge and enable write to SDMR + */ + // 0xE10B0002 + MCF_SDRAMC_SDCR = (0 + | MCF_SDRAMC_SDCR_MODE_EN + | MCF_SDRAMC_SDCR_CKE + | MCF_SDRAMC_SDCR_DDR + | MCF_SDRAMC_SDCR_MUX(1) // 13 x 10 x 2 ==> MUX=1 + | MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5)) + | MCF_SDRAMC_SDCR_IPALL + ); + + /* + * Write extended mode register + */ + // 0x40010000 + MCF_SDRAMC_SDMR = (0 + | MCF_SDRAMC_SDMR_BNKAD_LEMR + | MCF_SDRAMC_SDMR_AD(0x0) + | MCF_SDRAMC_SDMR_CMD + ); + + /* + * Write mode register and reset DLL + */ + // 0x048d0000 + MCF_SDRAMC_SDMR = (0 + | MCF_SDRAMC_SDMR_BNKAD_LMR + | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD) + | MCF_SDRAMC_SDMR_CMD + ); + + /* + * Execute a PALL command + */ + // 0xE10B0002 + MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; + + /* + * Perform two REF cycles + */ + // 0xE10B0004 + MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; + MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; + + /* + * Write mode register and clear reset DLL + */ + // 0x008D0000 + MCF_SDRAMC_SDMR = (0 + | MCF_SDRAMC_SDMR_BNKAD_LMR + | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD) + | MCF_SDRAMC_SDMR_CMD + ); + + /* + * Enable auto refresh and lock SDMR + */ + // 0x610B0000 + MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; + + // 0x710B0F00 + MCF_SDRAMC_SDCR |= (0 + | MCF_SDRAMC_SDCR_REF + | MCF_SDRAMC_SDCR_DQS_OE(0xF) + ); + } +} + +/** @file + * + * Target specific early chipselect and SDRAM init. + */
\ No newline at end of file diff --git a/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c b/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c new file mode 100644 index 0000000000..b7ab7c7d72 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c @@ -0,0 +1,41 @@ +/* + * (C) 2007,2008 Carsten Schlote <schlote@vahanus.net> + * See file CREDITS for list of people who contributed to this project. + * + * This file is part of barebox. + * + * barebox is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * barebox is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with barebox. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @file + * @brief This file contains callbacks for the PCI subsystem + * + */ +#include <common.h> +#include <config.h> + + +/** Returns mapping from PCI slot to CPU irq for the target board + * @return Coldfire IRQ vector number, or -1 for no irq + */ +int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin) +{ + int rc = -1; + switch (slot) + { + case 16 : break; + case 17 ... 21 : rc = 64 + 7; break; // Eport IRQ7 + } + return rc; +} diff --git a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c new file mode 100644 index 0000000000..3bc2d12a42 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c @@ -0,0 +1,134 @@ +/* + * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> + * See file CREDITS for list of people who contributed to this project. + * + * This file is part of barebox. + * + * barebox is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * barebox is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with barebox. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @file + * @brief This file contains ... + * + */ +#include <common.h> +#include <init.h> +#include <driver.h> +#include <fec.h> +#include <environment.h> +#include <mach/mcf54xx-regs.h> +#include <mach/clocks.h> +#include <asm/io.h> +#include <partition.h> + +/* + * Return board clock in MHz FIXME move to clocks file + */ +ulong mcfv4e_get_bus_clk(void) +{ + return CFG_SYSTEM_CORE_CLOCK; +} + +/* + * Up to 64MiB NOR type flash, connected to + * CS line 0, data width is 32 bit + */ +static struct device_d cfi_dev = +{ + .name = "cfi_flash", + .map_base = CFG_FLASH_ADDRESS, + .size = CFG_FLASH_SIZE, +}; + +/* + * Build in FastEthernetControllers (FECs) + */ +static struct fec_platform_data fec_info = +{ + .xcv_type = MII100, +}; + +static struct device_d network_dev0 = +{ + .name = "fec_mcf54xx", + .map_base = MCF_FEC_ADDR(0), + .size = MCF_FEC_SIZE(0), /* area size */ + .platform_data = &fec_info, +}; +static struct device_d network_dev1 = +{ + .name = "fec_mcf54xx", + .map_base = MCF_FEC_ADDR(1), + .size = MCF_FEC_SIZE(1), /* area size */ + .platform_data = &fec_info, +}; + +/* + * 128MiB of SDRAM, data width is 32 bit + */ +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = +{ + .name = "mem", + .map_base = CFG_SDRAM_ADDRESS, + .size = CFG_SDRAM_SIZE, + .platform_data = &ram_pdata, +}; + +static int mcfv4e_devices_init(void) +{ + printf("FIXME - setup board devices...\n"); + + register_device(&cfi_dev); + + /* + * Create partitions that should be + * not touched by any regular user + */ + devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0"); /* ourself */ + devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0"); /* environment */ + protect_file("/dev/env0", 1); + + register_device(&network_dev0); + //register_device(&network_dev1); + + register_device(&sdram_dev); + + return 0; +} + +device_initcall(mcfv4e_devices_init); + +static struct device_d mcfv4e_serial_device = +{ + .name = "mcfv4e_serial", + .map_base = 1 + CFG_EARLY_UART_PORT, + .size = 16 * 1024, +}; + +static int mcfv4e_console_init(void) +{ + /* init gpios for serial port */ + + /* Already set in lowlevel_init.c */ + + register_device(&mcfv4e_serial_device); + return 0; +} + +console_initcall(mcfv4e_console_init); diff --git a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox new file mode 100644 index 0000000000..36dd0ad195 --- /dev/null +++ b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox @@ -0,0 +1,14 @@ + +/** @page phycore_mcf54xx Phytec's phyCORE-MCF54x5 + +This target is based on a PhyTec PhyCore MCF54x5 CPU module. The card is shipped with: + +- up to 64MiB NOR type Flash Memory +- 128MiB synchronous dynamic RAM +- PCI USB 2.0 Host +- PCCard Controller +- MiniPCI Parallel +- MiniPCIe (USB lane only) +- ... + +*/ diff --git a/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig b/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig index ba21a008d3..bb91152210 100644 --- a/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig +++ b/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig @@ -71,7 +71,7 @@ CONFIG_EARLY_CONSOLE_PORT="psc0" CONFIG_EARLY_CONSOLE_BAUDRATE=115200 # CONFIG_OF_FLAT_TREE is not set CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/kp_ukd_r1_num/env/" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/kp_ukd_r1_num/env/" # # Debugging diff --git a/arch/m68k/configs/phycore_mcf54xx_defconfig b/arch/m68k/configs/phycore_mcf54xx_defconfig index 34ca73ffc7..f64ca8b022 100644 --- a/arch/m68k/configs/phycore_mcf54xx_defconfig +++ b/arch/m68k/configs/phycore_mcf54xx_defconfig @@ -71,7 +71,7 @@ CONFIG_EARLY_CONSOLE_PORT="psc0" CONFIG_EARLY_CONSOLE_BAUDRATE=115200 # CONFIG_OF_FLAT_TREE is not set CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/phycore_mcf54xx/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/phycore_mcf54xx/env" # # Debugging diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile index c24d3c3685..46d64e5bc6 100644 --- a/arch/ppc/Makefile +++ b/arch/ppc/Makefile @@ -35,7 +35,7 @@ PHONY += maketools ifneq ($(board-y),) -BOARD := board/$(board-y)/ +BOARD := arch/ppc/boards/$(board-y)/ else BOARD := endif diff --git a/arch/ppc/boards/pcm030/Makefile b/arch/ppc/boards/pcm030/Makefile new file mode 100644 index 0000000000..e7d744bfb4 --- /dev/null +++ b/arch/ppc/boards/pcm030/Makefile @@ -0,0 +1,2 @@ +obj-y += pcm030.o +extra-y += barebox.lds diff --git a/arch/ppc/boards/pcm030/barebox.lds.S b/arch/ppc/boards/pcm030/barebox.lds.S new file mode 100644 index 0000000000..ab99335675 --- /dev/null +++ b/arch/ppc/boards/pcm030/barebox.lds.S @@ -0,0 +1,139 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm-generic/barebox.lds.h> + +OUTPUT_ARCH("powerpc") +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + . = TEXT_BASE; + + /* Read-only sections, merged into text segment: */ + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + arch/ppc/mach-mpc5xxx/start.o (.text) + *(.text*) + *(.got1*) + . = ALIGN(16); + *(.rodata*) + *(.rodata1*) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _etext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + + .data : + { + *(.data*) + *(.data1*) + *(.sdata*) + *(.sdata2*) + *(.dynamic*) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __barebox_cmd_start = .; + .barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + __barebox_initcalls_start = .; + .barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + __initcall_entries = (__barebox_initcalls_end - __barebox_initcalls_start) >> 2; + + __usymtab_start = .; + __usymtab : { BAREBOX_SYMS } + __usymtab_end = .; + + __early_init_data_begin = .; + .early_init_data : { *(.early_init_data) } + __early_init_data_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __init_size = __init_end - _start; + + __bss_start = .; + .bss : + { + *(.sbss*) *(.scommon*) + *(.dynbss*) + *(.bss*) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/arch/ppc/boards/pcm030/config.h b/arch/ppc/boards/pcm030/config.h new file mode 100644 index 0000000000..a772ee6d96 --- /dev/null +++ b/arch/ppc/boards/pcm030/config.h @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2006 + * Eric Schumann, Phytec Messatechnik GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <mach/mpc5xxx.h> + +/* #define DEBUG */ + +/*------------------------------------------------------------------------------------------------------------------------------------------------------ +High Level Configuration Options +(easy to change) + ------------------------------------------------------------------------------------------------------------------------------------------------------*/ +#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ +#define CFG_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*------------------------------------------------------------------------------------------------------------------------------------------------------ +Serial console configuration + ------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#if (TEXT_BASE == 0xFF000000) /* Boot low */ +#define CFG_LOWBOOT 1 +#endif +/* RAMBOOT will be defined automatically in memory section */ + +/*------------------------------------------------------------------------------------------------------------------------------------------------------ +IPB Bus clocking configuration. + ------------------------------------------------------------------------------------------------------------------------------------------------------*/ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#if defined(CFG_IPBSPEED_133) +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. + */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#else +#undef CFG_PCISPEED_66 /* for 33MHz speed */ +#endif + +/* we only use CS-Boot */ +#define CFG_BOOTCS_START 0xFF000000 +#define CFG_BOOTCS_SIZE 0x01000000 + +#if CONFIG_MACH_PHYCORE_MPC5200B_TINY_REV == 1 +#define CFG_BOOTCS_CFG 0x0008FD00 +#else +#define CFG_BOOTCS_CFG 0x00083800 +#endif + +/*------------------------------------------------------------------------------------------------------------------------------------------------------ + Memory map + ------------------------------------------------------------------------------------------------------------------------------------------------------*/ +#define CFG_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */ +#define CFG_SDRAM_BASE 0x00000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ +#define CONFIG_EARLY_INITDATA_SIZE 0x100 + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*------------------------------------------------------------------------------------------------------------------------------------------------------ + GPIO configuration + ------------------------------------------------------------------------------------------------------------------------------------------------------*/ +#define CFG_GPS_PORT_CONFIG 0x00558c10 /* PSC6=UART, PSC3=UART ; Ether=100MBit with MD */ + +/*------------------------------------------------------------------------------------------------------------------------------------------------------ + Various low-level settings + ------------------------------------------------------------------------------------------------------------------------------------------------------*/ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define OF_CPU "PowerPC,5200@0" +#define OF_TBCLK CFG_MPC5XXX_CLKIN +#define OF_SOC "soc5200@f0000000" + +#endif /* __CONFIG_H */ diff --git a/arch/ppc/boards/pcm030/mt46v32m16-75.h b/arch/ppc/boards/pcm030/mt46v32m16-75.h new file mode 100644 index 0000000000..4d191f1f91 --- /dev/null +++ b/arch/ppc/boards/pcm030/mt46v32m16-75.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * Eric Schumann, Phytec Messtechnik + * adapted for mt46v32m16-75 DDR-RAM + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x715f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 + + +/* Settings for XLB = 99 MHz */ +/* +#define SDRAM_MODE 0x008D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714b0f00 +#define SDRAM_CONFIG1 0x63611730 +#define SDRAM_CONFIG2 0x47670000 +*/ + +#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */ diff --git a/arch/ppc/boards/pcm030/pcm030.c b/arch/ppc/boards/pcm030/pcm030.c new file mode 100644 index 0000000000..f3845adf4c --- /dev/null +++ b/arch/ppc/boards/pcm030/pcm030.c @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2006 + * Eric Schumann, Phytec Messtechnik GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <driver.h> +#include <init.h> +#include <mach/mpc5xxx.h> +#include <mach/fec.h> +#include <types.h> +#include <partition.h> +#include <mem_malloc.h> +#include <reloc.h> + +struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0xff000000, + .size = 16 * 1024 * 1024, +}; + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +struct device_d sdram_dev = { + .name = "mem", + .map_base = 0x0, + .size = 64 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +static struct mpc5xxx_fec_platform_data fec_info = { + .xcv_type = MII100, +}; + +struct device_d eth_dev = { + .name = "fec_mpc5xxx", + .map_base = MPC5XXX_FEC, + .platform_data = &fec_info, +}; + +static int devices_init (void) +{ + register_device(&cfi_dev); + register_device(&sdram_dev); + register_device(ð_dev); + + devfs_add_partition("nor0", 0x00f00000, 0x40000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x00f60000, 0x20000, PARTITION_FIXED, "env0"); + + return 0; +} + +device_initcall(devices_init); + +static struct device_d psc3 = { + .name = "mpc5xxx_serial", + .map_base = MPC5XXX_PSC3, + .size = 4096, +}; + +static struct device_d psc6 = { + .name = "mpc5xxx_serial", + .map_base = MPC5XXX_PSC6, + .size = 4096, +}; + +static int console_init(void) +{ + register_device(&psc3); + register_device(&psc6); + return 0; +} + +console_initcall(console_init); + +void *get_early_console_base(const char *name) +{ + if (!strcmp(name, RELOC("psc3"))) + return (void *)MPC5XXX_PSC3; + if (!strcmp(name, RELOC("psc6"))) + return (void *)MPC5XXX_PSC6; + return NULL; +} + +#include "mt46v32m16-75.h" + +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; + + ulong test1, test2; + + if ((ulong)RELOC(initdram) > (2 << 30)) { + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR && SDRAM_TAPDELAY + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x10000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x10000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + } else + puts(RELOC("skipping sdram initialization\n")); + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + + return dramsize + dramsize2; +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif + diff --git a/arch/ppc/boards/pcm030/pcm030.dox b/arch/ppc/boards/pcm030/pcm030.dox new file mode 100644 index 0000000000..b9ada839f2 --- /dev/null +++ b/arch/ppc/boards/pcm030/pcm030.dox @@ -0,0 +1,8 @@ +/** @page pcm030 Phytec's phyCORE-MPC5200B-tiny + +This CPU card is based on a Freescale MPC5200B CPU. The card is shipped with: + +- up to 16MiB NOR type Flash Memory +- 64MiB synchronous dynamic RAM + +*/ diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile index 6b8942eb16..4ca17ed839 100644 --- a/arch/sandbox/Makefile +++ b/arch/sandbox/Makefile @@ -3,8 +3,10 @@ CPPFLAGS += -fno-strict-aliasing machine-y := sandbox -board-y := sandbox -lds-y := board/sandbox/barebox.lds +board-y := arch/sandbox/board +BOARD := $(board-y)/ +lds-y := $(BOARD)/barebox.lds + TEXT_BASE = $(CONFIG_TEXT_BASE) @@ -62,6 +64,6 @@ cmd_barebox__ = $(CC) -o $@ -Wl,-T,$(barebox-lds) \ -Wl,--start-group $(barebox-common) -Wl,--end-group \ -lrt -lpthread -common-y += board/sandbox/ arch/sandbox/os/ +common-y += $(BOARD) arch/sandbox/os/ -CLEAN_FILES += board/sandbox/barebox.lds +CLEAN_FILES += $(BOARD)/barebox.lds diff --git a/arch/sandbox/board/.gitignore b/arch/sandbox/board/.gitignore new file mode 100644 index 0000000000..d1165788c9 --- /dev/null +++ b/arch/sandbox/board/.gitignore @@ -0,0 +1 @@ +barebox.lds diff --git a/arch/sandbox/board/Makefile b/arch/sandbox/board/Makefile new file mode 100644 index 0000000000..8abe5dde08 --- /dev/null +++ b/arch/sandbox/board/Makefile @@ -0,0 +1,9 @@ +obj-y += board.o +obj-y += clock.o +obj-y += hostfile.o +obj-y += console.o + +CPPFLAGS_barebox.lds = -U$(SUBARCH) -DELF_ARCH=$(ELF_ARCH) \ + -DELF_FORMAT="$(ELF_FORMAT)" +extra-y += barebox.lds + diff --git a/arch/sandbox/board/barebox.lds.S b/arch/sandbox/board/barebox.lds.S new file mode 100644 index 0000000000..53e9f6021a --- /dev/null +++ b/arch/sandbox/board/barebox.lds.S @@ -0,0 +1,229 @@ +#include <asm-generic/barebox.lds.h> + +OUTPUT_FORMAT(ELF_FORMAT) +OUTPUT_ARCH(ELF_ARCH) +ENTRY(_start) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x400000); . = 0x400000 + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .gnu.hash : { *(.gnu.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.dyn : + { + *(.rel.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rel.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rel.dtors) + *(.rel.got) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rel.ldata .rel.ldata.* .rel.gnu.linkonce.l.*) + *(.rel.lbss .rel.lbss.* .rel.gnu.linkonce.lb.*) + *(.rel.lrodata .rel.lrodata.* .rel.gnu.linkonce.lr.*) + } + .rela.dyn : + { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rela.ldata .rela.ldata.* .rela.gnu.linkonce.l.*) + *(.rela.lbss .rela.lbss.* .rela.gnu.linkonce.lb.*) + *(.rela.lrodata .rela.lrodata.* .rela.gnu.linkonce.lr.*) + } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : + { + KEEP (*(.init)) + } =0x90909090 + .plt : { *(.plt) } + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } =0x90909090 + .fini : + { + KEEP (*(.fini)) + } =0x90909090 + + . = ALIGN(64); + __barebox_initcalls_start = .; + __barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + . = ALIGN(64); + __barebox_cmd_start = .; + __barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } + .rodata1 : { *(.rodata1) } + .eh_frame_hdr : { *(.eh_frame_hdr) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } + /* Adjust the address for the data segment. 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When there is no .bss section, we don't + pad the .data section. */ + . = ALIGN(. != 0 ? 64 / 8 : 1); + } + .lbss : + { + *(.dynlbss) + *(.lbss .lbss.* .gnu.linkonce.lb.*) + *(LARGE_COMMON) + } + . = ALIGN(64 / 8); + .lrodata ALIGN(CONSTANT (MAXPAGESIZE)) + (. & (CONSTANT (MAXPAGESIZE) - 1)) : + { + *(.lrodata .lrodata.* .gnu.linkonce.lr.*) + } + .ldata ALIGN(CONSTANT (MAXPAGESIZE)) + (. & (CONSTANT (MAXPAGESIZE) - 1)) : + { + *(.ldata .ldata.* .gnu.linkonce.l.*) + . = ALIGN(. != 0 ? 64 / 8 : 1); + } + . = ALIGN(64 / 8); + _end = .; PROVIDE (end = .); + . = DATA_SEGMENT_END (.); + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /DISCARD/ : { *(.note.GNU-stack) } +} + diff --git a/arch/sandbox/board/board.c b/arch/sandbox/board/board.c new file mode 100644 index 0000000000..84017eb50d --- /dev/null +++ b/arch/sandbox/board/board.c @@ -0,0 +1,42 @@ +/* + * board.c + * + * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <driver.h> +#include <malloc.h> +#include <mach/linux.h> +#include <init.h> +#include <errno.h> + +static struct device_d tap_device = { + .name = "tap", +}; + +static int devices_init(void) +{ + register_device(&tap_device); + + return 0; +} + +device_initcall(devices_init); + diff --git a/arch/sandbox/board/clock.c b/arch/sandbox/board/clock.c new file mode 100644 index 0000000000..b15086432c --- /dev/null +++ b/arch/sandbox/board/clock.c @@ -0,0 +1,48 @@ +/* + * clock.c - wrapper between a barebox clocksource and linux + * + * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <init.h> +#include <clock.h> +#include <mach/linux.h> + +static uint64_t linux_clocksource_read(void) +{ + return linux_get_time(); +} + +static struct clocksource cs = { + .read = linux_clocksource_read, + .mask = 0xffffffff, + .shift = 10, +}; + +static int clocksource_init (void) +{ + cs.mult = clocksource_hz2mult(1000 * 1000 * 1000, cs.shift); + + init_clock(&cs); + + return 0; +} + +core_initcall(clocksource_init); diff --git a/arch/sandbox/board/config.h b/arch/sandbox/board/config.h new file mode 100644 index 0000000000..c96d762f2d --- /dev/null +++ b/arch/sandbox/board/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define __SANDBOX__ + +#endif /* __CONFIG_H */ diff --git a/arch/sandbox/board/console.c b/arch/sandbox/board/console.c new file mode 100644 index 0000000000..2959e85c7a --- /dev/null +++ b/arch/sandbox/board/console.c @@ -0,0 +1,52 @@ +/* + * console.c - register a console device + * + * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <driver.h> +#include <mach/linux.h> +#include <xfuncs.h> + +int barebox_register_console(char *name, int stdinfd, int stdoutfd) +{ + struct device_d *dev; + struct linux_console_data *data; + + dev = xzalloc(sizeof(struct device_d) + sizeof(struct linux_console_data)); + + data = (struct linux_console_data *)(dev + 1); + + dev->platform_data = data; + strcpy(dev->name, name); + + strcpy(dev->name, "console"); + + if (stdinfd >= 0) + data->flags = CONSOLE_STDIN; + if (stdoutfd >= 0) + data->flags |= CONSOLE_STDOUT | CONSOLE_STDERR; + + data->stdoutfd = stdoutfd; + data->stdinfd = stdinfd; + + return register_device(dev); +} + diff --git a/arch/sandbox/board/env/bin/init b/arch/sandbox/board/env/bin/init new file mode 100644 index 0000000000..a7cb7d563d --- /dev/null +++ b/arch/sandbox/board/env/bin/init @@ -0,0 +1,7 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + diff --git a/arch/sandbox/board/env/config b/arch/sandbox/board/env/config new file mode 100644 index 0000000000..2b148b6daa --- /dev/null +++ b/arch/sandbox/board/env/config @@ -0,0 +1,8 @@ +#!/bin/sh + +eth0.ipaddr=172.0.0.2 +eth0.netmask=255.255.255.0 +eth0.gateway=172.0.0.1 +eth0.serverip=172.0.0.1 +eth0.ethaddr=80:81:82:83:84:85 + diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c new file mode 100644 index 0000000000..ad625d7a6e --- /dev/null +++ b/arch/sandbox/board/hostfile.c @@ -0,0 +1,114 @@ +/* + * hostfile.c - use files from the host to simalute barebox devices + * + * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <driver.h> +#include <malloc.h> +#include <mach/linux.h> +#include <init.h> +#include <errno.h> +#include <mach/hostfile.h> +#include <xfuncs.h> + +struct hf_priv { + struct cdev cdev; + struct hf_platform_data *pdata; +}; + +static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, ulong offset, ulong flags) +{ + struct hf_platform_data *hf = cdev->priv; + int fd = hf->fd; + + if (linux_lseek(fd, offset) != offset) + return -EINVAL; + + return linux_read(fd, buf, count); +} + +static ssize_t hf_write(struct cdev *cdev, const void *buf, size_t count, ulong offset, ulong flags) +{ + struct hf_platform_data *hf = cdev->priv; + int fd = hf->fd; + + if (linux_lseek(fd, offset) != offset) + return -EINVAL; + + return linux_write(fd, buf, count); +} + +static void hf_info(struct device_d *dev) +{ + struct hf_platform_data *hf = dev->platform_data; + + printf("file: %s\n", hf->filename); +} + +static struct file_operations hf_fops = { + .read = hf_read, + .write = hf_write, +}; + +static int hf_probe(struct device_d *dev) +{ + struct hf_platform_data *hf = dev->platform_data; + struct hf_priv *priv = xzalloc(sizeof(*priv)); + + priv->pdata = hf; + + priv->cdev.name = hf->name; + priv->cdev.size = hf->size; + priv->cdev.ops = &hf_fops; + priv->cdev.priv = hf; + devfs_create(&priv->cdev); + + return 0; +} + +static struct driver_d hf_drv = { + .name = "hostfile", + .probe = hf_probe, + .info = hf_info, +}; + +static int hf_init(void) +{ + return register_driver(&hf_drv); +} + +device_initcall(hf_init); + +int barebox_register_filedev(struct hf_platform_data *hf) +{ + struct device_d *dev; + + dev = xzalloc(sizeof(struct device_d)); + + dev->platform_data = hf; + + strcpy(dev->name, "hostfile"); + dev->size = hf->size; + dev->map_base = hf->map_base; + + return register_device(dev); +} + diff --git a/arch/sandbox/configs/sandbox_defconfig b/arch/sandbox/configs/sandbox_defconfig index adcb07e49b..9037c8ba92 100644 --- a/arch/sandbox/configs/sandbox_defconfig +++ b/arch/sandbox/configs/sandbox_defconfig @@ -41,7 +41,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/sandbox/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/sandbox/board/env" # # Debugging diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 2e2cb810d7..57c5dbc3b0 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -26,7 +26,7 @@ all: $(KBUILD_IMAGE) ifneq ($(board-y),) -BOARD := board/$(board-y)/ +BOARD := arch/x86/boards/$(board-y)/ else BOARD := endif diff --git a/arch/x86/boards/x86_generic/Makefile b/arch/x86/boards/x86_generic/Makefile new file mode 100644 index 0000000000..248240da07 --- /dev/null +++ b/arch/x86/boards/x86_generic/Makefile @@ -0,0 +1 @@ +obj-y += generic_pc.o diff --git a/arch/x86/boards/x86_generic/config.h b/arch/x86/boards/x86_generic/config.h new file mode 100644 index 0000000000..39bea1844b --- /dev/null +++ b/arch/x86/boards/x86_generic/config.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2009 Juergen Beisert, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* nothing special yet */ diff --git a/arch/x86/boards/x86_generic/env/bin/boot b/arch/x86/boards/x86_generic/env/bin/boot new file mode 100644 index 0000000000..fcfffe3194 --- /dev/null +++ b/arch/x86/boards/x86_generic/env/bin/boot @@ -0,0 +1,37 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xdisk ]; then + root=disk + kernel=disk +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xdisk ]; then + bootargs="$bootargs root=$rootpart_disk rootfstype=$rootpart_fs rw" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp rw" +fi + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootargs="BOOT_IMAGE=$kernel_device auto $bootargs" + linux16 $kernel_device +fi + diff --git a/arch/x86/boards/x86_generic/env/bin/init b/arch/x86/boards/x86_generic/env/bin/init new file mode 100644 index 0000000000..2924a4449a --- /dev/null +++ b/arch/x86/boards/x86_generic/env/bin/init @@ -0,0 +1,15 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + exit +fi + +boot diff --git a/arch/x86/boards/x86_generic/env/config b/arch/x86/boards/x86_generic/env/config new file mode 100644 index 0000000000..dd57aad716 --- /dev/null +++ b/arch/x86/boards/x86_generic/env/config @@ -0,0 +1,31 @@ +# +# basic config +# +# boot source: 'disk' or 'net' +kernel=disk +root=disk + +# data for the NFS case +nfsroot="/path/to/nfs_root" + +# data for the disk case +kernel_device=/dev/biosdisk0.1 +rootpart_disk=/dev/sda1 +rootpart_fs=ext2 + +baudrate=115200 +serial=ttyS0 + +# use UART for console +bootargs="console=$serial,$baudrate" + +autoboot_timeout=3 + +# use 'dhcp' to do dhcp in uboot and in kernel +# ip=dhcp +# or set your networking parameters here +# eth0.ipaddr=192.168.3.11 +# eth0.netmask=255.255.255.0 +# eth0.gateway=a.b.c.d +# eth0.serverip=192.168.3.10 +# eth0.ethaddr=aa.bb.cc.dd.ee.ff diff --git a/arch/x86/boards/x86_generic/generic_pc.c b/arch/x86/boards/x86_generic/generic_pc.c new file mode 100644 index 0000000000..bd93bc168d --- /dev/null +++ b/arch/x86/boards/x86_generic/generic_pc.c @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2009 Juergen Beisert, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/** + * @file + * @brief Generic PC support to let barebox acting as a boot loader + */ + +#include <common.h> +#include <types.h> +#include <driver.h> +#include <init.h> +#include <asm/syslib.h> +#include <ns16550.h> + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .size = 16 * 1024 * 1024, + .map_base = 0, + .platform_data = &ram_pdata, +}; + +static struct device_d bios_disk_dev = { + .name = "biosdrive", + .size = 1, +}; + +/* + * These datas are from the MBR, created by the linker and filled by the + * setup tool while installing barebox on the disk drive + */ +extern uint64_t pers_env_storage; +extern uint16_t pers_env_size; +extern uint8_t pers_env_drive; + +/** + * Persistant environment "not used" marker. + * Note: Must be in accordance to the value the tool "setup_mbr" writes. + */ +#define PATCH_AREA_PERS_SIZE_UNUSED 0x000 + +static int devices_init(void) +{ + int rc; + + sdram_dev.size = bios_get_memsize(); /* extended memory only */ + sdram_dev.size <<= 10; + + register_device(&sdram_dev); + register_device(&bios_disk_dev); + + if (pers_env_size != PATCH_AREA_PERS_SIZE_UNUSED) { + rc = devfs_add_partition("disk0", /* FIXME */ + pers_env_storage * 512, + (unsigned)pers_env_size * 512, + DEVFS_PARTITION_FIXED, "env0"); + printf("Partition: %d\n", rc); + } else + printf("No persistant storage defined\n"); + + return 0; +} +device_initcall(devices_init); + +#ifdef CONFIG_DRIVER_SERIAL_NS16550 + +static struct NS16550_plat serial_plat = { + .clock = 1843200, + .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR, + .reg_read = x86_uart_read, + .reg_write = x86_uart_write, +}; + +/* we are expecting always one serial interface */ +static struct device_d generic_pc_serial_device = { + .name = "serial_ns16550", + .map_base = 0x3f8, + .size = 8, + .platform_data = (void *)&serial_plat, +}; + +static int pc_console_init(void) +{ + /* Register the serial port */ + return register_device(&generic_pc_serial_device); +} +console_initcall(pc_console_init); + +#endif + +/** @page generic_pc Generic PC based bootloader + +This platform acts as a generic PC based bootloader. It depends on at least +one boot media that is connected locally (no network boot) and can be +handled by the regular BIOS (any kind of hard disks for example). + +The created @a barebox image can be used to boot a standard x86 bzImage +Linux kernel. + +Refer section @ref x86_bootloader_preparations how to do so. + +How to get the binary image: + +Using the default configuration: + +@code +make ARCH=x86 generic_defconfig +@endcode + +Build the binary image: + +@code +make ARCH=x86 CROSS_COMPILE=x86compiler +@endcode + +@note replace the 'x86compiler' with your x86 (cross) compiler. + +*/ diff --git a/arch/x86/configs/generic_defconfig b/arch/x86/configs/generic_defconfig index 091f696e3a..3c72242415 100644 --- a/arch/x86/configs/generic_defconfig +++ b/arch/x86/configs/generic_defconfig @@ -63,7 +63,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y # CONFIG_OF_FLAT_TREE is not set CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="board/x86_generic/env" +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/x86/boards/x86_generic/env" # # Debugging |