diff options
Diffstat (limited to 'arch')
163 files changed, 4893 insertions, 676 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 13f0bd41be..3c9b81ab06 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -109,6 +109,7 @@ config ARCH_MVEBU select MVEBU_MBUS select OFTREE select OF_ADDRESS_PCI + select PINCTRL config ARCH_MXS bool "Freescale i.MX23/28 (mxs) based" @@ -208,6 +209,7 @@ config ARCH_TEGRA select OFTREE select RELOCATABLE select RESET_CONTROLLER + select PINCTRL config ARCH_UEMD bool "RC Module UEMD Platform" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 337aef175b..cf81c9c083 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -163,7 +163,7 @@ KBUILD_IMAGE := barebox.ubl endif quiet_cmd_am35xx_spi_image = SPI-IMG $@ - cmd_am35xx_spi_image = scripts/mk-am3xxx-spi-image -s am35xx -a $(TEXT_BASE) $< > $@ + cmd_am35xx_spi_image = scripts/mk-omap-image -s -a $(TEXT_BASE) $< > $@ barebox.spi: $(KBUILD_BINARY) FORCE $(call if_changed,am35xx_spi_image) diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 122f5cde5e..c80b9c920a 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -1,4 +1,5 @@ # keep sorted by CONFIG_* macro name. +obj-$(CONFIG_MACH_AFI_GF) += afi-gf/ obj-$(CONFIG_MACH_ANIMEO_IP) += animeo_ip/ obj-$(CONFIG_MACH_ARCHOSG9) += archosg9/ obj-$(CONFIG_MACH_AT91SAM9260EK) += at91sam9260ek/ @@ -48,6 +49,7 @@ obj-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += globalscale-mirabox/ obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/ obj-$(CONFIG_MACH_GUF_SANTARO) += guf-santaro/ obj-$(CONFIG_MACH_GUF_VINCELL) += guf-vincell/ +obj-$(CONFIG_MACH_GW_VENTANA) += gateworks-ventana/ obj-$(CONFIG_MACH_HIGHBANK) += highbank/ obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/ obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/ @@ -92,6 +94,7 @@ obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/ obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/ obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/ obj-$(CONFIG_MACH_SAMA5D3_XPLAINED) += sama5d3_xplained/ +obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ @@ -108,6 +111,7 @@ obj-$(CONFIG_MACH_TX25) += karo-tx25/ obj-$(CONFIG_MACH_TX28) += karo-tx28/ obj-$(CONFIG_MACH_TX51) += karo-tx51/ obj-$(CONFIG_MACH_TX53) += karo-tx53/ +obj-$(CONFIG_MACH_TX6X) += karo-tx6x/ obj-$(CONFIG_MACH_UDOO) += udoo/ obj-$(CONFIG_MACH_USB_A9260) += usb-a926x/ obj-$(CONFIG_MACH_USB_A9263) += usb-a926x/ diff --git a/arch/arm/boards/afi-gf/Makefile b/arch/arm/boards/afi-gf/Makefile new file mode 100644 index 0000000000..399a4b8cc0 --- /dev/null +++ b/arch/arm/boards/afi-gf/Makefile @@ -0,0 +1,3 @@ +lwl-y += lowlevel.o +obj-y += board.o +bbenv-y += defaultenv-gf diff --git a/arch/arm/boards/afi-gf/board.c b/arch/arm/boards/afi-gf/board.c new file mode 100644 index 0000000000..dfcb579f24 --- /dev/null +++ b/arch/arm/boards/afi-gf/board.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <string.h> +#include <init.h> +#include <sizes.h> +#include <envfs.h> +#include <bootsource.h> +#include <asm/armlinux.h> +#include <mach/bbu.h> +#include <mach/am33xx-generic.h> + +static int board_console_init(void) +{ + if (!of_machine_is_compatible("afi,gf")) + return 0; + + switch (bootsource_get()) { + default: + case BOOTSOURCE_SPI: + of_device_enable_path("/chosen/environment-spi"); + break; + case BOOTSOURCE_MMC: + omap_set_bootmmc_devname("mmc0"); + break; + } + + defaultenv_append_directory(defaultenv_gf); + am33xx_register_ethaddr(0, 0); + am33xx_register_ethaddr(1, 1); + barebox_set_hostname("gf"); + am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.mlo"); + am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.boot"); + + return 0; +} +coredevice_initcall(board_console_init); diff --git a/arch/arm/boards/afi-gf/config.h b/arch/arm/boards/afi-gf/config.h new file mode 100644 index 0000000000..aeeda3695b --- /dev/null +++ b/arch/arm/boards/afi-gf/config.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd b/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd new file mode 100644 index 0000000000..dce060542a --- /dev/null +++ b/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "kernel & rootfs on SD card" + exit +fi + +global.bootm.image=/boot/uImage +global.bootm.oftree=/boot/oftree +#global.bootm.initrd=<path to initrd> +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" diff --git a/arch/arm/boards/afi-gf/defaultenv-gf/init/automount b/arch/arm/boards/afi-gf/defaultenv-gf/init/automount new file mode 100644 index 0000000000..c67bd1ba50 --- /dev/null +++ b/arch/arm/boards/afi-gf/defaultenv-gf/init/automount @@ -0,0 +1,15 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth1.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth1 && mount -t tftp $eth1.serverip /mnt/tftp' + +# eth0 is on the mezzanine board +mkdir -p /mnt/tftp-eth0 +automount /mnt/tftp-eth0 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' diff --git a/arch/arm/boards/afi-gf/defaultenv-gf/network/eth1 b/arch/arm/boards/afi-gf/defaultenv-gf/network/eth1 new file mode 100644 index 0000000000..1ed3017e96 --- /dev/null +++ b/arch/arm/boards/afi-gf/defaultenv-gf/network/eth1 @@ -0,0 +1,18 @@ +#!/bin/sh + +# ip setting (static/dhcp) +ip=dhcp +global.dhcp.vendor_id=barebox-${global.hostname} + +# static setup used if ip=static +ipaddr= +netmask= +gateway= +serverip= + +# MAC address if needed +#ethaddr=xx:xx:xx:xx:xx:xx + +# put code to discover eth1 (i.e. 'usb') to /env/network/eth0-discover + +exit 0 diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c new file mode 100644 index 0000000000..fdc340c057 --- /dev/null +++ b/arch/arm/boards/afi-gf/lowlevel.c @@ -0,0 +1,266 @@ +#include <init.h> +#include <sizes.h> +#include <io.h> +#include <asm/armlinux.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <linux/bitops.h> +#include <mach/am33xx-generic.h> +#include <mach/am33xx-silicon.h> +#include <mach/am33xx-clock.h> +#include <mach/sdrc.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> +#include <mach/am33xx-mux.h> +#include <mach/wdt.h> +#include <debug_ll.h> + +/* AM335X EMIF Register values */ +#define VTP_CTRL_READY (0x1 << 5) +#define VTP_CTRL_ENABLE (0x1 << 6) +#define VTP_CTRL_LOCK_EN (0x1 << 4) +#define VTP_CTRL_START_EN (0x1) +#define DDR2_RATIO 0x80 /* for mDDR */ // +#define CMD_FORCE 0x00 /* common #def */ +#define CMD_DELAY 0x00 + +#define EMIF_READ_LATENCY 0x05 // (CL + 2 - 1) +#define EMIF_TIM1 0x04447289 // +#define EMIF_TIM2 0x10160580 // +#define EMIF_TIM3 0x000000E7 // check tREFI +#define EMIF_SDCFG 0x0 \ + | (1 << 29) /* reg_sdram_type = 1 (LPDDR1) */ \ + | (0 << 27) /* reg_ibank_pos = 0 */ \ + | (0 << 24) /* reg_ddr_term = 0? */ \ + | (0 << 23) /* reg_ddr2_ddqs = 0 (single ended DQS for LPDDR) */ \ + | (0 << 21) /* reg_dyn_odt = 0 (only used for DDR3) */ \ + | (0 << 20) /* reg_ddr_disable_dll = 0 */ \ + | (1 << 18) /* reg_sdram_drive = 1? (1/2 for LPDDR) */ \ + | (0 << 16) /* reg_cwl = 0 (only for DDR3) */ \ + | (1 << 14) /* reg_narrow_mode = 1 (AM335x is always 16 bit) */ \ + | (3 << 10) /* reg_cl = 3 */ \ + | (5 << 7) /* reg_rowsize = 5 (unused?, 14 row bits) */ \ + | (2 << 4) /* reg_ibank = 2 (4 banks) */ \ + | (0 << 3) /* reg_ebank = 0 */ \ + | (3 << 0) /* reg_pagesize = 3? (11 column bits = 2048 words) */ +#define EMIF_SDREF 0x00000618 // +#define DDR2_DLL_LOCK_DIFF 0x0 +#define DDR2_RD_DQS 0x40 // +#define DDR2_WR_DQS 0x2 // +#define DDR2_PHY_WRLVL 0x00 +#define DDR2_PHY_GATELVL 0x00 +#define DDR2_PHY_FIFO_WE 0x110 // +#define DDR2_PHY_WR_DATA 0x40 // + +#define DDR2_INVERT_CLKOUT 0x0 // +#define PHY_RANK0_DELAY 0x1 // +#define PHY_DLL_LOCK_DIFF 0x0 +#define DDR_IOCTRL_VALUE 0x18B // + +static void board_data_macro_config(int dataMacroNum) +{ + u32 BaseAddrOffset = 0x00; + + if (dataMacroNum == 1) + BaseAddrOffset = 0xA4; + + __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) + |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), + (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_RD_DQS>>2, + (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) + |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), + (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_WR_DQS>>2, + (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) + |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), + (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_PHY_WRLVL>>2, + (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) + |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), + (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_PHY_GATELVL>>2, + (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) + |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), + (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_PHY_FIFO_WE>>2, + (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) + |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), + (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_PHY_WR_DATA>>2, + (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset)); + __raw_writel(PHY_DLL_LOCK_DIFF, + (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset)); +} + +static void board_cmd_macro_config(void) +{ + __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0); + __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0); + __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0); + __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0); + __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0); + + __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0); + __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0); + __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0); + __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0); + __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0); + + __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0); + __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0); + __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0); + __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0); + __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0); +} + +static void board_config_vtp(void) +{ + __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE, + AM33XX_VTP0_CTRL_REG); + __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN), + AM33XX_VTP0_CTRL_REG); + __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN, + AM33XX_VTP0_CTRL_REG); + + /* Poll for READY */ + while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY); +} + +static void board_config_emif_ddr(void) +{ + u32 i; + + /*Program EMIF0 CFG Registers*/ + __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); + __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); + __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); + __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); + __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); + __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); + __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); + __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); + __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); + + __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); + __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); + + __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); + __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + + for (i = 0; i < 5000; i++) { + + } + + __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); + __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + + __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); + __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); +} + +static void board_config_ddr(void) +{ + am33xx_enable_ddr_clocks(); + + board_config_vtp(); + + board_cmd_macro_config(); + board_data_macro_config(0); + board_data_macro_config(1); + + __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); + __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); + + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); + + __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) | BIT(28), AM33XX_DDR_IO_CTRL); + __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | BIT(0), AM33XX_DDR_CKE_CTRL); + + board_config_emif_ddr(); +} + +static const struct module_pin_mux board_can_pin_mux[] = { + {OFFSET(mii1_txd3), (MODE(1) | PULLUP_EN)}, /* dcan0_tx_mux0 */ + {OFFSET(mii1_txd2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* dcan0_rx_mux0 */ + {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUP_EN)}, /* gpio3[18] / DCAN0_LBK */ + {-1}, +}; + +extern char __dtb_am335x_afi_gf_start[]; + +/** + * @brief The basic entry point for board initialization. + * + * This is called as part of machine init (after arch init). + * This is again called with stack in SRAM, so not too many + * constructs possible here. + * + * @return void + */ +static noinline int gf_sram_init(void) +{ + void *fdt; + + fdt = __dtb_am335x_afi_gf_start; + + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); + while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); + while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + + /* Setup the PLLs and the clocks for the peripherals */ + am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_200); + + board_config_ddr(); + + /* + * FIXME configure CAN pinmux early to avoid driving the bus + * with the low by default pins. + */ + configure_module_pin_mux(board_can_pin_mux); + + am33xx_uart_soft_reset((void *)AM33XX_UART2_BASE); + am33xx_enable_uart2_pin_mux(); + omap_uart_lowlevel_init((void *)AM33XX_UART2_BASE); + putc_ll('>'); + + barebox_arm_entry(0x80000000, SZ_256M, fdt); +} + +ENTRY_FUNCTION(start_am33xx_afi_gf_sram, bootinfo, r1, r2) +{ + am33xx_save_bootinfo((void *)bootinfo); + + /* + * Setup C environment, the board init code uses global variables. + * Stackpointer has already been initialized by the ROM code. + */ + relocate_to_current_adr(); + setup_c(); + + gf_sram_init(); +} + +ENTRY_FUNCTION(start_am33xx_afi_gf_sdram, r0, r1, r2) +{ + void *fdt; + + fdt = __dtb_am335x_afi_gf_start - get_runtime_offset(); + + putc_ll('>'); + + barebox_arm_entry(0x80000000, SZ_256M, fdt); +} diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c index e388e28168..25f45dfcc0 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/board.c +++ b/arch/arm/boards/datamodul-edm-qmx6/board.c @@ -49,6 +49,7 @@ #define RQ7_GPIO_ENET_MODE2 IMX_GPIO_NR(6, 28) #define RQ7_GPIO_ENET_MODE3 IMX_GPIO_NR(6, 29) #define RQ7_GPIO_ENET_EN_CLK125 IMX_GPIO_NR(6, 24) +#define RQ7_GPIO_ENET_RESET IMX_GPIO_NR(1, 25) static iomux_v3_cfg_t realq7_pads_gpio[] = { MX6Q_PAD_RGMII_RXC__GPIO_6_30, @@ -57,6 +58,7 @@ static iomux_v3_cfg_t realq7_pads_gpio[] = { MX6Q_PAD_RGMII_RD2__GPIO_6_28, MX6Q_PAD_RGMII_RD3__GPIO_6_29, MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24, + MX6Q_PAD_ENET_CRS_DV__GPIO_1_25, }; static int ksz9031rn_phy_fixup(struct phy_device *dev) @@ -85,12 +87,14 @@ static int realq7_enet_init(void) gpio_direction_output(RQ7_GPIO_ENET_MODE3, 1); gpio_direction_output(RQ7_GPIO_ENET_EN_CLK125, 1); - gpio_direction_output(25, 0); + gpio_direction_output(RQ7_GPIO_ENET_RESET, 0); mdelay(50); - gpio_direction_output(25, 1); + gpio_direction_output(RQ7_GPIO_ENET_RESET, 1); mdelay(50); + gpio_free(RQ7_GPIO_ENET_RESET); + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, ksz9031rn_phy_fixup); diff --git a/arch/arm/boards/gateworks-ventana/Makefile b/arch/arm/boards/gateworks-ventana/Makefile new file mode 100644 index 0000000000..7d195eebd6 --- /dev/null +++ b/arch/arm/boards/gateworks-ventana/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o gsc.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/gateworks-ventana/board.c b/arch/arm/boards/gateworks-ventana/board.c new file mode 100644 index 0000000000..82dba7c93d --- /dev/null +++ b/arch/arm/boards/gateworks-ventana/board.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2014 Lucas Stach, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <environment.h> +#include <i2c/i2c.h> +#include <init.h> +#include <linux/marvell_phy.h> +#include <linux/phy.h> +#include <mach/bbu.h> +#include <mach/imx6.h> +#include <net.h> + +#include "gsc.h" + +static int gw54xx_devices_init(void) +{ + struct i2c_client client; + struct device_node *dnode; + u8 reg; + u8 mac[6]; + + if (!of_machine_is_compatible("gw,imx6q-gw54xx")) + return 0; + + client.adapter = i2c_get_adapter(0); + if (!client.adapter) { + pr_err("could not get system controller i2c bus\n"); + return -ENODEV; + } + + /* disable the GSC boot watchdog */ + client.addr = GSC_SC_ADDR; + gsc_i2c_read(&client, GSC_SC_CTRL1, ®, 1); + reg |= GSC_SC_CTRL1_WDDIS; + gsc_i2c_write(&client, GSC_SC_CTRL1, ®, 1); + + /* read MAC adresses from EEPROM and attach to eth devices */ + dnode = of_find_node_by_alias(of_get_root_node(), "ethernet0"); + if (dnode) { + client.addr = GSC_EEPROM_ADDR; + gsc_i2c_read(&client, 0x00, mac, 6); + of_eth_register_ethaddr(dnode, mac); + } + dnode = of_find_node_by_alias(of_get_root_node(), "ethernet1"); + if (dnode) { + client.addr = GSC_EEPROM_ADDR; + gsc_i2c_read(&client, 0x06, mac, 6); + of_eth_register_ethaddr(dnode, mac); + } + + imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + + barebox_set_hostname("gw54xx"); + + return 0; +} +device_initcall(gw54xx_devices_init); + +static int marvell_88e1510_phy_fixup(struct phy_device *dev) +{ + u32 val; + + /* LED settings */ + phy_write(dev, 22, 3); + val = phy_read(dev, 16); + val &= 0xff00; + val |= 0x0017; + phy_write(dev, 16, val); + phy_write(dev, 22, 0); + + return 0; +} + +static int gw54xx_coredevices_init(void) +{ + if (!of_machine_is_compatible("gw,imx6q-gw54xx")) + return 0; + + phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK, + marvell_88e1510_phy_fixup); + + return 0; +} +coredevice_initcall(gw54xx_coredevices_init); diff --git a/arch/arm/boards/gateworks-ventana/clocks.imxcfg b/arch/arm/boards/gateworks-ventana/clocks.imxcfg new file mode 100644 index 0000000000..bfd5331f01 --- /dev/null +++ b/arch/arm/boards/gateworks-ventana/clocks.imxcfg @@ -0,0 +1,8 @@ +wm 32 MX6_CCM_CCGR0 0x00C03F3F +wm 32 MX6_CCM_CCGR1 0x0030FC03 +wm 32 MX6_CCM_CCGR2 0x0FFFC000 +wm 32 MX6_CCM_CCGR3 0x3FF00000 +wm 32 MX6_CCM_CCGR4 0xFFFFF300 +wm 32 MX6_CCM_CCGR5 0x0F0000C3 +wm 32 MX6_CCM_CCGR6 0x000003FF +wm 32 MX6_CCM_CCOSR 0x000000FB diff --git a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg new file mode 100644 index 0000000000..75271e477d --- /dev/null +++ b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg @@ -0,0 +1,11 @@ +soc imx6 +loadaddr 0x20000000 +dcdofs 0x400 + +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6q-ddr-regs.h> +#include <mach/imx6-ccm-regs.h> + +#include "ram-base.imxcfg" +#include "quad_128x64.imxcfg" +#include "clocks.imxcfg" diff --git a/arch/arm/boards/gateworks-ventana/gsc.c b/arch/arm/boards/gateworks-ventana/gsc.c new file mode 100644 index 0000000000..3614230482 --- /dev/null +++ b/arch/arm/boards/gateworks-ventana/gsc.c @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * Copyright (C) 2014 Lucas Stach, Pengutronix + * Author: Tim Harvey <tharvey@gateworks.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * The Gateworks System Controller will fail to ACK a master transaction if + * it is busy, which can occur during its 1HZ timer tick while reading ADC's. + * When this does occur, it will never be busy long enough to fail more than + * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with + * 3 retries. + */ + +#include <common.h> +#include <i2c/i2c.h> + +#include "gsc.h" + +int gsc_i2c_read(struct i2c_client *client, u32 addr, u8 *buf, u16 count) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_read_reg(client, addr, buf, count); + if (!ret) + break; + pr_debug("GSC read failed\n"); + if (ret != -ENODEV) + break; + mdelay(10); + } + + return ret; +} + +int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_write_reg(client, addr, buf, count); + if (!ret) + break; + pr_debug("GSC write failed\n"); + if (ret != -ENODEV) + break; + mdelay(10); + } + mdelay(100); + + return ret; +} diff --git a/arch/arm/boards/gateworks-ventana/gsc.h b/arch/arm/boards/gateworks-ventana/gsc.h new file mode 100644 index 0000000000..a6e7e2232d --- /dev/null +++ b/arch/arm/boards/gateworks-ventana/gsc.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * Copyright (C) 2014 Lucas Stach, Pengutronix + * Author: Tim Harvey <tharvey@gateworks.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* i2c slave addresses */ +#define GSC_SC_ADDR 0x20 +#define GSC_RTC_ADDR 0x68 +#define GSC_HWMON_ADDR 0x29 +#define GSC_EEPROM_ADDR 0x51 + +/* System Controller registers */ +#define GSC_SC_CTRL0 0x00 +#define GSC_SC_CTRL1 0x01 +#define GSC_SC_CTRL1_WDDIS (1 << 7) +#define GSC_SC_STATUS 0x0a +#define GSC_SC_FWVER 0x0e + +/* System Controller Interrupt bits */ +#define GSC_SC_IRQ_PB 0 /* Pushbutton switch */ +#define GSC_SC_IRQ_SECURE 1 /* Secure Key erase complete */ +#define GSC_SC_IRQ_EEPROM_WP 2 /* EEPROM write violation */ +#define GSC_SC_IRQ_GPIO 4 /* GPIO change */ +#define GSC_SC_IRQ_TAMPER 5 /* Tamper detect */ +#define GSC_SC_IRQ_WATCHDOG 6 /* Watchdog trip */ +#define GSC_SC_IRQ_PBLONG 7 /* Pushbutton long hold */ + +/* Hardware Monitor registers */ +#define GSC_HWMON_TEMP 0x00 +#define GSC_HWMON_VIN 0x02 +#define GSC_HWMON_VDD_3P3 0x05 +#define GSC_HWMON_VBATT 0x08 +#define GSC_HWMON_VDD_5P0 0x0b +#define GSC_HWMON_VDD_CORE 0x0e +#define GSC_HWMON_VDD_HIGH 0x14 +#define GSC_HWMON_VDD_DDR 0x17 +#define GSC_HWMON_VDD_SOC 0x11 +#define GSC_HWMON_VDD_1P8 0x1d +#define GSC_HWMON_VDD_2P5 0x23 +#define GSC_HWMON_VDD_1P0 0x20 + +/* + * I2C transactions to the GSC are done via these functions which + * perform retries in the case of a busy GSC NAK'ing the transaction + */ +int gsc_i2c_read(struct i2c_client *client, u32 addr, u8 *buf, u16 count); +int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count); diff --git a/arch/arm/boards/gateworks-ventana/lowlevel.c b/arch/arm/boards/gateworks-ventana/lowlevel.c new file mode 100644 index 0000000000..10b2c4c780 --- /dev/null +++ b/arch/arm/boards/gateworks-ventana/lowlevel.c @@ -0,0 +1,18 @@ +#include <common.h> +#include <sizes.h> +#include <mach/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> + +extern char __dtb_imx6q_gw54xx_start[]; + +ENTRY_FUNCTION(start_imx6q_gw54xx_1gx64, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_imx6q_gw54xx_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} diff --git a/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg b/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg new file mode 100644 index 0000000000..daf01a8ad1 --- /dev/null +++ b/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg @@ -0,0 +1,41 @@ +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00190017 +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00140026 +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x0021001C +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x0011001D + +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43380347 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x433C034D +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x032C0324 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03310232 + +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x3C313539 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x37343141 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x36393C39 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x42344438 + +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227 + +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 + +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDCFG0 0x54597955 +wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDASP 0x0000007F +wm 32 MX6_MMDC_P0_MDMISC 0x00011740 +wm 32 MX6_MMDC_P0_MDOR 0x00591023 +wm 32 MX6_MMDC_P0_MDCTL 0x831A0000 +wm 32 MX6_MMDC_P0_MDSCR 0x02088032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00408031 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xA1390003 +wm 32 MX6_MMDC_P0_MDREF 0x00007800 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/gateworks-ventana/ram-base.imxcfg b/arch/arm/boards/gateworks-ventana/ram-base.imxcfg new file mode 100644 index 0000000000..07dc34c0bb --- /dev/null +++ b/arch/arm/boards/gateworks-ventana/ram-base.imxcfg @@ -0,0 +1,56 @@ +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 + +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 + +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 + +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 + +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 + +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 + +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 + +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 diff --git a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg new file mode 100644 index 0000000000..b5c59e3c3c --- /dev/null +++ b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg @@ -0,0 +1,101 @@ +/* MDMISC mirroring interleaved (row/bank/col) */ +wm 32 MX6_MMDC_P0_MDMISC 0x00000742 +check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 + +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 + +wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 +check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 + +wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333 +wm 32 MX6_MMDC_P0_MDCFG1 0x926e8a63 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x00431023 +wm 32 MX6_MMDC_P0_MDOTC 0x1b333030 +wm 32 MX6_MMDC_P0_MDPDC 0x0002006d +wm 32 MX6_MMDC_P1_MDPDC 0x0002006d +wm 32 MX6_MMDC_P0_MDASP 0x00000027 + +wm 32 MX6_MMDC_P0_MDSCR 0x05208030 +wm 32 MX6_MMDC_P0_MDSCR 0x00048031 +wm 32 MX6_MMDC_P0_MDSCR 0x00408032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDREF 0x0000c000 +wm 32 MX6_MMDC_P0_MDSCR 0x00008020 + +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022222 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022222 + +wm 32 MX6_MMDC_P0_MPPDCMPR2 0x00000003 +wm 32 MX6_MMDC_P0_MAPSR 0x00001007 +wm 32 MX6_MMDC_P0_MDSCR 0x04008010 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 + +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390001 +check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1380000 + +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001e001e +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001e001e +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001e001e + +wm 32 MX6_MMDC_P0_MDSCR 0x00048033 +wm 32 MX6_IOM_DRAM_SDQS0 0x00007030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00007030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00007030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00007030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00007030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00007030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00007030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00007030 + +wm 32 MX6_MMDC_P0_MDSCR 0x00008020 +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 + +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x40404040 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x40404040 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x40404040 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 + +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x50800000 +check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000 + +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 + +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 +wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 + +check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f + +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f + +wm 32 MX6_MMDC_P0_MDSCR 0x04008050 +wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 +check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b +wm 32 MX6_MMDC_P0_MDREF 0x00001800 +wm 32 MX6_MMDC_P0_MAPSR 0x00001006 +wm 32 MX6_MMDC_P0_MDPDC 0x0002556d +wm 32 MX6_MMDC_P1_MDPDC 0x0002556d +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/Makefile b/arch/arm/boards/karo-tx6x/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/karo-tx6x/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/karo-tx6x/board.c b/arch/arm/boards/karo-tx6x/board.c new file mode 100644 index 0000000000..6d9dd9a505 --- /dev/null +++ b/arch/arm/boards/karo-tx6x/board.c @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar, Pengutronix + * + * + * with the PMIC init code taken from u-boot + * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <gpio.h> +#include <init.h> +#include <i2c/i2c.h> +#include <linux/clk.h> +#include <environment.h> +#include <mach/bbu.h> +#include <mach/imx6.h> +#include <mfd/imx6q-iomuxc-gpr.h> + +#define ETH_PHY_RST IMX_GPIO_NR(7, 6) +#define ETH_PHY_PWR IMX_GPIO_NR(3, 20) +#define ETH_PHY_INT IMX_GPIO_NR(7, 1) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d)) + +#define LTC3676_BUCK1 0x01 +#define LTC3676_BUCK2 0x02 +#define LTC3676_BUCK3 0x03 +#define LTC3676_BUCK4 0x04 +#define LTC3676_DVB1A 0x0A +#define LTC3676_DVB1B 0x0B +#define LTC3676_DVB2A 0x0C +#define LTC3676_DVB2B 0x0D +#define LTC3676_DVB3A 0x0E +#define LTC3676_DVB3B 0x0F +#define LTC3676_DVB4A 0x10 +#define LTC3676_DVB4B 0x11 +#define LTC3676_MSKPG 0x13 +#define LTC3676_CLIRQ 0x1f + +#define LTC3676_BUCK_DVDT_FAST (1 << 0) +#define LTC3676_BUCK_KEEP_ALIVE (1 << 1) +#define LTC3676_BUCK_CLK_RATE_LOW (1 << 2) +#define LTC3676_BUCK_PHASE_SEL (1 << 3) +#define LTC3676_BUCK_ENABLE_300 (1 << 4) +#define LTC3676_BUCK_PULSE_SKIP (0 << 5) +#define LTC3676_BUCK_BURST_MODE (1 << 5) +#define LTC3676_BUCK_CONTINUOUS (2 << 5) +#define LTC3676_BUCK_ENABLE (1 << 7) + +#define LTC3676_PGOOD_MASK (1 << 5) + +#define LTC3676_MSKPG_BUCK1 (1 << 0) +#define LTC3676_MSKPG_BUCK2 (1 << 1) +#define LTC3676_MSKPG_BUCK3 (1 << 2) +#define LTC3676_MSKPG_BUCK4 (1 << 3) +#define LTC3676_MSKPG_LDO2 (1 << 5) +#define LTC3676_MSKPG_LDO3 (1 << 6) +#define LTC3676_MSKPG_LDO4 (1 << 7) + +#define VDD_IO_VAL mV_to_regval(vout_to_vref(3300 * 10, 5)) +#define VDD_IO_VAL_LP mV_to_regval(vout_to_vref(3100 * 10, 5)) +#define VDD_IO_VAL_2 mV_to_regval(vout_to_vref(3300 * 10, 5_2)) +#define VDD_IO_VAL_2_LP mV_to_regval(vout_to_vref(3100 * 10, 5_2)) +#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1425 * 10, 6)) +#define VDD_SOC_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 6)) +#define VDD_DDR_VAL mV_to_regval(vout_to_vref(1500 * 10, 7)) +#define VDD_DDR_VAL_LP mV_to_regval(vout_to_vref(1500 * 10, 7)) +#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1425 * 10, 8)) +#define VDD_CORE_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 8)) + +/* LDO1 */ +#define R1_1 470 +#define R2_1 150 +/* LDO4 */ +#define R1_4 470 +#define R2_4 150 +/* Buck1 */ +#define R1_5 390 +#define R2_5 110 +#define R1_5_2 470 +#define R2_5_2 150 +/* Buck2 (SOC) */ +#define R1_6 150 +#define R2_6 180 +/* Buck3 (DDR) */ +#define R1_7 150 +#define R2_7 140 +/* Buck4 (CORE) */ +#define R1_8 150 +#define R2_8 180 + +/* calculate voltages in 10mV */ +#define R1(idx) R1_##idx +#define R2(idx) R2_##idx + +#define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx))) +#define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx)) + +#define mV_to_regval(mV) DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125) +#define regval_to_mV(v) (((v) * 125 + 4125)) + +static struct ltc3673_regs { + u8 addr; + u8 val; + u8 mask; +} ltc3676_regs[] = { + { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, }, + { LTC3676_DVB2B, VDD_SOC_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, }, + { LTC3676_DVB3B, VDD_DDR_VAL_LP, ~0x3f, }, + { LTC3676_DVB4B, VDD_CORE_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, }, + { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, }, + { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, }, + { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, }, + { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, }, + { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, }, + { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, }, + { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, }, + { LTC3676_CLIRQ, 0, }, /* clear interrupt status */ +}; + +static struct ltc3673_regs ltc3676_regs_2[] = { + { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, }, + { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, }, +}; + + +static int setup_pmic_voltages(void) +{ + struct i2c_adapter *adapter = NULL; + struct i2c_client client; + int addr = 0x3c; + int bus = 0; + int i; + struct ltc3673_regs *r; + + adapter = i2c_get_adapter(bus); + if (!adapter) { + pr_err("i2c bus %d not found\n", bus); + return -ENODEV; + } + + client.adapter = adapter; + client.addr = addr; + + r = ltc3676_regs; + + for (i = 0; i < ARRAY_SIZE(ltc3676_regs); i++, r++) { + if (i2c_write_reg(&client, r->addr, &r->val, 1) != 1) { + pr_err("i2c write error\n"); + return -EIO; + } + } + + r = ltc3676_regs_2; + + for (i = 0; i < ARRAY_SIZE(ltc3676_regs_2); i++, r++) { + if (i2c_write_reg(&client, r->addr, &r->val, 1) != 1) { + pr_err("i2c write error\n"); + return -EIO; + } + } + + return 0; +} + +static void eth_init(void) +{ + void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR; + uint32_t val; + + val = readl(iomux + IOMUXC_GPR1); + val |= IMX6Q_GPR1_ENET_CLK_SEL_ANATOP; + writel(val, iomux + IOMUXC_GPR1); +} + +static int tx6x_devices_init(void) +{ + if (!of_machine_is_compatible("karo,imx6dl-tx6dl") && + !of_machine_is_compatible("karo,imx6q-tx6q")) + return 0; + + barebox_set_hostname("tx6u"); + + eth_init(); + + setup_pmic_voltages(); + + imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + + return 0; +} +device_initcall(tx6x_devices_init); diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg new file mode 100644 index 0000000000..2a1c42aeed --- /dev/null +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg @@ -0,0 +1,10 @@ +soc imx6 +loadaddr 0x20000000 +dcdofs 0x400 + +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx6-ccm-regs.h> + +#include "ram-base.imxcfg" +#include "1600mhz_4x128mx16.imxcfg" diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c new file mode 100644 index 0000000000..00008d403c --- /dev/null +++ b/arch/arm/boards/karo-tx6x/lowlevel.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <debug_ll.h> +#include <common.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <image-metadata.h> +#include <mach/generic.h> +#include <sizes.h> + +static inline void setup_uart(void) +{ + void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR; + void __iomem *uartbase = (void *)MX6_UART1_BASE_ADDR; + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + writel(0x1, iomuxbase + 0x0314); + writel(0x1, iomuxbase + 0x0318); + writel(0x1, iomuxbase + 0x0330); + writel(0x1, iomuxbase + 0x032c); + + writel(0xffffffff, ccmbase + 0x68); + writel(0xffffffff, ccmbase + 0x6c); + writel(0xffffffff, ccmbase + 0x70); + writel(0xffffffff, ccmbase + 0x74); + writel(0xffffffff, ccmbase + 0x78); + writel(0xffffffff, ccmbase + 0x7c); + writel(0xffffffff, ccmbase + 0x80); + + writel(0x00000000, uartbase + 0x80); + writel(0x00004027, uartbase + 0x84); + writel(0x00000784, uartbase + 0x88); + writel(0x00000a81, uartbase + 0x90); + writel(0x0000002b, uartbase + 0x9c); + writel(0x0001b0b0, uartbase + 0xb0); + writel(0x0000047f, uartbase + 0xa4); + writel(0x0000c34f, uartbase + 0xa8); + writel(0x00000001, uartbase + 0x80); + + putc_ll('>'); +} + +extern char __dtb_imx6dl_tx6u_801x_start[]; + +BAREBOX_IMD_TAG_STRING(tx6x_mx6_memsize_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0); + +ENTRY_FUNCTION(start_imx6dl_tx6x_1g, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + arm_setup_stack(0x00920000 - 8); + + IMD_USED(tx6x_mx6_memsize_1G); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_imx6dl_tx6u_801x_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} diff --git a/arch/arm/boards/karo-tx6x/ram-base.imxcfg b/arch/arm/boards/karo-tx6x/ram-base.imxcfg new file mode 100644 index 0000000000..e912fb0f2b --- /dev/null +++ b/arch/arm/boards/karo-tx6x/ram-base.imxcfg @@ -0,0 +1,71 @@ +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 + +wm 32 MX6_IOM_DRAM_ADDR00 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR01 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR02 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR03 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR04 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR05 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR06 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR07 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR08 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR09 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR10 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR11 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR12 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR13 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR14 0x00000000 +wm 32 MX6_IOM_DRAM_ADDR15 0x00000000 + +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 + +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDBA0 0x00000000 +wm 32 MX6_IOM_DRAM_SDBA1 0x00000000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 + +/* (differential input) */ +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +/* disable ddr pullups */ +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +/* (differential input) */ +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_CTLDS 0x00000030 + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00002000 +/* GRP_DDRHYS */ +wm 32 MX6_IOM_GRP_DDRHYS 0x00000000 + +/* Read data DQ Byte0-3 delay */ +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 diff --git a/arch/arm/boards/phytec-phycard-imx6/Makefile b/arch/arm/boards/phytec-phycard-imx6/Makefile index 01c7a259e9..de67f04dde 100644 --- a/arch/arm/boards/phytec-phycard-imx6/Makefile +++ b/arch/arm/boards/phytec-phycard-imx6/Makefile @@ -1,2 +1,3 @@ obj-y += board.o lwl-y += lowlevel.o +bbenv-y += defaultenv-phycard-imx6 diff --git a/arch/arm/boards/phytec-phycard-imx6/board.c b/arch/arm/boards/phytec-phycard-imx6/board.c index d425b48347..27b84aa1b8 100644 --- a/arch/arm/boards/phytec-phycard-imx6/board.c +++ b/arch/arm/boards/phytec-phycard-imx6/board.c @@ -17,6 +17,7 @@ * */ +#include <envfs.h> #include <environment.h> #include <bootsource.h> #include <common.h> @@ -44,6 +45,8 @@ static int phytec_pcaaxl3_init(void) imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + defaultenv_append_directory(defaultenv_phycard_imx6); + return 0; } device_initcall(phytec_pcaaxl3_init); diff --git a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/nand b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/nand new file mode 100644 index 0000000000..3f3a9aa2fc --- /dev/null +++ b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/nand @@ -0,0 +1,7 @@ +#!/bin/sh + +global.bootm.image="/dev/nand0.kernel.bb" +global.bootm.oftree="/dev/nand0.oftree.bb" +bootargs-ip +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" + diff --git a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/sd-ext3 b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/sd-ext3 new file mode 100644 index 0000000000..fd35fe0c74 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/sd-ext3 @@ -0,0 +1,6 @@ +#!/bin/sh + +global.bootm.image="/mnt/mmc/linuximage" +global.bootm.oftree="/mnt/mmc/oftree" +bootargs-ip +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait rw" diff --git a/arch/arm/boards/phytec-phycard-imx6/env/config-board b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/config-board index 44008aa3e7..4d7b37c313 100644 --- a/arch/arm/boards/phytec-phycard-imx6/env/config-board +++ b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/config-board @@ -3,5 +3,7 @@ # board defaults, do not change in running system. Change /env/config # instead +global.boot.default=nand + global.hostname=phyCARD-i.MX6 global.linux.bootargs.base="console=ttymxc2,115200" diff --git a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/init/automount b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/init/automount new file mode 100644 index 0000000000..49d99bd78d --- /dev/null +++ b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/init/automount @@ -0,0 +1,14 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +mkdir -p /mnt/mmc +automount -d /mnt/mmc 'mmc2.probe=1 && [ -e /dev/mmc2.0 ] && mount /dev/mmc2.0 /mnt/mmc' diff --git a/arch/arm/boards/phytec-phycard-imx6/env/boot/nand b/arch/arm/boards/phytec-phycard-imx6/env/boot/nand deleted file mode 100644 index cf3b25c11d..0000000000 --- a/arch/arm/boards/phytec-phycard-imx6/env/boot/nand +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" -bootargs-ip -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" - diff --git a/arch/arm/boards/phytec-phycard-imx6/env/boot/sd-ext3 b/arch/arm/boards/phytec-phycard-imx6/env/boot/sd-ext3 deleted file mode 100644 index 443563390c..0000000000 --- a/arch/arm/boards/phytec-phycard-imx6/env/boot/sd-ext3 +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -global.bootm.image="/mnt/kernel/linuximage" -#global.bootm.oftree="/boot/oftree" -bootargs-ip -global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" diff --git a/arch/arm/boards/phytec-phycore-am335x/board.c b/arch/arm/boards/phytec-phycore-am335x/board.c index 9482b80ed7..035866b969 100644 --- a/arch/arm/boards/phytec-phycore-am335x/board.c +++ b/arch/arm/boards/phytec-phycore-am335x/board.c @@ -78,8 +78,10 @@ static int pcm051_devices_init(void) defaultenv_append_directory(defaultenv_phycore_am335x); am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload"); + am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox"); am33xx_bbu_nand_xloadslots_register_handler("MLO.nand", xloadslots, ARRAY_SIZE(xloadslots)); + am33xx_bbu_nand_register_handler("nand", "/dev/nand0.barebox.bb"); return 0; } diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c index ff1f04e87f..66bae806c4 100644 --- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c @@ -16,15 +16,15 @@ #include <debug_ll.h> static const struct am33xx_cmd_control pcm051_cmd = { - .slave_ratio0 = 0x40, + .slave_ratio0 = 0x80, .dll_lock_diff0 = 0x0, - .invert_clkout0 = 0x1, - .slave_ratio1 = 0x40, + .invert_clkout0 = 0x0, + .slave_ratio1 = 0x80, .dll_lock_diff1 = 0x0, - .invert_clkout1 = 0x1, - .slave_ratio2 = 0x40, + .invert_clkout1 = 0x0, + .slave_ratio2 = 0x80, .dll_lock_diff2 = 0x0, - .invert_clkout2 = 0x1, + .invert_clkout2 = 0x0, }; struct pcm051_sdram_timings { @@ -33,66 +33,86 @@ struct pcm051_sdram_timings { }; enum { - MT41J128M16125IT_1x256M16, - MT41J64M1615IT_1x128M16, - MT41J256M16HA15EIT_1x512M16, + MT41J128M16125IT_256MB, + MT41J64M1615IT_128MB, + MT41J256M16HA15EIT_512MB, + MT41J512M8125IT_2x512MB, }; struct pcm051_sdram_timings timings[] = { - /* 1x256M16 */ - [MT41J128M16125IT_1x256M16] = { + /* 256MB */ + [MT41J128M16125IT_256MB] = { .regs = { - .emif_read_latency = 0x6, - .emif_tim1 = 0x0888A39B, - .emif_tim2 = 0x26337FDA, - .emif_tim3 = 0x501F830F, - .sdram_config = 0x61C04AB2, + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAD4DB, + .emif_tim2 = 0x26437FDA, + .emif_tim3 = 0x501F83FF, + .sdram_config = 0x61C052B2, .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x0000093B, + .sdram_ref_ctrl = 0x00000C30, }, .data = { .rd_slave_ratio0 = 0x3B, - .wr_dqs_slave_ratio0 = 0x3B, - .fifo_we_slave_ratio0 = 0x97, - .wr_slave_ratio0 = 0x76, + .wr_dqs_slave_ratio0 = 0x33, + .fifo_we_slave_ratio0 = 0x9c, + .wr_slave_ratio0 = 0x6f, }, }, - /* 1x128M16 */ - [MT41J64M1615IT_1x128M16] = { + /* 128MB */ + [MT41J64M1615IT_128MB] = { .regs = { - .emif_read_latency = 0x6, - .emif_tim1 = 0x0888A39B, - .emif_tim2 = 0x26247FDA, - .emif_tim3 = 0x501F821F, - .sdram_config = 0x61C04A32, + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x262F7FDA, + .emif_tim3 = 0x501F82BF, + .sdram_config = 0x61C05232, .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x0000093B, + .sdram_ref_ctrl = 0x00000C30, }, .data = { - .rd_slave_ratio0 = 0x3A, - .wr_dqs_slave_ratio0 = 0x36, + .rd_slave_ratio0 = 0x38, + .wr_dqs_slave_ratio0 = 0x34, .fifo_we_slave_ratio0 = 0xA2, - .wr_slave_ratio0 = 0x74, + .wr_slave_ratio0 = 0x72, }, }, - /* 1x512MB */ - [MT41J256M16HA15EIT_1x512M16] = { + /* 512MB */ + [MT41J256M16HA15EIT_512MB] = { .regs = { - .emif_read_latency = 0x6, - .emif_tim1 = 0x0888A39B, - .emif_tim2 = 0x26517FDA, - .emif_tim3 = 0x501F84EF, - .sdram_config = 0x61C04B32, + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x266B7FDA, + .emif_tim3 = 0x501F867F, + .sdram_config = 0x61C05332, .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x0000093B, + .sdram_ref_ctrl = 0x00000C30 }, .data = { - .rd_slave_ratio0 = 0x3B, - .wr_dqs_slave_ratio0 = 0x3B, - .fifo_we_slave_ratio0 = 0x96, - .wr_slave_ratio0 = 0x76, + .rd_slave_ratio0 = 0x35, + .wr_dqs_slave_ratio0 = 0x43, + .fifo_we_slave_ratio0 = 0x97, + .wr_slave_ratio0 = 0x7b, + }, + }, + + /* 1024MB */ + [MT41J512M8125IT_2x512MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x266B7FDA, + .emif_tim3 = 0x501F867F, + .sdram_config = 0x61C053B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30 + }, + .data = { + .rd_slave_ratio0 = 0x32, + .wr_dqs_slave_ratio0 = 0x48, + .fifo_we_slave_ratio0 = 0x99, + .wr_slave_ratio0 = 0x80, }, }, }; @@ -122,7 +142,7 @@ static noinline void pcm051_board_init(int sdram) writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); - am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303); + am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_400); am335x_sdram_init(0x18B, &pcm051_cmd, &timing->regs, @@ -154,19 +174,24 @@ static noinline void pcm051_board_entry(unsigned long bootinfo, int sdram) pcm051_board_init(sdram); } -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x256m16, bootinfo, r1, r2) +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_256mb, bootinfo, r1, r2) +{ + pcm051_board_entry(bootinfo, MT41J128M16125IT_256MB); +} + +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_128mb, bootinfo, r1, r2) { - pcm051_board_entry(bootinfo, MT41J128M16125IT_1x256M16); + pcm051_board_entry(bootinfo, MT41J64M1615IT_128MB); } -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x128m16, bootinfo, r1, r2) +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_512mb, bootinfo, r1, r2) { - pcm051_board_entry(bootinfo, MT41J64M1615IT_1x128M16); + pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_512MB); } -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x512m16, bootinfo, r1, r2) +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_2x512mb, bootinfo, r1, r2) { - pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_1x512M16); + pcm051_board_entry(bootinfo, MT41J512M8125IT_2x512MB); } ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2) diff --git a/arch/arm/boards/phytec-phyflex-imx6/Makefile b/arch/arm/boards/phytec-phyflex-imx6/Makefile index 01c7a259e9..11e1c7dc38 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/Makefile +++ b/arch/arm/boards/phytec-phyflex-imx6/Makefile @@ -1,2 +1,3 @@ obj-y += board.o lwl-y += lowlevel.o +bbenv-y += defaultenv-phyflex-imx6 diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c index 94e3f6fcf1..09a5c79a9a 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/board.c +++ b/arch/arm/boards/phytec-phyflex-imx6/board.c @@ -17,6 +17,9 @@ * */ +#include <envfs.h> +#include <environment.h> +#include <bootsource.h> #include <common.h> #include <gpio.h> #include <init.h> @@ -29,8 +32,6 @@ #include <mach/iomux-mx6.h> #include <mach/imx6.h> -#define ETH_PHY_RST IMX_GPIO_NR(3, 23) - #define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \ MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS @@ -62,27 +63,9 @@ static void phyflex_err006282_workaround(void) gpio_direction_input(MX6_PHYFLEX_ERR006282); } -static int eth_phy_reset(void) -{ - gpio_request(ETH_PHY_RST, "phy reset"); - gpio_direction_output(ETH_PHY_RST, 0); - mdelay(1); - gpio_set_value(ETH_PHY_RST, 1); - - return 0; -} - -static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) -{ - phy_write(dev, 0x0d, device); - phy_write(dev, 0x0e, reg); - phy_write(dev, 0x0d, (1 << 14) | device); - phy_write(dev, 0x0e, val); -} - static int ksz9031rn_phy_fixup(struct phy_device *dev) { - mmd_write_reg(dev, 2, 8, 0x039F); + phy_write_mmd_indirect(dev, 8, 2, 0x039F); return 0; } @@ -96,12 +79,26 @@ static int phytec_pfla02_init(void) phyflex_err006282_workaround(); - eth_phy_reset(); phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, ksz9031rn_phy_fixup); imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + of_device_enable_path("/chosen/environment-sd"); + break; + case BOOTSOURCE_NAND: + of_device_enable_path("/chosen/environment-nand"); + break; + default: + case BOOTSOURCE_SPI: + of_device_enable_path("/chosen/environment-spinor"); + break; + } + + defaultenv_append_directory(defaultenv_phyflex_imx6); + return 0; } device_initcall(phytec_pfla02_init); diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/nand b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/nand new file mode 100644 index 0000000000..79dc03c34a --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/nand @@ -0,0 +1,6 @@ +#!/bin/sh + +global.bootm.image="/dev/nand0.kernel.bb" +global.bootm.oftree="/dev/nand0.oftree.bb" +bootargs-ip +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/sd-ext3 b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/sd-ext3 new file mode 100644 index 0000000000..fd35fe0c74 --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/sd-ext3 @@ -0,0 +1,6 @@ +#!/bin/sh + +global.bootm.image="/mnt/mmc/linuximage" +global.bootm.oftree="/mnt/mmc/oftree" +bootargs-ip +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait rw" diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/config-board b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/config-board new file mode 100644 index 0000000000..b40a4de8c7 --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/config-board @@ -0,0 +1,9 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.boot.default=nand + +global.hostname=phyFLEX-i.MX6 +global.linux.bootargs.base="console=ttymxc3,115200" diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/init/automount b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/init/automount new file mode 100644 index 0000000000..49d99bd78d --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/init/automount @@ -0,0 +1,14 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +mkdir -p /mnt/mmc +automount -d /mnt/mmc 'mmc2.probe=1 && [ -e /dev/mmc2.0 ] && mount /dev/mmc2.0 /mnt/mmc' diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg index d73207c364..f6061f25b4 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg @@ -1,3 +1,5 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x3c409b85 #define SETUP_1GIB_2GIB_4GIB \ wm 32 0x021b0040 0x00000017; \ diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg index 2291b71e8c..2bfa836c4f 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg @@ -1,3 +1,5 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x565c9b85 #define SETUP_1GIB_2GIB_4GIB \ wm 32 0x021b0040 0x00000027; \ diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg index c6dc775d8f..491f89357c 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg @@ -1,6 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x8c929b85 #define SETUP_1GIB_2GIB_4GIB \ - wm 32 0x021b0040 0x00000047; \ - wm 32 0x021b0000 0xC41A0000 + wm 32 0x021b0040 0x00000047; \ + wm 32 0x021b0000 0xC41A0000 #include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h index 138ae36ee3..98b3c1869b 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h @@ -2,46 +2,60 @@ soc imx6 loadaddr 0x20000000 dcdofs 0x400 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 -wm 32 0x020e057c 0x00020030 +wm 32 0x020e0798 0x000C0000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 wm 32 0x020e0590 0x00003000 wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 +wm 32 0x020e078c 0x00000030 wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 +wm 32 0x020e05a8 0x00000028 +wm 32 0x020e05b0 0x00000028 +wm 32 0x020e0524 0x00000028 +wm 32 0x020e051c 0x00000028 +wm 32 0x020e0518 0x00000028 +wm 32 0x020e050c 0x00000028 +wm 32 0x020e05b8 0x00000028 +wm 32 0x020e05c0 0x00000028 wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0798 0x000c0000 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e0788 0x00000028 +wm 32 0x020e0794 0x00000028 +wm 32 0x020e079c 0x00000028 +wm 32 0x020e07a0 0x00000028 +wm 32 0x020e07a4 0x00000028 +wm 32 0x020e07a8 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e05ac 0x00000028 +wm 32 0x020e05b4 0x00000028 +wm 32 0x020e0528 0x00000028 +wm 32 0x020e0520 0x00000028 +wm 32 0x020e0514 0x00000028 +wm 32 0x020e0510 0x00000028 +wm 32 0x020e05bc 0x00000028 +wm 32 0x020e05c4 0x00000028 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b080c 0x00110011 +wm 32 0x021b0810 0x00240024 +wm 32 0x021b480c 0x00260038 +wm 32 0x021b4810 0x002C0038 +wm 32 0x021b083c 0x03400350 +wm 32 0x021b0840 0x03440340 +wm 32 0x021b483c 0x034C0354 +wm 32 0x021b4840 0x035C033C +wm 32 0x021b0848 0x322A2A2A +wm 32 0x021b4848 0x302C2834 +wm 32 0x021b0850 0x34303834 +wm 32 0x021b4850 0x422A3E36 wm 32 0x021b081c 0x33333333 wm 32 0x021b0820 0x33333333 wm 32 0x021b0824 0x33333333 @@ -50,15 +64,19 @@ wm 32 0x021b481c 0x33333333 wm 32 0x021b4820 0x33333333 wm 32 0x021b4824 0x33333333 wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00081740 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0008 0x09444040 + +SETUP_MDCFG0 + +wm 32 0x021b0010 0xff538f64 +wm 32 0x021b0014 0x01ff0124 +wm 32 0x021b0018 0x00091740 wm 32 0x021b001c 0x00008000 -wm 32 0x021b000c 0x555a7975 -wm 32 0x021b0010 0xff538e64 -wm 32 0x021b0014 0x01ff00db wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x005b0e21 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 +wm 32 0x021b0030 0x003F1023 SETUP_1GIB_2GIB_4GIB @@ -66,34 +84,19 @@ wm 32 0x021b001c 0x04088032 wm 32 0x021b001c 0x0408803a wm 32 0x021b001c 0x00008033 wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x00048039 wm 32 0x021b001c 0x09408030 wm 32 0x021b001c 0x09408038 wm 32 0x021b001c 0x04008040 wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1380003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00022227 -wm 32 0x021b4818 0x00022227 -wm 32 0x021b083c 0x433c033f -wm 32 0x021b0840 0x033e033d -wm 32 0x021b483c 0x43490351 -wm 32 0x021b4840 0x0344032f -wm 32 0x021b0848 0x4a434146 -wm 32 0x021b4848 0x4745434b -wm 32 0x021b0850 0x3d3d433a -wm 32 0x021b4850 0x48334b3e -wm 32 0x021b080c 0x000f0011 -wm 32 0x021b0810 0x00200022 -wm 32 0x021b480c 0x0033002e -wm 32 0x021b4810 0x003e003b -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 +wm 32 0x021b0020 0x00007800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b0004 0x00025576 wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 wm 32 0x020e0010 0xf00000ff -wm 32 0x020e0018 0x007f007f -wm 32 0x020e001c 0x007f007f +wm 32 0x020e0018 0x007F007F +wm 32 0x020e001c 0x007F007F wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg index e5a729223f..dfd4336f06 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg @@ -1,3 +1,5 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x8c929b85 #define SETUP_S_DL_512MB_1GB \ wm 32 0x021b0040 0x00000017; \ diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h index 0f83bc9964..8fbd66141a 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h @@ -2,46 +2,60 @@ soc imx6 loadaddr 0x20000000 dcdofs 0x400 -wm 32 0x020e04bc 0x00000030 -wm 32 0x020e04c0 0x00000030 -wm 32 0x020e04c4 0x00000030 -wm 32 0x020e04c8 0x00000030 -wm 32 0x020e04cc 0x00000030 -wm 32 0x020e04d0 0x00000030 -wm 32 0x020e04d4 0x00000030 -wm 32 0x020e04d8 0x00000030 -wm 32 0x020e0470 0x00020030 -wm 32 0x020e0474 0x00020030 -wm 32 0x020e0478 0x00020030 -wm 32 0x020e047c 0x00020030 -wm 32 0x020e0480 0x00020030 -wm 32 0x020e0484 0x00020030 -wm 32 0x020e0488 0x00020030 -wm 32 0x020e048c 0x00020030 -wm 32 0x020e0464 0x00020030 -wm 32 0x020e0490 0x00020030 -wm 32 0x020e04ac 0x00020030 -wm 32 0x020e04b0 0x00020030 -wm 32 0x020e0494 0x00020030 +wm 32 0x020e0774 0x000C0000 +wm 32 0x020e0754 0x00000000 +wm 32 0x020e04ac 0x00000030 +wm 32 0x020e04b0 0x00000030 +wm 32 0x020e0464 0x00000030 +wm 32 0x020e0490 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0494 0x00000030 +wm 32 0x020e04a0 0x00000000 +wm 32 0x020e04b4 0x00000030 +wm 32 0x020e04b8 0x00000030 wm 32 0x020e04a4 0x00003000 wm 32 0x020e04a8 0x00003000 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e04b4 0x00003030 -wm 32 0x020e04b8 0x00003030 -wm 32 0x020e0764 0x00000030 -wm 32 0x020e0770 0x00000030 -wm 32 0x020e0778 0x00000030 -wm 32 0x020e077c 0x00000030 -wm 32 0x020e0780 0x00000030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 +wm 32 0x020e076c 0x00000030 wm 32 0x020e0750 0x00020000 -wm 32 0x020e0754 0x00000000 +wm 32 0x020e04bc 0x00000028 +wm 32 0x020e04c0 0x00000028 +wm 32 0x020e04c4 0x00000028 +wm 32 0x020e04c8 0x00000028 +wm 32 0x020e04cc 0x00000028 +wm 32 0x020e04d0 0x00000028 +wm 32 0x020e04d4 0x00000028 +wm 32 0x020e04d8 0x00000028 wm 32 0x020e0760 0x00020000 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0774 0x000c0000 +wm 32 0x020e0764 0x00000028 +wm 32 0x020e0770 0x00000028 +wm 32 0x020e0778 0x00000028 +wm 32 0x020e077c 0x00000028 +wm 32 0x020e0780 0x00000028 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e078c 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e0470 0x00000028 +wm 32 0x020e0474 0x00000028 +wm 32 0x020e0478 0x00000028 +wm 32 0x020e047c 0x00000028 +wm 32 0x020e0480 0x00000028 +wm 32 0x020e0484 0x00000028 +wm 32 0x020e0488 0x00000028 +wm 32 0x020e048c 0x00000028 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b080c 0x00110011 +wm 32 0x021b0810 0x00240024 +wm 32 0x021b480c 0x00260038 +wm 32 0x021b4810 0x002C0038 +wm 32 0x021b083c 0x02480248 +wm 32 0x021b0840 0x022f022d +wm 32 0x021b483c 0x02540258 +wm 32 0x021b4840 0x0236021e +wm 32 0x021b0848 0x332f3033 +wm 32 0x021b4848 0x302d2c35 +wm 32 0x021b0850 0x3030362a +wm 32 0x021b4850 0x3423372d wm 32 0x021b081c 0x33333333 wm 32 0x021b0820 0x33333333 wm 32 0x021b0824 0x33333333 @@ -50,15 +64,19 @@ wm 32 0x021b481c 0x33333333 wm 32 0x021b4820 0x33333333 wm 32 0x021b4824 0x33333333 wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00081740 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0008 0x09444040 + +SETUP_MDCFG0 + +wm 32 0x021b0010 0xff538f64 +wm 32 0x021b0014 0x01ff0124 +wm 32 0x021b0018 0x00091740 wm 32 0x021b001c 0x00008000 -wm 32 0x021b000c 0x555a7975 -wm 32 0x021b0010 0xff538e64 -wm 32 0x021b0014 0x01ff00db wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x005b0e21 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 +wm 32 0x021b0030 0x003F1023 SETUP_S_DL_512MB_1GB @@ -72,24 +90,9 @@ wm 32 0x021b001c 0x09408030 wm 32 0x021b001c 0x09408038 wm 32 0x021b001c 0x04008040 wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1380003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b0020 0x00005800 +wm 32 0x021b0020 0x00007800 wm 32 0x021b0818 0x00011117 wm 32 0x021b4818 0x00011117 -wm 32 0x021b083c 0x422D0230 -wm 32 0x021b0840 0x022F022E -wm 32 0x021b483c 0x4237023D -wm 32 0x021b4840 0x02340224 -wm 32 0x021b0848 0x38333135 -wm 32 0x021b4848 0x36353338 -wm 32 0x021b0850 0x2E2E332C -wm 32 0x021b4850 0x3727382F -wm 32 0x021b080c 0x000C000D -wm 32 0x021b0810 0x0018001A -wm 32 0x021b480c 0x00270023 -wm 32 0x021b4810 0x002F002D -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 +wm 32 0x021b0004 0x00025576 wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg index 3116e3613d..2e428f9fd0 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg @@ -1,3 +1,5 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x565c9b85 #define SETUP_S_DL_512MB_1GB \ wm 32 0x021b0040 0x00000017; \ diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c index 1d08f0561a..84014d772a 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c @@ -63,7 +63,7 @@ BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_1G, IMD_TYPE_PARAMETER, "memsize=1024 BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_2G, IMD_TYPE_PARAMETER, "memsize=2048", 0); BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_4G, IMD_TYPE_PARAMETER, "memsize=4096", 0); -ENTRY_FUNCTION(start_phytec_pbab01_1gib, r0, r1, r2) +static void __noreturn start_imx6q_phytec_pbab01_common(uint32_t size) { void *fdt; @@ -71,17 +71,16 @@ ENTRY_FUNCTION(start_phytec_pbab01_1gib, r0, r1, r2) arm_setup_stack(0x00920000 - 8); - IMD_USED(phyflex_mx6_memsize_1G); - if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); fdt = __dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); - barebox_arm_entry(0x10000000, SZ_1G, fdt); + barebox_arm_entry(0x10000000, size, fdt); } -ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2) + +static void __noreturn start_imx6dl_phytec_pbab01_common(uint32_t size) { void *fdt; @@ -89,44 +88,37 @@ ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2) arm_setup_stack(0x00920000 - 8); - IMD_USED(phyflex_mx6_memsize_2G); + fdt = __dtb_imx6dl_phytec_pbab01_start - get_runtime_offset(); - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); + barebox_arm_entry(0x10000000, size, fdt); +} - fdt = __dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); +ENTRY_FUNCTION(start_phytec_pbab01_1gib, r0, r1, r2) +{ + IMD_USED(phyflex_mx6_memsize_1G); - barebox_arm_entry(0x10000000, SZ_2G, fdt); + start_imx6q_phytec_pbab01_common(SZ_1G); } -ENTRY_FUNCTION(start_phytec_pbab01_4gib, r0, r1, r2) +ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2) { - void *fdt; - - imx6_cpu_lowlevel_init(); + IMD_USED(phyflex_mx6_memsize_2G); - arm_setup_stack(0x00920000 - 8); + start_imx6q_phytec_pbab01_common(SZ_2G); +} +ENTRY_FUNCTION(start_phytec_pbab01_4gib, r0, r1, r2) +{ IMD_USED(phyflex_mx6_memsize_4G); - fdt = __dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); - - barebox_arm_entry(0x10000000, 0xEFFFFFF8, fdt); + start_imx6q_phytec_pbab01_common(0xEFFFFFF8); } ENTRY_FUNCTION(start_phytec_pbab01dl_1gib, r0, r1, r2) { - void *fdt; - - imx6_cpu_lowlevel_init(); - - arm_setup_stack(0x00920000 - 8); - IMD_USED(phyflex_mx6_memsize_1G); - fdt = __dtb_imx6dl_phytec_pbab01_start - get_runtime_offset(); - - barebox_arm_entry(0x10000000, SZ_1G, fdt); + start_imx6dl_phytec_pbab01_common(SZ_1G); } ENTRY_FUNCTION(start_phytec_pbab01s_512mb, r0, r1, r2) diff --git a/arch/arm/boards/sama5d4ek/Makefile b/arch/arm/boards/sama5d4ek/Makefile new file mode 100644 index 0000000000..4363b39243 --- /dev/null +++ b/arch/arm/boards/sama5d4ek/Makefile @@ -0,0 +1 @@ +obj-y += sama5d4ek.o diff --git a/arch/arm/boards/sama5d4ek/env/bin/init_board b/arch/arm/boards/sama5d4ek/env/bin/init_board new file mode 100644 index 0000000000..f3d417e356 --- /dev/null +++ b/arch/arm/boards/sama5d4ek/env/bin/init_board @@ -0,0 +1,15 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + +exit 1 diff --git a/arch/arm/boards/sama5d4ek/env/config b/arch/arm/boards/sama5d4ek/env/config new file mode 100644 index 0000000000..1007345b9b --- /dev/null +++ b/arch/arm/boards/sama5d4ek/env/config @@ -0,0 +1,42 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=nfs +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net +# can be either 'nfs', 'tftp', 'nand' or empty +oftree_loc=nfs + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type +ubiroot=rootfs + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +kernelimage=zImage +#kernelimage=uImage +#kernelimage=Image +#kernelimage=Image.lzo + +nand_device=atmel_nand +nand_parts="256k(at91bootstrap),512k(barebox)ro,256k(bareboxenv),256k(bareboxenv2),256k(spare),512k(oftree),6M(kernel),-(rootfs)" +rootfs_mtdblock_nand=7 + +m25p80_parts="64k(bootstrap),384k(barebox),256k(bareboxenv),256k(bareboxenv2),128k(oftree),-(updater)" + +autoboot_timeout=3 + +bootargs="console=ttyS0,115200" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# " diff --git a/arch/arm/boards/sama5d4ek/sama5d4ek.c b/arch/arm/boards/sama5d4ek/sama5d4ek.c new file mode 100644 index 0000000000..91cffa3b48 --- /dev/null +++ b/arch/arm/boards/sama5d4ek/sama5d4ek.c @@ -0,0 +1,317 @@ +/* + * SAMA5D4EK board configureation. + * + * Copyright (C) 2014 Atmel Corporation, + * Bo Shen <voice.shen@atmel.com> + * + * Licensed under GPLv2 or later. + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <asm/armlinux.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <io.h> +#include <mach/hardware.h> +#include <nand.h> +#include <sizes.h> +#include <linux/mtd/nand.h> +#include <mach/board.h> +#include <mach/at91sam9_smc.h> +#include <gpio.h> +#include <mach/iomux.h> +#include <mach/at91_pmc.h> +#include <mach/at91_rstc.h> +#include <mach/at91sam9x5_matrix.h> +#include <input/qt1070.h> +#include <readkey.h> +#include <spi/spi.h> +#include <linux/clk.h> + +#if defined(CONFIG_NAND_ATMEL) +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = -EINVAL, + .enable_pin = -EINVAL, + .ecc_mode = NAND_ECC_HW, + .pmecc_sector_size = 512, + .pmecc_corr_cap = 8, + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config cm_nand_smc_config = { + .ncs_read_setup = 1, + .nrd_setup = 1, + .ncs_write_setup = 1, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 2, + .ncs_write_pulse = 3, + .nwe_pulse = 2, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 3, + + .tclr = 2, + .tadl = 7, + .tar = 2, + .ocms = 0, + .trr = 3, + .twb = 7, + .rbnsel = 3, + .nfsel = 1, +}; + +static void ek_add_device_nand(void) +{ + struct clk *clk = clk_get(NULL, "smc_clk"); + + clk_enable(clk); + + /* configure chip-select 3 (NAND) */ + sama5_smc_configure(0, 3, &cm_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} +#else +static void ek_add_device_nand(void) {} +#endif + +#if defined(CONFIG_DRIVER_NET_MACB) +static struct macb_platform_data macb0_pdata = { + .phy_interface = PHY_INTERFACE_MODE_RMII, + .phy_addr = 0, +}; + +static void ek_add_device_eth(void) +{ + at91_add_device_eth(0, &macb0_pdata); +} +#else +static void ek_add_device_eth(void) {} +#endif + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "LG", + .refresh = 60, + .xres = 800, .yres = 480, + .pixclock = KHZ2PICOS(33260), + + .left_margin = 88, .right_margin = 168, + .upper_margin = 8, .lower_margin = 37, + .hsync_len = 128, .vsync_len = 2, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +/* Output mode is TFT 18 bits */ +#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_18BPP) + +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static void ek_add_device_lcdc(void) +{ + at91_add_device_lcdc(&ek_lcdc_data); +} +#else +static void ek_add_device_lcdc(void) {} +#endif + +#if defined(CONFIG_MCI_ATMEL) +static struct atmel_mci_platform_data mci1_data = { + .bus_width = 4, + .detect_pin = AT91_PIN_PE6, + .wp_pin = -EINVAL, +}; + +static void ek_add_device_mci(void) +{ + /* MMC1 */ + at91_add_device_mci(1, &mci1_data); + + /* power on MCI1 */ + at91_set_gpio_output(AT91_PIN_PE15, 0); +} +#else +static void ek_add_device_mci(void) {} +#endif + +#if defined(CONFIG_I2C_GPIO) +struct qt1070_platform_data qt1070_pdata = { + .irq_pin = AT91_PIN_PE25, +}; + +static struct i2c_board_info i2c_devices[] = { + { + .platform_data = &qt1070_pdata, + I2C_BOARD_INFO("qt1070", 0x1b), + }, +}; + +static void ek_add_device_i2c(void) +{ + at91_set_gpio_input(qt1070_pdata.irq_pin, 0); + at91_set_deglitch(qt1070_pdata.irq_pin, 1); + at91_add_device_i2c(0, i2c_devices, ARRAY_SIZE(i2c_devices)); +} +#else +static void ek_add_device_i2c(void) {} +#endif + +#if defined(CONFIG_DRIVER_SPI_ATMEL) +static const struct spi_board_info ek_spi_devices[] = { + { + .name = "m25p80", + .chip_select = 0, + .max_speed_hz = 30 * 1000 * 1000, + .bus_num = 0, + } +}; + +static unsigned spi0_standard_cs[] = { AT91_PIN_PC3 }; +static struct at91_spi_platform_data spi_pdata = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +}; + +static void ek_add_device_spi(void) +{ + spi_register_board_info(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); + at91_add_device_spi(0, &spi_pdata); +} +#else +static void ek_add_device_spi(void) {} +#endif + +#ifdef CONFIG_LED_GPIO +struct gpio_led leds[] = { + { + .gpio = AT91_PIN_PE28, + .active_low = 0, + .led = { + .name = "d8", + }, + }, { + .gpio = AT91_PIN_PE9, + .active_low = 1, + .led = { + .name = "d9", + }, + }, { + .gpio = AT91_PIN_PE8, + .active_low = 0, + .led = { + .name = "d10", + }, + }, +}; + +static void ek_add_led(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(leds); i++) { + at91_set_gpio_output(leds[i].gpio, leds[i].active_low); + led_gpio_register(&leds[i]); + } + led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); +} +#else +static void ek_add_led(void) {} +#endif + +static int sama5d4ek_mem_init(void) +{ + at91_add_device_sdram(0); + + return 0; +} +mem_initcall(sama5d4ek_mem_init); + +static const struct devfs_partition sama5d4ek_nand0_partitions[] = { + { + .offset = 0x00000, + .size = SZ_256K, + .flags = DEVFS_PARTITION_FIXED, + .name = "at91bootstrap_raw", + .bbname = "at91bootstrap", + }, { + .offset = DEVFS_PARTITION_APPEND, + .size = SZ_512K, + .flags = DEVFS_PARTITION_FIXED, + .name = "bootloader_raw", + .bbname = "bootloader", + }, { + .offset = DEVFS_PARTITION_APPEND, + .size = SZ_256K, + .flags = DEVFS_PARTITION_FIXED, + .name = "env_raw", + .bbname = "env0", + }, { + .offset = DEVFS_PARTITION_APPEND, + .size = SZ_256K, + .flags = DEVFS_PARTITION_FIXED, + .name = "env_raw1", + .bbname = "env1", + }, { + /* sentinel */ + } +}; + +static int sama5d4ek_devices_init(void) +{ + ek_add_device_i2c(); + ek_add_device_nand(); + ek_add_led(); + ek_add_device_eth(); + ek_add_device_spi(); + ek_add_device_mci(); + ek_add_device_lcdc(); + + devfs_create_partitions("nand0", sama5d4ek_nand0_partitions); + + return 0; +} +device_initcall(sama5d4ek_devices_init); + +static int sama5d4ek_console_init(void) +{ + barebox_set_model("Atmel sama5d4ek"); + barebox_set_hostname("sama5d4ek"); + + at91_register_uart(4, 0); + + return 0; +} +console_initcall(sama5d4ek_console_init); + +static int sama5d4ek_main_clock(void) +{ + at91_set_main_clock(12000000); + + return 0; +} +pure_initcall(sama5d4ek_main_clock); diff --git a/arch/arm/configs/am335x_defconfig b/arch/arm/configs/am335x_defconfig index 4dc6cbf127..6ef9c838fd 100644 --- a/arch/arm/configs/am335x_defconfig +++ b/arch/arm/configs/am335x_defconfig @@ -1,7 +1,8 @@ CONFIG_ARCH_OMAP=y CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO=y -CONFIG_BAREBOX_UPDATE_AM33XX_NAND_XLOADSLOTS=y +CONFIG_BAREBOX_UPDATE_AM33XX_NAND=y CONFIG_OMAP_MULTI_BOARDS=y +CONFIG_MACH_AFI_GF=y CONFIG_MACH_BEAGLEBONE=y CONFIG_MACH_PCM051=y CONFIG_THUMB2_BAREBOX=y @@ -74,6 +75,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_LED=y CONFIG_CMD_SPI=y CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_USBGADGET=y CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y @@ -88,6 +90,9 @@ CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y CONFIG_DRIVER_NET_CPSW=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y +CONFIG_NET_USB_SMSC95XX=y CONFIG_DRIVER_SPI_OMAP3=y CONFIG_I2C=y CONFIG_I2C_OMAP=y @@ -97,6 +102,15 @@ CONFIG_NAND=y CONFIG_NAND_OMAP_GPMC=y CONFIG_MTD_UBI=y CONFIG_USB_HOST=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DFU=y +CONFIG_USB_GADGET_SERIAL=y +CONFIG_USB_GADGET_FASTBOOT=y +CONFIG_USB_MUSB=y +CONFIG_USB_MUSB_AM335X=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_GADGET=y CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_OMAP_HSMMC=y diff --git a/arch/arm/configs/am335x_mlo_defconfig b/arch/arm/configs/am335x_mlo_defconfig index 19f78d0ae8..dee8c5bd43 100644 --- a/arch/arm/configs/am335x_mlo_defconfig +++ b/arch/arm/configs/am335x_mlo_defconfig @@ -1,6 +1,7 @@ CONFIG_ARCH_OMAP=y CONFIG_OMAP_BUILD_IFT=y CONFIG_OMAP_MULTI_BOARDS=y +CONFIG_MACH_AFI_GF=y CONFIG_MACH_BEAGLEBONE=y CONFIG_MACH_PCM051=y CONFIG_THUMB2_BAREBOX=y diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig index 7569cde6f5..4c83102ce1 100644 --- a/arch/arm/configs/eukrea_cpuimx35_defconfig +++ b/arch/arm/configs/eukrea_cpuimx35_defconfig @@ -1,71 +1,81 @@ CONFIG_ARCH_IMX=y -CONFIG_CACHE_L2X0=y -CONFIG_ARCH_IMX35=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_MACH_EUKREA_CPUIMX35=y CONFIG_IMX_IIM=y CONFIG_IMX_IIM_FUSE_BLOW=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_PBL_RELOCATABLE=y CONFIG_MMU=y -CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_MALLOC_SIZE=0x800000 CONFIG_EXPERIMENTAL=y CONFIG_MALLOC_TLSF=y -CONFIG_LONGHELP=y +CONFIG_RELOCATABLE=y CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y -# CONFIG_CONSOLE_ACTIVATE_FIRST is not set CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_COMPRESSION_LZO=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx35/env" -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_AUTOMOUNT=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_MEMINFO=y +CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_FLASH=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_RESET=y CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_RESET=y CONFIG_CMD_PARTITION=y +CONFIG_CMD_AUTOMOUNT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y CONFIG_CMD_SPLASH=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y CONFIG_CMD_I2C=y CONFIG_CMD_LED=y CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_USBGADGET=y +CONFIG_CMD_OFTREE=y CONFIG_NET=y -CONFIG_CMD_DHCP=y CONFIG_NET_NFS=y -CONFIG_CMD_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y CONFIG_NET_NETCONSOLE=y CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_SMSC_PHY=y # CONFIG_SPI is not set CONFIG_I2C=y CONFIG_I2C_IMX=y CONFIG_MTD=y CONFIG_MTD_RAW_DEVICE=y CONFIG_NAND=y +CONFIG_NAND_ALLOW_ERASE_BAD=y CONFIG_NAND_IMX=y +CONFIG_NAND_IMX_BBM=y CONFIG_USB_HOST=y CONFIG_USB_EHCI=y CONFIG_USB_STORAGE=y @@ -79,6 +89,7 @@ CONFIG_MCI_IMX_ESDHC=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_TRIGGERS=y +CONFIG_FS_TFTP=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/globalscale_guruplug_defconfig b/arch/arm/configs/globalscale_guruplug_defconfig deleted file mode 100644 index d21de45c5d..0000000000 --- a/arch/arm/configs/globalscale_guruplug_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_TEXT_BASE=0x2000000 -CONFIG_DEBUG_LL=y -CONFIG_CMD_RESET=y -CONFIG_DRIVER_SERIAL_NS16550=y diff --git a/arch/arm/configs/globalscale_mirabox_defconfig b/arch/arm/configs/globalscale_mirabox_defconfig deleted file mode 100644 index ed9d94d867..0000000000 --- a/arch/arm/configs/globalscale_mirabox_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_ARCH_MVEBU=y -CONFIG_AEABI=y -CONFIG_DEBUG_LL=y -CONFIG_CMD_LOADY=y -CONFIG_CMD_LOADS=y -CONFIG_CMD_RESET=y -CONFIG_CMD_CLK=y -CONFIG_DRIVER_SERIAL_NS16550=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index cad47fdff3..2c8eb856cf 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -1,6 +1,7 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y CONFIG_MACH_EFIKA_MX_SMARTBOOK=y +CONFIG_MACH_EMBEDSKY_E9=y CONFIG_MACH_FREESCALE_MX51_PDK=y CONFIG_MACH_FREESCALE_MX53_LOCO=y CONFIG_MACH_TQMA53=y @@ -16,10 +17,10 @@ CONFIG_MACH_SABRELITE=y CONFIG_MACH_SABRESD=y CONFIG_MACH_NITROGEN6X=y CONFIG_MACH_SOLIDRUN_MICROSOM=y -CONFIG_MACH_EMBEDSKY_E9=y CONFIG_MACH_EMBEST_RIOTBOARD=y CONFIG_MACH_UDOO=y CONFIG_MACH_VARISCITE_MX6=y +CONFIG_MACH_GW_VENTANA=y CONFIG_IMX_IIM=y CONFIG_IMX_IIM_FUSE_BLOW=y CONFIG_IMX_OCOTP=y diff --git a/arch/arm/configs/marvell_armada_xp_gp_defconfig b/arch/arm/configs/marvell_armada_xp_gp_defconfig deleted file mode 100644 index 5a7ef52b5f..0000000000 --- a/arch/arm/configs/marvell_armada_xp_gp_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_ARMADA_XP=y -CONFIG_MACH_MARVELL_ARMADA_XP_GP=y -CONFIG_AEABI=y -CONFIG_DEBUG_LL=y -CONFIG_CMD_LOADY=y -CONFIG_CMD_LOADS=y -CONFIG_CMD_RESET=y -CONFIG_CMD_CLK=y -CONFIG_DRIVER_SERIAL_NS16550=y diff --git a/arch/arm/configs/solidrun_cubox_defconfig b/arch/arm/configs/mvebu_defconfig index 7ba42a98ef..253cb0934d 100644 --- a/arch/arm/configs/solidrun_cubox_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -1,84 +1,101 @@ CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_DOVE=y -CONFIG_THUMB2_BAREBOX=y -CONFIG_CMD_ARM_MMUINFO=y +CONFIG_MACH_GLOBALSCALE_MIRABOX=y +CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3=y +CONFIG_MACH_MARVELL_ARMADA_XP_GP=y +CONFIG_MACH_SOLIDRUN_CUBOX=y +CONFIG_MACH_GLOBALSCALE_GURUPLUG=y +CONFIG_MACH_USI_TOPKICK=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y CONFIG_TEXT_BASE=0x0 CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y CONFIG_RELOCATABLE=y -CONFIG_LONGHELP=y CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMD_GETOPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y +CONFIG_BLSPEC=y +CONFIG_IMD_TARGET=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_PARTITION_DISK_EFI=y -CONFIG_DEBUG_LL=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_LET=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_GLOBAL=y -CONFIG_CMD_AUTOMOUNT=y -CONFIG_CMD_BASENAME=y -CONFIG_CMD_DIRNAME=y -CONFIG_CMD_LN=y -CONFIG_CMD_READLINK=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_LOADY=y -CONFIG_CMD_LOADS=y -CONFIG_CMD_MEMINFO=y +CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_SHA1SUM=y -CONFIG_CMD_SHA256SUM=y -CONFIG_CMD_SHA224SUM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_CMD_BOOT=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -CONFIG_FLEXIBLE_BOOTARGS=y -CONFIG_CMD_RESET=y CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y CONFIG_CMD_PARTITION=y +CONFIG_CMD_AUTOMOUNT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_GLOBAL=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_BASENAME=y +CONFIG_CMD_DIRNAME=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_READLINK=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SHA224SUM=y +CONFIG_CMD_SHA256SUM=y CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_GETOPT=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_HOST=y +CONFIG_NET_CMD_IFUP=y +CONFIG_CMD_PING=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_MENUTREE=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y CONFIG_CMD_LED=y +CONFIG_CMD_SPI=y CONFIG_CMD_LED_TRIGGER=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y CONFIG_CMD_WD=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y CONFIG_OFDEVICE=y CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_NET_ORION=y +CONFIG_MARVELL_PHY=y CONFIG_DRIVER_SPI_MVEBU=y CONFIG_I2C=y +CONFIG_I2C_MV64XXX=y CONFIG_MTD=y CONFIG_MTD_M25P80=y +CONFIG_NAND=y +CONFIG_NAND_ORION=y CONFIG_DISK_AHCI=y CONFIG_USB_HOST=y CONFIG_USB_EHCI=y @@ -87,8 +104,14 @@ CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_MMC_BOOT_PARTITIONS=y CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y CONFIG_LED_TRIGGERS=y +CONFIG_EEPROM_AT25=y +CONFIG_KEYBOARD_GPIO=y CONFIG_WATCHDOG=y +CONFIG_GPIO_ORION=y +CONFIG_PCI_MVEBU=y CONFIG_FS_CRAMFS=y CONFIG_FS_EXT4=y CONFIG_FS_FAT=y diff --git a/arch/arm/configs/plathome_openblocks_ax3_defconfig b/arch/arm/configs/plathome_openblocks_ax3_defconfig deleted file mode 100644 index 95449c9741..0000000000 --- a/arch/arm/configs/plathome_openblocks_ax3_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_ARMADA_XP=y -CONFIG_AEABI=y -CONFIG_DEBUG_LL=y -CONFIG_CMD_LOADY=y -CONFIG_CMD_LOADS=y -CONFIG_CMD_RESET=y -CONFIG_CMD_CLK=y -CONFIG_DRIVER_SERIAL_NS16550=y diff --git a/arch/arm/configs/sama5d4ek_defconfig b/arch/arm/configs/sama5d4ek_defconfig new file mode 100644 index 0000000000..bbf254abf0 --- /dev/null +++ b/arch/arm/configs/sama5d4ek_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARCH_SAMA5D4=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000 +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x26f00000 +CONFIG_MALLOC_SIZE=0xA00000 +CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y +CONFIG_PROMPT="A5D4EK:" +CONFIG_GLOB=y +CONFIG_PROMPT_HUSH_PS2="y" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/sama5d4ek/env" +CONFIG_DEBUG_INFO=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_LONGHELP=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_SPI=y +CONFIG_CMD_OFTREE=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_OFDEVICE=y +CONFIG_DRIVER_NET_MACB=y +CONFIG_MICREL_PHY=y +CONFIG_DRIVER_SPI_ATMEL=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +CONFIG_MTD_RAW_DEVICE=y +CONFIG_MTD_M25P80=y +CONFIG_NAND=y +# CONFIG_NAND_ECC_SOFT is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +CONFIG_NAND_ATMEL=y +CONFIG_NAND_ATMEL_PMECC=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_ATMEL_HLCD=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_ATMEL=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_TRIGGERS=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_QT1070=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_PNG=y diff --git a/arch/arm/configs/tqma53_defconfig b/arch/arm/configs/tqma53_defconfig index f163b7c701..144abbf5fb 100644 --- a/arch/arm/configs/tqma53_defconfig +++ b/arch/arm/configs/tqma53_defconfig @@ -19,7 +19,6 @@ CONFIG_AUTO_COMPLETE=y CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/tqma53/env/" CONFIG_DEBUG_INFO=y CONFIG_CMD_EDIT=y CONFIG_CMD_SLEEP=y diff --git a/arch/arm/configs/tx53stk5_defconfig b/arch/arm/configs/tx53stk5_defconfig index fc6a9a69ff..5751623295 100644 --- a/arch/arm/configs/tx53stk5_defconfig +++ b/arch/arm/configs/tx53stk5_defconfig @@ -20,7 +20,6 @@ CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/karo-tx53/env" CONFIG_RESET_SOURCE=y CONFIG_CMD_EDIT=y CONFIG_CMD_SLEEP=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dcf014db97..3fcd5f1cc0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -5,6 +5,7 @@ obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o # created. obj-y += empty.o +pbl-dtb-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o pbl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o pbl-dtb-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o pbl-dtb-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o @@ -17,6 +18,7 @@ pbl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o pbl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o +pbl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o pbl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o pbl-dtb-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o pbl-dtb-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o @@ -41,6 +43,7 @@ pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o pbl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o pbl-dtb-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o pbl-dtb-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o +pbl-dtb-$(CONFIG_MACH_TX6X) += imx6dl-tx6u-801x.dtb.o pbl-dtb-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o pbl-dtb-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o pbl-dtb-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o diff --git a/arch/arm/dts/am335x-afi-gf.dts b/arch/arm/dts/am335x-afi-gf.dts new file mode 100644 index 0000000000..479c6cf170 --- /dev/null +++ b/arch/arm/dts/am335x-afi-gf.dts @@ -0,0 +1,559 @@ +/* + * Copyright (C) Jan Luebbe <jlu@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "GF"; + compatible = "afi,gf", "ti,am33xx"; + + chosen { + stdout-path = &uart2; + + environment@0 { + compatible = "barebox,environment"; + device-path = &environment_spi; + }; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 128 MB */ + }; + + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + linux,code = <116>; /* KEY_POWER */ + gpios = <&gpio0 26 1>; + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + gpios = <&gpio1 18 0>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + gpios = <&gpio1 19 0>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led3 { + gpios = <&gpio0 22 0>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + onewire-internal { + compatible = "w1-gpio"; + gpios = <&gpio1 3 0>; + }; + + vdd_5v_reg: vdd-5v@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&uart0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + tps: tps@2d { + reg = <0x2d>; + interrupt-parent = <&gpio0>; + interrupts = <27 1>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + ds2483@18 { + compatible = "maxim,ds2482"; + reg = <0x18>; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +/include/ "tps65910.dtsi" + +&tps { + vcc1-supply = <&vdd_5v_reg>; + vcc2-supply = <&vdd_5v_reg>; + vcc3-supply = <&vdd_5v_reg>; + vcc4-supply = <&vdd_5v_reg>; + vcc5-supply = <&vdd_5v_reg>; + vcc6-supply = <&vdd_5v_reg>; + vcc7-supply = <&vdd_5v_reg>; + vccio-supply = <&vdd_5v_reg>; + + ti,system-power-controller; + + ti,en-ck32k-xtal; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + /* VDD_DDR supplies LPDDR */ + regulator-name = "vdd_ddr"; + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + /* VDD_BOOST is not connected */ + }; + + vdig1_reg: regulator@5 { + /* VDD_DIG1 is not connected */ + }; + + vdig2_reg: regulator@6 { + /* VDD_DIG2 supplies some SoC terminals */ + regulator-always-on; + }; + + vpll_reg: regulator@7 { + /* VDD_PLL is not connected */ + }; + + vdac_reg: regulator@8 { + /* VDD_DAC is not connected */ + }; + + vaux1_reg: regulator@9 { + /* VDD_AUX1 supplies USB */ + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + /* VDD_AUX2 supplies various ICs */ + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + /* VDD_AUX33 supplies USB */ + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + /* VDD_MMC supplies uSD and ethernet phy */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vbb_reg: regulator@13 { + /* Backup Battery regulator */ + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmc_reg>; + cd-gpios = <&gpio1 14 1>; + status = "okay"; +}; + +&edma { + ti,edma-xbar-event-map = <32 12>; +}; + +&dcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_pins>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_pins>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio3_pins>; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + /* uncomment for unmodified Fee */ + /* ti,pindir-d0-out-d1-in; */ + + spi_nor: nor@0 { + compatible = "nymonyx,n25q128a13"; + spi-max-frequency = <48000000>; // actually 108 MHz + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "mlo"; + reg = <0x0 0x20000>; + }; + + partition@20000 { + label = "boot"; + reg = <0x20000 0x100000>; + }; + + environment_spi: partition@120000 { + label = "environment"; + reg = <0x120000 0x20000>; + }; + }; + + fram@1 { + compatible = "ramtron,fm25cl64b", "atmel,at25"; + spi-max-frequency = <20000000>; + reg = <1>; + size = <8192>; + pagesize = <8192>; // FIXME - is this correct? + address-width = <16>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + + ti,pindir-d0-out-d1-in; + + spi1_0: spidev@0 { + compatible = "linux,spidev"; + reg = <0>; + spi-max-frequency = <10000000>; // FIXME + }; + + spi1_1: spidev@1 { + compatible = "linux,spidev"; + reg = <1>; + spi-max-frequency = <10000000>; // FIXME + }; +}; + +&usb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins &usb1_pins>; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&mac { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rmii"; +}; + +&davinci_mdio { + status = "okay"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +&am33xx_pinmux { + dcan0_pins: pinmux_dcan0_pins { + pinctrl-single,pins = < + 0x11c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* mii1_txd3.dcan0_tx_mux0, OUTPUT_PULLUP | MODE1 */ + 0x120 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_txd2.dcan0_rx_mux0, INPUT_PULLUP | MODE1 */ + >; + }; + eth_pins: pinmux_eth_pins { + pinctrl-single,pins = < + /* RMII2 (mezzanine) */ + 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen, OUTPUT_PULLDOWN | MODE3 */ + 0x050 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1, INPUT_PULLDOWN | MODE3 */ + 0x054 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0, INPUT_PULLDOWN | MODE3 */ + 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a10.rmii2_rxd1, INPUT_PULLDOWN | MODE3 */ + 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a11.rmii2_rxd0, INPUT_PULLDOWN | MODE3 */ + 0x070 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv, INPUT_PULLUP | MODE3 */ /* PHYAD pin */ + 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxer, INPUT_PULLUP | MODE3 */ + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_col.rmii2_refclk, INPUT_PULLDOWN | MODE1 */ + /* RMII1 (board) */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv, INPUT_PULLDOWN | MODE1 */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_er.rmii1_rxer, INPUT_PULLDOWN | MODE1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen, OUTPUT_PULLDOWN | MODE1 */ + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1, INPUT_PULLDOWN | MODE1 */ + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0, INPUT_PULLDOWN | MODE1 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1, INPUT_PULLDOWN | MODE1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0, INPUT_PULLDOWN | MODE1 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk, INPUT_PULLDOWN | MODE0 */ + /* MDIO (board & mezzanine) */ + 0x148 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio.mdio_data, INPUT_PULLUP | MODE0 */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdc.mdio_clk, OUTPUT_PULLUP | MODE0 */ + >; + }; + spi0_pins: pinmux_spi0_pins { /* SPI NOR-Flash & FRAM */ + pinctrl-single,pins = < + 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk, INPUT_PULLUP | MODE0 */ + 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0, INPUT_PULLUP | MODE0 */ + 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1, INPUT_PULLUP | MODE0 */ + 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0, OUTPUT_PULLUP | MODE0 */ + 0x160 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs1, OUTPUT_PULLUP | MODE0 */ + >; + }; + spi1_pins: pinmux_spi1_pins { /* SPI (mezzanine) */ + pinctrl-single,pins = < + 0x170 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* uart0_rxd.spi1_cs0_mux3, OUTPUT_PULLUP | MODE1 */ + 0x174 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* uart0_txd.spi1_cs1_mux3, OUTPUT_PULLUP | MODE1 */ + 0x190 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk_mux2, INPUT_PULLUP | MODE3 */ + 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_fsx.spi1_d0_mux2, INPUT_PULLUP | MODE3 */ + 0x198 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_axr0.spi1_d1_mux2, INPUT_PULLUP | MODE3 */ + >; + }; + usb0_pins: pinmux_usb0_pins { /* USB-HOST (mezzanine) */ + pinctrl-single,pins = < + 0x208 (PIN_INPUT | MUX_MODE0) /* usb0_dm, INPUT | MODE0 */ + 0x20c (PIN_INPUT | MUX_MODE0) /* usb0_dp, INPUT | MODE0 */ + 0x210 (PIN_INPUT | MUX_MODE0) /* usb0_ce, INPUT | MODE0 */ + 0x214 (PIN_INPUT | MUX_MODE0) /* usb0_id, INPUT | MODE0 */ + 0x218 (PIN_INPUT | MUX_MODE0) /* usb0_vbus, INPUT | MODE0 */ + 0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus, OUTPUT_PULLDOWN | MODE0 */ + >; + }; + usb1_pins: pinmux_usb1_pins { /* USB-OTG (front) */ + pinctrl-single,pins = < + 0x220 (PIN_INPUT | MUX_MODE0) /* usb1_dm, INPUT | MODE0 */ + 0x224 (PIN_INPUT | MUX_MODE0) /* usb1_dp, INPUT | MODE0 */ + 0x228 (PIN_INPUT | MUX_MODE0) /* usb1_ce, INPUT | MODE0 */ + 0x22c (PIN_INPUT | MUX_MODE0) /* usb1_id, INPUT | MODE0 */ + 0x230 (PIN_INPUT | MUX_MODE0) /* usb1_vbus, INPUT | MODE0 */ + 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus, OUTPUT_PULLDOWN | MODE0 */ + >; + }; + uart0_pins: pinmux_uart0_pins { /* debug, later spi1 CS1/2 */ + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd */ + >; + }; + uart1_pins: pinmux_uart1_pins { /* UART1 (PRU) */ + pinctrl-single,pins = < + 0x180 (PIN_INPUT | MUX_MODE5) /* uart1_rxd.pr1_uart0_rxd_mux1, INPUT | MODE5 (RS485_RXD)*/ + 0x184 (PIN_OUTPUT | MUX_MODE5) /* uart1_txd.pr1_uart0_txd_mux1, OUTPUT | MODE5 (RS485_TXD) */ + >; + }; + uart2_pins: pinmux_uart2_pins { /* UART2 (console) */ + pinctrl-single,pins = < + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_clk.uart2_rxd_mux0, INPUT_PULLDOWN | MODE1 (UART2_RXD) */ + 0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_clk.uart2_txd_mux0, OUTPUT_PULLDOWN | MODE1 (UART2_TXD) */ + >; + }; + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ + >; + }; + i2c1_pins: pinmux_i2c1_pins { /* 1-wire */ + pinctrl-single,pins = < + 0x168 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_ctsn.i2c1_sda_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x16c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_rtsn.i2c1_scl_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + >; + }; + i2c2_pins: pinmux_i2c2_pins { /* (mezzanine) */ + pinctrl-single,pins = < + 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + >; + }; + gpio0_pins: pinmux_gpio0_pins { + pinctrl-single,pins = < + 0x020 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.gpio0[22], OUTPUT_PULLDOWN | MODE7 (LED3) */ /* PWM later */ + 0x024 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.gpio0[23], INPUT_PULLDOWN | MODE7 (RMII2_INTRP) */ + 0x028 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad10.gpio0[26], INPUT_PULLUP | MODE7 (BUTTON0) */ + 0x02c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.gpio0[27], INPUT_PULLDOWN | MODE7 (PWR_INT)*/ + 0x0d0 (PIN_INPUT | MUX_MODE7) /* lcd_data12.gpio0[8], INPUT | MODE7 (SYSBOOT12) */ + 0x0d4 (PIN_INPUT | MUX_MODE7) /* lcd_data13.gpio0[9], INPUT | MODE7 (SYSBOOT13) */ + 0x0d8 (PIN_INPUT | MUX_MODE7) /* lcd_data14.gpio0[10], INPUT | MODE7 (SYSBOOT14) */ + 0x0dc (PIN_INPUT | MUX_MODE7) /* lcd_data15.gpio0[11], INPUT | MODE7 (SYSBOOT15) */ + 0x164 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0[7], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO0) */ + 0x1b4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* xdma_event_intr1.gpio0[20], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO3) */ + >; + }; + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + 0x000 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1[0], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x004 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1[1], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x008 (PIN_INPUT | MUX_MODE7) /* gpmc_ad2.gpio1[2], INPUT | MODE7 (BOARD_REV1) */ + 0x00c (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad3.gpio1[3], INPUT_PULLUP | MODE7 (1WIRE_INT) */ + 0x010 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1[4], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x014 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1[5], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x018 (PIN_INPUT | MUX_MODE7) /* gpmc_ad6.gpio1[6], INPUT | MODE7 (BOARD_REV0) */ + 0x01c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1[7], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x030 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad12.gpio1[12], INPUT_PULLUP | MODE7 (PG_24V) */ + 0x034 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x038 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad14.gpio1[14], INPUT_PULLUP | MODE7 (SDCARD_CD) */ + 0x03c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x044 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.gpio1[17], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x048 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.gpio1[18], OUTPUT_PULLDOWN | MODE7 (LED1) */ /* PWM later */ + 0x04c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.gpio1[19], OUTPUT_PULLDOWN | MODE7 (LED2) */ /* PWM later */ + 0x058 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1[22], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x05c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1[23], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x060 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.gpio1[24], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x064 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1[25], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28], INPUT_PULLUP | MODE7 (USB1_OCn) */ + 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn0.gpio1[29], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x080 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1[30], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x084 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1[31], OUTPUT_PULLDOWN | MODE7 (NC) */ + >; + }; + gpio2_pins: pinmux_gpio2_pins { + pinctrl-single,pins = < + 0x088 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2[0], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x08c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.gpio2[1], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x090 (PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2[2], INPUT | MODE7 (BOARD_REV2) */ + 0x094 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2[3], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x098 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_wen.gpio2[4], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2[5], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x0a0 (PIN_INPUT | MUX_MODE7) /* lcd_data0.gpio2[6], INPUT | MODE7 (SYSBOOT0) */ + 0x0a4 (PIN_INPUT | MUX_MODE7) /* lcd_data1.gpio2[7], INPUT | MODE7 (SYSBOOT1) */ + 0x0a8 (PIN_INPUT | MUX_MODE7) /* lcd_data2.gpio2[8], INPUT | MODE7 (SYSBOOT2) */ + 0x0ac (PIN_INPUT | MUX_MODE7) /* lcd_data3.gpio2[9], INPUT | MODE7 (SYSBOOT3) */ + 0x0b0 (PIN_INPUT | MUX_MODE7) /* lcd_data4.gpio2[10], INPUT | MODE7 (SYSBOOT4) */ + 0x0b4 (PIN_INPUT | MUX_MODE7) /* lcd_data5.gpio2[11], INPUT | MODE7 (SYSBOOT5) */ + 0x0b8 (PIN_INPUT | MUX_MODE7) /* lcd_data6.gpio2[12], INPUT | MODE7 (SYSBOOT6) */ + 0x0bc (PIN_INPUT | MUX_MODE7) /* lcd_data7.gpio2[13], INPUT | MODE7 (SYSBOOT7) */ + 0x0c0 (PIN_INPUT | MUX_MODE7) /* lcd_data8.gpio2[14], INPUT | MODE7 (SYSBOOT8) */ + 0x0c4 (PIN_INPUT | MUX_MODE7) /* lcd_data9.gpio2[15], INPUT | MODE7 (SYSBOOT9) */ + 0x0c8 (PIN_INPUT | MUX_MODE7) /* lcd_data10.gpio2[16], INPUT | MODE7 (SYSBOOT10) */ + 0x0cc (PIN_INPUT | MUX_MODE7) /* lcd_data11.gpio2[17], INPUT | MODE7 (SYSBOOT11) */ + 0x0e0 (PIN_INPUT | MUX_MODE7) /* lcd_vsync.gpio2[22], INPUT | MODE7 (BOARD_CONF1) */ + 0x0e4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x0e8 (PIN_INPUT | MUX_MODE7) /* lcd_pclk.gpio2[24], INPUT | MODE7 (BOARD_CONF0) */ + 0x0ec (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x134 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd3.gpio2[18], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd2.gpio2[19], OUTPUT_PULLDOWN | MODE7 (NC) */ + >; + }; + gpio3_pins: pinmux_gpio3_pins { + pinctrl-single,pins = < + 0x118 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_rx_dv.gpio3[4], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x19c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.gpio3[17], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO1) */ + 0x1a0 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], OUTPUT_PULLUP | MODE7 (DCAN0_LBK) */ /* enable loopback by default */ + 0x1a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsr.gpio3[19], OUTPUT_PULLDOWN | MODE7 (RS485_DE) */ + 0x1a8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_axr1.gpio3[20], OUTPUT_PULLUP | MODE7 (1WIRE_SLEEP) */ + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3[21], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO2) */ + >; + }; +}; diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index e1effac323..ef97d90661 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -178,31 +178,31 @@ &usb { status = "okay"; +}; - control@44e10000 { - status = "okay"; - }; +&usb_ctrl_mod { + status = "okay"; +}; - usb-phy@47401300 { - status = "okay"; - }; +&usb0_phy { + status = "okay"; +}; - usb-phy@47401b00 { - status = "okay"; - }; +&usb1_phy { + status = "okay"; +}; - usb@47401000 { - status = "okay"; - }; +&usb0 { + status = "okay"; +}; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; +&usb1 { + status = "okay"; + dr_mode = "host"; +}; - dma-controller@07402000 { - status = "okay"; - }; +&cppi41dma { + status = "okay"; }; &i2c0 { diff --git a/arch/arm/dts/am335x-phytec-phycore.dts b/arch/arm/dts/am335x-phytec-phycore.dts index 5678138f66..e7e7780826 100644 --- a/arch/arm/dts/am335x-phytec-phycore.dts +++ b/arch/arm/dts/am335x-phytec-phycore.dts @@ -50,10 +50,10 @@ spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < - 0x150 (INPUT_EN | MUX_MODE0) - 0x154 (PULL_UP | INPUT_EN | MUX_MODE0) - 0x158 (INPUT_EN | MUX_MODE0) - 0x15c (PULL_UP | INPUT_EN | MUX_MODE0) + 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ + 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ + 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ >; }; @@ -172,9 +172,9 @@ status = "okay"; flash: m25p80 { - compatible = "sst,sst25vf032b", "m25p80"; - spi-max-frequency = <15000000>; - reg = <1>; + compatible = "m25p80"; + spi-max-frequency = <48000000>; + reg = <0>; #address-cells = <1>; #size-cells = <1>; @@ -194,8 +194,13 @@ }; partition@3 { + label = "oftree"; + reg = <0xc0000 0x20000>; + }; + + partition@4 { label = "kernel"; - reg = <0xc0000 0x400000>; + reg = <0xe0000 0x400000>; }; }; }; @@ -305,13 +310,22 @@ }; partition@6 { - label = "kernel"; - reg = <0x120000 0x800000>; + label = "oftree"; + reg = <0x120000 0x20000>; }; partition@7 { + label = "kernel"; + reg = <0x140000 0x800000>; + }; + + partition@8 { label = "root"; - reg = <0x920000 0x1f6e0000>; + /* + * Size 0x0 extends partition to + * end of nand flash. + */ + reg = <0x940000 0x0>; }; }; }; diff --git a/arch/arm/dts/imx53-voipac-bsb.dts b/arch/arm/dts/imx53-voipac-bsb.dts index 54c8bcd40a..12ce592a47 100644 --- a/arch/arm/dts/imx53-voipac-bsb.dts +++ b/arch/arm/dts/imx53-voipac-bsb.dts @@ -10,4 +10,5 @@ */ #include <arm/imx53-voipac-bsb.dts> +#include "imx53-voipac-dmm-668.dtsi" #include "imx53.dtsi" diff --git a/arch/arm/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/dts/imx53-voipac-dmm-668.dtsi new file mode 100644 index 0000000000..6f76d2867a --- /dev/null +++ b/arch/arm/dts/imx53-voipac-dmm-668.dtsi @@ -0,0 +1,35 @@ +/ { + chosen { + linux,stdout-path = &uart1; + + environment@0 { + compatible = "barebox,environment"; + device-path = &nfc, "partname:environment"; + }; + }; +}; + +&nfc { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "environment"; + reg = <0x80000 0x80000>; + }; + + partition@2 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x500000 0x07B00000>; + }; +}; diff --git a/arch/arm/dts/imx6dl-phytec-pbab01.dts b/arch/arm/dts/imx6dl-phytec-pbab01.dts index 0e90c47768..4b77838926 100644 --- a/arch/arm/dts/imx6dl-phytec-pbab01.dts +++ b/arch/arm/dts/imx6dl-phytec-pbab01.dts @@ -20,10 +20,5 @@ chosen { linux,stdout-path = &uart4; - - environment@0 { - compatible = "barebox,environment"; - device-path = &flash, "partname:barebox-environment"; - }; }; }; diff --git a/arch/arm/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi index fa3a49aa3c..0f801aebc9 100644 --- a/arch/arm/dts/imx6dl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi @@ -15,27 +15,8 @@ / { model = "Phytec phyFLEX-i.MX6 Dual Lite"; compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x40000000>; - }; }; &ecspi3 { status = "okay"; }; - -&flash { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0x80000>; - }; - - partition@1 { - label = "barebox-environment"; - reg = <0x80000 0x10000>; - }; -}; diff --git a/arch/arm/dts/imx6dl-tx6u-801x.dts b/arch/arm/dts/imx6dl-tx6u-801x.dts new file mode 100644 index 0000000000..43104b2b88 --- /dev/null +++ b/arch/arm/dts/imx6dl-tx6u-801x.dts @@ -0,0 +1,65 @@ +#include <arm/imx6dl-tx6u-801x.dts> +#include "imx6qdl.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-801x Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + chosen { + linux,stdout-path = &uart1; + + environment@0 { + compatible = "barebox,environment"; + device-path = &gpmi, "partname:barebox-environment"; + }; + }; +}; + +&gpmi { + partition@0 { + label = "barebox"; + reg = <0x0 0x100000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x100000 0x100000>; + }; +}; + +&iomuxc { + imx6qdl-tx6 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ + MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + >; + }; + }; +}; + +&fec { + phy-reset-duration = <22>; +}; + +&ocotp { + barebox,provide-mac-address = <&fec 0x620>; +}; diff --git a/arch/arm/dts/imx6q-gw54xx.dts b/arch/arm/dts/imx6q-gw54xx.dts new file mode 100644 index 0000000000..ab518d66a7 --- /dev/null +++ b/arch/arm/dts/imx6q-gw54xx.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw54xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Quad GW54XX"; + compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-phytec-pbab01.dts b/arch/arm/dts/imx6q-phytec-pbab01.dts index 26046e01c3..580338dff8 100644 --- a/arch/arm/dts/imx6q-phytec-pbab01.dts +++ b/arch/arm/dts/imx6q-phytec-pbab01.dts @@ -19,10 +19,5 @@ chosen { linux,stdout-path = &uart4; - - environment@0 { - compatible = "barebox,environment"; - device-path = &flash, "partname:barebox-environment"; - }; }; }; diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi index 45f36692fe..78c33349dc 100644 --- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi +++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi @@ -144,13 +144,18 @@ }; partition@2 { - label = "kernel"; - reg = <0x420000 0x800000>; + label = "oftree"; + reg = <0x420000 0x20000>; }; partition@3 { + label = "kernel"; + reg = <0x440000 0x800000>; + }; + + partition@4 { label = "root"; - reg = <0xC20000 0x0>; + reg = <0xC40000 0x0>; }; }; diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi index 781a90ae9d..0aec5d0352 100644 --- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6q-phytec-pfla02.dtsi @@ -15,27 +15,8 @@ / { model = "Phytec phyFLEX-i.MX6 Quad"; compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x40000000>; - }; }; &ecspi3 { status = "okay"; }; - -&flash { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0x80000>; - }; - - partition@1 { - label = "barebox-environment"; - reg = <0x80000 0x10000>; - }; -}; diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi new file mode 100644 index 0000000000..ea5739ddcb --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + #include <arm/imx6qdl-gw54xx.dtsi> + + / { + chosen { + linux,stdout-path = &uart2; + + environment@0 { + compatible = "barebox,environment"; + device-path = &gpmi, "partname:barebox-environment"; + }; + }; +}; + +&gpmi { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x400000 0x20000>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi index 8f5dea7407..157e130ff1 100644 --- a/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi @@ -9,23 +9,10 @@ * http://www.gnu.org/copyleft/gpl.html */ -/ { - chosen { - environment@0 { - compatible = "barebox,environment"; - device-path = &flash, "partname:barebox-environment"; - }; - }; -}; - &fec { status = "okay"; }; -&ocotp { - barebox,provide-mac-address = <&fec 0x620>; -}; - &uart1 { status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index a981fd40a3..5c7bcee7f7 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -9,6 +9,28 @@ * http://www.gnu.org/copyleft/gpl.html */ +/ { + chosen { + environment-nand { + compatible = "barebox,environment"; + device-path = &gpmi, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-spinor { + compatible = "barebox,environment"; + device-path = &flash, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-sd { + compatible = "barebox,environment"; + device-path = &usdhc3, "partname:barebox-environment"; + status = "disabled"; + }; + }; +}; + &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; @@ -20,6 +42,20 @@ compatible = "m25p80"; spi-max-frequency = <20000000>; reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x10000>; + }; + }; }; @@ -36,6 +72,33 @@ pinctrl-0 = <&pinctrl_gpmi_nand>; nand-on-flash-bbt; status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x400000 0x20000>; + }; + + partition@2 { + label = "oftree"; + reg = <0x420000 0x20000>; + }; + + partition@3 { + label = "kernel"; + reg = <0x440000 0x800000>; + }; + + partition@4 { + label = "root"; + reg = <0xC40000 0x0>; + }; }; &iomuxc { @@ -149,6 +212,10 @@ }; }; +&ocotp { + barebox,provide-mac-address = <&fec 0x620>; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -169,4 +236,16 @@ cd-gpios = <&gpio1 27 0>; wp-gpios = <&gpio1 29 0>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; }; diff --git a/arch/arm/dts/imx6s-phytec-pfla02.dtsi b/arch/arm/dts/imx6s-phytec-pfla02.dtsi index 83224262b3..d84fa4f15f 100644 --- a/arch/arm/dts/imx6s-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6s-phytec-pfla02.dtsi @@ -15,8 +15,4 @@ / { model = "Phytec phyFLEX-i.MX6 Single"; compatible = "phytec,imx6s-pfla02", "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x20000000>; - }; }; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 3368b459d0..afac867c99 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -465,6 +465,12 @@ status = "disabled"; }; + fpgamgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000>, + <0xffb90000 0x1000>; + }; + gpio0: gpio@ff708000 { compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 826917e12c..8c10c10359 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -6,6 +6,9 @@ config HAVE_AT91_DBGU0 config HAVE_AT91_DBGU1 bool +config HAVE_AT91_DBGU2 + bool + config HAVE_AT91_LOWLEVEL_INIT bool @@ -168,6 +171,13 @@ config ARCH_SAMA5D3 select HAS_MACB select AT91SAM9G45_RESET +config ARCH_SAMA5D4 + bool "SAMA5D4" + select SOC_SAMA5 + select HAVE_AT91_DBGU2 + select HAS_MACB + select AT91SAM9G45_RESET + endchoice config ARCH_BAREBOX_MAX_BARE_INIT_SIZE @@ -472,6 +482,22 @@ endif # ---------------------------------------------------------- +if ARCH_SAMA5D4 + +choice + prompt "SAMA5D4 Board Type" + +config MACH_SAMA5D4EK + bool "Atmel SAMA5D4 Evaluation Kit" + help + Select this if you are using Atmel's SAMA5D4-EK Evaluation Kit. + +endchoice + +endif + +# ---------------------------------------------------------- + comment "AT91 Board Options" config MTD_AT91_DATAFLASH_CARD diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 8599f507c4..c2991b0136 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -12,6 +12,7 @@ lowlevel_init-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5_lowlevel_init.o lowlevel_init-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12_lowlevel_init.o lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o lowlevel_init-$(CONFIG_ARCH_SAMA5D3) += sama5d3_lowlevel_init.o +lowlevel_init-$(CONFIG_ARCH_SAMA5D4) += sama5d3_lowlevel_init.o lwl-y += $(lowlevel_init-y) obj-$(CONFIG_AT91SAM9_RESET) += at91sam9_reset.o @@ -31,3 +32,4 @@ obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o obj-$(CONFIG_ARCH_SAMA5D3) += sama5d3.o sama5d3_devices.o +obj-$(CONFIG_ARCH_SAMA5D4) += sama5d4.o sama5d4_devices.o diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 9a50debb16..ce6ce90db2 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -192,11 +192,6 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), - CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk), - CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk), - CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk), - CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk), - CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk), CLKDEV_DEV_ID("at91-pit", &mck), CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk), }; @@ -238,6 +233,14 @@ static void __init at91sam9g45_register_clocks(void) clkdev_add_table(usart_clocks_lookups, ARRAY_SIZE(usart_clocks_lookups)); + clkdev_add_physbase(&twi0_clk, AT91SAM9G45_BASE_TWI0, NULL); + clkdev_add_physbase(&twi1_clk, AT91SAM9G45_BASE_TWI1, NULL); + clkdev_add_physbase(&pioA_clk, AT91SAM9G45_BASE_PIOA, NULL); + clkdev_add_physbase(&pioB_clk, AT91SAM9G45_BASE_PIOB, NULL); + clkdev_add_physbase(&pioC_clk, AT91SAM9G45_BASE_PIOC, NULL); + clkdev_add_physbase(&pioDE_clk, AT91SAM9G45_BASE_PIOD, NULL); + clkdev_add_physbase(&pioDE_clk, AT91SAM9G45_BASE_PIOE, NULL); + if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) clk_register(&vdec_clk); diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 9d2a846447..7a4282e615 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -37,6 +37,7 @@ #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) +#define clk_is_periph_h64mx(x) ((x)->type & CLK_TYPE_PERIPH_H64MX) /* @@ -45,7 +46,10 @@ #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_sama5d3()) + || cpu_is_sama5d3() \ + || cpu_is_sama5d4()) + +#define cpu_has_1200M_plla() (cpu_is_sama5d4()) #define cpu_has_1056M_plla() (cpu_is_sama5d3()) @@ -65,11 +69,13 @@ #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_sama5d3())) + || cpu_is_sama5d3() \ + || cpu_is_sama5d4())) #define cpu_has_upll() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_sama5d3()) + || cpu_is_sama5d3() \ + || cpu_is_sama5d4()) /* USB host HS & FS */ #define cpu_has_uhp() (!cpu_is_at91sam9rl()) @@ -78,21 +84,30 @@ #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_sama5d3())) + || cpu_is_sama5d3() \ + || cpu_is_sama5d4())) #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ || cpu_is_at91sam9n12() \ - || cpu_is_sama5d3()) + || cpu_is_sama5d3() \ + || cpu_is_sama5d4()) #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ || cpu_is_at91sam9n12() \ - || cpu_is_sama5d3()) + || cpu_is_sama5d3() \ + || cpu_is_sama5d4()) #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ || cpu_is_at91sam9n12() \ - || cpu_is_sama5d3()) + || cpu_is_sama5d3() \ + || cpu_is_sama5d4()) + +#define cpu_has_pcr() (cpu_is_sama5d3() \ + || cpu_is_sama5d4()) + +#define cpu_has_dual_matrix() (cpu_is_sama5d4()) static LIST_HEAD(clocks); @@ -212,6 +227,12 @@ struct clk mck = { .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ }; +struct clk h32mx_clk = { + .name = "h32mx", + .parent = &mck, + .pmc_mask = AT91_PMC_H32MXDIV, /* in PMC_MCKR */ +}; + static void pmc_periph_mode(struct clk *clk, int is_on) { u32 regval = 0; @@ -221,7 +242,7 @@ static void pmc_periph_mode(struct clk *clk, int is_on) * register is not enough to manage their clocks. A peripheral * control register has been introduced to solve this issue. */ - if (cpu_is_sama5d3()) { + if (cpu_has_pcr()) { regval |= AT91_PMC_PCR_CMD; /* write command */ regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */ regval |= AT91_PMC_PCR_DIV(clk->div); @@ -453,9 +474,13 @@ static void __init at91_clk_add(struct clk *clk) int clk_register(struct clk *clk) { if (clk_is_peripheral(clk)) { - if (!clk->parent) - clk->parent = &mck; - if (cpu_is_sama5d3()) + if (!clk->parent) { + if (!cpu_has_dual_matrix() || clk_is_periph_h64mx(clk)) + clk->parent = &mck; + else + clk->parent = &h32mx_clk; + } + if (cpu_has_pcr()) clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz, 1 << clk->div); clk->mode = pmc_periph_mode; } @@ -482,7 +507,7 @@ static u32 at91_pll_rate(struct clk *pll, u32 freq, u32 reg) unsigned mul, div; div = reg & 0xff; - if (cpu_is_sama5d3()) + if (cpu_is_sama5d3() || cpu_is_sama5d4()) mul = (reg >> 18) & 0x7ff; else mul = (reg >> 16) & 0x7ff; @@ -647,7 +672,10 @@ int at91_clock_init(void) /* report if PLLA is more than mildly overclocked */ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); - if (cpu_has_1056M_plla()) { + if (cpu_has_1200M_plla()) { + if (plla.rate_hz > 1200000000) + pll_overclock = 1; + } else if (cpu_has_1056M_plla()) { if (plla.rate_hz > 1056000000) pll_overclock = 1; } else if (cpu_has_300M_plla()) { @@ -734,6 +762,12 @@ int at91_clock_init(void) mck.id = 4; } + if (cpu_has_dual_matrix()) { + at91_clk_add(&h32mx_clk); + h32mx_clk.rate_hz = h32mx_clk.parent->rate_hz; + h32mx_clk.rate_hz /= (1 << ((mckr & AT91_PMC_H32MXDIV) >> 24)); /* H32MX divisor by 2 */ + } + cpu_freq = freq; /* Register the PMC's standard clocks */ @@ -754,6 +788,8 @@ int at91_clock_init(void) /* MCK and CPU clock are "always on" */ clk_enable(&mck); + if (cpu_has_dual_matrix()) + clk_enable(&h32mx_clk); return 0; } @@ -787,7 +823,7 @@ static int at91_clock_reset(void) continue; if (clk->mode == pmc_periph_mode) { - if (cpu_is_sama5d3()) { + if (cpu_has_pcr()) { u32 pmc_mask = 1 << (clk->pid % 32); if (clk->pid > 31) @@ -805,7 +841,7 @@ static int at91_clock_reset(void) } at91_pmc_write(AT91_PMC_PCDR, pcdr); - if (cpu_is_sama5d3()) + if (cpu_has_pcr()) at91_pmc_write(AT91_PMC_PCDR1, pcdr1); at91_pmc_write(AT91_PMC_SCDR, scdr); @@ -821,12 +857,12 @@ static int do_at91clk(int argc, char *argv[]) scsr = at91_pmc_read(AT91_PMC_SCSR); pcsr = at91_pmc_read(AT91_PMC_PCSR); - if (cpu_is_sama5d3()) + if (cpu_has_pcr()) pcsr1 = at91_pmc_read(AT91_PMC_PCSR1); sr = at91_pmc_read(AT91_PMC_SR); printf("SCSR = %8x\n", scsr); printf("PCSR = %8x\n", pcsr); - if (cpu_is_sama5d3()) + if (cpu_has_pcr()) printf("PCSR1 = %8x\n", pcsr1); printf("MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); printf("MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); @@ -852,7 +888,7 @@ static int do_at91clk(int argc, char *argv[]) state = (scsr & clk->pmc_mask) ? "on" : "off"; mode = "sys"; } else if (clk->mode == pmc_periph_mode) { - if (cpu_is_sama5d3()) { + if (cpu_has_pcr()) { u32 pmc_mask = 1 << (clk->pid % 32); if (clk->pid > 31) diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h index 8af8d963c8..97a08fd83f 100644 --- a/arch/arm/mach-at91/clock.h +++ b/arch/arm/mach-at91/clock.h @@ -13,7 +13,7 @@ #define CLK_TYPE_PROGRAMMABLE 0x4 #define CLK_TYPE_PERIPHERAL 0x8 #define CLK_TYPE_SYSTEM 0x10 - +#define CLK_TYPE_PERIPH_H64MX 0x80 struct clk { struct list_head node; diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 61078717c6..d74c14011c 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -118,6 +118,7 @@ #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ #define AT91_PMC_PLLADIV2_OFF (0 << 12) #define AT91_PMC_PLLADIV2_ON (1 << 12) +#define AT91_PMC_H32MXDIV (1 << 24) /* AHB 32-bit Matrix Divisor [some SAMA5 only] */ #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index 36e940d928..4fe8fd891c 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h @@ -118,6 +118,7 @@ #define AT91_MATRIX 0 /* not supported */ +#define AT91_PMC 0xfffffc00 /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 3f3a0e1a54..919901d6da 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -125,6 +125,8 @@ #define AT91_ID_UHP AT91SAM9260_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP +#define AT91_PMC 0xfffffc00 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 1b48e230b4..9124df5caa 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -102,6 +102,7 @@ #define AT91_USART2 AT91SAM9261_BASE_US2 #define AT91_NB_USART 4 +#define AT91_PMC 0xfffffc00 /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index b42d191b99..e7ca8b63aa 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -129,6 +129,8 @@ #define AT91_ID_UHP AT91SAM9263_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP +#define AT91_PMC 0xfffffc00 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index c81bb80c53..ff12ce458a 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -134,6 +134,8 @@ #define AT91_USART3 AT91SAM9G45_BASE_US3 #define AT91_NB_USART 5 +#define AT91_PMC 0xfffffc00 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h index 26bdd13498..249bde466b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h +++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h @@ -129,6 +129,7 @@ #define AT91_USART3 AT91SAM9X5_BASE_US3 #define AT91_NB_USART 5 +#define AT91_PMC 0xfffffc00 /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 13b4f44379..7ba2e3b9b1 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -136,6 +136,7 @@ #define AT91_USART3 AT91SAM9X5_BASE_US3 #define AT91_NB_USART 5 +#define AT91_PMC 0xfffffc00 /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 0e213ce9da..f684d32949 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -26,7 +26,7 @@ #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ #define ARCH_ID_AT91SAM9X5 0x819a05a0 #define ARCH_ID_AT91SAM9N12 0x819a07a0 -#define ARCH_ID_SAMA5D3 0x8A5C07C0 +#define ARCH_ID_SAMA5 0x8A5C07C0 #define ARCH_ID_AT91SAM9XE128 0x329973a0 #define ARCH_ID_AT91SAM9XE256 0x329a93a0 @@ -48,12 +48,19 @@ #define ARCH_EXID_AT91SAM9G25 0x00000003 #define ARCH_EXID_AT91SAM9X25 0x00000004 +#define ARCH_EXID_SAMA5D3 0x00004300 #define ARCH_EXID_SAMA5D31 0x00444300 #define ARCH_EXID_SAMA5D33 0x00414300 #define ARCH_EXID_SAMA5D34 0x00414301 #define ARCH_EXID_SAMA5D35 0x00584300 #define ARCH_EXID_SAMA5D36 0x00004301 +#define ARCH_EXID_SAMA5D4 0x00000007 +#define ARCH_EXID_SAMA5D41 0x00000001 +#define ARCH_EXID_SAMA5D42 0x00000002 +#define ARCH_EXID_SAMA5D43 0x00000003 +#define ARCH_EXID_SAMA5D44 0x00000004 + #define ARCH_FAMILY_AT91X92 0x09200000 #define ARCH_FAMILY_AT91SAM9 0x01900000 #define ARCH_FAMILY_AT91SAM9XE 0x02900000 @@ -85,6 +92,9 @@ enum at91_soc_type { /* SAMA5D3 */ AT91_SOC_SAMA5D3, + /* SAMA5D4 */ + AT91_SOC_SAMA5D4, + /* Unknown type */ AT91_SOC_NONE }; @@ -107,6 +117,10 @@ enum at91_soc_subtype { AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, + /* SAMA5D4 */ + AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43, + AT91_SOC_SAMA5D44, + /* Unknown subtype */ AT91_SOC_SUBTYPE_NONE }; @@ -217,6 +231,20 @@ static inline int at91_soc_is_detected(void) #define cpu_is_sama5d36() (0) #endif +#ifdef CONFIG_ARCH_SAMA5D4 +#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4) +#define cpu_is_sama5d41() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D41) +#define cpu_is_sama5d42() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D42) +#define cpu_is_sama5d43() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D43) +#define cpu_is_sama5d44() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D44) +#else +#define cpu_is_sama5d4() (0) +#define cpu_is_sama5d41() (0) +#define cpu_is_sama5d42() (0) +#define cpu_is_sama5d43() (0) +#define cpu_is_sama5d44() (0) +#endif + /* * Since this is ARM, we will never run on any AVR32 CPU. But these * definitions may reduce clutter in common drivers. diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 8f004deb42..bbaad714cf 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -19,8 +19,8 @@ #define AT91_BASE_DBGU0 0xfffff200 /* 9263, 9g45 */ #define AT91_BASE_DBGU1 0xffffee00 - -#define AT91_PMC 0xfffffc00 +/* sama5d4 */ +#define AT91_BASE_DBGU2 0xfc069000 #if defined(CONFIG_ARCH_AT91RM9200) #include <mach/at91rm9200.h> @@ -40,6 +40,8 @@ #include <mach/at91sam9x5.h> #elif defined(CONFIG_ARCH_SAMA5D3) #include <mach/sama5d3.h> +#elif defined(CONFIG_ARCH_SAMA5D4) +#include <mach/sama5d4.h> #elif defined(CONFIG_ARCH_AT91CAP9) #include <mach/at91cap9.h> #elif defined(CONFIG_ARCH_AT91X40) diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 6884ff6a7e..e98b101ee0 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -108,6 +108,8 @@ #define AT91_NB_USART 3 +#define AT91_PMC 0xfffffc00 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h new file mode 100644 index 0000000000..046fdb0426 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -0,0 +1,134 @@ +/* + * Chip-specific header file for the SAMA5D4 family + * + * Copyright (C) 2014 Atmel Corporation, + * Bo Shen <voice.shen@atmel.com> + * + * Common definitions. + * Based on SAMA5D4 datasheet. + * + * Licensed under GPLv2 or later. + */ + +#ifndef SAMA5D4_H +#define SAMA5D4_H + +/* + * Peripheral identifiers/interrupts. + */ +#define SAMA5D4_ID_PIT 3 +#define SAMA5D4_ID_WDT 4 +#define SAMA5D4_ID_PIOD 5 +#define SAMA5D4_ID_USART0 6 +#define SAMA5D4_ID_USART1 7 +#define SAMA5D4_ID_DMA0 8 +#define SAMA5D4_ID_ICM 9 +#define SAMA5D4_ID_PKCC 10 +#define SAMA5D4_ID_SCI 11 +#define SAMA5D4_ID_AES 12 +#define SAMA5D4_ID_AESB 13 +#define SAMA5D4_ID_TDES 14 +#define SAMA5D4_ID_SHA 15 +#define SAMA5D4_ID_MPDDRC 16 +#define SAMA5D4_ID_MATRIX1 17 +#define SAMA5D4_ID_MATRIX0 18 +#define SAMA5D4_ID_VDEC 19 +#define SAMA5D4_ID_SECUMOD 20 +#define SAMA5D4_ID_MSADCC 21 +#define SAMA5D4_ID_HSMC 22 +#define SAMA5D4_ID_PIOA 23 +#define SAMA5D4_ID_PIOB 24 +#define SAMA5D4_ID_PIOC 25 +#define SAMA5D4_ID_PIOE 26 +#define SAMA5D4_ID_UART0 27 +#define SAMA5D4_ID_UART1 28 +#define SAMA5D4_ID_USART2 29 +#define SAMA5D4_ID_USART3 30 +#define SAMA5D4_ID_USART4 31 +#define SAMA5D4_ID_TWI0 32 +#define SAMA5D4_ID_TWI1 33 +#define SAMA5D4_ID_TWI2 34 +#define SAMA5D4_ID_HSMCI0 35 +#define SAMA5D4_ID_HSMCI1 36 +#define SAMA5D4_ID_SPI0 37 +#define SAMA5D4_ID_SPI1 38 +#define SAMA5D4_ID_SPI2 39 +#define SAMA5D4_ID_TC0 40 +#define SAMA5D4_ID_TC1 41 +#define SAMA5D4_ID_TC2 42 +#define SAMA5D4_ID_PWM 43 +#define SAMA5D4_ID_ADC 44 +#define SAMA5D4_ID_DBGU 45 +#define SAMA5D4_ID_UHPHS 46 +#define SAMA5D4_ID_UDPHS 47 +#define SAMA5D4_ID_SSC0 48 +#define SAMA5D4_ID_SSC1 49 +#define SAMA5D4_ID_DMA1 50 +#define SAMA5D4_ID_LCDC 51 +#define SAMA5D4_ID_ISI 52 +#define SAMA5D4_ID_TRNG 53 +#define SAMA5D4_ID_GMAC0 54 +#define SAMA5D4_ID_IRQ 56 +#define SAMA5D4_ID_IRQ 56 +#define SAMA5D4_ID_SFC 57 +#define SAMA5D4_ID_SECURAM 59 +#define SAMA5D4_ID_CTB 60 +#define SAMA5D4_ID_SMD 61 +#define SAMA5D4_ID_TWI3 62 +#define SAMA5D4_ID_CATB 63 +#define SAMA5D4_ID_SFR 64 +#define SAMA5D4_ID_AIC 65 +#define SAMA5D4_ID_SAIC 66 +#define SAMA5D4_ID_L2CC 67 + +/* + * User Peripheral physical base addresses. + */ + +#define SAMA5D4_BASE_LCDC 0xf0000000 /* (HLCDC5) Base Address */ +#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */ +#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */ +#define SAMA5D4_BASE_HSMCI0 0xf8000000 /* (MMCI0) Base Address */ +#define SAMA5D4_BASE_UART0 0xf8004000 /* (UART0) Base Address */ +#define SAMA5D4_BASE_SPI0 0xf8010000 /* (SPI0) Base Address */ +#define SAMA5D4_BASE_TC0 0xf801c000 /* (TC0) Base Address */ +#define SAMA5D4_BASE_GMAC0 0xf8020000 /* (GMAC0) Base Address */ +#define SAMA5D4_BASE_USART0 0xf802c000 /* (USART0) Base Address */ +#define SAMA5D4_BASE_USART1 0xf8030000 /* (USART1) Base Address */ +#define SAMA5D4_BASE_HSMCI1 0xfc000000 /* (HSMCI1) Base Address */ +#define SAMA5D4_BASE_UART1 0xfc004000 /* (UART1) Base Address */ +#define SAMA5D4_BASE_USART2 0xfc008000 /* (USART2) Base Address */ +#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3) Base Address */ +#define SAMA5D4_BASE_USART4 0xfc010000 /* (USART4) Base Address */ +#define SAMA5D4_BASE_SPI1 0xfc018000 /* (SPI1) Base Address */ +#define SAMA5D4_BASE_GMAC1 0xfc028000 /* (GMAC1) Base Address */ +#define SAMA5D4_BASE_HSMC 0xfc05c000 /* (HSMC) Base Address */ +#define SAMA5D4_BASE_PMECC 0xfc05c070 /* (PMECC) Base Address */ +#define SAMA5D4_BASE_PMERRLOC 0xfc05c500 /* (PMERRLOC) Base Address */ +#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */ +#define SAMA5D4_BASE_PIT 0xfc068630 /* (PIT) Base Address */ +#define SAMA5D4_BASE_DBGU 0xfc069000 /* (DBGU) Base Address */ +#define SAMA5D4_BASE_PIOA 0xfc06a000 /* (PIOA) Base Address */ +#define SAMA5D4_BASE_PIOB 0xfc06b000 /* (PIOB) Base Address */ +#define SAMA5D4_BASE_PIOC 0xfc06c000 /* (PIOC) Base Address */ +#define SAMA5D4_BASE_PIOE 0xfc06d000 /* (PIOE) Base Address */ +#define SAMA5D4_BASE_AIC 0xfc06e000 /* (AIC) Base Address */ + +#define SAMA5D4_CHIPSELECT_3 0x80000000 + +/* + * Internal Memory. + */ +#define SAMA5D4_SRAM_BASE 0x00200000 /* Internal SRAM base address */ +#define SAMA5D4_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size */ + +#define AT91_NB_USART 7 +#define AT91_BASE_SYS 0xf0000000 +#define AT91_PMC SAMA5D4_BASE_PMC +#define AT91_DDRSDRC0 (0xf0010000 - AT91_BASE_SYS) +#define AT91_RSTC (0xfc068600 - AT91_BASE_SYS) +#define SAMA5D3_BASE_MPDDRC SAMA5D4_BASE_MPDDRC +#define SAMA5D3_SRAM_BASE SAMA5D4_SRAM_BASE +#define SAMA5D3_SRAM_SIZE SAMA5D4_SRAM_SIZE + +#endif diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index 403fa9b1c4..6346bb440c 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -20,7 +20,9 @@ #define AT91_SAM9_SMC_CS_STRIDE 0x10 #define AT91_SAMA5_SMC_CS_STRIDE 0x14 -#define AT91_SMC_CS_STRIDE ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? AT91_SAMA5_SMC_CS_STRIDE : AT91_SAM9_SMC_CS_STRIDE) +#define AT91_SMC_CS_STRIDE ((at91_soc_initdata.type == AT91_SOC_SAMA5D3 \ + || at91_soc_initdata.type == AT91_SOC_SAMA5D4) \ + ? AT91_SAMA5_SMC_CS_STRIDE : AT91_SAM9_SMC_CS_STRIDE) #define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * AT91_SMC_CS_STRIDE)) static void __iomem *smc_base_addr[2]; @@ -30,7 +32,15 @@ static void sam9_smc_cs_write_mode(void __iomem *base, { void __iomem *mode_reg; - mode_reg = base + ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? AT91_SAMA5_SMC_MODE : AT91_SAM9_SMC_MODE); + switch (at91_soc_initdata.type) { + case AT91_SOC_SAMA5D3: + case AT91_SOC_SAMA5D4: + mode_reg = base + AT91_SAMA5_SMC_MODE; + break; + default: + mode_reg = base + AT91_SAM9_SMC_MODE; + break; + } __raw_writel(config->mode | AT91_SMC_TDF_(config->tdf_cycles), @@ -96,7 +106,15 @@ static void sam9_smc_cs_read_mode(void __iomem *base, u32 val; void __iomem *mode_reg; - mode_reg = base + ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? AT91_SAMA5_SMC_MODE : AT91_SAM9_SMC_MODE); + switch (at91_soc_initdata.type) { + case AT91_SOC_SAMA5D3: + case AT91_SOC_SAMA5D4: + mode_reg = base + AT91_SAMA5_SMC_MODE; + break; + default: + mode_reg = base + AT91_SAM9_SMC_MODE; + break; + } val = __raw_readl(mode_reg); diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c new file mode 100644 index 0000000000..4d380ed88e --- /dev/null +++ b/arch/arm/mach-at91/sama5d4.c @@ -0,0 +1,304 @@ +/* + * Chip-specific setup code for the SAMA5D4 family + * + * Copyright (C) 2014 Atmel Corporation, + * Bo Shen <voice.shen@atmel.com> + * + * Licensed under GPLv2 or later. + */ + +#include <common.h> +#include <gpio.h> +#include <init.h> +#include <mach/hardware.h> +#include <mach/at91_pmc.h> +#include <mach/io.h> +#include <mach/cpu.h> +#include <linux/clk.h> + +#include "soc.h" +#include "generic.h" +#include "clock.h" + +/* + * The peripheral clocks. + */ +static struct clk pit_clk = { + .name = "pit_clk", + .pid = SAMA5D4_ID_PIT, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk smc_clk = { + .name = "smc_clk", + .pid = SAMA5D4_ID_HSMC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioA_clk = { + .name = "pioA_clk", + .pid = SAMA5D4_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pid = SAMA5D4_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pid = SAMA5D4_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioD_clk = { + .name = "pioD_clk", + .pid = SAMA5D4_ID_PIOD, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioE_clk = { + .name = "pioE_clk", + .pid = SAMA5D4_ID_PIOE, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pid = SAMA5D4_ID_USART0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pid = SAMA5D4_ID_USART2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart3_clk = { + .name = "usart3_clk", + .pid = SAMA5D4_ID_USART3, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart4_clk = { + .name = "usart4_clk", + .pid = SAMA5D4_ID_USART4, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc0_clk = { + .name = "mci0_clk", + .pid = SAMA5D4_ID_HSMCI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc1_clk = { + .name = "mci1_clk", + .pid = SAMA5D4_ID_HSMCI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tcb0_clk = { + .name = "tcb0_clk", + .pid = SAMA5D4_ID_TC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tcb1_clk = { + .name = "tcb1_clk", + .pid = SAMA5D4_ID_TC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk adc_clk = { + .name = "adc_clk", + .pid = SAMA5D4_ID_ADC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk dma0_clk = { + .name = "dma0_clk", + .pid = SAMA5D4_ID_DMA0, + .type = CLK_TYPE_PERIPHERAL | CLK_TYPE_PERIPH_H64MX, +}; +static struct clk dma1_clk = { + .name = "dma1_clk", + .pid = SAMA5D4_ID_DMA1, + .type = CLK_TYPE_PERIPHERAL | CLK_TYPE_PERIPH_H64MX, +}; +static struct clk uhphs_clk = { + .name = "uhphs", + .pid = SAMA5D4_ID_UHPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udphs_clk = { + .name = "udphs_clk", + .pid = SAMA5D4_ID_UDPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .pid = SAMA5D4_ID_LCDC, + .type = CLK_TYPE_PERIPHERAL | CLK_TYPE_PERIPH_H64MX, +}; +static struct clk isi_clk = { + .name = "isi_clk", + .pid = SAMA5D4_ID_ISI, + .type = CLK_TYPE_PERIPHERAL | CLK_TYPE_PERIPH_H64MX, +}; +static struct clk macb0_clk = { + .name = "macb0_clk", + .pid = SAMA5D4_ID_GMAC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi0_clk = { + .name = "twi0_clk", + .pid = SAMA5D4_ID_TWI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi2_clk = { + .name = "twi2_clk", + .pid = SAMA5D4_ID_TWI2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi0_clk = { + .name = "spi0_clk", + .pid = SAMA5D4_ID_SPI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk smd_clk = { + .name = "smd_clk", + .pid = SAMA5D4_ID_SMD, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc0_clk = { + .name = "ssc0_clk", + .pid = SAMA5D4_ID_SSC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc1_clk = { + .name = "ssc1_clk", + .pid = SAMA5D4_ID_SSC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk sha_clk = { + .name = "sha_clk", + .pid = SAMA5D4_ID_SHA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk aes_clk = { + .name = "aes_clk", + .pid = SAMA5D4_ID_AES, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tdes_clk = { + .name = "tdes_clk", + .pid = SAMA5D4_ID_TDES, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] __initdata = { + &pit_clk, + &smc_clk, + &pioA_clk, + &pioB_clk, + &pioC_clk, + &pioD_clk, + &pioE_clk, + &usart0_clk, + &usart2_clk, + &usart3_clk, + &usart4_clk, + &mmc0_clk, + &mmc1_clk, + &tcb0_clk, + &tcb1_clk, + &adc_clk, + &dma0_clk, + &dma1_clk, + &uhphs_clk, + &udphs_clk, + &lcdc_clk, + &isi_clk, + &macb0_clk, + &twi0_clk, + &twi2_clk, + &spi0_clk, + &smd_clk, + &ssc0_clk, + &ssc1_clk, + &sha_clk, + &aes_clk, + &tdes_clk, +}; + +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; + +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; + +static struct clk pck2 = { + .name = "pck2", + .pmc_mask = AT91_PMC_PCK2, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 2, +}; + +static struct clk_lookup periph_clocks_lookups[] = { + CLKDEV_CON_DEV_ID("macb_clk", "macb0", &macb0_clk), + CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk), + CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), + CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), + CLKDEV_DEV_ID("at91-pit", &pit_clk), + CLKDEV_CON_DEV_ID("hck1", "atmel_hlcdfb", &lcdc_clk), +}; + +static struct clk_lookup usart_clocks_lookups[] = { + CLKDEV_CON_DEV_ID("usart", "atmel_usart0", &mck), + CLKDEV_CON_DEV_ID("usart", "atmel_usart1", &usart0_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart3", &usart2_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart4", &usart3_clk), +}; + +static void __init sama5d4_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clkdev_add_physbase(&pioA_clk, SAMA5D4_BASE_PIOA, 0); + clkdev_add_physbase(&pioB_clk, SAMA5D4_BASE_PIOB, 0); + clkdev_add_physbase(&pioC_clk, SAMA5D4_BASE_PIOC, 0); + clkdev_add_physbase(&pioD_clk, SAMA5D4_BASE_PIOD, 0); + clkdev_add_physbase(&pioE_clk, SAMA5D4_BASE_PIOE, 0); + + clkdev_add_table(periph_clocks_lookups, + ARRAY_SIZE(periph_clocks_lookups)); + + clkdev_add_table(usart_clocks_lookups, + ARRAY_SIZE(usart_clocks_lookups)); + + clk_register(&pck0); + clk_register(&pck1); + clk_register(&pck2); +} + +/* -------------------------------------------------------------------- + * Processor initialization + * -------------------------------------------------------------------- */ +static void sama5d4_initialize(void) +{ + /* Register the processor-specific clocks */ + sama5d4_register_clocks(); + + /* Register GPIO subsystem */ + at91_add_sam9x5_gpio(0, SAMA5D4_BASE_PIOA); + at91_add_sam9x5_gpio(1, SAMA5D4_BASE_PIOB); + at91_add_sam9x5_gpio(2, SAMA5D4_BASE_PIOC); + at91_add_sam9x5_gpio(3, SAMA5D4_BASE_PIOD); + at91_add_sam9x5_gpio(4, SAMA5D4_BASE_PIOE); + + at91_add_pit(SAMA5D4_BASE_PIT); + at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D4_BASE_HSMC + 0x600, 0xa0); +} + +AT91_SOC_START(sama5d4) + .init = sama5d4_initialize, +AT91_SOC_END diff --git a/arch/arm/mach-at91/sama5d4_devices.c b/arch/arm/mach-at91/sama5d4_devices.c new file mode 100644 index 0000000000..3806971688 --- /dev/null +++ b/arch/arm/mach-at91/sama5d4_devices.c @@ -0,0 +1,495 @@ +/* + * On-Chip devices setup code for the SAMA5D4 family + * + * Copyright (C) 2014 Atmel Corporation. + * Bo Shen <voice.shen@atmel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <common.h> +#include <init.h> +#include <sizes.h> +#include <gpio.h> +#include <asm/armlinux.h> +#include <mach/hardware.h> +#include <mach/board.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9x5_matrix.h> +#include <mach/at91sam9_ddrsdr.h> +#include <mach/iomux.h> +#include <mach/io.h> +#include <mach/cpu.h> +#include <i2c/i2c-gpio.h> + +#include "generic.h" + +void at91_add_device_sdram(u32 size) +{ + if (!size) + size = at91sama5_get_ddram_size(); + + arm_add_mem_device("ram0", SAMA5_DDRCS, size); + add_mem_device("sram0", SAMA5D4_SRAM_BASE, + SAMA5D4_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); +} + +/* -------------------------------------------------------------------- + * NAND / SmartMedia + * -------------------------------------------------------------------- */ +#if defined(CONFIG_NAND_ATMEL) +static struct resource nand_resources[] = { + [0] = { + .start = SAMA5D4_CHIPSELECT_3, + .end = SAMA5D4_CHIPSELECT_3 + SZ_128M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SAMA5D4_BASE_PMECC, + .end = SAMA5D4_BASE_PMECC + 0x490 - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = SAMA5D4_BASE_PMERRLOC, + .end = SAMA5D4_BASE_PMERRLOC + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +void __init at91_add_device_nand(struct atmel_nand_data *data) +{ + if (!data) + return; + + at91_set_A_periph(AT91_PIN_PC5, 0); /* D0 */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* D1 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* D2 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* D3 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* D4 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* D5 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* D6 */ + at91_set_A_periph(AT91_PIN_PC12, 0); /* D7 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* RE */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* WE */ + at91_set_A_periph(AT91_PIN_PC15, 1); /* NCS */ + at91_set_A_periph(AT91_PIN_PC16, 1); /* RDY */ + at91_set_A_periph(AT91_PIN_PC17, 1); /* ALE */ + at91_set_A_periph(AT91_PIN_PC18, 1); /* CLE */ + + /* enable pin */ + if (gpio_is_valid(data->enable_pin)) + at91_set_gpio_output(data->enable_pin, 1); + + /* ready/busy pin */ + if (gpio_is_valid(data->rdy_pin)) + at91_set_gpio_input(data->rdy_pin, 1); + + /* card detect pin */ + if (gpio_is_valid(data->det_pin)) + at91_set_gpio_input(data->det_pin, 1); + + add_generic_device_res("atmel_nand", 0, nand_resources, + ARRAY_SIZE(nand_resources), data); +} +#else +void __init at91_add_device_nand(struct atmel_nand_data *data) {} +#endif + +#if defined(CONFIG_DRIVER_NET_MACB) +void at91_add_device_eth(int id, struct macb_platform_data *data) +{ + if (!data) + return; + + switch (id) { + case 0: + at91_set_A_periph(AT91_PIN_PB16, 0); /* GMDC */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* GMDIO */ + + at91_set_A_periph(AT91_PIN_PB0, 0); /* GTXCK */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* GTXEN */ + at91_set_A_periph(AT91_PIN_PB6, 0); /* GRXDV */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* GRXER */ + + switch (data->phy_interface) { + case PHY_INTERFACE_MODE_MII: + at91_set_A_periph(AT91_PIN_PB4, 0); /* GCRS */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* GCOL */ + at91_set_A_periph(AT91_PIN_PB14, 0); /* GTX2 */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* GTX3 */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* GTXER */ + at91_set_A_periph(AT91_PIN_PB1, 0); /* GRXCK */ + at91_set_A_periph(AT91_PIN_PB10, 0); /* GRX2 */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* GRX3 */ + case PHY_INTERFACE_MODE_RMII: + at91_set_A_periph(AT91_PIN_PB12, 0); /* GTX0 */ + at91_set_A_periph(AT91_PIN_PB13, 0); /* GTX1 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* GRX0 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* GRX1 */ + break; + default: + return; + } + + add_generic_device("macb", id, NULL, SAMA5D4_BASE_GMAC0, SZ_16K, + IORESOURCE_MEM, data); + break; + case 1: + at91_set_B_periph(AT91_PIN_PA22, 0); /* GMDC */ + at91_set_B_periph(AT91_PIN_PA23, 0); /* GMDIO */ + + at91_set_B_periph(AT91_PIN_PA2, 0); /* GTXCK */ + at91_set_B_periph(AT91_PIN_PA4, 0); /* GTXEN */ + at91_set_B_periph(AT91_PIN_PA10, 0); /* GRXDV */ + at91_set_B_periph(AT91_PIN_PA11, 0); /* GRXER */ + + switch (data->phy_interface) { + case PHY_INTERFACE_MODE_MII: + at91_set_B_periph(AT91_PIN_PA6, 0); /* GCRS */ + at91_set_B_periph(AT91_PIN_PA9, 0); /* GCOL */ + at91_set_B_periph(AT91_PIN_PA20, 0); /* GTX2 */ + at91_set_B_periph(AT91_PIN_PA21, 0); /* GTX3 */ + at91_set_B_periph(AT91_PIN_PA5, 0); /* GTXER */ + at91_set_B_periph(AT91_PIN_PA3, 0); /* GRXCK */ + at91_set_B_periph(AT91_PIN_PA18, 0); /* GRX2 */ + at91_set_B_periph(AT91_PIN_PA19, 0); /* GRX3 */ + case PHY_INTERFACE_MODE_RMII: + at91_set_B_periph(AT91_PIN_PA12, 0); /* GTX0 */ + at91_set_B_periph(AT91_PIN_PA13, 0); /* GTX1 */ + at91_set_B_periph(AT91_PIN_PA8, 0); /* GRX0 */ + at91_set_B_periph(AT91_PIN_PA9, 0); /* GRX1 */ + break; + default: + return; + } + + add_generic_device("macb", id, NULL, SAMA5D4_BASE_GMAC1, SZ_16K, + IORESOURCE_MEM, data); + break; + default: + return; + } + +} +#else +void at91_add_device_eth(int id, struct macb_platform_data *data) {} +#endif + +#if defined(CONFIG_MCI_ATMEL) +void __init at91_add_device_mci(short mmc_id, + struct atmel_mci_platform_data *data) +{ + resource_size_t start = ~0; + + if (!data) + return; + + /* Must have at least one usable slot */ + if (!data->bus_width) + return; + + /* input/irq */ + if (gpio_is_valid(data->detect_pin)) { + at91_set_gpio_input(data->detect_pin, 1); + at91_set_deglitch(data->detect_pin, 1); + } + + if (gpio_is_valid(data->wp_pin)) + at91_set_gpio_input(data->wp_pin, 1); + + switch (mmc_id) { + /* MCI0 */ + case 0: + start = SAMA5D4_BASE_HSMCI0; + + /* CLK */ + at91_set_B_periph(AT91_PIN_PC4, 0); + + /* CMD */ + at91_set_B_periph(AT91_PIN_PC5, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_B_periph(AT91_PIN_PC6, 1); + switch (data->bus_width) { + case 8: + at91_set_B_periph(AT91_PIN_PC10, 1); + at91_set_B_periph(AT91_PIN_PC11, 1); + at91_set_B_periph(AT91_PIN_PC12, 1); + at91_set_B_periph(AT91_PIN_PC13, 1); + case 4: + at91_set_B_periph(AT91_PIN_PC7, 1); + at91_set_B_periph(AT91_PIN_PC8, 1); + at91_set_B_periph(AT91_PIN_PC9, 1); + }; + + break; + /* MCI1 */ + case 1: + start = SAMA5D4_BASE_HSMCI1; + + /* + * As the mci1 io internal pull down is to strong, + * which cause external pull up doesn't work, so, + * disable internal pull down. + */ + + /* CLK */ + at91_set_C_periph(AT91_PIN_PE18, 0); + at91_set_pulldown(AT91_PIN_PE18, 0); + + /* CMD */ + at91_set_C_periph(AT91_PIN_PE19, 1); + at91_set_pulldown(AT91_PIN_PE19, 0); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_C_periph(AT91_PIN_PE20, 1); + at91_set_pulldown(AT91_PIN_PE20, 0); + if (data->bus_width == 4) { + at91_set_C_periph(AT91_PIN_PE21, 1); + at91_set_pulldown(AT91_PIN_PE21, 0); + at91_set_C_periph(AT91_PIN_PE22, 1); + at91_set_pulldown(AT91_PIN_PE22, 0); + at91_set_C_periph(AT91_PIN_PE23, 1); + at91_set_pulldown(AT91_PIN_PE23, 0); + } + + break; + } + + add_generic_device("atmel_mci", mmc_id, NULL, start, SZ_16K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_mci(short mmc_id, + struct atmel_mci_platform_data *data) {} +#endif + +#if defined(CONFIG_I2C_GPIO) +static struct i2c_gpio_platform_data pdata_i2c[] = { + { + .sda_pin = AT91_PIN_PA30, + .sda_is_open_drain = 1, + .scl_pin = AT91_PIN_PA31, + .scl_is_open_drain = 1, + .udelay = 5, /* ~100 kHz */ + }, { + .sda_pin = AT91_PIN_PE29, + .sda_is_open_drain = 1, + .scl_pin = AT91_PIN_PE30, + .scl_is_open_drain = 1, + .udelay = 5, /* ~100 kHz */ + }, { + .sda_pin = AT91_PIN_PB29, + .sda_is_open_drain = 1, + .scl_pin = AT91_PIN_PB30, + .scl_is_open_drain = 1, + .udelay = 5, /* ~100 kHz */ + }, { + .sda_pin = AT91_PIN_PC25, + .sda_is_open_drain = 1, + .scl_pin = AT91_PIN_PC26, + .scl_is_open_drain = 1, + .udelay = 5, /* ~100 kHz */ + } +}; + +void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, + int nr_devices) +{ + struct i2c_gpio_platform_data *pdata; + + if (i2c_id > ARRAY_SIZE(pdata_i2c)) + return; + + i2c_register_board_info(i2c_id, devices, nr_devices); + + pdata = &pdata_i2c[i2c_id]; + + at91_set_GPIO_periph(pdata->sda_pin, 1); /* TWD (SDA) */ + at91_set_multi_drive(pdata->sda_pin, 1); + + at91_set_GPIO_periph(pdata->scl_pin, 1); /* TWCK (SCL) */ + at91_set_multi_drive(pdata->scl_pin, 1); + + add_generic_device_res("i2c-gpio", i2c_id, NULL, 0, pdata); +} +#else +void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, + int nr_devices) {} +#endif + +/* -------------------------------------------------------------------- + * SPI + * -------------------------------------------------------------------- */ +#if defined(CONFIG_DRIVER_SPI_ATMEL) +static unsigned spi0_standard_cs[2] = { AT91_PIN_PC3, AT91_PIN_PC4 }; +static unsigned spi1_standard_cs[2] = { AT91_PIN_PB21, AT91_PIN_PB22 }; + +static struct at91_spi_platform_data spi_pdata[] = { + [0] = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), + }, + [1] = { + .chipselect = spi1_standard_cs, + .num_chipselect = ARRAY_SIZE(spi1_standard_cs), + }, +}; + +void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) +{ + int i; + int cs_pin; + resource_size_t start = ~0; + + BUG_ON(spi_id > 1); + + if (!pdata) + pdata = &spi_pdata[spi_id]; + + for (i = 0; i < pdata->num_chipselect; i++) { + cs_pin = pdata->chipselect[i]; + + /* enable chip-select pin */ + if (gpio_is_valid(cs_pin)) + at91_set_gpio_output(cs_pin, 1); + } + + /* Configure SPI bus(es) */ + switch (spi_id) { + case 0: + start = SAMA5D4_BASE_SPI0; + at91_set_A_periph(AT91_PIN_PC0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* SPI0_SPCK */ + break; + case 1: + start = SAMA5D4_BASE_SPI1; + at91_set_A_periph(AT91_PIN_PB18, 0); /* SPI1_MISO */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* SPI1_MOSI */ + at91_set_A_periph(AT91_PIN_PB20, 0); /* SPI1_SPCK */ + break; + } + + add_generic_device("atmel_spi", spi_id, NULL, start, SZ_16K, + IORESOURCE_MEM, pdata); +} +#else +void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} +#endif + +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + at91_set_A_periph(AT91_PIN_PA24, 0); /* LCDPWM */ + at91_set_A_periph(AT91_PIN_PA25, 0); /* LCDDISP */ + at91_set_A_periph(AT91_PIN_PA26, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PA28, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PA29, 0); /* LCDDEN */ + + at91_set_A_periph(AT91_PIN_PA2, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PA3, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PA4, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PA5, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PA6, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PA7, 0); /* LCDD7 */ + + at91_set_A_periph(AT91_PIN_PA10, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PA11, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PA15, 0); /* LCDD15 */ + + at91_set_A_periph(AT91_PIN_PA18, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PA19, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PA20, 0); /* LCDD20 */ + at91_set_A_periph(AT91_PIN_PA21, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PA22, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PA23, 0); /* LCDD23 */ + + add_generic_device("atmel_hlcdfb", DEVICE_ID_SINGLE, NULL, + SAMA5D4_BASE_LCDC, SZ_4K, IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + +/* -------------------------------------------------------------------- + * UART + * -------------------------------------------------------------------- */ +#if defined(CONFIG_DRIVER_SERIAL_ATMEL) +resource_size_t __init at91_configure_dbgu(void) +{ + at91_set_A_periph(AT91_PIN_PB25, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB24, 0); /* RXD1 */ + + return SAMA5D4_BASE_DBGU; +} + +resource_size_t __init at91_configure_usart0(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PD13, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD12, 0); /* RXD1 */ + + return SAMA5D4_BASE_USART0; +} + +resource_size_t __init at91_configure_usart1(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PD17, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD16, 0); /* RXD1 */ + + return SAMA5D4_BASE_USART1; +} + + +resource_size_t __init at91_configure_usart2(unsigned pins) +{ + at91_set_B_periph(AT91_PIN_PB5, 1); /* TXD1 */ + at91_set_B_periph(AT91_PIN_PB4, 0); /* RXD1 */ + + return SAMA5D4_BASE_USART2; +} + +resource_size_t __init at91_configure_usart3(unsigned pins) +{ + at91_set_B_periph(AT91_PIN_PE17, 1); /* TXD1 */ + at91_set_B_periph(AT91_PIN_PE16, 0); /* RXD1 */ + + return SAMA5D4_BASE_USART3; +} + +resource_size_t __init at91_configure_usart4(unsigned pins) +{ + at91_set_B_periph(AT91_PIN_PE27, 1); /* TXD1 */ + at91_set_B_periph(AT91_PIN_PE26, 0); /* RXD1 */ + + return SAMA5D4_BASE_USART4; +} + +resource_size_t __init at91_configure_usart5(unsigned pins) +{ + at91_set_B_periph(AT91_PIN_PE30, 1); /* TXD1 */ + at91_set_B_periph(AT91_PIN_PE29, 0); /* RXD1 */ + + return SAMA5D4_BASE_UART0; +} + +resource_size_t __init at91_configure_usart6(unsigned pins) +{ + at91_set_C_periph(AT91_PIN_PC26, 1); /* TXD1 */ + at91_set_C_periph(AT91_PIN_PC25, 0); /* RXD1 */ + + return SAMA5D4_BASE_UART1; +} +#endif diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 076d0812b3..030b8a2c58 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -39,6 +39,9 @@ static void __init soc_detect(u32 dbgu_base) cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR); socid = cidr & ~AT91_CIDR_VERSION; + /* sub version of soc */ + at91_soc_initdata.exid = __raw_readl(dbgu_base + AT91_DBGU_EXID); + switch (socid) { case ARCH_ID_AT91RM9200: at91_soc_initdata.type = AT91_SOC_RM9200; @@ -89,9 +92,16 @@ static void __init soc_detect(u32 dbgu_base) at91_boot_soc = at91sam9n12_soc; break; - case ARCH_ID_SAMA5D3: - at91_soc_initdata.type = AT91_SOC_SAMA5D3; - at91_boot_soc = at91sama5d3_soc; + case ARCH_ID_SAMA5: + if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) { + at91_soc_initdata.type = AT91_SOC_SAMA5D3; + at91_boot_soc = at91sama5d3_soc; + } else { + if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) { + at91_soc_initdata.type = AT91_SOC_SAMA5D4; + at91_boot_soc = at91sama5d4_soc; + } + } break; } @@ -112,9 +122,6 @@ static void __init soc_detect(u32 dbgu_base) at91_soc_initdata.cidr = cidr; - /* sub version of soc */ - at91_soc_initdata.exid = __raw_readl(dbgu_base + AT91_DBGU_EXID); - if (at91_soc_initdata.type == AT91_SOC_SAM9G45) { switch (at91_soc_initdata.exid) { case ARCH_EXID_AT91SAM9M10: @@ -168,6 +175,23 @@ static void __init soc_detect(u32 dbgu_base) break; } } + + if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) { + switch (at91_soc_initdata.exid) { + case ARCH_EXID_SAMA5D41: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D41; + break; + case ARCH_EXID_SAMA5D42: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D42; + break; + case ARCH_EXID_SAMA5D43: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D43; + break; + case ARCH_EXID_SAMA5D44: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D44; + break; + } + } } static const char *soc_name[] = { @@ -182,6 +206,7 @@ static const char *soc_name[] = { [AT91_SOC_SAM9X5] = "at91sam9x5", [AT91_SOC_SAM9N12] = "at91sam9n12", [AT91_SOC_SAMA5D3] = "sama5d3", + [AT91_SOC_SAMA5D4] = "sama5d4", [AT91_SOC_NONE] = "Unknown" }; @@ -209,6 +234,10 @@ static const char *soc_subtype_name[] = { [AT91_SOC_SAMA5D34] = "sama5d34", [AT91_SOC_SAMA5D35] = "sama5d35", [AT91_SOC_SAMA5D36] = "sama5d36", + [AT91_SOC_SAMA5D41] = "sama5d41", + [AT91_SOC_SAMA5D42] = "sama5d42", + [AT91_SOC_SAMA5D43] = "sama5d43", + [AT91_SOC_SAMA5D44] = "sama5d44", [AT91_SOC_SUBTYPE_NONE] = "Unknown" }; @@ -226,6 +255,8 @@ static int at91_detect(void) soc_detect(AT91_BASE_DBGU0); if (!at91_soc_is_detected()) soc_detect(AT91_BASE_DBGU1); + if (!at91_soc_is_detected()) + soc_detect(AT91_BASE_DBGU2); if (!at91_soc_is_detected()) panic("AT91: Impossible to detect the SOC type"); diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index b2278a5b32..76e4621f8a 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h @@ -19,6 +19,7 @@ extern struct at91_init_soc at91sam9rl_soc; extern struct at91_init_soc at91sam9x5_soc; extern struct at91_init_soc at91sam9n12_soc; extern struct at91_init_soc at91sama5d3_soc; +extern struct at91_init_soc at91sama5d4_soc; #define AT91_SOC_START(_name) \ struct at91_init_soc __initdata at91##_name##_soc \ @@ -66,6 +67,10 @@ static inline int at91_soc_is_enabled(void) #define at91sam9n12_soc at91_boot_soc #endif -#if !defined(CONFIG_SOC_SAMA5) +#if !defined(CONFIG_ARCH_SAMA5D3) #define at91sama5d3_soc at91_boot_soc #endif + +#if !defined(CONFIG_ARCH_SAMA5D4) +#define at91sama5d4_soc at91_boot_soc +#endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 53a44a06e9..ef7c0a1963 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -261,6 +261,10 @@ config MACH_TQMA6X bool "TQ tqma6x on mba6x" select ARCH_IMX6 +config MACH_TX6X + bool "Karo TX6x" + select ARCH_IMX6 + config MACH_SABRELITE bool "Freescale i.MX6 Sabre Lite" select ARCH_IMX6 @@ -291,6 +295,9 @@ config MACH_VARISCITE_MX6 bool "Variscite i.MX6 Quad SOM" select ARCH_IMX6 +config MACH_GW_VENTANA + bool "Gateworks Ventana SBC" + select ARCH_IMX6 endif diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h index bbfde2339a..b30037cf83 100644 --- a/arch/arm/mach-imx/include/mach/imx35-regs.h +++ b/arch/arm/mach-imx/include/mach/imx35-regs.h @@ -153,6 +153,7 @@ #define MX35_CCM_CGR1_FEC_SHIFT 0 #define MX35_CCM_CGR1_I2C1_SHIFT 10 #define MX35_CCM_CGR1_SDHC1_SHIFT 26 +#define MX35_CCM_CGR2_UART2_SHIFT 18 #define MX35_CCM_CGR2_USB_SHIFT 22 #define MX35_CCM_RCSR_MEM_CTRL_SHIFT 25 diff --git a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h index 69707f0976..ac2764f1b6 100644 --- a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h @@ -37,6 +37,9 @@ #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850 +#define MX6_MMDC_P0_MPRDDLHWCTL 0x021b0860 +#define MX6_MMDC_P0_MPWRDLHWCTL 0x021b0864 +#define MX6_MMDC_P0_MPPDCMPR2 0x021b0890 #define MX6_MMDC_P0_MPMUR0 0x021b08b8 #define MX6_MMDC_P1_MDCTL 0x021b4000 @@ -64,4 +67,7 @@ #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850 +#define MX6_MMDC_P1_MPRDDLHWCTL 0x021b4860 +#define MX6_MMDC_P1_MPWRDLHWCTL 0x021b4864 +#define MX6_MMDC_P1_MPPDCMPR2 0x021b4890 #define MX6_MMDC_P1_MPMUR0 0x021b48b8 diff --git a/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h index 541d00e244..a312e63a99 100644 --- a/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h @@ -12,6 +12,23 @@ * GNU General Public License for more details. */ +#define MX6_IOM_DRAM_ADDR00 0x020e0424 +#define MX6_IOM_DRAM_ADDR01 0x020e0428 +#define MX6_IOM_DRAM_ADDR10 0x020e042c +#define MX6_IOM_DRAM_ADDR11 0x020e0430 +#define MX6_IOM_DRAM_ADDR12 0x020e0434 +#define MX6_IOM_DRAM_ADDR13 0x020e0438 +#define MX6_IOM_DRAM_ADDR14 0x020e043c +#define MX6_IOM_DRAM_ADDR15 0x020e0440 +#define MX6_IOM_DRAM_ADDR02 0x020e0444 +#define MX6_IOM_DRAM_ADDR03 0x020e0448 +#define MX6_IOM_DRAM_ADDR04 0x020e044c +#define MX6_IOM_DRAM_ADDR05 0x020e0450 +#define MX6_IOM_DRAM_ADDR06 0x020e0454 +#define MX6_IOM_DRAM_ADDR07 0x020e0458 +#define MX6_IOM_DRAM_ADDR08 0x020e045c +#define MX6_IOM_DRAM_ADDR09 0x020e0460 + #define MX6_IOM_DRAM_DQM0 0x020e0470 #define MX6_IOM_DRAM_DQM1 0x020e0474 #define MX6_IOM_DRAM_DQM2 0x020e0478 @@ -24,6 +41,8 @@ #define MX6_IOM_DRAM_CAS 0x020e0464 #define MX6_IOM_DRAM_RAS 0x020e0490 #define MX6_IOM_DRAM_RESET 0x020e0494 +#define MX6_IOM_DRAM_SDBA0 0x020e0498 +#define MX6_IOM_DRAM_SDBA1 0x020e049c #define MX6_IOM_DRAM_SDCLK_0 0x020e04ac #define MX6_IOM_DRAM_SDCLK_1 0x020e04b0 #define MX6_IOM_DRAM_SDBA2 0x020e04a0 @@ -52,6 +71,7 @@ #define MX6_IOM_GRP_ADDDS 0x020e074c #define MX6_IOM_DDRMODE_CTL 0x020e0750 #define MX6_IOM_GRP_DDRPKE 0x020e0754 +#define MX6_IOM_GRP_DDRHYS 0x020e075c #define MX6_IOM_GRP_DDRMODE 0x020e0760 #define MX6_IOM_GRP_CTLDS 0x020e076c #define MX6_IOM_GRP_DDR_TYPE 0x020e0774 diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 3270f9265b..8323b66041 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -7,87 +7,77 @@ config ARCH_TEXT_BASE default 0x2000000 if ARCH_DOVE default 0x2000000 if ARCH_KIRKWOOD -choice - prompt "Marvell EBU Processor" - config ARCH_ARMADA_370 - bool "Armada 370" + bool select CPU_V7 select CLOCKSOURCE_MVEBU - select PINCTRL_ARMADA_370 config ARCH_ARMADA_XP - bool "Armada XP" + bool select CPU_V7 select CLOCKSOURCE_MVEBU - select PINCTRL_ARMADA_XP config ARCH_DOVE - bool "Dove 88AP510" + bool select CPU_V7 select CLOCKSOURCE_ORION - select PINCTRL_DOVE config ARCH_KIRKWOOD - bool "Kirkwood" + bool select CPU_FEROCEON select CLOCKSOURCE_ORION - select PINCTRL_KIRKWOOD - -endchoice # # Armada 370 SoC boards # -if ARCH_ARMADA_370 +comment "Armada 370 based boards" config MACH_GLOBALSCALE_MIRABOX bool "Globalscale Mirabox" - -endif # ARCH_ARMADA_370 + select ARCH_ARMADA_370 # # Armada XP SoC boards # -if ARCH_ARMADA_XP +comment "Armada XP based boards" config MACH_PLATHOME_OPENBLOCKS_AX3 bool "PlatHome OpenBlocks AX3" + select ARCH_ARMADA_XP config MACH_MARVELL_ARMADA_XP_GP bool "Marvell Armada XP GP" - -endif # ARCH_ARMADA_XP + select ARCH_ARMADA_XP # # Dove 88AP510 SoC boards # -if ARCH_DOVE +comment "Dove based boards" config MACH_SOLIDRUN_CUBOX bool "SolidRun CuBox" - -endif # ARCH_DOVE + select ARCH_DOVE # # Kirkwood SoC boards # -if ARCH_KIRKWOOD +comment "Kirkwood based boards" config MACH_GLOBALSCALE_GURUPLUG bool "Guruplug" + select ARCH_KIRKWOOD config MACH_PLATHOME_OPENBLOCKS_A6 bool "PlatHome OpenBlocks A6" + select ARCH_KIRKWOOD config MACH_USI_TOPKICK bool "Topkick" - -endif # ARCH_KIRKWOOD + select ARCH_KIRKWOOD # # Common options diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index f2b991e5a7..57f6a5fe0d 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -44,11 +44,24 @@ static inline void armada_370_xp_memory_find(unsigned long *phys_base, } } -static int armada_370_xp_init_soc(void) +static void __noreturn armada_370_xp_reset_cpu(unsigned long addr) +{ + writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x60); + writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x64); + while (1) + ; +} + +static int armada_370_xp_init_soc(struct device_node *root, void *context) { unsigned long phys_base, phys_size; u32 reg; + if (!of_machine_is_compatible("marvell,armada-370-xp")) + return 0; + + mvebu_set_reset(armada_370_xp_reset_cpu); + barebox_set_model("Marvell Armada 370/XP"); barebox_set_hostname("armada"); @@ -60,17 +73,14 @@ static int armada_370_xp_init_soc(void) armada_370_xp_memory_find(&phys_base, &phys_size); mvebu_set_memory(phys_base, phys_size); - mvebu_mbus_add_range(0xf0, 0x01, MVEBU_REMAP_INT_REG_BASE); return 0; } -core_initcall(armada_370_xp_init_soc); -void __noreturn reset_cpu(unsigned long addr) +static int armada_370_xp_register_soc_fixup(void) { - writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x60); - writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x64); - while (1) - ; + mvebu_mbus_add_range("marvell,armada-370-xp", 0xf0, 0x01, + MVEBU_REMAP_INT_REG_BASE); + return of_register_fixup(armada_370_xp_init_soc, NULL); } -EXPORT_SYMBOL(reset_cpu); +pure_initcall(armada_370_xp_register_soc_fixup); diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c index ac4b332e01..309f7a6aaa 100644 --- a/arch/arm/mach-mvebu/common.c +++ b/arch/arm/mach-mvebu/common.c @@ -21,6 +21,7 @@ #include <of.h> #include <of_address.h> #include <linux/clk.h> +#include <mach/common.h> /* * Marvell MVEBU SoC id and revision can be read from any PCIe @@ -80,29 +81,21 @@ static int mvebu_soc_id_init(void) } postcore_initcall(mvebu_soc_id_init); -static u64 mvebu_mem[2]; - -void mvebu_set_memory(u64 phys_base, u64 phys_size) -{ - mvebu_mem[0] = phys_base; - mvebu_mem[1] = phys_size; -} - /* * Memory size is set up by BootROM and can be read from SoC's ram controller * registers. Fixup provided DTs to reflect accessible amount of directly * attached RAM. Removable RAM, e.g. SODIMM, should be added by a per-board * fixup. */ -static int mvebu_memory_of_fixup(struct device_node *root, void *context) +int mvebu_set_memory(u64 phys_base, u64 phys_size) { - struct device_node *np; + struct device_node *np, *root; __be32 reg[4]; int na, ns; - /* bail out on zero-sized mem */ - if (!mvebu_mem[1]) - return -ENODEV; + root = of_get_root_node(); + if (!root) + return -EINVAL; np = of_find_node_by_path("/memory"); if (!np) @@ -114,17 +107,17 @@ static int mvebu_memory_of_fixup(struct device_node *root, void *context) ns = of_n_size_cells(np); if (na == 2) { - reg[0] = cpu_to_be32(mvebu_mem[0] >> 32); - reg[1] = cpu_to_be32(mvebu_mem[0] & 0xffffffff); + reg[0] = cpu_to_be32(phys_base >> 32); + reg[1] = cpu_to_be32(phys_base & 0xffffffff); } else { - reg[0] = cpu_to_be32(mvebu_mem[0] & 0xffffffff); + reg[0] = cpu_to_be32(phys_base & 0xffffffff); } if (ns == 2) { - reg[2] = cpu_to_be32(mvebu_mem[1] >> 32); - reg[3] = cpu_to_be32(mvebu_mem[1] & 0xffffffff); + reg[2] = cpu_to_be32(phys_size >> 32); + reg[3] = cpu_to_be32(phys_size & 0xffffffff); } else { - reg[1] = cpu_to_be32(mvebu_mem[1] & 0xffffffff); + reg[1] = cpu_to_be32(phys_size & 0xffffffff); } if (of_set_property(np, "device_type", "memory", sizeof("memory"), 1) || @@ -134,7 +127,15 @@ static int mvebu_memory_of_fixup(struct device_node *root, void *context) return 0; } -static int mvebu_memory_fixup_register(void) { - return of_register_fixup(mvebu_memory_of_fixup, NULL); +static __noreturn void (*mvebu_reset_cpu)(unsigned long addr); + +void __noreturn reset_cpu(unsigned long addr) +{ + mvebu_reset_cpu(addr); +} +EXPORT_SYMBOL(reset_cpu); + +void mvebu_set_reset(void __noreturn (*reset)(unsigned long addr)) +{ + mvebu_reset_cpu = reset; } -pure_initcall(mvebu_memory_fixup_register); diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c index 69c6436b24..c2852f8986 100644 --- a/arch/arm/mach-mvebu/dove.c +++ b/arch/arm/mach-mvebu/dove.c @@ -68,10 +68,24 @@ static inline void dove_memory_find(unsigned long *phys_base, } } -static int dove_init_soc(void) +static void __noreturn dove_reset_cpu(unsigned long addr) +{ + /* enable and assert RSTOUTn */ + writel(SOFT_RESET_OUT_EN, DOVE_BRIDGE_BASE + BRIDGE_RSTOUT_MASK); + writel(SOFT_RESET_EN, DOVE_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET); + while (1) + ; +} + +static int dove_init_soc(struct device_node *root, void *context) { unsigned long phys_base, phys_size; + if (!of_machine_is_compatible("marvell,dove")) + return 0; + + mvebu_set_reset(dove_reset_cpu); + barebox_set_model("Marvell Dove"); barebox_set_hostname("dove"); @@ -79,19 +93,16 @@ static int dove_init_soc(void) dove_memory_find(&phys_base, &phys_size); mvebu_set_memory(phys_base, phys_size); - mvebu_mbus_add_range(0xf0, 0x01, MVEBU_REMAP_INT_REG_BASE); - mvebu_mbus_add_range(0xf0, 0x02, DOVE_REMAP_MC_REGS); return 0; } -core_initcall(dove_init_soc); -void __noreturn reset_cpu(unsigned long addr) +static int dove_register_soc_fixup(void) { - /* enable and assert RSTOUTn */ - writel(SOFT_RESET_OUT_EN, DOVE_BRIDGE_BASE + BRIDGE_RSTOUT_MASK); - writel(SOFT_RESET_EN, DOVE_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET); - while (1) - ; + mvebu_mbus_add_range("marvell,dove", 0xf0, 0x01, + MVEBU_REMAP_INT_REG_BASE); + mvebu_mbus_add_range("marvell,dove", 0xf0, 0x02, + DOVE_REMAP_MC_REGS); + return of_register_fixup(dove_init_soc, NULL); } -EXPORT_SYMBOL(reset_cpu); +pure_initcall(dove_register_soc_fixup); diff --git a/arch/arm/mach-mvebu/include/mach/common.h b/arch/arm/mach-mvebu/include/mach/common.h index 9f6118e4ec..5ce33fd882 100644 --- a/arch/arm/mach-mvebu/include/mach/common.h +++ b/arch/arm/mach-mvebu/include/mach/common.h @@ -20,6 +20,7 @@ #define MVEBU_REMAP_INT_REG_BASE 0xf1000000 -void mvebu_set_memory(u64 phys_base, u64 phys_size); +int mvebu_set_memory(u64 phys_base, u64 phys_size); +void mvebu_set_reset(void __noreturn (*reset)(unsigned long addr)); #endif diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c index c114bdb360..d7903f732e 100644 --- a/arch/arm/mach-mvebu/kirkwood.c +++ b/arch/arm/mach-mvebu/kirkwood.c @@ -43,27 +43,37 @@ static inline void kirkwood_memory_find(unsigned long *phys_base, } } -static int kirkwood_init_soc(void) +static void __noreturn kirkwood_reset_cpu(unsigned long addr) +{ + writel(SOFT_RESET_OUT_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_RSTOUT_MASK); + writel(SOFT_RESET_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET); + for(;;) + ; +} + +static int kirkwood_init_soc(struct device_node *root, void *context) { unsigned long phys_base, phys_size; + if (!of_machine_is_compatible("marvell,kirkwood")) + return 0; + + mvebu_set_reset(kirkwood_reset_cpu); + barebox_set_model("Marvell Kirkwood"); barebox_set_hostname("kirkwood"); kirkwood_memory_find(&phys_base, &phys_size); mvebu_set_memory(phys_base, phys_size); - mvebu_mbus_add_range(0xf0, 0x01, MVEBU_REMAP_INT_REG_BASE); return 0; } -core_initcall(kirkwood_init_soc); -void __noreturn reset_cpu(unsigned long addr) +static int kirkwood_register_soc_fixup(void) { - writel(SOFT_RESET_OUT_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_RSTOUT_MASK); - writel(SOFT_RESET_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET); - for(;;) - ; + mvebu_mbus_add_range("marvell,kirkwood", 0xf0, 0x01, + MVEBU_REMAP_INT_REG_BASE); + return of_register_fixup(kirkwood_init_soc, NULL); } -EXPORT_SYMBOL(reset_cpu); +pure_initcall(kirkwood_register_soc_fixup); diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index 732de15fec..e30027ef2e 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -93,15 +93,16 @@ config BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO Say Y for barebox update SPI NOR MLO handler. AM35xx, AM33xx chips use big endian MLO for SPI NOR flash. -config BAREBOX_UPDATE_AM33XX_NAND_XLOADSLOTS - prompt "barebox update nand xload slots handler" +config BAREBOX_UPDATE_AM33XX_NAND + prompt "barebox update NAND handler" bool depends on BAREBOX_UPDATE help - Say Y for barebox update nand xload slots handler. - This update handler updates 4 default nand xload slots - with a single command. + Say Y for barebox update NAND handler. This update handler updates + 4 default NAND xload slots with a single command. The Handler also checks if the given image has a valid CH header. + This also includes a handler for updating the regular barebox binary + in NAND. config ARCH_TEXT_BASE hex @@ -124,6 +125,12 @@ config OMAP_MULTI_BOARDS if OMAP_MULTI_BOARDS +config MACH_AFI_GF + bool "af inventions GF" + select ARCH_AM33XX + help + Say Y here if you are using afis GF + config MACH_BEAGLEBONE bool "Texas Instrument's Beagle Bone" select ARCH_AM33XX @@ -135,6 +142,7 @@ config MACH_PCM051 select ARCH_AM33XX help Say Y here if you are using Phytecs phyCORE pcm051 board + endif choice diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile index 0ebfae7437..bef1d0500f 100644 --- a/arch/arm/mach-omap/Makefile +++ b/arch/arm/mach-omap/Makefile @@ -33,4 +33,4 @@ obj-$(CONFIG_MFD_TWL6030) += omap4_twl6030_mmc.o obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o obj-$(CONFIG_CMD_BOOT_ORDER) += boot_order.o obj-$(CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO) += am33xx_bbu_spi_mlo.o -obj-$(CONFIG_BAREBOX_UPDATE_AM33XX_NAND_XLOADSLOTS) += am33xx_bbu_nand_xloadslots.o +obj-$(CONFIG_BAREBOX_UPDATE_AM33XX_NAND) += am33xx_bbu_nand.o diff --git a/arch/arm/mach-omap/am33xx_bbu_nand_xloadslots.c b/arch/arm/mach-omap/am33xx_bbu_nand.c index 0b4f1ccf05..ee767d32e4 100644 --- a/arch/arm/mach-omap/am33xx_bbu_nand_xloadslots.c +++ b/arch/arm/mach-omap/am33xx_bbu_nand.c @@ -80,12 +80,12 @@ static int nand_xloadslots_update_handler(struct bbu_handler *handler, nh = container_of(handler, struct nand_bbu_handler, bbu_handler); + ret = bbu_confirm(data); + if (ret != 0) + return ret; + /* check if the devicefile has been overwritten */ if (strcmp(data->devicefile, nh->devicefile[0]) != 0) { - ret = bbu_confirm(data); - if (ret != 0) - return ret; - ret = write_image(data->devicefile, image, size); if (ret != 0) return ret; @@ -120,3 +120,42 @@ int am33xx_bbu_nand_xloadslots_register_handler(const char *name, return ret; } + +static int nand_update_handler(struct bbu_handler *handler, + struct bbu_data *data) +{ + int ret = 0; + const void *image = data->image; + size_t size = data->len; + struct nand_bbu_handler *nh; + + if (file_detect_type(image, size) != filetype_arm_barebox) { + pr_err("%s is not a valid barebox image\n", data->imagefile); + return -EINVAL; + } + + nh = container_of(handler, struct nand_bbu_handler, bbu_handler); + + ret = bbu_confirm(data); + if (ret != 0) + return ret; + + return write_image(data->devicefile, image, size); +} + +int am33xx_bbu_nand_register_handler(const char *name, char *devicefile) +{ + struct nand_bbu_handler *handler; + int ret; + + handler = xzalloc(sizeof(*handler)); + handler->bbu_handler.devicefile = devicefile; + handler->bbu_handler.handler = nand_update_handler; + handler->bbu_handler.name = name; + + ret = bbu_register_handler(&handler->bbu_handler); + if (ret) + free(handler); + + return ret; +} diff --git a/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c index 8ac0a185c0..97dc54ee10 100644 --- a/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c +++ b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c @@ -19,6 +19,7 @@ #include <bbu.h> #include <fs.h> #include <fcntl.h> +#include <linux/stat.h> /* * AM35xx, AM33xx chips use big endian MLO for SPI NOR flash @@ -34,17 +35,34 @@ static int spi_nor_mlo_handler(struct bbu_handler *handler, void *image = data->image; uint32_t *header; int swap = 0; + struct stat s; header = data->image; - if (header[5] == 0x43485345) { + + if (header[5] == 0x43485345 || header[10] == 0x62617265) { swap = 0; - } else if (header[5] == 0x45534843) { + } else if (header[5] == 0x45534843 || header[10] == 0x65726142) { swap = 1; } else { if (!bbu_force(data, "Not a MLO image")) return -EINVAL; } + ret = stat(data->devicefile, &s); + if (ret) { + printf("could not open %s: %s", data->devicefile, errno_str()); + return ret; + } + + if (size > s.st_size) { + printf("Image too big, need %d, have %lld\n", size, s.st_size); + return -ENOSPC; + } + + ret = bbu_confirm(data); + if (ret != 0) + return ret; + dstfd = open(data->devicefile, O_WRONLY); if (dstfd < 0) { printf("could not open %s: %s", data->devicefile, errno_str()); diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c index 9105ddc8b8..6d8addef32 100644 --- a/arch/arm/mach-omap/am33xx_clock.c +++ b/arch/arm/mach-omap/am33xx_clock.c @@ -88,8 +88,10 @@ static void power_domain_transition_enable(void) /* * Enable the module clock and the power domain for required peripherals */ -static void per_clocks_enable(void) +void am33xx_enable_per_clocks(void) { + u32 clkdcoldo; + /* Enable the module clock */ __raw_writel(PRCM_MOD_EN, CM_PER_TIMER2_CLKCTRL); while (__raw_readl(CM_PER_TIMER2_CLKCTRL) != PRCM_MOD_EN); @@ -154,6 +156,15 @@ static void per_clocks_enable(void) __raw_writel(PRCM_MOD_EN, CM_PER_SPI1_CLKCTRL); while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN); + + /* USB */ + __raw_writel(PRCM_MOD_EN, CM_PER_USB0_CLKCTRL); + while ((__raw_readl(CM_PER_USB0_CLKCTRL) & 0x30000) != 0x0); + + clkdcoldo = __raw_readl(CM_CLKDCOLDO_DPLL_PER); + clkdcoldo = clkdcoldo | 0x100; + __raw_writel(clkdcoldo, CM_CLKDCOLDO_DPLL_PER); + while ((__raw_readl(CM_CLKDCOLDO_DPLL_PER) & 0x00000200) != 0x200); } static void mpu_pll_config(int mpupll_M, int osc) @@ -305,5 +316,5 @@ void am33xx_pll_init(int mpupll_M, int osc, int ddrpll_M) /* Enable power domain transition */ power_domain_transition_enable(); /* Enable the required peripherals */ - per_clocks_enable(); + am33xx_enable_per_clocks(); } diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 71c528ca8b..f2931340cb 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -207,6 +207,8 @@ int am33xx_init(void) { omap_gpmc_base = (void *)AM33XX_GPMC_BASE; + am33xx_enable_per_clocks(); + return am33xx_bootsource(); } diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index 10c2f29dcd..2d6a727e1c 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -44,6 +44,7 @@ /* DDR Freq is 266 MHZ for now*/ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ +#define DDRPLL_M_200 200 #define DDRPLL_M_266 266 #define DDRPLL_M_303 303 #define DDRPLL_M_400 400 @@ -74,6 +75,7 @@ #define CM_CLKMODE_DPLL_PER (CM_WKUP + 0x8c) #define CM_DIV_M2_DPLL_PER (CM_WKUP + 0xAC) #define CM_IDLEST_DPLL_PER (CM_WKUP + 0x70) +#define CM_CLKDCOLDO_DPLL_PER (CM_WKUP + 0x7C) /* for USB_PHY clock */ /* Display PLL */ #define CM_CLKSEL_DPLL_DISP (CM_WKUP + 0x54) @@ -140,6 +142,7 @@ #define CM_PER_MMC0_CLKCTRL (CM_PER + 0x3C) #define CM_PER_MMC1_CLKCTRL (CM_PER + 0xF4) #define CM_PER_MMC2_CLKCTRL (CM_PER + 0xF8) +#define CM_PER_USB0_CLKCTRL (CM_PER + 0x1c) /* USB */ /* PRCM */ #define CM_DPLL_OFFSET (AM33XX_PRM_BASE + 0x0300) diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h b/arch/arm/mach-omap/include/mach/am33xx-generic.h index 75ac00aa51..6c85d51597 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-generic.h +++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h @@ -30,6 +30,7 @@ u32 am33xx_running_in_sdram(void); void __noreturn am33xx_reset_cpu(unsigned long addr); +void am33xx_enable_per_clocks(void); int am33xx_init(void); int am33xx_devices_init(void); diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index ceca10a619..a44973e979 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -125,10 +125,10 @@ /* DDR offsets */ #define AM33XX_DDR_PHY_BASE_ADDR 0x44E12000 -#define AM33XX_DDR_IO_CTRL 0x44E10E04 -#define AM33XX_DDR_CKE_CTRL 0x44E1131C #define AM33XX_CONTROL_BASE_ADDR 0x44E10000 +#define AM33XX_DDR_IO_CTRL (AM33XX_CONTROL_BASE_ADDR + 0x0E04) +#define AM33XX_DDR_CKE_CTRL (AM33XX_CONTROL_BASE_ADDR + 0x131C) #define AM33XX_DDR_CMD0_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1404) #define AM33XX_DDR_CMD1_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1408) #define AM33XX_DDR_CMD2_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x140C) diff --git a/arch/arm/mach-omap/include/mach/bbu.h b/arch/arm/mach-omap/include/mach/bbu.h index 8c4c5e3eb8..36d87e1a00 100644 --- a/arch/arm/mach-omap/include/mach/bbu.h +++ b/arch/arm/mach-omap/include/mach/bbu.h @@ -18,10 +18,11 @@ static inline int am33xx_bbu_spi_nor_register_handler(const char *name, char *de } #endif -#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_NAND_XLOADSLOTS +#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_NAND int am33xx_bbu_nand_xloadslots_register_handler(const char *name, char **devicefile, int num_devicefiles); +int am33xx_bbu_nand_register_handler(const char *name, char *devicefile); #else static inline int am33xx_bbu_nand_xloadslots_register_handler(const char *name, char **devicefile, @@ -29,6 +30,11 @@ static inline int am33xx_bbu_nand_xloadslots_register_handler(const char *name, { return 0; } + +static inline int am33xx_bbu_nand_register_handler(const char *name, char *devicefile) +{ + return 0; +} #endif #endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index d8bf067430..12585c5476 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -2,3 +2,4 @@ obj-y += generic.o nic301.o bootsource.o reset-manager.o pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o pbl-y += clock-manager.o iocsr-config-cyclone5.o obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o +obj-$(CONFIG_ARCH_SOCFPGA_FPGA) += fpga.o diff --git a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h b/arch/arm/mach-socfpga/include/mach/socfpga-regs.h index 9d1e677cb7..b124ed675c 100644 --- a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h +++ b/arch/arm/mach-socfpga/include/mach/socfpga-regs.h @@ -2,10 +2,12 @@ #define __MACH_SOCFPGA_REGS_H #define CYCLONE5_SDMMC_ADDRESS 0xff704000 +#define CYCLONE5_FPGAMGRREGS_ADDRESS 0xff706000 #define CYCLONE5_GPIO0_BASE 0xff708000 #define CYCLONE5_GPIO1_BASE 0xff709000 #define CYCLONE5_GPIO2_BASE 0xff70A000 #define CYCLONE5_L3REGS_ADDRESS 0xff800000 +#define CYCLONE5_FPGAMGRDATA_ADDRESS 0xffb90000 #define CYCLONE5_UART0_ADDRESS 0xffc02000 #define CYCLONE5_UART1_ADDRESS 0xffc03000 #define CYCLONE5_SDR_ADDRESS 0xffc20000 diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 7214ecaf3a..2c69406dfc 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -44,15 +44,12 @@ endchoice config ARCH_TEGRA_2x_SOC bool - select PINCTRL_TEGRA20 config ARCH_TEGRA_3x_SOC bool - select PINCTRL_TEGRA30 config ARCH_TEGRA_124_SOC bool - select PINCTRL_TEGRA30 menu "select Tegra boards to be built" diff --git a/arch/blackfin/boards/ipe337/.gitignore b/arch/blackfin/boards/ipe337/.gitignore new file mode 100644 index 0000000000..d1165788c9 --- /dev/null +++ b/arch/blackfin/boards/ipe337/.gitignore @@ -0,0 +1 @@ +barebox.lds diff --git a/arch/efi/Makefile b/arch/efi/Makefile index af280859f0..85cb655615 100644 --- a/arch/efi/Makefile +++ b/arch/efi/Makefile @@ -24,7 +24,7 @@ cmd_barebox__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_barebox) -o $@ \ $(filter-out $(barebox-lds) $(barebox-common) FORCE ,$^) quiet_cmd_efi_image = EFI-IMG $@ - cmd_efi_image = objcopy -j .text -j .sdata -j .data -j .dynamic \ + cmd_efi_image = $(OBJCOPY) -j .text -j .sdata -j .data -j .dynamic \ -j .dynsym -j .rel -j .rela -j .reloc -j __barebox_initcalls \ -j __barebox_cmd -j .barebox_magicvar -j .bbenv.* \ --target=$(TARGET) $< $@ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bc68c679d5..40d5d83732 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -82,7 +82,6 @@ config MACH_MIPS_LOONGSON config MACH_MIPS_XBURST bool "Ingenic XBurst-based boards" - select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_32BIT_KERNEL select DRIVER_SERIAL_NS16550 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a3cf112b79..f3f4f67d86 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -89,6 +89,7 @@ board-$(CONFIG_BOARD_LOONGSON_TECH_LS1B) := loongson-ls1b machine-$(CONFIG_MACH_MIPS_XBURST) := xburst board-$(CONFIG_BOARD_RZX50) := ritmix-rzx50 +board-$(CONFIG_BOARD_CI20) := img-ci20 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) diff --git a/arch/mips/boards/img-ci20/Makefile b/arch/mips/boards/img-ci20/Makefile new file mode 100644 index 0000000000..dcfc2937d3 --- /dev/null +++ b/arch/mips/boards/img-ci20/Makefile @@ -0,0 +1 @@ +obj-y += board.o diff --git a/arch/mips/boards/img-ci20/board.c b/arch/mips/boards/img-ci20/board.c new file mode 100644 index 0000000000..515ebaece6 --- /dev/null +++ b/arch/mips/boards/img-ci20/board.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <init.h> + +static int ci20_hostname_init(void) +{ + barebox_set_hostname("ci20"); + + return 0; +} +console_initcall(ci20_hostname_init); diff --git a/arch/mips/boards/img-ci20/include/board/board_pbl_start.h b/arch/mips/boards/img-ci20/include/board/board_pbl_start.h new file mode 100644 index 0000000000..26232f58c5 --- /dev/null +++ b/arch/mips/boards/img-ci20/include/board/board_pbl_start.h @@ -0,0 +1,43 @@ +/* + * Startup Code for Imagination Creator CI20 board + * + * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm/pbl_macros.h> +#include <mach/debug_ll.h> +#include <asm/pbl_nmon.h> + + .macro board_pbl_start + .set push + .set noreorder + + mips_disable_interrupts + + /* CPU/SoC specific setup ... */ + /* ... absent */ + + debug_ll_ns16550_init + + debug_ll_ns16550_outc '.' + debug_ll_ns16550_outnl + + mips_nmon + + copy_to_link_location pbl_start + + .set pop + .endm diff --git a/arch/mips/boards/img-ci20/include/board/debug_ll.h b/arch/mips/boards/img-ci20/include/board/debug_ll.h new file mode 100644 index 0000000000..72612cff2b --- /dev/null +++ b/arch/mips/boards/img-ci20/include/board/debug_ll.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __INCLUDE_CI20_BOARD_DEBUG_LL_H__ +#define __INCLUDE_CI20_BOARD_DEBUG_LL_H__ + +#include <mach/debug_ll_jz4780.h> + +#endif /* __INCLUDE_CI20_BOARD_DEBUG_LL_H__ */ diff --git a/arch/mips/configs/img-ci20_defconfig b/arch/mips/configs/img-ci20_defconfig new file mode 100644 index 0000000000..56235c4cf3 --- /dev/null +++ b/arch/mips/configs/img-ci20_defconfig @@ -0,0 +1,42 @@ +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="img-ci20" +CONFIG_MACH_MIPS_XBURST=y +CONFIG_BOARD_CI20=y +CONFIG_PBL_IMAGE=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +CONFIG_POLLER=y +CONFIG_DEBUG_LL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_SAVES=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_GETOPT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_OFDEVICE=y +# CONFIG_SPI is not set +CONFIG_CLOCKSOURCE_DUMMY=y +CONFIG_CLOCKSOURCE_DUMMY_RATE=3500 +CONFIG_SHA1=y +CONFIG_SHA224=y +CONFIG_SHA256=y diff --git a/arch/mips/configs/ritmix-rzx50_defconfig b/arch/mips/configs/ritmix-rzx50_defconfig index fb67014532..0814883e89 100644 --- a/arch/mips/configs/ritmix-rzx50_defconfig +++ b/arch/mips/configs/ritmix-rzx50_defconfig @@ -1,7 +1,7 @@ CONFIG_BUILTIN_DTB=y CONFIG_BUILTIN_DTB_NAME="rzx50" CONFIG_MACH_MIPS_XBURST=y -CONFIG_JZ4750D_DEBUG_LL_UART1=y +CONFIG_JZ47XX_DEBUG_LL_UART1=y CONFIG_PBL_IMAGE=y CONFIG_BAUDRATE=57600 CONFIG_GLOB=y @@ -12,6 +12,7 @@ CONFIG_AUTO_COMPLETE=y CONFIG_DEBUG_LL=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y diff --git a/arch/mips/dts/ar9331.dtsi b/arch/mips/dts/ar9331.dtsi index 8280588ab3..8e7afcddff 100644 --- a/arch/mips/dts/ar9331.dtsi +++ b/arch/mips/dts/ar9331.dtsi @@ -10,24 +10,24 @@ device_type = "soc"; ranges; - serial0: serial@b8020000 { + serial0: serial@18020000 { compatible = "qca,ar9330-uart"; - reg = <0xb8020000 0x14>; + reg = <0x18020000 0x14>; clocks = <&ar9331_clk AR933X_CLK_UART>; status = "disabled"; }; ar9331_clk: clock { compatible = "qca,ar933x-clk"; - reg = <0xb8050000 0x48>; + reg = <0x18050000 0x48>; #clock-cells = <1>; }; - spi: spi@bf000000{ + spi: spi@1f000000{ #address-cells = <1>; #size-cells = <0>; compatible = "qca,ath79-spi"; - reg = <0xbf000000 0x01000000>; + reg = <0x1f000000 0x01000000>; status = "disabled"; }; }; diff --git a/arch/mips/dts/dlink-dir-320.dts b/arch/mips/dts/dlink-dir-320.dts index bad41d9da7..b961c9dca3 100644 --- a/arch/mips/dts/dlink-dir-320.dts +++ b/arch/mips/dts/dlink-dir-320.dts @@ -17,9 +17,9 @@ device_type = "soc"; ranges; - serial0: serial@b8000300 { + serial0: serial@18000300 { compatible = "ns16550a"; - reg = <0xb8000300 0x08>; + reg = <0x18000300 0x08>; reg-shift = <0>; clock-frequency = <25804800>; status = "disabled"; diff --git a/arch/mips/dts/img-ci20.dts b/arch/mips/dts/img-ci20.dts new file mode 100644 index 0000000000..f2022dd273 --- /dev/null +++ b/arch/mips/dts/img-ci20.dts @@ -0,0 +1,35 @@ +/* + * CI20 device tree + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/dts-v1/; + +#include "jz4780.dtsi" + +/ { + model = "MIPS Creator CI20"; + compatible = "img,ci20"; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/mips/dts/jz4755.dtsi b/arch/mips/dts/jz4755.dtsi index b83d884a24..137156df7e 100644 --- a/arch/mips/dts/jz4755.dtsi +++ b/arch/mips/dts/jz4755.dtsi @@ -8,35 +8,35 @@ #size-cells = <1>; ranges; - wdt: wdt@b0002000 { + wdt: wdt@10002000 { compatible = "ingenic,jz4740-wdt"; - reg = <0xb0002000 0x10>; + reg = <0x10002000 0x10>; }; rtc: rtc@10003000 { compatible = "ingenic,jz4740-rtc"; - reg = <0xb0003000 0x38>; + reg = <0x10003000 0x38>; }; - serial0: serial@b0030000 { + serial0: serial@10030000 { compatible = "ingenic,jz4740-uart"; - reg = <0xb0030000 0x20>; + reg = <0x10030000 0x20>; reg-shift = <2>; clock-frequency = <12000000>; status = "disabled"; }; - serial1: serial@b0031000 { + serial1: serial@10031000 { compatible = "ingenic,jz4740-uart"; - reg = <0xb0031000 0x20>; + reg = <0x10031000 0x20>; reg-shift = <2>; clock-frequency = <12000000>; status = "disabled"; }; - serial2: serial@b0032000 { + serial2: serial@10032000 { compatible = "ingenic,jz4740-uart"; - reg = <0xb0032000 0x20>; + reg = <0x10032000 0x20>; reg-shift = <2>; clock-frequency = <12000000>; status = "disabled"; @@ -45,42 +45,42 @@ gpio0: gpio@10010000 { compatible = "ingenic,jz4740-gpio"; gpio-controller; - reg = <0xb0010000 0x100>; + reg = <0x10010000 0x100>; #gpio-cells = <2>; }; gpio1: gpio@10010100 { compatible = "ingenic,jz4740-gpio"; gpio-controller; - reg = <0xb0010100 0x100>; + reg = <0x10010100 0x100>; #gpio-cells = <2>; }; gpio2: gpio@10010200 { compatible = "ingenic,jz4740-gpio"; gpio-controller; - reg = <0xb0010200 0x100>; + reg = <0x10010200 0x100>; #gpio-cells = <2>; }; gpio3: gpio@10010300 { compatible = "ingenic,jz4740-gpio"; gpio-controller; - reg = <0xb0010300 0x100>; + reg = <0x10010300 0x100>; #gpio-cells = <2>; }; gpio4: gpio@10010400 { compatible = "ingenic,jz4740-gpio"; gpio-controller; - reg = <0xb0010400 0x100>; + reg = <0x10010400 0x100>; #gpio-cells = <2>; }; gpio5: gpio@10010500 { compatible = "ingenic,jz4740-gpio"; gpio-controller; - reg = <0xb0010500 0x100>; + reg = <0x10010500 0x100>; #gpio-cells = <2>; }; }; diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi new file mode 100644 index 0000000000..9f0de5d1ae --- /dev/null +++ b/arch/mips/dts/jz4780.dtsi @@ -0,0 +1,56 @@ +#include "skeleton.dtsi" + +/ { + soc { + model = "Ingenic JZ4780"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <>; + + wdt: wdt@10002000 { + compatible = "ingenic,jz4740-wdt"; + reg = <0x10002000 0x10>; + }; + + uart0: serial@10030000 { + compatible = "ingenic,jz4740-uart"; + reg = <0x10030000 0x100>; + reg-shift = <2>; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart1: serial@10031000 { + compatible = "ingenic,jz4740-uart"; + reg = <0x10031000 0x100>; + reg-shift = <2>; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart2: serial@10032000 { + compatible = "ingenic,jz4740-uart"; + reg = <0x10032000 0x100>; + reg-shift = <2>; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart3: serial@10033000 { + compatible = "ingenic,jz4740-uart"; + reg = <0x10033000 0x100>; + reg-shift = <2>; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart4: serial@10034000 { + compatible = "ingenic,jz4740-uart"; + reg = <0x10034000 0x100>; + reg-shift = <2>; + clock-frequency = <48000000>; + status = "disabled"; + }; + }; +}; diff --git a/arch/mips/dts/ls1b.dtsi b/arch/mips/dts/ls1b.dtsi index f4ff8b6edd..af7119f1d0 100644 --- a/arch/mips/dts/ls1b.dtsi +++ b/arch/mips/dts/ls1b.dtsi @@ -8,33 +8,33 @@ device_type = "soc"; ranges; - serial0: serial@bfe40000 { + serial0: serial@1fe40000 { compatible = "ns16550a"; - reg = <0xbfe40000 0x8>; + reg = <0x1fe40000 0x8>; reg-shift = <0>; clock-frequency = <83000000>; status = "disabled"; }; - serial1: serial@bfe44000 { + serial1: serial@1fe44000 { compatible = "ns16550a"; - reg = <0xbfe44000 0x8>; + reg = <0x1fe44000 0x8>; reg-shift = <0>; clock-frequency = <83000000>; status = "disabled"; }; - serial2: serial@bfe48000 { + serial2: serial@1fe48000 { compatible = "ns16550a"; - reg = <0xbfe48000 0x8>; + reg = <0x1fe48000 0x8>; reg-shift = <0>; clock-frequency = <83000000>; status = "disabled"; }; - serial3: serial@bfe4c000 { + serial3: serial@1fe4c000 { compatible = "ns16550a"; - reg = <0xbfe4c000 0x8>; + reg = <0x1fe4c000 0x8>; reg-shift = <0>; clock-frequency = <83000000>; status = "disabled"; diff --git a/arch/mips/dts/qemu-malta.dts b/arch/mips/dts/qemu-malta.dts index cc1c9609ef..9b0c594e87 100644 --- a/arch/mips/dts/qemu-malta.dts +++ b/arch/mips/dts/qemu-malta.dts @@ -17,9 +17,9 @@ reg = <0x00000000 0x10000000>; }; - uart0: serial@b80003f8 { + uart0: serial@180003f8 { compatible = "ns16550a"; - reg = <0xb80003f8 0x08>; + reg = <0x180003f8 0x08>; reg-shift = <0>; /* no matter for emulated port */ clock-frequency = <1843200>; @@ -28,7 +28,7 @@ gpio: gpio@1f000b00 { compatible = "mti,malta-fpga-i2c-gpio"; gpio-controller; - reg = <0xbf000b00 0x20>; + reg = <0x1f000b00 0x20>; #gpio-cells = <2>; }; @@ -44,19 +44,19 @@ status = "disabled"; }; - uart2: serial@bf000900 { + uart2: serial@1f000900 { compatible = "ns16550a"; - reg = <0xbf000900 0x40>; + reg = <0x1f000900 0x40>; reg-shift = <3>; /* no matter for emulated port */ clock-frequency = <1843200>; }; - nor0: flash@be000000 { + nor0: flash@1e000000 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; - reg = <0xbe000000 0x00400000>; + reg = <0x1e000000 0x00400000>; partition@0 { label = "barebox"; diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index dcc2a27a97..572cabba34 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -27,6 +27,7 @@ #define PRID_COMP_MIPS 0x010000 #define PRID_COMP_BROADCOM 0x020000 #define PRID_COMP_INGENIC 0xd00000 +#define PRID_COMP_INGENIC2 0xe10000 /* * Assigned Processor ID (implementation) values for bits 15:8 of the PRId diff --git a/arch/mips/lib/cpu-probe.c b/arch/mips/lib/cpu-probe.c index 8235a54ae7..4622bcdd61 100644 --- a/arch/mips/lib/cpu-probe.c +++ b/arch/mips/lib/cpu-probe.c @@ -158,6 +158,7 @@ void cpu_probe(void) cpu_probe_broadcom(c); break; case PRID_COMP_INGENIC: + case PRID_COMP_INGENIC2: cpu_probe_ingenic(c); break; } diff --git a/arch/mips/mach-xburst/Kconfig b/arch/mips/mach-xburst/Kconfig index f7b8470cb8..2598c41cdf 100644 --- a/arch/mips/mach-xburst/Kconfig +++ b/arch/mips/mach-xburst/Kconfig @@ -6,6 +6,13 @@ config ARCH_TEXT_BASE config CPU_JZ4755 bool + select SYS_HAS_CPU_MIPS32_R1 + select WATCHDOG + select WATCHDOG_JZ4740 + +config CPU_JZ4780 + bool + select SYS_HAS_CPU_MIPS32_R2 select WATCHDOG select WATCHDOG_JZ4740 @@ -17,24 +24,37 @@ config BOARD_RZX50 select HAS_POWEROFF select CPU_JZ4755 +config BOARD_CI20 + bool "Imagination Creator CI20" + select CPU_JZ4780 + endchoice if DEBUG_LL -if CPU_JZ4755 choice prompt "DEBUG_LL port" -config JZ4750D_DEBUG_LL_UART0 +config JZ47XX_DEBUG_LL_UART0 + depends on CPU_JZ4755 || CPU_JZ4780 bool "UART0" -config JZ4750D_DEBUG_LL_UART1 +config JZ47XX_DEBUG_LL_UART1 + depends on CPU_JZ4755 || CPU_JZ4780 bool "UART1" -config JZ4750D_DEBUG_LL_UART2 +config JZ47XX_DEBUG_LL_UART2 + depends on CPU_JZ4755 || CPU_JZ4780 bool "UART2" +config JZ47XX_DEBUG_LL_UART3 + depends on CPU_JZ4780 + bool "UART3" + +config JZ47XX_DEBUG_LL_UART4 + depends on CPU_JZ4780 + bool "UART4" + endchoice -endif # CPU_JZ4755 endif # DEBUG_LL -endif +endif # MACH_MIPS_XBURST diff --git a/arch/mips/mach-xburst/include/mach/debug_ll_jz4750d.h b/arch/mips/mach-xburst/include/mach/debug_ll_jz4750d.h index 2a55dea437..6d18366c5b 100644 --- a/arch/mips/mach-xburst/include/mach/debug_ll_jz4750d.h +++ b/arch/mips/mach-xburst/include/mach/debug_ll_jz4750d.h @@ -20,15 +20,15 @@ #include <mach/jz4750d_regs.h> -#ifdef CONFIG_JZ4750D_DEBUG_LL_UART0 +#ifdef CONFIG_JZ47XX_DEBUG_LL_UART0 #define DEBUG_LL_UART_ADDR UART0_BASE #endif -#ifdef CONFIG_JZ4750D_DEBUG_LL_UART1 +#ifdef CONFIG_JZ47XX_DEBUG_LL_UART1 #define DEBUG_LL_UART_ADDR UART1_BASE #endif -#ifdef CONFIG_JZ4750D_DEBUG_LL_UART2 +#ifdef CONFIG_JZ47XX_DEBUG_LL_UART2 #define DEBUG_LL_UART_ADDR UART2_BASE #endif diff --git a/arch/mips/mach-xburst/include/mach/debug_ll_jz4780.h b/arch/mips/mach-xburst/include/mach/debug_ll_jz4780.h new file mode 100644 index 0000000000..0bdc58caa2 --- /dev/null +++ b/arch/mips/mach-xburst/include/mach/debug_ll_jz4780.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __INCLUDE_DEBUG_LL_JZ4780_H__ +#define __INCLUDE_DEBUG_LL_JZ4780_H__ + +#include <mach/jz4780.h> + +#ifdef CONFIG_JZ47XX_DEBUG_LL_UART0 +#define DEBUG_LL_UART_ADDR JZ4780_UART0_BASE +#endif + +#ifdef CONFIG_JZ47XX_DEBUG_LL_UART1 +#define DEBUG_LL_UART_ADDR JZ4780_UART1_BASE +#endif + +#ifdef CONFIG_JZ47XX_DEBUG_LL_UART2 +#define DEBUG_LL_UART_ADDR JZ4780_UART2_BASE +#endif + +#ifdef CONFIG_JZ47XX_DEBUG_LL_UART3 +#define DEBUG_LL_UART_ADDR JZ4780_UART3_BASE +#endif + +#ifdef CONFIG_JZ47XX_DEBUG_LL_UART4 +#define DEBUG_LL_UART_ADDR JZ4780_UART4_BASE +#endif + +#define DEBUG_LL_UART_SHIFT 2 + +#ifndef DEBUG_LL_UART_CLK +#define DEBUG_LL_UART_CLK (48000000 / 16) +#endif +#define DEBUG_LL_UART_BPS CONFIG_BAUDRATE +#define DEBUG_LL_UART_DIVISOR (DEBUG_LL_UART_CLK / DEBUG_LL_UART_BPS) + +#endif /* __INCLUDE_DEBUG_LL_JZ4780_H__ */ diff --git a/arch/mips/mach-xburst/include/mach/jz4780.h b/arch/mips/mach-xburst/include/mach/jz4780.h new file mode 100644 index 0000000000..4503a93ec1 --- /dev/null +++ b/arch/mips/mach-xburst/include/mach/jz4780.h @@ -0,0 +1,30 @@ +/* + * JZ4780 SoC definitions + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MIPS_ASM_MACH_JZ4780_JZ4780_H__ +#define __MIPS_ASM_MACH_JZ4780_JZ4780_H__ + +/* APB bus devices */ +#define JZ4780_UART0_BASE 0xb0030000 +#define JZ4780_UART1_BASE 0xb0031000 +#define JZ4780_UART2_BASE 0xb0032000 +#define JZ4780_UART3_BASE 0xb0033000 +#define JZ4780_UART4_BASE 0xb0034000 +#define JZ4780_UARTn_BASE(n) (JZ4780_UART0_BASE + (n * 0x1000)) + +#endif /* __MIPS_ASM_MACH_JZ4780_JZ4780_H__ */ diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index 23c6a71f3a..483ae6db4a 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -1,5 +1,6 @@ config OPENRISC bool + select OFTREE select HAS_CACHE select HAVE_CONFIGURABLE_MEMORY_LAYOUT select HAVE_DEFAULT_ENVIRONMENT_NEW @@ -11,6 +12,14 @@ config ARCH_TEXT_BASE hex default 0x00000000 +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + choice prompt "Select your board" diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile index fd8bbbf4d7..b0c8566e4e 100644 --- a/arch/openrisc/Makefile +++ b/arch/openrisc/Makefile @@ -19,3 +19,10 @@ common-y += arch/openrisc/lib/ common-y += arch/openrisc/cpu/ lds-y += arch/openrisc/cpu/barebox.lds + +common-$(CONFIG_BUILTIN_DTB) += arch/openrisc/dts/ + +dts := arch/openrisc/dts + +%.dtb: scripts + $(Q)$(MAKE) $(build)=$(dts) $(dts)/$@ diff --git a/arch/openrisc/boards/generic/config.h b/arch/openrisc/boards/generic/config.h index 6ebab42692..f6a054beed 100644 --- a/arch/openrisc/boards/generic/config.h +++ b/arch/openrisc/boards/generic/config.h @@ -8,13 +8,8 @@ #define OPENRISC_SOPC_MEMORY_BASE 0x00000000 #define OPENRISC_SOPC_MEMORY_SIZE 0x02000000 -#define OPENRISC_SOPC_UART_FREQ CONFIG_SYS_CLK_FREQ -#define OPENRISC_SOPC_UART_BASE 0x90000000 - -#define OPENRISC_SOPC_ETHOC_BASE 0x92000000 - -/* We reserve 256K for barebox */ -#define BAREBOX_RESERVED_SIZE 0x40000 +/* We reserve 512K for barebox */ +#define BAREBOX_RESERVED_SIZE 0x80000 /* Barebox will be at top of main memory */ #define OPENRISC_SOPC_TEXT_BASE (OPENRISC_SOPC_MEMORY_BASE + OPENRISC_SOPC_MEMORY_SIZE - BAREBOX_RESERVED_SIZE) diff --git a/arch/openrisc/boards/generic/generic.c b/arch/openrisc/boards/generic/generic.c index 9f680073cb..ff6f9f4d42 100644 --- a/arch/openrisc/boards/generic/generic.c +++ b/arch/openrisc/boards/generic/generic.c @@ -1,30 +1,10 @@ #include <common.h> #include <init.h> -#include <driver.h> -#include <partition.h> -#include <ns16550.h> -static struct NS16550_plat serial_plat = { - .clock = OPENRISC_SOPC_UART_FREQ, - .shift = 0, -}; - -static int openrisc_console_init(void) +static int openrisc_core_init(void) { - barebox_set_model("OpenRISC or1k"); barebox_set_hostname("or1k"); - /* Register the serial port */ - add_ns16550_device(DEVICE_ID_DYNAMIC, OPENRISC_SOPC_UART_BASE, 1024, - IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat); - -#ifdef CONFIG_DRIVER_NET_ETHOC - add_generic_device("ethoc", DEVICE_ID_DYNAMIC, NULL, - OPENRISC_SOPC_ETHOC_BASE, 0x1000, - IORESOURCE_MEM, NULL); -#endif - return 0; } - -console_initcall(openrisc_console_init); +core_initcall(openrisc_core_init); diff --git a/arch/openrisc/configs/generic_defconfig b/arch/openrisc/configs/generic_defconfig index deaef2a3aa..1f2d40eae9 100644 --- a/arch/openrisc/configs/generic_defconfig +++ b/arch/openrisc/configs/generic_defconfig @@ -1,26 +1,35 @@ -CONFIG_LONGHELP=y +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="or1ksim" CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_TIME=y -CONFIG_CMD_ECHO_E=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y CONFIG_CMD_MEMINFO=y -CONFIG_CMD_FLASH=y # CONFIG_CMD_BOOTM is not set -CONFIG_CMD_RESET=y CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_RESET=y CONFIG_CMD_PARTITION=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_NET=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_NET_ETHOC=y +CONFIG_FS_TFTP=y diff --git a/arch/openrisc/cpu/barebox.lds.S b/arch/openrisc/cpu/barebox.lds.S index add9181e13..dbecdbfbfc 100644 --- a/arch/openrisc/cpu/barebox.lds.S +++ b/arch/openrisc/cpu/barebox.lds.S @@ -69,6 +69,8 @@ SECTIONS __usymtab : { BAREBOX_SYMS } > ram ___usymtab_end = .; + .dtb : { BAREBOX_DTB() } > ram + __etext = .; /* End of text and rodata section */ . = ALIGN(4); diff --git a/arch/openrisc/dts/Makefile b/arch/openrisc/dts/Makefile new file mode 100644 index 0000000000..6d6c9a3ce0 --- /dev/null +++ b/arch/openrisc/dts/Makefile @@ -0,0 +1,5 @@ + +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +clean-files := *.dtb *.dtb.S diff --git a/arch/openrisc/dts/or1ksim.dts b/arch/openrisc/dts/or1ksim.dts new file mode 100644 index 0000000000..7316cc6770 --- /dev/null +++ b/arch/openrisc/dts/or1ksim.dts @@ -0,0 +1,51 @@ +/dts-v1/; +/ { + model = "or1ksim"; + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=uart,mmio,0x90000000,115200"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible = "opencores,or1k-pic"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible = "ns16550a"; + reg = <0x90000000 0x100>; + interrupts = <2>; + clock-frequency = <50000000>; + }; + + enet0: ethoc@92000000 { + compatible = "opencores,ethoc"; + reg = <0x92000000 0x100>; + interrupts = <4>; + }; +}; diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile index 0b3cc5068c..62082feed0 100644 --- a/arch/openrisc/lib/Makefile +++ b/arch/openrisc/lib/Makefile @@ -5,3 +5,4 @@ obj-y += muldi3.o obj-y += lshrdi3.o obj-y += ashldi3.o obj-y += ashrdi3.o +obj-$(CONFIG_BUILTIN_DTB) += dtb.o diff --git a/arch/openrisc/lib/dtb.c b/arch/openrisc/lib/dtb.c new file mode 100644 index 0000000000..4f63a7760f --- /dev/null +++ b/arch/openrisc/lib/dtb.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> + * + * Based on arch/arm/cpu/dtb.c: + * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <init.h> +#include <of.h> + +extern char __dtb_start[]; + +static int of_openrisc_init(void) +{ + struct device_node *root; + + root = of_get_root_node(); + if (root) + return 0; + + root = of_unflatten_dtb(__dtb_start); + if (root) { + pr_debug("using internal DTB\n"); + of_set_root_node(root); + if (IS_ENABLED(CONFIG_OFDEVICE)) + of_probe(); + } + + return 0; +} +core_initcall(of_openrisc_init); diff --git a/arch/ppc/mach-mpc85xx/.gitignore b/arch/ppc/mach-mpc85xx/.gitignore new file mode 100644 index 0000000000..d1165788c9 --- /dev/null +++ b/arch/ppc/mach-mpc85xx/.gitignore @@ -0,0 +1 @@ +barebox.lds |