diff options
Diffstat (limited to 'arch')
107 files changed, 2972 insertions, 428 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 09bbe05bad..f682803bf1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -120,6 +120,7 @@ config ARCH_MVEBU config ARCH_MXS bool "Freescale i.MX23/28 (mxs) based" + select GPIOLIB select GENERIC_GPIO select COMMON_CLK select CLKDEV_LOOKUP diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 193f731e90..f0133d4165 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -13,8 +13,6 @@ AS += -EL LD += -EL endif -comma = , - # This selects which instruction set is used. # Note that GCC does not numerically define an architecture version # macro, but instead defines a whole series of macros which makes diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 9961ca8f11..a85de760f7 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_MACH_CFA10036) += crystalfontz-cfa10036/ obj-$(CONFIG_MACH_CHUMBY) += chumby_falconwing/ obj-$(CONFIG_MACH_CLEP7212) += clep7212/ obj-$(CONFIG_MACH_DFI_FS700_M60) += dfi-fs700-m60/ +obj-$(CONFIG_MACH_DUCKBILL) += duckbill/ obj-$(CONFIG_MACH_DSS11) += dss11/ obj-$(CONFIG_MACH_EDB93012) += edb93xx/ obj-$(CONFIG_MACH_EDB9301) += edb93xx/ @@ -50,10 +51,12 @@ obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/ obj-$(CONFIG_MACH_GUF_SANTARO) += guf-santaro/ obj-$(CONFIG_MACH_GUF_VINCELL) += guf-vincell/ obj-$(CONFIG_MACH_GW_VENTANA) += gateworks-ventana/ +obj-$(CONFIG_MACH_HABA_KNX_LITE) += haba-knx/ obj-$(CONFIG_MACH_HIGHBANK) += highbank/ obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/ obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/ obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/ +obj-$(CONFIG_MACH_LUBBOCK) += lubbock/ obj-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += marvell-armada-xp-gp/ obj-$(CONFIG_MACH_MB7707) += module-mb7707/ obj-$(CONFIG_MACH_MIOA701) += mioa701/ @@ -124,4 +127,5 @@ obj-$(CONFIG_MACH_VERSATILEPB) += versatile/ obj-$(CONFIG_MACH_VEXPRESS) += vexpress/ obj-$(CONFIG_MACH_VIRT2REAL) += virt2real/ obj-$(CONFIG_MACH_ZEDBOARD) += avnet-zedboard/ +obj-$(CONFIG_MACH_ZYLONITE) += zylonite/ obj-$(CONFIG_MACH_VARISCITE_MX6) += variscite-mx6/ diff --git a/arch/arm/boards/a9m2410/env/config b/arch/arm/boards/a9m2410/env/config index 79150ce017..2b09318934 100644 --- a/arch/arm/boards/a9m2410/env/config +++ b/arch/arm/boards/a9m2410/env/config @@ -23,4 +23,4 @@ eth0.ipaddr=192.168.42.31 eth0.netmask=255.255.0.0 eth0.gateway=192.168.23.1 eth0.serverip=192.168.23.2 -eth0.ethaddr=00:04:f3:00:06:35 +#eth0.ethaddr= diff --git a/arch/arm/boards/a9m2440/env/config b/arch/arm/boards/a9m2440/env/config index 936c35f9a9..d1fb01b731 100644 --- a/arch/arm/boards/a9m2440/env/config +++ b/arch/arm/boards/a9m2440/env/config @@ -23,4 +23,4 @@ eth0.ipaddr=192.168.42.32 eth0.netmask=255.255.0.0 eth0.gateway=192.168.23.1 eth0.serverip=192.168.23.2 -eth0.ethaddr=00:04:f3:00:06:35 +#eth0.ethaddr= diff --git a/arch/arm/boards/at91sam9n12ek/env/bin/init_board b/arch/arm/boards/at91sam9n12ek/env/bin/init_board index 6b44044f17..4931342a0b 100644 --- a/arch/arm/boards/at91sam9n12ek/env/bin/init_board +++ b/arch/arm/boards/at91sam9n12ek/env/bin/init_board @@ -12,7 +12,7 @@ button_wait=5 dfu_config="/dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.rootfs.bb(rootfs)r" -if [ $at91_udc0.vbus != 1 ] +if [ $at91_udc.vbus != 1 ] then echo "No USB Device cable plugged, normal boot" exit @@ -30,7 +30,7 @@ fi echo "${button_name} pressed detected wait ${button_wait}s" timeout -s -a ${button_wait} -if [ $at91_udc0.vbus != 1 ] +if [ $at91_udc.vbus != 1 ] then echo "No USB Device cable plugged, normal boot" exit diff --git a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c index 1412eff4a7..6e83570c55 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c +++ b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c @@ -127,9 +127,6 @@ static int cfa10036_devices_init(void) add_generic_device("mxs_mci", 0, NULL, IMX_SSP0_BASE, SZ_8K, IORESOURCE_MEM, &mci_pdata); - add_generic_device("ocotp", 0, NULL, IMX_OCOTP_BASE, SZ_8K, - IORESOURCE_MEM, NULL); - i2c_register_board_info(0, cfa10036_i2c_devices, ARRAY_SIZE(cfa10036_i2c_devices)); add_generic_device_res("i2c-gpio", 0, NULL, 0, &i2c_gpio_pdata); diff --git a/arch/arm/boards/duckbill/Makefile b/arch/arm/boards/duckbill/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/duckbill/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/duckbill/board.c b/arch/arm/boards/duckbill/board.c new file mode 100644 index 0000000000..3c6ab8e596 --- /dev/null +++ b/arch/arm/boards/duckbill/board.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de> + * Copyright (C) 2011 Marc Kleine-Budde, Pengutronix <mkl@pengutronix.de> + * Copyright (C) 2011 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <environment.h> +#include <errno.h> +#include <gpio.h> +#include <init.h> +#include <io.h> +#include <net.h> + +#include <mach/clock.h> +#include <mach/imx-regs.h> +#include <mach/iomux-imx28.h> +#include <mach/iomux.h> +#include <mach/ocotp.h> +#include <mach/devices.h> +#include <mach/usb.h> +#include <usb/fsl_usb2.h> + +#include <asm/armlinux.h> +#include <asm/mmu.h> + +static void duckbill_get_ethaddr(void) +{ + u8 mac_ocotp[3], mac[6]; + int ret; + + ret = mxs_ocotp_read(mac_ocotp, 3, 0); + if (ret != 3) { + pr_err("Reading MAC from OCOTP failed!\n"); + return; + } + + mac[0] = 0x00; + mac[1] = 0x04; + mac[2] = 0x9f; + mac[3] = mac_ocotp[2]; + mac[4] = mac_ocotp[1]; + mac[5] = mac_ocotp[0]; + + eth_register_ethaddr(0, mac); +} + +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, +}; + +static int duckbill_devices_init(void) +{ + duckbill_get_ethaddr(); /* must be after registering ocotp */ + + imx28_usb_phy0_enable(); + add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_USB0_BASE, + 0x200, IORESOURCE_MEM, &usb_pdata); + + return 0; +} +fs_initcall(duckbill_devices_init); + +static int duckbill_console_init(void) +{ + barebox_set_model("I2SE Duckbill"); + barebox_set_hostname("duckbill"); + + return 0; +} +console_initcall(duckbill_console_init); diff --git a/arch/arm/boards/duckbill/lowlevel.c b/arch/arm/boards/duckbill/lowlevel.c new file mode 100644 index 0000000000..77d2e83aed --- /dev/null +++ b/arch/arm/boards/duckbill/lowlevel.c @@ -0,0 +1,73 @@ +#define pr_fmt(fmt) "Freescale MX28evk: " fmt +#define DEBUG + +#include <common.h> +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx28-regs.h> +#include <mach/init.h> +#include <io.h> +#include <debug_ll.h> +#include <mach/iomux.h> +#include <stmp-device.h> + +extern char __dtb_imx28_duckbill_start[]; + +ENTRY_FUNCTION(start_barebox_duckbill, r0, r1, r2) +{ + void *fdt; + + pr_debug("here we are!\n"); + + fdt = __dtb_imx28_duckbill_start - get_runtime_offset(); + + barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, fdt); +} + +static const uint32_t iomux_pads[] = { + /* EMI */ + EMI_DATA0, EMI_DATA1, EMI_DATA2, EMI_DATA3, EMI_DATA4, EMI_DATA5, + EMI_DATA6, EMI_DATA7, EMI_DATA8, EMI_DATA9, EMI_DATA10, EMI_DATA11, + EMI_DATA12, EMI_DATA13, EMI_DATA14, EMI_DATA15, EMI_ODT0, EMI_DQM0, + EMI_ODT1, EMI_DQM1, EMI_DDR_OPEN_FB, EMI_CLK, EMI_DSQ0, EMI_DSQ1, + EMI_DDR_OPEN, EMI_A0, EMI_A1, EMI_A2, EMI_A3, EMI_A4, EMI_A5, + EMI_A6, EMI_A7, EMI_A8, EMI_A9, EMI_A10, EMI_A11, EMI_A12, EMI_A13, + EMI_A14, EMI_BA0, EMI_BA1, EMI_BA2, EMI_CASN, EMI_RASN, EMI_WEN, + EMI_CE0N, EMI_CE1N, EMI_CKE, + + /* Debug UART */ + PWM0_DUART_RX | VE_3_3V, + PWM1_DUART_TX | VE_3_3V, +}; + +static noinline void duckbill_init(void) +{ + int i; + + /* initialize muxing */ + for (i = 0; i < ARRAY_SIZE(iomux_pads); i++) + imx_gpio_mode(iomux_pads[i]); + + pr_debug("initializing power...\n"); + + mx28_power_init(0, 0, 1); + + pr_debug("initializing SDRAM...\n"); + + mx28_mem_init(); + + pr_debug("DONE\n"); +} + +ENTRY_FUNCTION(prep_start_barebox_duckbill, r0, r1, r2) +{ + void (*back)(unsigned long) = (void *)get_lr(); + + relocate_to_current_adr(); + setup_c(); + + duckbill_init(); + + back(0); +} diff --git a/arch/arm/boards/edb93xx/env/config b/arch/arm/boards/edb93xx/env/config index 47ab209d82..3266272742 100644 --- a/arch/arm/boards/edb93xx/env/config +++ b/arch/arm/boards/edb93xx/env/config @@ -3,7 +3,7 @@ eth0.ipaddr=192.168.0.50 eth0.netmask=255.255.0.0 eth0.serverip=192.168.0.8 -eth0.ethaddr=80:81:82:83:84:85 +#eth0.ethaddr= board=edb9301 autoboot_timeout=3 diff --git a/arch/arm/boards/embedsky-e9/board.c b/arch/arm/boards/embedsky-e9/board.c index 1e7e06788a..e8aac0c1b0 100644 --- a/arch/arm/boards/embedsky-e9/board.c +++ b/arch/arm/boards/embedsky-e9/board.c @@ -40,6 +40,7 @@ #include <mach/spi.h> #include <mach/usb.h> #include <envfs.h> +#include <bootsource.h> #define PHY_ID_RTL8211E 0x001cc915 #define PHY_ID_MASK 0xffffffff @@ -59,11 +60,25 @@ static int rtl8211e_phy_fixup(struct phy_device *dev) static int e9_devices_init(void) { + int ret; + char *environment_path; + if (!of_machine_is_compatible("embedsky,e9")) return 0; armlinux_set_architecture(3980); - barebox_set_hostname("e9"); + + environment_path = asprintf("/chosen/environment-mmc%d", + bootsource_get_instance()); + + ret = of_device_enable_path(environment_path); + + if (ret < 0) + pr_warn("Failed to enable environment partition '%s' (%d)\n", + environment_path, ret); + + free(environment_path); + defaultenv_append_directory(defaultenv_e9); return 0; diff --git a/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc3 b/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc3 index 374eb1cfe6..f6cb529d3c 100644 --- a/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc3 +++ b/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc3 @@ -2,5 +2,5 @@ mount /dev/mmc3.0 -global.bootm.image=/mnt/mmc3.0/boot/zImage -global.linux.bootargs.dyn.root="root=/dev/mmcblk1p1 rootwait" +global.bootm.image=/mnt/mmc3.0/zImage +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait" diff --git a/arch/arm/boards/freescale-mx25-3ds/env/config b/arch/arm/boards/freescale-mx25-3ds/env/config index a5e492e339..8469935b20 100644 --- a/arch/arm/boards/freescale-mx25-3ds/env/config +++ b/arch/arm/boards/freescale-mx25-3ds/env/config @@ -26,4 +26,4 @@ eth0.ipaddr=192.168.3.11 eth0.netmask=255.255.255.0 #eth0.gateway=a.b.c.d eth0.serverip=192.168.3.10 -eth0.ethaddr=00:50:c2:8c:e6:0e +#eth0.ethaddr= diff --git a/arch/arm/boards/freescale-mx28-evk/env/config b/arch/arm/boards/freescale-mx28-evk/env/config deleted file mode 100644 index adbe7f4973..0000000000 --- a/arch/arm/boards/freescale-mx28-evk/env/config +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh - -#user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.serverip=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.ethaddr=de:ad:be:ef:00:00 - -# can be either 'tftp', 'nfs', 'nand', 'nor' or 'disk' -kernel_loc=tftp -# can be either 'net', 'nand', 'nor', 'disk' or 'initrd' -rootfs_loc=net - -# for flash based rootfs: 'jffs2' or 'ubifs' -# in case of disk any regular filesystem like 'ext2', 'ext3', 'reiserfs' -rootfs_type=ext2 -# where is the rootfs in case of 'rootfs_loc=disk' (linux name) -rootfs_part_linux_dev=mmcblk0p4 -rootfsimage=rootfs-${global.hostname}.$rootfs_type - -# where is the kernel image in case of 'kernel_loc=disk' -kernel_part=disk0.2 - -kernelimage=zImage-${global.hostname} -bareboximage=barebox-${global.hostname}.bin -bareboxenvimage=barebox-${global.hostname}.bin - -if [ -n $user ]; then - bareboximage="$user"-"$bareboximage" - bareboxenvimage="$user"-"$bareboxenvimage" - kernelimage="$user"-"$kernelimage" - rootfsimage="$user"-"$rootfsimage" - nfsroot="/home/$user/nfsroot/${global.hostname}" -else - nfsroot="/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttyAMA0,115200" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/freescale-mx28-evk/lowlevel.c b/arch/arm/boards/freescale-mx28-evk/lowlevel.c index 3c7248ef65..1f567568da 100644 --- a/arch/arm/boards/freescale-mx28-evk/lowlevel.c +++ b/arch/arm/boards/freescale-mx28-evk/lowlevel.c @@ -1,11 +1,65 @@ +#define pr_fmt(fmt) "Freescale MX28evk: " fmt +#define DEBUG + #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <mach/imx28-regs.h> +#include <mach/init.h> +#include <io.h> +#include <debug_ll.h> +#include <mach/iomux.h> +#include <stmp-device.h> -void __naked barebox_arm_reset_vector(void) +ENTRY_FUNCTION(start_barebox_freescale_mx28evk, r0, r1, r2) { - arm_cpu_lowlevel_init(); barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, NULL); } + +static const uint32_t iomux_pads[] = { + /* EMI */ + EMI_DATA0, EMI_DATA1, EMI_DATA2, EMI_DATA3, EMI_DATA4, EMI_DATA5, + EMI_DATA6, EMI_DATA7, EMI_DATA8, EMI_DATA9, EMI_DATA10, EMI_DATA11, + EMI_DATA12, EMI_DATA13, EMI_DATA14, EMI_DATA15, EMI_ODT0, EMI_DQM0, + EMI_ODT1, EMI_DQM1, EMI_DDR_OPEN_FB, EMI_CLK, EMI_DSQ0, EMI_DSQ1, + EMI_DDR_OPEN, EMI_A0, EMI_A1, EMI_A2, EMI_A3, EMI_A4, EMI_A5, + EMI_A6, EMI_A7, EMI_A8, EMI_A9, EMI_A10, EMI_A11, EMI_A12, EMI_A13, + EMI_A14, EMI_BA0, EMI_BA1, EMI_BA2, EMI_CASN, EMI_RASN, EMI_WEN, + EMI_CE0N, EMI_CE1N, EMI_CKE, + + /* Debug UART */ + PWM0_DUART_RX | VE_3_3V, + PWM1_DUART_TX | VE_3_3V, +}; + +static noinline void freescale_mx28evk_init(void) +{ + int i; + + /* initialize muxing */ + for (i = 0; i < ARRAY_SIZE(iomux_pads); i++) + imx_gpio_mode(iomux_pads[i]); + + pr_debug("initializing power...\n"); + + mx28_power_init(0, 1, 0); + + pr_debug("initializing SDRAM...\n"); + + mx28_mem_init(); + + pr_debug("DONE\n"); +} + +ENTRY_FUNCTION(prep_start_barebox_freescale_mx28evk, r0, r1, r2) +{ + void (*back)(unsigned long) = (void *)get_lr(); + + relocate_to_current_adr(); + setup_c(); + + freescale_mx28evk_init(); + + back(0); +} diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c index dce6d31030..d77a6c7156 100644 --- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c +++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c @@ -275,8 +275,6 @@ static int mx28_evk_devices_init(void) add_generic_device("stmfb", 0, NULL, IMX_FB_BASE, 0x2000, IORESOURCE_MEM, &mx28_evk_fb_pdata); - add_generic_device("ocotp", 0, NULL, IMX_OCOTP_BASE, 0x2000, - IORESOURCE_MEM, NULL); mx28_evk_get_ethaddr(); /* must be after registering ocotp */ mx28_evk_fec_reset(); diff --git a/arch/arm/boards/friendlyarm-mini6410/env/config b/arch/arm/boards/friendlyarm-mini6410/env/config index a1c86e1fba..74beeff4fa 100644 --- a/arch/arm/boards/friendlyarm-mini6410/env/config +++ b/arch/arm/boards/friendlyarm-mini6410/env/config @@ -12,7 +12,7 @@ ip=dhcp #eth0.ipaddr=a.b.c.d.e #eth0.netmask=a.b.c.d.e #eth0.gateway=a.b.c.d.e -eth0.ethaddr=08:90:90:90:90:90 +#eth0.ethaddr= # can be either 'nfs', 'tftp' or 'nand' kernel_loc=tftp diff --git a/arch/arm/boards/friendlyarm-tiny6410/env/config b/arch/arm/boards/friendlyarm-tiny6410/env/config index 35d0fac334..6422e9f6a6 100644 --- a/arch/arm/boards/friendlyarm-tiny6410/env/config +++ b/arch/arm/boards/friendlyarm-tiny6410/env/config @@ -12,7 +12,7 @@ ip=dhcp #eth0.ipaddr=a.b.c.d.e #eth0.netmask=a.b.c.d.e #eth0.gateway=a.b.c.d.e -eth0.ethaddr=08:90:90:90:90:90 +#eth0.ethaddr= # can be either 'nfs', 'tftp' or 'nand' kernel_loc=tftp diff --git a/arch/arm/boards/haba-knx/Makefile b/arch/arm/boards/haba-knx/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/haba-knx/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/haba-knx/env/bin/init_board b/arch/arm/boards/haba-knx/env/bin/init_board new file mode 100644 index 0000000000..0a6baf722b --- /dev/null +++ b/arch/arm/boards/haba-knx/env/bin/init_board @@ -0,0 +1,49 @@ +#!/bin/sh + +button_name="dfu_bp" +button_wait=5 + +product_id=0x1234 +vendor_id=0x4321 + +dfu_config="/dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.rootfs.bb(rootfs)r" + +if [ $at91_udc0.vbus != 1 ] +then + echo "No USB Device cable plugged, normal boot" + exit +fi + +gpio_get_value ${dfu_button} +if [ $? != 0 ] +then + autoboot_timeout=16 + echo "enable tty over USB Device, increase the boot delay to ${autoboot_timeout}s" + usbserial + exit +fi + +echo "${button_name} pressed detected wait ${button_wait}s" +timeout -s -a ${button_wait} + +if [ $at91_udc0.vbus != 1 ] +then + echo "No USB Device cable plugged, normal boot" + exit +fi + +gpio_get_value ${dfu_button} +if [ $? != 0 ] +then + echo "${button_name} released, normal boot" + autoboot_timeout=16 + echo "enable tty over USB Device, increase the boot delay to ${autoboot_timeout}s" + usbserial + exit +fi + +echo "" +echo "Start DFU Mode" +echo "" + +dfu ${dfu_config} -P ${product_id} -V ${vendor_id} diff --git a/arch/arm/boards/haba-knx/env/config b/arch/arm/boards/haba-knx/env/config new file mode 100644 index 0000000000..d1dca105ad --- /dev/null +++ b/arch/arm/boards/haba-knx/env/config @@ -0,0 +1,40 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=none +#ip=dhcp-barebox +[ x$armlinux_architecture = x4310 ] && dhcp_vendor_id=barebox-haba-knx-lite + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=nand +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=nand +# can be either 'nfs', 'tftp', 'nor', 'nand' or empty +oftree_loc=nand + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type + +kernelimage=zImage +#kernelimage=uImage +#kernelimage=Image +#kernelimage=Image.lzo + +nand_device=atmel_nand +nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)" +rootfs_mtdblock_nand=6 + +autoboot_timeout=3 + +bootargs="console=ttyS0,115200" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# " diff --git a/arch/arm/boards/haba-knx/init.c b/arch/arm/boards/haba-knx/init.c new file mode 100644 index 0000000000..f9d8f0f903 --- /dev/null +++ b/arch/arm/boards/haba-knx/init.c @@ -0,0 +1,348 @@ +/* + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD + * Copyright (C) 2014 Gregory Hermant <gregory.hermant@calao-systems.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <io.h> +#include <mach/hardware.h> +#include <nand.h> +#include <linux/sizes.h> +#include <linux/mtd/nand.h> +#include <linux/clk.h> +#include <mach/board.h> +#include <mach/at91sam9_smc.h> +#include <gpio.h> +#include <led.h> +#include <mach/io.h> +#include <mach/iomux.h> +#include <mach/at91_pmc.h> +#include <mach/at91_rstc.h> +#include <spi/spi.h> +#include <i2c/i2c.h> +#include <libfile.h> + +#if defined(CONFIG_NAND_ATMEL) +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, + .ecc_mode = NAND_ECC_SOFT, + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config haba_knx_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 3, +}; + +static void haba_knx_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(0, 3, &haba_knx_nand_smc_config); + at91_add_device_nand(&nand_pdata); +} +#else +static void haba_knx_add_device_nand(void) {} +#endif + +#if defined(CONFIG_DRIVER_NET_MACB) +static struct macb_platform_data macb_pdata = { + .phy_interface = PHY_INTERFACE_MODE_RMII, + .phy_addr = -1, +}; + +static void haba_knx_phy_reset(void) +{ + unsigned long rstc; + struct clk *clk = clk_get(NULL, "macb_clk"); + + clk_enable(clk); + + at91_set_gpio_input(AT91_PIN_PA14, 0); + at91_set_gpio_input(AT91_PIN_PA15, 0); + at91_set_gpio_input(AT91_PIN_PA17, 0); + at91_set_gpio_input(AT91_PIN_PA18, 0); + + rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0d << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)) + ; + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (rstc) | + AT91_RSTC_URSTEN); +} + +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c + +static int haba_ip_get_macb_ethaddr(u8 *addr) +{ + u32 top, bottom; + void __iomem *base = IOMEM(AT91SAM9260_BASE_EMAC); + + bottom = readl(base + MACB_SA1B); + top = readl(base + MACB_SA1T); + addr[0] = bottom & 0xff; + addr[1] = (bottom >> 8) & 0xff; + addr[2] = (bottom >> 16) & 0xff; + addr[3] = (bottom >> 24) & 0xff; + addr[4] = top & 0xff; + addr[5] = (top >> 8) & 0xff; + + /* valid and not private */ + if (is_valid_ether_addr(addr) && !(addr[0] & 0x02)) + return 0; + + return -EINVAL; +} + +#define EEPROM_OFFSET 250 +#define EEPROM_SIZE 256 + +static int haba_set_ethaddr(void) +{ + char addr[6]; + char eep_data[256]; + int i, fd, ret; + + fd = open("/dev/eeprom0", O_RDONLY); + if (fd < 0) { + ret = fd; + goto err; + } + + ret = read_full(fd, eep_data, EEPROM_SIZE); + if (ret < 0) + goto err_open; + + for (i = 0; i < 6; i++) + addr[i] = eep_data[EEPROM_OFFSET+i]; + + eth_register_ethaddr(0, addr); + + ret = 0; + +err_open: + close(fd); +err: + if (ret) + pr_err("can't read eeprom /dev/eeprom0 (%s)\n", strerror(ret)); + + return ret; +} + +static void haba_knx_add_device_eth(void) +{ + u8 enetaddr[6]; + + if (!haba_ip_get_macb_ethaddr(enetaddr)) + eth_register_ethaddr(0, enetaddr); + else + haba_set_ethaddr(); + + haba_knx_phy_reset(); + at91_add_device_eth(0, &macb_pdata); +} +#else +static void haba_knx_add_device_eth(void) {} +#endif + +/* + * USB Device port + */ +static struct at91_udc_data __initdata ek_udc_data = { + .vbus_pin = AT91_PIN_PB2, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("24c02", 0x50) + } +}; + +static const struct spi_board_info ek_spi_devices[] = { + { + .name = "m25p16", + .max_speed_hz = 30 * 1000 * 1000, + .bus_num = 0, + .chip_select = 0, + }, + { + .name = "spi_mci", + .max_speed_hz = 25 * 1000 * 1000, + .bus_num = 0, + .chip_select = 1, + } +}; + +static unsigned spi0_standard_cs[] = { AT91_PIN_PA3, AT91_PIN_PA27 }; +static struct at91_spi_platform_data spi_pdata = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +}; + +static void haba_knx_add_device_spi(void) +{ + if (machine_is_haba_knx_lite()) { + spi_register_board_info(ek_spi_devices, + ARRAY_SIZE(ek_spi_devices)); + at91_add_device_spi(0, &spi_pdata); + } +} + +static struct at91_usbh_data haba_knx_usbh_data = { + .ports = 2, + .vbus_pin = { -EINVAL, -EINVAL }, +}; + +static void haba_knx_add_device_usb(void) +{ + at91_add_device_usbh_ohci(&haba_knx_usbh_data); +} + +struct gpio_led led = { + .gpio = AT91_PIN_PA28, + .led = { + .name = "user_led", + }, +}; + +static void __init ek_add_led(void) +{ + if (!machine_is_haba_knx_lite()) + return; + at91_set_gpio_output(led.gpio, led.active_low); + led_gpio_register(&led); +} + +static int haba_knx_mem_init(void) +{ + at91_add_device_sdram(0); + return 0; +} +mem_initcall(haba_knx_mem_init); + +static void __init ek_add_device_button(void) +{ + at91_set_GPIO_periph(AT91_PIN_PC3, 1); /* user btn, pull up enabled */ + at91_set_deglitch(AT91_PIN_PC3, 1); + export_env_ull("dfu_button", AT91_PIN_PC3); +} + +static const struct devfs_partition haba_knx_nand0_partitions[] = { + { + .offset = 0x00000, + .size = SZ_128K, + .flags = DEVFS_PARTITION_FIXED, + .name = "at91bootstrap_raw", + .bbname = "at91bootstrap", + }, { + .offset = DEVFS_PARTITION_APPEND, + .size = SZ_256K, + .flags = DEVFS_PARTITION_FIXED, + .name = "self_raw", + .bbname = "self0", + }, { + .offset = DEVFS_PARTITION_APPEND, + .size = SZ_128K, + .flags = DEVFS_PARTITION_FIXED, + .name = "env_raw", + .bbname = "env0", + }, { + .offset = DEVFS_PARTITION_APPEND, + .size = SZ_128K, + .flags = DEVFS_PARTITION_FIXED, + .name = "env_raw1", + .bbname = "env1", + }, { + /* sentinel */ + } +}; + +static int haba_knx_devices_init(void) +{ + at91_add_device_i2c(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + haba_knx_add_device_nand(); + haba_knx_add_device_eth(); + haba_knx_add_device_spi(); + haba_knx_add_device_usb(); + at91_add_device_udc(&ek_udc_data); + ek_add_led(); + ek_add_device_button(); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + armlinux_set_architecture(MACH_TYPE_HABA_KNX_LITE); + + devfs_create_partitions("nand0", haba_knx_nand0_partitions); + + return 0; +} +device_initcall(haba_knx_devices_init); + +static int haba_knx_console_init(void) +{ + barebox_set_model("CALAO HABA-KNX-LITE"); + barebox_set_hostname("haba-knx-lite"); + + at91_register_uart(0, 0); + at91_set_A_periph(AT91_PIN_PB14, 1); /* Enable pull-up on DRXD */ + + at91_set_gpio_input(AT91_PIN_PB0, 1); /* Enable pull-up on usd CD */ + return 0; +} +console_initcall(haba_knx_console_init); + +static int haba_knx_main_clock(void) +{ + at91_set_main_clock(12000000); + return 0; +} +pure_initcall(haba_knx_main_clock); diff --git a/arch/arm/boards/imx233-olinuxino/lowlevel.c b/arch/arm/boards/imx233-olinuxino/lowlevel.c index 6e4b830485..ce46f7e143 100644 --- a/arch/arm/boards/imx233-olinuxino/lowlevel.c +++ b/arch/arm/boards/imx233-olinuxino/lowlevel.c @@ -154,7 +154,7 @@ static noinline void imx23_olinuxino_init(void) pr_debug("initializing power...\n"); - mx23_power_init(); + mx23_power_init(0, 1, 0); pr_debug("initializing SDRAM...\n"); diff --git a/arch/arm/boards/karo-tx28/lowlevel.c b/arch/arm/boards/karo-tx28/lowlevel.c index c5fdda1902..96a8b9bfc6 100644 --- a/arch/arm/boards/karo-tx28/lowlevel.c +++ b/arch/arm/boards/karo-tx28/lowlevel.c @@ -43,7 +43,7 @@ static noinline void karo_tx28_init(void) pr_debug("initializing power...\n"); - mx28_power_init_battery_input(); + mx28_power_init(0, 1, 0); pr_debug("initializing SDRAM...\n"); diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c index c4c51099b4..9b86d1c883 100644 --- a/arch/arm/boards/karo-tx28/tx28-stk5.c +++ b/arch/arm/boards/karo-tx28/tx28-stk5.c @@ -382,9 +382,6 @@ void base_board_init(void) add_generic_device("stmfb", 0, NULL, IMX_FB_BASE, 0x2000, IORESOURCE_MEM, &tx28_fb_pdata); - add_generic_device("ocotp", 0, NULL, IMX_OCOTP_BASE, 0x2000, - IORESOURCE_MEM, NULL); - tx28_get_ethaddr(); add_generic_device("imx28-fec", 0, NULL, IMX_FEC0_BASE, 0x4000, diff --git a/arch/arm/boards/lubbock/Makefile b/arch/arm/boards/lubbock/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/lubbock/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/lubbock/board.c b/arch/arm/boards/lubbock/board.c new file mode 100644 index 0000000000..6f517d8926 --- /dev/null +++ b/arch/arm/boards/lubbock/board.c @@ -0,0 +1,134 @@ +/* + * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <driver.h> +#include <environment.h> +#include <fs.h> +#include <init.h> +#include <partition.h> +#include <led.h> +#include <gpio.h> +#include <pwm.h> +#include <linux/sizes.h> + +#include <mach/devices.h> +#include <mach/mfp-pxa27x.h> +#include <mach/pxa-regs.h> +#include <mach/udc_pxa2xx.h> +#include <mach/mci_pxa2xx.h> + +#include <net/smc91111.h> +#include <asm/armlinux.h> +#include <asm/io.h> +#include <asm/mmu.h> + +#include <generated/mach-types.h> + +#define ECOR 0x8000 +#define ECOR_RESET 0x80 +#define ECOR_LEVEL_IRQ 0x40 +#define ECOR_WR_ATTRIB 0x04 +#define ECOR_ENABLE 0x01 + +#define ECSR 0x8002 +#define ECSR_IOIS8 0x20 +#define ECSR_PWRDWN 0x04 +#define ECSR_INT 0x02 + +static struct smc91c111_pdata smsc91x_pdata = { + .control_setup = 0x0800, + .config_setup = 0x10b2, + .bus_width = 16, + .addr_shift = 2, +}; + +static unsigned long lubbock_pin_config[] = { + GPIO15_nCS_1, /* CS1 - Flash */ + GPIO78_nCS_2, /* CS2 - Baseboard FGPA + SRAM */ + GPIO79_nCS_3, /* CS3 - SMC ethernet */ + GPIO80_nCS_4, /* CS4 - SA1111 */ + + /* LCD - 16bpp DSTN */ + GPIOxx_LCD_DSTN_16BPP, + + /* FFUART */ + GPIO34_FFUART_RXD, + GPIO35_FFUART_CTS, + GPIO36_FFUART_DCD, + GPIO37_FFUART_DSR, + GPIO38_FFUART_RI, + GPIO39_FFUART_TXD, + GPIO40_FFUART_DTR, + GPIO41_FFUART_RTS, +}; + +static int lubbock_devices_init(void) +{ + void *nor0_iospace; + + armlinux_set_architecture(MACH_TYPE_LUBBOCK); + + pxa_add_uart((void *)0x40100000, 0); + pxa_add_pwm((void *)0x40b00000, 0); + + nor0_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_64M); + add_cfi_flash_device(0, (ulong)nor0_iospace, SZ_64M, 0); + add_cfi_flash_device(1, 0x04000000, SZ_64M, 0); + devfs_add_partition("nor0", SZ_2M, SZ_256K, DEVFS_PARTITION_FIXED, + "env0"); + add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, + 0x0c000300, 0xff4000, IORESOURCE_MEM, + &smsc91x_pdata); + return 0; +} + +device_initcall(lubbock_devices_init); + +static void smc_init(void) +{ + /* SMC91c96 */ + void __iomem *attaddr = (void __iomem *)0x0e000000; + + writel(ECOR_RESET, attaddr + (ECOR << 2)); + mdelay(100); + writel(0, attaddr + (ECOR << 2)); + writel(ECOR_ENABLE, attaddr + (ECOR << 2)); + + /* force 16-bit mode */ + writel(0, attaddr + (ECSR << 2)); + mdelay(100); +} + +static int lubbock_coredevice_init(void) +{ + barebox_set_model("Lubbock PXA25x"); + barebox_set_hostname("lubbock"); + pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config)); + smc_init(); + return 0; +} +coredevice_initcall(lubbock_coredevice_init); + +static int lubbock_mem_init(void) +{ + arm_add_mem_device("ram0", 0xa0000000, SZ_64M); + add_mem_device("sram0", 0x0a000000, SZ_1M, IORESOURCE_MEM_WRITEABLE); + return 0; +} +mem_initcall(lubbock_mem_init); diff --git a/arch/arm/boards/lubbock/env/boot/nor-ubi b/arch/arm/boards/lubbock/env/boot/nor-ubi new file mode 100644 index 0000000000..533605e86a --- /dev/null +++ b/arch/arm/boards/lubbock/env/boot/nor-ubi @@ -0,0 +1,5 @@ +#!/bin/sh + +global.bootm.image="/dev/nor0.kernel" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:linux_root ubi.mtd=nor0.root rootfstype=ubifs" diff --git a/arch/arm/boards/lubbock/env/init/mtdparts-nor b/arch/arm/boards/lubbock/env/init/mtdparts-nor new file mode 100644 index 0000000000..3307596467 --- /dev/null +++ b/arch/arm/boards/lubbock/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)" +kernelname="application-flash" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/lubbock/env/nv/linux.bootargs.base b/arch/arm/boards/lubbock/env/nv/linux.bootargs.base new file mode 100644 index 0000000000..476b1fbe49 --- /dev/null +++ b/arch/arm/boards/lubbock/env/nv/linux.bootargs.base @@ -0,0 +1 @@ +console=ttyS0,115200 diff --git a/arch/arm/boards/lubbock/lowlevel.c b/arch/arm/boards/lubbock/lowlevel.c new file mode 100644 index 0000000000..3c8ae76e03 --- /dev/null +++ b/arch/arm/boards/lubbock/lowlevel.c @@ -0,0 +1,192 @@ +#include <common.h> +#include <init.h> +#include <io.h> + +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <linux/sizes.h> +#include <mach/pxa-regs.h> +#include <mach/regs-ost.h> + +/* + * Memory settings + */ +#define DEFAULT_MSC0_VAL 0x23d223d2 +#define DEFAULT_MSC1_VAL 0x3ff1a441 +#define DEFAULT_MSC2_VAL 0x7ff17ff1 +#define DEFAULT_MDCNFG_VAL 0x00001ac9 +#define DEFAULT_MDREFR_VAL 0x00018018 +#define DEFAULT_MDMRS_VAL 0x00000000 + +#define DEFAULT_FLYCNFG_VAL 0x00000000 +#define DEFAULT_SXCNFG_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define DEFAULT_MECR_VAL 0x00000000 +#define DEFAULT_MCMEM0_VAL 0x00010504 +#define DEFAULT_MCMEM1_VAL 0x00010504 +#define DEFAULT_MCATT0_VAL 0x00010504 +#define DEFAULT_MCATT1_VAL 0x00010504 +#define DEFAULT_MCIO0_VAL 0x00004715 +#define DEFAULT_MCIO1_VAL 0x00004715 + +static inline void writelrb(uint32_t val, volatile u32 __iomem *addr) +{ + writel(val, addr); + barrier(); + readl(addr); + barrier(); +} + +static inline void pxa_wait_ticks(int ticks) +{ + writel(0, &OSCR); + while (readl(&OSCR) < ticks) + barrier(); +} + +static inline void pxa2xx_dram_init(void) +{ + uint32_t tmp; + int i; + /* + * 1) Initialize Asynchronous static memory controller + */ + + writelrb(DEFAULT_MSC0_VAL, &MSC0); + writelrb(DEFAULT_MSC1_VAL, &MSC1); + writelrb(DEFAULT_MSC2_VAL, &MSC2); + /* + * 2) Initialize Card Interface + */ + + /* MECR: Memory Expansion Card Register */ + writelrb(DEFAULT_MECR_VAL, &MECR); + /* MCMEM0: Card Interface slot 0 timing */ + writelrb(DEFAULT_MCMEM0_VAL, &MCMEM0); + /* MCMEM1: Card Interface slot 1 timing */ + writelrb(DEFAULT_MCMEM1_VAL, &MCMEM1); + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + writelrb(DEFAULT_MCATT0_VAL, &MCATT0); + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + writelrb(DEFAULT_MCATT1_VAL, &MCATT1); + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + writelrb(DEFAULT_MCIO0_VAL, &MCIO0); + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + writelrb(DEFAULT_MCIO1_VAL, &MCIO1); + + /* + * 3) Configure Fly-By DMA register + */ + + writelrb(DEFAULT_FLYCNFG_VAL, &FLYCNFG); + + /* + * 4) Initialize Timing for Sync Memory (SDCLK0) + */ + + /* + * Before accessing MDREFR we need a valid DRI field, so we set + * this to power on defaults + DRI field. + */ + + /* Read current MDREFR config and zero out DRI */ + tmp = readl(&MDREFR) & ~0xfff; + /* Add user-specified DRI */ + tmp |= DEFAULT_MDREFR_VAL & 0xfff; + /* Configure important bits */ + tmp |= MDREFR_K0RUN | MDREFR_SLFRSH; + tmp &= ~(MDREFR_APD | MDREFR_E1PIN); + + /* Write MDREFR back */ + writelrb(tmp, &MDREFR); + + /* + * 5) Initialize Synchronous Static Memory (Flash/Peripherals) + */ + + /* Initialize SXCNFG register. Assert the enable bits. + * + * Write SXMRS to cause an MRS command to all enabled banks of + * synchronous static memory. Note that SXLCR need not be written + * at this time. + */ + writelrb(DEFAULT_SXCNFG_VAL, &SXCNFG); + + /* + * 6) Initialize SDRAM + */ + + writelrb(DEFAULT_MDREFR_VAL & ~MDREFR_SLFRSH, &MDREFR); + writelrb(DEFAULT_MDREFR_VAL | MDREFR_E1PIN, &MDREFR); + + /* + * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure + * but not enable each SDRAM partition pair. + */ + + writelrb(DEFAULT_MDCNFG_VAL & + ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), &MDCNFG); + /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ + pxa_wait_ticks(0x300); + + /* + * 8) Trigger a number (usually 8) refresh cycles by attempting + * non-burst read or write accesses to disabled SDRAM, as commonly + * specified in the power up sequence documented in SDRAM data + * sheets. The address(es) used for this purpose must not be + * cacheable. + */ + for (i = 9; i >= 0; i--) { + writel(i, 0xa0000000); + barrier(); + } + /* + * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). + */ + + tmp = DEFAULT_MDCNFG_VAL & + (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3); + tmp |= readl(&MDCNFG); + writelrb(tmp, &MDCNFG); + + /* + * 10) Write MDMRS. + */ + + writelrb(DEFAULT_MDMRS_VAL, &MDMRS); + + /* + * 11) Enable APD + */ + + if (DEFAULT_MDREFR_VAL & MDREFR_APD) { + tmp = readl(&MDREFR); + tmp |= MDREFR_APD; + writelrb(tmp, &MDREFR); + } +} + +void __bare_init __naked barebox_arm_reset_vector(void) +{ + unsigned long pssr = PSSR; + unsigned long pc = get_pc(); + + arm_cpu_lowlevel_init(); + CKEN |= CKEN_OSTIMER | CKEN_MEMC | CKEN_FFUART; + + /* + * When not running from SDRAM, get it out of self refresh, and/or + * initialize it. + */ + if (!(pc >= 0xa0000000 && pc < 0xb0000000)) + pxa2xx_dram_init(); + + if ((pssr >= 0xa0000000 && pssr < 0xb0000000) || + (pssr >= 0x04000000 && pssr < 0x10000000)) + asm("mov pc, %0" : : "r"(pssr) : ); + + barebox_arm_entry(0xa0000000, SZ_64M, 0); +} diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c index 1551460393..5f65261a9f 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/board.c +++ b/arch/arm/boards/phytec-phyflex-imx6/board.c @@ -17,6 +17,7 @@ * */ +#include <malloc.h> #include <envfs.h> #include <environment.h> #include <bootsource.h> @@ -65,6 +66,9 @@ static void phyflex_err006282_workaround(void) static int phytec_pfla02_init(void) { + int ret; + char *environment_path; + if (!of_machine_is_compatible("phytec,imx6q-pfla02") && !of_machine_is_compatible("phytec,imx6dl-pfla02") && !of_machine_is_compatible("phytec,imx6s-pfla02")) @@ -76,19 +80,38 @@ static int phytec_pfla02_init(void) switch (bootsource_get()) { case BOOTSOURCE_MMC: - of_device_enable_path("/chosen/environment-sd"); + environment_path = asprintf("/chosen/environment-sd%d", + bootsource_get_instance() + 1); break; case BOOTSOURCE_NAND: - of_device_enable_path("/chosen/environment-nand"); + environment_path = asprintf("/chosen/environment-nand"); break; default: case BOOTSOURCE_SPI: - of_device_enable_path("/chosen/environment-spinor"); + environment_path = asprintf("/chosen/environment-spinor"); break; } - defaultenv_append_directory(defaultenv_phyflex_imx6); + ret = of_device_enable_path(environment_path); + if (ret < 0) + pr_warn("Failed to enable environment partition '%s' (%d)\n", + environment_path, ret); + + free(environment_path); return 0; } device_initcall(phytec_pfla02_init); + +static int phytec_pbab0x_init(void) +{ + if (!of_machine_is_compatible("phytec,imx6x-pbab01") && + !of_machine_is_compatible("phytec,imx6dl-pbab05") && + !of_machine_is_compatible("phytec,imx6q-pbab02")) + return 0; + + defaultenv_append_directory(defaultenv_phyflex_imx6); + + return 0; +} +device_initcall(phytec_pbab0x_init); diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg new file mode 100644 index 0000000000..e414b6e612 --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x565c9b85 + +#define SETUP_1GIB_2GIB_4GIB \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x831a0000 + +#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c index dbd264aed2..ee6d7fb262 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c @@ -90,6 +90,7 @@ static void __noreturn start_imx6_phytec_common(uint32_t size, } PHYTEC_ENTRY(start_phytec_pbab01_1gib, imx6q_phytec_pbab01, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_pbab01_1gib_1bank, imx6q_phytec_pbab01, SZ_1G, true); PHYTEC_ENTRY(start_phytec_pbab01_2gib, imx6q_phytec_pbab01, SZ_2G, true); PHYTEC_ENTRY(start_phytec_pbab01_4gib, imx6q_phytec_pbab01, SZ_4G, true); PHYTEC_ENTRY(start_phytec_pbab01dl_1gib, imx6dl_phytec_pbab01, SZ_1G, false); diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c index 57dc7b0667..7504bf83b0 100644 --- a/arch/arm/boards/sama5d3xek/init.c +++ b/arch/arm/boards/sama5d3xek/init.c @@ -49,11 +49,13 @@ #include "hw_version.h" +#ifdef CONFIG_W1_MASTER_GPIO struct w1_gpio_platform_data w1_pdata = { .pin = AT91_PIN_PE25, .ext_pullup_enable_pin = -EINVAL, .is_open_drain = 0, }; +#endif #if defined(CONFIG_NAND_ATMEL) static struct atmel_nand_data nand_pdata = { @@ -123,12 +125,12 @@ static void ek_add_device_nand(void) {} #if defined(CONFIG_DRIVER_NET_MACB) static struct macb_platform_data gmac_pdata = { .phy_interface = PHY_INTERFACE_MODE_RGMII, - .phy_addr = 7, + .phy_addr = -1, }; static struct macb_platform_data macb_pdata = { .phy_interface = PHY_INTERFACE_MODE_RMII, - .phy_addr = 0, + .phy_addr = -1, }; static bool used_23 = false; @@ -323,11 +325,13 @@ struct gpio_led leds[] = { .name = "d1", }, }, { +#ifndef CONFIG_W1_MASTER_GPIO .gpio = AT91_PIN_PE25, .active_low = 1, .led = { .name = "d2", }, +#endif }, }; @@ -353,6 +357,7 @@ static int at91sama5d3xek_mem_init(void) } mem_initcall(at91sama5d3xek_mem_init); +#ifdef CONFIG_W1_MASTER_GPIO static void ek_add_device_w1(void) { at91_set_gpio_input(w1_pdata.pin, 0); @@ -361,6 +366,9 @@ static void ek_add_device_w1(void) at91sama5d3xek_devices_detect_hw(); } +#else +static void ek_add_device_w1(void) {} +#endif #ifdef CONFIG_POLLER /* diff --git a/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c b/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c index fe6876a9eb..f5b885ce0d 100644 --- a/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c +++ b/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c @@ -40,6 +40,7 @@ static struct atmel_nand_data nand_pdata = { .rdy_pin = -EINVAL, .enable_pin = -EINVAL, .ecc_mode = NAND_ECC_HW, + .has_pmecc = 1, .pmecc_sector_size = 512, .pmecc_corr_cap = 8, .on_flash_bbt = 1, @@ -161,7 +162,7 @@ static void ek_add_device_mci(void) at91_add_device_mci(1, &mci1_data); /* power on MCI1 */ - at91_set_gpio_output(AT91_PIN_PE15, 0); + at91_set_gpio_output(AT91_PIN_PE4, 0); } #else static void ek_add_device_mci(void) {} @@ -245,15 +246,15 @@ static void ek_add_led(void) static void ek_add_led(void) {} #endif -static int sama5d4ek_mem_init(void) +static int sama5d4_xplained_mem_init(void) { at91_add_device_sdram(0); return 0; } -mem_initcall(sama5d4ek_mem_init); +mem_initcall(sama5d4_xplained_mem_init); -static const struct devfs_partition sama5d4ek_nand0_partitions[] = { +static const struct devfs_partition sama5d4_xplained_nand0_partitions[] = { { .offset = 0x00000, .size = SZ_256K, @@ -283,7 +284,7 @@ static const struct devfs_partition sama5d4ek_nand0_partitions[] = { } }; -static int sama5d4ek_devices_init(void) +static int sama5d4_xplained_devices_init(void) { ek_add_device_i2c(); ek_add_device_nand(); @@ -293,27 +294,27 @@ static int sama5d4ek_devices_init(void) ek_add_device_mci(); ek_add_device_lcdc(); - devfs_create_partitions("nand0", sama5d4ek_nand0_partitions); + devfs_create_partitions("nand0", sama5d4_xplained_nand0_partitions); return 0; } -device_initcall(sama5d4ek_devices_init); +device_initcall(sama5d4_xplained_devices_init); -static int sama5d4ek_console_init(void) +static int sama5d4_xplained_console_init(void) { - barebox_set_model("Atmel sama5d4ek"); - barebox_set_hostname("sama5d4ek"); + barebox_set_model("Atmel sama5d4_xplained"); + barebox_set_hostname("sama5d4_xplained"); at91_register_uart(4, 0); return 0; } -console_initcall(sama5d4ek_console_init); +console_initcall(sama5d4_xplained_console_init); -static int sama5d4ek_main_clock(void) +static int sama5d4_xplained_main_clock(void) { at91_set_main_clock(12000000); return 0; } -pure_initcall(sama5d4ek_main_clock); +pure_initcall(sama5d4_xplained_main_clock); diff --git a/arch/arm/boards/sama5d4ek/sama5d4ek.c b/arch/arm/boards/sama5d4ek/sama5d4ek.c index bbc53c6758..790a063266 100644 --- a/arch/arm/boards/sama5d4ek/sama5d4ek.c +++ b/arch/arm/boards/sama5d4ek/sama5d4ek.c @@ -1,5 +1,5 @@ /* - * SAMA5D4EK board configureation. + * SAMA5D4EK board configuration. * * Copyright (C) 2014 Atmel Corporation, * Bo Shen <voice.shen@atmel.com> @@ -40,6 +40,7 @@ static struct atmel_nand_data nand_pdata = { .rdy_pin = -EINVAL, .enable_pin = -EINVAL, .ecc_mode = NAND_ECC_HW, + .has_pmecc = 1, .pmecc_sector_size = 512, .pmecc_corr_cap = 8, .on_flash_bbt = 1, diff --git a/arch/arm/boards/virt2real/Makefile b/arch/arm/boards/virt2real/Makefile index b2f44bba1b..01c7a259e9 100644 --- a/arch/arm/boards/virt2real/Makefile +++ b/arch/arm/boards/virt2real/Makefile @@ -1 +1,2 @@ -obj-y += lowlevel.o board.o +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/zylonite/Makefile b/arch/arm/boards/zylonite/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/zylonite/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/zylonite/board.c b/arch/arm/boards/zylonite/board.c new file mode 100644 index 0000000000..dabc6ffb0b --- /dev/null +++ b/arch/arm/boards/zylonite/board.c @@ -0,0 +1,101 @@ +/* + * (C) 2014 Robert Jarzmik <robert.jarzmik@free.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> + +#include <driver.h> +#include <environment.h> +#include <fs.h> +#include <gpio.h> +#include <init.h> +#include <partition.h> +#include <led.h> +#include <net/smc91111.h> +#include <platform_data/mtd-nand-mrvl.h> +#include <pwm.h> + +#include <mach/devices.h> +#include <mach/mfp-pxa3xx.h> +#include <mach/pxa-regs.h> + +#include <asm/armlinux.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <generated/mach-types.h> + +#include "zylonite.h" + +static struct smc91c111_pdata smsc91x_pdata; +static struct mrvl_nand_platform_data nand_pdata = { + .keep_config = 0, + .flash_bbt = 1, +}; + +static mfp_cfg_t pxa310_mfp_cfg[] = { + /* FFUART */ + MFP_CFG_LPM(GPIO99, AF1, FLOAT), /* GPIO99_UART1_RXD */ + MFP_CFG_LPM(GPIO100, AF1, FLOAT), /* GPIO100_UART1_RXD */ + MFP_CFG_LPM(GPIO101, AF1, FLOAT), /* GPIO101_UART1_CTS */ + MFP_CFG_LPM(GPIO106, AF1, FLOAT), /* GPIO106_UART1_CTS */ + + /* Ethernet */ + MFP_CFG(GPIO2, AF1), /* GPIO2_nCS3 */ +}; + +static int zylonite_devices_init(void) +{ + armlinux_set_architecture(MACH_TYPE_ZYLONITE); + pxa_add_uart((void *)0x40100000, 0); + add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, + 0x14000300, 0x100000, IORESOURCE_MEM, + &smsc91x_pdata); + add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL, + 0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata); + return 0; +} +device_initcall(zylonite_devices_init); + +static int zylonite_coredevice_init(void) +{ + barebox_set_model("Zylonite"); + barebox_set_hostname("zylonite"); + + mfp_init(); + if (cpu_is_pxa310()) + pxa3xx_mfp_config(pxa310_mfp_cfg, ARRAY_SIZE(pxa310_mfp_cfg)); + CKENA |= CKEN_NAND | CKEN_SMC | CKEN_FFUART | CKEN_GPIO; + /* + * Configure Ethernet controller : + * MCS1: setup VLIO on nCS3, with 15 DF_SCLK cycles (max) for hold, + * setup and assertion times + * CSADRCFG3: DFI AA/D multiplexing VLIO, addr split at bit <16>, full + * latched mode, 7 DF_SCLK cycles (max) for nLUA and nLLA. + */ + MSC1 = 0x7ffc0000 | (MSC1 & 0x0000ffff); + CSADRCFG3 = 0x003e080b; + + return 0; +} +coredevice_initcall(zylonite_coredevice_init); + +static int zylonite_mem_init(void) +{ + arm_add_mem_device("ram0", 0x80000000, 64 * 1024 * 1024); + return 0; +} +mem_initcall(zylonite_mem_init); diff --git a/arch/arm/boards/zylonite/env/bin/init b/arch/arm/boards/zylonite/env/bin/init new file mode 100644 index 0000000000..a6bc087b22 --- /dev/null +++ b/arch/arm/boards/zylonite/env/bin/init @@ -0,0 +1,25 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +addpart /dev/nand0 $mtdparts +usbserial -s "Zylonite usb gadget" + +# Phase1: check for MTD override +mtd_env_override +if [ $? = 0 ]; then + echo "Switching to custom environment" + /env/init + exit +fi + +# Phase2: initiate network +dhcp -H zylonite + +# Phase3: activate netconsole, broadcast everywhere +netconsole.ip=255.255.255.255 +netconsole.active=ioe +netconsole.port=6666 + diff --git a/arch/arm/boards/zylonite/env/bin/mtd_env_override b/arch/arm/boards/zylonite/env/bin/mtd_env_override new file mode 100644 index 0000000000..6ea253a4f0 --- /dev/null +++ b/arch/arm/boards/zylonite/env/bin/mtd_env_override @@ -0,0 +1,4 @@ +#!/bin/sh + +loadenv /dev/nand0.barebox-env +exit $? diff --git a/arch/arm/boards/zylonite/env/config b/arch/arm/boards/zylonite/env/config new file mode 100644 index 0000000000..ee66e37cc3 --- /dev/null +++ b/arch/arm/boards/zylonite/env/config @@ -0,0 +1,6 @@ +#!/bin/sh + +autoboot_timeout=3 + +mtdparts="128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)" +bootargs="$bootargs mtdparts=pxa3xx_nand-0:$mtdparts ubi.mtd=5 rootfstype=ubifs root=ubi0:root ro ram=64M console=ttyS0,115200" diff --git a/arch/arm/boards/zylonite/lowlevel.c b/arch/arm/boards/zylonite/lowlevel.c new file mode 100644 index 0000000000..9f1aa6641c --- /dev/null +++ b/arch/arm/boards/zylonite/lowlevel.c @@ -0,0 +1,10 @@ +#include <common.h> +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> + +void __naked barebox_arm_reset_vector(void) +{ + arm_cpu_lowlevel_init(); + barebox_arm_entry(0x80000000, SZ_64M, NULL); +} diff --git a/arch/arm/boards/zylonite/zylonite.h b/arch/arm/boards/zylonite/zylonite.h new file mode 100644 index 0000000000..d39ab72d3d --- /dev/null +++ b/arch/arm/boards/zylonite/zylonite.h @@ -0,0 +1,22 @@ +/* + * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef _ZYLONITE_H_ +#define _ZYLONITE_H_ + + +#endif /* _ZYLONITE_H */ diff --git a/arch/arm/configs/duckbill_defconfig b/arch/arm/configs/duckbill_defconfig new file mode 100644 index 0000000000..6210416130 --- /dev/null +++ b/arch/arm/configs/duckbill_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARCH_MXS=y +CONFIG_ARCH_IMX28=y +CONFIG_MACH_DUCKBILL=y +CONFIG_ARCH_MXS_USBLOADER=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x0 +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_BLSPEC=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_RESET_SOURCE=y +CONFIG_DEBUG_INFO=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_CMP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_HOST=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENUTREE=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y +CONFIG_CMD_NANDTEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_USBGADGET=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_NET=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_AUART=y +CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_DRIVER_SPI_MXS=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DFU=y +CONFIG_USB_GADGET_SERIAL=y +CONFIG_USB_GADGET_FASTBOOT=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_STM=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_MXS=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y +CONFIG_MXS_APBH_DMA=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/freescale-mx28-evk_defconfig b/arch/arm/configs/freescale-mx28-evk_defconfig index b6a63200c7..22ed7bc3ef 100644 --- a/arch/arm/configs/freescale-mx28-evk_defconfig +++ b/arch/arm/configs/freescale-mx28-evk_defconfig @@ -3,37 +3,71 @@ CONFIG_ARCH_IMX28=y CONFIG_MACH_MX28EVK=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y CONFIG_MMU=y -CONFIG_TEXT_BASE=0x43000000 -CONFIG_MALLOC_SIZE=0x800000 -CONFIG_BROKEN=y -CONFIG_LONGHELP=y -CONFIG_GLOB=y +CONFIG_TEXT_BASE=0x0 +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx28-evk/env" +CONFIG_MENU=y +CONFIG_BLSPEC=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_RESET_SOURCE=y CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_PARTITION=y CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_CMP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_HOST=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y CONFIG_CMD_ECHO_E=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENUTREE=y CONFIG_CMD_SPLASH=y +CONFIG_CMD_READLINE=y CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y CONFIG_CMD_GPIO=y +CONFIG_CMD_NANDTEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y CONFIG_NET=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_NET_RESOLV=y CONFIG_DRIVER_SERIAL_AUART=y CONFIG_DRIVER_NET_FEC_IMX=y CONFIG_DRIVER_SPI_MXS=y @@ -48,4 +82,5 @@ CONFIG_MCI_MXS=y CONFIG_MXS_APBH_DMA=y CONFIG_FS_TFTP=y CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/haba_knx_lite_defconfig b/arch/arm/configs/haba_knx_lite_defconfig new file mode 100644 index 0000000000..62d66bc5f2 --- /dev/null +++ b/arch/arm/configs/haba_knx_lite_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARCH_AT91SAM9G20=y +CONFIG_MACH_HABA_KNX_LITE=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x27f00000 +CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y +CONFIG_PROMPT="HABA-KNX-LITE:" +CONFIG_GLOB=y +CONFIG_PROMPT_HUSH_PS2="y" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/haba-knx/env" +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_LONGHELP=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LED=y +CONFIG_CMD_SPI=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OFTREE=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_NET_NETCONSOLE=y +CONFIG_DRIVER_NET_MACB=y +CONFIG_DRIVER_SPI_ATMEL=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_M25P80=y +CONFIG_NAND=y +# CONFIG_NAND_ECC_HW is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +CONFIG_MTD_UBI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_SERIAL=y +CONFIG_MCI=y +# CONFIG_MCI_INFO is not set +# CONFIG_MCI_WRITE is not set +CONFIG_MCI_SPI=y +CONFIG_MMC_SPI_CRC_ON=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_TRIGGERS=y +CONFIG_EEPROM_AT24=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UBIFS=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig new file mode 100644 index 0000000000..bf04fa3b18 --- /dev/null +++ b/arch/arm/configs/lubbock_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARCH_PXA=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000 +CONFIG_AEABI=y +CONFIG_ARM_BOARD_APPEND_ATAG=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +# CONFIG_BANNER is not set +CONFIG_MMU=y +CONFIG_TEXT_BASE=0xa3d00000 +CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000 +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_EXPERIMENTAL=y +CONFIG_MODULES=y +CONFIG_KALLSYMS=y +CONFIG_PROMPT="lubbock-barebox:" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/lubbock/env" +CONFIG_RESET_SOURCE=y +CONFIG_DEBUG_INFO=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_SAVES=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_HOST=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_LSMOD=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_PXA=y +CONFIG_DRIVER_NET_SMC91111=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_DRIVER_CFI=y +# CONFIG_DRIVER_CFI_AMD is not set +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_MCI=y +CONFIG_MCI_PXA=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_GENERIC_PHY=y +CONFIG_FS_CRAMFS=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UBIFS=y +CONFIG_FS_UBIFS_COMPRESSION_LZO=y +CONFIG_FS_UBIFS_COMPRESSION_ZLIB=y +CONFIG_BZLIB=y +CONFIG_BMP=y +CONFIG_PNG=y diff --git a/arch/arm/configs/mioa701_defconfig b/arch/arm/configs/mioa701_defconfig index 20f71e9374..d405edf01b 100644 --- a/arch/arm/configs/mioa701_defconfig +++ b/arch/arm/configs/mioa701_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_PXA=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000 +CONFIG_ARCH_PXA27X=y CONFIG_AEABI=y CONFIG_ARM_BOARD_APPEND_ATAG=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y diff --git a/arch/arm/configs/phytec-phycore-pxa270_defconfig b/arch/arm/configs/phytec-phycore-pxa270_defconfig index b7bf190df2..57eaff09ec 100644 --- a/arch/arm/configs/phytec-phycore-pxa270_defconfig +++ b/arch/arm/configs/phytec-phycore-pxa270_defconfig @@ -1,4 +1,5 @@ CONFIG_ARCH_PXA=y +CONFIG_ARCH_PXA27X=y CONFIG_MACH_PCM027=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y diff --git a/arch/arm/configs/zylonite310_defconfig b/arch/arm/configs/zylonite310_defconfig new file mode 100644 index 0000000000..77e4f84ff1 --- /dev/null +++ b/arch/arm/configs/zylonite310_defconfig @@ -0,0 +1,117 @@ +CONFIG_ARCH_PXA=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000 +CONFIG_ARCH_PXA3XX=y +CONFIG_AEABI=y +CONFIG_ARM_BOARD_APPEND_ATAG=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +# CONFIG_BANNER is not set +CONFIG_MMU=y +CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000 +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_EXPERIMENTAL=y +CONFIG_MODULES=y +CONFIG_KALLSYMS=y +CONFIG_PROMPT="zylonite-barebox:" +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/zylonite/env" +CONFIG_RESET_SOURCE=y +CONFIG_DEFAULT_LOGLEVEL=8 +CONFIG_DEBUG_INFO=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +CONFIG_FLEXIBLE_BOOTARGS=y +CONFIG_CMD_BOOT=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_SAVES=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_AUTOMOUNT=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_GLOBAL=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_BASENAME=y +CONFIG_CMD_CMP=y +CONFIG_CMD_DIRNAME=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_READLINK=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_HOST=y +CONFIG_NET_CMD_IFUP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_LOGIN=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_2048=y +CONFIG_CMD_LSMOD=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_PXA=y +CONFIG_DRIVER_NET_SMC91111=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MRVL_NFC=y +CONFIG_MTD_UBI=y +CONFIG_MCI=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_PWM=y +# CONFIG_PINCTRL is not set +CONFIG_FS_CRAMFS=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UBIFS=y +CONFIG_FS_UBIFS_COMPRESSION_LZO=y +CONFIG_FS_UBIFS_COMPRESSION_ZLIB=y +CONFIG_BZLIB=y +CONFIG_BMP=y +CONFIG_PNG=y +CONFIG_SHA256=y diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig index 8934df0074..4f5d9b6e16 100644 --- a/arch/arm/cpu/Kconfig +++ b/arch/arm/cpu/Kconfig @@ -69,6 +69,12 @@ config CPU_V7 bool select CPU_32v7 +config CPU_XSC3 + bool + select CPU_32v4T + help + Select code specific to PXA3xx variants + # Xscale PXA25x, PXA27x config CPU_XSCALE bool diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index 09fe8d592a..e733ec4b81 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -1,6 +1,4 @@ /* - * start-pbl.c - * * Copyright (c) 2009-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/cpu/setupc.S b/arch/arm/cpu/setupc.S index 2df2683128..c232b08d3b 100644 --- a/arch/arm/cpu/setupc.S +++ b/arch/arm/cpu/setupc.S @@ -40,7 +40,7 @@ ENDPROC(setup_c) /* * void relocate_to_adr(unsigned long targetadr) * - * Copy binary to targetadr, relocate code, clear bss and continue + * Copy binary to targetadr, relocate code and continue * executing at new address. */ .section .text.relocate_to_adr diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c index 418870fb69..304ed0cee7 100644 --- a/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c @@ -1,6 +1,4 @@ /* - * start-arm.c - * * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix * * See file CREDITS for list of people who contributed to this diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dc32dd37c2..7b3db8ce48 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -5,11 +5,12 @@ endif # just to build a built-in.o. Otherwise compilation fails when no devicetree is # created. -obj-y += empty.o +obj- += dummy.o pbl-dtb-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o pbl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o pbl-dtb-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o +pbl-dtb-$(CONFIG_MACH_DUCKBILL) += imx28-duckbill.dtb.o pbl-dtb-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o pbl-dtb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o pbl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi index c34ae38271..7d0e3c5466 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi @@ -17,6 +17,13 @@ }; &am33xx_pinmux { + usb_pins: pinmux_usb_pins { + pinctrl-single,pins = < + 0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ + 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + >; + }; + i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ @@ -106,6 +113,29 @@ }; }; +&cppi41dma { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb { + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins>; + status = "okay"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1_phy { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; diff --git a/arch/arm/dts/am335x-phytec-phyflex.dts b/arch/arm/dts/am335x-phytec-phyflex.dts index 6c49567107..5459cd24db 100644 --- a/arch/arm/dts/am335x-phytec-phyflex.dts +++ b/arch/arm/dts/am335x-phytec-phyflex.dts @@ -39,6 +39,13 @@ }; &am33xx_pinmux { + usb_pins: pinmux_usb { + pinctrl-single,pins = < + 0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ + 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + >; + }; + i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda */ @@ -129,6 +136,30 @@ }; }; +&cppi41dma { + status = "okay"; +}; + + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb { + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins>; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; diff --git a/arch/arm/dts/empty.c b/arch/arm/dts/empty.c deleted file mode 100644 index d141224cf8..0000000000 --- a/arch/arm/dts/empty.c +++ /dev/null @@ -1,3 +0,0 @@ -static inline void empty(void) -{ -} diff --git a/arch/arm/dts/imx28-duckbill.dts b/arch/arm/dts/imx28-duckbill.dts new file mode 100644 index 0000000000..2a995a7938 --- /dev/null +++ b/arch/arm/dts/imx28-duckbill.dts @@ -0,0 +1,15 @@ +#include <arm/imx28-duckbill.dts> + +/ { + chosen { + stdout-path = &duart; + }; +}; + +&duart { + arm,primecell-periphid = <0x00041011>; +}; + +&ocotp { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-embedsky-e9.dts b/arch/arm/dts/imx6q-embedsky-e9.dts index d8a606a1bb..53665cf9d5 100644 --- a/arch/arm/dts/imx6q-embedsky-e9.dts +++ b/arch/arm/dts/imx6q-embedsky-e9.dts @@ -19,9 +19,16 @@ chosen { linux,stdout-path = &uart4; - environment@0 { + environment-mmc1 { compatible = "barebox,environment"; device-path = &usdhc2, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-mmc3 { + compatible = "barebox,environment"; + device-path = &usdhc4, "partname:barebox-environment"; + status = "disabled"; }; }; @@ -40,3 +47,17 @@ reg = <0x80000 0x80000>; }; }; + +&usdhc4 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index 32ce088fee..5ac0ef9431 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -23,11 +23,29 @@ status = "disabled"; }; - environment-sd { + environment-sd1 { + compatible = "barebox,environment"; + device-path = &usdhc1, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-sd2 { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-sd3 { compatible = "barebox,environment"; device-path = &usdhc3, "partname:barebox-environment"; status = "disabled"; }; + + environment-sd4 { + compatible = "barebox,environment"; + device-path = &usdhc4, "partname:barebox-environment"; + status = "disabled"; + }; }; }; @@ -48,14 +66,23 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0x100000>; }; partition@1 { label = "barebox-environment"; - reg = <0x80000 0x10000>; + reg = <0x100000 0x20000>; }; + partition@2 { + label = "oftree"; + reg = <0x120000 0x20000>; + }; + + partition@3 { + label = "kernel"; + reg = <0x140000 0x0>; + }; }; }; @@ -95,22 +122,22 @@ partition@1 { label = "barebox-environment"; - reg = <0x400000 0x20000>; + reg = <0x400000 0x100000>; }; partition@2 { label = "oftree"; - reg = <0x420000 0x20000>; + reg = <0x500000 0x100000>; }; partition@3 { label = "kernel"; - reg = <0x440000 0x800000>; + reg = <0x600000 0x800000>; }; partition@4 { label = "root"; - reg = <0xC40000 0x0>; + reg = <0xe00000 0x0>; }; }; diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h index 9ad07cb77a..dbc8aaaba7 100644 --- a/arch/arm/include/asm/barebox-arm.h +++ b/arch/arm/include/asm/barebox-arm.h @@ -29,6 +29,8 @@ #include <asm-generic/memory_layout.h> #include <linux/kernel.h> #include <linux/types.h> +#include <linux/compiler.h> +#include <asm/barebox-arm-head.h> /* cpu/.../cpu.c */ int cleanup_before_linux(void); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 9ee4f303b8..b85e6fa356 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -352,6 +352,11 @@ config MACH_QIL_A9G20 Select this if you are using a Calao Systems QIL-A9G20 Board. <http://www.calao-systems.com> +config MACH_HABA_KNX_LITE + bool "CALAO HABA-KNX-LITE" + help + Select this if you are using a Calao Systems HABA-KNX-LITE. + <http://www.calao-systems.com> endchoice endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 9ac36e1453..477207e646 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -119,6 +119,7 @@ config BAREBOX_UPDATE_IMX6_NAND depends on BAREBOX_UPDATE depends on MTD depends on MTD_WRITE + depends on NAND_MXS default y comment "Freescale i.MX System-on-Chip" diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c index 2ae8d6aa3a..ea805b0f64 100644 --- a/arch/arm/mach-imx/clk-imx5.c +++ b/arch/arm/mach-imx/clk-imx5.c @@ -372,6 +372,7 @@ int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART1_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART2_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART4_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C1_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C2_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C3_BASE_ADDR, NULL); diff --git a/arch/arm/mach-imx/imx6-bbu-nand.c b/arch/arm/mach-imx/imx6-bbu-nand.c index 1b46e514e9..d2bfedbad5 100644 --- a/arch/arm/mach-imx/imx6-bbu-nand.c +++ b/arch/arm/mach-imx/imx6-bbu-nand.c @@ -30,6 +30,7 @@ #include <fs.h> #include <mach/bbu.h> #include <linux/mtd/mtd-abi.h> +#include <linux/mtd/nand_mxs.h> #include <linux/mtd/mtd.h> #include <linux/stat.h> @@ -235,22 +236,9 @@ static int fcb_create(struct fcb_block *fcb, struct mtd_info *mtd) fcb->TotalPageSize = mtd->writesize + mtd->oobsize; fcb->SectorsPerBlock = mtd->erasesize / mtd->writesize; - if (mtd->writesize == 2048) { - fcb->EccBlock0EccType = 4; - } else if (mtd->writesize == 4096) { - if (mtd->oobsize == 218) { - fcb->EccBlock0EccType = 8; - } else if (mtd->oobsize == 128) { - fcb->EccBlock0EccType = 4; - } else { - pr_err("Illegal oobsize %d\n", mtd->oobsize); - return -EINVAL; - } - } else { - pr_err("Illegal writesize %d\n", mtd->writesize); - return -EINVAL; - } - + /* Divide ECC strength by two and save the value into FCB structure. */ + fcb->EccBlock0EccType = + mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1; fcb->EccBlockNEccType = fcb->EccBlock0EccType; /* Also hardcoded in kobs-ng */ @@ -267,12 +255,8 @@ static int fcb_create(struct fcb_block *fcb, struct mtd_info *mtd) /* DBBT search area starts at third block */ fcb->DBBTSearchAreaStartAddress = mtd->erasesize / mtd->writesize * 2; - if (mtd->writesize == 2048) { - fcb->BadBlockMarkerByte = 0x000007cf; - } else { - pr_err("BadBlockMarkerByte unknown for writesize %d\n", mtd->writesize); - return -EINVAL; - } + fcb->BadBlockMarkerByte = mxs_nand_mark_byte_offset(mtd); + fcb->BadBlockMarkerStartBit = mxs_nand_mark_bit_offset(mtd); fcb->BBMarkerPhysicalOffset = mtd->writesize; @@ -437,6 +421,16 @@ static int imx6_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *da fcb_create(fcb, mtd); encode_hamming_13_8(fcb, ecc, 512); + + /* + * Set the first and second byte of OOB data to 0xFF, not 0x00. These + * bytes are used as the Manufacturers Bad Block Marker (MBBM). Since + * the FCB is mostly written to the first page in a block, a scan for + * factory bad blocks will detect these blocks as bad, e.g. when + * function nand_scan_bbt() is executed to build a new bad block table. + */ + memset(fcb_raw_page + mtd->writesize, 0xFF, 2); + ret = raw_write_page(mtd, fcb_raw_page, 0); if (ret) goto out; diff --git a/arch/arm/mach-imx/include/mach/devices-imx53.h b/arch/arm/mach-imx/include/mach/devices-imx53.h index 88be4fdbc8..10caae8c93 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx53.h +++ b/arch/arm/mach-imx/include/mach/devices-imx53.h @@ -47,6 +47,11 @@ static inline struct device_d *imx53_add_uart2(void) return imx_add_uart_imx21((void *)MX53_UART3_BASE_ADDR, 2); } +static inline struct device_d *imx53_add_uart3(void) +{ + return imx_add_uart_imx21((void *)MX53_UART4_BASE_ADDR, 3); +} + static inline struct device_d *imx53_add_fec(struct fec_platform_data *pdata) { return imx_add_fec_imx27((void *)MX53_FEC_BASE_ADDR, pdata); diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 4022710007..ea0fa5a62b 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -68,10 +68,20 @@ config MACH_TX28 config MACH_MX28EVK bool "mx28-evk" + select HAVE_DEFAULT_ENVIRONMENT_NEW select MXS_OCOTP + select HAVE_PBL_MULTI_IMAGES help Say Y here if you are using the Freescale i.MX28-EVK board +config MACH_DUCKBILL + bool "Duckbill" + select HAVE_DEFAULT_ENVIRONMENT_NEW + select MXS_OCOTP + select HAVE_PBL_MULTI_IMAGES + help + Say Y here if you are using the I2SE Duckbill board + config MACH_CFA10036 bool "cfa-10036" select HAVE_DEFAULT_ENVIRONMENT_NEW diff --git a/arch/arm/mach-mxs/include/mach/init.h b/arch/arm/mach-mxs/include/mach/init.h index 1f9d8d48c0..90b413e47e 100644 --- a/arch/arm/mach-mxs/include/mach/init.h +++ b/arch/arm/mach-mxs/include/mach/init.h @@ -12,10 +12,10 @@ void mxs_early_delay(int delay); -void mx23_power_init(void); -void mx23_power_init_battery_input(void); -void mx28_power_init(void); -void mx28_power_init_battery_input(void); +void mx23_power_init(int __has_battery, int __use_battery_input, + int __use_5v_input); +void mx28_power_init(int __has_battery, int __use_battery_input, + int __use_5v_input); void mxs_power_wait_pswitch(void); extern uint32_t mx28_dram_vals[]; diff --git a/arch/arm/mach-mxs/iomux-imx.c b/arch/arm/mach-mxs/iomux-imx.c index 84c6ca4ca7..68a4e3cbd6 100644 --- a/arch/arm/mach-mxs/iomux-imx.c +++ b/arch/arm/mach-mxs/iomux-imx.c @@ -75,12 +75,6 @@ static unsigned calc_output_reg(unsigned no) return ((no >> 5) << 4) + HW_PINCTRL_DOUT0; } -static unsigned calc_input_reg(unsigned no) -{ - /* each register controls 32 pads */ - return ((no >> 5) << 4) + HW_PINCTRL_DIN0; -} - /** * @param[in] m One pin define per call from iomux-mx23.h/iomux-mx28.h */ @@ -168,57 +162,3 @@ void imx_gpio_mode(uint32_t m) } } } - -int gpio_direction_input(unsigned gpio) -{ - unsigned reg_offset; - - if (gpio > MAX_GPIO_NO) - return -EINVAL; - - reg_offset = calc_output_enable_reg(gpio); - writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_CLR); - - return 0; -} - -int gpio_direction_output(unsigned gpio, int val) -{ - unsigned reg_offset; - - if (gpio > MAX_GPIO_NO) - return -EINVAL; - - /* first set the output value... */ - reg_offset = calc_output_reg(gpio); - writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + - reg_offset + (val != 0 ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR)); - /* ...then the direction */ - reg_offset = calc_output_enable_reg(gpio); - writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + STMP_OFFSET_REG_SET); - - return 0; -} - -void gpio_set_value(unsigned gpio, int val) -{ - unsigned reg_offset; - - reg_offset = calc_output_reg(gpio); - writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + - reg_offset + (val != 0 ? - STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR)); -} - -int gpio_get_value(unsigned gpio) -{ - uint32_t reg; - unsigned reg_offset; - - reg_offset = calc_input_reg(gpio); - reg = readl(IMX_IOMUXC_BASE + reg_offset); - if (reg & (0x1 << (gpio % 32))) - return 1; - - return 0; -} diff --git a/arch/arm/mach-mxs/mem-init.c b/arch/arm/mach-mxs/mem-init.c index 9773f94903..43165ac100 100644 --- a/arch/arm/mach-mxs/mem-init.c +++ b/arch/arm/mach-mxs/mem-init.c @@ -255,17 +255,6 @@ void mxs_mem_setup_cpu_and_hbus(void) mxs_early_delay(15000); } -void mxs_mem_setup_vdda(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)IMX_POWER_BASE; - - writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | - (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | - POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, - &power_regs->hw_power_vddactrl); -} - static void mx23_mem_setup_vddmem(void) { struct mxs_power_regs *power_regs = @@ -287,8 +276,6 @@ void mx23_mem_init(void) /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ mxs_mem_init_clock(33); - mxs_mem_setup_vdda(); - /* * Reset/ungate the EMI block. This is essential, otherwise the system * suffers from memory instability. This thing is mx23 specific and is @@ -340,8 +327,6 @@ void mx28_mem_init(void) /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ mxs_mem_init_clock(21); - mxs_mem_setup_vdda(); - /* Set DDR2 mode */ writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, IMX_IOMUXC_BASE + 0x1b80); diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c index abdd445b5d..2029b90acb 100644 --- a/arch/arm/mach-mxs/ocotp.c +++ b/arch/arm/mach-mxs/ocotp.c @@ -207,9 +207,18 @@ static int mxs_ocotp_probe(struct device_d *dev) return 0; } +static __maybe_unused struct of_device_id mxs_ocotp_compatible[] = { + { + .compatible = "fsl,ocotp", + }, { + /* sentinel */ + } +}; + static struct driver_d mxs_ocotp_driver = { .name = DRIVERNAME, .probe = mxs_ocotp_probe, + .of_compatible = DRV_OF_COMPAT(mxs_ocotp_compatible), }; static int mxs_ocotp_init(void) diff --git a/arch/arm/mach-mxs/power-init.c b/arch/arm/mach-mxs/power-init.c index 977c6e4e27..595b51c5ba 100644 --- a/arch/arm/mach-mxs/power-init.c +++ b/arch/arm/mach-mxs/power-init.c @@ -25,6 +25,56 @@ #include <mach/regs-lradc.h> /* + * has_battery - true when this board has a battery. + */ +static int has_battery; + +/* + * use_battery_input - true when this board is supplied from the + * battery input, but has a DC source instead of a real battery + */ +static int use_battery_input; + +/* + * use_5v_input - true when this board can use the 5V input + */ +static int use_5v_input; + +static void mxs_power_status(void) +{ + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)IMX_POWER_BASE; + static int linregofs[] = { 0, 1, -1, -2 }; + + uint32_t vddio = readl(&power_regs->hw_power_vddioctrl); + uint32_t vdda = readl(&power_regs->hw_power_vddactrl); + uint32_t vddd = readl(&power_regs->hw_power_vdddctrl); + uint32_t vddmem = readl(&power_regs->hw_power_vddmemctrl); + + printf("vddio: %dmV (BO -%dmV), Linreg enabled, Linreg offset: %d, FET %sabled\n", + (vddio & 0x1f) * 50 + 2800, + ((vddio >> 8) & 0x7) * 50, + linregofs[((vdda >> 12) & 0x3)], + (vddio & (1 << 16)) ? "dis" : "en"); + printf("vdda: %dmV (BO -%dmV), Linreg %sabled, Linreg offset: %d, FET %sabled\n", + (vdda & 0x1f) * 25 + 1500, + ((vdda >> 8) & 0x7) * 25, + (vdda & (1 << 17)) ? "en" : "dis", + linregofs[((vdda >> 12) & 0x3)], + (vdda & (1 << 16)) ? "dis" : "en"); + printf("vddd: %dmV (BO -%dmV), Linreg %sabled, Linreg offset: %d, FET %sabled\n", + (vddd & 0x1f) * 25 + 800, + ((vddd >> 8) & 0x7) * 25, + (vddd & (1 << 21)) ? "en" : "dis", + linregofs[((vdda >> 16) & 0x3)], + (vdda & (1 << 20)) ? "dis" : "en"); + printf("vddmem: %dmV (BO -%dmV), Linreg %sabled\n", + (vddmem & 0x1f) * 25 + 1100, + ((vddmem >> 5) & 0x7) * 25, + (vddmem & (1 << 8)) ? "en" : "dis"); +} + +/* * This delay function is intended to be used only in early stage of boot, where * clock are not set up yet. The timer used here is reset on every boot and * takes a few seconds to roll. The boot doesn't take that long, so to keep the @@ -299,36 +349,6 @@ static void mxs_src_power_init(void) } /** - * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator - * - * This function configures the necessary parameters for the 4P2 linear - * regulator to supply the DC-DC converter from 5V input. - */ -static void mxs_power_init_4p2_params(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)IMX_POWER_BASE; - - /* Setup 4P2 parameters */ - clrsetbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, - POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET)); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_HEADROOM_ADJ_MASK, - 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET); - - clrsetbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_DROPOUT_CTRL_MASK, - POWER_DCDC4P2_DROPOUT_CTRL_100MV | - POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); -} - -/** * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2 * @xfer: Select if the input shall be enabled or disabled * @@ -431,16 +451,82 @@ static void mxs_enable_4p2_dcdc_input(int xfer) } /** - * mxs_power_init_4p2_regulator() - Start the 4P2 regulator + * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source + * + * This function configures the DC-DC converter to be supplied from the 4P2 + * linear regulator. + */ +static void mxs_power_init_dcdc_4p2_source(void) +{ + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)IMX_POWER_BASE; + + if (!(readl(&power_regs->hw_power_dcdc4p2) & + POWER_DCDC4P2_ENABLE_DCDC)) { + hang(); + } + + mxs_enable_4p2_dcdc_input(1); + + if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + writel(POWER_5VCTRL_ENABLE_DCDC, + &power_regs->hw_power_5vctrl_clr); + charger_4p2_disable(); + } +} + +/** + * mxs_power_enable_4p2() - Power up the 4P2 regulator * - * This function enables the 4P2 regulator and switches the DC-DC converter - * to use the 4P2 input. + * This function drives the process of powering up the 4P2 linear regulator + * and switching the DC-DC converter input over to the 4P2 linear regulator. */ -static void mxs_power_init_4p2_regulator(void) +static void mxs_power_enable_4p2(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)IMX_POWER_BASE; - uint32_t tmp, tmp2; + uint32_t vdddctrl, vddactrl, vddioctrl; + uint32_t tmp, tmp2, dropout_ctrl; + + vdddctrl = readl(&power_regs->hw_power_vdddctrl); + vddactrl = readl(&power_regs->hw_power_vddactrl); + vddioctrl = readl(&power_regs->hw_power_vddioctrl); + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | + POWER_VDDDCTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | + POWER_VDDACTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); + + /* Setup 4P2 parameters */ + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, + POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET)); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_HEADROOM_ADJ_MASK, + 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET); + + if (has_battery || use_battery_input) + dropout_ctrl = POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL; + else + dropout_ctrl = POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2; + + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_DROPOUT_CTRL_MASK, + POWER_DCDC4P2_DROPOUT_CTRL_100MV | + dropout_ctrl); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); @@ -516,65 +602,6 @@ static void mxs_power_init_4p2_regulator(void) clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); -} - -/** - * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source - * - * This function configures the DC-DC converter to be supplied from the 4P2 - * linear regulator. - */ -static void mxs_power_init_dcdc_4p2_source(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)IMX_POWER_BASE; - - if (!(readl(&power_regs->hw_power_dcdc4p2) & - POWER_DCDC4P2_ENABLE_DCDC)) { - hang(); - } - - mxs_enable_4p2_dcdc_input(1); - - if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { - clrbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_ENABLE_DCDC); - writel(POWER_5VCTRL_ENABLE_DCDC, - &power_regs->hw_power_5vctrl_clr); - charger_4p2_disable(); - } -} - -/** - * mxs_power_enable_4p2() - Power up the 4P2 regulator - * - * This function drives the process of powering up the 4P2 linear regulator - * and switching the DC-DC converter input over to the 4P2 linear regulator. - */ -static void mxs_power_enable_4p2(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)IMX_POWER_BASE; - uint32_t vdddctrl, vddactrl, vddioctrl; - uint32_t tmp; - - vdddctrl = readl(&power_regs->hw_power_vdddctrl); - vddactrl = readl(&power_regs->hw_power_vddactrl); - vddioctrl = readl(&power_regs->hw_power_vddioctrl); - - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | - POWER_VDDDCTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddactrl, - POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | - POWER_VDDACTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); - - mxs_power_init_4p2_params(); - mxs_power_init_4p2_regulator(); /* Shutdown battery (none present) */ if (!mxs_is_batt_ready()) { @@ -1021,6 +1048,19 @@ static const struct mxs_vddx_cfg mxs_vddmem_cfg = { .bo_offset_offset = 0, }; +static const struct mxs_vddx_cfg mxs_vdda_cfg = { + .reg = &(((struct mxs_power_regs *)IMX_POWER_BASE)-> + hw_power_vddactrl), + .step_mV = 25, + .lowest_mV = 1500, + .powered_by_linreg = NULL, + .trg_mask = POWER_VDDACTRL_TRG_MASK, + .bo_irq = POWER_CTRL_VDDA_BO_IRQ, + .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO, + .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK, + .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET, +}; + /** * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail * @cfg: Configuration data of the DC-DC converter rail @@ -1143,11 +1183,16 @@ static void mx23_ungate_power(void) * This function calls all the power block initialization functions in * proper sequence to start the power block. */ -static void __mx23_power_init(int has_battery) +void mx23_power_init(int __has_battery, int __use_battery_input, + int __use_5v_input) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)IMX_POWER_BASE; + has_battery = __has_battery; + use_battery_input = __use_battery_input; + use_5v_input = __use_5v_input; + mx23_ungate_power(); mxs_power_clock2xtal(); @@ -1161,8 +1206,10 @@ static void __mx23_power_init(int has_battery) if (has_battery) mxs_power_configure_power_source(); - else + else if (use_battery_input) mxs_enable_battery_input(); + else if (use_5v_input) + mxs_boot_valid_5v(); mxs_power_clock2pll(); @@ -1177,8 +1224,9 @@ static void __mx23_power_init(int has_battery) mxs_enable_output_rail_protection(); mxs_power_set_vddx(&mx23_vddio_cfg, 3300, 3150); - mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000); + mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1325); mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700); + mxs_power_set_vddx(&mxs_vdda_cfg, 1800, 1650); writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | @@ -1190,27 +1238,23 @@ static void __mx23_power_init(int has_battery) mxs_early_delay(1000); } -void mx23_power_init(void) -{ - __mx23_power_init(1); -} - -void mx23_power_init_battery_input(void) -{ - __mx23_power_init(0); -} - /** * mx28_power_init() - The power block init main function * * This function calls all the power block initialization functions in * proper sequence to start the power block. */ -static void __mx28_power_init(int has_battery) +void mx28_power_init(int __has_battery, int __use_battery_input, + int __use_5v_input) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)IMX_POWER_BASE; + has_battery = __has_battery; + use_battery_input = __use_battery_input; + use_5v_input = __use_5v_input; + + mxs_power_status(); mxs_power_clock2xtal(); mxs_power_set_auto_restart(); mxs_power_set_linreg(); @@ -1222,8 +1266,10 @@ static void __mx28_power_init(int has_battery) if (has_battery) mxs_power_configure_power_source(); - else + else if (use_battery_input) mxs_enable_battery_input(); + else if (use_5v_input) + mxs_boot_valid_5v(); mxs_power_clock2pll(); @@ -1234,7 +1280,8 @@ static void __mx28_power_init(int has_battery) mxs_enable_output_rail_protection(); mxs_power_set_vddx(&mx28_vddio_cfg, 3300, 3150); - mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000); + mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1325); + mxs_power_set_vddx(&mxs_vdda_cfg, 1800, 1650); writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | @@ -1244,16 +1291,8 @@ static void __mx28_power_init(int has_battery) writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); mxs_early_delay(1000); -} -void mx28_power_init(void) -{ - __mx28_power_init(1); -} - -void mx28_power_init_battery_input(void) -{ - __mx28_power_init(0); + mxs_power_status(); } /** diff --git a/arch/arm/mach-mxs/soc-imx23.c b/arch/arm/mach-mxs/soc-imx23.c index b21986536f..339c57748f 100644 --- a/arch/arm/mach-mxs/soc-imx23.c +++ b/arch/arm/mach-mxs/soc-imx23.c @@ -38,8 +38,14 @@ EXPORT_SYMBOL(reset_cpu); static int imx23_devices_init(void) { + if (of_get_root_node()) + return 0; + add_generic_device("imx23-dma-apbh", 0, NULL, MXS_APBH_BASE, 0x2000, IORESOURCE_MEM, NULL); add_generic_device("imx23-clkctrl", 0, NULL, IMX_CCM_BASE, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx23-gpio", 0, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); + add_generic_device("imx23-gpio", 1, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); + add_generic_device("imx23-gpio", 2, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c index c7252f537e..b4ec38d912 100644 --- a/arch/arm/mach-mxs/soc-imx28.c +++ b/arch/arm/mach-mxs/soc-imx28.c @@ -56,8 +56,17 @@ postcore_initcall(imx28_init); static int imx28_devices_init(void) { + if (of_get_root_node()) + return 0; + add_generic_device("imx28-dma-apbh", 0, NULL, MXS_APBH_BASE, 0x2000, IORESOURCE_MEM, NULL); add_generic_device("imx28-clkctrl", 0, NULL, IMX_CCM_BASE, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx28-gpio", 0, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); + add_generic_device("imx28-gpio", 1, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); + add_generic_device("imx28-gpio", 2, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); + add_generic_device("imx28-gpio", 3, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); + add_generic_device("imx28-gpio", 4, NULL, IMX_IOMUXC_BASE, 0x2000, IORESOURCE_MEM, NULL); + add_generic_device("ocotp", 0, NULL, IMX_OCOTP_BASE, 0x2000, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index cdec1b7e5d..a45e01a702 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -4,6 +4,7 @@ config ARCH_TEXT_BASE hex default 0xa0000000 if MACH_MIOA701 default 0xa3f00000 if MACH_PCM027 + default 0x83f00000 if MACH_ZYLONITE # ---------------------------------------------------------- @@ -11,17 +12,48 @@ config ARCH_PXA2XX bool select CPU_XSCALE +config ARCH_PXA3XX + bool + select CPU_XSC3 + +config ARCH_PXA310 + bool + choice prompt "Intel/Marvell PXA Processor" +config ARCH_PXA25X + bool "PXA25x" + select ARCH_PXA2XX + config ARCH_PXA27X bool "PXA27x" select ARCH_PXA2XX +config ARCH_PXA3XX + bool "PXA3xx" + endchoice # ---------------------------------------------------------- +if ARCH_PXA25X + +choice + prompt "PXA25x Board Type" + bool + +config MACH_LUBBOCK + bool "Lubbock board" + select PWM + help + Say Y here if you are using a Lubbock board +endchoice + +endif + +# ---------------------------------------------------------- + if ARCH_PXA27X choice @@ -55,4 +87,26 @@ endif # ---------------------------------------------------------- +if ARCH_PXA3XX + +config MACH_ZYLONITE + bool + +choice + prompt "PXA3xx Board Type" + +config MACH_ZYLONITE_PXA310 + bool "Zylonite board based on a PXA310 pxa SoC" + help + Say Y here if you are using a Zylonite board, based + on a PXA31x SoC. + select ARCH_PXA310 + select MACH_ZYLONITE + +endchoice + +endif + +# ---------------------------------------------------------- + endif diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 6ddb6e58e5..0c3219807b 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -4,6 +4,7 @@ obj-y += gpio.o obj-y += devices.o obj-y += sleep.o -obj-$(CONFIG_ARCH_PXA2XX) += mfp-pxa2xx.o +obj-$(CONFIG_ARCH_PXA2XX) += mfp-pxa2xx.o pxa2xx.o +obj-$(CONFIG_ARCH_PXA25X) += speed-pxa25x.o obj-$(CONFIG_ARCH_PXA27X) += speed-pxa27x.o -obj-$(CONFIG_RESET_SOURCE) += reset_source.o +obj-$(CONFIG_ARCH_PXA3XX) += speed-pxa3xx.o mfp-pxa3xx.o pxa3xx.o diff --git a/arch/arm/mach-pxa/common.c b/arch/arm/mach-pxa/common.c index 0c114ed58e..2c27d812fc 100644 --- a/arch/arm/mach-pxa/common.c +++ b/arch/arm/mach-pxa/common.c @@ -27,12 +27,12 @@ #define OWER_WME (1 << 0) /* Watch-dog Match Enable */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ -extern void pxa_suspend(int mode); +extern void pxa_clear_reset_source(void); void reset_cpu(ulong addr) { /* Clear last reset source */ - RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR; + pxa_clear_reset_source(); /* Initialize the watchdog and let it fire */ writel(OWER_WME, OWER); @@ -41,14 +41,3 @@ void reset_cpu(ulong addr) while (1); } - -void __noreturn poweroff() -{ - shutdown_barebox(); - - /* Clear last reset source */ - RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR; - - pxa_suspend(PWRMODE_DEEPSLEEP); - unreachable(); -} diff --git a/arch/arm/mach-pxa/include/mach/clock.h b/arch/arm/mach-pxa/include/mach/clock.h index f86152f7af..40f6223cd9 100644 --- a/arch/arm/mach-pxa/include/mach/clock.h +++ b/arch/arm/mach-pxa/include/mach/clock.h @@ -14,6 +14,7 @@ unsigned long pxa_get_uartclk(void); unsigned long pxa_get_mmcclk(void); unsigned long pxa_get_lcdclk(void); +unsigned long pxa_get_nandclk(void); unsigned long pxa_get_pwmclk(void); #endif /* !__MACH_CLOCK_H */ diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index c5f40d7c08..902d11ddfc 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -13,7 +13,7 @@ #ifdef CONFIG_ARCH_PXA2XX #define cpu_is_pxa2xx() (1) #else -#define cpi_is_pxa2xx() (0) +#define cpu_is_pxa2xx() (0) #endif #ifdef CONFIG_ARCH_PXA25X @@ -28,6 +28,22 @@ #define cpu_is_pxa27x() (0) #endif +#ifdef CONFIG_ARCH_PXA3XX +#define cpu_is_pxa3xx() (1) +# ifdef CONFIG_ARCH_PXA320 +# define cpu_is_pxa320() (1) +# else +# define cpu_is_pxa320() (0) +# endif +# ifdef CONFIG_ARCH_PXA310 +# define cpu_is_pxa310() (1) +# else +# define cpu_is_pxa310() (0) +# endif +#else +#define cpu_is_pxa3xx() (0) +#endif + #ifdef __ASSEMBLY__ #define __REG(x) (x) #endif diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h new file mode 100644 index 0000000000..7bdd44db13 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h @@ -0,0 +1,25 @@ +#ifndef __ASM_ARCH_MFP_PXA3XX_H +#define __ASM_ARCH_MFP_PXA3XX_H + +#include <plat/mfp.h> + +#define MFPR_BASE (0x40e10000) + +/* NOTE: usage of these two functions is not recommended, + * use pxa3xx_mfp_config() instead. + */ +static inline unsigned long pxa3xx_mfp_read(int mfp) +{ + return mfp_read(mfp); +} + +static inline void pxa3xx_mfp_write(int mfp, unsigned long val) +{ + mfp_write(mfp, val); +} + +static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num) +{ + mfp_config(mfp_cfg, num); +} +#endif /* __ASM_ARCH_MFP_PXA3XX_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index c32d2ae704..9bcb5efb7f 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -24,8 +24,12 @@ # include <mach/pxa2xx-regs.h> #endif -#ifdef CONFIG_ARCH_PXA27X +#if defined(CONFIG_ARCH_PXA27X) # include <mach/pxa27x-regs.h> +#elif defined(CONFIG_ARCH_PXA3XX) +# include <mach/pxa3xx-regs.h> +#elif defined(CONFIG_ARCH_PXA25X) +# include <mach/pxa25x-regs.h> #else # error "unknown PXA soc type" #endif diff --git a/arch/arm/mach-pxa/include/mach/pxa25x-regs.h b/arch/arm/mach-pxa/include/mach/pxa25x-regs.h new file mode 100644 index 0000000000..a7f16bd418 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa25x-regs.h @@ -0,0 +1,6 @@ +#ifndef __MACH_PXA25X_REGS +#define __MACH_PXA25X_REGS + +/* this file intentionally left blank */ + +#endif /* !__MACH_PXA25X_REGS */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index b43648e3c4..dc7704eda2 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -53,6 +53,7 @@ #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ +#define FLYCNFG __REG(0x48000020) /* Flycnfg Register */ #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h new file mode 100644 index 0000000000..373711d92f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -0,0 +1,224 @@ +/* + * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h + * + * PXA3xx specific register definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_PXA3XX_REGS +#define __MACH_PXA3XX_REGS + +#include <mach/hardware.h> + +/* + * Oscillator Configuration Register (OSCC) + */ +#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ + +#define OSCC_PEN (1 << 11) /* 13MHz POUT */ + + +/* + * Service Power Management Unit (MPMU) + */ +#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ +#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ +#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ +#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ +#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ +#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ +#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ +#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ +#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ +#define PCMD(x) __REG(0x40F50110 + ((x) << 2)) + +/* + * Slave Power Management Unit + */ +#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ +#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ +#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ +#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ +#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ +#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ +#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ +#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ +#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ +#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ +#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ +#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ +#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ +#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ + +/* + * Application Subsystem Configuration bits. + */ +#define ASCR_RDH (1 << 31) +#define ASCR_D1S (1 << 2) +#define ASCR_D2S (1 << 1) +#define ASCR_D3S (1 << 0) + +/* + * Application Reset Status bits. + */ +#define ARSR_GPR (1 << 3) +#define ARSR_LPMR (1 << 2) +#define ARSR_WDT (1 << 1) +#define ARSR_HWR (1 << 0) + +/* + * Application Subsystem Wake-Up bits. + */ +#define ADXER_WRTC (1 << 31) /* RTC */ +#define ADXER_WOST (1 << 30) /* OS Timer */ +#define ADXER_WTSI (1 << 29) /* Touchscreen */ +#define ADXER_WUSBH (1 << 28) /* USB host */ +#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ +#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ +#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ +#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ +#define ADXER_WKP (1 << 21) /* Keypad */ +#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ +#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ +#define ADXER_WOTG (1 << 16) /* USBOTG input */ +#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ +#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ +#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ +#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ +#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ +#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ +#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ +#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ +#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ +#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ +#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ +#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ +#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ +#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ +#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ +#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ + +/* + * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. + */ +#define ADXR_L2 (1 << 8) +#define ADXR_R5 (1 << 5) +#define ADXR_R4 (1 << 4) +#define ADXR_R3 (1 << 3) +#define ADXR_R2 (1 << 2) +#define ADXR_R1 (1 << 1) +#define ADXR_R0 (1 << 0) + +/* + * Values for PWRMODE CP15 register + */ +#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ +#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ +#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ +#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ +#define PXA3xx_PM_S0D0C1 0x01 + +/* + * Application Subsystem Clock + */ +#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ +#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ +#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ +#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ +#define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define CKENC __REG(0x41340024) /* C Clock Enable Register */ +#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ + +#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ +#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ +#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ +#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ +#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ + +#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ +#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ +#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ +#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ +#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ +#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ +#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ + +#define ACCR_SMCFS(x) (((x) & 0x7) << 23) +#define ACCR_SFLFS(x) (((x) & 0x3) << 18) +#define ACCR_XSPCLK(x) (((x) & 0x3) << 16) +#define ACCR_HSS(x) (((x) & 0x3) << 14) +#define ACCR_DMCFS(x) (((x) & 0x3) << 12) +#define ACCR_XN(x) (((x) & 0x7) << 8) +#define ACCR_XL(x) ((x) & 0x1f) + +/* + * Clock Enable Bit + */ +#define CKEN_LCD 1 /* < LCD Clock Enable */ +#define CKEN_USBH 2 /* < USB host clock enable */ +#define CKEN_CAMERA 3 /* < Camera interface clock enable */ +#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ +#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ +#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ +#define CKEN_SMC 9 /* < Static Memory Controller clock enable */ +#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ +#define CKEN_BOOT 11 /* < Boot rom clock enable */ +#define CKEN_MMC1 12 /* < MMC1 Clock enable */ +#define CKEN_MMC2 13 /* < MMC2 clock enable */ +#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ +#define CKEN_CIR 15 /* < Consumer IR Clock Enable */ +#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ +#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ +#define CKEN_TPM 19 /* < TPM clock enable */ +#define CKEN_UDC 20 /* < UDC clock enable */ +#define CKEN_BTUART 21 /* < BTUART clock enable */ +#define CKEN_FFUART 22 /* < FFUART clock enable */ +#define CKEN_STUART 23 /* < STUART clock enable */ +#define CKEN_AC97 24 /* < AC97 clock enable */ +#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ +#define CKEN_SSP1 26 /* < SSP1 clock enable */ +#define CKEN_SSP2 27 /* < SSP2 clock enable */ +#define CKEN_SSP3 28 /* < SSP3 clock enable */ +#define CKEN_SSP4 29 /* < SSP4 clock enable */ +#define CKEN_MSL0 30 /* < MSL0 clock enable */ +#define CKEN_PWM0 32 /* < PWM[0] clock enable */ +#define CKEN_PWM1 33 /* < PWM[1] clock enable */ +#define CKEN_I2C 36 /* < I2C clock enable */ +#define CKEN_INTC 38 /* < Interrupt controller clock enable */ +#define CKEN_GPIO 39 /* < GPIO clock enable */ +#define CKEN_1WIRE 40 /* < 1-wire clock enable */ +#define CKEN_HSIO2 41 /* < HSIO2 clock enable */ +#define CKEN_MINI_IM 48 /* < Mini-IM */ +#define CKEN_MINI_LCD 49 /* < Mini LCD */ + +#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ +#define CKEN_MVED 43 /* < MVED clock enable */ + +/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ +#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ +#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ + +/* + * Static Memory Controller + */ +#define MSC0 __REG(0x4a000008) /* Static Memory Control 0 */ +#define MSC1 __REG(0x4a00000c) /* Static Memory Control 1 */ +#define MECR __REG(0x4a000014) /* Expansion Memory Configuration */ +#define SXCNFG __REG(0x4a00001c) /* Synchronous Static Memory Control */ +#define MCMEM0 __REG(0x4a000028) /* Expansion Memory Timing */ +#define MCATT0 __REG(0x4a000030) /* Expansion Memory Timing */ +#define MCIO0 __REG(0x4a000038) /* Expansion Memory Timing */ +#define MEMCLKCFG __REG(0x4a000068) /* Clock configuration */ +#define CSADRCFG0 __REG(0x4a000080) /* CS0 address configuration */ +#define CSADRCFG1 __REG(0x4a000084) /* CS1 address configuration */ +#define CSADRCFG2 __REG(0x4a000088) /* CS2 address configuration */ +#define CSADRCFG3 __REG(0x4a00008c) /* CS3 address configuration */ +#define CSADRCFGP __REG(0x4a000090) /* CSP address configuration */ +#define CSMSADRCFG __REG(0x4a0000a0) /* CSP address configuration */ + +#endif /* !__MACH_PXA3XX_REGS */ diff --git a/arch/arm/mach-pxa/include/plat/mfp.h b/arch/arm/mach-pxa/include/plat/mfp.h index 755b02062b..aedb956cd3 100644 --- a/arch/arm/mach-pxa/include/plat/mfp.h +++ b/arch/arm/mach-pxa/include/plat/mfp.h @@ -416,7 +416,7 @@ typedef unsigned long mfp_cfg_t; ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) -#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP) +#if defined(CONFIG_ARCH_PXA3XX) /* * each MFP pin will have a MFPR register, since the offset of the * register varies between processors, the processor specific code @@ -449,7 +449,7 @@ struct mfp_addr_map { #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } -void __init mfp_init_base(unsigned long mfpr_base); +void __init mfp_init_base(void __iomem *mfpr_base); void __init mfp_init_addr(struct mfp_addr_map *map); /* @@ -463,6 +463,7 @@ void mfp_write(int mfp, unsigned long mfpr_val); void mfp_config(unsigned long *mfp_cfgs, int num); void mfp_config_run(void); void mfp_config_lpm(void); -#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */ +void mfp_init(void); +#endif /* CONFIG_ARCH_PXA3XX */ #endif /* __ASM_PLAT_MFP_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 4f393c4d47..2456cef936 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -169,8 +169,10 @@ static int __init pxa2xx_mfp_init(void) if (!cpu_is_pxa2xx()) return 0; - if (cpu_is_pxa25x()) + if (cpu_is_pxa25x()) { + pxa_init_gpio(0, 84); pxa25x_mfp_init(); + } if (cpu_is_pxa27x()) { pxa_init_gpio(2, 120); diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c new file mode 100644 index 0000000000..df4922453d --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c @@ -0,0 +1,338 @@ +/* + * linux/arch/arm/plat-pxa/mfp.c + * + * Multi-Function Pin Support + * + * Copyright (C) 2007 Marvell Internation Ltd. + * + * 2007-08-21: eric miao <eric.miao@marvell.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <mach/hardware.h> +#include <mach/mfp-pxa3xx.h> +#include <plat/mfp.h> + +#define MFPR_SIZE (PAGE_SIZE) + +/* MFPR register bit definitions */ +#define MFPR_PULL_SEL (0x1 << 15) +#define MFPR_PULLUP_EN (0x1 << 14) +#define MFPR_PULLDOWN_EN (0x1 << 13) +#define MFPR_SLEEP_SEL (0x1 << 9) +#define MFPR_SLEEP_OE_N (0x1 << 7) +#define MFPR_EDGE_CLEAR (0x1 << 6) +#define MFPR_EDGE_FALL_EN (0x1 << 5) +#define MFPR_EDGE_RISE_EN (0x1 << 4) + +#define MFPR_SLEEP_DATA(x) ((x) << 8) +#define MFPR_DRIVE(x) (((x) & 0x7) << 10) +#define MFPR_AF_SEL(x) (((x) & 0x7) << 0) + +#define MFPR_EDGE_NONE (0) +#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) +#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) +#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) + +/* + * Table that determines the low power modes outputs, with actual settings + * used in parentheses for don't-care values. Except for the float output, + * the configured driven and pulled levels match, so if there is a need for + * non-LPM pulled output, the same configuration could probably be used. + * + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel + * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) + * + * Input 0 X(0) X(0) X(0) 0 + * Drive 0 0 0 0 X(1) 0 + * Drive 1 0 1 X(1) 0 0 + * Pull hi (1) 1 X(1) 1 0 0 + * Pull lo (0) 1 X(0) 0 1 0 + * Z (float) 1 X(0) 0 0 0 + */ +#define MFPR_LPM_INPUT (0) +#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) +#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) +#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) +#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) +#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) +#define MFPR_LPM_MASK (0xe080) + +/* + * The pullup and pulldown state of the MFP pin at run mode is by default + * determined by the selected alternate function. In case that some buggy + * devices need to override this default behavior, the definitions below + * indicates the setting of corresponding MFPR bits + * + * Definition pull_sel pullup_en pulldown_en + * MFPR_PULL_NONE 0 0 0 + * MFPR_PULL_LOW 1 0 1 + * MFPR_PULL_HIGH 1 1 0 + * MFPR_PULL_BOTH 1 1 1 + * MFPR_PULL_FLOAT 1 0 0 + */ +#define MFPR_PULL_NONE (0) +#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) +#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) +#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) +#define MFPR_PULL_FLOAT (MFPR_PULL_SEL) + +/* mfp_spin_lock is used to ensure that MFP register configuration + * (most likely a read-modify-write operation) is atomic, and that + * mfp_table[] is consistent + */ +static void __iomem *mfpr_mmio_base; + +struct mfp_pin { + unsigned long config; /* -1 for not configured */ + unsigned long mfpr_off; /* MFPRxx Register offset */ + unsigned long mfpr_run; /* Run-Mode Register Value */ + unsigned long mfpr_lpm; /* Low Power Mode Register Value */ +}; + +static struct mfp_pin mfp_table[MFP_PIN_MAX]; + +/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */ +static const unsigned long mfpr_lpm[] = { + MFPR_LPM_INPUT, + MFPR_LPM_DRIVE_LOW, + MFPR_LPM_DRIVE_HIGH, + MFPR_LPM_PULL_LOW, + MFPR_LPM_PULL_HIGH, + MFPR_LPM_FLOAT, + MFPR_LPM_INPUT, +}; + +/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ +static const unsigned long mfpr_pull[] = { + MFPR_PULL_NONE, + MFPR_PULL_LOW, + MFPR_PULL_HIGH, + MFPR_PULL_BOTH, + MFPR_PULL_FLOAT, +}; + +/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ +static const unsigned long mfpr_edge[] = { + MFPR_EDGE_NONE, + MFPR_EDGE_RISE, + MFPR_EDGE_FALL, + MFPR_EDGE_BOTH, +}; + +#define mfpr_readl(off) \ + __raw_readl(mfpr_mmio_base + (off)) + +#define mfpr_writel(off, val) \ + __raw_writel(val, mfpr_mmio_base + (off)) + +#define mfp_configured(p) ((p)->config != -1) + +/* + * perform a read-back of any valid MFPR register to make sure the + * previous writings are finished + */ +static unsigned long mfpr_off_readback; +#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + mfpr_off_readback) + +static inline void __mfp_config_run(struct mfp_pin *p) +{ + if (mfp_configured(p)) + mfpr_writel(p->mfpr_off, p->mfpr_run); +} + +static inline void __mfp_config_lpm(struct mfp_pin *p) +{ + if (mfp_configured(p)) { + unsigned long mfpr_clr = + (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR; + + if (mfpr_clr != p->mfpr_run) + mfpr_writel(p->mfpr_off, mfpr_clr); + if (p->mfpr_lpm != mfpr_clr) + mfpr_writel(p->mfpr_off, p->mfpr_lpm); + } +} + +void mfp_config(unsigned long *mfp_cfgs, int num) +{ + int i; + + for (i = 0; i < num; i++, mfp_cfgs++) { + unsigned long tmp, c = *mfp_cfgs; + struct mfp_pin *p; + int pin, af, drv, lpm, edge, pull; + + pin = MFP_PIN(c); + BUG_ON(pin >= MFP_PIN_MAX); + p = &mfp_table[pin]; + + af = MFP_AF(c); + drv = MFP_DS(c); + lpm = MFP_LPM_STATE(c); + edge = MFP_LPM_EDGE(c); + pull = MFP_PULL(c); + + /* run-mode pull settings will conflict with MFPR bits of + * low power mode state, calculate mfpr_run and mfpr_lpm + * individually if pull != MFP_PULL_NONE + */ + tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv); + + if (likely(pull == MFP_PULL_NONE)) { + p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; + p->mfpr_lpm = p->mfpr_run; + } else { + p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; + p->mfpr_run = tmp | mfpr_pull[pull]; + } + + p->config = c; __mfp_config_run(p); + } + + mfpr_sync(); +} + +unsigned long mfp_read(int mfp) +{ + unsigned long val; + + BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX); + + val = mfpr_readl(mfp_table[mfp].mfpr_off); + return val; +} + +void mfp_write(int mfp, unsigned long val) +{ + BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX); + + mfpr_writel(mfp_table[mfp].mfpr_off, val); + mfpr_sync(); +} + +void __init mfp_init_base(void __iomem *mfpr_base) +{ + int i; + + /* initialize the table with default - unconfigured */ + for (i = 0; i < ARRAY_SIZE(mfp_table); i++) + mfp_table[i].config = -1; + + mfpr_mmio_base = mfpr_base; +} + +void __init mfp_init_addr(struct mfp_addr_map *map) +{ + struct mfp_addr_map *p; + unsigned long offset; + int i; + + /* mfp offset for readback */ + mfpr_off_readback = map[0].offset; + + for (p = map; p->start != MFP_PIN_INVALID; p++) { + offset = p->offset; + i = p->start; + + do { + mfp_table[i].mfpr_off = offset; + mfp_table[i].mfpr_run = 0; + mfp_table[i].mfpr_lpm = 0; + offset += 4; i++; + } while ((i <= p->end) && (p->end != -1)); + } +} + +void mfp_config_lpm(void) +{ + struct mfp_pin *p = &mfp_table[0]; + int pin; + + for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) + __mfp_config_lpm(p); +} + +void mfp_config_run(void) +{ + struct mfp_pin *p = &mfp_table[0]; + int pin; + + for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) + __mfp_config_run(p); +} + +static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = { + + MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), + MFP_ADDR_X(GPIO3, GPIO26, 0x027c), + MFP_ADDR_X(GPIO27, GPIO98, 0x0400), + MFP_ADDR_X(GPIO99, GPIO127, 0x0600), + MFP_ADDR_X(GPIO0_2, GPIO1_2, 0x0674), + MFP_ADDR_X(GPIO2_2, GPIO6_2, 0x02dc), + + MFP_ADDR(nBE0, 0x0204), + MFP_ADDR(nBE1, 0x0208), + + MFP_ADDR(nLUA, 0x0244), + MFP_ADDR(nLLA, 0x0254), + + MFP_ADDR(DF_CLE_nOE, 0x0240), + MFP_ADDR(DF_nRE_nOE, 0x0200), + MFP_ADDR(DF_ALE_nWE, 0x020C), + MFP_ADDR(DF_INT_RnB, 0x00C8), + MFP_ADDR(DF_nCS0, 0x0248), + MFP_ADDR(DF_nCS1, 0x0278), + MFP_ADDR(DF_nWE, 0x00CC), + + MFP_ADDR(DF_ADDR0, 0x0210), + MFP_ADDR(DF_ADDR1, 0x0214), + MFP_ADDR(DF_ADDR2, 0x0218), + MFP_ADDR(DF_ADDR3, 0x021C), + + MFP_ADDR(DF_IO0, 0x0220), + MFP_ADDR(DF_IO1, 0x0228), + MFP_ADDR(DF_IO2, 0x0230), + MFP_ADDR(DF_IO3, 0x0238), + MFP_ADDR(DF_IO4, 0x0258), + MFP_ADDR(DF_IO5, 0x0260), + MFP_ADDR(DF_IO6, 0x0268), + MFP_ADDR(DF_IO7, 0x0270), + MFP_ADDR(DF_IO8, 0x0224), + MFP_ADDR(DF_IO9, 0x022C), + MFP_ADDR(DF_IO10, 0x0234), + MFP_ADDR(DF_IO11, 0x023C), + MFP_ADDR(DF_IO12, 0x025C), + MFP_ADDR(DF_IO13, 0x0264), + MFP_ADDR(DF_IO14, 0x026C), + MFP_ADDR(DF_IO15, 0x0274), + + MFP_ADDR_END, +}; + +/* override pxa300 MFP register addresses */ +static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = { + MFP_ADDR_X(GPIO30, GPIO98, 0x0418), + MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), + + MFP_ADDR(ULPI_STP, 0x040C), + MFP_ADDR(ULPI_NXT, 0x0410), + MFP_ADDR(ULPI_DIR, 0x0414), + + MFP_ADDR_END, +}; + +void mfp_init(void) +{ + mfp_init_base((void __iomem *)MFPR_BASE); + mfp_init_addr(pxa300_mfp_addr_map); + if (cpu_is_pxa310()) + mfp_init_addr(pxa310_mfp_addr_map); +} diff --git a/arch/arm/mach-pxa/reset_source.c b/arch/arm/mach-pxa/pxa2xx.c index a90584b1a6..b712b388c8 100644 --- a/arch/arm/mach-pxa/reset_source.c +++ b/arch/arm/mach-pxa/pxa2xx.c @@ -15,8 +15,11 @@ #include <common.h> #include <init.h> #include <reset_source.h> +#include <mach/hardware.h> #include <mach/pxa-regs.h> +extern void pxa_suspend(int mode); + static int pxa_detect_reset_source(void) { u32 reg = RCSR; @@ -38,4 +41,19 @@ static int pxa_detect_reset_source(void) return 0; } +void pxa_clear_reset_source(void) +{ + RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR; +} + device_initcall(pxa_detect_reset_source); + +void __noreturn poweroff(void) +{ + shutdown_barebox(); + + /* Clear last reset source */ + pxa_clear_reset_source(); + pxa_suspend(PWRMODE_DEEPSLEEP); + unreachable(); +} diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c new file mode 100644 index 0000000000..86ca63b160 --- /dev/null +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <reset_source.h> +#include <mach/hardware.h> +#include <mach/pxa-regs.h> + +extern void pxa3xx_suspend(int mode); + +static int pxa_detect_reset_source(void) +{ + u32 reg = ARSR; + + /* + * Order is important, as many bits can be set together + */ + if (reg & ARSR_GPR) + reset_source_set(RESET_RST); + else if (reg & ARSR_WDT) + reset_source_set(RESET_WDG); + else if (reg & ARSR_HWR) + reset_source_set(RESET_POR); + else if (reg & ARSR_LPMR) + reset_source_set(RESET_WKE); + else + reset_source_set(RESET_UKWN); + + return 0; +} + +void pxa_clear_reset_source(void) +{ + ARSR = ARSR_GPR | ARSR_LPMR | ARSR_WDT | ARSR_HWR; +} + +device_initcall(pxa_detect_reset_source); + +void __noreturn poweroff(void) +{ + shutdown_barebox(); + + /* Clear last reset source */ + pxa_clear_reset_source(); + pxa3xx_suspend(PXA3xx_PM_S3D4C4); + unreachable(); +} diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 881033da21..1c678158c9 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -21,7 +21,7 @@ #define UNCACHED_PHYS_0 0 .text -#ifdef CONFIG_ARCH_PXA27X +#if (defined CONFIG_ARCH_PXA27X || defined CONFIG_ARCH_PXA25X) /* * pxa27x_finish_suspend() * @@ -79,3 +79,10 @@ pxa_cpu_do_suspend: @ enter sleep mode mcr p14, 0, r1, c7, c0, 0 @ PWRMODE 20: b 20b @ loop waiting for sleep + + /* + * pxa3xx_finish_suspend() - forces CPU into sleep state + */ +ENTRY(pxa3xx_suspend) + mcr p14, 0, r0, c7, c0, 0 @ enter sleep +20: b 20b @ waiting for sleep diff --git a/arch/arm/mach-pxa/speed-pxa25x.c b/arch/arm/mach-pxa/speed-pxa25x.c new file mode 100644 index 0000000000..69143431e4 --- /dev/null +++ b/arch/arm/mach-pxa/speed-pxa25x.c @@ -0,0 +1,54 @@ +/* + * clock.h - implementation of the PXA clock functions + * + * Copyright (C) 2014 Robert Jarzmik <robert.jarzmik@free.fr> + * + * This file is released under the GPLv2 + * + */ + +#include <common.h> +#include <mach/clock.h> +#include <mach/pxa-regs.h> + +/* Crystal clock: 13MHz */ +#define BASE_CLK 13000000 + +unsigned long pxa_get_uartclk(void) +{ + return 14857000; +} + +unsigned long pxa_get_mmcclk(void) +{ + return 19500000; +} + +/* + * Return the current LCD clock frequency in units of 10kHz as + */ +static unsigned int pxa_get_lcdclk_10khz(void) +{ + unsigned long ccsr; + unsigned int l, L, k, K; + + ccsr = CCSR; + + l = ccsr & 0x1f; + k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; + + L = l * BASE_CLK; + K = L / k; + + return (K / 10000); +} + +unsigned long pxa_get_lcdclk(void) +{ + return pxa_get_lcdclk_10khz() * 10000; +} + +unsigned long pxa_get_pwmclk(void) +{ + return BASE_CLK; +} diff --git a/arch/arm/mach-pxa/speed-pxa3xx.c b/arch/arm/mach-pxa/speed-pxa3xx.c new file mode 100644 index 0000000000..6a08ea78f0 --- /dev/null +++ b/arch/arm/mach-pxa/speed-pxa3xx.c @@ -0,0 +1,33 @@ +/* + * clock.h - implementation of the PXA clock functions + * + * Copyright (C) 2014 by Robert Jarzmik <robert.jarzmik@free.fr> + * + * This file is released under the GPLv2 + * + */ + +#include <common.h> +#include <mach/clock.h> +#include <mach/pxa-regs.h> + +/* Crystal clock: 13MHz */ +#define BASE_CLK 13000000 + +unsigned long pxa_get_uartclk(void) +{ + return 14857000; +} + +unsigned long pxa_get_pwmclk(void) +{ + return BASE_CLK; +} + +unsigned long pxa_get_nandclk(void) +{ + if (cpu_is_pxa320()) + return 104000000; + else + return 156000000; +} diff --git a/arch/blackfin/boards/ipe337/barebox.lds.S b/arch/blackfin/boards/ipe337/barebox.lds.S index 21a91eeb0a..9bb7cc4953 100644 --- a/arch/blackfin/boards/ipe337/barebox.lds.S +++ b/arch/blackfin/boards/ipe337/barebox.lds.S @@ -68,9 +68,9 @@ SECTIONS .barebox_cmd : { BAREBOX_CMDS } ___barebox_cmd_end = .; - __barebox_magicvar_start = .; + ___barebox_magicvar_start = .; .barebox_magicvar : { BAREBOX_MAGICVARS } - __barebox_magicvar_end = .; + ___barebox_magicvar_end = .; ___barebox_initcalls_start = .; .barebox_initcalls : { INITCALLS } diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h index 0f547271f8..f7d6d47a04 100644 --- a/arch/blackfin/include/asm/linkage.h +++ b/arch/blackfin/include/asm/linkage.h @@ -1,54 +1,13 @@ /* - * barebox - linkage.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright 2004-2009 Analog Devices Inc. * + * Licensed under the GPL-2 or later. */ -#ifndef _LINUX_LINKAGE_H -#define _LINUX_LINKAGE_H - -#ifdef __cplusplus -#define CPP_ASMLINKAGE extern "C" -#else -#define CPP_ASMLINKAGE -#endif - -#define asmlinkage CPP_ASMLINKAGE +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H -#define SYMBOL_NAME_STR(X) #X -#define SYMBOL_NAME(X) X -#ifdef __STDC__ -#define SYMBOL_NAME_LABEL(X) X##: -#else -#define SYMBOL_NAME_LABEL(X) X: -#endif - -#define __ALIGN .align 4 -#define __ALIGN_STR ".align 4" - -#ifdef __ASSEMBLY__ - -#define ALIGN __ALIGN -#define ALIGN_STR __ALIGN_STR - -#define ENTRY(name) \ - .globl SYMBOL_NAME(name); \ - ALIGN; \ - SYMBOL_NAME_LABEL(name) -#endif +#define __ALIGN .align 4 +#define __ALIGN_STR ".align 4" #endif diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index 581fd42397..f11dd4ebf1 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h @@ -21,7 +21,7 @@ #ifndef _BLACKFIN_SYSTEM_H #define _BLACKFIN_SYSTEM_H -#include <asm/linkage.h> +#include <linux/linkage.h> #include <asm/blackfin.h> #include <asm/segment.h> #include <asm/entry.h> diff --git a/arch/blackfin/lib/flush.S b/arch/blackfin/lib/flush.S index 62aa496986..4ee5d870ac 100644 --- a/arch/blackfin/lib/flush.S +++ b/arch/blackfin/lib/flush.S @@ -8,7 +8,7 @@ */ #define ASSEMBLY -#include <asm/linkage.h> +#include <linux/linkage.h> #include <asm/cplb.h> #include <asm/blackfin.h> diff --git a/arch/efi/Makefile b/arch/efi/Makefile index 85cb655615..b078bd0e35 100644 --- a/arch/efi/Makefile +++ b/arch/efi/Makefile @@ -1,3 +1,5 @@ +KBUILD_DEFCONFIG := efi_defconfig + CFLAGS += -fpic -fshort-wchar -mno-sse -mno-mmx ifeq ($(CONFIG_X86_32),y) diff --git a/arch/nios2/cpu/.gitignore b/arch/nios2/cpu/.gitignore new file mode 100644 index 0000000000..d1165788c9 --- /dev/null +++ b/arch/nios2/cpu/.gitignore @@ -0,0 +1 @@ +barebox.lds diff --git a/arch/ppc/lib/crtsavres.S b/arch/ppc/lib/crtsavres.S index a764ae4ce6..b0fbbfc997 100644 --- a/arch/ppc/lib/crtsavres.S +++ b/arch/ppc/lib/crtsavres.S @@ -33,13 +33,11 @@ * the executable file might be covered by the GNU General Public License. */ +#include <linux/stringify.h> #include <asm/ppc_asm.tmpl> #define N_FUN 36 -#define __stringify_1(x...) #x -#define __stringify(x...) __stringify_1(x) - #define _GLOBAL(n) \ .text; \ .stabs __stringify(n:F-1),N_FUN,0,0,n;\ diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile index ed5d3a3dab..e3fb039554 100644 --- a/arch/sandbox/Makefile +++ b/arch/sandbox/Makefile @@ -1,3 +1,4 @@ +KBUILD_DEFCONFIG := sandbox_defconfig CPPFLAGS += -D__SANDBOX__ -fno-strict-aliasing diff --git a/arch/sandbox/os/Makefile b/arch/sandbox/os/Makefile index 2e65be5eed..537f848e06 100644 --- a/arch/sandbox/os/Makefile +++ b/arch/sandbox/os/Makefile @@ -8,6 +8,8 @@ else CPPFLAGS = $(patsubst %,-I$(srctree)/%include,$(machdirs)) endif +CPPFLAGS += -DCONFIG_MALLOC_SIZE=$(CONFIG_MALLOC_SIZE) + CFLAGS := -Wall NOSTDINC_FLAGS := diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c index 412393811e..0854fb5d80 100644 --- a/arch/sandbox/os/common.c +++ b/arch/sandbox/os/common.c @@ -285,7 +285,7 @@ int main(int argc, char *argv[]) { void *ram; int opt, ret, fd; - int malloc_size = 8 * 1024 * 1024; + int malloc_size = CONFIG_MALLOC_SIZE; char str[6]; int fdno = 0, envno = 0, option_index = 0; diff --git a/arch/x86/Makefile b/arch/x86/Makefile index a78fa22ac6..da17d70bdc 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -1,3 +1,5 @@ +KBUILD_DEFCONFIG := generic_defconfig + CPPFLAGS += -D__X86__ -fno-strict-aliasing board-y := x86_generic |