diff options
Diffstat (limited to 'arch')
100 files changed, 3504 insertions, 1349 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2b5446baf8..f567531d1b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -26,7 +26,7 @@ choice config ARCH_AT91 bool "Atmel AT91" - select GENERIC_GPIO + select GPIOLIB select CLKDEV_LOOKUP select HAS_DEBUG_LL select HAVE_MACH_ARM_HEAD diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 3bd645fbfa..478b0d8bc5 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -150,6 +150,7 @@ board-$(CONFIG_MACH_TINY210) := friendlyarm-tiny210 board-$(CONFIG_MACH_SABRELITE) := freescale-mx6-sabrelite board-$(CONFIG_MACH_TX53) := karo-tx53 board-$(CONFIG_MACH_GUF_VINCELL) := guf-vincell +board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) := efika-mx-smartbook machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c index f5d242ff94..a40d3b9036 100644 --- a/arch/arm/boards/at91rm9200ek/init.c +++ b/arch/arm/boards/at91rm9200ek/init.c @@ -47,6 +47,7 @@ mem_initcall(at91rm9200ek_mem_init); static struct at91_usbh_data ek_usbh_data = { .ports = 2, + .vbus_pin = { -EINVAL, -EINVAL }, }; #ifdef CONFIG_LED_GPIO diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c index e9bfee6f0d..7bd02793b1 100644 --- a/arch/arm/boards/at91sam9260ek/init.c +++ b/arch/arm/boards/at91sam9260ek/init.c @@ -31,7 +31,6 @@ #include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h> @@ -59,7 +58,7 @@ static void ek_set_board_type(void) static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, -/* .det_pin = ... not connected */ + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, #if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) @@ -122,7 +121,7 @@ static void ek_add_device_nand(void) smc->mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, smc); + sam9_smc_configure(0, 3, smc); at91_add_device_nand(&nand_pdata); } @@ -135,7 +134,7 @@ static struct at91_ether_platform_data macb_pdata = { static void at91sam9260ek_phy_reset(void) { unsigned long rstc; - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + at91_pmc_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); at91_set_gpio_input(AT91_PIN_PA14, 0); at91_set_gpio_input(AT91_PIN_PA15, 0); @@ -187,6 +186,7 @@ static void ek_usb_add_device_mci(void) {} */ static struct at91_usbh_data __initdata ek_usbh_data = { .ports = 2, + .vbus_pin = { -EINVAL, -EINVAL }, }; /* diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c index 8842cfe144..7c95435c8d 100644 --- a/arch/arm/boards/at91sam9261ek/init.c +++ b/arch/arm/boards/at91sam9261ek/init.c @@ -33,7 +33,6 @@ #include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <dm9000.h> #include <gpio_keys.h> #include <readkey.h> @@ -42,7 +41,7 @@ static struct atmel_nand_data nand_pdata = { .ale = 22, .cle = 21, -/* .det_pin = ... not connected */ + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC15, .enable_pin = AT91_PIN_PC14, #if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) @@ -80,7 +79,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&nand_pdata); } @@ -118,7 +117,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = { static void __init ek_add_device_dm9000(void) { /* Configure chip-select 2 (DM9000) */ - sam9_smc_configure(2, &dm9000_smc_config); + sam9_smc_configure(0, 2, &dm9000_smc_config); /* Configure Reset signal as output */ at91_set_gpio_output(AT91_PIN_PC10, 0); diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c index 45a30fd537..a86c0fd510 100644 --- a/arch/arm/boards/at91sam9263ek/init.c +++ b/arch/arm/boards/at91sam9263ek/init.c @@ -35,12 +35,11 @@ #include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, -/* .det_pin = ... not connected */ + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PA22, .enable_pin = AT91_PIN_PD15, #if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) @@ -78,7 +77,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&nand_pdata); } @@ -176,7 +175,7 @@ static int at91sam9263ek_devices_init(void) * 0 - disable */ at91_set_gpio_output(AT91_PIN_PB27, 1); - at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ + gpio_set_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ ek_add_device_nand(); at91_add_device_eth(0, &macb_pdata); diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c index 4b6d5c4014..d77b2bfb09 100644 --- a/arch/arm/boards/at91sam9m10g45ek/init.c +++ b/arch/arm/boards/at91sam9m10g45ek/init.c @@ -36,7 +36,6 @@ #include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio_keys.h> #include <readkey.h> @@ -63,7 +62,7 @@ static void ek_set_board_revision(void) static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, -/* .det_pin = ... not connected */ + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC8, .enable_pin = AT91_PIN_PC14, #if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) @@ -101,7 +100,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&nand_pdata); } diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c index 3d4ab5b0cc..310f41898a 100644 --- a/arch/arm/boards/at91sam9n12ek/init.c +++ b/arch/arm/boards/at91sam9n12ek/init.c @@ -31,7 +31,6 @@ #include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h> @@ -44,7 +43,7 @@ static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, - .det_pin = 0, + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PD5, .enable_pin = AT91_PIN_PD4, .ecc_mode = NAND_ECC_HW, @@ -77,7 +76,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&nand_pdata); } @@ -112,7 +111,7 @@ static struct sam9_smc_config __initdata ks8851_smc_config = { static void __init ek_add_device_ks8851(void) { /* Configure chip-select 2 (KS8851) */ - sam9_smc_configure(2, &ks8851_smc_config); + sam9_smc_configure(0, 2, &ks8851_smc_config); /* Configure NCS signal */ at91_set_B_periph(AT91_PIN_PD19, 0); /* Configure Interrupt pin as input, no pull-up */ @@ -186,7 +185,7 @@ static void ek_add_device_spi(void) */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PB16, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; struct gpio_led leds[] = { diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c index ba5bc470e4..8cc119eb3e 100644 --- a/arch/arm/boards/at91sam9x5ek/init.c +++ b/arch/arm/boards/at91sam9x5ek/init.c @@ -31,7 +31,6 @@ #include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h> @@ -53,7 +52,7 @@ struct w1_gpio_platform_data w1_pdata = { static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, - .det_pin = 0, + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PD5, .enable_pin = AT91_PIN_PD4, .ecc_mode = NAND_ECC_HW, @@ -92,7 +91,7 @@ static void ek_add_device_nand(void) cm_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &cm_nand_smc_config); + sam9_smc_configure(0, 3, &cm_nand_smc_config); if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT)) { unsigned long csa; @@ -223,7 +222,7 @@ static void __init ek_add_led(void) at91_set_gpio_output(leds[i].gpio, leds[i].active_low); led_gpio_register(&leds[i]); } - led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); + led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[1].led); } static int at91sam9x5ek_mem_init(void) diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c index aacef3342f..a2e98259c1 100644 --- a/arch/arm/boards/dss11/init.c +++ b/arch/arm/boards/dss11/init.c @@ -29,16 +29,15 @@ #include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> -#include <mach/at91_pmc.h> #include <mach/at91_rstc.h> +#include <linux/clk.h> static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, -/* .det_pin = ... not connected */ + .det_pin = -EINVAL, .ecc_mode = NAND_ECC_HW, .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, @@ -69,7 +68,7 @@ static void dss11_add_device_nand(void) dss11_nand_smc_config.mode |= AT91_SMC_DBW_16; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &dss11_nand_smc_config); + sam9_smc_configure(0, 3, &dss11_nand_smc_config); at91_add_device_nand(&nand_pdata); } @@ -82,7 +81,9 @@ static struct at91_ether_platform_data macb_pdata = { static void dss11_phy_reset(void) { unsigned long rstc; - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + struct clk *clk = clk_get(NULL, "macb_clk"); + + clk_enable(clk); at91_set_gpio_input(AT91_PIN_PA14, 0); at91_set_gpio_input(AT91_PIN_PA15, 0); @@ -117,6 +118,7 @@ static struct atmel_mci_platform_data dss11_mci_data = { static struct at91_usbh_data dss11_usbh_data = { .ports = 2, + .vbus_pin = { -EINVAL, -EINVAL }, }; static int dss11_mem_init(void) diff --git a/arch/arm/boards/efika-mx-smartbook/Makefile b/arch/arm/boards/efika-mx-smartbook/Makefile new file mode 100644 index 0000000000..d08bb68a5c --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o +obj-y += flash_header.o +pbl-y += flash_header.o diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c new file mode 100644 index 0000000000..a455c55b8d --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/board.c @@ -0,0 +1,510 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/gpio.h> +#include <asm/armlinux.h> +#include <partition.h> +#include <notifier.h> +#include <fs.h> +#include <led.h> +#include <fcntl.h> +#include <nand.h> +#include <usb/ulpi.h> +#include <usb/chipidea-imx.h> +#include <spi/spi.h> +#include <mfd/mc13xxx.h> +#include <mfd/mc13892.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <mach/imx-nand.h> +#include <mach/spi.h> +#include <mach/generic.h> +#include <mach/imx5.h> +#include <mach/bbu.h> +#include <mach/iomux-mx51.h> +#include <mach/imx51-regs.h> +#include <mach/devices-imx51.h> +#include <mach/imx-flash-header.h> +#include <mach/revision.h> + +#define GPIO_EFIKA_SDHC1_WP IMX_GPIO_NR(1, 1) +#define GPIO_EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0) +#define GPIO_EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27) +#define GPIO_EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8) +#define GPIO_EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7) + +#define GPIO_BACKLIGHT_POWER IMX_GPIO_NR(4, 12) +#define GPIO_BACKLIGHT_PWM IMX_GPIO_NR(1, 2) +#define GPIO_LVDS_POWER IMX_GPIO_NR(3, 7) +#define GPIO_LVDS_RESET IMX_GPIO_NR(3, 5) +#define GPIO_LVDS_ENABLE IMX_GPIO_NR(3, 12) +#define GPIO_LCD_ENABLE IMX_GPIO_NR(3, 13) + +#define GPIO_BLUETOOTH IMX_GPIO_NR(2, 11) +#define GPIO_WIFI_ENABLE IMX_GPIO_NR(2, 16) +#define GPIO_WIFI_RESET IMX_GPIO_NR(2, 10) +#define GPIO_HUB_RESET IMX_GPIO_NR(1, 5) +#define GPIO_SMSC3317_RESET IMX_GPIO_NR(2, 9) + +static iomux_v3_cfg_t efika_pads[] = { + /* ECSPI1 */ + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + MX51_PAD_GPIO1_6__GPIO1_6, + + /* ESDHC1 */ + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + MX51_PAD_GPIO1_1__GPIO1_1, + + /* USB HOST1 */ + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + MX51_PAD_USBH1_STP__GPIO1_27, + MX51_PAD_EIM_A16__GPIO2_10, + + /* USB HOST2 */ + MX51_PAD_EIM_D27__GPIO2_9, + MX51_PAD_GPIO1_5__GPIO1_5, + MX51_PAD_EIM_D16__USBH2_DATA0, + MX51_PAD_EIM_D17__USBH2_DATA1, + MX51_PAD_EIM_D18__USBH2_DATA2, + MX51_PAD_EIM_D19__USBH2_DATA3, + MX51_PAD_EIM_D20__USBH2_DATA4, + MX51_PAD_EIM_D21__USBH2_DATA5, + MX51_PAD_EIM_D22__USBH2_DATA6, + MX51_PAD_EIM_D23__USBH2_DATA7, + MX51_PAD_EIM_A24__USBH2_CLK, + MX51_PAD_EIM_A25__USBH2_DIR, + MX51_PAD_EIM_A26__GPIO2_20, + MX51_PAD_EIM_A27__USBH2_NXT, + + /* PATA */ + MX51_PAD_NANDF_WE_B__PATA_DIOW, + MX51_PAD_NANDF_RE_B__PATA_DIOR, + MX51_PAD_NANDF_ALE__PATA_BUFFER_EN, + MX51_PAD_NANDF_CLE__PATA_RESET_B, + MX51_PAD_NANDF_WP_B__PATA_DMACK, + MX51_PAD_NANDF_RB0__PATA_DMARQ, + MX51_PAD_NANDF_RB1__PATA_IORDY, + MX51_PAD_GPIO_NAND__PATA_INTRQ, + MX51_PAD_NANDF_CS2__PATA_CS_0, + MX51_PAD_NANDF_CS3__PATA_CS_1, + MX51_PAD_NANDF_CS4__PATA_DA_0, + MX51_PAD_NANDF_CS5__PATA_DA_1, + MX51_PAD_NANDF_CS6__PATA_DA_2, + MX51_PAD_NANDF_D15__PATA_DATA15, + MX51_PAD_NANDF_D14__PATA_DATA14, + MX51_PAD_NANDF_D13__PATA_DATA13, + MX51_PAD_NANDF_D12__PATA_DATA12, + MX51_PAD_NANDF_D11__PATA_DATA11, + MX51_PAD_NANDF_D10__PATA_DATA10, + MX51_PAD_NANDF_D9__PATA_DATA9, + MX51_PAD_NANDF_D8__PATA_DATA8, + MX51_PAD_NANDF_D7__PATA_DATA7, + MX51_PAD_NANDF_D6__PATA_DATA6, + MX51_PAD_NANDF_D5__PATA_DATA5, + MX51_PAD_NANDF_D4__PATA_DATA4, + MX51_PAD_NANDF_D3__PATA_DATA3, + MX51_PAD_NANDF_D2__PATA_DATA2, + MX51_PAD_NANDF_D1__PATA_DATA1, + MX51_PAD_NANDF_D0__PATA_DATA0, + + MX51_PAD_EIM_A22__GPIO2_16, /* WLAN enable (1 = on) */ + MX51_PAD_EIM_A17__GPIO2_11, + + /* I2C2 */ + MX51_PAD_KEY_COL4__I2C2_SCL, + MX51_PAD_KEY_COL5__I2C2_SDA, + + MX51_PAD_GPIO1_2__GPIO1_2, /* Backlight (should be pwm) (1 = on) */ + MX51_PAD_CSI2_D19__GPIO4_12, /* Backlight power (0 = on) */ + + MX51_PAD_DISPB2_SER_CLK__GPIO3_7, /* LVDS power (1 = on) */ + MX51_PAD_DISPB2_SER_DIN__GPIO3_5, /* LVDS reset (1 = reset) */ + MX51_PAD_CSI1_D8__GPIO3_12, /* LVDS enable (1 = enable) */ + MX51_PAD_CSI1_D9__GPIO3_13, /* LCD enable (1 = on) */ + + MX51_PAD_DI1_PIN12__GPIO3_1, /* WLAN switch (0 = on) */ + + MX51_PAD_GPIO1_4__WDOG1_WDOG_B, +}; + +static iomux_v3_cfg_t efikasb_pads[] = { + /* LEDs */ + MX51_PAD_EIM_CS0__GPIO2_25, + MX51_PAD_GPIO1_3__GPIO1_3, + + /* ESHC2 */ + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + MX51_PAD_GPIO1_7__GPIO1_7, + MX51_PAD_GPIO1_8__GPIO1_8, + + MX51_PAD_EIM_CS2__GPIO2_27, +}; + +static iomux_v3_cfg_t efikamx_pads[] = { + MX51_PAD_GPIO1_0__GPIO1_0, +}; + +/* + * Generally this should work on the Efika MX smarttop aswell, + * but I do not have the hardware to test it, so hardcode this + * for the smartbook for now. + */ +static inline int machine_is_efikasb(void) +{ + return 1; +} + +static int efikamx_mem_init(void) +{ + arm_add_mem_device("ram0", 0x90000000, SZ_512M); + + return 0; +} +mem_initcall(efikamx_mem_init); + +static int spi_0_cs[] = { IMX_GPIO_NR(4, 24), IMX_GPIO_NR(4, 25) }; + +static struct spi_imx_master spi_0_data = { + .chipselect = spi_0_cs, + .num_chipselect = ARRAY_SIZE(spi_0_cs), +}; + +static const struct spi_board_info efikamx_spi_board_info[] = { + { + .name = "mc13xxx-spi", + .max_speed_hz = 30 * 1000 * 1000, + .bus_num = 0, + .chip_select = 0, + }, { + .name = "m25p80", + .chip_select = 1, + .max_speed_hz = 20 * 1000 * 1000, + .bus_num = 0, + }, +}; + +static void efikamx_power_init(void) +{ + unsigned int val; + struct mc13xxx *mc; + + mc = mc13xxx_get(); + if (!mc) { + printf("could not get mc13892\n"); + return; + } + + /* Write needed to Power Gate 2 register */ + mc13xxx_reg_read(mc, MC13892_REG_POWER_MISC, &val); + val &= ~MC13892_POWER_MISC_PWGT2SPIEN; + mc13xxx_reg_write(mc, MC13892_REG_POWER_MISC, val); + + /* Externally powered */ + mc13xxx_reg_read(mc, MC13892_REG_CHARGE, &val); + val |= MC13782_CHARGE_ICHRG0 | MC13782_CHARGE_ICHRG1 | + MC13782_CHARGE_ICHRG2 | MC13782_CHARGE_ICHRG3 | + MC13782_CHARGE_CHGAUTOB; + mc13xxx_reg_write(mc, MC13892_REG_CHARGE, val); + + /* power up the system first */ + mc13xxx_reg_write(mc, MC13892_REG_POWER_MISC, + MC13892_POWER_MISC_PWUP); + + /* Set core voltage to 1.1V */ + mc13xxx_reg_read(mc, MC13892_REG_SW_0, &val); + val &= ~MC13892_SWx_SWx_VOLT_MASK; + val |= MC13892_SWx_SWx_1_100V; + mc13xxx_reg_write(mc, MC13892_REG_SW_0, val); + + /* Setup VCC (SW2) to 1.25 */ + mc13xxx_reg_read(mc, MC13892_REG_SW_1, &val); + val &= ~MC13892_SWx_SWx_VOLT_MASK; + val |= MC13892_SWx_SWx_1_250V; + mc13xxx_reg_write(mc, MC13892_REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + mc13xxx_reg_read(mc, MC13892_REG_SW_2, &val); + val &= ~MC13892_SWx_SWx_VOLT_MASK; + val |= MC13892_SWx_SWx_1_250V; + mc13xxx_reg_write(mc, MC13892_REG_SW_2, val); + udelay(50); + + /* Raise the core frequency to 800MHz */ + console_flush(); + imx51_init_lowlevel(800); + clock_notifier_call_chain(); + + /* Set switchers in Auto in NORMAL mode & STANDBY mode */ + /* Setup the switcher mode for SW1 & SW2*/ + mc13xxx_reg_read(mc, MC13892_REG_SW_4, &val); + val = (val & ~((MC13892_SWMODE_MASK << MC13892_SWMODE1_SHIFT) | + (MC13892_SWMODE_MASK << MC13892_SWMODE2_SHIFT))); + val |= (MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE1_SHIFT) | + (MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE2_SHIFT); + mc13xxx_reg_write(mc, MC13892_REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + mc13xxx_reg_read(mc, MC13892_REG_SW_5, &val); + val = (val & ~((MC13892_SWMODE_MASK << MC13892_SWMODE3_SHIFT) | + (MC13892_SWMODE_MASK << MC13892_SWMODE4_SHIFT))); + val |= (MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE3_SHIFT) | + (MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE4_SHIFT); + mc13xxx_reg_write(mc, MC13892_REG_SW_5, val); + + /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ + mc13xxx_reg_read(mc, MC13892_REG_SETTING_0, &val); + val &= ~(MC13892_SETTING_0_VCAM_MASK | + MC13892_SETTING_0_VGEN3_MASK | + MC13892_SETTING_0_VDIG_MASK); + val |= MC13892_SETTING_0_VDIG_1_8 | + MC13892_SETTING_0_VGEN3_1_8 | + MC13892_SETTING_0_VCAM_2_6; + mc13xxx_reg_write(mc, MC13892_REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + mc13xxx_reg_read(mc, MC13892_REG_SETTING_1, &val); + val &= ~(MC13892_SETTING_1_VVIDEO_MASK | + MC13892_SETTING_1_VSD_MASK | + MC13892_SETTING_1_VAUDIO_MASK); + val |= MC13892_SETTING_1_VSD_3_15 | + MC13892_SETTING_1_VAUDIO_3_0 | + MC13892_SETTING_1_VVIDEO_2_775 | + MC13892_SETTING_1_VGEN1_1_2 | + MC13892_SETTING_1_VGEN2_3_15; + mc13xxx_reg_write(mc, MC13892_REG_SETTING_1, val); + + /* Enable VGEN1, VGEN2, VDIG, VPLL */ + mc13xxx_reg_read(mc, MC13892_REG_MODE_0, &val); + val |= MC13892_MODE_0_VGEN1EN | + MC13892_MODE_0_VDIGEN | + MC13892_MODE_0_VGEN2EN | + MC13892_MODE_0_VPLLEN; + mc13xxx_reg_write(mc, MC13892_REG_MODE_0, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = MC13892_MODE_1_VGEN3CONFIG | + MC13892_MODE_1_VCAMCONFIG; + mc13xxx_reg_write(mc, MC13892_REG_MODE_1, val); + udelay(200); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = MC13892_MODE_1_VGEN3EN | + MC13892_MODE_1_VGEN3CONFIG | + MC13892_MODE_1_VCAMEN | + MC13892_MODE_1_VCAMCONFIG | + MC13892_MODE_1_VVIDEOEN | + MC13892_MODE_1_VAUDIOEN | + MC13892_MODE_1_VSDEN; + mc13xxx_reg_write(mc, MC13892_REG_MODE_1, val); + + mc13xxx_reg_read(mc, MC13892_REG_POWER_CTL2, &val); + val |= MC13892_POWER_CONTROL_2_WDIRESET; + mc13xxx_reg_write(mc, MC13892_REG_POWER_CTL2, val); + + udelay(2500); +} + +static struct esdhc_platform_data efikasb_sd2_data = { + .cd_gpio = GPIO_EFIKASB_SDHC2_CD, + .wp_gpio = GPIO_EFIKASB_SDHC2_WP, + .cd_type = ESDHC_CD_GPIO, + .wp_type = ESDHC_WP_GPIO, + .devname = "mmc_left", +}; + +static struct esdhc_platform_data efikamx_sd1_data = { + .cd_gpio = GPIO_EFIKAMX_SDHC1_CD, + .wp_gpio = GPIO_EFIKA_SDHC1_WP, + .cd_type = ESDHC_CD_GPIO, + .wp_type = ESDHC_WP_GPIO, +}; + +static struct esdhc_platform_data efikasb_sd1_data = { + .cd_gpio = GPIO_EFIKASB_SDHC1_CD, + .wp_gpio = GPIO_EFIKA_SDHC1_WP, + .cd_type = ESDHC_CD_GPIO, + .wp_type = ESDHC_WP_GPIO, + .devname = "mmc_back", +}; + +struct imxusb_platformdata efikamx_usbh1_pdata = { + .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI, + .mode = IMX_USB_MODE_HOST, +}; + +static int efikamx_usb_init(void) +{ + gpio_direction_output(GPIO_BLUETOOTH, 0); + gpio_direction_output(GPIO_WIFI_ENABLE, 1); + gpio_direction_output(GPIO_WIFI_RESET, 0); + gpio_direction_output(GPIO_SMSC3317_RESET, 0); + gpio_direction_output(GPIO_HUB_RESET, 0); + + mdelay(10); + + gpio_set_value(GPIO_HUB_RESET, 1); + gpio_set_value(GPIO_SMSC3317_RESET, 1); + gpio_set_value(GPIO_BLUETOOTH, 1); + gpio_set_value(GPIO_WIFI_RESET, 1); + + mxc_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__GPIO1_27); + gpio_set_value(IMX_GPIO_NR(1, 27), 1); + mdelay(1); + mxc_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP); + + if (machine_is_efikasb()) { + mxc_iomux_v3_setup_pad(MX51_PAD_EIM_A26__GPIO2_20); + gpio_set_value(IMX_GPIO_NR(2, 20), 1); + mdelay(1); + mxc_iomux_v3_setup_pad(MX51_PAD_EIM_A26__USBH2_STP); + } + + imx51_add_usbh1(&efikamx_usbh1_pdata); + + /* + * At least for the EfikaSB these do not seem to be interesting. + * The external ports are all connected to host1. + * + * imx51_add_usbotg(pdata); + * imx51_add_usbh2(pdate); + */ + + return 0; +} + +static struct gpio_led leds[] = { + { + .gpio = IMX_GPIO_NR(1, 3), + .active_low = 1, + .led.name = "mail", + }, { + .gpio = IMX_GPIO_NR(2, 25), + .led.name = "white", + }, +}; + +#define DCD_NAME static struct imx_dcd_entry dcd_entry + +#include "dcd-data.h" + +static int efikamx_devices_init(void) +{ + int i; + + mxc_iomux_v3_setup_multiple_pads(efika_pads, ARRAY_SIZE(efika_pads)); + if (machine_is_efikasb()) { + gpio_direction_output(GPIO_BACKLIGHT_POWER, 1); + mxc_iomux_v3_setup_multiple_pads(efikasb_pads, + ARRAY_SIZE(efikasb_pads)); + } else { + mxc_iomux_v3_setup_multiple_pads(efikamx_pads, + ARRAY_SIZE(efikamx_pads)); + } + + spi_register_board_info(efikamx_spi_board_info, + ARRAY_SIZE(efikamx_spi_board_info)); + imx51_add_spi0(&spi_0_data); + + efikamx_power_init(); + + if (machine_is_efikasb()) + imx51_add_mmc0(&efikasb_sd1_data); + else + imx51_add_mmc0(&efikamx_sd1_data); + + imx51_add_mmc1(&efikasb_sd2_data); + + for (i = 0; i < ARRAY_SIZE(leds); i++) + led_gpio_register(&leds[i]); + + imx51_add_i2c1(NULL); + + efikamx_usb_init(); + + imx51_add_pata(); + + writew(0x0, MX51_WDOG_BASE_ADDR + 0x8); + + imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc_left", + BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry), + 0); + + armlinux_set_bootparams((void *)0x90000100); + armlinux_set_architecture(2370); + armlinux_set_revision(0x5100 | imx_silicon_revision()); + + return 0; +} +device_initcall(efikamx_devices_init); + +static int efikamx_part_init(void) +{ + if (imx_bootsource() == bootsource_mmc) { + devfs_add_partition("mmc_left", 0x00000, 0x80000, + DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("mmc_left", 0x80000, 0x80000, + DEVFS_PARTITION_FIXED, "env0"); + } + + return 0; +} +late_initcall(efikamx_part_init); + +static iomux_v3_cfg_t efika_uart_pads[] = { + /* UART */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, +}; + +static int efikamx_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(efika_uart_pads, + ARRAY_SIZE(efika_uart_pads)); + + imx51_add_uart0(); + + return 0; +} +console_initcall(efikamx_console_init); diff --git a/arch/arm/boards/efika-mx-smartbook/config.h b/arch/arm/boards/efika-mx-smartbook/config.h new file mode 100644 index 0000000000..143adf2552 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/config.h @@ -0,0 +1,17 @@ +/** + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/efika-mx-smartbook/dcd-data.h b/arch/arm/boards/efika-mx-smartbook/dcd-data.h new file mode 100644 index 0000000000..6795e19017 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/dcd-data.h @@ -0,0 +1,56 @@ +DCD_NAME[] = { + { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000000, }, + { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000005, }, + { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000005, }, + { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, }, + { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, }, + { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000005, }, + { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000005, }, + { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e5, }, + { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e5, }, + { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e5, }, + { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e5, }, + { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e4, }, + { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0xcaaaf6d0, }, + { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x333574aa, }, + { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x333574aa, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, }, + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, }, + { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, }, +}; diff --git a/arch/arm/boards/efika-mx-smartbook/env/bin/lvds_init b/arch/arm/boards/efika-mx-smartbook/env/bin/lvds_init new file mode 100644 index 0000000000..692392cd6c --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/bin/lvds_init @@ -0,0 +1,22 @@ +#!/bin/sh + +# Initialize lvds and backlight in case your Kernel does not handle this... + +GPIO_BACKLIGHT_POWER=108 +GPIO_BACKLIGHT_PWM=2 +GPIO_LVDS_POWER=71 +GPIO_LVDS_RESET=69 +GPIO_LVDS_ENABLE=76 +GPIO_LCD_ENABLE=77 + +gpio_direction_output $GPIO_BACKLIGHT_PWM 0 +gpio_direction_output $GPIO_LVDS_RESET 1 +gpio_direction_output $GPIO_LVDS_POWER 1 +msleep 5 +gpio_direction_output $GPIO_LVDS_RESET 0 +msleep 5 +gpio_direction_output $GPIO_LVDS_ENABLE 1 +gpio_direction_output $GPIO_BACKLIGHT_POWER 0 +gpio_direction_output $GPIO_LCD_ENABLE 1 +msleep 300 +gpio_direction_output $GPIO_BACKLIGHT_PWM 1 diff --git a/arch/arm/boards/efika-mx-smartbook/env/boot/hd-internal b/arch/arm/boards/efika-mx-smartbook/env/boot/hd-internal new file mode 100644 index 0000000000..ccd0f69bb4 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/boot/hd-internal @@ -0,0 +1,17 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "internal harddisk" + exit +fi + +path="/mnt/internal-hd0.0" + +global.bootm.image="${path}/linuximage" + +oftree=${path}/oftree +if [ -f $oftree ]; then + global.bootm.oftree="$oftree" +fi + +global.linux.bootargs.dyn.root="root=/dev/sda2" diff --git a/arch/arm/boards/efika-mx-smartbook/env/boot/mmc-left b/arch/arm/boards/efika-mx-smartbook/env/boot/mmc-left new file mode 100644 index 0000000000..21935c6fff --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/boot/mmc-left @@ -0,0 +1,19 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "left MMC slot" + exit +fi + +path="/mnt/mmc-left.0" + +global.bootm.image="${path}/linuximage" + +oftree=${path}/oftree +if [ -f $oftree ]; then + global.bootm.oftree="$oftree" +fi + +# The rootdevice may actually be mmcblk1p2 if a card +# is inserted to the back MMC slot +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2" diff --git a/arch/arm/boards/efika-mx-smartbook/env/config b/arch/arm/boards/efika-mx-smartbook/env/config new file mode 100644 index 0000000000..46aff49088 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/config @@ -0,0 +1,29 @@ +#!/bin/sh + +# change network settings in /env/network/eth0 +# change mtd partition settings and automountpoints in /env/init/* + +#global.hostname= + +# set to false if you do not want to have colors +global.allow_color=true + +# user (used for network filenames) +global.user=none + +# timeout in seconds before the default boot entry is started +global.autoboot_timeout=1 + +# default boot entry (one of /env/boot/*) +# (if not overwritten here, the bootdevice barebox comes from +# is used) +#global.boot.default=net + +# base bootargs +global.linux.bootargs.base="console=ttymxc0,115200 console=tty1" + +# suitable for 800MHz +global linux.bootargs.lpj="lpj=3997696" + +# speed up booting by being more quiet +global linux.bootargs.quiet="quiet" diff --git a/arch/arm/boards/efika-mx-smartbook/env/init/automount b/arch/arm/boards/efika-mx-smartbook/env/init/automount new file mode 100644 index 0000000000..8cb5eaf792 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/init/automount @@ -0,0 +1,29 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +# automount nfs server example + +# internal harddisk /boot partition +mkdir -p /mnt/internal-hd0.0 +automount -d /mnt/internal-hd0.0 'mount /dev/ata0.0 /mnt/internal-hd0.0' + +# internal harddisk rootfs +mkdir -p /mnt/internal-hd0.1 +automount -d /mnt/internal-hd0.1 'mount /dev/ata0.1 /mnt/internal-hd0.1' + +# left SD card slot, first partition +mkdir -p /mnt/mmc-left.0 +automount -d /mnt/mmc-left.0 'mount /dev/mmc_left.0 /mnt/mmc-left.0' + +# back SD card slot, first partition +mkdir -p /mnt/mmc-back.0 +automount -d /mnt/mmc-back.0 'mount /dev/mmc_back.0 /mnt/mmc-back.0' diff --git a/arch/arm/boards/efika-mx-smartbook/env/init/bootsource b/arch/arm/boards/efika-mx-smartbook/env/init/bootsource new file mode 100644 index 0000000000..fb084696a3 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/init/bootsource @@ -0,0 +1,10 @@ +#!/bin/sh + +# by default pick kernel from MMC card if booting from +# it, otherwise default to boot from internal harddisk + +if [ $barebox_loc = mmc ]; then + global.boot.default=mmc-left +else + global.boot.default=hd-internal +fi diff --git a/arch/arm/boards/efika-mx-smartbook/env/init/config-board b/arch/arm/boards/efika-mx-smartbook/env/init/config-board new file mode 100644 index 0000000000..22993f9c29 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/init/config-board @@ -0,0 +1,9 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=efikasb +global.linux.bootargs.base="console=ttymxc0,115200" + +[ -f /env/config ] && /env/config diff --git a/arch/arm/boards/efika-mx-smartbook/env/network/eth0-discover b/arch/arm/boards/efika-mx-smartbook/env/network/eth0-discover new file mode 100644 index 0000000000..f8368a5ec6 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/network/eth0-discover @@ -0,0 +1,4 @@ +#!/bin/sh + +usb +sleep 3 diff --git a/arch/arm/boards/efika-mx-smartbook/flash_header.c b/arch/arm/boards/efika-mx-smartbook/flash_header.c new file mode 100644 index 0000000000..f3f1e4bfd5 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/flash_header.c @@ -0,0 +1,29 @@ +#include <common.h> +#include <mach/imx-flash-header.h> +#include <asm/barebox-arm-head.h> + +void __naked __flash_header_start go(void) +{ + barebox_arm_head(); +} + +#define DCD_NAME struct imx_dcd_entry __dcd_entry_section dcd_entry + +#include "dcd-data.h" + +#define APP_DEST 0x90000000 + +struct imx_flash_header __flash_header_section flash_header = { + .app_code_jump_vector = APP_DEST + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = APP_DEST, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof (dcd_entry), +}; + +unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE; + diff --git a/arch/arm/boards/mmccpu/init.c b/arch/arm/boards/mmccpu/init.c index 67bfcea874..1e6bbab99f 100644 --- a/arch/arm/boards/mmccpu/init.c +++ b/arch/arm/boards/mmccpu/init.c @@ -54,7 +54,7 @@ static int mmccpu_devices_init(void) * 0 - disable */ at91_set_gpio_output(AT91_PIN_PB27, 1); - at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ + gpio_set_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ at91_add_device_eth(0, &macb_pdata); add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0); diff --git a/arch/arm/boards/pcm037/Makefile b/arch/arm/boards/pcm037/Makefile index fcfa40d3fe..859501ce92 100644 --- a/arch/arm/boards/pcm037/Makefile +++ b/arch/arm/boards/pcm037/Makefile @@ -16,6 +16,6 @@ # # -obj-y += lowlevel_init.o -pbl-y += lowlevel_init.o +obj-y += lowlevel.o +pbl-y += lowlevel.o obj-y += pcm037.o diff --git a/arch/arm/boards/pcm037/env/boot/nand-ubi b/arch/arm/boards/pcm037/env/boot/nand-ubi new file mode 100644 index 0000000000..67b0cb4afe --- /dev/null +++ b/arch/arm/boards/pcm037/env/boot/nand-ubi @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "nand (UBI)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/pcm037/env/config b/arch/arm/boards/pcm037/env/config deleted file mode 100644 index 569bfe4b68..0000000000 --- a/arch/arm/boards/pcm037/env/config +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/sh - -global.hostname=pcm037 -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" -rootfs_mtdblock_nor=3 - -nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" -rootfs_mtdblock_nand=7 -nand_device="mxc_nand" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/pcm037/env/init/config-board b/arch/arm/boards/pcm037/env/init/config-board new file mode 100644 index 0000000000..03f9e97fca --- /dev/null +++ b/arch/arm/boards/pcm037/env/init/config-board @@ -0,0 +1,7 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=pcm037 +global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/pcm037/env/init/mtdparts-nand b/arch/arm/boards/pcm037/env/init/mtdparts-nand new file mode 100644 index 0000000000..84220b77b3 --- /dev/null +++ b/arch/arm/boards/pcm037/env/init/mtdparts-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" +kernelname="mxc_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm037/env/init/mtdparts-nor b/arch/arm/boards/pcm037/env/init/mtdparts-nor new file mode 100644 index 0000000000..2ef6ead71a --- /dev/null +++ b/arch/arm/boards/pcm037/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="256k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" +kernelname="physmap-flash.0" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm037/lowlevel.c b/arch/arm/boards/pcm037/lowlevel.c new file mode 100644 index 0000000000..baf63a53b9 --- /dev/null +++ b/arch/arm/boards/pcm037/lowlevel.c @@ -0,0 +1,162 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <init.h> +#include <io.h> +#include <mach/imx-nand.h> +#include <asm/barebox-arm.h> +#include <asm/system.h> +#include <asm-generic/memory_layout.h> +#include <asm-generic/sections.h> +#include <asm/barebox-arm-head.h> +#include <mach/imx31-regs.h> +#include <mach/imx-pll.h> +#include <asm/barebox-arm-head.h> +#include <mach/esdctl.h> + +#ifdef CONFIG_NAND_IMX_BOOT +static void __bare_init __naked insdram(void) +{ + /* setup a stack to be able to call imx_nand_load_image() */ + arm_setup_stack(STACK_BASE + STACK_SIZE - 12); + + imx_nand_load_image(_text, barebox_image_size); + + board_init_lowlevel_return(); +} +#endif + +#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) + +void __bare_init __naked reset(void) +{ + uint32_t r; + volatile int v; +#ifdef CONFIG_NAND_IMX_BOOT + int i; + unsigned int *trg, *src; +#endif + common_reset(); + + writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); + + writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); + + for (v = 0; v < 0x4000; v++); + + writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + + MX31_CCM_CCMR); + writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, + MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); + + writel(MX31_PDR0_CSI_PODF(0xff1) | \ + MX31_PDR0_PER_PODF(7) | \ + MX31_PDR0_HSP_PODF(3) | \ + MX31_PDR0_NFC_PODF(5) | \ + MX31_PDR0_IPG_PODF(1) | \ + MX31_PDR0_MAX_PODF(3) | \ + MX31_PDR0_MCU_PODF(0), \ + MX31_CCM_BASE_ADDR + MX31_CCM_PDR0); + + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | + IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), + MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL); + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | + IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + + MX31_CCM_SPCTL); + + /* + * Configure IOMUXC + * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), + * 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) + * (behaviour copied by sha, source unknown) + */ + writel(0, 0x43fac26c); + writel(0, 0x43fac270); + writel(0, 0x43fac274); + + writel(0x1000, 0x43fac27c); + + for (r = 0x43fac284; r <= 0x43fac2dc; r += 4) + writel(0, r); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0x80000000 && r < 0xa0000000) + board_init_lowlevel_return(); + +#if defined CONFIG_PCM037_SDRAM_BANK0_128MB +#define ROWS0 ESDCTL0_ROW13 +#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB +#define ROWS0 ESDCTL0_ROW14 +#endif + writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00); + writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x12344321, MX31_CSD0_BASE_ADDR); + writel(0x12344321, MX31_CSD0_BASE_ADDR); + writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33); + writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000); + writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR); + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); + +#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE +#if defined CONFIG_PCM037_SDRAM_BANK1_128MB +#define ROWS1 ESDCTL0_ROW13 +#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB +#define ROWS1 ESDCTL0_ROW14 +#endif + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1); + writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00); + writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writel(0x12344321, MX31_CSD1_BASE_ADDR); + writel(0x12344321, MX31_CSD1_BASE_ADDR); + writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33); + writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000); + writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR); + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); +#endif + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < MX31_NFC_BASE_ADDR || r > MX31_NFC_BASE_ADDR + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)MX31_NFC_BASE_ADDR; + trg = (unsigned int *)_text; + + /* Move ourselves out of NFC SRAM */ + for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ + r = (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S deleted file mode 100644 index 9560841bcb..0000000000 --- a/arch/arm/boards/pcm037/lowlevel_init.S +++ /dev/null @@ -1,170 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <mach/imx31-regs.h> -#include <mach/imx-pll.h> -#include <asm/barebox-arm-head.h> -#include <mach/esdctl.h> - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#define writeb(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - strb r1, [r0]; - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - - .section ".text_bare_init","ax" - -.globl reset -reset: - - common_reset r0 - - writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR) - - writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) - - DELAY 0x40000 - - writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + - MX31_CCM_CCMR) - writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, - MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) - - writel(MX31_PDR0_CSI_PODF(0xff1) | \ - MX31_PDR0_PER_PODF(7) | \ - MX31_PDR0_HSP_PODF(3) | \ - MX31_PDR0_NFC_PODF(5) | \ - MX31_PDR0_IPG_PODF(1) | \ - MX31_PDR0_MAX_PODF(3) | \ - MX31_PDR0_MCU_PODF(0), \ - MX31_CCM_BASE_ADDR + MX31_CCM_PDR0) - - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | - IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), - MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL) - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | - IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + - MX31_CCM_SPCTL) - - /* Configure IOMUXC - * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) - * (behaviour copied by sha, source unknown) - */ - mov r1, #0; - ldr r0, =0x43FAC26C - str r1, [r0], #4 - str r1, [r0], #4 - str r1, [r0], #0x10 - - ldr r2, =0x43FAC2DC -clear_iomux: - str r1, [r0], #4 - cmp r0, r2 - bls clear_iomux - writel(0x1000, 0x43FAC27C )/* CS2 CSD0) */ - - /* Skip SDRAM initialization if we run from RAM */ - cmp pc, #0x80000000 - blo 1f - cmp pc, #0x90000000 - bhs 1f - - b board_init_lowlevel_return -1: - -#if defined CONFIG_PCM037_SDRAM_BANK0_128MB -#define ROWS0 ESDCTL0_ROW13 -#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB -#define ROWS0 ESDCTL0_ROW14 -#endif - writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) - writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0) - writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writel(0x12344321, MX31_CSD0_BASE_ADDR) - writel(0x12344321, MX31_CSD0_BASE_ADDR) - writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33) - writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR) - writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) - -#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE -#if defined CONFIG_PCM037_SDRAM_BANK1_128MB -#define ROWS1 ESDCTL0_ROW13 -#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB -#define ROWS1 ESDCTL0_ROW14 -#endif - writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1) - writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) - writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) - writel(0x12344321, MX31_CSD1_BASE_ADDR) - writel(0x12344321, MX31_CSD1_BASE_ADDR) - writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) - writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33) - writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) - writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR) - writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) -#endif - -#ifdef CONFIG_NAND_IMX_BOOT - ldr sp, =0x80f00000 /* Setup a temporary stack in SDRAM */ - - ldr r0, =MX31_NFC_BASE_ADDR /* start of NFC SRAM */ - ldr r2, =MX31_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */ - - /* skip NAND boot if not running from NFC space */ - cmp pc, r0 - blo ret - cmp pc, r2 - bhs ret - - /* Move ourselves out of NFC SRAM */ - ldr r1, =_text - -copy_loop: - ldmia r0!, {r3-r9} /* copy from source address [r0] */ - stmia r1!, {r3-r9} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - ble copy_loop - - ldr pc, =1f /* Jump to SDRAM */ -1: - b nand_boot /* Load barebox from NAND Flash */ -ret: -#endif /* CONFIG_NAND_IMX_BOOT */ - - b board_init_lowlevel_return - diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c index 68a6c8d92a..7894ff3bdb 100644 --- a/arch/arm/boards/pcm037/pcm037.c +++ b/arch/arm/boards/pcm037/pcm037.c @@ -163,6 +163,8 @@ static int imx31_devices_init(void) */ add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); + imx31_add_mmc0(NULL); + /* * Create partitions that should be * not touched by any regular user @@ -202,13 +204,49 @@ static int imx31_devices_init(void) device_initcall(imx31_devices_init); +static unsigned int pcm037_iomux[] = { + /* UART1 */ + MX31_PIN_RXD1__RXD1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + /* I2C */ + MX31_PIN_CSPI2_MOSI__SCL, + MX31_PIN_CSPI2_MISO__SDA, + MX31_PIN_CSPI2_SS2__I2C3_SDA, + MX31_PIN_CSPI2_SCLK__I2C3_SCL, + /* SDHC1 */ + MX31_PIN_SD1_DATA3__SD1_DATA3, + MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA1__SD1_DATA1, + MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_CLK__SD1_CLK, + MX31_PIN_SD1_CMD__SD1_CMD, + IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ + IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ + /* SPI1 */ + MX31_PIN_CSPI1_MOSI__MOSI, + MX31_PIN_CSPI1_MISO__MISO, + MX31_PIN_CSPI1_SCLK__SCLK, + MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, + MX31_PIN_CSPI1_SS0__SS0, + MX31_PIN_CSPI1_SS1__SS1, + MX31_PIN_CSPI1_SS2__SS2, + /* UART2 */ + MX31_PIN_TXD2__TXD2, + MX31_PIN_RXD2__RXD2, + MX31_PIN_CTS2__CTS2, + MX31_PIN_RTS2__RTS2, + /* UART3 */ + MX31_PIN_CSPI3_MOSI__RXD3, + MX31_PIN_CSPI3_MISO__TXD3, + MX31_PIN_CSPI3_SCLK__RTS3, + MX31_PIN_CSPI3_SPI_RDY__CTS3, +}; + static int imx31_console_init(void) { - /* init gpios for serial port */ - imx_iomux_mode(MX31_PIN_RXD1__RXD1); - imx_iomux_mode(MX31_PIN_TXD1__TXD1); - imx_iomux_mode(MX31_PIN_CTS1__CTS1); - imx_iomux_mode(MX31_PIN_RTS1__RTS1); + imx_iomux_setup_multiple_pins(pcm037_iomux, ARRAY_SIZE(pcm037_iomux)); imx31_add_uart0(); return 0; diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c index 93a183988a..a50a1f2e97 100644 --- a/arch/arm/boards/pcm038/pcm970.c +++ b/arch/arm/boards/pcm038/pcm970.c @@ -21,34 +21,12 @@ #include <mach/weim.h> #include <mach/gpio.h> #include <mach/devices-imx27.h> -#include <usb/ulpi.h> +#include <usb/chipidea-imx.h> #define GPIO_IDE_POWER (GPIO_PORTE + 18) #define GPIO_IDE_PCOE (GPIO_PORTF + 7) #define GPIO_IDE_RESET (GPIO_PORTF + 10) -#ifdef CONFIG_USB -static void pcm970_usbh2_init(void) -{ - uint32_t temp; - - temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600); - temp &= ~((3 << 21) | 1); - temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); - writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600); - - temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584); - temp &= ~(3 << 30); - temp |= 2 << 30; - writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584); - - mdelay(10); - - if (!ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1)) - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL); -} -#endif - #ifdef CONFIG_DISK_INTF_PLATFORM_IDE static struct resource pcm970_ide_resources[] = { { @@ -168,6 +146,11 @@ static void pcm970_mmc_init(void) imx27_add_mmc1(NULL); } +struct imxusb_platformdata pcm970_usbh2_pdata = { + .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI, + .mode = IMX_USB_MODE_HOST, +}; + static int pcm970_init(void) { int i; @@ -177,7 +160,7 @@ static int pcm970_init(void) PA1_PF_USBH2_DIR, PA2_PF_USBH2_DATA7, PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, + 4 | GPIO_PORTA | GPIO_GPIO | GPIO_OUT, PD19_AF_USBH2_DATA4, PD20_AF_USBH2_DATA3, PD21_AF_USBH2_DATA6, @@ -193,9 +176,14 @@ static int pcm970_init(void) /* Configure SJA1000 on cs4 */ imx27_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302); -#ifdef CONFIG_USB - pcm970_usbh2_init(); -#endif + if (IS_ENABLED(CONFIG_USB)) { + /* Stop ULPI */ + gpio_direction_output(4, 1); + mdelay(1); + imx_gpio_mode(PA4_PF_USBH2_STP); + + imx27_add_usbh2(&pcm970_usbh2_pdata); + } #ifdef CONFIG_DISK_INTF_PLATFORM_IDE pcm970_ide_init(); diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c index 6d2ac98156..207092c528 100644 --- a/arch/arm/boards/pm9261/init.c +++ b/arch/arm/boards/pm9261/init.c @@ -34,7 +34,6 @@ #include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <dm9000.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> @@ -47,7 +46,7 @@ struct w1_gpio_platform_data w1_pdata = { static struct atmel_nand_data nand_pdata = { .ale = 22, .cle = 21, -/* .det_pin = ... not connected */ + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PA16, .enable_pin = AT91_PIN_PC14, #if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) @@ -84,7 +83,7 @@ static void pm_add_device_nand(void) pm_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &pm_nand_smc_config); + sam9_smc_configure(0, 3, &pm_nand_smc_config); at91_add_device_nand(&nand_pdata); } @@ -123,7 +122,7 @@ static void __init pm_add_device_dm9000(void) { w1_local_mac_address_register(0, "ron", "w1-1-0"); /* Configure chip-select 2 (DM9000) */ - sam9_smc_configure(2, &dm9000_smc_config); + sam9_smc_configure(0, 2, &dm9000_smc_config); add_dm9000_device(0, AT91_CHIPSELECT_2, AT91_CHIPSELECT_2 + 4, IORESOURCE_MEM_16BIT, &dm9000_data); diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c index 486df9a18e..f7ef148b8c 100644 --- a/arch/arm/boards/pm9263/init.c +++ b/arch/arm/boards/pm9263/init.c @@ -35,7 +35,6 @@ #include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> @@ -47,7 +46,7 @@ struct w1_gpio_platform_data w1_pdata = { static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, -/* .det_pin = ... not connected */ + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PB30, .enable_pin = AT91_PIN_PD15, #if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) @@ -84,7 +83,7 @@ static void pm_add_device_nand(void) pm_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &pm_nand_smc_config); + sam9_smc_configure(0, 3, &pm_nand_smc_config); at91_add_device_nand(&nand_pdata); } @@ -102,7 +101,7 @@ static void pm9263_phy_init(void) * 0 - disable */ at91_set_gpio_output(AT91_PIN_PB27, 1); - at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ + gpio_set_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ } static void pm9263_add_device_eth(void) diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c index a79b128089..8e29f62e8e 100644 --- a/arch/arm/boards/pm9g45/init.c +++ b/arch/arm/boards/pm9g45/init.c @@ -34,7 +34,6 @@ #include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> @@ -46,7 +45,7 @@ struct w1_gpio_platform_data w1_pdata = { static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, -/* .det_pin = ... not connected */ + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PD3, .enable_pin = AT91_PIN_PC14, .bus_width_16 = 0, @@ -76,7 +75,7 @@ static void pm_add_device_nand(void) pm_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &pm_nand_smc_config); + sam9_smc_configure(0, 3, &pm_nand_smc_config); at91_add_device_nand(&nand_pdata); } @@ -102,7 +101,7 @@ static void pm9g45_add_device_mci(void) {} #ifdef CONFIG_USB_OHCI_AT91 static struct at91_usbh_data __initdata usbh_data = { .ports = 2, - .vbus_pin = { AT91_PIN_PD0, 0x0 }, + .vbus_pin = { AT91_PIN_PD0, -EINVAL }, }; static void __init pm9g45_add_device_usbh(void) @@ -126,7 +125,7 @@ static void pm9g45_phy_init(void) * 0 - disable */ at91_set_gpio_output(AT91_PIN_PD2, 1); - at91_set_gpio_value(AT91_PIN_PD2, 1); + gpio_set_value(AT91_PIN_PD2, 1); } static void pm9g45_add_device_eth(void) diff --git a/arch/arm/boards/qil-a9260/init.c b/arch/arm/boards/qil-a9260/init.c index 3bec4e2d27..4977d3b75e 100644 --- a/arch/arm/boards/qil-a9260/init.c +++ b/arch/arm/boards/qil-a9260/init.c @@ -22,7 +22,6 @@ #include <linux/clk.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <led.h> #include <mach/io.h> @@ -32,7 +31,7 @@ static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, - .det_pin = 0, + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .on_flash_bbt = 1, @@ -59,7 +58,7 @@ static struct sam9_smc_config nand_smc_config = { static void qil_a9260_add_device_nand(void) { /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &nand_smc_config); + sam9_smc_configure(0, 3, &nand_smc_config); at91_add_device_nand(&nand_pdata); } @@ -120,7 +119,7 @@ static void qil_a9260_phy_reset(void) */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; static void __init qil_a9260_add_device_mb(void) diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c index 98f1d2b52e..5fe653173a 100644 --- a/arch/arm/boards/tny-a926x/init.c +++ b/arch/arm/boards/tny-a926x/init.c @@ -32,7 +32,6 @@ #include <mach/board.h> #include <mach/at91sam9_smc.h> #include <mach/at91sam9_sdramc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h> @@ -52,7 +51,7 @@ static void tny_a9260_set_board_type(void) static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, - .det_pin = 0, + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .on_flash_bbt = 1, @@ -100,9 +99,9 @@ static void tny_a9260_add_device_nand(void) { /* configure chip-select 3 (NAND) */ if (machine_is_tny_a9g20()) - sam9_smc_configure(3, &tny_a9g20_nand_smc_config); + sam9_smc_configure(0, 3, &tny_a9g20_nand_smc_config); else - sam9_smc_configure(3, &tny_a9260_nand_smc_config); + sam9_smc_configure(0, 3, &tny_a9260_nand_smc_config); if (machine_is_tny_a9263()) { nand_pdata.rdy_pin = AT91_PIN_PA22; @@ -132,7 +131,7 @@ static void __init ek_add_device_macb(void) {} */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PB30, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; static struct spi_eeprom eeprom = { diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c index 5190aca8a8..95ac6a80ce 100644 --- a/arch/arm/boards/usb-a926x/init.c +++ b/arch/arm/boards/usb-a926x/init.c @@ -32,7 +32,6 @@ #include <mach/board.h> #include <mach/at91sam9_smc.h> #include <mach/at91sam9_sdramc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <led.h> #include <mach/io.h> @@ -55,7 +54,7 @@ static void usb_a9260_set_board_type(void) static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, -/* .det_pin = ... not connected */ + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .on_flash_bbt = 1, @@ -101,9 +100,9 @@ static void usb_a9260_add_device_nand(void) { /* configure chip-select 3 (NAND) */ if (machine_is_usb_a9g20()) - sam9_smc_configure(3, &usb_a9g20_nand_smc_config); + sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config); else - sam9_smc_configure(3, &usb_a9260_nand_smc_config); + sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config); if (machine_is_usb_a9263()) { nand_pdata.rdy_pin = AT91_PIN_PA22; @@ -208,6 +207,7 @@ static void usb_a9260_add_device_mci(void) {} static struct at91_usbh_data ek_usbh_data = { .ports = 2, + .vbus_pin = { -EINVAL, -EINVAL }, }; /* diff --git a/arch/arm/configs/efika-mx-smartbook_defconfig b/arch/arm/configs/efika-mx-smartbook_defconfig new file mode 100644 index 0000000000..2ef33b448f --- /dev/null +++ b/arch/arm/configs/efika-mx-smartbook_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX51=y +CONFIG_MACH_EFIKA_MX_SMARTBOOK=y +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/efika-mx-smartbook/env/" +CONFIG_RESET_SOURCE=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DIRNAME=y +CONFIG_CMD_LN=y +CONFIG_CMD_READLINK=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_OFTREE_PROBE=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_CMD_WD=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y +CONFIG_NET_USB_SMSC95XX=y +CONFIG_DRIVER_SPI_IMX=y +CONFIG_I2C=y +CONFIG_I2C_IMX=y +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_MTD_M25P80=y +CONFIG_DISK_INTF_PLATFORM_IDE=y +CONFIG_DISK_PATA_IMX=y +CONFIG_USB=y +CONFIG_USB_IMX_CHIPIDEA=y +CONFIG_USB_EHCI=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_MFD_MC13XXX=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_TRIGGERS=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_IMX=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale_mx53_loco_defconfig b/arch/arm/configs/freescale_mx53_loco_defconfig index b61f0cfa46..fb6fcf8d36 100644 --- a/arch/arm/configs/freescale_mx53_loco_defconfig +++ b/arch/arm/configs/freescale_mx53_loco_defconfig @@ -79,7 +79,7 @@ CONFIG_USB_STORAGE=y CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_IMX_ESDHC=y -CONFIG_I2C_MC34708=y +CONFIG_MFD_MC34708=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_IMX=y CONFIG_FS_TFTP=y diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig index 5a527d56a9..7c630a59d2 100644 --- a/arch/arm/configs/pcm037_defconfig +++ b/arch/arm/configs/pcm037_defconfig @@ -11,25 +11,36 @@ CONFIG_MALLOC_SIZE=0x01000000 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y CONFIG_LONGHELP=y -CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y CONFIG_PARTITION=y CONFIG_PARTITION_DISK=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm037/env" +CONFIG_RESET_SOURCE=y CONFIG_CMD_EDIT=y CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y CONFIG_CMD_EXPORT=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y CONFIG_CMD_TIME=y +CONFIG_CMD_DIRNAME=y +CONFIG_CMD_LN=y +CONFIG_CMD_READLINK=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y CONFIG_CMD_FLASH=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y @@ -37,23 +48,24 @@ CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set # CONFIG_CMD_BOOTU is not set CONFIG_CMD_RESET=y CONFIG_CMD_GO=y +CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y CONFIG_CMD_GPIO=y CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_SPI=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y CONFIG_NET=y CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y CONFIG_DRIVER_NET_SMC911X=y CONFIG_NET_USB=y CONFIG_NET_USB_ASIX=y @@ -65,5 +77,11 @@ CONFIG_NAND_IMX=y CONFIG_UBI=y CONFIG_USB=y CONFIG_USB_EHCI=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y CONFIG_ZLIB=y CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig index bab4002a6a..e2f5388d60 100644 --- a/arch/arm/configs/pcm038_defconfig +++ b/arch/arm/configs/pcm038_defconfig @@ -2,7 +2,6 @@ CONFIG_ARCH_IMX=y CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y CONFIG_ARCH_IMX27=y CONFIG_MACH_PCM038=y -CONFIG_IMX_CLKO=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y @@ -16,8 +15,6 @@ CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y -CONFIG_PARTITION=y -CONFIG_PARTITION_DISK=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm038/env" CONFIG_CMD_EDIT=y @@ -32,7 +29,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_IOMEM=y -CONFIG_CMD_MTEST=y CONFIG_CMD_FLASH=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y @@ -40,16 +36,16 @@ CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set # CONFIG_CMD_BOOTU is not set CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_SPLASH=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SPLASH=y CONFIG_CMD_GPIO=y CONFIG_CMD_UNCOMPRESS=y CONFIG_NET=y @@ -68,8 +64,10 @@ CONFIG_NAND=y # CONFIG_NAND_ECC_HW_SYNDROME is not set CONFIG_NAND_IMX=y CONFIG_USB=y +CONFIG_USB_IMX_CHIPIDEA=y CONFIG_USB_EHCI=y CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_DRIVER_VIDEO_IMX=y CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 4dda00f990..fcba7fb94b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -1,5 +1,23 @@ if ARCH_AT91 +config HAVE_AT91_DBGU0 + bool + +config HAVE_AT91_DBGU1 + bool + +config AT91SAM9_SMC + bool + +config AT91SAM9_TIMER + bool + +config SOC_AT91SAM9 + bool + select CPU_ARM926T + select AT91SAM9_SMC + select AT91SAM9_TIMER + config ARCH_TEXT_BASE hex default 0x73f00000 if ARCH_AT91SAM9G45 @@ -43,60 +61,108 @@ config AT91SAM9G45_RESET comment "Atmel AT91 System-on-Chip" +config SOC_AT91RM9200 + bool + select CPU_ARM920T + select HAVE_AT91_DBGU0 + select HAS_AT91_ETHER + select MACH_HAS_LOWLEVEL_INIT + +config SOC_AT91SAM9260 + bool + select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 + select HAS_MACB + select AT91SAM9_RESET + help + Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE + or AT91SAM9G20 SoC. + +config SOC_AT91SAM9261 + bool + select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 + select AT91SAM9_RESET + help + Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. + +config SOC_AT91SAM9263 + bool + select SOC_AT91SAM9 + select HAVE_AT91_DBGU1 + select HAS_MACB + select AT91SAM9_RESET + +config SOC_AT91SAM9G45 + bool + select SOC_AT91SAM9 + select HAVE_AT91_DBGU1 + select HAS_MACB + select AT91SAM9G45_RESET + help + Select this if you are using one of Atmel's AT91SAM9G45 family SoC. + This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. + +config SOC_AT91SAM9X5 + bool + select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 + select HAS_MACB + select AT91SAM9G45_RESET + help + Select this if you are using one of Atmel's AT91SAM9x5 family SoC. + This means that your SAM9 name finishes with a '5' (except if it is + AT91SAM9G45!). + This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35 + and AT91SAM9X35. + +config SOC_AT91SAM9N12 + bool + select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 + select AT91SAM9G45_RESET + help + Select this if you are using Atmel's AT91SAM9N12 SoC. + choice prompt "Atmel AT91 Processor" config ARCH_AT91RM9200 bool "AT91RM9200" - select CPU_ARM920T - select HAS_AT91_ETHER - select MACH_HAS_LOWLEVEL_INIT select MACH_DO_LOWLEVEL_INIT + select SOC_AT91RM9200 config ARCH_AT91SAM9260 bool "AT91SAM9260" - select CPU_ARM926T - select HAS_MACB - select AT91SAM9_RESET + select SOC_AT91SAM9260 config ARCH_AT91SAM9261 bool "AT91SAM9261" - select CPU_ARM926T - select AT91SAM9_RESET + select SOC_AT91SAM9261 config ARCH_AT91SAM9263 bool "AT91SAM9263" - select CPU_ARM926T - select HAS_MACB - select AT91SAM9_RESET + select SOC_AT91SAM9263 config ARCH_AT91SAM9G10 bool "AT91SAM9G10" - select CPU_ARM926T - select AT91SAM9_RESET + select SOC_AT91SAM9261 config ARCH_AT91SAM9G20 bool "AT91SAM9G20" - select CPU_ARM926T - select HAS_MACB - select AT91SAM9_RESET + select SOC_AT91SAM9260 config ARCH_AT91SAM9G45 bool "AT91SAM9G45 or AT91SAM9M10" - select CPU_ARM926T - select HAS_MACB - select AT91SAM9G45_RESET + select SOC_AT91SAM9G45 config ARCH_AT91SAM9X5 bool "AT91SAM9X5" - select CPU_ARM926T - select HAS_MACB - select AT91SAM9G45_RESET + select SOC_AT91SAM9X5 config ARCH_AT91SAM9N12 bool "AT91SAM9N12" - select CPU_ARM926T - select AT91SAM9G45_RESET + select SOC_AT91SAM9N12 endchoice @@ -413,4 +479,8 @@ config CALAO_MB_QIL_A9260 bool "MB-QIL A9260 Motherboard Board support" depends on MACH_QIL_A9260 +config CMD_AT91MUX + bool "at91mux dump command" + default y + endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 7a1e50643b..53b4dd89ab 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,4 +1,4 @@ -obj-y += clock.o gpio.o +obj-y += setup.o clock.o gpio.o lowlevel_init-y = at91sam926x_lowlevel_init.o lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o @@ -9,13 +9,16 @@ pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) obj-$(CONFIG_AT91SAM9_RESET) += at91sam9_reset.o obj-$(CONFIG_AT91SAM9G45_RESET) += at91sam9g45_reset.o +obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o +obj-$(CONFIG_AT91SAM9_TIMER) += at91sam926x_time.o + # CPU-specific support obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o at91sam9x5_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam926x_time.o at91sam9n12_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o +obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o +obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o +obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 5e3fdeb31c..8eeaa551eb 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -4,6 +4,7 @@ #include <asm/hardware.h> #include <mach/at91_pmc.h> +#include "soc.h" #include "clock.h" #include "generic.h" @@ -157,6 +158,13 @@ static struct clk *periph_clocks[] __initdata = { // irq0 .. irq6 }; +static struct clk_lookup periph_clocks_lookups[] = { + CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk), + CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk), + CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk), + CLKDEV_DEV_ID("at91rm9200-gpio3", &pioD_clk), +}; + static struct clk_lookup usart_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "atmel_usart0", &mck), CLKDEV_CON_DEV_ID("usart", "atmel_usart1", &usart0_clk), @@ -201,6 +209,8 @@ static void __init at91rm9200_register_clocks(void) for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) clk_register(periph_clocks[i]); + clkdev_add_table(periph_clocks_lookups, + ARRAY_SIZE(periph_clocks_lookups)); clkdev_add_table(usart_clocks_lookups, ARRAY_SIZE(usart_clocks_lookups)); @@ -211,42 +221,23 @@ static void __init at91rm9200_register_clocks(void) } /* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91rm9200_gpio[] = { - { - .regbase = IOMEM(AT91_BASE_PIOA), - .clock = &pioA_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOB), - .clock = &pioB_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOC), - .clock = &pioC_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOD), - .clock = &pioD_clk, - } -}; - - -/* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */ -static int __init at91rm9200_initialize(void) +static void __init at91rm9200_initialize(void) { - /* Init clock subsystem */ at91_clock_init(AT91_MAIN_CLOCK); /* Register the processor-specific clocks */ at91rm9200_register_clocks(); - /* Initialize GPIO subsystem */ - at91_gpio_init(at91rm9200_gpio, ARRAY_SIZE(at91rm9200_gpio)); - - return 0; + /* Register GPIO subsystem */ + at91_add_rm9200_gpio(0, AT91RM9200_BASE_PIOA); + at91_add_rm9200_gpio(1, AT91RM9200_BASE_PIOB); + at91_add_rm9200_gpio(2, AT91RM9200_BASE_PIOC); + at91_add_rm9200_gpio(3, AT91RM9200_BASE_PIOD); } -core_initcall(at91rm9200_initialize); +AT91_SOC_START(rm9200) + .init = at91rm9200_initialize, +AT91_SOC_END diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 47516646d3..4109172a5f 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -54,12 +54,12 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #ifdef CONFIG_USB_GADGET_DRIVER_AT91 void __init at91_add_device_udc(struct at91_udc_data *data) { - if (data->vbus_pin > 0) { + if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } - if (data->pullup_pin > 0) + if (gpio_is_valid(data->pullup_pin)) at91_set_gpio_output(data->pullup_pin, 0); add_generic_device("at91_udc", DEVICE_ID_DYNAMIC, NULL, AT91RM9200_BASE_UDP, @@ -134,15 +134,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) ); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */ diff --git a/arch/arm/mach-at91/at91rm9200_lowlevel_init.c b/arch/arm/mach-at91/at91rm9200_lowlevel_init.c index 3ce3e6743e..4add3d9284 100644 --- a/arch/arm/mach-at91/at91rm9200_lowlevel_init.c +++ b/arch/arm/mach-at91/at91rm9200_lowlevel_init.c @@ -4,6 +4,8 @@ * Under GPLv2 */ +#define __LOWLEVEL_INIT__ + #include <common.h> #include <asm/system.h> #include <asm/barebox-arm.h> @@ -31,17 +33,17 @@ void __naked __bare_init reset(void) /* * PMC Check if the PLL is already initialized */ - r = at91_sys_read(AT91_PMC_MCKR); + r = at91_pmc_read(AT91_PMC_MCKR); if (r & AT91_PMC_CSS) goto end; /* * Enable the Main Oscillator */ - at91_sys_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL); + at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL); do { - r = at91_sys_read(AT91_PMC_SR); + r = at91_pmc_read(AT91_PMC_SR); } while (!(r & AT91_PMC_MOSCS)); /* @@ -61,24 +63,24 @@ void __naked __bare_init reset(void) /* * PLLAR: x MHz for PCK */ - at91_sys_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL); + at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL); do { - r = at91_sys_read(AT91_PMC_SR); + r = at91_pmc_read(AT91_PMC_SR); } while (!(r & AT91_PMC_LOCKA)); /* * PCK/x = MCK Master Clock from SLOW */ - at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1); + at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1); /* * PCK/x = MCK Master Clock from PLLA */ - at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2); + at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2); do { - r = at91_sys_read(AT91_PMC_SR); + r = at91_pmc_read(AT91_PMC_SR); } while (!(r & AT91_PMC_MCKRDY)); /* diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index cf9e51191c..fa65fe7fef 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -4,6 +4,7 @@ #include <asm/hardware.h> #include <mach/at91_pmc.h> +#include "soc.h" #include "generic.h" #include "clock.h" @@ -172,6 +173,10 @@ static struct clk *periph_clocks[] = { static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), + CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk), + CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk), + CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -217,24 +222,7 @@ static void __init at91sam9260_register_clocks(void) clk_register(&pck1); } -/* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91sam9260_gpio[] = { - { - .regbase = IOMEM(AT91_BASE_PIOA), - .clock = &pioA_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOB), - .clock = &pioB_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOC), - .clock = &pioC_clk, - } -}; - -static int at91sam9260_initialize(void) +static void at91sam9260_initialize(void) { /* Init clock subsystem */ at91_clock_init(AT91_MAIN_CLOCK); @@ -243,8 +231,14 @@ static int at91sam9260_initialize(void) at91sam9260_register_clocks(); /* Register GPIO subsystem */ - at91_gpio_init(at91sam9260_gpio, 3); - return 0; + at91_add_rm9200_gpio(0, AT91SAM9260_BASE_PIOA); + at91_add_rm9200_gpio(1, AT91SAM9260_BASE_PIOB); + at91_add_rm9200_gpio(2, AT91SAM9260_BASE_PIOC); + + at91_add_pit(AT91SAM9260_BASE_PIT); + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9260_BASE_SMC, 0x200); } -core_initcall(at91sam9260_initialize); +AT91_SOC_START(sam9260) + .init = at91sam9260_initialize, +AT91_SOC_END diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 04a9c5f1e3..a893a9581a 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -59,7 +59,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #ifdef CONFIG_USB_GADGET_DRIVER_AT91 void __init at91_add_device_udc(struct at91_udc_data *data) { - if (data->vbus_pin > 0) { + if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } @@ -137,15 +137,15 @@ void at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); add_generic_device_res("atmel_nand", 0, nand_resources, @@ -221,7 +221,7 @@ void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata cs_pin = pdata->chipselect[i]; /* enable chip-select pin */ - if (cs_pin > 0) + if (gpio_is_valid(cs_pin)) at91_set_gpio_output(cs_pin, 1); } @@ -346,12 +346,12 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) return; /* input/irq */ - if (data->detect_pin) { + if (gpio_is_valid(data->detect_pin)) { at91_set_gpio_input(data->detect_pin, 1); at91_set_deglitch(data->detect_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); /* CLK */ diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index d20b2502cd..edac177400 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -4,6 +4,7 @@ #include <asm/hardware.h> #include <mach/at91_pmc.h> +#include "soc.h" #include "generic.h" #include "clock.h" @@ -136,6 +137,10 @@ static struct clk *periph_clocks[] = { static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), + CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk), + CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk), + CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -209,26 +214,7 @@ static void at91sam9261_register_clocks(void) clk_register(&hck1); } - -/* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91sam9261_gpio[] = { - { - .regbase = IOMEM(AT91_BASE_PIOA), - .clock = &pioA_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOB), - .clock = &pioB_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOC), - .clock = &pioC_clk, - } -}; - - -static int at91sam9261_initialize(void) +static void at91sam9261_initialize(void) { /* Init clock subsystem */ at91_clock_init(AT91_MAIN_CLOCK); @@ -237,8 +223,14 @@ static int at91sam9261_initialize(void) at91sam9261_register_clocks(); /* Register GPIO subsystem */ - at91_gpio_init(at91sam9261_gpio, 3); - return 0; + at91_add_rm9200_gpio(0, AT91SAM9261_BASE_PIOA); + at91_add_rm9200_gpio(1, AT91SAM9261_BASE_PIOB); + at91_add_rm9200_gpio(2, AT91SAM9261_BASE_PIOC); + + at91_add_pit(AT91SAM9261_BASE_PIT); + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200); } -core_initcall(at91sam9261_initialize); +AT91_SOC_START(sam9261) + .init = at91sam9261_initialize, +AT91_SOC_END diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 68d75c3fad..becd25f376 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -62,7 +62,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #ifdef CONFIG_USB_GADGET_DRIVER_AT91 void __init at91_add_device_udc(struct at91_udc_data *data) { - if (data->vbus_pin > 0) { + if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } @@ -86,15 +86,15 @@ void at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ @@ -172,7 +172,7 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) cs_pin = pdata->chipselect[i]; /* enable chip-select pin */ - if (cs_pin > 0) + if (gpio_is_valid(cs_pin)) at91_set_gpio_output(cs_pin, 1); } @@ -260,12 +260,12 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) return; /* input/irq */ - if (data->detect_pin) { + if (gpio_is_valid(data->detect_pin)) { at91_set_gpio_input(data->detect_pin, 1); at91_set_deglitch(data->detect_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); /* CLK */ diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index b3116d33d3..eeea1cea20 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -4,6 +4,7 @@ #include <asm/hardware.h> #include <mach/at91_pmc.h> +#include "soc.h" #include "clock.h" #include "generic.h" @@ -168,6 +169,12 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), + CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk), + CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk), + CLKDEV_DEV_ID("at91rm9200-gpio2", &pioCDE_clk), + CLKDEV_DEV_ID("at91rm9200-gpio3", &pioCDE_clk), + CLKDEV_DEV_ID("at91rm9200-gpio4", &pioCDE_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -224,30 +231,7 @@ static void __init at91sam9263_register_clocks(void) clk_register(&pck3); } -/* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91sam9263_gpio[] = { - { - .regbase = IOMEM(AT91_BASE_PIOA), - .clock = &pioA_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOB), - .clock = &pioB_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOC), - .clock = &pioCDE_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOD), - .clock = &pioCDE_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOE), - .clock = &pioCDE_clk, - } -}; - -static int at91sam9263_initialize(void) +static void at91sam9263_initialize(void) { /* Init clock subsystem */ at91_clock_init(AT91_MAIN_CLOCK); @@ -256,8 +240,17 @@ static int at91sam9263_initialize(void) at91sam9263_register_clocks(); /* Register GPIO subsystem */ - at91_gpio_init(at91sam9263_gpio, 5); - return 0; + at91_add_rm9200_gpio(0, AT91SAM9263_BASE_PIOA); + at91_add_rm9200_gpio(1, AT91SAM9263_BASE_PIOB); + at91_add_rm9200_gpio(2, AT91SAM9263_BASE_PIOC); + at91_add_rm9200_gpio(3, AT91SAM9263_BASE_PIOD); + at91_add_rm9200_gpio(4, AT91SAM9263_BASE_PIOE); + + at91_add_pit(AT91SAM9263_BASE_PIT); + at91_add_sam9_smc(0, AT91SAM9263_BASE_SMC0, 0x200); + at91_add_sam9_smc(1, AT91SAM9263_BASE_SMC1, 0x200); } -core_initcall(at91sam9263_initialize); +AT91_SOC_START(sam9263) + .init = at91sam9263_initialize, +AT91_SOC_END diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index fcd157d2c7..b72cc5a84a 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -49,7 +49,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { - if (data->vbus_pin[i]) + if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], 0); } @@ -67,7 +67,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #ifdef CONFIG_USB_GADGET_DRIVER_AT91 void __init at91_add_device_udc(struct at91_udc_data *data) { - if (data->vbus_pin > 0) { + if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } @@ -139,15 +139,15 @@ void at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); add_generic_device_res("atmel_nand", DEVICE_ID_DYNAMIC, nand_resources, @@ -222,7 +222,7 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) cs_pin = pdata->chipselect[i]; /* enable chip-select pin */ - if (cs_pin > 0) + if (gpio_is_valid(cs_pin)) at91_set_gpio_output(cs_pin, 1); } @@ -310,12 +310,12 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) return; /* input/irq */ - if (data->detect_pin) { + if (gpio_is_valid(data->detect_pin)) { at91_set_gpio_input(data->detect_pin, 1); at91_set_deglitch(data->detect_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); if (mmc_id == 0) { /* MCI0 */ diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c index 0ee0345a3a..cfae9824d3 100644 --- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c +++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c @@ -5,6 +5,8 @@ * Under GPLv2 */ +#define __LOWLEVEL_INIT__ + #include <common.h> #include <asm/system.h> #include <asm/barebox-arm.h> @@ -30,7 +32,7 @@ static void inline pmc_check_mckrdy(void) u32 r; do { - r = at91_sys_read(AT91_PMC_SR); + r = at91_pmc_read(AT91_PMC_SR); } while (!(r & AT91_PMC_MCKRDY)); } @@ -41,7 +43,7 @@ void __naked __bare_init reset(void) common_reset(); - at91_sys_write(AT91_WDT_MR, CONFIG_SYS_WDTC_WDMR_VAL); + __raw_writel(CONFIG_SYS_WDTC_WDMR_VAL, AT91_BASE_WDT + AT91_WDT_MR); /* configure PIOx as EBI0 D[16-31] */ #ifdef CONFIG_ARCH_AT91SAM9263 @@ -60,50 +62,50 @@ void __naked __bare_init reset(void) #endif /* flash */ - at91_sys_write(AT91_SMC_MODE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_MODE_VAL); + at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_MODE, CONFIG_SYS_SMC_MODE_VAL); - at91_sys_write(AT91_SMC_CYCLE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_CYCLE_VAL); + at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_CYCLE, CONFIG_SYS_SMC_CYCLE_VAL); - at91_sys_write(AT91_SMC_PULSE(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_PULSE_VAL); + at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_PULSE, CONFIG_SYS_SMC_PULSE_VAL); - at91_sys_write(AT91_SMC_SETUP(CONFIG_SYS_SMC_CS), CONFIG_SYS_SMC_SETUP_VAL); + at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_SETUP, CONFIG_SYS_SMC_SETUP_VAL); /* * PMC Check if the PLL is already initialized */ - r = at91_sys_read(AT91_PMC_MCKR); + r = at91_pmc_read(AT91_PMC_MCKR); if (r & AT91_PMC_CSS) goto end; /* * Enable the Main Oscillator */ - at91_sys_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL); + at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL); do { - r = at91_sys_read(AT91_PMC_SR); + r = at91_pmc_read(AT91_PMC_SR); } while (!(r & AT91_PMC_MOSCS)); /* * PLLAR: x MHz for PCK */ - at91_sys_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL); + at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL); do { - r = at91_sys_read(AT91_PMC_SR); + r = at91_pmc_read(AT91_PMC_SR); } while (!(r & AT91_PMC_LOCKA)); /* * PCK/x = MCK Master Clock from SLOW */ - at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL); + at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL); pmc_check_mckrdy(); /* * PCK/x = MCK Master Clock from PLLA */ - at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL); + at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL); pmc_check_mckrdy(); diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index 7425e0a107..e18458ac96 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -30,15 +30,20 @@ #include <clock.h> #include <asm/hardware.h> #include <mach/at91_pit.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> #include <mach/io.h> #include <io.h> #include <linux/clk.h> +#include <linux/err.h> + +#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) +#define pit_write(reg, val) __raw_writel(val, pit_base + reg) +#define pit_read(reg) __raw_readl(pit_base + reg) + +static __iomem void *pit_base; uint64_t at91sam9_clocksource_read(void) { - return at91_sys_read(AT91_PIT_PIIR); + return pit_read(AT91_PIT_PIIR); } static struct clocksource cs = { @@ -47,20 +52,48 @@ static struct clocksource cs = { .shift = 10, }; -static int clocksource_init (void) +static void at91_pit_stop(void) +{ + /* Disable timer and irqs */ + pit_write(AT91_PIT_MR, 0); + + /* Clear any pending interrupts, wait for PIT to stop counting */ + while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0); +} + +static void at91sam926x_pit_reset(void) +{ + at91_pit_stop(); + + /* Start PIT but don't enable IRQ */ + pit_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN); +} + +static int at91_pit_probe(struct device_d *dev) { + struct clk *clk; u32 pit_rate; + int ret; + + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(dev, "clock not found: %d\n", ret); + return ret; + } + + ret = clk_enable(clk); + if (ret < 0) { + dev_err(dev, "clock failed to enable: %d\n", ret); + clk_put(clk); + return ret; + } - /* - * Enable PITC Clock - * The clock is already enabled for system controller in boot - */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + pit_base = dev_request_mem_region(dev, 0); - pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16; + pit_rate = clk_get_rate(clk) / 16; - /* Enable PITC */ - at91_sys_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN); + at91sam926x_pit_reset(); cs.mult = clocksource_hz2mult(pit_rate, cs.shift); @@ -69,4 +102,13 @@ static int clocksource_init (void) return 0; } -core_initcall(clocksource_init); +static struct driver_d at91_pit_driver = { + .name = "at91-pit", + .probe = at91_pit_probe, +}; + +static int at91_pit_init(void) +{ + return platform_driver_register(&at91_pit_driver); +} +postcore_initcall(at91_pit_init); diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index a6717f1968..7118efe9a4 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -6,6 +6,7 @@ #include <mach/at91_pmc.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h" @@ -190,6 +191,12 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), + CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk), + CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk), + CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk), + CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk), + CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -236,30 +243,7 @@ static void __init at91sam9g45_register_clocks(void) clk_register(&pck1); } -/* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91sam9g45_gpio[] = { - { - .regbase = IOMEM(AT91_BASE_PIOA), - .clock = &pioA_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOB), - .clock = &pioB_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOC), - .clock = &pioC_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOD), - .clock = &pioDE_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOE), - .clock = &pioDE_clk, - } -}; - -static int at91sam9g45_initialize(void) +static void at91sam9g45_initialize(void) { /* Init clock subsystem */ at91_clock_init(AT91_MAIN_CLOCK); @@ -268,8 +252,16 @@ static int at91sam9g45_initialize(void) at91sam9g45_register_clocks(); /* Register GPIO subsystem */ - at91_gpio_init(at91sam9g45_gpio, 5); - return 0; + at91_add_rm9200_gpio(0, AT91SAM9G45_BASE_PIOA); + at91_add_rm9200_gpio(1, AT91SAM9G45_BASE_PIOB); + at91_add_rm9200_gpio(2, AT91SAM9G45_BASE_PIOC); + at91_add_rm9200_gpio(3, AT91SAM9G45_BASE_PIOD); + at91_add_rm9200_gpio(4, AT91SAM9G45_BASE_PIOE); + + at91_add_pit(AT91SAM9G45_BASE_PIT); + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200); } -core_initcall(at91sam9g45_initialize); +AT91_SOC_START(sam9g45) + .init = at91sam9g45_initialize, +AT91_SOC_END diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 2529404233..c5f99b1523 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -43,7 +43,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { - if (data->vbus_pin[i]) + if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], 0); } @@ -115,15 +115,15 @@ void at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); add_generic_device_res("atmel_nand", DEVICE_ID_DYNAMIC, nand_resources, @@ -256,12 +256,12 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) return; /* input/irq */ - if (data->detect_pin) { + if (gpio_is_valid(data->detect_pin)) { at91_set_gpio_input(data->detect_pin, 1); at91_set_deglitch(data->detect_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); if (mmc_id == 0) { /* MCI0 */ @@ -348,7 +348,7 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) cs_pin = pdata->chipselect[i]; /* enable chip-select pin */ - if (cs_pin > 0) + if (gpio_is_valid(cs_pin)) at91_set_gpio_output(cs_pin, 1); } diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index b74a72a8ec..c177975f33 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -6,6 +6,7 @@ #include <mach/io.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h" @@ -150,6 +151,11 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_ID("ohci_clk", &uhpfs_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio0", &pioAB_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio1", &pioAB_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioCD_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioCD_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -195,30 +201,10 @@ static void __init at91sam9n12_register_clocks(void) } /* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91sam9n12_gpio[] = { - { - .regbase = IOMEM(AT91_BASE_PIOA), - .clock = &pioAB_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOB), - .clock = &pioAB_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOC), - .clock = &pioCD_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOD), - .clock = &pioCD_clk, - } -}; - -/* -------------------------------------------------------------------- * AT91SAM9N12 processor initialization * -------------------------------------------------------------------- */ -static int at91sam9n12_initialize(void) +static void at91sam9n12_initialize(void) { /* Init clock subsystem */ at91_clock_init(AT91_MAIN_CLOCK); @@ -227,7 +213,15 @@ static int at91sam9n12_initialize(void) at91sam9n12_register_clocks(); /* Register GPIO subsystem */ - at91_gpio_init(at91sam9n12_gpio, 4); - return 0; + at91_add_sam9x5_gpio(0, AT91SAM9N12_BASE_PIOA); + at91_add_sam9x5_gpio(1, AT91SAM9N12_BASE_PIOB); + at91_add_sam9x5_gpio(2, AT91SAM9N12_BASE_PIOC); + at91_add_sam9x5_gpio(3, AT91SAM9N12_BASE_PIOD); + + at91_add_pit(AT91SAM9N12_BASE_PIT); + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200); } -core_initcall(at91sam9n12_initialize); + +AT91_SOC_START(sam9n12) + .init = at91sam9n12_initialize, +AT91_SOC_END diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c index 33baf41743..3f41f3e3b5 100644 --- a/arch/arm/mach-at91/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/at91sam9n12_devices.c @@ -45,7 +45,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { - if (data->vbus_pin[i]) + if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], 0); } @@ -63,7 +63,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #ifdef CONFIG_USB_GADGET_DRIVER_AT91 void __init at91_add_device_udc(struct at91_udc_data *data) { - if (data->vbus_pin > 0) { + if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } @@ -87,11 +87,11 @@ void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *da return; /* input/irq */ - if (data->detect_pin) { + if (gpio_is_valid(data->detect_pin)) { at91_set_gpio_input(data->detect_pin, 1); at91_set_deglitch(data->detect_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); /* CLK */ @@ -167,15 +167,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); /* configure NANDOE */ diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 7c7d997260..5d43423eb3 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -6,6 +6,7 @@ #include <mach/io.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h" @@ -209,6 +210,11 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio0", &pioAB_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio1", &pioAB_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioCD_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioCD_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -280,30 +286,10 @@ static void __init at91sam9x5_register_clocks(void) } /* -------------------------------------------------------------------- - * GPIO - * -------------------------------------------------------------------- */ - -static struct at91_gpio_bank at91sam9x5_gpio[] = { - { - .regbase = IOMEM(AT91_BASE_PIOA), - .clock = &pioAB_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOB), - .clock = &pioAB_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOC), - .clock = &pioCD_clk, - }, { - .regbase = IOMEM(AT91_BASE_PIOD), - .clock = &pioCD_clk, - } -}; - -/* -------------------------------------------------------------------- * AT91SAM9x5 processor initialization * -------------------------------------------------------------------- */ -static int at91sam9x5_initialize(void) +static void at91sam9x5_initialize(void) { /* Init clock subsystem */ at91_clock_init(AT91_MAIN_CLOCK); @@ -312,7 +298,15 @@ static int at91sam9x5_initialize(void) at91sam9x5_register_clocks(); /* Register GPIO subsystem */ - at91_gpio_init(at91sam9x5_gpio, 4); - return 0; + at91_add_sam9x5_gpio(0, AT91SAM9X5_BASE_PIOA); + at91_add_sam9x5_gpio(1, AT91SAM9X5_BASE_PIOB); + at91_add_sam9x5_gpio(2, AT91SAM9X5_BASE_PIOC); + at91_add_sam9x5_gpio(3, AT91SAM9X5_BASE_PIOD); + + at91_add_pit(AT91SAM9X5_BASE_PIT); + at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9X5_BASE_SMC, 0x200); } -core_initcall(at91sam9x5_initialize); + +AT91_SOC_START(sam9x5) + .init = at91sam9x5_initialize, +AT91_SOC_END diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c index c2b64e9802..e92fa0de21 100644 --- a/arch/arm/mach-at91/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/at91sam9x5_devices.c @@ -44,7 +44,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { - if (data->vbus_pin[i]) + if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], 0); } @@ -137,11 +137,11 @@ void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *da return; /* input/irq */ - if (data->detect_pin) { + if (gpio_is_valid(data->detect_pin)) { at91_set_gpio_input(data->detect_pin, 1); at91_set_deglitch(data->detect_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); if (mmc_id == 0) { /* MCI0 */ @@ -226,15 +226,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) data->pmecc_lookup_table_offset = 0x8000; /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); add_generic_device_res("atmel_nand", 0, nand_resources, @@ -336,7 +336,7 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) cs_pin = pdata->chipselect[i]; /* enable chip-select pin */ - if (cs_pin > 0) + if (gpio_is_valid(cs_pin)) at91_set_gpio_output(cs_pin, 1); } diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index e911270abc..b231ec0789 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -126,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on) value = 0; // REVISIT: Add work-around for AT91RM9200 Errata #26 ? - at91_sys_write(AT91_CKGR_PLLBR, value); + at91_pmc_write(AT91_CKGR_PLLBR, value); do { barrier(); - } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); + } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); } static struct clk pllb = { @@ -145,14 +145,14 @@ static struct clk pllb = { static void pmc_sys_mode(struct clk *clk, int is_on) { if (is_on) - at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); + at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask); else - at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); + at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask); } static void pmc_uckr_mode(struct clk *clk, int is_on) { - unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); + unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR); if (cpu_is_at91sam9g45()) { if (is_on) @@ -163,13 +163,13 @@ static void pmc_uckr_mode(struct clk *clk, int is_on) if (is_on) { is_on = AT91_PMC_LOCKU; - at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); + at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); } else - at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); + at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); do { barrier(); - } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); + } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); } /* USB function clocks (PLLB must be 48 MHz) */ @@ -205,9 +205,9 @@ struct clk mck = { static void pmc_periph_mode(struct clk *clk, int is_on) { if (is_on) - at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); + at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); else - at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); + at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); } static struct clk *at91_css_to_clk(unsigned long css) @@ -352,10 +352,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (actual && actual <= rate) { u32 pckr; - pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); + pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id)); pckr &= css_mask; /* keep clock selection */ pckr |= prescale << prescale_offset; - at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); + at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr); clk->rate_hz = actual; break; } @@ -386,7 +386,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) clk->rate_hz = parent->rate_hz; clk->parent = parent; - at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); + at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id); return 0; } @@ -404,7 +404,7 @@ static void init_programmable_clock(struct clk *clk) else css_mask = AT91_PMC_CSS; - pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); + pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id)); parent = at91_css_to_clk(pckr & css_mask); clk->parent = parent; clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr); @@ -550,14 +550,14 @@ static void at91_pllb_usbfs_clock_init(unsigned long main_clock) if (cpu_is_at91rm9200()) { uhpck.pmc_mask = AT91RM9200_PMC_UHP; udpck.pmc_mask = AT91RM9200_PMC_UDP; - at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); + at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) { uhpck.pmc_mask = AT91SAM926x_PMC_UHP; udpck.pmc_mask = AT91SAM926x_PMC_UDP; } - at91_sys_write(AT91_CKGR_PLLBR, 0); + at91_pmc_write(AT91_CKGR_PLLBR, 0); udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); @@ -574,13 +574,13 @@ static void at91_upll_usbfs_clock_init(unsigned long main_clock) /* Setup divider by 10 to reach 48 MHz */ usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; - at91_sys_write(AT91_PMC_USB, usbr); + at91_pmc_write(AT91_PMC_USB, usbr); /* Now set uhpck values */ uhpck.parent = &utmi_clk; uhpck.pmc_mask = AT91SAM926x_PMC_UHP; uhpck.rate_hz = utmi_clk.rate_hz; - uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); + uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); } static int pll_overclock = 0; @@ -591,6 +591,8 @@ int at91_clock_init(unsigned long main_clock) unsigned tmp, freq, mckr; int i; + + /* * When the bootloader initialized the main oscillator correctly, * there's no problem using the cycle counter. But if it didn't, @@ -599,14 +601,14 @@ int at91_clock_init(unsigned long main_clock) */ if (!main_clock) { do { - tmp = at91_sys_read(AT91_CKGR_MCFR); + tmp = at91_pmc_read(AT91_CKGR_MCFR); } while (!(tmp & AT91_PMC_MAINRDY)); main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); } main_clk.rate_hz = main_clock; /* report if PLLA is more than mildly overclocked */ - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); if (cpu_has_300M_plla()) { if (plla.rate_hz > 300000000) pll_overclock = 1; @@ -625,7 +627,7 @@ int at91_clock_init(unsigned long main_clock) } if (cpu_has_plladiv2()) { - mckr = at91_sys_read(AT91_PMC_MCKR); + mckr = at91_pmc_read(AT91_PMC_MCKR); plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ } @@ -664,7 +666,7 @@ int at91_clock_init(unsigned long main_clock) * MCK and CPU derive from one of those primary clocks. * For now, assume this parentage won't change. */ - mckr = at91_sys_read(AT91_PMC_MCKR); + mckr = at91_pmc_read(AT91_PMC_MCKR); mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); freq = mck.parent->rate_hz; freq /= pmc_prescaler_divider(mckr); /* prescale */ @@ -748,8 +750,8 @@ static int at91_clock_reset(void) pr_debug("Clocks: disable unused %s\n", clk->name); } - at91_sys_write(AT91_PMC_PCDR, pcdr); - at91_sys_write(AT91_PMC_SCDR, scdr); + at91_pmc_write(AT91_PMC_PCDR, pcdr); + at91_pmc_write(AT91_PMC_SCDR, scdr); return 0; } diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 768c91fb06..a19c1c5391 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -10,3 +10,28 @@ /* Clocks */ extern int __init at91_clock_init(unsigned long main_clock); + +static inline struct device_d *at91_add_rm9200_gpio(int id, resource_size_t start) +{ + return add_generic_device("at91rm9200-gpio", id, NULL, start, 512, + IORESOURCE_MEM, NULL); +} + +static inline struct device_d *at91_add_sam9x5_gpio(int id, resource_size_t start) +{ + return add_generic_device("at91sam9x5-gpio", id, NULL, start, 512, + IORESOURCE_MEM, NULL); +} + +static inline struct device_d *at91_add_pit(resource_size_t start) +{ + return add_generic_device("at91-pit", DEVICE_ID_SINGLE, NULL, start, 16, + IORESOURCE_MEM, NULL); +} + +static inline struct device_d *at91_add_sam9_smc(int id, resource_size_t start, + resource_size_t size) +{ + return add_generic_device("at91sam9-smc", id, NULL, start, size, + IORESOURCE_MEM, NULL); +} diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index c35f00e142..10efccfdf7 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -1,6 +1,6 @@ /* - * - * (c) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> + * Copyright (C) 2005 HP Labs + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * * See file CREDITS for list of people who contributed to this * project. @@ -18,148 +18,343 @@ */ #include <common.h> +#include <command.h> +#include <complete.h> #include <linux/clk.h> +#include <linux/err.h> #include <errno.h> #include <io.h> #include <mach/gpio.h> #include <mach/io.h> #include <mach/cpu.h> #include <gpio.h> +#include <init.h> +#include <driver.h> +#include <getopt.h> + +#define MAX_GPIO_BANKS 5 +#define MAX_NB_GPIO_PER_BANK 32 -static int gpio_banks; -static int cpu_has_pio3; -static struct at91_gpio_bank *gpio; +static int gpio_banks = 0; /* * Functionnality can change with newer chips */ +struct at91_gpio_chip { + struct gpio_chip chip; + void __iomem *regbase; /* PIO bank virtual address */ + struct at91_pinctrl_mux_ops *ops; /* ops */ +}; + +#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) + +static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS]; +static inline unsigned pin_to_bank(unsigned pin) +{ + return pin / MAX_NB_GPIO_PER_BANK; +} +static inline unsigned pin_to_bank_offset(unsigned pin) +{ + return pin % MAX_NB_GPIO_PER_BANK; +} -static inline void __iomem *pin_to_controller(unsigned pin) +static inline struct at91_gpio_chip *pin_to_controller(unsigned pin) { - pin -= PIN_BASE; - pin /= 32; + pin /= MAX_NB_GPIO_PER_BANK; if (likely(pin < gpio_banks)) - return gpio[pin].regbase; + return &gpio_chip[pin]; return NULL; } static inline unsigned pin_to_mask(unsigned pin) { - pin -= PIN_BASE; - return 1 << (pin % 32); + return 1 << pin_to_bank_offset(pin); } -/* - * mux the pin to the "GPIO" peripheral role. +/** + * struct at91_pinctrl_mux_ops - describes an At91 mux ops group + * on new IP with support for periph C and D the way to mux in + * periph A and B has changed + * So provide the right call back + * if not present means the IP does not support it + * @get_periph: return the periph mode configured + * @mux_A_periph: mux as periph A + * @mux_B_periph: mux as periph B + * @mux_C_periph: mux as periph C + * @mux_D_periph: mux as periph D + * @set_deglitch: enable/disable deglitch + * @set_debounce: enable/disable debounce + * @set_pulldown: enable/disable pulldown + * @disable_schmitt_trig: disable schmitt trigger */ -int at91_set_GPIO_periph(unsigned pin, int use_pullup) +struct at91_pinctrl_mux_ops { + enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); + void (*mux_A_periph)(void __iomem *pio, unsigned mask); + void (*mux_B_periph)(void __iomem *pio, unsigned mask); + void (*mux_C_periph)(void __iomem *pio, unsigned mask); + void (*mux_D_periph)(void __iomem *pio, unsigned mask); + bool (*get_deglitch)(void __iomem *pio, unsigned pin); + void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on); + bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); + void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div); + bool (*get_pulldown)(void __iomem *pio, unsigned pin); + void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on); + bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); + void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); +}; + +static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - - if (!pio) - return -EINVAL; __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_PER); - return 0; } -EXPORT_SYMBOL(at91_set_GPIO_periph); -/* - * mux the pin to the "A" internal peripheral role. - */ -int at91_set_A_periph(unsigned pin, int use_pullup) +static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); + __raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR)); +} - if (!pio) - return -EINVAL; +static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) +{ + __raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR)); +} - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - if (cpu_has_pio3) { - __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, - pio + PIO_ABCDSR1); - __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, - pio + PIO_ABCDSR2); - } else { - __raw_writel(mask, pio + PIO_ASR); - } - __raw_writel(mask, pio + PIO_PDR); - return 0; +static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) +{ + __raw_writel(mask, pio + PIO_ASR); } -EXPORT_SYMBOL(at91_set_A_periph); -/* - * mux the pin to the "B" internal peripheral role. - */ -int at91_set_B_periph(unsigned pin, int use_pullup) +static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); + __raw_writel(mask, pio + PIO_BSR); +} - if (!pio) - return -EINVAL; +static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) +{ - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - if (cpu_has_pio3) { - __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, - pio + PIO_ABCDSR1); - __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, - pio + PIO_ABCDSR2); + __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, + pio + PIO_ABCDSR1); + __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, + pio + PIO_ABCDSR2); +} + +static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) +{ + __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, + pio + PIO_ABCDSR1); + __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, + pio + PIO_ABCDSR2); +} + +static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) +{ + __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); + __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); +} + +static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) +{ + __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); + __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); +} + +static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) +{ + __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); +} + +static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) +{ + if (is_on) + __raw_writel(mask, pio + PIO_IFSCDR); + at91_mux_set_deglitch(pio, mask, is_on); +} + +static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, + bool is_on, u32 div) +{ + if (is_on) { + __raw_writel(mask, pio + PIO_IFSCER); + __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); + __raw_writel(mask, pio + PIO_IFER); } else { - __raw_writel(mask, pio + PIO_BSR); + __raw_writel(mask, pio + PIO_IFDR); } - __raw_writel(mask, pio + PIO_PDR); - return 0; } -EXPORT_SYMBOL(at91_set_B_periph); -/* - * mux the pin to the "C" internal peripheral role. - */ -int at91_set_C_periph(unsigned pin, int use_pullup) +static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); + __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); +} - if (!pio || !cpu_has_pio3) - return -EINVAL; +static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) +{ + __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); +} - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); - __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); +#ifdef CONFIG_CMD_AT91MUX +static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) +{ + return (__raw_readl(pio + PIO_PUSR) >> pin) & 0x1; +} + +static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) +{ + return (__raw_readl(pio + PIO_MDSR) >> pin) & 0x1; +} + +static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) +{ + unsigned select; + + if (__raw_readl(pio + PIO_PSR) & mask) + return AT91_MUX_GPIO; + + select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask); + select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1); + + return select + 1; +} + +static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) +{ + unsigned select; + + if (__raw_readl(pio + PIO_PSR) & mask) + return AT91_MUX_GPIO; + + select = __raw_readl(pio + PIO_ABSR) & mask; + + return select + 1; +} + +static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) +{ + return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; +} + +static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) +{ + *div = __raw_readl(pio + PIO_SCDR); + + return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1; +} + +static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) +{ + return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1; +} + +static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) +{ + return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; +} +#else +#define at91_mux_get_periph NULL +#define at91_mux_pio3_get_periph NULL +#define at91_mux_get_deglitch NULL +#define at91_mux_pio3_get_debounce NULL +#define at91_mux_pio3_get_pulldown NULL +#define at91_mux_pio3_get_schmitt_trig NULL +#endif + +static struct at91_pinctrl_mux_ops at91rm9200_ops = { + .get_periph = at91_mux_get_periph, + .mux_A_periph = at91_mux_set_A_periph, + .mux_B_periph = at91_mux_set_B_periph, + .get_deglitch = at91_mux_get_deglitch, + .set_deglitch = at91_mux_set_deglitch, +}; + +static struct at91_pinctrl_mux_ops at91sam9x5_ops = { + .get_periph = at91_mux_pio3_get_periph, + .mux_A_periph = at91_mux_pio3_set_A_periph, + .mux_B_periph = at91_mux_pio3_set_B_periph, + .mux_C_periph = at91_mux_pio3_set_C_periph, + .mux_D_periph = at91_mux_pio3_set_D_periph, + .get_deglitch = at91_mux_get_deglitch, + .set_deglitch = at91_mux_pio3_set_deglitch, + .get_debounce = at91_mux_pio3_get_debounce, + .set_debounce = at91_mux_pio3_set_debounce, + .get_pulldown = at91_mux_pio3_get_pulldown, + .set_pulldown = at91_mux_pio3_set_pulldown, + .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, + .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, +}; + +static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) +{ __raw_writel(mask, pio + PIO_PDR); - return 0; } -EXPORT_SYMBOL(at91_set_C_periph); -/* - * mux the pin to the "C" internal peripheral role. - */ -int at91_set_D_periph(unsigned pin, int use_pullup) +static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); + __raw_writel(mask, pio + PIO_PER); +} - if (!pio || !cpu_has_pio3) +static void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input) +{ + __raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER)); +} + +int at91_mux_pin(unsigned pin, enum at91_mux mux, int use_pullup) +{ + struct at91_gpio_chip *at91_gpio = pin_to_controller(pin); + void __iomem *pio = at91_gpio->regbase; + unsigned mask = pin_to_mask(pin); + int bank = pin_to_bank(pin); + struct device_d *dev = at91_gpio->chip.dev; + + if (!at91_gpio) return -EINVAL; - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); - __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); - __raw_writel(mask, pio + PIO_PDR); + pio = at91_gpio->regbase; + if (!pio) + return -EINVAL; + + at91_mux_disable_interrupt(pio, mask); + + pin %= MAX_NB_GPIO_PER_BANK; + if (mux) { + dev_dbg(dev, "pio%c%d configured as periph%c with pullup = %d\n", + bank + 'A', pin, mux - 1 + 'A', use_pullup); + } else { + dev_dbg(dev, "pio%c%d configured as gpio with pullup = %d\n", + bank + 'A', pin, use_pullup); + } + + switch(mux) { + case AT91_MUX_GPIO: + at91_mux_gpio_enable(pio, mask); + break; + case AT91_MUX_PERIPH_A: + at91_gpio->ops->mux_A_periph(pio, mask); + break; + case AT91_MUX_PERIPH_B: + at91_gpio->ops->mux_B_periph(pio, mask); + break; + case AT91_MUX_PERIPH_C: + if (!at91_gpio->ops->mux_C_periph) + return -EINVAL; + at91_gpio->ops->mux_C_periph(pio, mask); + break; + case AT91_MUX_PERIPH_D: + if (!at91_gpio->ops->mux_D_periph) + return -EINVAL; + at91_gpio->ops->mux_D_periph(pio, mask); + break; + } + if (mux) + at91_mux_gpio_disable(pio, mask); + + if (use_pullup >= 0) + at91_mux_set_pullup(pio, mask, use_pullup); + return 0; } -EXPORT_SYMBOL(at91_set_D_periph); +EXPORT_SYMBOL(at91_mux_pin); /* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and @@ -167,19 +362,22 @@ EXPORT_SYMBOL(at91_set_D_periph); */ int at91_set_gpio_input(unsigned pin, int use_pullup) { - void __iomem *pio = pin_to_controller(pin); + struct at91_gpio_chip *at91_gpio = pin_to_controller(pin); + void __iomem *pio = at91_gpio->regbase; unsigned mask = pin_to_mask(pin); + int ret; - if (!pio) - return -EINVAL; + ret = at91_mux_pin(pin, AT91_MUX_GPIO, use_pullup); + if (ret) + return ret; + + dev_dbg(at91_gpio->chip.dev, "pio%c%d configured as input\n", + pin_to_bank(pin) + 'A', pin_to_bank_offset(pin)); + + at91_mux_gpio_input(pio, mask, true); - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); - __raw_writel(mask, pio + PIO_ODR); - __raw_writel(mask, pio + PIO_PER); return 0; } -EXPORT_SYMBOL(at91_set_gpio_input); /* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), @@ -187,17 +385,20 @@ EXPORT_SYMBOL(at91_set_gpio_input); */ int at91_set_gpio_output(unsigned pin, int value) { - void __iomem *pio = pin_to_controller(pin); + struct at91_gpio_chip *at91_gpio = pin_to_controller(pin); + void __iomem *pio = at91_gpio->regbase; unsigned mask = pin_to_mask(pin); + int ret; - if (!pio) - return -EINVAL; + ret = at91_mux_pin(pin, AT91_MUX_GPIO, -1); + if (ret) + return ret; - __raw_writel(mask, pio + PIO_IDR); - __raw_writel(mask, pio + PIO_PUDR); + dev_dbg(at91_gpio->chip.dev, "pio%c%d configured as output val = %d\n", + pin_to_bank(pin) + 'A', pin_to_bank_offset(pin), value); + + at91_mux_gpio_input(pio, mask, false); __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); - __raw_writel(mask, pio + PIO_OER); - __raw_writel(mask, pio + PIO_PER); return 0; } EXPORT_SYMBOL(at91_set_gpio_output); @@ -207,15 +408,14 @@ EXPORT_SYMBOL(at91_set_gpio_output); */ int at91_set_deglitch(unsigned pin, int is_on) { - void __iomem *pio = pin_to_controller(pin); + struct at91_gpio_chip *at91_gpio = pin_to_controller(pin); + void __iomem *pio = at91_gpio->regbase; unsigned mask = pin_to_mask(pin); if (!pio) return -EINVAL; - if (cpu_has_pio3 && is_on) - __raw_writel(mask, pio + PIO_IFSCDR); - __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); + at91_gpio->ops->set_deglitch(pio, mask, is_on); return 0; } EXPORT_SYMBOL(at91_set_deglitch); @@ -225,19 +425,14 @@ EXPORT_SYMBOL(at91_set_deglitch); */ int at91_set_debounce(unsigned pin, int is_on, int div) { - void __iomem *pio = pin_to_controller(pin); + struct at91_gpio_chip *at91_gpio = pin_to_controller(pin); + void __iomem *pio = at91_gpio->regbase; unsigned mask = pin_to_mask(pin); - if (!pio || !cpu_has_pio3) + if (!pio || !at91_gpio->ops->set_debounce) return -EINVAL; - if (is_on) { - __raw_writel(mask, pio + PIO_IFSCER); - __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); - __raw_writel(mask, pio + PIO_IFER); - } else { - __raw_writel(mask, pio + PIO_IFDR); - } + at91_gpio->ops->set_debounce(pio, mask, is_on, div); return 0; } EXPORT_SYMBOL(at91_set_debounce); @@ -248,13 +443,14 @@ EXPORT_SYMBOL(at91_set_debounce); */ int at91_set_multi_drive(unsigned pin, int is_on) { - void __iomem *pio = pin_to_controller(pin); + struct at91_gpio_chip *at91_gpio = pin_to_controller(pin); + void __iomem *pio = at91_gpio->regbase; unsigned mask = pin_to_mask(pin); if (!pio) return -EINVAL; - __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); + at91_mux_set_multidrive(pio, mask, is_on); return 0; } EXPORT_SYMBOL(at91_set_multi_drive); @@ -265,15 +461,16 @@ EXPORT_SYMBOL(at91_set_multi_drive); */ int at91_set_pulldown(unsigned pin, int is_on) { - void __iomem *pio = pin_to_controller(pin); + struct at91_gpio_chip *at91_gpio = pin_to_controller(pin); + void __iomem *pio = at91_gpio->regbase; unsigned mask = pin_to_mask(pin); - if (!pio || !cpu_has_pio3) + if (!pio || !at91_gpio->ops->set_pulldown) return -EINVAL; /* Disable pull-up anyway */ - __raw_writel(mask, pio + PIO_PUDR); - __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); + at91_mux_set_pullup(pio, mask, 0); + at91_gpio->ops->set_pulldown(pio, mask, is_on); return 0; } EXPORT_SYMBOL(at91_set_pulldown); @@ -283,88 +480,303 @@ EXPORT_SYMBOL(at91_set_pulldown); */ int at91_disable_schmitt_trig(unsigned pin) { - void __iomem *pio = pin_to_controller(pin); + struct at91_gpio_chip *at91_gpio = pin_to_controller(pin); + void __iomem *pio = at91_gpio->regbase; unsigned mask = pin_to_mask(pin); - if (!pio || !cpu_has_pio3) + if (!pio || !at91_gpio->ops->disable_schmitt_trig) return -EINVAL; - __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); + at91_gpio->ops->disable_schmitt_trig(pio, mask); return 0; } EXPORT_SYMBOL(at91_disable_schmitt_trig); -/* - * assuming the pin is muxed as a gpio output, set its value. - */ -int at91_set_gpio_value(unsigned pin, int value) +#ifdef CONFIG_CMD_AT91MUX +static void at91mux_printf_mode(unsigned bank, unsigned pin) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); + struct at91_gpio_chip *at91_gpio = &gpio_chip[bank]; + void __iomem *pio = at91_gpio->regbase; + enum at91_mux mode; + u32 pdsr; + + unsigned mask = pin_to_mask(pin); + + mode = at91_gpio->ops->get_periph(pio, mask); + + if (mode == AT91_MUX_GPIO) { + pdsr = __raw_readl(pio + PIO_PDSR); + + printf("[gpio] %s", pdsr & mask ? "set" : "clear"); + } else { + printf("[periph %c]", mode + 'A' - 1); + } +} + +static void at91mux_dump_config(void) +{ + int bank, j; + + /* print heading */ + printf("Pin\t"); + for (bank = 0; bank < gpio_banks; bank++) { + printf("PIO%c\t\t", 'A' + bank); + }; + printf("\n\n"); + + /* print pin status */ + for (j = 0; j < 32; j++) { + printf("%i:\t", j); + + for (bank = 0; bank < gpio_banks; bank++) { + at91mux_printf_mode(bank, j); + + printf("\t"); + } + + printf("\n"); + } +} + +static void at91mux_print_en_disable(const char *str, bool is_on) +{ + printf("%s = ", str); + + if (is_on) + printf("enable\n"); + else + printf("disable\n"); +} + +static void at91mux_dump_pio_config(unsigned bank, unsigned pin) +{ + struct at91_gpio_chip *at91_gpio = &gpio_chip[bank]; + void __iomem *pio = at91_gpio->regbase; + u32 div; + + printf("pio%c%d configuration\n\n", bank + 'A', pin); + + at91mux_printf_mode(bank, pin); + printf("\n"); + + at91mux_print_en_disable("multidrive", + at91_mux_get_multidrive(pio, pin)); + + at91mux_print_en_disable("pullup", + at91_mux_get_pullup(pio, pin)); + + if (at91_gpio->ops->get_deglitch) + at91mux_print_en_disable("degitch", + at91_gpio->ops->get_deglitch(pio, pin)); + + if (at91_gpio->ops->get_debounce) { + printf("debounce = "); + if (at91_gpio->ops->get_debounce(pio, pin, &div)) + printf("enable at %d\n", div); + else + printf("disable\n"); + } + + if (at91_gpio->ops->get_pulldown) + at91mux_print_en_disable("pulldown", + at91_gpio->ops->get_pulldown(pio, pin)); + + if (at91_gpio->ops->get_schmitt_trig) + at91mux_print_en_disable("schmitt trigger", + !at91_gpio->ops->get_schmitt_trig(pio, pin)); +} + +static int do_at91mux(int argc, char *argv[]) +{ + int opt; + unsigned bank = 0; + unsigned pin = 0; + + if (argc < 2) { + at91mux_dump_config(); + return 0; + } + + while ((opt = getopt(argc, argv, "b:p:")) > 0) { + switch (opt) { + case 'b': + bank = simple_strtoul(optarg, NULL, 10); + break; + case 'p': + pin = simple_strtoul(optarg, NULL, 10); + break; + } + } + + if (bank >= gpio_banks) { + printf("bank %c >= supported %c banks\n", bank + 'A', + gpio_banks + 'A'); + return 1; + } + + if (pin >= 32) { + printf("pin %d >= supported %d pins\n", pin, 32); + return 1; + } + + at91mux_dump_pio_config(bank, pin); - if (!pio) - return -EINVAL; - __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); return 0; } -EXPORT_SYMBOL(at91_set_gpio_value); -/* - * read the pin's value (works even if it's not muxed as a gpio). - */ -int at91_get_gpio_value(unsigned pin) +BAREBOX_CMD_HELP_START(at91mux) +BAREBOX_CMD_HELP_USAGE("at91mux [-p <pin> -b <bank>]\n") +BAREBOX_CMD_HELP_SHORT("dump current mux configuration if bank/pin specified dump pin details\n"); +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(at91mux) + .cmd = do_at91mux, + .usage = "dump current mux configuration", + BAREBOX_CMD_HELP(cmd_at91mux_help) + BAREBOX_CMD_COMPLETE(empty_complete) +BAREBOX_CMD_END +#endif +/*--------------------------------------------------------------------------*/ + +static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); - u32 pdsr; + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + unsigned mask = 1 << offset; + u32 pdsr; - if (!pio) - return -EINVAL; pdsr = __raw_readl(pio + PIO_PDSR); return (pdsr & mask) != 0; } -EXPORT_SYMBOL(at91_get_gpio_value); -int gpio_direction_input(unsigned pin) +static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + unsigned mask = 1 << offset; - if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) - return -EINVAL; - __raw_writel(mask, pio + PIO_ODR); - return 0; + __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); } -EXPORT_SYMBOL(gpio_direction_input); -int gpio_direction_output(unsigned pin, int value) +static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) { - void __iomem *pio = pin_to_controller(pin); - unsigned mask = pin_to_mask(pin); + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + unsigned mask = 1 << offset; - if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) - return -EINVAL; __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); __raw_writel(mask, pio + PIO_OER); + return 0; } -EXPORT_SYMBOL(gpio_direction_output); -/*--------------------------------------------------------------------------*/ +static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + unsigned mask = 1 << offset; + + __raw_writel(mask, pio + PIO_ODR); + + return 0; +} -int at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) +static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) { - unsigned i; + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + unsigned mask = 1 << offset; + + dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, + 'A' + pin_to_bank(chip->base), offset, chip->base + offset); + at91_mux_gpio_enable(pio, mask); + + return 0; +} - gpio = data; - gpio_banks = nr_banks; +static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, + 'A' + pin_to_bank(chip->base), offset, chip->base + offset); +} - for (i = 0; i < nr_banks; i++, data++) { - /* enable PIO controller's clock */ - clk_enable(data->clock); +static struct gpio_ops at91_gpio_ops = { + .request = at91_gpio_request, + .free = at91_gpio_free, + .direction_input = at91_gpio_direction_input, + .direction_output = at91_gpio_direction_output, + .get = at91_gpio_get, + .set = at91_gpio_set, +}; + +static int at91_gpio_probe(struct device_d *dev) +{ + struct at91_gpio_chip *at91_gpio; + struct clk *clk; + int ret; + + BUG_ON(dev->id > MAX_GPIO_BANKS); + + at91_gpio = &gpio_chip[dev->id]; + + ret = dev_get_drvdata(dev, (unsigned long *)&at91_gpio->ops); + if (ret) { + dev_err(dev, "dev_get_drvdata failed: %d\n", ret); + return ret; + } + + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(dev, "clock not found: %d\n", ret); + return ret; } - cpu_has_pio3 = cpu_is_at91sam9x5() || cpu_is_at91sam9n12(); + ret = clk_enable(clk); + if (ret < 0) { + dev_err(dev, "clock failed to enable: %d\n", ret); + clk_put(clk); + return ret; + } + + gpio_banks = max(gpio_banks, dev->id + 1); + at91_gpio->regbase = dev_request_mem_region(dev, 0); + + at91_gpio->chip.ops = &at91_gpio_ops; + at91_gpio->chip.ngpio = MAX_NB_GPIO_PER_BANK; + at91_gpio->chip.dev = dev; + at91_gpio->chip.base = dev->id * MAX_NB_GPIO_PER_BANK; + + ret = gpiochip_add(&at91_gpio->chip); + if (ret) { + dev_err(dev, "couldn't add gpiochip, ret = %d\n", ret); + return ret; + } return 0; } + +static struct platform_device_id at91_gpio_ids[] = { + { + .name = "at91rm9200-gpio", + .driver_data = (unsigned long)&at91rm9200_ops, + }, { + .name = "at91sam9x5-gpio", + .driver_data = (unsigned long)&at91sam9x5_ops, + }, { + /* sentinel */ + }, +}; + +static struct driver_d at91_gpio_driver = { + .name = "at91-gpio", + .probe = at91_gpio_probe, + .id_table = at91_gpio_ids, +}; + +static int at91_gpio_init(void) +{ + return platform_driver_register(&at91_gpio_driver); +} +postcore_initcall(at91_gpio_init); diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h index 6dcaa77168..3b5948566e 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h @@ -16,22 +16,22 @@ #ifndef AT91_DBGU_H #define AT91_DBGU_H -#ifdef AT91_DBGU -#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ -#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ -#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ +#if !defined(CONFIG_ARCH_AT91X40) +#define AT91_DBGU_CR (0x00) /* Control Register */ +#define AT91_DBGU_MR (0x04) /* Mode Register */ +#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ -#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ -#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ -#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ -#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ -#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ -#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ +#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */ +#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */ +#define AT91_DBGU_SR (0x14) /* Status Register */ +#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */ +#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ +#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */ -#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ -#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ -#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ +#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */ +#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */ +#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ #endif /* AT91_DBGU */ diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h index 94dd242a5f..8581efacb9 100644 --- a/arch/arm/mach-at91/include/mach/at91_pit.h +++ b/arch/arm/mach-at91/include/mach/at91_pit.h @@ -16,16 +16,16 @@ #ifndef AT91_PIT_H #define AT91_PIT_H -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ +#define AT91_PIT_MR 0x00 /* Mode Register */ #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ +#define AT91_PIT_SR 0x04 /* Status Register */ #define AT91_PIT_PITS (1 << 0) /* Timer Status */ -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ +#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */ +#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */ #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 59037cf946..6fcbf40729 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -16,10 +16,16 @@ #ifndef AT91_PMC_H #define AT91_PMC_H -#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ -#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ +#define at91_pmc_read(field) \ + __raw_readl(AT91_PMC + field) -#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#define at91_pmc_write(field, value) \ + __raw_writel(value, AT91_PMC + field) + +#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ +#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ + +#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ @@ -35,17 +41,17 @@ #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ -#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ +#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ +#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ +#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ +#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ +#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ @@ -54,12 +60,12 @@ #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ -#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ -#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ -#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ +#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ #define AT91_PMC_DIV (0xff << 0) /* Divider */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ @@ -71,7 +77,7 @@ #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ -#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#define AT91_PMC_MCKR 0x30 /* Master Clock Register */ #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ #define AT91_PMC_CSS_SLOW (0 << 0) #define AT91_PMC_CSS_MAIN (1 << 0) @@ -113,27 +119,27 @@ #define AT91_PMC_PLLADIV2_OFF (0 << 12) #define AT91_PMC_PLLADIV2_ON (1 << 12) -#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ +#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ #define AT91_PMC_USBS_PLLA (0 << 0) #define AT91_PMC_USBS_UPLL (1 << 0) #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ -#define AT91_PMC_SMD (AT91_PMC + 0x3c) /* Soft Modem Clock Register [some SAM9 only] */ +#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ #define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ #define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ #define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ +#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ #define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ #define AT91_PMC_CSSMCK_CSS (0 << 8) #define AT91_PMC_CSSMCK_MCK (1 << 8) -#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ -#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ -#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ +#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ +#define AT91_PMC_SR 0x68 /* Status Register */ #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ @@ -146,14 +152,14 @@ #define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ -#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ +#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ -#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ #define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ #define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ -#define AT91_PMC_WPSR (AT91_PMC + 0xe8) /* Write Protect Status Register [some SAM9] */ +#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index 7e18537cfb..36d37b9d2d 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -17,11 +17,11 @@ #ifndef AT91_WDT_H #define AT91_WDT_H -#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ +#define AT91_WDT_CR 0x00 /* Watchdog Control Register */ #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ -#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ +#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ @@ -31,7 +31,7 @@ #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ -#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ +#define AT91_WDT_SR 0x08 /* Watchdog Status Register */ #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index 2850f0d73c..36e940d928 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h @@ -78,21 +78,31 @@ #define AT91RM9200_BASE_SPI 0xfffe0000 #define AT91_BASE_SYS 0xfffff000 +/* + * System Peripherals + */ +#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ +#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ +#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ +#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ +#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ +#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */ +#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ +#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ + /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ -#define AT91_BASE_PIOA 0xfffff400 /* PIO Controller A */ -#define AT91_BASE_PIOB 0xfffff600 /* PIO Controller B */ -#define AT91_BASE_PIOC 0xfffff800 /* PIO Controller C */ -#define AT91_BASE_PIOD 0xfffffa00 /* PIO Controller D */ +#define AT91_BASE_PIOA AT91RM9200_BASE_PIOA /* PIO Controller A */ +#define AT91_BASE_PIOB AT91RM9200_BASE_PIOB /* PIO Controller B */ +#define AT91_BASE_PIOC AT91RM9200_BASE_PIOC /* PIO Controller C */ +#define AT91_BASE_PIOD AT91RM9200_BASE_PIOD /* PIO Controller D */ #define AT91_USART0 AT91RM9200_BASE_US0 #define AT91_USART1 AT91RM9200_BASE_US1 diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index be07e57267..3f3a0e1a54 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -78,26 +78,39 @@ #define AT91_BASE_SYS 0xffffe800 /* + * System Peripherals + */ +#define AT91SAM9260_BASE_ECC 0xffffe800 +#define AT91SAM9260_BASE_SDRAMC 0xffffea00 +#define AT91SAM9260_BASE_SMC 0xffffec00 +#define AT91SAM9260_BASE_MATRIX 0xffffee00 +#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 +#define AT91SAM9260_BASE_PIOA 0xfffff400 +#define AT91SAM9260_BASE_PIOB 0xfffff600 +#define AT91SAM9260_BASE_PIOC 0xfffff800 +#define AT91SAM9260_BASE_RSTC 0xfffffd00 +#define AT91SAM9260_BASE_SHDWC 0xfffffd10 +#define AT91SAM9260_BASE_RTT 0xfffffd20 +#define AT91SAM9260_BASE_PIT 0xfffffd30 +#define AT91SAM9260_BASE_WDT 0xfffffd40 +#define AT91SAM9260_BASE_GPBR 0xfffffd50 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91_BASE_PIOA 0xfffff400 -#define AT91_BASE_PIOB 0xfffff600 -#define AT91_BASE_PIOC 0xfffff800 + +#define AT91_BASE_WDT AT91SAM9260_BASE_WDT +#define AT91_BASE_SMC AT91SAM9260_BASE_SMC +#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA +#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9260_BASE_PIOC #define AT91_USART0 AT91SAM9260_BASE_US0 #define AT91_USART1 AT91SAM9260_BASE_US1 diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index d51673eab6..1b48e230b4 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -66,24 +66,36 @@ /* + * System Peripherals + */ +#define AT91SAM9261_BASE_SMC 0xffffec00 +#define AT91SAM9261_BASE_MATRIX 0xffffee00 +#define AT91SAM9261_BASE_SDRAMC 0xffffea00 +#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 +#define AT91SAM9261_BASE_PIOA 0xfffff400 +#define AT91SAM9261_BASE_PIOB 0xfffff600 +#define AT91SAM9261_BASE_PIOC 0xfffff800 +#define AT91SAM9261_BASE_RSTC 0xfffffd00 +#define AT91SAM9261_BASE_SHDWC 0xfffffd10 +#define AT91SAM9261_BASE_RTT 0xfffffd20 +#define AT91SAM9261_BASE_PIT 0xfffffd30 +#define AT91SAM9261_BASE_WDT 0xfffffd40 +#define AT91SAM9261_BASE_GPBR 0xfffffd50 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91_BASE_PIOA 0xfffff400 -#define AT91_BASE_PIOB 0xfffff600 -#define AT91_BASE_PIOC 0xfffff800 + +#define AT91_BASE_WDT AT91SAM9261_BASE_WDT +#define AT91_BASE_SMC AT91SAM9261_BASE_SMC +#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9261_BASE_PIOC #define AT91_USART0 AT91SAM9261_BASE_US0 #define AT91_USART1 AT91SAM9261_BASE_US1 diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index c8374a7e58..b42d191b99 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -74,40 +74,54 @@ #define AT91SAM9263_BASE_2DGE 0xfffc8000 #define AT91_BASE_SYS 0xffffe000 + +/* + * System Peripherals + */ +#define AT91SAM9263_BASE_ECC0 0xffffe000 +#define AT91SAM9263_BASE_SDRAMC0 0xffffe200 +#define AT91SAM9263_BASE_SMC0 0xffffe400 +#define AT91SAM9263_BASE_ECC1 0xffffe600 +#define AT91SAM9263_BASE_SDRAMC1 0xffffe800 +#define AT91SAM9263_BASE_SMC1 0xffffea00 +#define AT91SAM9263_BASE_MATRIX 0xffffec00 +#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 +#define AT91SAM9263_BASE_PIOA 0xfffff200 +#define AT91SAM9263_BASE_PIOB 0xfffff400 +#define AT91SAM9263_BASE_PIOC 0xfffff600 +#define AT91SAM9263_BASE_PIOD 0xfffff800 +#define AT91SAM9263_BASE_PIOE 0xfffffa00 +#define AT91SAM9263_BASE_RSTC 0xfffffd00 +#define AT91SAM9263_BASE_SHDWC 0xfffffd10 +#define AT91SAM9263_BASE_RTT0 0xfffffd20 +#define AT91SAM9263_BASE_PIT 0xfffffd30 +#define AT91SAM9263_BASE_WDT 0xfffffd40 +#define AT91SAM9263_BASE_RTT1 0xfffffd50 +#define AT91SAM9263_BASE_GPBR 0xfffffd60 + /* * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) -#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) - -#define AT91_BASE_PIOA 0xfffff200 -#define AT91_BASE_PIOB 0xfffff400 -#define AT91_BASE_PIOC 0xfffff600 -#define AT91_BASE_PIOD 0xfffff800 -#define AT91_BASE_PIOE 0xfffffa00 + +#define AT91_BASE_WDT AT91SAM9263_BASE_WDT +#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0 +#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9263_BASE_PIOC +#define AT91_BASE_PIOD AT91SAM9263_BASE_PIOD +#define AT91_BASE_PIOE AT91SAM9263_BASE_PIOE #define AT91_USART0 AT91SAM9263_BASE_US0 #define AT91_USART1 AT91SAM9263_BASE_US1 #define AT91_USART2 AT91SAM9263_BASE_US2 #define AT91_NB_USART 4 -#define AT91_SMC AT91_SMC0 #define AT91_SDRAMC AT91_SDRAMC0 #define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h index d64511b36d..d5cf5f762d 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h @@ -16,7 +16,42 @@ #ifndef AT91SAM9_SMC_H #define AT91SAM9_SMC_H -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ +#define at91_smc_read(id, field) \ + __raw_readl(AT91_BASE_SMC + ((id) * 0x10) + field) + +#define at91_smc_write(id, field, value) \ + __raw_writel(value, AT91_BASE_SMC + ((id) * 0x10) + field) + +#ifndef __ASSEMBLY__ +struct sam9_smc_config { + /* Setup register */ + u8 ncs_read_setup; + u8 nrd_setup; + u8 ncs_write_setup; + u8 nwe_setup; + + /* Pulse register */ + u8 ncs_read_pulse; + u8 nrd_pulse; + u8 ncs_write_pulse; + u8 nwe_pulse; + + /* Cycle register */ + u16 read_cycle; + u16 write_cycle; + + /* Mode register */ + u32 mode; + u8 tdf_cycles:4; +}; + +extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); +extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); +extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); +extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); +#endif + +#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ #define AT91_SMC_NWESETUP_(x) ((x) << 0) #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ @@ -26,7 +61,7 @@ #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ +#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */ #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ #define AT91_SMC_NWEPULSE_(x) ((x) << 0) #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ @@ -36,13 +71,13 @@ #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ +#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */ #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ #define AT91_SMC_NWECYCLE_(x) ((x) << 0) #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ +#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */ #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ @@ -66,11 +101,4 @@ #define AT91_SMC_PS_16 (2 << 28) #define AT91_SMC_PS_32 (3 << 28) -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#endif - #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 10f31703b7..c81bb80c53 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -87,30 +87,46 @@ #define AT91_BASE_SYS 0xffffe200 /* + * System Peripherals + */ +#define AT91SAM9G45_BASE_ECC 0xffffe200 +#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400 +#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600 +#define AT91SAM9G45_BASE_DMA 0xffffec00 +#define AT91SAM9G45_BASE_SMC 0xffffe800 +#define AT91SAM9G45_BASE_MATRIX 0xffffea00 +#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 +#define AT91SAM9G45_BASE_PIOA 0xfffff200 +#define AT91SAM9G45_BASE_PIOB 0xfffff400 +#define AT91SAM9G45_BASE_PIOC 0xfffff600 +#define AT91SAM9G45_BASE_PIOD 0xfffff800 +#define AT91SAM9G45_BASE_PIOE 0xfffffa00 +#define AT91SAM9G45_BASE_RSTC 0xfffffd00 +#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 +#define AT91SAM9G45_BASE_RTT 0xfffffd20 +#define AT91SAM9G45_BASE_PIT 0xfffffd30 +#define AT91SAM9G45_BASE_WDT 0xfffffd40 +#define AT91SAM9G45_BASE_RTC 0xfffffdb0 +#define AT91SAM9G45_BASE_GPBR 0xfffffd60 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) -#define AT91_BASE_PIOA 0xfffff200 -#define AT91_BASE_PIOB 0xfffff400 -#define AT91_BASE_PIOC 0xfffff600 -#define AT91_BASE_PIOD 0xfffff800 -#define AT91_BASE_PIOE 0xfffffa00 +#define AT91_BASE_WDT AT91SAM9G45_BASE_WDT +#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC +#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOC +#define AT91_BASE_PIOD AT91SAM9G45_BASE_PIOD +#define AT91_BASE_PIOE AT91SAM9G45_BASE_PIOE #define AT91_USART0 AT91SAM9G45_BASE_US0 #define AT91_USART1 AT91SAM9G45_BASE_US1 diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h index dcbdb1b694..26bdd13498 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h +++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h @@ -82,29 +82,46 @@ #define AT91_BASE_SYS 0xffffc000 /* + * System Peripherals + */ +#define AT91SAM9N12_BASE_FUSE 0xffffdc00 +#define AT91SAM9N12_BASE_MATRIX 0xffffde00 +#define AT91SAM9N12_BASE_PMECC 0xffffe000 +#define AT91SAM9N12_BASE_PMERRLOC 0xffffe600 +#define AT91SAM9N12_BASE_DDRSDRC0 0xffffe800 +#define AT91SAM9N12_BASE_SMC 0xffffea00 +#define AT91SAM9N12_BASE_DMA 0xffffec00 +#define AT91SAM9N12_BASE_AIC 0xfffff000 +#define AT91SAM9N12_BASE_DBGU 0xfffff200 +#define AT91SAM9N12_BASE_PIOA 0xfffff400 +#define AT91SAM9N12_BASE_PIOB 0xfffff600 +#define AT91SAM9N12_BASE_PIOC 0xfffff800 +#define AT91SAM9N12_BASE_PIOD 0xfffffa00 +#define AT91SAM9N12_BASE_PMC 0xfffffc00 +#define AT91SAM9N12_BASE_RSTC 0xfffffe00 +#define AT91SAM9N12_BASE_SHDWC 0xfffffe10 +#define AT91SAM9N12_BASE_PIT 0xfffffe30 +#define AT91SAM9N12_BASE_WDT 0xfffffe40 +#define AT91SAM9N12_BASE_GPBR 0xfffffe60 +#define AT91SAM9N12_BASE_RTC 0xfffffeb0 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_FUSE (0xffffdc00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS) #define AT91_PMECC (0xffffe000 - AT91_BASE_SYS) #define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS) #define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffeb0 - AT91_BASE_SYS) -#define AT91_BASE_PIOA 0xfffff400 -#define AT91_BASE_PIOB 0xfffff600 -#define AT91_BASE_PIOC 0xfffff800 -#define AT91_BASE_PIOD 0xfffffa00 +#define AT91_BASE_WDT AT91SAM9N12_BASE_WDT +#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC +#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC +#define AT91_BASE_PIOD AT91SAM9N12_BASE_PIOD #define AT91_USART0 AT91SAM9X5_BASE_US0 #define AT91_USART1 AT91SAM9X5_BASE_US1 diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 22407102cf..13b4f44379 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -89,29 +89,46 @@ #define AT91_BASE_SYS 0xffffc000 /* + * System Peripherals + */ +#define AT91SAM9X5_BASE_MATRIX 0xffffde00 +#define AT9SAM9X5_BASE1_PMECC 0xffffe000 +#define AT91SAM9X5_BASE_PMERRLOC 0xffffe600 +#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 +#define AT91SAM9X5_BASE_SMC 0xffffea00 +#define AT91SAM9X5_BASE_DMA0 0xffffec00 +#define AT91SAM9X5_BASE_DMA1 0xffffee00 +#define AT91SAM9X5_BASE_AIC 0xfffff000 +#define AT91SAM9X5_BASE_DBGU 0xfffff200 +#define AT91SAM9X5_BASE_PIOA 0xfffff400 +#define AT91SAM9X5_BASE_PIOB 0xfffff600 +#define AT91SAM9X5_BASE_PIOC 0xfffff800 +#define AT91SAM9X5_BASE_PIOD 0xfffffa00 +#define AT91SAM9X5_BASE_PMC 0xfffffc00 +#define AT91SAM9X5_BASE_RSTC 0xfffffe00 +#define AT91SAM9X5_BASE_SHDWC 0xfffffe10 +#define AT91SAM9X5_BASE_PIT 0xfffffe30 +#define AT91SAM9X5_BASE_WDT 0xfffffe40 +#define AT91SAM9X5_BASE_GPBR 0xfffffe60 +#define AT91SAM9X5_BASE_RTC 0xfffffeb0 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS) #define AT91_PMECC (0xffffe000 - AT91_BASE_SYS) #define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA0 (0xffffec00 - AT91_BASE_SYS) -#define AT91_DMA1 (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS) #define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffeb0 - AT91_BASE_SYS) -#define AT91_BASE_PIOA 0xfffff400 -#define AT91_BASE_PIOB 0xfffff600 -#define AT91_BASE_PIOC 0xfffff800 -#define AT91_BASE_PIOD 0xfffffa00 +#define AT91_BASE_WDT AT91SAM9X5_BASE_WDT +#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC +#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOC +#define AT91_BASE_PIOD AT91SAM9X5_BASE_PIOD #define AT91_USART0 AT91SAM9X5_BASE_US0 #define AT91_USART1 AT91SAM9X5_BASE_US1 diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index d4a3e3b78d..b18f1c0a3d 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -28,7 +28,7 @@ /* USB Host */ struct at91_usbh_data { u8 ports; /* number of ports on root hub */ - u8 vbus_pin[2]; /* port power-control pin */ + int vbus_pin[2]; /* port power-control pin */ }; extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data); @@ -46,9 +46,9 @@ extern void __init at91_add_device_udc(struct at91_udc_data *data); /* NAND / SmartMedia */ struct atmel_nand_data { - u8 enable_pin; /* chip enable */ - u8 det_pin; /* card detect */ - u8 rdy_pin; /* ready/busy */ + int enable_pin; /* chip enable */ + int det_pin; /* card detect */ + int rdy_pin; /* ready/busy */ u8 ale; /* address line number connected to ALE */ u8 cle; /* address line number connected to CLE */ u8 bus_width_16; /* buswidth is 16 bit */ @@ -148,8 +148,8 @@ struct atmel_mci_platform_data { unsigned slot_b; unsigned bus_width; unsigned host_caps; /* MCI_MODE_* from mci.h */ - unsigned detect_pin; - unsigned wp_pin; + int detect_pin; + int wp_pin; }; void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data); diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 90b9f8a391..b6504c19d5 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -1,7 +1,8 @@ /* * arch/arm/mach-at91/include/mach/cpu.h * - * Copyright (C) 2006 SAN People + * Copyright (C) 2006 SAN People + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,12 +11,8 @@ * */ -#ifndef __ASM_ARCH_CPU_H -#define __ASM_ARCH_CPU_H - -#include <mach/hardware.h> -#include <mach/at91_dbgu.h> - +#ifndef __MACH_CPU_H__ +#define __MACH_CPU_H__ #define ARCH_ID_AT91RM9200 0x09290780 #define ARCH_ID_AT91SAM9260 0x019803a0 @@ -29,29 +26,16 @@ #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ #define ARCH_ID_AT91SAM9X5 0x819a05a0 #define ARCH_ID_AT91SAM9N12 0x819a07a0 -#define ARCH_ID_AT91CAP9 0x039A03A0 #define ARCH_ID_AT91SAM9XE128 0x329973a0 #define ARCH_ID_AT91SAM9XE256 0x329a93a0 #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 -#define ARCH_ID_AT572D940HF 0x0e0303e0 - #define ARCH_ID_AT91M40800 0x14080044 #define ARCH_ID_AT91R40807 0x44080746 #define ARCH_ID_AT91M40807 0x14080745 #define ARCH_ID_AT91R40008 0x44000840 -static inline unsigned long at91_cpu_identify(void) -{ - return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); -} - -static inline unsigned long at91_cpu_fully_identify(void) -{ - return at91_sys_read(AT91_DBGU_CIDR); -} - #define ARCH_EXID_AT91SAM9M11 0x00000001 #define ARCH_EXID_AT91SAM9M10 0x00000002 #define ARCH_EXID_AT91SAM9G46 0x00000003 @@ -63,86 +47,116 @@ static inline unsigned long at91_cpu_fully_identify(void) #define ARCH_EXID_AT91SAM9G25 0x00000003 #define ARCH_EXID_AT91SAM9X25 0x00000004 -static inline unsigned long at91_exid_identify(void) -{ - return at91_sys_read(AT91_DBGU_EXID); -} - - #define ARCH_FAMILY_AT91X92 0x09200000 #define ARCH_FAMILY_AT91SAM9 0x01900000 #define ARCH_FAMILY_AT91SAM9XE 0x02900000 -static inline unsigned long at91_arch_identify(void) -{ - return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); -} +/* RM9200 type */ +#define ARCH_REVISON_9200_BGA (0 << 0) +#define ARCH_REVISON_9200_PQFP (1 << 0) + +#ifndef __ASSEMBLY__ +enum at91_soc_type { + /* 920T */ + AT91_SOC_RM9200, + + /* SAM92xx */ + AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, + + /* SAM9Gxx */ + AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45, + + /* SAM9RL */ + AT91_SOC_SAM9RL, + + /* SAM9X5 */ + AT91_SOC_SAM9X5, + + /* SAM9N12 */ + AT91_SOC_SAM9N12, -#ifdef CONFIG_ARCH_AT91CAP9 -#include <mach/at91_pmc.h> + /* Unknown type */ + AT91_SOC_NONE +}; -#define ARCH_REVISION_CAP9_B 0x399 -#define ARCH_REVISION_CAP9_C 0x601 +enum at91_soc_subtype { + /* RM9200 */ + AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, -static inline unsigned long at91cap9_rev_identify(void) + /* SAM9260 */ + AT91_SOC_SAM9XE, + + /* SAM9G45 */ + AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11, + + /* SAM9X5 */ + AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, + AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, + + /* Unknown subtype */ + AT91_SOC_SUBTYPE_NONE +}; + +struct at91_socinfo { + unsigned int type, subtype; + unsigned int cidr, exid; +}; + +extern struct at91_socinfo at91_soc_initdata; +const char *at91_get_soc_type(struct at91_socinfo *c); +const char *at91_get_soc_subtype(struct at91_socinfo *c); + +static inline int at91_soc_is_detected(void) { - return (at91_sys_read(AT91_PMC_VER)); + return at91_soc_initdata.type != AT91_SOC_NONE; } -#endif -#ifdef CONFIG_ARCH_AT91RM9200 -#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) +#ifdef CONFIG_SOC_AT91RM9200 +#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200) +#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA) +#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP) #else #define cpu_is_at91rm9200() (0) +#define cpu_is_at91rm9200_bga() (0) +#define cpu_is_at91rm9200_pqfp() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9260 -#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE) -#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe()) +#ifdef CONFIG_SOC_AT91SAM9260 +#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE) +#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260) +#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) #else #define cpu_is_at91sam9xe() (0) #define cpu_is_at91sam9260() (0) -#endif - -#ifdef CONFIG_ARCH_AT91SAM9G20 -#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20) -#else #define cpu_is_at91sam9g20() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9261 -#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) +#ifdef CONFIG_SOC_AT91SAM9261 +#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261) +#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10) #else #define cpu_is_at91sam9261() (0) -#endif - -#ifdef CONFIG_ARCH_AT91SAM9G10 -#define cpu_is_at91sam9g10() ((at91_cpu_identify() & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) -#else #define cpu_is_at91sam9g10() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9263 -#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) +#ifdef CONFIG_SOC_AT91SAM9263 +#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263) #else #define cpu_is_at91sam9263() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9RL -#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) +#ifdef CONFIG_SOC_AT91SAM9RL +#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL) #else #define cpu_is_at91sam9rl() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9G45 -#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) -#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES) -#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9M10)) -#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9G46)) -#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9M11)) +#ifdef CONFIG_SOC_AT91SAM9G45 +#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45) +#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES) +#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10) +#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46) +#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11) #else #define cpu_is_at91sam9g45() (0) #define cpu_is_at91sam9g45es() (0) @@ -151,18 +165,13 @@ static inline unsigned long at91cap9_rev_identify(void) #define cpu_is_at91sam9m11() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9X5 -#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5) -#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9G15)) -#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9G35)) -#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9X35)) -#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9G25)) -#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9X25)) +#ifdef CONFIG_SOC_AT91SAM9X5 +#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5) +#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15) +#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35) +#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35) +#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25) +#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25) #else #define cpu_is_at91sam9x5() (0) #define cpu_is_at91sam9g15() (0) @@ -172,32 +181,17 @@ static inline unsigned long at91cap9_rev_identify(void) #define cpu_is_at91sam9x25() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9N12 -#define cpu_is_at91sam9n12() (at91_cpu_identify() == ARCH_ID_AT91SAM9N12) +#ifdef CONFIG_SOC_AT91SAM9N12 +#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12) #else #define cpu_is_at91sam9n12() (0) #endif -#ifdef CONFIG_ARCH_AT91CAP9 -#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) -#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) -#define cpu_is_at91cap9_revC() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_C) -#else -#define cpu_is_at91cap9() (0) -#define cpu_is_at91cap9_revB() (0) -#define cpu_is_at91cap9_revC() (0) -#endif - -#ifdef CONFIG_ARCH_AT572D940HF -#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF) -#else -#define cpu_is_at572d940hf() (0) -#endif - /* * Since this is ARM, we will never run on any AVR32 CPU. But these * definitions may reduce clutter in common drivers. */ #define cpu_is_at32ap7000() (0) +#endif /* __ASSEMBLY__ */ -#endif +#endif /* __MACH_CPU_H__ */ diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h b/arch/arm/mach-at91/include/mach/debug_ll.h index a85fdee994..1a85ae4835 100644 --- a/arch/arm/mach-at91/include/mach/debug_ll.h +++ b/arch/arm/mach-at91/include/mach/debug_ll.h @@ -11,7 +11,11 @@ #include <asm/io.h> #include <mach/hardware.h> -#define UART_BASE (AT91_BASE_SYS + AT91_DBGU) +#ifdef COFNIG_HAVE_AT91_DBGU0 +#define UART_BASE AT91_BASE_DBGU0 +#else +#define UART_BASE AT91_BASE_DBGU1 +#endif #define ATMEL_US_CSR 0x0014 #define ATMEL_US_THR 0x001c diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index fa695a617c..eb64bd4ce2 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -17,202 +17,228 @@ #include <asm-generic/errno.h> #include <mach/at91_pio.h> #include <mach/hardware.h> - -#define PIN_BASE 32 - -/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ +#include <asm-generic/gpio.h> #define ARCH_NR_GPIOS 256 -static inline int gpio_is_valid(int gpio) -{ - if (gpio < 1) - return 0; - if (gpio < ARCH_NR_GPIOS) - return 1; - return 0; -} +#define AT91_PIN_PA0 (0x00 + 0) +#define AT91_PIN_PA1 (0x00 + 1) +#define AT91_PIN_PA2 (0x00 + 2) +#define AT91_PIN_PA3 (0x00 + 3) +#define AT91_PIN_PA4 (0x00 + 4) +#define AT91_PIN_PA5 (0x00 + 5) +#define AT91_PIN_PA6 (0x00 + 6) +#define AT91_PIN_PA7 (0x00 + 7) +#define AT91_PIN_PA8 (0x00 + 8) +#define AT91_PIN_PA9 (0x00 + 9) +#define AT91_PIN_PA10 (0x00 + 10) +#define AT91_PIN_PA11 (0x00 + 11) +#define AT91_PIN_PA12 (0x00 + 12) +#define AT91_PIN_PA13 (0x00 + 13) +#define AT91_PIN_PA14 (0x00 + 14) +#define AT91_PIN_PA15 (0x00 + 15) +#define AT91_PIN_PA16 (0x00 + 16) +#define AT91_PIN_PA17 (0x00 + 17) +#define AT91_PIN_PA18 (0x00 + 18) +#define AT91_PIN_PA19 (0x00 + 19) +#define AT91_PIN_PA20 (0x00 + 20) +#define AT91_PIN_PA21 (0x00 + 21) +#define AT91_PIN_PA22 (0x00 + 22) +#define AT91_PIN_PA23 (0x00 + 23) +#define AT91_PIN_PA24 (0x00 + 24) +#define AT91_PIN_PA25 (0x00 + 25) +#define AT91_PIN_PA26 (0x00 + 26) +#define AT91_PIN_PA27 (0x00 + 27) +#define AT91_PIN_PA28 (0x00 + 28) +#define AT91_PIN_PA29 (0x00 + 29) +#define AT91_PIN_PA30 (0x00 + 30) +#define AT91_PIN_PA31 (0x00 + 31) -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) +#define AT91_PIN_PB0 (0x20 + 0) +#define AT91_PIN_PB1 (0x20 + 1) +#define AT91_PIN_PB2 (0x20 + 2) +#define AT91_PIN_PB3 (0x20 + 3) +#define AT91_PIN_PB4 (0x20 + 4) +#define AT91_PIN_PB5 (0x20 + 5) +#define AT91_PIN_PB6 (0x20 + 6) +#define AT91_PIN_PB7 (0x20 + 7) +#define AT91_PIN_PB8 (0x20 + 8) +#define AT91_PIN_PB9 (0x20 + 9) +#define AT91_PIN_PB10 (0x20 + 10) +#define AT91_PIN_PB11 (0x20 + 11) +#define AT91_PIN_PB12 (0x20 + 12) +#define AT91_PIN_PB13 (0x20 + 13) +#define AT91_PIN_PB14 (0x20 + 14) +#define AT91_PIN_PB15 (0x20 + 15) +#define AT91_PIN_PB16 (0x20 + 16) +#define AT91_PIN_PB17 (0x20 + 17) +#define AT91_PIN_PB18 (0x20 + 18) +#define AT91_PIN_PB19 (0x20 + 19) +#define AT91_PIN_PB20 (0x20 + 20) +#define AT91_PIN_PB21 (0x20 + 21) +#define AT91_PIN_PB22 (0x20 + 22) +#define AT91_PIN_PB23 (0x20 + 23) +#define AT91_PIN_PB24 (0x20 + 24) +#define AT91_PIN_PB25 (0x20 + 25) +#define AT91_PIN_PB26 (0x20 + 26) +#define AT91_PIN_PB27 (0x20 + 27) +#define AT91_PIN_PB28 (0x20 + 28) +#define AT91_PIN_PB29 (0x20 + 29) +#define AT91_PIN_PB30 (0x20 + 30) +#define AT91_PIN_PB31 (0x20 + 31) -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) +#define AT91_PIN_PC0 (0x40 + 0) +#define AT91_PIN_PC1 (0x40 + 1) +#define AT91_PIN_PC2 (0x40 + 2) +#define AT91_PIN_PC3 (0x40 + 3) +#define AT91_PIN_PC4 (0x40 + 4) +#define AT91_PIN_PC5 (0x40 + 5) +#define AT91_PIN_PC6 (0x40 + 6) +#define AT91_PIN_PC7 (0x40 + 7) +#define AT91_PIN_PC8 (0x40 + 8) +#define AT91_PIN_PC9 (0x40 + 9) +#define AT91_PIN_PC10 (0x40 + 10) +#define AT91_PIN_PC11 (0x40 + 11) +#define AT91_PIN_PC12 (0x40 + 12) +#define AT91_PIN_PC13 (0x40 + 13) +#define AT91_PIN_PC14 (0x40 + 14) +#define AT91_PIN_PC15 (0x40 + 15) +#define AT91_PIN_PC16 (0x40 + 16) +#define AT91_PIN_PC17 (0x40 + 17) +#define AT91_PIN_PC18 (0x40 + 18) +#define AT91_PIN_PC19 (0x40 + 19) +#define AT91_PIN_PC20 (0x40 + 20) +#define AT91_PIN_PC21 (0x40 + 21) +#define AT91_PIN_PC22 (0x40 + 22) +#define AT91_PIN_PC23 (0x40 + 23) +#define AT91_PIN_PC24 (0x40 + 24) +#define AT91_PIN_PC25 (0x40 + 25) +#define AT91_PIN_PC26 (0x40 + 26) +#define AT91_PIN_PC27 (0x40 + 27) +#define AT91_PIN_PC28 (0x40 + 28) +#define AT91_PIN_PC29 (0x40 + 29) +#define AT91_PIN_PC30 (0x40 + 30) +#define AT91_PIN_PC31 (0x40 + 31) -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) +#define AT91_PIN_PD0 (0x60 + 0) +#define AT91_PIN_PD1 (0x60 + 1) +#define AT91_PIN_PD2 (0x60 + 2) +#define AT91_PIN_PD3 (0x60 + 3) +#define AT91_PIN_PD4 (0x60 + 4) +#define AT91_PIN_PD5 (0x60 + 5) +#define AT91_PIN_PD6 (0x60 + 6) +#define AT91_PIN_PD7 (0x60 + 7) +#define AT91_PIN_PD8 (0x60 + 8) +#define AT91_PIN_PD9 (0x60 + 9) +#define AT91_PIN_PD10 (0x60 + 10) +#define AT91_PIN_PD11 (0x60 + 11) +#define AT91_PIN_PD12 (0x60 + 12) +#define AT91_PIN_PD13 (0x60 + 13) +#define AT91_PIN_PD14 (0x60 + 14) +#define AT91_PIN_PD15 (0x60 + 15) +#define AT91_PIN_PD16 (0x60 + 16) +#define AT91_PIN_PD17 (0x60 + 17) +#define AT91_PIN_PD18 (0x60 + 18) +#define AT91_PIN_PD19 (0x60 + 19) +#define AT91_PIN_PD20 (0x60 + 20) +#define AT91_PIN_PD21 (0x60 + 21) +#define AT91_PIN_PD22 (0x60 + 22) +#define AT91_PIN_PD23 (0x60 + 23) +#define AT91_PIN_PD24 (0x60 + 24) +#define AT91_PIN_PD25 (0x60 + 25) +#define AT91_PIN_PD26 (0x60 + 26) +#define AT91_PIN_PD27 (0x60 + 27) +#define AT91_PIN_PD28 (0x60 + 28) +#define AT91_PIN_PD29 (0x60 + 29) +#define AT91_PIN_PD30 (0x60 + 30) +#define AT91_PIN_PD31 (0x60 + 31) -#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) -#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) -#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) -#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) -#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) -#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) -#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) -#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) -#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) -#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) -#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) -#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) -#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) -#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) -#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) -#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) -#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) -#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) -#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) -#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) -#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) -#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) -#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) -#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) -#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) -#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) -#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) -#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) -#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) -#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) -#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) -#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) +#define AT91_PIN_PE0 (0x80 + 0) +#define AT91_PIN_PE1 (0x80 + 1) +#define AT91_PIN_PE2 (0x80 + 2) +#define AT91_PIN_PE3 (0x80 + 3) +#define AT91_PIN_PE4 (0x80 + 4) +#define AT91_PIN_PE5 (0x80 + 5) +#define AT91_PIN_PE6 (0x80 + 6) +#define AT91_PIN_PE7 (0x80 + 7) +#define AT91_PIN_PE8 (0x80 + 8) +#define AT91_PIN_PE9 (0x80 + 9) +#define AT91_PIN_PE10 (0x80 + 10) +#define AT91_PIN_PE11 (0x80 + 11) +#define AT91_PIN_PE12 (0x80 + 12) +#define AT91_PIN_PE13 (0x80 + 13) +#define AT91_PIN_PE14 (0x80 + 14) +#define AT91_PIN_PE15 (0x80 + 15) +#define AT91_PIN_PE16 (0x80 + 16) +#define AT91_PIN_PE17 (0x80 + 17) +#define AT91_PIN_PE18 (0x80 + 18) +#define AT91_PIN_PE19 (0x80 + 19) +#define AT91_PIN_PE20 (0x80 + 20) +#define AT91_PIN_PE21 (0x80 + 21) +#define AT91_PIN_PE22 (0x80 + 22) +#define AT91_PIN_PE23 (0x80 + 23) +#define AT91_PIN_PE24 (0x80 + 24) +#define AT91_PIN_PE25 (0x80 + 25) +#define AT91_PIN_PE26 (0x80 + 26) +#define AT91_PIN_PE27 (0x80 + 27) +#define AT91_PIN_PE28 (0x80 + 28) +#define AT91_PIN_PE29 (0x80 + 29) +#define AT91_PIN_PE30 (0x80 + 30) +#define AT91_PIN_PE31 (0x80 + 31) -#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) -#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) -#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) -#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) -#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) -#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) -#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) -#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) -#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) -#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) -#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) -#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) -#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) -#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) -#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) -#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) -#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) -#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) -#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) -#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) -#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) -#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) -#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) -#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) -#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) -#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) -#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) -#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) -#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) -#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) -#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) -#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) +enum at91_mux { + AT91_MUX_GPIO = 0, + AT91_MUX_PERIPH_A = 1, + AT91_MUX_PERIPH_B = 2, + AT91_MUX_PERIPH_C = 3, + AT91_MUX_PERIPH_D = 4, +}; /* - * mux the pin to the "GPIO" peripheral role. + * mux the pin */ -int at91_set_GPIO_periph(unsigned pin, int use_pullup); +int at91_mux_pin(unsigned pin, enum at91_mux mux, int use_pullup); +/* + * mux the pin to the "GPIO" peripheral role. + */ +static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) +{ + return at91_mux_pin(pin, AT91_MUX_GPIO, use_pullup); +} /* * mux the pin to the "A" internal peripheral role. */ -int at91_set_A_periph(unsigned pin, int use_pullup); +static inline int at91_set_A_periph(unsigned pin, int use_pullup) +{ + return at91_mux_pin(pin, AT91_MUX_PERIPH_A, use_pullup); +} /* * mux the pin to the "B" internal peripheral role. */ -int at91_set_B_periph(unsigned pin, int use_pullup); +static inline int at91_set_B_periph(unsigned pin, int use_pullup) +{ + return at91_mux_pin(pin, AT91_MUX_PERIPH_B, use_pullup); +} + +/* + * mux the pin to the "C" internal peripheral role. + */ +static inline int at91_set_C_periph(unsigned pin, int use_pullup) +{ + return at91_mux_pin(pin, AT91_MUX_PERIPH_C, use_pullup); +} + +/* + * mux the pin to the "C" internal peripheral role. + */ +static inline int at91_set_D_periph(unsigned pin, int use_pullup) +{ + return at91_mux_pin(pin, AT91_MUX_PERIPH_D, use_pullup); +} + /* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and * configure it for an input. @@ -236,32 +262,8 @@ int at91_set_deglitch(unsigned pin, int is_on); */ int at91_set_multi_drive(unsigned pin, int is_on); -/* - * assuming the pin is muxed as a gpio output, set its value. - */ -int at91_set_gpio_value(unsigned pin, int value); - -extern int at91_set_C_periph(unsigned pin, int use_pullup); -extern int at91_set_D_periph(unsigned pin, int use_pullup); extern int at91_set_debounce(unsigned pin, int is_on, int div); extern int at91_set_pulldown(unsigned pin, int is_on); extern int at91_disable_schmitt_trig(unsigned pin); -/* - * read the pin's value (works even if it's not muxed as a gpio). - */ -int at91_get_gpio_value(unsigned pin); - -struct at91_gpio_bank { - void __iomem *regbase; /* base of register bank */ - struct clk *clock; -}; - -extern int at91_gpio_init(struct at91_gpio_bank *data, int nr_banks); - -extern int gpio_direction_input(unsigned gpio); -extern int gpio_direction_output(unsigned gpio, int value); -#define gpio_get_value at91_get_gpio_value -#define gpio_set_value at91_set_gpio_value - #endif /* __ASM_ARCH_AT91SAM9_GPIO_H */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index f8ac7910e5..e283b9d9ad 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -14,6 +14,14 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H +/* DBGU base */ +/* rm9200, 9260/9g20, 9261/9g10, 9rl */ +#define AT91_BASE_DBGU0 0xfffff200 +/* 9263, 9g45 */ +#define AT91_BASE_DBGU1 0xffffee00 + +#define AT91_PMC 0xfffffc00 + #if defined(CONFIG_ARCH_AT91RM9200) #include <mach/at91rm9200.h> #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) diff --git a/arch/arm/mach-at91/include/mach/sam9_smc.h b/arch/arm/mach-at91/include/mach/sam9_smc.h deleted file mode 100644 index bf72cfb345..0000000000 --- a/arch/arm/mach-at91/include/mach/sam9_smc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * linux/arch/arm/mach-at91/sam9_smc. - * - * Copyright (C) 2008 Andrew Victor - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -struct sam9_smc_config { - /* Setup register */ - u8 ncs_read_setup; - u8 nrd_setup; - u8 ncs_write_setup; - u8 nwe_setup; - - /* Pulse register */ - u8 ncs_read_pulse; - u8 nrd_pulse; - u8 ncs_write_pulse; - u8 nwe_pulse; - - /* Cycle register */ - u16 read_cycle; - u16 write_cycle; - - /* Mode register */ - u32 mode; - u8 tdf_cycles:4; -}; - -extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config); diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index c397fe46b5..b48275e07e 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -9,40 +9,142 @@ */ #include <common.h> +#include <init.h> #include <io.h> #include <mach/hardware.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> -void sam9_smc_configure(int cs, struct sam9_smc_config* config) +#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10)) + +static void __iomem *smc_base_addr[2]; + +static void sam9_smc_cs_write_mode(void __iomem *base, + struct sam9_smc_config *config) +{ + __raw_writel(config->mode + | AT91_SMC_TDF_(config->tdf_cycles), + base + AT91_SMC_MODE); +} + +void sam9_smc_write_mode(int id, int cs, + struct sam9_smc_config *config) +{ + sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config); +} + +static void sam9_smc_cs_configure(void __iomem *base, + struct sam9_smc_config *config) +{ + + /* Setup register */ + __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup) + | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) + | AT91_SMC_NRDSETUP_(config->nrd_setup) + | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup), + base + AT91_SMC_SETUP); + + /* Pulse register */ + __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse) + | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) + | AT91_SMC_NRDPULSE_(config->nrd_pulse) + | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse), + base + AT91_SMC_PULSE); + + /* Cycle register */ + __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle) + | AT91_SMC_NRDCYCLE_(config->read_cycle), + base + AT91_SMC_CYCLE); + + /* Mode register */ + sam9_smc_cs_write_mode(base, config); +} + +void sam9_smc_configure(int id, int cs, + struct sam9_smc_config *config) +{ + sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); +} + +static void sam9_smc_cs_read_mode(void __iomem *base, + struct sam9_smc_config *config) +{ + u32 val = __raw_readl(base + AT91_SMC_MODE); + + config->mode = (val & ~AT91_SMC_NWECYCLE); + config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; +} + +void sam9_smc_read_mode(int id, int cs, + struct sam9_smc_config *config) +{ + sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config); +} + +static void sam9_smc_cs_read(void __iomem *base, + struct sam9_smc_config *config) { + u32 val; + /* Setup register */ - at91_sys_write(AT91_SMC_SETUP(cs), - AT91_SMC_NWESETUP_(config->nwe_setup) - | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) - | AT91_SMC_NRDSETUP_(config->nrd_setup) - | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup) - ); + val = __raw_readl(base + AT91_SMC_SETUP); + + config->nwe_setup = val & AT91_SMC_NWESETUP; + config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8; + config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16; + config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24; /* Pulse register */ - at91_sys_write(AT91_SMC_PULSE(cs), - AT91_SMC_NWEPULSE_(config->nwe_pulse) - | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) - | AT91_SMC_NRDPULSE_(config->nrd_pulse) - | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse) - ); + val = __raw_readl(base + AT91_SMC_PULSE); + + config->nwe_setup = val & AT91_SMC_NWEPULSE; + config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; + config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16; + config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; /* Cycle register */ - at91_sys_write(AT91_SMC_CYCLE(cs), - AT91_SMC_NWECYCLE_(config->write_cycle) - | AT91_SMC_NRDCYCLE_(config->read_cycle) - ); + val = __raw_readl(base + AT91_SMC_CYCLE); + + config->write_cycle = val & AT91_SMC_NWECYCLE; + config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16; /* Mode register */ - at91_sys_write(AT91_SMC_MODE(cs), - config->mode - | AT91_SMC_TDF_(config->tdf_cycles) - ); + sam9_smc_cs_read_mode(base, config); +} + +void sam9_smc_read(int id, int cs, struct sam9_smc_config *config) +{ + sam9_smc_cs_read(AT91_SMC_CS(id, cs), config); +} + +static int at91sam9_smc_probe(struct device_d *dev) +{ + int id; + + if (dev->id < 0) { + id = 0; + } else if (dev->id > 1) { + dev_warn(dev, ": id > 2\n"); + return -EIO; + } + + smc_base_addr[id] = dev_request_mem_region(dev, 0); + if (!smc_base_addr[id]) { + dev_err(dev, "Impossible to request smc.%d\n", id); + return -ENOMEM; + } + + return 0; +} + +static struct driver_d at91sam9_smc_driver = { + .name = "at91sam9-smc", + .probe = at91sam9_smc_probe, +}; + +static int at91sam9_smc_init(void) +{ + return platform_driver_register(&at91sam9_smc_driver); } +coredevice_initcall(at91sam9_smc_init); diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c new file mode 100644 index 0000000000..9b73bcf496 --- /dev/null +++ b/arch/arm/mach-at91/setup.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2007 Atmel Corporation. + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <io.h> +#include <init.h> + +#include <mach/hardware.h> +#include <mach/cpu.h> +#include <mach/at91_dbgu.h> + +#include "soc.h" + +struct at91_init_soc __initdata at91_boot_soc; + +struct at91_socinfo at91_soc_initdata; +EXPORT_SYMBOL(at91_soc_initdata); + +void __init at91rm9200_set_type(int type) +{ + if (type == ARCH_REVISON_9200_PQFP) + at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP; + else + at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; + + pr_info("AT91: filled in soc subtype: %s\n", + at91_get_soc_subtype(&at91_soc_initdata)); +} + +static void __init soc_detect(u32 dbgu_base) +{ + u32 cidr, socid; + + cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR); + socid = cidr & ~AT91_CIDR_VERSION; + + switch (socid) { + case ARCH_ID_AT91RM9200: + at91_soc_initdata.type = AT91_SOC_RM9200; + if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE) + at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; + at91_boot_soc = at91rm9200_soc; + break; + + case ARCH_ID_AT91SAM9260: + at91_soc_initdata.type = AT91_SOC_SAM9260; + at91_boot_soc = at91sam9260_soc; + break; + + case ARCH_ID_AT91SAM9261: + at91_soc_initdata.type = AT91_SOC_SAM9261; + at91_boot_soc = at91sam9261_soc; + break; + + case ARCH_ID_AT91SAM9263: + at91_soc_initdata.type = AT91_SOC_SAM9263; + at91_boot_soc = at91sam9263_soc; + break; + + case ARCH_ID_AT91SAM9G20: + at91_soc_initdata.type = AT91_SOC_SAM9G20; + at91_boot_soc = at91sam9260_soc; + break; + + case ARCH_ID_AT91SAM9G45: + at91_soc_initdata.type = AT91_SOC_SAM9G45; + if (cidr == ARCH_ID_AT91SAM9G45ES) + at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES; + at91_boot_soc = at91sam9g45_soc; + break; + + case ARCH_ID_AT91SAM9RL64: + at91_soc_initdata.type = AT91_SOC_SAM9RL; + at91_boot_soc = at91sam9rl_soc; + break; + + case ARCH_ID_AT91SAM9X5: + at91_soc_initdata.type = AT91_SOC_SAM9X5; + at91_boot_soc = at91sam9x5_soc; + break; + + case ARCH_ID_AT91SAM9N12: + at91_soc_initdata.type = AT91_SOC_SAM9N12; + at91_boot_soc = at91sam9n12_soc; + break; + } + + /* at91sam9g10 */ + if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { + at91_soc_initdata.type = AT91_SOC_SAM9G10; + at91_boot_soc = at91sam9261_soc; + } + /* at91sam9xe */ + else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) { + at91_soc_initdata.type = AT91_SOC_SAM9260; + at91_soc_initdata.subtype = AT91_SOC_SAM9XE; + at91_boot_soc = at91sam9260_soc; + } + + if (!at91_soc_is_detected()) + return; + + at91_soc_initdata.cidr = cidr; + + /* sub version of soc */ + at91_soc_initdata.exid = __raw_readl(dbgu_base + AT91_DBGU_EXID); + + if (at91_soc_initdata.type == AT91_SOC_SAM9G45) { + switch (at91_soc_initdata.exid) { + case ARCH_EXID_AT91SAM9M10: + at91_soc_initdata.subtype = AT91_SOC_SAM9M10; + break; + case ARCH_EXID_AT91SAM9G46: + at91_soc_initdata.subtype = AT91_SOC_SAM9G46; + break; + case ARCH_EXID_AT91SAM9M11: + at91_soc_initdata.subtype = AT91_SOC_SAM9M11; + break; + } + } + + if (at91_soc_initdata.type == AT91_SOC_SAM9X5) { + switch (at91_soc_initdata.exid) { + case ARCH_EXID_AT91SAM9G15: + at91_soc_initdata.subtype = AT91_SOC_SAM9G15; + break; + case ARCH_EXID_AT91SAM9G35: + at91_soc_initdata.subtype = AT91_SOC_SAM9G35; + break; + case ARCH_EXID_AT91SAM9X35: + at91_soc_initdata.subtype = AT91_SOC_SAM9X35; + break; + case ARCH_EXID_AT91SAM9G25: + at91_soc_initdata.subtype = AT91_SOC_SAM9G25; + break; + case ARCH_EXID_AT91SAM9X25: + at91_soc_initdata.subtype = AT91_SOC_SAM9X25; + break; + } + } +} + +static const char *soc_name[] = { + [AT91_SOC_RM9200] = "at91rm9200", + [AT91_SOC_SAM9260] = "at91sam9260", + [AT91_SOC_SAM9261] = "at91sam9261", + [AT91_SOC_SAM9263] = "at91sam9263", + [AT91_SOC_SAM9G10] = "at91sam9g10", + [AT91_SOC_SAM9G20] = "at91sam9g20", + [AT91_SOC_SAM9G45] = "at91sam9g45", + [AT91_SOC_SAM9RL] = "at91sam9rl", + [AT91_SOC_SAM9X5] = "at91sam9x5", + [AT91_SOC_SAM9N12] = "at91sam9n12", + [AT91_SOC_NONE] = "Unknown" +}; + +const char *at91_get_soc_type(struct at91_socinfo *c) +{ + return soc_name[c->type]; +} +EXPORT_SYMBOL(at91_get_soc_type); + +static const char *soc_subtype_name[] = { + [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA", + [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP", + [AT91_SOC_SAM9XE] = "at91sam9xe", + [AT91_SOC_SAM9G45ES] = "at91sam9g45es", + [AT91_SOC_SAM9M10] = "at91sam9m10", + [AT91_SOC_SAM9G46] = "at91sam9g46", + [AT91_SOC_SAM9M11] = "at91sam9m11", + [AT91_SOC_SAM9G15] = "at91sam9g15", + [AT91_SOC_SAM9G35] = "at91sam9g35", + [AT91_SOC_SAM9X35] = "at91sam9x35", + [AT91_SOC_SAM9G25] = "at91sam9g25", + [AT91_SOC_SAM9X25] = "at91sam9x25", + [AT91_SOC_SUBTYPE_NONE] = "Unknown" +}; + +const char *at91_get_soc_subtype(struct at91_socinfo *c) +{ + return soc_subtype_name[c->subtype]; +} +EXPORT_SYMBOL(at91_get_soc_subtype); + +static int at91_detect(void) +{ + at91_soc_initdata.type = AT91_SOC_NONE; + at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; + + soc_detect(AT91_BASE_DBGU0); + if (!at91_soc_is_detected()) + soc_detect(AT91_BASE_DBGU1); + + if (!at91_soc_is_detected()) + panic("AT91: Impossible to detect the SOC type"); + + pr_info("AT91: Detected soc type: %s\n", + at91_get_soc_type(&at91_soc_initdata)); + pr_info("AT91: Detected soc subtype: %s\n", + at91_get_soc_subtype(&at91_soc_initdata)); + + if (!at91_soc_is_enabled()) + panic("AT91: Soc not enabled"); + + if (at91_boot_soc.init) + at91_boot_soc.init(); + + return 0; +} +postcore_initcall(at91_detect); + +static int at91_soc_device(void) +{ + struct device_d *dev; + + dev = add_generic_device_res("soc", DEVICE_ID_SINGLE, NULL, 0, NULL); + dev_add_param_fixed(dev, "name", (char*)at91_get_soc_type(&at91_soc_initdata)); + dev_add_param_fixed(dev, "subname", (char*)at91_get_soc_subtype(&at91_soc_initdata)); + + return 0; +} +coredevice_initcall(at91_soc_device); diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h new file mode 100644 index 0000000000..8019ced861 --- /dev/null +++ b/arch/arm/mach-at91/soc.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +struct at91_init_soc { + int builtin; + void (*init)(void); +}; + +extern struct at91_init_soc at91_boot_soc; +extern struct at91_init_soc at91rm9200_soc; +extern struct at91_init_soc at91sam9260_soc; +extern struct at91_init_soc at91sam9261_soc; +extern struct at91_init_soc at91sam9263_soc; +extern struct at91_init_soc at91sam9g45_soc; +extern struct at91_init_soc at91sam9rl_soc; +extern struct at91_init_soc at91sam9x5_soc; +extern struct at91_init_soc at91sam9n12_soc; + +#define AT91_SOC_START(_name) \ +struct at91_init_soc __initdata at91##_name##_soc \ + __used \ + = { \ + .builtin = 1, \ + +#define AT91_SOC_END \ +}; + +static inline int at91_soc_is_enabled(void) +{ + return at91_boot_soc.builtin; +} + +#if !defined(CONFIG_SOC_AT91RM9200) +#define at91rm9200_soc at91_boot_soc +#endif + +#if !defined(CONFIG_SOC_AT91SAM9260) +#define at91sam9260_soc at91_boot_soc +#endif + +#if !defined(CONFIG_SOC_AT91SAM9261) +#define at91sam9261_soc at91_boot_soc +#endif + +#if !defined(CONFIG_SOC_AT91SAM9263) +#define at91sam9263_soc at91_boot_soc +#endif + +#if !defined(CONFIG_SOC_AT91SAM9G45) +#define at91sam9g45_soc at91_boot_soc +#endif + +#if !defined(CONFIG_SOC_AT91SAM9RL) +#define at91sam9rl_soc at91_boot_soc +#endif + +#if !defined(CONFIG_SOC_AT91SAM9X5) +#define at91sam9x5_soc at91_boot_soc +#endif + +#if !defined(CONFIG_SOC_AT91SAM9N12) +#define at91sam9n12_soc at91_boot_soc +#endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index ec4f864164..feef9ad1d5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -29,6 +29,7 @@ config ARCH_TEXT_BASE default 0x4fc00000 if MACH_SABRELITE default 0x8fe00000 if MACH_TX53 default 0x7fc00000 if MACH_GUF_VINCELL + default 0x97f00000 if MACH_EFIKA_MX_SMARTBOOK config BOARDINFO default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25 @@ -48,6 +49,7 @@ config BOARDINFO default "Freescale i.MX51 PDK" if MACH_FREESCALE_MX51_PDK default "Freescale i.MX53 LOCO" if MACH_FREESCALE_MX53_LOCO default "Freescale i.MX53 SMD" if MACH_FREESCALE_MX53_SMD + default "Efika MX smartbook" if MACH_EFIKA_MX_SMARTBOOK default "Garz+Fricke Cupid" if MACH_GUF_CUPID default "Ka-Ro tx25" if MACH_TX25 default "TQ tqma53" if MACH_TQMA53 @@ -333,6 +335,7 @@ config MACH_PCM037 bool "phyCORE-i.MX31" select MACH_HAS_LOWLEVEL_INIT select USB_ULPI if USB + select HAVE_DEFAULT_ENVIRONMENT_NEW select ARCH_HAS_L2X0 help Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped @@ -428,6 +431,12 @@ config MACH_CCMX51_BASEBOARD This adds board specific devices that can be found on Digi evaluation board for CCMX51 module. +config MACH_EFIKA_MX_SMARTBOOK + bool "Efika MX smartbook" + select HAVE_DEFAULT_ENVIRONMENT_NEW + help + Choose this to compile barebox for the Efika MX Smartbook + endchoice endif diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c index d82fbf7e6b..682f39a3ac 100644 --- a/arch/arm/mach-imx/devices.c +++ b/arch/arm/mach-imx/devices.c @@ -72,3 +72,8 @@ struct device_d *imx_add_pata(void *base) { return imx_add_device("imx-pata", -1, base, 0x1000, NULL); } + +struct device_d *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata) +{ + return imx_add_device("imx-usb", id, base, 0x200, pdata); +} diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c index 31117f4501..6d30276284 100644 --- a/arch/arm/mach-imx/imx27.c +++ b/arch/arm/mach-imx/imx27.c @@ -118,6 +118,7 @@ static int imx27_init(void) add_generic_device("imx1-gpio", 5, NULL, MX27_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx21-wdt", 0, NULL, MX27_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx27-esdctl", 0, NULL, MX27_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx27-usb-misc", 0, NULL, MX27_USB_OTG_BASE_ADDR + 0x600, 0x100, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c index 2882675788..f0954b5d54 100644 --- a/arch/arm/mach-imx/imx31.c +++ b/arch/arm/mach-imx/imx31.c @@ -39,6 +39,7 @@ static int imx31_init(void) add_generic_device("imx31-gpio", 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx21-wdt", 0, NULL, MX31_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-esdctl", 0, NULL, MX31_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-usb-misc", 0, NULL, MX31_USB_OTG_BASE_ADDR + 0x600, 0x100, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index a62daf8480..cffcca3920 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -70,6 +70,7 @@ static int imx51_init(void) add_generic_device("imx31-gpio", 3, NULL, MX51_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx21-wdt", 0, NULL, MX51_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx51-esdctl", 0, NULL, MX51_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx51-usb-misc", 0, NULL, MX51_OTG_BASE_ADDR + 0x800, 0x100, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h index 79da93531d..d6c884a30a 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx27.h +++ b/arch/arm/mach-imx/include/mach/devices-imx27.h @@ -70,3 +70,18 @@ static inline struct device_d *imx27_add_mmc2(void *pdata) { return imx_add_mmc((void *)MX27_SDHC3_BASE_ADDR, 2, pdata); } + +static inline struct device_d *imx27_add_usbotg(void *pdata) +{ + return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx27_add_usbh1(void *pdata) +{ + return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR + 0x200, 1, pdata); +} + +static inline struct device_d *imx27_add_usbh2(void *pdata) +{ + return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR + 0x400, 2, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h index fe719301ad..7cf9114fbd 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx31.h +++ b/arch/arm/mach-imx/include/mach/devices-imx31.h @@ -51,3 +51,28 @@ static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pda { return imx_add_ipufb((void *)MX31_IPU_CTRL_BASE_ADDR, pdata); } + +static inline struct device_d *imx31_add_mmc0(void *pdata) +{ + return imx_add_mmc((void *)MX31_SDHC1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx31_add_mmc1(void *pdata) +{ + return imx_add_mmc((void *)MX31_SDHC2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx31_add_usbotg(void *pdata) +{ + return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx31_add_usbh1(void *pdata) +{ + return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR + 0x200, 1, pdata); +} + +static inline struct device_d *imx31_add_usbh2(void *pdata) +{ + return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR + 0x400, 2, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h index 95497fa664..ec8467ae9c 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx51.h +++ b/arch/arm/mach-imx/include/mach/devices-imx51.h @@ -98,3 +98,18 @@ static inline struct device_d *imx51_add_pata(void) { return imx_add_pata((void *)MX51_ATA_BASE_ADDR); } + +static inline struct device_d *imx51_add_usbotg(void *pdata) +{ + return imx_add_usb((void *)MX51_OTG_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx51_add_usbh1(void *pdata) +{ + return imx_add_usb((void *)MX51_OTG_BASE_ADDR + 0x200, 1, pdata); +} + +static inline struct device_d *imx51_add_usbh2(void *pdata) +{ + return imx_add_usb((void *)MX51_OTG_BASE_ADDR + 0x400, 2, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices.h b/arch/arm/mach-imx/include/mach/devices.h index 016778a138..59296585af 100644 --- a/arch/arm/mach-imx/include/mach/devices.h +++ b/arch/arm/mach-imx/include/mach/devices.h @@ -7,6 +7,7 @@ #include <mach/imxfb.h> #include <mach/imx-ipu-fb.h> #include <mach/esdhc.h> +#include <usb/chipidea-imx.h> struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata); struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata); @@ -21,3 +22,4 @@ struct device_d *imx_add_mmc(void *base, int id, void *pdata); struct device_d *imx_add_esdhc(void *base, int id, struct esdhc_platform_data *pdata); struct device_d *imx_add_kpp(void *base, struct matrix_keymap_data *pdata); struct device_d *imx_add_pata(void *base); +struct device_d *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata); diff --git a/arch/arm/mach-imx/include/mach/esdhc.h b/arch/arm/mach-imx/include/mach/esdhc.h index b4c1aa9ebe..06863c8f1b 100644 --- a/arch/arm/mach-imx/include/mach/esdhc.h +++ b/arch/arm/mach-imx/include/mach/esdhc.h @@ -41,5 +41,6 @@ struct esdhc_platform_data { enum wp_types wp_type; enum cd_types cd_type; unsigned caps; + char *devname; }; #endif /* __ASM_ARCH_IMX_ESDHC_H */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx31.h b/arch/arm/mach-imx/include/mach/iomux-mx31.h index afb6fbaffb..258ccee034 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx31.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx31.h @@ -12,12 +12,10 @@ * GNU General Public License for more details. * */ - -#ifndef __MACH_MX31_IOMUX_H__ -#define __MACH_MX31_IOMUX_H__ +#ifndef __MACH_IOMUX_MX3_H__ +#define __MACH_IOMUX_MX3_H__ #include <linux/types.h> - /* * various IOMUX output functions */ @@ -30,7 +28,7 @@ #define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ #define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ #define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ +#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ #define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ #define IOMUX_ICONFIG_FUNC 2 /* used as function */ #define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ @@ -88,7 +86,7 @@ enum iomux_gp_func { MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, MUX_TAMPER_DETECT_EN = 1 << 16, MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGB_USB_COMMON = 1 << 18, + MUX_PGP_USB_COMMON = 1 << 18, MUX_SDHC_MEMSTICK1 = 1 << 19, MUX_SDHC_MEMSTICK2 = 1 << 20, MUX_PGP_SPLL_BYP = 1 << 21, @@ -105,21 +103,23 @@ enum iomux_gp_func { }; /* - * This function enables/disables the general purpose function for a particular - * signal. + * setups mutliple pins + * convenient way to call the above function with tables */ -void iomux_config_gpr(enum iomux_gp_func , int); +int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count); /* - * set the mode for a IOMUX pin. + * This function enables/disables the general purpose function for a particular + * signal. */ -int mxc_iomux_mode(unsigned int); +void imx_iomux_set_gpr(enum iomux_gp_func, bool en); /* - * This function enables/disables the general purpose function for a particular - * signal. + * This function only configures the iomux hardware. + * It is called by the setup functions and should not be called directly anymore. + * It is here visible for backward compatibility */ -void mxc_iomux_set_gpr(enum iomux_gp_func, int); +int imx_iomux_mode(unsigned int pin_mode); #define IOMUX_PADNUM_MASK 0x1ff #define IOMUX_GPIONUM_SHIFT 9 @@ -135,9 +135,6 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, int); #define IOMUX_TO_GPIO(iomux_pin) \ ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) -#define IOMUX_TO_IRQ(iomux_pin) \ - (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ - MXC_GPIO_INT_BASE) /* * This enumeration is constructed based on the Section @@ -476,6 +473,9 @@ enum iomux_pins { MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), }; +#define PIN_MAX 327 +#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */ + /* * Convenience values for use with mxc_iomux_mode() * @@ -483,14 +483,28 @@ enum iomux_pins { */ #define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) #define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI3_SCLK__RTS3 IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1) #define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2) #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2) #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2) #define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) #define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE) #define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) #define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) #define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) @@ -503,7 +517,9 @@ enum iomux_pins { #define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1) #define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1) #define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) @@ -521,29 +537,192 @@ enum iomux_pins { #define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) #define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) +#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC) +#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC) +#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC) +#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_I2C_CLK__SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_I2C_DAT__SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI2_SCLK__I2C3_SCL IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) +#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) +#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) +#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) +#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO) +#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC) -/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 - * cspi1_ss1*/ /* - * This function configures the pad value for a IOMUX pin. + * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, + * cspi2_ss1, cspi1_ss0 cspi1_ss1 */ -int imx_iomux_mode(unsigned int pin_mode); -void imx_iomux_set_pad(enum iomux_pins pin, u32 config); -void imx_iomux_set_gpr(enum iomux_gp_func gp, int en); - -#endif +/* + * This function configures the pad value for a IOMUX pin. + */ +void imx_iomux_set_pad(enum iomux_pins, u32); +#endif /* ifndef __MACH_IOMUX_MX3_H__ */ diff --git a/arch/arm/mach-imx/iomux-v2.c b/arch/arm/mach-imx/iomux-v2.c index dbbb8a26fd..cef0340909 100644 --- a/arch/arm/mach-imx/iomux-v2.c +++ b/arch/arm/mach-imx/iomux-v2.c @@ -88,7 +88,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad); * This function enables/disables the general purpose function for a particular * signal. */ -void imx_iomux_set_gpr(enum iomux_gp_func gp, int en) +void imx_iomux_set_gpr(enum iomux_gp_func gp, bool en) { u32 l; @@ -105,6 +105,16 @@ void imx_iomux_set_gpr(enum iomux_gp_func gp, int en) } EXPORT_SYMBOL(mxc_iomux_set_gpr); +int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count) +{ + int i; + + for (i = 0; i < count; i++) + imx_iomux_mode(pin_list[i]); + + return 0; +} + static int imx_iomux_probe(struct device_d *dev) { base = dev_request_mem_region(dev, 0); diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index 451783eaa5..27626a2cbd 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -67,8 +67,12 @@ config OMAP_GPMC NAND, OneNAND etc. config OMAP_BUILD_IFT - prompt "build ift binary" + prompt "build ift binary (MLO)" bool + help + Say Y here if you want to build an MLO binary. On TI SoCs, this + binary is loaded to SRAM. It is responsible for initializing + the SDRAM and possibly chainloading a full-featured barebox. config OMAP_BUILD_SPI prompt "build SPI binary" |