diff options
Diffstat (limited to 'arch')
174 files changed, 3606 insertions, 2454 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9b6c626dfb..50f30958ba 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -159,6 +159,8 @@ config ARCH_ROCKCHIP select PINCTRL select PINCTRL_ROCKCHIP select HAVE_PBL_MULTI_IMAGES + select HAS_DEBUG_LL + select ARCH_HAS_L2X0 config ARCH_SOCFPGA bool "Altera SOCFPGA cyclone5" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index f0133d4165..96c9f5797e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -105,10 +105,12 @@ CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) # Add cleanup flags CPPFLAGS += -fdata-sections -ffunction-sections -LDFLAGS_barebox += -static --gc-sections +LDFLAGS_barebox += --gc-sections ifdef CONFIG_RELOCATABLE LDFLAGS_barebox += -pie +else +LDFLAGS_barebox += -static endif ifdef CONFIG_IMAGE_COMPRESSION @@ -217,7 +219,6 @@ barebox.imximg: $(KBUILD_BINARY) FORCE boarddir = $(srctree)/arch/arm/boards imxcfg-$(CONFIG_MACH_FREESCALE_MX53_SMD) += $(boarddir)/freescale-mx53-smd/flash-header.imxcfg -imxcfg-$(CONFIG_MACH_MX6Q_ARM2) += $(boarddir)/freescale-mx6-arm2/flash-header.imxcfg imxcfg-$(CONFIG_MACH_CCMX51) += $(boarddir)/ccxmx51/flash-header.imxcfg imxcfg-$(CONFIG_MACH_TX51) += $(boarddir)/karo-tx51/flash-header-karo-tx51.imxcfg imxcfg-$(CONFIG_MACH_GUF_VINCELL) += $(boarddir)/guf-vincell/flash-header.imxcfg diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index a85de760f7..aee16656dd 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -64,7 +64,6 @@ obj-$(CONFIG_MACH_MMCCPU) += mmccpu/ obj-$(CONFIG_MACH_MX23EVK) += freescale-mx23-evk/ obj-$(CONFIG_MACH_MX28EVK) += freescale-mx28-evk/ obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard/ -obj-$(CONFIG_MACH_MX6Q_ARM2) += freescale-mx6-arm2/ obj-$(CONFIG_MACH_NESO) += guf-neso/ obj-$(CONFIG_MACH_NOMADIK_8815NHK) += nhk8815/ obj-$(CONFIG_MACH_NVIDIA_BEAVER) += nvidia-beaver/ @@ -81,8 +80,7 @@ obj-$(CONFIG_MACH_PCM037) += phytec-phycore-imx31/ obj-$(CONFIG_MACH_PCM038) += phytec-phycore-imx27/ obj-$(CONFIG_MACH_PCM043) += phytec-phycore-imx35/ obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/ -obj-$(CONFIG_MACH_PCM051) += phytec-phycore-am335x/ -obj-$(CONFIG_MACH_PFLA03) += phytec-phyflex-am335x/ +obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += phytec-som-am335x/ obj-$(CONFIG_MACH_PHYTEC_PFLA02) += phytec-phyflex-imx6/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/ @@ -102,6 +100,7 @@ obj-$(CONFIG_MACH_SAMA5D3_XPLAINED) += sama5d3_xplained/ obj-$(CONFIG_MACH_SAMA5D4_XPLAINED) += sama5d4_xplained/ obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ +obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ diff --git a/arch/arm/boards/altera-socdk/Makefile b/arch/arm/boards/altera-socdk/Makefile new file mode 100644 index 0000000000..8c927fe291 --- /dev/null +++ b/arch/arm/boards/altera-socdk/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel.o board.o +pbl-y += lowlevel.o diff --git a/arch/arm/boards/altera-socdk/board.c b/arch/arm/boards/altera-socdk/board.c new file mode 100644 index 0000000000..d7fb923a04 --- /dev/null +++ b/arch/arm/boards/altera-socdk/board.c @@ -0,0 +1,38 @@ +#include <common.h> +#include <types.h> +#include <driver.h> +#include <init.h> +#include <asm/armlinux.h> +#include <linux/micrel_phy.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <fcntl.h> +#include <fs.h> +#include <mach/socfpga-regs.h> + +static int ksz9021rn_phy_fixup(struct phy_device *dev) +{ + phy_write(dev, 0x09, 0x0f00); + + /* rx skew */ + phy_write(dev, 0x0b, 0x8105); + phy_write(dev, 0x0c, 0x0000); + + /* clk/ctrl skew */ + phy_write(dev, 0x0b, 0x8104); + phy_write(dev, 0x0c, 0xa0d0); + + return 0; +} + +static int socfpga_console_init(void) +{ + if (!of_machine_is_compatible("altr,socdk")) + return 0; + + phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, + ksz9021rn_phy_fixup); + + return 0; +} +console_initcall(socfpga_console_init); diff --git a/arch/arm/boards/altera-socdk/config.h b/arch/arm/boards/altera-socdk/config.h new file mode 100644 index 0000000000..da84fa5f6b --- /dev/null +++ b/arch/arm/boards/altera-socdk/config.h @@ -0,0 +1 @@ +/* nothing */ diff --git a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c new file mode 100644 index 0000000000..07a4485f1f --- /dev/null +++ b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c @@ -0,0 +1,678 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <mach/scan-manager.h> + +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] + = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00020080, + 0x08020000, + 0x08000000, + 0x00018020, + 0x00000000, + 0x00004000, + 0x00010040, + 0x04010000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x02008000, + 0x02000000, + 0x00000008, + 0x00002008, + 0x00001000, +}; + +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] + = { + 0x000C0300, + 0x10040000, + 0x100000C0, + 0x00000040, + 0x00010040, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x00010040, + 0x10000000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00004010, + 0x01004000, + 0x01000000, + 0x00003004, + 0x00001004, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00800000, + 0x00000002, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00401000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00600802, + 0x00000000, + 0x80200000, + 0x80000600, + 0x00000200, + 0x00000100, + 0x00300401, + 0xC0100400, + 0x40100000, + 0x40000300, + 0x000C0100, + 0x00000080, +}; + +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] + = { + 0x80040100, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C010040, + 0x00008000, + 0x18020080, + 0x00000000, + 0x08000000, + 0x00040020, + 0x06018060, + 0x00004000, + 0x0C0300C0, + 0x04010000, + 0x00000030, + 0x00000000, + 0x03004010, + 0x00002000, + 0x06018060, + 0x06018000, + 0x06000018, + 0x00006018, + 0x01806018, + 0x00001000, + 0x0300C030, + 0x0300C000, + 0x0300000C, + 0x0000300C, + 0x00C0300C, + 0x00000800, +}; + +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] + = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x41034051, + 0x12481A00, + 0x802080D0, + 0x34051406, + 0x01A02490, + 0x080D0000, + 0x51406802, + 0x02490340, + 0xD000001A, + 0x06802080, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x49034051, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x5140680A, + 0x02490340, + 0xD012481A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x59647A01, + 0xD32CA3DE, + 0xF551451E, + 0x035CD348, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xDE69A47A, + 0x1ED32CA3, + 0x48F55E79, + 0x00035C92, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xD228A3DE, + 0xF55E791E, + 0x035CD348, + 0x821A0186, + 0x0000D000, + 0x00000680, + 0xDE69A47A, + 0x1E9228A3, + 0x48F65E79, + 0x00035CD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x79E47A03, + 0xB2AAA3D9, + 0xF751451E, + 0x0342D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD159647A, + 0x1ED32CA3, + 0x48F75145, + 0x000342D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0x9228A3DE, + 0xF55E791E, + 0x034C9248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDE59647A, + 0x1ED32CA3, + 0x48F55E79, + 0x00035CD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x001A1A1A, + 0x005506A0, + 0x0000E1D4, + 0x005506A0, + 0x0000E1D4, + 0x005506A0, + 0x8000E1D4, + 0x00000200, + 0x00000004, + 0x04000000, + 0x00000009, + 0x00002410, + 0x00000040, + 0x41000000, + 0x00002082, + 0x00000350, + 0x000000DA, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x002A8350, + 0x000070EA, + 0x86000000, + 0x08000004, + 0x00000000, + 0x00482000, + 0x21800000, + 0x00101061, + 0x001541A8, + 0x00003875, + 0x001541A8, + 0x00003875, + 0x001541A8, + 0x20003875, + 0x00000080, + 0x00000001, + 0x41000000, + 0x00000002, + 0x00FF0904, + 0x00000000, + 0x90400000, + 0x00000820, + 0xC0000001, + 0xFFD606AF, + 0x86FFFFFF, + 0x0A0A78B4, + 0x000D020A, + 0x00006800, + 0x00824320, + 0xEF34D23D, + 0x8F691451, + 0xA47AAF3C, + 0x0001AE69, + 0x00410D00, + 0x40000068, + 0x3D000003, + 0x91E8ACB2, + 0x2C8F49E7, + 0x69A47A2B, + 0x000001AE, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000540, + 0x000003A8, + 0x00AA0D40, + 0x8001C3A8, + 0x0000007F, + 0x00000000, + 0x00004060, + 0xE1208000, + 0x0000001F, + 0x00004100, +}; diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c new file mode 100644 index 0000000000..02c995fe45 --- /dev/null +++ b/arch/arm/boards/altera-socdk/lowlevel.c @@ -0,0 +1,76 @@ +#include <common.h> +#include <linux/sizes.h> +#include <io.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/generic.h> +#include <debug_ll.h> +#include <asm/cache.h> +#include "sdram_config.h" +#include <mach/sdram_config.h> +#include "pinmux_config.c" +#include "pll_config.h" +#include <mach/pll_config.h> +#include "sequencer_defines.h" +#include "sequencer_auto.h" +#include <mach/sequencer.c> +#include "sequencer_auto_inst_init.c" +#include "sequencer_auto_ac_init.c" +#include "iocsr_config_cyclone5.c" + +extern char __dtb_socfpga_cyclone5_socdk_start[]; + +ENTRY_FUNCTION(start_socfpga_socdk, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_socfpga_cyclone5_socdk_start - get_runtime_offset(); + + barebox_arm_entry(0x0, SZ_1G, fdt); +} + +static noinline void socdk_entry(void) +{ + struct socfpga_io_config io_config; + int ret; + + arm_early_mmu_cache_invalidate(); + + relocate_to_current_adr(); + setup_c(); + + io_config.pinmux = sys_mgr_init_table; + io_config.num_pin = ARRAY_SIZE(sys_mgr_init_table); + io_config.iocsr_emac_mixed2 = iocsr_scan_chain0_table; + io_config.iocsr_mixed1_flash = iocsr_scan_chain1_table; + io_config.iocsr_general = iocsr_scan_chain2_table; + io_config.iocsr_ddr = iocsr_scan_chain3_table; + + socfpga_lowlevel_init(&cm_default_cfg, &io_config); + + puts_ll("lowlevel init done\n"); + puts_ll("SDRAM setup...\n"); + + socfpga_sdram_mmr_init(); + + puts_ll("SDRAM calibration...\n"); + + ret = socfpga_mem_calibration(); + if (!ret) + hang(); + + puts_ll("done\n"); + + barebox_arm_entry(0x0, SZ_1G, NULL); +} + +ENTRY_FUNCTION(start_socfpga_socdk_xload, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K - 16); + + socdk_entry(); +} diff --git a/arch/arm/boards/altera-socdk/pinmux_config.c b/arch/arm/boards/altera-socdk/pinmux_config.c new file mode 100644 index 0000000000..ff784bbecf --- /dev/null +++ b/arch/arm/boards/altera-socdk/pinmux_config.c @@ -0,0 +1,241 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <common.h> + +/* pin MUX configuration data */ +static unsigned long sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 3, /* GENERALIO0 */ + 3, /* GENERALIO1 */ + 3, /* GENERALIO2 */ + 3, /* GENERALIO3 */ + 3, /* GENERALIO4 */ + 3, /* GENERALIO5 */ + 3, /* GENERALIO6 */ + 3, /* GENERALIO7 */ + 3, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 2, /* GENERALIO13 */ + 2, /* GENERALIO14 */ + 3, /* GENERALIO15 */ + 3, /* GENERALIO16 */ + 2, /* GENERALIO17 */ + 2, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; diff --git a/arch/arm/boards/altera-socdk/pll_config.h b/arch/arm/boards/altera-socdk/pll_config.h new file mode 100644 index 0000000000..a9d05fa004 --- /dev/null +++ b/arch/arm/boards/altera-socdk/pll_config.h @@ -0,0 +1,107 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PRELOADER_PLL_CONFIG_H_ +#define _PRELOADER_PLL_CONFIG_H_ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 (1) + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (73) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (4) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (18) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1850000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) +#define CONFIG_HPS_CLK_EMAC0_HZ (1953125) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (370000000) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (100000000) +#define CONFIG_HPS_CLK_CAN1_HZ (12500000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) + +#define CONFIG_HPS_ALTERAGRP_MPUCLK (1) +#define CONFIG_HPS_ALTERAGRP_MAINCLK (4) +#define CONFIG_HPS_ALTERAGRP_DBGATCLK (4) + +#endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/arch/arm/boards/altera-socdk/sdram_config.h b/arch/arm/boards/altera-socdk/sdram_config.h new file mode 100644 index 0000000000..85dcd9e40e --- /dev/null +++ b/arch/arm/boards/altera-socdk/sdram_config.h @@ -0,0 +1,108 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SDRAM_CONFIG_H +#define __SDRAM_CONFIG_H + +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN (1) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN (1) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN (1) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT (10) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL (7) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW (12) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC (104) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI (3120) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS (14) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (20) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (512) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES (8) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS (1) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (40) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK (3) +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2) +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2) +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE (0) +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC (0) +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x3FFD1088) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 (0x21084210) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x1EF84) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x2020) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0xF800) +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 (0x200) + +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH (0x44555) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP (0x2C011000) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP (0xB00088) +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP (0x760210) +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP (0x980543) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR (0x5A56A) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 (0x20820820) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 (0x8208208) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ +(0x0101) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x0) + +#endif /*#ifndef__SDRAM_CONFIG_H */ diff --git a/arch/arm/boards/altera-socdk/sequencer_auto.h b/arch/arm/boards/altera-socdk/sequencer_auto.h new file mode 100644 index 0000000000..d965c5cde5 --- /dev/null +++ b/arch/arm/boards/altera-socdk/sequencer_auto.h @@ -0,0 +1,227 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#define __RW_MGR_ac_mrs1 0x04 +#define __RW_MGR_ac_mrs3 0x06 +#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C +#define __RW_MGR_ac_act_1 0x11 +#define __RW_MGR_ac_write_postdata 0x1A +#define __RW_MGR_ac_act_0 0x10 +#define __RW_MGR_ac_des 0x0D +#define __RW_MGR_ac_init_reset_1_cke_0 0x01 +#define __RW_MGR_ac_write_data 0x19 +#define __RW_MGR_ac_init_reset_0_cke_0 0x00 +#define __RW_MGR_ac_read_bank_0_1_norden 0x22 +#define __RW_MGR_ac_pre_all 0x12 +#define __RW_MGR_ac_mrs0_user 0x02 +#define __RW_MGR_ac_mrs0_dll_reset 0x03 +#define __RW_MGR_ac_read_bank_0_0 0x1D +#define __RW_MGR_ac_write_bank_0_col_1 0x16 +#define __RW_MGR_ac_read_bank_0_1 0x1F +#define __RW_MGR_ac_write_bank_1_col_0 0x15 +#define __RW_MGR_ac_write_bank_1_col_1 0x17 +#define __RW_MGR_ac_write_bank_0_col_0 0x14 +#define __RW_MGR_ac_read_bank_1_0 0x1E +#define __RW_MGR_ac_mrs1_mirr 0x0A +#define __RW_MGR_ac_read_bank_1_1 0x20 +#define __RW_MGR_ac_des_odt_1 0x0E +#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09 +#define __RW_MGR_ac_zqcl 0x07 +#define __RW_MGR_ac_write_predata 0x18 +#define __RW_MGR_ac_mrs0_user_mirr 0x08 +#define __RW_MGR_ac_ref 0x13 +#define __RW_MGR_ac_nop 0x0F +#define __RW_MGR_ac_rdimm 0x23 +#define __RW_MGR_ac_mrs2_mirr 0x0B +#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B +#define __RW_MGR_ac_read_en 0x21 +#define __RW_MGR_ac_mrs3_mirr 0x0C +#define __RW_MGR_ac_mrs2 0x05 +#define __RW_MGR_CONTENT_ac_mrs1 0x10090044 +#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000 +#define __RW_MGR_CONTENT_ac_act_1 0x106B0000 +#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000 +#define __RW_MGR_CONTENT_ac_act_0 0x10680000 +#define __RW_MGR_CONTENT_ac_des 0x30780000 +#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000 +#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000 +#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000 +#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008 +#define __RW_MGR_CONTENT_ac_pre_all 0x10280400 +#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080431 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080530 +#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008 +#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008 +#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000 +#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000 +#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000 +#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0024 +#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008 +#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100804C8 +#define __RW_MGR_CONTENT_ac_zqcl 0x10380400 +#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000 +#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080449 +#define __RW_MGR_CONTENT_ac_ref 0x10480000 +#define __RW_MGR_CONTENT_ac_nop 0x30780000 +#define __RW_MGR_CONTENT_ac_rdimm 0x10780000 +#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090010 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000 +#define __RW_MGR_CONTENT_ac_read_en 0x33780000 +#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000 +#define __RW_MGR_CONTENT_ac_mrs2 0x100A0008 + +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#define __RW_MGR_READ_B2B_WAIT2 0x6B +#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define __RW_MGR_REFRESH_ALL 0x14 +#define __RW_MGR_ZQCL 0x06 +#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define __RW_MGR_ACTIVATE_0_AND_1 0x0D +#define __RW_MGR_MRS2_MIRR 0x0A +#define __RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define __RW_MGR_ACTIVATE_1 0x0F +#define __RW_MGR_MRS2 0x04 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define __RW_MGR_MRS1 0x03 +#define __RW_MGR_IDLE_LOOP1 0x7B +#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define __RW_MGR_MRS3 0x05 +#define __RW_MGR_IDLE_LOOP2 0x7A +#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define __RW_MGR_RDIMM_CMD 0x79 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define __RW_MGR_GUARANTEED_READ_CONT 0x54 +#define __RW_MGR_REFRESH_DELAY 0x15 +#define __RW_MGR_MRS3_MIRR 0x0B +#define __RW_MGR_IDLE 0x00 +#define __RW_MGR_READ_B2B 0x59 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define __RW_MGR_GUARANTEED_WRITE 0x18 +#define __RW_MGR_PRECHARGE_ALL 0x12 +#define __RW_MGR_SGLE_READ 0x7D +#define __RW_MGR_MRS0_USER_MIRR 0x0C +#define __RW_MGR_RETURN 0x01 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define __RW_MGR_MRS0_USER 0x07 +#define __RW_MGR_GUARANTEED_READ 0x4C +#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define __RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define __RW_MGR_MRS0_DLL_RESET 0x02 +#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define __RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define __RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define __RW_MGR_MRS1_MIRR 0x09 +#define __RW_MGR_READ_B2B_WAIT1 0x61 +#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 +#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980 +#define __RW_MGR_CONTENT_ZQCL 0x008380 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800 +#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580 +#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680 +#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880 +#define __RW_MGR_CONTENT_MRS2 0x008280 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00 +#define __RW_MGR_CONTENT_MRS1 0x008200 +#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8 +#define __RW_MGR_CONTENT_MRS3 0x008300 +#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88 +#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 +#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 +#define __RW_MGR_CONTENT_REFRESH_DELAY 0x00A680 +#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600 +#define __RW_MGR_CONTENT_IDLE 0x080000 +#define __RW_MGR_CONTENT_READ_B2B 0x040E88 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 +#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 +#define __RW_MGR_CONTENT_SGLE_READ 0x040F08 +#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 +#define __RW_MGR_CONTENT_RETURN 0x080680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80 +#define __RW_MGR_CONTENT_MRS0_USER 0x008100 +#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168 +#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480 +#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00 +#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80 +#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 +#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500 +#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 diff --git a/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c new file mode 100644 index 0000000000..6531383807 --- /dev/null +++ b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c @@ -0,0 +1,68 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +static const uint32_t ac_rom_init_size = 36; +static const uint32_t ac_rom_init[36] = { + 0x20700000, + 0x20780000, + 0x10080431, + 0x10080530, + 0x10090044, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080449, + 0x100804c8, + 0x100a0024, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; diff --git a/arch/arm/boards/altera-socdk/sequencer_auto_inst_init.c b/arch/arm/boards/altera-socdk/sequencer_auto_inst_init.c new file mode 100644 index 0000000000..9e4f18df0f --- /dev/null +++ b/arch/arm/boards/altera-socdk/sequencer_auto_inst_init.c @@ -0,0 +1,159 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +static const uint32_t inst_rom_init_size = 127; +static const uint32_t inst_rom_init[127] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; diff --git a/arch/arm/boards/altera-socdk/sequencer_defines.h b/arch/arm/boards/altera-socdk/sequencer_defines.h new file mode 100644 index 0000000000..55e5cdfb02 --- /dev/null +++ b/arch/arm/boards/altera-socdk/sequencer_defines.h @@ -0,0 +1,162 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _SEQUENCER_DEFINES_H_ +#define _SEQUENCER_DEFINES_H_ + +#define AC_ROM_MR1_MIRR 0000000100100 +#define AC_ROM_MR1_OCD_ENABLE +#define AC_ROM_MR2_MIRR 0000000010000 +#define AC_ROM_MR3_MIRR 0000000000000 +#define AC_ROM_MR0_CALIB +#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000 +#define AC_ROM_MR0_DLL_RESET 0010100110000 +#define AC_ROM_MR0_MIRR 0010001001001 +#define AC_ROM_MR0 0010000110001 +#define AC_ROM_MR1 0000001000100 +#define AC_ROM_MR2 0000000001000 +#define AC_ROM_MR3 0000000000000 +#define AC_ROM_USER_ADD_0 0_0000_0000_0000 +#define AC_ROM_USER_ADD_1 0_0000_0000_1000 +#define AFI_CLK_FREQ 401 +#define AFI_RATE_RATIO 1 +#define AP_MODE 0 +#define ARRIAVGZ 0 +#define ARRIAV 0 +#define AVL_CLK_FREQ 67 +#define BFM_MODE 0 +#define BURST2 0 +#define CALIBRATE_BIT_SLIPS 0 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define CYCLONEV 1 +#define DDR2 0 +#define DDR3 1 +#define DDRX 1 +#define DM_PINS_ENABLED 1 +#define ENABLE_ASSERT 0 +#define ENABLE_BRINGUP_DEBUGGING 0 +#define ENABLE_DELAY_CHAIN_WRITE 0 +#define ENABLE_DQS_IN_CENTERING 1 +#define ENABLE_DQS_OUT_CENTERING 0 +#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 +#define ENABLE_INST_ROM_WRITE 1 +#define ENABLE_MARGIN_REPORT_GEN 0 +#define ENABLE_NON_DESTRUCTIVE_CALIB 0 +#define ENABLE_NON_DES_CAL_TEST 0 +#define ENABLE_NON_DES_CAL 0 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define ENABLE_TCL_DEBUG 0 +#define FAKE_CAL_FAIL 0 +#define FULL_RATE 1 +#define GUARANTEED_READ_BRINGUP_TEST 0 +#define HALF_RATE 0 +#define HARD_PHY 1 +#define HARD_VFIFO 1 +#define HCX_COMPAT_MODE 0 +#define HHP_HPS_SIMULATION 0 +#define HHP_HPS_VERIFICATION 0 +#define HHP_HPS 1 +#define HPS_HW 1 +#define HR_DDIO_OUT_HAS_THREE_REGS 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DM_OUT_RESERVE 0 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_DQ_OUT_RESERVE 0 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define LPDDR1 0 +#define LPDDR2 0 +#define LRDIMM 0 +#define MARGIN_VARIATION_TEST 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define MEM_ADDR_WIDTH 13 +#define MRS_MIRROR_PING_PONG_ATSO 0 +#define MULTIPLE_AFI_WLAT 0 +#define NON_DES_CAL 0 +#define NUM_SHADOW_REGS 1 +#define QDRII 0 +#define QUARTER_RATE 0 +#define RDIMM 0 +#define READ_AFTER_WRITE_CALIBRATION 1 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define RLDRAM3 0 +#define RLDRAMII 0 +#define RLDRAMX 0 +#define RUNTIME_CAL_REPORT 0 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_ADDRESS_WIDTH 15 +#define RW_MGR_MEM_BANK_WIDTH 3 +#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1 +#define RW_MGR_MEM_CLK_EN_WIDTH 1 +#define RW_MGR_MEM_CONTROL_WIDTH 1 +#define RW_MGR_MEM_DATA_MASK_WIDTH 5 +#define RW_MGR_MEM_DATA_WIDTH 40 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_ODT_WIDTH 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_MR0_BL 1 +#define RW_MGR_MR0_CAS_LATENCY 3 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5 +#define RW_MGR_WRITE_TO_DEBUG_READ 1.0 +#define SKEW_CALIBRATION 0 +#define STATIC_FULL_CALIBRATION 1 +#define STATIC_SIM_FILESET 0 +#define STATIC_SKIP_MEM_INIT 0 +#define STRATIXV 0 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TINIT_CNTR0_VAL 99 +#define TRACKING_ERROR_TEST 0 +#define TRACKING_WATCH_TEST 0 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 +#define TRESET_CNTR0_VAL 99 +#define USE_DQS_TRACKING 1 +#define USE_SHADOW_REGS 0 +#define USE_USER_RDIMM_VALUE 0 + +#endif /* _SEQUENCER_DEFINES_H_ */ diff --git a/arch/arm/boards/at91sam9m10ihd/env/nv/linux.bootargs.base b/arch/arm/boards/at91sam9m10ihd/env/nv/linux.bootargs.console index 476b1fbe49..476b1fbe49 100644 --- a/arch/arm/boards/at91sam9m10ihd/env/nv/linux.bootargs.base +++ b/arch/arm/boards/at91sam9m10ihd/env/nv/linux.bootargs.console diff --git a/arch/arm/boards/avnet-zedboard/env/nv/linux.bootargs.base b/arch/arm/boards/avnet-zedboard/env/nv/linux.bootargs.console index 6c9f9dabcf..6c9f9dabcf 100644 --- a/arch/arm/boards/avnet-zedboard/env/nv/linux.bootargs.base +++ b/arch/arm/boards/avnet-zedboard/env/nv/linux.bootargs.console diff --git a/arch/arm/boards/beagle/env/nv/linux.bootargs.base b/arch/arm/boards/beagle/env/nv/linux.bootargs.base deleted file mode 100644 index 5fef726ba3..0000000000 --- a/arch/arm/boards/beagle/env/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttyO2,115200 diff --git a/arch/arm/boards/ccxmx51/env/nv/linux.bootargs.base b/arch/arm/boards/ccxmx51/env/nv/linux.bootargs.base deleted file mode 100644 index d83eb9414a..0000000000 --- a/arch/arm/boards/ccxmx51/env/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -earlyprintk console=ttymxc0,115200n8 diff --git a/arch/arm/boards/clep7212/env/nv/linux.bootargs.base b/arch/arm/boards/clep7212/env/nv/linux.bootargs.console index 77ea2ecf0f..77ea2ecf0f 100644 --- a/arch/arm/boards/clep7212/env/nv/linux.bootargs.base +++ b/arch/arm/boards/clep7212/env/nv/linux.bootargs.console diff --git a/arch/arm/boards/crystalfontz-cfa10036/env/nv/linux.bootargs.base b/arch/arm/boards/crystalfontz-cfa10036/env/nv/linux.bootargs.console index 5b56cafbec..5b56cafbec 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/env/nv/linux.bootargs.base +++ b/arch/arm/boards/crystalfontz-cfa10036/env/nv/linux.bootargs.console diff --git a/arch/arm/boards/efika-mx-smartbook/env/nv/linux.bootargs.base b/arch/arm/boards/efika-mx-smartbook/env/nv/linux.bootargs.console index 04415e6303..04415e6303 100644 --- a/arch/arm/boards/efika-mx-smartbook/env/nv/linux.bootargs.base +++ b/arch/arm/boards/efika-mx-smartbook/env/nv/linux.bootargs.console diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 4edbbe4b8a..7ae8a18e06 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -37,6 +37,8 @@ void __bare_init __naked barebox_arm_reset_vector(void) arm_cpu_lowlevel_init(); + arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12); + /* restart the MPLL and wait until it's stable */ writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27), MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); @@ -127,12 +129,9 @@ void __bare_init __naked barebox_arm_reset_vector(void) writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000); writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { - /* setup a stack to be able to call imx25_barebox_boot_nand_external() */ - arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12); - + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) imx25_barebox_boot_nand_external(0); - } + out: imx25_barebox_entry(NULL); } diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S index f8e3c23540..b3504832d7 100644 --- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -76,6 +76,8 @@ barebox_arm_reset_vector: bl arm_cpu_lowlevel_init + ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4; + /* ahb lite ip interface */ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) @@ -124,9 +126,6 @@ barebox_arm_reset_vector: sdram_init #ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND - /* Setup a temporary stack in SDRAM */ - ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4; - mov r0, #0 b imx27_barebox_boot_nand_external #endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index 4788ae2e42..83c25feb41 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -43,6 +43,8 @@ void __bare_init __naked barebox_arm_reset_vector(void) arm_cpu_lowlevel_init(); + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + r = get_cr(); r |= CR_Z; /* Flow prediction (Z) */ r |= CR_U; /* unaligned accesses */ @@ -137,9 +139,6 @@ void __bare_init __naked barebox_arm_reset_vector(void) r |= 0x1 << 28; writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - imx35_barebox_boot_nand_external(0); } diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c index 7a85b489d2..ad89076329 100644 --- a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c @@ -6,5 +6,6 @@ void __naked barebox_arm_reset_vector(void) { imx5_cpu_lowlevel_init(); + arm_setup_stack(0x20000000 - 16); imx51_barebox_entry(NULL); } diff --git a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S index 4ca4c82d32..a5d54e8d01 100644 --- a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S @@ -17,6 +17,7 @@ * */ +#include <linux/sizes.h> #include <asm-generic/memory_layout.h> #include <mach/imx25-regs.h> #include <mach/imx-pll.h> @@ -71,6 +72,9 @@ barebox_arm_reset_vector: writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2) writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR) + /* Setup a temporary stack in SRAM */ + ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4 + /* Skip SDRAM initialization if we run from RAM */ cmp pc, #0x80000000 bls 1f @@ -99,9 +103,6 @@ barebox_arm_reset_vector: #ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND - /* Setup a temporary stack in SRAM */ - ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4 - mov r0, #0 b imx25_barebox_boot_nand_external #endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ diff --git a/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S index 45f39921ec..e79b96dd2c 100644 --- a/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S @@ -54,6 +54,8 @@ barebox_arm_reset_vector: bl arm_cpu_lowlevel_init + ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4; + /* ahb lite ip interface */ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) diff --git a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S index 6d37f35a2e..0f9e813191 100644 --- a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S @@ -60,6 +60,9 @@ CCM_BASE_ADDR_W: .word MX35_CCM_BASE_ADDR barebox_arm_reset_vector: bl arm_cpu_lowlevel_init + /* Setup a temporary stack in internal SRAM */ + ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4 + mrc 15, 0, r1, c1, c0, 0 mrc 15, 0, r0, c1, c0, 1 @@ -155,9 +158,6 @@ barebox_arm_reset_vector: str r3, [r0, #0x30] #ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND - /* Setup a temporary stack in internal SRAM */ - ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4 - mov r0, #0 b imx35_barebox_boot_nand_external #endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c index 1b9ba16ef6..0f453f3367 100644 --- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c +++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c @@ -11,6 +11,7 @@ ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); + arm_setup_stack(0x20000000 - 16); fdt = __dtb_imx51_babbage_start - get_runtime_offset(); diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c index f65b55658f..dd2abb5f5d 100644 --- a/arch/arm/boards/freescale-mx53-qsb/board.c +++ b/arch/arm/boards/freescale-mx53-qsb/board.c @@ -85,10 +85,6 @@ static int loco_late_init(void) !of_machine_is_compatible("fsl,imx53-qsrb")) return 0; - device_detect_by_name("mmc0"); - - devfs_add_partition("mmc0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); - mc34708 = mc13xxx_get(); if (mc34708) { unsigned int val; diff --git a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c index aff6e3bc54..ce6a290ca2 100644 --- a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c @@ -12,6 +12,7 @@ ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); + arm_setup_stack(0xf8020000 - 8); fdt = __dtb_imx53_qsb_start - get_runtime_offset(); @@ -25,6 +26,7 @@ ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); + arm_setup_stack(0xf8020000 - 8); fdt = __dtb_imx53_qsrb_start - get_runtime_offset(); diff --git a/arch/arm/boards/freescale-mx53-smd/lowlevel.c b/arch/arm/boards/freescale-mx53-smd/lowlevel.c index 306db09acf..5ad0312e82 100644 --- a/arch/arm/boards/freescale-mx53-smd/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-smd/lowlevel.c @@ -6,5 +6,6 @@ void __naked barebox_arm_reset_vector(void) { imx5_cpu_lowlevel_init(); + arm_setup_stack(0xf8020000 - 8); imx53_barebox_entry(NULL); } diff --git a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c index 487a9fd899..3545a1c352 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c @@ -11,6 +11,7 @@ ENTRY_FUNCTION(start_imx53_vmx53, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); + arm_setup_stack(0xf8020000 - 8); fdt = __dtb_imx53_voipac_bsb_start - get_runtime_offset(); diff --git a/arch/arm/boards/freescale-mx6-arm2/board.c b/arch/arm/boards/freescale-mx6-arm2/board.c deleted file mode 100644 index 3d5576c065..0000000000 --- a/arch/arm/boards/freescale-mx6-arm2/board.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) 2012 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <init.h> -#include <environment.h> -#include <mach/imx6-regs.h> -#include <fec.h> -#include <gpio.h> -#include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <linux/phy.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <mach/generic.h> -#include <linux/sizes.h> -#include <mach/imx6.h> -#include <mach/devices-imx6.h> -#include <mach/iomux-mx6.h> - -static iomux_v3_cfg_t arm2_pads[] = { - /* UART1 */ - MX6Q_PAD_KEY_COL0__UART4_TXD, - MX6Q_PAD_KEY_ROW0__UART4_RXD, - - MX6Q_PAD_SD1_CLK__USDHC1_CLK, - MX6Q_PAD_SD1_CMD__USDHC1_CMD, - MX6Q_PAD_SD1_DAT0__USDHC1_DAT0, - MX6Q_PAD_SD1_DAT1__USDHC1_DAT1, - MX6Q_PAD_SD1_DAT2__USDHC1_DAT2, - MX6Q_PAD_SD1_DAT3__USDHC1_DAT3, - - MX6Q_PAD_SD2_CLK__USDHC2_CLK, - MX6Q_PAD_SD2_CMD__USDHC2_CMD, - MX6Q_PAD_SD2_DAT0__USDHC2_DAT0, - MX6Q_PAD_SD2_DAT1__USDHC2_DAT1, - MX6Q_PAD_SD2_DAT2__USDHC2_DAT2, - MX6Q_PAD_SD2_DAT3__USDHC2_DAT3, - - MX6Q_PAD_SD3_CLK__USDHC3_CLK, - MX6Q_PAD_SD3_CMD__USDHC3_CMD, - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0, - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1, - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2, - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3, - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4, - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5, - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6, - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7, - MX6Q_PAD_GPIO_18__USDHC3_VSELECT, - - MX6Q_PAD_SD4_CLK__USDHC4_CLK, - MX6Q_PAD_SD4_CMD__USDHC4_CMD, - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0, - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1, - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2, - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3, - MX6Q_PAD_SD4_DAT4__USDHC4_DAT4, - MX6Q_PAD_SD4_DAT5__USDHC4_DAT5, - MX6Q_PAD_SD4_DAT6__USDHC4_DAT6, - MX6Q_PAD_SD4_DAT7__USDHC4_DAT7, - - MX6Q_PAD_KEY_COL1__ENET_MDIO, - MX6Q_PAD_KEY_COL2__ENET_MDC, - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC, - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0, - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1, - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2, - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3, - MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL, - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK, - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC, - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0, - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1, - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2, - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3, - MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL, - MX6Q_PAD_GPIO_0__CCM_CLKO, - MX6Q_PAD_GPIO_3__CCM_CLKO2, -}; - -static int arm2_mem_init(void) -{ - arm_add_mem_device("ram0", 0x10000000, SZ_2G); - - return 0; -} -mem_initcall(arm2_mem_init); - -static void mx6_rgmii_rework(struct phy_device *dev) -{ - u16 val; - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(dev, 0xd, 0x7); - phy_write(dev, 0xe, 0x8016); - phy_write(dev, 0xd, 0x4007); - - val = phy_read(dev, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(dev, 0xe, val); - - /* introduce tx clock delay */ - phy_write(dev, 0x1d, 0x5); - - val = phy_read(dev, 0x1e); - val |= 0x0100; - phy_write(dev, 0x1e, val); -} - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RGMII, - .phy_init = mx6_rgmii_rework, - .phy_addr = 0, -}; - -static int arm2_devices_init(void) -{ - imx6_add_mmc3(NULL); - - imx6_add_fec(&fec_info); - - armlinux_set_architecture(3837); - - devfs_add_partition("disk0", 0, SZ_1M, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("disk0", SZ_1M + SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "env0"); - - return 0; -} - -device_initcall(arm2_devices_init); - -static int arm2_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(arm2_pads, ARRAY_SIZE(arm2_pads)); - - barebox_set_model("Freescale i.MX6 Armadillo2"); - barebox_set_hostname("armadillo2"); - - imx6_add_uart3(); - - return 0; -} -console_initcall(arm2_console_init); diff --git a/arch/arm/boards/freescale-mx6-arm2/env/config b/arch/arm/boards/freescale-mx6-arm2/env/config deleted file mode 100644 index 0ab5bdf0e0..0000000000 --- a/arch/arm/boards/freescale-mx6-arm2/env/config +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/sh - -machine=armadillo2 -serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=disk - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-$machine.$rootfs_type - -# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo -kernelimage=zImage-$machine - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$serverip:/home/$user/nfsroot/$machine" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc2,115200" - -disk_parts="1M(barebox)ro,3M(bareboxenv),4M(kernel),-(root)" - -rootfs_part_linux_dev=sda1 -rootfs_type=ext2 - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/freescale-mx6-arm2/flash-header.imxcfg b/arch/arm/boards/freescale-mx6-arm2/flash-header.imxcfg deleted file mode 100644 index 403d184834..0000000000 --- a/arch/arm/boards/freescale-mx6-arm2/flash-header.imxcfg +++ /dev/null @@ -1,122 +0,0 @@ -soc imx6 -loadaddr 0x10000000 -dcdofs 0x400 - -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 - -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 - -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 - -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 - -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 - -wm 32 0x020e057c 0x00020030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 - -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 - -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 - -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 - -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0798 0x000C0000 - -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 - -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 - -wm 32 0x021b0018 0x00081740 - -wm 32 0x021b001c 0x00008000 -wm 32 0x021b000c 0x555A7975 -wm 32 0x021b0010 0xFF538E64 -wm 32 0x021b0014 0x01FF00DB -wm 32 0x021b002c 0x000026D2 - -wm 32 0x021b0030 0x005B0E21 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0xC31A0000 - -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803A -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803B -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 - -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xA1380003 -wm 32 0x021b4800 0xA1380003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00022227 -wm 32 0x021b4818 0x00022227 - -wm 32 0x021b083c 0x434B0350 -wm 32 0x021b0840 0x034C0359 -wm 32 0x021b483c 0x434B0350 -wm 32 0x021b4840 0x03650348 -wm 32 0x021b0848 0x4436383B -wm 32 0x021b4848 0x39393341 -wm 32 0x021b0850 0x35373933 -wm 32 0x021b4850 0x48254A36 - -wm 32 0x021b080c 0x001F001F -wm 32 0x021b0810 0x001F001F - -wm 32 0x021b480c 0x00440044 -wm 32 0x021b4810 0x00440044 - -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 - -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 - -/* enable AXI cache for VDOA/VPU/IPU */ -wm 32 0x020e0010 0xf00000ff - -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -wm 32 0x020e0018 0x007f007f -wm 32 0x020e001c 0x007f007f diff --git a/arch/arm/boards/freescale-mx6-arm2/lowlevel.c b/arch/arm/boards/freescale-mx6-arm2/lowlevel.c deleted file mode 100644 index f833893335..0000000000 --- a/arch/arm/boards/freescale-mx6-arm2/lowlevel.c +++ /dev/null @@ -1,11 +0,0 @@ -#include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/generic.h> - -void __naked barebox_arm_reset_vector(void) -{ - imx6_cpu_lowlevel_init(); - barebox_arm_entry(0x10000000, SZ_2G, NULL); -} diff --git a/arch/arm/boards/friendlyarm-mini2440/Kconfig b/arch/arm/boards/friendlyarm-mini2440/Kconfig index a8e79b3b07..feb905e96e 100644 --- a/arch/arm/boards/friendlyarm-mini2440/Kconfig +++ b/arch/arm/boards/friendlyarm-mini2440/Kconfig @@ -25,4 +25,10 @@ config MINI2440_VIDEO_SVGA help This adds support for MINI2440 SVGA (1024x768) video output adapter. +config MINI2440_VIDEO_W35 + bool "Support W35 display (320x240)" + select MINI2440_VIDEO + help + This adds support for Sharp 3.5 inch TFT display. + endif diff --git a/arch/arm/boards/friendlyarm-mini2440/mini2440.c b/arch/arm/boards/friendlyarm-mini2440/mini2440.c index 2dcb7db4db..b59c8367f3 100644 --- a/arch/arm/boards/friendlyarm-mini2440/mini2440.c +++ b/arch/arm/boards/friendlyarm-mini2440/mini2440.c @@ -29,6 +29,7 @@ #include <asm/sections.h> #include <io.h> #include <gpio.h> +#include <mach/bbu.h> #include <mach/iomux.h> #include <mach/s3c-iomap.h> #include <mach/devices-s3c24xx.h> @@ -116,6 +117,23 @@ static struct fb_videomode s3c24x0_fb_modes[] = { .vmode = FB_VMODE_NONINTERLACED, }, #endif +#ifdef CONFIG_MINI2440_VIDEO_W35 + { + .name = "W35", + .refresh = 60, + .xres = 320, + .left_margin = 68, + .right_margin = 66, + .hsync_len = 4, + .yres = 240, + .upper_margin = 4, + .lower_margin = 4, + .vsync_len = 9, + .pixclock = 115913, + .sync = FB_SYNC_USE_PWREN | FB_SYNC_CLK_INVERT, + .vmode = FB_VMODE_NONINTERLACED, + }, +#endif }; static struct s3c_fb_platform_data s3c24x0_fb_data = { @@ -300,6 +318,8 @@ static int mini2440_devices_init(void) devfs_del_partition("env_raw"); devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); + + s3c24x0_bbu_nand_register_handler(); #endif s3c24xx_add_mci(&mci_data); s3c24xx_add_fb(&s3c24x0_fb_data); diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index 6fc90fbbdc..bcd2a24f8f 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -313,9 +313,6 @@ void __bare_init __naked barebox_arm_reset_vector(void) r0 |= 0x1 << 28; writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - imx35_barebox_boot_nand_external(0); } diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index 2828359598..98512a976c 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -39,6 +39,8 @@ void __bare_init __naked barebox_arm_reset_vector(void) arm_cpu_lowlevel_init(); + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); + /* ahb lite ip interface */ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); @@ -86,12 +88,8 @@ void __bare_init __naked barebox_arm_reset_vector(void) ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { - /* setup a stack to be able to call imx27_barebox_boot_nand_external() */ - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); - + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) imx27_barebox_boot_nand_external(0); - } out: imx27_barebox_entry(NULL); diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c index 0c46ade9fc..ded7a3797e 100644 --- a/arch/arm/boards/guf-vincell/board.c +++ b/arch/arm/boards/guf-vincell/board.c @@ -29,6 +29,7 @@ #include <io.h> #include <i2c/i2c.h> #include <linux/clk.h> +#include <usb/fsl_usb2.h> #include <generated/mach-types.h> @@ -42,6 +43,7 @@ #include <mach/bbu.h> #include <mach/imx-flash-header.h> #include <mach/imx5.h> +#include <mach/usb.h> #include <asm/armlinux.h> #include <asm/mmu.h> @@ -265,6 +267,11 @@ static struct i2c_board_info i2c_devices[] = { }, }; +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, +}; + static int vincell_devices_init(void) { writel(0, MX53_M4IF_BASE_ADDR + 0xc); @@ -280,6 +287,9 @@ static int vincell_devices_init(void) i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); imx53_add_i2c0(NULL); + add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX53_OTG_BASE_ADDR, 0x200, + IORESOURCE_MEM, &usb_pdata); + vincell_fec_reset(); armlinux_set_architecture(3297); diff --git a/arch/arm/boards/guf-vincell/env/nv/linux.bootargs.base b/arch/arm/boards/guf-vincell/env/nv/linux.bootargs.base deleted file mode 100644 index d775310b40..0000000000 --- a/arch/arm/boards/guf-vincell/env/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttymxc0,115200 diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c index 00e34fba39..629529d90a 100644 --- a/arch/arm/boards/guf-vincell/lowlevel.c +++ b/arch/arm/boards/guf-vincell/lowlevel.c @@ -129,6 +129,7 @@ void __bare_init __naked barebox_arm_reset_vector(void) u32 r; imx5_cpu_lowlevel_init(); + arm_setup_stack(0xf8020000 - 8); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); diff --git a/arch/arm/boards/highbank/env/nv/bootargs.base b/arch/arm/boards/highbank/env/nv/linux.bootargs.console index 826debe7c2..826debe7c2 100644 --- a/arch/arm/boards/highbank/env/nv/bootargs.base +++ b/arch/arm/boards/highbank/env/nv/linux.bootargs.console diff --git a/arch/arm/boards/imx233-olinuxino/defaultenv-imx233-olinuxino/nv/linux.bootargs.base b/arch/arm/boards/imx233-olinuxino/defaultenv-imx233-olinuxino/nv/linux.bootargs.console index 5b56cafbec..5b56cafbec 100644 --- a/arch/arm/boards/imx233-olinuxino/defaultenv-imx233-olinuxino/nv/linux.bootargs.base +++ b/arch/arm/boards/imx233-olinuxino/defaultenv-imx233-olinuxino/nv/linux.bootargs.console diff --git a/arch/arm/boards/karo-tx51/lowlevel.c b/arch/arm/boards/karo-tx51/lowlevel.c index 7a85b489d2..ad89076329 100644 --- a/arch/arm/boards/karo-tx51/lowlevel.c +++ b/arch/arm/boards/karo-tx51/lowlevel.c @@ -6,5 +6,6 @@ void __naked barebox_arm_reset_vector(void) { imx5_cpu_lowlevel_init(); + arm_setup_stack(0x20000000 - 16); imx51_barebox_entry(NULL); } diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c index 8adbd8d666..fdfb1b7573 100644 --- a/arch/arm/boards/karo-tx53/lowlevel.c +++ b/arch/arm/boards/karo-tx53/lowlevel.c @@ -8,6 +8,7 @@ void __naked barebox_arm_reset_vector(void) { imx5_cpu_lowlevel_init(); + arm_setup_stack(0xf8020000 - 8); /* * For the TX53 rev 8030 the SDRAM setup is not stable without diff --git a/arch/arm/boards/lubbock/env/nv/linux.bootargs.base b/arch/arm/boards/lubbock/env/nv/linux.bootargs.console index 476b1fbe49..476b1fbe49 100644 --- a/arch/arm/boards/lubbock/env/nv/linux.bootargs.base +++ b/arch/arm/boards/lubbock/env/nv/linux.bootargs.console diff --git a/arch/arm/boards/mx31moboard/env/nv/linux.bootargs.base b/arch/arm/boards/mx31moboard/env/nv/linux.bootargs.base deleted file mode 100644 index 84e488d459..0000000000 --- a/arch/arm/boards/mx31moboard/env/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttymxc0,921600 diff --git a/arch/arm/boards/panda/env/nv/linux.bootargs.base b/arch/arm/boards/panda/env/nv/linux.bootargs.base deleted file mode 100644 index 5fef726ba3..0000000000 --- a/arch/arm/boards/panda/env/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttyO2,115200 diff --git a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/nv/bootargs.base b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/nv/bootargs.base deleted file mode 100644 index 6b62c99dbf..0000000000 --- a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/nv/bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttymxc2,115200 diff --git a/arch/arm/boards/phytec-phycore-am335x/Makefile b/arch/arm/boards/phytec-phycore-am335x/Makefile deleted file mode 100644 index 173a6b6fd5..0000000000 --- a/arch/arm/boards/phytec-phycore-am335x/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -lwl-y += lowlevel.o -obj-y += board.o -bbenv-y += defaultenv-phycore-am335x diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/mmc b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/mmc deleted file mode 100644 index 6a6076101e..0000000000 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/mmc +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -global.bootm.image=/boot/linuximage -#global.bootm.oftree=/boot/oftree - -bootargs-ip - -global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rw rootwait" diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/nand b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/nand deleted file mode 100644 index 1dfbef9d8b..0000000000 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/nand +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" - -bootargs-ip - -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rw rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/spi b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/spi deleted file mode 100644 index 2f858bd0d9..0000000000 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/spi +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/m25p0.kernel" - -bootargs-ip - -# Use rootfs from NAND -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/init/init-usbserial b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/init/init-usbserial deleted file mode 100644 index a154fd1805..0000000000 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/init/init-usbserial +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -#otg1.mode=peripheral -usbgadget -a -A /dev/nand0.kernel.bb(kernel) diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/nv/bootargs.base b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/nv/bootargs.base deleted file mode 100644 index d7b01a1683..0000000000 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/nv/bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttyO0,115200 diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/nv/hostname b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/nv/hostname deleted file mode 100644 index 988ab6dd32..0000000000 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/nv/hostname +++ /dev/null @@ -1 +0,0 @@ -pcm051 diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c deleted file mode 100644 index 843929e945..0000000000 --- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c +++ /dev/null @@ -1,215 +0,0 @@ -#include <common.h> -#include <linux/sizes.h> -#include <io.h> -#include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/am33xx-silicon.h> -#include <mach/am33xx-clock.h> -#include <mach/generic.h> -#include <mach/sdrc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/am33xx-mux.h> -#include <mach/am33xx-generic.h> -#include <mach/wdt.h> -#include <debug_ll.h> - -static const struct am33xx_cmd_control pcm051_cmd = { - .slave_ratio0 = 0x80, - .dll_lock_diff0 = 0x0, - .invert_clkout0 = 0x0, - .slave_ratio1 = 0x80, - .dll_lock_diff1 = 0x0, - .invert_clkout1 = 0x0, - .slave_ratio2 = 0x80, - .dll_lock_diff2 = 0x0, - .invert_clkout2 = 0x0, -}; - -struct pcm051_sdram_timings { - struct am33xx_emif_regs regs; - struct am33xx_ddr_data data; -}; - -enum { - MT41J128M16125IT_256MB, - MT41J64M1615IT_128MB, - MT41J256M16HA15EIT_512MB, - MT41J512M8125IT_2x512MB, -}; - -struct pcm051_sdram_timings timings[] = { - /* 256MB */ - [MT41J128M16125IT_256MB] = { - .regs = { - .emif_read_latency = 0x7, - .emif_tim1 = 0x0AAAD4DB, - .emif_tim2 = 0x26437FDA, - .emif_tim3 = 0x501F83FF, - .sdram_config = 0x61C052B2, - .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x00000C30, - }, - .data = { - .rd_slave_ratio0 = 0x3B, - .wr_dqs_slave_ratio0 = 0x33, - .fifo_we_slave_ratio0 = 0x9c, - .wr_slave_ratio0 = 0x6f, - }, - }, - - /* 128MB */ - [MT41J64M1615IT_128MB] = { - .regs = { - .emif_read_latency = 0x7, - .emif_tim1 = 0x0AAAE4DB, - .emif_tim2 = 0x262F7FDA, - .emif_tim3 = 0x501F82BF, - .sdram_config = 0x61C05232, - .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x00000C30, - }, - .data = { - .rd_slave_ratio0 = 0x38, - .wr_dqs_slave_ratio0 = 0x34, - .fifo_we_slave_ratio0 = 0xA2, - .wr_slave_ratio0 = 0x72, - }, - }, - - /* 512MB */ - [MT41J256M16HA15EIT_512MB] = { - .regs = { - .emif_read_latency = 0x7, - .emif_tim1 = 0x0AAAE4DB, - .emif_tim2 = 0x266B7FDA, - .emif_tim3 = 0x501F867F, - .sdram_config = 0x61C05332, - .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x00000C30 - }, - .data = { - .rd_slave_ratio0 = 0x35, - .wr_dqs_slave_ratio0 = 0x43, - .fifo_we_slave_ratio0 = 0x97, - .wr_slave_ratio0 = 0x7b, - }, - }, - - /* 1024MB */ - [MT41J512M8125IT_2x512MB] = { - .regs = { - .emif_read_latency = 0x7, - .emif_tim1 = 0x0AAAE4DB, - .emif_tim2 = 0x266B7FDA, - .emif_tim3 = 0x501F867F, - .sdram_config = 0x61C053B2, - .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x00000C30 - }, - .data = { - .rd_slave_ratio0 = 0x32, - .wr_dqs_slave_ratio0 = 0x48, - .fifo_we_slave_ratio0 = 0x99, - .wr_slave_ratio0 = 0x80, - }, - }, -}; - -extern char __dtb_am335x_phytec_phycore_som_start[]; -extern char __dtb_am335x_phytec_phycore_som_mlo_start[]; -extern char __dtb_am335x_phytec_phycore_som_no_spi_start[]; - -/** - * @brief The basic entry point for board initialization. - * - * This is called as part of machine init (after arch init). - * This is again called with stack in SRAM, so not too many - * constructs possible here. - * - * @return void - */ -static noinline void pcm051_board_init(int sdram) -{ - void *fdt; - struct pcm051_sdram_timings *timing = &timings[sdram]; - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); - - writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); - - am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_400); - - am335x_sdram_init(0x18B, &pcm051_cmd, - &timing->regs, - &timing->data); - - am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE); - am33xx_enable_uart0_pin_mux(); - omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); - putc_ll('>'); - - fdt = __dtb_am335x_phytec_phycore_som_mlo_start - get_runtime_offset(); - - am335x_barebox_entry(fdt); -} - -static noinline void pcm051_board_entry(unsigned long bootinfo, int sdram) -{ - am33xx_save_bootinfo((void *)bootinfo); - - arm_cpu_lowlevel_init(); - - /* - * Setup C environment, the board init code uses global variables. - * Stackpointer has already been initialized by the ROM code. - */ - relocate_to_current_adr(); - setup_c(); - - pcm051_board_init(sdram); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_256mb, bootinfo, r1, r2) -{ - pcm051_board_entry(bootinfo, MT41J128M16125IT_256MB); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_128mb, bootinfo, r1, r2) -{ - pcm051_board_entry(bootinfo, MT41J64M1615IT_128MB); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_512mb, bootinfo, r1, r2) -{ - pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_512MB); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_2x512mb, bootinfo, r1, r2) -{ - pcm051_board_entry(bootinfo, MT41J512M8125IT_2x512MB); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2) -{ - void *fdt; - - fdt = __dtb_am335x_phytec_phycore_som_start - get_runtime_offset(); - - am335x_barebox_entry(fdt); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phycore_no_spi_sdram, r0, r1, r2) -{ - void *fdt; - - fdt = __dtb_am335x_phytec_phycore_som_no_spi_start - get_runtime_offset(); - - am335x_barebox_entry(fdt); -} diff --git a/arch/arm/boards/phytec-phycore-imx31/env/nv/linux.bootargs.base b/arch/arm/boards/phytec-phycore-imx31/env/nv/linux.bootargs.base deleted file mode 100644 index d775310b40..0000000000 --- a/arch/arm/boards/phytec-phycore-imx31/env/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttymxc0,115200 diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c index 44fc5bc765..27e275676f 100644 --- a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c @@ -39,6 +39,8 @@ void __bare_init __naked barebox_arm_reset_vector(void) arm_cpu_lowlevel_init(); + arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); + writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); @@ -125,12 +127,8 @@ void __bare_init __naked barebox_arm_reset_vector(void) writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); #endif - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { - /* setup a stack to be able to call imx31_barebox_boot_nand_external() */ - arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); - + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) imx31_barebox_boot_nand_external(0); - } else { + else imx31_barebox_entry(NULL); - } } diff --git a/arch/arm/boards/phytec-phycore-imx35/env/nv/linux.bootargs.base b/arch/arm/boards/phytec-phycore-imx35/env/nv/linux.bootargs.base deleted file mode 100644 index d775310b40..0000000000 --- a/arch/arm/boards/phytec-phycore-imx35/env/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttymxc0,115200 diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c index 919a9af3da..1ad5439c28 100644 --- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c @@ -49,6 +49,8 @@ void __bare_init __naked barebox_arm_reset_vector(void) arm_cpu_lowlevel_init(); + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + r = get_cr(); r |= CR_Z; /* Flow prediction (Z) */ r |= CR_U; /* unaligned accesses */ @@ -189,9 +191,6 @@ void __bare_init __naked barebox_arm_reset_vector(void) r |= 0x1 << 28; writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - imx35_barebox_boot_nand_external(0); } diff --git a/arch/arm/boards/phytec-phycore-pxa270/env/config b/arch/arm/boards/phytec-phycore-pxa270/env/config deleted file mode 100644 index d42780090b..0000000000 --- a/arch/arm/boards/phytec-phycore-pxa270/env/config +++ /dev/null @@ -1,45 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttyS0,115200" - -nor_parts="512k(barebox)ro,256k(bareboxenv),4M(kernel),-(root)" -rootfs_mtdblock_nor=3 - -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor new file mode 100644 index 0000000000..e617cbaaba --- /dev/null +++ b/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="512k(nor0.barebox),256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" +kernelname="physmap-flash.0" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/telit-evk-pro3/env/nv/bootargs.base b/arch/arm/boards/phytec-phycore-pxa270/env/nv/linux.bootargs.base index 476b1fbe49..476b1fbe49 100644 --- a/arch/arm/boards/telit-evk-pro3/env/nv/bootargs.base +++ b/arch/arm/boards/phytec-phycore-pxa270/env/nv/linux.bootargs.base diff --git a/arch/arm/boards/phytec-phyflex-am335x/Makefile b/arch/arm/boards/phytec-phyflex-am335x/Makefile deleted file mode 100644 index 54734b5736..0000000000 --- a/arch/arm/boards/phytec-phyflex-am335x/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -lwl-y += lowlevel.o -obj-y += board.o -bbenv-y += defaultenv-phyflex-am335x diff --git a/arch/arm/boards/phytec-phyflex-am335x/board.c b/arch/arm/boards/phytec-phyflex-am335x/board.c deleted file mode 100644 index e635532d29..0000000000 --- a/arch/arm/boards/phytec-phyflex-am335x/board.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * pfla03 - phyFLEX-AM335x Board Initalization Code - * - * Copyright (C) 2014 Stefan Müller-Klieser, Phytec Messtechnik GmbH - * - * Based on arch/arm/boards/omap/board-beagle.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <bootsource.h> -#include <common.h> -#include <nand.h> -#include <init.h> -#include <io.h> -#include <linux/sizes.h> -#include <envfs.h> -#include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <linux/phy.h> -#include <linux/micrel_phy.h> -#include <mach/am33xx-generic.h> -#include <mach/am33xx-silicon.h> -#include <mach/bbu.h> - -static int pfla03_coredevice_init(void) -{ - if (!of_machine_is_compatible("phytec,phyflex-am335x-som")) - return 0; - - am33xx_register_ethaddr(0, 0); - am33xx_register_ethaddr(1, 1); - - return 0; -} -coredevice_initcall(pfla03_coredevice_init); - -static struct omap_barebox_part pfla03_barebox_part = { - .nand_offset = SZ_512K, - .nand_size = SZ_512K, - .nor_offset = SZ_128K, - .nor_size = SZ_512K, -}; - -static char *xloadslots[] = { - "/dev/nand0.xload.bb", - "/dev/nand0.xload_backup1.bb", - "/dev/nand0.xload_backup2.bb", - "/dev/nand0.xload_backup3.bb" -}; - -static int pfla03_devices_init(void) -{ - if (!of_machine_is_compatible("phytec,phyflex-am335x-som")) - return 0; - - switch (bootsource_get()) { - case BOOTSOURCE_SPI: - of_device_enable_path("/chosen/environment-spi"); - break; - case BOOTSOURCE_MMC: - omap_set_bootmmc_devname("mmc0"); - break; - default: - of_device_enable_path("/chosen/environment-nand"); - break; - } - - omap_set_barebox_part(&pfla03_barebox_part); - armlinux_set_architecture(MACH_TYPE_PFLA03); - defaultenv_append_directory(defaultenv_phyflex_am335x); - - am33xx_select_rmii2_crs_dv(); - - am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload"); - am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox"); - am33xx_bbu_nand_xloadslots_register_handler("MLO.nand", - xloadslots, ARRAY_SIZE(xloadslots)); - am33xx_bbu_nand_register_handler("nand", "/dev/nand0.barebox.bb"); - - return 0; -} -device_initcall(pfla03_devices_init); diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/mmc b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/mmc deleted file mode 100644 index 6a6076101e..0000000000 --- a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/mmc +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -global.bootm.image=/boot/linuximage -#global.bootm.oftree=/boot/oftree - -bootargs-ip - -global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rw rootwait" diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/init/bootsource b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/init/bootsource deleted file mode 100644 index 3f2ff4bcc8..0000000000 --- a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/init/bootsource +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -if [ -n "$nv.boot.default" ]; then - exit -fi - -if [ $bootsource = mmc ]; then - global.boot.default="mmc nand spi net" -elif [ $bootsource = nand ]; then - global.boot.default="nand spi mmc net" -elif [ $bootsource = spi ]; then - global.boot.default="spi nand mmc net" -elif [ $bootsource = net ]; then - global.boot.default="net nand spi mmc" -fi diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/nv/hostname b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/nv/hostname deleted file mode 100644 index 09c5821d49..0000000000 --- a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/nv/hostname +++ /dev/null @@ -1 +0,0 @@ -pfla03 diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/nv/linux.bootargs.base b/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/nv/linux.bootargs.base deleted file mode 100644 index d7b01a1683..0000000000 --- a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttyO0,115200 diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/nv/linux.bootargs.base b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/nv/linux.bootargs.base deleted file mode 100644 index c61c6032cd..0000000000 --- a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -console=ttymxc3,115200 diff --git a/arch/arm/boards/freescale-mx6-arm2/Makefile b/arch/arm/boards/phytec-som-am335x/Makefile index 01c7a259e9..78397bd59f 100644 --- a/arch/arm/boards/freescale-mx6-arm2/Makefile +++ b/arch/arm/boards/phytec-som-am335x/Makefile @@ -1,2 +1,3 @@ -obj-y += board.o lwl-y += lowlevel.o +obj-y += board.o +bbenv-y += defaultenv-physom-am335x diff --git a/arch/arm/boards/phytec-phycore-am335x/board.c b/arch/arm/boards/phytec-som-am335x/board.c index 61a11cfaa3..74e39d70fc 100644 --- a/arch/arm/boards/phytec-phycore-am335x/board.c +++ b/arch/arm/boards/phytec-som-am335x/board.c @@ -1,9 +1,10 @@ /* - * pcm051 - phyCORE-AM335x Board Initalization Code + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH * - * Copyright (C) 2012 Teresa Gámez, Phytec Messtechnik GmbH - * - * Based on arch/arm/boards/omap/board-beagle.c + * Device initialization for the following modules and board variants: + * - phyCORE: PCM-953, phyBOARD-MAIA, phyBOARD-WEGA + * - phyFLEX: PBA-B-01 + * - phyCARD: PCA-A-XS1 * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -27,22 +28,23 @@ #include <asm/armlinux.h> #include <generated/mach-types.h> #include <linux/phy.h> +#include <linux/micrel_phy.h> #include <mach/am33xx-generic.h> #include <mach/am33xx-silicon.h> #include <mach/bbu.h> - -static int pcm051_coredevice_init(void) +static int physom_coredevice_init(void) { - if (!of_machine_is_compatible("phytec,phycore-am335x-som")) + if (!of_machine_is_compatible("phytec,am335x-som")) return 0; am33xx_register_ethaddr(0, 0); + return 0; } -coredevice_initcall(pcm051_coredevice_init); +coredevice_initcall(physom_coredevice_init); -static struct omap_barebox_part pcm051_barebox_part = { +static struct omap_barebox_part physom_barebox_part = { .nand_offset = SZ_512K, .nand_size = SZ_512K, .nor_offset = SZ_128K, @@ -56,9 +58,9 @@ static char *xloadslots[] = { "/dev/nand0.xload_backup3.bb" }; -static int pcm051_devices_init(void) +static int physom_devices_init(void) { - if (!of_machine_is_compatible("phytec,phycore-am335x-som")) + if (!of_machine_is_compatible("phytec,am335x-som")) return 0; switch (bootsource_get()) { @@ -73,10 +75,27 @@ static int pcm051_devices_init(void) break; } - omap_set_barebox_part(&pcm051_barebox_part); - armlinux_set_architecture(MACH_TYPE_PCM051); - defaultenv_append_directory(defaultenv_phycore_am335x); + omap_set_barebox_part(&physom_barebox_part); + defaultenv_append_directory(defaultenv_physom_am335x); + + /* Special module set up */ + if (of_machine_is_compatible("phytec,phycore-am335x-som")) { + armlinux_set_architecture(MACH_TYPE_PCM051); + barebox_set_hostname("pcm051"); + } + + if (of_machine_is_compatible("phytec,phyflex-am335x-som")) { + armlinux_set_architecture(MACH_TYPE_PFLA03); + am33xx_select_rmii2_crs_dv(); + barebox_set_hostname("pfla03"); + } + + if (of_machine_is_compatible("phytec,phycard-am335x-som")) { + armlinux_set_architecture(MACH_TYPE_PCAAXS1); + barebox_set_hostname("pcaaxs1"); + } + /* Register update handler */ am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload"); am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox"); am33xx_bbu_nand_xloadslots_register_handler("MLO.nand", @@ -88,4 +107,4 @@ static int pcm051_devices_init(void) return 0; } -device_initcall(pcm051_devices_init); +device_initcall(physom_devices_init); diff --git a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc new file mode 100644 index 0000000000..670afc78e4 --- /dev/null +++ b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc @@ -0,0 +1,8 @@ +#!/bin/sh + +global.bootm.image=/boot/linuximage +global.bootm.oftree=/boot/oftree + +bootargs-ip + +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rw rootwait" diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/nand b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/nand index 1dfbef9d8b..c6e49be3c5 100644 --- a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/nand +++ b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/nand @@ -1,7 +1,7 @@ #!/bin/sh global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" +global.bootm.oftree="/dev/nand0.oftree.bb" bootargs-ip diff --git a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/spi b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/spi index 2f858bd0d9..43a89fe126 100644 --- a/arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/spi +++ b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/spi @@ -1,8 +1,9 @@ #!/bin/sh global.bootm.image="/dev/m25p0.kernel" +global.bootm.oftree="/dev/m25p0.oftree" bootargs-ip # Use rootfs from NAND -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs" +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rw rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/init/bootsource b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/init/bootsource index 3f2ff4bcc8..3f2ff4bcc8 100644 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/init/bootsource +++ b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/init/bootsource diff --git a/arch/arm/boards/phytec-phyflex-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c index a240401555..948bfa5147 100644 --- a/arch/arm/boards/phytec-phyflex-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c @@ -1,9 +1,5 @@ /* - * pfla03 - phyFLEX-AM335x lowlevel code - * - * Copyright (C) 2014 Stefan Müller-Klieser, Phytec Messtechnik GmbH - * - * Based on arch/arm/boards/omap/board-beagle.c + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -34,10 +30,12 @@ #include <mach/wdt.h> #include <debug_ll.h> +#include "ram-timings.h" + #define CLK_M_OSC_MHZ 25 #define DDR_IOCTRL 0x18B -static const struct am33xx_cmd_control pfla03_cmd = { +static const struct am33xx_cmd_control physom_cmd = { .slave_ratio0 = 0x80, .dll_lock_diff0 = 0x0, .invert_clkout0 = 0x0, @@ -49,61 +47,6 @@ static const struct am33xx_cmd_control pfla03_cmd = { .invert_clkout2 = 0x0, }; -struct pfla03_sdram_timings { - struct am33xx_emif_regs regs; - struct am33xx_ddr_data data; -}; - -enum { - MT41K128M16JT_256MB, - MT41K256M16HA_512MB, -}; - -struct pfla03_sdram_timings pfla03_timings[] = { - /* 256 MB */ - [MT41K128M16JT_256MB] = { - .regs = { - .emif_read_latency = 0x7, - .emif_tim1 = 0x0AAAD4DB, - .emif_tim2 = 0x26437FDA, - .emif_tim3 = 0x501F83FF, - .sdram_config = 0x61C052B2, - .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x00000C30, - }, - .data = { - .rd_slave_ratio0 = 0x34, - .wr_dqs_slave_ratio0 = 0x47, - .fifo_we_slave_ratio0 = 0x9a, - .wr_slave_ratio0 = 0x7e, - .use_rank0_delay = 0x0, - .dll_lock_diff0 = 0x0, - }, - }, - /* 512 MB */ - [MT41K256M16HA_512MB] = { - .regs = { - .emif_read_latency = 0x7, - .emif_tim1 = 0x0AAAE4DB, - .emif_tim2 = 0x266B7FDA, - .emif_tim3 = 0x501F867F, - .sdram_config = 0x61C05332, - .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x00000C30, - }, - .data = { - .rd_slave_ratio0 = 0x36, - .wr_dqs_slave_ratio0 = 0x47, - .fifo_we_slave_ratio0 = 0x95, - .wr_slave_ratio0 = 0x7f, - .use_rank0_delay = 0x0, - .dll_lock_diff0 = 0x0, - }, - }, -}; - -extern char __dtb_am335x_phytec_phyflex_start[]; - /** * @brief The basic entry point for board initialization. * @@ -113,10 +56,9 @@ extern char __dtb_am335x_phytec_phyflex_start[]; * * @return void */ -static noinline void pfla03_board_init(int sdram) +static noinline void physom_board_init(int sdram, void *fdt) { - void *fdt; - struct pfla03_sdram_timings *timing = &pfla03_timings[sdram]; + struct am335x_sdram_timings *timing = &physom_timings[sdram]; /* * WDT1 is already running when the bootloader gets control @@ -125,12 +67,13 @@ static noinline void pfla03_board_init(int sdram) writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); + writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); am33xx_pll_init(MPUPLL_M_600, CLK_M_OSC_MHZ, DDRPLL_M_400); - am335x_sdram_init(DDR_IOCTRL, &pfla03_cmd, + am335x_sdram_init(DDR_IOCTRL, &physom_cmd, &timing->regs, &timing->data); @@ -139,12 +82,10 @@ static noinline void pfla03_board_init(int sdram) omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); putc_ll('>'); - fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset(); - am335x_barebox_entry(fdt); } -static noinline void pfla03_board_entry(unsigned long bootinfo, int sdram) +static noinline void physom_board_entry(unsigned long bootinfo, int sdram, void *fdt) { am33xx_save_bootinfo((void *)bootinfo); @@ -157,24 +98,40 @@ static noinline void pfla03_board_entry(unsigned long bootinfo, int sdram) relocate_to_current_adr(); setup_c(); - pfla03_board_init(sdram); + physom_board_init(sdram, fdt); } -ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sram_256mb, bootinfo, r1, r2) -{ - pfla03_board_entry(bootinfo, MT41K128M16JT_256MB); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sram_512mb, bootinfo, r1, r2) -{ - pfla03_board_entry(bootinfo, MT41K256M16HA_512MB); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sdram, r0, r1, r2) -{ - void *fdt; - - fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset(); - - am335x_barebox_entry(fdt); -} +#define PHYTEC_ENTRY_MLO(name, fdt_name, sdram) \ + ENTRY_FUNCTION(name, bootinfo, r1, r2) \ + { \ + extern char __dtb_##fdt_name##_start[]; \ + void *fdt =__dtb_##fdt_name##_start - \ + get_runtime_offset(); \ + physom_board_entry(bootinfo, sdram, fdt); \ + } + +#define PHYTEC_ENTRY(name, fdt_name) \ + ENTRY_FUNCTION(name, r0, r1, r2) \ + { \ + extern char __dtb_##fdt_name##_start[]; \ + void *fdt =__dtb_##fdt_name##_start - \ + get_runtime_offset(); \ + am335x_barebox_entry(fdt); \ + } + +/* phycore-som */ +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_128mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J64M1615IT_128MB); +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J128M16125IT_256MB); +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J256M16HA15EIT_512MB); +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_2x512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J512M8125IT_2x512MB); +PHYTEC_ENTRY(start_am33xx_phytec_phycore_sdram, am335x_phytec_phycore_som); +PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_spi_sdram, am335x_phytec_phycore_som_no_spi); + +/* phyflex-som */ +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_256mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K128M16JT_256MB); +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_512mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K256M16HA_512MB); +PHYTEC_ENTRY(start_am33xx_phytec_phyflex_sdram, am335x_phytec_phyflex_som); + +/* phycard-som */ +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycard_sram_256mb, am335x_phytec_phycard_som_mlo, PHYCARD_NT5CB128M16BP_256MB); +PHYTEC_ENTRY(start_am33xx_phytec_phycard_sdram, am335x_phytec_phycard_som); diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h new file mode 100644 index 0000000000..3dcee207ee --- /dev/null +++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __RAM_TIMINGS_H +#define __RAM_TIMINGS_H + +struct am335x_sdram_timings { + struct am33xx_emif_regs regs; + struct am33xx_ddr_data data; +}; + +enum { + PHYFLEX_MT41K128M16JT_256MB, + PHYFLEX_MT41K256M16HA_512MB, + + PHYCORE_MT41J128M16125IT_256MB, + PHYCORE_MT41J64M1615IT_128MB, + PHYCORE_MT41J256M16HA15EIT_512MB, + PHYCORE_MT41J512M8125IT_2x512MB, + + PHYCARD_NT5CB128M16BP_256MB, +}; + +struct am335x_sdram_timings physom_timings[] = { + /* 256 MB */ + [PHYFLEX_MT41K128M16JT_256MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAD4DB, + .emif_tim2 = 0x26437FDA, + .emif_tim3 = 0x501F83FF, + .sdram_config = 0x61C052B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x34, + .wr_dqs_slave_ratio0 = 0x47, + .fifo_we_slave_ratio0 = 0x9a, + .wr_slave_ratio0 = 0x7e, + .use_rank0_delay = 0x0, + .dll_lock_diff0 = 0x0, + }, + }, + + /* 512 MB */ + [PHYFLEX_MT41K256M16HA_512MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x266B7FDA, + .emif_tim3 = 0x501F867F, + .sdram_config = 0x61C05332, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x36, + .wr_dqs_slave_ratio0 = 0x47, + .fifo_we_slave_ratio0 = 0x95, + .wr_slave_ratio0 = 0x7f, + .use_rank0_delay = 0x0, + .dll_lock_diff0 = 0x0, + }, + }, + + /* 256MB */ + [PHYCORE_MT41J128M16125IT_256MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAD4DB, + .emif_tim2 = 0x26437FDA, + .emif_tim3 = 0x501F83FF, + .sdram_config = 0x61C052B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x3B, + .wr_dqs_slave_ratio0 = 0x33, + .fifo_we_slave_ratio0 = 0x9c, + .wr_slave_ratio0 = 0x6f, + }, + }, + + /* 128MB */ + [PHYCORE_MT41J64M1615IT_128MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x262F7FDA, + .emif_tim3 = 0x501F82BF, + .sdram_config = 0x61C05232, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x38, + .wr_dqs_slave_ratio0 = 0x34, + .fifo_we_slave_ratio0 = 0xA2, + .wr_slave_ratio0 = 0x72, + }, + }, + + /* 512MB */ + [PHYCORE_MT41J256M16HA15EIT_512MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x266B7FDA, + .emif_tim3 = 0x501F867F, + .sdram_config = 0x61C05332, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30 + }, + .data = { + .rd_slave_ratio0 = 0x35, + .wr_dqs_slave_ratio0 = 0x43, + .fifo_we_slave_ratio0 = 0x97, + .wr_slave_ratio0 = 0x7b, + }, + }, + + /* 1024MB */ + [PHYCORE_MT41J512M8125IT_2x512MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x266B7FDA, + .emif_tim3 = 0x501F867F, + .sdram_config = 0x61C053B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30 + }, + .data = { + .rd_slave_ratio0 = 0x32, + .wr_dqs_slave_ratio0 = 0x48, + .fifo_we_slave_ratio0 = 0x99, + .wr_slave_ratio0 = 0x80, + }, + }, + + /* 256MB */ + [PHYCARD_NT5CB128M16BP_256MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAD4DB, + .emif_tim2 = 0x26437FDA, + .emif_tim3 = 0x501F83FF, + .sdram_config = 0x61C052B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x35, + .wr_dqs_slave_ratio0 = 0x3A, + .fifo_we_slave_ratio0 = 0x9b, + .wr_slave_ratio0 = 0x73, + .use_rank0_delay = 0x01, + .dll_lock_diff0 = 0x0, + }, + }, +}; + +#endif diff --git a/arch/arm/boards/radxa-rock/board.c b/arch/arm/boards/radxa-rock/board.c index 3d9b5be344..ec053f9123 100644 --- a/arch/arm/boards/radxa-rock/board.c +++ b/arch/arm/boards/radxa-rock/board.c @@ -16,8 +16,9 @@ #include <io.h> #include <i2c/i2c.h> #include <i2c/i2c-gpio.h> -#include <mach/rockchip-pll.h> +#include <mach/rockchip-regs.h> #include <mfd/act8846.h> +#include <asm/armlinux.h> static struct i2c_board_info radxa_rock_i2c_devices[] = { { @@ -43,20 +44,6 @@ static void radxa_rock_pmic_init(void) act8846_set_bits(pmic, ACT8846_LDO9_CTRL, BIT(7), BIT(7)); } -static int setup_plls(void) -{ - if (!of_machine_is_compatible("radxa,rock")) - return 0; - - /* Codec PLL frequency: 594 MHz */ - rk3188_pll_set_parameters(RK3188_CPLL, 2, 198, 4); - /* General PLL frequency: 300 MHz */ - rk3188_pll_set_parameters(RK3188_GPLL, 1, 50, 4); - - return 0; -} -coredevice_initcall(setup_plls); - static int devices_init(void) { if (!of_machine_is_compatible("radxa,rock")) @@ -68,20 +55,12 @@ static int devices_init(void) radxa_rock_pmic_init(); - /* Set mac_pll divisor to 6 (50MHz output) */ - writel((5 << 8) | (0x1f << 24), 0x20000098); + armlinux_set_architecture(3066); - return 0; -} -device_initcall(devices_init); - -static int hostname_init(void) -{ - if (!of_machine_is_compatible("radxa,rock")) - return 0; - - barebox_set_hostname("radxa-rock"); + /* Map SRAM to address 0, kernel relies on this */ + writel((RK_SOC_CON0_REMAP << 16) | RK_SOC_CON0_REMAP, + RK_GRF_BASE + RK_GRF_SOC_CON0); return 0; } -postcore_initcall(hostname_init); +device_initcall(devices_init); diff --git a/arch/arm/boards/radxa-rock/env/boot/mshc1 b/arch/arm/boards/radxa-rock/env/boot/mshc1 new file mode 100644 index 0000000000..964b6cc3eb --- /dev/null +++ b/arch/arm/boards/radxa-rock/env/boot/mshc1 @@ -0,0 +1,9 @@ +#!/bin/sh + +mount /dev/mshc1.0 + +oftree -f +oftree -l /mnt/mshc1.0/rk3188-radxarock.dtb + +global.bootm.image=/mnt/mshc1.0/zImage +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait" diff --git a/arch/arm/boards/radxa-rock/env/boot/mshc1-old b/arch/arm/boards/radxa-rock/env/boot/mshc1-old new file mode 100644 index 0000000000..1e1b57751d --- /dev/null +++ b/arch/arm/boards/radxa-rock/env/boot/mshc1-old @@ -0,0 +1,8 @@ +#!/bin/sh + +mount /dev/mshc1.0 + +oftree -f + +global.bootm.image=/mnt/mshc1.0/zImage-old +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait" diff --git a/arch/arm/boards/radxa-rock/env/init/bootsource b/arch/arm/boards/radxa-rock/env/init/bootsource new file mode 100644 index 0000000000..4e8299b8dd --- /dev/null +++ b/arch/arm/boards/radxa-rock/env/init/bootsource @@ -0,0 +1,7 @@ +#!/bin/sh + +if [ -n "$nv.boot.default" ]; then + exit +fi + +global.boot.default=mshc1 diff --git a/arch/arm/boards/radxa-rock/env/nv/hostname b/arch/arm/boards/radxa-rock/env/nv/hostname new file mode 100644 index 0000000000..16523aca12 --- /dev/null +++ b/arch/arm/boards/radxa-rock/env/nv/hostname @@ -0,0 +1 @@ +radxa-rock diff --git a/arch/arm/boards/radxa-rock/env/nv/linux.bootargs.base b/arch/arm/boards/radxa-rock/env/nv/linux.bootargs.console index 37a03fd430..37a03fd430 100644 --- a/arch/arm/boards/radxa-rock/env/nv/linux.bootargs.base +++ b/arch/arm/boards/radxa-rock/env/nv/linux.bootargs.console diff --git a/arch/arm/boards/sama5d4ek/env/boot/nand b/arch/arm/boards/sama5d4ek/env/boot/nand new file mode 100644 index 0000000000..29489bf613 --- /dev/null +++ b/arch/arm/boards/sama5d4ek/env/boot/nand @@ -0,0 +1,6 @@ +#!/bin/sh + +global.bootm.image="/dev/nand0.kernel.bb" +global.bootm.oftree="/dev/nand0.oftree.bb" + +global.linux.bootargs.dyn.root="root=ubi0:rootfs ubi.mtd=rootfs rootfstype=ubifs noinitrd" diff --git a/arch/arm/boards/sama5d4ek/env/config b/arch/arm/boards/sama5d4ek/env/config deleted file mode 100644 index 1007345b9b..0000000000 --- a/arch/arm/boards/sama5d4ek/env/config +++ /dev/null @@ -1,42 +0,0 @@ -#!/bin/sh - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=nfs -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net -# can be either 'nfs', 'tftp', 'nand' or empty -oftree_loc=nfs - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root.$rootfs_type -ubiroot=rootfs - -# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo -kernelimage=zImage -#kernelimage=uImage -#kernelimage=Image -#kernelimage=Image.lzo - -nand_device=atmel_nand -nand_parts="256k(at91bootstrap),512k(barebox)ro,256k(bareboxenv),256k(bareboxenv2),256k(spare),512k(oftree),6M(kernel),-(rootfs)" -rootfs_mtdblock_nand=7 - -m25p80_parts="64k(bootstrap),384k(barebox),256k(bareboxenv),256k(bareboxenv2),128k(oftree),-(updater)" - -autoboot_timeout=3 - -bootargs="console=ttyS0,115200" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# " diff --git a/arch/arm/boards/sama5d4ek/env/init/mtdparts-nand b/arch/arm/boards/sama5d4ek/env/init/mtdparts-nand new file mode 100644 index 0000000000..c947910643 --- /dev/null +++ b/arch/arm/boards/sama5d4ek/env/init/mtdparts-nand @@ -0,0 +1,6 @@ +#!/bin/sh + +mtdparts="256k(at91bootstrap),512k(barebox)ro,256k(bareboxenv),256k(bareboxenv2),256k(spare),512k(oftree),6M(kernel),-(rootfs)" +kernelname="atmel_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/sama5d4ek/env/init/mtdparts-nor b/arch/arm/boards/sama5d4ek/env/init/mtdparts-nor new file mode 100644 index 0000000000..01fa752c3c --- /dev/null +++ b/arch/arm/boards/sama5d4ek/env/init/mtdparts-nor @@ -0,0 +1,6 @@ +#!/bin/sh + +mtdparts="64k(bootstrap),64k(bareboxenv),512k(barebox),384k(oftree),-(kernel)" +kernelname="m25p800" + +mtdparts-add -d m25p0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/sama5d4ek/env/bin/init_board b/arch/arm/boards/sama5d4ek/env/init/splash index f3d417e356..190ef3149e 100644 --- a/arch/arm/boards/sama5d4ek/env/bin/init_board +++ b/arch/arm/boards/sama5d4ek/env/init/splash @@ -1,10 +1,5 @@ #!/bin/sh -PATH=/env/bin -export PATH - -. /env/config - splash=/env/splash.png if [ -f ${splash} -a -e /dev/fb0 ]; then diff --git a/arch/arm/boards/sama5d4ek/env/nv/boot.default b/arch/arm/boards/sama5d4ek/env/nv/boot.default new file mode 100644 index 0000000000..d287b22cbb --- /dev/null +++ b/arch/arm/boards/sama5d4ek/env/nv/boot.default @@ -0,0 +1 @@ +nand net diff --git a/arch/arm/boards/sama5d4ek/env/nv/hostname b/arch/arm/boards/sama5d4ek/env/nv/hostname new file mode 100644 index 0000000000..b74056d082 --- /dev/null +++ b/arch/arm/boards/sama5d4ek/env/nv/hostname @@ -0,0 +1 @@ +sama5d4ek diff --git a/arch/arm/boards/sama5d4ek/env/nv/linux.bootargs.console b/arch/arm/boards/sama5d4ek/env/nv/linux.bootargs.console new file mode 100644 index 0000000000..476b1fbe49 --- /dev/null +++ b/arch/arm/boards/sama5d4ek/env/nv/linux.bootargs.console @@ -0,0 +1 @@ +console=ttyS0,115200 diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S index 717bb90e40..73afc09b70 100644 --- a/arch/arm/boards/scb9328/lowlevel_init.S +++ b/arch/arm/boards/scb9328/lowlevel_init.S @@ -100,7 +100,7 @@ barebox_arm_reset_vector: cmp pc, #0x09000000 bhi 1f - b imx1_barebox_entry + b 2f 1: @@ -129,5 +129,7 @@ barebox_arm_reset_vector: writel(0x0, 0x08223000) /* Set to Normal Mode CAS 2 */ writel(0x810a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) +2: + ldr sp, =0x08100000 - 4; b imx1_barebox_entry diff --git a/arch/arm/boards/solidrun-microsom/board.c b/arch/arm/boards/solidrun-microsom/board.c index 783ec53c1d..c231c17103 100644 --- a/arch/arm/boards/solidrun-microsom/board.c +++ b/arch/arm/boards/solidrun-microsom/board.c @@ -63,7 +63,7 @@ static int ar8035_phy_fixup(struct phy_device *dev) static int hummingboard_device_init(void) { - if (!of_machine_is_compatible("solidrun,hummingboard")) + if (!of_machine_is_compatible("solidrun,hummingboard/dl")) return 0; phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup); @@ -80,7 +80,7 @@ device_initcall(hummingboard_device_init); static int hummingboard_late_init(void) { - if (!of_machine_is_compatible("solidrun,hummingboard")) + if (!of_machine_is_compatible("solidrun,hummingboard/dl")) return 0; imx6_bbu_internal_mmc_register_handler("sdcard", "/dev/mmc1.barebox", diff --git a/arch/arm/boards/telit-evk-pro3/env/nv/linux.bootargs.console b/arch/arm/boards/telit-evk-pro3/env/nv/linux.bootargs.console new file mode 100644 index 0000000000..476b1fbe49 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/env/nv/linux.bootargs.console @@ -0,0 +1 @@ +console=ttyS0,115200 diff --git a/arch/arm/boards/versatile/env/nv/linux.bootargs.base b/arch/arm/boards/versatile/env/nv/linux.bootargs.console index 826debe7c2..826debe7c2 100644 --- a/arch/arm/boards/versatile/env/nv/linux.bootargs.base +++ b/arch/arm/boards/versatile/env/nv/linux.bootargs.console diff --git a/arch/arm/configs/am335x_defconfig b/arch/arm/configs/am335x_defconfig index e9bc1ba309..0db2075d20 100644 --- a/arch/arm/configs/am335x_defconfig +++ b/arch/arm/configs/am335x_defconfig @@ -4,8 +4,7 @@ CONFIG_BAREBOX_UPDATE_AM33XX_NAND=y CONFIG_OMAP_MULTI_BOARDS=y CONFIG_MACH_AFI_GF=y CONFIG_MACH_BEAGLEBONE=y -CONFIG_MACH_PCM051=y -CONFIG_MACH_PFLA03=y +CONFIG_MACH_PHYTEC_SOM_AM335X=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_BOARD_APPEND_ATAG=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y @@ -25,6 +24,7 @@ CONFIG_MENU=y CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_RESET_SOURCE=y CONFIG_DEBUG_INFO=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y @@ -125,6 +125,7 @@ CONFIG_EEPROM_AT24=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_PINCTRL_SINGLE=y CONFIG_BUS_OMAP_GPMC=y +CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y CONFIG_FS_NFS=y CONFIG_FS_FAT=y diff --git a/arch/arm/configs/am335x_mlo_defconfig b/arch/arm/configs/am335x_mlo_defconfig index 9734da60c7..1dd7567d0d 100644 --- a/arch/arm/configs/am335x_mlo_defconfig +++ b/arch/arm/configs/am335x_mlo_defconfig @@ -4,8 +4,7 @@ CONFIG_OMAP_SERIALBOOT=y CONFIG_OMAP_MULTI_BOARDS=y CONFIG_MACH_AFI_GF=y CONFIG_MACH_BEAGLEBONE=y -CONFIG_MACH_PCM051=y -CONFIG_MACH_PFLA03=y +CONFIG_MACH_PHYTEC_SOM_AM335X=y CONFIG_THUMB2_BAREBOX=y # CONFIG_MEMINFO is not set CONFIG_MMU=y diff --git a/arch/arm/configs/freescale-mx6-arm2_defconfig b/arch/arm/configs/freescale-mx6-arm2_defconfig deleted file mode 100644 index f4119f0986..0000000000 --- a/arch/arm/configs/freescale-mx6-arm2_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_MACH_MX6Q_ARM2=y -CONFIG_IMX_IIM=y -CONFIG_IMX_IIM_FUSE_BLOW=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x8000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx6-arm2/env/" -CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_NET=y -CONFIG_CMD_DHCP=y -CONFIG_NET_NFS=y -CONFIG_CMD_PING=y -CONFIG_NET_NETCONSOLE=y -CONFIG_DRIVER_NET_FEC_IMX=y -CONFIG_NET_USB=y -CONFIG_NET_USB_ASIX=y -CONFIG_NET_USB_SMSC95XX=y -# CONFIG_SPI is not set -CONFIG_USB_HOST=y -CONFIG_USB_EHCI=y -CONFIG_USB_STORAGE=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_IMX_ESDHC=y -CONFIG_FS_TFTP=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 755217f062..c4c28a01d2 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -179,3 +179,4 @@ CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y CONFIG_FS_UBIFS=y CONFIG_FS_UBIFS_COMPRESSION_LZO=y +CONFIG_PNG=y diff --git a/arch/arm/configs/phytec-phycore-pxa270_defconfig b/arch/arm/configs/phytec-phycore-pxa270_defconfig index 57eaff09ec..304624bc29 100644 --- a/arch/arm/configs/phytec-phycore-pxa270_defconfig +++ b/arch/arm/configs/phytec-phycore-pxa270_defconfig @@ -8,50 +8,48 @@ CONFIG_MMU=y CONFIG_MALLOC_SIZE=0x1000000 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_PARTITION=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-pxa270/env" CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_AUTOMOUNT=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y +CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y -CONFIG_CMD_FLASH=y +CONFIG_CMD_MEMINFO=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set # CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_GPIO=y +CONFIG_CMD_SAVEENV=y CONFIG_CMD_UNCOMPRESS=y -CONFIG_NET=y +CONFIG_CMD_SLEEP=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y CONFIG_DRIVER_SERIAL_PXA=y CONFIG_DRIVER_NET_SMC91111=y # CONFIG_SPI is not set @@ -59,4 +57,5 @@ CONFIG_MTD=y CONFIG_DRIVER_CFI=y CONFIG_VIDEO=y CONFIG_DRIVER_VIDEO_PXA=y +CONFIG_FS_TFTP=y CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/sama5d4ek_defconfig b/arch/arm/configs/sama5d4ek_defconfig index bbf254abf0..f050fe4b97 100644 --- a/arch/arm/configs/sama5d4ek_defconfig +++ b/arch/arm/configs/sama5d4ek_defconfig @@ -9,13 +9,12 @@ CONFIG_MALLOC_SIZE=0xA00000 CONFIG_EXPERIMENTAL=y CONFIG_MALLOC_TLSF=y CONFIG_PROMPT="A5D4EK:" -CONFIG_GLOB=y CONFIG_PROMPT_HUSH_PS2="y" CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_CONSOLE_ACTIVATE_ALL=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/sama5d4ek/env" CONFIG_DEBUG_INFO=y # CONFIG_CMD_ARM_CPUINFO is not set @@ -35,6 +34,8 @@ CONFIG_CMD_PARTITION=y CONFIG_CMD_EXPORT=y CONFIG_CMD_LOADENV=y CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y CONFIG_CMD_SAVEENV=y CONFIG_CMD_FILETYPE=y CONFIG_CMD_SLEEP=y diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c index 34d30902bd..7b161d59d6 100644 --- a/arch/arm/cpu/cache.c +++ b/arch/arm/cpu/cache.c @@ -4,8 +4,6 @@ #include <asm/cache.h> #include <asm/system_info.h> -int arm_architecture; - struct cache_fns { void (*dma_clean_range)(unsigned long start, unsigned long end); void (*dma_flush_range)(unsigned long start, unsigned long end); diff --git a/arch/arm/cpu/exceptions.S b/arch/arm/cpu/exceptions.S index 167c8d1fe2..f17f1e11e4 100644 --- a/arch/arm/cpu/exceptions.S +++ b/arch/arm/cpu/exceptions.S @@ -88,6 +88,21 @@ movs pc, lr .endm + .macro try_data_abort + ldr r13, =arm_ignore_data_abort @ check try mode + ldr r13, [r13] + cmp r13, #0 + beq do_abort_\@ + ldr r13, =arm_data_abort_occurred + str r13, [r13] + mrs r13, spsr @ read saved CPSR + tst r13, #1<<5 @ check Thumb mode + subeq lr, #4 @ next ARM instr + subne lr, #6 @ next Thumb instr + movs pc, lr +do_abort_\@: + .endm + .macro get_irq_stack @ setup IRQ stack ldr sp, IRQ_STACK_START .endm @@ -122,6 +137,7 @@ prefetch_abort: .align 5 data_abort: + try_data_abort get_bad_stack bad_save_user_regs bl do_data_abort @@ -202,5 +218,11 @@ _fiq: .word fiq .section .data .align 4 +.global arm_ignore_data_abort +arm_ignore_data_abort: +.word arm_ignore_data_abort /* When != 0 data aborts are ignored */ +.global arm_data_abort_occurred +arm_data_abort_occurred: +.word arm_data_abort_occurred /* set != 0 by the data abort handler */ abort_stack: .space 8 diff --git a/arch/arm/cpu/interrupts.c b/arch/arm/cpu/interrupts.c index 6e60adc43a..c437af7188 100644 --- a/arch/arm/cpu/interrupts.c +++ b/arch/arm/cpu/interrupts.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <abort.h> #include <asm/ptrace.h> #include <asm/unwind.h> @@ -161,3 +162,19 @@ void do_irq (struct pt_regs *pt_regs) printf ("interrupt request\n"); do_exception(pt_regs); } + +extern volatile int arm_ignore_data_abort; +extern volatile int arm_data_abort_occurred; + +void data_abort_mask(void) +{ + arm_data_abort_occurred = 0; + arm_ignore_data_abort = 1; +} + +int data_abort_unmask(void) +{ + arm_ignore_data_abort = 0; + + return arm_data_abort_occurred != 0; +} diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index ba48010f0d..37bfa058a5 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -65,8 +65,6 @@ static inline void tlb_invalidate(void) ); } -extern int arm_architecture; - #define PTE_FLAGS_CACHED_V7 (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE) #define PTE_FLAGS_UNCACHED_V7 (0) #define PTE_FLAGS_CACHED_V4 (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7b3db8ce48..2bb9c1c04b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -29,8 +29,9 @@ pbl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o -pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore-som.dtb.o am335x-phytec-phycore-som-no-spi.dtb.o am335x-phytec-phycore-som-mlo.dtb.o -pbl-dtb-$(CONFIG_MACH_PFLA03) += am335x-phytec-phyflex.dtb.o +pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o \ + am335x-phytec-phycore-som.dtb.o am335x-phytec-phycore-som-no-spi.dtb.o am335x-phytec-phycore-som-mlo.dtb.o \ + am335x-phytec-phycard-som.dtb.o am335x-phytec-phycard-som-mlo.dtb.o pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o imx6q-phytec-phyboard-alcor.dtb.o imx6dl-phytec-phyboard-subra.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o @@ -39,6 +40,7 @@ pbl-dtb-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o pbl-dtb-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o +pbl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o diff --git a/arch/arm/dts/am335x-phytec-phycard-som-mlo.dts b/arch/arm/dts/am335x-phytec-phycard-som-mlo.dts new file mode 100644 index 0000000000..17d9152977 --- /dev/null +++ b/arch/arm/dts/am335x-phytec-phycard-som-mlo.dts @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2015 Wadim Egorov <w.egorovphytec.de> PHYTEC Messtechnik GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-phytec-phycard-som.dtsi" + +/ { + model = "Phytec phyCARD AM335x"; + compatible = "phytec,phycard-am335x-som", "phytec,am335x-som", "ti,am33xx"; +}; + +/* Keep all bootsources disabled, we enable and register them + * later while booting. + */ + +&mmc1 { + status = "disabled"; +}; + +&gpmc { + status = "disabled"; +}; diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dts b/arch/arm/dts/am335x-phytec-phycard-som.dts new file mode 100644 index 0000000000..6b43180231 --- /dev/null +++ b/arch/arm/dts/am335x-phytec-phycard-som.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2015 Wadim Egorov <w.egorovphytec.de> PHYTEC Messtechnik GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-phytec-phycard-som.dtsi" + +/ { + model = "Phytec phyCARD AM335x"; + compatible = "phytec,phycard-am335x-som", "phytec,am335x-som", "ti,am33xx"; +}; + +&eeprom { + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dtsi b/arch/arm/dts/am335x-phytec-phycard-som.dtsi new file mode 100644 index 0000000000..1f1036f432 --- /dev/null +++ b/arch/arm/dts/am335x-phytec-phycard-som.dtsi @@ -0,0 +1,228 @@ +/ { + chosen { + linux,stdout-path = &uart0; + + environment-nand { + compatible = "barebox,environment"; + device-path = &nand, "partname:bareboxenv"; + status = "disabled"; + }; + }; +}; + +&am33xx_pinmux { + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart3_pins: pinmux_uart3 { + pinctrl-single,pins = < + 0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */ + 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ + 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ + 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ + 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ + 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ + 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + >; + }; + + emac_rmii1_pins: pinmux_emac_rmii1_pins { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ + 0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + eeprom: 24c32@52 { + status = "disabled"; + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x54>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; +}; + +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rmii1_pins>; + slaves = <1>; + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + nand: nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; + gpmc,wait-pin = <1>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <50>; + gpmc,cycle2cycle-diffcsen; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + + partition@0 { + label = "xload"; + reg = <0x0 0x20000>; + }; + + partition@1 { + label = "xload_backup1"; + reg = <0x20000 0x20000>; + }; + + partition@2 { + label = "xload_backup2"; + reg = <0x40000 0x20000>; + }; + + partition@3 { + label = "xload_backup3"; + reg = <0x60000 0x20000>; + }; + + partition@4 { + label = "barebox"; + reg = <0x80000 0x80000>; + }; + + partition@5 { + label = "bareboxenv"; + reg = <0x100000 0x40000>; + }; + + partition@6 { + label = "oftree"; + reg = <0x140000 0x40000>; + }; + + partition@7 { + label = "kernel"; + reg = <0x180000 0x800000>; + }; + + partition@8 { + label = "root"; + reg = <0x980000 0x0>; + }; + }; +}; diff --git a/arch/arm/dts/am335x-phytec-phycore-som-mlo.dts b/arch/arm/dts/am335x-phytec-phycore-som-mlo.dts index d8fceff6cb..b08a59e0f5 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som-mlo.dts +++ b/arch/arm/dts/am335x-phytec-phycore-som-mlo.dts @@ -12,7 +12,7 @@ / { model = "Phytec phyCORE AM335x"; - compatible = "phytec,phycore-am335x-som", "ti,am33xx"; + compatible = "phytec,phycore-am335x-som", "phytec,am335x-som", "ti,am33xx"; }; /* Keep all bootsources disabled, we enable and register them diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dts b/arch/arm/dts/am335x-phytec-phycore-som.dts index 93f09e2c14..f13e0d6bdd 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som.dts +++ b/arch/arm/dts/am335x-phytec-phycore-som.dts @@ -12,7 +12,7 @@ / { model = "Phytec phyCORE AM335x"; - compatible = "phytec,phycore-am335x-som", "ti,am33xx"; + compatible = "phytec,phycore-am335x-som", "phytec,am335x-som", "ti,am33xx"; }; &spi0 { diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi index 7d0e3c5466..ed8e257b59 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi @@ -291,17 +291,17 @@ partition@5 { label = "bareboxenv"; - reg = <0x100000 0x20000>; + reg = <0x100000 0x40000>; }; partition@6 { label = "oftree"; - reg = <0x120000 0x20000>; + reg = <0x140000 0x40000>; }; partition@7 { label = "kernel"; - reg = <0x140000 0x800000>; + reg = <0x180000 0x800000>; }; partition@8 { @@ -310,7 +310,7 @@ * Size 0x0 extends partition to * end of nand flash. */ - reg = <0x940000 0x0>; + reg = <0x980000 0x0>; }; }; }; diff --git a/arch/arm/dts/am335x-phytec-phyflex-som-mlo.dts b/arch/arm/dts/am335x-phytec-phyflex-som-mlo.dts new file mode 100644 index 0000000000..5294ff5976 --- /dev/null +++ b/arch/arm/dts/am335x-phytec-phyflex-som-mlo.dts @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2015 Wadim Egorov <w.egorov@phytec.de> PHYTEC Messtechnik GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-phytec-phyflex-som.dtsi" + +/ { + model = "Phytec phyFLEX AM335x"; + compatible = "phytec,phyflex-am335x-som", "phytec,am335x-som", "ti,am33xx"; +}; + +/* Keep all bootsources disabled, we enable and register them + * later while booting. + */ + +&mmc1 { + status = "disabled"; +}; + +&gpmc { + status = "disabled"; +}; diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dts b/arch/arm/dts/am335x-phytec-phyflex-som.dts new file mode 100644 index 0000000000..2be83b6b9d --- /dev/null +++ b/arch/arm/dts/am335x-phytec-phyflex-som.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2015 Wadim Egorov <w.egorov@phytec.de> PHYTEC Messtechnik GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-phytec-phyflex-som.dtsi" + +/ { + model = "Phytec phyFLEX AM335x"; + compatible = "phytec,phyflex-am335x-som", "phytec,am335x-som", "ti,am33xx"; +}; + +&spi0 { + status = "okay"; +}; + +&at24c32 { + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-phytec-phyflex.dts b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi index 5459cd24db..fc9c9bafeb 100644 --- a/arch/arm/dts/am335x-phytec-phyflex.dts +++ b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi @@ -1,11 +1,4 @@ -/dts-v1/; - -#include "am33xx.dtsi" - / { - model = "Phytec phyFLEX AM335x"; - compatible = "phytec,phyflex-am335x-som", "ti,am33xx"; - chosen { linux,stdout-path = &uart0; @@ -36,16 +29,10 @@ regulator-max-microvolt = <3300000>; regulator-boot-on; }; + }; &am33xx_pinmux { - usb_pins: pinmux_usb { - pinctrl-single,pins = < - 0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ - 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ - >; - }; - i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda */ @@ -77,7 +64,7 @@ 0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ - >; + >; }; emac_rgmii1_pins: pinmux_emac_rgmii1_pins { @@ -136,30 +123,6 @@ }; }; -&cppi41dma { - status = "okay"; -}; - - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb { - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins>; - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -187,7 +150,7 @@ &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - status = "okay"; + status = "disabled"; flash: m25p80 { compatible = "m25p80"; spi-max-frequency = <48000000>; @@ -340,22 +303,22 @@ partition@5 { label = "bareboxenv"; - reg = <0x100000 0x20000>; + reg = <0x100000 0x40000>; }; partition@6 { label = "oftree"; - reg = <0x120000 0x20000>; + reg = <0x140000 0x40000>; }; partition@7 { label = "kernel"; - reg = <0x140000 0x800000>; + reg = <0x180000 0x800000>; }; partition@8 { label = "root"; - reg = <0x940000 0x0>; + reg = <0x980000 0x0>; }; }; }; diff --git a/arch/arm/dts/imx6dl-hummingboard.dts b/arch/arm/dts/imx6dl-hummingboard.dts index 4599a54905..24f6bfa817 100644 --- a/arch/arm/dts/imx6dl-hummingboard.dts +++ b/arch/arm/dts/imx6dl-hummingboard.dts @@ -4,11 +4,9 @@ * The code contained herein is licensed under the GNU General Public * License version 2. */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" +#include <arm/imx6dl-hummingboard.dts> +#include "imx6qdl.dtsi" / { chosen { diff --git a/arch/arm/dts/imx6q-embedsky-e9.dts b/arch/arm/dts/imx6q-embedsky-e9.dts index 53665cf9d5..ab70d05ad9 100644 --- a/arch/arm/dts/imx6q-embedsky-e9.dts +++ b/arch/arm/dts/imx6q-embedsky-e9.dts @@ -17,7 +17,7 @@ / { chosen { - linux,stdout-path = &uart4; + linux,stdout-path = &uart1; environment-mmc1 { compatible = "barebox,environment"; diff --git a/arch/arm/dts/imx6q-embedsky-e9.dtsi b/arch/arm/dts/imx6q-embedsky-e9.dtsi index a29de9f3c4..f117cae920 100644 --- a/arch/arm/dts/imx6q-embedsky-e9.dtsi +++ b/arch/arm/dts/imx6q-embedsky-e9.dtsi @@ -372,10 +372,7 @@ &hdmi { status = "okay"; -}; - -&pcie { - status = "okay"; + ddc-i2c-bus = <&i2c2>; }; &can1 { diff --git a/arch/arm/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/dts/imx6qdl-microsom-ar8035.dtsi deleted file mode 100644 index c1be487dfc..0000000000 --- a/arch/arm/dts/imx6qdl-microsom-ar8035.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2013 Russell King - * - * The code contained herein is licensed under the GNU General Public - * License version 2. - * - * This describes the hookup for an AR8035 to the IMX6 on the Cubox-i - * MicroSOM. - * - * FIXME: we need to configure PLL_ENET to produce 25MHz, but there - * doesn't seem to be a way to do that yet from DT. (Writing 0x2000 - * to 0x020c80e0 phys will do this.) - */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; - phy-mode = "rgmii"; - phy-reset-duration = <2>; - phy-reset-gpios = <&gpio4 15 0>; - status = "okay"; -}; - -&iomuxc { - enet { - pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - /* AR8035 reset */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000 - /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 - >; - }; - }; -}; diff --git a/arch/arm/dts/imx6qdl-microsom.dtsi b/arch/arm/dts/imx6qdl-microsom.dtsi deleted file mode 100644 index 0bf618ecb8..0000000000 --- a/arch/arm/dts/imx6qdl-microsom.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright 2013 Russell King - * - * The code contained herein is licensed under the GNU General Public - * License version 2. - */ -#include <arm/imx6qdl-microsom.dtsi> - -&usbotg { - phy_type = "utmi"; -}; - -&usbh1 { - phy_type = "utmi"; - dr_mode = "host"; -}; diff --git a/arch/arm/dts/rk3188-clocks.dtsi b/arch/arm/dts/rk3188-clocks.dtsi deleted file mode 100644 index b1b92dc245..0000000000 --- a/arch/arm/dts/rk3188-clocks.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - dummy48m: dummy48m { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - dummy150m: dummy150m { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy150m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_aclk_core", - "reserved", "gate_i2s0", - "gate_i2s0_frac", "reserved", - "reserved", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer3", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@200000d8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d8 0x4>; - clocks = <&clk_gates2 1>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&clk_gates2 3>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_periph_src", "gate_aclk_periph", - "gate_hclk_periph", "gate_pclk_periph", - "gate_smc", "gate_mac", - "gate_hsadc", "gate_hsadc_frac", - "gate_saradc", "gate_spi0", - "gate_spi1", "gate_mmc0", - "gate_mac_lbtest", "gate_mmc1", - "gate_emmc", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@200000dc { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000dc 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&xin24m>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", - "gate_dclk_lcdc1", "gate_pclkin_cif0", - "gate_timer2", "gate_timer4", - "gate_hsicphy", "gate_cif0_out", - "gate_timer5", "gate_aclk_vepu", - "gate_hclk_vepu", "gate_aclk_vdpu", - "gate_hclk_vdpu", "reserved", - "gate_timer6", "gate_aclk_gpu_src"; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@200000e0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e0 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates2 3>, - <&clk_gates2 1>, <&clk_gates2 1>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 3>, <&dummy>, - <&clk_gates0 3>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", - "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", - "gate_aclk_pei_niu", "gate_hclk_usb_peri", - "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", - "gate_hclk_cpubus", "gate_hclk_ahb2apb", - "gate_aclk_strc_sys", "reserved", - "gate_aclk_intmem", "reserved", - "gate_hclk_imem1", "gate_hclk_imem0"; - - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@200000e4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e4 0x4>; - clocks = <&clk_gates0 3>, <&clk_gates2 1>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 4>, <&clk_gates0 5>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates4 5>; - - clock-output-names = - "gate_aclk_dmac1", "gate_aclk_dmac2", - "gate_pclk_efuse", "gate_pclk_tzpc", - "gate_pclk_grf", "gate_pclk_pmu", - "gate_hclk_rom", "gate_pclk_ddrupctl", - "gate_aclk_smc", "gate_hclk_nandc", - "gate_hclk_mmc0", "gate_hclk_mmc1", - "gate_hclk_emmc", "gate_hclk_otg0"; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@200000e8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e8 0x4>; - clocks = <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&dummy>, <&dummy>, - <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>; - - clock-output-names = - "gate_aclk_lcdc0", "gate_hclk_lcdc0", - "gate_hclk_lcdc1", "gate_aclk_lcdc1", - "gate_hclk_cif0", "gate_aclk_cif0", - "reserved", "reserved", - "gate_aclk_ipp", "gate_hclk_ipp", - "gate_hclk_rga", "gate_aclk_rga", - "gate_hclk_vio_bus", "gate_aclk_vio0"; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@200000ec { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000ec 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates0 4>, - <&clk_gates0 4>, <&dummy>, - <&dummy>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates0 5>, - <&dummy>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>; - - clock-output-names = - "gate_hclk_emac", "gate_hclk_spdif", - "gate_hclk_i2s0_2ch", "gate_hclk_otg1", - "gate_hclk_hsic", "gate_hclk_hsadc", - "gate_hclk_pidf", "gate_pclk_timer0", - "reserved", "gate_pclk_timer2", - "gate_pclk_pwm01", "gate_pclk_pwm23", - "gate_pclk_spi0", "gate_pclk_spi1", - "gate_pclk_saradc", "gate_pclk_wdt"; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@200000f0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f0 0x4>; - clocks = <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&dummy>; - - clock-output-names = - "gate_pclk_uart0", "gate_pclk_uart1", - "gate_pclk_uart2", "gate_pclk_uart3", - "gate_pclk_i2c0", "gate_pclk_i2c1", - "gate_pclk_i2c2", "gate_pclk_i2c3", - "gate_pclk_i2c4", "gate_pclk_gpio0", - "gate_pclk_gpio1", "gate_pclk_gpio2", - "gate_pclk_gpio3", "gate_aclk_gps"; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@200000f4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f4 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_clk_core_dbg", "gate_pclk_dbg", - "gate_clk_trace", "gate_atclk", - "gate_clk_l2c", "gate_aclk_vio1", - "gate_pclk_publ", "gate_aclk_gpu"; - - #clock-cells = <1>; - }; - }; - -}; diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index 2d49d6981c..47b2487dd9 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -12,22 +12,30 @@ * GNU General Public License for more details. */ -/dts-v1/; -#include "rk3188.dtsi" +#include <arm/rk3188-radxarock.dts> / { - model = "Radxa Rock"; - compatible = "radxa,rock", "rockchip,rk3188"; + chosen { + linux,stdout-path = &uart2; - memory { - reg = <0x60000000 0x80000000>; - }; - - soc { - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; + environment { + compatible = "barebox,environment"; + device-path = &mmc0, "partname:barebox-environment"; status = "okay"; }; }; }; + +&mmc0 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi deleted file mode 100644 index 277a915096..0000000000 --- a/arch/arm/dts/rk3188.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include "rk3xxx.dtsi" -#include "rk3188-clocks.dtsi" - -/* barebox additions */ -/ { - soc { - ethernet@10204000 { - compatible = "snps,arc-emac"; - reg = <0x10204000 0x100>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <50000000>; - max-speed = <100>; - phy = <&phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&emac0_pins>; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - pinctrl@20008000 { - emac0 { - emac0_pins: emac0-pins { - rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_up>, - <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_up>, - <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_up>, - <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_up>, - <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_up>, - <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, - <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_up>, - <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_up>, - <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_up>, - <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_up>; - }; - }; - }; - }; -}; - -/* original rk3188.dtsi from Linux 3.16 */ -/ { - compatible = "rockchip,rk3188"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x3>; - }; - }; - - soc { - global-timer@1013c200 { - interrupts = <GIC_PPI 11 0xf04>; - }; - - local-timer@1013c600 { - interrupts = <GIC_PPI 13 0xf04>; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x8000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@0x2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@0x2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 10>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 11>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 12>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg_pull_up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg_pull_down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg_pull_none { - bias-disable; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, - <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>, - <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>, - <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>, - <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi deleted file mode 100644 index 2adf1cc9e8..0000000000 --- a/arch/arm/dts/rk3xxx.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; - reg = <0x20004000 0x100>; - }; - - grf: grf@20008000 { - compatible = "syscon"; - reg = <0x20008000 0x200>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - - L2: l2-cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = <GIC_PPI 11 0x304>; - clocks = <&dummy150m>; - }; - - local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = <GIC_PPI 13 0x304>; - clocks = <&dummy150m>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 8>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 10>; - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 12>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 14>; - status = "disabled"; - }; - - dwmmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&clk_gates5 10>, <&clk_gates2 11>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; - - dwmmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&clk_gates5 11>, <&clk_gates2 13>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts new file mode 100644 index 0000000000..025d07c18c --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/include/ "socfpga_cyclone5.dtsi" + +/ { + model = "Altera SOCFPGA Cyclone V SoC Development Kit"; + compatible = "altr,socdk", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x0>; + }; + + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&mmc { + cd-gpios = <&gpio1 18 0>; + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; +}; diff --git a/arch/arm/include/asm/barebox.h b/arch/arm/include/asm/barebox.h index 2b08d68909..31a8e15630 100644 --- a/arch/arm/include/asm/barebox.h +++ b/arch/arm/include/asm/barebox.h @@ -5,4 +5,8 @@ #define ARCH_HAS_STACK_DUMP #endif +#ifdef CONFIG_ARM_EXCEPTIONS +#define ARCH_HAS_DATA_ABORT_MASK +#endif + #endif /* _BAREBOX_H_ */ diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index b85e6fa356..5b275264b5 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -494,6 +494,7 @@ choice config MACH_SAMA5D4EK bool "Atmel SAMA5D4 Evaluation Kit" + select HAVE_DEFAULT_ENVIRONMENT_NEW help Select this if you are using Atmel's SAMA5D4-EK Evaluation Kit. diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index f684d32949..def49dc00d 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -48,6 +48,10 @@ #define ARCH_EXID_AT91SAM9G25 0x00000003 #define ARCH_EXID_AT91SAM9X25 0x00000004 +#define ARCH_EXID_AT91SAM9N12 0x00000006 +#define ARCH_EXID_AT91SAM9CN11 0x00000009 +#define ARCH_EXID_AT91SAM9CN12 0x00000005 + #define ARCH_EXID_SAMA5D3 0x00004300 #define ARCH_EXID_SAMA5D31 0x00444300 #define ARCH_EXID_SAMA5D33 0x00414300 @@ -113,6 +117,9 @@ enum at91_soc_subtype { AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, + /* SAM9N12 */ + AT91_SOC_SAM9CN11, AT91_SOC_SAM9CN12, + /* SAMA5D3 */ AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 030b8a2c58..341979ae89 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -156,6 +156,20 @@ static void __init soc_detect(u32 dbgu_base) } } + if (at91_soc_initdata.type == AT91_SOC_SAM9N12) { + switch (at91_soc_initdata.exid) { + case ARCH_EXID_AT91SAM9N12: + at91_soc_initdata.subtype = AT91_SOC_SAM9N12; + break; + case ARCH_EXID_AT91SAM9CN11: + at91_soc_initdata.subtype = AT91_SOC_SAM9CN11; + break; + case ARCH_EXID_AT91SAM9CN12: + at91_soc_initdata.subtype = AT91_SOC_SAM9CN12; + break; + } + } + if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) { switch (at91_soc_initdata.exid) { case ARCH_EXID_SAMA5D31: @@ -229,6 +243,9 @@ static const char *soc_subtype_name[] = { [AT91_SOC_SAM9X35] = "at91sam9x35", [AT91_SOC_SAM9G25] = "at91sam9g25", [AT91_SOC_SAM9X25] = "at91sam9x25", + [AT91_SOC_SAM9N12] = "at91sam9n12", + [AT91_SOC_SAM9CN11] = "at91sam9cn11", + [AT91_SOC_SAM9CN12] = "at91sam9cn12", [AT91_SOC_SAMA5D31] = "sama5d31", [AT91_SOC_SAMA5D33] = "sama5d33", [AT91_SOC_SAMA5D34] = "sama5d34", diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 477207e646..c62cea8a0b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -26,7 +26,6 @@ config ARCH_TEXT_BASE default 0x93d00000 if MACH_TX25 default 0x7ff00000 if MACH_TQMA53 default 0x97f00000 if MACH_TX51 - default 0x4fc00000 if MACH_MX6Q_ARM2 default 0x97f00000 if MACH_CCMX51 default 0x4fc00000 if MACH_SABRELITE default 0x8fe00000 if MACH_TX53 @@ -174,6 +173,7 @@ config ARCH_IMX6 select ARCH_HAS_FEC_IMX select CPU_V7 select PINCTRL_IMX_IOMUX_V3 + select COMMON_CLK_OF_PROVIDER config ARCH_IMX6SX bool @@ -527,12 +527,6 @@ config MACH_GUF_VINCELL select ARCH_IMX53 select HAVE_DEFAULT_ENVIRONMENT_NEW -comment "i.MX6 Boards" - -config MACH_MX6Q_ARM2 - bool "Freescale i.MX6q Armadillo2" - select ARCH_IMX6 - endchoice # ---------------------------------------------------------- diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c index ea805b0f64..8a0d875049 100644 --- a/arch/arm/mach-imx/clk-imx5.c +++ b/arch/arm/mach-imx/clk-imx5.c @@ -178,9 +178,7 @@ static const char *ipu_sel[] = { "ahb", }; -static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil, - unsigned long rate_osc, unsigned long rate_ckih1, - unsigned long rate_ckih2) +static void __init mx5_clocks_common_init(struct device_d *dev, void __iomem *base) { writel(0xffffffff, base + CCM_CCGR0); writel(0xffffffff, base + CCM_CCGR1); @@ -191,11 +189,10 @@ static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate writel(0xffffffff, base + CCM_CCGR6); writel(0xffffffff, base + CCM_CCGR7); - clks[IMX5_CLK_DUMMY] = clk_fixed("dummy", 0); - clks[IMX5_CLK_CKIL] = clk_fixed("ckil", rate_ckil); - clks[IMX5_CLK_OSC] = clk_fixed("osc", rate_osc); - clks[IMX5_CLK_CKIH1] = clk_fixed("ckih1", rate_ckih1); - clks[IMX5_CLK_CKIH2] = clk_fixed("ckih2", rate_ckih2); + if (!IS_ENABLED(COMMON_CLK_OF_PROVIDER) || !dev->device_node) { + clks[IMX5_CLK_CKIL] = clk_fixed("ckil", 32768); + clks[IMX5_CLK_OSC] = clk_fixed("osc", 24000000); + } clks[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1, lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); @@ -273,14 +270,13 @@ static void mx51_clocks_ipu_init(void __iomem *regs) clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX51_IPU_BASE_ADDR, "di1"); } -int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc, - unsigned long rate_ckih1, unsigned long rate_ckih2) +int __init mx51_clocks_init(struct device_d *dev, void __iomem *regs) { clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR); clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR); clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL3_BASE_ADDR); - mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2); + mx5_clocks_common_init(dev, regs); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART1_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART2_BASE_ADDR, NULL); @@ -314,7 +310,7 @@ static int imx51_ccm_probe(struct device_d *dev) if (IS_ERR(regs)) return PTR_ERR(regs); - mx51_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */ + mx51_clocks_init(dev, regs); return 0; } @@ -359,15 +355,14 @@ static void mx53_clocks_ipu_init(void __iomem *regs) clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX53_IPU_BASE_ADDR, "di1"); } -int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc, - unsigned long rate_ckih1, unsigned long rate_ckih2) +int __init mx53_clocks_init(struct device_d *dev, void __iomem *regs) { clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR); clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR); clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX53_PLL3_BASE_ADDR); clks[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR); - mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2); + mx5_clocks_common_init(dev, regs); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART1_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART2_BASE_ADDR, NULL); @@ -401,7 +396,7 @@ static int imx53_ccm_probe(struct device_d *dev) regs = dev_request_mem_region(dev, 0); - mx53_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */ + mx53_clocks_init(dev, regs); return 0; } diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c index 3bc59497a8..dccf0a8c20 100644 --- a/arch/arm/mach-imx/clk-imx6.c +++ b/arch/arm/mach-imx/clk-imx6.c @@ -21,6 +21,7 @@ #include <mach/imx6-regs.h> #include <mach/revision.h> #include <mach/imx6.h> +#include <dt-bindings/clock/imx6qdl-clock.h> #include "clk.h" @@ -55,44 +56,8 @@ #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) -enum mx6q_clks { - dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, - pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, - pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw, - periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel, - esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel, - gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel, - ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel, - ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, - ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel, - usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel, - emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2, - periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf, - asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root, - gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf, - ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre, - ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf, - ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf, - usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf, - emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf, - mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial, - can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet, - esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, - hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, - ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, - mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, - gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, - ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, - usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, - pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, - ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, - sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, - spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, - lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, enfc_gate, clk_max, -}; - -static struct clk *clks[clk_max]; +static struct clk *clks[IMX6QDL_CLK_END]; +static struct clk_onecell_data clk_data; static const char *step_sels[] = { "osc", @@ -144,7 +109,7 @@ static const char *enfc_sels[] = { "pll2_pfd2_396m", }; -static const char *emi_sels[] = { +static const char *eim_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", @@ -256,65 +221,56 @@ static struct clk_div_table video_div_table[] = { static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb) { - clks[pll5_post_div] = imx_clk_divider_table("pll5_post_div", "pll5_video", anab + 0xa0, 19, 2, post_div_table); - clks[pll5_video_div] = imx_clk_divider_table("pll5_video_div", "pll5_post_div", anab + 0x170, 30, 2, video_div_table); - - clks[ipu1_sel] = imx_clk_mux("ipu1_sel", cb + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); - clks[ipu2_sel] = imx_clk_mux("ipu2_sel", cb + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); - clks[ldb_di0_sel] = imx_clk_mux_p("ldb_di0_sel", cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); - clks[ldb_di1_sel] = imx_clk_mux_p("ldb_di1_sel", cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); - clks[ipu1_di0_pre_sel] = imx_clk_mux_p("ipu1_di0_pre_sel", cb + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); - clks[ipu1_di1_pre_sel] = imx_clk_mux_p("ipu1_di1_pre_sel", cb + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); - clks[ipu2_di0_pre_sel] = imx_clk_mux_p("ipu2_di0_pre_sel", cb + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); - clks[ipu2_di1_pre_sel] = imx_clk_mux_p("ipu2_di1_pre_sel", cb + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); - clks[ipu1_di0_sel] = imx_clk_mux_p("ipu1_di0_sel", cb + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels)); - clks[ipu1_di1_sel] = imx_clk_mux_p("ipu1_di1_sel", cb + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels)); - clks[ipu2_di0_sel] = imx_clk_mux_p("ipu2_di0_sel", cb + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels)); - clks[ipu2_di1_sel] = imx_clk_mux_p("ipu2_di1_sel", cb + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); - - clks[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", cb + 0x3c, 11, 3); - clks[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", cb + 0x3c, 16, 3); - clks[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); - clks[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1); - clks[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); - clks[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1); - clks[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", cb + 0x34, 3, 3); - clks[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", cb + 0x34, 12, 3); - clks[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3); - clks[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", cb + 0x38, 12, 3); - - clkdev_add_physbase(clks[ipu1_podf], MX6_IPU1_BASE_ADDR, "bus"); - clkdev_add_physbase(clks[ipu1_di0_sel], MX6_IPU1_BASE_ADDR, "di0"); - clkdev_add_physbase(clks[ipu1_di1_sel], MX6_IPU1_BASE_ADDR, "di1"); - clkdev_add_physbase(clks[ipu2_podf], MX6_IPU2_BASE_ADDR, "bus"); - clkdev_add_physbase(clks[ipu2_di0_sel], MX6_IPU2_BASE_ADDR, "di0"); - clkdev_add_physbase(clks[ipu2_di1_sel], MX6_IPU2_BASE_ADDR, "di1"); - - clkdev_add_physbase(clks[ldb_di0_sel], 0x020e0008, "di0_pll"); - clkdev_add_physbase(clks[ldb_di1_sel], 0x020e0008, "di1_pll"); - clkdev_add_physbase(clks[ipu1_di0_sel], 0x020e0008, "di0_sel"); - clkdev_add_physbase(clks[ipu1_di1_sel], 0x020e0008, "di1_sel"); - clkdev_add_physbase(clks[ipu2_di0_sel], 0x020e0008, "di2_sel"); - clkdev_add_physbase(clks[ipu2_di1_sel], 0x020e0008, "di3_sel"); - clkdev_add_physbase(clks[ldb_di0], 0x020e0008, "di0"); - clkdev_add_physbase(clks[ldb_di1], 0x020e0008, "di1"); - clkdev_add_physbase(clks[ahb], 0x00120000, "iahb"); - clkdev_add_physbase(clks[pll3_pfd1_540m], 0x00120000, "isfr"); - - clk_set_parent(clks[ipu1_di0_sel], clks[ipu1_di0_pre]); - clk_set_parent(clks[ipu1_di1_sel], clks[ipu1_di1_pre]); - clk_set_parent(clks[ipu2_di0_sel], clks[ipu2_di0_pre]); - clk_set_parent(clks[ipu2_di1_sel], clks[ipu2_di1_pre]); - - clk_set_parent(clks[ipu1_di0_pre_sel], clks[pll5_video_div]); - clk_set_parent(clks[ipu1_di1_pre_sel], clks[pll5_video_div]); - clk_set_parent(clks[ipu2_di0_pre_sel], clks[pll5_video_div]); - clk_set_parent(clks[ipu2_di1_pre_sel], clks[pll5_video_div]); + clks[IMX6QDL_CLK_PLL5_POST_DIV] = imx_clk_divider_table("pll5_post_div", "pll5_video", anab + 0xa0, 19, 2, post_div_table); + clks[IMX6QDL_CLK_PLL5_VIDEO_DIV] = imx_clk_divider_table("pll5_video_div", "pll5_post_div", anab + 0x170, 30, 2, video_div_table); + + clks[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", cb + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); + clks[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", cb + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); + clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel", cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + clks[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_p("ipu1_di0_pre_sel", cb + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); + clks[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_p("ipu1_di1_pre_sel", cb + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); + clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_p("ipu2_di0_pre_sel", cb + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); + clks[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_p("ipu2_di1_pre_sel", cb + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); + clks[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_p("ipu1_di0_sel", cb + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels)); + clks[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_p("ipu1_di1_sel", cb + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels)); + clks[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_p("ipu2_di0_sel", cb + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels)); + clks[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_p("ipu2_di1_sel", cb + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); + + clks[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", cb + 0x3c, 11, 3); + clks[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", cb + 0x3c, 16, 3); + clks[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); + clks[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1); + clks[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); + clks[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1); + clks[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", cb + 0x34, 3, 3); + clks[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", cb + 0x34, 12, 3); + clks[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3); + clks[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", cb + 0x38, 12, 3); + + clks[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", cb + 0x74, 0); + clks[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", cb + 0x74, 2); + clks[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", cb + 0x74, 4); + clks[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", cb + 0x74, 6); + clks[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", cb + 0x74, 8); + clks[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", cb + 0x74, 12); + clks[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", cb + 0x74, 14); + clks[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", cb + 0x74, 10); + + clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI0_SEL], clks[IMX6QDL_CLK_IPU1_DI0_PRE]); + clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_SEL], clks[IMX6QDL_CLK_IPU1_DI1_PRE]); + clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI0_SEL], clks[IMX6QDL_CLK_IPU2_DI0_PRE]); + clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI1_SEL], clks[IMX6QDL_CLK_IPU2_DI1_PRE]); + + clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]); if ((imx_silicon_revision() != IMX_CHIP_REV_1_0) || cpu_is_mx6dl()) { - clk_set_parent(clks[ldb_di0_sel], clks[pll5_video_div]); - clk_set_parent(clks[ldb_di1_sel], clks[pll5_video_div]); + clk_set_parent(clks[IMX6QDL_CLK_LDB_DI0_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]); + clk_set_parent(clks[IMX6QDL_CLK_LDB_DI1_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]); } } @@ -322,9 +278,6 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb) static int imx6_ccm_probe(struct device_d *dev) { void __iomem *base, *anatop_base, *ccm_base; - unsigned long ckil_rate = 32768; - unsigned long ckih_rate = 0; - unsigned long osc_rate = 24000000; anatop_base = (void *)MX6_ANATOP_BASE_ADDR; ccm_base = dev_request_mem_region(dev, 0); @@ -333,126 +286,129 @@ static int imx6_ccm_probe(struct device_d *dev) base = anatop_base; - clks[dummy] = clk_fixed("dummy", 0); - clks[ckil] = clk_fixed("ckil", ckil_rate); - clks[ckih] = clk_fixed("ckih", ckih_rate); - clks[osc] = clk_fixed("osc", osc_rate); - /* type name parent_name base div_mask */ - clks[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); - clks[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); - clks[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); - clks[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); - clks[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); - clks[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0); - clks[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); - clks[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); + clks[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); + clks[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); + clks[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); + clks[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); + clks[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); + clks[IMX6QDL_CLK_PLL8_MLB] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0); + clks[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); + clks[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); - clks[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); - clks[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); + clks[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); + clks[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); - clks[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); - clks[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); - clks[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); - clks[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); + clks[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); + clks[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); + clks[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); + clks[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); - clks[enet_ref] = imx_clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table); + clks[IMX6QDL_CLK_ENET_REF] = imx_clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table); /* name parent_name reg idx */ - clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); - clks[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); - clks[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); - clks[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); - clks[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); - clks[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); - clks[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); + clks[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); + clks[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); + clks[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); + clks[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); + clks[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); + clks[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); + clks[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); /* name parent_name mult div */ - clks[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); - clks[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); - clks[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); - clks[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); - clks[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); + clks[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); + clks[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); + clks[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); + clks[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); + clks[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); base = ccm_base; /* name reg shift width parent_names num_parents */ - clks[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clks[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); - clks[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clks[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clks[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clks[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clks[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); - clks[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); - clks[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels)); - clks[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels)); - clks[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); - clks[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); + clks[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); + clks[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); + clks[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clks[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clks[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); + clks[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); + clks[IMX6QDL_CLK_EIM_SEL] = imx_clk_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels)); + clks[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_sels, ARRAY_SIZE(eim_sels)); + clks[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); + clks[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); /* name reg shift width busy: reg, shift parent_names num_parents */ - clks[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); - clks[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); - - clks[enfc_gate] = imx_clk_gate2("enfc_gate", "enfc_sel", base + 0x70, 14); + clks[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); + clks[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); /* name parent_name reg shift width */ - clks[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); - clks[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); - clks[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); - clks[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6); - clks[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); - clks[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); - clks[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); - clks[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); - clks[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); - clks[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); - clks[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); - clks[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_gate", base + 0x2c, 18, 3); - clks[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); - clks[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3); - clks[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3); - clks[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); + clks[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); + clks[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); + clks[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); + clks[IMX6QDL_CLK_IPG_PER] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6); + clks[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); + clks[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); + clks[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); + clks[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); + clks[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); + clks[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); + clks[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); + clks[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); + clks[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); + clks[IMX6QDL_CLK_EIM_PODF] = imx_clk_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3); + clks[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); + clks[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); /* name parent_name reg shift width busy: reg, shift */ - clks[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); - clks[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); - clks[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); - clks[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); - clks[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); - - clkdev_add_physbase(clks[uart_serial_podf], MX6_UART1_BASE_ADDR, NULL); - clkdev_add_physbase(clks[uart_serial_podf], MX6_UART2_BASE_ADDR, NULL); - clkdev_add_physbase(clks[uart_serial_podf], MX6_UART3_BASE_ADDR, NULL); - clkdev_add_physbase(clks[uart_serial_podf], MX6_UART4_BASE_ADDR, NULL); - clkdev_add_physbase(clks[uart_serial_podf], MX6_UART5_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI1_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI2_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI3_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI4_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI5_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ipg_per], MX6_GPT_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ipg], MX6_ENET_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ipg], MX6_OCOTP_BASE_ADDR, NULL); - clkdev_add_physbase(clks[usdhc1_podf], MX6_USDHC1_BASE_ADDR, NULL); - clkdev_add_physbase(clks[usdhc2_podf], MX6_USDHC2_BASE_ADDR, NULL); - clkdev_add_physbase(clks[usdhc3_podf], MX6_USDHC3_BASE_ADDR, NULL); - clkdev_add_physbase(clks[usdhc4_podf], MX6_USDHC4_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ipg_per], MX6_I2C1_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ipg_per], MX6_I2C2_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ipg_per], MX6_I2C3_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ahb], MX6_SATA_BASE_ADDR, NULL); - clkdev_add_physbase(clks[usbphy1], MX6_USBPHY1_BASE_ADDR, NULL); - clkdev_add_physbase(clks[usbphy2], MX6_USBPHY2_BASE_ADDR, NULL); - clkdev_add_physbase(clks[enfc_podf], MX6_GPMI_BASE_ADDR, NULL); - clkdev_add_physbase(clks[ipg_per], MX6_PWM1_BASE_ADDR, "per"); - clkdev_add_physbase(clks[ipg_per], MX6_PWM2_BASE_ADDR, "per"); - clkdev_add_physbase(clks[ipg_per], MX6_PWM3_BASE_ADDR, "per"); - clkdev_add_physbase(clks[ipg_per], MX6_PWM4_BASE_ADDR, "per"); + clks[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); + clks[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); + clks[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); + clks[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); + clks[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); + + /* name parent_name reg shift */ + clks[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); + clks[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); + clks[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); + clks[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); + clks[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); + if (cpu_is_mx6dl()) + clks[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); + else + clks[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); + clks[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); + clks[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); + clks[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); + clks[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); + clks[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); + clks[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); + clks[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); + clks[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); + clks[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); + clks[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); + clks[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); + clks[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); + clks[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); + clks[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); + clks[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); + clks[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); + clks[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); + clks[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); + clks[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); + clks[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); + clks[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); + clks[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); + clks[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); + clks[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); + clks[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); + clks[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); + clks[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); + clks[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3)) imx6_add_video_clks(anatop_base, ccm_base); @@ -469,9 +425,13 @@ static int imx6_ccm_probe(struct device_d *dev) writel(0xffff3fff, ccm_base + CCGR6); /* gate VPU */ writel(0xffffffff, ccm_base + CCGR7); - clk_enable(clks[pll6_enet]); - clk_enable(clks[sata_ref_100m]); - clk_enable(clks[enfc_podf]); + clk_data.clks = clks; + clk_data.clk_num = IMX6QDL_CLK_END; + of_clk_add_provider(dev->device_node, of_clk_src_onecell_get, &clk_data); + + clk_enable(clks[IMX6QDL_CLK_PLL6_ENET]); + clk_enable(clks[IMX6QDL_CLK_SATA_REF_100M]); + clk_enable(clks[IMX6QDL_CLK_ENFC_PODF]); return 0; } diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index c6479a0e54..0a71db66d7 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -480,7 +480,7 @@ upper_or_coalesced_range(unsigned long base0, unsigned long size0, } } -void __naked __noreturn imx1_barebox_entry(void *boarddata) +void __noreturn imx1_barebox_entry(void *boarddata) { unsigned long base, size; @@ -493,7 +493,7 @@ void __naked __noreturn imx1_barebox_entry(void *boarddata) barebox_arm_entry(base, size, boarddata); } -void __naked __noreturn imx25_barebox_entry(void *boarddata) +void __noreturn imx25_barebox_entry(void *boarddata) { unsigned long base, size; @@ -506,7 +506,7 @@ void __naked __noreturn imx25_barebox_entry(void *boarddata) barebox_arm_entry(base, size, boarddata); } -void __naked __noreturn imx27_barebox_entry(void *boarddata) +void __noreturn imx27_barebox_entry(void *boarddata) { unsigned long base, size; @@ -521,7 +521,7 @@ void __naked __noreturn imx27_barebox_entry(void *boarddata) barebox_arm_entry(base, size, boarddata); } -void __naked __noreturn imx31_barebox_entry(void *boarddata) +void __noreturn imx31_barebox_entry(void *boarddata) { unsigned long base, size; @@ -536,7 +536,7 @@ void __naked __noreturn imx31_barebox_entry(void *boarddata) barebox_arm_entry(base, size, boarddata); } -void __naked __noreturn imx35_barebox_entry(void *boarddata) +void __noreturn imx35_barebox_entry(void *boarddata) { unsigned long base, size; @@ -551,7 +551,7 @@ void __naked __noreturn imx35_barebox_entry(void *boarddata) barebox_arm_entry(base, size, boarddata); } -void __naked __noreturn imx51_barebox_entry(void *boarddata) +void __noreturn imx51_barebox_entry(void *boarddata) { unsigned long base, size; @@ -564,7 +564,7 @@ void __naked __noreturn imx51_barebox_entry(void *boarddata) barebox_arm_entry(base, size, boarddata); } -void __naked __noreturn imx53_barebox_entry(void *boarddata) +void __noreturn imx53_barebox_entry(void *boarddata) { unsigned long base, size; diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h index 28d44da938..468a9280c7 100644 --- a/arch/arm/mach-imx/include/mach/esdctl.h +++ b/arch/arm/mach-imx/include/mach/esdctl.h @@ -128,14 +128,14 @@ #define ESDCFGx_tRC_16 0x0000000f #ifndef __ASSEMBLY__ -void __naked __noreturn imx1_barebox_entry(void *boarddata); -void __naked __noreturn imx25_barebox_entry(void *boarddata); -void __naked __noreturn imx27_barebox_entry(void *boarddata); -void __naked __noreturn imx31_barebox_entry(void *boarddata); -void __naked __noreturn imx35_barebox_entry(void *boarddata); -void __naked __noreturn imx51_barebox_entry(void *boarddata); -void __naked __noreturn imx53_barebox_entry(void *boarddata); -void __naked __noreturn imx6_barebox_entry(void *boarddata); +void __noreturn imx1_barebox_entry(void *boarddata); +void __noreturn imx25_barebox_entry(void *boarddata); +void __noreturn imx27_barebox_entry(void *boarddata); +void __noreturn imx31_barebox_entry(void *boarddata); +void __noreturn imx35_barebox_entry(void *boarddata); +void __noreturn imx51_barebox_entry(void *boarddata); +void __noreturn imx53_barebox_entry(void *boarddata); +void __noreturn imx6_barebox_entry(void *boarddata); void imx_esdctl_disable(void); #endif diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index 7aa37ebd0f..444ddf8377 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -147,17 +147,11 @@ config MACH_BEAGLEBONE help Say Y here if you are using Beagle Bone -config MACH_PCM051 - bool "Phytec phyCORE pcm051" +config MACH_PHYTEC_SOM_AM335X + bool "Phytec AM335X SOMs" select ARCH_AM33XX help - Say Y here if you are using Phytecs phyCORE pcm051 board - -config MACH_PFLA03 - bool "Phytec phyFLEX am335x pfla03" - select ARCH_AM33XX - help - Say Y here if you are using Phytecs phyFLEX pfla03 board + Say Y here if you are using a am335x based Phytecs SOM endif choice diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 912138d419..ee30351fa4 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -26,6 +26,7 @@ #include <mach/sys_info.h> #include <mach/am33xx-generic.h> #include <mach/gpmc.h> +#include <reset_source.h> void __noreturn am33xx_reset_cpu(unsigned long addr) { @@ -152,6 +153,38 @@ static int am33xx_bootsource(void) return 0; } +static void am33xx_detect_reset_reason(void) +{ + uint32_t val = 0; + + val = readl(AM33XX_PRM_RSTST); + /* clear AM33XX_PRM_RSTST - must be cleared by software + * (warm reset insensitive) */ + writel(val, AM33XX_PRM_RSTST); + + switch (val) { + case (1 << 9): + reset_source_set(RESET_JTAG); + break; + case (1 << 5): + reset_source_set(RESET_EXT); + break; + case (1 << 4): + case (1 << 3): + reset_source_set(RESET_WDG); + break; + case (1 << 1): + reset_source_set(RESET_RST); + break; + case (1 << 0): + reset_source_set(RESET_POR); + break; + default: + reset_source_set(RESET_UKWN); + break; + } +} + int am33xx_register_ethaddr(int eth_id, int mac_id) { void __iomem *mac_id_low = (void *)AM33XX_MAC_ID0_LO + mac_id * 8; @@ -209,6 +242,9 @@ int am33xx_init(void) am33xx_enable_per_clocks(); + if (IS_ENABLED(CONFIG_RESET_SOURCE)) + am33xx_detect_reset_reason(); + return am33xx_bootsource(); } diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index 4e63b437ea..7c209ec5d8 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -68,6 +68,7 @@ #define AM33XX_PRM_RSTCTRL (AM33XX_PRM_BASE + 0x0f00) #define AM33XX_PRM_RSTCTRL_RESET 0x1 +#define AM33XX_PRM_RSTST (AM33XX_PRM_BASE + 0x0f08) /* CTRL */ #define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000) diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index a45e01a702..67d1f4b5a9 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -64,6 +64,7 @@ config MACH_MIOA701 bool "Mitac Mio A701" select BCH_CONST_PARAMS select PWM + select POLLER help Say Y here if you are using a Mitac Mio A701 smartphone diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 6f4ec169e3..820eb10ac2 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -1,2 +1 @@ obj-y += core.o -obj-y += pll.o
\ No newline at end of file diff --git a/arch/arm/mach-rockchip/include/mach/debug_ll.h b/arch/arm/mach-rockchip/include/mach/debug_ll.h new file mode 100644 index 0000000000..c666b99e81 --- /dev/null +++ b/arch/arm/mach-rockchip/include/mach/debug_ll.h @@ -0,0 +1,60 @@ +#ifndef __MACH_DEBUG_LL_H__ +#define __MACH_DEBUG_LL_H__ + +#include <io.h> + +#if CONFIG_DEBUG_ROCKCHIP_UART_PORT == 0 +#define UART_BASE 0x10124000 +#endif +#if CONFIG_DEBUG_ROCKCHIP_UART_PORT == 1 +#define UART_BASE 0x10126000 +#endif +#if CONFIG_DEBUG_ROCKCHIP_UART_PORT == 2 +#define UART_BASE 0x20064000 +#endif +#if CONFIG_DEBUG_ROCKCHIP_UART_PORT == 3 +#define UART_BASE 0x20068000 +#endif + +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR (5 << 2) +#define THR (0 << 2) + +#define LCR_BKSE 0x80 /* Bank select enable */ +#define LSR (5 << 2) +#define THR (0 << 2) +#define DLL (0 << 2) +#define IER (1 << 2) +#define DLM (1 << 2) +#define FCR (2 << 2) +#define LCR (3 << 2) +#define MCR (4 << 2) +#define MDR (8 << 2) + +static inline void INIT_LL(void) +{ + unsigned int clk = 100000000; + unsigned int divisor = clk / 16 / 115200; + + writeb(0x00, UART_BASE + LCR); + writeb(0x00, UART_BASE + IER); + writeb(0x07, UART_BASE + MDR); + writeb(LCR_BKSE, UART_BASE + LCR); + writeb(divisor & 0xff, UART_BASE + DLL); + writeb(divisor >> 8, UART_BASE + DLM); + writeb(0x03, UART_BASE + LCR); + writeb(0x03, UART_BASE + MCR); + writeb(0x07, UART_BASE + FCR); + writeb(0x00, UART_BASE + MDR); +} + +static inline void PUTC_LL(char c) +{ + /* Wait until there is space in the FIFO */ + while ((readb(UART_BASE + LSR) & LSR_THRE) == 0); + /* Send the character */ + writeb(c, UART_BASE + THR); + /* Wait to make sure it hits the line, in case we die too soon. */ + while ((readb(UART_BASE + LSR) & LSR_THRE) == 0); +} +#endif diff --git a/arch/arm/mach-rockchip/include/mach/rockchip-pll.h b/arch/arm/mach-rockchip/include/mach/rockchip-pll.h deleted file mode 100644 index c2cd888b00..0000000000 --- a/arch/arm/mach-rockchip/include/mach/rockchip-pll.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_ROCKCHIP_PLL_H -#define __MACH_ROCKCHIP_PLL_H - -enum rk3188_plls { - RK3188_APLL = 0, /* ARM */ - RK3188_DPLL, /* DDR */ - RK3188_CPLL, /* Codec */ - RK3188_GPLL, /* General */ -}; - -int rk3188_pll_set_parameters(int pll, int nr, int nf, int no); - -#endif /* __MACH_ROCKCHIP_PLL_H */ diff --git a/arch/arm/mach-rockchip/pll.c b/arch/arm/mach-rockchip/pll.c deleted file mode 100644 index fce192ccdb..0000000000 --- a/arch/arm/mach-rockchip/pll.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * Based on Linux clk driver: - * Copyright (c) 2014 MundoReader S.L. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <asm/io.h> -#include <common.h> -#include <mach/rockchip-regs.h> - -#define RK3188_CLK_BASE 0x20000000 -#define RK3188_PLL_LOCK_REG 0x200080ac - -#define PLL_MODE_MASK 0x3 -#define PLL_MODE_SLOW 0x0 -#define PLL_MODE_NORM 0x1 -#define PLL_MODE_DEEP 0x2 - -#define PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1) - -#define PLLCON0_OD_MASK 0xf -#define PLLCON0_OD_SHIFT 0 -#define PLLCON0_NR_MASK 0x3f -#define PLLCON0_NR_SHIFT 8 - -#define PLLCON1_NF_MASK 0x1fff -#define PLLCON1_NF_SHIFT 0 - -#define PLLCON2_BWADJ_MASK 0xfff -#define PLLCON2_BWADJ_SHIFT 0 - -#define PLLCON3_RESET (1 << 1) -#define PLLCON3_BYPASS (1 << 0) - -struct rockchip_pll_data { - int con_base; - int mode_offset; - int mode_shift; - int lock_shift; -}; - -struct rockchip_pll_data rk3188_plls[] = { - { 0x00, 0x40, 0x00, 0x06 }, - { 0x10, 0x40, 0x04, 0x05 }, - { 0x20, 0x40, 0x08, 0x07 }, - { 0x30, 0x40, 0x0c, 0x08 }, -}; - -#define HIWORD_UPDATE(val, mask, shift) \ - ((val) << (shift) | (mask) << ((shift) + 16)) - -int rk3188_pll_set_parameters(int pll, int nr, int nf, int no) -{ - struct rockchip_pll_data *d = &rk3188_plls[pll]; - int delay = 0; - - debug("rk3188 pll %d: set param %d %d %d\n", pll, nr, nf, no); - - /* pull pll in slow mode */ - writel(HIWORD_UPDATE(PLL_MODE_SLOW, PLL_MODE_MASK, d->mode_shift), - RK3188_CLK_BASE + d->mode_offset); - /* enter reset */ - writel(HIWORD_UPDATE(PLLCON3_RESET, PLLCON3_RESET, 0), - RK3188_CLK_BASE + d->con_base + 12); - - /* update pll values */ - writel(HIWORD_UPDATE(nr - 1, PLLCON0_NR_MASK, PLLCON0_NR_SHIFT) | - HIWORD_UPDATE(no - 1, PLLCON0_OD_MASK, PLLCON0_OD_SHIFT), - RK3188_CLK_BASE + d->con_base + 0); - writel(HIWORD_UPDATE(nf - 1, PLLCON1_NF_MASK, PLLCON1_NF_SHIFT), - RK3188_CLK_BASE + d->con_base + 4); - writel(HIWORD_UPDATE(nf >> 1, PLLCON2_BWADJ_MASK, PLLCON2_BWADJ_SHIFT), - RK3188_CLK_BASE + d->con_base + 8); - - /* leave reset and wait the reset_delay */ - writel(HIWORD_UPDATE(0, PLLCON3_RESET, 0), - RK3188_CLK_BASE + d->con_base + 12); - udelay(PLL_RESET_DELAY(nr)); - - /* wait for the pll to lock */ - while (delay++ < 24000000) { - if (readl(RK3188_PLL_LOCK_REG) & BIT(d->lock_shift)) - break; - } - - /* go back to normal mode */ - writel(HIWORD_UPDATE(PLL_MODE_NORM, PLL_MODE_MASK, d->mode_shift), - RK3188_CLK_BASE + d->mode_offset); - - return 0; -} -EXPORT_SYMBOL(rk3188_pll_set_parameters); diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig index 13dac29dcc..8f421bb839 100644 --- a/arch/arm/mach-samsung/Kconfig +++ b/arch/arm/mach-samsung/Kconfig @@ -166,6 +166,12 @@ config S3C_NAND_BOOT Add generic support to boot from NAND flash. Image loading will be skipped if the code is running from NOR or already from SDRAM. +config BAREBOX_UPDATE_NAND_S3C24XX + bool + depends on BAREBOX_UPDATE + depends on S3C_NAND_BOOT + default y + endmenu endif diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile index 46393e1725..284c80a2ad 100644 --- a/arch/arm/mach-samsung/Makefile +++ b/arch/arm/mach-samsung/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o mem-s3c64xx.o obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o pbl-$(CONFIG_ARCH_S5PCxx) += mem-s5pcxx.o +obj-$(CONFIG_BAREBOX_UPDATE_NAND_S3C24XX) += bbu-nand-s3c24x0.o obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y) diff --git a/arch/arm/mach-samsung/bbu-nand-s3c24x0.c b/arch/arm/mach-samsung/bbu-nand-s3c24x0.c new file mode 100644 index 0000000000..0d25abfeb7 --- /dev/null +++ b/arch/arm/mach-samsung/bbu-nand-s3c24x0.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2014 Michael Olbrich, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#include <common.h> +#include <malloc.h> +#include <bbu.h> +#include <fs.h> +#include <fcntl.h> + +static int nand_update(struct bbu_handler *handler, struct bbu_data *data) +{ + int fd, ret; + + if (file_detect_type(data->image, data->len) != filetype_arm_barebox && + !bbu_force(data, "Not an ARM barebox image")) + return -EINVAL; + + ret = bbu_confirm(data); + if (ret) + return ret; + + fd = open(data->devicefile, O_WRONLY); + if (fd < 0) + return fd; + + debug("%s: eraseing %s from 0 to 0x%08x\n", __func__, + data->devicefile, data->len); + ret = erase(fd, data->len, 0); + if (ret) { + printf("erasing %s failed with %s\n", data->devicefile, + strerror(-ret)); + goto err_close; + } + + ret = write(fd, data->image, data->len); + if (ret < 0) { + printf("writing update to %s failed with %s\n", data->devicefile, + strerror(-ret)); + goto err_close; + } + + ret = 0; + +err_close: + close(fd); + + return ret; +} + +/* + * Register a s3c24x0 update handler for NAND + */ +int s3c24x0_bbu_nand_register_handler(void) +{ + struct bbu_handler *handler; + int ret; + + handler = xzalloc(sizeof(*handler)); + handler->devicefile = "/dev/nand0.barebox"; + handler->name = "nand"; + handler->handler = nand_update; + handler->flags = BBU_HANDLER_FLAG_DEFAULT; + + ret = bbu_register_handler(handler); + if (ret) + free(handler); + + return ret; +} diff --git a/arch/arm/mach-samsung/include/mach/bbu.h b/arch/arm/mach-samsung/include/mach/bbu.h new file mode 100644 index 0000000000..7ce7052bcf --- /dev/null +++ b/arch/arm/mach-samsung/include/mach/bbu.h @@ -0,0 +1,16 @@ +#ifndef __MACH_BBU_H +#define __MACH_BBU_H + +#include <bbu.h> +#include <errno.h> + +#ifdef CONFIG_BAREBOX_UPDATE_NAND_S3C24XX +int s3c24x0_bbu_nand_register_handler(void); +#else +static inline int s3c24x0_bbu_nand_register_handler(void) +{ + return -ENOSYS; +} +#endif + +#endif diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index f43bc408fd..90b3533b1f 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -8,6 +8,10 @@ config ARCH_TEXT_BASE hex default 0x00100000 if MACH_SOCFPGA_CYCLONE5 +config MACH_SOCFPGA_ALTERA_SOCDK + select HAVE_DEFAULT_ENVIRONMENT_NEW + bool "Altera SoCFPGA Development Kit" + config MACH_SOCFPGA_EBV_SOCRATES select HAVE_DEFAULT_ENVIRONMENT_NEW bool "EBV Socrates" diff --git a/arch/arm/pbl/Makefile b/arch/arm/pbl/Makefile index 1b90b377a6..4c1788dd9d 100644 --- a/arch/arm/pbl/Makefile +++ b/arch/arm/pbl/Makefile @@ -31,10 +31,11 @@ $(obj)/zbarebox.S: $(obj)/zbarebox FORCE $(call if_changed,disasm) PBL_CPPFLAGS += -fdata-sections -ffunction-sections -LDFLAGS_zbarebox := -Map $(obj)/zbarebox.map -LDFLAGS_zbarebox += -static --gc-sections +LDFLAGS_zbarebox := -Map $(obj)/zbarebox.map --gc-sections ifdef CONFIG_PBL_RELOCATABLE LDFLAGS_zbarebox += -pie +else +LDFLAGS_zbarebox += -static endif zbarebox-common := $(barebox-pbl-common) $(obj)/$(piggy_o) zbarebox-lds := $(obj)/zbarebox.lds diff --git a/arch/mips/boards/qemu-malta/include/board/debug_ll.h b/arch/mips/boards/qemu-malta/include/board/debug_ll.h index 1e56040ffe..abeee5345a 100644 --- a/arch/mips/boards/qemu-malta/include/board/debug_ll.h +++ b/arch/mips/boards/qemu-malta/include/board/debug_ll.h @@ -22,6 +22,9 @@ #define DEBUG_LL_UART_ADDR MALTA_PIIX4_UART0 #define DEBUG_LL_UART_SHIFT 0 -#define DEBUG_LL_UART_DIVISOR 1843200 /* no matter for emulated port */ + +#define DEBUG_LL_UART_CLK 1843200 +#define DEBUG_LL_UART_BPS CONFIG_BAUDRATE +#define DEBUG_LL_UART_DIVISOR (DEBUG_LL_UART_CLK / DEBUG_LL_UART_BPS) #endif /* __INCLUDE_BOARD_DEBUG_LL_QEMU_MALTA_H__ */ diff --git a/arch/mips/configs/gxemul-malta_defconfig b/arch/mips/configs/gxemul-malta_defconfig new file mode 100644 index 0000000000..2352d38145 --- /dev/null +++ b/arch/mips/configs/gxemul-malta_defconfig @@ -0,0 +1,57 @@ +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="qemu-malta" +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R1=y +CONFIG_PBL_IMAGE=y +CONFIG_STACK_SIZE=0x7000 +CONFIG_EXPERIMENTAL=y +CONFIG_BAUDRATE=38400 +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PARTITION=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +CONFIG_POLLER=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_GETOPT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_LOGIN=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +# CONFIG_SPI is not set +CONFIG_FS_CRAMFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/mips/configs/qemu-malta_defconfig b/arch/mips/configs/qemu-malta_defconfig index a5af258b19..62b5e76f45 100644 --- a/arch/mips/configs/qemu-malta_defconfig +++ b/arch/mips/configs/qemu-malta_defconfig @@ -2,8 +2,8 @@ CONFIG_BUILTIN_DTB=y CONFIG_BUILTIN_DTB_NAME="qemu-malta" CONFIG_PBL_IMAGE=y CONFIG_STACK_SIZE=0x7000 -CONFIG_BROKEN=y CONFIG_EXPERIMENTAL=y +CONFIG_BAUDRATE=38400 CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y @@ -38,9 +38,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_EDIT=y +CONFIG_CMD_LOGIN=y CONFIG_CMD_MENU=y CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_LOGIN=y CONFIG_CMD_PASSWD=y CONFIG_CMD_READLINE=y CONFIG_CMD_TIMEOUT=y diff --git a/arch/openrisc/cpu/barebox.lds.S b/arch/openrisc/cpu/barebox.lds.S index dbecdbfbfc..9c353f30f1 100644 --- a/arch/openrisc/cpu/barebox.lds.S +++ b/arch/openrisc/cpu/barebox.lds.S @@ -16,7 +16,7 @@ #include <config.h> #include <asm-generic/barebox.lds.h> -OUTPUT_FORMAT("elf32-or32", "elf32-or32", "elf32-or32") +OUTPUT_FORMAT("elf32-or1k", "elf32-or1k", "elf32-or1k") __DYNAMIC = 0; MEMORY diff --git a/arch/ppc/boards/pcm030/env/init/mtdparts-nor b/arch/ppc/boards/pcm030/env/init/mtdparts-nor new file mode 100644 index 0000000000..e900a3b223 --- /dev/null +++ b/arch/ppc/boards/pcm030/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="512k(nor0.bareboxlow),4M(nor0.kernel),512k(nor0.oftree),26M(nor0.root),512k(nor0.barebox),512k(nor0.bareboxenv)" +kernelname="physmap-flash.0" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/ppc/boards/pcm030/env/nv/linux.bootargs.base b/arch/ppc/boards/pcm030/env/nv/linux.bootargs.base new file mode 100644 index 0000000000..31ce0e71eb --- /dev/null +++ b/arch/ppc/boards/pcm030/env/nv/linux.bootargs.base @@ -0,0 +1 @@ +console=ttyPSC0,115200 diff --git a/arch/ppc/configs/pcm030_defconfig b/arch/ppc/configs/pcm030_defconfig index 204f946f1a..7b84e2f3b6 100644 --- a/arch/ppc/configs/pcm030_defconfig +++ b/arch/ppc/configs/pcm030_defconfig @@ -1,42 +1,42 @@ CONFIG_TEXT_BASE=0x3e00000 CONFIG_MALLOC_SIZE=0x1000000 -CONFIG_LONGHELP=y -CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_PARTITION=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/ppc/boards/pcm030/env" +CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y -CONFIG_CMD_FLASH=y +CONFIG_CMD_MEMINFO=y CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_RESET=y CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y CONFIG_CMD_UNCOMPRESS=y -CONFIG_NET=y +CONFIG_CMD_SLEEP=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y -CONFIG_ARCH_MPC5XXX=y -CONFIG_MACH_PHYCORE_MPC5200B_TINY=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y CONFIG_DRIVER_NET_MPC5200=y CONFIG_MTD=y CONFIG_DRIVER_CFI=y CONFIG_CFI_BUFFER_WRITE=y +CONFIG_FS_TFTP=y CONFIG_ZLIB=y diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 707fca3dc3..9c72673bde 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -1,5 +1,6 @@ config SANDBOX bool + select OFTREE default y config ARCH_TEXT_BASE diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile index e3fb039554..a539a901fc 100644 --- a/arch/sandbox/Makefile +++ b/arch/sandbox/Makefile @@ -50,4 +50,6 @@ cmd_barebox__ = $(CC) -o $@ -Wl,-T,$(barebox-lds) \ common-y += $(BOARD) arch/sandbox/os/ +common-$(CONFIG_OFTREE) += arch/sandbox/dts/ + CLEAN_FILES += $(BOARD)/barebox.lds diff --git a/arch/sandbox/board/Makefile b/arch/sandbox/board/Makefile index 5104f5cb26..460116332d 100644 --- a/arch/sandbox/board/Makefile +++ b/arch/sandbox/board/Makefile @@ -3,5 +3,6 @@ obj-y += clock.o obj-y += hostfile.o obj-y += console.o obj-y += devices.o +obj-y += dtb.o extra-y += barebox.lds diff --git a/arch/sandbox/board/dtb.c b/arch/sandbox/board/dtb.c new file mode 100644 index 0000000000..af4a64a9c7 --- /dev/null +++ b/arch/sandbox/board/dtb.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * Copyright (c) 2015 Marc Kleine-Budde <mkl@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <init.h> +#include <of.h> + +#include <mach/linux.h> +#include <linux/err.h> + +static const void *dtb; + +int barebox_register_dtb(const void *new_dtb) +{ + if (dtb) + return -EBUSY; + + dtb = new_dtb; + + return 0; +} + +static int of_sandbox_init(void) +{ + struct device_node *root; + int ret; + + if (dtb) { + root = of_unflatten_dtb(dtb); + } else { + root = of_new_node(NULL, NULL); + + ret = of_property_write_u32(root, "#address-cells", 2); + if (ret) + return ret; + + ret = of_property_write_u32(root, "#size-cells", 1); + if (ret) + return ret; + } + + if (IS_ERR(root)) + return PTR_ERR(root); + + of_set_root_node(root); + of_fix_tree(root); + if (IS_ENABLED(CONFIG_OFDEVICE)) + of_probe(); + + return 0; +} +core_initcall(of_sandbox_init); diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c index ac29cfa47a..c1a2643bc7 100644 --- a/arch/sandbox/board/hostfile.c +++ b/arch/sandbox/board/hostfile.c @@ -23,18 +23,22 @@ #include <mach/linux.h> #include <init.h> #include <errno.h> +#include <linux/err.h> #include <mach/hostfile.h> #include <xfuncs.h> +#include <linux/err.h> + struct hf_priv { struct cdev cdev; - struct hf_platform_data *pdata; + const char *filename; + int fd; }; static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, loff_t offset, ulong flags) { - struct hf_platform_data *hf = cdev->priv; - int fd = hf->fd; + struct hf_priv *priv= cdev->priv; + int fd = priv->fd; if (linux_lseek(fd, offset) != offset) return -EINVAL; @@ -44,8 +48,8 @@ static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, loff_t offset static ssize_t hf_write(struct cdev *cdev, const void *buf, size_t count, loff_t offset, ulong flags) { - struct hf_platform_data *hf = cdev->priv; - int fd = hf->fd; + struct hf_priv *priv = cdev->priv; + int fd = priv->fd; if (linux_lseek(fd, offset) != offset) return -EINVAL; @@ -55,9 +59,9 @@ static ssize_t hf_write(struct cdev *cdev, const void *buf, size_t count, loff_t static void hf_info(struct device_d *dev) { - struct hf_platform_data *hf = dev->platform_data; + struct hf_priv *priv = dev->priv; - printf("file: %s\n", hf->filename); + printf("file: %s\n", priv->filename); } static struct file_operations hf_fops = { @@ -68,48 +72,87 @@ static struct file_operations hf_fops = { static int hf_probe(struct device_d *dev) { - struct hf_platform_data *hf = dev->platform_data; struct hf_priv *priv = xzalloc(sizeof(*priv)); + struct resource *res; + int err; + + res = dev_get_resource(dev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) + return PTR_ERR(res); + + priv->cdev.size = resource_size(res); - priv->pdata = hf; + if (!dev->device_node) + return -ENODEV; - priv->cdev.name = hf->name; - priv->cdev.size = hf->size; + err = of_property_read_u32(dev->device_node, "barebox,fd", &priv->fd); + if (err) + return err; + + err = of_property_read_string(dev->device_node, "barebox,filename", + &priv->filename); + if (err) + return err; + + priv->cdev.name = dev->device_node->name; + priv->cdev.dev = dev; priv->cdev.ops = &hf_fops; - priv->cdev.priv = hf; + priv->cdev.priv = priv; dev->info = hf_info; + dev->priv = priv; -#ifdef CONFIG_FS_DEVFS - devfs_create(&priv->cdev); -#endif - - return 0; + return devfs_create(&priv->cdev); } +static __maybe_unused struct of_device_id hostfile_dt_ids[] = { + { + .compatible = "barebox,hostfile", + }, { + /* sentinel */ + } +}; + static struct driver_d hf_drv = { .name = "hostfile", + .of_compatible = DRV_OF_COMPAT(hostfile_dt_ids), .probe = hf_probe, }; -device_platform_driver(hf_drv); +coredevice_platform_driver(hf_drv); -int barebox_register_filedev(struct hf_platform_data *hf) +static int of_hostfile_fixup(struct device_node *root, void *ctx) { - struct device_d *dev; - struct resource *res; - - dev = xzalloc(sizeof(*dev)); - strcpy(dev->name, "hostfile"); - dev->id = DEVICE_ID_DYNAMIC; - dev->platform_data = hf; - - res = xzalloc(sizeof(struct resource)); - res[0].start = hf->base; - res[0].end = hf->base + hf->size - 1; - res[0].flags = IORESOURCE_MEM; - - dev->resource = res; - dev->num_resources = 1; + struct hf_info *hf = ctx; + struct device_node *node; + uint32_t reg[] = { + hf->base >> 32, + hf->base, + hf->size + }; + int ret; + + node = of_new_node(root, hf->devname); + + ret = of_set_property(node, "compatible", hostfile_dt_ids->compatible, + strlen(hostfile_dt_ids->compatible) + 1, 1); + if (ret) + return ret; + + ret = of_property_write_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); + if (ret) + return ret; + + ret = of_property_write_u32(node, "barebox,fd", hf->fd); + if (ret) + return ret; + + ret = of_set_property(node, "barebox,filename", hf->filename, + strlen(hf->filename) + 1, 1); + + return ret; +} - return sandbox_add_device(dev); +int barebox_register_filedev(struct hf_info *hf) +{ + return of_register_fixup(of_hostfile_fixup, hf); } diff --git a/arch/sandbox/configs/sandbox_defconfig b/arch/sandbox/configs/sandbox_defconfig index 7ce2569501..ec045f7c0b 100644 --- a/arch/sandbox/configs/sandbox_defconfig +++ b/arch/sandbox/configs/sandbox_defconfig @@ -5,25 +5,36 @@ CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/sandbox/board/env" CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TFTP=y +CONFIG_LONGHELP=y CONFIG_CMD_MEMINFO=y -CONFIG_CMD_CRC=y -CONFIG_CMD_FLASH=y # CONFIG_CMD_BOOTM is not set -CONFIG_CMD_RESET=y CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_RESET=y CONFIG_CMD_PARTITION=y -CONFIG_NET=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_SLEEP=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_2048=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_DISPLAY_TIMINGS=y +CONFIG_CMD_OFTREE=y +CONFIG_NET=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_NET_TAP=y # CONFIG_SPI is not set +# CONFIG_PINCTRL is not set CONFIG_FS_CRAMFS=y CONFIG_FS_TFTP=y diff --git a/arch/sandbox/dts/.gitignore b/arch/sandbox/dts/.gitignore new file mode 100644 index 0000000000..077903c50a --- /dev/null +++ b/arch/sandbox/dts/.gitignore @@ -0,0 +1 @@ +*dtb* diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile new file mode 100644 index 0000000000..6f68388578 --- /dev/null +++ b/arch/sandbox/dts/Makefile @@ -0,0 +1,11 @@ +ifeq ($(CONFIG_OFTREE),y) +dtb-y += \ + sandbox.dtb +endif + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts new file mode 100644 index 0000000000..2595aa13fa --- /dev/null +++ b/arch/sandbox/dts/sandbox.dts @@ -0,0 +1,7 @@ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + +}; diff --git a/arch/sandbox/dts/skeleton.dtsi b/arch/sandbox/dts/skeleton.dtsi new file mode 100644 index 0000000000..38ead821bb --- /dev/null +++ b/arch/sandbox/dts/skeleton.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0>; }; +}; diff --git a/arch/sandbox/mach-sandbox/include/mach/hostfile.h b/arch/sandbox/mach-sandbox/include/mach/hostfile.h index 7c4e67cf68..627fe28e76 100644 --- a/arch/sandbox/mach-sandbox/include/mach/hostfile.h +++ b/arch/sandbox/mach-sandbox/include/mach/hostfile.h @@ -1,15 +1,14 @@ #ifndef __ASM_ARCH_HOSTFILE_H #define __ASM_ARCH_HOSTFILE_H -struct hf_platform_data { +struct hf_info { int fd; - size_t size; unsigned long base; - char *filename; - char *name; + size_t size; + const char *devname; + const char *filename; }; -int barebox_register_filedev(struct hf_platform_data *hf); +int barebox_register_filedev(struct hf_info *hf); #endif /* __ASM_ARCH_HOSTFILE_H */ - diff --git a/arch/sandbox/mach-sandbox/include/mach/linux.h b/arch/sandbox/mach-sandbox/include/mach/linux.h index 98f9067046..990173e10b 100644 --- a/arch/sandbox/mach-sandbox/include/mach/linux.h +++ b/arch/sandbox/mach-sandbox/include/mach/linux.h @@ -20,6 +20,8 @@ int linux_execve(const char * filename, char *const argv[], char *const envp[]); int barebox_register_console(char *name_template, int stdinfd, int stdoutfd); +int barebox_register_dtb(const void *dtb); + struct linux_console_data { int stdinfd; int stdoutfd; diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c index 0854fb5d80..d627391890 100644 --- a/arch/sandbox/os/common.c +++ b/arch/sandbox/os/common.c @@ -206,31 +206,41 @@ int linux_execve(const char * filename, char *const argv[], char *const envp[]) extern void start_barebox(void); extern void mem_malloc_init(void *start, void *end); -static int add_image(char *str, char *name) +static int add_image(char *str, char *devname_template, int *devname_number) { - char *file; - int readonly = 0, map = 1; + struct hf_info *hf = malloc(sizeof(struct hf_info)); + char *filename, *devname; + char tmp[16]; + int readonly = 0; struct stat s; char *opt; int fd, ret; - struct hf_platform_data *hf = malloc(sizeof(struct hf_platform_data)); if (!hf) return -1; - file = strtok(str, ","); + filename = strtok(str, ","); while ((opt = strtok(NULL, ","))) { if (!strcmp(opt, "ro")) readonly = 1; - if (!strcmp(opt, "map")) - map = 1; } - printf("add file %s(%s)\n", file, readonly ? "ro" : ""); + /* parses: "devname=filename" */ + devname = strtok(filename, "="); + filename = strtok(NULL, "="); + if (!filename) { + filename = devname; + snprintf(tmp, sizeof(tmp), + devname_template, (*devname_number)++); + devname = strdup(tmp); + } + + printf("add %s backed by file %s%s\n", devname, + filename, readonly ? "(ro)" : ""); - fd = open(file, readonly ? O_RDONLY : O_RDWR); + fd = open(filename, readonly ? O_RDONLY : O_RDWR); hf->fd = fd; - hf->filename = file; + hf->filename = filename; if (fd < 0) { perror("open"); @@ -243,15 +253,13 @@ static int add_image(char *str, char *name) } hf->size = s.st_size; - hf->name = strdup(name); - - if (map) { - hf->base = (unsigned long)mmap(NULL, hf->size, - PROT_READ | (readonly ? 0 : PROT_WRITE), - MAP_SHARED, fd, 0); - if ((void *)hf->base == MAP_FAILED) - printf("warning: mmapping %s failed\n", file); - } + hf->devname = strdup(devname); + + hf->base = (unsigned long)mmap(NULL, hf->size, + PROT_READ | (readonly ? 0 : PROT_WRITE), + MAP_SHARED, fd, 0); + if ((void *)hf->base == MAP_FAILED) + printf("warning: mmapping %s failed\n", filename); ret = barebox_register_filedev(hf); if (ret) @@ -265,6 +273,42 @@ err_out: return -1; } +static int add_dtb(const char *file) +{ + struct stat s; + void *dtb = NULL; + int fd; + + fd = open(file, O_RDONLY); + if (fd < 0) { + perror("open"); + goto err_out; + } + + if (fstat(fd, &s)) { + perror("fstat"); + goto err_out; + } + + dtb = mmap(NULL, s.st_size, PROT_READ, MAP_SHARED, fd, 0); + if (dtb == MAP_FAILED) { + perror("mmap"); + goto err_out; + } + + if (barebox_register_dtb(dtb)) + goto err_out; + + return 0; + + err_out: + if (dtb) + munmap(dtb, s.st_size); + if (fd > 0) + close(fd); + return -1; +} + static void print_usage(const char*); static struct option long_options[] = { @@ -272,6 +316,7 @@ static struct option long_options[] = { {"malloc", 1, 0, 'm'}, {"image", 1, 0, 'i'}, {"env", 1, 0, 'e'}, + {"dtb", 1, 0, 'd'}, {"stdout", 1, 0, 'O'}, {"stdin", 1, 0, 'I'}, {"xres", 1, 0, 'x'}, @@ -279,14 +324,13 @@ static struct option long_options[] = { {0, 0, 0, 0}, }; -static const char optstring[] = "hm:i:e:O:I:x:y:"; +static const char optstring[] = "hm:i:e:d:O:I:x:y:"; int main(int argc, char *argv[]) { void *ram; int opt, ret, fd; int malloc_size = CONFIG_MALLOC_SIZE; - char str[6]; int fdno = 0, envno = 0, option_index = 0; while (1) { @@ -308,6 +352,13 @@ int main(int argc, char *argv[]) break; case 'e': break; + case 'd': + ret = add_dtb(optarg); + if (ret) { + printf("Failed to load dtb: '%s'\n", optarg); + exit(1); + } + break; case 'O': fd = open(optarg, O_WRONLY); if (fd < 0) { @@ -361,18 +412,14 @@ int main(int argc, char *argv[]) switch (opt) { case 'i': - sprintf(str, "fd%d", fdno); - ret = add_image(optarg, str); + ret = add_image(optarg, "fd%d", &fdno); if (ret) exit(1); - fdno++; break; case 'e': - sprintf(str, "env%d", envno); - ret = add_image(optarg, str); + ret = add_image(optarg, "env%d", &envno); if (ret) exit(1); - envno++; break; default: break; @@ -399,15 +446,19 @@ static void print_usage(const char *prgname) "Usage: %s [OPTIONS]\n" "Start barebox.\n\n" "Options:\n\n" -" -m, --malloc=<size> Start sandbox with a specified malloc-space size in bytes.\n" +" -m, --malloc=<size> Start sandbox with a specified malloc-space size in bytes.\n" " -i, --image=<file> Map an image file to barebox. This option can be given\n" " multiple times. The files will show up as\n" " /dev/fd0 ... /dev/fdx under barebox.\n" +" -i, --image=<dev>=<file>\n" +" Same as above, the files will show up as\n" +" /dev/<dev>\n" " -e, --env=<file> Map a file with an environment to barebox. With this \n" " option, files are mapped as /dev/env0 ... /dev/envx\n" " and thus are used as the default environment.\n" " An empty file generated with dd will do to get started\n" " with an empty environment.\n" +" -d, --dtb=<file> Map a device tree binary blob (dtb) into barebox.\n" " -O, --stdout=<file> Register a file as a console capable of doing stdout.\n" " <file> can be a regular file or a FIFO.\n" " -I, --stdin=<file> Register a file as a console capable of doing stdin.\n" |