diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boards/beaglebone/lowlevel.c | 2 | ||||
-rw-r--r-- | arch/arm/boards/phytec-som-am335x/ram-timings.h | 11 | ||||
-rw-r--r-- | arch/arm/mach-omap/am33xx_generic.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-omap/include/mach/am33xx-silicon.h | 2 |
4 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c index 100f64fdd9..a56b4b6240 100644 --- a/arch/arm/boards/beaglebone/lowlevel.c +++ b/arch/arm/boards/beaglebone/lowlevel.c @@ -41,6 +41,7 @@ static const struct am33xx_emif_regs ddr2_regs = { .emif_tim1 = 0x0666B3C9, .emif_tim2 = 0x243631CA, .emif_tim3 = 0x0000033F, + .ocp_config = 0x00141414, .sdram_config = 0x41805332, .sdram_config2 = 0x41805332, .sdram_ref_ctrl = 0x0000081A, @@ -97,6 +98,7 @@ static const struct am33xx_emif_regs ddr3_regs = { .emif_tim1 = 0x0AAAD4DB, .emif_tim2 = 0x266B7FDA, .emif_tim3 = 0x501F867F, + .ocp_config = 0x00141414, .zq_config = 0x50074BE4, .sdram_config = 0x61C05332, .sdram_config2 = 0x0, diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h index 9576d265e5..4ea654db12 100644 --- a/arch/arm/boards/phytec-som-am335x/ram-timings.h +++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h @@ -45,6 +45,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAD4DB, .emif_tim2 = 0x26437FDA, .emif_tim3 = 0x501F83FF, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C052B2, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30, @@ -66,6 +67,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAE4DB, .emif_tim2 = 0x266B7FDA, .emif_tim3 = 0x501F867F, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C05332, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30, @@ -87,6 +89,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAD4DB, .emif_tim2 = 0x26437FDA, .emif_tim3 = 0x501F83FF, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C052B2, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30, @@ -106,6 +109,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAE4DB, .emif_tim2 = 0x262F7FDA, .emif_tim3 = 0x501F82BF, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C05232, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30, @@ -125,6 +129,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAE4DB, .emif_tim2 = 0x266B7FDA, .emif_tim3 = 0x501F867F, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C05332, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30 @@ -144,6 +149,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAE4DB, .emif_tim2 = 0x266B7FDA, .emif_tim3 = 0x501F867F, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C053B2, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30 @@ -163,6 +169,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAE4DB, .emif_tim2 = 0x268F7FDA, .emif_tim3 = 0x501F88BF, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C053B2, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30 @@ -182,6 +189,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAD4DB, .emif_tim2 = 0x26437FDA, .emif_tim3 = 0x501F83FF, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C052B2, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30, @@ -203,6 +211,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAD4DB, .emif_tim2 = 0x266B7FDA, .emif_tim3 = 0x501F867F, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C05332, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30, @@ -222,6 +231,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAD4DB, .emif_tim2 = 0x26437FDA, .emif_tim3 = 0x501F83FF, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C052B2, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30, @@ -241,6 +251,7 @@ struct am335x_sdram_timings physom_timings[] = { .emif_tim1 = 0x0AAAD4DB, .emif_tim2 = 0x268F7FDA, .emif_tim3 = 0x501F88BF, + .ocp_config = 0x003d3d3d, .sdram_config = 0x61C053B2, .zq_config = 0x50074BE4, .sdram_ref_ctrl = 0x00000C30, diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 5eead5c589..513746248e 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -341,6 +341,9 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs) writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); + if (regs->ocp_config) + writel(regs->ocp_config, AM33XX_EMIF4_0_REG(OCP_CONFIG)); + if (regs->zq_config) { /* * A value of 0x2800 for the REF CTRL will give us diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index 10595d5ee7..0729369255 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -114,6 +114,7 @@ #define EMIF4_SDRAM_TIM_3_SHADOW 0x2C #define EMIF0_SDRAM_MGMT_CTRL 0x38 #define EMIF0_SDRAM_MGMT_CTRL_SHD 0x3C +#define EMIF4_OCP_CONFIG 0x54 #define EMIF4_ZQ_CONFIG 0xC8 #define EMIF4_DDR_PHY_CTRL_1 0xE4 #define EMIF4_DDR_PHY_CTRL_1_SHADOW 0xE8 @@ -217,6 +218,7 @@ struct am33xx_emif_regs { u32 emif_tim1; u32 emif_tim2; u32 emif_tim3; + u32 ocp_config; u32 sdram_config; u32 sdram_config2; u32 zq_config; |