diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-imx/Kconfig | 4 | ||||
-rw-r--r-- | arch/arm/mach-imx/imx6.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-imx/include/mach/imx6.h | 19 |
3 files changed, 25 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 4dc109828c..c1ed5b2f2a 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -148,6 +148,10 @@ config ARCH_IMX6 select COMMON_CLK_OF_PROVIDER select HW_HAS_PCI +config ARCH_IMX6SL + bool + select ARCH_IMX6 + config ARCH_IMX6SX bool select ARCH_IMX6 diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index b2979b049e..44a8dbefd0 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -151,6 +151,9 @@ int imx6_init(void) case IMX6_CPUTYPE_IMX6S: cputypestr = "i.MX6 Solo"; break; + case IMX6_CPUTYPE_IMX6SL: + cputypestr = "i.MX6 SoloLite"; + break; case IMX6_CPUTYPE_IMX6SX: cputypestr = "i.MX6 SoloX"; break; diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h index e201721094..327676bc69 100644 --- a/arch/arm/mach-imx/include/mach/imx6.h +++ b/arch/arm/mach-imx/include/mach/imx6.h @@ -9,7 +9,9 @@ void imx6_init_lowlevel(void); #define IMX6_ANATOP_SI_REV 0x260 +#define IMX6SL_ANATOP_SI_REV 0x280 +#define IMX6_CPUTYPE_IMX6SL 0x160 #define IMX6_CPUTYPE_IMX6S 0x161 #define IMX6_CPUTYPE_IMX6DL 0x261 #define IMX6_CPUTYPE_IMX6SX 0x462 @@ -36,6 +38,16 @@ static inline int __imx6_cpu_type(void) val = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV); val = (val >> 16) & 0xff; + /* non-MX6-standard SI_REV reg offset for MX6SL */ + if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && + val < (IMX6_CPUTYPE_IMX6S & 0xff)) { + uint32_t tmp; + tmp = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV); + tmp = (tmp >> 16) & 0xff; + if ((IMX6_CPUTYPE_IMX6SL & 0xff) == tmp) + /* intentionally skip scu_get_core_count() for MX6SL */ + return IMX6_CPUTYPE_IMX6SL; + } val |= scu_get_core_count() << 8; @@ -68,14 +80,19 @@ DEFINE_MX6_CPU_TYPE(mx6dl, IMX6_CPUTYPE_IMX6DL); DEFINE_MX6_CPU_TYPE(mx6q, IMX6_CPUTYPE_IMX6Q); DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D); DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX); +DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL); DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL); static inline int __imx6_cpu_revision(void) { uint32_t rev; + uint32_t si_rev_offset = IMX6_ANATOP_SI_REV; + + if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && cpu_mx6_is_mx6sl()) + si_rev_offset = IMX6SL_ANATOP_SI_REV; - rev = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV); + rev = readl(MX6_ANATOP_BASE_ADDR + si_rev_offset); switch (rev & 0xfff) { case 0x00: |