diff options
Diffstat (limited to 'arch')
147 files changed, 4630 insertions, 771 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8465d4a7f7..9f34e1089b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2,6 +2,8 @@ config ARM bool select HAS_KALLSYMS select HAS_MODULES + select HAS_DMA + select HAS_CACHE select HAVE_CONFIGURABLE_TEXT_BASE select HAVE_PBL_IMAGE select HAVE_IMAGE_COMPRESSION @@ -60,6 +62,15 @@ config ARCH_DAVINCI select HAS_DEBUG_LL select GPIOLIB +config ARCH_DIGIC + bool "Canon DIGIC-based cameras" + select CPU_ARM946E + select HAS_DEBUG_LL + select CLOCKSOURCE_DIGIC + select GPIOLIB + help + Support for Canon's digital cameras that use the DIGIC4 chip. + config ARCH_EP93XX bool "Cirrus Logic EP93xx" select CPU_ARM920T @@ -93,6 +104,7 @@ config ARCH_MVEBU select GPIOLIB select HAS_DEBUG_LL select HAVE_PBL_MULTI_IMAGES + select HW_HAS_PCI select MVEBU_MBUS select OFTREE select OF_ADDRESS_PCI @@ -218,6 +230,7 @@ source arch/arm/mach-at91/Kconfig source arch/arm/mach-bcm2835/Kconfig source arch/arm/mach-clps711x/Kconfig source arch/arm/mach-davinci/Kconfig +source arch/arm/mach-digic/Kconfig source arch/arm/mach-ep93xx/Kconfig source arch/arm/mach-highbank/Kconfig source arch/arm/mach-imx/Kconfig diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 983f7f57cd..337aef175b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -55,6 +55,7 @@ machine-$(CONFIG_ARCH_AT91) := at91 machine-$(CONFIG_ARCH_BCM2835) := bcm2835 machine-$(CONFIG_ARCH_CLPS711X) := clps711x machine-$(CONFIG_ARCH_DAVINCI) := davinci +machine-$(CONFIG_ARCH_DIGIC) := digic machine-$(CONFIG_ARCH_EP93XX) := ep93xx machine-$(CONFIG_ARCH_HIGHBANK) := highbank machine-$(CONFIG_ARCH_IMX) := imx @@ -184,6 +185,16 @@ ifeq ($(machine-y),zynq) KBUILD_IMAGE := barebox.zynq endif +quiet_cmd_canon_a1100_image = DD $@ + cmd_canon_a1100_image = scripts/canon-a1100-image $< $@ || \ + echo "WARNING: Couldn't create Canon A1100 image due to previous errors." +barebox.canon-a1100.bin: $(KBUILD_BINARY) FORCE + $(call if_changed,canon_a1100_image) + +ifeq ($(CONFIG_MACH_CANON_A1100),y) +KBUILD_IMAGE := barebox.canon-a1100.bin +endif + KWBIMAGE_OPTS = \ -c -i $(srctree)/$(BOARD)/kwbimage.cfg -d $(TEXT_BASE) -e $(TEXT_BASE) diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index d200512758..c60da81261 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MACH_AT91SAM9N12EK) += at91sam9n12ek/ obj-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek/ obj-$(CONFIG_MACH_BEAGLE) += beagle/ obj-$(CONFIG_MACH_BEAGLEBONE) += beaglebone/ +obj-$(CONFIG_MACH_CANON_A1100) += canon-a1100/ obj-$(CONFIG_MACH_NITROGEN6X) += boundarydevices-nitrogen6x/ obj-$(CONFIG_MACH_CCMX51) += ccxmx51/ obj-$(CONFIG_MACH_CFA10036) += crystalfontz-cfa10036/ @@ -28,6 +29,7 @@ obj-$(CONFIG_MACH_EDB9307) += edb93xx/ obj-$(CONFIG_MACH_EDB9315A) += edb93xx/ obj-$(CONFIG_MACH_EDB9315) += edb93xx/ obj-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += efika-mx-smartbook/ +obj-$(CONFIG_MACH_EMBEDSKY_E9) += embedsky-e9/ obj-$(CONFIG_MACH_EMBEST_RIOTBOARD) += embest-riotboard/ obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += eukrea_cpuimx25/ obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27/ diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.c b/arch/arm/boards/at91sam9m10ihd/hw_version.c index 8e729013c7..96fb02d801 100644 --- a/arch/arm/boards/at91sam9m10ihd/hw_version.c +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.c @@ -18,6 +18,7 @@ #include <fs.h> #include <fcntl.h> #include <libbb.h> +#include <libfile.h> #include <asm/armlinux.h> #include <of.h> diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.c b/arch/arm/boards/at91sam9x5ek/hw_version.c index 2da4e5ed8c..37eb1f80c5 100644 --- a/arch/arm/boards/at91sam9x5ek/hw_version.c +++ b/arch/arm/boards/at91sam9x5ek/hw_version.c @@ -18,6 +18,7 @@ #include <fs.h> #include <fcntl.h> #include <libbb.h> +#include <libfile.h> #include <asm/armlinux.h> #include <of.h> diff --git a/arch/arm/boards/canon-a1100/Makefile b/arch/arm/boards/canon-a1100/Makefile new file mode 100644 index 0000000000..b08c4a93ca --- /dev/null +++ b/arch/arm/boards/canon-a1100/Makefile @@ -0,0 +1 @@ +lwl-y += lowlevel.o diff --git a/arch/arm/boards/canon-a1100/lowlevel.c b/arch/arm/boards/canon-a1100/lowlevel.c new file mode 100644 index 0000000000..bbae825661 --- /dev/null +++ b/arch/arm/boards/canon-a1100/lowlevel.c @@ -0,0 +1,23 @@ +#include <common.h> +#include <sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> + +void __naked barebox_arm_reset_vector(void) +{ + arm_cpu_lowlevel_init(); + + /* FIXME: can we determine RAM size using CP15 register? + * + * see http://chdk.setepontos.com/index.php?topic=5980.90 + * + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363e/Bgbcdeca.html + * 4.2.19. c6, MPU memory region programming registers + * + * But the 'cpuinfo' command says that the Protection + * unit is disabled. + * The Control Register value (mrc p15, 0, %0, c0, c1, 4) + * is 0x00051078. + */ + barebox_arm_entry(0x0, SZ_64M, 0); +} diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c index e28dd49fad..c94cb355e2 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c +++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c @@ -21,6 +21,7 @@ #include <fs.h> #include <globalvar.h> #include <libbb.h> +#include <libfile.h> #include <magicvar.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/embedsky-e9/Makefile b/arch/arm/boards/embedsky-e9/Makefile new file mode 100644 index 0000000000..db2dba7769 --- /dev/null +++ b/arch/arm/boards/embedsky-e9/Makefile @@ -0,0 +1,4 @@ +obj-y += board.o flash-header-e9.dcd.o +extra-y += flash-header-e9.dcd.S flash-header-e9.dcd +lwl-y += lowlevel.o +bbenv-y += defaultenv-e9 diff --git a/arch/arm/boards/embedsky-e9/board.c b/arch/arm/boards/embedsky-e9/board.c new file mode 100644 index 0000000000..55b4320219 --- /dev/null +++ b/arch/arm/boards/embedsky-e9/board.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2014 Andrey Panov <rockford@yandex.ru> + * + * based on arch/arm/boards/freescale-mx6-sabresd/board.c + * Copyright (C) 2013 Hubert Feurstein <h.feurstein@gmail.com> + * + * based on arch/arm/boards/freescale-mx6-sabrelite/board.c + * Copyright (C) 2012 Steffen Trumtrar, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <environment.h> +#include <mach/imx6-regs.h> +#include <fec.h> +#include <gpio.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <linux/phy.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <mach/generic.h> +#include <sizes.h> +#include <net.h> +#include <mach/imx6.h> +#include <mach/devices-imx6.h> +#include <mach/iomux-mx6.h> +#include <spi/spi.h> +#include <mach/spi.h> +#include <mach/usb.h> +#include <envfs.h> + +#define PHY_ID_RTL8211E 0x001cc915 +#define PHY_ID_MASK 0xffffffff + +/* + * This should reset a PHY. Taken from E9 U-Boot/Linux source. + */ +static int rtl8211e_phy_fixup(struct phy_device *dev) +{ + phy_write(dev, 0x00, 0x3140); + mdelay(10); + phy_write(dev, 0x00, 0x3340); + mdelay(10); + + return 0; +} + +static int e9_devices_init(void) +{ + if (!of_machine_is_compatible("embedsky,e9")) + return 0; + + armlinux_set_architecture(3980); + barebox_set_hostname("e9"); + defaultenv_append_directory(defaultenv_e9); + + return 0; +} +device_initcall(e9_devices_init); + +static int e9_coredevices_init(void) +{ + if (!of_machine_is_compatible("embedsky,e9")) + return 0; + + phy_register_fixup_for_uid(PHY_ID_RTL8211E, PHY_ID_MASK, + rtl8211e_phy_fixup); + + return 0; +} +/* + * Do this before the fec initializes but after our + * gpios are available. + */ +coredevice_initcall(e9_coredevices_init); diff --git a/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc1 b/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc1 new file mode 100644 index 0000000000..0177e6c6b8 --- /dev/null +++ b/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc1 @@ -0,0 +1,6 @@ +#!/bin/sh + +mount /dev/mmc1.0 + +global.bootm.image=/mnt/mmc1.0/zImage +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait" diff --git a/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc3 b/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc3 new file mode 100644 index 0000000000..374eb1cfe6 --- /dev/null +++ b/arch/arm/boards/embedsky-e9/defaultenv-e9/boot/mmc3 @@ -0,0 +1,6 @@ +#!/bin/sh + +mount /dev/mmc3.0 + +global.bootm.image=/mnt/mmc3.0/boot/zImage +global.linux.bootargs.dyn.root="root=/dev/mmcblk1p1 rootwait" diff --git a/arch/arm/boards/embedsky-e9/defaultenv-e9/config-board b/arch/arm/boards/embedsky-e9/defaultenv-e9/config-board new file mode 100644 index 0000000000..6cba769921 --- /dev/null +++ b/arch/arm/boards/embedsky-e9/defaultenv-e9/config-board @@ -0,0 +1,7 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=e9 +global.boot.default=$bootsource$bootsource_instance diff --git a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg new file mode 100644 index 0000000000..52edefd77a --- /dev/null +++ b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg @@ -0,0 +1,87 @@ +loadaddr 0x27800000 +soc imx6 +dcdofs 0x400 + +wm 32 0x020e0798 0x000c0000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00000018 +wm 32 0x020e05b0 0x00000018 +wm 32 0x020e0524 0x00000018 +wm 32 0x020e051c 0x00000018 +wm 32 0x020e0518 0x00000018 +wm 32 0x020e050c 0x00000018 +wm 32 0x020e05b8 0x00000018 +wm 32 0x020e05c0 0x00000018 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000018 +wm 32 0x020e0788 0x00000018 +wm 32 0x020e0794 0x00000018 +wm 32 0x020e079c 0x00000018 +wm 32 0x020e07a0 0x00000018 +wm 32 0x020e07a4 0x00000018 +wm 32 0x020e07a8 0x00000018 +wm 32 0x020e0748 0x00000018 +wm 32 0x020e05ac 0x00000018 +wm 32 0x020e05b4 0x00000018 +wm 32 0x020e0528 0x00000018 +wm 32 0x020e0520 0x00000018 +wm 32 0x020e0514 0x00000018 +wm 32 0x020e0510 0x00000018 +wm 32 0x020e05bc 0x00000018 +wm 32 0x020e05c4 0x00000018 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b080c 0x001f001f +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f +wm 32 0x021b083c 0x4333033f +wm 32 0x021b0840 0x032c031d +wm 32 0x021b483c 0x43200332 +wm 32 0x021b4840 0x031a026a +wm 32 0x021b0848 0x4d464746 +wm 32 0x021b4848 0x47453f4d +wm 32 0x021b0850 0x3e434440 +wm 32 0x021b4850 0x47384839 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x09444040 +wm 32 0x021b000c 0x8a8f7955 +wm 32 0x021b0010 0xff328f64 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b0018 0x00001740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x008f1023 +wm 32 0x021b0040 0x00000047 +wm 32 0x021b0000 0x841a0000 +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/embedsky-e9/lowlevel.c b/arch/arm/boards/embedsky-e9/lowlevel.c new file mode 100644 index 0000000000..fee1011700 --- /dev/null +++ b/arch/arm/boards/embedsky-e9/lowlevel.c @@ -0,0 +1,18 @@ +#include <common.h> +#include <sizes.h> +#include <mach/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> + +extern char __dtb_imx6q_embedsky_e9_start[]; + +ENTRY_FUNCTION(start_imx6q_embedsky_e9, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_imx6q_embedsky_e9_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_2G, fdt); +} diff --git a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c index 51b9ef8db7..7d1c1d5b2a 100644 --- a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c @@ -2,6 +2,7 @@ #include <mach/esdctl.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> +#include <image-metadata.h> extern char __dtb_imx53_qsb_start[]; diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c index 855b6924f3..ff1f04e87f 100644 --- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c @@ -15,7 +15,7 @@ #include <mach/wdt.h> #include <debug_ll.h> -static const struct am33xx_cmd_control MT41J256M16HA15EIT_1x512MB_cmd = { +static const struct am33xx_cmd_control pcm051_cmd = { .slave_ratio0 = 0x40, .dll_lock_diff0 = 0x0, .invert_clkout0 = 0x1, @@ -27,21 +27,74 @@ static const struct am33xx_cmd_control MT41J256M16HA15EIT_1x512MB_cmd = { .invert_clkout2 = 0x1, }; -static const struct am33xx_emif_regs MT41J256M16HA15EIT_1x512MB_regs = { - .emif_read_latency = 0x6, - .emif_tim1 = 0x0888A39B, - .emif_tim2 = 0x26517FDA, - .emif_tim3 = 0x501F84EF, - .sdram_config = 0x61C04B32, - .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x0000093B, +struct pcm051_sdram_timings { + struct am33xx_emif_regs regs; + struct am33xx_ddr_data data; }; -static const struct am33xx_ddr_data MT41J256M16HA15EIT_1x512MB_data = { - .rd_slave_ratio0 = 0x3B, - .wr_dqs_slave_ratio0 = 0x3B, - .fifo_we_slave_ratio0 = 0x96, - .wr_slave_ratio0 = 0x76, +enum { + MT41J128M16125IT_1x256M16, + MT41J64M1615IT_1x128M16, + MT41J256M16HA15EIT_1x512M16, +}; + +struct pcm051_sdram_timings timings[] = { + /* 1x256M16 */ + [MT41J128M16125IT_1x256M16] = { + .regs = { + .emif_read_latency = 0x6, + .emif_tim1 = 0x0888A39B, + .emif_tim2 = 0x26337FDA, + .emif_tim3 = 0x501F830F, + .sdram_config = 0x61C04AB2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x0000093B, + }, + .data = { + .rd_slave_ratio0 = 0x3B, + .wr_dqs_slave_ratio0 = 0x3B, + .fifo_we_slave_ratio0 = 0x97, + .wr_slave_ratio0 = 0x76, + }, + }, + + /* 1x128M16 */ + [MT41J64M1615IT_1x128M16] = { + .regs = { + .emif_read_latency = 0x6, + .emif_tim1 = 0x0888A39B, + .emif_tim2 = 0x26247FDA, + .emif_tim3 = 0x501F821F, + .sdram_config = 0x61C04A32, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x0000093B, + }, + .data = { + .rd_slave_ratio0 = 0x3A, + .wr_dqs_slave_ratio0 = 0x36, + .fifo_we_slave_ratio0 = 0xA2, + .wr_slave_ratio0 = 0x74, + }, + }, + + /* 1x512MB */ + [MT41J256M16HA15EIT_1x512M16] = { + .regs = { + .emif_read_latency = 0x6, + .emif_tim1 = 0x0888A39B, + .emif_tim2 = 0x26517FDA, + .emif_tim3 = 0x501F84EF, + .sdram_config = 0x61C04B32, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x0000093B, + }, + .data = { + .rd_slave_ratio0 = 0x3B, + .wr_dqs_slave_ratio0 = 0x3B, + .fifo_we_slave_ratio0 = 0x96, + .wr_slave_ratio0 = 0x76, + }, + }, }; extern char __dtb_am335x_phytec_phycore_start[]; @@ -55,9 +108,10 @@ extern char __dtb_am335x_phytec_phycore_start[]; * * @return void */ -static noinline void pcm051_board_init(void) +static noinline void pcm051_board_init(int sdram) { void *fdt; + struct pcm051_sdram_timings *timing = &timings[sdram]; /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets @@ -70,9 +124,9 @@ static noinline void pcm051_board_init(void) am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303); - am335x_sdram_init(0x18B, &MT41J256M16HA15EIT_1x512MB_cmd, - &MT41J256M16HA15EIT_1x512MB_regs, - &MT41J256M16HA15EIT_1x512MB_data); + am335x_sdram_init(0x18B, &pcm051_cmd, + &timing->regs, + &timing->data); am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE); am33xx_enable_uart0_pin_mux(); @@ -81,10 +135,10 @@ static noinline void pcm051_board_init(void) fdt = __dtb_am335x_phytec_phycore_start - get_runtime_offset(); - barebox_arm_entry(0x80000000, SZ_512M, fdt); + am335x_barebox_entry(fdt); } -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram, bootinfo, r1, r2) +static noinline void pcm051_board_entry(unsigned long bootinfo, int sdram) { am33xx_save_bootinfo((void *)bootinfo); @@ -97,7 +151,22 @@ ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram, bootinfo, r1, r2) relocate_to_current_adr(); setup_c(); - pcm051_board_init(); + pcm051_board_init(sdram); +} + +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x256m16, bootinfo, r1, r2) +{ + pcm051_board_entry(bootinfo, MT41J128M16125IT_1x256M16); +} + +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x128m16, bootinfo, r1, r2) +{ + pcm051_board_entry(bootinfo, MT41J64M1615IT_1x128M16); +} + +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x512m16, bootinfo, r1, r2) +{ + pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_1x512M16); } ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2) @@ -106,5 +175,5 @@ ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2) fdt = __dtb_am335x_phytec_phycore_start - get_runtime_offset(); - barebox_arm_entry(0x80000000, SZ_512M, fdt); + am335x_barebox_entry(fdt); } diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c index 55aae00954..1d08f0561a 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c @@ -16,6 +16,7 @@ #include <common.h> #include <sizes.h> #include <io.h> +#include <image-metadata.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <asm/sections.h> @@ -57,6 +58,11 @@ extern char __dtb_imx6q_phytec_pbab01_start[]; extern char __dtb_imx6dl_phytec_pbab01_start[]; extern char __dtb_imx6s_phytec_pbab01_start[]; +BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_512M, IMD_TYPE_PARAMETER, "memsize=512", 0); +BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0); +BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_2G, IMD_TYPE_PARAMETER, "memsize=2048", 0); +BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_4G, IMD_TYPE_PARAMETER, "memsize=4096", 0); + ENTRY_FUNCTION(start_phytec_pbab01_1gib, r0, r1, r2) { void *fdt; @@ -65,6 +71,8 @@ ENTRY_FUNCTION(start_phytec_pbab01_1gib, r0, r1, r2) arm_setup_stack(0x00920000 - 8); + IMD_USED(phyflex_mx6_memsize_1G); + if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); @@ -81,6 +89,8 @@ ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2) arm_setup_stack(0x00920000 - 8); + IMD_USED(phyflex_mx6_memsize_2G); + if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); @@ -97,6 +107,8 @@ ENTRY_FUNCTION(start_phytec_pbab01_4gib, r0, r1, r2) arm_setup_stack(0x00920000 - 8); + IMD_USED(phyflex_mx6_memsize_4G); + fdt = __dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); barebox_arm_entry(0x10000000, 0xEFFFFFF8, fdt); @@ -110,6 +122,8 @@ ENTRY_FUNCTION(start_phytec_pbab01dl_1gib, r0, r1, r2) arm_setup_stack(0x00920000 - 8); + IMD_USED(phyflex_mx6_memsize_1G); + fdt = __dtb_imx6dl_phytec_pbab01_start - get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_1G, fdt); @@ -123,6 +137,8 @@ ENTRY_FUNCTION(start_phytec_pbab01s_512mb, r0, r1, r2) arm_setup_stack(0x00920000 - 8); + IMD_USED(phyflex_mx6_memsize_512M); + fdt = __dtb_imx6s_phytec_pbab01_start - get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_512M, fdt); diff --git a/arch/arm/boards/sama5d3_xplained/init.c b/arch/arm/boards/sama5d3_xplained/init.c index ae18863acd..ae84209cbb 100644 --- a/arch/arm/boards/sama5d3_xplained/init.c +++ b/arch/arm/boards/sama5d3_xplained/init.c @@ -57,21 +57,30 @@ static struct atmel_nand_data nand_pdata = { }; static struct sam9_smc_config sama5d3_xplained_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 1, - .ncs_write_setup = 0, - .nwe_setup = 1, + .ncs_read_setup = 1, + .nrd_setup = 2, + .ncs_write_setup = 1, + .nwe_setup = 2, - .ncs_read_pulse = 6, - .nrd_pulse = 4, + .ncs_read_pulse = 5, + .nrd_pulse = 3, .ncs_write_pulse = 5, .nwe_pulse = 3, - .read_cycle = 6, - .write_cycle = 5, + .read_cycle = 8, + .write_cycle = 8, .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, - .tdf_cycles = 1, + .tdf_cycles = 3, + + .tclr = 3, + .tadl = 10, + .tar = 3, + .ocms = 0, + .trr = 4, + .twb = 5, + .rbnsel = 3, + .nfsel = 1 }; static void ek_add_device_nand(void) @@ -87,7 +96,7 @@ static void ek_add_device_nand(void) sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config); + sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config); at91_add_device_nand(&nand_pdata); } diff --git a/arch/arm/boards/sama5d3xek/hw_version.c b/arch/arm/boards/sama5d3xek/hw_version.c index 450eb9f8a1..c809c37742 100644 --- a/arch/arm/boards/sama5d3xek/hw_version.c +++ b/arch/arm/boards/sama5d3xek/hw_version.c @@ -18,6 +18,7 @@ #include <fs.h> #include <fcntl.h> #include <libbb.h> +#include <libfile.h> #include <asm/armlinux.h> #include <of.h> diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c index e078642242..743197fe47 100644 --- a/arch/arm/boards/sama5d3xek/init.c +++ b/arch/arm/boards/sama5d3xek/init.c @@ -72,21 +72,30 @@ static struct atmel_nand_data nand_pdata = { }; static struct sam9_smc_config cm_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 1, - .ncs_write_setup = 0, - .nwe_setup = 1, + .ncs_read_setup = 1, + .nrd_setup = 2, + .ncs_write_setup = 1, + .nwe_setup = 2, - .ncs_read_pulse = 6, - .nrd_pulse = 4, + .ncs_read_pulse = 5, + .nrd_pulse = 3, .ncs_write_pulse = 5, .nwe_pulse = 3, - .read_cycle = 6, - .write_cycle = 5, + .read_cycle = 8, + .write_cycle = 8, .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, - .tdf_cycles = 1, + .tdf_cycles = 3, + + .tclr = 3, + .tadl = 10, + .tar = 3, + .ocms = 0, + .trr = 4, + .twb = 5, + .rbnsel = 3, + .nfsel = 1 }; static void ek_add_device_nand(void) @@ -102,7 +111,7 @@ static void ek_add_device_nand(void) cm_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(0, 3, &cm_nand_smc_config); + sama5_smc_configure(0, 3, &cm_nand_smc_config); at91_add_device_nand(&nand_pdata); } diff --git a/arch/arm/boards/tqma53/lowlevel.c b/arch/arm/boards/tqma53/lowlevel.c index 0a67228008..cd87212555 100644 --- a/arch/arm/boards/tqma53/lowlevel.c +++ b/arch/arm/boards/tqma53/lowlevel.c @@ -5,6 +5,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <mach/imx5.h> +#include <image-metadata.h> extern char __dtb_imx53_mba53_start[]; @@ -34,6 +35,8 @@ static void __noreturn start_imx53_tqma53_common(void *fdt) imx53_barebox_entry(fdt); } +BAREBOX_IMD_TAG_STRING(tqma53_memsize_512M, IMD_TYPE_PARAMETER, "memsize=512", 0); + ENTRY_FUNCTION(start_imx53_mba53_512mib, r0, r1, r2) { void *fdt; @@ -42,6 +45,8 @@ ENTRY_FUNCTION(start_imx53_mba53_512mib, r0, r1, r2) arm_setup_stack(0xf8020000 - 8); + IMD_USED(tqma53_memsize_512M); + imx53_init_lowlevel_early(800); fdt = __dtb_imx53_mba53_start - get_runtime_offset(); @@ -49,6 +54,8 @@ ENTRY_FUNCTION(start_imx53_mba53_512mib, r0, r1, r2) start_imx53_tqma53_common(fdt); } +BAREBOX_IMD_TAG_STRING(tqma53_memsize_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0); + ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2) { void *fdt; @@ -57,6 +64,8 @@ ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2) arm_setup_stack(0xf8020000 - 8); + IMD_USED(tqma53_memsize_1G); + imx53_init_lowlevel_early(800); fdt = __dtb_imx53_mba53_start - get_runtime_offset(); diff --git a/arch/arm/configs/am335x_defconfig b/arch/arm/configs/am335x_defconfig index 0c92c96e45..d3feb108a1 100644 --- a/arch/arm/configs/am335x_defconfig +++ b/arch/arm/configs/am335x_defconfig @@ -1,11 +1,11 @@ CONFIG_ARCH_OMAP=y CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO=y +CONFIG_BAREBOX_UPDATE_AM33XX_NAND_XLOADSLOTS=y CONFIG_OMAP_MULTI_BOARDS=y CONFIG_MACH_BEAGLEBONE=y CONFIG_MACH_PCM051=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_BOARD_APPEND_ATAG=y -CONFIG_CMD_ARM_MMUINFO=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y CONFIG_MMU=y @@ -15,7 +15,6 @@ CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y CONFIG_RELOCATABLE=y CONFIG_PROMPT="barebox> " -CONFIG_LONGHELP=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y @@ -25,61 +24,63 @@ CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_READF=y -CONFIG_CMD_LET=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENUTREE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_LN=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_MEMINFO=y +CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y -CONFIG_CMD_MM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_ARM_MMUINFO=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_BOOTZ=y # CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y +CONFIG_CMD_BOOTZ=y CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y CONFIG_CMD_PARTITION=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENUTREE=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MM=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y CONFIG_CMD_LED=y +CONFIG_CMD_SPI=y CONFIG_CMD_LED_TRIGGER=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_DETECT=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y CONFIG_NET=y -CONFIG_CMD_DHCP=y CONFIG_NET_NFS=y -CONFIG_CMD_PING=y CONFIG_NET_NETCONSOLE=y CONFIG_NET_RESOLV=y CONFIG_OFDEVICE=y diff --git a/arch/arm/configs/canon-a1100_defconfig b/arch/arm/configs/canon-a1100_defconfig new file mode 100644 index 0000000000..5c1e195a2d --- /dev/null +++ b/arch/arm/configs/canon-a1100_defconfig @@ -0,0 +1,56 @@ +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="canon-a1100" +CONFIG_ARCH_DIGIC=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_IMAGE_COMPRESSION_LZ4=y +CONFIG_TEXT_BASE=0x00300000 +CONFIG_MALLOC_SIZE=0x200000 +CONFIG_PROMPT="canon-a1100 > " +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +CONFIG_DEBUG_LL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_GO=y +CONFIG_CMD_LOADY=y +# CONFIG_CMD_MOUNT is not set +# CONFIG_CMD_UMOUNT is not set +CONFIG_CMD_EXPORT=y +CONFIG_CMD_GLOBAL=y +CONFIG_CMD_MD5SUM=y +# CONFIG_CMD_PWD is not set +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +# CONFIG_CMD_CLEAR is not set +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_OFDEVICE=y +CONFIG_DRIVER_SERIAL_DIGIC=y +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_WRITE is not set +CONFIG_DRIVER_CFI=y +# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set +CONFIG_CLOCKSOURCE_DUMMY=y +CONFIG_CLOCKSOURCE_DUMMY_RATE=2000 +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_GPIO_DIGIC=y +CONFIG_ZLIB=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 66fc123223..0a4f2fe129 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -16,6 +16,7 @@ CONFIG_MACH_SABRELITE=y CONFIG_MACH_SABRESD=y CONFIG_MACH_NITROGEN6X=y CONFIG_MACH_SOLIDRUN_MICROSOM=y +CONFIG_MACH_EMBEDSKY_E9=y CONFIG_MACH_EMBEST_RIOTBOARD=y CONFIG_MACH_UDOO=y CONFIG_MACH_VARISCITE_MX6=y diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig index aed4cb7c63..fb1a9998b0 100644 --- a/arch/arm/cpu/Kconfig +++ b/arch/arm/cpu/Kconfig @@ -39,6 +39,19 @@ config CPU_ARM926T Say Y if you want support for the ARM926T processor. Otherwise, say N. +# ARM946E-S +config CPU_ARM946E + bool + depends on !MMU + select CPU_32v4T + help + ARM946E-S is a member of the ARM9E-S family of high- + performance, 32-bit system-on-chip processor solutions. + The TCM and ARMv5TE 32-bit instruction set is supported. + + Say Y if you want support for the ARM946E-S processor. + Otherwise, say N. + # Feroceon config CPU_FEROCEON bool diff --git a/arch/arm/cpu/dtb.c b/arch/arm/cpu/dtb.c index abc3ccb4c0..ae4ff2a9ad 100644 --- a/arch/arm/cpu/dtb.c +++ b/arch/arm/cpu/dtb.c @@ -50,6 +50,7 @@ static int of_arm_init(void) root = of_unflatten_dtb(fdt); if (root) { of_set_root_node(root); + of_fix_tree(root); if (IS_ENABLED(CONFIG_OFDEVICE)) of_probe(); } diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c index 961873d6bb..264420d084 100644 --- a/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c @@ -103,7 +103,7 @@ static noinline __noreturn void __start(unsigned long membase, /* * Maximum malloc space is the Kconfig value if given - * or 64MB. + * or 1GB. */ if (MALLOC_SIZE > 0) { malloc_start = malloc_end - MALLOC_SIZE; @@ -111,8 +111,8 @@ static noinline __noreturn void __start(unsigned long membase, malloc_start = membase; } else { malloc_start = malloc_end - (malloc_end - membase) / 2; - if (malloc_end - malloc_start > SZ_64M) - malloc_start = malloc_end - SZ_64M; + if (malloc_end - malloc_start > SZ_1G) + malloc_start = malloc_end - SZ_1G; } mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 72ad5e6a6f..fac2b273cb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,93 +1,47 @@ -dtb-$(CONFIG_ARCH_AM33XX) += \ - am335x-bone.dtb \ - am335x-boneblack.dtb \ - am335x-bone-common.dtb \ - am335x-phytec-phycore.dtb -dtb-$(CONFIG_ARCH_IMX25) += imx25-karo-tx25.dtb -dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk-bb.dtb \ - imx27-phytec-phycore-rdk.dtb -dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \ - imx51-genesi-efika-sb.dtb -dtb-$(CONFIG_ARCH_IMX53) += imx53-mba53.dtb \ - imx53-qsb.dtb \ - imx53-qsrb.dtb \ - imx53-voipac-bsb.dtb -dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \ - imx6dl-dfi-fs700-m60-6s.dtb \ - imx6q-dfi-fs700-m60-6q.dtb \ - imx6q-dmo-edmqmx6.dtb \ - imx6q-sabrelite.dtb \ - imx6dl-sabrelite.dtb \ - imx6q-sabresd.dtb \ - imx6dl-mba6x.dtb \ - imx6q-mba6x.dtb \ - imx6dl-phytec-pbab01.dtb \ - imx6q-phytec-pbab01.dtb \ - imx6s-phytec-pbab01.dtb \ - imx6dl-hummingboard.dtb \ - imx6q-guf-santaro.dtb \ - imx6q-nitrogen6x.dtb \ - imx6dl-nitrogen6x.dtb \ - imx6q-udoo.dtb \ - imx6q-var-custom.dtb \ - imx6s-riotboard.dtb \ - imx6q-phytec-pbaa03.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3188-radxarock.dtb -dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb -dtb-$(CONFIG_ARCH_TEGRA) += \ - tegra20-colibri-iris.dtb \ - tegra20-paz00.dtb \ - tegra30-beaver.dtb \ - tegra124-jetson-tk1.dtb - BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) -obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o - -pbl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o -pbl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o -pbl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o -pbl-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o -pbl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o -pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o -pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o -pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o -pbl-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o -pbl-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o -pbl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o -pbl-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o -pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o -pbl-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o -pbl-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o -pbl-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o -pbl-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o -pbl-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o -pbl-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o -pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o -pbl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o -pbl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o -pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o -pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o -pbl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o -pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o -pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o -pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o -pbl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o -pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o -pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o -pbl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o -pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o -pbl-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o -pbl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o -pbl-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o -pbl-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o - -.SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S -.SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y)) +obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o -targets += dtbs -targets += $(dtb-y) +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj-y += empty.o -extra-y += $(dtb-y) +pbl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o +pbl-dtb-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o +pbl-dtb-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o +pbl-dtb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o +pbl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o +pbl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o +pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o +pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o +pbl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o +pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o +pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o +pbl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o +pbl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o +pbl-dtb-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o +pbl-dtb-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o +pbl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o +pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o +pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o +pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o +pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o +pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o +pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o +pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o +pbl-dtb-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o +pbl-dtb-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o +pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o +pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o +pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o +pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o +pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o +pbl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o +pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o +pbl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o +pbl-dtb-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o +pbl-dtb-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o +pbl-dtb-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o +pbl-dtb-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o +pbl-dtb-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index 4cf7fdbb48..e1effac323 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -276,13 +276,14 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; - + status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; }; &mmc1 { diff --git a/arch/arm/dts/am335x-phytec-phycore.dts b/arch/arm/dts/am335x-phytec-phycore.dts index 6196eb3244..5678138f66 100644 --- a/arch/arm/dts/am335x-phytec-phycore.dts +++ b/arch/arm/dts/am335x-phytec-phycore.dts @@ -22,11 +22,6 @@ }; }; - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -214,6 +209,7 @@ &davinci_mdio { pinctrl-names = "default"; pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; }; &phy_sel { @@ -236,6 +232,7 @@ pinctrl-names = "default"; pinctrl-0 = <&emac_rmii1_pins>; dual_emac = <1>; + status = "okay"; }; &gpmc { diff --git a/arch/arm/dts/armada-370-mirabox-bb.dts b/arch/arm/dts/armada-370-mirabox-bb.dts index de37a75bb9..315678151a 100644 --- a/arch/arm/dts/armada-370-mirabox-bb.dts +++ b/arch/arm/dts/armada-370-mirabox-bb.dts @@ -11,9 +11,6 @@ }; soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; - internal-regs { gpio_leds { green_pwr_led { diff --git a/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts index 611d72707f..e88f1dc781 100644 --- a/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts +++ b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts @@ -11,10 +11,6 @@ }; soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>; - internal-regs { gpio_leds { red_led { diff --git a/arch/arm/dts/canon-a1100.dts b/arch/arm/dts/canon-a1100.dts new file mode 100644 index 0000000000..a88eacf4d4 --- /dev/null +++ b/arch/arm/dts/canon-a1100.dts @@ -0,0 +1,35 @@ +/dts-v1/; + +/include/ "digic4.dtsi" + +/ { + model = "Canon PowerShot A1100 IS"; + compatible = "canon,a1100"; + + memory { + reg = <0x00000000 0x04000000>; + }; + + flash@f8000000 { + compatible = "cfi-flash"; + reg = <0xf8000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + direct_print { + label = "direct-print (blue)"; + gpios = <&gpio 51 0>; + }; + + auto_focus { + label = "auto-focus (red)"; + gpios = <&gpio 55 0>; + }; + }; +}; + +&timer2 { + status = "okay"; +}; diff --git a/arch/arm/dts/digic4.dtsi b/arch/arm/dts/digic4.dtsi new file mode 100644 index 0000000000..21b004d4a2 --- /dev/null +++ b/arch/arm/dts/digic4.dtsi @@ -0,0 +1,42 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "canon,digic4"; + + timer0: timer@c0210000 { + compatible = "canon,digic-timer"; + reg = <0xc0210000 0x1c>; + status = "disabled"; + }; + + timer1: timer@c0210100 { + compatible = "canon,digic-timer"; + reg = <0xc0210100 0x1c>; + status = "disabled"; + }; + + timer2: timer@c0210200 { + compatible = "canon,digic-timer"; + reg = <0xc0210200 0x1c>; + status = "disabled"; + }; + + /* + * I don't know real max GPIO number but this page + * http://magiclantern.wikia.com/wiki/Register_Map#GPIO_Ports + * says about 93 pins on 5DMkIII. + * Assume that DIGIC4 has at least 96 pins. + * So resource size is 96 * 4 = 0x180. + */ + gpio: gpio { + compatible = "canon,digic-gpio"; + reg = <0xc0220000 0x180>; + #gpio-cells = <2>; + gpio-controller; + }; + + uart: uart { + compatible = "canon,digic-uart"; + reg = <0xc0800000 0x1c>; + }; +}; diff --git a/arch/arm/dts/empty.c b/arch/arm/dts/empty.c new file mode 100644 index 0000000000..d141224cf8 --- /dev/null +++ b/arch/arm/dts/empty.c @@ -0,0 +1,3 @@ +static inline void empty(void) +{ +} diff --git a/arch/arm/dts/imx6q-embedsky-e9.dts b/arch/arm/dts/imx6q-embedsky-e9.dts new file mode 100644 index 0000000000..14f6d5fe15 --- /dev/null +++ b/arch/arm/dts/imx6q-embedsky-e9.dts @@ -0,0 +1,42 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include <arm/imx6q-embedsky-e9.dtsi> + +/ { + chosen { + linux,stdout-path = &uart4; + + environment@0 { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + }; + + }; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; diff --git a/arch/arm/lib/barebox.lds.S b/arch/arm/lib/barebox.lds.S index d9588736f8..bb0354ae29 100644 --- a/arch/arm/lib/barebox.lds.S +++ b/arch/arm/lib/barebox.lds.S @@ -75,6 +75,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data*) } + .barebox_imd : { BAREBOX_IMD } + . = .; __barebox_cmd_start = .; .barebox_cmd : { BAREBOX_CMDS } diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index d9b9111ce1..baf0946a47 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -6,6 +6,7 @@ #include <image.h> #include <init.h> #include <fs.h> +#include <libfile.h> #include <linux/list.h> #include <xfuncs.h> #include <malloc.h> @@ -414,6 +415,11 @@ static int do_bootm_aimage(struct image_data *data) int to_read; struct android_header_comp *cmp; unsigned long mem_free; + unsigned long mem_start, mem_size; + + ret = sdram_start_and_size(&mem_start, &mem_size); + if (ret) + return ret; fd = open(data->os_file, O_RDONLY); if (fd < 0) { @@ -447,8 +453,17 @@ static int do_bootm_aimage(struct image_data *data) cmp = &header->kernel; data->os_res = request_sdram_region("akernel", cmp->load_addr, cmp->size); if (!data->os_res) { - ret = -ENOMEM; - goto err_out; + pr_err("Cannot request region 0x%08x - 0x%08x, using default load address\n", + cmp->load_addr, cmp->size); + + data->os_address = mem_start + PAGE_ALIGN(cmp->size * 4); + data->os_res = request_sdram_region("akernel", data->os_address, cmp->size); + if (!data->os_res) { + pr_err("Cannot request region 0x%08x - 0x%08x\n", + cmp->load_addr, cmp->size); + ret = -ENOMEM; + goto err_out; + } } ret = aimage_load_resource(fd, data->os_res, buf, header->page_size); diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S index 76184a0eec..9afee2964a 100644 --- a/arch/arm/lib/pbl.lds.S +++ b/arch/arm/lib/pbl.lds.S @@ -54,6 +54,8 @@ SECTIONS . = ALIGN(4); .rodata : { *(.rodata*) } + .barebox_imd : { BAREBOX_IMD } + _etext = .; /* End of text and rodata section */ . = ALIGN(4); diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c index 985203ae59..e69e4a86bf 100644 --- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c +++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c @@ -130,7 +130,7 @@ void __bare_init at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg) at91_sys_write(cfg->matrix_csa, cfg->ebi_csa); /* flash */ - at91_smc_write(cfg->smc_cs, AT91_SMC_MODE, cfg->smc_mode); + at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode); at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle); diff --git a/arch/arm/mach-at91/boot_test_cmd.c b/arch/arm/mach-at91/boot_test_cmd.c index 66c598b7ce..4fd1998ad0 100644 --- a/arch/arm/mach-at91/boot_test_cmd.c +++ b/arch/arm/mach-at91/boot_test_cmd.c @@ -7,6 +7,7 @@ #include <common.h> #include <command.h> #include <libbb.h> +#include <libfile.h> #include <getopt.h> #include <fs.h> #include <fcntl.h> diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h index d5cf5f762d..d19cf82eca 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h @@ -43,12 +43,24 @@ struct sam9_smc_config { /* Mode register */ u32 mode; u8 tdf_cycles:4; + + /* Timings register */ + u8 tclr; + u8 tadl; + u8 tar; + u8 ocms; + u8 trr; + u8 twb; + u8 rbnsel; + u8 nfsel; }; extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); + +extern void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config); #endif #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ @@ -77,7 +89,26 @@ extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) -#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */ +#define AT91_SAMA5_SMC_TIMINGS 0x0c /* Timings register for CS n */ +#define AT91_SMC_TCLR (0x0f << 0) /* CLE to REN Low Delay */ +#define AT91_SMC_TCLR_(x) ((x) << 0) +#define AT91_SMC_TADL (0x0f << 4) /* ALE to Data Start */ +#define AT91_SMC_TADL_(x) ((x) << 4) +#define AT91_SMC_TAR (0x0f << 8) /* ALE to REN Low Delay */ +#define AT91_SMC_TAR_(x) ((x) << 8) +#define AT91_SMC_OCMS (0x1 << 12) /* Off Chip Memory Scrambling Enable */ +#define AT91_SMC_OCMS_(x) ((x) << 12) +#define AT91_SMC_TRR (0x0f << 16) /* Ready to REN Low Delay */ +#define AT91_SMC_TRR_(x) ((x) << 16) +#define AT91_SMC_TWB (0x0f << 24) /* WEN High to REN to Busy */ +#define AT91_SMC_TWB_(x) ((x) << 24) +#define AT91_SMC_RBNSEL (0x07 << 28) /* Ready/Busy Line Selection */ +#define AT91_SMC_RBNSEL_(x) ((x) << 28) +#define AT91_SMC_NFSEL (0x01 << 31) /* Nand Flash Selection */ +#define AT91_SMC_NFSEL_(x) ((x) << 31) + +#define AT91_SAM9_SMC_MODE 0xc +#define AT91_SAMA5_SMC_MODE 0x10 #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index c7bfdfda63..9f028079c2 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -17,7 +17,9 @@ #include <mach/at91sam9_smc.h> -#define AT91_SMC_CS_STRIDE ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? 0x14 : 0x10) +#define AT91_SAM9_SMC_CS_STRIDE 0x10 +#define AT91_SAMA5_SMC_CS_STRIDE 0x14 +#define AT91_SMC_CS_STRIDE ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? AT91_SAMA5_SMC_CS_STRIDE : AT91_SAM9_SMC_CS_STRIDE) #define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * AT91_SMC_CS_STRIDE)) static void __iomem *smc_base_addr[2]; @@ -25,9 +27,27 @@ static void __iomem *smc_base_addr[2]; static void sam9_smc_cs_write_mode(void __iomem *base, struct sam9_smc_config *config) { + void __iomem *mode_reg; + + mode_reg = base + ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? AT91_SAMA5_SMC_MODE : AT91_SAM9_SMC_MODE); + __raw_writel(config->mode | AT91_SMC_TDF_(config->tdf_cycles), - base + AT91_SMC_MODE); + mode_reg); +} + +static void sam9_smc_cs_write_timings(void __iomem *base, + struct sam9_smc_config *config) +{ + __raw_writel(AT91_SMC_TCLR_(config->tclr) + | AT91_SMC_TADL_(config->tadl) + | AT91_SMC_TAR_(config->tar) + | AT91_SMC_OCMS_(config->ocms) + | AT91_SMC_TRR_(config->trr) + | AT91_SMC_TWB_(config->twb) + | AT91_SMC_RBNSEL_(config->rbnsel) + | AT91_SMC_NFSEL_(config->nfsel), + base + AT91_SAMA5_SMC_TIMINGS); } void sam9_smc_write_mode(int id, int cs, @@ -72,7 +92,12 @@ void sam9_smc_configure(int id, int cs, static void sam9_smc_cs_read_mode(void __iomem *base, struct sam9_smc_config *config) { - u32 val = __raw_readl(base + AT91_SMC_MODE); + u32 val; + void __iomem *mode_reg; + + mode_reg = base + ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? AT91_SAMA5_SMC_MODE : AT91_SAM9_SMC_MODE); + + val = __raw_readl(mode_reg); config->mode = (val & ~AT91_SMC_NWECYCLE); config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; @@ -120,6 +145,13 @@ void sam9_smc_read(int id, int cs, struct sam9_smc_config *config) sam9_smc_cs_read(AT91_SMC_CS(id, cs), config); } +void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config) +{ + sam9_smc_configure(id, cs, config); + + sam9_smc_cs_write_timings(AT91_SMC_CS(id, cs), config); +} + static int at91sam9_smc_probe(struct device_d *dev) { int id = dev->id; diff --git a/arch/arm/mach-digic/Kconfig b/arch/arm/mach-digic/Kconfig new file mode 100644 index 0000000000..d25c3b3f51 --- /dev/null +++ b/arch/arm/mach-digic/Kconfig @@ -0,0 +1,15 @@ +if ARCH_DIGIC + +choice + prompt "camera type" + +config MACH_CANON_A1100 + bool "Canon PowerShot A1100 IS" + +endchoice + +config ARCH_TEXT_BASE + hex + default 0x00001900 if MACH_CANON_A1100 + +endif diff --git a/arch/arm/mach-digic/Makefile b/arch/arm/mach-digic/Makefile new file mode 100644 index 0000000000..820eb10ac2 --- /dev/null +++ b/arch/arm/mach-digic/Makefile @@ -0,0 +1 @@ +obj-y += core.o diff --git a/arch/arm/mach-digic/core.c b/arch/arm/mach-digic/core.c new file mode 100644 index 0000000000..b1caec0bc8 --- /dev/null +++ b/arch/arm/mach-digic/core.c @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> + +void __noreturn reset_cpu(unsigned long ignored) +{ + pr_err("%s: unimplemented\n", __func__); + hang(); +} +EXPORT_SYMBOL(reset_cpu); diff --git a/arch/arm/mach-digic/include/mach/debug_ll.h b/arch/arm/mach-digic/include/mach/debug_ll.h new file mode 100644 index 0000000000..721fd444c2 --- /dev/null +++ b/arch/arm/mach-digic/include/mach/debug_ll.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2013, 2014 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_DEBUG_LL_H__ +#define __MACH_DEBUG_LL_H__ + +#include <io.h> +#include <mach/digic4.h> +#include <mach/uart.h> + +#define DEBUG_LL_UART DIGIC4_UART + +/* Serial interface registers */ +#define DEBUG_LL_UART_TX (DEBUG_LL_UART + DIGIC_UART_TX) +#define DEBUG_LL_UART_ST (DEBUG_LL_UART + DIGIC_UART_ST) + +static inline void PUTC_LL(char ch) +{ + while (!(readl(DEBUG_LL_UART_ST) & DIGIC_UART_ST_TX_RDY)) + ; /* noop */ + + writel(0x06, DEBUG_LL_UART_ST); + writel(ch, DEBUG_LL_UART_TX); +} + +#endif /* __MACH_DEBUG_LL_H__ */ diff --git a/arch/arm/mach-digic/include/mach/digic4.h b/arch/arm/mach-digic/include/mach/digic4.h new file mode 100644 index 0000000000..ffc7979a9c --- /dev/null +++ b/arch/arm/mach-digic/include/mach/digic4.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __DIGIC4_H__ +#define __DIGIC4_H__ + +#define DIGIC4_UART 0xc0800000 + +#endif /* __DIGIC4_H__ */ diff --git a/arch/arm/mach-digic/include/mach/uart.h b/arch/arm/mach-digic/include/mach/uart.h new file mode 100644 index 0000000000..043f7cd0e9 --- /dev/null +++ b/arch/arm/mach-digic/include/mach/uart.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __DIGIC_UART_H__ +#define __DIGIC_UART_H__ + +/* Serial interface registers offsets */ +#define DIGIC_UART_TX 0x0 +#define DIGIC_UART_RX 0x4 +#define DIGIC_UART_ST 0x14 +# define DIGIC_UART_ST_RX_RDY 1 +# define DIGIC_UART_ST_TX_RDY 2 + +#endif /* __DIGIC_UART_H__ */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 2d99f3eec5..53a44a06e9 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -208,6 +208,12 @@ config MACH_EFIKA_MX_SMARTBOOK help Choose this to compile barebox for the Efika MX Smartbook +config MACH_EMBEDSKY_E9 + bool "Embedsky E9 Mini-PC" + select ARCH_IMX6 + help + Choose this to compile barebox for the Embedsky E9 Mini PC + config MACH_FREESCALE_MX51_PDK bool "Freescale i.MX51 PDK" select ARCH_IMX51 diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index 125415ec8d..56369a0f94 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -168,7 +168,7 @@ static int imx_bbu_internal_v1_update(struct bbu_handler *handler, struct bbu_da * layer. */ static int imx_bbu_internal_v2_write_nand_dbbt(struct imx_internal_bbu_handler *imx_handler, - struct bbu_data *data, void *image, int image_len) + struct bbu_data *data) { struct mtd_info_user meminfo; int fd; @@ -178,6 +178,11 @@ static int imx_bbu_internal_v2_write_nand_dbbt(struct imx_internal_bbu_handler * uint32_t *ptr, *num_bb, *bb; uint64_t offset; int block = 0, len, now, blocksize; + int dbbt_start_page = 4; + int firmware_start_page = 12; + void *dbbt_base; + void *image, *freep = NULL; + int pre_image_size; ret = stat(data->devicefile, &s); if (ret) @@ -193,32 +198,40 @@ static int imx_bbu_internal_v2_write_nand_dbbt(struct imx_internal_bbu_handler * if (ret) goto out; + pre_image_size = firmware_start_page * meminfo.writesize; + image = freep = xzalloc(data->len + pre_image_size); + memcpy(image + pre_image_size, data->image, data->len); + blocksize = meminfo.erasesize; ptr = image + 0x4; *ptr++ = FCB_MAGIC; /* FCB */ *ptr++ = 1; /* FCB version */ + ptr = image + 0x68; /* Firmware start page */ + *ptr = firmware_start_page; + ptr = image + 0x78; /* DBBT start page */ - *ptr = 4; + *ptr = dbbt_start_page; - ptr = image + 4 * 2048 + 4; + dbbt_base = image + dbbt_start_page * meminfo.writesize; + ptr = dbbt_base + 4; *ptr++ = DBBT_MAGIC; /* DBBT */ *ptr = 1; /* DBBT version */ - ptr = (u32*)(image + 0x2010); + ptr = (u32*)(dbbt_base + 0x10); /* * This is marked as reserved in the i.MX53 reference manual, but * must be != 0. Otherwise the ROM ignores the DBBT */ *ptr = 1; - ptr = (u32*)(image + 0x4004); /* start of DBBT */ + ptr = (u32*)(dbbt_base + 4 * meminfo.writesize + 4); /* start of DBBT */ num_bb = ptr; bb = ptr + 1; offset = 0; - size_need = data->len + 0x8000; + size_need = data->len + pre_image_size; /* * Collect bad blocks and construct DBBT @@ -261,18 +274,18 @@ static int imx_bbu_internal_v2_write_nand_dbbt(struct imx_internal_bbu_handler * } debug("total image size: 0x%08zx. Space needed including bad blocks: 0x%08zx\n", - data->len + 0x8000, - data->len + 0x8000 + *num_bb * blocksize); + data->len + pre_image_size, + data->len + pre_image_size + *num_bb * blocksize); - if (data->len + 0x8000 + *num_bb * blocksize > imx_handler->device_size) { + if (data->len + pre_image_size + *num_bb * blocksize > imx_handler->device_size) { printf("needed space (0x%08zx) exceeds partition space (0x%08zx)\n", - data->len + 0x8000 + *num_bb * blocksize, + data->len + pre_image_size + *num_bb * blocksize, imx_handler->device_size); ret = -ENOSPC; goto out; } - len = data->len + 0x8000; + len = data->len + pre_image_size; offset = 0; /* @@ -312,6 +325,7 @@ static int imx_bbu_internal_v2_write_nand_dbbt(struct imx_internal_bbu_handler * out: close(fd); + free(freep); return ret; } @@ -329,10 +343,7 @@ static int imx_bbu_internal_v2_update(struct bbu_handler *handler, struct bbu_da { struct imx_internal_bbu_handler *imx_handler = container_of(handler, struct imx_internal_bbu_handler, handler); - void *imx_pre_image = NULL; - int imx_pre_image_size; - int ret, image_len; - void *buf; + int ret; uint32_t *barker; ret = imx_bbu_check_prereq(data); @@ -346,26 +357,10 @@ static int imx_bbu_internal_v2_update(struct bbu_handler *handler, struct bbu_da return -EINVAL; } - imx_pre_image_size = 0; - - if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND) { - /* NAND needs additional space for the DBBT */ - imx_pre_image_size += 0x6000; - imx_pre_image = xzalloc(imx_pre_image_size); - - /* Create a buffer containing header and image data */ - image_len = data->len + imx_pre_image_size; - buf = xzalloc(image_len); - memcpy(buf, imx_pre_image, imx_pre_image_size); - memcpy(buf + imx_pre_image_size, data->image, data->len); - - ret = imx_bbu_internal_v2_write_nand_dbbt(imx_handler, data, buf, - image_len); - free(buf); - free(imx_pre_image); - } else { + if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND) + ret = imx_bbu_internal_v2_write_nand_dbbt(imx_handler, data); + else ret = imx_bbu_write_device(imx_handler, data, data->image, data->len); - } return ret; } diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 18f61f74f9..131f3a67ea 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -14,11 +14,13 @@ config ARCH_ARMADA_370 bool "Armada 370" select CPU_V7 select CLOCKSOURCE_MVEBU + select PINCTRL_ARMADA_370 config ARCH_ARMADA_XP bool "Armada XP" select CPU_V7 select CLOCKSOURCE_MVEBU + select PINCTRL_ARMADA_XP config ARCH_DOVE bool "Dove 88AP510" diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index e416a38765..f2b991e5a7 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -18,6 +18,7 @@ #include <init.h> #include <io.h> #include <asm/memory.h> +#include <linux/mbus.h> #include <mach/armada-370-xp-regs.h> static inline void armada_370_xp_memory_find(unsigned long *phys_base, @@ -46,12 +47,20 @@ static inline void armada_370_xp_memory_find(unsigned long *phys_base, static int armada_370_xp_init_soc(void) { unsigned long phys_base, phys_size; + u32 reg; barebox_set_model("Marvell Armada 370/XP"); barebox_set_hostname("armada"); + /* Disable MBUS error propagation */ + reg = readl(ARMADA_370_XP_FABRIC_BASE); + reg &= ~BIT(8); + writel(reg, ARMADA_370_XP_FABRIC_BASE); + armada_370_xp_memory_find(&phys_base, &phys_size); - arm_add_mem_device("ram0", phys_base, phys_size); + + mvebu_set_memory(phys_base, phys_size); + mvebu_mbus_add_range(0xf0, 0x01, MVEBU_REMAP_INT_REG_BASE); return 0; } diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c index b054bf5aff..ac4b332e01 100644 --- a/arch/arm/mach-mvebu/common.c +++ b/arch/arm/mach-mvebu/common.c @@ -79,3 +79,62 @@ static int mvebu_soc_id_init(void) return 0; } postcore_initcall(mvebu_soc_id_init); + +static u64 mvebu_mem[2]; + +void mvebu_set_memory(u64 phys_base, u64 phys_size) +{ + mvebu_mem[0] = phys_base; + mvebu_mem[1] = phys_size; +} + +/* + * Memory size is set up by BootROM and can be read from SoC's ram controller + * registers. Fixup provided DTs to reflect accessible amount of directly + * attached RAM. Removable RAM, e.g. SODIMM, should be added by a per-board + * fixup. + */ +static int mvebu_memory_of_fixup(struct device_node *root, void *context) +{ + struct device_node *np; + __be32 reg[4]; + int na, ns; + + /* bail out on zero-sized mem */ + if (!mvebu_mem[1]) + return -ENODEV; + + np = of_find_node_by_path("/memory"); + if (!np) + np = of_create_node(root, "/memory"); + if (!np) + return -EINVAL; + + na = of_n_addr_cells(np); + ns = of_n_size_cells(np); + + if (na == 2) { + reg[0] = cpu_to_be32(mvebu_mem[0] >> 32); + reg[1] = cpu_to_be32(mvebu_mem[0] & 0xffffffff); + } else { + reg[0] = cpu_to_be32(mvebu_mem[0] & 0xffffffff); + } + + if (ns == 2) { + reg[2] = cpu_to_be32(mvebu_mem[1] >> 32); + reg[3] = cpu_to_be32(mvebu_mem[1] & 0xffffffff); + } else { + reg[1] = cpu_to_be32(mvebu_mem[1] & 0xffffffff); + } + + if (of_set_property(np, "device_type", "memory", sizeof("memory"), 1) || + of_set_property(np, "reg", reg, sizeof(u32) * (na + ns), 1)) + pr_err("Unable to fixup memory node\n"); + + return 0; +} + +static int mvebu_memory_fixup_register(void) { + return of_register_fixup(mvebu_memory_of_fixup, NULL); +} +pure_initcall(mvebu_memory_fixup_register); diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c index bcbf4b8ad7..69c6436b24 100644 --- a/arch/arm/mach-mvebu/dove.c +++ b/arch/arm/mach-mvebu/dove.c @@ -18,6 +18,7 @@ #include <init.h> #include <io.h> #include <asm/memory.h> +#include <linux/mbus.h> #include <mach/dove-regs.h> static inline void dove_remap_mc_regs(void) @@ -76,7 +77,10 @@ static int dove_init_soc(void) dove_remap_mc_regs(); dove_memory_find(&phys_base, &phys_size); - arm_add_mem_device("ram0", phys_base, phys_size); + + mvebu_set_memory(phys_base, phys_size); + mvebu_mbus_add_range(0xf0, 0x01, MVEBU_REMAP_INT_REG_BASE); + mvebu_mbus_add_range(0xf0, 0x02, DOVE_REMAP_MC_REGS); return 0; } diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h index 5fd16e5733..ccc687c03b 100644 --- a/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h +++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h @@ -42,6 +42,8 @@ #define DDR_SIZE_CS_SHIFT 2 #define DDR_SIZE_MASK 0xff000000 +#define ARMADA_370_XP_FABRIC_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x20200) + #define ARMADA_370_XP_TIMER_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x20300) #endif /* __MACH_MVEBU_DOVE_REGS_H */ diff --git a/arch/arm/mach-mvebu/include/mach/common.h b/arch/arm/mach-mvebu/include/mach/common.h index 3cc1bf71c0..9f6118e4ec 100644 --- a/arch/arm/mach-mvebu/include/mach/common.h +++ b/arch/arm/mach-mvebu/include/mach/common.h @@ -20,4 +20,6 @@ #define MVEBU_REMAP_INT_REG_BASE 0xf1000000 +void mvebu_set_memory(u64 phys_base, u64 phys_size); + #endif diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c index fe9ca9cbe4..c114bdb360 100644 --- a/arch/arm/mach-mvebu/kirkwood.c +++ b/arch/arm/mach-mvebu/kirkwood.c @@ -17,6 +17,7 @@ #include <init.h> #include <io.h> #include <asm/memory.h> +#include <linux/mbus.h> #include <mach/kirkwood-regs.h> static inline void kirkwood_memory_find(unsigned long *phys_base, @@ -50,7 +51,9 @@ static int kirkwood_init_soc(void) barebox_set_hostname("kirkwood"); kirkwood_memory_find(&phys_base, &phys_size); - arm_add_mem_device("ram0", phys_base, phys_size); + + mvebu_set_memory(phys_base, phys_size); + mvebu_mbus_add_range(0xf0, 0x01, MVEBU_REMAP_INT_REG_BASE); return 0; } diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile index c9b6f4bb9f..0ebfae7437 100644 --- a/arch/arm/mach-omap/Makefile +++ b/arch/arm/mach-omap/Makefile @@ -24,6 +24,7 @@ pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o +obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index 606e3918b3..71c528ca8b 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -19,6 +19,7 @@ #include <init.h> #include <io.h> #include <net.h> +#include <asm/barebox-arm.h> #include <mach/am33xx-silicon.h> #include <mach/am33xx-clock.h> #include <mach/generic.h> @@ -318,6 +319,61 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs) writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); } +/** + * am335x_sdram_size - read back SDRAM size from sdram_config register + * + * @return: The SDRAM size + */ +unsigned long am335x_sdram_size(void) +{ + int rows, cols, width, banks; + unsigned long size; + uint32_t sdram_config = readl(CM_EMIF_SDRAM_CONFIG); + + rows = ((sdram_config >> 7) & 0x7) + 9; + cols = (sdram_config & 0x7) + 8; + + switch ((sdram_config >> 14) & 0x3) { + case 0: + width = 4; + break; + case 1: + width = 2; + break; + default: + return 0; + } + + switch ((sdram_config >> 4) & 0x7) { + case 0: + banks = 1; + break; + case 1: + banks = 2; + break; + case 2: + banks = 4; + break; + case 3: + banks = 8; + break; + default: + return 0; + } + + size = (1 << rows) * (1 << cols) * banks * width; + + debug("%s: sdram_config: 0x%08x cols: %2d rows: %2d width: %2d banks: %2d size: 0x%08lx\n", + __func__, sdram_config, cols, rows, width, banks, size); + + return size; +} + +void __noreturn am335x_barebox_entry(void *boarddata) +{ + barebox_arm_entry(0x80000000, am335x_sdram_size(), boarddata); +} + void am33xx_config_io_ctrl(int ioctrl) { writel(ioctrl, AM33XX_DDR_CMD0_IOCTRL); diff --git a/arch/arm/mach-omap/am33xx_scrm.c b/arch/arm/mach-omap/am33xx_scrm.c new file mode 100644 index 0000000000..67529f8226 --- /dev/null +++ b/arch/arm/mach-omap/am33xx_scrm.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2014 Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <io.h> +#include <errno.h> +#include <sizes.h> +#include <init.h> +#include <of.h> +#include <asm/barebox-arm.h> +#include <asm/memory.h> +#include <mach/am33xx-silicon.h> + +static int am33xx_scrm_probe(struct device_d *dev) +{ + arm_add_mem_device("ram0", 0x80000000, am335x_sdram_size()); + + return 0; +} + +static __maybe_unused struct of_device_id am33xx_scrm_dt_ids[] = { + { + .compatible = "ti,am3-scrm", + }, { + /* sentinel */ + } +}; + +static struct driver_d am33xx_scrm_driver = { + .name = "am33xx-scrm", + .probe = am33xx_scrm_probe, + .of_compatible = DRV_OF_COMPAT(am33xx_scrm_dt_ids), +}; + +static int am33xx_scrm_init(void) +{ + return platform_driver_register(&am33xx_scrm_driver); +} + +mem_initcall(am33xx_scrm_init); diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index 20b8e81c1c..ceca10a619 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -237,5 +237,7 @@ void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr); void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl, const struct am33xx_emif_regs *emif_regs, const struct am33xx_ddr_data *ddr_data); +unsigned long am335x_sdram_size(void); +void am335x_barebox_entry(void *boarddata); #endif diff --git a/arch/arm/mach-omap/omap_generic.c b/arch/arm/mach-omap/omap_generic.c index 060c59277f..334cf8db56 100644 --- a/arch/arm/mach-omap/omap_generic.c +++ b/arch/arm/mach-omap/omap_generic.c @@ -20,6 +20,7 @@ #include <io.h> #include <fs.h> #include <malloc.h> +#include <libfile.h> #include <linux/stat.h> #include <mach/gpmc.h> #include <mach/generic.h> diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c index a309450109..e9d7bbb2e9 100644 --- a/arch/arm/mach-omap/xload.c +++ b/arch/arm/mach-omap/xload.c @@ -5,6 +5,7 @@ #include <init.h> #include <driver.h> #include <linux/mtd/mtd.h> +#include <libfile.h> #include <fs.h> #include <fcntl.h> #include <sizes.h> diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index bea9f51e1e..6233614e19 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -5,6 +5,7 @@ config BLACKFIN select HAS_MODULES select HAVE_CONFIGURABLE_MEMORY_LAYOUT select HAVE_CONFIGURABLE_TEXT_BASE + select GENERIC_FIND_NEXT_BIT default y config BF561 diff --git a/arch/blackfin/boards/ipe337/cmd_alternate.c b/arch/blackfin/boards/ipe337/cmd_alternate.c index 992d274847..b332cfb059 100644 --- a/arch/blackfin/boards/ipe337/cmd_alternate.c +++ b/arch/blackfin/boards/ipe337/cmd_alternate.c @@ -1,5 +1,6 @@ #include <common.h> #include <command.h> +#include <libfile.h> #include <linux/stat.h> #include <malloc.h> #include <fs.h> diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 4ab1471522..e77ab83202 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -1,11 +1,4 @@ /* - * barebox - bitops.h Routines for bit operations - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -16,349 +9,27 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * + * */ -#ifndef _BLACKFIN_BITOPS_H -#define _BLACKFIN_BITOPS_H - -/* - * Copyright 1992, Linus Torvalds. - */ - -#include <asm/byteorder.h> -#include <asm/system.h> - -#ifdef __KERNEL__ -/* - * Function prototypes to keep gcc -Wall happy - */ - -/* - * The __ functions are not atomic - */ - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static __inline__ unsigned long ffz(unsigned long word) -{ - unsigned long result = 0; - - while (word & 1) { - result++; - word >>= 1; - } - return result; -} - -static __inline__ void set_bit(int nr, volatile void *addr) -{ - int *a = (int *) addr; - int mask; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - *a |= mask; - restore_flags(flags); -} - -static __inline__ void __set_bit(int nr, volatile void *addr) -{ - int *a = (int *) addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a |= mask; -} - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -static __inline__ void clear_bit(int nr, volatile void *addr) -{ - int *a = (int *) addr; - int mask; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - *a &= ~mask; - restore_flags(flags); -} - -static __inline__ void change_bit(int nr, volatile void *addr) -{ - int mask, flags; - unsigned long *ADDR = (unsigned long *) addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - save_and_cli(flags); - *ADDR ^= mask; - restore_flags(flags); -} - -static __inline__ void __change_bit(int nr, volatile void *addr) -{ - int mask; - unsigned long *ADDR = (unsigned long *) addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - *ADDR ^= mask; -} - -static __inline__ int test_and_set_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - retval = (mask & *a) != 0; - *a |= mask; - restore_flags(flags); - - return retval; -} - -static __inline__ int __test_and_set_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a |= mask; - return retval; -} - -static __inline__ int test_and_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - retval = (mask & *a) != 0; - *a &= ~mask; - restore_flags(flags); - - return retval; -} - -static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a &= ~mask; - return retval; -} - -static __inline__ int test_and_change_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - retval = (mask & *a) != 0; - *a ^= mask; - restore_flags(flags); - - return retval; -} - -static __inline__ int __test_and_change_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a ^= mask; - return retval; -} - -/* - * This routine doesn't need to be atomic. - */ -static __inline__ int __constant_test_bit(int nr, - const volatile void *addr) -{ - return ((1UL << (nr & 31)) & - (((const volatile unsigned int *) addr)[nr >> 5])) != 0; -} - -static __inline__ int __test_bit(int nr, volatile void *addr) -{ - int *a = (int *) addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *a) != 0); -} - -#define test_bit(nr,addr) \ -(__builtin_constant_p(nr) ? \ - __constant_test_bit((nr),(addr)) : \ - __test_bit((nr),(addr))) - -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) - -static __inline__ int find_next_zero_bit(void *addr, int size, int offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (32 - offset); - if (size < 32) - goto found_first; - if (~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size & ~31UL) { - if (~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - - found_first: - tmp |= ~0UL >> size; - found_middle: - return result + ffz(tmp); -} +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ #include <asm-generic/bitops/__ffs.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/ffs.h> #include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> #include <asm-generic/bitops/hweight.h> - -static __inline__ int ext2_set_bit(int nr, volatile void *addr) -{ - int mask, retval; - unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - save_and_cli(flags); - retval = (mask & *ADDR) != 0; - *ADDR |= mask; - restore_flags(flags); - return retval; -} - -static __inline__ int ext2_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - save_and_cli(flags); - retval = (mask & *ADDR) != 0; - *ADDR &= ~mask; - restore_flags(flags); - return retval; -} - -static __inline__ int ext2_test_bit(int nr, const volatile void *addr) -{ - int mask; - const volatile unsigned char *ADDR = (const unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - return ((mask & *ADDR) != 0); -} - -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) - -static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, - unsigned long size, - unsigned long - offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (32 - offset); - if (size < 32) - goto found_first; - if (~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size & ~31UL) { - if (~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - - found_first: - tmp |= ~0UL >> size; - found_middle: - return result + ffz(tmp); -} - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif - -#endif +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit(x, y) __set_bit(x, y) +#define clear_bit(x, y) __clear_bit(x, y) +#define change_bit(x, y) __change_bit(x, y) +#define test_and_set_bit(x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit(x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_BITOPS_H_ */ diff --git a/arch/efi/Kconfig b/arch/efi/Kconfig new file mode 100644 index 0000000000..26fecaa392 --- /dev/null +++ b/arch/efi/Kconfig @@ -0,0 +1,52 @@ +config ARCH_EFI + bool + default y + select HAS_DEBUG_LL + select HAS_KALLSYMS + select HAVE_DEFAULT_ENVIRONMENT_NEW + select EFI_GUID + select EFI_DEVICEPATH + select PRINTF_UUID + select GENERIC_FIND_NEXT_BIT + +config ARCH_TEXT_BASE + hex + default 0x0 + +menu "EFI specific settings" + +config 64BIT + def_bool y + help + Say yes to build a 64-bit binary - formerly known as x86_64 + Say no to build a 32-bit binary - formerly known as i386. + + 32-bit support currently does not compile and is not tested + due to the lack of hardware. + +config X86_32 + def_bool y + depends on !64BIT + +config X86_64 + def_bool y + depends on 64BIT + +config ARCH_EFI_REGISTER_COM1 + bool "Register first serial port" + help + Say yes here to register the first serial port on ioport 0x3f8. + This is useful to control barebox over a serial port if the board + has one. Enabling this option may not work on boards which do not + have a serial port. Also enable DRIVER_SERIAL_NS16550 to enable + the NS16550 driver. + +endmenu + +source common/Kconfig +source commands/Kconfig +source net/Kconfig +source drivers/Kconfig +source fs/Kconfig +source lib/Kconfig +source crypto/Kconfig diff --git a/arch/efi/Makefile b/arch/efi/Makefile new file mode 100644 index 0000000000..af280859f0 --- /dev/null +++ b/arch/efi/Makefile @@ -0,0 +1,41 @@ +CFLAGS += -fpic -fshort-wchar -mno-sse -mno-mmx + +ifeq ($(CONFIG_X86_32),y) + UTS_MACHINE := i386 + biarch := $(call cc-option,-m32) + AFLAGS += $(biarch) + CFLAGS += $(biarch) + TARGET = efi-app-ia32 +else + UTS_MACHINE := x86_64 + AFLAGS += -m64 + CFLAGS += -m64 -mno-red-zone + TARGET = efi-app-x86_64 +endif + +lds-$(CONFIG_X86_32) := arch/efi/lib/elf_ia32_efi.lds +lds-$(CONFIG_X86_64) := arch/efi/lib/elf_x86_64_efi.lds + +cmd_barebox__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_barebox) -o $@ \ + -T $(lds-y) \ + -shared -Bsymbolic -nostdlib -znocombreloc \ + --start-group $(barebox-common) \ + --end-group \ + $(filter-out $(barebox-lds) $(barebox-common) FORCE ,$^) + +quiet_cmd_efi_image = EFI-IMG $@ + cmd_efi_image = objcopy -j .text -j .sdata -j .data -j .dynamic \ + -j .dynsym -j .rel -j .rela -j .reloc -j __barebox_initcalls \ + -j __barebox_cmd -j .barebox_magicvar -j .bbenv.* \ + --target=$(TARGET) $< $@ + +KBUILD_BINARY := barebox + +LDFLAGS := -m elf_$(UTS_MACHINE) --no-undefined + +barebox.efi: $(KBUILD_BINARY) FORCE + $(call if_changed,efi_image) + +KBUILD_IMAGE := barebox.efi + +common-y += arch/efi/efi/ arch/efi/lib/ diff --git a/arch/efi/configs/efi_defconfig b/arch/efi/configs/efi_defconfig new file mode 100644 index 0000000000..456f70d32b --- /dev/null +++ b/arch/efi/configs/efi_defconfig @@ -0,0 +1,78 @@ +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_PROMPT="barebox> " +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_PARTITION_DISK_EFI=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_POLLER=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_HOST=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENUTREE=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MM=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_2048=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_NET_NETCONSOLE=y +CONFIG_DRIVER_SERIAL_EFI_STDIO=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_NET_EFI_SNP=y +# CONFIG_SPI is not set +CONFIG_DISK=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_EFI=y +CONFIG_FS_EFIVARFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/efi/efi/Makefile b/arch/efi/efi/Makefile new file mode 100644 index 0000000000..a856e5907c --- /dev/null +++ b/arch/efi/efi/Makefile @@ -0,0 +1,2 @@ +obj-y += efi.o clocksource.o efi-block-io.o efi-device.o efi-image.o +bbenv-y += env-efi diff --git a/arch/efi/efi/clocksource.c b/arch/efi/efi/clocksource.c new file mode 100644 index 0000000000..2f33b43cce --- /dev/null +++ b/arch/efi/efi/clocksource.c @@ -0,0 +1,60 @@ +#include <common.h> +#include <efi.h> +#include <mach/efi.h> +#include <clock.h> + +#ifdef __x86_64__ +uint64_t ticks_read(void) +{ + uint64_t a, d; + + __asm__ volatile ("rdtsc" : "=a" (a), "=d" (d)); + + return (d << 32) | a; +} +#else +uint64_t ticks_read(void) +{ + uint64_t val; + + __asm__ volatile ("rdtsc" : "=A" (val)); + + return val; +} +#endif + +static uint64_t freq; + +/* count TSC ticks during a millisecond delay */ +static uint64_t ticks_freq(void) +{ + uint64_t ticks_start, ticks_end; + + ticks_start = ticks_read(); + BS->stall(1000); + ticks_end = ticks_read(); + + return (ticks_end - ticks_start) * 1000; +} + +static uint64_t efi_clocksource_read(void) +{ + return 1000 * 1000 * ticks_read() / freq; +} + +static struct clocksource cs = { + .read = efi_clocksource_read, + .mask = CLOCKSOURCE_MASK(64), + .shift = 0, +}; + +int efi_clocksource_init(void) +{ + cs.mult = clocksource_hz2mult(1000 * 1000, cs.shift); + + freq = ticks_freq(); + + init_clock(&cs); + + return 0; +} diff --git a/arch/efi/efi/efi-block-io.c b/arch/efi/efi/efi-block-io.c new file mode 100644 index 0000000000..00115317fc --- /dev/null +++ b/arch/efi/efi/efi-block-io.c @@ -0,0 +1,174 @@ +#include <common.h> +#include <driver.h> +#include <init.h> +#include <malloc.h> +#include <fs.h> +#include <string.h> +#include <command.h> +#include <errno.h> +#include <linux/stat.h> +#include <xfuncs.h> +#include <fcntl.h> +#include <efi.h> +#include <block.h> +#include <disks.h> +#include <mach/efi.h> +#include <mach/efi-device.h> + +#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001 +#define EFI_BLOCK_IO_PROTOCOL_REVISION3 ((2<<16) | (31)) + +struct efi_block_io_media{ + u32 media_id; + bool removable_media; + bool media_present; + bool logical_partition; + bool read_only; + bool write_caching; + u32 block_size; + u32 io_align; + u64 last_block; + u64 lowest_aligned_lba; /* added in Revision 2 */ + u32 logical_blocks_per_physical_block; /* added in Revision 2 */ + u32 optimal_transfer_length_granularity; /* added in Revision 3 */ +}; + +struct efi_block_io_protocol { + u64 revision; + struct efi_block_io_media *media; + efi_status_t(EFIAPI *reset)(struct efi_block_io_protocol *this, + bool ExtendedVerification); + efi_status_t(EFIAPI *read)(struct efi_block_io_protocol *this, u32 media_id, + u64 lba, unsigned long buffer_size, void *buf); + efi_status_t(EFIAPI *write)(struct efi_block_io_protocol *this, u32 media_id, + u64 lba, unsigned long buffer_size, void *buf); + efi_status_t(EFIAPI *flush)(struct efi_block_io_protocol *this); +}; + +struct efi_bio_priv { + struct efi_block_io_protocol *protocol; + struct device_d *dev; + struct block_device blk; + u32 media_id; +}; + +static int efi_bio_read(struct block_device *blk, void *buffer, int block, + int num_blocks) +{ + struct efi_bio_priv *priv = container_of(blk, struct efi_bio_priv, blk); + efi_status_t efiret; + + efiret = priv->protocol->read(priv->protocol, priv->media_id, + block, num_blocks * 512, buffer); + + if (EFI_ERROR(efiret)) + return -efi_errno(efiret); + + return 0; +} + +static int efi_bio_write(struct block_device *blk, + const void *buffer, int block, int num_blocks) +{ + struct efi_bio_priv *priv = container_of(blk, struct efi_bio_priv, blk); + efi_status_t efiret; + + efiret = priv->protocol->write(priv->protocol, priv->media_id, + block, num_blocks * 512, (void *)buffer); + if (EFI_ERROR(efiret)) + return -efi_errno(efiret); + + return 0; +} + +static int efi_bio_flush(struct block_device *blk) +{ + struct efi_bio_priv *priv = container_of(blk, struct efi_bio_priv, blk); + efi_status_t efiret; + + efiret = priv->protocol->flush(priv->protocol); + if (EFI_ERROR(efiret)) + return -efi_errno(efiret); + + return 0; +} + +static struct block_device_ops efi_bio_ops = { + .read = efi_bio_read, + .write = efi_bio_write, + .flush = efi_bio_flush, +}; + +static void efi_bio_print_info(struct efi_bio_priv *priv) +{ + struct efi_block_io_media *media = priv->protocol->media; + u64 revision = priv->protocol->revision; + + dev_dbg(priv->dev, "revision: 0x%016llx\n", revision); + dev_dbg(priv->dev, "media_id: 0x%08x\n", media->media_id); + dev_dbg(priv->dev, "removable_media: %d\n", media->removable_media); + dev_dbg(priv->dev, "media_present: %d\n", media->media_present); + dev_dbg(priv->dev, "logical_partition: %d\n", media->logical_partition); + dev_dbg(priv->dev, "read_only: %d\n", media->read_only); + dev_dbg(priv->dev, "write_caching: %d\n", media->write_caching); + dev_dbg(priv->dev, "block_size: 0x%08x\n", media->block_size); + dev_dbg(priv->dev, "io_align: 0x%08x\n", media->io_align); + dev_dbg(priv->dev, "last_block: 0x%016llx\n", media->last_block); + + if (revision < EFI_BLOCK_IO_PROTOCOL_REVISION2) + return; + + dev_dbg(priv->dev, "u64 lowest_aligned_lba: 0x%08llx\n", + media->lowest_aligned_lba); + dev_dbg(priv->dev, "logical_blocks_per_physical_block: 0x%08x\n", + media->logical_blocks_per_physical_block); + + if (revision < EFI_BLOCK_IO_PROTOCOL_REVISION3) + return; + + dev_dbg(priv->dev, "optimal_transfer_length_granularity: 0x%08x\n", + media->optimal_transfer_length_granularity); +} + +int efi_bio_probe(struct efi_device *efidev) +{ + int ret; + struct efi_bio_priv *priv; + struct efi_block_io_media *media; + + priv = xzalloc(sizeof(*priv)); + + BS->handle_protocol(efidev->handle, &efi_block_io_protocol_guid, + (void **)&priv->protocol); + if (!priv->protocol) + return -ENODEV; + + media = priv->protocol->media; + efi_bio_print_info(priv); + priv->dev = &efidev->dev; + + priv->blk.cdev.name = asprintf("disk%d", cdev_find_free_index("disk")); + priv->blk.blockbits = ffs(media->block_size) - 1; + priv->blk.num_blocks = media->last_block; + priv->blk.ops = &efi_bio_ops; + priv->blk.dev = &efidev->dev; + + priv->media_id = media->media_id; + + ret = blockdevice_register(&priv->blk); + if (ret) + return ret; + + parse_partition_table(&priv->blk); + + return 0; +} + +static struct efi_driver efi_fs_driver = { + .driver = { + .name = "efi-block-io", + }, + .probe = efi_bio_probe, + .guid = EFI_BLOCK_IO_PROTOCOL_GUID, +}; +device_efi_driver(efi_fs_driver); diff --git a/arch/efi/efi/efi-device.c b/arch/efi/efi/efi-device.c new file mode 100644 index 0000000000..1c9553d906 --- /dev/null +++ b/arch/efi/efi/efi-device.c @@ -0,0 +1,349 @@ +/* + * efi-device.c - barebox EFI payload support + * + * Copyright (c) 2014 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <command.h> +#include <common.h> +#include <driver.h> +#include <malloc.h> +#include <memory.h> +#include <string.h> +#include <sizes.h> +#include <wchar.h> +#include <init.h> +#include <efi.h> +#include <mach/efi.h> +#include <mach/efi-device.h> +#include <linux/err.h> + +int efi_locate_handle(enum efi_locate_search_type search_type, + efi_guid_t *protocol, + void *search_key, + unsigned long *no_handles, + efi_handle_t **buffer) +{ + efi_status_t efiret; + unsigned long buffer_size = 0; + efi_handle_t *buf; + + efiret = BS->locate_handle(search_type, protocol, search_key, &buffer_size, + NULL); + if (EFI_ERROR(efiret) && efiret != EFI_BUFFER_TOO_SMALL) + return -efi_errno(efiret); + + buf = malloc(buffer_size); + if (!buf) + return -ENOMEM; + + efiret = BS->locate_handle(search_type, protocol, search_key, &buffer_size, + buf); + if (EFI_ERROR(efiret)) { + free(buf); + return -efi_errno(efiret); + } + + *no_handles = buffer_size / sizeof(efi_handle_t); + *buffer = buf; + + return 0; +} + +static struct efi_device *efi_find_device(efi_handle_t *handle) +{ + struct device_d *dev; + struct efi_device *efidev; + + bus_for_each_device(&efi_bus, dev) { + efidev = container_of(dev, struct efi_device, dev); + + if (efidev->handle == handle) + return efidev; + } + + return NULL; +} + +static void efi_devinfo(struct device_d *dev) +{ + struct efi_device *efidev = to_efi_device(dev); + int i; + + printf("Protocols:\n"); + + for (i = 0; i < efidev->num_guids; i++) + printf(" %d: %pUl: %s\n", i, &efidev->guids[i], + efi_guid_string(&efidev->guids[i])); +} + +static efi_handle_t *efi_find_parent(efi_handle_t *handle) +{ + unsigned long handle_count = 0; + efi_handle_t *handles = NULL, *parent; + unsigned long num_guids; + efi_guid_t **guids; + int ret, i, j, k; + efi_status_t efiret; + struct efi_open_protocol_information_entry *entry_buffer; + unsigned long entry_count; + + ret = efi_locate_handle(all_handles, NULL, NULL, &handle_count, &handles); + if (ret) + return NULL; + + /* + * Normally one would expect a function/pointer to retrieve the parent. + * With EFI we have to: + * - get all handles + * - for each handle get the registered protocols + * - for each protocol get the users + * - the user which matches the input handle is the parent + */ + for (i = 0; i < handle_count; i++) { + efiret = BS->open_protocol(handles[i], &efi_device_path_protocol_guid, + NULL, NULL, NULL, EFI_OPEN_PROTOCOL_TEST_PROTOCOL); + if (EFI_ERROR(efiret)) + continue; + + BS->protocols_per_handle(handles[i], &guids, &num_guids); + for (j = 0; j < num_guids; j++) { + efiret = BS->open_protocol_information(handles[i], guids[j], + &entry_buffer, &entry_count); + for (k = 0; k < entry_count; k++) { + if (entry_buffer[k].controller_handle == NULL) + continue; + if (entry_buffer[k].controller_handle == handles[i]) + continue; + if (entry_buffer[k].controller_handle == handle) { + parent = handles[i]; + goto out; + } + } + } + } + + parent = NULL; + + free(handles); +out: + return parent; +} + +static struct efi_device *efi_add_device(efi_handle_t *handle, efi_guid_t **guids, + int num_guids) +{ + struct efi_device *efidev; + int i; + efi_guid_t *guidarr; + efi_status_t efiret; + void *devpath; + + efidev = efi_find_device(handle); + if (efidev) + return ERR_PTR(-EEXIST); + + efiret = BS->open_protocol(handle, &efi_device_path_protocol_guid, + NULL, NULL, NULL, EFI_OPEN_PROTOCOL_TEST_PROTOCOL); + if (EFI_ERROR(efiret)) + return ERR_PTR(-EINVAL); + + guidarr = malloc(sizeof(efi_guid_t) * num_guids); + + for (i = 0; i < num_guids; i++) + memcpy(&guidarr[i], guids[i], sizeof(efi_guid_t)); + + efiret = BS->open_protocol(handle, &efi_device_path_protocol_guid, + &devpath, NULL, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR(efiret)) + return ERR_PTR(-EINVAL); + + efidev = xzalloc(sizeof(*efidev)); + + efidev->guids = guidarr; + efidev->num_guids = num_guids; + efidev->handle = handle; + efidev->dev.bus = &efi_bus; + efidev->dev.id = DEVICE_ID_SINGLE; + efidev->dev.info = efi_devinfo; + efidev->devpath = devpath; + + BS->handle_protocol(handle, &guidarr[0], &efidev->protocol); + + sprintf(efidev->dev.name, "handle-%p", handle); + + efidev->parent_handle = efi_find_parent(efidev->handle); + + return efidev; +} + + +static int efi_register_device(struct efi_device *efidev) +{ + char *dev_path_str; + struct efi_device *parent; + int ret; + + if (efi_find_device(efidev->handle)) + return -EEXIST; + + if (efidev->parent_handle) { + parent = efi_find_device(efidev->parent_handle); + if (!parent) + return -EINVAL; + + efidev->dev.parent = &parent->dev; + } + + ret = register_device(&efidev->dev); + if (ret) + return ret; + + dev_path_str = device_path_to_str(efidev->devpath); + if (dev_path_str) { + dev_add_param_fixed(&efidev->dev, "devpath", dev_path_str); + free(dev_path_str); + } + + debug("registered efi device %s\n", dev_name(&efidev->dev)); + + return 0; +} + +/** + * efi_register_devices - iterate over all EFI handles and register + * the devices found + * + * in barebox we treat all EFI handles which support the device_path + * protocol as devices. This function iterates over all handles and + * registers the corresponding devices. efi_register_devices is safe + * to call multiple times. Already registered devices will be ignored. + * + */ +void efi_register_devices(void) +{ + unsigned long handle_count = 0; + efi_handle_t *handles = NULL; + unsigned long num_guids; + efi_guid_t **guids; + int ret, i; + struct efi_device **efidevs; + int registered; + + ret = efi_locate_handle(all_handles, NULL, NULL, &handle_count, &handles); + if (ret) + return; + + efidevs = xzalloc(handle_count * sizeof(struct efi_device *)); + + for (i = 0; i < handle_count; i++) { + BS->protocols_per_handle(handles[i], &guids, &num_guids); + + efidevs[i] = efi_add_device(handles[i], guids, num_guids); + } + + /* + * We have a list of devices we want to register, but can only + * register a device when all parents are registered already. + * Do this by continiously iterating over the list until no + * further devices are registered. + */ + do { + registered = 0; + + for (i = 0; i < handle_count; i++) { + if (IS_ERR(efidevs[i])) + continue; + + ret = efi_register_device(efidevs[i]); + if (!ret) { + efidevs[i] = ERR_PTR(-EEXIST); + registered = 1; + } + } + } while (registered); + + free(efidevs); + free(handles); +} + +int efi_connect_all(void) +{ + efi_status_t efiret; + unsigned long handle_count; + efi_handle_t *handle_buffer; + int i; + + efiret = BS->locate_handle_buffer(all_handles, NULL, NULL, &handle_count, + &handle_buffer); + if (EFI_ERROR(efiret)) + return -efi_errno(efiret); + + for (i = 0; i < handle_count; i++) + efiret = BS->connect_controller(handle_buffer[i], NULL, NULL, true); + + if (handle_buffer) + BS->free_pool(handle_buffer); + + return 0; +} + +static int efi_bus_match(struct device_d *dev, struct driver_d *drv) +{ + struct efi_driver *efidrv = to_efi_driver(drv); + struct efi_device *efidev = to_efi_device(dev); + int i; + + for (i = 0; i < efidev->num_guids; i++) { + if (!memcmp(&efidrv->guid, &efidev->guids[i], sizeof(efi_guid_t))) + return 0; + } + + return 1; +} + +static int efi_bus_probe(struct device_d *dev) +{ + struct efi_driver *efidrv = to_efi_driver(dev->driver); + struct efi_device *efidev = to_efi_device(dev); + + return efidrv->probe(efidev); +} + +static void efi_bus_remove(struct device_d *dev) +{ + struct efi_driver *efidrv = to_efi_driver(dev->driver); + struct efi_device *efidev = to_efi_device(dev); + + return efidrv->remove(efidev); +} + +struct bus_type efi_bus = { + .name = "efi", + .match = efi_bus_match, + .probe = efi_bus_probe, + .remove = efi_bus_remove, +}; + +static int efi_init_devices(void) +{ + bus_register(&efi_bus); + + efi_register_devices(); + + return 0; +} +core_initcall(efi_init_devices); diff --git a/arch/efi/efi/efi-image.c b/arch/efi/efi/efi-image.c new file mode 100644 index 0000000000..18757d2697 --- /dev/null +++ b/arch/efi/efi/efi-image.c @@ -0,0 +1,105 @@ +/* + * efi-image.c - barebox EFI payload support + * + * Copyright (c) 2014 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <sizes.h> +#include <memory.h> +#include <command.h> +#include <magicvar.h> +#include <init.h> +#include <driver.h> +#include <io.h> +#include <efi.h> +#include <malloc.h> +#include <string.h> +#include <linux/err.h> +#include <boot.h> +#include <fs.h> +#include <binfmt.h> +#include <wchar.h> +#include <mach/efi.h> +#include <mach/efi-device.h> + +static int efi_execute_image(const char *file) +{ + void *exe; + size_t size; + efi_handle_t handle; + efi_status_t efiret; + const char *options; + efi_loaded_image_t *loaded_image; + + exe = read_file(file, &size); + if (!exe) + return -EINVAL; + + efiret = BS->load_image(false, efi_parent_image, efi_device_path, exe, size, + &handle); + if (EFI_ERROR(efiret)) { + pr_err("failed to LoadImage: %s\n", efi_strerror(efiret)); + return -efi_errno(efiret);; + }; + + efiret = BS->open_protocol(handle, &efi_loaded_image_protocol_guid, + (void **)&loaded_image, + efi_parent_image, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR(efiret)) + return -efi_errno(efiret); + + options = linux_bootargs_get(); + loaded_image->load_options = strdup_char_to_wchar(options); + loaded_image->load_options_size = (strlen(options) + 1) * sizeof(wchar_t); + + efiret = BS->start_image(handle, NULL, NULL); + + efi_connect_all(); + efi_register_devices(); + + return 0; +} + +static int do_bootm_efi(struct image_data *data) +{ + return efi_execute_image(data->os_file); +} + +static struct image_handler efi_handle_tr = { + .name = "EFI Application", + .bootm = do_bootm_efi, + .filetype = filetype_exe, +}; + +static int efi_execute(struct binfmt_hook *b, char *file, int argc, char **argv) +{ + return efi_execute_image(file); +} + +static struct binfmt_hook binfmt_efi_hook = { + .type = filetype_exe, + .hook = efi_execute, +}; + +static int efi_register_image_handler(void) +{ + register_image_handler(&efi_handle_tr); + binfmt_register(&binfmt_efi_hook); + + return 0; +} +late_initcall(efi_register_image_handler); diff --git a/arch/efi/efi/efi.c b/arch/efi/efi/efi.c new file mode 100644 index 0000000000..ff97783b13 --- /dev/null +++ b/arch/efi/efi/efi.c @@ -0,0 +1,343 @@ +/* + * efi.c - barebox EFI payload support + * + * Copyright (c) 2014 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <sizes.h> +#include <memory.h> +#include <clock.h> +#include <command.h> +#include <magicvar.h> +#include <init.h> +#include <driver.h> +#include <ns16550.h> +#include <io.h> +#include <efi.h> +#include <malloc.h> +#include <string.h> +#include <linux/err.h> +#include <boot.h> +#include <fs.h> +#include <binfmt.h> +#include <wchar.h> +#include <envfs.h> +#include <efi.h> +#include <mach/efi.h> +#include <mach/efi-device.h> + +efi_runtime_services_t *RT; +efi_boot_services_t *BS; +efi_system_table_t *efi_sys_table; +efi_handle_t efi_parent_image; +struct efi_device_path *efi_device_path; +efi_loaded_image_t *efi_loaded_image; + +void *efi_get_variable(char *name, efi_guid_t *vendor, int *var_size) +{ + efi_status_t efiret; + void *buf; + unsigned long size = 0; + s16 *name16 = strdup_char_to_wchar(name); + + efiret = RT->get_variable(name16, vendor, NULL, &size, NULL); + + if (EFI_ERROR(efiret) && efiret != EFI_BUFFER_TOO_SMALL) { + buf = ERR_PTR(-efi_errno(efiret)); + goto out; + } + + buf = malloc(size); + if (!buf) { + buf = ERR_PTR(-ENOMEM); + goto out; + } + + efiret = RT->get_variable(name16, vendor, NULL, &size, buf); + if (EFI_ERROR(efiret)) { + free(buf); + buf = ERR_PTR(-efi_errno(efiret)); + goto out; + } + + if (var_size) + *var_size = size; + +out: + free(name16); + + return buf; +} + +struct efi_boot { + u32 attributes; + u16 file_path_len; + char *description; + struct efi_device_path *path; + void *binary; +}; + +struct efi_boot *efi_get_boot(int num) +{ + struct efi_boot *boot = xzalloc(sizeof(*boot)); + void *buf, *ptr; + int size; + char *name; + + name = asprintf("Boot%04X", num); + + buf = efi_get_global_var(name, &size); + + free(name); + + if (!buf) { + free(boot); + return NULL; + } + + ptr = buf; + + boot->attributes = *(u32 *)ptr; + + ptr += sizeof(u32); + + boot->file_path_len = *(u16 *)ptr; + + ptr += sizeof(u16); + + boot->description = strdup_wchar_to_char(ptr); + + ptr += (strlen(boot->description) + 1) * 2; + + printf("description: %s\n", boot->description); + + boot->path = memdup(ptr, boot->file_path_len); + + printf("path: %s\n", device_path_to_str(boot->path)); + + return boot; +} + +static int misc_init(void) +{ + efi_get_boot(1); + efi_get_boot(2); + efi_get_boot(3); + + return 0; +} +late_initcall(misc_init); + +const char *efi_strerror(efi_status_t err) +{ + const char *str; + + switch (err) { + case EFI_SUCCESS: str = "Success"; break; + case EFI_LOAD_ERROR: str = "Load Error"; break; + case EFI_INVALID_PARAMETER: str = "Invalid Parameter"; break; + case EFI_UNSUPPORTED: str = "Unsupported"; break; + case EFI_BAD_BUFFER_SIZE: str = "Bad Buffer Size"; break; + case EFI_BUFFER_TOO_SMALL: str = "Buffer Too Small"; break; + case EFI_NOT_READY: str = "Not Ready"; break; + case EFI_DEVICE_ERROR: str = "Device Error"; break; + case EFI_WRITE_PROTECTED: str = "Write Protected"; break; + case EFI_OUT_OF_RESOURCES: str = "Out of Resources"; break; + case EFI_VOLUME_CORRUPTED: str = "Volume Corrupt"; break; + case EFI_VOLUME_FULL: str = "Volume Full"; break; + case EFI_NO_MEDIA: str = "No Media"; break; + case EFI_MEDIA_CHANGED: str = "Media changed"; break; + case EFI_NOT_FOUND: str = "Not Found"; break; + case EFI_ACCESS_DENIED: str = "Access Denied"; break; + case EFI_NO_RESPONSE: str = "No Response"; break; + case EFI_NO_MAPPING: str = "No mapping"; break; + case EFI_TIMEOUT: str = "Time out"; break; + case EFI_NOT_STARTED: str = "Not started"; break; + case EFI_ALREADY_STARTED: str = "Already started"; break; + case EFI_ABORTED: str = "Aborted"; break; + case EFI_ICMP_ERROR: str = "ICMP Error"; break; + case EFI_TFTP_ERROR: str = "TFTP Error"; break; + case EFI_PROTOCOL_ERROR: str = "Protocol Error"; break; + case EFI_INCOMPATIBLE_VERSION: str = "Incompatible Version"; break; + case EFI_SECURITY_VIOLATION: str = "Security Violation"; break; + case EFI_CRC_ERROR: str = "CRC Error"; break; + case EFI_END_OF_MEDIA: str = "End of Media"; break; + case EFI_END_OF_FILE: str = "End of File"; break; + case EFI_INVALID_LANGUAGE: str = "Invalid Language"; break; + case EFI_COMPROMISED_DATA: str = "Compromised Data"; break; + default: str = "unknown error"; + } + + return str; +} + +int efi_errno(efi_status_t err) +{ + int ret; + + switch (err) { + case EFI_SUCCESS: ret = 0; break; + case EFI_LOAD_ERROR: ret = EIO; break; + case EFI_INVALID_PARAMETER: ret = EINVAL; break; + case EFI_UNSUPPORTED: ret = ENOTSUPP; break; + case EFI_BAD_BUFFER_SIZE: ret = EINVAL; break; + case EFI_BUFFER_TOO_SMALL: ret = EINVAL; break; + case EFI_NOT_READY: ret = EAGAIN; break; + case EFI_DEVICE_ERROR: ret = EIO; break; + case EFI_WRITE_PROTECTED: ret = EROFS; break; + case EFI_OUT_OF_RESOURCES: ret = ENOMEM; break; + case EFI_VOLUME_CORRUPTED: ret = EIO; break; + case EFI_VOLUME_FULL: ret = ENOSPC; break; + case EFI_NO_MEDIA: ret = ENOMEDIUM; break; + case EFI_MEDIA_CHANGED: ret = ENOMEDIUM; break; + case EFI_NOT_FOUND: ret = ENODEV; break; + case EFI_ACCESS_DENIED: ret = EACCES; break; + case EFI_NO_RESPONSE: ret = ETIMEDOUT; break; + case EFI_NO_MAPPING: ret = EINVAL; break; + case EFI_TIMEOUT: ret = ETIMEDOUT; break; + case EFI_NOT_STARTED: ret = EINVAL; break; + case EFI_ALREADY_STARTED: ret = EINVAL; break; + case EFI_ABORTED: ret = EINTR; break; + case EFI_ICMP_ERROR: ret = EINVAL; break; + case EFI_TFTP_ERROR: ret = EINVAL; break; + case EFI_PROTOCOL_ERROR: ret = EPROTO; break; + case EFI_INCOMPATIBLE_VERSION: ret = EINVAL; break; + case EFI_SECURITY_VIOLATION: ret = EINVAL; break; + case EFI_CRC_ERROR: ret = EINVAL; break; + case EFI_END_OF_MEDIA: ret = EINVAL; break; + case EFI_END_OF_FILE: ret = EINVAL; break; + case EFI_INVALID_LANGUAGE: ret = EINVAL; break; + case EFI_COMPROMISED_DATA: ret = EINVAL; break; + default: ret = EINVAL; + } + + return ret; +} + +static struct NS16550_plat ns16550_plat = { + .clock = 115200 * 16, +}; + +static int efi_console_init(void) +{ + barebox_set_model("barebox EFI payload"); + + add_generic_device("efi-stdio", DEVICE_ID_SINGLE, NULL, 0 , 0, 0, NULL); + + if (IS_ENABLED(CONFIG_ARCH_EFI_REGISTER_COM1)) + add_ns16550_device(0, 0x3f8, 0x10, IORESOURCE_IO | IORESOURCE_MEM_8BIT, + &ns16550_plat); + + return 0; +} +console_initcall(efi_console_init); + +void reset_cpu(unsigned long addr) +{ + BS->exit(efi_parent_image, EFI_SUCCESS, 0, NULL); + + while(1); +} + +extern char image_base[]; +extern initcall_t __barebox_initcalls_start[], __barebox_early_initcalls_end[], + __barebox_initcalls_end[]; + +/* + * We have a position independent binary generated with -fpic. This function + * fixes the linker generated tables. + */ +static void fixup_tables(void) +{ + initcall_t *initcall; + unsigned long offset = (unsigned long)image_base; + struct command *cmdtp; + struct magicvar *m; + + for (initcall = __barebox_initcalls_start; + initcall < __barebox_initcalls_end; initcall++) + *initcall += offset; + + for (cmdtp = &__barebox_cmd_start; + cmdtp != &__barebox_cmd_end; + cmdtp++) { + cmdtp->name += offset; + cmdtp->cmd += offset; + if (cmdtp->complete) + cmdtp->complete += offset; + if (cmdtp->desc) + cmdtp->desc += offset; + if (cmdtp->help) + cmdtp->help += offset; + if (cmdtp->opts) + cmdtp->opts += offset; + if (cmdtp->aliases) + cmdtp->aliases = (void *)cmdtp->aliases + offset; + } + + for (m = &__barebox_magicvar_start; + m != &__barebox_magicvar_end; + m++) { + m->name += offset; + m->description += offset; + } +} + +static int efi_init(void) +{ + defaultenv_append_directory(env_efi); + + return 0; +} +device_initcall(efi_init); + +/** + * efi-main - Entry point for EFI images + */ +efi_status_t efi_main(efi_handle_t image, efi_system_table_t *sys_table) +{ + void *mem; + efi_status_t efiret; + +#ifdef DEBUG + sys_table->con_out->output_string(sys_table->con_out, L"barebox\n"); +#endif + + BS = sys_table->boottime; + + efi_parent_image = image; + efi_sys_table = sys_table; + RT = sys_table->runtime; + + efiret = BS->open_protocol(efi_parent_image, &efi_loaded_image_protocol_guid, + (void **)&efi_loaded_image, + efi_parent_image, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (!EFI_ERROR(efiret)) + BS->handle_protocol(efi_loaded_image->device_handle, + &efi_device_path_protocol_guid, (void **)&efi_device_path); + + fixup_tables(); + + BS->allocate_pool(efi_loaded_image->image_data_type, SZ_16M, &mem); + mem_malloc_init(mem, mem + SZ_16M); + + efi_clocksource_init(); + + start_barebox(); + + return EFI_SUCCESS; +} diff --git a/arch/efi/efi/env-efi/network/eth0-discover b/arch/efi/efi/env-efi/network/eth0-discover new file mode 100644 index 0000000000..62c31a553c --- /dev/null +++ b/arch/efi/efi/env-efi/network/eth0-discover @@ -0,0 +1,5 @@ +#!/bin/sh + +for i in /boot/network-drivers/*; do + $i; +done diff --git a/arch/efi/include/asm/barebox.h b/arch/efi/include/asm/barebox.h new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/arch/efi/include/asm/barebox.h @@ -0,0 +1 @@ +/* dummy */ diff --git a/arch/efi/include/asm/bitops.h b/arch/efi/include/asm/bitops.h new file mode 100644 index 0000000000..447023da63 --- /dev/null +++ b/arch/efi/include/asm/bitops.h @@ -0,0 +1,22 @@ +#ifndef _SANDBOX_BITOPS_H +#define _SANDBOX_BITOPS_H + +/* nothing but the defaults.. */ +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit(x, y) __set_bit(x, y) +#define clear_bit(x, y) __clear_bit(x, y) +#define change_bit(x, y) __change_bit(x, y) +#define test_and_set_bit(x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit(x, y) __test_and_change_bit(x, y) + +#endif diff --git a/arch/efi/include/asm/byteorder.h b/arch/efi/include/asm/byteorder.h new file mode 100644 index 0000000000..37316f2371 --- /dev/null +++ b/arch/efi/include/asm/byteorder.h @@ -0,0 +1,8 @@ +#ifndef _I386_BYTEORDER_H +#define _I386_BYTEORDER_H + +#include <asm/types.h> + +#include <linux/byteorder/little_endian.h> + +#endif /* _I386_BYTEORDER_H */ diff --git a/arch/efi/include/asm/common.h b/arch/efi/include/asm/common.h new file mode 100644 index 0000000000..b0e6b7fb18 --- /dev/null +++ b/arch/efi/include/asm/common.h @@ -0,0 +1,4 @@ +#ifndef ASM_COMMON_H +#define ASM_COMMON_H + +#endif /* ASM_COMMON_H */ diff --git a/arch/efi/include/asm/dma.h b/arch/efi/include/asm/dma.h new file mode 100644 index 0000000000..459536779e --- /dev/null +++ b/arch/efi/include/asm/dma.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __ASM_DMA_H +#define __ASM_DMA_H + +/* empty*/ + +#endif /* __ASM_DMA_H */ diff --git a/arch/efi/include/asm/elf.h b/arch/efi/include/asm/elf.h new file mode 100644 index 0000000000..ddde035188 --- /dev/null +++ b/arch/efi/include/asm/elf.h @@ -0,0 +1,60 @@ +#ifndef __ASM_SANDBOX_ELF_H__ +#define __ASM_SANDBOX_ELF_H__ + +#ifdef __i386__ + +typedef struct user_fxsr_struct elf_fpxregset_t; + +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 +#define R_386_NUM 11 + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_386 + +#else + +/* x86-64 relocation types */ +#define R_X86_64_NONE 0 /* No reloc */ +#define R_X86_64_64 1 /* Direct 64 bit */ +#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ +#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ +#define R_X86_64_PLT32 4 /* 32 bit PLT address */ +#define R_X86_64_COPY 5 /* Copy symbol at runtime */ +#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ +#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ +#define R_X86_64_RELATIVE 8 /* Adjust by program base */ +#define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative + offset to GOT */ +#define R_X86_64_32 10 /* Direct 32 bit zero extended */ +#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ +#define R_X86_64_16 12 /* Direct 16 bit zero extended */ +#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ +#define R_X86_64_8 14 /* Direct 8 bit sign extended */ +#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ + +#define R_X86_64_NUM 16 + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS64 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_X86_64 + +#endif + +#endif /* __ASM_SANDBOX_ELF_H__ */ diff --git a/arch/efi/include/asm/io.h b/arch/efi/include/asm/io.h new file mode 100644 index 0000000000..ac8a9c1b35 --- /dev/null +++ b/arch/efi/include/asm/io.h @@ -0,0 +1,55 @@ +#ifndef __ASM_SANDBOX_IO_H +#define __ASM_SANDBOX_IO_H + +#define build_mmio_read(name, size, type, reg, barrier) \ + static inline type name(const volatile void *addr) \ + { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ + :"m" (*(volatile type*)addr) barrier); return ret; } + +build_mmio_read(readb, "b", unsigned char, "=q", :"memory") +build_mmio_read(readw, "w", unsigned short, "=r", :"memory") +build_mmio_read(readl, "l", unsigned int, "=r", :"memory") + +#define build_mmio_write(name, size, type, reg, barrier) \ + static inline void name(type val, volatile void *addr) \ + { asm volatile("mov" size " %0,%1": :reg (val), \ + "m" (*(volatile type*)addr) barrier); } + +build_mmio_write(writeb, "b", unsigned char, "q", :"memory") +build_mmio_write(writew, "w", unsigned short, "r", :"memory") +build_mmio_write(writel, "l", unsigned int, "r", :"memory") + +#define BUILDIO(bwl, bw, type) \ +static inline void out##bwl(unsigned type value, int port) \ +{ \ + asm volatile("out" #bwl " %" #bw "0, %w1" \ + : : "a"(value), "Nd"(port)); \ +} \ + \ +static inline unsigned type in##bwl(int port) \ +{ \ + unsigned type value; \ + asm volatile("in" #bwl " %w1, %" #bw "0" \ + : "=a"(value) : "Nd"(port)); \ + return value; \ +} \ + \ +static inline void outs##bwl(int port, const void *addr, unsigned long count) \ +{ \ + asm volatile("rep; outs" #bwl \ + : "+S"(addr), "+c"(count) : "d"(port)); \ +} \ + \ +static inline void ins##bwl(int port, void *addr, unsigned long count) \ +{ \ + asm volatile("rep; ins" #bwl \ + : "+D"(addr), "+c"(count) : "d"(port)); \ +} + +BUILDIO(b, b, char) +BUILDIO(w, w, short) +BUILDIO(l, , int) + +#define IO_SPACE_LIMIT 0xffff + +#endif /* __ASM_SANDBOX_IO_H */ diff --git a/arch/efi/include/asm/posix_types.h b/arch/efi/include/asm/posix_types.h new file mode 100644 index 0000000000..6985b8eb4a --- /dev/null +++ b/arch/efi/include/asm/posix_types.h @@ -0,0 +1,93 @@ +#ifndef __ARCH_I386_POSIX_TYPES_H +#define __ARCH_I386_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +/* + * Most 32 bit architectures use "unsigned int" size_t, + * and all 64 bit architectures use "unsigned long" size_t. + * + * TODO: It's not clean to use __x86_64__ here. It's better + * to check on __BITS_PER_LONG here. But this is wrong set in + * arch/sandbox/include/asm/types.h. + */ +#ifdef __x86_64__ +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#else +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +#endif +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd,fdsetp) \ + __asm__ __volatile__("btsl %1,%0": \ + "=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd))) + +#undef __FD_CLR +#define __FD_CLR(fd,fdsetp) \ + __asm__ __volatile__("btrl %1,%0": \ + "=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd))) + +#undef __FD_ISSET +#define __FD_ISSET(fd,fdsetp) (__extension__ ({ \ + unsigned char __result; \ + __asm__ __volatile__("btl %1,%2 ; setb %0" \ + :"=q" (__result) :"r" ((int) (fd)), \ + "m" (*(__kernel_fd_set *) (fdsetp))); \ + __result; })) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ +do { \ + int __d0, __d1; \ + __asm__ __volatile__("cld ; rep ; stosl" \ + :"=m" (*(__kernel_fd_set *) (fdsetp)), \ + "=&c" (__d0), "=&D" (__d1) \ + :"a" (0), "1" (__FDSET_LONGS), \ + "2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \ +} while (0) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif diff --git a/arch/efi/include/asm/sections.h b/arch/efi/include/asm/sections.h new file mode 100644 index 0000000000..2b8c516038 --- /dev/null +++ b/arch/efi/include/asm/sections.h @@ -0,0 +1 @@ +#include <asm-generic/sections.h> diff --git a/arch/efi/include/asm/string.h b/arch/efi/include/asm/string.h new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/arch/efi/include/asm/string.h @@ -0,0 +1 @@ +/* dummy */ diff --git a/arch/efi/include/asm/swab.h b/arch/efi/include/asm/swab.h new file mode 100644 index 0000000000..60a90120b6 --- /dev/null +++ b/arch/efi/include/asm/swab.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +/* nothing. use generic functions */ + +#endif /* _ASM_SWAB_H */ diff --git a/arch/efi/include/asm/types.h b/arch/efi/include/asm/types.h new file mode 100644 index 0000000000..3204448dce --- /dev/null +++ b/arch/efi/include/asm/types.h @@ -0,0 +1,73 @@ +#ifndef __ASM_I386_TYPES_H +#define __ASM_I386_TYPES_H + +#ifndef __ASSEMBLY__ + +#ifdef __x86_64__ +/* + * This is used in dlmalloc. On X86_64 we need it to be + * 64 bit + */ +#define INTERNAL_SIZE_T unsigned long + +/* + * This is a Kconfig variable in the Kernel, but we want to detect + * this during compile time, so we set it here. + */ +#define CONFIG_PHYS_ADDR_T_64BIT + +#endif + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#ifdef __x86_64__ +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#endif /* __KERNEL__ */ + +#endif + +#endif diff --git a/arch/efi/include/asm/unaligned.h b/arch/efi/include/asm/unaligned.h new file mode 100644 index 0000000000..d02da6e60d --- /dev/null +++ b/arch/efi/include/asm/unaligned.h @@ -0,0 +1,19 @@ +#ifndef _ASM_SANDBOX_UNALIGNED_H +#define _ASM_SANDBOX_UNALIGNED_H + +/* + * The architecture sandbox is compiled on can do unaligned accesses itself. + */ + +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_SANDBOX_UNALIGNED_H */ diff --git a/arch/efi/include/mach/debug_ll.h b/arch/efi/include/mach/debug_ll.h new file mode 100644 index 0000000000..0fb2cb8c2a --- /dev/null +++ b/arch/efi/include/mach/debug_ll.h @@ -0,0 +1,20 @@ +#ifndef __MACH_DEBUG_LL_H__ +#define __MACH_DEBUG_LL_H__ + +#define EFI_DEBUG 0 +#define EFI_DEBUG_CLEAR_MEMORY 0 + +#include <efi.h> +#include <mach/efi.h> + +static inline void PUTC_LL(char c) +{ + uint16_t str[2] = {}; + struct efi_simple_text_output_protocol *con_out = efi_sys_table->con_out; + + str[0] = c; + + con_out->output_string(con_out, str); +} + +#endif diff --git a/arch/efi/include/mach/efi-device.h b/arch/efi/include/mach/efi-device.h new file mode 100644 index 0000000000..fe074a44bb --- /dev/null +++ b/arch/efi/include/mach/efi-device.h @@ -0,0 +1,45 @@ +#ifndef __MACH_EFI_DEVICE_H +#define __MACH_EFI_DEVICE_H + +struct efi_device { + struct device_d dev; + efi_guid_t *guids; + int num_guids; + efi_handle_t handle; + efi_handle_t parent_handle; + void *protocol; + struct efi_device_path *devpath; +}; + +struct efi_driver { + struct driver_d driver; + int (*probe)(struct efi_device *efidev); + void (*remove)(struct efi_device *efidev); + efi_guid_t guid; +}; + +extern struct bus_type efi_bus; + +static inline struct efi_device *to_efi_device(struct device_d *dev) +{ + return container_of(dev, struct efi_device, dev); +} + +static inline struct efi_driver *to_efi_driver(struct driver_d *drv) +{ + return container_of(drv, struct efi_driver, driver); +} + +#define device_efi_driver(drv) \ + register_driver_macro(device, efi, drv) + +static inline int efi_driver_register(struct efi_driver *efidrv) +{ + efidrv->driver.bus = &efi_bus; + return register_driver(&efidrv->driver); +} + +int efi_connect_all(void); +void efi_register_devices(void); + +#endif /* __MACH_EFI_DEVICE_H */ diff --git a/arch/efi/include/mach/efi.h b/arch/efi/include/mach/efi.h new file mode 100644 index 0000000000..1e9782a136 --- /dev/null +++ b/arch/efi/include/mach/efi.h @@ -0,0 +1,24 @@ +#ifndef __MACH_EFI_H +#define __MACH_EFI_H + +#include <efi.h> + +const char *efi_strerror(efi_status_t err); + +extern efi_system_table_t *efi_sys_table; +extern efi_handle_t efi_parent_image; +extern struct efi_device_path *efi_device_path; +extern efi_loaded_image_t *efi_loaded_image; + +int efi_errno(efi_status_t err); + +int efi_clocksource_init(void); + +void *efi_get_variable(char *name, efi_guid_t *vendor, int *var_size); + +static inline void *efi_get_global_var(char *name, int *var_size) +{ + return efi_get_variable(name, &efi_global_variable_guid, var_size); +} + +#endif /* __MACH_EFI_H */ diff --git a/arch/efi/lib/.gitignore b/arch/efi/lib/.gitignore new file mode 100644 index 0000000000..847e317701 --- /dev/null +++ b/arch/efi/lib/.gitignore @@ -0,0 +1,2 @@ +elf_x86_64_efi.lds +elf_ia32_efi.lds diff --git a/arch/efi/lib/Makefile b/arch/efi/lib/Makefile new file mode 100644 index 0000000000..c8a97bae07 --- /dev/null +++ b/arch/efi/lib/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_X86_64) += reloc_x86_64.o crt0-efi-x86_64.o +obj-$(CONFIG_X86_32) += reloc_ia32.o crt0-efi-ia32.o +extra-$(CONFIG_X86_32) += elf_ia32_efi.lds +extra-$(CONFIG_X86_64) += elf_x86_64_efi.lds diff --git a/arch/efi/lib/crt0-efi-ia32.S b/arch/efi/lib/crt0-efi-ia32.S new file mode 100644 index 0000000000..6f0f2e872e --- /dev/null +++ b/arch/efi/lib/crt0-efi-ia32.S @@ -0,0 +1,76 @@ +/* crt0-efi-ia32.S - x86 EFI startup code. + Copyright (C) 1999 Hewlett-Packard Co. + Contributed by David Mosberger <davidm@hpl.hp.com>. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + * Neither the name of Hewlett-Packard Co. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. +*/ + + .text + .align 4 + + .globl _start +_start: + pushl %ebp + movl %esp,%ebp + + pushl 12(%ebp) # copy "image" argument + pushl 8(%ebp) # copy "systab" argument + + call 0f +0: popl %eax + movl %eax,%ebx + + addl $image_base-0b,%eax # %eax = ldbase + addl $_DYNAMIC-0b,%ebx # %ebx = _DYNAMIC + + pushl %ebx # pass _DYNAMIC as second argument + pushl %eax # pass ldbase as first argument + call _relocate + popl %ebx + popl %ebx + testl %eax,%eax + jne .exit + + call efi_main # call app with "image" and "systab" argument + +.exit: leave + ret + + /* hand-craft a dummy .reloc section so EFI knows it's a relocatable executable: */ + + .data +dummy: .long 0 + +#define IMAGE_REL_ABSOLUTE 0 + .section .reloc + .long dummy /* Page RVA */ + .long 10 /* Block Size (2*4+2) */ + .word (IMAGE_REL_ABSOLUTE<<12) + 0 /* reloc for dummy */ diff --git a/arch/efi/lib/crt0-efi-x86_64.S b/arch/efi/lib/crt0-efi-x86_64.S new file mode 100644 index 0000000000..aa03106e9c --- /dev/null +++ b/arch/efi/lib/crt0-efi-x86_64.S @@ -0,0 +1,75 @@ +/* crt0-efi-x86_64.S - x86_64 EFI startup code. + Copyright (C) 1999 Hewlett-Packard Co. + Contributed by David Mosberger <davidm@hpl.hp.com>. + Copyright (C) 2005 Intel Co. + Contributed by Fenghua Yu <fenghua.yu@intel.com>. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + * Neither the name of Hewlett-Packard Co. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. +*/ + .text + .align 4 + + .globl _start +_start: + subq $8, %rsp + pushq %rcx + pushq %rdx + +0: + lea image_base(%rip), %rdi + lea _DYNAMIC(%rip), %rsi + + popq %rcx + popq %rdx + pushq %rcx + pushq %rdx + call _relocate + + popq %rdi + popq %rsi + + call efi_main + addq $8, %rsp + +.exit: + ret + + /* hand-craft a dummy .reloc section so EFI knows it's a relocatable executable: */ + + .data +dummy: .long 0 + +#define IMAGE_REL_ABSOLUTE 0 + .section .reloc, "a" +label1: + .long dummy-label1 /* Page RVA */ + .long 10 /* Block Size (2*4+2) */ + .word (IMAGE_REL_ABSOLUTE<<12) + 0 /* reloc for dummy */ diff --git a/arch/efi/lib/elf_ia32_efi.lds.S b/arch/efi/lib/elf_ia32_efi.lds.S new file mode 100644 index 0000000000..a5f6287500 --- /dev/null +++ b/arch/efi/lib/elf_ia32_efi.lds.S @@ -0,0 +1,102 @@ +#include <asm-generic/barebox.lds.h> + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) +SECTIONS +{ + . = 0; + image_base = .; + .hash : { *(.hash) } /* this MUST come first! */ + . = ALIGN(4096); + .text : + { + _stext = .; + _text = .; + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } + + _etext = .; + + . = ALIGN(4096); + .sdata : { + *(.got.plt) + *(.got) + *(.srodata) + *(.sdata) + *(.sbss) + *(.scommon) + } + + . = ALIGN(4096); + _sdata = .; + + .data : { + *(.rodata*) + *(.data) + *(.data1) + *(.data.*) + *(.sdata) + *(.got.plt) + *(.got) + /* the EFI loader doesn't seem to like a .bss section, so we stick + * it all into .data: */ + *(.sbss) + *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + . = ALIGN(64); + + __barebox_initcalls_start = .; + __barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + + . = ALIGN(64); + __barebox_magicvar_start = .; + .barebox_magicvar : { BAREBOX_MAGICVARS } + __barebox_magicvar_end = .; + + . = ALIGN(64); + __barebox_cmd_start = .; + __barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + . = ALIGN(4096); + .dynamic : { *(.dynamic) } + . = ALIGN(4096); + .rel : { + *(.rel.data) + *(.rel.data.*) + *(.rel.got) + *(.rel.stab) + *(.data.rel.ro.local) + *(.data.rel.local) + *(.data.rel.ro) + *(.data.rel*) + } + + . = ALIGN(4096); + .reloc : /* This is the PECOFF .reloc section! */ + { + *(.reloc) + } + + . = ALIGN(4096); + .dynsym : { *(.dynsym) } + . = ALIGN(4096); + .dynstr : { *(.dynstr) } + . = ALIGN(4096); + /DISCARD/ : + { + *(.rel.reloc) + *(.eh_frame) + *(.note.GNU-stack) + } + + .comment 0 : { *(.comment) } +} diff --git a/arch/efi/lib/elf_x86_64_efi.lds.S b/arch/efi/lib/elf_x86_64_efi.lds.S new file mode 100644 index 0000000000..d48432d21b --- /dev/null +++ b/arch/efi/lib/elf_x86_64_efi.lds.S @@ -0,0 +1,93 @@ +#include <asm-generic/barebox.lds.h> + +/* Same as elf_x86_64_fbsd_efi.lds, except for OUTPUT_FORMAT below - KEEP IN SYNC */ + +OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64") +OUTPUT_ARCH(i386:x86-64) +ENTRY(_start) +SECTIONS +{ + . = 0; + image_base = .; + .hash : { *(.hash) } /* this MUST come first! */ + . = ALIGN(4096); + .eh_frame : { + *(.eh_frame) + } + + . = ALIGN(4096); + + .text : { + _stext = .; + _text = .; + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } + + _etext = .; + + . = ALIGN(4096); + + .reloc : { + *(.reloc) + } + + . = ALIGN(4096); + _sdata = .; + + .data : { + *(.rodata*) + *(.got.plt) + *(.got) + *(.data*) + *(.sdata) + /* the EFI loader doesn't seem to like a .bss section, so we stick + * it all into .data: */ + *(.sbss) + *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + *(.rel.local) + } + + . = ALIGN(64); + + __barebox_initcalls_start = .; + __barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + + . = ALIGN(64); + __barebox_magicvar_start = .; + .barebox_magicvar : { BAREBOX_MAGICVARS } + __barebox_magicvar_end = .; + + . = ALIGN(64); + __barebox_cmd_start = .; + __barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + . = ALIGN(4096); + .dynamic : { *(.dynamic) } + . = ALIGN(4096); + + .rela : { + *(.rela.data*) + *(.rela.got) + *(.rela.stab) + } + + . = ALIGN(4096); + .dynsym : { *(.dynsym) } + . = ALIGN(4096); + .dynstr : { *(.dynstr) } + . = ALIGN(4096); + .ignored.reloc : { + *(.rela.reloc) + *(.eh_frame) + *(.note.GNU-stack) + } + + .comment 0 : { *(.comment) } +} diff --git a/arch/efi/lib/reloc_ia32.c b/arch/efi/lib/reloc_ia32.c new file mode 100644 index 0000000000..46929631ec --- /dev/null +++ b/arch/efi/lib/reloc_ia32.c @@ -0,0 +1,97 @@ +/* reloc_ia32.c - position independent x86 ELF shared object relocator + Copyright (C) 1999 Hewlett-Packard Co. + Contributed by David Mosberger <davidm@hpl.hp.com>. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + * Neither the name of Hewlett-Packard Co. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. +*/ + +#include <common.h> +#include <efi.h> + +#include <elf.h> + +efi_status_t _relocate(long ldbase, Elf32_Dyn *dyn, efi_handle_t image, efi_system_table_t *systab) +{ + long relsz = 0, relent = 0; + Elf32_Rel *rel = 0; + unsigned long *addr; + int i; + + for (i = 0; dyn[i].d_tag != DT_NULL; ++i) { + switch (dyn[i].d_tag) { + case DT_REL: + rel = (Elf32_Rel*) + ((unsigned long)dyn[i].d_un.d_ptr + + ldbase); + break; + + case DT_RELSZ: + relsz = dyn[i].d_un.d_val; + break; + + case DT_RELENT: + relent = dyn[i].d_un.d_val; + break; + + case DT_RELA: + break; + + default: + break; + } + } + + if (!rel && relent == 0) + return EFI_SUCCESS; + + if (!rel || relent == 0) + return EFI_LOAD_ERROR; + + while (relsz > 0) { + /* apply the relocs */ + switch (ELF32_R_TYPE (rel->r_info)) { + case R_386_NONE: + break; + + case R_386_RELATIVE: + addr = (unsigned long *) + (ldbase + rel->r_offset); + *addr += ldbase; + break; + + default: + break; + } + rel = (Elf32_Rel*) ((char *) rel + relent); + relsz -= relent; + } + return EFI_SUCCESS; +} diff --git a/arch/efi/lib/reloc_x86_64.c b/arch/efi/lib/reloc_x86_64.c new file mode 100644 index 0000000000..1db72f5dbc --- /dev/null +++ b/arch/efi/lib/reloc_x86_64.c @@ -0,0 +1,96 @@ +/* reloc_x86_64.c - position independent x86_64 ELF shared object relocator + Copyright (C) 1999 Hewlett-Packard Co. + Contributed by David Mosberger <davidm@hpl.hp.com>. + Copyright (C) 2005 Intel Co. + Contributed by Fenghua Yu <fenghua.yu@intel.com>. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + * Neither the name of Hewlett-Packard Co. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. +*/ + +#include <common.h> +#include <efi.h> + +#include <elf.h> + +efi_status_t _relocate (long ldbase, Elf64_Dyn *dyn, efi_handle_t image, efi_system_table_t *systab) +{ + long relsz = 0, relent = 0; + Elf64_Rel *rel = 0; + unsigned long *addr; + int i; + + for (i = 0; dyn[i].d_tag != DT_NULL; ++i) { + switch (dyn[i].d_tag) { + case DT_RELA: + rel = (Elf64_Rel*) + ((unsigned long)dyn[i].d_un.d_ptr + + ldbase); + break; + + case DT_RELASZ: + relsz = dyn[i].d_un.d_val; + break; + + case DT_RELAENT: + relent = dyn[i].d_un.d_val; + break; + + default: + break; + } + } + + if (!rel && relent == 0) + return EFI_SUCCESS; + + if (!rel || relent == 0) + return EFI_LOAD_ERROR; + + while (relsz > 0) { + /* apply the relocs */ + switch (ELF64_R_TYPE (rel->r_info)) { + case R_X86_64_NONE: + break; + + case R_X86_64_RELATIVE: + addr = (unsigned long *) + (ldbase + rel->r_offset); + *addr += ldbase; + break; + + default: + break; + } + rel = (Elf64_Rel*) ((char *) rel + relent); + relsz -= relent; + } + return EFI_SUCCESS; +} diff --git a/arch/mips/configs/qemu-malta_defconfig b/arch/mips/configs/qemu-malta_defconfig index 6ee302df02..5a1ca36822 100644 --- a/arch/mips/configs/qemu-malta_defconfig +++ b/arch/mips/configs/qemu-malta_defconfig @@ -14,6 +14,7 @@ CONFIG_POLLER=y CONFIG_DEBUG_INFO=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_GO=y diff --git a/arch/mips/configs/ritmix-rzx50_defconfig b/arch/mips/configs/ritmix-rzx50_defconfig index 3a2cf5450e..fb67014532 100644 --- a/arch/mips/configs/ritmix-rzx50_defconfig +++ b/arch/mips/configs/ritmix-rzx50_defconfig @@ -30,12 +30,18 @@ CONFIG_CMD_GETOPT=y CONFIG_CMD_SLEEP=y CONFIG_CMD_EDIT=y CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y CONFIG_CMD_POWEROFF=y +CONFIG_CMD_LED_TRIGGER=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OFTREE=y CONFIG_OFDEVICE=y # CONFIG_SPI is not set +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y CONFIG_GPIO_JZ4740=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_JZ4740=y diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 7ccb2f811c..6d6c9a3ce0 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -2,14 +2,4 @@ BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o -dtb-y += ${BUILTIN_DTB}.dtb - -.SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S -.SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y)) - -targets += dtbs -targets += $(dtb-y) - -extra-y += $(dtb-y) - clean-files := *.dtb *.dtb.S diff --git a/arch/mips/dts/jz4755.dtsi b/arch/mips/dts/jz4755.dtsi index ed64f9ab15..b83d884a24 100644 --- a/arch/mips/dts/jz4755.dtsi +++ b/arch/mips/dts/jz4755.dtsi @@ -8,6 +8,11 @@ #size-cells = <1>; ranges; + wdt: wdt@b0002000 { + compatible = "ingenic,jz4740-wdt"; + reg = <0xb0002000 0x10>; + }; + rtc: rtc@10003000 { compatible = "ingenic,jz4740-rtc"; reg = <0xb0003000 0x38>; diff --git a/arch/mips/dts/rzx50.dts b/arch/mips/dts/rzx50.dts index 360c1bf5de..7ec3352666 100644 --- a/arch/mips/dts/rzx50.dts +++ b/arch/mips/dts/rzx50.dts @@ -9,6 +9,16 @@ memory { reg = <0x00000000 0x4000000>; }; + + gpio-leds { + compatible = "gpio-leds"; + + lcd-backlight-enable { + label = "lcd backlight"; + gpios = <&gpio4 22 0>; + linux,default-trigger = "default-on"; + }; + }; }; &serial1 { diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index ebf8cf04d3..e77ab83202 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -12,20 +12,24 @@ * */ -/** - * @file - * @brief mips bit operations - * - * This file is required only to make all sources happy including - * 'linux/bitops.h' - */ - -#ifndef _ASM_MIPS_BITOPS_H_ -#define _ASM_MIPS_BITOPS_H_ +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ #include <asm-generic/bitops/__ffs.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/ffs.h> #include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit(x, y) __set_bit(x, y) +#define clear_bit(x, y) __clear_bit(x, y) +#define change_bit(x, y) __change_bit(x, y) +#define test_and_set_bit(x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit(x, y) __test_and_change_bit(x, y) -#endif /* _ASM_MIPS_BITOPS_H_ */ +#endif /* _ASM_BITOPS_H_ */ diff --git a/arch/mips/lib/barebox.lds.S b/arch/mips/lib/barebox.lds.S index 4ee4252b6d..c690e71976 100644 --- a/arch/mips/lib/barebox.lds.S +++ b/arch/mips/lib/barebox.lds.S @@ -49,6 +49,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data*) } + .barebox_imd : { BAREBOX_IMD } + . = ALIGN(4); .got : { *(.got*) } diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 3d6a4ce648..0e03aa9bcb 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -1,5 +1,6 @@ #include <boot.h> #include <common.h> +#include <libfile.h> #include <init.h> #include <fs.h> #include <errno.h> diff --git a/arch/mips/mach-xburst/Kconfig b/arch/mips/mach-xburst/Kconfig index 706d59249b..f7b8470cb8 100644 --- a/arch/mips/mach-xburst/Kconfig +++ b/arch/mips/mach-xburst/Kconfig @@ -6,6 +6,8 @@ config ARCH_TEXT_BASE config CPU_JZ4755 bool + select WATCHDOG + select WATCHDOG_JZ4740 choice prompt "Board type" diff --git a/arch/mips/mach-xburst/include/mach/jz4750d_regs.h b/arch/mips/mach-xburst/include/mach/jz4750d_regs.h index 7a3daadb18..396c823a1f 100644 --- a/arch/mips/mach-xburst/include/mach/jz4750d_regs.h +++ b/arch/mips/mach-xburst/include/mach/jz4750d_regs.h @@ -59,28 +59,6 @@ #define TCU_OSTCSR_PCK_EN (1 << 0) /* select pclk as the timer clock input */ /************************************************************************* - * WDT (WatchDog Timer) - *************************************************************************/ -#define WDT_TDR (WDT_BASE + 0x00) -#define WDT_TCER (WDT_BASE + 0x04) -#define WDT_TCNT (WDT_BASE + 0x08) -#define WDT_TCSR (WDT_BASE + 0x0c) - -#define WDT_TCSR_PRESCALE_BIT 3 -#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - -/************************************************************************* * RTC *************************************************************************/ #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ diff --git a/arch/mips/mach-xburst/reset-jz4750.c b/arch/mips/mach-xburst/reset-jz4750.c index 8f33672280..25830f130e 100644 --- a/arch/mips/mach-xburst/reset-jz4750.c +++ b/arch/mips/mach-xburst/reset-jz4750.c @@ -24,8 +24,6 @@ #include <io.h> #include <mach/jz4750d_regs.h> -#define JZ_EXTAL 24000000 - static void __noreturn jz4750d_halt(void) { while (1) { @@ -39,22 +37,6 @@ static void __noreturn jz4750d_halt(void) unreachable(); } -void __noreturn reset_cpu(ulong addr) -{ - __raw_writew(WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN, (u16 *)WDT_TCSR); - __raw_writew(0, (u16 *)WDT_TCNT); - - /* reset after 4ms */ - __raw_writew(JZ_EXTAL / 1000, (u16 *)WDT_TDR); - /* enable wdt clock */ - __raw_writel(TCU_TSCR_WDTSC, (u32 *)TCU_TSCR); - /* start wdt */ - __raw_writeb(WDT_TCER_TCEN, (u8 *)WDT_TCER); - - unreachable(); -} -EXPORT_SYMBOL(reset_cpu); - void __noreturn poweroff() { u32 ctrl; diff --git a/arch/mips/pbl/zbarebox.lds.S b/arch/mips/pbl/zbarebox.lds.S index 3a26942b4c..a883fdb2db 100644 --- a/arch/mips/pbl/zbarebox.lds.S +++ b/arch/mips/pbl/zbarebox.lds.S @@ -44,6 +44,8 @@ SECTIONS . = ALIGN(4); .rodata : { *(.rodata*) } + .barebox_imd : { BAREBOX_IMD } + _etext = .; /* End of text and rodata section */ . = ALIGN(4); diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig index 116daa9bb9..199540ba74 100644 --- a/arch/nios2/Kconfig +++ b/arch/nios2/Kconfig @@ -2,7 +2,9 @@ config NIOS2 bool select HAS_KALLSYMS select HAS_MODULES + select HAS_CACHE select HAVE_CONFIGURABLE_MEMORY_LAYOUT + select GENERIC_FIND_NEXT_BIT default y config ARCH_TEXT_BASE diff --git a/arch/nios2/include/asm/bitops.h b/arch/nios2/include/asm/bitops.h index 07128451c1..e77ab83202 100644 --- a/arch/nios2/include/asm/bitops.h +++ b/arch/nios2/include/asm/bitops.h @@ -1,9 +1,35 @@ -#ifndef _ASM_BITOPS_H -#define _ASM_BITOPS_H +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ #include <asm-generic/bitops/__ffs.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/ffs.h> #include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit(x, y) __set_bit(x, y) +#define clear_bit(x, y) __clear_bit(x, y) +#define change_bit(x, y) __change_bit(x, y) +#define test_and_set_bit(x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit(x, y) __test_and_change_bit(x, y) -#endif /* _ASM_BITOPS_H */ +#endif /* _ASM_BITOPS_H_ */ diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index d8d4ee9b6d..23c6a71f3a 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -1,7 +1,9 @@ config OPENRISC bool + select HAS_CACHE select HAVE_CONFIGURABLE_MEMORY_LAYOUT select HAVE_DEFAULT_ENVIRONMENT_NEW + select GENERIC_FIND_NEXT_BIT default y # not used diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h index fa57901476..e77ab83202 100644 --- a/arch/openrisc/include/asm/bitops.h +++ b/arch/openrisc/include/asm/bitops.h @@ -1,6 +1,4 @@ /* - * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -11,14 +9,27 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * + * */ -#ifndef __ASM_OPENRISC_BITOPS_H -#define __ASM_OPENRISC_BITOPS_H +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> -#define PLATFORM_FLS -#include <asm/bitops/fls.h> -#define PLATFORM_FFS -#include <asm/bitops/ffs.h> +#define set_bit(x, y) __set_bit(x, y) +#define clear_bit(x, y) __clear_bit(x, y) +#define change_bit(x, y) __change_bit(x, y) +#define test_and_set_bit(x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit(x, y) __test_and_change_bit(x, y) -#endif /* __ASM_GENERIC_BITOPS_H */ +#endif /* _ASM_BITOPS_H_ */ diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index eaf60e0fe4..97e6c00689 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -3,6 +3,8 @@ config PPC select HAVE_CONFIGURABLE_TEXT_BASE select HAS_KALLSYMS select HAS_MODULES + select HAS_CACHE + select GENERIC_FIND_NEXT_BIT select OFTREE default y diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile index b9b355aeee..fb9b0b89f8 100644 --- a/arch/ppc/Makefile +++ b/arch/ppc/Makefile @@ -12,6 +12,7 @@ CPPFLAGS += -Wa,-me500x2 -msoft-float -mno-string endif board-$(CONFIG_MACH_PHYCORE_MPC5200B_TINY) := pcm030 +board-$(CONFIG_P1010RDB) := freescale-p1010rdb board-$(CONFIG_P2020RDB) := freescale-p2020rdb board-$(CONFIG_P1022DS) := freescale-p1022ds board-$(CONFIG_DA923RC) := geip-da923rc diff --git a/arch/ppc/boards/freescale-p1010rdb/Makefile b/arch/ppc/boards/freescale-p1010rdb/Makefile new file mode 100644 index 0000000000..2a51091e14 --- /dev/null +++ b/arch/ppc/boards/freescale-p1010rdb/Makefile @@ -0,0 +1,4 @@ +obj-y += p1010rdb.o +obj-y += law.o +obj-y += tlb.o +obj-y += ddr.o
\ No newline at end of file diff --git a/arch/ppc/boards/freescale-p1010rdb/config.h b/arch/ppc/boards/freescale-p1010rdb/config.h new file mode 100644 index 0000000000..4f67183507 --- /dev/null +++ b/arch/ppc/boards/freescale-p1010rdb/config.h @@ -0,0 +1,58 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_CLK_FREQ 66666666 +#define CFG_DDR_CLK_FREQ 66666666 + +#define CFG_CHIP_SELECTS_PER_CTRL 1 + +/* + * Memory map + * + * 0x0000_0000 0x3fff_ffff DDR 1G cacheable + * + * Localbus non-cacheable + * 0xee0_0000 0xefff_ffff FLASH 32M non-cacheable + * 0xffb0_0000 0xffb0_0fff PIXIS 4K Cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_CCSRBAR_DEFAULT 0xff700000 +#define CFG_CCSRBAR 0xffe00000 +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR +#define CFG_IMMR CFG_CCSRBAR + +#define CFG_INIT_RAM_ADDR 0xffd00000 +#define CFG_INIT_RAM_SIZE 0x00004000 +#define CFG_INIT_BI_SIZE 0x00000100 +#define CFG_INIT_SP_OFFSET (CFG_INIT_RAM_SIZE - CFG_INIT_BI_SIZE) + +#define CFG_BOOT_BLOCK 0xe0000000 +#define CFG_BOOT_BLOCK_PHYS CFG_BOOT_BLOCK +#define CFG_FLASH_BASE 0xee000000 +#define CFG_FLASH_BASE_PHYS CFG_FLASH_BASE +#define CFG_CPLD_BASE 0xffb00000 +#define CFG_CPLD_BASE_PHYS CFG_CPLD_BASE + +#define CFG_IFC_CSPR0 (CSPR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | CSPR_MSEL_NOR | \ + CSPR_V) +#define CFG_IFC_CSOR0 CSOR_NOR_ADM_SHIFT(7) +#define CFG_IFC_AMASK0 IFC_AMASK(32*1024*1024) + +#endif /* __CONFIG_H */ diff --git a/arch/ppc/boards/freescale-p1010rdb/ddr.c b/arch/ppc/boards/freescale-p1010rdb/ddr.c new file mode 100644 index 0000000000..18069f4df1 --- /dev/null +++ b/arch/ppc/boards/freescale-p1010rdb/ddr.c @@ -0,0 +1,60 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <init.h> +#include <mach/fsl_i2c.h> +#include <mach/immap_85xx.h> +#include <mach/clock.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/fsl_lbc.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include "p1010rdb.h" + +static const u8 spd_addr = 0x52; + +int fsl_ddr_board_info(struct ddr_board_info_s *info) +{ + p1010rdb_early_init(); + + info->fsl_ddr_ver = 0; + info->ddr_base = IOMEM(MPC85xx_DDR_ADDR); + /* Actual number of chip select used */ + info->cs_per_ctrl = CFG_CHIP_SELECTS_PER_CTRL; + info->dimm_slots_per_ctrl = 1; + info->i2c_bus = 1; + info->i2c_slave = 0x7f; + info->i2c_speed = 400000; + info->i2c_base = IOMEM(I2C2_BASE_ADDR); + info->spd_i2c_addr = &spd_addr; + + return 0; +} + +void fsl_ddr_board_options(struct memctl_options_s *popts, + struct dimm_params_s *pdimm) +{ + popts->cs_local_opts[0].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[0].odt_wr_cfg = FSL_DDR_ODT_CS; + popts->cs_local_opts[0].odt_rtt_norm = DDR3_RTT_40_OHM; + popts->cs_local_opts[0].odt_rtt_wr = DDR3_RTT_OFF; + + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + popts->dll_rst_dis = 1; +} diff --git a/arch/ppc/boards/freescale-p1010rdb/env/bin/init b/arch/ppc/boards/freescale-p1010rdb/env/bin/init new file mode 100644 index 0000000000..c0e04c1f2d --- /dev/null +++ b/arch/ppc/boards/freescale-p1010rdb/env/bin/init @@ -0,0 +1,2 @@ +#!/bin/sh +source /env/config diff --git a/arch/ppc/boards/freescale-p1010rdb/env/config b/arch/ppc/boards/freescale-p1010rdb/env/config new file mode 100644 index 0000000000..bffd86882e --- /dev/null +++ b/arch/ppc/boards/freescale-p1010rdb/env/config @@ -0,0 +1,2 @@ +#!/bin/sh +export bootargs="root=/dev/nfs rw ip=bootp console=ttyS0,115200"
\ No newline at end of file diff --git a/arch/ppc/boards/freescale-p1010rdb/law.c b/arch/ppc/boards/freescale-p1010rdb/law.c new file mode 100644 index 0000000000..6edfbc2fb8 --- /dev/null +++ b/arch/ppc/boards/freescale-p1010rdb/law.c @@ -0,0 +1,24 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <asm/fsl_law.h> + +struct law_entry law_table[] = { + FSL_SET_LAW(CFG_BOOT_BLOCK_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), + FSL_SET_LAW(CFG_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/arch/ppc/boards/freescale-p1010rdb/p1010rdb.c b/arch/ppc/boards/freescale-p1010rdb/p1010rdb.c new file mode 100644 index 0000000000..5bae5849ca --- /dev/null +++ b/arch/ppc/boards/freescale-p1010rdb/p1010rdb.c @@ -0,0 +1,209 @@ +/* + * Copyright 2014 GE Intelligent Platforms, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <ns16550.h> +#include <net.h> +#include <types.h> +#include <i2c/i2c.h> +#include <partition.h> +#include <memory.h> +#include <asm/cache.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ifc.h> +#include <mach/mpc85xx.h> +#include <mach/mmu.h> +#include <mach/immap_85xx.h> +#include <mach/gianfar.h> +#include <mach/clock.h> +#include <mach/gpio.h> +#include <mach/early_udelay.h> +#include <of.h> + +static struct gfar_info_struct gfar_info[] = { + { + .phyaddr = 1, + .tbiana = 0, + .tbicr = 0, + .mdiobus_tbi = 0, + }, + { + .phyaddr = 0, + .tbiana = 0x1a0, + .tbicr = 0x9140, + .mdiobus_tbi = 1, + }, + { + .phyaddr = 2, + .tbiana = 0x1a0, + .tbicr = 0x9140, + .mdiobus_tbi = 2, + }, +}; + +struct i2c_platform_data i2cplat[] = { + { .bitrate = 400000, }, + { .bitrate = 400000, }, +}; + +void p1010rdb_early_init(void) +{ + void __iomem *ifc = IFC_BASE_ADDR; + void __iomem *gur = IOMEM(MPC85xx_GUTS_ADDR); + + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(ifc + FSL_IFC_GCR_OFFSET, + 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + + /* Erratum A003549 */ + setbits_be32(gur + MPC85xx_GUTS_PMUXCR_OFFSET, + MPC85xx_PMUXCR_LCLK_IFC_CS3); + + /* Update CS0 timings to access boot flash */ + set_ifc_ftim(IFC_CS0, IFC_FTIM0, FTIM0_NOR_TACSE(0x4) | + FTIM0_NOR_TEADC(0x5) | FTIM0_NOR_TEAHC(0x5)); + set_ifc_ftim(IFC_CS0, IFC_FTIM1, FTIM1_NOR_TACO(0x1e) | + FTIM1_NOR_TRAD_NOR(0x0f)); + set_ifc_ftim(IFC_CS0, IFC_FTIM2, FTIM2_NOR_TCS(0x4) | + FTIM2_NOR_TCH(0x4) | FTIM2_NOR_TWP(0x1c)); + set_ifc_ftim(IFC_CS0, IFC_FTIM3, 0); + + /* Map the CPLD */ + set_ifc_cspr(IFC_CS3, CSPR_PHYS_ADDR(CFG_CPLD_BASE_PHYS) | + CSPR_PORT_SIZE_8 | CSPR_MSEL_GPCM | CSPR_V); + set_ifc_csor(IFC_CS3, 0); + set_ifc_amask(IFC_CS3, IFC_AMASK(64*1024)); + set_ifc_ftim(IFC_CS3, IFC_FTIM0, FTIM0_GPCM_TACSE(0xe) | + FTIM0_GPCM_TEADC(0x0e) | FTIM0_GPCM_TEAHC(0x0e)); + set_ifc_ftim(IFC_CS3, IFC_FTIM1, FTIM1_GPCM_TACO(0x1e) | + FTIM1_GPCM_TRAD(0x0f)); + set_ifc_ftim(IFC_CS3, IFC_FTIM2, FTIM2_GPCM_TCS(0xe) | + FTIM2_GPCM_TCH(0) | FTIM2_GPCM_TWP(0x1f)); + set_ifc_ftim(IFC_CS3, IFC_FTIM3, 0); + + /* PCIe reset through GPIO 4 */ + gpio_direction_output(4, 1); +} + +static void board_eth_init(void) +{ + fsl_eth_init(1, &gfar_info[0]); + fsl_eth_init(2, &gfar_info[1]); + fsl_eth_init(3, &gfar_info[2]); +} + +static int p1010rdb_devices_init(void) +{ + add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 32 << 20, 0); + devfs_add_partition("nor0", 0x1f80000, 0x80000, DEVFS_PARTITION_FIXED, + "self0"); + devfs_add_partition("nor0", 0x1f60000, 0x10000, DEVFS_PARTITION_FIXED, + "env0"); + add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, 0x100, + IORESOURCE_MEM, &i2cplat[0]); + add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, 0x100, + IORESOURCE_MEM, &i2cplat[1]); + board_eth_init(); + + return 0; +} + +device_initcall(p1010rdb_devices_init); + +static struct NS16550_plat serial_plat = { + .clock = 0, + .shift = 0, +}; + +static int p1010rdb_console_init(void) +{ + barebox_set_model("Freescale P1010RDB"); + barebox_set_hostname("p1010rdb"); + + serial_plat.clock = fsl_get_bus_freq(0); + add_ns16550_device(1, CFG_IMMR + 0x4500, 16, + IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat); + return 0; +} + +console_initcall(p1010rdb_console_init); + +static int p1010rdb_mem_init(void) +{ + barebox_add_memory_bank("ram0", 0x0, fsl_get_effective_memsize()); + return 0; +} + +mem_initcall(p1010rdb_mem_init); + +static int p1010rdb_board_init_r(void) +{ + const uint32_t flashbase = CFG_BOOT_BLOCK; + const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1); + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + e500_disable_tlb(flash_esel); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + e500_set_tlb(1, flashbase, CFG_BOOT_BLOCK_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + fsl_l2_cache_init(); + + return 0; +} + +core_initcall(p1010rdb_board_init_r); + +static int fdt_board_setup(struct device_node *blob, void *unused) +{ + struct device_node *node; + + node = of_find_compatible_node(blob, NULL, "fsl,esdhc"); + if (node) + of_delete_node(node); + + node = of_find_compatible_node(blob, NULL, "fsl,starlite-tdm"); + if (node) + of_delete_node(node); + + node = of_find_compatible_node(blob, NULL, "fsl,p1010-flexcan"); + if (node) + of_delete_node(node); + + node = of_find_compatible_node(blob, NULL, "fsl,p1010-flexcan"); + if (node) + of_delete_node(node); + + return 0; +} + +static int of_register_p1010rdb_fixup(void) +{ + return of_register_fixup(fdt_board_setup, NULL); +} +late_initcall(of_register_p1010rdb_fixup); diff --git a/arch/ppc/boards/freescale-p1010rdb/p1010rdb.h b/arch/ppc/boards/freescale-p1010rdb/p1010rdb.h new file mode 100644 index 0000000000..f325ff48fd --- /dev/null +++ b/arch/ppc/boards/freescale-p1010rdb/p1010rdb.h @@ -0,0 +1,14 @@ +/* + * Copyright 2014 GE Intelligent Platforms, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +void p1010rdb_early_init(void); diff --git a/arch/ppc/boards/freescale-p1010rdb/tlb.c b/arch/ppc/boards/freescale-p1010rdb/tlb.c new file mode 100644 index 0000000000..23ef0f2ade --- /dev/null +++ b/arch/ppc/boards/freescale-p1010rdb/tlb.c @@ -0,0 +1,59 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <mach/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (4 * 1024), + CFG_INIT_RAM_ADDR + (4 * 1024), + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (8 * 1024), + CFG_INIT_RAM_ADDR + (8 * 1024), + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (12 * 1024), + CFG_INIT_RAM_ADDR + (12 * 1024), + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + FSL_SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + FSL_SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + FSL_SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK_PHYS, + MAS3_SX | MAS3_SR, MAS2_M | MAS2_W | MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + FSL_SET_TLB_ENTRY(1, CFG_CPLD_BASE, CFG_CPLD_BASE_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_128K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/arch/ppc/boards/geip-da923rc/product_data.c b/arch/ppc/boards/geip-da923rc/product_data.c index 09cd84d930..0c4600611a 100644 --- a/arch/ppc/boards/geip-da923rc/product_data.c +++ b/arch/ppc/boards/geip-da923rc/product_data.c @@ -20,12 +20,20 @@ #include <mach/fsl_i2c.h> #include "product_data.h" +static int ge_pd_header_check(unsigned short header) +{ + if (header != 0xa5a5) + return -1; + else + return 0; +} + static int ge_is_data_valid(struct ge_product_data *v) { int crc, ret = 0; const unsigned char *p = (const unsigned char *)v; - if (v->v1.pdh.tag != 0xa5a5) + if (ge_pd_header_check(v->v1.pdh.tag)) return -1; switch (v->v1.pdh.version) { @@ -51,12 +59,20 @@ int ge_get_product_data(struct ge_product_data *productp) { struct i2c_adapter *adapter; struct i2c_client client; + unsigned int width = 0; int ret; adapter = i2c_get_adapter(0); client.addr = 0x51; client.adapter = adapter; ret = i2c_read_reg(&client, 0, (uint8_t *) productp, + sizeof(unsigned short)); + + /* If there is no valid header, it may be a 16-bit eeprom. */ + if (ge_pd_header_check(productp->v1.pdh.tag)) + width = I2C_ADDR_16_BIT; + + ret = i2c_read_reg(&client, width, (uint8_t *) productp, sizeof(struct ge_product_data)); if (ret == sizeof(struct ge_product_data)) diff --git a/arch/ppc/configs/p1010rdb_defconfig b/arch/ppc/configs/p1010rdb_defconfig new file mode 100644 index 0000000000..d193940d46 --- /dev/null +++ b/arch/ppc/configs/p1010rdb_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARCH_MPC85XX=y +CONFIG_P1010RDB=y +CONFIG_P101010=y +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_BOOTM_ZLIB=y +CONFIG_CMD_BOOTM_BZLIB=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_ZLIB=y +CONFIG_BZLIB=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_RESET=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_GO=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=n +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/ppc/boards/freescale-p1010rdb/env/" +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_DRIVER_CFI=y +CONFIG_DRIVER_CFI_AMD=y +CONFIG_DRIVER_CFI_INTEL=y +CONFIG_DRIVER_CFI_BANK_WIDTH_1=n +CONFIG_DRIVER_CFI_BANK_WIDTH_2=y +CONFIG_DRIVER_CFI_BANK_WIDTH_4=n +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_MTD_WRITE=y +CONFIG_MALLOC_SIZE=0x4000000 +CONFIG_BAUDRATE=115200 +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_RELOCATABLE=y +CONFIG_DRIVER_NET_GIANFAR=y +CONFIG_NET=y +CONFIG_NET_PING=y +CONFIG_FS_TFTP=y +CONFIG_NET_TFTP=y +CONFIG_CMD_TFTP=y +CONFIG_PING=y +CONFIG_I2C=y +CONFIG_I2C_IMX=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_EXPORT=y +CONFIG_OFTREE=y +CONFIG_CMD_OFTREE_PROBE=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMTEST=y diff --git a/arch/ppc/cpu-85xx/start.S b/arch/ppc/cpu-85xx/start.S index 514fd8c516..82c2c0ad8c 100644 --- a/arch/ppc/cpu-85xx/start.S +++ b/arch/ppc/cpu-85xx/start.S @@ -105,6 +105,29 @@ _start_e500: isync .endm + .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high \ + scratch + lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h + ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l + mtspr MAS0, \scratch + lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h + ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l + mtspr MAS1, \scratch + lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h + ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l + mtspr MAS2, \scratch + lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h + ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l + mtspr MAS3, \scratch + lis \scratch, \phy_high@h + ori \scratch, \scratch, \phy_high@l + mtspr MAS7, \scratch + isync + msync + tlbwe + isync + .endm + /* Setup interrupt vectors */ lis r1,TEXT_BASE@h mtspr IVPR,r1 @@ -278,6 +301,89 @@ nexti: mflr r1 /* R1 = our PC */ 0, r6 #endif +/* + * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default + * location is not where we want it. This typically happens on a 36-bit + * system, where we want to move CCSR to near the top of 36-bit address space. + * + * To move CCSR, we create two temporary TLBs, one for the old location, and + * another for the new location. On CoreNet systems, we also need to create + * a special, temporary LAW. + * + * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for + * long-term TLBs, so we use TLB0 here. + */ +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) +create_ccsr_new_tlb: + /* + * Create a TLB for the new location of CCSR. Register R8 is reserved + * for the virtual address of this TLB (CFG_CCSRBAR). + */ + lis r8, CFG_CCSRBAR@h + ori r8, r8, CFG_CCSRBAR@l + lis r9, (CFG_CCSRBAR + 0x1000)@h + ori r9, r9, (CFG_CCSRBAR + 0x1000)@l + create_tlb0_entry 0, \ + 0, BOOKE_PAGESZ_4K, \ + CFG_CCSRBAR, MAS2_I|MAS2_G, \ + CFG_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, \ + 0, r3 + + /* + * Create a TLB for the current location of CCSR. Register R9 is + * reserved for the virtual address of this TLB (CFG_CCSRBAR + 0x1000). + */ +create_ccsr_old_tlb: + create_tlb0_entry 1, \ + 0, BOOKE_PAGESZ_4K, \ + CFG_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ + CFG_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ + 0, r3 + + /* + * We have a TLB for what we think is the current (old) CCSR. Let's + * verify that, otherwise we won't be able to move it. + * CFG_CCSRBAR_DEFAULT is always a 32-bit number, so we only + * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. + */ +verify_old_ccsr: + lis r0, CFG_CCSRBAR_DEFAULT@h + ori r0, r0, CFG_CCSRBAR_DEFAULT@l + lwz r1, 0(r9) + slwi r1, r1, 12 + cmpl 0, r0, r1 + + /* + * If the value we read from CCSRBAR is not what we expect, then + * enter an infinite loop. This will at least allow a debugger to + * halt execution and examine TLBs, etc. There's no point in going + * on. + */ +infinite_debug_loop: + bne infinite_debug_loop + + /* + * Read the current value of CCSRBAR using a load word instruction + * followed by an isync. This forces all accesses to configuration + * space to complete. + */ +write_new_ccsrbar: + sync + lwz r0, 0(r9) + isync + lis r0, (CFG_CCSRBAR_PHYS >> 12)@h + ori r0, r0, (CFG_CCSRBAR_PHYS >> 12)@l + stw r0, 0(r9) + sync + isync + + /* + * Read the contents of CCSRBAR from its new location, followed by + * another isync. + */ + lwz r0, 0(r8) + isync +#endif /* Enable/invalidate the I-Cache */ lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h diff --git a/arch/ppc/include/asm/bitops.h b/arch/ppc/include/asm/bitops.h index eea9e0c430..c4ed2de65f 100644 --- a/arch/ppc/include/asm/bitops.h +++ b/arch/ppc/include/asm/bitops.h @@ -153,6 +153,11 @@ extern __inline__ int ffz(unsigned int x) return __ilog2(x & -x); } +static __inline__ int __ffs(unsigned long x) +{ + return __ilog2(x & -x); +} + /* * fls: find last (most-significant) bit set. * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. @@ -182,49 +187,7 @@ extern __inline__ int ffs(int x) #endif /* __KERNEL__ */ -/* - * This implementation of find_{first,next}_zero_bit was stolen from - * Linus' asm-alpha/bitops.h. - */ -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) - -extern __inline__ unsigned long find_next_zero_bit(void * addr, - unsigned long size, unsigned long offset) -{ - unsigned int * p = ((unsigned int *) addr) + (offset >> 5); - unsigned int result = offset & ~31UL; - unsigned int tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *p++; - tmp |= ~0UL >> (32-offset); - if (size < 32) - goto found_first; - if (tmp != ~0U) - goto found_middle; - size -= 32; - result += 32; - } - while (size >= 32) { - if ((tmp = *p++) != ~0U) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; -found_first: - tmp |= ~0UL << size; -found_middle: - return result + ffz(tmp); -} - +#include <asm-generic/bitops/find.h> #define _EXT2_HAVE_ASM_BITOPS_ diff --git a/arch/ppc/include/asm/fsl_ifc.h b/arch/ppc/include/asm/fsl_ifc.h new file mode 100644 index 0000000000..8faff75033 --- /dev/null +++ b/arch/ppc/include/asm/fsl_ifc.h @@ -0,0 +1,267 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat <dipen.dudhat@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_IFC_H +#define __FSL_IFC_H + +#include <config.h> +#include <common.h> + +/* Big-Endian */ +#define ifc_in32(a) in_be32(a) +#define ifc_out32(a, v) out_be32(a, v) +#define ifc_in16(a) in_be16(a) + +/* + * CSPR - Chip Select Property Register + */ +#define CSPR_BA 0xFFFF0000 +#define CSPR_BA_SHIFT 16 +#define CSPR_PORT_SIZE 0x00000180 +#define CSPR_PORT_SIZE_SHIFT 7 +#define CSPR_PORT_SIZE_8 0x00000080 +#define CSPR_PORT_SIZE_16 0x00000100 +#define CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define CSPR_WP 0x00000040 +#define CSPR_WP_SHIFT 6 +#define CSPR_MSEL 0x00000006 +#define CSPR_MSEL_SHIFT 1 +#define CSPR_MSEL_NOR 0x00000000 +#define CSPR_MSEL_NAND 0x00000002 +#define CSPR_MSEL_GPCM 0x00000004 +#define CSPR_V 0x00000001 +#define CSPR_V_SHIFT 0 + +/* Convert an address into the right format for the CSPR Registers */ +#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (__ilog2(n) - IFC_AMASK_SHIFT)) + +/* + * Chip Select Option Register IFC_NAND Machine + */ +#define CSOR_NAND_ECC_ENC_EN 0x80000000 +#define CSOR_NAND_ECC_MODE_MASK 0x30000000 +/* 4 bit correction per 520 Byte sector */ +#define CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define CSOR_NAND_ECC_MODE_8 0x10000000 +#define CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define CSOR_NAND_RAL_MASK 0x01800000 +#define CSOR_NAND_RAL_SHIFT 20 +#define CSOR_NAND_RAL_1 0x00000000 +#define CSOR_NAND_RAL_2 0x00800000 +#define CSOR_NAND_RAL_3 0x01000000 +#define CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define CSOR_NAND_PGS_MASK 0x00180000 +#define CSOR_NAND_PGS_SHIFT 16 +#define CSOR_NAND_PGS_512 0x00000000 +#define CSOR_NAND_PGS_2K 0x00080000 +#define CSOR_NAND_PGS_4K 0x00100000 +#define CSOR_NAND_PGS_8K 0x00180000 +/* Spare region Size */ +#define CSOR_NAND_SPRZ_MASK 0x0000E000 +#define CSOR_NAND_SPRZ_SHIFT 13 +#define CSOR_NAND_SPRZ_16 0x00000000 +#define CSOR_NAND_SPRZ_64 0x00002000 +#define CSOR_NAND_SPRZ_128 0x00004000 +#define CSOR_NAND_SPRZ_210 0x00006000 +#define CSOR_NAND_SPRZ_218 0x00008000 +#define CSOR_NAND_SPRZ_224 0x0000A000 +#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 +/* Pages Per Block */ +#define CSOR_NAND_PB_MASK 0x00000700 +#define CSOR_NAND_PB_SHIFT 8 +#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NAND_TRHZ_MASK 0x0000001C +#define CSOR_NAND_TRHZ_SHIFT 2 +#define CSOR_NAND_TRHZ_20 0x00000000 +#define CSOR_NAND_TRHZ_40 0x00000004 +#define CSOR_NAND_TRHZ_60 0x00000008 +#define CSOR_NAND_TRHZ_80 0x0000000C +#define CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NAND_BCTLD 0x00000001 + +/* + * Chip Select Option Register - NOR Flash Mode + */ +/* Enable Address shift Mode */ +#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define CSOR_NOR_ADM_MASK 0x0003E000 +#define CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) +/* Type of the NOR device hooked */ +#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NOR_TRHZ_MASK 0x0000001C +#define CSOR_NOR_TRHZ_SHIFT 2 +#define CSOR_NOR_TRHZ_20 0x00000000 +#define CSOR_NOR_TRHZ_40 0x00000004 +#define CSOR_NOR_TRHZ_60 0x00000008 +#define CSOR_NOR_TRHZ_80 0x0000000C +#define CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NOR_BCTLD 0x00000001 + +/* + * Flash Timing Registers (FTIM0 - FTIM2_CSn) + */ + +/* + * FTIM0 - NOR Flash Mode + */ +#define FTIM0_NOR 0xF03F3F3F +#define FTIM0_NOR_TACSE_SHIFT 28 +#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) +#define FTIM0_NOR_TEADC_SHIFT 16 +#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) +#define FTIM0_NOR_TAVDS_SHIFT 8 +#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) +#define FTIM0_NOR_TEAHC_SHIFT 0 +#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) +/* + * FTIM1 - NOR Flash Mode + */ +#define FTIM1_NOR 0xFF003F3F +#define FTIM1_NOR_TACO_SHIFT 24 +#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) +#define FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) +#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) +/* + * FTIM2 - NOR Flash Mode + */ +#define FTIM2_NOR 0x0F3CFCFF +#define FTIM2_NOR_TCS_SHIFT 24 +#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) +#define FTIM2_NOR_TCH_SHIFT 18 +#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) +#define FTIM2_NOR_TWPH_SHIFT 10 +#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) +#define FTIM2_NOR_TWP_SHIFT 0 +#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) + +/* + * FTIM0 - Normal GPCM Mode + */ +#define FTIM0_GPCM 0xF03F3F3F +#define FTIM0_GPCM_TACSE_SHIFT 28 +#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) +#define FTIM0_GPCM_TEADC_SHIFT 16 +#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) +#define FTIM0_GPCM_TAVDS_SHIFT 8 +#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) +#define FTIM0_GPCM_TEAHC_SHIFT 0 +#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) +/* + * FTIM1 - Normal GPCM Mode + */ +#define FTIM1_GPCM 0xFF003F00 +#define FTIM1_GPCM_TACO_SHIFT 24 +#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) +#define FTIM1_GPCM_TRAD_SHIFT 8 +#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) +/* + * FTIM2 - Normal GPCM Mode + */ +#define FTIM2_GPCM 0x0F3C00FF +#define FTIM2_GPCM_TCS_SHIFT 24 +#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) +#define FTIM2_GPCM_TCH_SHIFT 18 +#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) +#define FTIM2_GPCM_TWP_SHIFT 0 +#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) + +/* + * General Control Register (GCR) + */ +#define IFC_GCR_MASK 0x8000F800 +/* reset all IFC hardware */ +#define IFC_GCR_SOFT_RST_ALL 0x80000000 +/* Turnaroud Time of external buffer */ +#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 +#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 + +/* + * Clock Control Register (CCR) + */ +#define IFC_CCR_MASK 0x0F0F8800 +/* Clock division ratio */ +#define IFC_CCR_CLK_DIV_MASK 0x0F000000 +#define IFC_CCR_CLK_DIV_SHIFT 24 +#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) +/* IFC Clock Delay */ +#define IFC_CCR_CLK_DLY_MASK 0x000F0000 +#define IFC_CCR_CLK_DLY_SHIFT 16 +#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) + +#ifndef __ASSEMBLY__ +#include <asm/io.h> + +#define IFC_BASE_ADDR ((void __iomem *)IFC_ADDR) +#define FSL_IFC_CSPRX(i) (0x10 + ((i) * 0xc)) +#define FSL_IFC_CSORX(i) (0x130 + ((i) * 0xc)) +#define FSL_IFC_AMASKX(i) (0xa0 + ((i) * 0xc)) +#define FSL_IFC_CSX_FTIMY(i, j) ((0x1c0 + ((i) * 0x30)) + ((j) * 4)) + +#define get_ifc_cspr(i) (ifc_in32(IFC_BASE_ADDR + FSL_IFC_CSPRX(i))) +#define get_ifc_csor(i) (ifc_in32(IFC_BASE_ADDR + FSL_IFC_CSORX(i)) +#define get_ifc_amask(i) (ifc_in32(IFC_BASE_ADDR + FSL_IFC_AMASKX(i))) +#define get_ifc_ftim(i, j) (ifc_in32(IFC_BASE_ADDR + FSL_IFC_CSX_FTIMY(i, j))) + +#define set_ifc_cspr(i, v) (ifc_out32(IFC_BASE_ADDR + FSL_IFC_CSPRX(i), v)) +#define set_ifc_csor(i, v) (ifc_out32(IFC_BASE_ADDR + FSL_IFC_CSORX(i), v)) +#define set_ifc_amask(i, v) (ifc_out32(IFC_BASE_ADDR + FSL_IFC_AMASKX(i), v)) +#define set_ifc_ftim(i, j, v) \ + (ifc_out32(IFC_BASE_ADDR + FSL_IFC_CSX_FTIMY(i, j), v)) + +#define FSL_IFC_GCR_OFFSET 0x40c +#define FSL_IFC_CCR_OFFSET 0x44c + +enum ifc_chip_sel { + IFC_CS0, + IFC_CS1, + IFC_CS2, + IFC_CS3, + IFC_CS4, + IFC_CS5, + IFC_CS6, + IFC_CS7, +}; + +enum ifc_ftims { + IFC_FTIM0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +}; + +#ifdef CONFIG_FSL_ERRATUM_IFC_A002769 +#undef CSPR_MSEL_NOR +#define CSPR_MSEL_NOR CSPR_MSEL_GPCM +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __FSL_IFC_H */ diff --git a/arch/ppc/include/asm/fsl_law.h b/arch/ppc/include/asm/fsl_law.h index 813a8ee0b3..7acb63c9de 100644 --- a/arch/ppc/include/asm/fsl_law.h +++ b/arch/ppc/include/asm/fsl_law.h @@ -69,6 +69,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO +#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC #if defined(CONFIG_P2020) diff --git a/arch/ppc/include/asm/processor.h b/arch/ppc/include/asm/processor.h index c9633fe507..e8a9c1402c 100644 --- a/arch/ppc/include/asm/processor.h +++ b/arch/ppc/include/asm/processor.h @@ -851,7 +851,7 @@ #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ /* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit */ #define IS_E_PROCESSOR(svr) ((svr) & 0x80000) /* @@ -867,6 +867,7 @@ #define SVR_8641 0x8090 #define SVR_8544 0x803401 #define SVR_8544_E 0x803C01 +#define SVR_P1010 0x80F100 #define SVR_P1022 0x80E600 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 diff --git a/arch/ppc/mach-mpc85xx/Kconfig b/arch/ppc/mach-mpc85xx/Kconfig index ec5f04ca30..e29be9c19e 100644 --- a/arch/ppc/mach-mpc85xx/Kconfig +++ b/arch/ppc/mach-mpc85xx/Kconfig @@ -5,17 +5,17 @@ config MMU config BTB bool - default y if P2020RDB || P1022DS || DA923RC + default y config TEXT_BASE hex - default 0xeff80000 if P2020RDB || P1022DS + default 0xeff80000 if P1010RDB || P2020RDB || P1022DS default 0xfff80000 if DA923RC config RESET_VECTOR_ADDRESS hex default 0xfffffffc if DA923RC - default 0xeffffffc if P2020RDB || P1022DS + default 0xeffffffc if P1010RDB || P2020RDB || P1022DS config MPC85xx bool @@ -31,55 +31,78 @@ config E500 choice prompt "Select your board" +config P1010RDB + bool "P1010RDB" + select P1010 + select DDR_SPD + select FSL_DDR3 + help + Say Y here if you are using the Freescale P1010RDB config P2020RDB bool "P2020RDB" + select P2020 + select FSL_ELBC help Say Y here if you are using the Freescale P2020RDB config P1022DS bool "P1022DS" + select P1022 + select DDR_SPD + select FSL_DDR3 + select FSL_ELBC help Say Y here if you are using the Freescale P1022DS config DA923RC bool "DA923RC" + select MPC8544 + select DDR_SPD + select FSL_DDR2 help Say Y here if you are using the GE Intelligent Platforms DA923RC endchoice endif -config FSL_ELBC - bool - default y if P2020RDB || P1022DS - -config DDR_SPD +config P1010 + select FSL_IFC + select FSL_ERRATUM_IFC_A002769 + select FSL_ERRATUM_P1010_A003549 + select FSL_ERRATUM_IFC_A003399 bool - select CRC16 - default y if DA923RC || P1022DS -if P2020RDB config P2020 bool - default y -endif -if P1022DS config P1022 bool - default y -config FSL_DDR3 +config MPC8544 bool - default y -endif -if DA923RC -config MPC8544 +config DDR_SPD bool - default y + select CRC16 config FSL_DDR2 bool - default y -endif + +config FSL_DDR3 + bool + +config FSL_IFC + bool + +config FSL_ELBC + bool + +config FSL_ERRATUM_IFC_A002769 + bool + +config FSL_ERRATUM_IFC_A003399 + bool + +config FSL_ERRATUM_P1010_A003549 + bool + diff --git a/arch/ppc/mach-mpc85xx/cpu_init.c b/arch/ppc/mach-mpc85xx/cpu_init.c index 7b50cef5c4..003a5f15b4 100644 --- a/arch/ppc/mach-mpc85xx/cpu_init.c +++ b/arch/ppc/mach-mpc85xx/cpu_init.c @@ -27,29 +27,111 @@ #include <common.h> #include <init.h> #include <asm/processor.h> +#include <asm/cache.h> #include <asm/fsl_law.h> +#include <asm/fsl_ifc.h> #include <mach/mpc85xx.h> #include <mach/mmu.h> #include <mach/immap_85xx.h> -static void fsl_setup_ccsrbar(void) +/* NOR workaround for P1010 erratum A003399 */ +#if defined(CONFIG_FSL_ERRATUM_P1010_A003549) +#define SRAM_BASE_ADDR 0x100 +void setup_ifc(void) { - u32 temp; u32 mas0, mas1, mas2, mas3, mas7; - u32 *ccsr_virt = (u32 *)(CFG_CCSRBAR + 0x1000); - - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); - mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); - mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR + 0x1000, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CFG_CCSRBAR_DEFAULT); + phys_addr_t flash_phys = CFG_FLASH_BASE_PHYS; + + /* + * Adjust the TLB we were running out of to match the phys addr of the + * chip select we are adjusting and will return to. + */ + flash_phys += (~CFG_IFC_AMASK0) + 1 - 4*1024*1024; + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | + MAS1_TSIZE(BOOKE_PAGESZ_4M); + mas2 = FSL_BOOKE_MAS2(CONFIG_TEXT_BASE, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); + mas7 = FSL_BOOKE_MAS7(flash_phys); + mtspr(MAS0, mas0); + mtspr(MAS1, mas1); + mtspr(MAS2, mas2); + mtspr(MAS3, mas3); + mtspr(MAS7, mas7); + asm volatile("isync;msync;tlbwe;isync"); + +#if defined(PPC_E500_DEBUG_TLB) + /* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is + * changed to 0. A TLB entry (in AS0) is required to handle + * debug exception generated * in AS1. + * + * TLB entry is created for IVPR + IVOR15 to map on valid OP + * code address because flash's physical address is going to + * change as CFG_FLASH_BASE_PHYS. + */ + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(PPC_E500_DEBUG_TLB); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT | + MAS1_TSIZE(BOOKE_PAGESZ_4M); + mas2 = FSL_BOOKE_MAS2(CONFIG_TEXT_BASE, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); + mas7 = FSL_BOOKE_MAS7(flash_phys); + + mtspr(MAS0, mas0); + mtspr(MAS1, mas1); + mtspr(MAS2, mas2); + mtspr(MAS3, mas3); + mtspr(MAS7, mas7); + + asm volatile("isync;msync;tlbwe;isync"); +#endif + set_ifc_cspr(0, CFG_IFC_CSPR0); + set_ifc_csor(0, CFG_IFC_CSOR0); + set_ifc_amask(0, CFG_IFC_AMASK0); +} +void fsl_erratum_ifc_a003399(void) +{ + u32 mas0, mas1, mas2, mas3, mas7; + void __iomem *l2cache = IOMEM(MPC85xx_L2_ADDR); + void (*setup_ifc_sram)(void) = (void *)SRAM_BASE_ADDR; + u32 *dst, *src, ix; + + /* TLB for SRAM */ + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | + MAS1_TSIZE(BOOKE_PAGESZ_1M); + mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I); + mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, + MAS3_SX | MAS3_SW | MAS3_SR); + mas7 = FSL_BOOKE_MAS7(0); e500_write_tlb(mas0, mas1, mas2, mas3, mas7); - temp = in_be32(ccsr_virt); - out_be32(ccsr_virt, CFG_CCSRBAR_PHYS >> 12); - temp = in_be32((u32 *)CFG_CCSRBAR); + out_be32(l2cache + MPC85xx_L2_L2SRBAR0_OFFSET, SRAM_BASE_ADDR); + out_be32(l2cache + MPC85xx_L2_L2ERRDIS_OFFSET, + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + out_be32(l2cache + MPC85xx_L2_CTL_OFFSET, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + /* + * Copy the code in setup_ifc to L2SRAM. Do a word copy + * because NOR Flash on P1010 does not support byte + * access (Erratum IFC-A002769) + */ + dst = (u32 *) SRAM_BASE_ADDR; + src = (u32 *) setup_ifc; + for (ix = 0; ix < 1024; ix++) + *dst++ = *src++; + setup_ifc_sram(); + + clrbits_be32(l2cache + MPC85xx_L2_CTL_OFFSET, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + out_be32(l2cache + MPC85xx_L2_L2SRBAR0_OFFSET, 0x0); } +#else +void fsl_erratum_ifc_a003399(void) {} +#endif int fsl_l2_cache_init(void) { @@ -93,23 +175,35 @@ int fsl_l2_cache_init(void) return 0; } +#if defined(CONFIG_FSL_ERRATUM_P1010_A003549) +void fsl_erratum_p1010_a003549(void) +{ + void __iomem *guts = IOMEM(MPC85xx_GUTS_ADDR); + + setbits_be32(guts + MPC85xx_GUTS_PMUXCR_OFFSET, + MPC85xx_PMUXCR_LCLK_IFC_CS3); +} +#else +void fsl_erratum_p1010_a003549(void) {} +#endif + void cpu_init_early_f(void) { u32 mas0, mas1, mas2, mas3, mas7; - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); - mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); - mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | + MAS1_TSIZE(BOOKE_PAGESZ_1M); + mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR, MAS2_I | MAS2_G); + mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_PHYS, 0, MAS3_SW | MAS3_SR); mas7 = FSL_BOOKE_MAS7(CFG_CCSRBAR_PHYS); e500_write_tlb(mas0, mas1, mas2, mas3, mas7); - /* set up CCSR if we want it moved */ - if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) - fsl_setup_ccsrbar(); - + fsl_erratum_p1010_a003549(); fsl_init_laws(); + fsl_erratum_ifc_a003399(); + e500_invalidate_tlb(1); e500_init_tlbs(); } diff --git a/arch/ppc/mach-mpc85xx/cpuid.c b/arch/ppc/mach-mpc85xx/cpuid.c index 21892e3ff1..1f54a2b1c9 100644 --- a/arch/ppc/mach-mpc85xx/cpuid.c +++ b/arch/ppc/mach-mpc85xx/cpuid.c @@ -29,6 +29,7 @@ struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(8544, 8544, 1), CPU_TYPE_ENTRY(8544, 8544_E, 1), + CPU_TYPE_ENTRY(P1010, P1010, 1), CPU_TYPE_ENTRY(P1022, P1022, 2), CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P2020, P2020_E, 2), diff --git a/arch/ppc/mach-mpc85xx/fsl_gpio.c b/arch/ppc/mach-mpc85xx/fsl_gpio.c index ca6305ad7c..468c780ff8 100644 --- a/arch/ppc/mach-mpc85xx/fsl_gpio.c +++ b/arch/ppc/mach-mpc85xx/fsl_gpio.c @@ -44,4 +44,23 @@ void gpio_set_value(unsigned gpio, int val) gpoutdr &= ~MPC85xx_GPIOBIT(gpio); out_be32(gpout, gpoutdr); } +#else +int gpio_direction_output(unsigned gpio, int val) +{ + void __iomem *gpior = IOMEM(MPC85xx_GPIO_ADDR); + + if (gpio >= 16) + return -EINVAL; + + if (val) + setbits_be32(gpior + MPC85xx_GPIO_GPDAT_OFFSET, + 1 << (32 - gpio)); + else + clrbits_be32(gpior + MPC85xx_GPIO_GPDAT_OFFSET, + 1 << (32 - gpio)); + + setbits_be32(gpior + MPC85xx_GPIO_GPDIR_OFFSET, 1 << (32 - gpio)); + + return 0; +} #endif diff --git a/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h b/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h index f9d8299b6d..fad2c47d11 100644 --- a/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h +++ b/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h @@ -48,6 +48,15 @@ #define FSL_TSECV2 #define FSL_ERRATUM_A005125 +#elif defined(CONFIG_P1010) +#define MAX_CPUS 1 +#define FSL_NUM_LAWS 12 +#define FSL_NUM_TSEC 3 +#define FSL_SEC_COMPAT 4 +#define FSL_ERRATUM_A005125 +#define PPC_E500_DEBUG_TLB 2 +#define FSL_TSECV2 + #else #error Processor type not defined for this platform #endif diff --git a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h index 87bc5c7c63..abcdb5c1e0 100644 --- a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h +++ b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h @@ -26,6 +26,7 @@ #include <asm/types.h> #include <asm/fsl_lbc.h> +#include <asm/fsl_ifc.h> #include <asm/config.h> #define MPC85xx_LOCAL_OFFSET 0x0000 @@ -35,6 +36,7 @@ #define MPC85xx_PCI1_OFFSET 0x8000 #define MPC85xx_GPIO_OFFSET 0xf000 +#define MPC85xx_IFC_OFFSET 0x1e000 #define MPC85xx_L2_OFFSET 0x20000 #ifdef FSL_TSECV2 #define TSEC1_OFFSET 0xB0000 @@ -50,6 +52,7 @@ #define MPC85xx_GUTS_ADDR (CFG_IMMR + MPC85xx_GUTS_OFFSET) #define MPC85xx_DDR_ADDR (CFG_IMMR + MPC85xx_DDR_OFFSET) #define LBC_ADDR (CFG_IMMR + MPC85xx_LBC_OFFSET) +#define IFC_ADDR (CFG_IMMR + MPC85xx_IFC_OFFSET) #define MPC85xx_GPIO_ADDR (CFG_IMMR + MPC85xx_GPIO_OFFSET) #define MPC85xx_L2_ADDR (CFG_IMMR + MPC85xx_L2_OFFSET) #define MPC8xxx_PIC_ADDR (CFG_IMMR + MPC85xx_PIC_OFFSET) @@ -152,8 +155,13 @@ /* * L2 Cache Register Offsets */ -#define MPC85xx_L2_CTL_OFFSET 0x0 /* L2 configuration 0 */ -#define MPC85xx_L2CTL_L2E 0x80000000 +#define MPC85xx_L2_CTL_OFFSET 0x0 /* L2 configuration 0 */ +#define MPC85xx_L2CTL_L2E 0x80000000 +#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 +#define MPC85xx_L2_L2SRBAR0_OFFSET 0x100 +#define MPC85xx_L2_L2ERRDIS_OFFSET 0xe44 +#define MPC85xx_L2ERRDIS_MBECC 0x00000008 +#define MPC85xx_L2ERRDIS_SBECC 0x00000004 /* PIC registers offsets */ #define MPC85xx_PIC_WHOAMI_OFFSET 0x090 @@ -174,6 +182,7 @@ #define MPC85xx_GUTS_PORDEVSR2_OFFSET 0x14 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 #define MPC85xx_GUTS_PMUXCR_OFFSET 0x60 +#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 #define MPC85xx_GUTS_PMUXCR2_OFFSET 0x64 #define MPC85xx_GUTS_DEVDISR_OFFSET 0x70 #define MPC85xx_DEVDISR_TB0 0x00004000 diff --git a/arch/ppc/mach-mpc85xx/speed.c b/arch/ppc/mach-mpc85xx/speed.c index eb9d725dd4..610949443c 100644 --- a/arch/ppc/mach-mpc85xx/speed.c +++ b/arch/ppc/mach-mpc85xx/speed.c @@ -33,8 +33,7 @@ void fsl_get_sys_info(struct sys_info *sysInfo) { void __iomem *gur = (void __iomem *)(MPC85xx_GUTS_ADDR); - uint plat_ratio, e500_ratio, half_freqSystemBus; - uint lcrr_div; + uint plat_ratio, e500_ratio, half_freqSystemBus, lcrr_div, ccr; int i; plat_ratio = in_be32(gur + MPC85xx_GUTS_PORPLLSR_OFFSET) & 0x0000003e; @@ -65,22 +64,39 @@ void fsl_get_sys_info(struct sys_info *sysInfo) } #endif - lcrr_div = in_be32(LBC_BASE_ADDR + FSL_LBC_LCCR) & LCRR_CLKDIV; + if (IS_ENABLED(CONFIG_FSL_IFC)) { + void __iomem *ifc = IFC_BASE_ADDR; - if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { - /* - * The entire PQ38 family use the same bit-representation - * for twice the clock divider values. - */ + ccr = in_be32(ifc + FSL_IFC_CCR_OFFSET); + ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT); + sysInfo->freqLocalBus = sysInfo->freqSystemBus / (ccr + 1); + } else { + lcrr_div = in_be32(LBC_BASE_ADDR + FSL_LBC_LCCR) & LCRR_CLKDIV; + + if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { + /* + * The entire PQ38 family use the same bit + * representation for twice the clock divider values. + */ lcrr_div *= 2; sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div; - } else { - /* In case anyone cares what the unknown value is */ - sysInfo->freqLocalBus = lcrr_div; + } else { + /* In case anyone cares what the unknown value is */ + sysInfo->freqLocalBus = lcrr_div; + } } } +unsigned long fsl_get_local_freq(void) +{ + struct sys_info sys_info; + + fsl_get_sys_info(&sys_info); + + return sys_info.freqLocalBus; +} + unsigned long fsl_get_bus_freq(ulong dummy) { struct sys_info sys_info; diff --git a/arch/sandbox/include/asm/bitops.h b/arch/sandbox/include/asm/bitops.h index 447023da63..e77ab83202 100644 --- a/arch/sandbox/include/asm/bitops.h +++ b/arch/sandbox/include/asm/bitops.h @@ -1,15 +1,28 @@ -#ifndef _SANDBOX_BITOPS_H -#define _SANDBOX_BITOPS_H +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ -/* nothing but the defaults.. */ #include <asm-generic/bitops/__ffs.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/ffs.h> #include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/ffz.h> -#include <asm-generic/bitops/find.h> -#include <asm-generic/bitops/fls64.h> #include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> #include <asm-generic/bitops/ops.h> #define set_bit(x, y) __set_bit(x, y) @@ -19,4 +32,4 @@ #define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) #define test_and_change_bit(x, y) __test_and_change_bit(x, y) -#endif +#endif /* _ASM_BITOPS_H_ */ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d8d7f0e651..346640dcda 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -20,6 +20,7 @@ config X86 select HAS_MODULES select HAVE_CONFIGURABLE_MEMORY_LAYOUT select HAVE_CONFIGURABLE_TEXT_BASE + select GENERIC_FIND_NEXT_BIT default y config X86_BOOTLOADER diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index d741e44d4a..e77ab83202 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -12,22 +12,24 @@ * */ -/** - * @file - * @brief x86 bit operations - * - * This file is required only to make all sources happy including - * 'linux/bitops.h' - */ - -#ifndef _ASM_X86_BITOPS_H_ -#define _ASM_X86_BITOPS_H_ +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ -#define BITS_PER_LONG 32 - -#include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/__ffs.h> -#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit(x, y) __set_bit(x, y) +#define clear_bit(x, y) __clear_bit(x, y) +#define change_bit(x, y) __change_bit(x, y) +#define test_and_set_bit(x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit(x, y) __test_and_change_bit(x, y) -#endif /* _ASM_X86_BITOPS_H_ */ +#endif /* _ASM_BITOPS_H_ */ diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h index d473405ff9..b3fd1f644b 100644 --- a/arch/x86/include/asm/types.h +++ b/arch/x86/include/asm/types.h @@ -41,6 +41,8 @@ typedef unsigned int u32; typedef signed long long s64; typedef unsigned long long u64; +#define BITS_PER_LONG 32 + #endif /* __ASSEMBLY__ */ #endif /* __ASM_X86_TYPES_H */ |