diff options
Diffstat (limited to 'arch')
109 files changed, 1069 insertions, 398 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9cba6552df..a54ad03445 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,9 @@ config ARM_LINUX default y depends on CMD_BOOTZ || CMD_BOOTU || CMD_BOOTM +config HAVE_MACH_ARM_HEAD + bool + menu "System Type " choice @@ -25,6 +28,8 @@ config ARCH_AT91 bool "Atmel AT91" select GENERIC_GPIO select CLKDEV_LOOKUP + select HAS_DEBUG_LL + select HAVE_MACH_ARM_HEAD config ARCH_EP93XX bool "Cirrus Logic EP93xx" @@ -34,6 +39,7 @@ config ARCH_EP93XX config ARCH_IMX bool "Freescale iMX-based" select GENERIC_GPIO + select GPIOLIB config ARCH_MXS bool "Freescale i.MX23/28 (mxs) based" diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c index daadf9489f..826f00e353 100644 --- a/arch/arm/boards/at91sam9260ek/init.c +++ b/arch/arm/boards/at91sam9260ek/init.c @@ -234,7 +234,7 @@ static void __init ek_add_led(void) static int at91sam9260ek_mem_init(void) { - at91_add_device_sdram(64 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c index b0cab5b0e6..5abe87c966 100644 --- a/arch/arm/boards/at91sam9261ek/init.c +++ b/arch/arm/boards/at91sam9261ek/init.c @@ -236,7 +236,7 @@ static void ek_device_add_leds(void) {} static int at91sam9261ek_mem_init(void) { - at91_add_device_sdram(64 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c index 68f4bfc3f1..573fac4562 100644 --- a/arch/arm/boards/at91sam9263ek/init.c +++ b/arch/arm/boards/at91sam9263ek/init.c @@ -166,7 +166,7 @@ static void __init ek_add_device_buttons(void) static int at91sam9263ek_mem_init(void) { - at91_add_device_sdram(64 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c index 9ddf3172f2..76c9be4fac 100644 --- a/arch/arm/boards/beagle/board.c +++ b/arch/arm/boards/beagle/board.c @@ -253,7 +253,7 @@ static struct NS16550_plat serial_plat = { static int beagle_console_init(void) { /* Register the serial port */ - add_ns16550_device(-1, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, + add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat); return 0; @@ -283,6 +283,12 @@ static struct i2c_board_info i2c_devices[] = { }, }; +static struct gpmc_nand_platform_data nand_plat = { + .device_width = 16, + .ecc_mode = OMAP_ECC_HAMMING_CODE_HW_ROMCODE, + .nand_cfg = &omap3_nand_cfg, +}; + static int beagle_mem_init(void) { arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024); @@ -306,8 +312,7 @@ static int beagle_devices_init(void) /* WP is made high and WAIT1 active Low */ gpmc_generic_init(0x10); #endif - gpmc_generic_nand_devices_init(0, 16, - OMAP_ECC_HAMMING_CODE_HW_ROMCODE, &omap3_nand_cfg); + omap_add_gpmc_nand_device(&nand_plat); add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K, IORESOURCE_MEM, NULL); diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c index f309e0c693..0b450d64e7 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51.c +++ b/arch/arm/boards/ccxmx51/ccxmx51.c @@ -307,7 +307,7 @@ static int ccxmx51_power_init(void) mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_2, val); } - if (mc13xxx_dev->revision <= MC13892_REVISION_2_0) { + if (mc13xxx_revision(mc13xxx_dev) <= MC13892_REVISION_2_0) { /* Set switchers in PWM mode for Atlas 2.0 and lower */ /* Setup the switcher mode for SW1 & SW2*/ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_4, &val); diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c index b40713d33b..60d1f6283c 100644 --- a/arch/arm/boards/chumby_falconwing/falconwing.c +++ b/arch/arm/boards/chumby_falconwing/falconwing.c @@ -318,7 +318,7 @@ static void falconwing_init_usb(void) imx23_usb_phy_enable(); - add_generic_usb_ehci_device(-1, IMX_USB_BASE, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_USB_BASE, NULL); } static int falconwing_devices_init(void) diff --git a/arch/arm/boards/crystalfontz-cfa10036/env/init/automount b/arch/arm/boards/crystalfontz-cfa10036/env/init/automount index fe67e55c5a..668775d89b 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/env/init/automount +++ b/arch/arm/boards/crystalfontz-cfa10036/env/init/automount @@ -6,4 +6,4 @@ if [ "$1" = menu ]; then fi mkdir -p /mnt/disk0.1 -automount -d /mnt/disk0.1 '[ -e /dev/disk0.1 ] && mount /dev/disk0.1 fat /mnt/disk0.1' +automount -d /mnt/disk0.1 '[ -e /dev/disk0.1 ] && mount /dev/disk0.1 /mnt/disk0.1' diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c index d32daf4923..3de4d4965e 100644 --- a/arch/arm/boards/edb93xx/edb93xx.c +++ b/arch/arm/boards/edb93xx/edb93xx.c @@ -57,7 +57,7 @@ mem_initcall(ep93xx_mem_init); static int ep93xx_devices_init(void) { - add_cfi_flash_device(-1, 0x60000000, EDB93XX_CFI_FLASH_SIZE, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x60000000, EDB93XX_CFI_FLASH_SIZE, 0); /* * Create partitions that should be diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c index 193c277561..10466ba117 100644 --- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -191,9 +191,9 @@ static int eukrea_cpuimx27_devices_init(void) for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); #ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB - add_cfi_flash_device(-1, 0xC2000000, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC2000000, 32 * 1024 * 1024, 0); #endif imx27_add_nand(&nand_info); @@ -227,13 +227,13 @@ device_initcall(eukrea_cpuimx27_devices_init); static int eukrea_cpuimx27_console_init(void) { #ifdef CONFIG_DRIVER_SERIAL_IMX - imx_add_uart((void *)IMX_UART1_BASE, -1); + imx_add_uart((void *)IMX_UART1_BASE, DEVICE_ID_DYNAMIC); #endif /* configure 8 bit UART on cs3 */ FMCR &= ~0x2; imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000); #ifdef CONFIG_DRIVER_SERIAL_NS16550 - add_ns16550_device(-1, IMX_CS3_BASE + QUART_OFFSET, 0xf, + add_ns16550_device(DEVICE_ID_DYNAMIC, IMX_CS3_BASE + QUART_OFFSET, 0xf, IORESOURCE_MEM_16BIT, &quad_uart_serial_plat); #endif return 0; diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c index 49dbabc491..e657e77e51 100644 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -220,13 +220,13 @@ static int eukrea_cpuimx35_devices_init(void) #ifdef CONFIG_USB imx35_usb_init(); - add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); #endif #ifdef CONFIG_USB_GADGET /* Workaround ENGcm09152 */ tmp = readl(IMX_OTG_BASE + 0x608); writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608); - add_generic_device("fsl-udc", -1, NULL, IMX_OTG_BASE, 0x200, + add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200, IORESOURCE_MEM, &usb_pdata); #endif armlinux_set_bootparams((void *)0x80000100); diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c index 97c1fd9427..f6162fd279 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c @@ -213,7 +213,7 @@ static int imx25_devices_init(void) * the CPLD has to be initialized. */ imx25_usb_init(); - add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); #endif imx25_iim_register_fec_ethaddr(); diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c index 9b255a55fa..cfd2c16f0d 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c @@ -159,7 +159,7 @@ static int f3s_devices_init(void) * This platform supports NOR and NAND */ imx35_add_nand(&nand_info); - add_cfi_flash_device(-1, IMX_CS0_BASE, 64 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 64 * 1024 * 1024, 0); switch ((reg >> 25) & 0x3) { case 0x01: /* NAND is the source */ @@ -362,7 +362,6 @@ static int f3s_get_rev(struct mc13xxx *mc13xxx) if (err) return err; - dev_info(&mc13xxx->client->dev, "revision: 0x%x\n", rev); if (rev == 0x00ffffff) return -ENODEV; @@ -379,8 +378,7 @@ static int f3s_pmic_init_v2(struct mc13xxx *mc13xxx) err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_SETTING_0, 0x03, 0x03); err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_MODE_0, 0x01, 0x01); if (err) - dev_err(&mc13xxx->client->dev, - "Init sequence failed, the system might not be working!\n"); + printf("mc13892 Init sequence failed, the system might not be working!\n"); return err; } diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c index 7c2c8fe71e..b67a509680 100644 --- a/arch/arm/boards/freescale-mx51-pdk/board.c +++ b/arch/arm/boards/freescale-mx51-pdk/board.c @@ -178,7 +178,7 @@ static void babbage_power_init(void) mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); } - if (mc13xxx->revision < MC13892_REVISION_2_0) { + if (mc13xxx_revision(mc13xxx) < MC13892_REVISION_2_0) { /* Set switchers in PWM mode for Atlas 2.0 and lower */ /* Setup the switcher mode for SW1 & SW2*/ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c index 13279bc95c..1ac401ebb1 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/board.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c @@ -77,6 +77,23 @@ static iomux_v3_cfg_t sabrelite_pads[] = { MX6Q_PAD_EIM_D17__ECSPI1_MISO, MX6Q_PAD_EIM_D18__ECSPI1_MOSI, MX6Q_PAD_EIM_D19__GPIO_3_19, /* CS1 */ + + /* I2C0 */ + MX6Q_PAD_EIM_D21__I2C1_SCL, + MX6Q_PAD_EIM_D28__I2C1_SDA, + + /* I2C1 */ + MX6Q_PAD_KEY_COL3__I2C2_SCL, + MX6Q_PAD_KEY_ROW3__I2C2_SDA, + + /* I2C2 */ + MX6Q_PAD_GPIO_5__I2C3_SCL, + MX6Q_PAD_GPIO_16__I2C3_SDA, + + /* USB */ + MX6Q_PAD_GPIO_17__GPIO_7_12, + MX6Q_PAD_EIM_D22__GPIO_3_22, + MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC, }; static iomux_v3_cfg_t sabrelite_enet_pads[] = { @@ -227,6 +244,19 @@ static struct esdhc_platform_data sabrelite_sd4_data = { .wp_type = ESDHC_WP_NONE, }; +static void sabrelite_ehci_init(void) +{ + imx6_usb_phy1_disable_oc(); + imx6_usb_phy1_enable(); + + /* hub reset */ + gpio_direction_output(204, 0); + udelay(2000); + gpio_set_value(204, 1); + + add_generic_usb_ehci_device(1, MX6_USBOH3_USB_BASE_ADDR + 0x200, NULL); +} + static int sabrelite_devices_init(void) { imx6_add_mmc2(&sabrelite_sd3_data); @@ -237,6 +267,8 @@ static int sabrelite_devices_init(void) imx6_add_fec(&fec_info); mx6_rgmii_rework(); + sabrelite_ehci_init(); + spi_register_board_info(sabrelite_spi_board_info, ARRAY_SIZE(sabrelite_spi_board_info)); imx6_add_spi0(&sabrelite_spi_0_data); diff --git a/arch/arm/boards/friendlyarm-tiny210/tiny210.c b/arch/arm/boards/friendlyarm-tiny210/tiny210.c index 1277649373..18494b0517 100644 --- a/arch/arm/boards/friendlyarm-tiny210/tiny210.c +++ b/arch/arm/boards/friendlyarm-tiny210/tiny210.c @@ -86,7 +86,7 @@ static int tiny210_console_init(void) s3c_gpio_mode(GPA02_NCTS0 | ENABLE_PU); s3c_gpio_mode(GPA03_NRTS0); - add_generic_device("s3c_serial", -1, NULL, + add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE, S3C_UART1_SIZE, IORESOURCE_MEM, NULL); return 0; diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c index fbb20c10e0..623dc0ad4e 100644 --- a/arch/arm/boards/guf-neso/board.c +++ b/arch/arm/boards/guf-neso/board.c @@ -280,7 +280,7 @@ static int neso_devices_init(void) #ifdef CONFIG_USB neso_usbh_init(); - add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); #endif imx27_add_fec(&fec_info); diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c index 2bbd5ede25..58086bca11 100644 --- a/arch/arm/boards/imx21ads/imx21ads.c +++ b/arch/arm/boards/imx21ads/imx21ads.c @@ -167,7 +167,7 @@ static int mx21ads_devices_init(void) for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - add_cfi_flash_device(-1, 0xC8000000, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC8000000, 32 * 1024 * 1024, 0); imx21_add_nand(&nand_info); add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, IMX_CS1_BASE, 0x1000, IORESOURCE_MEM, NULL); diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c index ff002249de..6b0fc724d8 100644 --- a/arch/arm/boards/imx27ads/imx27ads.c +++ b/arch/arm/boards/imx27ads/imx27ads.c @@ -108,7 +108,7 @@ static int mx27ads_devices_init(void) for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); imx27_add_fec(&fec_info); devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0"); diff --git a/arch/arm/boards/mioa701/board.c b/arch/arm/boards/mioa701/board.c index ab5a493e76..b5c05a6eea 100644 --- a/arch/arm/boards/mioa701/board.c +++ b/arch/arm/boards/mioa701/board.c @@ -121,7 +121,7 @@ static int mioa701_devices_init(void) pxa_add_pwm((void *)0x40b00000, 0); pxa_add_fb((void *)0x44000000, &mioa701_pxafb_info); - pxa_add_mmc((void *)0x41100000, -1, &mioa701_mmc_info); + pxa_add_mmc((void *)0x41100000, DEVICE_ID_DYNAMIC, &mioa701_mmc_info); docg3_iospace = map_io_sections(0x0, (void *)0xe0000000, 0x2000); add_generic_device("docg3", DEVICE_ID_DYNAMIC, NULL, (ulong) docg3_iospace, 0x2000, IORESOURCE_MEM, NULL); diff --git a/arch/arm/boards/mioa701/env/bin/sdcard_override b/arch/arm/boards/mioa701/env/bin/sdcard_override index 4b2ad51343..ab83534135 100644 --- a/arch/arm/boards/mioa701/env/bin/sdcard_override +++ b/arch/arm/boards/mioa701/env/bin/sdcard_override @@ -8,7 +8,7 @@ mci0.probe=1 if [ $mci0.probe = 1 ]; then mkdir /sdcard - mount /dev/disk0.0 fat /sdcard + mount /dev/disk0.0 /sdcard if [ -f /sdcard/barebox.env ]; then loadenv /sdcard/barebox.env /env.sd /env.sd/bin/init diff --git a/arch/arm/boards/netx/netx.c b/arch/arm/boards/netx/netx.c index c4a8733aad..fde1b9416a 100644 --- a/arch/arm/boards/netx/netx.c +++ b/arch/arm/boards/netx/netx.c @@ -47,7 +47,7 @@ static int netx_mem_init(void) mem_initcall(netx_mem_init); static int netx_devices_init(void) { - add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); add_generic_device("netx-eth", DEVICE_ID_DYNAMIC, NULL, 0, 0, IORESOURCE_MEM, ð0_data); diff --git a/arch/arm/boards/nhk8815/setup.c b/arch/arm/boards/nhk8815/setup.c index ccc0510555..5820114307 100644 --- a/arch/arm/boards/nhk8815/setup.c +++ b/arch/arm/boards/nhk8815/setup.c @@ -63,7 +63,7 @@ static struct resource nhk8815_nand_resources[] = { .flags = IORESOURCE_MEM, }, { .start = NAND_IO_DATA, - .end = NAND_IO_CMD + 0xfff, + .end = NAND_IO_DATA + 0xfff, .flags = IORESOURCE_MEM, } }; diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c index b5174f3a6e..8d4119331b 100644 --- a/arch/arm/boards/omap343xdsp/board.c +++ b/arch/arm/boards/omap343xdsp/board.c @@ -621,7 +621,7 @@ static struct NS16550_plat serial_plat = { static int sdp3430_console_init(void) { /* Register the serial port */ - add_ns16550_device(-1, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, + add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat); return 0; diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c index 84b4ecd77e..98c05b2f41 100644 --- a/arch/arm/boards/panda/board.c +++ b/arch/arm/boards/panda/board.c @@ -92,7 +92,7 @@ static void panda_ehci_init(void) /* enable power to hub */ gpio_set_value(GPIO_HUB_POWER, 1); - add_usb_ehci_device(-1, 0x4a064c00, + add_usb_ehci_device(DEVICE_ID_DYNAMIC, 0x4a064c00, 0x4a064c00 + 0x10, &ehci_pdata); } #else diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c index 8591fff053..0b4b199d34 100644 --- a/arch/arm/boards/panda/lowlevel.c +++ b/arch/arm/boards/panda/lowlevel.c @@ -28,6 +28,8 @@ #include <mach/syslib.h> #include <asm/barebox-arm.h> +#define TPS62361_VSEL0_GPIO 7 + void set_muxconf_regs(void); static const struct ddr_regs ddr_regs_400_mhz_2cs = { @@ -70,7 +72,7 @@ static void noinline panda_init_lowlevel(void) omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ - omap4_scale_vcores(); + omap4_scale_vcores(TPS62361_VSEL0_GPIO); board_init_lowlevel_return(); } diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c index 310e43372f..3783006ad6 100644 --- a/arch/arm/boards/panda/mux.c +++ b/arch/arm/boards/panda/mux.c @@ -3,6 +3,7 @@ #include <io.h> #include <mach/omap4-silicon.h> #include <mach/omap4-mux.h> +#include <mach/omap4-clock.h> static const struct pad_conf_entry core_padconf_array[] = { { GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat0 */ }, @@ -245,4 +246,11 @@ void set_muxconf_regs(void) omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array)); + + /* gpio_wk7 is used for controlling TPS on 4460 */ + if (omap4_revision() >= OMAP4460_ES1_0) { + writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ); + /* Enable GPIO-1 clocks before TPS initialization */ + omap4_enable_gpio1_wup_clocks(); + } } diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c index 8f1271fa5e..912d6ea603 100644 --- a/arch/arm/boards/pcm038/pcm038.c +++ b/arch/arm/boards/pcm038/pcm038.c @@ -292,7 +292,7 @@ static int pcm038_devices_init(void) pcm038_power_init(); - add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); imx27_add_nand(&nand_info); imx27_add_fb(&pcm038_fb_data); diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c index b95648270b..31af383c20 100644 --- a/arch/arm/boards/pcm038/pcm970.c +++ b/arch/arm/boards/pcm038/pcm970.c @@ -48,7 +48,7 @@ static void pcm970_usbh2_init(void) mdelay(10); if (!ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1)) - add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); } #endif @@ -73,7 +73,7 @@ static struct ide_port_info pcm970_ide_pdata = { }; static struct device_d pcm970_ide_device = { - .id = -1, + .id = DEVICE_ID_DYNAMIC, .name = "ide_intf", .num_resources = ARRAY_SIZE(pcm970_ide_resources), .resource = pcm970_ide_resources, diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c index 152b47ce65..95e12fdcb5 100644 --- a/arch/arm/boards/pcm043/pcm043.c +++ b/arch/arm/boards/pcm043/pcm043.c @@ -148,7 +148,7 @@ static int imx35_devices_init(void) * Up to 32MiB NOR type flash, connected to * CS line 0, data width is 16 bit */ - add_cfi_flash_device(-1, IMX_CS0_BASE, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 32 * 1024 * 1024, 0); if ((reg & 0xc00) == 0x800) { /* reset mode: external boot */ switch ( (reg >> 25) & 0x3) { diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c index 5b7854a5e3..3ef38a7831 100644 --- a/arch/arm/boards/pcm049/board.c +++ b/arch/arm/boards/pcm049/board.c @@ -94,6 +94,12 @@ static struct i2c_board_info i2c_devices[] = { }, }; +static struct gpmc_nand_platform_data nand_plat = { + .wait_mon_pin = 1, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW, + .nand_cfg = &omap4_nand_cfg, +}; + static int pcm049_devices_init(void) { i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); @@ -107,8 +113,7 @@ static int pcm049_devices_init(void) pcm049_network_init(); - gpmc_generic_nand_devices_init(0, 8, - OMAP_ECC_BCH8_CODE_HW, &omap4_nand_cfg); + omap_add_gpmc_nand_device(&nand_plat); #ifdef CONFIG_PARTITION devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "xload_raw"); diff --git a/arch/arm/boards/pcm049/env/bin/nand_bootstrap b/arch/arm/boards/pcm049/env/bin/nand_bootstrap index acd00dc904..f8873fabe2 100644 --- a/arch/arm/boards/pcm049/env/bin/nand_bootstrap +++ b/arch/arm/boards/pcm049/env/bin/nand_bootstrap @@ -4,7 +4,7 @@ echo "copying barebox to nand..." mci0.probe=1 mkdir mnt -mount /dev/disk0.0 fat /mnt +mount /dev/disk0.0 /mnt if [ $? != 0 ]; then echo "failed to mount mmc card" exit 1 diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c index 5b9109833b..65a29ec8ae 100644 --- a/arch/arm/boards/pcm049/lowlevel.c +++ b/arch/arm/boards/pcm049/lowlevel.c @@ -28,6 +28,8 @@ #include <mach/syslib.h> #include <asm/barebox-arm.h> +#define TPS62361_VSEL0_GPIO 182 + void set_muxconf_regs(void); static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { @@ -46,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { static void noinline pcm049_init_lowlevel(void) { struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; - struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; @@ -57,12 +60,16 @@ static void noinline pcm049_init_lowlevel(void) omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ - omap4_scale_vcores(); + omap4_scale_vcores(TPS62361_VSEL0_GPIO); writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); /* Configure all DPLL's at 100% OPP */ - omap4_configure_mpu_dpll(&mpu); + if (omap4_revision() < OMAP4460_ES1_0) + omap4_configure_mpu_dpll(&mpu44xx); + else + omap4_configure_mpu_dpll(&mpu4460); + omap4_configure_iva_dpll(&iva); omap4_configure_per_dpll(&per); omap4_configure_abe_dpll(&abe); @@ -88,7 +95,7 @@ void board_init_lowlevel(void) return; r = 0x4030d000; - __asm__ __volatile__("mov sp, %0" : : "r"(r)); + __asm__ __volatile__("mov sp, %0" : : "r"(r)); pcm049_init_lowlevel(); } diff --git a/arch/arm/boards/pcm049/mux.c b/arch/arm/boards/pcm049/mux.c index a7a77b5adc..04e1d67214 100644 --- a/arch/arm/boards/pcm049/mux.c +++ b/arch/arm/boards/pcm049/mux.c @@ -3,6 +3,7 @@ #include <io.h> #include <mach/omap4-silicon.h> #include <mach/omap4-mux.h> +#include <mach/omap4-clock.h> static const struct pad_conf_entry core_padconf_array[] = { {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ @@ -242,4 +243,11 @@ void set_muxconf_regs(void) omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array)); + + /* gpio_182 is used for controlling TPS on 4460 */ + if (omap4_revision() >= OMAP4460_ES1_0) { + writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT); + /* Enable GPIO-1 clocks before TPS initialization */ + omap4_enable_gpio_clocks(); + } } diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c index 1dc7678771..907198d783 100644 --- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c +++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c @@ -327,7 +327,7 @@ static struct NS16550_plat serial_plat = { */ static int pcaal1_init_console(void) { - add_ns16550_device(-1, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, + add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat); return 0; @@ -391,9 +391,16 @@ struct omap_hsmmc_platform_data pcaal1_hsmmc_plat = { }; #endif +static struct gpmc_nand_platform_data nand_plat = { + .device_width = 16, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW, + .nand_cfg = &omap3_nand_cfg, +}; + static int pcaal1_init_devices(void) { - gpmc_generic_nand_devices_init(0, 16, OMAP_ECC_BCH8_CODE_HW, &omap3_nand_cfg); + omap_add_gpmc_nand_device(&nand_plat); + #ifdef CONFIG_MCI_OMAP_HSMMC add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K, IORESOURCE_MEM, &pcaal1_hsmmc_plat); diff --git a/arch/arm/boards/phycard-a-xl2/env/bin/nand_bootstrap b/arch/arm/boards/phycard-a-xl2/env/bin/nand_bootstrap index acd00dc904..f8873fabe2 100644 --- a/arch/arm/boards/phycard-a-xl2/env/bin/nand_bootstrap +++ b/arch/arm/boards/phycard-a-xl2/env/bin/nand_bootstrap @@ -4,7 +4,7 @@ echo "copying barebox to nand..." mci0.probe=1 mkdir mnt -mount /dev/disk0.0 fat /mnt +mount /dev/disk0.0 /mnt if [ $? != 0 ]; then echo "failed to mount mmc card" exit 1 diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c index b8de2aad0a..38f80c9733 100644 --- a/arch/arm/boards/phycard-a-xl2/lowlevel.c +++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c @@ -28,6 +28,8 @@ #include <mach/syslib.h> #include <asm/barebox-arm.h> +#define TPS62361_VSEL0_GPIO 7 + void set_muxconf_regs(void); static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { @@ -46,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { static noinline void pcaaxl2_init_lowlevel(void) { struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; - struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; @@ -57,12 +60,16 @@ static noinline void pcaaxl2_init_lowlevel(void) omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ - omap4_scale_vcores(); + omap4_scale_vcores(TPS62361_VSEL0_GPIO); writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); /* Configure all DPLL's at 100% OPP */ - omap4_configure_mpu_dpll(&mpu); + if (omap4_revision() < OMAP4460_ES1_0) + omap4_configure_mpu_dpll(&mpu44xx); + else + omap4_configure_mpu_dpll(&mpu4460); + omap4_configure_iva_dpll(&iva); omap4_configure_per_dpll(&per); omap4_configure_abe_dpll(&abe); diff --git a/arch/arm/boards/phycard-a-xl2/mux.c b/arch/arm/boards/phycard-a-xl2/mux.c index 179e6b67ab..dc605e38b4 100644 --- a/arch/arm/boards/phycard-a-xl2/mux.c +++ b/arch/arm/boards/phycard-a-xl2/mux.c @@ -3,6 +3,7 @@ #include <io.h> #include <mach/omap4-silicon.h> #include <mach/omap4-mux.h> +#include <mach/omap4-clock.h> static const struct pad_conf_entry core_padconf_array[] = { {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ @@ -242,4 +243,11 @@ void set_muxconf_regs(void) omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array)); + + /* gpio_wk7 is used for controlling TPS on 4460 */ + if (omap4_revision() >= OMAP4460_ES1_0) { + writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ); + /* Enable GPIO-1 clocks before TPS initialization */ + omap4_enable_gpio1_wup_clocks(); + } } diff --git a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c index 128cb8fd28..4fec0f0e41 100644 --- a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c +++ b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c @@ -51,7 +51,7 @@ static struct NS16550_plat serial_plat = { static int pcaaxl2_console_init(void) { /* Register the serial port */ - add_ns16550_device(-1, OMAP44XX_UART3_BASE, 1024, + add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP44XX_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat); return 0; @@ -85,7 +85,7 @@ static void pcaaxl2_network_init(void) { gpmc_cs_config(5, &net_cfg); - add_ks8851_device(-1, net_cfg.base, net_cfg.base + 2, + add_ks8851_device(DEVICE_ID_DYNAMIC, net_cfg.base, net_cfg.base + 2, IORESOURCE_MEM_16BIT, NULL); } @@ -104,6 +104,12 @@ static struct omap_hsmmc_platform_data mmc_device = { #define OMAP4_MMC1_PBIASLITE_PWRDNZ (1<<22) #define OMAP4_MMC1_PWRDNZ (1<<26) +static struct gpmc_nand_platform_data nand_plat = { + .device_width = 16, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW, + .nand_cfg = &omap4_nand_cfg, +}; + static int pcaaxl2_devices_init(void) { u32 value; @@ -124,8 +130,7 @@ static int pcaaxl2_devices_init(void) pcaaxl2_network_init(); - gpmc_generic_nand_devices_init(0, 16, - OMAP_ECC_BCH8_CODE_HW, &omap4_nand_cfg); + omap_add_gpmc_nand_device(&nand_plat); #ifdef CONFIG_PARTITION devfs_add_partition("nand0", 0x00000, SZ_128K, diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c index 126f9efbac..614bfc65eb 100644 --- a/arch/arm/boards/phycard-i.MX27/pca100.c +++ b/arch/arm/boards/phycard-i.MX27/pca100.c @@ -141,9 +141,9 @@ static void pca100_usb_register(void) mdelay(10); ulpi_setup((void *)(IMX_OTG_BASE + 0x170), 1); - add_generic_usb_ehci_device(-1, IMX_OTG_BASE, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE, NULL); ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1); - add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); } #endif diff --git a/arch/arm/boards/qil-a9260/init.c b/arch/arm/boards/qil-a9260/init.c index 305d733a74..6b1ed85609 100644 --- a/arch/arm/boards/qil-a9260/init.c +++ b/arch/arm/boards/qil-a9260/init.c @@ -150,11 +150,7 @@ static void __init ek_add_led(void) static int qil_a9260_mem_init(void) { -#ifdef CONFIG_AT91_HAVE_SRAM_128M - at91_add_device_sdram(128 * 1024 * 1024); -#else - at91_add_device_sdram(64 * 1024 * 1024); -#endif + at91_add_device_sdram(0); return 0; } @@ -196,11 +192,17 @@ device_initcall(qil_a9260_devices_init); static int qil_a9260_console_init(void) { at91_register_uart(0, 0); + at91_set_A_periph(AT91_PIN_PB14, 1); /* Enable pull-up on DRXD */ + at91_register_uart(1, ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD | ATMEL_UART_RI); + at91_register_uart(2, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_set_A_periph(AT91_PIN_PB7, 1); /* Enable pull-up on RXD1 */ + at91_register_uart(3, ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_set_A_periph(AT91_PIN_PB9, 1); /* Enable pull-up on RXD2 */ return 0; } diff --git a/arch/arm/boards/qil-a9260/qil-a9260.dox b/arch/arm/boards/qil-a9260/qil-a9260.dox new file mode 100644 index 0000000000..da5c197b34 --- /dev/null +++ b/arch/arm/boards/qil-a9260/qil-a9260.dox @@ -0,0 +1,22 @@ +/** +@page qil-a9260 Calao-systems QIL-A9260 + +@section qil-a9260 The CPU module + +http://www.calao-systems.com + +This CPU module is based on an Atmel AT91SAM9260 CPU. The card is shipped with: + +- 64MiB or 128MiB SDRAM (3.3V) +- 256MiB NAND type Flash Memory (3.3V) +- 64Kib SPI EEPROM +- RMII 10/100 ethernet PHY +- Real Time Clock +- micro SD socket + +@section mob-qil-a9xxx Supported development board + +Supported development board is: +- MOB-QIL-A9xxx + +*/ diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c index 9a342a8170..671adbf274 100644 --- a/arch/arm/boards/scb9328/scb9328.c +++ b/arch/arm/boards/scb9328/scb9328.c @@ -88,8 +88,8 @@ static int scb9328_devices_init(void) CS5U = 0x00008400; CS5L = 0x00000D03; - add_cfi_flash_device(-1, 0x10000000, 16 * 1024 * 1024, 0); - add_dm9000_device(-1, 0x16000000, 0x16000004, + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x10000000, 16 * 1024 * 1024, 0); + add_dm9000_device(DEVICE_ID_DYNAMIC, 0x16000000, 0x16000004, IORESOURCE_MEM_16BIT, &dm9000_data); devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c index 2cb7da7cff..5538a44a67 100644 --- a/arch/arm/boards/tny-a926x/init.c +++ b/arch/arm/boards/tny-a926x/init.c @@ -89,7 +89,7 @@ static struct sam9_smc_config tny_a9g20_nand_smc_config = { .ncs_read_pulse = 4, .nrd_pulse = 4, .ncs_write_pulse = 4, - .nwe_pulse = 2, + .nwe_pulse = 4, .read_cycle = 7, .write_cycle = 7, @@ -171,7 +171,7 @@ static void __init ek_add_device_udc(void) static int tny_a9260_mem_init(void) { - at91_add_device_sdram(64 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } diff --git a/arch/arm/boards/tny-a926x/tny-a9263.dox b/arch/arm/boards/tny-a926x/tny-a9263.dox new file mode 100644 index 0000000000..68fcdd109c --- /dev/null +++ b/arch/arm/boards/tny-a926x/tny-a9263.dox @@ -0,0 +1,33 @@ +/** +@page tny-a9263 Calao-systems TNY-A9263 + +@section tny-a9263 The CPU module + +http://www.calao-systems.com + +This CPU module is based on an Atmel AT91SAM9263 CPU. The module is shipped with: + +- 64MiB SDRAM (3.3V) +- 256MiB NAND type Flash Memory (3.3V) +- USB device port +- Top expansion connector for daughter boards (GPS, WIFI/BT, GPRS, 3G, ZigBee, MBUS, ...) +- Bottom expansion connector for development boards + +@section mob-tny-a9xxx-md2 Supported development board + +Supported development board is: +- MOB-TNY-A9xxx-MD2 + +@section tny-db-boards Supported daughter boards + +Supported daughter boards are: +- DAB-GPI2-CXX +- DAB-GPS +- DAB-GPRS +- DAB-HSDPA +- DAB-WLAN-BT +- DAB-ZIGBEE +- DAB-MBUS +- DAB-KNX-RF + +*/ diff --git a/arch/arm/boards/tny-a926x/tny-a9g20-lpw.dox b/arch/arm/boards/tny-a926x/tny-a9g20-lpw.dox new file mode 100644 index 0000000000..e0021070b3 --- /dev/null +++ b/arch/arm/boards/tny-a926x/tny-a9g20-lpw.dox @@ -0,0 +1,37 @@ +/** +@page tny-a9g20-lpw Calao-systems TNY-A9G20-LPW + +@section tny-a9g20-lpw The CPU module + +http://www.calao-systems.com + +This CPU module is based on an Atmel AT91SAM9G20 CPU. The module is shipped with: + +- 64MiB Low Power SDRAM (1.8V) +- 256MiB NAND type Flash Memory (1.8V) +- Real Time Clock (I2C) +- Micro SD socket +- USB device port +- JTAG connector +- Top expansion connector for daughter boards (GPS, WIFI/BT, GPRS, 3G, ZigBee, MBUS, ...) +- Bottom expansion connector for development boards + +@section mob-tny-a9xxx-md2 Supported development board + +Supported development board is: +- MOB-TNY-A9xxx-MD2 + +@section tny-db-boards Supported daughter boards + +Supported daughter boards are: +- DAB-GPI2-CXX +- DAB-GPS +- DAB-GPRS +- DAB-HSDPA +- DAB-WLAN-BT +- DAB-ZIGBEE +- DAB-MBUS +- DAB-KNX-RF + + +*/ diff --git a/arch/arm/boards/toshiba-ac100/serial.c b/arch/arm/boards/toshiba-ac100/serial.c index 2ed0e3901c..39d2658a82 100644 --- a/arch/arm/boards/toshiba-ac100/serial.c +++ b/arch/arm/boards/toshiba-ac100/serial.c @@ -35,7 +35,7 @@ static struct NS16550_plat serial_plat = { static int ac100_serial_console_init(void) { /* Register the serial port */ - add_ns16550_device(-1, TEGRA_UARTA_BASE, 8 << serial_plat.shift, + add_ns16550_device(DEVICE_ID_DYNAMIC, TEGRA_UARTA_BASE, 8 << serial_plat.shift, IORESOURCE_MEM_8BIT, &serial_plat); return 0; diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c index 824a38a94d..00a215d140 100644 --- a/arch/arm/boards/usb-a926x/init.c +++ b/arch/arm/boards/usb-a926x/init.c @@ -90,7 +90,7 @@ static struct sam9_smc_config usb_a9g20_nand_smc_config = { .ncs_read_pulse = 4, .nrd_pulse = 4, .ncs_write_pulse = 4, - .nwe_pulse = 2, + .nwe_pulse = 4, .read_cycle = 7, .write_cycle = 7, @@ -203,11 +203,7 @@ static void __init ek_add_led(void) static int usb_a9260_mem_init(void) { -#ifdef CONFIG_AT91_HAVE_SRAM_128M - at91_add_device_sdram(128 * 1024 * 1024); -#else - at91_add_device_sdram(64 * 1024 * 1024); -#endif + at91_add_device_sdram(0); return 0; } @@ -294,7 +290,7 @@ static void usb_a9260_keyboard_device_dab_mmx(void) at91_set_deglitch(keys[i].gpio, 1); } - add_gpio_keys_device(-1, &gk_pdata); + add_gpio_keys_device(DEVICE_ID_DYNAMIC, &gk_pdata); } #else static void usb_a9260_keyboard_device_dab_mmx(void) {} diff --git a/arch/arm/boards/usb-a926x/usb-a9263.dox b/arch/arm/boards/usb-a926x/usb-a9263.dox new file mode 100644 index 0000000000..380a8e2d3d --- /dev/null +++ b/arch/arm/boards/usb-a926x/usb-a9263.dox @@ -0,0 +1,30 @@ +/** +@page usb-a9263 Calao-systems USB-A9263 + +@section usb-a9263 The CPU card + +http://www.calao-systems.com + +This CPU card is based on an Atmel AT91SAM9263 CPU. The card is shipped with: + +- 64MiB or 128MiB SDRAM (3.3V) +- 256MiB NAND type Flash Memory (3.3V) +- Ethernet 10/100M +- USB Host port 2.0 (FS) +- USB device port (FS) +- Top expansion connector for expansion boards (GPS, WIFI/BT, GPRS, 3G, ZigBee, MBUS, ...) +- Bottom expansion connector for development boards + +@section usb-db-boards Supported daughter boards + +Supported daughter boards are: +- DAB-GPI2-CXX +- DAB-GPS +- DAB-GPRS +- DAB-HSDPA +- DAB-WLAN-BT +- DAB-ZIGBEE +- DAB-MBUS +- DAB-KNX-RF + +*/ diff --git a/arch/arm/boards/usb-a926x/usb-a9g20-lpw.dox b/arch/arm/boards/usb-a926x/usb-a9g20-lpw.dox new file mode 100644 index 0000000000..024a3cedda --- /dev/null +++ b/arch/arm/boards/usb-a926x/usb-a9g20-lpw.dox @@ -0,0 +1,33 @@ +/** +@page usb-a9g20-lpw Calao-systems USB-A9G20-LPW + +@section usb-a9g20-lpw The CPU card + +http://www.calao-systems.com + +This CPU card is based on an Atmel AT91SAM9G20 CPU. The card is shipped with: + +- 64MiB or 128MiB SDRAM (1.8V) +- 256MiB NAND type Flash Memory (1.8V) +- Ethernet 10/100M +- USB Host port 2.0 (FS) +- USB device port (FS) +- Micro SD socket +- JTAG connector +- RTC with battery backup +- Top expansion connector for daughter boards (GPS, WIFI/BT, GPRS, 3G, ZigBee, MBUS, ...) +- Bottom expansion connector for development boards + +@section usb-db-boards Supported daughter boards + +Supported daughter boards are: +- DAB-GPI2-CXX +- DAB-GPS +- DAB-GPRS +- DAB-HSDPA +- DAB-WLAN-BT +- DAB-ZIGBEE +- DAB-MBUS +- DAB-KNX-RF + +*/ diff --git a/arch/arm/boards/versatile/versatilepb.c b/arch/arm/boards/versatile/versatilepb.c index b95e605ab2..b834bbbda2 100644 --- a/arch/arm/boards/versatile/versatilepb.c +++ b/arch/arm/boards/versatile/versatilepb.c @@ -50,7 +50,7 @@ mem_initcall(vpb_mem_init); static int vpb_devices_init(void) { - add_cfi_flash_device(-1, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0); devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self"); devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h index 2c250e948e..0b1d78644d 100644 --- a/arch/arm/include/asm/barebox-arm-head.h +++ b/arch/arm/include/asm/barebox-arm-head.h @@ -1,6 +1,9 @@ #ifndef __ASM_ARM_HEAD_H #define __ASM_ARM_HEAD_H +#ifdef CONFIG_HAVE_MACH_ARM_HEAD +#include <mach/barebox-arm-head.h> +#else static inline void barebox_arm_head(void) { __asm__ __volatile__ ( @@ -31,5 +34,6 @@ static inline void barebox_arm_head(void) ".word _barebox_image_size\n" /* image size to copy */ ); } +#endif #endif /* __ASM_ARM_HEAD_H */ diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index a8840fe42d..c5b76ea979 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -58,7 +58,9 @@ static int __do_bootm_linux(struct image_data *data, int swap) kernel = data->os_res->start + data->os_entry; - if (data->initrd_file && data->initrd_address == UIMAGE_INVALID_ADDRESS) { + initrd_start = data->initrd_address; + + if (data->initrd_file && initrd_start == UIMAGE_INVALID_ADDRESS) { initrd_start = data->os_res->start + SZ_8M; if (bootm_verbose(data)) { diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index b56ca14d1d..9c9534eccf 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -16,6 +16,7 @@ #include <mach/board.h> #include <mach/at91_pmc.h> #include <mach/at91sam9260_matrix.h> +#include <mach/at91sam9_sdramc.h> #include <mach/gpio.h> #include <mach/io.h> #include <mach/cpu.h> @@ -24,6 +25,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91_get_sdram_size(); + arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); if (cpu_is_at91sam9g20()) { add_mem_device("sram0", AT91SAM9G20_SRAM_BASE, diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index a109804139..0091e2dbe9 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -15,6 +15,7 @@ #include <asm/hardware.h> #include <mach/at91_pmc.h> #include <mach/at91sam9261_matrix.h> +#include <mach/at91sam9_sdramc.h> #include <mach/board.h> #include <mach/gpio.h> #include <mach/io.h> @@ -24,6 +25,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91_get_sdram_size(); + arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); if (cpu_is_at91sam9g10()) add_mem_device("sram0", AT91SAM9G10_SRAM_BASE, diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 7f916d21a4..e6864802b7 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -15,6 +15,7 @@ #include <asm/hardware.h> #include <mach/at91_pmc.h> #include <mach/at91sam9263_matrix.h> +#include <mach/at91sam9_sdramc.h> #include <mach/board.h> #include <mach/gpio.h> #include <mach/io.h> @@ -23,6 +24,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91_get_sdram_size(); + arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); add_mem_device("sram0", AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE, IORESOURCE_MEM_WRITEABLE); diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h index 5af2b54b12..1ab61e918b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h @@ -83,5 +83,33 @@ #define AT91_SDRAMC_MD_SDRAM 0 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 +#ifndef __ASSEMBLY__ +#include <mach/io.h> +static inline u32 at91_get_sdram_size(void) +{ + u32 val; + u32 size; + + val = at91_sys_read(AT91_SDRAMC_CR); + + /* Formula: + * size = bank << (col + row + 1); + * if (bandwidth == 32 bits) + * size <<= 1; + */ + size = 1; + /* COL */ + size += (val & AT91_SDRAMC_NC) + 8; + /* ROW */ + size += ((val & AT91_SDRAMC_NR) >> 2) + 11; + /* BANK */ + size = ((val & AT91_SDRAMC_NB) ? 4 : 2) << size; + /* bandwidth */ + if (!(val & AT91_SDRAMC_DBW)) + size <<= 1; + + return size; +} +#endif #endif diff --git a/arch/arm/mach-at91/include/mach/barebox-arm-head.h b/arch/arm/mach-at91/include/mach/barebox-arm-head.h new file mode 100644 index 0000000000..a9c8dd44a7 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/barebox-arm-head.h @@ -0,0 +1,33 @@ +#ifndef __MACH_ARM_HEAD_H +#define __MACH_ARM_HEAD_H + +#ifdef CONFIG_SHELL_NONE +#define AT91_EXV6 ".word _barebox_image_size\n" +#else +#define AT91_EXV6 ".word _barebox_bare_init_size\n" +#endif + +static inline void barebox_arm_head(void) +{ + __asm__ __volatile__ ( +#ifdef CONFIG_THUMB2_BAREBOX +#error Thumb2 is not supported +#else + "b reset\n" + "1: b 1b\n" + "1: b 1b\n" + "1: b 1b\n" + "1: b 1b\n" + AT91_EXV6 /* image size to load by the bootrom */ + "1: b 1b\n" + "1: b 1b\n" +#endif + ".asciz \"barebox\"\n" + ".word _text\n" /* text base. If copied there, + * barebox can skip relocation + */ + ".word _barebox_image_size\n" /* image size to copy */ + ); +} + +#endif /* __ASM_ARM_HEAD_H */ diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h b/arch/arm/mach-at91/include/mach/debug_ll.h new file mode 100644 index 0000000000..ee824cbf2f --- /dev/null +++ b/arch/arm/mach-at91/include/mach/debug_ll.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 + * Jean-Christophe PLAGNIOL-VILLARD <planioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#ifndef __MACH_DEBUG_LL_H__ +#define __MACH_DEBUG_LL_H__ + +#include <asm/io.h> +#include <mach/hardware.h> + +#define UART_BASE (AT91_BASE_SYS + AT91_DBGU) + +#define ATMEL_US_CSR 0x0014 +#define ATMEL_US_THR 0x001c +#define ATMEL_US_TXRDY (1 << 1) +#define ATMEL_US_TXEMPTY (1 << 9) + +/* + * The following code assumes the serial port has already been + * initialized by the bootloader. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * + * This does not append a newline + */ +static void putc(int c) +{ + while (!(__raw_readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXRDY)) + barrier(); + __raw_writel(c, UART_BASE + ATMEL_US_THR); + + while (!(__raw_readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) + barrier(); +} +#endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 82a86d74b8..2b595bce43 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -8,7 +8,7 @@ obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o -obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o +obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o usb-imx6.o obj-$(CONFIG_IMX_CLKO) += clko.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c index 8120f56828..9fde84f1a1 100644 --- a/arch/arm/mach-imx/devices.c +++ b/arch/arm/mach-imx/devices.c @@ -20,7 +20,7 @@ struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata) struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata) { - return imx_add_device("i2c-imx", id, base, 0x1000, pdata); + return imx_add_device("i2c-fsl", id, base, 0x1000, pdata); } struct device_d *imx_add_uart(void *base, int id) diff --git a/arch/arm/mach-imx/gpio.c b/arch/arm/mach-imx/gpio.c index fdee20b865..8d5d4ce2b0 100644 --- a/arch/arm/mach-imx/gpio.c +++ b/arch/arm/mach-imx/gpio.c @@ -27,7 +27,8 @@ #include <errno.h> #include <io.h> #include <mach/imx-regs.h> -#include <mach/gpio.h> +#include <gpio.h> +#include <init.h> #if defined CONFIG_ARCH_IMX1 || defined CONFIG_ARCH_IMX21 || defined CONFIG_ARCH_IMX27 #define GPIO_DR 0x1c @@ -48,21 +49,15 @@ #define GPIO_ISR 0x18 #endif -extern void __iomem *imx_gpio_base[]; -extern int imx_gpio_count; +struct imx_gpio_chip { + void __iomem *base; + struct gpio_chip chip; +}; -static void __iomem *gpio_get_base(unsigned gpio) +static void imx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) { - if (gpio >= imx_gpio_count) - return NULL; - - return imx_gpio_base[gpio / 32]; -} - -void gpio_set_value(unsigned gpio, int value) -{ - void __iomem *base = gpio_get_base(gpio); - int shift = gpio % 32; + struct imx_gpio_chip *imxgpio = container_of(chip, struct imx_gpio_chip, chip); + void __iomem *base = imxgpio->base; u32 val; if (!base) @@ -71,59 +66,88 @@ void gpio_set_value(unsigned gpio, int value) val = readl(base + GPIO_DR); if (value) - val |= 1 << shift; + val |= 1 << gpio; else - val &= ~(1 << shift); + val &= ~(1 << gpio); writel(val, base + GPIO_DR); } -int gpio_direction_input(unsigned gpio) +static int imx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { - void __iomem *base = gpio_get_base(gpio); - int shift = gpio % 32; + struct imx_gpio_chip *imxgpio = container_of(chip, struct imx_gpio_chip, chip); + void __iomem *base = imxgpio->base; u32 val; if (!base) return -EINVAL; val = readl(base + GPIO_GDIR); - val &= ~(1 << shift); + val &= ~(1 << gpio); writel(val, base + GPIO_GDIR); return 0; } -int gpio_direction_output(unsigned gpio, int value) +static int imx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) { - void __iomem *base = gpio_get_base(gpio); - int shift = gpio % 32; + struct imx_gpio_chip *imxgpio = container_of(chip, struct imx_gpio_chip, chip); + void __iomem *base = imxgpio->base; u32 val; - if (!base) - return -EINVAL; - - gpio_set_value(gpio, value); + gpio_set_value(gpio + chip->base, value); val = readl(base + GPIO_GDIR); - val |= 1 << shift; + val |= 1 << gpio; writel(val, base + GPIO_GDIR); return 0; } -int gpio_get_value(unsigned gpio) +static int imx_gpio_get_value(struct gpio_chip *chip, unsigned gpio) { - void __iomem *base = gpio_get_base(gpio); - int shift = gpio % 32; + struct imx_gpio_chip *imxgpio = container_of(chip, struct imx_gpio_chip, chip); + void __iomem *base = imxgpio->base; u32 val; - if (!base) - return -EINVAL; - val = readl(base + GPIO_PSR); - return val & (1 << shift) ? 1 : 0; + return val & (1 << gpio) ? 1 : 0; +} + +static struct gpio_ops imx_gpio_ops = { + .direction_input = imx_gpio_direction_input, + .direction_output = imx_gpio_direction_output, + .get = imx_gpio_get_value, + .set = imx_gpio_set_value, +}; + +static int imx_gpio_probe(struct device_d *dev) +{ + struct imx_gpio_chip *imxgpio; + + imxgpio = xzalloc(sizeof(*imxgpio)); + imxgpio->base = dev_request_mem_region(dev, 0); + imxgpio->chip.ops = &imx_gpio_ops; + imxgpio->chip.base = -1; + imxgpio->chip.ngpio = 32; + imxgpio->chip.dev = dev; + gpiochip_add(&imxgpio->chip); + + dev_info(dev, "probed gpiochip%d with base %d\n", dev->id, imxgpio->chip.base); + + return 0; } +static struct driver_d imx_gpio_driver = { + .name = "imx-gpio", + .probe = imx_gpio_probe, +}; + +static int imx_gpio_add(void) +{ + register_driver(&imx_gpio_driver); + return 0; +} +coredevice_initcall(imx_gpio_add); diff --git a/arch/arm/mach-imx/gpio.h b/arch/arm/mach-imx/gpio.h deleted file mode 100644 index 545cebef3b..0000000000 --- a/arch/arm/mach-imx/gpio.h +++ /dev/null @@ -1,4 +0,0 @@ - -extern void *imx_gpio_base[]; -extern int imx_gpio_count; - diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c index 742a260f0a..5a000bc96a 100644 --- a/arch/arm/mach-imx/imx1.c +++ b/arch/arm/mach-imx/imx1.c @@ -16,16 +16,15 @@ */ #include <common.h> +#include <init.h> -#include "gpio.h" - -void *imx_gpio_base[] = { - (void *)0x0021c000, - (void *)0x0021c100, - (void *)0x0021c200, - (void *)0x0021c300, -}; - -int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; - +static int imx1_init(void) +{ + add_generic_device("imx-gpio", 0, NULL, 0x0021c000, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, 0x0021c100, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, 0x0021c200, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 3, NULL, 0x0021c300, 0x100, IORESOURCE_MEM, NULL); + return 0; +} +coredevice_initcall(imx1_init); diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c index bbef33d2d4..85590ee8f4 100644 --- a/arch/arm/mach-imx/imx21.c +++ b/arch/arm/mach-imx/imx21.c @@ -18,8 +18,6 @@ #include <common.h> #include <mach/imx-regs.h> -#include "gpio.h" - int imx_silicon_revision(void) { // Known values: @@ -28,14 +26,15 @@ int imx_silicon_revision(void) return CID; } -void *imx_gpio_base[] = { - (void *)0x10015000, - (void *)0x10015100, - (void *)0x10015200, - (void *)0x10015300, - (void *)0x10015400, - (void *)0x10015500, -}; - -int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; +static int imx21_init(void) +{ + add_generic_device("imx-gpio", 0, NULL, 0x10015000, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, 0x10015100, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, 0x10015200, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 3, NULL, 0x10015300, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 4, NULL, 0x10015400, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 5, NULL, 0x10015500, 0x100, IORESOURCE_MEM, NULL); + return 0; +} +coredevice_initcall(imx21_init); diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c index 19a2909e18..d605022516 100644 --- a/arch/arm/mach-imx/imx25.c +++ b/arch/arm/mach-imx/imx25.c @@ -22,17 +22,6 @@ #include <io.h> #include <sizes.h> -#include "gpio.h" - -void *imx_gpio_base[] = { - (void *)0x53fcc000, - (void *)0x53fd0000, - (void *)0x53fa4000, - (void *)0x53f9c000, -}; - -int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; - u64 imx_uid(void) { u64 uid = 0; @@ -59,6 +48,10 @@ static int imx25_init(void) add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K, IORESOURCE_MEM, &imx25_iim_pdata); + add_generic_device("imx-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 3, NULL, 0x53f9c000, 0x1000, IORESOURCE_MEM, NULL); return 0; } coredevice_initcall(imx25_init); diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c index 1af291d33a..c6e6942c58 100644 --- a/arch/arm/mach-imx/imx27.c +++ b/arch/arm/mach-imx/imx27.c @@ -21,24 +21,11 @@ #include <init.h> #include <io.h> -#include "gpio.h" - int imx_silicon_revision(void) { return CID >> 28; } -void *imx_gpio_base[] = { - (void *)0x10015000, - (void *)0x10015100, - (void *)0x10015200, - (void *)0x10015300, - (void *)0x10015400, - (void *)0x10015500, -}; - -int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; - /* * Initialize MAX on i.MX27. necessary to give the DMA engine * higher priority to the memory than the CPU. Needed for proper @@ -86,6 +73,12 @@ static int imx27_init(void) imx27_init_max(); + add_generic_device("imx-gpio", 0, NULL, 0x10015000, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, 0x10015100, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, 0x10015200, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 3, NULL, 0x10015300, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 4, NULL, 0x10015400, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 5, NULL, 0x10015500, 0x100, IORESOURCE_MEM, NULL); return 0; } coredevice_initcall(imx27_init); diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c index bb713ca876..90dc4e3180 100644 --- a/arch/arm/mach-imx/imx31.c +++ b/arch/arm/mach-imx/imx31.c @@ -20,21 +20,15 @@ #include <sizes.h> #include <mach/imx-regs.h> -#include "gpio.h" - -void *imx_gpio_base[] = { - (void *)0x53fcc000, - (void *)0x53fd0000, - (void *)0x53fa4000, -}; - -int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; - static int imx31_init(void) { add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL); + return 0; } coredevice_initcall(imx31_init); diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c index fe0c99ea72..efbee985d3 100644 --- a/arch/arm/mach-imx/imx35.c +++ b/arch/arm/mach-imx/imx35.c @@ -23,16 +23,6 @@ #include <mach/iim.h> #include <mach/generic.h> -#include "gpio.h" - -void *imx_gpio_base[] = { - (void *)0x53fcc000, - (void *)0x53fd0000, - (void *)0x53fa4000, -}; - -int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; - int imx_silicon_revision() { uint32_t reg; @@ -66,6 +56,10 @@ static int imx35_init(void) add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL); + return 0; } coredevice_initcall(imx35_init); diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index 53205a9215..e43cc65ecd 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -24,17 +24,6 @@ #include <mach/imx-regs.h> #include <mach/clock-imx51_53.h> -#include "gpio.h" - -void *imx_gpio_base[] = { - (void *)MX51_GPIO1_BASE_ADDR, - (void *)MX51_GPIO2_BASE_ADDR, - (void *)MX51_GPIO3_BASE_ADDR, - (void *)MX51_GPIO4_BASE_ADDR, -}; - -int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; - #define SI_REV 0x48 static u32 mx51_silicon_revision; @@ -89,6 +78,11 @@ static int imx51_init(void) add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 0, NULL, 0x73f84000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, 0x73f88000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, 0x73f8c000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 3, NULL, 0x73f90000, 0x1000, IORESOURCE_MEM, NULL); + return 0; } coredevice_initcall(imx51_init); diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c index 7c679bbe79..cb945753b0 100644 --- a/arch/arm/mach-imx/imx53.c +++ b/arch/arm/mach-imx/imx53.c @@ -24,20 +24,6 @@ #include <mach/imx-regs.h> #include <mach/clock-imx51_53.h> -#include "gpio.h" - -void *imx_gpio_base[] = { - (void *)MX53_GPIO1_BASE_ADDR, - (void *)MX53_GPIO2_BASE_ADDR, - (void *)MX53_GPIO3_BASE_ADDR, - (void *)MX53_GPIO4_BASE_ADDR, - (void *)MX53_GPIO5_BASE_ADDR, - (void *)MX53_GPIO6_BASE_ADDR, - (void *)MX53_GPIO7_BASE_ADDR, -}; - -int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; - #define SI_REV 0x48 static u32 mx53_silicon_revision; @@ -88,6 +74,13 @@ static int imx53_init(void) add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 0, NULL, MX53_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, MX53_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, MX53_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 3, NULL, MX53_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 4, NULL, MX53_GPIO5_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 5, NULL, MX53_GPIO6_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 6, NULL, MX53_GPIO7_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } coredevice_initcall(imx53_init); diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index a443343853..c693724a51 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -21,20 +21,6 @@ #include <sizes.h> #include <mach/imx6-regs.h> -#include "gpio.h" - -void *imx_gpio_base[] = { - (void *)MX6_GPIO1_BASE_ADDR, - (void *)MX6_GPIO2_BASE_ADDR, - (void *)MX6_GPIO3_BASE_ADDR, - (void *)MX6_GPIO4_BASE_ADDR, - (void *)MX6_GPIO5_BASE_ADDR, - (void *)MX6_GPIO6_BASE_ADDR, - (void *)MX6_GPIO7_BASE_ADDR, -}; - -int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; - void imx6_init_lowlevel(void) { void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR; @@ -69,3 +55,17 @@ void imx6_init_lowlevel(void) writel(0xffffffff, 0x020c407c); writel(0xffffffff, 0x020c4080); } + +static int imx6_init(void) +{ + add_generic_device("imx-gpio", 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, MX6_GPIO2_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, MX6_GPIO3_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 3, NULL, MX6_GPIO4_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 4, NULL, MX6_GPIO5_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 5, NULL, MX6_GPIO6_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 6, NULL, MX6_GPIO7_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); + + return 0; +} +coredevice_initcall(imx6_init); diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h index 050b7f8921..f613395768 100644 --- a/arch/arm/mach-imx/include/mach/clock.h +++ b/arch/arm/mach-imx/include/mach/clock.h @@ -27,7 +27,7 @@ ulong imx_get_fecclk(void); ulong imx_get_gptclk(void); ulong imx_get_uartclk(void); ulong imx_get_lcdclk(void); -ulong imx_get_i2cclk(void); +ulong fsl_get_i2cclk(void); ulong imx_get_mmcclk(void); ulong imx_get_cspiclk(void); ulong imx_get_ipgclk(void); diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h index 6c0d750050..9ecaa35ffe 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx35.h +++ b/arch/arm/mach-imx/include/mach/devices-imx35.h @@ -16,6 +16,11 @@ static inline struct device_d *imx35_add_i2c2(struct i2c_platform_data *pdata) return imx_add_i2c((void *)IMX_I2C3_BASE, 2, pdata); } +static inline struct device_d *imx35_add_spi0(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)IMX_CSPI1_BASE, 0, pdata); +} + static inline struct device_d *imx35_add_uart0(void) { return imx_add_uart((void *)IMX_UART1_BASE, 0); diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h index ca063c5459..c73e4888ed 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx6.h +++ b/arch/arm/mach-imx/include/mach/devices-imx6.h @@ -49,3 +49,18 @@ static inline struct device_d *imx6_add_spi0(struct spi_imx_master *pdata) { return imx_add_spi((void *)MX6_ECSPI1_BASE_ADDR, 0, pdata); } + +static inline struct device_d *imx6_add_i2c0(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX6_I2C1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx6_add_i2c1(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX6_I2C2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx6_add_i2c2(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX6_I2C3_BASE_ADDR, 2, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h index fafcd61e33..91d4b9bf52 100644 --- a/arch/arm/mach-imx/include/mach/imx35-regs.h +++ b/arch/arm/mach-imx/include/mach/imx35-regs.h @@ -49,6 +49,7 @@ #define IMX_I2C1_BASE 0x43F80000 #define IMX_I2C2_BASE 0x43F98000 #define IMX_I2C3_BASE 0x43F84000 +#define IMX_CSPI1_BASE 0x43FA4000 #define IMX_SDHC1_BASE 0x53FB4000 #define IMX_SDHC2_BASE 0x53FB8000 #define IMX_SDHC3_BASE 0x53FBC000 @@ -75,6 +76,7 @@ #define CCM_CGR2 0x34 #define CCM_CGR3 0x38 +#define CCM_CGR0_CSPI1_SHIFT 10 #define CCM_CGR1_FEC_SHIFT 0 #define CCM_CGR1_I2C1_SHIFT 10 #define CCM_CGR1_SDHC1_SHIFT 26 diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index e62cc79a07..c7b7481d0f 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -74,6 +74,7 @@ #define MX6_WDOG2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x40000) #define MX6_CCM_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x44000) #define MX6_ANATOP_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x48000) +#define MX6_USBPHY1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4a000) #define MX6_SNVS_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4C000) #define MX6_EPIT1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x50000) #define MX6_EPIT2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x54000) diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c index ed14113f76..39e68c85a4 100644 --- a/arch/arm/mach-imx/speed-imx25.c +++ b/arch/arm/mach-imx/speed-imx25.c @@ -78,7 +78,7 @@ unsigned long imx_get_lcdclk(void) return imx_get_perclk(7); } -unsigned long imx_get_i2cclk(void) +unsigned long fsl_get_i2cclk(void) { return imx_get_perclk(6); } diff --git a/arch/arm/mach-imx/speed-imx27.c b/arch/arm/mach-imx/speed-imx27.c index 644fd0462a..7224382299 100644 --- a/arch/arm/mach-imx/speed-imx27.c +++ b/arch/arm/mach-imx/speed-imx27.c @@ -155,7 +155,7 @@ ulong imx_get_lcdclk(void) return imx_get_perclk3(); } -ulong imx_get_i2cclk(void) +ulong fsl_get_i2cclk(void) { return imx_get_ipgclk(); } diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c index 6d4236a020..e0ff1793c5 100644 --- a/arch/arm/mach-imx/speed-imx35.c +++ b/arch/arm/mach-imx/speed-imx35.c @@ -187,11 +187,16 @@ ulong imx_get_fecclk(void) return imx_get_ipgclk(); } -ulong imx_get_i2cclk(void) +ulong fsl_get_i2cclk(void) { return imx_get_ipg_perclk(); } +unsigned long imx_get_cspiclk(void) +{ + return imx_get_ipgclk(); +} + void imx_dump_clocks(void) { printf("mpll: %10ld Hz\n", imx_get_mpllclk()); diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c index 288fe1a640..3903afc821 100644 --- a/arch/arm/mach-imx/speed-imx51.c +++ b/arch/arm/mach-imx/speed-imx51.c @@ -179,7 +179,7 @@ unsigned long imx_get_fecclk(void) return imx_get_ipgclk(); } -unsigned long imx_get_i2cclk(void) +unsigned long fsl_get_i2cclk(void) { return imx_get_ipgclk(); } diff --git a/arch/arm/mach-imx/speed-imx53.c b/arch/arm/mach-imx/speed-imx53.c index ede5ffd75b..b1ba5fd1d2 100644 --- a/arch/arm/mach-imx/speed-imx53.c +++ b/arch/arm/mach-imx/speed-imx53.c @@ -190,7 +190,7 @@ static unsigned long imx_get_ipg_perclk(void) return 0; } -unsigned long imx_get_i2cclk(void) +unsigned long fsl_get_i2cclk(void) { return imx_get_ipg_perclk(); } @@ -232,5 +232,5 @@ void imx_dump_clocks(void) printf("ipg: %ld\n", imx_get_ipgclk()); printf("fec: %ld\n", imx_get_fecclk()); printf("gpt: %ld\n", imx_get_gptclk()); - printf("i2c: %ld\n", imx_get_i2cclk()); + printf("i2c: %ld\n", fsl_get_i2cclk()); } diff --git a/arch/arm/mach-imx/speed-imx6.c b/arch/arm/mach-imx/speed-imx6.c index df2454532d..645b2c9735 100644 --- a/arch/arm/mach-imx/speed-imx6.c +++ b/arch/arm/mach-imx/speed-imx6.c @@ -332,6 +332,11 @@ u32 imx_get_fecclk(void) return __get_ipg_clk(); } +u32 imx_get_i2cclk(void) +{ + return __get_ipg_per_clk(); +} + u32 imx_get_cspiclk(void) { return __get_cspi_clk(); @@ -351,6 +356,7 @@ void imx_dump_clocks(void) printf("mx6q pll8: %d\n", freq); printf("mcu main: %d\n", __get_mcu_main_clk()); printf("periph: %d\n", __get_periph_clk()); + printf("i2c: %d\n", __get_ipg_per_clk()); printf("ipg: %d\n", __get_ipg_clk()); printf("ipg per: %d\n", __get_ipg_per_clk()); printf("cspi: %d\n", __get_cspi_clk()); diff --git a/arch/arm/mach-imx/usb-imx6.c b/arch/arm/mach-imx/usb-imx6.c new file mode 100644 index 0000000000..cd234d2084 --- /dev/null +++ b/arch/arm/mach-imx/usb-imx6.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2012 Steffen Trumtrar, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#include <common.h> +#include <io.h> +#include <mach/imx6-regs.h> + +#define SET 0x4 +#define CLR 0x8 + +#define USBPHY_CTRL 0x30 +#define USB_OTG_CTRL 0x800 +#define USB_UH1_CTRL 0x804 +#define USB_UH2_CTRL 0x808 +#define USB_UH3_CTRL 0x80c + +#define USB_UH1_USBCMD 0x340 + +#define USB_CMD_RUNSTOP (1 << 0) +#define USB_CMD_RESET (1 << 1) + +#define USB_OVER_CUR_DIS (1 << 7) +#define USBPHY_CTRL_SFTRST (1 << 31) +#define USBPHY_CTRL_CLKGATE (1 << 30) +#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) +#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) + +#define USBPHY1_PLL_480_CTRL_EN (1 << 13) +#define USBPHY1_PLL_480_CTRL_POWER (1 << 12) +#define USBPHY1_PLL_480_CTRL_EN_USB_CLK (1 << 6) +#define USBPHY1_PLL_480_CTRL_BYPASS (1 << 16) + +int imx6_usb_phy1_disable_oc(void) +{ + int val; + + /* disable over current detection */ + val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_CTRL); + val |= USB_OVER_CUR_DIS; + writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH1_CTRL); + val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH2_CTRL); + val |= USB_OVER_CUR_DIS; + writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH2_CTRL); + val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH3_CTRL); + val |= USB_OVER_CUR_DIS; + writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH3_CTRL); + + return 0; +} + +int imx6_usb_phy1_enable(void) +{ + int val; + + /* disable external charger detector or DP will be poor */ + writel(0x00180000, MX6_ANATOP_BASE_ADDR + 0x1b0); + writel(0x00180000, MX6_ANATOP_BASE_ADDR + 0x210); + + /* enable usb pll */ + writel(USBPHY1_PLL_480_CTRL_EN | + USBPHY1_PLL_480_CTRL_POWER | + USBPHY1_PLL_480_CTRL_EN_USB_CLK, MX6_ANATOP_BASE_ADDR + 0x24); + + /* turn OFF clk bypass */ + /* at least on imx6 v1.0 this essential for usb to work */ + /* FIXME: test on v1.1. Datasheet declares bit as reserved */ + writel(USBPHY1_PLL_480_CTRL_BYPASS, MX6_ANATOP_BASE_ADDR + 0x28); + + /* stop then reset */ + val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD); + val &= ~USB_CMD_RUNSTOP; + writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD); + while (readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD) & USB_CMD_RUNSTOP); + + val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD); + val |= USB_CMD_RESET; + writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD); + while (readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD) & USB_CMD_RESET); + + /* reset usbphy */ + writel(USBPHY_CTRL_SFTRST, MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL + SET); + udelay(10); + /* clr reset and clkgate */ + writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL + CLR); + + /* clr all pwd bits => power up phy */ + writel(0xffffffff, MX6_USBPHY1_BASE_ADDR + CLR); + + /* set utmilvl2/3 */ + val = readl(MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL); + val |= USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2; + writel(val, MX6_USBPHY1_BASE_ADDR + USBPHY_CTRL + SET); + + return 0; +} diff --git a/arch/arm/mach-mxs/bcb.c b/arch/arm/mach-mxs/bcb.c index d0a3ddc8d3..af51d24b03 100644 --- a/arch/arm/mach-mxs/bcb.c +++ b/arch/arm/mach-mxs/bcb.c @@ -236,7 +236,7 @@ static struct mx28_fcb *create_fcb(struct mtd_info *mtd, void *buf, unsigned fw1 fcb->fw1_start_page = fw1_start_block / mtd->writesize; fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize); - if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) { + if (fw2_start_block) { fcb->fw2_start_page = fw2_start_block / mtd->writesize; fcb->fw2_sectors = fcb->fw1_sectors; } diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c index cf87b57d7f..64ca66619f 100644 --- a/arch/arm/mach-omap/devices-gpmc-nand.c +++ b/arch/arm/mach-omap/devices-gpmc-nand.c @@ -39,37 +39,23 @@ #define GPMC_CONF1_VALx8 0x00000800 #define GPMC_CONF1_VALx16 0x00001800 -/** NAND platform specific settings settings */ -static struct gpmc_nand_platform_data nand_plat = { - .cs = 0, - .max_timeout = MSECOND, - .wait_mon_pin = 0, -}; - /** * @brief gpmc_generic_nand_devices_init - init generic nand device * * @return success/fail based on device function */ -int gpmc_generic_nand_devices_init(int cs, int width, - enum gpmc_ecc_mode eccmode, struct gpmc_config *nand_cfg) +int omap_add_gpmc_nand_device(struct gpmc_nand_platform_data *pdata) { - nand_plat.cs = cs; - - if (width == 16) - nand_cfg->cfg[0] = GPMC_CONF1_VALx16; + if (pdata->device_width == 16) + pdata->nand_cfg->cfg[0] = GPMC_CONF1_VALx16; else - nand_cfg->cfg[0] = GPMC_CONF1_VALx8; - - nand_plat.device_width = width; - nand_plat.ecc_mode = eccmode; - nand_plat.priv = nand_cfg; + pdata->nand_cfg->cfg[0] = GPMC_CONF1_VALx8; /* Configure GPMC CS before register */ - gpmc_cs_config(nand_plat.cs, nand_cfg); + gpmc_cs_config(pdata->cs, pdata->nand_cfg); add_generic_device("gpmc_nand", DEVICE_ID_DYNAMIC, NULL, OMAP_GPMC_BASE, - 1024 * 4, IORESOURCE_MEM, &nand_plat); + 1024 * 4, IORESOURCE_MEM, pdata); return 0; } diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c index 92a8ae043d..5b4daaf031 100644 --- a/arch/arm/mach-omap/gpmc.c +++ b/arch/arm/mach-omap/gpmc.c @@ -31,6 +31,7 @@ #include <clock.h> #include <init.h> #include <io.h> +#include <errno.h> #include <mach/silicon.h> #include <mach/gpmc.h> #include <mach/sys_info.h> @@ -125,3 +126,63 @@ void gpmc_cs_config(char cs, struct gpmc_config *config) mdelay(1); /* Settling time */ } EXPORT_SYMBOL(gpmc_cs_config); + +#define CS_NUM_SHIFT 24 +#define ENABLE_PREFETCH (0x1 << 7) +#define DMA_MPU_MODE 2 + +/** + * gpmc_prefetch_enable - configures and starts prefetch transfer + * @cs: cs (chip select) number + * @fifo_th: fifo threshold to be used for read/ write + * @dma_mode: dma mode enable (1) or disable (0) + * @u32_count: number of bytes to be transferred + * @is_write: prefetch read(0) or write post(1) mode + */ +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, + unsigned int u32_count, int is_write) +{ + if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { + pr_err("gpmc: fifo threshold is not supported\n"); + return -EINVAL; + } + + /* Set the amount of bytes to be prefetched */ + writel(u32_count, GPMC_REG(PREFETCH_CONFIG2)); + + /* Set dma/mpu mode, the prefetch read / post write and + * enable the engine. Set which cs is has requested for. + */ + writel(((cs << CS_NUM_SHIFT) | PREFETCH_FIFOTHRESHOLD(fifo_th) | + ENABLE_PREFETCH | (dma_mode << DMA_MPU_MODE) | + (0x1 & is_write)), + GPMC_REG(PREFETCH_CONFIG1)); + + /* Start the prefetch engine */ + writel(0x1, GPMC_REG(PREFETCH_CONTROL)); + + return 0; +} +EXPORT_SYMBOL(gpmc_prefetch_enable); + +/** + * gpmc_prefetch_reset - disables and stops the prefetch engine + */ +int gpmc_prefetch_reset(int cs) +{ + u32 config1; + + /* check if the same module/cs is trying to reset */ + config1 = readl(GPMC_REG(PREFETCH_CONFIG1)); + if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs) + return -EINVAL; + + /* Stop the PFPW engine */ + writel(0x0, GPMC_REG(PREFETCH_CONTROL)); + + /* Reset/disable the PFPW engine */ + writel(0x0, GPMC_REG(PREFETCH_CONFIG1)); + + return 0; +} +EXPORT_SYMBOL(gpmc_prefetch_reset); diff --git a/arch/arm/mach-omap/include/mach/gpmc.h b/arch/arm/mach-omap/include/mach/gpmc.h index 3ddc5f5b87..ed4e82df7c 100644 --- a/arch/arm/mach-omap/include/mach/gpmc.h +++ b/arch/arm/mach-omap/include/mach/gpmc.h @@ -51,9 +51,10 @@ #define GPMC_TIMEOUT_CONTROL (0x40) #define GPMC_CFG (0x50) #define GPMC_STATUS (0x54) -#define GPMC_PREFETCH_CONFIG_1 (0x1E0) -#define GPMC_PREFETCH_CONFIG_2 (0x1E4) -#define GPMC_PREFETCH_CTRL (0x1EC) +#define GPMC_PREFETCH_CONFIG1 (0x1E0) +#define GPMC_PREFETCH_CONFIG2 (0x1E4) +#define GPMC_PREFETCH_CONTROL (0x1EC) +#define GPMC_PREFETCH_STATUS (0x1f0) #define GPMC_ECC_CONFIG (0x1F4) #define GPMC_ECC_CONTROL (0x1F8) #define GPMC_ECC_SIZE_CONFIG (0x1FC) @@ -138,6 +139,15 @@ #define GPMC_SIZE_32M 0x0E #define GPMC_SIZE_16M 0x0F +#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 +#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) +#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) +#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) + +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, + unsigned int u32_count, int is_write); +int gpmc_prefetch_reset(int cs); + #define NAND_WP_BIT 0x00000010 #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-omap/include/mach/gpmc_nand.h b/arch/arm/mach-omap/include/mach/gpmc_nand.h index b9c659d1a9..582fb36e8f 100644 --- a/arch/arm/mach-omap/include/mach/gpmc_nand.h +++ b/arch/arm/mach-omap/include/mach/gpmc_nand.h @@ -50,10 +50,6 @@ struct gpmc_nand_platform_data { /** If there are any special setups you'd want to do */ int (*nand_setup) (struct gpmc_nand_platform_data *); - /** set up if we want H/w ECC here and other - * platform specific configs here - */ - unsigned short plat_options; /** ecc mode to use */ enum gpmc_ecc_mode ecc_mode; /** setup any special options */ @@ -62,24 +58,14 @@ struct gpmc_nand_platform_data { char device_width; /** Set this to WAITx+1, so GPMC WAIT0 will be 1 and so on. */ char wait_mon_pin; - /** Set this to the max timeout for the device */ - uint64_t max_timeout; /* if you like a custom oob use this. */ struct nand_ecclayout *oob; - /** platform specific private data */ - void *priv; + /** gpmc config for nand */ + struct gpmc_config *nand_cfg; }; -/** Platform specific options definitions */ -/** plat_options: Wait montioring pin low */ -#define NAND_WAITPOL_LOW (0 << 0) -/** plat_options: Wait montioring pin high */ -#define NAND_WAITPOL_HIGH (1 << 0) -#define NAND_WAITPOL_MASK (1 << 0) - -int gpmc_generic_nand_devices_init(int cs, int width, - enum gpmc_ecc_mode, struct gpmc_config *nand_cfg); +int omap_add_gpmc_nand_device(struct gpmc_nand_platform_data *pdata); extern struct gpmc_config omap3_nand_cfg; extern struct gpmc_config omap4_nand_cfg; diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h index 0a31d09e06..e5302d6c74 100644 --- a/arch/arm/mach-omap/include/mach/omap4-clock.h +++ b/arch/arm/mach-omap/include/mach/omap4-clock.h @@ -271,6 +271,20 @@ #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 + /* Used to index into DPLL parameter tables */ struct dpll_param { unsigned int m; @@ -289,6 +303,8 @@ struct dpll_param { #define OMAP4_MPU_DPLL_PARAM_38M4 {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} #define OMAP4_MPU_DPLL_PARAM_38M4_MPU600 {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} #define OMAP4_MPU_DPLL_PARAM_38M4_MPU1000 {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} +/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */ +#define OMAP4_MPU_DPLL_PARAM_19M2_MPU920 {0x23F, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} #define OMAP4_IVA_DPLL_PARAM_19M2 {0x61, 0x01, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00} #define OMAP4_IVA_DPLL_PARAM_38M4 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00} @@ -316,5 +332,8 @@ void omap4_configure_usb_dpll(const struct dpll_param *dpll_param); void omap4_configure_core_dpll_no_lock(const struct dpll_param *param); void omap4_lock_core_dpll(void); void omap4_lock_core_dpll_shadow(const struct dpll_param *param); +void omap4_enable_gpio1_wup_clocks(void); +void omap4_enable_gpio_clocks(void); void omap4_enable_all_clocks(void); +void omap4_do_scale_tps62361(u32 reg, u32 volt_mv); diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h index c7854751ad..4082bac34a 100644 --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h +++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h @@ -60,6 +60,13 @@ #define OMAP44XX_PRM_VC_VAL_BYPASS (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba0) #define OMAP44XX_PRM_VC_CFG_I2C_MODE (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba8) #define OMAP44XX_PRM_VC_CFG_I2C_CLK (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7bac) +#define OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 +#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 +#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F +#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 +#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF +#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_SHIFT 16 +#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_MASK 0xFF /* IRQ */ #define OMAP44XX_PRM_IRQSTATUS_MPU_A9 (OMAP44XX_WAKEUP_L4_IO_BASE + 0x6010) @@ -94,6 +101,10 @@ #define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20) #define DMM_LISA_MAP_SYS_SIZE_SHIFT 20 #define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24) + +/* Memory Adapter (4460 onwards) */ +#define OMAP44XX_MA_BASE 0x482AF000 + /* * Hardware Register Details */ @@ -178,6 +189,6 @@ struct dpll_param; void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *); void omap4_power_i2c_send(u32); unsigned int omap4_revision(void); -noinline int omap4_scale_vcores(void); +noinline int omap4_scale_vcores(unsigned vsel0_pin); #endif diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c index 3ab01f0d3a..1481f16ffd 100644 --- a/arch/arm/mach-omap/omap4_clock.c +++ b/arch/arm/mach-omap/omap4_clock.c @@ -1,6 +1,7 @@ #include <common.h> #include <io.h> #include <mach/syslib.h> +#include <mach/silicon.h> #include <mach/clocks.h> #define LDELAY 12000000 @@ -13,6 +14,10 @@ void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param) sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */ + /* Errata ID: i700, clear CM_CLKSEL_DPLL_MPU[22] : DCC_EN */ + if (omap4_revision() >= OMAP4460_ES1_0) + sr32(CM_CLKSEL_DPLL_MPU, 0, 22, 0); + /* Set M,N,M2 values */ sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param->m); sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param->n); @@ -197,6 +202,27 @@ void omap4_lock_core_dpll_shadow(const struct dpll_param *param) wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_CORE, LDELAY); } +void omap4_enable_gpio_clocks(void) +{ + sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY); +} + +void omap4_enable_gpio1_wup_clocks(void) +{ + /* WKUP clocks */ + sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1); + wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY); +} + void omap4_enable_all_clocks(void) { /* Enable Ducati clocks */ @@ -254,16 +280,7 @@ void omap4_enable_all_clocks(void) wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY); /* GPIO clocks */ - sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY); + omap4_enable_gpio_clocks(); sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2); @@ -313,8 +330,7 @@ void omap4_enable_all_clocks(void) wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_UART4_CLKCTRL, LDELAY); /* WKUP clocks */ - sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1); - wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY); + omap4_enable_gpio1_wup_clocks(); sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002); wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY); @@ -378,3 +394,21 @@ void omap4_enable_all_clocks(void) sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); } +void omap4_do_scale_tps62361(u32 reg, u32 volt_mv) +{ + u32 temp, step; + + step = volt_mv - TPS62361_BASE_VOLT_MV; + step /= 10; + + temp = TPS62361_I2C_SLAVE_ADDR | + (reg << OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | + (step << OMAP44XX_PRM_VC_VAL_BYPASS_DATA_SHIFT) | + OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT; + debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step); + + writel(temp, OMAP44XX_PRM_VC_VAL_BYPASS); + if (!wait_on_value(OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT, 0, + OMAP44XX_PRM_VC_VAL_BYPASS, LDELAY)) + puts("Scaling voltage failed for vdd_mpu from TPS\n"); +} diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index de6993475d..617d786984 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -7,6 +7,7 @@ #include <mach/syslib.h> #include <mach/xload.h> #include <mach/gpmc.h> +#include <mach/gpio.h> /* * The following several lines are taken from U-Boot to support @@ -28,6 +29,10 @@ #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +/* EMIF_L3_CONFIG register value */ +#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 + void __noreturn reset_cpu(unsigned long addr) { writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); @@ -263,14 +268,15 @@ int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs) static void reset_phy(unsigned int base) { - *(volatile int*)(base + IODFT_TLGC) |= (1 << 10); + unsigned int val = readl(base + IODFT_TLGC); + val |= (1 << 10); + writel(val, base + IODFT_TLGC); } void omap4_ddr_init(const struct ddr_regs *ddr_regs, const struct dpll_param *core) { - unsigned int rev; - rev = omap4_revision(); + unsigned int rev = omap4_revision(); if (rev == OMAP4430_ES2_0) { writel(0x9e9e9e9e, 0x4A100638); @@ -290,8 +296,15 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, /* Both EMIFs 128 byte interleaved */ writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0); - *(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000; - *(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100; + writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2); + writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3); + + if (rev >= OMAP4460_ES1_0) { + writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0); + + writel(0x00000000, OMAP44XX_MA_BASE + DMM_LISA_MAP_2); + writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3); + } /* DDR needs to be initialised @ 19.2 MHz * So put core DPLL in bypass mode @@ -301,10 +314,10 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, /* No IDLE: BUG in SDC */ sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; - *(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; + writel(0x0, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL); + writel(0x0, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL); omap4_emif_config(OMAP44XX_EMIF1_BASE, ddr_regs); omap4_emif_config(OMAP44XX_EMIF2_BASE, ddr_regs); @@ -313,13 +326,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, omap4_lock_core_dpll_shadow(core); /* Set DLL_OVERRIDE = 0 */ - *(volatile int*)CM_DLL_CTRL = 0x0; + writel(0x0, CM_DLL_CTRL); delay(200); /* Check for DDR PHY ready for EMIF1 & EMIF2 */ - while((((*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \ - || (((*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04)); + while (((readl(OMAP44XX_EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04) \ + || ((readl(OMAP44XX_EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04)); /* Reprogram the DDR PYHY Control register */ /* PHY control values */ @@ -331,9 +344,16 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, /* No IDLE: BUG in SDC */ //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; - *(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; + //while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + writel(0x80000000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL); + writel(0x80000000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL); + + if (rev >= OMAP4460_ES1_0) { + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, + OMAP44XX_EMIF1_BASE + EMIF_L3_CONFIG); + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, + OMAP44XX_EMIF2_BASE + EMIF_L3_CONFIG); + } /* * DMM : DMM_LISA_MAP_0(Section_0) @@ -347,8 +367,8 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs, reset_phy(OMAP44XX_EMIF1_BASE); reset_phy(OMAP44XX_EMIF2_BASE); - *((volatile int *)0x80000000) = 0; - *((volatile int *)0x80000080) = 0; + writel(0, 0x80000000); + writel(0, 0x80000080); } void omap4_power_i2c_send(u32 r) @@ -466,7 +486,7 @@ enum omap_boot_src omap4_bootsrc(void) #define I2C_SLAVE 0x12 -noinline int omap4_scale_vcores(void) +noinline int omap4_scale_vcores(unsigned vsel0_pin) { unsigned int rev = omap4_revision(); @@ -476,8 +496,41 @@ noinline int omap4_scale_vcores(void) writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE); writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK); + /* TPS - supplies vdd_mpu on 4460 */ + if (rev >= OMAP4460_ES1_0) { + /* + * Setup SET1 and SET0 with right values so that kernel + * can use either of them based on its needs. + */ + omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430); + omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430); + + /* + * Select SET1 in TPS62361: + * VSEL1 is grounded on board. So the following selects + * VSEL1 = 0 and VSEL0 = 1 + */ + gpio_direction_output(vsel0_pin, 0); + gpio_set_value(vsel0_pin, 1); + } + /* set VCORE1 force VSEL */ - omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE); + /* + * 4430 : supplies vdd_mpu + * Setting a high voltage for Nitro mode as smart reflex is not enabled. + * We use the maximum possible value in the AVS range because the next + * higher voltage in the discrete range (code >= 0b111010) is way too + * high + * + * 4460 : supplies vdd_core + * + */ + if (rev < OMAP4460_ES1_0) + /* 0x55: i2c addr, 3A: ~ 1430 mvolts*/ + omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE); + else + /* 0x55: i2c addr, 28: ~ 1200 mvolts*/ + omap4_power_i2c_send((0x2855 << 8) | I2C_SLAVE); /* FIXME: set VCORE2 force VSEL, Check the reset value */ omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE); @@ -490,6 +543,7 @@ noinline int omap4_scale_vcores(void) case OMAP4430_ES2_1: omap4_power_i2c_send((0x2A61 << 8) | I2C_SLAVE); break; + /* > OMAP4460_ES1_0 : VCORE3 not connected */ } return 0; diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h new file mode 100644 index 0000000000..0f6c0987f2 --- /dev/null +++ b/arch/blackfin/include/asm/unaligned.h @@ -0,0 +1,11 @@ +#ifndef _ASM_BLACKFIN_UNALIGNED_H +#define _ASM_BLACKFIN_UNALIGNED_H + +#include <linux/unaligned/le_struct.h> +#include <linux/unaligned/be_byteshift.h> +#include <linux/unaligned/generic.h> + +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le + +#endif /* _ASM_BLACKFIN_UNALIGNED_H */ diff --git a/arch/mips/boards/dlink-dir-320/serial.c b/arch/mips/boards/dlink-dir-320/serial.c index 3eaab2a129..1185248d5d 100644 --- a/arch/mips/boards/dlink-dir-320/serial.c +++ b/arch/mips/boards/dlink-dir-320/serial.c @@ -35,7 +35,7 @@ static struct NS16550_plat serial_plat = { static int dir320_console_init(void) { /* Register the serial port */ - add_ns16550_device(-1, DEBUG_LL_UART_ADDR, 8, + add_ns16550_device(DEVICE_ID_DYNAMIC, DEBUG_LL_UART_ADDR, 8, IORESOURCE_MEM_8BIT, &serial_plat); return 0; diff --git a/arch/mips/boards/qemu-malta/init.c b/arch/mips/boards/qemu-malta/init.c index 0efc92a141..45f66f243d 100644 --- a/arch/mips/boards/qemu-malta/init.c +++ b/arch/mips/boards/qemu-malta/init.c @@ -58,7 +58,7 @@ static struct NS16550_plat serial_plat = { static int malta_console_init(void) { /* Register the serial port */ - add_ns16550_device(-1, DEBUG_LL_UART_ADDR, 8, + add_ns16550_device(DEVICE_ID_DYNAMIC, DEBUG_LL_UART_ADDR, 8, IORESOURCE_MEM_8BIT, &serial_plat); return 0; diff --git a/arch/mips/boards/rzx50/serial.c b/arch/mips/boards/rzx50/serial.c index 308cd18eaf..3f593c9a92 100644 --- a/arch/mips/boards/rzx50/serial.c +++ b/arch/mips/boards/rzx50/serial.c @@ -58,7 +58,7 @@ static struct NS16550_plat serial_plat = { static int rzx50_console_init(void) { /* Register the serial port */ - add_ns16550_device(-1, UART1_BASE, 8 << JZ4750D_UART_SHIFT, + add_ns16550_device(DEVICE_ID_DYNAMIC, UART1_BASE, 8 << JZ4750D_UART_SHIFT, IORESOURCE_MEM_8BIT, &serial_plat); return 0; diff --git a/arch/nios2/boards/generic/generic.c b/arch/nios2/boards/generic/generic.c index 2c998fe3ac..cdaaa02062 100644 --- a/arch/nios2/boards/generic/generic.c +++ b/arch/nios2/boards/generic/generic.c @@ -34,7 +34,7 @@ static struct device_d mac_dev = { static int generic_devices_init(void) { - add_cfi_flash_device(-1, NIOS_SOPC_FLASH_BASE, NIOS_SOPC_FLASH_SIZE, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, NIOS_SOPC_FLASH_BASE, NIOS_SOPC_FLASH_SIZE, 0); add_mem_device("ram0", NIOS_SOPC_MEMORY_BASE, NIOS_SOPC_MEMORY_SIZE, IORESOURCE_MEM_WRITEABLE); register_device(&mac_dev); diff --git a/arch/openrisc/boards/generic/generic.c b/arch/openrisc/boards/generic/generic.c index 6a9ce5b864..54c73a5aa3 100644 --- a/arch/openrisc/boards/generic/generic.c +++ b/arch/openrisc/boards/generic/generic.c @@ -12,7 +12,7 @@ static struct NS16550_plat serial_plat = { static int openrisc_console_init(void) { /* Register the serial port */ - add_ns16550_device(-1, OPENRISC_SOPC_UART_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat); + add_ns16550_device(DEVICE_ID_DYNAMIC, OPENRISC_SOPC_UART_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat); return 0; } diff --git a/arch/openrisc/include/asm/unaligned.h b/arch/openrisc/include/asm/unaligned.h new file mode 100644 index 0000000000..1141cbd6fd --- /dev/null +++ b/arch/openrisc/include/asm/unaligned.h @@ -0,0 +1,51 @@ +/* + * OpenRISC Linux + * + * Linux architectural port borrowing liberally from similar works of + * others. All original copyrights apply as per the original source + * declaration. + * + * OpenRISC implementation: + * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> + * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> + * et al. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ASM_OPENRISC_UNALIGNED_H +#define __ASM_OPENRISC_UNALIGNED_H + +/* + * This is copied from the generic implementation and the C-struct + * variant replaced with the memmove variant. The GCC compiler + * for the OR32 arch optimizes too aggressively for the C-struct + * variant to work, so use the memmove variant instead. + * + * It may be worth considering implementing the unaligned access + * exception handler and allowing unaligned accesses (access_ok.h)... + * not sure if it would be much of a performance win without further + * investigation. + */ +#include <asm/byteorder.h> + +#if defined(__LITTLE_ENDIAN) +# include <linux/unaligned/le_memmove.h> +# include <linux/unaligned/be_byteshift.h> +# include <linux/unaligned/generic.h> +# define get_unaligned __get_unaligned_le +# define put_unaligned __put_unaligned_le +#elif defined(__BIG_ENDIAN) +# include <linux/unaligned/be_memmove.h> +# include <linux/unaligned/le_byteshift.h> +# include <linux/unaligned/generic.h> +# define get_unaligned __get_unaligned_be +# define put_unaligned __put_unaligned_be +#else +# error need to define endianess +#endif + +#endif /* __ASM_OPENRISC_UNALIGNED_H */ diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c index 20897cbaee..c5fae0d7aa 100644 --- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c +++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c @@ -26,6 +26,7 @@ #include <driver.h> #include <ns16550.h> #include <types.h> +#include <i2c/i2c.h> #include <partition.h> #include <memory.h> #include <asm/cache.h> @@ -34,7 +35,7 @@ #include <mach/mpc85xx.h> #include <mach/mmu.h> #include <mach/immap_85xx.h> -#include <mach/clocks.h> +#include <mach/clock.h> #include <mach/early_udelay.h> #define VSC7385_RST_SET 0x00080000 @@ -61,9 +62,19 @@ #define SYSCLK_50 50000000 #define SYSCLK_100 100000000 +/* I2C busses. */ +struct i2c_platform_data i2cplat = { + .bitrate = 400000, +}; + static int devices_init(void) { - add_cfi_flash_device(-1, CFG_FLASH_BASE, 16 << 20, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 16 << 20, 0); + + add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, + 0x100, IORESOURCE_MEM, &i2cplat); + add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, + 0x100, IORESOURCE_MEM, &i2cplat); devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED, "self0"); @@ -81,7 +92,7 @@ static int p2020_console_init(void) { serial_plat.clock = fsl_get_bus_freq(0); - add_ns16550_device(-1, 0xffe04500, 16, IORESOURCE_MEM_8BIT, + add_ns16550_device(DEVICE_ID_DYNAMIC, 0xffe04500, 16, IORESOURCE_MEM_8BIT, &serial_plat); return 0; } diff --git a/arch/ppc/configs/p2020rdb_defconfig b/arch/ppc/configs/p2020rdb_defconfig index f8a0687251..c040635e70 100644 --- a/arch/ppc/configs/p2020rdb_defconfig +++ b/arch/ppc/configs/p2020rdb_defconfig @@ -21,3 +21,6 @@ CONFIG_MALLOC_SIZE=0x200000 CONFIG_BAUDRATE=115200 CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_RELOCATABLE=y +CONFIG_I2C=y +CONFIG_I2C_IMX=y +CONFIG_CMD_I2C=y diff --git a/arch/ppc/include/asm/fsl_i2c.h b/arch/ppc/include/asm/fsl_i2c.h deleted file mode 100644 index 4f71341327..0000000000 --- a/arch/ppc/include/asm/fsl_i2c.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Freescale I2C Controller - * - * Copyright 2006 Freescale Semiconductor, Inc. - * - * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, - * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), - * and Jeff Brown. - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_FSL_I2C_H_ -#define _ASM_FSL_I2C_H_ - -#include <asm/types.h> - -typedef struct fsl_i2c { - - u8 adr; /* I2C slave address */ - u8 res0[3]; -#define I2C_ADR 0xFE -#define I2C_ADR_SHIFT 1 -#define I2C_ADR_RES ~(I2C_ADR) - - u8 fdr; /* I2C frequency divider register */ - u8 res1[3]; -#define IC2_FDR 0x3F -#define IC2_FDR_SHIFT 0 -#define IC2_FDR_RES ~(IC2_FDR) - - u8 cr; /* I2C control redister */ - u8 res2[3]; -#define I2C_CR_MEN 0x80 -#define I2C_CR_MIEN 0x40 -#define I2C_CR_MSTA 0x20 -#define I2C_CR_MTX 0x10 -#define I2C_CR_TXAK 0x08 -#define I2C_CR_RSTA 0x04 -#define I2C_CR_BCST 0x01 - - u8 sr; /* I2C status register */ - u8 res3[3]; -#define I2C_SR_MCF 0x80 -#define I2C_SR_MAAS 0x40 -#define I2C_SR_MBB 0x20 -#define I2C_SR_MAL 0x10 -#define I2C_SR_BCSTM 0x08 -#define I2C_SR_SRW 0x04 -#define I2C_SR_MIF 0x02 -#define I2C_SR_RXAK 0x01 - - u8 dr; /* I2C data register */ - u8 res4[3]; -#define I2C_DR 0xFF -#define I2C_DR_SHIFT 0 -#define I2C_DR_RES ~(I2C_DR) - - u8 dfsrr; /* I2C digital filter sampling rate register */ - u8 res5[3]; -#define I2C_DFSRR 0x3F -#define I2C_DFSRR_SHIFT 0 -#define I2C_DFSRR_RES ~(I2C_DR) - - /* Fill out the reserved block */ - u8 res6[0xE8]; -} fsl_i2c_t; - -#endif /* _ASM_I2C_H_ */ diff --git a/arch/ppc/include/asm/unaligned.h b/arch/ppc/include/asm/unaligned.h new file mode 100644 index 0000000000..a41fa8cb4a --- /dev/null +++ b/arch/ppc/include/asm/unaligned.h @@ -0,0 +1,16 @@ +#ifndef _ASM_PPC_UNALIGNED_H +#define _ASM_PPC_UNALIGNED_H + +#ifdef __KERNEL__ + +/* + * The PowerPC can do unaligned accesses itself in big endian mode. + */ +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be + +#endif /* __KERNEL__ */ +#endif /* _ASM_PPC_UNALIGNED_H */ diff --git a/arch/ppc/mach-mpc85xx/include/mach/clocks.h b/arch/ppc/mach-mpc85xx/include/mach/clock.h index 2ab367b2ec..e20d68518e 100644 --- a/arch/ppc/mach-mpc85xx/include/mach/clocks.h +++ b/arch/ppc/mach-mpc85xx/include/mach/clock.h @@ -12,5 +12,6 @@ struct sys_info { unsigned long fsl_get_bus_freq(ulong dummy); unsigned long fsl_get_timebase_clock(void); +unsigned long fsl_get_i2c_freq(void); void fsl_get_sys_info(struct sys_info *sysInfo); #endif /* __ASM_ARCH_CLOCKS_H */ diff --git a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h index b80224952d..b686a09b6a 100644 --- a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h +++ b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h @@ -129,4 +129,7 @@ #define MPC85xx_DEVDISR_TB1 0x00001000 #define MPC85xx_GUTS_RSTCR_OFFSET 0xb0 +#define I2C1_BASE_ADDR (CFG_IMMR + 0x3000) +#define I2C2_BASE_ADDR (CFG_IMMR + 0x3100) + #endif /*__IMMAP_85xx__*/ diff --git a/arch/ppc/mach-mpc85xx/speed.c b/arch/ppc/mach-mpc85xx/speed.c index 40d3664188..6778d57c29 100644 --- a/arch/ppc/mach-mpc85xx/speed.c +++ b/arch/ppc/mach-mpc85xx/speed.c @@ -30,7 +30,7 @@ #include <common.h> #include <asm/processor.h> -#include <mach/clocks.h> +#include <mach/clock.h> #include <mach/immap_85xx.h> #include <mach/mpc85xx.h> @@ -102,3 +102,12 @@ unsigned long fsl_get_timebase_clock(void) return (sysinfo.freqSystemBus + 4UL)/8UL; } + +unsigned long fsl_get_i2c_freq(void) +{ + struct sys_info sysinfo; + + fsl_get_sys_info(&sysinfo); + + return sysinfo.freqSystemBus / 2; +} diff --git a/arch/ppc/mach-mpc85xx/time.c b/arch/ppc/mach-mpc85xx/time.c index 408a28a2eb..c50591c961 100644 --- a/arch/ppc/mach-mpc85xx/time.c +++ b/arch/ppc/mach-mpc85xx/time.c @@ -25,7 +25,7 @@ #include <common.h> #include <clock.h> #include <init.h> -#include <mach/clocks.h> +#include <mach/clock.h> uint64_t ppc_clocksource_read(void) { diff --git a/arch/x86/boards/x86_generic/generic_pc.c b/arch/x86/boards/x86_generic/generic_pc.c index 4be1237607..046f76db72 100644 --- a/arch/x86/boards/x86_generic/generic_pc.c +++ b/arch/x86/boards/x86_generic/generic_pc.c @@ -78,7 +78,7 @@ static struct NS16550_plat serial_plat = { static int pc_console_init(void) { /* Register the serial port */ - add_ns16550_device(-1, 0x3f8, 8, 0, &serial_plat); + add_ns16550_device(DEVICE_ID_DYNAMIC, 0x3f8, 8, 0, &serial_plat); return 0; } |