diff options
Diffstat (limited to 'arch')
35 files changed, 537 insertions, 572 deletions
diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c index c0825949a8..71ab793354 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c @@ -30,6 +30,13 @@ #include <asm/barebox-arm-head.h> #define TPS62361_VSEL0_GPIO 182 +#define LPDDR2_2G 0x5 +#define LPDDR2_4G 0x6 +#define LPDDR2_DENSITY_MASK 0x3C +#define LPDDR2_DENSITY_SHIFT 2 +#define EMIF_SDRAM_CONFIG 0x0008 +#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050 +#define EMIF_LPDDR2_MODE_REG_DATA 0x0040 void set_muxconf_regs(void); @@ -61,8 +68,23 @@ static const struct ddr_regs ddr_regs_mt42L128M64_25_400_mhz = { .mr2 = 0x4 }; +static const struct ddr_regs ddr_regs_mt42L128M64D2LL_25_400_mhz = { + .tim1 = 0x10EB0662, + .tim2 = 0x205715D2, + .tim3 = 0x00B1C53F, + .phy_ctrl_1 = 0x849FF409, + .ref_ctrl = 0x00000618, + .config_init = 0x80001AB2, + .config_final = 0x80001AB2, + .zq_config = 0x500B3214, + .mr1 = 0x83, + .mr2 = 0x4 +}; + static void noinline pcm049_init_lowlevel(void) { + unsigned int density; + struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; @@ -75,9 +97,17 @@ static void noinline pcm049_init_lowlevel(void) set_muxconf_regs(); #ifdef CONFIG_1024MB_DDR2RAM + omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); + writel(EMIF_SDRAM_CONFIG, OMAP44XX_EMIF1_BASE + + EMIF_LPDDR2_MODE_REG_CONFIG); + density = (readl(OMAP44XX_EMIF1_BASE + EMIF_LPDDR2_MODE_REG_DATA) & + LPDDR2_DENSITY_MASK) >> LPDDR2_DENSITY_SHIFT; + if (density == LPDDR2_2G) omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core); + else if (density == LPDDR2_4G) + omap4_ddr_init(&ddr_regs_mt42L128M64D2LL_25_400_mhz, &core); #else - omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); + omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); #endif /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ diff --git a/arch/arm/boards/phytec-som-imx6/Makefile b/arch/arm/boards/phytec-som-imx6/Makefile index 2f9c4a8a8f..73456aed8b 100644 --- a/arch/arm/boards/phytec-som-imx6/Makefile +++ b/arch/arm/boards/phytec-som-imx6/Makefile @@ -2,3 +2,4 @@ obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-physom-imx6 bbenv-y += defaultenv-physom-imx6-phycore +bbenv-y += defaultenv-physom-imx6ul-phycore diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index 930ad74d74..ed9453bdda 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -30,6 +30,9 @@ #include <of.h> #include <mach/bbu.h> #include <platform_data/eth-fec.h> +#include <mfd/imx6q-iomuxc-gpr.h> +#include <linux/clk.h> +#include <linux/micrel_phy.h> #include <globalvar.h> @@ -86,6 +89,56 @@ static unsigned int get_module_rev(void) return 16 - val; } +int ksz8081_phy_fixup(struct phy_device *phydev) +{ + phy_write(phydev, 0x1f, 0x8190); + phy_write(phydev, 0x16, 0x202); + + return 0; +} + +static int imx6ul_setup_fec(void) +{ + void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000; + uint32_t val; + struct clk *clk; + + phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, + ksz8081_phy_fixup); + + clk = clk_lookup("enet_ptp"); + if (IS_ERR(clk)) + goto err; + + clk_enable(clk); + + clk = clk_lookup("enet_ref"); + if (IS_ERR(clk)) + goto err; + clk_enable(clk); + + clk = clk_lookup("enet_ref_125m"); + if (IS_ERR(clk)) + goto err; + + clk_enable(clk); + + val = readl(gprbase + IOMUXC_GPR1); + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ + val &= ~(1 << 13); + val |= (1 << 17); + /* Use 50M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], set gpr1[18]*/ + val &= ~(1 << 14); + val |= (1 << 18); + writel(val, gprbase + IOMUXC_GPR1); + + return 0; +err: + pr_err("Setting up DFEC\n"); + + return -EIO; +} + static int physom_imx6_devices_init(void) { int ret; @@ -121,6 +174,11 @@ static int physom_imx6_devices_init(void) default_environment_path = "/chosen/environment-spinor"; default_envdev = "SPI NOR flash"; + } else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) { + barebox_set_hostname("phyCORE-i.MX6UL"); + default_environment_path = "/chosen/environment-nand"; + default_envdev = "NAND flash"; + imx6ul_setup_fec(); } else return 0; @@ -171,6 +229,8 @@ static int physom_imx6_devices_init(void) || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { defaultenv_append_directory(defaultenv_physom_imx6_phycore); + } else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) { + defaultenv_append_directory(defaultenv_physom_imx6ul_phycore); } return 0; diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/nand b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/nand new file mode 100644 index 0000000000..6ec0d44357 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/nand @@ -0,0 +1,8 @@ +#!/bin/sh + +[ ! -e /dev/nand0.root.ubi ] && ubiattach /dev/nand0.root + +global.bootm.image="/dev/nand0.root.ubi.kernel" +global.bootm.oftree="/dev/nand0.root.ubi.oftree" + +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/automount new file mode 100644 index 0000000000..71d9086582 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/automount @@ -0,0 +1,9 @@ +#!/bin/sh + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +mkdir -p /mnt/mmc +automount -d /mnt/mmc 'mmc0.probe=1 && [ -e /dev/mmc0.0 ] && mount /dev/mmc0.0 /mnt/mmc' diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg new file mode 100644 index 0000000000..c4122d245d --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg @@ -0,0 +1,9 @@ + +#define SETUP_MDCFG0 \ + wm 32 0x021B000C 0x676B52F3 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021B0040 0x0000004F; \ + wm 32 0x021B0000 0x84180000 + +#include "flash-header-phytec-pcl063.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h new file mode 100644 index 0000000000..5401e4243e --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h @@ -0,0 +1,70 @@ + +loadaddr 0x80000000 +soc imx6 +dcdofs 0x400 + +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +wm 32 0x020E027C 0x00000030 +wm 32 0x020E0250 0x00000030 +wm 32 0x020E024C 0x00000030 +wm 32 0x020E0490 0x00000030 +wm 32 0x020E0288 0x00000030 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000030 +wm 32 0x020E0264 0x00000030 +wm 32 0x020E04A0 0x00000030 +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000030 +wm 32 0x020E0284 0x00000030 +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000030 +wm 32 0x020E04A4 0x00000030 +wm 32 0x020E0244 0x00000030 +wm 32 0x020E0248 0x00000030 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +wm 32 0x021B080C 0x00000000 +wm 32 0x021B083C 0x41480148 +wm 32 0x021B0848 0x40403E42 +wm 32 0x021B0850 0x40405852 +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +wm 32 0x021B08C0 0x00922012 +wm 32 0x021B0858 0x00000F00 +wm 32 0x021B08b8 0x00000800 +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x1B333030 + +SETUP_MDCFG0 + +wm 32 0x021B0010 0xB66D0B63 +wm 32 0x021B0014 0x01FF00DB +wm 32 0x021B0018 0x00211740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x006B1023 + +SETUP_MDASP_MDCTL + +wm 32 0x021b0890 0x00400A38 +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 +wm 32 0x021B0020 0x00007800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002556D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index c732d32a96..3ab88f4a52 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -51,17 +51,28 @@ static void __noreturn start_imx6_phytec_common(uint32_t size, bool do_early_uart_config, void *fdt_blob_fixed_offset) { + int cpu_type = __imx6_cpu_type(); void *fdt; - imx6_cpu_lowlevel_init(); - - arm_setup_stack(0x00920000 - 8); + if (cpu_type == IMX6_CPUTYPE_IMX6UL) { + arm_cpu_lowlevel_init(); + /* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */ + arm_setup_stack(0x00910000 - 8); + } else { + imx6_cpu_lowlevel_init(); + /* OCRAM Free Area is 0x00907000 to 0x00938000 (196KB) */ + arm_setup_stack(0x00920000 - 8); + } if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); fdt = fdt_blob_fixed_offset - get_runtime_offset(); - barebox_arm_entry(0x10000000, size, fdt); + + if (cpu_type == IMX6_CPUTYPE_IMX6UL) + barebox_arm_entry(0x80000000, size, fdt); + else + barebox_arm_entry(0x10000000, size, fdt); } #define PHYTEC_ENTRY(name, fdt_name, memory_size, do_early_uart_config) \ @@ -98,3 +109,5 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_so PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); + +PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false); diff --git a/arch/arm/boards/vscom-baltos/lowlevel.c b/arch/arm/boards/vscom-baltos/lowlevel.c index 87f2a748f3..9f829b9977 100644 --- a/arch/arm/boards/vscom-baltos/lowlevel.c +++ b/arch/arm/boards/vscom-baltos/lowlevel.c @@ -126,6 +126,12 @@ ENTRY_FUNCTION(start_am33xx_baltos_sdram, r0, r1, r2) { void *fdt; + /* + * Prolong global reset duration to the max. value (0xff) + * and leave power domain reset to its default value (0x10). + */ + __raw_writel(0x000010ff, AM33XX_PRM_RSTTIME); + fdt = __dtb_am335x_baltos_minimal_start; fdt -= get_runtime_offset(); diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 39e7ef1798..dab3d7a45e 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -10,6 +10,7 @@ CONFIG_MACH_PLATHOME_OPENBLOCKS_A6=y CONFIG_MACH_USI_TOPKICK=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_MMU=y CONFIG_TEXT_BASE=0x0 CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 607c620806..8ba99577e0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -51,7 +51,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6q-phytec-phycore-som-nand.dtb.o \ imx6q-phytec-phycore-som-emmc.dtb.o \ imx6dl-phytec-phycore-som-nand.dtb.o \ - imx6dl-phytec-phycore-som-emmc.dtb.o + imx6dl-phytec-phycore-som-emmc.dtb.o \ + imx6ul-phytec-phycore-som.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o diff --git a/arch/arm/dts/imx53-guf-vincell-lt.dts b/arch/arm/dts/imx53-guf-vincell-lt.dts index 67a41332f5..2b1b54acc5 100644 --- a/arch/arm/dts/imx53-guf-vincell-lt.dts +++ b/arch/arm/dts/imx53-guf-vincell-lt.dts @@ -152,7 +152,7 @@ }; pmic: dialog@48 { /* DA9053-3HHA1 PMIC */ - compatible = "dialog,da9053-aa", "dialog,da9052"; + compatible = "dlg,da9053-aa", "dlg,da9052"; reg = <0x48>; interrupt-parent = <&gpio7>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/dts/imx53-guf-vincell.dts b/arch/arm/dts/imx53-guf-vincell.dts index 2f0153e7b2..f743f171d6 100644 --- a/arch/arm/dts/imx53-guf-vincell.dts +++ b/arch/arm/dts/imx53-guf-vincell.dts @@ -102,7 +102,7 @@ status = "okay"; pmic: dialog@48 { /* DA9053-3HHA1 PMIC */ - compatible = "dialog,da9053-aa", "dialog,da9052"; + compatible = "dlg,da9053-aa", "dlg,da9052"; reg = <0x48>; interrupt-parent = <&gpio7>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts index fc153a6b05..bffee5f154 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts @@ -29,21 +29,12 @@ status = "okay"; }; +ðphy { + max-speed = <100>; +}; + &fec { status = "okay"; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 14 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - reg = <3>; - max-speed = <100>; - }; - }; }; &flash { diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts index 3f2f1c7320..1b66fdabc6 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts @@ -24,21 +24,12 @@ status = "okay"; }; +ðphy { + max-speed = <100>; +}; + &fec { status = "okay"; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 14 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - reg = <3>; - max-speed = <100>; - }; - }; }; &gpmi { diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts index 74bc09b5d5..ecc5aa38e1 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts @@ -28,21 +28,12 @@ status = "okay"; }; +ðphy { + max-speed = <1000>; +}; + &fec { status = "okay"; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 14 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - reg = <3>; - max-speed = <1000>; - }; - }; }; &flash { diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts index aa2c94abee..9ad7eda740 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts @@ -29,21 +29,12 @@ status = "okay"; }; +ðphy { + max-speed = <1000>; +}; + &fec { status = "okay"; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 14 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - reg = <3>; - max-speed = <1000>; - }; - }; }; &flash { diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi index d446a5e9af..b10530cbcf 100644 --- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "imx6qdl.dtsi" +#include <dt-bindings/gpio/gpio.h> / { chosen { @@ -76,7 +76,21 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + reg = <3>; + txc-skew-ps = <1680>; + rxc-skew-ps = <1860>; + }; + }; }; &gpmi { @@ -119,9 +133,9 @@ clock-frequency = <400000>; status = "okay"; - eeprom: 24c32@50 { + eeprom: eeprom@50 { status = "disabled"; - compatible = "st,24c32"; + compatible = "24c32"; reg = <0x50>; }; }; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts new file mode 100644 index 0000000000..65a936551e --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp <c.hemp@phytec.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <arm/imx6ul.dtsi> + +/ { + model = "Phytec phyCORE-i.MX6 Ultra Lite SOM"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + chosen { + linux,stdout-path = &uart1; + + environment-nand { + compatible = "barebox,environment"; + device-path = &gpmi, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-sd1 { + compatible = "barebox,environment"; + device-path = &usdhc1, "partname:barebox-environment"; + status = "disabled"; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + eeprom@52 { + compatible = "cat,24c32"; + reg = <0x52>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6ul-phytec-phycore-som { + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + >; + }; + }; +}; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 5b141c2391..274c491804 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -25,17 +25,6 @@ clock-names = "qspi_clk"; status = "disabled"; }; - - fpgamgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xff706000 0x1000>, - <0xffb90000 0x1000>; - }; - - system_mgr: sysmgr@ffd08000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd08000 0x4000>; - }; }; }; &osc2 { diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c index 8502bb00ff..9dd575b744 100644 --- a/arch/arm/mach-at91/bootstrap.c +++ b/arch/arm/mach-at91/bootstrap.c @@ -155,7 +155,8 @@ void at91_bootstrap_menu(void) struct menu_entry *me; m = menu_alloc(); - m->display = m->name = "boot"; + m->name = "boot"; + menu_add_title(m, m->name); menu_add(m); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index af533ea84b..9dbe31c4b6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -80,6 +80,10 @@ config BAREBOX_UPDATE_IMX_EXTERNAL_NAND depends on MTD_WRITE default y +config RESET_IMX_SRC + def_bool y + depends on ARCH_IMX6 || ARCH_IMX50 || ARCH_IMX51 || ARCH_IMX53 + comment "Freescale i.MX System-on-Chip" config ARCH_IMX1 @@ -258,6 +262,7 @@ config MACH_FREESCALE_MX53_VMX53 config MACH_PHYTEC_SOM_IMX6 bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6" select ARCH_IMX6 + select ARCH_IMX6UL config MACH_DFI_FS700_M60 bool "DFI i.MX6 FS700 M60 Q7 Board" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 1a153250ab..d0fe7abc00 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o esdctl-v4.o pbl-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o esdctl-v4.o obj-$(CONFIG_ARCH_IMX6) += imx6.o usb-imx6.o lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o -obj-$(CONFIG_ARCH_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_IMX_OCOTP) += ocotp.o @@ -23,5 +22,6 @@ obj-y += devices.o imx.o obj-pbl-y += esdctl.o boot.o obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o +obj-$(CONFIG_RESET_IMX_SRC) += src.o lwl-y += cpu_init.o pbl-y += xload-spi.o xload-esdhc.o xload-common.o xload-imx-nand.o diff --git a/arch/arm/mach-imx/clk-imx6ul.c b/arch/arm/mach-imx/clk-imx6ul.c deleted file mode 100644 index 72b5fa2b75..0000000000 --- a/arch/arm/mach-imx/clk-imx6ul.c +++ /dev/null @@ -1,426 +0,0 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <linux/clk.h> -#include <io.h> -#include <of.h> -#include <linux/clkdev.h> -#include <linux/err.h> -#include <mach/imx6-regs.h> -#include <mach/revision.h> -#include <mach/imx6.h> -#include <dt-bindings/clock/imx6ul-clock.h> - -#include "clk.h" - -#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16) -#define CCDR 0x4 - -static const char *pll_bypass_src_sels[] = { "osc", "dummy", }; -static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; -static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; -static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; -static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; -static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; -static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; -static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; -static const char *ca7_secondary_sels[] = { "pll2_pfd2_396m", "pll2_bus", }; -static const char *step_sels[] = { "osc", "ca7_secondary_sel", }; -static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; -static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", }; -static const char *axi_sels[] = {"periph", "axi_alt_sel", }; -static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; -static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", }; -static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", }; -static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", }; -static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; -static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; -static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *bch_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *gpmi_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd0_720m", }; -static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", }; -static const char *sai_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", }; -static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", }; -static const char *sim_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", }; -static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", }; -static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", }; -static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", }; -static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", }; -static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", }; -static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", }; -static const char *ecspi_sels[] = { "pll3_60m", "osc", }; -static const char *uart_sels[] = { "pll3_80m", "osc", }; -static const char *perclk_sels[] = { "ipg", "osc", }; -static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; -static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; -static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; - -static struct clk *clks[IMX6UL_CLK_END]; -static struct clk_onecell_data clk_data; - -static int const clks_init_on[] __initconst = { - IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3, - IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, - IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG, -}; - -static struct clk_div_table clk_enet_ref_table[] = { - { .val = 0, .div = 20, }, - { .val = 1, .div = 10, }, - { .val = 2, .div = 5, }, - { .val = 3, .div = 4, }, - { } -}; - -static int imx6_ccm_probe(struct device_d *dev) -{ - struct resource *iores; - void __iomem *base, *anatop_base, *ccm_base; - int i; - struct device_node *ccm_node = dev->device_node; - - iores = dev_request_mem_resource(dev, 0); - if (IS_ERR(iores)) - return PTR_ERR(iores); - ccm_base = IOMEM(iores->start); - - base = anatop_base; - - clks[IMX6UL_CLK_DUMMY] = clk_fixed("dummy", 0); - - base = IOMEM(MX6_ANATOP_BASE_ADDR); - - clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); - clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); - clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); - clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); - clks[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); - clks[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); - clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); - - clks[IMX6UL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); - clks[IMX6UL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); - clks[IMX6UL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); - clks[IMX6UL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); - clks[IMX6UL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); - clks[IMX6UL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); - clks[IMX6UL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); - - clks[IMX6UL_PLL1_BYPASS] = imx_clk_mux_p("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels)); - clks[IMX6UL_PLL2_BYPASS] = imx_clk_mux_p("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels)); - clks[IMX6UL_PLL3_BYPASS] = imx_clk_mux_p("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels)); - clks[IMX6UL_PLL4_BYPASS] = imx_clk_mux_p("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels)); - clks[IMX6UL_PLL5_BYPASS] = imx_clk_mux_p("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels)); - clks[IMX6UL_PLL6_BYPASS] = imx_clk_mux_p("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels)); - clks[IMX6UL_PLL7_BYPASS] = imx_clk_mux_p("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels)); - clks[IMX6UL_CLK_CSI_SEL] = imx_clk_mux_p("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); - - /* Do not bypass PLLs initially */ - clk_set_parent(clks[IMX6UL_PLL1_BYPASS], clks[IMX6UL_CLK_PLL1]); - clk_set_parent(clks[IMX6UL_PLL2_BYPASS], clks[IMX6UL_CLK_PLL2]); - clk_set_parent(clks[IMX6UL_PLL3_BYPASS], clks[IMX6UL_CLK_PLL3]); - clk_set_parent(clks[IMX6UL_PLL4_BYPASS], clks[IMX6UL_CLK_PLL4]); - clk_set_parent(clks[IMX6UL_PLL5_BYPASS], clks[IMX6UL_CLK_PLL5]); - clk_set_parent(clks[IMX6UL_PLL6_BYPASS], clks[IMX6UL_CLK_PLL6]); - clk_set_parent(clks[IMX6UL_PLL7_BYPASS], clks[IMX6UL_CLK_PLL7]); - - clks[IMX6UL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1); - clks[IMX6UL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); - clks[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); - clks[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); - clks[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); - clks[IMX6UL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); - clks[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); - - /* - * Bit 20 is the reserved and read-only bit, we do this only for: - * - Do nothing for usbphy clk_enable/disable - * - Keep refcount when do usbphy clk_enable/disable, in that case, - * the clk framework many need to enable/disable usbphy's parent - */ - clks[IMX6UL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); - clks[IMX6UL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); - - /* - * usbphy*_gate needs to be on after system boots up, and software - * never needs to control it anymore. - */ - clks[IMX6UL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); - clks[IMX6UL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); - - /* name parent_name reg idx */ - clks[IMX6UL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); - clks[IMX6UL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); - clks[IMX6UL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); - clks[IMX6UL_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3); - clks[IMX6UL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); - clks[IMX6UL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); - clks[IMX6UL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); - clks[IMX6UL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); - - clks[IMX6UL_CLK_ENET_REF] = imx_clk_divider_table("enet_ref", "pll6_enet", - base + 0xe0, 0, 2, clk_enet_ref_table); - clks[IMX6UL_CLK_ENET2_REF] = imx_clk_divider_table("enet2_ref", "pll6_enet", - base + 0xe0, 2, 2, clk_enet_ref_table); - - clks[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20); - clks[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20); - clks[IMX6UL_CLK_ENET_PTP] = imx_clk_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21); - - /* name parent_name mult div */ - clks[IMX6UL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); - clks[IMX6UL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); - clks[IMX6UL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); - clks[IMX6UL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); - - base = ccm_base; - - clks[IMX6UL_CA7_SECONDARY_SEL] = imx_clk_mux("ca7_secondary_sel", base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels)); - clks[IMX6UL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clks[IMX6UL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); - clks[IMX6UL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); - clks[IMX6UL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels)); - clks[IMX6UL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clks[IMX6UL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); - clks[IMX6UL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clks[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); - clks[IMX6UL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); - clks[IMX6UL_CLK_GPMI_SEL] = imx_clk_mux("gpmi_sel", base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels)); - clks[IMX6UL_CLK_BCH_SEL] = imx_clk_mux("bch_sel", base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels)); - clks[IMX6UL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6UL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6UL_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels)); - clks[IMX6UL_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", base + 0x1c, 12, 2, sai_sels, ARRAY_SIZE(sai_sels)); - clks[IMX6UL_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels)); - clks[IMX6UL_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); - clks[IMX6UL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); - clks[IMX6UL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); - clks[IMX6UL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); - clks[IMX6UL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels)); - clks[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); - clks[IMX6UL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); - clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); - clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); - clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); - clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels)); - clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); - - clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); - clks[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); - - clks[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); - clks[IMX6UL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7); - clks[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7); - clks[IMX6UL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "qspi1_sel", 1, 7); - - clks[IMX6UL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); - clks[IMX6UL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); - - clks[IMX6UL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); - clks[IMX6UL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); - clks[IMX6UL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); - clks[IMX6UL_CLK_LCDIF_PODF] = imx_clk_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3); - clks[IMX6UL_CLK_QSPI1_PDOF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3); - clks[IMX6UL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); - clks[IMX6UL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); - clks[IMX6UL_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6); - clks[IMX6UL_CLK_GPMI_PODF] = imx_clk_divider("gpmi_podf", "gpmi_sel", base + 0x24, 22, 3); - clks[IMX6UL_CLK_BCH_PODF] = imx_clk_divider("bch_podf", "bch_sel", base + 0x24, 19, 3); - clks[IMX6UL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); - clks[IMX6UL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); - clks[IMX6UL_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); - clks[IMX6UL_CLK_SAI3_PRED] = imx_clk_divider("sai3_pred", "sai3_sel", base + 0x28, 22, 3); - clks[IMX6UL_CLK_SAI3_PODF] = imx_clk_divider("sai3_podf", "sai3_pred", base + 0x28, 16, 6); - clks[IMX6UL_CLK_SAI1_PRED] = imx_clk_divider("sai1_pred", "sai1_sel", base + 0x28, 6, 3); - clks[IMX6UL_CLK_SAI1_PODF] = imx_clk_divider("sai1_podf", "sai1_pred", base + 0x28, 0, 6); - clks[IMX6UL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); - clks[IMX6UL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); - clks[IMX6UL_CLK_SAI2_PRED] = imx_clk_divider("sai2_pred", "sai2_sel", base + 0x2c, 6, 3); - clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6); - clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); - clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); - clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3); - clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); - clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); - clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); - - clks[IMX6UL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); - clks[IMX6UL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); - clks[IMX6UL_CLK_AXI_PODF] = imx_clk_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); - clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); - - /* CCGR0 */ - clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); - clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); - clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4); - clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); - clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); - clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); - clks[IMX6UL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); - clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16); - clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); - clks[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20); - clks[IMX6UL_CLK_GPT2_BUS] = imx_clk_gate2("gpt2_bus", "perclk", base + 0x68, 24); - clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt2_serial", "perclk", base + 0x68, 26); - clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); - clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); - clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); - - /* CCGR1 */ - clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); - clks[IMX6UL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2); - clks[IMX6UL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4); - clks[IMX6UL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6); - clks[IMX6UL_CLK_ADC2] = imx_clk_gate2("adc2", "ipg", base + 0x6c, 8); - clks[IMX6UL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10); - clks[IMX6UL_CLK_UART3_SERIAL] = imx_clk_gate2("uart3_serial", "uart_podf", base + 0x6c, 10); - clks[IMX6UL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); - clks[IMX6UL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); - clks[IMX6UL_CLK_ADC1] = imx_clk_gate2("adc1", "ipg", base + 0x6c, 16); - clks[IMX6UL_CLK_GPT1_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20); - clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22); - clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24); - clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); - - /* CCGR2 */ - clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2); - clks[IMX6UL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); - clks[IMX6UL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); - clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); - clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); - clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14); - clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28); - clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30); - - /* CCGR3 */ - clks[IMX6UL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2); - clks[IMX6UL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2); - clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); - clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4); - clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6); - clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6); - clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); - clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14); - clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16); - clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20); - clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); - clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base + 0x74, 28); - - /* CCGR4 */ - clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", base + 0x78, 12); - clks[IMX6UL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); - clks[IMX6UL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); - clks[IMX6UL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); - clks[IMX6UL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); - clks[IMX6UL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "bch_podf", base + 0x78, 24); - clks[IMX6UL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "gpmi_podf", base + 0x78, 26); - clks[IMX6UL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc_podf", base + 0x78, 28); - clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "bch_podf", base + 0x78, 30); - - /* CCGR5 */ - clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); - clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); - clks[IMX6UL_CLK_KPP] = imx_clk_gate2("kpp", "ipg", base + 0x7c, 8); - clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10); - clks[IMX6UL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); - clks[IMX6UL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24); - clks[IMX6UL_CLK_UART1_SERIAL] = imx_clk_gate2("uart1_serial", "uart_podf", base + 0x7c, 24); - clks[IMX6UL_CLK_UART7_IPG] = imx_clk_gate2("uart7_ipg", "ipg", base + 0x7c, 26); - clks[IMX6UL_CLK_UART7_SERIAL] = imx_clk_gate2("uart7_serial", "uart_podf", base + 0x7c, 26); - - /* CCGR6 */ - clks[IMX6UL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); - clks[IMX6UL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); - clks[IMX6UL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); - clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6); - clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8); - clks[IMX6UL_CLK_EIM] = imx_clk_gate2("eim", "eim_slow_podf", base + 0x80, 10); - clks[IMX6UL_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16); - clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg", base + 0x80, 14); - clks[IMX6UL_CLK_UART8_SERIAL] = imx_clk_gate2("uart8_serial", "uart_podf", base + 0x80, 14); - clks[IMX6UL_CLK_WDOG3] = imx_clk_gate2("wdog3", "ipg", base + 0x80, 20); - clks[IMX6UL_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24); - clks[IMX6UL_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26); - clks[IMX6UL_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28); - clks[IMX6UL_CLK_PWM7] = imx_clk_gate2("pwm7", "perclk", base + 0x80, 30); - - /* mask handshake of mmdc */ - writel(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); - - clk_data.clks = clks; - clk_data.clk_num = ARRAY_SIZE(clks); - of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data); - - /* - * Lower the AHB clock rate before changing the parent clock source, - * as AHB clock rate can NOT be higher than 133MHz, but its parent - * will be switched from 396MHz PFD to 528MHz PLL in order to increase - * AXI clock rate, so we need to lower AHB rate first to make sure at - * any time, AHB rate is <= 133MHz. - */ - clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000); - - /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */ - clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); - clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]); - clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]); - clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]); - - /* Make sure AHB rate is 132MHz */ - clk_set_rate(clks[IMX6UL_CLK_AHB], 132000000); - - /* set perclk to from OSC */ - clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]); - - clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000); - clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); - clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); - - /* keep all the clks on just for bringup */ - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_enable(clks[clks_init_on[i]]); - - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_enable(clks[IMX6UL_CLK_USBPHY1_GATE]); - clk_enable(clks[IMX6UL_CLK_USBPHY2_GATE]); - } - - clk_set_parent(clks[IMX6UL_CLK_CAN_SEL], clks[IMX6UL_CLK_PLL3_60M]); - clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); - - clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]); - - return 0; -} - -static __maybe_unused struct of_device_id imx6_ccm_dt_ids[] = { - { - .compatible = "fsl,imx6ul-ccm", - }, { - /* sentinel */ - } -}; - -static struct driver_d imx6_ccm_driver = { - .probe = imx6_ccm_probe, - .name = "imx6-ccm", - .of_compatible = DRV_OF_COMPAT(imx6_ccm_dt_ids), -}; - -static int imx6_ccm_init(void) -{ - return platform_driver_register(&imx6_ccm_driver); -} -core_initcall(imx6_ccm_init); diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c new file mode 100644 index 0000000000..73350d15e1 --- /dev/null +++ b/arch/arm/mach-imx/src.c @@ -0,0 +1,57 @@ +/* + * Copyright 2016 Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <linux/err.h> + +#define SRC_SCR 0x0 + +#define SCR_WARM_RESET_ENABLE BIT(0) + +static int imx_src_reset_probe(struct device_d *dev) +{ + struct resource *res; + u32 val; + void __iomem *membase; + + res = dev_request_mem_resource(dev, 0); + if (IS_ERR(res)) + return PTR_ERR(res); + + membase = IOMEM(res->start); + + /* + * Generate cold reset for warm reset sources. Needed for + * some boards to come up properly after reset. + */ + val = readl(membase + SRC_SCR); + val &= ~SCR_WARM_RESET_ENABLE; + writel(val, membase + SRC_SCR); + + return 0; +} + +static const struct of_device_id imx_src_dt_ids[] = { + { .compatible = "fsl,imx51-src", }, + { /* sentinel */ }, +}; + +static struct driver_d imx_src_reset_driver = { + .name = "imx-src", + .probe = imx_src_reset_probe, + .of_compatible = DRV_OF_COMPAT(imx_src_dt_ids), +}; + +static int imx_src_reset_init(void) +{ + return platform_driver_register(&imx_src_reset_driver); +} +postcore_initcall(imx_src_reset_init); diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index e17e609879..10595d5ee7 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -71,6 +71,7 @@ #define AM33XX_PRM_RSTCTRL (AM33XX_PRM_BASE + 0x0f00) #define AM33XX_PRM_RSTCTRL_RESET 0x1 +#define AM33XX_PRM_RSTTIME (AM33XX_PRM_BASE + 0x0f04) #define AM33XX_PRM_RSTST (AM33XX_PRM_BASE + 0x0f08) /* CTRL */ diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index b81d57da26..dea0e075d1 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -2,4 +2,3 @@ obj-y += generic.o nic301.o bootsource.o reset-manager.o pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o pbl-y += clock-manager.o obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o -obj-$(CONFIG_ARCH_SOCFPGA_FPGA) += fpga.o diff --git a/arch/arm/mach-socfpga/xload.c b/arch/arm/mach-socfpga/xload.c index 993626966e..d24944bbb8 100644 --- a/arch/arm/mach-socfpga/xload.c +++ b/arch/arm/mach-socfpga/xload.c @@ -28,7 +28,7 @@ static struct socfpga_barebox_part default_parts[] = { }, { /* sentinel */ } }; -const struct socfpga_barebox_part *barebox_parts = &default_parts; +const struct socfpga_barebox_part *barebox_parts = default_parts; enum socfpga_clks { timer, mmc, qspi_clk, uart, clk_max @@ -111,7 +111,7 @@ static void socfpga_timer_init(void) static __noreturn int socfpga_xload(void) { enum bootsource bootsource = bootsource_get(); - struct socfpga_barebox_part *part; + const struct socfpga_barebox_part *part; void *buf = NULL; switch (bootsource) { diff --git a/arch/mips/configs/qemu-malta_defconfig b/arch/mips/configs/qemu-malta_defconfig index 004adacf8f..9671e93dc0 100644 --- a/arch/mips/configs/qemu-malta_defconfig +++ b/arch/mips/configs/qemu-malta_defconfig @@ -1,6 +1,7 @@ CONFIG_BUILTIN_DTB=y CONFIG_BUILTIN_DTB_NAME="qemu-malta" CONFIG_PBL_IMAGE=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x400000 CONFIG_STACK_SIZE=0x7000 CONFIG_EXPERIMENTAL=y CONFIG_BAUDRATE=38400 diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h index 4a6562f7c1..058814ecfd 100644 --- a/arch/mips/include/asm/debug_ll_ns16550.h +++ b/arch/mips/include/asm/debug_ll_ns16550.h @@ -128,38 +128,6 @@ static inline void PUTC_LL(char ch) .endm /* - * output a 32-bit value in hex - */ -.macro debug_ll_outhexw -#ifdef CONFIG_DEBUG_LL - .set push - .set reorder - - move t6, a0 - li t5, 32 - -202: - addi t5, t5, -4 - srlv a0, t6, t5 - - /* output one hex digit */ - andi a0, a0, 15 - blt a0, 10, 203f - - addi a0, a0, ('a' - '9' - 1) - -203: - addi a0, a0, '0' - - debug_ll_outc_a0 - - bgtz t5, 202b - - .set pop -#endif /* CONFIG_DEBUG_LL */ -.endm - -/* * check character in input buffer * return value: * v0 = 0 no character in input buffer diff --git a/arch/mips/include/asm/pbl_nmon.h b/arch/mips/include/asm/pbl_nmon.h index 90e2da8ef9..e0326bd7cd 100644 --- a/arch/mips/include/asm/pbl_nmon.h +++ b/arch/mips/include/asm/pbl_nmon.h @@ -43,6 +43,37 @@ .set pop .endm +/* + * output a 32-bit value in hex + */ +.macro debug_ll_outhexw +#ifdef CONFIG_DEBUG_LL + .set push + .set reorder + + move t6, a0 + li t5, 32 + +202: + addi t5, t5, -4 + srlv a0, t6, t5 + + /* output one hex digit */ + andi a0, a0, 15 + blt a0, 10, 203f + + addi a0, a0, ('a' - '9' - 1) + +203: + addi a0, a0, '0' + + debug_ll_outc_a0 + + bgtz t5, 202b + + .set pop +#endif /* CONFIG_DEBUG_LL */ +.endm .macro mips_nmon .set push diff --git a/arch/mips/mach-ath79/include/mach/debug_ll.h b/arch/mips/mach-ath79/include/mach/debug_ll.h index e0c3f797b2..04bd3ea72b 100644 --- a/arch/mips/mach-ath79/include/mach/debug_ll.h +++ b/arch/mips/mach-ath79/include/mach/debug_ll.h @@ -123,38 +123,6 @@ static inline void PUTC_LL(int ch) .endm /* - * output a 32-bit value in hex - */ -.macro debug_ll_outhexw -#ifdef CONFIG_DEBUG_LL - .set push - .set reorder - - move t6, a0 - li t5, 32 - -202: - addi t5, t5, -4 - srlv a0, t6, t5 - - /* output one hex digit */ - andi a0, a0, 15 - blt a0, 10, 203f - - addi a0, a0, ('a' - '9' - 1) - -203: - addi a0, a0, '0' - - debug_ll_outc_a0 - - bgtz t5, 202b - - .set pop -#endif /* CONFIG_DEBUG_LL */ -.endm - -/* * check character in input buffer * return value: * v0 = 0 no character in input buffer diff --git a/arch/nios2/Makefile b/arch/nios2/Makefile index 681944f22d..3e97155e7c 100644 --- a/arch/nios2/Makefile +++ b/arch/nios2/Makefile @@ -7,7 +7,7 @@ KALLSYMS += --symbol-prefix=_ archprepare: maketools @$(kecho) " SYMLINK include/nios_sopc.h -> arch/nios2/boards/$(board-y)/nios_sopc.h" - @ln -fsn ../arch/nios2/boards/$(board-y)/nios_sopc.h include/nios_sopc.h + @ln -fsn $(src)/arch/nios2/boards/$(board-y)/nios_sopc.h $(obj)/include/nios_sopc.h PHONY += maketools diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index b2164af812..77fde6be41 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -33,7 +33,7 @@ static void __noreturn nios2_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(nios2_restart_soc); + return restart_handler_register_fn(nios2_restart_soc); } coredevice_initcall(restart_register_feature); diff --git a/arch/x86/boot/boot_hdisk.S b/arch/x86/boot/boot_hdisk.S index 143336d3b4..6f98197512 100644 --- a/arch/x86/boot/boot_hdisk.S +++ b/arch/x86/boot/boot_hdisk.S @@ -164,7 +164,7 @@ output_message: .section .boot_data -notification_string: .asciz "UBOOT2 " +notification_string: .asciz "BAREBOX " chs_string: .asciz "CHS " jmp_string: .asciz "JMP " |