diff options
Diffstat (limited to 'arch')
139 files changed, 3757 insertions, 1451 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 986ea7a983..a02d80d2da 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -132,7 +132,7 @@ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ -obj-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2/ +obj-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp15xx-dkx/ obj-$(CONFIG_MACH_LXA_MC1) += lxa-mc1/ obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += technexion-pico-hobbit/ obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/ @@ -165,6 +165,7 @@ obj-$(CONFIG_MACH_VARISCITE_MX6) += variscite-mx6/ obj-$(CONFIG_MACH_VSCOM_BALTOS) += vscom-baltos/ obj-$(CONFIG_MACH_QEMU_VIRT64) += qemu-virt64/ obj-$(CONFIG_MACH_WARP7) += element14-warp7/ +obj-$(CONFIG_MACH_WEBASTO_CCBV2) += webasto-ccbv2/ obj-$(CONFIG_MACH_VF610_TWR) += freescale-vf610-twr/ obj-$(CONFIG_MACH_XILINX_ZCU104) += xilinx-zcu104/ obj-$(CONFIG_MACH_ZII_COMMON) += zii-common/ diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c index 13fba51fec..09437b047f 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51.c +++ b/arch/arm/boards/ccxmx51/ccxmx51.c @@ -31,7 +31,7 @@ static const struct ccxmx_ident { unsigned char eth1:1; unsigned char wless:1; unsigned char accel:1; -} *ccxmx_id, ccxmx51_ids[] = { +} ccxmx51_ids[] = { [0x00] = { NULL /* Unknown */, 0, 0, 0, 0, 0, 0 }, [0x01] = { NULL /* Not supported */, 0, 0, 0, 0, 0, 0 }, [0x02] = { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 800, 1, 1, 1, 1 }, @@ -52,7 +52,9 @@ static const struct ccxmx_ident { [0x11] = { "i.MX515@800MHz, PHY, Accel", SZ_128M, 800, 1, 0, 0, 1 }, [0x12] = { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_512M, 600, 1, 0, 1, 1 }, [0x13] = { "i.MX515@800MHz, PHY, Accel", SZ_512M, 800, 1, 0, 0, 1 }, -}; + [0x14] = { NULL, 0, 0, 0, 0, 0, 0 }, + [0x15] = { "i.MX515@600MHz, PHY, Accel", SZ_512M, 600, 1, 0, 0, 1 }, +}, *ccxmx_id = &ccxmx51_ids[0]; static u32 boardserial; @@ -228,13 +230,18 @@ static __init int ccxmx51_init(void) { char manloc = 'N'; u8 hwid[6]; + int ret; if (!ccxmx51_is_compatible()) return 0; - if ((imx_iim_read(1, 9, hwid, sizeof(hwid)) != sizeof(hwid)) || - (hwid[0] < 0x02) || (hwid[0] >= ARRAY_SIZE(ccxmx51_ids))) { - printf("Unknown board variant (0x%02x). System halted.\n", hwid[0]); + ret = imx_iim_read(1, 9, hwid, sizeof(hwid)); + if ((ret == sizeof(hwid)) && (hwid[0] < ARRAY_SIZE(ccxmx51_ids))) + ccxmx_id = &ccxmx51_ids[hwid[0]]; + + if (!ccxmx_id->mem_sz) { + printf("Unknown/unsupported board variant (0x%02x).\n" + "System halted.\n", hwid[0]); hang(); } diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c index 83c77feb89..fc39f0849a 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c +++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c @@ -99,4 +99,4 @@ void cfa10036_detect_hw(void) pr_info("Booting on a CFA10036 with %s\n", board_name); } -BAREBOX_MAGICVAR_NAMED(global_board_variant, global.board.variant, "The board variant"); +BAREBOX_MAGICVAR(global.board.variant, "The board variant"); diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c index f4f2994a51..1b39ef82c6 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/board.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c @@ -39,18 +39,6 @@ static iomux_v3_cfg_t sabrelite_enet_gpio_pads[] = { MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24, }; -static int sabrelite_mem_init(void) -{ - if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && - !of_machine_is_compatible("fsl,imx6dl-sabrelite")) - return 0; - - arm_add_mem_device("ram0", 0x10000000, SZ_1G); - - return 0; -} -mem_initcall(sabrelite_mem_init); - static int ksz9021rn_phy_fixup(struct phy_device *dev) { phy_write(dev, 0x09, 0x0f00); @@ -70,37 +58,37 @@ static int ksz9021rn_phy_fixup(struct phy_device *dev) static struct gpio fec_gpios[] = { { - .gpio = 87, + .gpio = IMX_GPIO_NR(3, 23), .flags = GPIOF_OUT_INIT_LOW, .label = "phy-rst", }, { - .gpio = 190, + .gpio = IMX_GPIO_NR(6, 30), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-addr2", }, { - .gpio = 23, + .gpio = IMX_GPIO_NR(1, 23), .flags = GPIOF_OUT_INIT_LOW, .label = "phy-led-mode", }, { /* MODE strap-in pins: advertise all capabilities */ - .gpio = 185, + .gpio = IMX_GPIO_NR(6, 25), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { - .gpio = 187, + .gpio = IMX_GPIO_NR(6, 27), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { - .gpio = 188, + .gpio = IMX_GPIO_NR(6, 28), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { - .gpio = 189, + .gpio = IMX_GPIO_NR(6, 29), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { /* Enable 125 MHz clock output */ - .gpio = 184, + .gpio = IMX_GPIO_NR(6, 24), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-125MHz", }, @@ -139,9 +127,9 @@ fs_initcall(sabrelite_ksz9021rn_setup); static void sabrelite_ehci_init(void) { /* hub reset */ - gpio_direction_output(204, 0); + gpio_direction_output(IMX_GPIO_NR(7, 12), 0); udelay(2000); - gpio_set_value(204, 1); + gpio_set_value(IMX_GPIO_NR(7, 12), 1); } static int sabrelite_devices_init(void) diff --git a/arch/arm/boards/kindle-mx50/board.c b/arch/arm/boards/kindle-mx50/board.c index a8d733c6ba..8fc5af8320 100644 --- a/arch/arm/boards/kindle-mx50/board.c +++ b/arch/arm/boards/kindle-mx50/board.c @@ -60,9 +60,9 @@ static const char *get_env_16char_tag(const char *tag) return value; } -BAREBOX_MAGICVAR_NAMED(global_atags_serial16, global.board.serial16, +BAREBOX_MAGICVAR(global.board.serial16, "Pass the kindle Serial as vendor-specific ATAG to linux"); -BAREBOX_MAGICVAR_NAMED(global_atags_revision16, global.board.revision16, +BAREBOX_MAGICVAR(global.board.revision16, "Pass the kindle BoardId as vendor-specific ATAG to linux"); /* The Kindle Kernel expects two custom ATAGs, ATAG_REVISION16 describing diff --git a/arch/arm/boards/kindle3/kindle3.c b/arch/arm/boards/kindle3/kindle3.c index 14e04deb94..a593dc424d 100644 --- a/arch/arm/boards/kindle3/kindle3.c +++ b/arch/arm/boards/kindle3/kindle3.c @@ -64,9 +64,9 @@ static const char *get_env_16char_tag(const char *tag) return value; } -BAREBOX_MAGICVAR_NAMED(global_atags_serial16, global.board.serial16, +BAREBOX_MAGICVAR(global.board.serial16, "Pass the kindle Serial as vendor-specific ATAG to linux"); -BAREBOX_MAGICVAR_NAMED(global_atags_revision16, global.board.revision16, +BAREBOX_MAGICVAR(global.board.revision16, "Pass the kindle BoardId as vendor-specific ATAG to linux"); /* The Kindle3 Kernel expects two custom ATAGs, ATAG_REVISION16 describing diff --git a/arch/arm/boards/lxa-mc1/board.c b/arch/arm/boards/lxa-mc1/board.c index 7f1f3ccd7e..9126973dcb 100644 --- a/arch/arm/boards/lxa-mc1/board.c +++ b/arch/arm/boards/lxa-mc1/board.c @@ -28,11 +28,9 @@ static int of_fixup_regulator_supply_disable(struct device_node *root, void *pat return 0; } -static int mc1_device_init(void) +static int mc1_probe(struct device_d *dev) { int flags; - if (!of_machine_is_compatible("lxa,stm32mp157c-mc1")) - return 0; flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", flags); @@ -55,4 +53,15 @@ static int mc1_device_init(void) */ return of_register_fixup(of_fixup_regulator_supply_disable, "/regulator_3v3"); } -device_initcall(mc1_device_init); + +static const struct of_device_id mc1_of_match[] = { + { .compatible = "lxa,stm32mp157c-mc1" }, + { /* sentinel */ }, +}; + +static struct driver_d mc1_board_driver = { + .name = "board-lxa-mc1", + .probe = mc1_probe, + .of_compatible = mc1_of_match, +}; +device_platform_driver(mc1_board_driver); diff --git a/arch/arm/boards/nxp-imx8mm-evk/board.c b/arch/arm/boards/nxp-imx8mm-evk/board.c index 8f5d851a88..4350abd157 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/board.c +++ b/arch/arm/boards/nxp-imx8mm-evk/board.c @@ -55,7 +55,7 @@ static int nxp_imx8mm_evk_init(void) imx8mq_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", emmc_sd_flag); - imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc2", + imx8mq_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c index b164bdec07..8d6cc389ba 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c +++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c @@ -118,7 +118,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = { { DDRC_FREQ2_INIT7(0), 0x0006004a }, /* boot start point */ - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 + { DDRC_MSTR2(0), 0x0 }, }; /* PHY Initialize Configuration */ @@ -1941,12 +1941,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { .fsp_cfg = lpddr4_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), }, { - /* P0 3000mts 2D */ - .drate = 3000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), - }, { /* P1 400mts 1D */ .drate = 400, .fw_type = FW_1D_IMAGE, @@ -1958,6 +1952,12 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { .fw_type = FW_1D_IMAGE, .fsp_cfg = lpddr4_fsp2_cfg, .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), }, }; diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c index e4f994a1d1..3298ded586 100644 --- a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c @@ -118,7 +118,7 @@ static void start_atf(void) power_init_board(); - imx8mm_ddr_init(&imx8mp_evk_dram_timing); + imx8mp_ddr_init(&imx8mp_evk_dram_timing); imx8mp_get_boot_source(&src, &instance); switch (src) { diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 407115c2a6..62a1c8de73 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -110,6 +110,7 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib, imx6qp_phytec_phycore_so PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_emmc_512mb, imx6ul_phytec_phycore_som_emmc, SZ_512M, false); PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_nand_512mb, imx6ul_phytec_phycore_som_nand, SZ_512M, false); PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_nand_256mb, imx6ull_phytec_phycore_som_lc_nand, SZ_256M, false); PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_nand_512mb, imx6ull_phytec_phycore_som_nand, SZ_512M, false); diff --git a/arch/arm/boards/seeed-odyssey/board.c b/arch/arm/boards/seeed-odyssey/board.c index e3fe536873..8c011898a3 100644 --- a/arch/arm/boards/seeed-odyssey/board.c +++ b/arch/arm/boards/seeed-odyssey/board.c @@ -7,14 +7,11 @@ #include <bootsource.h> #include <of.h> -static int odyssey_device_init(void) +static int odyssey_som_probe(struct device_d *dev) { int flags; int instance = bootsource_get_instance(); - if (!of_machine_is_compatible("seeed,stm32mp157c-odyssey-som")) - return 0; - flags = instance == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", flags); @@ -29,4 +26,15 @@ static int odyssey_device_init(void) return 0; } -device_initcall(odyssey_device_init); + +static const struct of_device_id odyssey_som_of_match[] = { + { .compatible = "seeed,stm32mp157c-odyssey-som" }, + { /* sentinel */ }, +}; + +static struct driver_d odyssey_som_driver = { + .name = "odyssey-som", + .probe = odyssey_som_probe, + .of_compatible = odyssey_som_of_match, +}; +device_platform_driver(odyssey_som_driver); diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c deleted file mode 100644 index 4636603121..0000000000 --- a/arch/arm/boards/stm32mp157c-dk2/board.c +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include <common.h> -#include <init.h> -#include <mach/bbu.h> - -static int dk2_postcore_init(void) -{ - if (!of_machine_is_compatible("st,stm32mp157c-dk2")) - return 0; - - stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", - BBU_HANDLER_FLAG_DEFAULT); - - barebox_set_model("STM32MP157C-DK2"); - - return 0; -} -postcore_initcall(dk2_postcore_init); diff --git a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c deleted file mode 100644 index 7261d7a8bc..0000000000 --- a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include <common.h> -#include <mach/entry.h> -#include <debug_ll.h> - -extern char __dtb_z_stm32mp157c_dk2_start[]; - -static void setup_uart(void) -{ - /* first stage has set up the UART, so nothing to do here */ - putc_ll('>'); -} - -ENTRY_FUNCTION(start_stm32mp157c_dk2, r0, r1, r2) -{ - void *fdt; - - stm32mp_cpu_lowlevel_init(); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); - - fdt = __dtb_z_stm32mp157c_dk2_start + get_runtime_offset(); - - stm32mp1_barebox_entry(fdt); -} diff --git a/arch/arm/boards/stm32mp157c-dk2/Makefile b/arch/arm/boards/stm32mp15xx-dkx/Makefile index 092c31d6b2..092c31d6b2 100644 --- a/arch/arm/boards/stm32mp157c-dk2/Makefile +++ b/arch/arm/boards/stm32mp15xx-dkx/Makefile diff --git a/arch/arm/boards/stm32mp15xx-dkx/board.c b/arch/arm/boards/stm32mp15xx-dkx/board.c new file mode 100644 index 0000000000..1ddfee698d --- /dev/null +++ b/arch/arm/boards/stm32mp15xx-dkx/board.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <init.h> +#include <mach/bbu.h> + +static int dkx_probe(struct device_d *dev) +{ + const void *model; + + stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", + BBU_HANDLER_FLAG_DEFAULT); + + if (dev_get_drvdata(dev, &model) == 0) + barebox_set_model(model); + + barebox_set_hostname("stm32mp15xx-dkx"); + + return 0; +} + +static const struct of_device_id dkx_of_match[] = { + { .compatible = "st,stm32mp157a-dk1", .data = "STM32MP157A-DK1" }, + { .compatible = "st,stm32mp157c-dk2", .data = "STM32MP157C-DK2" }, + { /* sentinel */ }, +}; + +static struct driver_d dkx_board_driver = { + .name = "board-stm32mp15xx-dkx", + .probe = dkx_probe, + .of_compatible = dkx_of_match, +}; +postcore_platform_driver(dkx_board_driver); diff --git a/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c new file mode 100644 index 0000000000..65f4bbb4da --- /dev/null +++ b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <mach/entry.h> +#include <debug_ll.h> +#include <mach/revision.h> + +extern char __dtb_z_stm32mp157c_dk2_start[]; +extern char __dtb_z_stm32mp157a_dk1_start[]; + +static void setup_uart(void) +{ + /* first stage has set up the UART, so nothing to do here */ + putc_ll('>'); +} + +ENTRY_FUNCTION(start_stm32mp15xx_dkx, r0, r1, r2) +{ + void *fdt; + u32 cputype; + int err; + + stm32mp_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + err = __stm32mp_get_cpu_type(&cputype); + if (!err && cputype == CPU_STM32MP157Axx) + fdt = __dtb_z_stm32mp157a_dk1_start; + else + fdt = __dtb_z_stm32mp157c_dk2_start; + + stm32mp1_barebox_entry(fdt + get_runtime_offset()); +} diff --git a/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c index 368c67744f..f26f1eaecb 100644 --- a/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c +++ b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c @@ -11,6 +11,6 @@ #ifdef CONFIG_MTD_DATAFLASH void * bootstrap_board_read_dataflash(void) { - return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864); + return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864, NULL); } #endif diff --git a/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c index 368c67744f..f26f1eaecb 100644 --- a/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c +++ b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c @@ -11,6 +11,6 @@ #ifdef CONFIG_MTD_DATAFLASH void * bootstrap_board_read_dataflash(void) { - return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864); + return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864, NULL); } #endif diff --git a/arch/arm/boards/webasto-ccbv2/Makefile b/arch/arm/boards/webasto-ccbv2/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/webasto-ccbv2/board.c b/arch/arm/boards/webasto-ccbv2/board.c new file mode 100644 index 0000000000..a78258ea6a --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/board.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Rouven Czerwinski, Pengutronix + */ + +#include <common.h> +#include <init.h> +#include <mach/generic.h> +#include <mach/bbu.h> +#include <of.h> +#include <string.h> + +#include "ccbv2.h" + +static int ccbv2_probe(struct device_d *dev) +{ + struct device_node *overlay; + struct fdt_header *fdt; + int ret; + + /* the bootloader is stored in one of the two boot partitions */ + imx6_bbu_internal_mmcboot_register_handler("emmc", "/dev/mmc1", + BBU_HANDLER_FLAG_DEFAULT); + + barebox_set_hostname("weabsto-ccbv2"); + + if(!IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE)) + return 0; + + fdt = (void*)OPTEE_OVERLAY_LOCATION; + overlay = of_unflatten_dtb(fdt); + + if (IS_ERR(overlay)) + return PTR_ERR(overlay); + + ret = of_register_overlay(overlay); + if (ret) { + printf("cannot apply oftree overlay: %s\n", strerror(-ret)); + goto err; + } + + return 0; +err: + of_delete_node(overlay); + return ret; + +} + +static const struct of_device_id ccbv2_of_match[] = { + { .compatible = "webasto,imx6ul-ccbv2" }, + { /* sentinel */ }, +}; + +static struct driver_d ccbv2_board_driver = { + .name = "board-imx6ul-ccbv2", + .probe = ccbv2_probe, + .of_compatible = ccbv2_of_match, +}; +postcore_platform_driver(ccbv2_board_driver); diff --git a/arch/arm/boards/webasto-ccbv2/ccbv2.h b/arch/arm/boards/webasto-ccbv2/ccbv2.h new file mode 100644 index 0000000000..bf43fe8410 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/ccbv2.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ccbv2.h - common defines between OP-TEE and barebox + * + * Copyright (c) 2019 Rouven Czerwinski <r.czerwinski@pengutronix.de>, Pengutronix + * + */ +#ifndef __CCBV2_H_ +#define __CCBV2_H_ + +/* MX6UL_MMDC_PORT0_BASE_ADDR + SZ_64M */ +#define OPTEE_OVERLAY_LOCATION 0x84000000 + + +#endif // __CCBV2_H_ diff --git a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg new file mode 100644 index 0000000000..ea327b2630 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +loadaddr 0x80000000 +soc imx6 +ivtofs 0x400 + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +/* IOMUX */ +/* DDR IO type */ +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +/* Clock */ +wm 32 0x020E027C 0x00000028 +/* Control */ +wm 32 0x020E0250 0x00000028 +wm 32 0x020E024C 0x00000028 +wm 32 0x020E0490 0x00000028 +wm 32 0x020E0288 0x00000028 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000028 +wm 32 0x020E0264 0x00000028 +wm 32 0x020E04A0 0x00000028 +/* Data strobe */ +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000028 +wm 32 0x020E0284 0x00000028 +/* Data */ +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000028 +wm 32 0x020E04A4 0x00000028 +wm 32 0x020E0244 0x00000028 +wm 32 0x020E0248 0x00000028 + +/* DDR Controller registers */ +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +/* Calibration values */ +wm 32 0x021B080C 0x000C0000 +wm 32 0x021B083C 0x01610162 +wm 32 0x021B0848 0x40405050 +wm 32 0x021B0850 0x4040544C +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +/* END of calibration values */ +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 + +/* MMDC init */ +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x1b333030 +wm 32 0x021B000C 0x3F4352F3 +wm 32 0x021B0010 0xB66D0B63 +wm 32 0x021B0014 0x01FF00DB +/* Consider reducing RALAT (currently set to 5) */ +wm 32 0x021B0018 0x00211740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x00431023 +wm 32 0x021B0040 0x00000047 +wm 32 0x021B0000 0x83180000 + +/* Mode registers writes for CS0 */ +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 + +/* Final DDR setup */ +wm 32 0x021B0020 0x00007800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002556D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 + +/* Disable TZASC bypass */ +wm 32 0x020E4024 0x00000001 + +#include <mach/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/webasto-ccbv2/lowlevel.c b/arch/arm/boards/webasto-ccbv2/lowlevel.c new file mode 100644 index 0000000000..8529ea3735 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/lowlevel.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Rouven Czerwinski, Pengutronix + */ + +#include <common.h> +#include <debug_ll.h> +#include <firmware.h> +#include <mach/generic.h> +#include <asm/barebox-arm.h> +#include <mach/esdctl.h> +#include <mach/iomux-mx6ul.h> +#include <asm/cache.h> +#include <tee/optee.h> + +#include "ccbv2.h" + +extern char __dtb_z_imx6ul_webasto_ccbv2_start[]; + +static void configure_uart(void) +{ + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + imx6_ungate_all_peripherals(); + + imx_setup_pad(iomuxbase, MX6_PAD_LCD_DATA16__UART7_DCE_TX); + imx_setup_pad(iomuxbase, MX6_PAD_LCD_DATA17__UART7_DCE_RX); + + imx6_uart_setup((void *)MX6_UART7_BASE_ADDR); + + putc_ll('>'); + +} + +static void noinline start_ccbv2(u32 r0) +{ + int tee_size; + void *tee; + + /* Enable normal/secure r/w for TZC380 region0 */ + writel(0xf0000000, 0x021D0108); + + configure_uart(); + + /* + * Chainloading barebox will pass a device tree within the RAM in r0, + * skip OP-TEE early loading in this case + */ + if(IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE) + && !(r0 > MX6_MMDC_P0_BASE_ADDR + && r0 < MX6_MMDC_P0_BASE_ADDR + SZ_256M)) { + get_builtin_firmware(ccbv2_optee_bin, &tee, &tee_size); + + memset((void *)OPTEE_OVERLAY_LOCATION, 0, 0x1000); + + start_optee_early(NULL, tee); + } + + imx6ul_barebox_entry(__dtb_z_imx6ul_webasto_ccbv2_start); +} + +ENTRY_FUNCTION(start_imx6ul_ccbv2, r0, r1, r2) +{ + + imx6ul_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + start_ccbv2(r0); +} diff --git a/arch/arm/configs/at91_multi_defconfig b/arch/arm/configs/at91_multi_defconfig new file mode 100644 index 0000000000..e6a554e87f --- /dev/null +++ b/arch/arm/configs/at91_multi_defconfig @@ -0,0 +1,144 @@ +CONFIG_AT91_MULTI_BOARDS=y +CONFIG_MACH_AT91SAM9263EK=y +CONFIG_MACH_AT91SAM9X5EK=y +CONFIG_MACH_MICROCHIP_KSZ9477_EVB=y +CONFIG_MACH_SAMA5D27_SOM1=y +CONFIG_MACH_SAMA5D27_GIANTBOARD=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BOOTM_OFTREE=y +CONFIG_BOOTM_OFTREE_UIMAGE=y +CONFIG_BLSPEC=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_PBL_CONSOLE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_REBOOT_MODE=y +CONFIG_STATE=y +CONFIG_STATE_CRYPTO=y +CONFIG_BOOTCHOOSER=y +CONFIG_RESET_SOURCE=y +CONFIG_FASTBOOT_SPARSE=y +CONFIG_FASTBOOT_CMD_OEM=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_POLLER=y +CONFIG_CMD_SLICE=y +CONFIG_CMD_AT91_BOOT_TEST=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_DEFAULTENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_USBGADGET=y +CONFIG_CMD_WD=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_DIFF=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_OF_BAREBOX_ENV_IN_FS=y +CONFIG_DRIVER_NET_MACB=y +CONFIG_DRIVER_NET_MICREL=y +CONFIG_I2C=y +CONFIG_I2C_AT91=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_ECC_BCH=y +CONFIG_NAND_ECC_HW_OOB_FIRST=y +CONFIG_NAND_ATMEL=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_USB_HOST=y +CONFIG_USB_OHCI_AT91=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DFU=y +CONFIG_USB_GADGET_SERIAL=y +CONFIG_USB_GADGET_FASTBOOT=y +CONFIG_VIDEO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_DRIVER_VIDEO_ATMEL_HLCD=y +CONFIG_DRIVER_VIDEO_SIMPLE_PANEL=y +CONFIG_MCI=y +CONFIG_MCI_MMC_BOOT_PARTITIONS=y +CONFIG_MCI_MMC_GPP_PARTITIONS=y +CONFIG_MCI_ATMEL=y +CONFIG_MCI_ATMEL_SDHCI=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_STATE_DRV=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_GPIO_RGB=y +CONFIG_LED_GPIO_BICOLOR=y +CONFIG_LED_TRIGGERS=y +CONFIG_EEPROM_AT25=y +CONFIG_EEPROM_AT24=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_QT1070=y +CONFIG_KEYBOARD_USB=y +CONFIG_INPUT_SPECIALKEYS=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_AT91SAM9=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED=y +CONFIG_GENERIC_PHY=y +CONFIG_USB_NOP_XCEIV=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UBIFS=y +CONFIG_FS_UBIFS_COMPRESSION_LZO=y diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig deleted file mode 100644 index 0cde5396af..0000000000 --- a/arch/arm/configs/at91sam9263ek_defconfig +++ /dev/null @@ -1,88 +0,0 @@ -CONFIG_AT91_MULTI_BOARDS=y -CONFIG_MACH_AT91SAM9263EK=y -CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_MMU=y -CONFIG_EXPERIMENTAL=y -CONFIG_MALLOC_TLSF=y -CONFIG_RELOCATABLE=y -CONFIG_PROMPT="9263-EK:" -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_BOOTM_SHOW_TYPE=y -CONFIG_BOOTM_INITRD=y -CONFIG_BOOTM_OFTREE=y -CONFIG_BOOTM_OFTREE_UIMAGE=y -CONFIG_CONSOLE_ACTIVATE_ALL=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_CMD_DMESG=y -CONFIG_LONGHELP=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_GO=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_RESET=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_HOST=y -CONFIG_NET_CMD_IFUP=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_PING=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_FBTEST=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_LED=y -CONFIG_CMD_LED_TRIGGER=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_DISPLAY_TIMINGS=y -CONFIG_CMD_OF_FIXUP_STATUS=y -CONFIG_CMD_OFTREE=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_OF_BAREBOX_DRIVERS=y -CONFIG_DRIVER_NET_MACB=y -CONFIG_DAVICOM_PHY=y -# CONFIG_SPI is not set -CONFIG_MTD=y -# CONFIG_MTD_OOB_DEVICE is not set -CONFIG_DRIVER_CFI=y -# CONFIG_DRIVER_CFI_INTEL is not set -# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set -CONFIG_NAND=y -# CONFIG_NAND_ECC_HW is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -# CONFIG_NAND_ECC_HW_NONE is not set -CONFIG_NAND_ATMEL=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DFU=y -CONFIG_USB_GADGET_SERIAL=y -CONFIG_VIDEO=y -CONFIG_DRIVER_VIDEO_ATMEL=y -CONFIG_MCI=y -CONFIG_MCI_ATMEL=y -CONFIG_SRAM=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_LED_GPIO_OF=y -CONFIG_LED_TRIGGERS=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_FS_TFTP=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_LFN=y -CONFIG_PNG=y diff --git a/arch/arm/configs/at91sam9x5ek_defconfig b/arch/arm/configs/at91sam9x5ek_defconfig deleted file mode 100644 index 7b743abfaa..0000000000 --- a/arch/arm/configs/at91sam9x5ek_defconfig +++ /dev/null @@ -1,91 +0,0 @@ -CONFIG_AT91_MULTI_BOARDS=y -CONFIG_MACH_AT91SAM9X5EK=y -CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0xa00000 -CONFIG_EXPERIMENTAL=y -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y -CONFIG_PROMPT="9G20-EK:" -CONFIG_GLOB=y -CONFIG_PROMPT_HUSH_PS2="y" -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_BOOTM_SHOW_TYPE=y -CONFIG_BOOTM_INITRD=y -CONFIG_BOOTM_OFTREE=y -CONFIG_BOOTM_OFTREE_UIMAGE=y -CONFIG_CONSOLE_ACTIVATE_ALL=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -# CONFIG_CMD_ARM_CPUINFO is not set -CONFIG_LONGHELP=y -CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_GO=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_RESET=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_LED=y -CONFIG_CMD_LED_TRIGGER=y -CONFIG_CMD_OFTREE=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_NET_NETCONSOLE=y -CONFIG_OF_BAREBOX_DRIVERS=y -CONFIG_DRIVER_NET_MACB=y -CONFIG_NET_USB=y -CONFIG_NET_USB_ASIX=y -CONFIG_DRIVER_SPI_ATMEL=y -CONFIG_I2C=y -CONFIG_I2C_GPIO=y -CONFIG_MTD=y -# CONFIG_MTD_OOB_DEVICE is not set -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_M25P80=y -CONFIG_NAND=y -# CONFIG_NAND_ECC_SOFT is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -# CONFIG_NAND_ECC_HW_NONE is not set -CONFIG_NAND_ATMEL=y -CONFIG_NAND_ATMEL_PMECC=y -CONFIG_USB_HOST=y -CONFIG_USB_EHCI=y -CONFIG_USB_EHCI_ATMEL=y -CONFIG_USB_STORAGE=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_ATMEL=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_LED_GPIO_OF=y -CONFIG_LED_TRIGGERS=y -CONFIG_EEPROM_AT24=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_QT1070=y -CONFIG_W1=y -CONFIG_W1_MASTER_GPIO=y -CONFIG_W1_SLAVE_DS2431=y -CONFIG_W1_SLAVE_DS2433=y -CONFIG_FS_TFTP=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 5dcdff0638..16e109464b 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -37,6 +37,7 @@ CONFIG_MACH_GW_VENTANA=y CONFIG_MACH_CM_FX6=y CONFIG_MACH_ADVANTECH_ROM_742X=y CONFIG_MACH_WARP7=y +CONFIG_MACH_WEBASTO_CCBV2=y CONFIG_MACH_VF610_TWR=y CONFIG_MACH_ZII_RDU1=y CONFIG_MACH_ZII_RDU2=y diff --git a/arch/arm/configs/microchip_ksz9477_evb_defconfig b/arch/arm/configs/microchip_ksz9477_evb_defconfig deleted file mode 100644 index 7130499490..0000000000 --- a/arch/arm/configs/microchip_ksz9477_evb_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_AT91_MULTI_BOARDS=y -CONFIG_MACH_MICROCHIP_KSZ9477_EVB=y -CONFIG_AEABI=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_BOOTM_SHOW_TYPE=y -CONFIG_BOOTM_OFTREE=y -CONFIG_BOOTM_OFTREE_UIMAGE=y -CONFIG_CONSOLE_ALLOW_COLOR=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_CMD_DMESG=y -CONFIG_LONGHELP=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_AT91_BOOT_TEST=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_GO=y -CONFIG_CMD_RESET=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_DEFAULTENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_LN=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_LET=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_READF=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MM=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIME=y -CONFIG_NET=y -CONFIG_NET_NFS=y -CONFIG_OF_BAREBOX_DRIVERS=y -CONFIG_OF_BAREBOX_ENV_IN_FS=y -CONFIG_DRIVER_NET_MACB=y -CONFIG_DRIVER_NET_MICREL=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_MMC_BOOT_PARTITIONS=y -CONFIG_MCI_ATMEL=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/stm32mp_defconfig b/arch/arm/configs/stm32mp_defconfig index 92bdf5b040..e9f89e69d9 100644 --- a/arch/arm/configs/stm32mp_defconfig +++ b/arch/arm/configs/stm32mp_defconfig @@ -1,5 +1,5 @@ CONFIG_ARCH_STM32MP=y -CONFIG_MACH_STM32MP157C_DK2=y +CONFIG_MACH_STM32MP15XX_DKX=y CONFIG_MACH_LXA_MC1=y CONFIG_MACH_SEEED_ODYSSEY=y CONFIG_THUMB2_BAREBOX=y @@ -12,7 +12,6 @@ CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y CONFIG_RELOCATABLE=y CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y CONFIG_BOOTM_SHOW_TYPE=y @@ -24,10 +23,14 @@ CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_PBL_CONSOLE=y +CONFIG_CONSOLE_RATP=y +CONFIG_RATP_CMD_I2C=y +CONFIG_RATP_CMD_GPIO=y CONFIG_PARTITION_DISK_EFI=y # CONFIG_PARTITION_DISK_EFI_GPT_NO_FORCE is not set # CONFIG_PARTITION_DISK_EFI_GPT_COMPARE is not set CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_REBOOT_MODE=y CONFIG_RESET_SOURCE=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y @@ -83,10 +86,12 @@ CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_OF_DIFF=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_OVERLAY=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y CONFIG_NET=y CONFIG_NET_NETCONSOLE=y +CONFIG_NET_FASTBOOT=y CONFIG_OFDEVICE=y CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_SERIAL_STM32=y @@ -111,6 +116,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_PWM=y CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y CONFIG_EEPROM_AT24=y CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_SPECIALKEYS=y @@ -132,11 +138,17 @@ CONFIG_STM32_REMOTEPROC=y CONFIG_RESET_STM32=y CONFIG_GENERIC_PHY=y CONFIG_PHY_STM32_USBPHYC=y +CONFIG_SYSCON_REBOOT_MODE=y CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y +CONFIG_FS_PSTORE=y +CONFIG_FS_PSTORE_CONSOLE=y +CONFIG_FS_PSTORE_RAMOOPS=y +CONFIG_FS_SQUASHFS=y +CONFIG_FS_RATP=y CONFIG_ZLIB=y CONFIG_CRC8=y diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig index f9f52a6252..ca3bd98962 100644 --- a/arch/arm/cpu/Kconfig +++ b/arch/arm/cpu/Kconfig @@ -89,6 +89,7 @@ config CPU_V8 select ARM_EXCEPTIONS select GENERIC_FIND_NEXT_BIT select ARCH_HAS_STACK_DUMP + select ARCH_HAS_ZERO_PAGE config CPU_XSC3 bool diff --git a/arch/arm/cpu/dtb.c b/arch/arm/cpu/dtb.c index 8094eebf07..35f251d99a 100644 --- a/arch/arm/cpu/dtb.c +++ b/arch/arm/cpu/dtb.c @@ -26,13 +26,7 @@ static int of_arm_init(void) return 0; } - root = of_unflatten_dtb(fdt); - if (!IS_ERR(root)) { - of_set_root_node(root); - of_fix_tree(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); - } + barebox_register_fdt(fdt); return 0; } diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c index 7e9ae84810..06049e0003 100644 --- a/arch/arm/cpu/mmu_64.c +++ b/arch/arm/cpu/mmu_64.c @@ -10,6 +10,7 @@ #include <init.h> #include <mmu.h> #include <errno.h> +#include <zero_page.h> #include <linux/sizes.h> #include <asm/memory.h> #include <asm/pgtable64.h> @@ -168,6 +169,16 @@ static void mmu_enable(void) set_cr(get_cr() | CR_M | CR_C | CR_I); } +void zero_page_access(void) +{ + create_sections(0x0, 0x0, PAGE_SIZE, CACHED_MEM); +} + +void zero_page_faulting(void) +{ + create_sections(0x0, 0x0, PAGE_SIZE, 0x0); +} + /* * Prepare MMU for usage enable it. */ @@ -194,7 +205,7 @@ void __mmu_init(bool mmu_on) create_sections(bank->start, bank->start, bank->size, CACHED_MEM); /* Make zero page faulting to catch NULL pointer derefs */ - create_sections(0x0, 0x0, 0x1000, 0x0); + zero_page_faulting(); mmu_enable(); } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index af061bd292..a1e0bb6a41 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -67,6 +67,7 @@ lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-phycard.dtb.o \ imx6dl-phytec-phycore-som-emmc.dtb.o \ imx6dl-phytec-phycore-som-lc-emmc.dtb.o \ imx6ul-phytec-phycore-som-nand.dtb.o \ + imx6ul-phytec-phycore-som-emmc.dtb.o \ imx6ull-phytec-phycore-som-lc-nand.dtb.o \ imx6ull-phytec-phycore-som-nand.dtb.o \ imx6ull-phytec-phycore-som-emmc.dtb.o @@ -110,7 +111,7 @@ lwl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingb imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \ imx6q-h100.dtb.o lwl-$(CONFIG_MACH_SEEED_ODYSSEY) += stm32mp157c-odyssey.dtb.o -lwl-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2.dtb.o +lwl-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp157c-dk2.dtb.o stm32mp157a-dk1.dtb.o lwl-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o lwl-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o lwl-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o @@ -138,6 +139,7 @@ lwl-$(CONFIG_MACH_VIRT2REAL) += virt2real.dtb.o lwl-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o lwl-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o lwl-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o +lwl-$(CONFIG_MACH_WEBASTO_CCBV2) += imx6ul-webasto-ccbv2.dtb.o lwl-$(CONFIG_MACH_ZII_RDU1) += \ imx51-zii-rdu1.dtb.o \ imx51-zii-scu2-mezz.dtb.o \ diff --git a/arch/arm/dts/am335x-afi-gf.dts b/arch/arm/dts/am335x-afi-gf.dts index cba8cbc8d6..54059dbfce 100644 --- a/arch/arm/dts/am335x-afi-gf.dts +++ b/arch/arm/dts/am335x-afi-gf.dts @@ -370,186 +370,186 @@ &am33xx_pinmux { dcan0_pins: pinmux_dcan0_pins { pinctrl-single,pins = < - 0x11c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* mii1_txd3.dcan0_tx_mux0, OUTPUT_PULLUP | MODE1 */ - 0x120 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_txd2.dcan0_rx_mux0, INPUT_PULLUP | MODE1 */ + 0x11c PIN_OUTPUT_PULLUP MUX_MODE1 /* mii1_txd3.dcan0_tx_mux0, OUTPUT_PULLUP | MODE1 */ + 0x120 PIN_INPUT_PULLUP MUX_MODE1 /* mii1_txd2.dcan0_rx_mux0, INPUT_PULLUP | MODE1 */ >; }; eth_pins: pinmux_eth_pins { pinctrl-single,pins = < /* RMII2 (mezzanine) */ - 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen, OUTPUT_PULLDOWN | MODE3 */ - 0x050 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1, INPUT_PULLDOWN | MODE3 */ - 0x054 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0, INPUT_PULLDOWN | MODE3 */ - 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a10.rmii2_rxd1, INPUT_PULLDOWN | MODE3 */ - 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a11.rmii2_rxd0, INPUT_PULLDOWN | MODE3 */ - 0x070 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv, INPUT_PULLUP | MODE3 */ /* PHYAD pin */ - 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxer, INPUT_PULLUP | MODE3 */ - 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_col.rmii2_refclk, INPUT_PULLDOWN | MODE1 */ + 0x040 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* gpmc_a0.rmii2_txen, OUTPUT_PULLDOWN | MODE3 */ + 0x050 PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a4.rmii2_txd1, INPUT_PULLDOWN | MODE3 */ + 0x054 PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a5.rmii2_txd0, INPUT_PULLDOWN | MODE3 */ + 0x068 PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a10.rmii2_rxd1, INPUT_PULLDOWN | MODE3 */ + 0x06c PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a11.rmii2_rxd0, INPUT_PULLDOWN | MODE3 */ + 0x070 PIN_INPUT_PULLUP MUX_MODE3 /* gpmc_wait0.rmii2_crs_dv, INPUT_PULLUP | MODE3 */ /* PHYAD pin */ + 0x074 PIN_INPUT_PULLUP MUX_MODE3 /* gpmc_wpn.rmii2_rxer, INPUT_PULLUP | MODE3 */ + 0x108 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_col.rmii2_refclk, INPUT_PULLDOWN | MODE1 */ /* RMII1 (board) */ - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv, INPUT_PULLDOWN | MODE1 */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_er.rmii1_rxer, INPUT_PULLDOWN | MODE1 */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen, OUTPUT_PULLDOWN | MODE1 */ - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1, INPUT_PULLDOWN | MODE1 */ - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0, INPUT_PULLDOWN | MODE1 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1, INPUT_PULLDOWN | MODE1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0, INPUT_PULLDOWN | MODE1 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk, INPUT_PULLDOWN | MODE0 */ + 0x10c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_crs.rmii1_crs_dv, INPUT_PULLDOWN | MODE1 */ + 0x110 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rx_er.rmii1_rxer, INPUT_PULLDOWN | MODE1 */ + 0x114 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_tx_en.rmii1_txen, OUTPUT_PULLDOWN | MODE1 */ + 0x124 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_txd1.rmii1_txd1, INPUT_PULLDOWN | MODE1 */ + 0x128 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_txd0.rmii1_txd0, INPUT_PULLDOWN | MODE1 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd1.rmii1_rxd1, INPUT_PULLDOWN | MODE1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd0.rmii1_rxd0, INPUT_PULLDOWN | MODE1 */ + 0x144 PIN_INPUT_PULLDOWN MUX_MODE0 /* rmii1_ref_clk.rmii1_refclk, INPUT_PULLDOWN | MODE0 */ /* MDIO (board & mezzanine) */ - 0x148 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio.mdio_data, INPUT_PULLUP | MODE0 */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdc.mdio_clk, OUTPUT_PULLUP | MODE0 */ + 0x148 PIN_INPUT_PULLUP MUX_MODE0 /* mdio.mdio_data, INPUT_PULLUP | MODE0 */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdc.mdio_clk, OUTPUT_PULLUP | MODE0 */ >; }; spi0_pins: pinmux_spi0_pins { /* SPI NOR-Flash & FRAM */ pinctrl-single,pins = < - 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk, INPUT_PULLUP | MODE0 */ - 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0, INPUT_PULLUP | MODE0 */ - 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1, INPUT_PULLUP | MODE0 */ - 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0, OUTPUT_PULLUP | MODE0 */ - 0x160 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs1, OUTPUT_PULLUP | MODE0 */ + 0x150 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_sclk, INPUT_PULLUP | MODE0 */ + 0x154 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_d0, INPUT_PULLUP | MODE0 */ + 0x158 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_d1, INPUT_PULLUP | MODE0 */ + 0x15c PIN_OUTPUT_PULLUP MUX_MODE0 /* spi0_cs0, OUTPUT_PULLUP | MODE0 */ + 0x160 PIN_OUTPUT_PULLUP MUX_MODE0 /* spi0_cs1, OUTPUT_PULLUP | MODE0 */ >; }; spi1_pins: pinmux_spi1_pins { /* SPI (mezzanine) */ pinctrl-single,pins = < - 0x170 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* uart0_rxd.spi1_cs0_mux3, OUTPUT_PULLUP | MODE1 */ - 0x174 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* uart0_txd.spi1_cs1_mux3, OUTPUT_PULLUP | MODE1 */ - 0x190 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk_mux2, INPUT_PULLUP | MODE3 */ - 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_fsx.spi1_d0_mux2, INPUT_PULLUP | MODE3 */ - 0x198 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_axr0.spi1_d1_mux2, INPUT_PULLUP | MODE3 */ + 0x170 PIN_OUTPUT_PULLUP MUX_MODE1 /* uart0_rxd.spi1_cs0_mux3, OUTPUT_PULLUP | MODE1 */ + 0x174 PIN_OUTPUT_PULLUP MUX_MODE1 /* uart0_txd.spi1_cs1_mux3, OUTPUT_PULLUP | MODE1 */ + 0x190 PIN_INPUT_PULLUP MUX_MODE3 /* mcasp0_aclkx.spi1_sclk_mux2, INPUT_PULLUP | MODE3 */ + 0x194 PIN_INPUT_PULLUP MUX_MODE3 /* mcasp0_fsx.spi1_d0_mux2, INPUT_PULLUP | MODE3 */ + 0x198 PIN_INPUT_PULLUP MUX_MODE3 /* mcasp0_axr0.spi1_d1_mux2, INPUT_PULLUP | MODE3 */ >; }; usb0_pins: pinmux_usb0_pins { /* USB-HOST (mezzanine) */ pinctrl-single,pins = < - 0x208 (PIN_INPUT | MUX_MODE0) /* usb0_dm, INPUT | MODE0 */ - 0x20c (PIN_INPUT | MUX_MODE0) /* usb0_dp, INPUT | MODE0 */ - 0x210 (PIN_INPUT | MUX_MODE0) /* usb0_ce, INPUT | MODE0 */ - 0x214 (PIN_INPUT | MUX_MODE0) /* usb0_id, INPUT | MODE0 */ - 0x218 (PIN_INPUT | MUX_MODE0) /* usb0_vbus, INPUT | MODE0 */ - 0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus, OUTPUT_PULLDOWN | MODE0 */ + 0x208 PIN_INPUT MUX_MODE0 /* usb0_dm, INPUT | MODE0 */ + 0x20c PIN_INPUT MUX_MODE0 /* usb0_dp, INPUT | MODE0 */ + 0x210 PIN_INPUT MUX_MODE0 /* usb0_ce, INPUT | MODE0 */ + 0x214 PIN_INPUT MUX_MODE0 /* usb0_id, INPUT | MODE0 */ + 0x218 PIN_INPUT MUX_MODE0 /* usb0_vbus, INPUT | MODE0 */ + 0x21c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* usb0_drvvbus, OUTPUT_PULLDOWN | MODE0 */ >; }; usb1_pins: pinmux_usb1_pins { /* USB-OTG (front) */ pinctrl-single,pins = < - 0x220 (PIN_INPUT | MUX_MODE0) /* usb1_dm, INPUT | MODE0 */ - 0x224 (PIN_INPUT | MUX_MODE0) /* usb1_dp, INPUT | MODE0 */ - 0x228 (PIN_INPUT | MUX_MODE0) /* usb1_ce, INPUT | MODE0 */ - 0x22c (PIN_INPUT | MUX_MODE0) /* usb1_id, INPUT | MODE0 */ - 0x230 (PIN_INPUT | MUX_MODE0) /* usb1_vbus, INPUT | MODE0 */ - 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus, OUTPUT_PULLDOWN | MODE0 */ + 0x220 PIN_INPUT MUX_MODE0 /* usb1_dm, INPUT | MODE0 */ + 0x224 PIN_INPUT MUX_MODE0 /* usb1_dp, INPUT | MODE0 */ + 0x228 PIN_INPUT MUX_MODE0 /* usb1_ce, INPUT | MODE0 */ + 0x22c PIN_INPUT MUX_MODE0 /* usb1_id, INPUT | MODE0 */ + 0x230 PIN_INPUT MUX_MODE0 /* usb1_vbus, INPUT | MODE0 */ + 0x234 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* usb1_drvvbus, OUTPUT_PULLDOWN | MODE0 */ >; }; uart0_pins: pinmux_uart0_pins { /* debug, later spi1 CS1/2 */ pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd */ >; }; uart1_pins: pinmux_uart1_pins { /* UART1 (PRU) */ pinctrl-single,pins = < - 0x180 (PIN_INPUT | MUX_MODE5) /* uart1_rxd.pr1_uart0_rxd_mux1, INPUT | MODE5 (RS485_RXD)*/ - 0x184 (PIN_OUTPUT | MUX_MODE5) /* uart1_txd.pr1_uart0_txd_mux1, OUTPUT | MODE5 (RS485_TXD) */ + 0x180 PIN_INPUT MUX_MODE5 /* uart1_rxd.pr1_uart0_rxd_mux1, INPUT | MODE5 (RS485_RXD)*/ + 0x184 PIN_OUTPUT MUX_MODE5 /* uart1_txd.pr1_uart0_txd_mux1, OUTPUT | MODE5 (RS485_TXD) */ >; }; uart2_pins: pinmux_uart2_pins { /* UART2 (console) */ pinctrl-single,pins = < - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_clk.uart2_rxd_mux0, INPUT_PULLDOWN | MODE1 (UART2_RXD) */ - 0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_clk.uart2_txd_mux0, OUTPUT_PULLDOWN | MODE1 (UART2_TXD) */ + 0x12c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_tx_clk.uart2_rxd_mux0, INPUT_PULLDOWN | MODE1 (UART2_RXD) */ + 0x130 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_rx_clk.uart2_txd_mux0, OUTPUT_PULLDOWN | MODE1 (UART2_TXD) */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ >; }; i2c1_pins: pinmux_i2c1_pins { /* 1-wire */ pinctrl-single,pins = < - 0x168 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_ctsn.i2c1_sda_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ - 0x16c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_rtsn.i2c1_scl_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x168 PIN_INPUT_PULLUP MUX_MODE3 /* uart0_ctsn.i2c1_sda_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x16c PIN_INPUT_PULLUP MUX_MODE3 /* uart0_rtsn.i2c1_scl_mux1, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ >; }; i2c2_pins: pinmux_i2c2_pins { /* (mezzanine) */ pinctrl-single,pins = < - 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ - 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x178 PIN_INPUT_PULLUP MUX_MODE3 /* uart1_ctsn.i2c2_sda_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ + 0x17c PIN_INPUT_PULLUP MUX_MODE3 /* uart1_rtsn.i2c2_scl_mux0, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */ >; }; gpio0_pins: pinmux_gpio0_pins { pinctrl-single,pins = < - 0x020 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.gpio0[22], OUTPUT_PULLDOWN | MODE7 (LED3) */ /* PWM later */ - 0x024 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.gpio0[23], INPUT_PULLDOWN | MODE7 (RMII2_INTRP) */ - 0x028 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad10.gpio0[26], INPUT_PULLUP | MODE7 (BUTTON0) */ - 0x02c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.gpio0[27], INPUT_PULLDOWN | MODE7 (PWR_INT)*/ - 0x0d0 (PIN_INPUT | MUX_MODE7) /* lcd_data12.gpio0[8], INPUT | MODE7 (SYSBOOT12) */ - 0x0d4 (PIN_INPUT | MUX_MODE7) /* lcd_data13.gpio0[9], INPUT | MODE7 (SYSBOOT13) */ - 0x0d8 (PIN_INPUT | MUX_MODE7) /* lcd_data14.gpio0[10], INPUT | MODE7 (SYSBOOT14) */ - 0x0dc (PIN_INPUT | MUX_MODE7) /* lcd_data15.gpio0[11], INPUT | MODE7 (SYSBOOT15) */ - 0x164 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0[7], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO0) */ - 0x1b4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* xdma_event_intr1.gpio0[20], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO3) */ + 0x020 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad8.gpio0[22], OUTPUT_PULLDOWN | MODE7 (LED3) */ /* PWM later */ + 0x024 PIN_INPUT_PULLDOWN MUX_MODE7 /* gpmc_ad9.gpio0[23], INPUT_PULLDOWN | MODE7 (RMII2_INTRP) */ + 0x028 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ad10.gpio0[26], INPUT_PULLUP | MODE7 (BUTTON0) */ + 0x02c PIN_INPUT_PULLDOWN MUX_MODE7 /* gpmc_ad11.gpio0[27], INPUT_PULLDOWN | MODE7 (PWR_INT)*/ + 0x0d0 PIN_INPUT MUX_MODE7 /* lcd_data12.gpio0[8], INPUT | MODE7 (SYSBOOT12) */ + 0x0d4 PIN_INPUT MUX_MODE7 /* lcd_data13.gpio0[9], INPUT | MODE7 (SYSBOOT13) */ + 0x0d8 PIN_INPUT MUX_MODE7 /* lcd_data14.gpio0[10], INPUT | MODE7 (SYSBOOT14) */ + 0x0dc PIN_INPUT MUX_MODE7 /* lcd_data15.gpio0[11], INPUT | MODE7 (SYSBOOT15) */ + 0x164 PIN_INPUT_PULLDOWN MUX_MODE7 /* ecap0_in_pwm0_out.gpio0[7], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO0) */ + 0x1b4 PIN_INPUT_PULLDOWN MUX_MODE7 /* xdma_event_intr1.gpio0[20], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO3) */ >; }; gpio1_pins: pinmux_gpio1_pins { pinctrl-single,pins = < - 0x000 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1[0], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x004 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1[1], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x008 (PIN_INPUT | MUX_MODE7) /* gpmc_ad2.gpio1[2], INPUT | MODE7 (BOARD_REV1) */ - 0x00c (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad3.gpio1[3], INPUT_PULLUP | MODE7 (1WIRE_INT) */ - 0x010 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1[4], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x014 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1[5], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x018 (PIN_INPUT | MUX_MODE7) /* gpmc_ad6.gpio1[6], INPUT | MODE7 (BOARD_REV0) */ - 0x01c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1[7], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x030 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad12.gpio1[12], INPUT_PULLUP | MODE7 (PG_24V) */ - 0x034 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x038 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad14.gpio1[14], INPUT_PULLUP | MODE7 (SDCARD_CD) */ - 0x03c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x044 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.gpio1[17], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x048 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.gpio1[18], OUTPUT_PULLDOWN | MODE7 (LED1) */ /* PWM later */ - 0x04c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.gpio1[19], OUTPUT_PULLDOWN | MODE7 (LED2) */ /* PWM later */ - 0x058 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1[22], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x05c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1[23], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x060 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.gpio1[24], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x064 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1[25], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28], INPUT_PULLUP | MODE7 (USB1_OCn) */ - 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn0.gpio1[29], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x080 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1[30], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x084 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1[31], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x000 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad0.gpio1[0], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x004 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad1.gpio1[1], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x008 PIN_INPUT MUX_MODE7 /* gpmc_ad2.gpio1[2], INPUT | MODE7 (BOARD_REV1) */ + 0x00c PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ad3.gpio1[3], INPUT_PULLUP | MODE7 (1WIRE_INT) */ + 0x010 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad4.gpio1[4], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x014 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad5.gpio1[5], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x018 PIN_INPUT MUX_MODE7 /* gpmc_ad6.gpio1[6], INPUT | MODE7 (BOARD_REV0) */ + 0x01c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad7.gpio1[7], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x030 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ad12.gpio1[12], INPUT_PULLUP | MODE7 (PG_24V) */ + 0x034 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad13.gpio1[13], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x038 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ad14.gpio1[14], INPUT_PULLUP | MODE7 (SDCARD_CD) */ + 0x03c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ad15.gpio1[15], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x044 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a1.gpio1[17], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x048 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a2.gpio1[18], OUTPUT_PULLDOWN | MODE7 (LED1) */ /* PWM later */ + 0x04c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a3.gpio1[19], OUTPUT_PULLDOWN | MODE7 (LED2) */ /* PWM later */ + 0x058 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a6.gpio1[22], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x05c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a7.gpio1[23], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x060 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a8.gpio1[24], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x064 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a9.gpio1[25], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x078 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ben1.gpio1[28], INPUT_PULLUP | MODE7 (USB1_OCn) */ + 0x07c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_csn0.gpio1[29], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x080 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_csn1.gpio1[30], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x084 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_csn2.gpio1[31], OUTPUT_PULLDOWN | MODE7 (NC) */ >; }; gpio2_pins: pinmux_gpio2_pins { pinctrl-single,pins = < - 0x088 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2[0], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x08c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.gpio2[1], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x090 (PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2[2], INPUT | MODE7 (BOARD_REV2) */ - 0x094 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2[3], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x098 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_wen.gpio2[4], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2[5], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x0a0 (PIN_INPUT | MUX_MODE7) /* lcd_data0.gpio2[6], INPUT | MODE7 (SYSBOOT0) */ - 0x0a4 (PIN_INPUT | MUX_MODE7) /* lcd_data1.gpio2[7], INPUT | MODE7 (SYSBOOT1) */ - 0x0a8 (PIN_INPUT | MUX_MODE7) /* lcd_data2.gpio2[8], INPUT | MODE7 (SYSBOOT2) */ - 0x0ac (PIN_INPUT | MUX_MODE7) /* lcd_data3.gpio2[9], INPUT | MODE7 (SYSBOOT3) */ - 0x0b0 (PIN_INPUT | MUX_MODE7) /* lcd_data4.gpio2[10], INPUT | MODE7 (SYSBOOT4) */ - 0x0b4 (PIN_INPUT | MUX_MODE7) /* lcd_data5.gpio2[11], INPUT | MODE7 (SYSBOOT5) */ - 0x0b8 (PIN_INPUT | MUX_MODE7) /* lcd_data6.gpio2[12], INPUT | MODE7 (SYSBOOT6) */ - 0x0bc (PIN_INPUT | MUX_MODE7) /* lcd_data7.gpio2[13], INPUT | MODE7 (SYSBOOT7) */ - 0x0c0 (PIN_INPUT | MUX_MODE7) /* lcd_data8.gpio2[14], INPUT | MODE7 (SYSBOOT8) */ - 0x0c4 (PIN_INPUT | MUX_MODE7) /* lcd_data9.gpio2[15], INPUT | MODE7 (SYSBOOT9) */ - 0x0c8 (PIN_INPUT | MUX_MODE7) /* lcd_data10.gpio2[16], INPUT | MODE7 (SYSBOOT10) */ - 0x0cc (PIN_INPUT | MUX_MODE7) /* lcd_data11.gpio2[17], INPUT | MODE7 (SYSBOOT11) */ - 0x0e0 (PIN_INPUT | MUX_MODE7) /* lcd_vsync.gpio2[22], INPUT | MODE7 (BOARD_CONF1) */ - 0x0e4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x0e8 (PIN_INPUT | MUX_MODE7) /* lcd_pclk.gpio2[24], INPUT | MODE7 (BOARD_CONF0) */ - 0x0ec (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x134 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd3.gpio2[18], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd2.gpio2[19], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x088 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_csn3.gpio2[0], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x08c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_clk.gpio2[1], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x090 PIN_INPUT MUX_MODE7 /* gpmc_advn_ale.gpio2[2], INPUT | MODE7 (BOARD_REV2) */ + 0x094 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_oen_ren.gpio2[3], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x098 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_wen.gpio2[4], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x09c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_ben0_cle.gpio2[5], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x0a0 PIN_INPUT MUX_MODE7 /* lcd_data0.gpio2[6], INPUT | MODE7 (SYSBOOT0) */ + 0x0a4 PIN_INPUT MUX_MODE7 /* lcd_data1.gpio2[7], INPUT | MODE7 (SYSBOOT1) */ + 0x0a8 PIN_INPUT MUX_MODE7 /* lcd_data2.gpio2[8], INPUT | MODE7 (SYSBOOT2) */ + 0x0ac PIN_INPUT MUX_MODE7 /* lcd_data3.gpio2[9], INPUT | MODE7 (SYSBOOT3) */ + 0x0b0 PIN_INPUT MUX_MODE7 /* lcd_data4.gpio2[10], INPUT | MODE7 (SYSBOOT4) */ + 0x0b4 PIN_INPUT MUX_MODE7 /* lcd_data5.gpio2[11], INPUT | MODE7 (SYSBOOT5) */ + 0x0b8 PIN_INPUT MUX_MODE7 /* lcd_data6.gpio2[12], INPUT | MODE7 (SYSBOOT6) */ + 0x0bc PIN_INPUT MUX_MODE7 /* lcd_data7.gpio2[13], INPUT | MODE7 (SYSBOOT7) */ + 0x0c0 PIN_INPUT MUX_MODE7 /* lcd_data8.gpio2[14], INPUT | MODE7 (SYSBOOT8) */ + 0x0c4 PIN_INPUT MUX_MODE7 /* lcd_data9.gpio2[15], INPUT | MODE7 (SYSBOOT9) */ + 0x0c8 PIN_INPUT MUX_MODE7 /* lcd_data10.gpio2[16], INPUT | MODE7 (SYSBOOT10) */ + 0x0cc PIN_INPUT MUX_MODE7 /* lcd_data11.gpio2[17], INPUT | MODE7 (SYSBOOT11) */ + 0x0e0 PIN_INPUT MUX_MODE7 /* lcd_vsync.gpio2[22], INPUT | MODE7 (BOARD_CONF1) */ + 0x0e4 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* lcd_hsync.gpio2[23], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x0e8 PIN_INPUT MUX_MODE7 /* lcd_pclk.gpio2[24], INPUT | MODE7 (BOARD_CONF0) */ + 0x0ec PIN_OUTPUT_PULLDOWN MUX_MODE7 /* lcd_ac_bias_en.gpio2[25], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x134 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* mii1_rxd3.gpio2[18], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x138 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* mii1_rxd2.gpio2[19], OUTPUT_PULLDOWN | MODE7 (NC) */ >; }; gpio3_pins: pinmux_gpio3_pins { pinctrl-single,pins = < - 0x118 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mii1_rx_dv.gpio3[4], OUTPUT_PULLDOWN | MODE7 (NC) */ - 0x19c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.gpio3[17], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO1) */ - 0x1a0 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], OUTPUT_PULLUP | MODE7 (DCAN0_LBK) */ /* enable loopback by default */ - 0x1a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsr.gpio3[19], OUTPUT_PULLDOWN | MODE7 (RS485_DE) */ - 0x1a8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_axr1.gpio3[20], OUTPUT_PULLUP | MODE7 (1WIRE_SLEEP) */ - 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3[21], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO2) */ + 0x118 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* mii1_rx_dv.gpio3[4], OUTPUT_PULLDOWN | MODE7 (NC) */ + 0x19c PIN_INPUT_PULLDOWN MUX_MODE7 /* mcasp0_ahclkr.gpio3[17], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO1) */ + 0x1a0 PIN_OUTPUT_PULLUP MUX_MODE7 /* mcasp0_aclkr.gpio3[18], OUTPUT_PULLUP | MODE7 (DCAN0_LBK) */ /* enable loopback by default */ + 0x1a4 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* mcasp0_fsr.gpio3[19], OUTPUT_PULLDOWN | MODE7 (RS485_DE) */ + 0x1a8 PIN_OUTPUT_PULLUP MUX_MODE7 /* mcasp0_axr1.gpio3[20], OUTPUT_PULLUP | MODE7 (1WIRE_SLEEP) */ + 0x1ac PIN_INPUT_PULLDOWN MUX_MODE7 /* mcasp0_ahclkx.gpio3[21], INPUT_PULLDOWN | MODE7 (MEZZANINE_GPIO2) */ >; }; }; diff --git a/arch/arm/dts/am335x-baltos-minimal.dts b/arch/arm/dts/am335x-baltos-minimal.dts index a57bb6c802..dff901f050 100644 --- a/arch/arm/dts/am335x-baltos-minimal.dts +++ b/arch/arm/dts/am335x-baltos-minimal.dts @@ -47,25 +47,25 @@ &am33xx_pinmux { mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ - 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ - 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ - 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ - 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ - 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + 0xf0 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat3.mmc0_dat3 */ + 0xf4 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat2.mmc0_dat2 */ + 0xf8 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat1.mmc0_dat1 */ + 0xfc (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat0.mmc0_dat0 */ + 0x100 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_clk.mmc0_clk */ + 0x104 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_cmd.mmc0_cmd */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ - 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ + 0x158 0x2a 0 /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ + 0x15c 0x2a 0 /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ >; }; tps65910_pins: pinmux_tps65910_pins { pinctrl-single,pins = < - 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ + 0x078 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_ben1.gpio1[28] */ >; }; @@ -77,99 +77,99 @@ uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd.uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd.uart0_txd */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ + 0x10c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_crs.rmii1_crs_dv */ + 0x114 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_tx_en.rmii1_txen */ + 0x124 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_txd1.rmii1_txd1 */ + 0x128 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_txd0.rmii1_txd0 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd1.rmii1_rxd1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd0.rmii1_rxd0 */ + 0x144 PIN_INPUT_PULLDOWN MUX_MODE0 /* rmii1_ref_clk.rmii1_refclk */ /* Slave 2 */ - 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + 0x40 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a0.rgmii2_tctl */ + 0x44 PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a1.rgmii2_rctl */ + 0x48 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a2.rgmii2_td3 */ + 0x4c PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a3.rgmii2_td2 */ + 0x50 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a4.rgmii2_td1 */ + 0x54 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a5.rgmii2_td0 */ + 0x58 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* gpmc_a6.rgmii2_tclk */ + 0x5c PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a7.rgmii2_rclk */ + 0x60 PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a8.rgmii2_rd3 */ + 0x64 PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a9.rgmii2_rd2 */ + 0x68 PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a10.rgmii2_rd1 */ + 0x6c PIN_INPUT_PULLDOWN MUX_MODE2 /* gpmc_a11.rgmii2_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x10c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x114 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x124 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x128 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x13c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x140 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x144 PIN_INPUT_PULLDOWN MUX_MODE7 /* Slave 2 reset value*/ - 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x40 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x44 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x48 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x4c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x50 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x54 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x58 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x5c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x60 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x64 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x68 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x6c PIN_INPUT_PULLDOWN MUX_MODE7 >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data.mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x148 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x14c PIN_INPUT_PULLDOWN MUX_MODE7 >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + 0x0 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad0.gpmc_ad0 */ + 0x4 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad1.gpmc_ad1 */ + 0x8 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad2.gpmc_ad2 */ + 0xc PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad3.gpmc_ad3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad4.gpmc_ad4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad5.gpmc_ad5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad6.gpmc_ad6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad7.gpmc_ad7 */ + 0x70 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_wait0.gpmc_wait0 */ + 0x74 PIN_INPUT_PULLUP MUX_MODE7 /* gpmc_wpn.gpio0_30 */ + 0x7c PIN_OUTPUT MUX_MODE0 /* gpmc_csn0.gpmc_csn0 */ + 0x90 PIN_OUTPUT MUX_MODE0 /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 PIN_OUTPUT MUX_MODE0 /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 PIN_OUTPUT MUX_MODE0 /* gpmc_wen.gpmc_wen */ + 0x9c PIN_OUTPUT MUX_MODE0 /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; }; diff --git a/arch/arm/dts/am335x-bone-common-strip.dtsi b/arch/arm/dts/am335x-bone-common-strip.dtsi index e03ae2a8d3..5be246bd6f 100644 --- a/arch/arm/dts/am335x-bone-common-strip.dtsi +++ b/arch/arm/dts/am335x-bone-common-strip.dtsi @@ -66,105 +66,105 @@ user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + 0x54 PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a5.gpio1_21 */ + 0x58 PIN_OUTPUT_PULLUP MUX_MODE7 /* gpmc_a6.gpio1_22 */ + 0x5c PIN_OUTPUT_PULLDOWN MUX_MODE7 /* gpmc_a7.gpio1_23 */ + 0x60 PIN_OUTPUT_PULLUP MUX_MODE7 /* gpmc_a8.gpio1_24 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda.i2c0_sda */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl.i2c0_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd.uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd.uart0_txd */ >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + 0x1b4 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* xdma_event_intr1.clkout2 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + 0x110 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxerr.mii1_rxerr */ + 0x114 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txen.mii1_txen */ + 0x118 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxdv.mii1_rxdv */ + 0x11c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txd3.mii1_txd3 */ + 0x120 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txd2.mii1_txd2 */ + 0x124 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txd1.mii1_txd1 */ + 0x128 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* mii1_txd0.mii1_txd0 */ + 0x12c PIN_INPUT_PULLUP MUX_MODE0 /* mii1_txclk.mii1_txclk */ + 0x130 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxclk.mii1_rxclk */ + 0x134 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxd3.mii1_rxd3 */ + 0x138 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxd2.mii1_rxd2 */ + 0x13c PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxd1.mii1_rxd1 */ + 0x140 PIN_INPUT_PULLUP MUX_MODE0 /* mii1_rxd0.mii1_rxd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x114 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x118 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x11c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x120 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x124 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x128 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x12c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x130 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x134 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x138 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x13c PIN_INPUT_PULLDOWN MUX_MODE7 + 0x140 PIN_INPUT_PULLDOWN MUX_MODE7 >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data.mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x148 PIN_INPUT_PULLDOWN MUX_MODE7 + 0x14c PIN_INPUT_PULLDOWN MUX_MODE7 >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ + 0x160 PIN_INPUT MUX_MODE7 /* GPIO0_6 */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + 0x80 PIN_INPUT_PULLUP MUX_MODE2 /* gpmc_csn1.mmc1_clk */ + 0x84 PIN_INPUT_PULLUP MUX_MODE2 /* gpmc_csn2.mmc1_cmd */ + 0x00 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad0.mmc1_dat0 */ + 0x04 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad1.mmc1_dat1 */ + 0x08 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad2.mmc1_dat2 */ + 0x0c PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad3.mmc1_dat3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad4.mmc1_dat4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad5.mmc1_dat5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad6.mmc1_dat6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad7.mmc1_dat7 */ >; }; }; diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts index 80d710b924..3c286c71bf 100644 --- a/arch/arm/dts/am335x-boneblack.dts +++ b/arch/arm/dts/am335x-boneblack.dts @@ -41,32 +41,32 @@ &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < - 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ - 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0x1b0 0x03 0 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ + 0xa0 0x08 0 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xa4 0x08 0 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xa8 0x08 0 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xac 0x08 0 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb0 0x08 0 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb4 0x08 0 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb8 0x08 0 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xbc 0x08 0 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc0 0x08 0 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc4 0x08 0 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc8 0x08 0 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xcc 0x08 0 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd0 0x08 0 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd4 0x08 0 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd8 0x08 0 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xdc 0x08 0 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xe0 0x00 0 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xe4 0x00 0 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xe8 0x00 0 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xec 0x00 0 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ >; }; nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { pinctrl-single,pins = < - 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ + 0x1b0 0x03 0 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ >; }; }; @@ -85,3 +85,13 @@ status = "okay"; }; }; + +&tscadc { + status = "okay"; + adc { + /* Ch 0-6 are on connector P9. Ch 7 measures the 3.3V rail + * divided by 2 (e.g., it should read 1650). + */ + ti,adc-channels = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; + }; +}; diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dtsi b/arch/arm/dts/am335x-phytec-phycard-som.dtsi index 1d45d60dc0..e459824a77 100644 --- a/arch/arm/dts/am335x-phytec-phycard-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycard-som.dtsi @@ -14,73 +14,73 @@ i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda.i2c0_sda */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl.i2c0_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd.uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd.uart0_txd */ >; }; uart3_pins: pinmux_uart3 { pinctrl-single,pins = < - 0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */ - 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */ + 0x134 PIN_INPUT_PULLUP MUX_MODE1 /* mii1_rxd3.uart3_rxd */ + 0x138 PIN_OUTPUT_PULLDOWN MUX_MODE1 /* mii1_rxd2.uart3_txd */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ - 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ - 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ - 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ - 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ - 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + 0xf0 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat3.mmc0_dat3 */ + 0xf4 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat2.mmc0_dat2 */ + 0xf8 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat1.mmc0_dat1 */ + 0xfc (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat0.mmc0_dat0 */ + 0x100 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_clk.mmc0_clk */ + 0x104 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_cmd.mmc0_cmd */ >; }; emac_rmii1_pins: pinmux_emac_rmii1_pins { pinctrl-single,pins = < - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ - 0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - 0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + 0x10c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_crs.rmii1_crs_dv */ + 0x110 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxerr.rmii1_rxerr */ + 0x114 PIN_OUTPUT MUX_MODE1 /* mii1_txen.rmii1_txen */ + 0x124 PIN_OUTPUT MUX_MODE1 /* mii1_txd1.rmii1_txd1 */ + 0x128 PIN_OUTPUT MUX_MODE1 /* mii1_txd0.rmii1_txd0 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd1.rmii1_rxd1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd0.rmii1_rxd0 */ + 0x144 PIN_INPUT_PULLDOWN MUX_MODE0 /* rmii1_refclk.rmii1_refclk */ >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + 0x0 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad0.gpmc_ad0 */ + 0x4 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad1.gpmc_ad1 */ + 0x8 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad2.gpmc_ad2 */ + 0xc PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad3.gpmc_ad3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad4.gpmc_ad4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad5.gpmc_ad5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad6.gpmc_ad6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad7.gpmc_ad7 */ + 0x70 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_wait0.gpmc_wait0 */ + 0x7c PIN_OUTPUT MUX_MODE0 /* gpmc_csn0.gpmc_csn0 */ + 0x90 PIN_OUTPUT MUX_MODE0 /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 PIN_OUTPUT MUX_MODE0 /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 PIN_OUTPUT MUX_MODE0 /* gpmc_wen.gpmc_wen */ + 0x9c PIN_OUTPUT MUX_MODE0 /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data.mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk.mdio_clk */ >; }; }; diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi index ae3f70acdd..4b2ff9b2ea 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi @@ -19,111 +19,111 @@ &am33xx_pinmux { usb_pins: pinmux_usb_pins { pinctrl-single,pins = < - 0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ - 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + 0x21c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* usb0_drvvbus.usb0_drvvbus */ + 0x234 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* usb1_drvvbus.usb1_drvvbus */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda.i2c0_sda */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl.i2c0_scl */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < - 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ - 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ - 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ - 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + 0x150 PIN_INPUT_PULLDOWN MUX_MODE0 /* spi0_clk.spi0_clk */ + 0x154 PIN_INPUT_PULLDOWN MUX_MODE0 /* spi0_d0.spi0_d0 */ + 0x158 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_d1.spi0_d1 */ + 0x15c PIN_INPUT_PULLUP MUX_MODE0 /* spi0_cs0.spi0_cs0 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd.uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd.uart0_txd */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ - 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ - 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ - 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ - 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ - 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + 0xf0 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ + 0xf4 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ + 0xf8 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ + 0xfc MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ + 0x100 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ + 0x104 MUX_MODE0 (INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + 0x80 PIN_INPUT_PULLUP MUX_MODE2 /* gpmc_csn1.mmc1_clk */ + 0x84 PIN_INPUT_PULLUP MUX_MODE2 /* gpmc_csn2.mmc1_cmd */ + 0x00 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad0.mmc1_dat0 */ + 0x04 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad1.mmc1_dat1 */ + 0x08 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad2.mmc1_dat2 */ + 0x0c PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad3.mmc1_dat3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad4.mmc1_dat4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad5.mmc1_dat5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad6.mmc1_dat6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE1 /* gpmc_ad7.mmc1_dat7 */ >; }; emac_rmii1_pins: pinmux_emac_rmii1_pins { pinctrl-single,pins = < - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ - 0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - 0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + 0x10c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_crs.rmii1_crs_dv */ + 0x110 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxerr.rmii1_rxerr */ + 0x114 PIN_OUTPUT MUX_MODE1 /* mii1_txen.rmii1_txen */ + 0x124 PIN_OUTPUT MUX_MODE1 /* mii1_txd1.rmii1_txd1 */ + 0x128 PIN_OUTPUT MUX_MODE1 /* mii1_txd0.rmii1_txd0 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd1.rmii1_rxd1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_rxd0.rmii1_rxd0 */ + 0x144 PIN_INPUT_PULLDOWN MUX_MODE0 /* rmii1_refclk.rmii1_refclk */ >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + 0x0 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad0.gpmc_ad0 */ + 0x4 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad1.gpmc_ad1 */ + 0x8 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad2.gpmc_ad2 */ + 0xc PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad3.gpmc_ad3 */ + 0x10 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad4.gpmc_ad4 */ + 0x14 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad5.gpmc_ad5 */ + 0x18 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad6.gpmc_ad6 */ + 0x1c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad7.gpmc_ad7 */ + 0x70 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_wait0.gpmc_wait0 */ + 0x7c PIN_OUTPUT MUX_MODE0 /* gpmc_csn0.gpmc_csn0 */ + 0x90 PIN_OUTPUT MUX_MODE0 /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 PIN_OUTPUT MUX_MODE0 /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 PIN_OUTPUT MUX_MODE0 /* gpmc_wen.gpmc_wen */ + 0x9c PIN_OUTPUT MUX_MODE0 /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data.mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk.mdio_clk */ >; }; pcm051_led_pins: pinmux_pcm051_led_pins { pinctrl-single,pins = < - 0x80 (MUX_MODE7) - 0x84 (MUX_MODE7) + 0x80 0 MUX_MODE7 + 0x84 0 MUX_MODE7 >; }; pcm051_user_pins: pinmux_pcm051_user_pins { pinctrl-single,pins = < - 0x1e4 (PULL_UP |INPUT_EN |MUX_MODE7) - 0x1e8 (PULL_UP |INPUT_EN |MUX_MODE7) + 0x1e4 (PULL_UP |INPUT_EN) MUX_MODE7 + 0x1e8 (PULL_UP |INPUT_EN) MUX_MODE7 >; }; }; diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi index 0325c81346..29776f4556 100644 --- a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi @@ -35,90 +35,90 @@ &am33xx_pinmux { i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl */ + 0x188 PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_sda */ + 0x18c PIN_INPUT_PULLUP MUX_MODE0 /* i2c0_scl */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < - 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ - 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ - 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ - 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + 0x150 PIN_INPUT_PULLDOWN MUX_MODE0 /* spi0_clk.spi0_clk */ + 0x154 PIN_INPUT_PULLDOWN MUX_MODE0 /* spi0_d0.spi0_d0 */ + 0x158 PIN_INPUT_PULLUP MUX_MODE0 /* spi0_d1.spi0_d1 */ + 0x15c PIN_INPUT_PULLUP MUX_MODE0 /* spi0_cs0.spi0_cs0 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd */ + 0x170 PIN_INPUT_PULLUP MUX_MODE0 /* uart0_rxd */ + 0x174 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* uart0_txd */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x0f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ - 0x0f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ - 0x0f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ - 0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ - 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ - 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + 0x0f0 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_dat3 */ + 0x0f4 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_dat2 */ + 0x0f8 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_dat1 */ + 0x0fc PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_dat0 */ + 0x100 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_clk */ + 0x104 PIN_INPUT_PULLUP MUX_MODE0 /* mmc0_cmd */ >; }; emac_rgmii1_pins: pinmux_emac_rgmii1_pins { pinctrl-single,pins = < - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_en.rgmii1_tctl */ - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_dv.rgmii1_rctl */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_clk.rgmii1_tclk */ - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_clk.rgmii1_rclk */ - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + 0x114 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_tx_en.rgmii1_tctl */ + 0x118 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rx_dv.rgmii1_rctl */ + 0x11c PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_txd3.rgmii1_td3 */ + 0x120 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_txd2.rgmii1_td2 */ + 0x124 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_txd1.rgmii1_td1 */ + 0x128 PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_txd0.rgmii1_td0 */ + 0x12c PIN_OUTPUT_PULLDOWN MUX_MODE2 /* mii1_tx_clk.rgmii1_tclk */ + 0x130 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rx_clk.rgmii1_rclk */ + 0x134 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rxd3.rgmii1_rd3 */ + 0x138 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rxd2.rgmii1_rd2 */ + 0x13c PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rxd1.rgmii1_rd1 */ + 0x140 PIN_INPUT_PULLDOWN MUX_MODE2 /* mii1_rxd0.rgmii1_rd0 */ >; }; emac_rmii2_pins: pinmux_emac_rmii2_pins { pinctrl-single,pins = < - 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */ - 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ - 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ - 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ - 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ - 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxer */ - 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_col.rmii2_refclk */ + 0x040 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* gpmc_a0.rmii2_txen */ + 0x050 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* gpmc_a4.rmii2_txd1 */ + 0x054 PIN_OUTPUT_PULLDOWN MUX_MODE3 /* gpmc_a5.rmii2_txd0 */ + 0x068 PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a10.rmii2_rxd1 */ + 0x06c PIN_INPUT_PULLDOWN MUX_MODE3 /* gpmc_a11.rmii2_rxd0 */ + 0x074 PIN_INPUT_PULLUP MUX_MODE3 /* gpmc_wpn.rmii2_rxer */ + 0x108 PIN_INPUT_PULLDOWN MUX_MODE1 /* mii1_col.rmii2_refclk */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 /* mdio_data */ + 0x14c PIN_OUTPUT_PULLUP MUX_MODE0 /* mdio_clk */ >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - 0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0 */ - 0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1 */ - 0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2 */ - 0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3 */ - 0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4 */ - 0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5 */ - 0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6 */ - 0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7 */ - 0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ - 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_csn0 */ - 0x090 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_advn_ale */ - 0x094 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_oen_ren */ - 0x098 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_wen */ - 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_be0n_cle */ + 0x000 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad0 */ + 0x004 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad1 */ + 0x008 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad2 */ + 0x00c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad3 */ + 0x010 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad4 */ + 0x014 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad5 */ + 0x018 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad6 */ + 0x01c PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_ad7 */ + 0x070 PIN_INPUT_PULLUP MUX_MODE0 /* gpmc_wait0 */ + 0x07c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_csn0 */ + 0x090 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_advn_ale */ + 0x094 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_oen_ren */ + 0x098 PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_wen */ + 0x09c PIN_OUTPUT_PULLDOWN MUX_MODE0 /* gpmc_be0n_cle */ >; }; }; diff --git a/arch/arm/dts/at91-microchip-ksz9477-evb.dts b/arch/arm/dts/at91-microchip-ksz9477-evb.dts index a0c3ce39bb..3eb2017942 100644 --- a/arch/arm/dts/at91-microchip-ksz9477-evb.dts +++ b/arch/arm/dts/at91-microchip-ksz9477-evb.dts @@ -29,7 +29,7 @@ }; }; -&{/memory} { +&{/memory@20000000} { reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/dts/at91sam9263ek.dts b/arch/arm/dts/at91sam9263ek.dts index 9013108144..29a615f482 100644 --- a/arch/arm/dts/at91sam9263ek.dts +++ b/arch/arm/dts/at91sam9263ek.dts @@ -3,12 +3,44 @@ chosen { environment { compatible = "barebox,environment"; - device-path = &nand_controller, "partname:bareboxenv"; + device-path = &environment_nand; }; }; }; +&nand_controller { + nand@3 { + /delete-node/ partitions; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x100000>; + }; + + environment_nand: bareboxenv@120000 { + label = "barebox-environment"; + reg = <0x120000 0x20000>; + }; + + rootfs@140000 { + label = "root"; + reg = <0x140000 0x0>; + }; + }; + }; +}; + &{/ahb/apb/mmc@fff84000} { pinctrl-0 = < &pinctrl_board_mmc1 diff --git a/arch/arm/dts/at91sam9x5ek.dts b/arch/arm/dts/at91sam9x5ek.dts index c753268fb9..3a6976a7d9 100644 --- a/arch/arm/dts/at91sam9x5ek.dts +++ b/arch/arm/dts/at91sam9x5ek.dts @@ -54,6 +54,38 @@ phy-mode = "rmii"; }; +&nand_controller { + nand@3 { + /delete-node/ partitions; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x100000>; + }; + + environment_nand: bareboxenv@120000 { + label = "barebox-environment"; + reg = <0x120000 0x20000>; + }; + + rootfs@140000 { + label = "root"; + reg = <0x140000 0x0>; + }; + }; + }; +}; + &{/ahb/apb/pinctrl@fffff400} { spi0 { pinctrl_board_spi: spi-board { diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index b83511cb01..cb5ca0aba2 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -84,6 +84,11 @@ }; &fec { + /* + * barebox doesn't have a driver for the PMIC providing the phy-supply + * (dlg,da9063). So remove the phy-supply property and rely on the + * PMIC's reset default which has this supply enabled. + */ /delete-property/ phy-supply; }; @@ -155,6 +160,10 @@ barebox,provide-mac-address = <&fec 0x620>; }; +&som_eeprom { + pagesize = <32>; +}; + &usdhc3 { #address-cells = <1>; #size-cells = <1>; @@ -175,12 +184,6 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - eeprom: eeprom@50 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x50>; - }; - pmic@58 { watchdog-priority = <500>; restart-priority = <500>; diff --git a/arch/arm/dts/imx6qdl-prti6q.dtsi b/arch/arm/dts/imx6qdl-prti6q.dtsi index f2b36553d4..bfc059e34f 100644 --- a/arch/arm/dts/imx6qdl-prti6q.dtsi +++ b/arch/arm/dts/imx6qdl-prti6q.dtsi @@ -27,6 +27,17 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address will be determined by the bootloader */ + ramoops { + compatible = "ramoops"; + }; + }; + reg_1v8: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "1v8"; diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index 828be9ce0d..c3e02d2117 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -6,5 +6,26 @@ pwm2 = &pwm3; pwm3 = &pwm4; ipu0 = &ipu1; + gpr.reboot_mode = &reboot_mode_gpr; + }; +}; + +&src { + compatible = "fsl,imx6q-src", "fsl,imx51-src", "syscon", "simple-mfd"; + + reboot_mode_gpr: reboot-mode { + compatible = "barebox,syscon-reboot-mode"; + offset = <0x40>, <0x44>; /* SRC_GPR{9,10} */ + mask = <0xffffffff>, <0x10000000>; + mode-normal = <0>, <0>; + mode-serial = <0x00000010>, <0x10000000>; + mode-spi0-0 = <0x08000030>, <0x10000000>; + mode-spi0-1 = <0x18000030>, <0x10000000>; + mode-spi0-2 = <0x28000030>, <0x10000000>; + mode-spi0-3 = <0x38000030>, <0x10000000>; + mode-mmc0 = <0x00002040>, <0x10000000>; + mode-mmc1 = <0x00002840>, <0x10000000>; + mode-mmc2 = <0x00003040>, <0x10000000>; + mode-mmc3 = <0x00003840>, <0x10000000>; }; }; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts new file mode 100644 index 0000000000..50ce75f12b --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-phycore-som-emmc.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Yunus Bas <y.bas@phytec.de> + */ + +/dts-v1/; +#ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY +#include CONFIG_BOOTM_FITIMAGE_PUBKEY +#endif +#include <arm/imx6ul.dtsi> +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-state.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX6 Ultra Light SOM with eMMC"; + compatible = "phytec,imx6ul-pcl063-emmc", "fsl,imx6ul"; +}; + +&fec1 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&state { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-webasto-ccbv2.dts b/arch/arm/dts/imx6ul-webasto-ccbv2.dts new file mode 100644 index 0000000000..93e9445b48 --- /dev/null +++ b/arch/arm/dts/imx6ul-webasto-ccbv2.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019, Webasto SE + * Author: Johannes Eigner <johannes.eigner@webasto.com> + */ + +/dts-v1/; + +#include "imx6ul-webasto-ccbv2.dtsi" + +/ { + chosen { + environment { + compatible = "barebox,environment"; + device-path = &environment_emmc; + }; + }; + + aliases { + state = &state_emmc; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dt-overlay@84000000 { + reg = <0x84000000 0x100000>; + no-map; + }; + }; + + state_emmc: state { + #address-cells = <1>; + #size-cells = <1>; + compatible = "barebox,state"; + magic = <0x290cf8c6>; + backend-type = "raw"; + backend = <&backend_state_emmc>; + backend-stridesize = <0x200>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@0 { + reg = <0x0 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@4 { + reg = <0x4 0x4>; + type = "uint32"; + default = <20>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts@8 { + reg = <0x8 0x4>; + type = "uint32"; + default = <3>; + }; + + priority@c { + reg = <0xc 0x4>; + type = "uint32"; + default = <21>; + }; + }; + + last_chosen@10 { + reg = <0x10 0x4>; + type = "uint32"; + }; + }; + }; +}; + +&usdhc2 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x100000>; + }; + + environment_emmc: partition@100000 { + label = "barebox-environment"; + reg = <0x100000 0x100000>; + }; + + backend_state_emmc: partition@200000 { + label = "barebox-state"; + reg = <0x200000 0x100000>; + }; + }; +}; + + +&ocotp { + barebox,provide-mac-address = <&fec1 0x620>; +}; + +/* include the FIT public key for verifying on demand */ +#ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY +#include CONFIG_BOOTM_FITIMAGE_PUBKEY +#endif diff --git a/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi b/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi new file mode 100644 index 0000000000..829485de32 --- /dev/null +++ b/arch/arm/dts/imx6ul-webasto-ccbv2.dtsi @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2019, Webasto SE +// +// Author: Johannes Eigner <johannes.eigner@webasto.com> + +/dts-v1/; + +#include <arm/imx6ul.dtsi> + +/ { + model = "Webasto common communication board version 2"; + compatible = "webasto,imx6ul-ccbv2", "fsl,imx6ul"; + + chosen { + stdout-path = &uart7; + }; + + reg_4v: regulator-4v { + compatible = "regulator-fixed"; + regulator-name = "V_+4V"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "wl1837"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_dp83822_en: regulator-dp83822 { + compatible = "regulator-fixed"; + regulator-name = "dp83822"; + vin-supply = <&vcc_eth>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-supply = <®_dp83822_en>; + phy-handle = <&dp83822i>; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + dp83822i: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + pmic: mc34pf3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + regulators { + sw1a_reg: sw1a { + regulator-name = "V_+3V3_SW1A"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + vdd_soc_in: sw1b { + regulator-name = "V_+1V4_SW1B"; + vin-supply = <®_4v>; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + }; + sw2_reg: sw2 { + regulator-name = "V_+3V3_SW2"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vcc_ddr3: sw3 { + regulator-name = "V_+1V35_SW3"; + vin-supply = <®_4v>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + swbst_reg: swbst { + regulator-name = "V_+5V0_SWBST"; + vin-supply = <®_4v>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + vdd_snvs: vsnvs { + regulator-name = "V_+3V0_SNVS"; + vin-supply = <®_4v>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + vrefddr: vrefddr { + regulator-name = "V_+0V675_VREFDDR"; + vin-supply = <&vcc_ddr3>; + regulator-boot-on; + regulator-always-on; + }; + /* 3V3 Supply: i.MX6 modules */ + vgen1_reg: vldo1 { + regulator-name = "V_+3V3_LDO1"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + }; + vdd_high_in: v33 { + regulator-name = "V_+3V3_V33"; + vin-supply = <®_4v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vcc_eth: vldo3 { + regulator-name = "V_+1V8_LDO3"; + vin-supply = <®_4v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + vgen6_reg: vldo4 { + regulator-name = "V_+1V8_LDO4"; + vin-supply = <®_4v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = < + &gpio3 26 GPIO_ACTIVE_LOW + &gpio3 10 GPIO_ACTIVE_LOW + &gpio3 12 GPIO_ACTIVE_LOW + >; + status = "okay"; + + cc2520: spi@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cc2520>; + compatible = "ti,cc2520"; + reg = <0>; + spi-max-frequency = <4000000>; + fifo-gpio = <&gpio3 15 0>; + fifop-gpio = <&gpio3 16 0>; + sfd-gpio = <&gpio3 24 0>; + cca-gpio = <&gpio3 20 0>; + vreg-gpio = <&gpio3 19 0>; + reset-gpio = <&gpio3 23 0>; + vin-supply = <&sw2_reg>; + }; + qca7000: spi@1 { + compatible = "qca,qca7000"; + reg = <1>; + spi-max-frequency = <8000000>; + interrupt-parent = <&gpio4>; + interrupts = <16 0x1>; + spi-cpha; + spi-cpol; + }; + tfr7970: spi@2 { + compatible = "ti,trf7970a"; + reg = <2>; + spi-max-frequency = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_trf7970>; + interrupt-parent = <&gpio3>; + interrupts = <14 0>; + ti,enable-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>, <&gpio3 17 GPIO_ACTIVE_HIGH>; + vin-supply = <®_4v>; + vdd-io-supply = <&sw2_reg>; + autosuspend-delay = <30000>; + clock-frequency = <27120000>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; + status = "okay"; + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + vin-supply = <®_4v>; + }; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + non-removable; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + vmmc-supply = <&sw1a_reg>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + keep-power-in-suspend; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_minipcie>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +®_arm { + vin-supply = <&vdd_soc_in>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&vdd_soc_in>; + regulator-allow-bypass; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x13030 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x13030 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10000 + >; + }; + + pinctrl_minipcie: minipciegrp { + fsl,pins = < + /* HYS=1, 100k PullDown, 50MHz, R0/6 */ + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x13030 + MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x13030 + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x13030 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x13030 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x13030 + >; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x1b0b0 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x1b0b0 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x1b0b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x17030 + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x17030 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x17030 + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x10030 + >; + }; + + pinctrl_cc2520: cc2520grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x13030 + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x13030 + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x13030 + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x13030 + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x13030 + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x13030 + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x17030 + + >; + }; + + pinctrl_trf7970: trf7970grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x17030 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x10030 + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x10030 + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x17000 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x1b0b0 + MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x1b0b0 + MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x1b0b0 + MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x1b0b0 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x13030 + MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x13030 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b0 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b0 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b0 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x10030 + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x00010 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b0 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x10059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x10059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x10059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x10059 + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x17000 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10030 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100e9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x100e9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x100e9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x100e9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x100e9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x100e9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x100e9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x100e9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x100e9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x100e9 + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10030 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x00b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts index 2201b4c1b2..afd99a3fd9 100644 --- a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts @@ -10,6 +10,7 @@ #endif #include <arm/imx6ull.dtsi> #include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-state.dtsi" / { model = "PHYTEC phyCORE-i.MX6 ULL SOM with eMMC"; @@ -24,6 +25,10 @@ status = "okay"; }; +&state { + status = "okay"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts index bb255e2c94..3264ade4b8 100644 --- a/arch/arm/dts/imx8mp-evk.dts +++ b/arch/arm/dts/imx8mp-evk.dts @@ -7,6 +7,7 @@ /dts-v1/; #include <arm64/freescale/imx8mp-evk.dts> +#include "imx8mp.dtsi" / { chosen { diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi new file mode 100644 index 0000000000..b251ebeada --- /dev/null +++ b/arch/arm/dts/imx8mp.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + remoteproc_cm7: remoteproc-cm7 { + compatible = "fsl,imx8mp-cm7"; + clocks = <&clk IMX8MP_CLK_M7_CORE>; + syscon = <&src>; + }; +}; diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index 5f2df35bc9..ec8347f38f 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -4,6 +4,14 @@ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> */ +/ { + remoteproc_cm4: remoteproc-cm4 { + compatible = "fsl,imx8mq-cm4"; + clocks = <&clk IMX8MQ_CLK_M4_CORE>; + syscon = <&src>; + }; +}; + &clk { assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>, <&clk IMX8MQ_CLK_USDHC2>, diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index c9af5f2f7a..15682f9d27 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -7,7 +7,7 @@ }; }; -/delete-node/ &{/memory}; +/delete-node/ &{/memory@20000000}; &sdmmc0 { assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index cc25400475..ca11492de5 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -28,6 +28,7 @@ pwm15 = &{/soc/timer@44006000/pwm}; pwm16 = &{/soc/timer@44007000/pwm}; pwm17 = &{/soc/timer@44008000/pwm}; + tamp.reboot_mode = &reboot_mode_tamp; }; }; @@ -42,6 +43,20 @@ compatible = "st,stm32mp1-ddr"; reg = <0x5a003000 0x1000>; }; + + tamp@5c00a000 { + compatible = "simple-bus", "syscon", "simple-mfd"; + reg = <0x5c00a000 0x400>; + + reboot_mode_tamp: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x150>; /* reg20 */ + mask = <0xff>; + mode-normal = <0>; + mode-loader = <0xBB>; + mode-recovery = <0xBC>; + }; + }; }; &bsec { diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index f2cafae66b..7a907cc314 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -5,4 +5,4 @@ */ #include <arm/stm32mp157a-dk1.dts> -#include "stm32mp157a-dk1.dtsi" +#include "stm32mp15xx-dkx.dtsi" diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 6e73162ea4..98525abd71 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -5,4 +5,4 @@ */ #include <arm/stm32mp157c-dk2.dts> -#include "stm32mp157a-dk1.dtsi" +#include "stm32mp15xx-dkx.dtsi" diff --git a/arch/arm/dts/stm32mp157a-dk1.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 173e64e04c..173e64e04c 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi diff --git a/arch/arm/lib32/bootm.c b/arch/arm/lib32/bootm.c index c33ecc2ad8..28a645a9d0 100644 --- a/arch/arm/lib32/bootm.c +++ b/arch/arm/lib32/bootm.c @@ -114,10 +114,11 @@ static int get_kernel_addresses(size_t image_size, kaddr = mem_start + image_decomp_size; /* - * Make sure we do not place the image past the end of the + * Make sure we do not place the image outside of the * available memory. */ - if (kaddr + image_size + spacing >= mem_end) + if (((kaddr + image_size + spacing) > mem_end) && + ((mem_end - image_size - spacing) >= mem_start)) kaddr = mem_end - image_size - spacing; *load_address = PAGE_ALIGN_DOWN(kaddr); @@ -745,8 +746,8 @@ static struct binfmt_hook binfmt_barebox_hook = { .exec = "bootm", }; -BAREBOX_MAGICVAR_NAMED(global_bootm_boot_atag, global.bootm.boot_atag, - "If true, ignore device tree and boot using ATAGs"); +BAREBOX_MAGICVAR(global.bootm.boot_atag, + "If true, ignore device tree and boot using ATAGs"); static int armlinux_register_image_handler(void) { diff --git a/arch/arm/mach-at91/at91_pmc_ll.c b/arch/arm/mach-at91/at91_pmc_ll.c index 9205322db9..e561f20755 100644 --- a/arch/arm/mach-at91/at91_pmc_ll.c +++ b/arch/arm/mach-at91/at91_pmc_ll.c @@ -88,6 +88,8 @@ void at91_pmc_init(void __iomem *pmc_base, unsigned int flags) tmp &= ~AT91_PMC_OSCBYPASS; tmp &= ~AT91_PMC_KEY_MASK; tmp |= AT91_PMC_KEY; + if (flags & AT91_PMC_LL_FLAG_MCK_BYPASS) + tmp |= AT91_PMC_OSCBYPASS; at91_pmc_write(AT91_CKGR_MOR, tmp); tmp = at91_pmc_read(AT91_CKGR_MOR); diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c index 5d21b2d021..0b1567cd23 100644 --- a/arch/arm/mach-at91/bootstrap.c +++ b/arch/arm/mach-at91/bootstrap.c @@ -78,7 +78,7 @@ static void at91bootstrap_boot_nand(bool is_barebox) kernel_entry_func func = NULL; printf("Boot %s from nand\n", name); - func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M); + func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M, NULL); bootstrap_boot(func, is_barebox); bootstrap_err("... failed\n"); free(func); @@ -89,7 +89,7 @@ static void at91bootstrap_boot_mmc(void) kernel_entry_func func = NULL; printf("Boot from mmc\n"); - func = bootstrap_read_disk("disk0.0", NULL); + func = bootstrap_read_disk("disk0.0", NULL, NULL); bootstrap_boot(func, false); bootstrap_err("... failed\n"); free(func); diff --git a/arch/arm/mach-at91/ddramc.c b/arch/arm/mach-at91/ddramc.c index a241ea9f0a..c3ef6b0090 100644 --- a/arch/arm/mach-at91/ddramc.c +++ b/arch/arm/mach-at91/ddramc.c @@ -52,8 +52,4 @@ static struct driver_d sama5_ddr_driver = { .of_compatible = sama5_ddr_dt_ids, }; -static int sama5_ddr_init(void) -{ - return platform_driver_register(&sama5_ddr_driver); -} -mem_initcall(sama5_ddr_init); +mem_platform_driver(sama5_ddr_driver); diff --git a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h index 6ec3ae0852..85896a01d5 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h @@ -16,6 +16,7 @@ #define AT91_PMC_LL_FLAG_H32MXDIV (1 << 3) #define AT91_PMC_LL_FLAG_PMC_UTMI (1 << 4) #define AT91_PMC_LL_FLAG_GCSR (1 << 5) +#define AT91_PMC_LL_FLAG_MCK_BYPASS (1 << 6) #define AT91_PMC_LL_AT91RM9200 (0) #define AT91_PMC_LL_AT91SAM9260 (0) @@ -30,6 +31,10 @@ #define AT91_PMC_LL_SAMA5D2 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ AT91_PMC_LL_FLAG_MEASURE_XTAL | \ AT91_PMC_LL_FLAG_PMC_UTMI) +/* This assumes a crystal on both XIN and XOUT. If your board + * instead has an extenal oscillator on XIN only, + * AT91_PMC_LL_FLAG_MCK_BYPASS needs to be OR`ed in as well + */ #define AT91_PMC_LL_SAMA5D3 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ AT91_PMC_LL_FLAG_DISABLE_RC | \ AT91_PMC_LL_FLAG_PMC_UTMI) diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index d295d35d1b..04924742a5 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -41,7 +41,7 @@ * Copyright (c) 2006, Atmel Corporation */ -#include <asm-generic/io.h> +#include <asm/io.h> static inline void at91_wdt_disable(void __iomem *wdt_base) { diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index 05584c0711..813c2a0d94 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -200,8 +200,4 @@ static struct driver_d at91sam9_smc_driver = { .probe = at91sam9_smc_probe, }; -static int at91sam9_smc_init(void) -{ - return platform_driver_register(&at91sam9_smc_driver); -} -coredevice_initcall(at91sam9_smc_init); +coredevice_platform_driver(at91sam9_smc_driver); diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c index 22abbb0ca5..9839683d03 100644 --- a/arch/arm/mach-bcm283x/mbox.c +++ b/arch/arm/mach-bcm283x/mbox.c @@ -179,8 +179,4 @@ static struct driver_d bcm2835_mbox_driver = { .probe = bcm2835_mbox_probe, }; -static int __init bcm2835_mbox_init(void) -{ - return platform_driver_register(&bcm2835_mbox_driver); -} -core_initcall(bcm2835_mbox_init); +core_platform_driver(bcm2835_mbox_driver); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 720fe874d7..dd49537fd5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -146,7 +146,7 @@ config ARCH_IMX6 select ARCH_HAS_IMX_GPT select CPU_V7 select PINCTRL_IMX_IOMUX_V3 - select OFTREE + select OFDEVICE select COMMON_CLK_OF_PROVIDER select HW_HAS_PCI @@ -157,8 +157,6 @@ config ARCH_IMX6SL config ARCH_IMX6SX bool select ARCH_IMX6 - select OFTREE - select COMMON_CLK_OF_PROVIDER config ARCH_IMX6UL bool @@ -340,6 +338,8 @@ config MACH_PHYTEC_SOM_IMX6 bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6" select ARCH_IMX6 select ARCH_IMX6UL + select I2C + select I2C_IMX config MACH_PROTONIC_IMX6 bool "Protonic-Holland i.MX6 based boards" @@ -578,6 +578,11 @@ config MACH_DIGI_CCIMX6ULSBCPRO select ARCH_IMX6UL select ARM_USE_COMPRESSED_DTB +config MACH_WEBASTO_CCBV2 + bool "Webasto Common Communication Board V2" + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB + endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index cc5d3a8359..426a96a3c4 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -703,12 +703,7 @@ static struct driver_d imx_esdctl_driver = { .of_compatible = DRV_OF_COMPAT(imx_esdctl_dt_ids), }; -static int imx_esdctl_init(void) -{ - return platform_driver_register(&imx_esdctl_driver); -} - -mem_initcall(imx_esdctl_init); +mem_platform_driver(imx_esdctl_driver); /* * The i.MX SoCs usually have two SDRAM chipselects. The following diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c index 2f9ffbd271..b60c5de7e1 100644 --- a/arch/arm/mach-imx/iim.c +++ b/arch/arm/mach-imx/iim.c @@ -586,10 +586,4 @@ static struct driver_d imx_iim_driver = { .of_compatible = DRV_OF_COMPAT(imx_iim_dt_ids), }; -static int imx_iim_init(void) -{ - platform_driver_register(&imx_iim_driver); - - return 0; -} -coredevice_initcall(imx_iim_init); +coredevice_platform_driver(imx_iim_driver); diff --git a/arch/arm/mach-imx/include/mach/clock-imx6.h b/arch/arm/mach-imx/include/mach/clock-imx6.h index 8e5e9d92b0..69fbedd51e 100644 --- a/arch/arm/mach-imx/include/mach/clock-imx6.h +++ b/arch/arm/mach-imx/include/mach/clock-imx6.h @@ -1,20 +1,5 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2010-2011 Freescale Semiconductor, Inc. */ #ifndef __ARCH_ARM_MACH_MX6_CRM_REGS_H__ #define __ARCH_ARM_MACH_MX6_CRM_REGS_H__ diff --git a/arch/arm/mach-imx/include/mach/iim.h b/arch/arm/mach-imx/include/mach/iim.h index cc89b0d109..3199e4e790 100644 --- a/arch/arm/mach-imx/include/mach/iim.h +++ b/arch/arm/mach-imx/include/mach/iim.h @@ -1,17 +1,5 @@ -/* - * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */ #ifndef __MACH_IMX_IIM_H #define __MACH_IMX_IIM_H diff --git a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h index 73028d26cf..651bf9a5c9 100644 --- a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h +++ b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h @@ -1,11 +1,5 @@ -/* - * Copyright (C) 2008 - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2008 Guennadi Liakhovetski <lg@denx.de>, DENX Software Engineering */ #ifndef __MACH_IMX_IPU_FB_H__ #define __MACH_IMX_IPU_FB_H__ diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index a5754c57db..d63669e1e0 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -1,17 +1,5 @@ -/* - * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */ #ifndef __ASM_ARCH_MX25_REGS_H #define __ASM_ARCH_MX25_REGS_H diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h index 3d6c91c503..56c518c120 100644 --- a/arch/arm/mach-imx/include/mach/imx31-regs.h +++ b/arch/arm/mach-imx/include/mach/imx31-regs.h @@ -1,17 +1,5 @@ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */ #ifndef __ASM_ARCH_MX31_REGS_H #define __ASM_ARCH_MX31_REGS_H diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h index 0a3f9273c7..4a4aa754aa 100644 --- a/arch/arm/mach-imx/include/mach/imx35-regs.h +++ b/arch/arm/mach-imx/include/mach/imx35-regs.h @@ -1,17 +1,5 @@ -/* - * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */ #ifndef __ASM_ARCH_MX35_REGS_H #define __ASM_ARCH_MX35_REGS_H diff --git a/arch/arm/mach-imx/include/mach/imx6-anadig.h b/arch/arm/mach-imx/include/mach/imx6-anadig.h index 65a7dbda4c..38f4ad7351 100644 --- a/arch/arm/mach-imx/include/mach/imx6-anadig.h +++ b/arch/arm/mach-imx/include/mach/imx6-anadig.h @@ -1,18 +1,7 @@ -/* - * Freescale ANADIG Register Definitions - * - * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2008-2011 Freescale Semiconductor, Inc. */ + +/* Freescale ANADIG Register Definitions */ #ifndef __ARCH_ARM___ANADIG_H #define __ARCH_ARM___ANADIG_H diff --git a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h index 39b3b55bb2..f10902cec2 100644 --- a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2013 Boundary Devices Inc. */ #define MX6_MMDC_P0_MDCTL 0x021b0000 #define MX6_MMDC_P0_MDPDC 0x021b0004 diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index 1ba22b5bc6..7350ffd16f 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -115,6 +115,7 @@ #define MX6_IP2APB_USBPHY1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x78000) #define MX6_IP2APB_USBPHY2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x7C000) +#define MX6_UART7_BASE_ADDR 0x02018000 #define MX6_SATA_BASE_ADDR 0x02200000 #define MX6_MMDC_PORT01_BASE_ADDR 0x10000000 diff --git a/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h index a312e63a99..9e5764276f 100644 --- a/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6dl-ddr-regs.h @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2013 Boundary Devices Inc. */ #define MX6_IOM_DRAM_ADDR00 0x020e0424 #define MX6_IOM_DRAM_ADDR01 0x020e0428 diff --git a/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h index f910574370..3f20b95091 100644 --- a/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6q-ddr-regs.h @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2013 Boundary Devices Inc. */ #define MX6_IOM_DRAM_DQM0 0x020e05ac #define MX6_IOM_DRAM_DQM1 0x020e05b4 diff --git a/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h index e66b2da11e..3ff690608a 100644 --- a/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h +++ b/arch/arm/mach-imx/include/mach/imx7-ddr-regs.h @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2017 Pengutronix, Fridolin Tux <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2017 Uwe Kleine-König <u.kleine-koenig@pengutronix.de>, Pengutronix */ #define MX7_DDRC_MSTR 0x307a0000 #define MX7_DDRC_STAT 0x307a0004 diff --git a/arch/arm/mach-imx/include/mach/iomux-mx21.h b/arch/arm/mach-imx/include/mach/iomux-mx21.h index 203190d1d7..308bfac99b 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx21.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx21.h @@ -1,15 +1,6 @@ -/* - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Holger Schurig <hs4233@mail.mn-solutions.de> */ + #ifndef __MACH_IOMUX_MX21_H__ #define __MACH_IOMUX_MX21_H__ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h index b6e334559d..5f8a3826f6 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx27.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx27.h @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2008 Sascha Hauer <kernel@pengutronix.de> */ +/* SPDX-FileCopyrightText: 2009 Holger Schurig <hs4233@mail.mn-solutions.de> */ + #ifndef __MACH_IOMUX_MX27_H__ #define __MACH_IOMUX_MX27_H__ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx2x.h b/arch/arm/mach-imx/include/mach/iomux-mx2x.h index 15c2e2b060..64f07c0c33 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx2x.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx2x.h @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2008 Sascha Hauer <kernel@pengutronix.de> */ +/* SPDX-FileCopyrightText: 2009 Holger Schurig <hs4233@mail.mn-solutions.de> */ + #ifndef __MACH_IOMUX_MX2x_H__ #define __MACH_IOMUX_MX2x_H__ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx31.h b/arch/arm/mach-imx/include/mach/iomux-mx31.h index c814c15912..d524125a85 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx31.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx31.h @@ -1,17 +1,7 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2004-2006 Freescale Semiconductor, Inc. */ +/* SPDX-FileCopyrightText: 2008 Sascha Hauer <kernel@pengutronix.de> */ + #ifndef __MACH_IOMUX_MX3_H__ #define __MACH_IOMUX_MX3_H__ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx35.h b/arch/arm/mach-imx/include/mach/iomux-mx35.h index 30b94e3b00..18f9a11171 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx35.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx35.h @@ -1,16 +1,5 @@ -/* - * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option, NO_PAD_CTRL) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Jan Weitzel <armlinux@phytec.de>, Phytec Messtechnik GmbH */ #ifndef __MACH_IOMUX_MX35_H__ #define __MACH_IOMUX_MX35_H__ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx50.h b/arch/arm/mach-imx/include/mach/iomux-mx50.h index c21bb3ea9b..aeb47092df 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx50.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx50.h @@ -1,22 +1,8 @@ -/* - * Copyright 2013 Greg Ungerer <gerg@uclinux.org> - * Copyright 2016 Alexander Kurz <akurz@blala.de> - * based on linux imx50-pinfunc.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc.. - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2013 Greg Ungerer <gerg@uclinux.org> */ +/* SPDX-FileCopyrightText: 2016 Alexander Kurz <akurz@blala.de> */ + +/* based on linux imx50-pinfunc.h */ #ifndef __MACH_IOMUX_MX50_H__ #define __MACH_IOMUX_MX50_H__ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx53.h b/arch/arm/mach-imx/include/mach/iomux-mx53.h index 527f8fe3e3..010fb6e5cc 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx53.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx53.h @@ -1,20 +1,5 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc.. - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2010-2011 Freescale Semiconductor, Inc. */ #ifndef __MACH_IOMUX_MX53_H__ #define __MACH_IOMUX_MX53_H__ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx6.h b/arch/arm/mach-imx/include/mach/iomux-mx6.h index 57d1a3bf9f..36e31e0657 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx6.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx6.h @@ -1,23 +1,6 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Auto Generate file, please don't edit it - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2011 Freescale Semiconductor, Inc. */ + #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) #ifndef __MACH_IOMUX_MX6Q_H__ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx6ul.h b/arch/arm/mach-imx/include/mach/iomux-mx6ul.h new file mode 100644 index 0000000000..b7727191c2 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx6ul.h @@ -0,0 +1,1064 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __ASM_ARCH_IMX6UL_PINS_H__ +#define __ASM_ARCH_IMX6UL_PINS_H__ + +#include <mach/iomux-v3.h> + +enum { + + MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x02A0, 0x0014, 5, 0x0000, 0, 0), + MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x02A4, 0x0018, 5, 0x0000, 0, 0), + /* + * The TAMPER Pin can be used for GPIO, which depends on + * fusemap TAMPER_PIN_DISABLE[1:0] settings. + */ + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x02A8, 0x001C, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x02AC, 0x0020, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x02B0, 0x0024, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x02B4, 0x0028, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x02B8, 0x002C, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x02BC, 0x0030, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x02C0, 0x0034, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x02C4, 0x0038, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x02C8, 0x003C, 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x02CC, 0x0040, 5, 0x0000, 0, 0), + + MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0), + MX6_PAD_JTAG_MOD__SPDIF_OUT = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__CCM_PMIC_RDY = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0), + MX6_PAD_JTAG_MOD__GPIO1_IO10 = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0), + + MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPT2_CAPTURE1 = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0), + MX6_PAD_JTAG_TMS__SAI2_MCLK = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0), + MX6_PAD_JTAG_TMS__CCM_CLKO1 = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__CCM_WAIT = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPIO1_IO11 = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0), + MX6_PAD_JTAG_TMS__EPIT1_OUT = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPT2_CAPTURE2 = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0), + MX6_PAD_JTAG_TDO__SAI2_TX_SYNC = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0), + MX6_PAD_JTAG_TDO__CCM_CLKO2 = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__CCM_STOP = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPIO1_IO12 = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__MQS_RIGHT = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__EPIT2_OUT = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPT2_COMPARE1 = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SAI2_TX_BCLK = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0), + MX6_PAD_JTAG_TDI__PWM6_OUT = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPIO1_IO13 = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__MQS_LEFT = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPT2_COMPARE2 = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0), + MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3 = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0), + MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1 = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1 = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0), + MX6_PAD_GPIO1_IO00__MQS_RIGHT = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO01__I2C2_SDA = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0), + MX6_PAD_GPIO1_IO01__GPT1_COMPARE1 = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__USB_OTG1_OC = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0), + MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2 = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0), + MX6_PAD_GPIO1_IO01__MQS_LEFT = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO02__I2C1_SCL = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0), + MX6_PAD_GPIO1_IO02__GPT1_COMPARE2 = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USDHC1_WP = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0), + MX6_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0), + MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DCE_TX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DTE_RX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0), + + MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0), + MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0), + MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0), + MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__UART1_DCE_RX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0), + MX6_PAD_GPIO1_IO03__UART1_DTE_TX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0), + MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DCE_TX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DTE_RX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0), + + MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2 = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0), + MX6_PAD_GPIO1_IO05__PWM4_OUT = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0), + MX6_PAD_GPIO1_IO05__CSI_FIELD = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0), + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__UART5_DCE_RX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0), + MX6_PAD_GPIO1_IO05__UART5_DTE_TX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO06__ENET1_MDIO = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0), + MX6_PAD_GPIO1_IO06__ENET2_MDIO = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0), + MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CSI_MCLK = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__USDHC2_WP = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0), + MX6_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_REF_EN_B = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DCE_CTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DTE_RTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0), + + MX6_PAD_GPIO1_IO07__ENET1_MDC = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__ENET2_MDC = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CSI_PIXCLK = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0), + MX6_PAD_GPIO1_IO07__USDHC2_CD_B = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0), + MX6_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__UART1_DCE_RTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0), + MX6_PAD_GPIO1_IO07__UART1_DTE_CTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__SPDIF_OUT = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CSI_VSYNC = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0), + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DTE_CTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__SPDIF_IN = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0), + MX6_PAD_GPIO1_IO09__CSI_HSYNC = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0), + MX6_PAD_GPIO1_IO09__USDHC2_RESET_B = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__USDHC1_RESET_B = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DTE_RTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__I2C3_SCL = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0), + MX6_PAD_UART1_TX_DATA__CSI_DATA02 = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0), + MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1 = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__GPIO1_IO16 = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__SPDIF_OUT = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__I2C3_SDA = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0), + MX6_PAD_UART1_RX_DATA__CSI_DATA03 = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0), + MX6_PAD_UART1_RX_DATA__GPT1_CLK = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0), + MX6_PAD_UART1_RX_DATA__GPIO1_IO17 = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__SPDIF_IN = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0), + + MX6_PAD_UART1_CTS_B__UART1_DCE_CTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_CTS_B__UART1_DTE_RTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC1_WP = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0), + MX6_PAD_UART1_CTS_B__CSI_DATA04 = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0), + MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__GPIO1_IO18 = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC2_WP = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0), + + MX6_PAD_UART1_RTS_B__UART1_DCE_RTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0), + + MX6_PAD_UART1_RTS_B__UART1_DTE_CTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__ENET1_TX_ER = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0), + MX6_PAD_UART1_RTS_B__CSI_DATA05 = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0), + MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__GPIO1_IO19 = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__I2C4_SCL = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0), + MX6_PAD_UART2_TX_DATA__CSI_DATA06 = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0), + MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1 = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0), + MX6_PAD_UART2_TX_DATA__GPIO1_IO20 = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__I2C4_SDA = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0), + MX6_PAD_UART2_RX_DATA__CSI_DATA07 = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0), + MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2 = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0), + MX6_PAD_UART2_RX_DATA__GPIO1_IO21 = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__SJC_DONE = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DCE_CTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DTE_RTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0), + MX6_PAD_UART2_CTS_B__ENET1_CRS = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__FLEXCAN2_TX = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__CSI_DATA08 = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0), + MX6_PAD_UART2_CTS_B__GPT1_COMPARE2 = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__GPIO1_IO22 = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__SJC_DE_B = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__ECSPI3_MOSI = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0), + + MX6_PAD_UART2_RTS_B__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0), + + MX6_PAD_UART2_RTS_B__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ENET1_COL = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__FLEXCAN2_RX = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0), + MX6_PAD_UART2_RTS_B__CSI_DATA09 = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0), + MX6_PAD_UART2_RTS_B__GPT1_COMPARE3 = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__GPIO1_IO23 = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__SJC_FAIL = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ECSPI3_MISO = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__CSI_DATA01 = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0), + MX6_PAD_UART3_TX_DATA__GPIO1_IO24 = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__CSI_DATA00 = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0), + MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0), + MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__GPIO1_IO25 = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__EPIT1_OUT = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__FLEXCAN1_TX = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__CSI_DATA10 = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0), + MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__GPIO1_IO26 = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__EPIT2_OUT = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0), + + MX6_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__ENET2_TX_ER = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__FLEXCAN1_RX = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0), + MX6_PAD_UART3_RTS_B__CSI_DATA11 = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0), + MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__GPIO1_IO27 = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__I2C1_SCL = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0), + MX6_PAD_UART4_TX_DATA__CSI_DATA12 = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0), + MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DCE_RX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DTE_TX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__I2C1_SDA = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0), + MX6_PAD_UART4_RX_DATA__CSI_DATA13 = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0), + MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__GPIO1_IO29 = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ECSPI2_SS0 = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0), + MX6_PAD_UART5_TX_DATA__GPIO1_IO30 = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0), + MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), + MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), + MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 5, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ENET2_COL = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__I2C2_SDA = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0), + MX6_PAD_UART5_RX_DATA__CSI_DATA15 = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0), + MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__GPIO1_IO31 = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ECSPI2_MISO = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__PWM1_OUT = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__CSI_DATA16 = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0), + MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__KPP_ROW00 = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0), + MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0), + MX6_PAD_ENET1_RX_DATA1__PWM2_OUT = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__CSI_DATA17 = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0), + MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0), + MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__KPP_COL00 = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0), + MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), + MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), + MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__KPP_ROW01 = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0), + MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), + MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), + MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), + MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__KPP_COL01 = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0), + MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0), + MX6_PAD_ENET1_TX_DATA1__PWM5_OUT = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__CSI_DATA20 = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0), + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0), + MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__KPP_ROW02 = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0), + MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0), + MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__PWM6_OUT = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__CSI_DATA21 = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0), + MX6_PAD_ENET1_TX_EN__ENET2_MDC = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__GPIO2_IO05 = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__KPP_COL02 = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0), + MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0), + MX6_PAD_ENET1_TX_CLK__PWM7_OUT = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__CSI_DATA22 = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0), + MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__KPP_ROW03 = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__GPT1_CLK = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0), + + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0), + MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__PWM8_OUT = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__CSI_DATA23 = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0), + MX6_PAD_ENET1_RX_ER__EIM_CRE = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPIO2_IO07 = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__KPP_COL03 = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2 = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0), + MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__I2C3_SCL = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0), + MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0), + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__I2C3_SDA = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0), + MX6_PAD_ENET2_RX_DATA1__ENET1_MDC = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0), + + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DTE_RX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0), + MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__I2C4_SCL = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0), + MX6_PAD_ENET2_RX_EN__EIM_ADDR26 = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__I2C4_SDA = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0), + MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0), + MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0), + MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03 = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0), + MX6_PAD_ENET2_TX_EN__UART8_DTE_TX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0), + MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0), + + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0), + MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0), + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0), + + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0), + MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__ECSPI4_SS0 = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DCE_TX = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DTE_RX = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0), + MX6_PAD_LCD_CLK__SAI3_MCLK = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0), + MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART4_DCE_RX = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0), + MX6_PAD_LCD_ENABLE__UART4_DTE_TX = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0), + MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0), + MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DCE_CTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DTE_RTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0), + MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0), + MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0), + MX6_PAD_LCD_VSYNC__UART4_DCE_RTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0), + MX6_PAD_LCD_VSYNC__UART4_DTE_CTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__SAI3_RX_DATA = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0), + MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__CA7_MX6UL_EVENTI = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__SAI3_TX_DATA = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0), + MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0), + + MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0), + MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0), + + MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0), + MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0), + + MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0), + MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0), + + MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0), + MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), + MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0), + MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), + MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0), + MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), + MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0), + MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SRC_BT_CFG08 = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__FLEXCAN1_TX = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0), + MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0), + MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SRC_BT_CFG09 = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__FLEXCAN1_RX = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0), + + MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0), + MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SRC_BT_CFG10 = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0), + MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SRC_BT_CFG11 = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__FLEXCAN2_RX = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0), + + MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0), + MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0), + MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SRC_BT_CFG12 = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__ECSPI1_RDY = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0), + MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0), + MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SRC_BT_CFG13 = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__USDHC2_RESET_B = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0), + MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0), + MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0), + + MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0), + MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0), + + MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0), + MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0), + MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0), + + MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), + MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0), + MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0), + + MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CA7_MX6UL_EVENTO = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CSI_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0), + MX6_PAD_LCD_DATA18__EIM_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__SRC_BT_CFG26 = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__USDHC2_CMD = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0), + MX6_PAD_LCD_DATA19__EIM_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__SRC_BT_CFG27 = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__USDHC2_CLK = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0), + + MX6_PAD_LCD_DATA19__LCDIF_DATA19 = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__PWM6_OUT = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__CSI_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0), + MX6_PAD_LCD_DATA20__EIM_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__SRC_BT_CFG28 = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__USDHC2_DATA0 = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0), + + MX6_PAD_LCD_DATA20__LCDIF_DATA20 = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DCE_TX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DTE_RX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0), + MX6_PAD_LCD_DATA20__ECSPI1_SCLK = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0), + MX6_PAD_LCD_DATA20__CSI_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0), + + MX6_PAD_LCD_DATA21__LCDIF_DATA21 = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__UART8_DCE_RX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0), + MX6_PAD_LCD_DATA21__UART8_DTE_TX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__ECSPI1_SS0 = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0), + MX6_PAD_LCD_DATA21__CSI_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0), + MX6_PAD_LCD_DATA21__EIM_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0), + + MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0), + MX6_PAD_LCD_DATA22__CSI_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0), + MX6_PAD_LCD_DATA22__EIM_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__SRC_BT_CFG30 = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__USDHC2_DATA2 = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0), + + MX6_PAD_LCD_DATA23__LCDIF_DATA23 = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__MQS_LEFT = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0), + MX6_PAD_LCD_DATA23__CSI_DATA15 = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0), + MX6_PAD_LCD_DATA23__EIM_DATA15 = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__SRC_BT_CFG31 = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__USDHC2_DATA3 = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0), + + MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__USDHC2_CLK = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0), + MX6_PAD_NAND_RE_B__QSPI_B_SCLK = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__KPP_ROW00 = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0), + MX6_PAD_NAND_RE_B__EIM_EB_B00 = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__GPIO4_IO00 = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__ECSPI3_SS2 = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__USDHC2_CMD = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__KPP_COL00 = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0), + MX6_PAD_NAND_WE_B__EIM_EB_B01 = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__GPIO4_IO01 = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__ECSPI3_SS3 = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__KPP_ROW01 = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0), + MX6_PAD_NAND_DATA00__EIM_AD08 = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__GPIO4_IO02 = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__ECSPI4_RDY = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0), + MX6_PAD_NAND_DATA01__QSPI_B_DQS = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__KPP_COL01 = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0), + MX6_PAD_NAND_DATA01__EIM_AD09 = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__GPIO4_IO03 = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__ECSPI4_SS1 = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__KPP_ROW02 = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0), + MX6_PAD_NAND_DATA02__EIM_AD10 = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__GPIO4_IO04 = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__ECSPI4_SS2 = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__KPP_COL02 = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0), + MX6_PAD_NAND_DATA03__EIM_AD11 = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__GPIO4_IO05 = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__ECSPI4_SS3 = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__ECSPI4_SCLK = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0), + MX6_PAD_NAND_DATA04__EIM_AD12 = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__GPIO4_IO06 = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DCE_TX = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DTE_RX = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0), + + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__ECSPI4_MOSI = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0), + MX6_PAD_NAND_DATA05__EIM_AD13 = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__GPIO4_IO07 = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__UART2_DCE_RX = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0), + MX6_PAD_NAND_DATA05__UART2_DTE_TX = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0), + MX6_PAD_NAND_DATA06__SAI2_RX_BCLK = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__ECSPI4_MISO = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0), + MX6_PAD_NAND_DATA06__EIM_AD14 = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__GPIO4_IO08 = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DCE_CTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DTE_RTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0), + + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__ECSPI4_SS0 = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0), + MX6_PAD_NAND_DATA07__EIM_AD15 = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__GPIO4_IO09 = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__UART2_DCE_RTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0), + MX6_PAD_NAND_DATA07__UART2_DTE_CTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__USDHC2_RESET_B = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__QSPI_A_DQS = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__PWM3_OUT = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__EIM_ADDR17 = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__GPIO4_IO10 = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__ECSPI3_SS1 = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__QSPI_A_SCLK = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__PWM4_OUT = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__EIM_BCLK = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__GPIO4_IO11 = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__ECSPI3_RDY = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__USDHC1_DATA4 = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__ECSPI3_SS0 = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0), + MX6_PAD_NAND_READY_B__EIM_CS1_B = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__GPIO4_IO12 = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DCE_TX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DTE_RX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0), + + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__ECSPI3_SCLK = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0), + MX6_PAD_NAND_CE0_B__EIM_DTACK_B = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__GPIO4_IO13 = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__UART3_DCE_RX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0), + MX6_PAD_NAND_CE0_B__UART3_DTE_TX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__ECSPI3_MOSI = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__GPIO4_IO14 = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DCE_CTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DTE_RTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0), + + MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__USDHC1_DATA7 = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__ECSPI3_MISO = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0), + MX6_PAD_NAND_CLE__EIM_ADDR16 = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__GPIO4_IO15 = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__UART3_DCE_RTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0), + MX6_PAD_NAND_CLE__UART3_DTE_CTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__CSI_FIELD = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__PWM5_OUT = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__EIM_WAIT = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__GPIO4_IO16 = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0), + MX6_PAD_NAND_DQS__SPDIF_EXT_CLK = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0), + + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT2_COMPARE1 = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SAI2_RX_SYNC = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SPDIF_OUT = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__EIM_ADDR19 = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO2_IO16 = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0), + MX6_PAD_SD1_CMD__USB_OTG1_PWR = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPT2_COMPARE2 = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SAI2_MCLK = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0), + MX6_PAD_SD1_CLK__SPDIF_IN = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0), + MX6_PAD_SD1_CLK__EIM_ADDR20 = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO2_IO17 = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USB_OTG1_OC = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0), + + MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPT2_COMPARE3 = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__SAI2_TX_SYNC = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0), + MX6_PAD_SD1_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__EIM_ADDR21 = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPIO2_IO18 = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0), + + MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPT2_CLK = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0), + MX6_PAD_SD1_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0), + MX6_PAD_SD1_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0), + MX6_PAD_SD1_DATA1__EIM_ADDR22 = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPIO2_IO19 = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPT2_CAPTURE1 = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0), + MX6_PAD_SD1_DATA2__SAI2_RX_DATA = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0), + MX6_PAD_SD1_DATA2__FLEXCAN2_TX = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__EIM_ADDR23 = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPIO2_IO20 = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__USB_OTG2_OC = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0), + + MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPT2_CAPTURE2 = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0), + MX6_PAD_SD1_DATA3__SAI2_TX_DATA = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__FLEXCAN2_RX = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0), + MX6_PAD_SD1_DATA3__EIM_ADDR24 = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPIO2_IO21 = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0), + + MX6_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__USDHC2_CD_B = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__I2C1_SDA = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0), + MX6_PAD_CSI_MCLK__EIM_CS0_B = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__GPIO4_IO17 = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DCE_TX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DTE_RX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0), + + MX6_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0), + MX6_PAD_CSI_PIXCLK__USDHC2_WP = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__I2C1_SCL = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0), + MX6_PAD_CSI_PIXCLK__EIM_OE = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__GPIO4_IO18 = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__UART6_DCE_RX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0), + MX6_PAD_CSI_PIXCLK__UART6_DTE_TX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0), + MX6_PAD_CSI_VSYNC__USDHC2_CLK = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0), + MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__I2C2_SDA = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0), + MX6_PAD_CSI_VSYNC__EIM_RW = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__GPIO4_IO19 = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__PWM7_OUT = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DCE_RTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DTE_CTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0), + MX6_PAD_CSI_HSYNC__USDHC2_CMD = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0), + MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__I2C2_SCL = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0), + MX6_PAD_CSI_HSYNC__EIM_LBA_B = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__GPIO4_IO20 = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__PWM8_OUT = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DCE_CTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DTE_RTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0), + + MX6_PAD_CSI_DATA00__CSI_DATA02 = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0), + MX6_PAD_CSI_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0), + MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0), + MX6_PAD_CSI_DATA00__EIM_AD00 = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__GPIO4_IO21 = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__SRC_INT_BOOT = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DCE_TX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DTE_RX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0), + + MX6_PAD_CSI_DATA01__CSI_DATA03 = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0), + MX6_PAD_CSI_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0), + MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__ECSPI2_SS0 = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0), + MX6_PAD_CSI_DATA01__EIM_AD01 = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__GPIO4_IO22 = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__SAI1_MCLK = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0), + MX6_PAD_CSI_DATA01__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0), + MX6_PAD_CSI_DATA01__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA02__CSI_DATA04 = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0), + MX6_PAD_CSI_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0), + MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__ECSPI2_MOSI = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0), + MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0), + MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), + MX6_PAD_CSI_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0), + MX6_PAD_CSI_DATA03__SIM2_PORT1_PD = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__ECSPI2_MISO = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0), + MX6_PAD_CSI_DATA03__EIM_AD03 = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__GPIO4_IO24 = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__SAI1_RX_BCLK = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DCE_CTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DTE_RTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0), + + MX6_PAD_CSI_DATA04__CSI_DATA06 = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0), + MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0), + MX6_PAD_CSI_DATA04__EIM_AD04 = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__GPIO4_IO25 = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__SAI1_TX_SYNC = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC1_WP = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0), + + MX6_PAD_CSI_DATA05__CSI_DATA07 = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0), + MX6_PAD_CSI_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0), + MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__ECSPI1_SS0 = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0), + MX6_PAD_CSI_DATA05__EIM_AD05 = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__GPIO4_IO26 = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__SAI1_TX_BCLK = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0), + MX6_PAD_CSI_DATA05__USDHC1_CD_B = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0), + + MX6_PAD_CSI_DATA06__CSI_DATA08 = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0), + MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__ECSPI1_MOSI = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0), + MX6_PAD_CSI_DATA06__EIM_AD06 = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__GPIO4_IO27 = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__SAI1_RX_DATA = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC1_RESET_B = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA07__CSI_DATA09 = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0), + MX6_PAD_CSI_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0), + MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__ECSPI1_MISO = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0), + MX6_PAD_CSI_DATA07__EIM_AD07 = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__GPIO4_IO28 = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__SAI1_TX_DATA = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__USDHC1_VSELECT = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX6UL_PINS_H__ */ diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h index d1a72a2cf5..e1d62ae4b8 100644 --- a/arch/arm/mach-imx/include/mach/iomux-v3.h +++ b/arch/arm/mach-imx/include/mach/iomux-v3.h @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2009 Jan Weitzel <armlinux@phytec.de>, Phytec Messtechnik GmbH */ #ifndef __MACH_IOMUX_V3_H__ #define __MACH_IOMUX_V3_H__ diff --git a/arch/arm/mach-layerscape/ppa.c b/arch/arm/mach-layerscape/ppa.c index 7eacf18cc9..53e73f6a58 100644 --- a/arch/arm/mach-layerscape/ppa.c +++ b/arch/arm/mach-layerscape/ppa.c @@ -69,14 +69,13 @@ static int ppa_init(void *ppa, size_t ppa_size, void *sec_firmware_addr) fit = fit_open_buf(ppa, ppa_size, false, BOOTM_VERIFY_AVAILABLE); if (IS_ERR(fit)) { - pr_err("Cannot open ppa FIT image: %s\n", strerrorp(fit)); + pr_err("Cannot open ppa FIT image: %pe\n", fit); return PTR_ERR(fit); } conf = fit_open_configuration(fit, NULL); if (IS_ERR(conf)) { - pr_err("Cannot open default config in ppa FIT image: %s\n", - strerrorp(conf)); + pr_err("Cannot open default config in ppa FIT image: %pe\n", conf); ret = PTR_ERR(conf); goto err; } diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c index f230d9ad89..a4df39c2e9 100644 --- a/arch/arm/mach-mxs/ocotp.c +++ b/arch/arm/mach-mxs/ocotp.c @@ -229,13 +229,7 @@ static struct driver_d mxs_ocotp_driver = { .of_compatible = DRV_OF_COMPAT(mxs_ocotp_compatible), }; -static int mxs_ocotp_init(void) -{ - platform_driver_register(&mxs_ocotp_driver); - - return 0; -} -coredevice_initcall(mxs_ocotp_init); +coredevice_platform_driver(mxs_ocotp_driver); int mxs_ocotp_read(void *buf, int count, int offset) { diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c index 0a49038270..8fa2c70aa2 100644 --- a/arch/arm/mach-omap/am33xx_clock.c +++ b/arch/arm/mach-omap/am33xx_clock.c @@ -165,6 +165,10 @@ void am33xx_enable_per_clocks(void) __raw_writel(PRCM_MOD_EN, CM_PER_USB0_CLKCTRL); while ((__raw_readl(CM_PER_USB0_CLKCTRL) & 0x30000) != 0x0); + /* TSC & ADC */ + __raw_writel(PRCM_MOD_EN, CM_WKUP_ADC_TSC_CLKCTRL); + while (__raw_readl(CM_WKUP_ADC_TSC_CLKCTRL) != PRCM_MOD_EN); + clkdcoldo = __raw_readl(CM_CLKDCOLDO_DPLL_PER); clkdcoldo = clkdcoldo | 0x100; __raw_writel(clkdcoldo, CM_CLKDCOLDO_DPLL_PER); diff --git a/arch/arm/mach-omap/am33xx_scrm.c b/arch/arm/mach-omap/am33xx_scrm.c index f03fb2bf6a..80510cf5b4 100644 --- a/arch/arm/mach-omap/am33xx_scrm.c +++ b/arch/arm/mach-omap/am33xx_scrm.c @@ -43,9 +43,4 @@ static struct driver_d am33xx_scrm_driver = { .of_compatible = DRV_OF_COMPAT(am33xx_scrm_dt_ids), }; -static int am33xx_scrm_init(void) -{ - return platform_driver_register(&am33xx_scrm_driver); -} - -mem_initcall(am33xx_scrm_init); +mem_platform_driver(am33xx_scrm_driver); diff --git a/arch/arm/mach-omap/boot_order.c b/arch/arm/mach-omap/boot_order.c index db22513bde..4b74fdba66 100644 --- a/arch/arm/mach-omap/boot_order.c +++ b/arch/arm/mach-omap/boot_order.c @@ -70,13 +70,13 @@ static int cmd_boot_order(int argc, char *argv[]) } BAREBOX_CMD_HELP_START(boot_order) -BAREBOX_CMD_HELP_TEXT("Set warm boot order of up to four devices. Each device can be one of:") +BAREBOX_CMD_HELP_TEXT("Set OMAP warm boot order of up to four devices. Each device can be one of:") BAREBOX_CMD_HELP_TEXT("xip xipwait nand onenand mmc1 mmc2_1 mmc2_2 uart usb_1 usb_ulpi usb_2") BAREBOX_CMD_HELP_END BAREBOX_CMD_START(boot_order) .cmd = cmd_boot_order, - BAREBOX_CMD_DESC("set warm boot order") + BAREBOX_CMD_DESC("set OMAP warm boot order") BAREBOX_CMD_OPTS("DEVICE...") BAREBOX_CMD_GROUP(CMD_GRP_BOOT) BAREBOX_CMD_HELP(cmd_boot_order_help) diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index 284d5f8cf6..e71ecbcd24 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -138,6 +138,7 @@ #define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */ #define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */ #define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x8) /* GPIO0 */ +#define CM_WKUP_ADC_TSC_CLKCTRL (CM_WKUP + 0xbc)/* TSCADC */ #define CM_PER_MMC0_CLKCTRL (CM_PER + 0x3C) #define CM_PER_MMC1_CLKCTRL (CM_PER + 0xF4) diff --git a/arch/arm/mach-socfpga/xload.c b/arch/arm/mach-socfpga/xload.c index ee7d194427..5c611ac6e1 100644 --- a/arch/arm/mach-socfpga/xload.c +++ b/arch/arm/mach-socfpga/xload.c @@ -8,6 +8,8 @@ #include <fs.h> #include <io.h> +#include <image-metadata.h> + #include <linux/clkdev.h> #include <linux/stat.h> #include <linux/clk.h> @@ -31,13 +33,14 @@ static __noreturn int socfpga_xload(void) enum bootsource bootsource = bootsource_get(); const struct socfpga_barebox_part *part; void *buf = NULL; + size_t bufsize; switch (bootsource) { case BOOTSOURCE_MMC: socfpga_cyclone5_mmc_init(); for (part = barebox_parts; part->mmc_disk; part++) { - buf = bootstrap_read_disk(barebox_parts->mmc_disk, "fat"); + buf = bootstrap_read_disk(barebox_parts->mmc_disk, "fat", &bufsize); if (!buf) { pr_info("failed to load barebox from MMC %s\n", part->mmc_disk); @@ -48,17 +51,35 @@ static __noreturn int socfpga_xload(void) pr_err("failed to load barebox.bin from MMC\n"); hang(); } + + if (IS_ENABLED(CONFIG_IMD)) + if (imd_verify_crc32(buf, bufsize) == -EILSEQ) { + pr_err("failed to verify barebox.bin loaded from eMMC\n"); + hang(); + } + break; case BOOTSOURCE_SPI: socfpga_cyclone5_qspi_init(); for (part = barebox_parts; part->nor_size; part++) { buf = bootstrap_read_devfs("mtd0", false, - part->nor_offset, part->nor_size, SZ_1M); + part->nor_offset, part->nor_size, SZ_1M, &bufsize); if (!buf) { pr_info("failed to load barebox from QSPI NOR flash at offset %#x\n", part->nor_offset); continue; } + + if (IS_ENABLED(CONFIG_IMD)) + if (imd_verify_crc32(buf, bufsize) == -EILSEQ) { + pr_err("failed to verify barebox loaded from " + "QSPI NOR flash at offset %#x\n", + part->nor_offset); + free(buf); + buf = NULL; + continue; + } + break; } diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index f064a38088..b8ccbaab67 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -8,9 +8,12 @@ config ARCH_STM32MP157 select ARM_PSCI_CLIENT bool -config MACH_STM32MP157C_DK2 +config MACH_STM32MP15XX_DKX select ARCH_STM32MP157 - bool "STM32MP157C-DK2 board" + bool "STM32MP157 DK1 and DK2 boards" + help + builds a single barebox-stm32mp15xx-dkx.img that can be deployed + as SSBL on both the stm32mp157a-dk1 and stm32mp157c-dk2 config MACH_LXA_MC1 select ARCH_STM32MP157 diff --git a/arch/arm/mach-stm32mp/ddrctrl.c b/arch/arm/mach-stm32mp/ddrctrl.c index 962d4c0d52..646fe4401a 100644 --- a/arch/arm/mach-stm32mp/ddrctrl.c +++ b/arch/arm/mach-stm32mp/ddrctrl.c @@ -148,8 +148,4 @@ static struct driver_d stm32mp1_ddr_driver = { .of_compatible = DRV_OF_COMPAT(stm32mp1_ddr_dt_ids), }; -static int stm32mp1_ddr_init(void) -{ - return platform_driver_register(&stm32mp1_ddr_driver); -} -mem_initcall(stm32mp1_ddr_init); +mem_platform_driver(stm32mp1_ddr_driver); diff --git a/arch/arm/mach-stm32mp/include/mach/bootsource.h b/arch/arm/mach-stm32mp/include/mach/bootsource.h index 1b6f562ac3..5750dc1448 100644 --- a/arch/arm/mach-stm32mp/include/mach/bootsource.h +++ b/arch/arm/mach-stm32mp/include/mach/bootsource.h @@ -18,16 +18,4 @@ enum stm32mp_boot_device { STM32MP_BOOT_SERIAL_USB_OTG = 0x62, }; -enum stm32mp_forced_boot_mode { - STM32MP_BOOT_NORMAL = 0x00, - STM32MP_BOOT_FASTBOOT = 0x01, - STM32MP_BOOT_RECOVERY = 0x02, - STM32MP_BOOT_STM32PROG = 0x03, - STM32MP_BOOT_UMS_MMC0 = 0x10, - STM32MP_BOOT_UMS_MMC1 = 0x11, - STM32MP_BOOT_UMS_MMC2 = 0x12, -}; - -enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void); - #endif diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h index 2eb4d44b33..2ef8ef30c3 100644 --- a/arch/arm/mach-stm32mp/include/mach/revision.h +++ b/arch/arm/mach-stm32mp/include/mach/revision.h @@ -6,6 +6,9 @@ #ifndef __MACH_CPUTYPE_H__ #define __MACH_CPUTYPE_H__ +#include <mach/bsec.h> +#include <asm/io.h> +#include <mach/stm32.h> /* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI @@ -45,4 +48,52 @@ int stm32mp_package(void); #define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx) #define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx) +/* DBGMCU register */ +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_DEV_ID_SHIFT 0 +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16 + +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* BSEC OTP index */ +#define BSEC_OTP_RPN 1 +#define BSEC_OTP_PKG 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(7, 0) + +static inline u32 stm32mp_read_idc(void) +{ + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + return readl(IOMEM(DBGMCU_IDC)); +} + +/* Get Device Part Number (RPN) from OTP */ +static inline int __stm32mp_get_cpu_rpn(u32 *rpn) +{ + int ret = bsec_read_field(BSEC_OTP_RPN, rpn); + if (ret) + return ret; + + *rpn = (*rpn >> RPN_SHIFT) & RPN_MASK; + return 0; +} + +static inline int __stm32mp_get_cpu_type(u32 *type) +{ + u32 id; + int ret = __stm32mp_get_cpu_rpn(type); + if (ret) + return ret; + + id = (stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; + *type |= id << 16; + return 0; +} + #endif /* __MACH_CPUTYPE_H__ */ diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c index 7f687fa4f2..01961ae456 100644 --- a/arch/arm/mach-stm32mp/init.c +++ b/arch/arm/mach-stm32mp/init.c @@ -15,26 +15,6 @@ #include <bootsource.h> #include <dt-bindings/pinctrl/stm32-pinfunc.h> -/* DBGMCU register */ -#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) -#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) -#define DBGMCU_APB4FZ1_IWDG2 BIT(2) -#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) -#define DBGMCU_IDC_DEV_ID_SHIFT 0 -#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) -#define DBGMCU_IDC_REV_ID_SHIFT 16 - -#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -/* BSEC OTP index */ -#define BSEC_OTP_RPN 1 -#define BSEC_OTP_PKG 16 - -/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(7, 0) - /* Package = bit 27:29 of OTP16 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm @@ -80,12 +60,6 @@ #define FIXUP_CPU_NUM(mask) ((mask) >> 16) #define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL) -static enum stm32mp_forced_boot_mode __stm32mp_forced_boot_mode; -enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void) -{ - return __stm32mp_forced_boot_mode; -} - static void setup_boot_mode(void) { u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); @@ -121,17 +95,11 @@ static void setup_boot_mode(void) break; } - __stm32mp_forced_boot_mode = boot_ctx & TAMP_BOOT_FORCED_MASK; - - pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d forced=0x%x\n", - boot_ctx, boot_mode, instance, __stm32mp_forced_boot_mode); + pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d\n", + boot_ctx, boot_mode, instance); bootsource_set(src); bootsource_set_instance(instance); - - /* clear TAMP for next reboot */ - clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, - STM32MP_BOOT_NORMAL); } static int __stm32mp_cputype; @@ -152,38 +120,9 @@ int stm32mp_package(void) return __stm32mp_package; } -static inline u32 read_idc(void) -{ - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - return readl(IOMEM(DBGMCU_IDC)); -} - -/* Get Device Part Number (RPN) from OTP */ -static int get_cpu_rpn(u32 *rpn) -{ - int ret = bsec_read_field(BSEC_OTP_RPN, rpn); - if (ret) - return ret; - - *rpn = (*rpn >> RPN_SHIFT) & RPN_MASK; - return 0; -} - static u32 get_cpu_revision(void) { - return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; -} - -static int get_cpu_type(u32 *type) -{ - u32 id; - int ret = get_cpu_rpn(type); - if (ret) - return ret; - - id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; - *type |= id << 16; - return 0; + return (stm32mp_read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; } static int get_cpu_package(u32 *pkg) @@ -250,7 +189,7 @@ static int setup_cpu_type(void) u32 pkg; int ret; - get_cpu_type(&__stm32mp_cputype); + __stm32mp_get_cpu_type(&__stm32mp_cputype); switch (__stm32mp_cputype) { case CPU_STM32MP157Fxx: cputypestr = "157F"; @@ -366,4 +305,4 @@ static int stm32mp_init(void) return 0; } -postcore_initcall(stm32mp_init); +core_initcall(stm32mp_init); diff --git a/arch/arm/mach-stm32mp/stm32image.c b/arch/arm/mach-stm32mp/stm32image.c index 84975c5c3b..207df6894d 100644 --- a/arch/arm/mach-stm32mp/stm32image.c +++ b/arch/arm/mach-stm32mp/stm32image.c @@ -43,8 +43,6 @@ static struct image_handler image_handler_stm32_image_v1_handler = { static int stm32mp_register_stm32image_image_handler(void) { - register_image_handler(&image_handler_stm32_image_v1_handler); - - return 0; + return register_image_handler(&image_handler_stm32_image_v1_handler); } late_initcall(stm32mp_register_stm32image_image_handler); diff --git a/arch/arm/mach-tegra/tegra20-timer.c b/arch/arm/mach-tegra/tegra20-timer.c index 2ba58bd65e..34d34f7723 100644 --- a/arch/arm/mach-tegra/tegra20-timer.c +++ b/arch/arm/mach-tegra/tegra20-timer.c @@ -104,8 +104,4 @@ static struct driver_d tegra20_timer_driver = { .of_compatible = DRV_OF_COMPAT(tegra20_timer_dt_ids), }; -static int tegra20_timer_init(void) -{ - return platform_driver_register(&tegra20_timer_driver); -} -core_initcall(tegra20_timer_init); +core_platform_driver(tegra20_timer_driver); diff --git a/arch/arm/mach-zynq/bootm-zynqimg.c b/arch/arm/mach-zynq/bootm-zynqimg.c index e903ab6679..77ed6880e4 100644 --- a/arch/arm/mach-zynq/bootm-zynqimg.c +++ b/arch/arm/mach-zynq/bootm-zynqimg.c @@ -42,8 +42,6 @@ static struct image_handler zynq_image_handler = { static int zynq_register_image_handler(void) { - register_image_handler(&zynq_image_handler); - - return 0; + return register_image_handler(&zynq_image_handler); } late_initcall(zynq_register_image_handler); diff --git a/arch/arm/mach-zynqmp/firmware-zynqmp.c b/arch/arm/mach-zynqmp/firmware-zynqmp.c index 6123aa1ea4..c23b434031 100644 --- a/arch/arm/mach-zynqmp/firmware-zynqmp.c +++ b/arch/arm/mach-zynqmp/firmware-zynqmp.c @@ -637,8 +637,4 @@ static struct driver_d zynqmp_firmware_driver = { .of_compatible = DRV_OF_COMPAT(zynqmp_firmware_id_table), }; -static int zynqmp_firmware_init(void) -{ - return platform_driver_register(&zynqmp_firmware_driver); -} -core_initcall(zynqmp_firmware_init); +core_platform_driver(zynqmp_firmware_driver); diff --git a/arch/kvx/lib/dtb.c b/arch/kvx/lib/dtb.c index 17dcab197f..54ffddaf0a 100644 --- a/arch/kvx/lib/dtb.c +++ b/arch/kvx/lib/dtb.c @@ -12,17 +12,7 @@ static int of_kvx_init(void) int ret; struct device_node *root; - root = of_unflatten_dtb(boot_dtb); - if (IS_ERR(root)) { - ret = PTR_ERR(root); - panic("Failed to parse DTB: %d\n", ret); - } - - ret = of_set_root_node(root); - if (ret) - panic("Failed to set of root node\n"); - - of_probe(); + barebox_register_fdt(boot_dtb); return 0; } diff --git a/arch/mips/boards/loongson-ls1b/lowlevel.S b/arch/mips/boards/loongson-ls1b/lowlevel.S index c533df3ce5..7240d351b4 100644 --- a/arch/mips/boards/loongson-ls1b/lowlevel.S +++ b/arch/mips/boards/loongson-ls1b/lowlevel.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> + * Copyright (C) 2020 Du Huanpeng <u74147@gmail.com> */ #define BOARD_PBL_START start_loongson_ls1b @@ -11,15 +12,42 @@ #include <asm/pbl_nmon.h> #include <linux/sizes.h> +#include <mach/pbl_macros.h> +#include <mach/pbl_ll_init_loongson1.h> + ENTRY_FUNCTION(BOARD_PBL_START) mips_barebox_10h mips_disable_interrupts + pbl_blt 0xbf000000 skip_pll_ram_config t0 + + pbl_loongson1_pll + + pbl_loongson1_uart_enable debug_ll_ns16550_init debug_ll_outc '.' debug_ll_ns16550_outnl + debug_ll_outc '1' + + pbl_loongson1_remap + debug_ll_outc '2' + + pbl_loongson1_ddr2_init + pbl_probe_mem t0, t1, KSEG1 + bne t0, t1, . + nop + + debug_ll_outc '3' + + mips_cache_reset + dcache_enable + debug_ll_outc '4' + +skip_pll_ram_config: + debug_ll_outc '5' + debug_ll_ns16550_outnl ENTRY_FUNCTION_END(BOARD_PBL_START, loongson_ls1b, SZ_64M) diff --git a/arch/mips/boot/dtb.c b/arch/mips/boot/dtb.c index 5e316270f6..6fce4700cc 100644 --- a/arch/mips/boot/dtb.c +++ b/arch/mips/boot/dtb.c @@ -35,20 +35,13 @@ extern char __dtb_start[]; static int of_mips_init(void) { - struct device_node *root; void *fdt; fdt = glob_fdt; if (!fdt) fdt = __dtb_start; - root = of_unflatten_dtb(fdt); - if (!IS_ERR(root)) { - pr_debug("using internal DTB\n"); - of_set_root_node(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); - } + barebox_register_fdt(fdt); return 0; } diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h index df58c4cf0d..703bfaee77 100644 --- a/arch/mips/include/asm/debug_ll_ns16550.h +++ b/arch/mips/include/asm/debug_ll_ns16550.h @@ -58,14 +58,14 @@ static inline void PUTC_LL(char ch) * Macros for use in assembly language code */ -.macro debug_ll_ns16550_init +.macro debug_ll_ns16550_init divisor=DEBUG_LL_UART_DIVISOR #ifdef CONFIG_DEBUG_LL la t0, DEBUG_LL_UART_ADDR li t1, UART_LCR_DLAB /* DLAB on */ sb t1, UART_LCR(t0) /* Write it out */ - li t1, DEBUG_LL_UART_DIVISOR + li t1, \divisor sb t1, UART_DLL(t0) /* write low order byte */ srl t1, t1, 8 sb t1, UART_DLM(t0) /* write high order byte */ diff --git a/arch/mips/mach-ath79/art.c b/arch/mips/mach-ath79/art.c index 44118c19e9..d119ca6d1a 100644 --- a/arch/mips/mach-ath79/art.c +++ b/arch/mips/mach-ath79/art.c @@ -103,10 +103,4 @@ static struct driver_d art_driver = { .of_compatible = art_dt_ids, }; -static int art_of_driver_init(void) -{ - platform_driver_register(&art_driver); - - return 0; -} -late_initcall(art_of_driver_init); +late_platform_driver(art_driver); diff --git a/arch/mips/mach-loongson/include/mach/pbl_ll_init_loongson1.h b/arch/mips/mach-loongson/include/mach/pbl_ll_init_loongson1.h new file mode 100644 index 0000000000..a4d7c78e1f --- /dev/null +++ b/arch/mips/mach-loongson/include/mach/pbl_ll_init_loongson1.h @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020 Du Huanpeng <u74147@gmail.com> + */ + +#ifndef __ASM_MACH_LOONGSON1_PBL_LL_INIT_LOONGSON1_H +#define __ASM_MACH_LOONGSON1_PBL_LL_INIT_LOONGSON1_H + +#include <asm/addrspace.h> +#include <asm/regdef.h> + +.macro __pbl_loongson1_ddr2_init + .set push + .set noreorder + + pbl_reg_writel 0x00000101, 0xAFFFFE00 + pbl_reg_writel 0x01000100, 0xAFFFFE04 + pbl_reg_writel 0x00000000, 0xAFFFFE10 + pbl_reg_writel 0x01000000, 0xAFFFFE14 + pbl_reg_writel 0x00000000, 0xAFFFFE20 + pbl_reg_writel 0x01000101, 0xAFFFFE24 + pbl_reg_writel 0x01000100, 0xAFFFFE30 + pbl_reg_writel 0x01010000, 0xAFFFFE34 + pbl_reg_writel 0x01010101, 0xAFFFFE40 + pbl_reg_writel 0x01000202, 0xAFFFFE44 + pbl_reg_writel 0x04030201, 0xAFFFFE50 + pbl_reg_writel 0x07000000, 0xAFFFFE54 + pbl_reg_writel 0x02020203, 0xAFFFFE60 + pbl_reg_writel 0x0a020203, 0xAFFFFE64 + pbl_reg_writel 0x00010506, 0xAFFFFE70 + pbl_reg_writel 0x00000400, 0xAFFFFE74 + pbl_reg_writel 0x08040201, 0xAFFFFE80 + pbl_reg_writel 0x08040201, 0xAFFFFE84 + pbl_reg_writel 0x00000000, 0xAFFFFE90 + pbl_reg_writel 0x00000306, 0xAFFFFE94 + pbl_reg_writel 0x3f0b020a, 0xAFFFFEA0 + pbl_reg_writel 0x0000003f, 0xAFFFFEA4 + pbl_reg_writel 0x00000000, 0xAFFFFEB0 + pbl_reg_writel 0x37570000, 0xAFFFFEB4 + pbl_reg_writel 0x08000000, 0xAFFFFEC0 + pbl_reg_writel 0x002a1503, 0xAFFFFEC4 + pbl_reg_writel 0x002a002a, 0xAFFFFED0 + pbl_reg_writel 0x002a002a, 0xAFFFFED4 + pbl_reg_writel 0x002a002a, 0xAFFFFEE0 + pbl_reg_writel 0x002a002a, 0xAFFFFEE4 + pbl_reg_writel 0x00000002, 0xAFFFFEF0 + pbl_reg_writel 0x00b40020, 0xAFFFFEF4 + pbl_reg_writel 0x00000087, 0xAFFFFF00 + pbl_reg_writel 0x000007ff, 0xAFFFFF04 + pbl_reg_writel 0x44240618, 0xAFFFFF10 + pbl_reg_writel 0x80808080, 0xAFFFFF14 + pbl_reg_writel 0x80808080, 0xAFFFFF20 + pbl_reg_writel 0x001c8080, 0xAFFFFF24 + pbl_reg_writel 0x00c8006b, 0xAFFFFF30 + pbl_reg_writel 0x36b00002, 0xAFFFFF34 + pbl_reg_writel 0x00c80017, 0xAFFFFF40 + pbl_reg_writel 0x00000000, 0xAFFFFF44 + pbl_reg_writel 0x00009c40, 0xAFFFFF50 + pbl_reg_writel 0x00000000, 0xAFFFFF54 + pbl_reg_writel 0x00000000, 0xAFFFFF60 + pbl_reg_writel 0x00000000, 0xAFFFFF64 + pbl_reg_writel 0x00000000, 0xAFFFFF70 + pbl_reg_writel 0x00000000, 0xAFFFFF74 + pbl_reg_writel 0x00000000, 0xAFFFFF80 + pbl_reg_writel 0x00000000, 0xAFFFFF84 + pbl_reg_writel 0x00000000, 0xAFFFFF90 + pbl_reg_writel 0x00000000, 0xAFFFFF94 + pbl_reg_writel 0x00000000, 0xAFFFFFA0 + pbl_reg_writel 0x00000000, 0xAFFFFFA4 + pbl_reg_writel 0x00000000, 0xAFFFFFB0 + pbl_reg_writel 0x00000000, 0xAFFFFFB4 + pbl_reg_writel 0x00000000, 0xAFFFFFC0 + pbl_reg_writel 0x00000000, 0xAFFFFFC4 + + .set pop +.endm + +.macro pbl_loongson1_ddr2_init + .set push + .set noreorder + + /* initial ddr2 controller */ + pbl_reg_writel 0xfc000000, 0xbfd010c8 + pbl_reg_writel 0x14000000, 0xbfd010f8 + + __pbl_loongson1_ddr2_init +10: + pbl_reg_writel 0x01010100, 0xaffffe34 + +9: + li t0, 0xaffffe00 + lw t1, 0x10 (t0) + andi t1, t1, 1 + beqz t1, 9b + nop + + lh t1, 0xf2 (t0) + sltiu t1, t1, 5 + beqz t1, 1f + nop + + lw t1, 0xf4 (t0) + addiu t1, t1, 4 + sw t1, 0xf4 (t0) + b 10b + nop +1: + /* 16bit ddr and disable conf */ + pbl_reg_set 0x110000, 0xbfd00424 + .set pop +.endm + +#endif /* __ASM_MACH_LOONGSON1_PBL_LL_INIT_LOONGSON1_H */ diff --git a/arch/mips/mach-loongson/include/mach/pbl_macros.h b/arch/mips/mach-loongson/include/mach/pbl_macros.h new file mode 100644 index 0000000000..93402d1c54 --- /dev/null +++ b/arch/mips/mach-loongson/include/mach/pbl_macros.h @@ -0,0 +1,81 @@ +#ifndef __ASM_MACH_LOONGSON1_PBL_MACROS_H +#define __ASM_MACH_LOONGSON1_PBL_MACROS_H + +#include <asm/addrspace.h> +#include <asm/regdef.h> +#include <mach/loongson1.h> + +#define PLL_FREQ 0xBFE78030 +#define PLL_DIV_PARAM 0xBFE78034 + +#define CONFIG_CPU_DIV 3 +#define CONFIG_DDR_DIV 4 +#define CONFIG_DC_DIV 4 +#define CONFIG_PLL_FREQ 0x1C +#define CONFIG_PLL_DIV_PARAM 0x92392a00 + +.macro pbl_loongson1_pll + .set push + .set noreorder + + pbl_reg_writel 0x92392a00, PLL_DIV_PARAM + pbl_reg_writel 0x0000001c, PLL_FREQ + pbl_sleep t8, 40 + + .set pop +.endm + +.macro set_cpu_window id, base, mask, mmap + .set push + .set noreorder + + li t8, 0xbfd00000 + sw $0, 0x80 + \id * 8 (t8) + li t9, \base + sw t9, 0x00 + \id * 8 (t8) + sw $0, 0x04 + \id * 8 (t8) + li t9, \mask + sw t9, 0x40 + \id * 8 (t8) + sw $0, 0x44 + \id * 8 (t8) + li t9, \mmap + sw t9, 0x80 + \id * 8 (t8) + sw $0, 0x84 + \id * 8 (t8) + + .set pop +.endm + +.macro pbl_loongson1_remap + .set push + + set_cpu_window 0, 0x1c300000, 0xfff00000, 0x1c3000d2 + set_cpu_window 1, 0x1fe10000, 0xffffe000, 0x1fe100d3 + set_cpu_window 2, 0x1fe20000, 0xffffe000, 0x1fe200d3 + set_cpu_window 3, 0x1fe10000, 0xffff0000, 0x1fe100d0 + set_cpu_window 4, 0x1fe20000, 0xffff0000, 0x1fe200d0 + set_cpu_window 5, 0x1ff00000, 0xfff00000, 0x1ff000d0 + set_cpu_window 6, 0x1f000000, 0xff000000, 0x1f0000d3 + set_cpu_window 7, 0x00000000, 0x00000000, 0x000000f0 + li t8, 0xbfd000e0 + lw t9, 0x0 (t8) + and t9, t9, 0xffffff00 + ori t9, t9, 0xd0 + sw t9, 0x0 (t8) + + lw t9, 0x8 (t8) + and t9, t9, 0xffffff00 + ori t9, t9, 0xd0 + sw t9, 0x8 (t8) + + .set pop +.endm + +#define GPIOCFG1 0xbfd010C4 +.macro pbl_loongson1_uart_enable + .set push + + pbl_reg_clr 0x00C00000, GPIOCFG1 + + .set pop +.endm + +#endif /* __ASM_MACH_LOONGSON1_PBL_MACROS_H */ diff --git a/arch/openrisc/lib/dtb.c b/arch/openrisc/lib/dtb.c index 2dd8e4e014..61cf35ddf3 100644 --- a/arch/openrisc/lib/dtb.c +++ b/arch/openrisc/lib/dtb.c @@ -28,13 +28,7 @@ static int of_openrisc_init(void) if (root) return 0; - root = of_unflatten_dtb(__dtb_start); - if (!IS_ERR(root)) { - pr_debug("using internal DTB\n"); - of_set_root_node(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); - } + barebox_register_fdt(__dtb_start); return 0; } diff --git a/arch/riscv/boot/dtb.c b/arch/riscv/boot/dtb.c index 5d73413a43..b9b68fc7f2 100644 --- a/arch/riscv/boot/dtb.c +++ b/arch/riscv/boot/dtb.c @@ -18,19 +18,7 @@ extern char __dtb_start[]; static int of_riscv_init(void) { - struct device_node *root; - - root = of_get_root_node(); - if (root) - return 0; - - root = of_unflatten_dtb(__dtb_start); - if (!IS_ERR(root)) { - pr_debug("using internal DTB\n"); - of_set_root_node(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); - } + barebox_register_fdt(__dtb_start); return 0; } diff --git a/arch/riscv/include/asm/debug_ll_ns16550.h b/arch/riscv/include/asm/debug_ll_ns16550.h index e891cbda25..f1c2ccbd0a 100644 --- a/arch/riscv/include/asm/debug_ll_ns16550.h +++ b/arch/riscv/include/asm/debug_ll_ns16550.h @@ -88,14 +88,14 @@ static inline void debug_ll_ns16550_init(void) * Macros for use in assembly language code */ -.macro debug_ll_ns16550_init +.macro debug_ll_ns16550_init divisor=DEBUG_LL_UART_DIVISOR #ifdef CONFIG_DEBUG_LL li t0, DEBUG_LL_UART_ADDR li t1, UART_LCR_DLAB /* DLAB on */ UART_REG_S t1, UART_LCR(t0) /* Write it out */ - li t1, DEBUG_LL_UART_DIVISOR + li t1, \divisor UART_REG_S t1, UART_DLL(t0) /* write low order byte */ srl t1, t1, 8 UART_REG_S t1, UART_DLM(t0) /* write high order byte */ diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index bced81f25e..113b619fc3 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -10,6 +10,7 @@ config SANDBOX select BLOCK select BLOCK_WRITE select PARTITION_DISK + select ARCH_HAS_STACK_DUMP if ASAN default y config ARCH_TEXT_BASE @@ -21,12 +22,6 @@ config LINUX default y select GENERIC_FIND_NEXT_BIT -config SANDBOX_UNWIND - bool - default y - select ARCH_HAS_STACK_DUMP - depends on UBSAN || ASAN - config SANDBOX_REEXEC prompt "exec(2) reset handler" def_bool y diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile index 09112c3ba8..17f9a298d7 100644 --- a/arch/sandbox/Makefile +++ b/arch/sandbox/Makefile @@ -24,6 +24,7 @@ KBUILD_CFLAGS += -Dmalloc=barebox_malloc -Dcalloc=barebox_calloc \ -Dgetenv=barebox_getenv -Dprintf=barebox_printf \ -Dglob=barebox_glob -Dglobfree=barebox_globfree \ -Dioctl=barebox_ioctl -Dfstat=barebox_fstat \ + -Dftruncate=barebox_ftruncate -Dasprintf=barebox_asprintf \ -Dopendir=barebox_opendir -Dreaddir=barebox_readdir \ -Dclosedir=barebox_closedir -Dreadlink=barebox_readlink \ -Doptarg=barebox_optarg -Doptind=barebox_optind diff --git a/arch/sandbox/board/Makefile b/arch/sandbox/board/Makefile index 26f6cb1922..c504c967de 100644 --- a/arch/sandbox/board/Makefile +++ b/arch/sandbox/board/Makefile @@ -4,7 +4,8 @@ obj-y += hostfile.o obj-y += console.o obj-y += devices.o obj-y += dtb.o -obj-y += poweroff.o +obj-y += power.o obj-y += dev-random.o +obj-y += watchdog.o extra-y += barebox.lds diff --git a/arch/sandbox/board/devices.c b/arch/sandbox/board/devices.c index 72e62552a3..26152a8b90 100644 --- a/arch/sandbox/board/devices.c +++ b/arch/sandbox/board/devices.c @@ -9,6 +9,9 @@ #include <mach/linux.h> #include <init.h> #include <mach/linux.h> +#include <asm/io.h> + +unsigned char __pci_iobase[IO_SPACE_LIMIT]; static LIST_HEAD(sandbox_device_list); @@ -23,9 +26,6 @@ static int sandbox_device_init(void) { struct device_d *dev, *tmp; - barebox_set_model("barebox sandbox"); - barebox_set_hostname("barebox"); - list_for_each_entry_safe(dev, tmp, &sandbox_device_list, list) { /* reset the list_head before registering for real */ dev->list.prev = NULL; diff --git a/arch/sandbox/board/dtb.c b/arch/sandbox/board/dtb.c index d11bde0249..4a8cbfb26f 100644 --- a/arch/sandbox/board/dtb.c +++ b/arch/sandbox/board/dtb.c @@ -32,32 +32,14 @@ int barebox_register_dtb(const void *new_dtb) return 0; } +extern char __dtb_sandbox_start[]; + static int of_sandbox_init(void) { - struct device_node *root; - int ret; - - if (dtb) { - root = of_unflatten_dtb(dtb); - } else { - root = of_new_node(NULL, NULL); - - ret = of_property_write_u32(root, "#address-cells", 2); - if (ret) - return ret; - - ret = of_property_write_u32(root, "#size-cells", 2); - if (ret) - return ret; - } - - if (IS_ERR(root)) - return PTR_ERR(root); + if (!dtb) + dtb = __dtb_sandbox_start; - of_set_root_node(root); - of_fix_tree(root); - if (IS_ENABLED(CONFIG_OFDEVICE)) - of_probe(); + barebox_register_fdt(dtb); return 0; } diff --git a/arch/sandbox/board/env/init/state b/arch/sandbox/board/env/init/state new file mode 100644 index 0000000000..0b8e40409f --- /dev/null +++ b/arch/sandbox/board/env/init/state @@ -0,0 +1,12 @@ +if [ "x$state.dirty" != "x1" -o $global.system.reset != "POR" ]; then + exit +fi + +source /env/data/ansi-colors + +echo -e $CYAN +echo "******************************************************************" +echo "*** Inconsistent barebox state buckets detected on first boot ***" +echo "*** barebox will repair them on next shutdown ***" +echo "*****************************************************************" +echo -e -n $NC diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c index 63530bd25e..e3e38b7119 100644 --- a/arch/sandbox/board/hostfile.c +++ b/arch/sandbox/board/hostfile.c @@ -124,9 +124,6 @@ static int hf_probe(struct device_d *dev) if (err) return err; - if (!priv->fd) - priv->fd = linux_open(priv->filename, true); - if (priv->fd < 0) return priv->fd; @@ -194,37 +191,98 @@ static int of_hostfile_fixup(struct device_node *root, void *ctx) { struct hf_info *hf = ctx; struct device_node *node; - uint32_t reg[] = { - hf->base >> 32, - hf->base, - hf->size >> 32, - hf->size - }; + bool name_only = false; int ret; - node = of_new_node(root, hf->devname); + node = of_get_child_by_name(root, hf->devname); + if (node) + name_only = true; + else + node = of_new_node(root, hf->devname); - ret = of_property_write_string(node, "compatible", hostfile_dt_ids->compatible); + ret = of_property_write_string(node, "barebox,filename", hf->filename); if (ret) return ret; - ret = of_property_write_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); + if (name_only) + return 0; + + ret = of_property_write_string(node, "compatible", hostfile_dt_ids->compatible); if (ret) return ret; - ret = of_property_write_u32(node, "barebox,fd", hf->fd); + ret = of_property_write_bool(node, "barebox,blockdev", hf->is_blockdev); if (ret) return ret; - ret = of_property_write_string(node, "barebox,filename", hf->filename); - - if (hf->is_blockdev) - ret = of_property_write_bool(node, "barebox,blockdev", true); + ret = of_property_write_bool(node, "barebox,cdev", hf->is_cdev); + if (ret) + return ret; - return ret; + return of_property_write_bool(node, "barebox,read-only", hf->is_readonly); } int barebox_register_filedev(struct hf_info *hf) { return of_register_fixup(of_hostfile_fixup, hf); } + +static int of_hostfile_map_fixup(struct device_node *root, void *ctx) +{ + struct device_node *node; + int ret; + + for_each_compatible_node_from(node, root, NULL, hostfile_dt_ids->compatible) { + struct hf_info hf = {}; + uint64_t reg[2] = {}; + bool no_filename; + + hf.devname = node->name; + + ret = of_property_read_string(node, "barebox,filename", &hf.filename); + no_filename = ret; + + hf.is_blockdev = of_property_read_bool(node, "barebox,blockdev"); + hf.is_cdev = of_property_read_bool(node, "barebox,cdev"); + hf.is_readonly = of_property_read_bool(node, "barebox,read-only"); + + of_property_read_u64_array(node, "reg", reg, ARRAY_SIZE(reg)); + + hf.base = reg[0]; + hf.size = reg[1]; + + ret = linux_open_hostfile(&hf); + if (ret) + goto out; + + reg[0] = hf.base; + reg[1] = hf.size; + + ret = of_property_write_u64_array(node, "reg", reg, ARRAY_SIZE(reg)); + if (ret) + goto out; + + ret = of_property_write_bool(node, "barebox,blockdev", hf.is_blockdev); + if (ret) + goto out; + + if (no_filename) { + ret = of_property_write_string(node, "barebox,filename", hf.filename); + if (ret) + goto out; + } + + ret = of_property_write_u32(node, "barebox,fd", hf.fd); +out: + if (ret) + pr_err("error fixing up %s: %pe\n", hf.devname, ERR_PTR(ret)); + } + + return 0; +} + +static int barebox_fixup_filedevs(void) +{ + return of_register_fixup(of_hostfile_map_fixup, NULL); +} +pure_initcall(barebox_fixup_filedevs); diff --git a/arch/sandbox/board/power.c b/arch/sandbox/board/power.c new file mode 100644 index 0000000000..3cc9447958 --- /dev/null +++ b/arch/sandbox/board/power.c @@ -0,0 +1,82 @@ +#include <common.h> +#include <driver.h> +#include <poweroff.h> +#include <restart.h> +#include <mach/linux.h> +#include <reset_source.h> +#include <mfd/syscon.h> + +struct sandbox_power { + struct restart_handler rst_hang, rst_reexec; + struct regmap *src; + u32 src_offset; +}; + +static void sandbox_poweroff(struct poweroff_handler *poweroff) +{ + linux_exit(); +} + +static void sandbox_rst_hang(struct restart_handler *rst) +{ + linux_hang(); +} + +static void sandbox_rst_reexec(struct restart_handler *rst) +{ + struct sandbox_power *power = container_of(rst, struct sandbox_power, rst_reexec); + regmap_update_bits(power->src, power->src_offset, 0xff, RESET_RST); + linux_reexec(); +} + +static int sandbox_power_probe(struct device_d *dev) +{ + struct sandbox_power *power = xzalloc(sizeof(*power)); + unsigned int rst; + int ret; + + poweroff_handler_register_fn(sandbox_poweroff); + + power->rst_hang = (struct restart_handler) { + .name = "hang", + .restart = sandbox_rst_hang + }; + + power->rst_reexec = (struct restart_handler) { + .name = "reexec", .priority = 200, + .restart = sandbox_rst_reexec, + }; + + restart_handler_register(&power->rst_hang); + + if (IS_ENABLED(CONFIG_SANDBOX_REEXEC)) + restart_handler_register(&power->rst_reexec); + + power->src = syscon_regmap_lookup_by_phandle(dev->device_node, "barebox,reset-source"); + if (IS_ERR(power->src)) + return 0; + + ret = of_property_read_u32_index(dev->device_node, "barebox,reset-source", 1, + &power->src_offset); + if (ret) + return 0; + + ret = regmap_read(power->src, power->src_offset, &rst); + if (ret == 0 && rst == 0) + rst = RESET_POR; + + reset_source_set_prinst(rst, RESET_SOURCE_DEFAULT_PRIORITY, 0); + return 0; +} + +static __maybe_unused struct of_device_id sandbox_power_dt_ids[] = { + { .compatible = "barebox,sandbox-power" }, + { /* sentinel */ } +}; + +static struct driver_d sandbox_power_drv = { + .name = "sandbox-power", + .of_compatible = sandbox_power_dt_ids, + .probe = sandbox_power_probe, +}; +coredevice_platform_driver(sandbox_power_drv); diff --git a/arch/sandbox/board/poweroff.c b/arch/sandbox/board/poweroff.c deleted file mode 100644 index 8ce739af72..0000000000 --- a/arch/sandbox/board/poweroff.c +++ /dev/null @@ -1,42 +0,0 @@ -#include <common.h> -#include <init.h> -#include <poweroff.h> -#include <restart.h> -#include <mach/linux.h> - -static void sandbox_poweroff(struct poweroff_handler *poweroff) -{ - linux_exit(); -} - -static void sandbox_rst_hang(struct restart_handler *rst) -{ - linux_hang(); -} - -static struct restart_handler rst_hang = { - .name = "hang", - .restart = sandbox_rst_hang -}; - -static void sandbox_rst_reexec(struct restart_handler *rst) -{ - linux_reexec(); -} - -static struct restart_handler rst_reexec = { - .name = "reexec", .priority = 200, - .restart = sandbox_rst_reexec, -}; - -static int poweroff_register_feature(void) -{ - poweroff_handler_register_fn(sandbox_poweroff); - restart_handler_register(&rst_hang); - - if (IS_ENABLED(CONFIG_SANDBOX_REEXEC)) - restart_handler_register(&rst_reexec); - - return 0; -} -coredevice_initcall(poweroff_register_feature); diff --git a/arch/sandbox/board/watchdog.c b/arch/sandbox/board/watchdog.c new file mode 100644 index 0000000000..336451282f --- /dev/null +++ b/arch/sandbox/board/watchdog.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <errno.h> +#include <driver.h> +#include <mach/linux.h> +#include <of.h> +#include <watchdog.h> +#include <mfd/syscon.h> +#include <reset_source.h> + +struct sandbox_watchdog { + struct watchdog wdd; + bool cant_disable :1; +}; + +static inline struct sandbox_watchdog *to_sandbox_watchdog(struct watchdog *wdd) +{ + return container_of(wdd, struct sandbox_watchdog, wdd); +} + +static int sandbox_watchdog_set_timeout(struct watchdog *wdd, unsigned int timeout) +{ + struct sandbox_watchdog *wd = to_sandbox_watchdog(wdd); + + if (!timeout && wd->cant_disable) + return -ENOSYS; + + if (timeout > wdd->timeout_max) + return -EINVAL; + + return linux_watchdog_set_timeout(timeout); +} + +static int sandbox_watchdog_probe(struct device_d *dev) +{ + struct device_node *np = dev->device_node; + struct sandbox_watchdog *wd; + struct watchdog *wdd; + struct regmap *src; + u32 src_offset; + int ret; + + wd = xzalloc(sizeof(*wd)); + + wdd = &wd->wdd; + wdd->hwdev = dev; + wdd->set_timeout = sandbox_watchdog_set_timeout; + wdd->timeout_max = 1000; + + wd->cant_disable = of_property_read_bool(np, "barebox,cant-disable"); + + ret = watchdog_register(wdd); + if (ret) { + dev_err(dev, "Failed to register watchdog device\n"); + return ret; + } + + src = syscon_regmap_lookup_by_phandle(np, "barebox,reset-source"); + if (IS_ERR(src)) + return 0; + + ret = of_property_read_u32_index(np, "barebox,reset-source", 1, &src_offset); + if (ret) + return 0; + + regmap_update_bits(src, src_offset, 0xff, RESET_WDG); + + dev_info(dev, "probed\n"); + return 0; +} + + +static __maybe_unused struct of_device_id sandbox_watchdog_dt_ids[] = { + { .compatible = "barebox,sandbox-watchdog" }, + { /* sentinel */ } +}; + +static struct driver_d sandbox_watchdog_drv = { + .name = "sandbox-watchdog", + .of_compatible = sandbox_watchdog_dt_ids, + .probe = sandbox_watchdog_probe, +}; +device_platform_driver(sandbox_watchdog_drv); diff --git a/arch/sandbox/configs/hosttools_defconfig b/arch/sandbox/configs/hosttools_defconfig index 72ec0fc462..7d33853124 100644 --- a/arch/sandbox/configs/hosttools_defconfig +++ b/arch/sandbox/configs/hosttools_defconfig @@ -2,6 +2,5 @@ CONFIG_IMD=y CONFIG_COMPILE_HOST_TOOLS=y CONFIG_ARCH_IMX_USBLOADER=y CONFIG_MVEBU_HOSTTOOLS=y -CONFIG_MXS_HOSTTOOLS=y CONFIG_OMAP3_USB_LOADER=y CONFIG_OMAP4_HOSTTOOL_USBBOOT=y diff --git a/arch/sandbox/configs/sandbox_defconfig b/arch/sandbox/configs/sandbox_defconfig index c343f053fa..ca24d81aca 100644 --- a/arch/sandbox/configs/sandbox_defconfig +++ b/arch/sandbox/configs/sandbox_defconfig @@ -2,20 +2,34 @@ CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y +CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_PARTITION=y +CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_COMPRESSION_GZIP=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_REBOOT_MODE=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/sandbox/board/env" +CONFIG_STATE=y +CONFIG_STATE_CRYPTO=y +CONFIG_RESET_SOURCE=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y CONFIG_CMD_IMD=y CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_BOOTM is not set +CONFIG_CMD_POLLER=y +CONFIG_CMD_SLICE=y CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_SAVES=y CONFIG_CMD_UIMAGE=y CONFIG_CMD_PARTITION=y CONFIG_CMD_EXPORT=y CONFIG_CMD_DEFAULTENV=y +CONFIG_CMD_LOADENV=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y @@ -39,14 +53,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_EDIT=y +CONFIG_CMD_LOGIN=y CONFIG_CMD_MENU=y CONFIG_CMD_MENU_MANAGEMENT=y CONFIG_CMD_MENUTREE=y +CONFIG_CMD_PASSWD=y CONFIG_CMD_SPLASH=y +CONFIG_CMD_FBTEST=y CONFIG_CMD_READLINE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_CRC=y CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MM=y CONFIG_CMD_DETECT=y CONFIG_CMD_FLASH=y @@ -56,18 +74,31 @@ CONFIG_CMD_LED=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_WD=y CONFIG_CMD_2048=y +CONFIG_CMD_KEYSTORE=y +CONFIG_CMD_LINUX_EXEC=y +CONFIG_CMD_OF_DIFF=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OF_DISPLAY_TIMINGS=y +CONFIG_CMD_OF_FIXUP_STATUS=y +CONFIG_CMD_OF_OVERLAY=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y +CONFIG_CMD_STATE=y +CONFIG_CMD_DHRYSTONE=y CONFIG_CMD_SPD_DECODE=y +CONFIG_CMD_SEED=y CONFIG_NET=y CONFIG_NET_NFS=y CONFIG_NET_NETCONSOLE=y +CONFIG_NET_SNTP=y +CONFIG_NET_FASTBOOT=y CONFIG_OFDEVICE=y CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_OF_BAREBOX_ENV_IN_FS=y +CONFIG_OF_OVERLAY_LIVE=y CONFIG_DRIVER_NET_TAP=y CONFIG_DRIVER_SPI_GPIO=y CONFIG_I2C=y @@ -76,6 +107,9 @@ CONFIG_MTD=y CONFIG_MTD_M25P80=y CONFIG_VIDEO=y CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_MFD_SYSCON=y +CONFIG_STATE_DRV=y +CONFIG_UBOOTVAR=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_GPIO_OF=y @@ -84,9 +118,12 @@ CONFIG_LED_GPIO_BICOLOR=y CONFIG_LED_TRIGGERS=y CONFIG_EEPROM_AT25=y CONFIG_EEPROM_AT24=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_POLLER=y # CONFIG_PINCTRL is not set CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y +CONFIG_SYSCON_REBOOT_MODE=y CONFIG_FS_CRAMFS=y CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y @@ -94,12 +131,17 @@ CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y +CONFIG_FS_JFFS2=y CONFIG_FS_BPKFS=y CONFIG_FS_UIMAGEFS=y +CONFIG_FS_PSTORE=y +CONFIG_FS_PSTORE_CONSOLE=y CONFIG_FS_SQUASHFS=y +CONFIG_FS_UBOOTVARFS=y CONFIG_BZLIB=y CONFIG_LZ4_DECOMPRESS=y CONFIG_XZ_DECOMPRESS=y +CONFIG_BASE64=y CONFIG_LZO_DECOMPRESS=y CONFIG_BMP=y CONFIG_PNG=y @@ -112,4 +154,3 @@ CONFIG_BAREBOX_LOGO_240=y CONFIG_BAREBOX_LOGO_320=y CONFIG_BAREBOX_LOGO_400=y CONFIG_BAREBOX_LOGO_640=y -CONFIG_DIGEST_HMAC_GENERIC=y diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index 6f4344da68..c8d83141ce 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -1,5 +1,5 @@ -always-$(CONFIG_OFTREE) += \ - sandbox.dtb +obj-$(CONFIG_OFTREE) += \ + sandbox.dtb.o # just to build a built-in.o. Otherwise compilation fails when no devicetree is # created. diff --git a/arch/sandbox/dts/sandbox-state-example.dtsi b/arch/sandbox/dts/sandbox-state-example.dtsi deleted file mode 100644 index 98640f6677..0000000000 --- a/arch/sandbox/dts/sandbox-state-example.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -/ { - aliases { - state = &state; - }; - - disk { - compatible = "barebox,hostfile"; - barebox,filename = "disk"; - reg = <0x0 0x0 0x0 0x100000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - hostfile_state: state@0 { - reg = <0x0 0x1000>; - label = "state"; - }; - }; - }; - - state: state { - magic = <0xaa3b86a6>; - compatible = "barebox,state"; - backend-type = "raw"; - backend = <&hostfile_state>; - backend-storage-type = "direct"; - backend-stridesize = <64>; - - #address-cells = <1>; - #size-cells = <1>; - vars { - #address-cells = <1>; - #size-cells = <1>; - - x { - reg = <0x0 0x4>; - type = "uint32"; - default = <1>; - }; - - y { - reg = <0x4 0x4>; - type = "uint32"; - default = <3>; - }; - }; - }; -}; diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 2595aa13fa..afe48154c4 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -1,7 +1,97 @@ /dts-v1/; -#include "skeleton.dtsi" - / { + model = "Sandbox"; + compatible = "barebox,sandbox"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + bmode = &bmode; + state = &state; + }; + + chosen { + environment { + compatible = "barebox,environment"; + device-path = &part_env; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0 0>; + }; + + state: state { + magic = <0xaa3b86a6>; + compatible = "barebox,state"; + backend-type = "raw"; + backend = <&part_state>; + backend-storage-type = "direct"; + backend-stridesize = <64>; + + #address-cells = <1>; + #size-cells = <1>; + + vars { + #address-cells = <1>; + #size-cells = <1>; + + x { + reg = <0x0 0x4>; + type = "uint32"; + default = <1>; + }; + + y { + reg = <0x4 0x4>; + type = "uint32"; + default = <3>; + }; + }; + }; + + stickypage: stickypage { + compatible = "barebox,hostfile", "syscon", "simple-mfd"; + reg = <0 0 0 4096>; + barebox,cdev; /* no caching allowed */ + + bmode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0>; + mask = <0xffffff00>; + mode-normal = <0x00000000>; + mode-loader = <0xbbbbbb00>; + }; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 0x00+4 reserved for syscon use */ + + part_env: env@400 { + reg = <0x400 0x800>; + label = "env"; + }; + + part_state: state@800 { + reg = <0xC00 0x400>; + label = "state"; + }; + }; + }; + + power { + compatible = "barebox,sandbox-power"; + barebox,reset-source = <&stickypage 0>; + }; + watchdog { + compatible = "barebox,sandbox-watchdog"; + barebox,reset-source = <&stickypage 0>; + }; }; diff --git a/arch/sandbox/dts/skeleton.dtsi b/arch/sandbox/dts/skeleton.dtsi deleted file mode 100644 index 8ba7663eb5..0000000000 --- a/arch/sandbox/dts/skeleton.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Skeleton device tree; the bare minimum needed to boot; just include and - * add a compatible value. The bootloader will typically populate the memory - * node. - */ - -/ { - #address-cells = <2>; - #size-cells = <2>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0 0 0>; }; -}; diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 6a0e77aead..9f9cd3a42a 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -1,7 +1,11 @@ #ifndef __ASM_SANDBOX_IO_H #define __ASM_SANDBOX_IO_H -#define IO_SPACE_LIMIT 0 +#define IO_SPACE_LIMIT 0xffff +/* pacify static analyzers */ +#define PCI_IOBASE ((void __iomem *)__pci_iobase) + +extern unsigned char __pci_iobase[IO_SPACE_LIMIT]; #include <asm-generic/io.h> #include <asm-generic/bitio.h> diff --git a/arch/sandbox/mach-sandbox/include/mach/hostfile.h b/arch/sandbox/mach-sandbox/include/mach/hostfile.h index c3f9af97c4..3ef34bcc1c 100644 --- a/arch/sandbox/mach-sandbox/include/mach/hostfile.h +++ b/arch/sandbox/mach-sandbox/include/mach/hostfile.h @@ -8,6 +8,8 @@ struct hf_info { const char *devname; const char *filename; unsigned int is_blockdev:1; + unsigned int is_cdev:1; + unsigned int is_readonly:1; }; int barebox_register_filedev(struct hf_info *hf); diff --git a/arch/sandbox/mach-sandbox/include/mach/linux.h b/arch/sandbox/mach-sandbox/include/mach/linux.h index 1ab48e52a0..b26bfc24a2 100644 --- a/arch/sandbox/mach-sandbox/include/mach/linux.h +++ b/arch/sandbox/mach-sandbox/include/mach/linux.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARCH_LINUX_H #define __ASM_ARCH_LINUX_H +struct hf_info; + struct device_d; int sandbox_add_device(struct device_d *dev); @@ -11,6 +13,7 @@ int linux_register_device(const char *name, void *start, void *end); int tap_alloc(const char *dev); uint64_t linux_get_time(void); int linux_open(const char *filename, int readwrite); +int linux_open_hostfile(struct hf_info *hf); int linux_read(int fd, void *buf, size_t count); int linux_read_nonblock(int fd, void *buf, size_t count); ssize_t linux_write(int fd, const void *buf, size_t count); @@ -22,6 +25,8 @@ void linux_reexec(void); int linux_execve(const char * filename, char *const argv[], char *const envp[]); +int linux_watchdog_set_timeout(unsigned int timeout); + int barebox_register_console(int stdinfd, int stdoutfd); int barebox_register_dtb(const void *dtb); diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c index 43ee95edb6..da87be29c7 100644 --- a/arch/sandbox/os/common.c +++ b/arch/sandbox/os/common.c @@ -19,6 +19,7 @@ * These are host includes. Never include any barebox header * files here... */ +#define _GNU_SOURCE #include <stdio.h> #include <stdlib.h> #include <stdint.h> @@ -38,6 +39,8 @@ #include <sys/wait.h> #include <sys/ioctl.h> #include <linux/fs.h> +#include <sys/time.h> +#include <signal.h> /* * ...except the ones needed to connect with barebox */ @@ -124,6 +127,7 @@ void __attribute__((noreturn)) linux_exit(void) exit(0); } +static size_t saved_argv_len; static char **saved_argv; void linux_reexec(void) @@ -242,6 +246,29 @@ int linux_execve(const char * filename, char *const argv[], char *const envp[]) } } +static void linux_watchdog(int signo) +{ + linux_reexec(); + _exit(0); +} + +int linux_watchdog_set_timeout(unsigned int timeout) +{ + static int signal_handler_installed; + + if (!signal_handler_installed) { + struct sigaction sact = { + .sa_flags = SA_NODEFER, .sa_handler = linux_watchdog + }; + + sigemptyset(&sact.sa_mask); + sigaction(SIGALRM, &sact, NULL); + signal_handler_installed = 1; + } + + return alarm(timeout); +} + extern void start_barebox(void); extern void mem_malloc_init(void *start, void *end); @@ -252,10 +279,8 @@ static int add_image(const char *_str, char *devname_template, int *devname_numb struct hf_info *hf = malloc(sizeof(struct hf_info)); char *str, *filename, *devname; char tmp[16]; - int readonly = 0, cdev = 0, blkdev = 0; - struct stat s; char *opt; - int fd, ret; + int ret; if (!hf) return -1; @@ -265,11 +290,11 @@ static int add_image(const char *_str, char *devname_template, int *devname_numb filename = strsep_unescaped(&str, ","); while ((opt = strsep_unescaped(&str, ","))) { if (!strcmp(opt, "ro")) - readonly = 1; + hf->is_readonly = 1; if (!strcmp(opt, "cdev")) - cdev = 1; + hf->is_cdev = 1; if (!strcmp(opt, "blkdev")) - blkdev = 1; + hf->is_blockdev = 1; } /* parses: "devname=filename" */ @@ -282,13 +307,64 @@ static int add_image(const char *_str, char *devname_template, int *devname_numb devname = tmp; } - printf("add %s backed by file %s%s\n", devname, - filename, readonly ? "(ro)" : ""); - - fd = open(filename, (readonly ? O_RDONLY : O_RDWR) | O_CLOEXEC); - hf->fd = fd; hf->filename = filename; - hf->is_blockdev = blkdev; + hf->devname = strdup(devname); + + ret = barebox_register_filedev(hf); + if (ret) + free(hf); + + return ret; +} + +int linux_open_hostfile(struct hf_info *hf) +{ + char *buf = NULL; + struct stat s; + int fd; + + printf("add %s %sbacked by file %s%s\n", hf->devname, + hf->filename ? "" : "initially un", hf->filename ?: "", + hf->is_readonly ? "(ro)" : ""); + + if (hf->filename) { + fd = hf->fd = open(hf->filename, (hf->is_readonly ? O_RDONLY : O_RDWR) | O_CLOEXEC); + } else { + char *filename; + int ret; + + ret = asprintf(&buf, "--image=%s=/tmp/barebox-hostfileXXXXXX", hf->devname); + if (ret < 0) { + perror("asprintf"); + goto err_out; + } + + filename = buf + strlen("--image==") + strlen(hf->devname); + + fd = hf->fd = mkstemp(filename); + if (fd >= 0) { + ret = fcntl(fd, F_SETFD, FD_CLOEXEC); + if (ret < 0) { + perror("fcntl"); + goto err_out; + } + + ret = ftruncate(fd, hf->size); + if (ret < 0) { + perror("ftruncate"); + goto err_out; + } + + hf->filename = filename; + + saved_argv = realloc(saved_argv, + ++saved_argv_len * sizeof(*saved_argv)); + if (!saved_argv) + exit(1); + saved_argv[saved_argv_len - 2] = buf; + saved_argv[saved_argv_len - 1] = NULL; + } + } if (fd < 0) { perror("open"); @@ -300,42 +376,41 @@ static int add_image(const char *_str, char *devname_template, int *devname_numb goto err_out; } + hf->base = (unsigned long)MAP_FAILED; hf->size = s.st_size; - hf->devname = strdup(devname); if (S_ISBLK(s.st_mode)) { if (ioctl(fd, BLKGETSIZE64, &hf->size) == -1) { perror("ioctl"); goto err_out; } - if (!cdev) + if (!hf->is_cdev) hf->is_blockdev = 1; } - if (hf->size <= SIZE_MAX) + if (hf->size <= SIZE_MAX) { hf->base = (unsigned long)mmap(NULL, hf->size, - PROT_READ | (readonly ? 0 : PROT_WRITE), + PROT_READ | (hf->is_readonly ? 0 : PROT_WRITE), MAP_SHARED, fd, 0); - else - printf("warning: %s: contiguous map failed\n", filename); - if (hf->base == (unsigned long)MAP_FAILED) - printf("warning: mmapping %s failed: %s\n", filename, strerror(errno)); + if (hf->base == (unsigned long)MAP_FAILED) + printf("warning: mmapping %s failed: %s\n", + hf->filename, strerror(errno)); + } else { + printf("warning: %s: contiguous map failed\n", hf->filename); + } - if (blkdev && hf->size % 512 != 0) { + if (hf->is_blockdev && hf->size % 512 != 0) { printf("warning: registering %s as block device failed: invalid block size\n", - filename); + hf->filename); return -EINVAL; } - ret = barebox_register_filedev(hf); - if (ret) - goto err_out; return 0; err_out: if (fd > 0) close(fd); - free(hf); + free(buf); return -1; } @@ -405,8 +480,6 @@ int main(int argc, char *argv[]) __sanitizer_set_death_callback(cookmode); #endif - saved_argv = argv; - while (1) { option_index = 0; opt = getopt_long(argc, argv, optstring, @@ -444,6 +517,12 @@ int main(int argc, char *argv[]) } } + saved_argv_len = argc + 1; + saved_argv = calloc(saved_argv_len, sizeof(*saved_argv)); + if (!saved_argv) + exit(1); + memcpy(saved_argv, argv, saved_argv_len * sizeof(*saved_argv)); + ram = malloc(malloc_size); if (!ram) { printf("unable to get malloc space\n"); diff --git a/arch/x86/configs/efi_defconfig b/arch/x86/configs/efi_defconfig index 83794d7a07..761ffbe261 100644 --- a/arch/x86/configs/efi_defconfig +++ b/arch/x86/configs/efi_defconfig @@ -15,14 +15,19 @@ CONFIG_CONSOLE_ACTIVATE_ALL=y CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_STATE=y +CONFIG_BOOTCHOOSER=y +CONFIG_RESET_SOURCE=y CONFIG_DEBUG_LL=y +CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_GO=y CONFIG_CMD_LOADB=y CONFIG_CMD_RESET=y CONFIG_CMD_UIMAGE=y +CONFIG_CMD_BOOTCHOOSER=y CONFIG_CMD_PARTITION=y CONFIG_CMD_EXPORT=y CONFIG_CMD_LOADENV=y @@ -56,6 +61,7 @@ CONFIG_CMD_POWEROFF=y CONFIG_CMD_WD=y CONFIG_CMD_2048=y CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_DIFF=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OFTREE=y @@ -64,12 +70,24 @@ CONFIG_CMD_STATE=y CONFIG_NET=y CONFIG_NET_NFS=y CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_OF_BAREBOX_ENV_IN_FS=y CONFIG_DRIVER_SERIAL_EFI_STDIO=y CONFIG_DRIVER_NET_EFI_SNP=y # CONFIG_SPI is not set CONFIG_DISK=y +CONFIG_DISK_WRITE=y +CONFIG_VIDEO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_DRIVER_VIDEO_EFI_GOP=y +CONFIG_FINTEK_SUPERIO=y +CONFIG_SMSC_SUPERIO=y +CONFIG_STATE_DRV=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_EFI=y +CONFIG_F71808E_WDT=y +# CONFIG_PINCTRL is not set CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y CONFIG_FS_NFS=y |