diff options
Diffstat (limited to 'arch')
28 files changed, 457 insertions, 82 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 1029e8f46f..5a755c9636 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_MACH_MX23EVK) += freescale-mx23-evk/ obj-$(CONFIG_MACH_MX28EVK) += freescale-mx28-evk/ obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard/ obj-$(CONFIG_MACH_NESO) += guf-neso/ +obj-$(CONFIG_MACH_NETGEAR_RN104) += netgear-rn104/ obj-$(CONFIG_MACH_NOMADIK_8815NHK) += nhk8815/ obj-$(CONFIG_MACH_NVIDIA_BEAVER) += nvidia-beaver/ obj-$(CONFIG_MACH_NVIDIA_JETSON) += nvidia-jetson-tk1/ diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c index 4aaecb9e88..efe15ec99f 100644 --- a/arch/arm/boards/afi-gf/lowlevel.c +++ b/arch/arm/boards/afi-gf/lowlevel.c @@ -222,7 +222,7 @@ static noinline int gf_sram_init(void) while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); /* Setup the PLLs and the clocks for the peripherals */ - am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_200); + am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_200); board_config_ddr(); diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c index 05b3e5f157..79d598561c 100644 --- a/arch/arm/boards/beaglebone/lowlevel.c +++ b/arch/arm/boards/beaglebone/lowlevel.c @@ -138,11 +138,11 @@ static noinline int beaglebone_sram_init(void) /* Setup the PLLs and the clocks for the peripherals */ if (is_beaglebone_black()) { - am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_400); + am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_400); am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data); } else { - am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_266); + am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_266); am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs, &ddr2_data); } diff --git a/arch/arm/boards/cm-fx6/board.c b/arch/arm/boards/cm-fx6/board.c index edef18f8ac..f4380629e3 100644 --- a/arch/arm/boards/cm-fx6/board.c +++ b/arch/arm/boards/cm-fx6/board.c @@ -84,9 +84,17 @@ late_initcall(cm_fx6_eeprom_init); static int cm_fx6_devices_init(void) { + const char *hostname; + if (!of_machine_is_compatible("compulab,cm-fx6")) return 0; + if (of_machine_is_compatible("compulab,utilite")) + hostname = "utilite"; + else + hostname = "cm-fx6"; + barebox_set_hostname(hostname); + if (IS_ENABLED(CONFIG_PHYLIB)) phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, phy_fixup); diff --git a/arch/arm/boards/netgear-rn104/Makefile b/arch/arm/boards/netgear-rn104/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/netgear-rn104/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/netgear-rn104/board.c b/arch/arm/boards/netgear-rn104/board.c new file mode 100644 index 0000000000..40a8c178f1 --- /dev/null +++ b/arch/arm/boards/netgear-rn104/board.c @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/boards/netgear-rn104/kwbimage.cfg b/arch/arm/boards/netgear-rn104/kwbimage.cfg new file mode 100644 index 0000000000..83a4149053 --- /dev/null +++ b/arch/arm/boards/netgear-rn104/kwbimage.cfg @@ -0,0 +1,7 @@ +VERSION 1 +BOOT_FROM nand +DESTADDR 00600000 +EXECADDR 006a0000 +NAND_BLKSZ 00020000 +NAND_BADBLK_LOCATION 01 +BINARY binary.0 0000005b 00000068 diff --git a/arch/arm/boards/netgear-rn104/lowlevel.c b/arch/arm/boards/netgear-rn104/lowlevel.c new file mode 100644 index 0000000000..f0d6df0da6 --- /dev/null +++ b/arch/arm/boards/netgear-rn104/lowlevel.c @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2014 Uwe Kleine-Koenig <uwe@kleine-koenig.org> + */ + +#include <common.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <mach/lowlevel.h> + +extern char __dtb_armada_370_rn104_bb_start[]; + +ENTRY_FUNCTION(start_netgear_rn104, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_armada_370_rn104_bb_start - + get_runtime_offset(); + + mvebu_barebox_entry(fdt); +} diff --git a/arch/arm/boards/nvidia-beaver/entry.c b/arch/arm/boards/nvidia-beaver/entry.c index 9b7e253b4f..0f487bbd67 100644 --- a/arch/arm/boards/nvidia-beaver/entry.c +++ b/arch/arm/boards/nvidia-beaver/entry.c @@ -15,9 +15,6 @@ */ #include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> #include <mach/lowlevel.h> #include <mach/lowlevel-dvc.h> @@ -25,15 +22,11 @@ extern char __dtb_tegra30_beaver_start[]; ENTRY_FUNCTION(start_nvidia_beaver, r0, r1, r2) { - uint32_t fdt; - - tegra_cpu_lowlevel_setup(); + tegra_cpu_lowlevel_setup(__dtb_tegra30_beaver_start); tegra_dvc_init(); tegra30_tps62366a_ramp_vddcore(); tegra30_tps65911_cpu_rail_enable(); - fdt = (uint32_t)__dtb_tegra30_beaver_start - get_runtime_offset(); - - tegra_avp_reset_vector(fdt); + tegra_avp_reset_vector(); } diff --git a/arch/arm/boards/nvidia-jetson-tk1/entry.c b/arch/arm/boards/nvidia-jetson-tk1/entry.c index 8f112a3a91..da40f74e85 100644 --- a/arch/arm/boards/nvidia-jetson-tk1/entry.c +++ b/arch/arm/boards/nvidia-jetson-tk1/entry.c @@ -15,9 +15,6 @@ */ #include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> #include <mach/lowlevel.h> #include <mach/lowlevel-dvc.h> @@ -25,15 +22,11 @@ extern char __dtb_tegra124_jetson_tk1_start[]; ENTRY_FUNCTION(start_nvidia_jetson, r0, r1, r2) { - uint32_t fdt; - - tegra_cpu_lowlevel_setup(); + tegra_cpu_lowlevel_setup(__dtb_tegra124_jetson_tk1_start); tegra_dvc_init(); tegra124_dvc_pinmux(); tegra124_as3722_enable_essential_rails(0x3c00); - fdt = (uint32_t)__dtb_tegra124_jetson_tk1_start - get_runtime_offset(); - - tegra_avp_reset_vector(fdt); + tegra_avp_reset_vector(); } diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c index 64c1c53f67..d7afbb6af3 100644 --- a/arch/arm/boards/phytec-som-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c @@ -32,7 +32,6 @@ #include "ram-timings.h" -#define CLK_M_OSC_MHZ 25 #define DDR_IOCTRL 0x18B static const struct am33xx_cmd_control physom_cmd = { @@ -67,11 +66,10 @@ static noinline void physom_board_init(int sdram, void *fdt) writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); - writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); - am33xx_pll_init(MPUPLL_M_600, CLK_M_OSC_MHZ, DDRPLL_M_400); + am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400); am335x_sdram_init(DDR_IOCTRL, &physom_cmd, &timing->regs, diff --git a/arch/arm/boards/toradex-colibri-t20/entry.c b/arch/arm/boards/toradex-colibri-t20/entry.c index a25958fb41..9557b13f95 100644 --- a/arch/arm/boards/toradex-colibri-t20/entry.c +++ b/arch/arm/boards/toradex-colibri-t20/entry.c @@ -15,22 +15,15 @@ */ #include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> #include <mach/lowlevel.h> extern char __dtb_tegra20_colibri_iris_start[]; static void common_toradex_colibri_t20_iris_start(void) { - uint32_t fdt; + tegra_cpu_lowlevel_setup(__dtb_tegra20_colibri_iris_start); - tegra_cpu_lowlevel_setup(); - - fdt = (uint32_t)__dtb_tegra20_colibri_iris_start - get_runtime_offset(); - - tegra_avp_reset_vector(fdt); + tegra_avp_reset_vector(); } ENTRY_FUNCTION(start_colibri_t20_256_usbload, r0, r1, r2) diff --git a/arch/arm/boards/toshiba-ac100/entry.c b/arch/arm/boards/toshiba-ac100/entry.c index fb695c32d6..56979c9ba1 100644 --- a/arch/arm/boards/toshiba-ac100/entry.c +++ b/arch/arm/boards/toshiba-ac100/entry.c @@ -15,20 +15,13 @@ */ #include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> #include <mach/lowlevel.h> extern char __dtb_tegra20_paz00_start[]; ENTRY_FUNCTION(start_toshiba_ac100, r0, r1, r2) { - uint32_t fdt; + tegra_cpu_lowlevel_setup(__dtb_tegra20_paz00_start); - tegra_cpu_lowlevel_setup(); - - fdt = (uint32_t)__dtb_tegra20_paz00_start - get_runtime_offset(); - - tegra_avp_reset_vector(fdt); + tegra_avp_reset_vector(); } diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 6d1b021768..39372fd93b 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_MVEBU=y CONFIG_MACH_GLOBALSCALE_MIRABOX=y +CONFIG_MACH_NETGEAR_RN104=y CONFIG_MACH_LENOVO_IX4_300D=y CONFIG_MACH_MARVELL_ARMADA_XP_GP=y CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2da930eb91..d85c23768e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -28,6 +28,7 @@ pbl-dtb-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell- pbl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o pbl-dtb-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o pbl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o +pbl-dtb-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o pbl-dtb-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o pbl-dtb-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o pbl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o diff --git a/arch/arm/dts/armada-370-rn104-bb.dts b/arch/arm/dts/armada-370-rn104-bb.dts new file mode 100644 index 0000000000..32f961e529 --- /dev/null +++ b/arch/arm/dts/armada-370-rn104-bb.dts @@ -0,0 +1,11 @@ +/* + * Barebox specific DT overlay for Netgear ReadyNAS 104 + */ + +#include "arm/armada-370-netgear-rn104.dts" + +/ { + chosen { + stdout-path = "/soc/internal-regs/serial@12000"; + }; +}; diff --git a/arch/arm/dts/imx53-ccxmx53.dts b/arch/arm/dts/imx53-ccxmx53.dts index ac6103ad83..85d20c3b63 100644 --- a/arch/arm/dts/imx53-ccxmx53.dts +++ b/arch/arm/dts/imx53-ccxmx53.dts @@ -10,6 +10,95 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <arm/imx53-ccxmx53.dts> +/dts-v1/; #include "imx53-ccxmx53.dtsi" -#include "imx53.dtsi" + +/ { + model = "Digi ConnectCore ccxmx53"; + compatible = "digi,imx53-ccxmx53", "fsl,imx53"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-ccxmx53 { + pinctrl_hog: hoggrp { + + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + /* SD2_CD */ + MX53_PAD_GPIO_4__GPIO1_4 0x1d5 + /* SD2_WP */ + MX53_PAD_GPIO_2__GPIO1_2 0x1d5 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + >; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + status = "okay"; +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + phy-reset-duration = <10>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&iim { + barebox,provide-mac-address = <&fec 1 9>; +}; diff --git a/arch/arm/dts/imx53-ccxmx53.dtsi b/arch/arm/dts/imx53-ccxmx53.dtsi index 6f76d2867a..5553c68e25 100644 --- a/arch/arm/dts/imx53-ccxmx53.dtsi +++ b/arch/arm/dts/imx53-ccxmx53.dtsi @@ -1,3 +1,19 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx53.dtsi" +#include <arm/imx53.dtsi> + + / { chosen { linux,stdout-path = &uart1; @@ -9,9 +25,210 @@ }; }; +/ { + memory { + reg = <0x70000000 0x40000000>; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-ccxmx53 { + pinctrl_hog: hoggrp { + + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 + MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + pmic: dialog@68 { + compatible = "dlg,da9053-aa"; + reg = <0x68>; + interrupt-parent = <&gpio7>; + interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */ + + regulators { + buck1_reg: buck1 { + regulator-name = "BUCKCORE"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "BUCKPRO"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "BUCKMEM"; + regulator-min-microvolt = <1420000>; + regulator-max-microvolt = <1580000>; + regulator-always-on; + }; + + buck4_reg: buck4 { + regulator-name = "BUCKPERI"; + regulator-min-microvolt = <2370000>; + regulator-max-microvolt = <2630000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "ldo3_3v3"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "ldo4_2v775"; + regulator-min-microvolt = <2770000>; + regulator-max-microvolt = <2780000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "ldo5_3v3"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "ldo6_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "ldo7_2v75"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "ldo8_1v8"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1850000>; + regulator-always-on; + }; + + ldo9_reg: ldo9 { + regulator-name = "ldo9_1v5"; + regulator-min-microvolt = <1450000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + ldo10_reg: ldo10 { + regulator-name = "ldo10_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + }; +}; + &nfc { #address-cells = <1>; #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; partition@0 { label = "barebox"; @@ -33,3 +250,9 @@ reg = <0x500000 0x07B00000>; }; }; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx53-guf-vincell-lt.dts b/arch/arm/dts/imx53-guf-vincell-lt.dts index 0a9bcb0f69..a577ab262e 100644 --- a/arch/arm/dts/imx53-guf-vincell-lt.dts +++ b/arch/arm/dts/imx53-guf-vincell-lt.dts @@ -30,10 +30,6 @@ }; }; - memory { - reg = <0x70000000 0x20000000>; - }; - clocks { ckih1 { clock-frequency = <0>; diff --git a/arch/arm/dts/imx53-guf-vincell.dts b/arch/arm/dts/imx53-guf-vincell.dts index ffc157f0b2..2f0153e7b2 100644 --- a/arch/arm/dts/imx53-guf-vincell.dts +++ b/arch/arm/dts/imx53-guf-vincell.dts @@ -25,10 +25,6 @@ linux,stdout-path = &uart2; }; - memory { - reg = <0x70000000 0x20000000>; - }; - clocks { ckih1 { clock-frequency = <0>; diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c index 8761d63682..3cfeebbe93 100644 --- a/arch/arm/mach-imx/imx25.c +++ b/arch/arm/mach-imx/imx25.c @@ -20,6 +20,9 @@ #include <mach/generic.h> #include <linux/sizes.h> +#define MX25_BOOTROM_HAB_MAGIC 0x3c95cac6 +#define MX25_DRYICE_GPR 0x3c + void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned additional) { @@ -55,9 +58,32 @@ u64 imx_uid(void) int imx25_init(void) { + int val; + imx25_boot_save_loc((void *)MX25_CCM_BASE_ADDR); add_generic_device("imx25-esdctl", 0, NULL, MX25_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + /* + * When the i.MX25 is used with internal boot, the boot ROM always + * performs some HAB actions. These will copy the value from DryIce + * GPR (0x53ffc03c) to a location in SRAM (0x78001734) and then overwrites + * the GPR with 0x3c95cac6. + * After the HAB routine is done, the boot ROM should copy the previously + * saved value from SRAM back to the GPR. The last step is not done. + * The boot ROM is officially broken in this regard. + * This renders the Non-volatile memory to a Non-Non-volatile memory. + * To still be able to use the GPR for its intended purpose, copy the + * saved SRAM value back manually. + */ + val = readl(MX25_IRAM_BASE_ADDR + 0x1734); + + /* + * When there is a different value in SRAM than the magic value + * it must be a value saved to the GPR. + */ + if (val != MX25_BOOTROM_HAB_MAGIC) + writel(val, MX25_DRYICE_BASE_ADDR + MX25_DRYICE_GPR); + return 0; } diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 5e96f16e8c..79fcc8d3ac 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -37,6 +37,10 @@ config MACH_GLOBALSCALE_MIRABOX bool "Globalscale Mirabox" select ARCH_ARMADA_370 +config MACH_NETGEAR_RN104 + bool "Netgear ReadyNAS 104" + select ARCH_ARMADA_370 + # # Armada XP SoC boards # diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c index 6d8addef32..ad735cb216 100644 --- a/arch/arm/mach-omap/am33xx_clock.c +++ b/arch/arm/mach-omap/am33xx_clock.c @@ -15,6 +15,7 @@ #include <common.h> #include <asm/io.h> #include <mach/am33xx-clock.h> +#include <asm-generic/div64.h> #define PRCM_MOD_EN 0x2 #define PRCM_FORCE_WAKEUP 0x2 @@ -304,8 +305,13 @@ void am33xx_enable_ddr_clocks(void) /* * Configure the PLL/PRCM for necessary peripherals */ -void am33xx_pll_init(int mpupll_M, int osc, int ddrpll_M) +void am33xx_pll_init(int mpupll_M, int ddrpll_M) { + int osc; + + osc = am33xx_get_osc_clock(); + osc /= 1000; + mpu_pll_config(mpupll_M, osc); core_pll_config(osc); per_pll_config(osc); @@ -318,3 +324,30 @@ void am33xx_pll_init(int mpupll_M, int osc, int ddrpll_M) /* Enable the required peripherals */ am33xx_enable_per_clocks(); } + +/* + * Return the OSC clock value from SYSBOOT pins in kHz. + */ +int am33xx_get_osc_clock(void) +{ + int osc; + u32 sysboot; + + sysboot = (readl(AM33XX_CTRL_STATUS) >> 22) & 3; + switch (sysboot) { + case 0: + osc = 19200; + break; + case 1: + osc = 24000; + break; + case 2: + osc = 25000; + break; + case 3: + osc = 26000; + break; + } + + return osc; +} diff --git a/arch/arm/mach-omap/dmtimer.c b/arch/arm/mach-omap/dmtimer.c index 56adda080a..e223b8cc8f 100644 --- a/arch/arm/mach-omap/dmtimer.c +++ b/arch/arm/mach-omap/dmtimer.c @@ -31,6 +31,7 @@ #include <init.h> #include <io.h> #include <mach/am33xx-silicon.h> +#include <mach/am33xx-clock.h> #include <stdio.h> @@ -82,24 +83,9 @@ static struct clocksource dmtimer_cs = { static int dmtimer_init(void) { u64 clk_speed; - int sysboot; - - sysboot = (readl(AM33XX_CTRL_STATUS) >> 22) & 3; - switch (sysboot) { - case 0: - clk_speed = 19200000; - break; - case 1: - clk_speed = 24000000; - break; - case 2: - clk_speed = 25000000; - break; - case 3: - clk_speed = 26000000; - break; - } + clk_speed = am33xx_get_osc_clock(); + clk_speed *= 1000; dmtimer_cs.mult = clocksource_hz2mult(clk_speed, dmtimer_cs.shift); /* Enable counter */ diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index 2d6a727e1c..284d5f8cf6 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -183,7 +183,8 @@ #define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL -void am33xx_pll_init(int mpupll_M, int osc, int ddrpll_M); +void am33xx_pll_init(int mpupll_M, int ddrpll_M); void am33xx_enable_ddr_clocks(void); +int am33xx_get_osc_clock(void); #endif /* endif _AM33XX_CLOCKS_H_ */ diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h index 0c76b8883c..f70688e029 100644 --- a/arch/arm/mach-tegra/include/mach/lowlevel.h +++ b/arch/arm/mach-tegra/include/mach/lowlevel.h @@ -24,6 +24,7 @@ #ifndef __TEGRA_LOWLEVEL_H #define __TEGRA_LOWLEVEL_H +#include <asm/barebox-arm.h> #include <linux/compiler.h> #include <linux/sizes.h> #include <io.h> @@ -244,18 +245,18 @@ void tegra_ll_delay_usec(int delay) } /* reset vector for the AVP, to be called from board reset vector */ -void tegra_avp_reset_vector(uint32_t boarddata); +void tegra_avp_reset_vector(void); /* reset vector for the main CPU complex */ -void tegra_maincomplex_entry(void); +void tegra_maincomplex_entry(char *fdt); static __always_inline -void tegra_cpu_lowlevel_setup(void) +void tegra_cpu_lowlevel_setup(char *fdt) { uint32_t r; if (tegra_cpu_is_maincomplex()) - tegra_maincomplex_entry(); + tegra_maincomplex_entry(fdt - get_runtime_offset()); /* set the cpu to SVC32 mode */ __asm__ __volatile__("mrs %0, cpsr":"=r"(r)); diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c index 20fcf3f1d1..16dc65be07 100644 --- a/arch/arm/mach-tegra/tegra_avp_init.c +++ b/arch/arm/mach-tegra/tegra_avp_init.c @@ -257,14 +257,11 @@ static void tegra_cluster_switch_hp(void) writel(reg, TEGRA_FLOW_CTRL_BASE + FLOW_CLUSTER_CONTROL); } -void tegra_avp_reset_vector(uint32_t boarddata) +void tegra_avp_reset_vector(void) { int num_cores; unsigned int entry_address = 0; - /* put boarddata in scratch reg, for main CPU to fetch after startup */ - writel(boarddata, TEGRA_PMC_BASE + PMC_SCRATCH(10)); - /* we want to bring up the high performance CPU complex */ if (tegra_get_chiptype() >= TEGRA30) tegra_cluster_switch_hp(); diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c b/arch/arm/mach-tegra/tegra_maincomplex_init.c index 6c6bdf6c15..27bb3363a3 100644 --- a/arch/arm/mach-tegra/tegra_maincomplex_init.c +++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c @@ -23,7 +23,7 @@ #include <mach/tegra20-pmc.h> #include <mach/tegra20-car.h> -void tegra_maincomplex_entry(void) +void tegra_maincomplex_entry(char *fdt) { uint32_t rambase, ramsize; enum tegra_chiptype chiptype; @@ -79,6 +79,5 @@ void tegra_maincomplex_entry(void) unreachable(); } - barebox_arm_entry(rambase, ramsize, - (void *)readl(TEGRA_PMC_BASE + PMC_SCRATCH(10))); + barebox_arm_entry(rambase, ramsize, fdt); } |