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-rw-r--r--arch/arm/boards/at91sam9261ek/init.c35
-rw-r--r--arch/arm/boards/at91sam9263ek/init.c26
-rw-r--r--arch/arm/boards/at91sam9m10ihd/init.c26
-rw-r--r--arch/arm/boards/at91sam9n12ek/init.c28
-rw-r--r--arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg94
-rw-r--r--arch/arm/dts/imx6ul-phytec-phycore-som.dtsi4
-rw-r--r--arch/arm/mach-at91/include/mach/barebox-arm-head.h18
7 files changed, 73 insertions, 158 deletions
diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c
index 72716b8186..58f253b1a6 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -158,22 +158,6 @@ static void ek_add_device_udc(void) {}
* LCD Controller
*/
#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
-static int ek_gpio_request_output(int gpio, const char *name)
-{
- int ret;
-
- ret = gpio_request(gpio, name);
- if (ret) {
- pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret);
- return ret;
- }
-
- ret = gpio_direction_output(gpio, 1);
- if (ret)
- pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret);
- return ret;
-}
-
/* TFT */
static struct fb_videomode at91_tft_vga_modes[] = {
{
@@ -195,35 +179,20 @@ static struct fb_videomode at91_tft_vga_modes[] = {
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-static void at91_lcdc_tft_power_control(int on)
-{
- if (on)
- gpio_set_value(AT91_PIN_PA12, 0); /* power up */
- else
- gpio_set_value(AT91_PIN_PA12, 1); /* power down */
-}
-
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 16,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91SAM9261_DEFAULT_TFT_LCDCON2,
.guard_time = 1,
- .atmel_lcdfb_power_control = at91_lcdc_tft_power_control,
+ .gpio_power_control = AT91_PIN_PA12,
+ .gpio_power_control_active_low = true,
.mode_list = at91_tft_vga_modes,
.num_modes = ARRAY_SIZE(at91_tft_vga_modes),
};
-static int at91_lcdc_gpio(void)
-{
- return ek_gpio_request_output(AT91_PIN_PA12, "lcdc_tft_power");
-}
-
static void ek_add_device_lcdc(void)
{
- if (at91_lcdc_gpio())
- return;
-
if (machine_is_at91sam9g10ek())
ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c
index 682449b7be..b71cc55179 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -156,22 +156,6 @@ static void ek_add_device_udc(void) {}
* LCD Controller
*/
#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
-static int ek_gpio_request_output(int gpio, const char *name)
-{
- int ret;
-
- ret = gpio_request(gpio, name);
- if (ret) {
- pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret);
- return ret;
- }
-
- ret = gpio_direction_output(gpio, 1);
- if (ret)
- pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret);
- return ret;
-}
-
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "TX09D50VM1CCA @ 60",
@@ -192,11 +176,6 @@ static struct fb_videomode at91_tft_vga_modes[] = {
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-static void at91_lcdc_power_control(int on)
-{
- gpio_set_value(AT91_PIN_PA30, on);
-}
-
/* Driver datas */
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
@@ -204,16 +183,13 @@ static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2,
.guard_time = 1,
- .atmel_lcdfb_power_control = at91_lcdc_power_control,
+ .gpio_power_control = AT91_PIN_PA30,
.mode_list = at91_tft_vga_modes,
.num_modes = ARRAY_SIZE(at91_tft_vga_modes),
};
static void ek_add_device_lcdc(void)
{
- if (ek_gpio_request_output(AT91_PIN_PA30, "lcdc_power"))
- return;
-
at91_add_device_lcdc(&ek_lcdc_data);
}
diff --git a/arch/arm/boards/at91sam9m10ihd/init.c b/arch/arm/boards/at91sam9m10ihd/init.c
index dcd93c10b3..de601d53b3 100644
--- a/arch/arm/boards/at91sam9m10ihd/init.c
+++ b/arch/arm/boards/at91sam9m10ihd/init.c
@@ -177,22 +177,6 @@ static int at91sam9m10g45ek_mem_init(void)
mem_initcall(at91sam9m10g45ek_mem_init);
#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
-static int ek_gpio_request_output(int gpio, const char *name)
-{
- int ret;
-
- ret = gpio_request(gpio, name);
- if (ret) {
- pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret);
- return ret;
- }
-
- ret = gpio_direction_output(gpio, 1);
- if (ret)
- pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret);
- return ret;
-}
-
static struct fb_videomode at91fb_default_monspecs[] = {
{
.name = "MULTEK",
@@ -213,11 +197,6 @@ static struct fb_videomode at91fb_default_monspecs[] = {
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-static void at91_lcdc_power_control(int on)
-{
- gpio_set_value(AT91_PIN_PE6, on);
-}
-
/* Driver datas */
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
@@ -226,16 +205,13 @@ static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2,
.guard_time = 9,
.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
- .atmel_lcdfb_power_control = at91_lcdc_power_control,
+ .gpio_power_control = AT91_PIN_PE6,
.mode_list = at91fb_default_monspecs,
.num_modes = ARRAY_SIZE(at91fb_default_monspecs),
};
static void ek_add_device_lcd(void)
{
- if (ek_gpio_request_output(AT91_PIN_PE6, "lcdc_power"))
- return;
-
at91_add_device_lcdc(&ek_lcdc_data);
}
#else
diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c
index b9431b2ee1..bc3fb8e089 100644
--- a/arch/arm/boards/at91sam9n12ek/init.c
+++ b/arch/arm/boards/at91sam9n12ek/init.c
@@ -127,23 +127,6 @@ static void __init ek_add_device_ks8851(void) {}
#endif /* CONFIG_DRIVER_NET_KS8851_MLL */
#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD)
-static int ek_gpio_request_output(int gpio, const char *name)
-{
- int ret;
-
- ret = gpio_request(gpio, name);
- if (ret) {
- pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret);
- return ret;
- }
-
- ret = gpio_direction_output(gpio, 1);
- if (ret)
- pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret);
- return ret;
-}
-
-
/*
* LCD Controller
*/
@@ -166,11 +149,6 @@ static struct fb_videomode at91_tft_vga_modes[] = {
/* Default output mode is TFT 24 bit */
#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP)
-static void at91_lcdc_power_control(int on)
-{
- gpio_set_value(AT91_PIN_PC25, !on);
-}
-
/* Driver datas */
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
@@ -179,16 +157,14 @@ static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5,
.guard_time = 9,
.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
- .atmel_lcdfb_power_control = at91_lcdc_power_control,
+ .gpio_power_control = AT91_PIN_PC25,
+ .gpio_power_control_active_low = true,
.mode_list = at91_tft_vga_modes,
.num_modes = ARRAY_SIZE(at91_tft_vga_modes),
};
static void ek_add_device_lcdc(void)
{
- if (ek_gpio_request_output(AT91_PIN_PC25, "lcdc_power"))
- return;
-
at91_add_device_lcdc(&ek_lcdc_data);
}
#else
diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
index b1608dd9c7..6c256e8fc5 100644
--- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
+++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
@@ -13,64 +13,66 @@ soc imx7
loadaddr 0x80000000
dcdofs 0x400
+#include <mach/imx7-ddr-regs.h>
+
wm 32 0x30340004 0x4F400005
/* Clear then set bit30 to ensure exit from DDR retention */
wm 32 0x30360388 0x40000000
wm 32 0x30360384 0x40000000
wm 32 0x30391000 0x00000002
-wm 32 0x307a0000 0x01040001
-wm 32 0x307a01a0 0x80400003
-wm 32 0x307a01a4 0x00100020
-wm 32 0x307a01a8 0x80100004
-wm 32 0x307a0064 0x00400046
-wm 32 0x307a0490 0x00000001
-wm 32 0x307a00d0 0x00020083
-wm 32 0x307a00d4 0x00690000
-wm 32 0x307a00dc 0x09300004
-wm 32 0x307a00e0 0x04080000
-wm 32 0x307a00e4 0x00100004
-wm 32 0x307a00f4 0x0000033f
-wm 32 0x307a0100 0x09081109
-wm 32 0x307a0104 0x0007020d
-wm 32 0x307a0108 0x03040407
-wm 32 0x307a010c 0x00002006
-wm 32 0x307a0110 0x04020205
-wm 32 0x307a0114 0x03030202
-wm 32 0x307a0120 0x00000803
-wm 32 0x307a0180 0x00800020
-wm 32 0x307a0184 0x02000100
-wm 32 0x307a0190 0x02098204
-wm 32 0x307a0194 0x00030303
-wm 32 0x307a0200 0x00000016
-wm 32 0x307a0204 0x00171717
-wm 32 0x307a0214 0x04040404
-wm 32 0x307a0218 0x0f040404
-wm 32 0x307a0240 0x06000604
-wm 32 0x307a0244 0x00000001
+wm 32 MX7_DDRC_MSTR 0x01040001
+wm 32 MX7_DDRC_DFIUPD0 0x80400003
+wm 32 MX7_DDRC_DFIUPD1 0x00100020
+wm 32 MX7_DDRC_DFIUPD2 0x80100004
+wm 32 MX7_DDRC_RFSHTMG 0x00400046
+wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001
+wm 32 MX7_DDRC_INIT0 0x00020083
+wm 32 MX7_DDRC_INIT1 0x00690000
+wm 32 MX7_DDRC_INIT3 0x09300004
+wm 32 MX7_DDRC_INIT4 0x04080000
+wm 32 MX7_DDRC_INIT5 0x00100004
+wm 32 MX7_DDRC_RANKCTL 0x0000033f
+wm 32 MX7_DDRC_DRAMTMG0 0x09081109
+wm 32 MX7_DDRC_DRAMTMG1 0x0007020d
+wm 32 MX7_DDRC_DRAMTMG2 0x03040407
+wm 32 MX7_DDRC_DRAMTMG3 0x00002006
+wm 32 MX7_DDRC_DRAMTMG4 0x04020205
+wm 32 MX7_DDRC_DRAMTMG5 0x03030202
+wm 32 MX7_DDRC_DRAMTMG8 0x00000803
+wm 32 MX7_DDRC_ZQCTL0 0x00800020
+wm 32 MX7_DDRC_ZQCTL1 0x02000100
+wm 32 MX7_DDRC_DFITMG0 0x02098204
+wm 32 MX7_DDRC_DFITMG1 0x00030303
+wm 32 MX7_DDRC_ADDRMAP0 0x00000016
+wm 32 MX7_DDRC_ADDRMAP1 0x00171717
+wm 32 MX7_DDRC_ADDRMAP5 0x04040404
+wm 32 MX7_DDRC_ADDRMAP6 0x0f040404
+wm 32 MX7_DDRC_ODTCFG 0x06000604
+wm 32 MX7_DDRC_ODTMAP 0x00000001
wm 32 0x30391000 0x00000000
-wm 32 0x30790000 0x17420f40
-wm 32 0x30790004 0x10210100
-wm 32 0x30790010 0x00060807
-wm 32 0x307900b0 0x1010007e
-wm 32 0x3079009c 0x00000d6e
-wm 32 0x30790020 0x08080808
-wm 32 0x30790030 0x08080808
-wm 32 0x30790050 0x01000010
-wm 32 0x30790050 0x00000010
+wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40
+wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100
+wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807
+wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e
+wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e
+wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808
+wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808
+wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010
+wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010
-wm 32 0x307900c0 0x0e407304
-wm 32 0x307900c0 0x0e447304
-wm 32 0x307900c0 0x0e447306
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306
-check 32 while_any_bit_clear 0x307900c4 0x1
+check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1
-wm 32 0x307900c0 0x0e447304
-wm 32 0x307900c0 0x0e407304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
wm 32 0x30384130 0x00000000
wm 32 0x30340020 0x00000178
wm 32 0x30384130 0x00000002
-wm 32 0x30790018 0x0000000f
+wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f
-check 32 while_any_bit_clear 0x307a0004 0x1
+check 32 while_any_bit_clear MX7_DDRC_STAT 0x1
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 96beef4e72..8cec1296a7 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -176,3 +176,7 @@
};
};
};
+
+&ocotp {
+ barebox,provide-mac-address = <&fec1 0x620 &fec2 0x632>;
+};
diff --git a/arch/arm/mach-at91/include/mach/barebox-arm-head.h b/arch/arm/mach-at91/include/mach/barebox-arm-head.h
index d4bb96f634..e0e07500a2 100644
--- a/arch/arm/mach-at91/include/mach/barebox-arm-head.h
+++ b/arch/arm/mach-at91/include/mach/barebox-arm-head.h
@@ -7,13 +7,13 @@
#define AT91_EXV6 ".word _barebox_bare_init_size\n"
#endif
-static inline void barebox_arm_head(void)
+static inline void __barebox_arm_head(void)
{
__asm__ __volatile__ (
#ifdef CONFIG_THUMB2_BAREBOX
#error Thumb2 is not supported
#else
- "b barebox_arm_reset_vector\n"
+ "b 2f\n"
"1: b 1b\n"
"1: b 1b\n"
"1: b 1b\n"
@@ -27,7 +27,19 @@ static inline void barebox_arm_head(void)
* barebox can skip relocation
*/
".word _barebox_image_size\n" /* image size to copy */
+ ".rept 8\n"
+ ".word 0x55555555\n"
+ ".endr\n"
+ "2:\n"
+ );
+}
+
+static inline void barebox_arm_head(void)
+{
+ __barebox_arm_head();
+ __asm__ __volatile__ (
+ "b barebox_arm_reset_vector\n"
);
}
-#endif /* __ASM_ARM_HEAD_H */
+#endif /* __MACH_ARM_HEAD_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-30 13:25:01 +0000