diff options
Diffstat (limited to 'arch')
34 files changed, 2261 insertions, 532 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 3cea2e0e5d..c5dc41526b 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/ obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += phytec-som-am335x/ obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += phytec-som-imx6/ obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += phytec-phycore-imx7/ +obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += phytec-som-imx8mq/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/ obj-$(CONFIG_MACH_PM9261) += pm9261/ diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 9d81c278ca..915534ea94 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -84,6 +84,7 @@ static void __noreturn start_imx6_phytec_common(uint32_t size, extern char __dtb_##fdt_name##_start[]; \ \ IMD_USED(physom_mx6_memsize_##memory_size); \ + IMD_USED_OF(fdt_name); \ \ start_imx6_phytec_common(memory_size, do_early_uart_config, \ __dtb_##fdt_name##_start); \ diff --git a/arch/arm/boards/phytec-som-imx8mq/.gitignore b/arch/arm/boards/phytec-som-imx8mq/.gitignore new file mode 100644 index 0000000000..ef13747c92 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mq/.gitignore @@ -0,0 +1 @@ +*.ddr-phy-fw* diff --git a/arch/arm/boards/phytec-som-imx8mq/Makefile b/arch/arm/boards/phytec-som-imx8mq/Makefile new file mode 100644 index 0000000000..2995f06f0f --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mq/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o ddr_init.o ddrphy_train.o diff --git a/arch/arm/boards/phytec-som-imx8mq/board.c b/arch/arm/boards/phytec-som-imx8mq/board.c new file mode 100644 index 0000000000..4fd098c5f6 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mq/board.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Christian Hemp + */ + +#include <asm/memory.h> +#include <bootsource.h> +#include <environment.h> +#include <common.h> +#include <init.h> +#include <linux/sizes.h> +#include <mach/bbu.h> + +#include <envfs.h> + +static int physom_imx8mq_devices_init(void) +{ + int flag_emmc = 0; + int flag_sd = 0; + + if (!of_machine_is_compatible("phytec,imx8mq-pcl066")) + return 0; + + barebox_set_hostname("phycore-imx8mq"); + + switch (bootsource_get_instance()) { + case 0: + flag_emmc = BBU_HANDLER_FLAG_DEFAULT; + of_device_enable_path("/chosen/environment-emmc"); + break; + case 1: + default: + flag_sd = BBU_HANDLER_FLAG_DEFAULT; + of_device_enable_path("/chosen/environment-sd"); + break; + } + + imx8mq_bbu_internal_mmc_register_handler("eMMC", + "/dev/mmc0.barebox", flag_emmc); + imx8mq_bbu_internal_mmc_register_handler("SD", + "/dev/mmc1.barebox", flag_sd); + + + return 0; +} +device_initcall(physom_imx8mq_devices_init); diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr.h b/arch/arm/boards/phytec-som-imx8mq/ddr.h new file mode 100644 index 0000000000..18ae6e9022 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mq/ddr.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2018 Christian Hemp + * + * Varios wrappers and macros needed to intgrate code generated by + * i.MX8M DDR Tool into rest of Barebox + */ +#include <common.h> +#include <io.h> +#include <mach/imx8-ddrc.h> + +/* + * Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the + * global identifiers below, so in order to avoid symbol name + * collisions with other boards we re-name them via a #define + */ +#define ddr_init phytec_imx8mq_phycore_ddr_init +#define ddr_cfg_phy phytec_imx8mq_phycore_ddr_cfg_phy + +void phytec_imx8mq_phycore_ddr_init(void); +void phytec_imx8mq_phycore_ddr_cfg_phy(void); + +#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \ + lpddr4_pmu_train_1d_dmem_bin +#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \ + lpddr4_pmu_train_2d_dmem_bin diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr_init.c b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c new file mode 100644 index 0000000000..aa327d3fb0 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c @@ -0,0 +1,225 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2017.03_4.9.51_imx8m_ga + */ + +#include "ddr.h" + +void ddr_cfg_phy(void); +volatile unsigned int tmp, tmp_t, i; +void ddr_init(void) +{ + /** Initialize DDR clock and DDRC registers **/ + reg32_write(0x3038a088,0x7070000); + reg32_write(0x3038a084,0x4030000); + reg32_write(0x303a00ec,0xffff); + tmp=reg32_read(0x303a00f8); + tmp |= 0x20; + reg32_write(0x303a00f8,tmp); + reg32_write(0x30391000,0x8f000000); + reg32_write(0x30391004,0x8f000000); + reg32_write(0x30360068,0xece580); + tmp=reg32_read(0x30360060); + tmp &= ~0x80; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp |= 0x200; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x20; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x10; + reg32_write(0x30360060,tmp); + do{ + tmp=reg32_read(0x30360060); + if(tmp&0x80000000) break; + }while(1); + reg32_write(0x30391000,0x8f000006); + reg32_write(0x3d400304,0x1); + reg32_write(0x3d400030,0x1); + reg32_write(0x3d400000,0xa1080020); + reg32_write(0x3d400028,0x0); + reg32_write(0x3d400020,0x203); + reg32_write(0x3d400024,0x186a000); + reg32_write(0x3d400064,0x6100e0); + reg32_write(0x3d4000d0,0xc003061c); + reg32_write(0x3d4000d4,0x9e0000); + reg32_write(0x3d4000dc,0xd4002d); + reg32_write(0x3d4000e0,0x310008); + reg32_write(0x3d4000e8,0x66004a); + reg32_write(0x3d4000ec,0x16004a); + reg32_write(0x3d400100,0x1a201b22); + reg32_write(0x3d400104,0x60633); + reg32_write(0x3d40010c,0xc0c000); + reg32_write(0x3d400110,0xf04080f); + reg32_write(0x3d400114,0x2040c0c); + reg32_write(0x3d400118,0x1010007); + reg32_write(0x3d40011c,0x401); + reg32_write(0x3d400130,0x20600); + reg32_write(0x3d400134,0xc100002); + reg32_write(0x3d400138,0xe6); + reg32_write(0x3d400144,0xa00050); + reg32_write(0x3d400180,0xc3200018); + reg32_write(0x3d400184,0x28061a8); + reg32_write(0x3d400188,0x0); + reg32_write(0x3d400190,0x497820a); + reg32_write(0x3d400194,0x80303); + reg32_write(0x3d4001a0,0xe0400018); + reg32_write(0x3d4001a4,0xdf00e4); + reg32_write(0x3d4001a8,0x80000000); + reg32_write(0x3d4001b0,0x11); + reg32_write(0x3d4001b4,0x170a); + reg32_write(0x3d4001c0,0x1); + reg32_write(0x3d4001c4,0x1); + reg32_write(0x3d4000f4,0x639); + reg32_write(0x3d400108,0x70e1617); + reg32_write(0x3d400200,0x1f); + reg32_write(0x3d40020c,0x0); + reg32_write(0x3d400210,0x1f1f); + reg32_write(0x3d400204,0x80808); + reg32_write(0x3d400214,0x7070707); + reg32_write(0x3d400218,0xf070707); + reg32_write(0x3d402020,0x1); + reg32_write(0x3d402024,0x518b00); + reg32_write(0x3d402050,0x20d040); + reg32_write(0x3d402064,0x14002f); + reg32_write(0x3d4020dc,0x940009); + reg32_write(0x3d4020e0,0x310000); + reg32_write(0x3d4020e8,0x66004a); + reg32_write(0x3d4020ec,0x16004a); + reg32_write(0x3d402100,0xb070508); + reg32_write(0x3d402104,0x3040b); + reg32_write(0x3d402108,0x305090c); + reg32_write(0x3d40210c,0x505000); + reg32_write(0x3d402110,0x4040204); + reg32_write(0x3d402114,0x2030303); + reg32_write(0x3d402118,0x1010004); + reg32_write(0x3d40211c,0x301); + reg32_write(0x3d402130,0x20300); + reg32_write(0x3d402134,0xa100002); + reg32_write(0x3d402138,0x31); + reg32_write(0x3d402144,0x220011); + reg32_write(0x3d402180,0xc0a70006); + reg32_write(0x3d402190,0x3858202); + reg32_write(0x3d402194,0x80303); + reg32_write(0x3d4021b4,0x502); + reg32_write(0x3d400244,0x0); + reg32_write(0x3d400250,0x29001505); + reg32_write(0x3d400254,0x2c); + reg32_write(0x3d40025c,0x5900575b); + reg32_write(0x3d400264,0x90000096); + reg32_write(0x3d40026c,0x1000012c); + reg32_write(0x3d400300,0x16); + reg32_write(0x3d400304,0x0); + reg32_write(0x3d40030c,0x0); + reg32_write(0x3d400320,0x1); + reg32_write(0x3d40036c,0x11); + reg32_write(0x3d400400,0x111); + reg32_write(0x3d400404,0x10f3); + reg32_write(0x3d400408,0x72ff); + reg32_write(0x3d400490,0x1); + reg32_write(0x3d400494,0xe00); + reg32_write(0x3d400498,0x62ffff); + reg32_write(0x3d40049c,0xe00); + reg32_write(0x3d4004a0,0xffff); + reg32_write(0x30391000,0x8f000004); + reg32_write(0x30391000,0x8f000000); + reg32_write(0x3d400030,0xa8); + do{ + tmp=reg32_read(0x3d400004); + if(tmp&0x223) break; + }while(1); + reg32_write(0x3d400320,0x0); + reg32_write(0x3d000000,0x1); + reg32_write(0x3d4001b0,0x10); + reg32_write(0x3c040280,0x0); + reg32_write(0x3c040284,0x1); + reg32_write(0x3c040288,0x2); + reg32_write(0x3c04028c,0x3); + reg32_write(0x3c040290,0x4); + reg32_write(0x3c040294,0x5); + reg32_write(0x3c040298,0x6); + reg32_write(0x3c04029c,0x7); + reg32_write(0x3c044280,0x0); + reg32_write(0x3c044284,0x1); + reg32_write(0x3c044288,0x2); + reg32_write(0x3c04428c,0x3); + reg32_write(0x3c044290,0x4); + reg32_write(0x3c044294,0x5); + reg32_write(0x3c044298,0x6); + reg32_write(0x3c04429c,0x7); + reg32_write(0x3c048280,0x0); + reg32_write(0x3c048284,0x1); + reg32_write(0x3c048288,0x2); + reg32_write(0x3c04828c,0x3); + reg32_write(0x3c048290,0x4); + reg32_write(0x3c048294,0x5); + reg32_write(0x3c048298,0x6); + reg32_write(0x3c04829c,0x7); + reg32_write(0x3c04c280,0x0); + reg32_write(0x3c04c284,0x1); + reg32_write(0x3c04c288,0x2); + reg32_write(0x3c04c28c,0x3); + reg32_write(0x3c04c290,0x4); + reg32_write(0x3c04c294,0x5); + reg32_write(0x3c04c298,0x6); + reg32_write(0x3c04c29c,0x7); + + /* Configure DDR PHY's registers */ + ddr_cfg_phy(); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x0000); + /* + * ------------------- 9 ------------------- + * Set DFIMISC.dfi_init_start to 1 + * ----------------------------------------- + */ + reg32_write(DDRC_DFIMISC(0), 0x00000030); + reg32_write(DDRC_SWCTL(0), 0x0001); + + /* wait DFISTAT.dfi_init_complete to 1 */ + tmp_t = 0; + while(tmp_t==0){ + tmp = reg32_read(DDRC_DFISTAT(0)); + tmp_t = tmp & 0x01; + tmp = reg32_read(DDRC_MRSTAT(0)); + } + + reg32_write(DDRC_SWCTL(0), 0x0000); + + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + reg32_write(DDRC_DFIMISC(0), 0x00000011); + reg32_write(DDRC_PWRCTL(0), 0x00000088); + + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + /* + * set SWCTL.sw_done to enable quasi-dynamic register + * programming outside reset. + */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* wait SWSTAT.sw_done_ack to 1 */ + while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0) + ; + + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ + while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1) + ; + + reg32_write(DDRC_PWRCTL(0), 0x00000088); + /* reg32_write(DDRC_PWRCTL(0), 0x018a); */ + tmp = reg32_read(DDRC_CRCPARSTAT(0)); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + /* enable DDR auto-refresh mode */ + tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; + reg32_write(DDRC_RFSHCTL3(0), tmp); +} diff --git a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c new file mode 100644 index 0000000000..56af647821 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c @@ -0,0 +1,947 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2017.03_4.9.51_imx8m_ga + */ + +#include "ddr.h" + +extern void wait_ddrphy_training_complete(void); +void ddr_cfg_phy(void) { + unsigned int tmp, tmp_t; + + //Init DDRPHY register... + reg32_write(0x3c080440,0x2); + reg32_write(0x3c080444,0x3); + reg32_write(0x3c080448,0x4); + reg32_write(0x3c08044c,0x5); + reg32_write(0x3c080450,0x0); + reg32_write(0x3c080454,0x1); + reg32_write(0x3c04017c,0x1ff); + reg32_write(0x3c04057c,0x1ff); + reg32_write(0x3c04417c,0x1ff); + reg32_write(0x3c04457c,0x1ff); + reg32_write(0x3c04817c,0x1ff); + reg32_write(0x3c04857c,0x1ff); + reg32_write(0x3c04c17c,0x1ff); + reg32_write(0x3c04c57c,0x1ff); + reg32_write(0x3c44017c,0x1ff); + reg32_write(0x3c44057c,0x1ff); + reg32_write(0x3c44417c,0x1ff); + reg32_write(0x3c44457c,0x1ff); + reg32_write(0x3c44817c,0x1ff); + reg32_write(0x3c44857c,0x1ff); + reg32_write(0x3c44c17c,0x1ff); + reg32_write(0x3c44c57c,0x1ff); + reg32_write(0x3c000154,0x1ff); + reg32_write(0x3c004154,0x1ff); + reg32_write(0x3c008154,0x1ff); + reg32_write(0x3c00c154,0x1ff); + reg32_write(0x3c010154,0x1ff); + reg32_write(0x3c014154,0x1ff); + reg32_write(0x3c018154,0x1ff); + reg32_write(0x3c01c154,0x1ff); + reg32_write(0x3c020154,0x1ff); + reg32_write(0x3c024154,0x1ff); + reg32_write(0x3c080314,0x19); + reg32_write(0x3c480314,0x7); + reg32_write(0x3c0800b8,0x2); + reg32_write(0x3c4800b8,0x1); + reg32_write(0x3c240810,0x0); + reg32_write(0x3c640810,0x0); + reg32_write(0x3c080090,0x1ab); + reg32_write(0x3c0800e8,0x0); + reg32_write(0x3c480090,0x1ab); + reg32_write(0x3c0800e8,0x0); + reg32_write(0x3c080158,0x3); + reg32_write(0x3c480158,0xa); + reg32_write(0x3c040134,0xe00); + reg32_write(0x3c040534,0xe00); + reg32_write(0x3c044134,0xe00); + reg32_write(0x3c044534,0xe00); + reg32_write(0x3c048134,0xe00); + reg32_write(0x3c048534,0xe00); + reg32_write(0x3c04c134,0xe00); + reg32_write(0x3c04c534,0xe00); + reg32_write(0x3c440134,0xe00); + reg32_write(0x3c440534,0xe00); + reg32_write(0x3c444134,0xe00); + reg32_write(0x3c444534,0xe00); + reg32_write(0x3c448134,0xe00); + reg32_write(0x3c448534,0xe00); + reg32_write(0x3c44c134,0xe00); + reg32_write(0x3c44c534,0xe00); + reg32_write(0x3c040124,0xfbe); + reg32_write(0x3c040524,0xfbe); + reg32_write(0x3c044124,0xfbe); + reg32_write(0x3c044524,0xfbe); + reg32_write(0x3c048124,0xfbe); + reg32_write(0x3c048524,0xfbe); + reg32_write(0x3c04c124,0xfbe); + reg32_write(0x3c04c524,0xfbe); + reg32_write(0x3c440124,0xfbe); + reg32_write(0x3c440524,0xfbe); + reg32_write(0x3c444124,0xfbe); + reg32_write(0x3c444524,0xfbe); + reg32_write(0x3c448124,0xfbe); + reg32_write(0x3c448524,0xfbe); + reg32_write(0x3c44c124,0xfbe); + reg32_write(0x3c44c524,0xfbe); + reg32_write(0x3c00010c,0x63); + reg32_write(0x3c00410c,0x63); + reg32_write(0x3c00810c,0x63); + reg32_write(0x3c00c10c,0x63); + reg32_write(0x3c01010c,0x63); + reg32_write(0x3c01410c,0x63); + reg32_write(0x3c01810c,0x63); + reg32_write(0x3c01c10c,0x63); + reg32_write(0x3c02010c,0x63); + reg32_write(0x3c02410c,0x63); + reg32_write(0x3c080060,0x3); + reg32_write(0x3c0801d4,0x4); + reg32_write(0x3c080140,0x0); + reg32_write(0x3c080020,0x320); + reg32_write(0x3c480020,0xa7); + reg32_write(0x3c080220,0x9); + reg32_write(0x3c0802c8,0xdc); + reg32_write(0x3c04010c,0x5a1); + reg32_write(0x3c04050c,0x5a1); + reg32_write(0x3c04410c,0x5a1); + reg32_write(0x3c04450c,0x5a1); + reg32_write(0x3c04810c,0x5a1); + reg32_write(0x3c04850c,0x5a1); + reg32_write(0x3c04c10c,0x5a1); + reg32_write(0x3c04c50c,0x5a1); + reg32_write(0x3c4802c8,0xdc); + reg32_write(0x3c44010c,0x5a1); + reg32_write(0x3c44050c,0x5a1); + reg32_write(0x3c44410c,0x5a1); + reg32_write(0x3c44450c,0x5a1); + reg32_write(0x3c44810c,0x5a1); + reg32_write(0x3c44850c,0x5a1); + reg32_write(0x3c44c10c,0x5a1); + reg32_write(0x3c44c50c,0x5a1); + reg32_write(0x3c0803e8,0x1); + reg32_write(0x3c4803e8,0x1); + reg32_write(0x3c080064,0x1); + reg32_write(0x3c480064,0x1); + reg32_write(0x3c0803c0,0x0); + reg32_write(0x3c0803c4,0x0); + reg32_write(0x3c0803c8,0x4444); + reg32_write(0x3c0803cc,0x8888); + reg32_write(0x3c0803d0,0x5555); + reg32_write(0x3c0803d4,0x0); + reg32_write(0x3c0803d8,0x0); + reg32_write(0x3c0803dc,0xf000); + reg32_write(0x3c080094,0x0); + reg32_write(0x3c0800b4,0x0); + reg32_write(0x3c4800b4,0x0); + reg32_write(0x3c08031c,0x80); + reg32_write(0x3c48031c,0x80); + reg32_write(0x3c080328,0x106); + reg32_write(0x3c480328,0x106); + + //enable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + //load the 1D training image + ddr_load_train_code(FW_1D_IMAGE); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x131f); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x110); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); + + //disable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + //Reset MPU and run + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); + wait_ddrphy_training_complete(); + + //configure DDRPHY-FW DMEM structure @clock1... + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + + //set the PHY input clock to the desired frequency for pstate 1 + reg32_write(0x3038a088,0x7070000); + reg32_write(0x3038a084,0x4030000); + reg32_write(0x303a00ec,0xffff); + tmp=reg32_read(0x303a00f8); + tmp |= 0x20; + reg32_write(0x303a00f8,tmp); + reg32_write(0x30360068,0xf5a406); + tmp=reg32_read(0x30360060); + tmp &= ~0x80; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp |= 0x200; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x20; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x10; + reg32_write(0x30360060,tmp); + do{ + tmp=reg32_read(0x30360060); + if(tmp&0x80000000) break; + }while(1); + reg32_write(0x30389808,0x1000000); + + //enable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + //load the 1D training image + ddr_load_train_code(FW_1D_IMAGE); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x29c); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x110); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x994); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x994); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x9400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3109); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x9400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3109); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); + + //disable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + //Reset MPU and run + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); + wait_ddrphy_training_complete(); + + //set the PHY input clock to the desired frequency for pstate 0 + reg32_write(0x3038a088,0x7070000); + reg32_write(0x3038a084,0x4030000); + reg32_write(0x303a00ec,0xffff); + tmp=reg32_read(0x303a00f8); + tmp |= 0x20; + reg32_write(0x303a00f8,tmp); + reg32_write(0x30360068,0xece580); + tmp=reg32_read(0x30360060); + tmp &= ~0x80; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp |= 0x200; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x20; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x10; + reg32_write(0x30360060,tmp); + do{ + tmp=reg32_read(0x30360060); + if(tmp&0x80000000) break; + }while(1); + reg32_write(0x30389808,0x1000000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + + + //enable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + //load the 2D training image + ddr_load_train_code(FW_2D_IMAGE); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x110); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); + + //disable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + //Reset MPU and run + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); + wait_ddrphy_training_complete(); + + //Halt MPU + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); + //enable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + + //Load firmware PIE image + reg32_write(0x3c240000,0x10); + reg32_write(0x3c240004,0x400); + reg32_write(0x3c240008,0x10e); + reg32_write(0x3c24000c,0x0); + reg32_write(0x3c240010,0x0); + reg32_write(0x3c240014,0x8); + reg32_write(0x3c2400a4,0xb); + reg32_write(0x3c2400a8,0x480); + reg32_write(0x3c2400ac,0x109); + reg32_write(0x3c2400b0,0x8); + reg32_write(0x3c2400b4,0x448); + reg32_write(0x3c2400b8,0x139); + reg32_write(0x3c2400bc,0x8); + reg32_write(0x3c2400c0,0x478); + reg32_write(0x3c2400c4,0x109); + reg32_write(0x3c2400c8,0x0); + reg32_write(0x3c2400cc,0xe8); + reg32_write(0x3c2400d0,0x109); + reg32_write(0x3c2400d4,0x2); + reg32_write(0x3c2400d8,0x10); + reg32_write(0x3c2400dc,0x139); + reg32_write(0x3c2400e0,0xf); + reg32_write(0x3c2400e4,0x7c0); + reg32_write(0x3c2400e8,0x139); + reg32_write(0x3c2400ec,0x44); + reg32_write(0x3c2400f0,0x630); + reg32_write(0x3c2400f4,0x159); + reg32_write(0x3c2400f8,0x14f); + reg32_write(0x3c2400fc,0x630); + reg32_write(0x3c240100,0x159); + reg32_write(0x3c240104,0x47); + reg32_write(0x3c240108,0x630); + reg32_write(0x3c24010c,0x149); + reg32_write(0x3c240110,0x4f); + reg32_write(0x3c240114,0x630); + reg32_write(0x3c240118,0x179); + reg32_write(0x3c24011c,0x8); + reg32_write(0x3c240120,0xe0); + reg32_write(0x3c240124,0x109); + reg32_write(0x3c240128,0x0); + reg32_write(0x3c24012c,0x7c8); + reg32_write(0x3c240130,0x109); + reg32_write(0x3c240134,0x0); + reg32_write(0x3c240138,0x1); + reg32_write(0x3c24013c,0x8); + reg32_write(0x3c240140,0x0); + reg32_write(0x3c240144,0x45a); + reg32_write(0x3c240148,0x9); + reg32_write(0x3c24014c,0x0); + reg32_write(0x3c240150,0x448); + reg32_write(0x3c240154,0x109); + reg32_write(0x3c240158,0x40); + reg32_write(0x3c24015c,0x630); + reg32_write(0x3c240160,0x179); + reg32_write(0x3c240164,0x1); + reg32_write(0x3c240168,0x618); + reg32_write(0x3c24016c,0x109); + reg32_write(0x3c240170,0x40c0); + reg32_write(0x3c240174,0x630); + reg32_write(0x3c240178,0x149); + reg32_write(0x3c24017c,0x8); + reg32_write(0x3c240180,0x4); + reg32_write(0x3c240184,0x48); + reg32_write(0x3c240188,0x4040); + reg32_write(0x3c24018c,0x630); + reg32_write(0x3c240190,0x149); + reg32_write(0x3c240194,0x0); + reg32_write(0x3c240198,0x4); + reg32_write(0x3c24019c,0x48); + reg32_write(0x3c2401a0,0x40); + reg32_write(0x3c2401a4,0x630); + reg32_write(0x3c2401a8,0x149); + reg32_write(0x3c2401ac,0x10); + reg32_write(0x3c2401b0,0x4); + reg32_write(0x3c2401b4,0x18); + reg32_write(0x3c2401b8,0x0); + reg32_write(0x3c2401bc,0x4); + reg32_write(0x3c2401c0,0x78); + reg32_write(0x3c2401c4,0x549); + reg32_write(0x3c2401c8,0x630); + reg32_write(0x3c2401cc,0x159); + reg32_write(0x3c2401d0,0xd49); + reg32_write(0x3c2401d4,0x630); + reg32_write(0x3c2401d8,0x159); + reg32_write(0x3c2401dc,0x94a); + reg32_write(0x3c2401e0,0x630); + reg32_write(0x3c2401e4,0x159); + reg32_write(0x3c2401e8,0x441); + reg32_write(0x3c2401ec,0x630); + reg32_write(0x3c2401f0,0x149); + reg32_write(0x3c2401f4,0x42); + reg32_write(0x3c2401f8,0x630); + reg32_write(0x3c2401fc,0x149); + reg32_write(0x3c240200,0x1); + reg32_write(0x3c240204,0x630); + reg32_write(0x3c240208,0x149); + reg32_write(0x3c24020c,0x0); + reg32_write(0x3c240210,0xe0); + reg32_write(0x3c240214,0x109); + reg32_write(0x3c240218,0xa); + reg32_write(0x3c24021c,0x10); + reg32_write(0x3c240220,0x109); + reg32_write(0x3c240224,0x9); + reg32_write(0x3c240228,0x3c0); + reg32_write(0x3c24022c,0x149); + reg32_write(0x3c240230,0x9); + reg32_write(0x3c240234,0x3c0); + reg32_write(0x3c240238,0x159); + reg32_write(0x3c24023c,0x18); + reg32_write(0x3c240240,0x10); + reg32_write(0x3c240244,0x109); + reg32_write(0x3c240248,0x0); + reg32_write(0x3c24024c,0x3c0); + reg32_write(0x3c240250,0x109); + reg32_write(0x3c240254,0x18); + reg32_write(0x3c240258,0x4); + reg32_write(0x3c24025c,0x48); + reg32_write(0x3c240260,0x18); + reg32_write(0x3c240264,0x4); + reg32_write(0x3c240268,0x58); + reg32_write(0x3c24026c,0xa); + reg32_write(0x3c240270,0x10); + reg32_write(0x3c240274,0x109); + reg32_write(0x3c240278,0x2); + reg32_write(0x3c24027c,0x10); + reg32_write(0x3c240280,0x109); + reg32_write(0x3c240284,0x5); + reg32_write(0x3c240288,0x7c0); + reg32_write(0x3c24028c,0x109); + reg32_write(0x3c240290,0x10); + reg32_write(0x3c240294,0x10); + reg32_write(0x3c240298,0x109); + reg32_write(0x3c100000,0x811); + reg32_write(0x3c100080,0x880); + reg32_write(0x3c100100,0x0); + reg32_write(0x3c100180,0x0); + reg32_write(0x3c100004,0x4008); + reg32_write(0x3c100084,0x83); + reg32_write(0x3c100104,0x4f); + reg32_write(0x3c100184,0x0); + reg32_write(0x3c100008,0x4040); + reg32_write(0x3c100088,0x83); + reg32_write(0x3c100108,0x51); + reg32_write(0x3c100188,0x0); + reg32_write(0x3c10000c,0x811); + reg32_write(0x3c10008c,0x880); + reg32_write(0x3c10010c,0x0); + reg32_write(0x3c10018c,0x0); + reg32_write(0x3c100010,0x720); + reg32_write(0x3c100090,0xf); + reg32_write(0x3c100110,0x1740); + reg32_write(0x3c100190,0x0); + reg32_write(0x3c100014,0x16); + reg32_write(0x3c100094,0x83); + reg32_write(0x3c100114,0x4b); + reg32_write(0x3c100194,0x0); + reg32_write(0x3c100018,0x716); + reg32_write(0x3c100098,0xf); + reg32_write(0x3c100118,0x2001); + reg32_write(0x3c100198,0x0); + reg32_write(0x3c10001c,0x716); + reg32_write(0x3c10009c,0xf); + reg32_write(0x3c10011c,0x2800); + reg32_write(0x3c10019c,0x0); + reg32_write(0x3c100020,0x716); + reg32_write(0x3c1000a0,0xf); + reg32_write(0x3c100120,0xf00); + reg32_write(0x3c1001a0,0x0); + reg32_write(0x3c100024,0x720); + reg32_write(0x3c1000a4,0xf); + reg32_write(0x3c100124,0x1400); + reg32_write(0x3c1001a4,0x0); + reg32_write(0x3c100028,0xe08); + reg32_write(0x3c1000a8,0xc15); + reg32_write(0x3c100128,0x0); + reg32_write(0x3c1001a8,0x0); + reg32_write(0x3c10002c,0x623); + reg32_write(0x3c1000ac,0x15); + reg32_write(0x3c10012c,0x0); + reg32_write(0x3c1001ac,0x0); + reg32_write(0x3c100030,0x4028); + reg32_write(0x3c1000b0,0x80); + reg32_write(0x3c100130,0x0); + reg32_write(0x3c1001b0,0x0); + reg32_write(0x3c100034,0xe08); + reg32_write(0x3c1000b4,0xc1a); + reg32_write(0x3c100134,0x0); + reg32_write(0x3c1001b4,0x0); + reg32_write(0x3c100038,0x623); + reg32_write(0x3c1000b8,0x1a); + reg32_write(0x3c100138,0x0); + reg32_write(0x3c1001b8,0x0); + reg32_write(0x3c10003c,0x4040); + reg32_write(0x3c1000bc,0x80); + reg32_write(0x3c10013c,0x0); + reg32_write(0x3c1001bc,0x0); + reg32_write(0x3c100040,0x2604); + reg32_write(0x3c1000c0,0x15); + reg32_write(0x3c100140,0x0); + reg32_write(0x3c1001c0,0x0); + reg32_write(0x3c100044,0x708); + reg32_write(0x3c1000c4,0x5); + reg32_write(0x3c100144,0x0); + reg32_write(0x3c1001c4,0x2002); + reg32_write(0x3c100048,0x8); + reg32_write(0x3c1000c8,0x80); + reg32_write(0x3c100148,0x0); + reg32_write(0x3c1001c8,0x0); + reg32_write(0x3c10004c,0x2604); + reg32_write(0x3c1000cc,0x1a); + reg32_write(0x3c10014c,0x0); + reg32_write(0x3c1001cc,0x0); + reg32_write(0x3c100050,0x708); + reg32_write(0x3c1000d0,0xa); + reg32_write(0x3c100150,0x0); + reg32_write(0x3c1001d0,0x2002); + reg32_write(0x3c100054,0x4040); + reg32_write(0x3c1000d4,0x80); + reg32_write(0x3c100154,0x0); + reg32_write(0x3c1001d4,0x0); + reg32_write(0x3c100058,0x60a); + reg32_write(0x3c1000d8,0x15); + reg32_write(0x3c100158,0x1200); + reg32_write(0x3c1001d8,0x0); + reg32_write(0x3c10005c,0x61a); + reg32_write(0x3c1000dc,0x15); + reg32_write(0x3c10015c,0x1300); + reg32_write(0x3c1001dc,0x0); + reg32_write(0x3c100060,0x60a); + reg32_write(0x3c1000e0,0x1a); + reg32_write(0x3c100160,0x1200); + reg32_write(0x3c1001e0,0x0); + reg32_write(0x3c100064,0x642); + reg32_write(0x3c1000e4,0x1a); + reg32_write(0x3c100164,0x1300); + reg32_write(0x3c1001e4,0x0); + reg32_write(0x3c100068,0x4808); + reg32_write(0x3c1000e8,0x880); + reg32_write(0x3c100168,0x0); + reg32_write(0x3c1001e8,0x0); + reg32_write(0x3c24029c,0x0); + reg32_write(0x3c2402a0,0x790); + reg32_write(0x3c2402a4,0x11a); + reg32_write(0x3c2402a8,0x8); + reg32_write(0x3c2402ac,0x7aa); + reg32_write(0x3c2402b0,0x2a); + reg32_write(0x3c2402b4,0x10); + reg32_write(0x3c2402b8,0x7b2); + reg32_write(0x3c2402bc,0x2a); + reg32_write(0x3c2402c0,0x0); + reg32_write(0x3c2402c4,0x7c8); + reg32_write(0x3c2402c8,0x109); + reg32_write(0x3c2402cc,0x10); + reg32_write(0x3c2402d0,0x2a8); + reg32_write(0x3c2402d4,0x129); + reg32_write(0x3c2402d8,0x8); + reg32_write(0x3c2402dc,0x370); + reg32_write(0x3c2402e0,0x129); + reg32_write(0x3c2402e4,0xa); + reg32_write(0x3c2402e8,0x3c8); + reg32_write(0x3c2402ec,0x1a9); + reg32_write(0x3c2402f0,0xc); + reg32_write(0x3c2402f4,0x408); + reg32_write(0x3c2402f8,0x199); + reg32_write(0x3c2402fc,0x14); + reg32_write(0x3c240300,0x790); + reg32_write(0x3c240304,0x11a); + reg32_write(0x3c240308,0x8); + reg32_write(0x3c24030c,0x4); + reg32_write(0x3c240310,0x18); + reg32_write(0x3c240314,0xe); + reg32_write(0x3c240318,0x408); + reg32_write(0x3c24031c,0x199); + reg32_write(0x3c240320,0x8); + reg32_write(0x3c240324,0x8568); + reg32_write(0x3c240328,0x108); + reg32_write(0x3c24032c,0x18); + reg32_write(0x3c240330,0x790); + reg32_write(0x3c240334,0x16a); + reg32_write(0x3c240338,0x8); + reg32_write(0x3c24033c,0x1d8); + reg32_write(0x3c240340,0x169); + reg32_write(0x3c240344,0x10); + reg32_write(0x3c240348,0x8558); + reg32_write(0x3c24034c,0x168); + reg32_write(0x3c240350,0x70); + reg32_write(0x3c240354,0x788); + reg32_write(0x3c240358,0x16a); + reg32_write(0x3c24035c,0x1ff8); + reg32_write(0x3c240360,0x85a8); + reg32_write(0x3c240364,0x1e8); + reg32_write(0x3c240368,0x50); + reg32_write(0x3c24036c,0x798); + reg32_write(0x3c240370,0x16a); + reg32_write(0x3c240374,0x60); + reg32_write(0x3c240378,0x7a0); + reg32_write(0x3c24037c,0x16a); + reg32_write(0x3c240380,0x8); + reg32_write(0x3c240384,0x8310); + reg32_write(0x3c240388,0x168); + reg32_write(0x3c24038c,0x8); + reg32_write(0x3c240390,0xa310); + reg32_write(0x3c240394,0x168); + reg32_write(0x3c240398,0xa); + reg32_write(0x3c24039c,0x408); + reg32_write(0x3c2403a0,0x169); + reg32_write(0x3c2403a4,0x6e); + reg32_write(0x3c2403a8,0x0); + reg32_write(0x3c2403ac,0x68); + reg32_write(0x3c2403b0,0x0); + reg32_write(0x3c2403b4,0x408); + reg32_write(0x3c2403b8,0x169); + reg32_write(0x3c2403bc,0x0); + reg32_write(0x3c2403c0,0x8310); + reg32_write(0x3c2403c4,0x168); + reg32_write(0x3c2403c8,0x0); + reg32_write(0x3c2403cc,0xa310); + reg32_write(0x3c2403d0,0x168); + reg32_write(0x3c2403d4,0x1ff8); + reg32_write(0x3c2403d8,0x85a8); + reg32_write(0x3c2403dc,0x1e8); + reg32_write(0x3c2403e0,0x68); + reg32_write(0x3c2403e4,0x798); + reg32_write(0x3c2403e8,0x16a); + reg32_write(0x3c2403ec,0x78); + reg32_write(0x3c2403f0,0x7a0); + reg32_write(0x3c2403f4,0x16a); + reg32_write(0x3c2403f8,0x68); + reg32_write(0x3c2403fc,0x790); + reg32_write(0x3c240400,0x16a); + reg32_write(0x3c240404,0x8); + reg32_write(0x3c240408,0x8b10); + reg32_write(0x3c24040c,0x168); + reg32_write(0x3c240410,0x8); + reg32_write(0x3c240414,0xab10); + reg32_write(0x3c240418,0x168); + reg32_write(0x3c24041c,0xa); + reg32_write(0x3c240420,0x408); + reg32_write(0x3c240424,0x169); + reg32_write(0x3c240428,0x58); + reg32_write(0x3c24042c,0x0); + reg32_write(0x3c240430,0x68); + reg32_write(0x3c240434,0x0); + reg32_write(0x3c240438,0x408); + reg32_write(0x3c24043c,0x169); + reg32_write(0x3c240440,0x0); + reg32_write(0x3c240444,0x8b10); + reg32_write(0x3c240448,0x168); + reg32_write(0x3c24044c,0x0); + reg32_write(0x3c240450,0xab10); + reg32_write(0x3c240454,0x168); + reg32_write(0x3c240458,0x0); + reg32_write(0x3c24045c,0x1d8); + reg32_write(0x3c240460,0x169); + reg32_write(0x3c240464,0x80); + reg32_write(0x3c240468,0x790); + reg32_write(0x3c24046c,0x16a); + reg32_write(0x3c240470,0x18); + reg32_write(0x3c240474,0x7aa); + reg32_write(0x3c240478,0x6a); + reg32_write(0x3c24047c,0xa); + reg32_write(0x3c240480,0x0); + reg32_write(0x3c240484,0x1e9); + reg32_write(0x3c240488,0x8); + reg32_write(0x3c24048c,0x8080); + reg32_write(0x3c240490,0x108); + reg32_write(0x3c240494,0xf); + reg32_write(0x3c240498,0x408); + reg32_write(0x3c24049c,0x169); + reg32_write(0x3c2404a0,0xc); + reg32_write(0x3c2404a4,0x0); + reg32_write(0x3c2404a8,0x68); + reg32_write(0x3c2404ac,0x9); + reg32_write(0x3c2404b0,0x0); + reg32_write(0x3c2404b4,0x1a9); + reg32_write(0x3c2404b8,0x0); + reg32_write(0x3c2404bc,0x408); + reg32_write(0x3c2404c0,0x169); + reg32_write(0x3c2404c4,0x0); + reg32_write(0x3c2404c8,0x8080); + reg32_write(0x3c2404cc,0x108); + reg32_write(0x3c2404d0,0x8); + reg32_write(0x3c2404d4,0x7aa); + reg32_write(0x3c2404d8,0x6a); + reg32_write(0x3c2404dc,0x0); + reg32_write(0x3c2404e0,0x8568); + reg32_write(0x3c2404e4,0x108); + reg32_write(0x3c2404e8,0xb7); + reg32_write(0x3c2404ec,0x790); + reg32_write(0x3c2404f0,0x16a); + reg32_write(0x3c2404f4,0x1f); + reg32_write(0x3c2404f8,0x0); + reg32_write(0x3c2404fc,0x68); + reg32_write(0x3c240500,0x8); + reg32_write(0x3c240504,0x8558); + reg32_write(0x3c240508,0x168); + reg32_write(0x3c24050c,0xf); + reg32_write(0x3c240510,0x408); + reg32_write(0x3c240514,0x169); + reg32_write(0x3c240518,0xc); + reg32_write(0x3c24051c,0x0); + reg32_write(0x3c240520,0x68); + reg32_write(0x3c240524,0x0); + reg32_write(0x3c240528,0x408); + reg32_write(0x3c24052c,0x169); + reg32_write(0x3c240530,0x0); + reg32_write(0x3c240534,0x8558); + reg32_write(0x3c240538,0x168); + reg32_write(0x3c24053c,0x8); + reg32_write(0x3c240540,0x3c8); + reg32_write(0x3c240544,0x1a9); + reg32_write(0x3c240548,0x3); + reg32_write(0x3c24054c,0x370); + reg32_write(0x3c240550,0x129); + reg32_write(0x3c240554,0x20); + reg32_write(0x3c240558,0x2aa); + reg32_write(0x3c24055c,0x9); + reg32_write(0x3c240560,0x0); + reg32_write(0x3c240564,0x400); + reg32_write(0x3c240568,0x10e); + reg32_write(0x3c24056c,0x8); + reg32_write(0x3c240570,0xe8); + reg32_write(0x3c240574,0x109); + reg32_write(0x3c240578,0x0); + reg32_write(0x3c24057c,0x8140); + reg32_write(0x3c240580,0x10c); + reg32_write(0x3c240584,0x10); + reg32_write(0x3c240588,0x8138); + reg32_write(0x3c24058c,0x10c); + reg32_write(0x3c240590,0x8); + reg32_write(0x3c240594,0x7c8); + reg32_write(0x3c240598,0x101); + reg32_write(0x3c24059c,0x8); + reg32_write(0x3c2405a0,0x0); + reg32_write(0x3c2405a4,0x8); + reg32_write(0x3c2405a8,0x8); + reg32_write(0x3c2405ac,0x448); + reg32_write(0x3c2405b0,0x109); + reg32_write(0x3c2405b4,0xf); + reg32_write(0x3c2405b8,0x7c0); + reg32_write(0x3c2405bc,0x109); + reg32_write(0x3c2405c0,0x0); + reg32_write(0x3c2405c4,0xe8); + reg32_write(0x3c2405c8,0x109); + reg32_write(0x3c2405cc,0x47); + reg32_write(0x3c2405d0,0x630); + reg32_write(0x3c2405d4,0x109); + reg32_write(0x3c2405d8,0x8); + reg32_write(0x3c2405dc,0x618); + reg32_write(0x3c2405e0,0x109); + reg32_write(0x3c2405e4,0x8); + reg32_write(0x3c2405e8,0xe0); + reg32_write(0x3c2405ec,0x109); + reg32_write(0x3c2405f0,0x0); + reg32_write(0x3c2405f4,0x7c8); + reg32_write(0x3c2405f8,0x109); + reg32_write(0x3c2405fc,0x8); + reg32_write(0x3c240600,0x8140); + reg32_write(0x3c240604,0x10c); + reg32_write(0x3c240608,0x0); + reg32_write(0x3c24060c,0x1); + reg32_write(0x3c240610,0x8); + reg32_write(0x3c240614,0x8); + reg32_write(0x3c240618,0x4); + reg32_write(0x3c24061c,0x8); + reg32_write(0x3c240620,0x8); + reg32_write(0x3c240624,0x7c8); + reg32_write(0x3c240628,0x101); + reg32_write(0x3c240018,0x0); + reg32_write(0x3c24001c,0x0); + reg32_write(0x3c240020,0x8); + reg32_write(0x3c240024,0x0); + reg32_write(0x3c240028,0x0); + reg32_write(0x3c24002c,0x0); + reg32_write(0x3c34039c,0x400); + reg32_write(0x3c24005c,0x0); + reg32_write(0x3c24007c,0x2a); + reg32_write(0x3c240098,0x6a); + reg32_write(0x3c100340,0x0); + reg32_write(0x3c100344,0x101); + reg32_write(0x3c100348,0x105); + reg32_write(0x3c10034c,0x107); + reg32_write(0x3c100350,0x10f); + reg32_write(0x3c100354,0x202); + reg32_write(0x3c100358,0x20a); + reg32_write(0x3c10035c,0x20b); + reg32_write(0x3c0800e8,0x2); + reg32_write(0x3c08002c,0x64); + reg32_write(0x3c080030,0xc8); + reg32_write(0x3c080034,0x7d0); + reg32_write(0x3c080038,0x2c); + reg32_write(0x3c48002c,0x14); + reg32_write(0x3c480030,0x29); + reg32_write(0x3c480034,0x1a1); + reg32_write(0x3c480038,0x10); + reg32_write(0x3c240030,0x0); + reg32_write(0x3c240034,0x173); + reg32_write(0x3c240038,0x60); + reg32_write(0x3c24003c,0x6110); + reg32_write(0x3c240040,0x2152); + reg32_write(0x3c240044,0xdfbd); + reg32_write(0x3c240048,0x60); + reg32_write(0x3c24004c,0x6152); + reg32_write(0x3c080040,0x5a); + reg32_write(0x3c080044,0x3); + reg32_write(0x3c480040,0x5a); + reg32_write(0x3c480044,0x3); + reg32_write(0x3c100200,0xe0); + reg32_write(0x3c100204,0x12); + reg32_write(0x3c100208,0xe0); + reg32_write(0x3c10020c,0x12); + reg32_write(0x3c100210,0xe0); + reg32_write(0x3c100214,0x12); + reg32_write(0x3c500200,0xe0); + reg32_write(0x3c500204,0x12); + reg32_write(0x3c500208,0xe0); + reg32_write(0x3c50020c,0x12); + reg32_write(0x3c500210,0xe0); + reg32_write(0x3c500214,0x12); + reg32_write(0x3c1003f4,0xf); + reg32_write(0x3c040044,0x1); + reg32_write(0x3c040048,0x1); + reg32_write(0x3c04004c,0x180); + reg32_write(0x3c040060,0x1); + reg32_write(0x3c040008,0x6209); + reg32_write(0x3c0402c8,0x1); + reg32_write(0x3c0406d0,0x1); + reg32_write(0x3c040ad0,0x1); + reg32_write(0x3c040ed0,0x1); + reg32_write(0x3c0412d0,0x1); + reg32_write(0x3c0416d0,0x1); + reg32_write(0x3c041ad0,0x1); + reg32_write(0x3c041ed0,0x1); + reg32_write(0x3c0422d0,0x1); + reg32_write(0x3c044044,0x1); + reg32_write(0x3c044048,0x1); + reg32_write(0x3c04404c,0x180); + reg32_write(0x3c044060,0x1); + reg32_write(0x3c044008,0x6209); + reg32_write(0x3c0442c8,0x1); + reg32_write(0x3c0446d0,0x1); + reg32_write(0x3c044ad0,0x1); + reg32_write(0x3c044ed0,0x1); + reg32_write(0x3c0452d0,0x1); + reg32_write(0x3c0456d0,0x1); + reg32_write(0x3c045ad0,0x1); + reg32_write(0x3c045ed0,0x1); + reg32_write(0x3c0462d0,0x1); + reg32_write(0x3c048044,0x1); + reg32_write(0x3c048048,0x1); + reg32_write(0x3c04804c,0x180); + reg32_write(0x3c048060,0x1); + reg32_write(0x3c048008,0x6209); + reg32_write(0x3c0482c8,0x1); + reg32_write(0x3c0486d0,0x1); + reg32_write(0x3c048ad0,0x1); + reg32_write(0x3c048ed0,0x1); + reg32_write(0x3c0492d0,0x1); + reg32_write(0x3c0496d0,0x1); + reg32_write(0x3c049ad0,0x1); + reg32_write(0x3c049ed0,0x1); + reg32_write(0x3c04a2d0,0x1); + reg32_write(0x3c04c044,0x1); + reg32_write(0x3c04c048,0x1); + reg32_write(0x3c04c04c,0x180); + reg32_write(0x3c04c060,0x1); + reg32_write(0x3c04c008,0x6209); + reg32_write(0x3c04c2c8,0x1); + reg32_write(0x3c04c6d0,0x1); + reg32_write(0x3c04cad0,0x1); + reg32_write(0x3c04ced0,0x1); + reg32_write(0x3c04d2d0,0x1); + reg32_write(0x3c04d6d0,0x1); + reg32_write(0x3c04dad0,0x1); + reg32_write(0x3c04ded0,0x1); + reg32_write(0x3c04e2d0,0x1); + reg32_write(0x3c0800e8,0x2); + reg32_write(0x3c300200,0x2); + //customer Post Train + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001); + /* + * CalBusy.0 =1, indicates the calibrator is actively calibrating. + * Wait Calibrating done. + */ + tmp_t = 1; + while(tmp_t) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097); + tmp_t = tmp & 0x01; + } + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); + //disable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); +} diff --git a/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg new file mode 100644 index 0000000000..aff8321b9a --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg @@ -0,0 +1,5 @@ +soc imx8mq + +loadaddr 0x007E1000 +max_load_size 0x3F000 +dcdofs 0x400 diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c new file mode 100644 index 0000000000..cfee13f3e7 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Christian Hemp + */ + +#include <common.h> +#include <linux/sizes.h> +#include <mach/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx8-ccm-regs.h> +#include <mach/iomux-mx8.h> +#include <mach/imx8-ddrc.h> +#include <mach/xload.h> +#include <io.h> +#include <debug_ll.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/mmu.h> +#include <mach/atf.h> +#include <mach/esdctl.h> + +#include "ddr.h" + +extern char __dtb_imx8mq_phytec_phycore_som_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) + +static void setup_uart(void) +{ + void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); + void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); + + writel(CCM_CCGR_SETTINGn_NEEDED(0), + ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); + writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK, + ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); + writel(CCM_CCGR_SETTINGn_NEEDED(0), + ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + + imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + + imx8_uart_setup_ll(); + + putc_ll('>'); +} + +static void phytec_imx8mq_som_sram_setup(void) +{ + enum bootsource src = BOOTSOURCE_UNKNOWN; + int instance = BOOTSOURCE_INSTANCE_UNKNOWN; + int ret = -ENOTSUPP; + + ddr_init(); + + imx8_get_boot_source(&src, &instance); + + if (src == BOOTSOURCE_MMC) + ret = imx8_esdhc_start_image(instance); + + BUG_ON(ret); +} + +/* + * Power-on execution flow of start_phytec_phycore_imx8mq() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time + * + * 2. DDR is initialized and full i.MX image is loaded to the + * beginning of RAM + * + * 3. start_phytec_phycore_imx8mq, now in RAM, is executed again + * + * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it + * + * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, + * executing start_phytec_phycore_imx8mq() the third time + * + * 6. Standard barebox boot flow continues + */ +ENTRY_FUNCTION(start_phytec_phycore_imx8mq, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) { + /* + * We assume that we were just loaded by MaskROM into + * SRAM if we are not running from DDR. We also assume + * that means DDR needs to be initialized for the + * first time. + */ + phytec_imx8mq_som_sram_setup(); + } + /* + * Straight from the power-on we are at EL3, so the following + * code _will_ load and jump to ATF. + * + * However when we are re-executed upon exit from ATF's + * initialization routine, it is EL2 which means we'll skip + * loadting ATF blob again + */ + if (current_el() == 3) { + const u8 *bl31; + size_t bl31_size; + + get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size); + imx8mq_atf_load_bl31(bl31, bl31_size); + } + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mq_barebox_entry(__dtb_imx8mq_phytec_phycore_som_start); +} diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig index aa0a78ad93..4571ef6902 100644 --- a/arch/arm/configs/imx_v8_defconfig +++ b/arch/arm/configs/imx_v8_defconfig @@ -2,6 +2,7 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y CONFIG_MACH_ZII_IMX8MQ_DEV=y CONFIG_MACH_NXP_IMX8MQ_EVK=y +CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_MMU=y CONFIG_MALLOC_SIZE=0x0 @@ -81,6 +82,7 @@ CONFIG_OFDEVICE=y CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_SERIAL_DEV_BUS=y CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_DP83867_PHY=y CONFIG_MICREL_PHY=y CONFIG_NET_DSA_MV88E6XXX=y CONFIG_MDIO_BITBANG=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3cdee1ffb7..917a1eb0b7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -67,6 +67,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6ull-phytec-phycore-som-lc.dtb.o \ imx6ull-phytec-phycore-som.dtb.o pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o +pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts index 7e4a5aba2a..e602b77e99 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts @@ -52,17 +52,20 @@ &usdhc1 { status = "okay"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; }; }; diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts index ffcbdc2134..77f143438b 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts @@ -47,16 +47,19 @@ &usdhc1 { status = "okay"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; }; }; diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi index 63dd966b87..66b547ad8e 100644 --- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi +++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi @@ -131,22 +131,26 @@ pinctrl-0 = <&pinctrl_gpmi_nand>; nand-on-flash-bbt; status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0x400000>; - }; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - environment_nand: partition@400000 { - label = "barebox-environment"; - reg = <0x400000 0x20000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; - partition@420000 { - label = "root"; - reg = <0x420000 0x0>; + environment_nand: partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x20000>; + }; + + partition@420000 { + label = "root"; + reg = <0x420000 0x0>; + }; }; }; diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts index 6e12b26d38..94a70389f0 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts @@ -51,17 +51,20 @@ &usdhc1 { status = "okay"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; }; }; diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts index d9e37b7fca..6d82ec34d6 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts @@ -56,16 +56,19 @@ &usdhc1 { status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; - - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; }; }; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index 8bb9ec8db7..aba86a3ec1 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -58,27 +58,30 @@ &ecspi3 { flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "barebox-environment"; - reg = <0x100000 0x20000>; - }; - - partition@120000 { - label = "oftree"; - reg = <0x120000 0x20000>; - }; - - partition@140000 { - label = "kernel"; - reg = <0x140000 0x0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "barebox-environment"; + reg = <0x100000 0x20000>; + }; + + partition@120000 { + label = "oftree"; + reg = <0x120000 0x20000>; + }; + + partition@140000 { + label = "kernel"; + reg = <0x140000 0x0>; + }; }; }; }; @@ -101,22 +104,25 @@ }; &gpmi { - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0x400000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; - partition@400000 { - label = "barebox-environment"; - reg = <0x400000 0x100000>; - }; + partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; - partition@500000 { - label = "root"; - reg = <0x500000 0x0>; + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; }; }; diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi index 3c197ddf01..8fde27bd0c 100644 --- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi @@ -76,27 +76,30 @@ reg = <0>; status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "barebox-environment"; - reg = <0x100000 0x20000>; - }; - - partition@120000 { - label = "oftree"; - reg = <0x120000 0x20000>; - }; - - partition@140000 { - label = "kernel"; - reg = <0x140000 0x0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "barebox-environment"; + reg = <0x100000 0x20000>; + }; + + partition@120000 { + label = "oftree"; + reg = <0x120000 0x20000>; + }; + + partition@140000 { + label = "kernel"; + reg = <0x140000 0x0>; + }; }; }; }; @@ -126,22 +129,26 @@ pinctrl-0 = <&pinctrl_gpmi_nand>; nand-on-flash-bbt; status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0x400000>; - }; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@400000 { - label = "barebox-environment"; - reg = <0x400000 0x100000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; - partition@500000 { - label = "root"; - reg = <0x500000 0x0>; + partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; }; }; diff --git a/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts index c2756142b5..437457ce75 100644 --- a/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts @@ -54,16 +54,19 @@ &usdhc1 { status = "okay"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; }; }; diff --git a/arch/arm/dts/imx6ul-liteboard.dts b/arch/arm/dts/imx6ul-liteboard.dts index 03a4bfc784..eb34e11ddb 100644 --- a/arch/arm/dts/imx6ul-liteboard.dts +++ b/arch/arm/dts/imx6ul-liteboard.dts @@ -42,6 +42,7 @@ */ #include <arm/imx6ul-liteboard.dts> +#include "imx6ul-litesom.dtsi" / { chosen { diff --git a/arch/arm/dts/imx6ul-litesom.dtsi b/arch/arm/dts/imx6ul-litesom.dtsi new file mode 100644 index 0000000000..8b73bfdd6f --- /dev/null +++ b/arch/arm/dts/imx6ul-litesom.dtsi @@ -0,0 +1,8 @@ +/* + * Include file to switch board DTS from using hardcoded memory node + * to dynamic memory size detection based on DDR controller settings + */ + +/ { + /delete-node/ memory@80000000; +}; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi index 398546d7b9..964f91950d 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -51,22 +51,25 @@ nand-on-flash-bbt; status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "barebox"; - reg = <0x0 0x400000>; - }; + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; - partition@400000 { - label = "barebox-environment"; - reg = <0x400000 0x100000>; - }; + partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; - partition@500000 { - label = "root"; - reg = <0x500000 0x0>; + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; }; }; diff --git a/arch/arm/dts/imx8mq-phytec-phycore-som.dts b/arch/arm/dts/imx8mq-phytec-phycore-som.dts new file mode 100644 index 0000000000..de8ed1873f --- /dev/null +++ b/arch/arm/dts/imx8mq-phytec-phycore-som.dts @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Christian Hemp <christian.hemp@posteo.de> + */ + +/dts-v1/; + +#include <arm64/freescale/imx8mq.dtsi> +#include <dt-bindings/net/ti-dp83867.h> +#include "imx8mq.dtsi" +#include "imx8mq-ddrc.dtsi" + +/ { + model = "Phytec phyCORE-i.MX8"; + compatible = "phytec,imx8mq-pcl066", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &bareboxenvemmc; + status = "disabled"; + }; + + environment-sd { + compatible = "barebox,environment"; + device-path = &bareboxenvsd; + status = "disabled"; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + enet-phy-lane-no-swap; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <975000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1675000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1625000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3625000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec1 0x640>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vqmmc-supply = <&sw4_reg>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + bareboxenvemmc: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + bareboxenvsd: artition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; +}; diff --git a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts index b2b3a560b5..dd4379bd59 100644 --- a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts +++ b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts @@ -37,3 +37,7 @@ >; }; }; + +&usb_hub { + swap-dx-lanes = <0>; +}; diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi index a6b2b89662..ccf80d3de8 100644 --- a/arch/arm/dts/imx8mq-zii-ultra.dtsi +++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi @@ -37,6 +37,18 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; }; &fec1 { @@ -214,6 +226,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + + usb_hub: usb2513b@2c { + compatible = "microchip,usb2513b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2513b>; + reg = <0x2c>; + reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + }; }; &i2c4 { @@ -227,6 +247,41 @@ barebox,provide-mac-address = <&fec1 0x640>; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; + + host@0 { + reg = <0 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + i210: i210@0 { + reg = <0 0 0 0 0>; + }; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -264,6 +319,24 @@ }; }; +&usb_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb3_phy1 { + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -344,6 +417,20 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x76 + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x76 + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16 + >; + }; + pinctrl_reg_usdhc2: regusdhc2grpgpio { fsl,pins = < MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -364,6 +451,12 @@ >; }; + pinctrl_usb2513b: usb2513bgrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index 1ddb51f898..d6a4c715bd 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -4,6 +4,7 @@ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> */ +#include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/thermal/thermal.h> / { @@ -106,6 +107,67 @@ reg = <0x30350000 0x10000>; clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; }; + + src: src@30390000 { + compatible = "fsl,imx8mq-src", "syscon"; + reg = <0x30390000 0x10000>; + #reset-cells = <1>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc"; + reg = <0x303a0000 0x10000>; + #power-domain-cells = <1>; + + interrupt-controller; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + /* + * As per comment in ATF source code: + * + * PCIE1 and PCIE2 share the + * same reset signal, if we power + * down PCIE2, PCIE1 will be held + * in reset too. + * + * So instead of creating two + * separate power domains for + * PCIE1 and PCIE2. We create + * a link between 1 and 10 and + * use what was supposed to be + * domain 1 as a shared PCIE + * power domain powering both + * PCIE1 and PCIE2 at the same + * time + */ + pgc_pcie_phy: gpc_power_domain@1 { + #power-domain-cells = <0>; + reg = <1>; + power-domains = <&pgc_pcie2_phy>; + }; + + pgc_otg1: power-domain@2 { + #power-domain-cells = <0>; + reg = <2>; + }; + + pgc_otg2: power-domain@3 { + #power-domain-cells = <0>; + reg = <3>; + }; + + pgc_pcie2_phy: gpc_power_domain@10 { + #power-domain-cells = <0>; + reg = <10>; + }; + }; + }; }; bus@30800000 { @@ -119,6 +181,128 @@ status = "disabled"; }; }; + + + usb_dwc3_0: usb@38100000 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + reg = <0x38100000 0x10000>; + clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>, + <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&pgc_otg1>; + status = "disabled"; + }; + + usb3_phy0: phy@381f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x381f0040 0x40>; + clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb_dwc3_1: usb@38200000 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + reg = <0x38200000 0x10000>; + clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>, + <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&pgc_otg2>; + status = "disabled"; + }; + + usb3_phy1: phy@382f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x382f0040 0x40>; + clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie0: pcie@33800000 { + compatible = "fsl,imx8mq-pcie"; + reg = <0x33800000 0x400000>, + <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + fsl,controller-id = <0>; + status = "disabled"; + }; + + pcie1: pcie@33c00000 { + compatible = "fsl,imx8mq-pcie"; + reg = <0x33c00000 0x400000>, + <0x27f00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + fsl,controller-id = <1>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index b101e61d22..efed738278 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -53,12 +53,38 @@ config SOC_AT91SAM9 select AT91SAM9_SMC select CLOCKSOURCE_ATMEL_PIT select PINCTRL + select HAVE_AT91_SMD + select HAVE_AT91_USB_CLK + select HAVE_AT91_UTMI config SOC_SAMA5 bool select CPU_V7 + +config SOC_SAMA5D2 + bool + select SOC_SAMA5 + select AT91SAM9_SMC + select CLOCKSOURCE_ATMEL_PIT + +config SOC_SAMA5D3 + bool + select SOC_SAMA5 select AT91SAM9_SMC select CLOCKSOURCE_ATMEL_PIT + select HAVE_AT91_SMD + select HAVE_AT91_USB_CLK + select HAVE_AT91_UTMI + +config SOC_SAMA5D4 + bool + select SOC_SAMA5 + select AT91SAM9_SMC + select CLOCKSOURCE_ATMEL_PIT + select HAVE_AT91_H32MX + select HAVE_AT91_SMD + select HAVE_AT91_USB_CLK + select HAVE_AT91_UTMI config ARCH_TEXT_BASE hex @@ -82,8 +108,9 @@ comment "Atmel AT91 System-on-Chip" config SOC_AT91RM9200 bool select CPU_ARM920T - select HAVE_AT91_DBGU0 select HAS_AT91_ETHER + select HAVE_AT91_DBGU0 + select HAVE_AT91_USB_CLK config SOC_AT91SAM9260 bool @@ -122,9 +149,6 @@ config SOC_AT91SAM9X5 select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAS_MACB - select HAVE_AT91_SMD - select HAVE_AT91_USB_CLK - select HAVE_AT91_UTMI select COMMON_CLK_OF_PROVIDER help Select this if you are using one of Atmel's AT91SAM9x5 family SoC. @@ -188,14 +212,14 @@ config ARCH_AT91SAM9N12 config ARCH_SAMA5D3 bool "SAMA5D3x" - select SOC_SAMA5 + select SOC_SAMA5D3 select HAVE_AT91_DBGU1 select HAS_MACB select HAVE_MACH_ARM_HEAD config ARCH_SAMA5D4 bool "SAMA5D4" - select SOC_SAMA5 + select SOC_SAMA5D4 select HAVE_AT91_DBGU2 select HAS_MACB select HAVE_MACH_ARM_HEAD @@ -522,7 +546,6 @@ config MACH_AT91SAM9263EK depends on ARCH_AT91SAM9263 select OFDEVICE select COMMON_CLK_OF_PROVIDER - select HAVE_AT91_USB_CLK select HAVE_NAND_ATMEL_BUSWIDTH_16 select HAVE_AT91_BOOTSTRAP select AT91SAM926X_BOARD_INIT diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index 886f81e9ad..4c4b51180c 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -102,6 +102,7 @@ resource_size_t __init at91_configure_usart2(unsigned pins); resource_size_t __init at91_configure_usart3(unsigned pins); resource_size_t __init at91_configure_usart4(unsigned pins); resource_size_t __init at91_configure_usart5(unsigned pins); +resource_size_t __init at91_configure_usart6(unsigned pins); #if defined(CONFIG_DRIVER_SERIAL_ATMEL) static inline struct device_d * at91_register_uart(unsigned id, unsigned pins) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8b859ab2f6..f3f3a49339 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -388,6 +388,7 @@ config MACH_TECHNEXION_WANDBOARD bool "Technexion Wandboard" select ARCH_IMX6 select ARM_USE_COMPRESSED_DTB + select MCI_IMX_ESDHC_PBL config MACH_EMBEST_RIOTBOARD bool "Embest RIoTboard" @@ -439,6 +440,7 @@ config MACH_ZII_RDU1 config MACH_ZII_RDU2 bool "ZII i.MX6Q(+) RDU2" select ARCH_IMX6 + select MCI_IMX_ESDHC_PBL config MACH_ZII_IMX8MQ_DEV bool "ZII i.MX8MQ based devices" @@ -446,6 +448,7 @@ config MACH_ZII_IMX8MQ_DEV select FIRMWARE_IMX_LPDDR4_PMU_TRAIN select FIRMWARE_IMX8MQ_ATF select ARM_SMCCC + select MCI_IMX_ESDHC_PBL config MACH_ZII_VF610_DEV bool "ZII VF610 Dev Family" @@ -482,6 +485,15 @@ config MACH_NXP_IMX8MQ_EVK select FIRMWARE_IMX_LPDDR4_PMU_TRAIN select FIRMWARE_IMX8MQ_ATF select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + +config MACH_PHYTEC_SOM_IMX8MQ + bool "Phytec i.MX8M SOM" + select ARCH_IMX8MQ + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MQ_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL config MACH_GRINN_LITEBOARD bool "Grinn liteboard" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 97c54406e6..2b817e5dd8 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -26,4 +26,4 @@ obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o obj-$(CONFIG_RESET_IMX_SRC) += src.o lwl-y += cpu_init.o -pbl-y += xload-spi.o xload-esdhc.o xload-common.o xload-imx-nand.o +pbl-y += xload-spi.o xload-common.o xload-imx-nand.o diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c index 4d00da5f0d..3f6b433a57 100644 --- a/arch/arm/mach-imx/imx8mq.c +++ b/arch/arm/mach-imx/imx8mq.c @@ -21,6 +21,7 @@ #include <mach/imx8mq.h> #include <mach/reset-reason.h> +#include <linux/iopoll.h> #include <linux/arm-smccc.h> #define FSL_SIP_BUILDINFO 0xC2000003 @@ -28,6 +29,9 @@ static int imx8mq_init_syscnt_frequency(void) { + if (!cpu_is_mx8mq()) + return 0; + if (current_el() == 3) { void __iomem *syscnt = IOMEM(MX8MQ_SYSCNT_CTRL_BASE_ADDR); /* @@ -81,3 +85,42 @@ int imx8mq_init(void) return 0; } + +#define KEEP_ALIVE 0x18 +#define VER_L 0x1c +#define VER_H 0x20 +#define VER_LIB_L_ADDR 0x24 +#define VER_LIB_H_ADDR 0x28 +#define FW_ALIVE_TIMEOUT_US 100000 + +static int imx8mq_report_hdmi_firmware(void) +{ + void __iomem *hdmi = IOMEM(MX8MQ_HDMI_CTRL_BASE_ADDR); + u16 ver_lib, ver; + u32 reg; + int ret; + + if (!cpu_is_mx8mq()) + return 0; + + /* check the keep alive register to make sure fw working */ + ret = readl_poll_timeout(hdmi + KEEP_ALIVE, + reg, reg, FW_ALIVE_TIMEOUT_US); + if (ret < 0) { + pr_info("HDP firmware is not running\n"); + return 0; + } + + ver = readl(hdmi + VER_H) & 0xff; + ver <<= 8; + ver |= readl(hdmi + VER_L) & 0xff; + + ver_lib = readl(hdmi + VER_LIB_H_ADDR) & 0xff; + ver_lib <<= 8; + ver_lib |= readl(hdmi + VER_LIB_L_ADDR) & 0xff; + + pr_info("HDP firmware ver: %d ver_lib: %d\n", ver, ver_lib); + + return 0; +} +console_initcall(imx8mq_report_hdmi_firmware); diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c deleted file mode 100644 index 6455cabf98..0000000000 --- a/arch/arm/mach-imx/xload-esdhc.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ - -#define pr_fmt(fmt) "xload-esdhc: " fmt - -#include <common.h> -#include <io.h> -#include <mci.h> -#include <mach/atf.h> -#include <mach/imx6-regs.h> -#include <mach/imx8mq-regs.h> -#include <mach/xload.h> -#include <linux/sizes.h> -#include <mach/imx-header.h> -#include "../../../drivers/mci/sdhci.h" -#include "../../../drivers/mci/imx-esdhc.h" - -#define SECTOR_SIZE 512 - -#define esdhc_read32(a) readl(a) -#define esdhc_write32(a, v) writel(v,a) -#define IMX_SDHCI_MIXCTRL 0x48 - -struct esdhc { - void __iomem *regs; - int is_mx6; -}; - -static void __udelay(int us) -{ - volatile int i; - - for (i = 0; i < us * 4; i++); -} - -static u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data) -{ - u32 xfertyp = 0; - - if (data) - xfertyp |= COMMAND_DPSEL | TRANSFER_MODE_MSBSEL | - TRANSFER_MODE_BCEN |TRANSFER_MODE_DTDSEL; - - if (cmd->resp_type & MMC_RSP_CRC) - xfertyp |= COMMAND_CCCEN; - if (cmd->resp_type & MMC_RSP_OPCODE) - xfertyp |= COMMAND_CICEN; - if (cmd->resp_type & MMC_RSP_136) - xfertyp |= COMMAND_RSPTYP_136; - else if (cmd->resp_type & MMC_RSP_BUSY) - xfertyp |= COMMAND_RSPTYP_48_BUSY; - else if (cmd->resp_type & MMC_RSP_PRESENT) - xfertyp |= COMMAND_RSPTYP_48; - - return COMMAND_CMD(cmd->cmdidx) | xfertyp; -} - -static int esdhc_do_data(struct esdhc *esdhc, struct mci_data *data) -{ - void __iomem *regs = esdhc->regs; - char *buffer; - u32 databuf; - u32 size; - u32 irqstat; - u32 timeout; - u32 present; - - buffer = data->dest; - - timeout = 1000000; - size = data->blocksize * data->blocks; - irqstat = esdhc_read32(regs + SDHCI_INT_STATUS); - - while (size) { - present = esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_BREN; - if (present) { - databuf = esdhc_read32(regs + SDHCI_BUFFER); - *((u32 *)buffer) = databuf; - buffer += 4; - size -= 4; - } - - if (!timeout--) { - pr_err("read time out\n"); - return -ETIMEDOUT; - } - } - - return 0; -} - -static int -esdhc_send_cmd(struct esdhc *esdhc, struct mci_cmd *cmd, struct mci_data *data) -{ - u32 xfertyp, mixctrl; - u32 irqstat; - void __iomem *regs = esdhc->regs; - int ret; - int timeout; - - esdhc_write32(regs + SDHCI_INT_STATUS, -1); - - /* Wait at least 8 SD clock cycles before the next command */ - __udelay(1); - - if (data) { - unsigned long dest = (unsigned long)data->dest; - - if (dest > 0xffffffff) - return -EINVAL; - - /* Set up for a data transfer if we have one */ - esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)dest); - esdhc_write32(regs + SDHCI_BLOCK_SIZE__BLOCK_COUNT, data->blocks << 16 | SECTOR_SIZE); - } - - /* Figure out the transfer arguments */ - xfertyp = esdhc_xfertyp(cmd, data); - - /* Send the command */ - esdhc_write32(regs + SDHCI_ARGUMENT, cmd->cmdarg); - - if (esdhc->is_mx6) { - /* write lower-half of xfertyp to mixctrl */ - mixctrl = xfertyp & 0xFFFF; - /* Keep the bits 22-25 of the register as is */ - mixctrl |= (esdhc_read32(regs + IMX_SDHCI_MIXCTRL) & (0xF << 22)); - esdhc_write32(regs + IMX_SDHCI_MIXCTRL, mixctrl); - } - - esdhc_write32(regs + SDHCI_TRANSFER_MODE__COMMAND, xfertyp); - - /* Wait for the command to complete */ - timeout = 10000; - while (!(esdhc_read32(regs + SDHCI_INT_STATUS) & IRQSTAT_CC)) { - __udelay(1); - if (!timeout--) - return -ETIMEDOUT; - } - - irqstat = esdhc_read32(regs + SDHCI_INT_STATUS); - esdhc_write32(regs + SDHCI_INT_STATUS, irqstat); - - if (irqstat & CMD_ERR) - return -EIO; - - if (irqstat & IRQSTAT_CTOE) - return -ETIMEDOUT; - - /* Copy the response to the response buffer */ - cmd->response[0] = esdhc_read32(regs + SDHCI_RESPONSE_0); - - /* Wait until all of the blocks are transferred */ - if (data) { - ret = esdhc_do_data(esdhc, data); - if (ret) - return ret; - } - - esdhc_write32(regs + SDHCI_INT_STATUS, -1); - - /* Wait for the bus to be idle */ - timeout = 10000; - while (esdhc_read32(regs + SDHCI_PRESENT_STATE) & - (PRSSTAT_CICHB | PRSSTAT_CIDHB | PRSSTAT_DLA)) { - __udelay(1); - if (!timeout--) - return -ETIMEDOUT; - } - - return 0; -} - -static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len) -{ - struct mci_cmd cmd; - struct mci_data data; - u32 val; - int ret; - - writel(IRQSTATEN_CC | IRQSTATEN_TC | IRQSTATEN_CINT | IRQSTATEN_CTOE | - IRQSTATEN_CCE | IRQSTATEN_CEBE | IRQSTATEN_CIE | - IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE | - IRQSTATEN_DINT, esdhc->regs + SDHCI_INT_ENABLE); - - val = readl(esdhc->regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET); - val |= SYSCTL_HCKEN | SYSCTL_IPGEN; - writel(val, esdhc->regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET); - - cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; - cmd.cmdarg = 0; - cmd.resp_type = MMC_RSP_R1; - - data.dest = dst; - data.blocks = len / SECTOR_SIZE; - data.blocksize = SECTOR_SIZE; - data.flags = MMC_DATA_READ; - - ret = esdhc_send_cmd(esdhc, &cmd, &data); - if (ret) { - pr_debug("send command failed with %d\n", ret); - return ret; - } - - cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; - cmd.cmdarg = 0; - cmd.resp_type = MMC_RSP_R1b; - - esdhc_send_cmd(esdhc, &cmd, NULL); - - return 0; -} - -static int -esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, ptrdiff_t entry, u32 offset) -{ - - void *buf = (void *)address; - struct imx_flash_header_v2 *hdr; - int ret, len; - void __noreturn (*bb)(void); - unsigned int ofs; - int i, header_count = 1; - - len = imx_image_size(); - len = ALIGN(len, SECTOR_SIZE); - - for (i = 0; i < header_count; i++) { - ret = esdhc_read_blocks(esdhc, buf, - offset + SZ_1K + SECTOR_SIZE); - if (ret) - return ret; - - hdr = buf + offset + SZ_1K; - - if (!is_imx_flash_header_v2(hdr)) { - pr_debug("IVT header not found on SD card. " - "Found tag: 0x%02x length: 0x%04x " - "version: %02x\n", - hdr->header.tag, hdr->header.length, - hdr->header.version); - return -EINVAL; - } - - if (IS_ENABLED(CONFIG_ARCH_IMX8MQ) && - hdr->boot_data.plugin & PLUGIN_HDMI_IMAGE) { - /* - * In images that include signed HDMI - * firmware, first v2 header would be - * dedicated to that and would not contain any - * useful for us information. In order for us - * to pull the rest of the bootloader image - * in, we need to re-read header from SD/MMC, - * this time skipping anything HDMI firmware - * related. - */ - offset += hdr->boot_data.size + hdr->header.length; - header_count++; - } - } - - pr_debug("Check ok, loading image\n"); - - ofs = offset + hdr->entry - hdr->boot_data.start; - - if (entry != address) { - /* - * Passing entry different from address is interpreted - * as a request to place the image such that its entry - * point would be exactly at 'entry', that is: - * - * buf + ofs = entry - * - * solving the above for 'buf' gvies us the - * adjustement that needs to be made: - * - * buf = entry - ofs - * - */ - if (WARN_ON(entry - ofs < address)) { - /* - * We want to make sure we won't try to place - * the start of the image before the beginning - * of the memory buffer we were given in - * address. - */ - return -EINVAL; - } - - buf = (void *)(entry - ofs); - } - - ret = esdhc_read_blocks(esdhc, buf, offset + len); - if (ret) { - pr_err("Loading image failed with %d\n", ret); - return ret; - } - - pr_debug("Image loaded successfully\n"); - - bb = buf + ofs; - - bb(); -} - -/** - * imx6_esdhc_start_image - Load and start an image from USDHC controller - * @instance: The USDHC controller instance (0..4) - * - * This uses esdhc_start_image() to load an image from SD/MMC. It is - * assumed that the image is the currently running barebox image (This - * information is used to calculate the length of the image). The - * image is started afterwards. - * - * Return: If successful, this function does not return. A negative error - * code is returned when this function fails. - */ -int imx6_esdhc_start_image(int instance) -{ - struct esdhc esdhc; - - switch (instance) { - case 0: - esdhc.regs = IOMEM(MX6_USDHC1_BASE_ADDR); - break; - case 1: - esdhc.regs = IOMEM(MX6_USDHC2_BASE_ADDR); - break; - case 2: - esdhc.regs = IOMEM(MX6_USDHC3_BASE_ADDR); - break; - case 3: - esdhc.regs = IOMEM(MX6_USDHC4_BASE_ADDR); - break; - default: - return -EINVAL; - } - - esdhc.is_mx6 = 1; - - return esdhc_start_image(&esdhc, 0x10000000, 0x10000000, 0); -} - -/** - * imx8_esdhc_start_image - Load and start an image from USDHC controller - * @instance: The USDHC controller instance (0..2) - * - * This uses esdhc_start_image() to load an image from SD/MMC. It is - * assumed that the image is the currently running barebox image (This - * information is used to calculate the length of the image). The - * image is started afterwards. - * - * Return: If successful, this function does not return. A negative error - * code is returned when this function fails. - */ -int imx8_esdhc_start_image(int instance) -{ - struct esdhc esdhc; - - switch (instance) { - case 0: - esdhc.regs = IOMEM(MX8MQ_USDHC1_BASE_ADDR); - break; - case 1: - esdhc.regs = IOMEM(MX8MQ_USDHC2_BASE_ADDR); - break; - default: - return -EINVAL; - } - - esdhc.is_mx6 = 1; - - return esdhc_start_image(&esdhc, MX8MQ_DDR_CSD1_BASE_ADDR, - MX8MQ_ATF_BL33_BASE_ADDR, SZ_32K); -}
\ No newline at end of file diff --git a/arch/x86/configs/efi_defconfig b/arch/x86/configs/efi_defconfig index fdf092e9ba..f489770eba 100644 --- a/arch/x86/configs/efi_defconfig +++ b/arch/x86/configs/efi_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_MM=y CONFIG_CMD_DETECT=y CONFIG_CMD_FLASH=y CONFIG_CMD_POWEROFF=y +CONFIG_CMD_WD=y CONFIG_CMD_2048=y CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_OF_NODE=y @@ -71,6 +72,8 @@ CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_NET_EFI_SNP=y # CONFIG_SPI is not set CONFIG_DISK=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_EFI=y CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y CONFIG_FS_NFS=y |