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-rw-r--r--arch/arm/Kconfig34
-rw-r--r--arch/arm/Makefile4
-rw-r--r--arch/arm/boards/a9m2440/lowlevel_init.S2
-rw-r--r--arch/arm/boards/at91rm9200ek/env/config2
-rw-r--r--arch/arm/boards/at91sam9260ek/Makefile1
-rw-r--r--arch/arm/boards/at91sam9x5ek/Makefile1
-rw-r--r--arch/arm/boards/at91sam9x5ek/env/config4
-rw-r--r--arch/arm/boards/at91sam9x5ek/hw_version.c272
-rw-r--r--arch/arm/boards/at91sam9x5ek/hw_version.h34
-rw-r--r--arch/arm/boards/at91sam9x5ek/init.c119
-rw-r--r--arch/arm/boards/ccxmx51/ccxmx51.c3
-rw-r--r--arch/arm/boards/ccxmx51/ccxmx51js.c2
-rw-r--r--arch/arm/boards/clep7212/Makefile2
-rw-r--r--arch/arm/boards/clep7212/clep7212.c64
-rw-r--r--arch/arm/boards/clep7212/config.h4
-rw-r--r--arch/arm/boards/clep7212/env/bin/mtdparts-add21
-rw-r--r--arch/arm/boards/clep7212/env/boot/nor9
-rw-r--r--arch/arm/boards/clep7212/env/init/automount6
-rw-r--r--arch/arm/boards/clep7212/env/init/bootargs-base (renamed from arch/arm/boards/freescale-mx6-sabrelite/env/init/bootargs-base)2
-rw-r--r--arch/arm/boards/clep7212/env/init/general12
-rw-r--r--arch/arm/boards/clep7212/env/init/hostname (renamed from arch/arm/boards/pcm038/env/init/hostname)2
-rw-r--r--arch/arm/boards/clep7212/lowlevel.c56
-rw-r--r--arch/arm/boards/crystalfontz-cfa10036/env/boot/mmc-ext32
-rw-r--r--arch/arm/boards/crystalfontz-cfa10036/env/init/bootargs-base8
-rw-r--r--arch/arm/boards/crystalfontz-cfa10036/env/init/config-board7
-rw-r--r--arch/arm/boards/crystalfontz-cfa10036/env/init/hostname8
-rw-r--r--arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c17
-rw-r--r--arch/arm/boards/eukrea_cpuimx25/flash_header.c2
-rw-r--r--arch/arm/boards/eukrea_cpuimx25/lowlevel.c31
-rw-r--r--arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c10
-rw-r--r--arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S77
-rw-r--r--arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c22
-rw-r--r--arch/arm/boards/eukrea_cpuimx35/flash_header.c2
-rw-r--r--arch/arm/boards/eukrea_cpuimx35/lowlevel.c43
-rw-r--r--arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c2
-rw-r--r--arch/arm/boards/freescale-mx25-3-stack/3stack.c10
-rw-r--r--arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S8
-rw-r--r--arch/arm/boards/freescale-mx28-evk/mx28-evk.c2
-rw-r--r--arch/arm/boards/freescale-mx35-3-stack/3stack.c13
-rw-r--r--arch/arm/boards/freescale-mx35-3-stack/flash_header.c2
-rw-r--r--arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S22
-rw-r--r--arch/arm/boards/freescale-mx51-pdk/board.c12
-rw-r--r--arch/arm/boards/freescale-mx51-pdk/dcd-data.h60
-rw-r--r--arch/arm/boards/freescale-mx51-pdk/env/init/config-board7
-rw-r--r--arch/arm/boards/freescale-mx51-pdk/env/init/hostname8
-rw-r--r--arch/arm/boards/freescale-mx51-pdk/flash_header.c61
-rw-r--r--arch/arm/boards/freescale-mx53-loco/board.c15
-rw-r--r--arch/arm/boards/freescale-mx53-loco/dcd-data.h54
-rw-r--r--arch/arm/boards/freescale-mx53-loco/flash_header.c56
-rw-r--r--arch/arm/boards/freescale-mx53-smd/board.c2
-rw-r--r--arch/arm/boards/freescale-mx6-arm2/board.c2
-rw-r--r--arch/arm/boards/freescale-mx6-sabrelite/board.c4
-rw-r--r--arch/arm/boards/freescale-mx6-sabrelite/env/init/config-board7
-rw-r--r--arch/arm/boards/friendlyarm-tiny210/Makefile1
-rw-r--r--arch/arm/boards/guf-cupid/board.c8
-rw-r--r--arch/arm/boards/guf-cupid/lowlevel.c61
-rw-r--r--arch/arm/boards/guf-neso/board.c8
-rw-r--r--arch/arm/boards/guf-neso/lowlevel.c55
-rw-r--r--arch/arm/boards/guf-neso/pll_init.S39
-rw-r--r--arch/arm/boards/imx21ads/imx21ads.c7
-rw-r--r--arch/arm/boards/imx21ads/lowlevel_init.S20
-rw-r--r--arch/arm/boards/imx27ads/imx27ads.c2
-rw-r--r--arch/arm/boards/imx27ads/lowlevel_init.S30
-rw-r--r--arch/arm/boards/karo-tx25/board.c14
-rw-r--r--arch/arm/boards/karo-tx25/lowlevel.c21
-rw-r--r--arch/arm/boards/karo-tx28/tx28-stk5.c2
-rw-r--r--arch/arm/boards/karo-tx51/tx51.c2
-rw-r--r--arch/arm/boards/karo-tx53/Makefile3
-rw-r--r--arch/arm/boards/karo-tx53/board.c49
-rw-r--r--arch/arm/boards/karo-tx53/dcd-data-1011.h94
-rw-r--r--arch/arm/boards/karo-tx53/dcd-data-xx30.h144
-rw-r--r--arch/arm/boards/karo-tx53/env/init/bootargs-base8
-rw-r--r--arch/arm/boards/karo-tx53/env/init/config-board7
-rw-r--r--arch/arm/boards/karo-tx53/env/init/hostname8
-rw-r--r--arch/arm/boards/karo-tx53/flash_header.c118
-rw-r--r--arch/arm/boards/karo-tx53/lowlevel.c22
-rw-r--r--arch/arm/boards/panda/lowlevel.c6
-rw-r--r--arch/arm/boards/pcm037/lowlevel_init.S65
-rw-r--r--arch/arm/boards/pcm037/pcm037.c4
-rw-r--r--arch/arm/boards/pcm038/env/boot/nand-ubi2
-rw-r--r--arch/arm/boards/pcm038/env/init/bootargs-base8
-rw-r--r--arch/arm/boards/pcm038/env/init/config-board7
-rw-r--r--arch/arm/boards/pcm038/lowlevel.c62
-rw-r--r--arch/arm/boards/pcm038/pcm038.c29
-rw-r--r--arch/arm/boards/pcm038/pcm970.c26
-rw-r--r--arch/arm/boards/pcm038/pll.h54
-rw-r--r--arch/arm/boards/pcm043/lowlevel.c44
-rw-r--r--arch/arm/boards/pcm043/pcm043.c8
-rw-r--r--arch/arm/boards/pcm049/lowlevel.c6
-rw-r--r--arch/arm/boards/phycard-a-xl2/lowlevel.c5
-rw-r--r--arch/arm/boards/phycard-i.MX27/lowlevel_init.S70
-rw-r--r--arch/arm/boards/phycard-i.MX27/pca100.c6
-rw-r--r--arch/arm/boards/pm9261/init.c10
-rw-r--r--arch/arm/boards/pm9263/init.c38
-rw-r--r--arch/arm/boards/pm9g45/env/config13
-rw-r--r--arch/arm/boards/pm9g45/init.c29
-rw-r--r--arch/arm/boards/raspberry-pi/Makefile1
-rw-r--r--arch/arm/boards/raspberry-pi/config.h4
-rw-r--r--arch/arm/boards/raspberry-pi/env/init/bootargs-base (renamed from arch/arm/boards/freescale-mx51-pdk/env/init/bootargs-base)0
-rw-r--r--arch/arm/boards/raspberry-pi/env/init/hostname (renamed from arch/arm/boards/freescale-mx6-sabrelite/env/init/hostname)2
-rw-r--r--arch/arm/boards/raspberry-pi/rpi.c44
-rw-r--r--arch/arm/boards/scb9328/lowlevel_init.S31
-rw-r--r--arch/arm/boards/scb9328/scb9328.c7
-rw-r--r--arch/arm/boards/tqma53/board.c2
-rw-r--r--arch/arm/boards/tqma53/env/init/bootargs-base8
-rw-r--r--arch/arm/boards/tqma53/env/init/config-board7
-rw-r--r--arch/arm/boards/tqma53/env/init/hostname8
-rw-r--r--arch/arm/boards/versatile/versatilepb.c1
-rw-r--r--arch/arm/configs/at91rm9200ek_defconfig5
-rw-r--r--arch/arm/configs/at91sam9x5ek_defconfig21
-rw-r--r--arch/arm/configs/clps711x_defconfig42
-rw-r--r--arch/arm/configs/freescale_mx53_loco_defconfig1
-rw-r--r--arch/arm/configs/pm9261_defconfig2
-rw-r--r--arch/arm/configs/pm9263_defconfig2
-rw-r--r--arch/arm/configs/pm9g45_defconfig34
-rw-r--r--arch/arm/configs/rpi_defconfig41
-rw-r--r--arch/arm/configs/tx53stk5_defconfig12
-rw-r--r--arch/arm/configs/versatilepb_defconfig5
-rw-r--r--arch/arm/cpu/Kconfig5
-rw-r--r--arch/arm/cpu/Makefile7
-rw-r--r--arch/arm/cpu/cache-armv4.S28
-rw-r--r--arch/arm/cpu/cache-armv5.S30
-rw-r--r--arch/arm/cpu/cache-armv6.S34
-rw-r--r--arch/arm/cpu/cache-armv7.S38
-rw-r--r--arch/arm/cpu/cache.c103
-rw-r--r--arch/arm/cpu/cpu.c71
-rw-r--r--arch/arm/cpu/exceptions.S16
-rw-r--r--arch/arm/cpu/interrupts.c6
-rw-r--r--arch/arm/cpu/mmu.c28
-rw-r--r--arch/arm/cpu/setupc.S34
-rw-r--r--arch/arm/cpu/start-pbl.c52
-rw-r--r--arch/arm/cpu/start.c45
-rw-r--r--arch/arm/include/asm/barebox-arm.h2
-rw-r--r--arch/arm/include/asm/cache.h2
-rw-r--r--arch/arm/include/asm/common.h5
-rw-r--r--arch/arm/include/asm/cputype.h100
-rw-r--r--arch/arm/include/asm/ptrace.h56
-rw-r--r--arch/arm/include/asm/system_info.h60
-rw-r--r--arch/arm/lib/bootm.c4
-rw-r--r--arch/arm/lib/bootz.c12
-rw-r--r--arch/arm/mach-at91/Kconfig1
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c28
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c32
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c31
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c31
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c50
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c4
-rw-r--r--arch/arm/mach-at91/at91sam9x5_devices.c182
-rw-r--r--arch/arm/mach-at91/include/mach/board.h3
-rw-r--r--arch/arm/mach-at91/include/mach/gpio.h11
-rw-r--r--arch/arm/mach-bcm2835/Kconfig18
-rw-r--r--arch/arm/mach-bcm2835/Makefile1
-rw-r--r--arch/arm/mach-bcm2835/core.c101
-rw-r--r--arch/arm/mach-bcm2835/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-bcm2835/include/mach/core.h (renamed from arch/arm/boards/at91sam9260ek/lowlevel_init.S)17
-rw-r--r--arch/arm/mach-bcm2835/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-bcm2835/include/mach/platform.h50
-rw-r--r--arch/arm/mach-bcm2835/include/mach/wd.h47
-rw-r--r--arch/arm/mach-clps711x/Kconfig26
-rw-r--r--arch/arm/mach-clps711x/Makefile1
-rw-r--r--arch/arm/mach-clps711x/clock.c113
-rw-r--r--arch/arm/mach-clps711x/devices.c97
-rw-r--r--arch/arm/mach-clps711x/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-clps711x/include/mach/clps711x.h284
-rw-r--r--arch/arm/mach-clps711x/include/mach/devices.h7
-rw-r--r--arch/arm/mach-clps711x/reset.c21
-rw-r--r--arch/arm/mach-ep93xx/include/mach/gpio.h27
-rw-r--r--arch/arm/mach-imx/Kconfig13
-rw-r--r--arch/arm/mach-imx/Makefile5
-rw-r--r--arch/arm/mach-imx/boot.c211
-rw-r--r--arch/arm/mach-imx/clk-imx1.c9
-rw-r--r--arch/arm/mach-imx/clk-imx21.c26
-rw-r--r--arch/arm/mach-imx/clk-imx25.c29
-rw-r--r--arch/arm/mach-imx/clk-imx27.c102
-rw-r--r--arch/arm/mach-imx/clk-imx31.c9
-rw-r--r--arch/arm/mach-imx/clk-imx35.c9
-rw-r--r--arch/arm/mach-imx/clk-imx5.c21
-rw-r--r--arch/arm/mach-imx/clk-imx6.c9
-rw-r--r--arch/arm/mach-imx/clk-pllv2.c1
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c1
-rw-r--r--arch/arm/mach-imx/clk.h6
-rw-r--r--arch/arm/mach-imx/clocksource.c50
-rw-r--r--arch/arm/mach-imx/devices.c18
-rw-r--r--arch/arm/mach-imx/external-nand-boot.c36
-rw-r--r--arch/arm/mach-imx/gpio.c2
-rw-r--r--arch/arm/mach-imx/imx-bbu-internal.c543
-rw-r--r--arch/arm/mach-imx/imx.c31
-rw-r--r--arch/arm/mach-imx/imx1.c32
-rw-r--r--arch/arm/mach-imx/imx21.c14
-rw-r--r--arch/arm/mach-imx/imx25.c10
-rw-r--r--arch/arm/mach-imx/imx27.c37
-rw-r--r--arch/arm/mach-imx/imx31.c4
-rw-r--r--arch/arm/mach-imx/imx35.c17
-rw-r--r--arch/arm/mach-imx/imx51.c100
-rw-r--r--arch/arm/mach-imx/imx53.c36
-rw-r--r--arch/arm/mach-imx/imx6.c2
-rw-r--r--arch/arm/mach-imx/include/mach/bbu.h51
-rw-r--r--arch/arm/mach-imx/include/mach/devices-imx1.h4
-rw-r--r--arch/arm/mach-imx/include/mach/devices-imx21.h8
-rw-r--r--arch/arm/mach-imx/include/mach/devices-imx25.h12
-rw-r--r--arch/arm/mach-imx/include/mach/devices-imx27.h10
-rw-r--r--arch/arm/mach-imx/include/mach/devices-imx31.h12
-rw-r--r--arch/arm/mach-imx/include/mach/devices-imx35.h8
-rw-r--r--arch/arm/mach-imx/include/mach/devices-imx51.h8
-rw-r--r--arch/arm/mach-imx/include/mach/devices-imx53.h8
-rw-r--r--arch/arm/mach-imx/include/mach/devices-imx6.h10
-rw-r--r--arch/arm/mach-imx/include/mach/devices.h6
-rw-r--r--arch/arm/mach-imx/include/mach/esdctl.h10
-rw-r--r--arch/arm/mach-imx/include/mach/generic.h27
-rw-r--r--arch/arm/mach-imx/include/mach/gpio.h7
-rw-r--r--arch/arm/mach-imx/include/mach/imx-flash-header.h35
-rw-r--r--arch/arm/mach-imx/include/mach/imx-regs.h119
-rw-r--r--arch/arm/mach-imx/include/mach/imx1-regs.h176
-rw-r--r--arch/arm/mach-imx/include/mach/imx21-regs.h136
-rw-r--r--arch/arm/mach-imx/include/mach/imx25-regs.h77
-rw-r--r--arch/arm/mach-imx/include/mach/imx27-regs.h232
-rw-r--r--arch/arm/mach-imx/include/mach/imx31-regs.h138
-rw-r--r--arch/arm/mach-imx/include/mach/imx35-regs.h70
-rw-r--r--arch/arm/mach-imx/include/mach/imx51-regs.h4
-rw-r--r--arch/arm/mach-imx/include/mach/imx53-regs.h4
-rw-r--r--arch/arm/mach-imx/include/mach/imx6-regs.h6
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-mx1.h135
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-mx21.h1
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-mx27.h1
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-mx35.h2
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-v1.h48
-rw-r--r--arch/arm/mach-imx/include/mach/revision.h22
-rw-r--r--arch/arm/mach-imx/iomux-v1.c123
-rw-r--r--arch/arm/mach-imx/iomux-v2.c66
-rw-r--r--arch/arm/mach-imx/iomux-v3.c43
-rw-r--r--arch/arm/mach-imx/nand.c58
-rw-r--r--arch/arm/mach-imx/reset_source.c72
-rw-r--r--arch/arm/mach-mxs/include/mach/gpio.h6
-rw-r--r--arch/arm/mach-nomadik/8815.c5
-rw-r--r--arch/arm/mach-nomadik/include/mach/mtu.h46
-rw-r--r--arch/arm/mach-nomadik/include/mach/timex.h6
-rw-r--r--arch/arm/mach-nomadik/timer.c54
-rw-r--r--arch/arm/mach-omap/Makefile1
-rw-r--r--arch/arm/mach-omap/gpio.c2
-rw-r--r--arch/arm/mach-omap/include/mach/gpio.h43
-rw-r--r--arch/arm/mach-omap/omap3_generic.c14
-rw-r--r--arch/arm/mach-omap/omap4_generic.c41
-rw-r--r--arch/arm/mach-samsung/Kconfig1
-rw-r--r--arch/arm/mach-samsung/Makefile1
-rw-r--r--arch/arm/mach-samsung/include/mach/gpio.h6
-rw-r--r--arch/arm/mach-versatile/core.c17
-rw-r--r--arch/arm/mach-versatile/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-versatile/include/mach/init.h1
-rw-r--r--arch/arm/pbl/.gitignore1
-rw-r--r--arch/mips/include/asm/mipsregs.h3
-rw-r--r--arch/nios2/lib/longlong.h2
-rw-r--r--arch/sandbox/Makefile7
-rw-r--r--arch/sandbox/os/common.c18
253 files changed, 5650 insertions, 2421 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8278c82e3a..3afd88514f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -31,6 +31,20 @@ config ARCH_AT91
select HAS_DEBUG_LL
select HAVE_MACH_ARM_HEAD
+config ARCH_BCM2835
+ bool "Broadcom BCM2835 boards"
+ select GPIOLIB
+ select CPU_ARM1176
+ select CLKDEV_LOOKUP
+ select COMMON_CLK
+ select CLOCKSOURCE_BCM2835
+ select ARM_AMBA
+
+config ARCH_CLPS711X
+ bool "Cirrus Logic EP711x/EP721x/EP731x"
+ select CLKDEV_LOOKUP
+ select CPU_32v4T
+
config ARCH_EP93XX
bool "Cirrus Logic EP93xx"
select CPU_ARM920T
@@ -42,6 +56,7 @@ config ARCH_IMX
select GPIOLIB
select COMMON_CLK
select CLKDEV_LOOKUP
+ select WATCHDOG_IMX_RESET_SOURCE
config ARCH_MXS
bool "Freescale i.MX23/28 (mxs) based"
@@ -54,6 +69,7 @@ config ARCH_NETX
config ARCH_NOMADIK
bool "STMicroelectronics Nomadik"
select CPU_ARM926T
+ select CLOCKSOURCE_NOMADIK
help
Support for the Nomadik platform by ST-Ericsson
@@ -71,14 +87,12 @@ config ARCH_S3C24xx
select ARCH_SAMSUNG
select CPU_ARM920T
select GENERIC_GPIO
-#
-# Currently no board support
-#
-#config ARCH_S5PCxx
-# bool "Samsung S5PC110, S5PV210"
-# select ARCH_SAMSUNG
-# select CPU_V7
-# select GENERIC_GPIO
+
+config ARCH_S5PCxx
+ bool "Samsung S5PC110, S5PV210"
+ select ARCH_SAMSUNG
+ select CPU_V7
+ select GENERIC_GPIO
config ARCH_S3C64xx
bool "Samsung S3C64xx"
@@ -89,6 +103,7 @@ config ARCH_S3C64xx
config ARCH_VERSATILE
bool "ARM Versatile boards (ARM926EJ-S)"
select CPU_ARM926T
+ select GPIOLIB
config ARCH_TEGRA
bool "Nvidia Tegra-based boards"
@@ -99,6 +114,8 @@ endchoice
source arch/arm/cpu/Kconfig
source arch/arm/mach-at91/Kconfig
+source arch/arm/mach-bcm2835/Kconfig
+source arch/arm/mach-clps711x/Kconfig
source arch/arm/mach-ep93xx/Kconfig
source arch/arm/mach-imx/Kconfig
source arch/arm/mach-mxs/Kconfig
@@ -123,6 +140,7 @@ config AEABI
config THUMB2_BAREBOX
select ARM_ASM_UNIFIED
+ select AEABI
depends on CPU_V7
bool "Compile barebox in thumb-2 mode (read help)"
help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 855043aedf..4b630ab4cb 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -52,6 +52,8 @@ AFLAGS += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) := at91
+machine-$(CONFIG_ARCH_BCM2835) := bcm2835
+machine-$(CONFIG_ARCH_CLPS711X) := clps711x
machine-$(CONFIG_ARCH_EP93XX) := ep93xx
machine-$(CONFIG_ARCH_IMX) := imx
machine-$(CONFIG_ARCH_MXS) := mxs
@@ -75,6 +77,7 @@ board-$(CONFIG_MACH_AT91SAM9G10EK) := at91sam9261ek
board-$(CONFIG_MACH_AT91SAM9G20EK) := at91sam9260ek
board-$(CONFIG_MACH_AT91SAM9X5EK) := at91sam9x5ek
board-$(CONFIG_MACH_AT91SAM9M10G45EK) := at91sam9m10g45ek
+board-$(CONFIG_MACH_CLEP7212) := clep7212
board-$(CONFIG_MACH_DSS11) := dss11
board-$(CONFIG_MACH_EDB9301) := edb93xx
board-$(CONFIG_MACH_EDB9302) := edb93xx
@@ -112,6 +115,7 @@ board-$(CONFIG_MACH_PCM043) := pcm043
board-$(CONFIG_MACH_PM9261) := pm9261
board-$(CONFIG_MACH_PM9263) := pm9263
board-$(CONFIG_MACH_PM9G45) := pm9g45
+board-$(CONFIG_MACH_RPI) := raspberry-pi
board-$(CONFIG_MACH_SCB9328) := scb9328
board-$(CONFIG_MACH_NESO) := guf-neso
board-$(CONFIG_MACH_MX23EVK) := freescale-mx23-evk
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
index da29efdc21..8f6cfcbe68 100644
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ b/arch/arm/boards/a9m2440/lowlevel_init.S
@@ -225,7 +225,7 @@ reset:
cmp pc, #S3C_SDRAM_END
bhs 1f
- mov pc, r10
+ b board_init_lowlevel_return
/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
1:
diff --git a/arch/arm/boards/at91rm9200ek/env/config b/arch/arm/boards/at91rm9200ek/env/config
index a3830cb31a..76c180bcac 100644
--- a/arch/arm/boards/at91rm9200ek/env/config
+++ b/arch/arm/boards/at91rm9200ek/env/config
@@ -15,6 +15,8 @@ global.dhcp.vendor_id=barebox-at91rm9200ek
kernel_loc=nfs
# can be either 'net', 'nor' or 'initrd'
rootfs_loc=net
+# can be either 'nfs', 'tftp', or empty
+oftree_loc=nfs
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
diff --git a/arch/arm/boards/at91sam9260ek/Makefile b/arch/arm/boards/at91sam9260ek/Makefile
index 73ef72e210..eb072c0161 100644
--- a/arch/arm/boards/at91sam9260ek/Makefile
+++ b/arch/arm/boards/at91sam9260ek/Makefile
@@ -1,2 +1 @@
-obj-y += lowlevel_init.o
obj-y += init.o
diff --git a/arch/arm/boards/at91sam9x5ek/Makefile b/arch/arm/boards/at91sam9x5ek/Makefile
index eb072c0161..f2acf201b4 100644
--- a/arch/arm/boards/at91sam9x5ek/Makefile
+++ b/arch/arm/boards/at91sam9x5ek/Makefile
@@ -1 +1,2 @@
obj-y += init.o
+obj-y += hw_version.o
diff --git a/arch/arm/boards/at91sam9x5ek/env/config b/arch/arm/boards/at91sam9x5ek/env/config
index 6a985cedc5..b8cf4e3f30 100644
--- a/arch/arm/boards/at91sam9x5ek/env/config
+++ b/arch/arm/boards/at91sam9x5ek/env/config
@@ -4,6 +4,7 @@
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp-barebox
global.dhcp.vendor_id=barebox-at91sam9x5ek
+global.dhcp.client_id="${at91sam9x5cm.board}-${at91sam9x5cm.vendor}"
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
@@ -21,6 +22,7 @@ oftree_loc=nfs
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root.$rootfs_type
+ubiroot=rootfs
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
kernelimage=zImage
@@ -29,7 +31,7 @@ kernelimage=zImage
#kernelimage=Image.lzo
nand_device=atmel_nand
-nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),1M(free),4M(kernel),120M(rootfs),-(data)"
+nand_parts="256k(at91bootstrap),384k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),1M(free),6M(kernel),120M(rootfs),-(data)"
rootfs_mtdblock_nand=7
autoboot_timeout=3
diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.c b/arch/arm/boards/at91sam9x5ek/hw_version.c
new file mode 100644
index 0000000000..47c640a35f
--- /dev/null
+++ b/arch/arm/boards/at91sam9x5ek/hw_version.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#include <common.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <libbb.h>
+#include <asm/armlinux.h>
+#include <of.h>
+#include <libfdt.h>
+
+#include "hw_version.h"
+
+enum board_type {
+ BOARD_TYPE_EK,
+ BOARD_TYPE_DM,
+ BOARD_TYPE_CPU,
+};
+
+static struct board_info {
+ char *name;
+ enum board_type type;
+ unsigned char id;
+} board_list[] = {
+ {"SAM9x5-EK", BOARD_TYPE_EK, 0},
+ {"SAM9x5-DM", BOARD_TYPE_DM, 1},
+ {"SAM9G15-CM", BOARD_TYPE_CPU, 2},
+ {"SAM9G25-CM", BOARD_TYPE_CPU, 3},
+ {"SAM9G35-CM", BOARD_TYPE_CPU, 4},
+ {"SAM9X25-CM", BOARD_TYPE_CPU, 5},
+ {"SAM9X35-CM", BOARD_TYPE_CPU, 6},
+ {"PDA-DM", BOARD_TYPE_DM, 7},
+};
+
+static struct board_info* get_board_info_by_name(const char *name)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(board_list); i++)
+ if (strcmp(name, board_list[i].name) == 0)
+ return &board_list[i];
+
+ return NULL;
+}
+
+static struct vendor_info {
+ char *name;
+ enum vendor_id id;
+} vendor_list[] = {
+ {"EMBEST", VENDOR_EMBEST},
+ {"FLEX", VENDOR_FLEX},
+ {"RONETIX", VENDOR_RONETIX},
+ {"COGENT", VENDOR_COGENT},
+ {"PDA", VENDOR_PDA},
+};
+
+static struct vendor_info* get_vendor_info_by_name(const char *name)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(vendor_list); i++)
+ if (strcmp(name, vendor_list[i].name) == 0)
+ return &vendor_list[i];
+
+ return NULL;
+}
+
+#define BOARD_NAME_LEN 12
+#define VENDOR_NAME_LEN 10
+#define VENDOR_COUNTRY_LEN 2
+
+struct one_wire_info {
+ u8 total_bytes;
+ u8 vendor_name[VENDOR_NAME_LEN];
+ u8 vendor_country[VENDOR_COUNTRY_LEN];
+ u8 board_name[BOARD_NAME_LEN];
+ u8 year;
+ u8 week;
+ u8 revision_code;
+ u8 revision_id;
+ u8 reserved;
+ u8 checksum_l;
+ u8 checksum_h;
+}__attribute__ ((packed));
+
+static int at91sam9x5ek_read_w1(const char *file, struct one_wire_info *info)
+{
+ int fd;
+ int ret;
+
+ fd = open(file, O_RDONLY);
+ if (fd < 0) {
+ ret = fd;
+ goto err;
+ }
+
+ ret = read_full(fd, info, sizeof(*info));
+ if (ret < 0)
+ goto err_open;
+
+ if (ret < sizeof(*info)) {
+ ret = -EINVAL;
+ goto err_open;
+ }
+
+ pr_debug("total_bytes = %d\n", info->total_bytes);
+ pr_debug("vendor_name = %s\n", info->vendor_name);
+ pr_debug("vendor_country = %.2s\n", info->vendor_country);
+ pr_debug("board_name = %s\n", info->board_name);
+ pr_debug("year = %d\n", info->year);
+ pr_debug("week = %d\n", info->week);
+ pr_debug("revision_code = %x\n", info->revision_code);
+ pr_debug("revision_id = %x\n", info->revision_id);
+ pr_debug("reserved = %x\n", info->reserved);
+ pr_debug("checksum_l = %x\n", info->checksum_l);
+ pr_debug("checksum_h = %x\n", info->checksum_h);
+
+ ret = 0;
+
+err_open:
+ close(fd);
+err:
+ if (ret)
+ pr_err("can not read 1-wire %s (%s)\n", file, strerror(ret));
+ return ret;
+}
+
+static u32 sn = 0;
+static u32 rev = 0;
+
+bool at91sam9x5ek_cm_is_vendor(enum vendor_id vid)
+{
+ return ((sn >> 5) & 0x1f) == vid;
+}
+
+bool at91sam9x5ek_ek_is_vendor(enum vendor_id vid)
+{
+ return ((sn >> 15) & 0x1f) == vid;
+}
+
+bool at91sam9x5ek_dm_is_vendor(enum vendor_id vid)
+{
+ return ((sn >> 25) & 0x1f) == vid;
+}
+
+static void at91sam9x5ek_devices_detect_one(const char *name)
+{
+ struct one_wire_info info;
+ struct board_info* binfo;
+ struct vendor_info* vinfo;
+ struct device_d *dev = NULL;
+ char str[16];
+ u8 vendor_id = 0;
+
+ if (at91sam9x5ek_read_w1(name, &info))
+ return;
+
+ binfo = get_board_info_by_name(info.board_name);
+
+ if (!binfo) {
+ pr_err("board %s no supported\n", info.board_name);
+ return;
+ }
+
+ vinfo = get_vendor_info_by_name(info.vendor_name);
+ if (vinfo)
+ vendor_id = vinfo->id;
+
+ switch (binfo->type) {
+ case BOARD_TYPE_CPU:
+ dev = add_generic_device_res("at91sam9x5cm", DEVICE_ID_SINGLE, NULL, 0, NULL);
+ if (!dev)
+ return;
+ sn |= (binfo->id & 0x1f);
+ sn |= ((vendor_id & 0x1f) << 5);
+ rev |= (info.revision_code - 'A');
+ rev |= (((info.revision_id - '0') & 0x3) << 15);
+ pr_info("CM");
+ break;
+ case BOARD_TYPE_EK:
+ dev = add_generic_device_res("at91sam9x5ek", DEVICE_ID_SINGLE, NULL, 0, NULL);
+ if (!dev)
+ return;
+ sn |= ((binfo->id & 0x1f) << 20);
+ sn |= ((vendor_id & 0x1f) << 25);
+ rev |= ((info.revision_code - 'A') << 10);
+ rev |= (((info.revision_id - '0') & 0x3) << 21);
+ pr_info("EK");
+ break;
+ case BOARD_TYPE_DM:
+ dev = add_generic_device_res("at91sam9x5dm", DEVICE_ID_SINGLE, NULL, 0, NULL);
+ if (!dev)
+ return;
+ sn |= ((binfo->id & 0x1f) << 10);
+ sn |= ((vendor_id & 0x1f) << 15);
+ rev |= ((info.revision_code - 'A') << 5);
+ rev |= (((info.revision_id - '0') & 0x3) << 18);
+ pr_info("DM");
+ break;
+ }
+
+ pr_info(": %s [%c%c] from %s\n",
+ info.board_name, info.revision_code, info.revision_id,
+ info.vendor_name);
+
+ dev_add_param_fixed(dev, "vendor", info.vendor_name);
+ dev_add_param_fixed(dev, "board", info.board_name);
+ sprintf(str, "%.2s", info.vendor_country);
+ dev_add_param_fixed(dev, "country", str);
+ sprintf(str, "%d", info.year);
+ dev_add_param_fixed(dev, "year", str);
+ sprintf(str, "%d", info.week);
+ dev_add_param_fixed(dev, "week", str);
+ sprintf(str, "%c", info.revision_code);
+ dev_add_param_fixed(dev, "revision_code", str);
+ sprintf(str, "%c", info.revision_id);
+ dev_add_param_fixed(dev, "revision_id", str);
+}
+
+#define NODE_NAME_LEN 128
+
+static int cm_cogent_fixup(struct fdt_header *fdt)
+{
+ int off, ret;
+ char node_name[NODE_NAME_LEN];
+
+ off = fdt_node_offset_by_compatible(fdt, -1, "atmel,hsmci");
+
+ while (off != -FDT_ERR_NOTFOUND) {
+ off = fdt_subnode_offset(fdt, off, "slot");
+ fdt_get_path(fdt, off, node_name, NODE_NAME_LEN);
+ ret = fdt_setprop(fdt, off, "broken-cd", NULL, 0);
+ if (ret < 0) {
+ pr_err("error %d while adding broken-cd property to node %s\n",
+ ret, node_name);
+ return ret;
+ } else {
+ pr_debug("add broken-cd property to node %s\n", node_name);
+ }
+
+ off = fdt_node_offset_by_compatible(fdt, off, "atmel,hsmci");
+ }
+
+ return 0;
+}
+
+void at91sam9x5ek_devices_detect_hw(void)
+{
+ at91sam9x5ek_devices_detect_one("/dev/ds24310");
+ at91sam9x5ek_devices_detect_one("/dev/ds24311");
+ at91sam9x5ek_devices_detect_one("/dev/ds24330");
+
+ pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev);
+ armlinux_set_revision(rev);
+ armlinux_set_serial(sn);
+
+ if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT))
+ of_register_fixup(cm_cogent_fixup);
+}
diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.h b/arch/arm/boards/at91sam9x5ek/hw_version.h
new file mode 100644
index 0000000000..91fd42942d
--- /dev/null
+++ b/arch/arm/boards/at91sam9x5ek/hw_version.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#ifndef __HW_REVISION_H__
+#define __HW_REVISION_H__
+
+enum vendor_id {
+ VENDOR_UNKNOWN = 0,
+ VENDOR_EMBEST = 1,
+ VENDOR_FLEX = 2,
+ VENDOR_RONETIX = 3,
+ VENDOR_COGENT = 4,
+ VENDOR_PDA = 5,
+};
+
+bool at91sam9x5ek_cm_is_vendor(enum vendor_id vid);
+bool at91sam9x5ek_ek_is_vendor(enum vendor_id vid);
+bool at91sam9x5ek_dm_is_vendor(enum vendor_id vid);
+void at91sam9x5ek_devices_detect_hw(void);
+
+#endif /* __HW_REVISION_H__ */
diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c
index d7dc30def7..2536477316 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -36,8 +36,19 @@
#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
-#include <gpio_keys.h>
+#include <mach/at91sam9x5_matrix.h>
+#include <input/qt1070.h>
#include <readkey.h>
+#include <linux/w1-gpio.h>
+#include <w1_mac_address.h>
+#include <spi/spi.h>
+
+#include "hw_version.h"
+
+struct w1_gpio_platform_data w1_pdata = {
+ .pin = AT91_PIN_PB18,
+ .is_open_drain = 0,
+};
static struct atmel_nand_data nand_pdata = {
.ale = 21,
@@ -80,6 +91,14 @@ static void ek_add_device_nand(void)
/* configure chip-select 3 (NAND) */
sam9_smc_configure(3, &cm_nand_smc_config);
+ if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT)) {
+ unsigned long csa;
+
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ csa |= AT91_MATRIX_EBI_VDDIOMSEL_1_8V;
+ at91_sys_write(AT91_MATRIX_EBICSA, csa);
+ }
+
at91_add_device_nand(&nand_pdata);
}
@@ -88,6 +107,88 @@ static struct at91_ether_platform_data macb_pdata = {
.phy_addr = 0,
};
+static void ek_add_device_eth(void)
+{
+ if (w1_local_mac_address_register(0, "tml", "w1-2d-0"))
+ w1_local_mac_address_register(0, "tml", "w1-23-0");
+
+ at91_add_device_eth(0, &macb_pdata);
+}
+
+/*
+ * MCI (SD/MMC)
+ */
+/* mci0 detect_pin is revision dependent */
+static struct atmel_mci_platform_data mci0_data = {
+ .bus_width = 4,
+ .detect_pin = AT91_PIN_PD15,
+ .wp_pin = 0,
+};
+
+static void ek_add_device_mci(void)
+{
+ if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT))
+ mci0_data.detect_pin = 0;
+
+ /* MMC0 */
+ at91_add_device_mci(0, &mci0_data);
+}
+
+struct qt1070_platform_data qt1070_pdata = {
+ .irq_pin = AT91_PIN_PA7,
+};
+
+static struct i2c_board_info i2c_devices[] = {
+ {
+ .platform_data = &qt1070_pdata,
+ I2C_BOARD_INFO("qt1070", 0x1b),
+ }, {
+ I2C_BOARD_INFO("24c512", 0x51)
+ },
+};
+
+static void ek_add_device_i2c(void)
+{
+ at91_set_gpio_input(qt1070_pdata.irq_pin, 0);
+ at91_set_deglitch(qt1070_pdata.irq_pin, 1);
+ at91_add_device_i2c(0, i2c_devices, ARRAY_SIZE(i2c_devices));
+}
+
+static const struct spi_board_info ek_cm_cogent_spi_devices[] = {
+ {
+ .name = "mtd_dataflash",
+ .chip_select = 0,
+ .max_speed_hz = 15 * 1000 * 1000,
+ .bus_num = 0,
+ }
+};
+
+static const struct spi_board_info ek_spi_devices[] = {
+ {
+ .name = "m25p80",
+ .chip_select = 0,
+ .max_speed_hz = 30 * 1000 * 1000,
+ .bus_num = 0,
+ }
+};
+
+static unsigned spi0_standard_cs[] = { AT91_PIN_PA14};
+static struct at91_spi_platform_data spi_pdata = {
+ .chipselect = spi0_standard_cs,
+ .num_chipselect = ARRAY_SIZE(spi0_standard_cs),
+};
+
+static void ek_add_device_spi(void)
+{
+ if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT))
+ spi_register_board_info(ek_cm_cogent_spi_devices,
+ ARRAY_SIZE(ek_cm_cogent_spi_devices));
+ else
+ spi_register_board_info(ek_spi_devices,
+ ARRAY_SIZE(ek_spi_devices));
+ at91_add_device_spi(0, &spi_pdata);
+}
+
/*
* USB Host port
*/
@@ -130,12 +231,25 @@ static int at91sam9x5ek_mem_init(void)
}
mem_initcall(at91sam9x5ek_mem_init);
+static void ek_add_device_w1(void)
+{
+ at91_set_gpio_input(w1_pdata.pin, 0);
+ at91_set_multi_drive(w1_pdata.pin, 1);
+ add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata);
+
+ at91sam9x5ek_devices_detect_hw();
+}
+
static int at91sam9x5ek_devices_init(void)
{
+ ek_add_device_w1();
ek_add_device_nand();
- at91_add_device_eth(0, &macb_pdata);
+ ek_add_device_eth();
+ ek_add_device_spi();
+ ek_add_device_mci();
at91_add_device_usbh_ohci(&ek_usbh_data);
ek_add_led();
+ ek_add_device_i2c();
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(CONFIG_MACH_AT91SAM9X5EK);
@@ -157,7 +271,6 @@ static int at91sam9x5ek_console_init(void)
{
at91_register_uart(0, 0);
at91_register_uart(1, 0);
- at91_register_uart(2, 0);
return 0;
}
console_initcall(at91sam9x5ek_console_init);
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c
index 0b450d64e7..a8d172c0ff 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51.c
+++ b/arch/arm/boards/ccxmx51/ccxmx51.c
@@ -23,7 +23,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
@@ -45,6 +45,7 @@
#include <mach/iim.h>
#include <mach/clock-imx51_53.h>
#include <mach/imx5.h>
+#include <mach/revision.h>
#include "ccxmx51.h"
diff --git a/arch/arm/boards/ccxmx51/ccxmx51js.c b/arch/arm/boards/ccxmx51/ccxmx51js.c
index f04615d888..c947a1ee97 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51js.c
+++ b/arch/arm/boards/ccxmx51/ccxmx51js.c
@@ -20,7 +20,7 @@
#include <init.h>
#include <mci.h>
#include <asm/armlinux.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <mach/iomux-mx51.h>
#include <mach/devices-imx51.h>
#include <generated/mach-types.h>
diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile
new file mode 100644
index 0000000000..a63aeaef39
--- /dev/null
+++ b/arch/arm/boards/clep7212/Makefile
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o clep7212.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c
new file mode 100644
index 0000000000..a32337fafe
--- /dev/null
+++ b/arch/arm/boards/clep7212/clep7212.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+#include <partition.h>
+#include <io.h>
+#include <sizes.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+
+#include <mach/clps711x.h>
+#include <mach/devices.h>
+
+static int clps711x_mem_init(void)
+{
+ ulong memsize = get_ram_size((ulong *)SDRAM0_BASE, SZ_32M);
+
+ arm_add_mem_device("ram0", SDRAM0_BASE, memsize);
+
+ return 0;
+}
+mem_initcall(clps711x_mem_init);
+
+static int clps711x_devices_init(void)
+{
+ u32 serial_h = 0, serial_l = readl(UNIQID);
+
+ /* Setup Chipselects */
+ clps711x_setup_memcfg(0, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_16);
+ clps711x_setup_memcfg(1, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_8);
+ clps711x_setup_memcfg(2, MEMCFG_WAITSTATE_8_3 | MEMCFG_BUS_WIDTH_16 |
+ MEMCFG_CLKENB);
+ clps711x_setup_memcfg(3, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_32);
+
+ add_cfi_flash_device(0, CS0_BASE, SZ_32M, 0);
+
+ devfs_add_partition("nor0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED,
+ "self0");
+ devfs_add_partition("nor0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED,
+ "env0");
+
+ armlinux_set_bootparams((void *)SDRAM0_BASE + 0x100);
+ armlinux_set_architecture(MACH_TYPE_CLEP7212);
+ armlinux_set_serial(((u64)serial_h << 32) | serial_l);
+
+ return 0;
+}
+device_initcall(clps711x_devices_init);
+
+static int clps711x_console_init(void)
+{
+ clps711x_add_uart(0);
+
+ return 0;
+}
+console_initcall(clps711x_console_init);
diff --git a/arch/arm/boards/clep7212/config.h b/arch/arm/boards/clep7212/config.h
new file mode 100644
index 0000000000..6ae9a40e19
--- /dev/null
+++ b/arch/arm/boards/clep7212/config.h
@@ -0,0 +1,4 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/clep7212/env/bin/mtdparts-add b/arch/arm/boards/clep7212/env/bin/mtdparts-add
new file mode 100644
index 0000000000..ef1bc0215f
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/bin/mtdparts-add
@@ -0,0 +1,21 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "Partitions"
+ exit
+fi
+
+norparts="256k(barebox),256k(bareboxenv),3584k(kernel),-(root)"
+ramparts="-(ramdisk)"
+
+if [ -e /dev/nor0 ]; then
+ addpart -n /dev/nor0 "${norparts}"
+
+ global linux.mtdparts.nor
+ global.linux.mtdparts.nor="physmap-flash.0:${norparts}"
+else
+ echo "NOR Flash not found."
+fi
+
+global linux.mtdparts.ram
+global.linux.mtdparts.ram="mtd-ram.0:${ramparts}"
diff --git a/arch/arm/boards/clep7212/env/boot/nor b/arch/arm/boards/clep7212/env/boot/nor
new file mode 100644
index 0000000000..5cf1e15833
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/boot/nor
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ boot-menu-add-entry "$0" "NOR Flash"
+ exit
+fi
+
+global.bootm.image="/dev/kernel"
+global.linux.bootargs.dyn.root="root=/dev/mtdblock4 ro"
diff --git a/arch/arm/boards/clep7212/env/init/automount b/arch/arm/boards/clep7212/env/init/automount
new file mode 100644
index 0000000000..978b96450d
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/init/automount
@@ -0,0 +1,6 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "Automountpoints"
+ exit
+fi
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/env/init/bootargs-base b/arch/arm/boards/clep7212/env/init/bootargs-base
index 2c51febff7..ec08e39181 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/env/init/bootargs-base
+++ b/arch/arm/boards/clep7212/env/init/bootargs-base
@@ -5,4 +5,4 @@ if [ "$1" = menu ]; then
exit
fi
-global.linux.bootargs.base="console=ttymxc1,115200"
+global.linux.bootargs.base="earlyprintk console=ttyCL0,57600n8"
diff --git a/arch/arm/boards/clep7212/env/init/general b/arch/arm/boards/clep7212/env/init/general
new file mode 100644
index 0000000000..77e6a59e6b
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/init/general
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "general config settings"
+ exit
+fi
+
+global.user=barebox
+global.autoboot_timeout=2
+global.boot.default=nor
+
+/env/bin/mtdparts-add
diff --git a/arch/arm/boards/pcm038/env/init/hostname b/arch/arm/boards/clep7212/env/init/hostname
index 09c2f08c38..684ee63ba5 100644
--- a/arch/arm/boards/pcm038/env/init/hostname
+++ b/arch/arm/boards/clep7212/env/init/hostname
@@ -5,4 +5,4 @@ if [ "$1" = menu ]; then
exit
fi
-global.hostname=pcm038
+global.hostname=clep7212
diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
new file mode 100644
index 0000000000..9b7e2410f3
--- /dev/null
+++ b/arch/arm/boards/clep7212/lowlevel.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/io.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+
+#include <mach/clps711x.h>
+
+#define MAIN_CLOCK 3686400
+#define CPU_SPEED 92160000
+#define BUS_SPEED (CPU_SPEED / 2)
+
+#define PLL_VALUE (((CPU_SPEED * 2) / MAIN_CLOCK) << 24)
+#define SDRAM_REFRESH_RATE (64 * (BUS_SPEED / (8192 * 1000)))
+
+void __naked __bare_init reset(void)
+{
+ u32 tmp;
+
+ common_reset();
+
+ /* Setup base clock */
+ writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
+ asm("nop");
+
+ /* Setup PLL */
+ writel(PLL_VALUE, PLLW);
+ asm("nop");
+
+ /* CLKEN select, SDRAM width=32 */
+ writel(SYSCON2_CLKENSL, SYSCON2);
+
+ /* Enable SDQM pins */
+ tmp = readl(SYSCON3);
+ tmp &= ~SYSCON3_ENPD67;
+ writel(tmp, SYSCON3);
+
+ /* Setup Refresh Rate (64ms 8K Blocks) */
+ writel(SDRAM_REFRESH_RATE, SDRFPR);
+
+ /* Setup SDRAM (32MB, 16Bit*2, CAS=3) */
+ writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
+ SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
+
+ board_init_lowlevel_return();
+}
diff --git a/arch/arm/boards/crystalfontz-cfa10036/env/boot/mmc-ext3 b/arch/arm/boards/crystalfontz-cfa10036/env/boot/mmc-ext3
index 7d7eb50b37..b2325af1aa 100644
--- a/arch/arm/boards/crystalfontz-cfa10036/env/boot/mmc-ext3
+++ b/arch/arm/boards/crystalfontz-cfa10036/env/boot/mmc-ext3
@@ -7,4 +7,4 @@ fi
global.bootm.image="/mnt/disk0.1/zImage-cfa10036"
global.bootm.oftree="/mnt/disk0.1/oftree-cfa10036"
-bootargs-root-ext -r 3 -m mmcblk0p3
+global.linux.bootargs.dyn.root="root=/dev/mmcblk0p3 rootfstype=ext3 rootwait"
diff --git a/arch/arm/boards/crystalfontz-cfa10036/env/init/bootargs-base b/arch/arm/boards/crystalfontz-cfa10036/env/init/bootargs-base
deleted file mode 100644
index 4dda5501e3..0000000000
--- a/arch/arm/boards/crystalfontz-cfa10036/env/init/bootargs-base
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Base bootargs"
- exit
-fi
-
-global.linux.bootargs.base="console=ttyAMA0,115200"
diff --git a/arch/arm/boards/crystalfontz-cfa10036/env/init/config-board b/arch/arm/boards/crystalfontz-cfa10036/env/init/config-board
new file mode 100644
index 0000000000..b99866ecfe
--- /dev/null
+++ b/arch/arm/boards/crystalfontz-cfa10036/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=cfa10036
+global.linux.bootargs.base="console=ttyAMA0,115200"
diff --git a/arch/arm/boards/crystalfontz-cfa10036/env/init/hostname b/arch/arm/boards/crystalfontz-cfa10036/env/init/hostname
deleted file mode 100644
index 1dbe346fdf..0000000000
--- a/arch/arm/boards/crystalfontz-cfa10036/env/init/hostname
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "hostname"
- exit
-fi
-
-global.hostname=cfa10036
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index bf3cbc375a..92e8df2b9f 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -22,7 +22,7 @@
#include <init.h>
#include <driver.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <asm/armlinux.h>
#include <asm/barebox-arm.h>
#include <asm-generic/sections.h>
@@ -250,18 +250,3 @@ void __bare_init nand_boot(void)
imx_nand_load_image(_text, barebox_image_size);
}
#endif
-
-static int eukrea_cpuimx25_core_init(void) {
- /* enable UART1, FEC, SDHC, USB & I2C clock */
- writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR0) | (1 << 6) | (1 << 23)
- | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28),
- MX25_CCM_BASE_ADDR + CCM_CGCR0);
- writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR1) | (1 << 23) | (1 << 15)
- | (1 << 13), MX25_CCM_BASE_ADDR + CCM_CGCR1);
- writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR2) | (1 << 14),
- MX25_CCM_BASE_ADDR + CCM_CGCR2);
-
- return 0;
-}
-
-core_initcall(eukrea_cpuimx25_core_init);
diff --git a/arch/arm/boards/eukrea_cpuimx25/flash_header.c b/arch/arm/boards/eukrea_cpuimx25/flash_header.c
index 344c7ffc13..9102c2a371 100644
--- a/arch/arm/boards/eukrea_cpuimx25/flash_header.c
+++ b/arch/arm/boards/eukrea_cpuimx25/flash_header.c
@@ -23,7 +23,7 @@
*/
#include <common.h>
#include <mach/imx-flash-header.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index cd80b251be..36ce98bc69 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -19,7 +19,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <io.h>
@@ -36,8 +36,7 @@ static void __bare_init __naked insdram(void)
uint32_t r;
/* setup a stack to be able to call imx_nand_load_image() */
- r = STACK_BASE + STACK_SIZE - 12;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
@@ -57,15 +56,15 @@ void __bare_init __naked reset(void)
common_reset();
/* restart the MPLL and wait until it's stable */
- writel(readl(MX25_CCM_BASE_ADDR + CCM_CCTL) | (1 << 27),
- MX25_CCM_BASE_ADDR + CCM_CCTL);
- while (readl(MX25_CCM_BASE_ADDR + CCM_CCTL) & (1 << 27)) {};
+ writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27),
+ MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
+ while (readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) & (1 << 27)) {};
/* Configure dividers and ARM clock source
* ARM @ 400 MHz
* AHB @ 133 MHz
*/
- writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL);
+ writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
/* Enable UART1 / FEC / */
/* writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0);
@@ -118,10 +117,10 @@ void __bare_init __naked reset(void)
writel(0x1, 0xb8003000);
/* Speed up NAND controller by adjusting the NFC divider */
- r = readl(MX25_CCM_BASE_ADDR + CCM_PCDR2);
+ r = readl(MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
r &= ~0xf;
r |= 0x1;
- writel(r, MX25_CCM_BASE_ADDR + CCM_PCDR2);
+ writel(r, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -129,22 +128,22 @@ void __bare_init __naked reset(void)
board_init_lowlevel_return();
/* Init Mobile DDR */
- writel(0x0000000E, ESDMISC);
- writel(0x00000004, ESDMISC);
+ writel(0x0000000E, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x00000004, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
- writel(0x0029572B, ESDCFG0);
- writel(0x92210000, ESDCTL0);
+ writel(0x0029572B, MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+ writel(0x92210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400);
- writel(0xA2210000, ESDCTL0);
+ writel(0xA2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX25_CSD0_BASE_ADDR);
writeb(0xda, MX25_CSD0_BASE_ADDR);
- writel(0xB2210000, ESDCTL0);
+ writel(0xB2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33);
writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000);
- writel(0x82216080, ESDCTL0);
+ writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index cff4f77985..c89ce8a192 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -21,7 +21,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <fec.h>
#include <notifier.h>
#include <mach/gpio.h>
@@ -194,7 +194,6 @@ static int eukrea_cpuimx27_devices_init(void)
#endif
imx27_add_nand(&nand_info);
- PCCR0 |= PCCR0_I2C1_EN;
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx27_add_i2c0(NULL);
@@ -223,11 +222,16 @@ device_initcall(eukrea_cpuimx27_devices_init);
static int eukrea_cpuimx27_console_init(void)
{
+ uint32_t val;
+
#ifdef CONFIG_DRIVER_SERIAL_IMX
imx27_add_uart0();
#endif
/* configure 8 bit UART on cs3 */
- FMCR &= ~0x2;
+ val = readl(MX27_SYSCTRL_BASE_ADDR + MX27_FMCR);
+ val &= ~0x2;
+ writel(val, MX27_SYSCTRL_BASE_ADDR + MX27_FMCR);
+
imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000);
#ifdef CONFIG_DRIVER_SERIAL_NS16550
add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf,
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index 1983d480f9..4ee6efb84e 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -1,6 +1,7 @@
#include <config.h>
#include <asm-generic/memory_layout.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
+#include <mach/esdctl.h>
#include <asm/barebox-arm-head.h>
#define writel(val, reg) \
@@ -9,10 +10,10 @@
str r1, [r0];
#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
-#define ROWS0 ESDCTL_ROW14
+#define ROWS0 ESDCTL0_ROW14
#define CFG0 0x0029572D
#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
-#define ROWS0 ESDCTL_ROW13
+#define ROWS0 ESDCTL0_ROW13
#define CFG0 0x00095728
#endif
@@ -22,20 +23,26 @@
/*
* DDR on CSD0
*/
- writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */
-
- writel(0x55555555, DSCR(3)) /* Set the driving strength */
- writel(0x55555555, DSCR(5))
- writel(0x55555555, DSCR(6))
- writel(0x00005005, DSCR(7))
- writel(0x15555555, DSCR(8))
-
- writel(0x00000004, ESDMISC) /* Initial reset */
- writel(CFG0, ESDCFG0)
-
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */
+ /* Enable DDR SDRAM operation */
+ writel(0x0000000C, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
+
+ /* Set the driving strength */
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3))
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5))
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6))
+ writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7))
+ writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8))
+
+ /* Initial reset */
+ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
+ writel(CFG0, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
+
+ /* precharge CSD0 all banks */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xa0000f00
mov r1, #0
@@ -45,7 +52,8 @@
subs r2, #1
bne 1b
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xA0000033
mov r1, #0xda
strb r1, [r0]
@@ -56,7 +64,9 @@
#endif
mov r1, #0xff
strb r1, [r0]
- writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
.endm
.section ".text_bare_init","ax"
@@ -67,23 +77,26 @@ reset:
common_reset r0
/* ahb lite ip interface */
- writel(0x20040304, AIPI1_PSR0)
- writel(0xDFFBFCFB, AIPI1_PSR1)
- writel(0x00000000, AIPI2_PSR0)
- writel(0xFFFFFFFF, AIPI2_PSR1)
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
/* disable mpll/spll */
- ldr r0, =CSCR
+ ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR
ldr r1, [r0]
bic r1, r1, #0x03
str r1, [r0]
-
+
/*
* pll clock initialization - see section 3.4.3 of the i.MX27 manual
*/
- writel(0x00331C23, MPCTL0) /* MPLL = 399 MHz */
- writel(0x040C2403, SPCTL0) /* SPLL = 240 MHz */
- writel(0x33F38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
+ /* MPLL = 399 MHz */
+ writel(0x00331C23, MX27_CCM_BASE_ADDR + MX27_MPCTL0)
+ /* SPLL = 240 MHz */
+ writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0)
+ writel(0x33F38107 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
+ MX27_CCM_BASE_ADDR + MX27_CSCR)
/* add some delay here */
mov r1, #0x1000
@@ -91,12 +104,14 @@ reset:
bne 1b
/* clock gating enable */
- writel(0x00050f08, GPCR)
+ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR)
/* peripheral clock divider */
- writel(0x130400c3, PCDR0) /* FIXME */
- writel(0x09030208, PCDR1) /* PERDIV1=08 @133 MHz */
- /* PERDIV1=04 @266 MHz */
+ /* FIXME */
+ writel(0x130400c3, MX27_CCM_BASE_ADDR + MX27_PCDR0)
+ /* PERDIV1=08 @133 MHz */
+ writel(0x09030208, MX27_CCM_BASE_ADDR + MX27_PCDR1)
+ /* PERDIV1=04 @266 MHz */
/* skip sdram initialization if we run from ram */
cmp pc, #0xa0000000
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 53cc428c84..fdbc26ab42 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -41,7 +41,7 @@
#include <mach/gpio.h>
#include <mach/imx-nand.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/iomux-mx35.h>
#include <mach/iomux-v3.h>
#include <mach/imx-ipu-fb.h>
@@ -246,14 +246,14 @@ static int eukrea_cpuimx35_core_init(void)
u32 reg;
/* enable clock for I2C1, SDHC1, USB and FEC */
- reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
- reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
- reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT;
- reg |= 0x3 << CCM_CGR1_I2C1_SHIFT,
- reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1);
- reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR2);
- reg |= 0x3 << CCM_CGR2_USB_SHIFT;
- reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR2);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
+ reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
+ reg |= 0x3 << MX35_CCM_CGR1_SDHC1_SHIFT;
+ reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT,
+ reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR2);
+ reg |= 0x3 << MX35_CCM_CGR2_USB_SHIFT;
+ reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR2);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
@@ -345,10 +345,10 @@ static int do_cpufreq(int argc, char *argv[])
switch (freq) {
case 399:
- writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
case 532:
- writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
index 26752d1cbf..6fa9c8b0ef 100644
--- a/arch/arm/boards/eukrea_cpuimx35/flash_header.c
+++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
@@ -1,6 +1,6 @@
#include <common.h>
#include <mach/imx-flash-header.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index ea932f773e..052333503d 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
@@ -41,14 +41,13 @@ static void __bare_init __naked insdram(void)
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
- r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
+ r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
- writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
+ writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
- r = STACK_BASE + STACK_SIZE - 12;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
@@ -106,27 +105,27 @@ void __bare_init __naked reset(void)
* End of ARM1136 init
*/
- writel(0x003F4208, ccm_base + CCM_CCMR);
+ writel(0x003F4208, ccm_base + MX35_CCM_CCMR);
/* Set MPLL , arm clock and ahb clock*/
- writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL);
- writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
- writel(0x00001000, ccm_base + CCM_PDR0);
+ writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL);
+ writel(0x00001000, ccm_base + MX35_CCM_PDR0);
- r = readl(ccm_base + CCM_CGR0);
+ r = readl(ccm_base + MX35_CCM_CGR0);
r |= 0x00300000;
- writel(r, ccm_base + CCM_CGR0);
+ writel(r, ccm_base + MX35_CCM_CGR0);
- r = readl(ccm_base + CCM_CGR1);
+ r = readl(ccm_base + MX35_CCM_CGR1);
r |= 0x00030C00;
r |= 0x00000003;
- writel(r, ccm_base + CCM_CGR1);
+ writel(r, ccm_base + MX35_CCM_CGR1);
/* enable watchdog asap */
- r = readl(ccm_base + CCM_CGR2);
+ r = readl(ccm_base + MX35_CCM_CGR2);
r |= 0x03000000;
- writel(r, ccm_base + CCM_CGR2);
+ writel(r, ccm_base + MX35_CCM_CGR2);
r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
r |= 0x1000;
@@ -138,22 +137,22 @@ void __bare_init __naked reset(void)
board_init_lowlevel_return();
/* Init Mobile DDR */
- writel(0x0000000E, ESDMISC);
- writel(0x00000004, ESDMISC);
+ writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
- writel(0x0009572B, ESDCFG0);
- writel(0x92220000, ESDCTL0);
+ writel(0x0009572B, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+ writel(0x92220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400);
- writel(0xA2220000, ESDCTL0);
+ writel(0xA2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX35_CSD0_BASE_ADDR);
writeb(0xda, MX35_CSD0_BASE_ADDR);
- writel(0xB2220000, ESDCTL0);
+ writel(0xB2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33);
writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000);
- writel(0x82228080, ESDCTL0);
+ writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index 1279f8965a..ab0ff81d73 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -19,7 +19,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index a0ae938809..5ce2f8e290 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -21,7 +21,7 @@
#include <init.h>
#include <driver.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
@@ -167,8 +167,8 @@ static int imx25_3ds_fec_init(void)
* FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
* FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12
*/
- writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */
- writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */
+ writel(0x8, MX25_IOMUXC_BASE_ADDR + 0x0238); /* open drain */
+ writel(0x0, MX25_IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */
#define FEC_ENABLE_GPIO 35
#define FEC_RESET_B_GPIO 104
@@ -215,7 +215,7 @@ static int imx25_devices_init(void)
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
- if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14))
+ if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14))
nand_info.width = 2;
imx25_add_nand(&nand_info);
@@ -298,7 +298,7 @@ void __bare_init nand_boot(void)
static int imx25_core_setup(void)
{
- writel(0x01010103, MX25_CCM_BASE_ADDR + CCM_PCDR2);
+ writel(0x01010103, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
return 0;
}
diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
index f911f9d7f8..fb980991a6 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
@@ -18,7 +18,7 @@
*/
#include <asm-generic/memory_layout.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/barebox-arm-head.h>
@@ -66,9 +66,9 @@ reset:
str r1, [r0, #MX25_CCM_MCR]
/* enable all the clocks */
- writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0)
- writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1)
- writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2)
+ writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0)
+ writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1)
+ writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2)
writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR)
/* Skip SDRAM initialization if we run from RAM */
diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c
index 7cd61f9e96..5bcb24cf45 100644
--- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c
+++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c
@@ -236,7 +236,7 @@ static int mx28_evk_devices_init(void)
imx_enable_enetclk();
mx28_evk_fec_reset();
- add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0x4000,
+ add_generic_device("imx28-fec", 0, NULL, IMX_FEC0_BASE, 0x4000,
IORESOURCE_MEM, &fec_info);
return 0;
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 9a01424402..7da031ab6b 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -41,12 +41,13 @@
#include <mach/gpio.h>
#include <mach/weim.h>
#include <mach/imx-nand.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/iomux-mx35.h>
#include <mach/iomux-v3.h>
#include <mach/imx-ipu-fb.h>
#include <mach/generic.h>
#include <mach/devices-imx35.h>
+#include <mach/revision.h>
#include <i2c/i2c.h>
#include <mfd/mc13xxx.h>
@@ -143,7 +144,7 @@ static int f3s_devices_init(void)
/* CS0: Nor Flash */
imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
- reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
@@ -281,10 +282,10 @@ static int f3s_core_init(void)
imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00);
/* enable clock for I2C1 and FEC */
- reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
- reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
- reg |= 0x3 << CCM_CGR1_I2C1_SHIFT;
- reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
+ reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
+ reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
+ reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
diff --git a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
index 66763dbf2a..076b816491 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
@@ -1,6 +1,6 @@
#include <common.h>
#include <mach/imx-flash-header.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
index e5d0feb18f..dada5f3fd5 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
@@ -17,7 +17,7 @@
*
*/
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
@@ -98,27 +98,27 @@ reset:
ldr r0, CCM_BASE_ADDR_W
ldr r2, CCM_CCMR_W
- str r2, [r0, #CCM_CCMR]
+ str r2, [r0, #MX35_CCM_CCMR]
ldr r3, MPCTL_PARAM_532_W /* consumer path*/
/* Set MPLL, arm clock and ahb clock */
- str r3, [r0, #CCM_MPCTL]
+ str r3, [r0, #MX35_CCM_MPCTL]
ldr r1, PPCTL_PARAM_W
- str r1, [r0, #CCM_PPCTL]
+ str r1, [r0, #MX35_CCM_PPCTL]
ldr r1, CCM_PDR0_W
- str r1, [r0, #CCM_PDR0]
+ str r1, [r0, #MX35_CCM_PDR0]
- ldr r1, [r0, #CCM_CGR0]
+ ldr r1, [r0, #MX35_CCM_CGR0]
orr r1, r1, #0x00300000
- str r1, [r0, #CCM_CGR0]
+ str r1, [r0, #MX35_CCM_CGR0]
- ldr r1, [r0, #CCM_CGR1]
+ ldr r1, [r0, #MX35_CCM_CGR1]
orr r1, r1, #0x00000C00
orr r1, r1, #0x00000003
- str r1, [r0, #CCM_CGR1]
+ str r1, [r0, #MX35_CCM_CGR1]
/* Skip SDRAM initialization if we run from RAM */
cmp pc, #CSD0_BASE_ADDR
@@ -140,13 +140,13 @@ reset:
/* setup bank 0 */
mov r5, #0x00
mov r2, #0x00
- mov r1, #CSD0_BASE_ADDR
+ mov r1, #MX35_CSD0_BASE_ADDR
bl setup_sdram_bank
/* setup bank 1 */
mov r5, #0x00
mov r2, #0x00
- mov r1, #CSD1_BASE_ADDR
+ mov r1, #MX35_CSD1_BASE_ADDR
bl setup_sdram_bank
mov lr, fp
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
index 3a8e5eaf04..9db0ed9bef 100644
--- a/arch/arm/boards/freescale-mx51-pdk/board.c
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -17,7 +17,7 @@
#include <common.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
@@ -25,6 +25,7 @@
#include <partition.h>
#include <fs.h>
#include <fcntl.h>
+#include <mach/bbu.h>
#include <nand.h>
#include <notifier.h>
#include <spi/spi.h>
@@ -37,7 +38,9 @@
#include <mach/generic.h>
#include <mach/iomux-mx51.h>
#include <mach/devices-imx51.h>
+#include <mach/revision.h>
#include <mach/iim.h>
+#include <mach/imx-flash-header.h>
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
@@ -234,6 +237,10 @@ static void babbage_power_init(void)
mdelay(50);
}
+#define DCD_NAME static struct imx_dcd_entry dcd_entry
+
+#include "dcd-data.h"
+
static int f3s_devices_init(void)
{
spi_register_board_info(mx51_babbage_spi_board_info,
@@ -254,6 +261,9 @@ static int f3s_devices_init(void)
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
+ imx51_bbu_internal_mmc_register_handler("mmc", "/dev/disk0",
+ BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry));
+
return 0;
}
diff --git a/arch/arm/boards/freescale-mx51-pdk/dcd-data.h b/arch/arm/boards/freescale-mx51-pdk/dcd-data.h
new file mode 100644
index 0000000000..4dd6c0d26c
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/dcd-data.h
@@ -0,0 +1,60 @@
+
+DCD_NAME[] = {
+ { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, },
+ { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, },
+ { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, },
+ { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, },
+ { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, },
+ { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, },
+ { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, },
+ { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, },
+ { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, },
+ { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, },
+ { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, },
+ { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, },
+ { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, },
+ { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, },
+ { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, },
+ { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, },
+ { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, },
+ { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, },
+ { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, },
+ { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, },
+ { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, },
+ { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, },
+ { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, },
+ { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, },
+ { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, },
+ { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, },
+ { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, },
+};
+
diff --git a/arch/arm/boards/freescale-mx51-pdk/env/init/config-board b/arch/arm/boards/freescale-mx51-pdk/env/init/config-board
new file mode 100644
index 0000000000..cfc483eb3d
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=babbage
+global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/freescale-mx51-pdk/env/init/hostname b/arch/arm/boards/freescale-mx51-pdk/env/init/hostname
deleted file mode 100644
index 4c78902a17..0000000000
--- a/arch/arm/boards/freescale-mx51-pdk/env/init/hostname
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "hostname"
- exit
-fi
-
-global.hostname=babbage
diff --git a/arch/arm/boards/freescale-mx51-pdk/flash_header.c b/arch/arm/boards/freescale-mx51-pdk/flash_header.c
index c148eea4ff..f3f1e4bfd5 100644
--- a/arch/arm/boards/freescale-mx51-pdk/flash_header.c
+++ b/arch/arm/boards/freescale-mx51-pdk/flash_header.c
@@ -7,64 +7,9 @@ void __naked __flash_header_start go(void)
barebox_arm_head();
}
-struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
- { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, },
- { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, },
- { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, },
- { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, },
- { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, },
- { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, },
- { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, },
- { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, },
- { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, },
- { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, },
- { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, },
- { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, },
- { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, },
- { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, },
- { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, },
- { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, },
- { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, },
- { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, },
- { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, },
- { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, },
- { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, },
- { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, },
- { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, },
- { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, },
- { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, },
- { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, },
- { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, },
- { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, },
- { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, },
- { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, },
- { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, },
- { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, },
-};
+#define DCD_NAME struct imx_dcd_entry __dcd_entry_section dcd_entry
+
+#include "dcd-data.h"
#define APP_DEST 0x90000000
diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c
index 0d715559dc..216d26a0a8 100644
--- a/arch/arm/boards/freescale-mx53-loco/board.c
+++ b/arch/arm/boards/freescale-mx53-loco/board.c
@@ -27,7 +27,7 @@
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
@@ -35,6 +35,9 @@
#include <mach/imx-nand.h>
#include <mach/iim.h>
#include <mach/imx5.h>
+#include <mach/revision.h>
+#include <mach/bbu.h>
+#include <mach/imx-flash-header.h>
#include <i2c/i2c.h>
#include <mfd/mc34708.h>
@@ -176,10 +179,15 @@ static void loco_ehci_init(void)
add_generic_usb_ehci_device(1, MX53_OTG_BASE_ADDR + 0x200, NULL);
}
+#define DCD_NAME static struct imx_dcd_v2_entry dcd_entry
+
+#include "dcd-data.h"
+
static int loco_devices_init(void)
{
imx53_iim_register_fec_ethaddr();
+ loco_fec_reset();
imx53_add_fec(&fec_info);
imx53_add_mmc0(&loco_sd1_data);
imx53_add_mmc2(&loco_sd3_data);
@@ -189,13 +197,14 @@ static int loco_devices_init(void)
if (IS_ENABLED(CONFIG_USB_EHCI))
loco_ehci_init();
- loco_fec_reset();
-
set_silicon_rev(imx_silicon_revision());
armlinux_set_bootparams((void *)0x70000100);
armlinux_set_architecture(MACH_TYPE_MX53_LOCO);
+ imx53_bbu_internal_mmc_register_handler("mmc", "/dev/disk0",
+ BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry));
+
return 0;
}
diff --git a/arch/arm/boards/freescale-mx53-loco/dcd-data.h b/arch/arm/boards/freescale-mx53-loco/dcd-data.h
new file mode 100644
index 0000000000..9f95fb4b89
--- /dev/null
+++ b/arch/arm/boards/freescale-mx53-loco/dcd-data.h
@@ -0,0 +1,54 @@
+
+DCD_NAME[] = {
+ { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), },
+ { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), },
+ { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), },
+ { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), },
+ { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), },
+ { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), },
+ { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), },
+ { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), },
+ { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), },
+ { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), },
+ { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), },
+ { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), },
+ { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), },
+ { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), },
+ { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), },
+ { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), },
+ { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), },
+ { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
+ { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), },
+ { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), },
+ { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
+ { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
+ { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
+ { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
+};
diff --git a/arch/arm/boards/freescale-mx53-loco/flash_header.c b/arch/arm/boards/freescale-mx53-loco/flash_header.c
index c2ab25582e..dc1162bac8 100644
--- a/arch/arm/boards/freescale-mx53-loco/flash_header.c
+++ b/arch/arm/boards/freescale-mx53-loco/flash_header.c
@@ -23,59 +23,9 @@ void __naked __flash_header_start go(void)
barebox_arm_head();
}
-struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
- { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), },
- { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), },
- { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), },
- { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), },
- { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), },
- { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), },
- { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), },
- { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), },
- { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), },
- { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), },
- { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), },
- { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), },
- { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), },
- { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), },
- { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), },
- { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), },
- { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), },
- { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
- { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), },
- { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), },
- { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
- { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
- { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
- { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
-};
+#define DCD_NAME struct imx_dcd_v2_entry __dcd_entry_section dcd_entry
+
+#include "dcd-data.h"
#define APP_DEST 0x70000000
diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c
index 04831030a8..a5ad009106 100644
--- a/arch/arm/boards/freescale-mx53-smd/board.c
+++ b/arch/arm/boards/freescale-mx53-smd/board.c
@@ -27,7 +27,7 @@
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
diff --git a/arch/arm/boards/freescale-mx6-arm2/board.c b/arch/arm/boards/freescale-mx6-arm2/board.c
index ccc73182db..ce9874d85f 100644
--- a/arch/arm/boards/freescale-mx6-arm2/board.c
+++ b/arch/arm/boards/freescale-mx6-arm2/board.c
@@ -15,7 +15,7 @@
#include <common.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx6-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c
index 25402d7c9c..da37e17b8f 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/board.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c
@@ -17,7 +17,7 @@
#include <common.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx6-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
@@ -200,7 +200,7 @@ static inline int imx6_iim_register_fec_ethaddr(void)
return 0;
}
-static int sabrelite_spi_cs[] = {GPIO_PORTC + 19};
+static int sabrelite_spi_cs[] = {IMX_GPIO_NR(3, 19)};
static struct spi_imx_master sabrelite_spi_0_data = {
.chipselect = sabrelite_spi_cs,
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/env/init/config-board b/arch/arm/boards/freescale-mx6-sabrelite/env/init/config-board
new file mode 100644
index 0000000000..e39e4b6141
--- /dev/null
+++ b/arch/arm/boards/freescale-mx6-sabrelite/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=SabreLite
+global.linux.bootargs.base="console=ttymxc1,115200"
diff --git a/arch/arm/boards/friendlyarm-tiny210/Makefile b/arch/arm/boards/friendlyarm-tiny210/Makefile
index 9c38e6038b..20060a53e3 100644
--- a/arch/arm/boards/friendlyarm-tiny210/Makefile
+++ b/arch/arm/boards/friendlyarm-tiny210/Makefile
@@ -1 +1,2 @@
obj-y += tiny210.o lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index 933a9cd057..5b1732631a 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -25,7 +25,7 @@
#include <driver.h>
#include <environment.h>
#include <fs.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <asm/armlinux.h>
#include <mach/gpio.h>
#include <io.h>
@@ -117,7 +117,7 @@ static int cupid_devices_init(void)
gpio_direction_output(GPIO_LCD_ENABLE, 0);
gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
- reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
@@ -339,10 +339,10 @@ static int do_cpufreq(int argc, char *argv[])
switch (freq) {
case 399:
- writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
case 532:
- writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index d451fd9393..f2e44af7a5 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
@@ -54,8 +54,7 @@ static void __bare_init __naked insdram(void)
writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
- r = STACK_BASE + STACK_SIZE - 12;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
@@ -71,15 +70,15 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
u32 r1, r0;
/* disable second SDRAM region to save power */
- r1 = readl(ESDCTL1);
+ r1 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
r1 &= ~ESDCTL0_SDE;
- writel(r1, ESDCTL1);
+ writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
mode |= ESDMISC_RST | ESDMISC_MDDR_DL_RST;
- writel(mode, ESDMISC);
+ writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
mode &= ~(ESDMISC_RST | ESDMISC_MDDR_DL_RST);
- writel(mode, ESDMISC);
+ writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
/* wait for esdctl reset */
for (loop = 0; loop < 0x20000; loop++);
@@ -90,16 +89,18 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 |
ESDCFGx_tRCD_3 | ESDCFGx_tRC_20;
- writel(r1, ESDCFG0);
+ writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
/* enable SDRAM controller */
- writel(memsize | ESDCTL0_SMODE_NORMAL, ESDCTL0);
+ writel(memsize | ESDCTL0_SMODE_NORMAL,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
/* Micron Datasheet Initialization Step 3: Wait 200us before first command */
for (loop = 0; loop < 1000; loop++);
/* Micron Datasheet Initialization Step 4: PRE CHARGE ALL */
- writel(memsize | ESDCTL0_SMODE_PRECHARGE, ESDCTL0);
+ writel(memsize | ESDCTL0_SMODE_PRECHARGE,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(r11, sdram_addr);
/* Micron Datasheet Initialization Step 5: NOP for tRP (at least 22.5ns)
@@ -109,7 +110,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
/* Micron Datasheet Initialization Step 6: 2 AUTO REFRESH and tRFC NOP
* (at least 140ns)
*/
- writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0);
+ writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(r11, r9); /* AUTO REFRESH #1 */
for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */
@@ -119,7 +121,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */
/* Micron Datasheet Initialization Step 7: LOAD MODE REGISTER */
- writel(memsize | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0);
+ writel(memsize | ESDCTL0_SMODE_LOAD_MODE,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(r11, r9 + (SDRAM_MODE_BL_8 | SDRAM_MODE_BSEQ | SDRAM_MODE_CL_3));
/* Micron Datasheet Initialization Step 8: tMRD = 2 tCK NOP
@@ -134,7 +137,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
*/
/* Now configure SDRAM-Controller and check that it works */
- writel(memsize | ESDCTL0_BL | ESDCTL0_REF4, ESDCTL0);
+ writel(memsize | ESDCTL0_BL | ESDCTL0_REF4,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
/* Freescale asks for first access to be a write to properly
* initialize DQS pin-state and keepers
@@ -156,10 +160,10 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
/* if both value are identical, we don't have 14 rows. assume 13 instead */
if (readl(r9) == readl(r9 + (1 << 25))) {
- r0 = readl(ESDCTL0);
+ r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
r0 &= ~ESDCTL0_ROW_MASK;
r0 |= ESDCTL0_ROW13;
- writel(r0, ESDCTL0);
+ writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
}
/* So far we asssumed that we have 10 columns, verify this */
@@ -168,10 +172,10 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
/* if both value are identical, we don't have 10 cols. assume 9 instead */
if (readl(r9) == readl(r9 + (1 << 11))) {
- r0 = readl(ESDCTL0);
+ r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
r0 &= ~ESDCTL0_COL_MASK;
r0 |= ESDCTL0_COL9;
- writel(r0, ESDCTL0);
+ writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
}
}
@@ -182,7 +186,7 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
void __bare_init __naked reset(void)
{
u32 r0, r1;
- void *iomuxc_base = (void *)IMX_IOMUXC_BASE;
+ void *iomuxc_base = (void *)MX35_IOMUXC_BASE_ADDR;
int i;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
@@ -190,8 +194,7 @@ void __bare_init __naked reset(void)
common_reset();
- r0 = 0x10000000 + 128 * 1024 - 16;
- __asm__ __volatile__("mov sp, %0" : : "r"(r0));
+ arm_setup_stack(0x10000000 + 128 * 1024 - 16);
/*
* ARM1136 init
@@ -299,27 +302,27 @@ void __bare_init __naked reset(void)
/* Configure clocks */
/* setup cpu/bus clocks */
- writel(0x003f4208, MX35_CCM_BASE_ADDR + CCM_CCMR);
+ writel(0x003f4208, MX35_CCM_BASE_ADDR + MX35_CCM_CCMR);
/* configure MPLL */
- writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
/* configure PPLL */
- writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + CCM_PPCTL);
+ writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + MX35_CCM_PPCTL);
/* configure core dividers */
- r0 = PDR0_CCM_PER_AHB(1) | PDR0_HSP_PODF(2);
+ r0 = MX35_PDR0_CCM_PER_AHB(1) | MX35_PDR0_HSP_PODF(2);
- writel(r0, MX35_CCM_BASE_ADDR + CCM_PDR0);
+ writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR0);
/* configure clock-gates */
- r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR0);
+ r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
r0 |= 0x00300000;
- writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR0);
+ writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
- r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
+ r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
r0 |= 0x00000c03;
- writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR1);
+ writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
/* Configure SDRAM */
/* Try 32-Bit 256 MB DDR memory */
diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c
index 7adee929b0..200a2efc53 100644
--- a/arch/arm/boards/guf-neso/board.c
+++ b/arch/arm/boards/guf-neso/board.c
@@ -35,7 +35,7 @@
#include <mach/gpio.h>
#include <mach/spi.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/iomux-mx27.h>
#include <mach/imx-nand.h>
#include <mach/imx-pll.h>
@@ -320,10 +320,10 @@ static int neso_pll(void)
pllfunc();
/* clock gating enable */
- GPCR = 0x00050f08;
+ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR);
- PCDR0 = 0x130410c3;
- PCDR1 = 0x09030911;
+ writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0);
+ writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1);
/* Clocks have changed. Notify clients */
clock_notifier_call_chain();
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
index 52fe6cffa8..ad414d9208 100644
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ b/arch/arm/boards/guf-neso/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
@@ -33,13 +33,8 @@
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
- uint32_t r;
-
- PCCR1 |= PCCR1_NFC_BAUDEN;
-
/* setup a stack to be able to call imx_nand_load_image() */
- r = STACK_BASE + STACK_SIZE - 12;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
@@ -60,10 +55,10 @@ void __bare_init __naked reset(void)
common_reset();
/* ahb lite ip interface */
- AIPI1_PSR0 = 0x20040304;
- AIPI1_PSR1 = 0xDFFBFCFB;
- AIPI2_PSR0 = 0x00000000;
- AIPI2_PSR1 = 0xFFFFFFFF;
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -73,30 +68,38 @@ void __bare_init __naked reset(void)
/*
* DDR on CSD0
*/
- writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */
-
- DSCR(3) = 0x55555555; /* Set the driving strength */
- DSCR(5) = 0x55555555;
- DSCR(6) = 0x55555555;
- DSCR(7) = 0x00005005;
- DSCR(8) = 0x15555555;
-
- writel(0x00000004, ESDMISC); /* Initial reset */
- writel(0x006ac73a, ESDCFG0);
-
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */
+ /* Enable DDR SDRAM operation */
+ writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+
+ /* Set the driving strength */
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
+ writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
+ writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
+
+ /* Initial reset */
+ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+
+ /* precharge CSD0 all banks */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0);
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
for (i = 0; i < 8; i++)
writel(0, 0xa0000f00);
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0);
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, 0xa0000033);
writeb(0xff, 0xa1000000);
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
- ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0);
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/guf-neso/pll_init.S b/arch/arm/boards/guf-neso/pll_init.S
index 87e5312fb4..4c6cb67fd4 100644
--- a/arch/arm/boards/guf-neso/pll_init.S
+++ b/arch/arm/boards/guf-neso/pll_init.S
@@ -1,5 +1,5 @@
#include <config.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <linux/linkage.h>
@@ -8,34 +8,37 @@
ldr r1, =val; \
str r1, [r0];
-#define CSCR_VAL CSCR_USB_DIV(3) | \
- CSCR_SD_CNT(3) | \
- CSCR_MSHC_SEL | \
- CSCR_H264_SEL | \
- CSCR_SSI1_SEL | \
- CSCR_SSI2_SEL | \
- CSCR_MCU_SEL | \
- CSCR_ARM_SRC_MPLL | \
- CSCR_SP_SEL | \
- CSCR_ARM_DIV(0) | \
- CSCR_FPM_EN | \
- CSCR_SPEN | \
- CSCR_MPEN | \
- CSCR_AHB_DIV(1)
+#define CSCR_VAL MX27_CSCR_USB_DIV(3) | \
+ MX27_CSCR_SD_CNT(3) | \
+ MX27_CSCR_MSHC_SEL | \
+ MX27_CSCR_H264_SEL | \
+ MX27_CSCR_SSI1_SEL | \
+ MX27_CSCR_SSI2_SEL | \
+ MX27_CSCR_MCU_SEL | \
+ MX27_CSCR_ARM_SRC_MPLL | \
+ MX27_CSCR_SP_SEL | \
+ MX27_CSCR_ARM_DIV(0) | \
+ MX27_CSCR_FPM_EN | \
+ MX27_CSCR_SPEN | \
+ MX27_CSCR_MPEN | \
+ MX27_CSCR_AHB_DIV(1)
ENTRY(neso_pll_init)
+ /* 399 MHz */
writel(IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
- IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */
+ IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0)
+ /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
writel(IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
- IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
+ IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0)
- writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
+ writel(CSCR_VAL | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
+ MX27_CCM_BASE_ADDR + MX27_CSCR)
ldr r2, =16000
1:
diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c
index 22406beb5a..ca566c831a 100644
--- a/arch/arm/boards/imx21ads/imx21ads.c
+++ b/arch/arm/boards/imx21ads/imx21ads.c
@@ -21,7 +21,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx21-regs.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
@@ -95,10 +95,10 @@ static int imx21ads_timing_init(void)
imx21_setup_eimcs(4, 0x0, 0x0);
imx21_setup_eimcs(5, 0x0, 0x0);
- temp = PCDR0;
+ temp = readl(MX21_CCM_BASE_ADDR + MX21_PCDR0);
temp &= ~0xF000;
temp |= 0xA000; /* Set NFC divider; 0xA yields 24.18MHz */
- PCDR0 = temp;
+ writel(temp, MX21_CCM_BASE_ADDR + MX21_PCDR0);
return 0;
}
@@ -193,7 +193,6 @@ console_initcall(mx21ads_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
- PCCR0 |= PCCR0_NFC_EN;
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S
index 0cb8aaf950..e52cac1443 100644
--- a/arch/arm/boards/imx21ads/lowlevel_init.S
+++ b/arch/arm/boards/imx21ads/lowlevel_init.S
@@ -15,7 +15,7 @@
#include <config.h>
#include <asm-generic/memory_layout.h>
-#include <mach/imx-regs.h>
+#include <mach/imx21-regs.h>
#include <asm/barebox-arm-head.h>
.section ".text_bare_init","ax"
@@ -30,17 +30,17 @@ reset:
* on chip peripherals) as described in section 7.2 of rev3 of the i.MX21
* reference manual.
*/
- ldr r0, =AIPI1_PSR0
+ ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR0
ldr r1, =0x00040304
str r1, [r0]
- ldr r0, =AIPI1_PSR1
+ ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR1
ldr r1, =0xfffbfcfb
str r1, [r0]
- ldr r0, =AIPI2_PSR0
+ ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR0
ldr r1, =0x3ffc0000
str r1, [r0]
- ldr r0, =AIPI2_PSR1
+ ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR1
ldr r1, =0xffffffff
str r1, [r0]
@@ -48,11 +48,11 @@ reset:
* Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable
* the clock to peripherals.
*/
- ldr r0, =CSCR
+ ldr r0, =MX21_CCM_BASE_ADDR + MX21_CSCR
ldr r1, =0x17180607
str r1, [r0]
- ldr r0, =PCCR1
+ ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCCR1
ldr r1, =0x0e000000
str r1, [r0]
@@ -65,7 +65,7 @@ reset:
* CSD1 not required, because the MX21ADS board only contains 64Mbyte.
* CS3 can therefore be made available.
*/
- ldr r0, =FMCR
+ ldr r0, =MX21_SYSCTRL_BASE_ADDR + MX21_FMCR
ldr r1, =0xffffffc9
str r1, [r0]
@@ -79,7 +79,7 @@ reset:
1:
/* Precharge */
- ldr r0, =SDCTL0
+ ldr r0, =MX21_X_MEMC_BASE_ADDR + MX21_SDCTL0
ldr r1, =0x92120300
str r1, [r0]
ldr r2, =0xc0200000
@@ -113,7 +113,7 @@ reset:
str r1, [r0]
/* Set NFC_CLK to 24MHz */
- ldr r0, =PCDR0
+ ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCDR0
ldr r1, =0x6419a007
str r1, [r0]
diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c
index 22c6e40f9f..f41b155d16 100644
--- a/arch/arm/boards/imx27ads/imx27ads.c
+++ b/arch/arm/boards/imx27ads/imx27ads.c
@@ -18,7 +18,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <asm/armlinux.h>
#include <io.h>
#include <fec.h>
diff --git a/arch/arm/boards/imx27ads/lowlevel_init.S b/arch/arm/boards/imx27ads/lowlevel_init.S
index 1bebb1d0a4..2dc34b5967 100644
--- a/arch/arm/boards/imx27ads/lowlevel_init.S
+++ b/arch/arm/boards/imx27ads/lowlevel_init.S
@@ -5,7 +5,7 @@
*/
#include <config.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <asm/barebox-arm-head.h>
#define writel(val, reg) \
@@ -118,13 +118,13 @@ reset:
common_reset r0
/* ahb lite ip interface */
- writel(0x20040304, AIPI1_PSR0)
- writel(0xDFFBFCFB, AIPI1_PSR1)
- writel(0x00000000, AIPI2_PSR0)
- writel(0xFFFFFFFF, AIPI2_PSR1)
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
/* disable mpll/spll */
- ldr r0, =CSCR
+ ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR
ldr r1, [r0]
bic r1, r1, #0x03
str r1, [r0]
@@ -136,15 +136,16 @@ reset:
* with 1.2 V core voltage! Find out if this is
* documented somewhere.
*/
- writel(0x00191403, MPCTL0) /* MPLL = 199.5*2 MHz */
- writel(0x040C2403, SPCTL0) /* SPLL = FIXME (needs review) */
+ writel(0x00191403, MX27_CCM_BASE_ADDR + MX27_MPCTL0) /* MPLL = 199.5*2 MHz */
+ writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) /* SPLL = FIXME (needs review) */
/*
* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
* System clock (HCLK) = 133 MHz
*/
- writel(0x33F30307 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
+ writel(0x33F30307 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
+ MX27_CCM_BASE_ADDR + MX27_CSCR)
/* add some delay here */
mov r1, #0x1000
@@ -152,13 +153,14 @@ reset:
bne 1b
/* clock gating enable */
- writel(0x00050f08, GPCR)
+ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR)
/* peripheral clock divider */
- writel(0x23C8F403, PCDR0) /* FIXME */
- writel(0x09030913, PCDR1) /* PERDIV1=08 @133 MHz */
- /* PERDIV1=04 @266 MHz *
- * /
+ /* FIXME */
+ writel(0x23C8F403, MX27_CCM_BASE_ADDR + MX27_PCDR0)
+ /* PERDIV1=08 @133 MHz */
+ /* PERDIV1=04 @266 MHz */
+ writel(0x09030913, MX27_CCM_BASE_ADDR + MX27_PCDR1)
/* skip sdram initialization if we run from ram */
cmp pc, #0xa0000000
bls 1f
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 5413ea801c..1ffd890dd6 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -21,7 +21,7 @@
#include <init.h>
#include <driver.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
@@ -75,8 +75,8 @@ static iomux_v3_cfg_t karo_tx25_padsd_fec[] = {
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
};
-#define TX25_FEC_PWR_GPIO (GPIO_PORTD | 9)
-#define TX25_FEC_RST_GPIO (GPIO_PORTD | 7)
+#define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9)
+#define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7)
static void noinline gpio_fec_active(void)
{
@@ -108,7 +108,7 @@ static int tx25_devices_init(void)
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
- if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14))
+ if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14))
nand_info.width = 2;
imx25_add_nand(&nand_info);
@@ -217,9 +217,9 @@ static struct imx_fb_videomode stk5_fb_mode = {
.pcr = PCR_TFT | PCR_COLOR | PCR_FLMPOL | PCR_LPPOL | PCR_SCLK_SEL,
};
-#define STK5_LCD_BACKLIGHT_GPIO (GPIO_PORTA | 26)
-#define STK5_LCD_RESET_GPIO (GPIO_PORTB | 4)
-#define STK5_LCD_POWER_GPIO (GPIO_PORTB | 5)
+#define STK5_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 26)
+#define STK5_LCD_RESET_GPIO IMX_GPIO_NR(2, 4)
+#define STK5_LCD_POWER_GPIO IMX_GPIO_NR(2, 5)
static void tx25_fb_enable(int enable)
{
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index 3192abdeb6..9c5cc5c8ee 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <mach/esdctl.h>
#include <io.h>
#include <mach/imx-nand.h>
@@ -34,8 +34,7 @@ static void __bare_init __naked insdram(void)
uint32_t r;
/* setup a stack to be able to call imx_nand_load_image() */
- r = STACK_BASE + STACK_SIZE - 12;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
@@ -46,8 +45,8 @@ static void __bare_init __naked insdram(void)
static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,
uint32_t esdcfg)
{
- uint32_t esdctlreg = ESDCTL0;
- uint32_t esdcfgreg = ESDCFG0;
+ uint32_t esdctlreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0;
+ uint32_t esdcfgreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0;
if (base == 0x90000000) {
esdctlreg += 8;
@@ -122,12 +121,12 @@ void __bare_init __naked reset(void)
writel(0x1, 0xb8003000);
/* configure ARM clk */
- writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL);
+ writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
/* enable all the clocks */
- writel(0x1fffffff, MX25_CCM_BASE_ADDR + CCM_CGCR0);
- writel(0xffffffff, MX25_CCM_BASE_ADDR + CCM_CGCR1);
- writel(0x000fdfff, MX25_CCM_BASE_ADDR + CCM_CGCR2);
+ writel(0x1fffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0);
+ writel(0xffffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1);
+ writel(0x000fdfff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -137,9 +136,9 @@ void __bare_init __naked reset(void)
/* set to 3.3v SDRAM */
writel(0x800, MX25_IOMUXC_BASE_ADDR + 0x454);
- writel(ESDMISC_RST, ESDMISC);
+ writel(ESDMISC_RST, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
- while (!(readl(ESDMISC) & (1 << 31)));
+ while (!(readl(MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC) & (1 << 31)));
#define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \
ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL)
diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c
index 961787669b..766e77b247 100644
--- a/arch/arm/boards/karo-tx28/tx28-stk5.c
+++ b/arch/arm/boards/karo-tx28/tx28-stk5.c
@@ -393,7 +393,7 @@ void base_board_init(void)
tx28_get_ethaddr();
imx_enable_enetclk();
- add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0x4000,
+ add_generic_device("imx28-fec", 0, NULL, IMX_FEC0_BASE, 0x4000,
IORESOURCE_MEM, &fec_info);
ret = register_persistent_environment();
diff --git a/arch/arm/boards/karo-tx51/tx51.c b/arch/arm/boards/karo-tx51/tx51.c
index 3ee0ebd66e..dd377c140a 100644
--- a/arch/arm/boards/karo-tx51/tx51.c
+++ b/arch/arm/boards/karo-tx51/tx51.c
@@ -18,7 +18,7 @@
#include <common.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/karo-tx53/Makefile b/arch/arm/boards/karo-tx53/Makefile
index b56ce7f50d..2f45976184 100644
--- a/arch/arm/boards/karo-tx53/Makefile
+++ b/arch/arm/boards/karo-tx53/Makefile
@@ -1,2 +1,5 @@
obj-y += board.o
obj-y += flash_header.o
+pbl-y += flash_header.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c
index c8509bebcb..8f87c9c9a8 100644
--- a/arch/arm/boards/karo-tx53/board.c
+++ b/arch/arm/boards/karo-tx53/board.c
@@ -25,7 +25,7 @@
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
@@ -33,6 +33,8 @@
#include <mach/imx-nand.h>
#include <mach/iim.h>
#include <mach/imx5.h>
+#include <mach/imx-flash-header.h>
+#include <mach/bbu.h>
#include <asm/armlinux.h>
#include <io.h>
@@ -99,7 +101,10 @@ static iomux_v3_cfg_t tx53_pads[] = {
static int tx53_mem_init(void)
{
- arm_add_mem_device("ram0", 0x70000000, SZ_1G);
+ if (IS_ENABLED(CONFIG_TX53_REV_1011))
+ arm_add_mem_device("ram0", 0x70000000, SZ_1G);
+ else
+ arm_add_mem_device("ram0", 0x70000000, SZ_512M);
return 0;
}
@@ -203,6 +208,14 @@ static inline void tx53_fec_init(void)
ARRAY_SIZE(tx53_fec_pads));
}
+#define DCD_NAME_1011 static struct imx_dcd_v2_entry dcd_entry_1011
+
+#include "dcd-data-1011.h"
+
+#define DCD_NAME_XX30 static u32 dcd_entry_xx30
+
+#include "dcd-data-xx30.h"
+
static int tx53_devices_init(void)
{
imx53_iim_register_fec_ethaddr();
@@ -214,6 +227,14 @@ static int tx53_devices_init(void)
armlinux_set_bootparams((void *)0x70000100);
armlinux_set_architecture(MACH_TYPE_TX53);
+ /* rev xx30 can boot from nand or USB */
+ imx53_bbu_internal_nand_register_handler("nand-xx30",
+ BBU_HANDLER_FLAG_DEFAULT, (void *)dcd_entry_xx30, sizeof(dcd_entry_xx30), SZ_512K);
+
+ /* rev 1011 can boot from MMC/SD, other bootsource currently unknown */
+ imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0",
+ 0, (void *)dcd_entry_1011, sizeof(dcd_entry_1011));
+
return 0;
}
@@ -221,8 +242,25 @@ device_initcall(tx53_devices_init);
static int tx53_part_init(void)
{
- devfs_add_partition("disk0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
- devfs_add_partition("disk0", SZ_512K, SZ_1M, DEVFS_PARTITION_FIXED, "env0");
+ const char *envdev;
+
+ switch (imx_bootsource()) {
+ case bootsource_mmc:
+ devfs_add_partition("disk0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("disk0", SZ_512K, SZ_1M, DEVFS_PARTITION_FIXED, "env0");
+ envdev = "MMC";
+ break;
+ case bootsource_nand:
+ default:
+ devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw");
+ dev_add_bb_dev("self_raw", "self0");
+ devfs_add_partition("nand0", 0x80000, 0x100000, DEVFS_PARTITION_FIXED, "env_raw");
+ dev_add_bb_dev("env_raw", "env0");
+ envdev = "NAND";
+ break;
+ }
+
+ printf("Using environment in %s\n", envdev);
return 0;
}
@@ -232,7 +270,8 @@ static int tx53_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
- imx53_init_lowlevel(1000);
+ if (!IS_ENABLED(CONFIG_TX53_REV_XX30))
+ imx53_init_lowlevel(1000);
imx53_add_uart0();
return 0;
diff --git a/arch/arm/boards/karo-tx53/dcd-data-1011.h b/arch/arm/boards/karo-tx53/dcd-data-1011.h
new file mode 100644
index 0000000000..7034ff80de
--- /dev/null
+++ b/arch/arm/boards/karo-tx53/dcd-data-1011.h
@@ -0,0 +1,94 @@
+DCD_NAME_1011[] = {
+ { .addr = cpu_to_be32(0x53fd406c), .val = cpu_to_be32(0xffffffff), },
+ { .addr = cpu_to_be32(0x53fd4070), .val = cpu_to_be32(0xffffffff), },
+ { .addr = cpu_to_be32(0x53fd4074), .val = cpu_to_be32(0xffffffff), },
+ { .addr = cpu_to_be32(0x53fd4078), .val = cpu_to_be32(0xffffffff), },
+ { .addr = cpu_to_be32(0x53fd407c), .val = cpu_to_be32(0xffffffff), },
+ { .addr = cpu_to_be32(0x53fd4080), .val = cpu_to_be32(0xffffffff), },
+ { .addr = cpu_to_be32(0x53fd4088), .val = cpu_to_be32(0xffffffff), },
+ { .addr = cpu_to_be32(0x53fa8174), .val = cpu_to_be32(0x00000011), },
+ { .addr = cpu_to_be32(0x63fd800c), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00200040), },
+ { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00200040), },
+ { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00200040), },
+ { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00200040), },
+ { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00200040), },
+ { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00200040), },
+ { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00200000), },
+ { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00280000), },
+ { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00280000), },
+ { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00280000), },
+ { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00280000), },
+ { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000200), },
+ { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x06000000), },
+ { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x36353b38), },
+ { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x49434942), },
+ { .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), },
+ { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01350138), },
+ { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x01380139), },
+ { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00001710), },
+ { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x84110000), },
+ { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x4d5122d2), },
+ { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb6f18a22), },
+ { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x00c700db), },
+ { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
+ { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f000e), },
+ { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12272000), },
+ { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x00030012), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008010), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0a528030), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x03868031), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00068031), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
+ { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
+ { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00033332), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00448031), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008018), },
+ { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
+ { .addr = cpu_to_be32(0x53fa8004), .val = cpu_to_be32(0x00194005), },
+ { .addr = cpu_to_be32(0x53fa819c), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa81a0), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa81a4), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa81a8), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa81ac), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa81b0), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa81b4), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa81b8), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa81dc), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa81e0), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa8228), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa822c), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa8230), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa8234), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa8238), .val = cpu_to_be32(0x00000000), },
+ { .addr = cpu_to_be32(0x53fa84ec), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa84f0), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa84f4), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa84f8), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa84fc), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa8500), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa8504), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa8508), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa852c), .val = cpu_to_be32(0x00000004), },
+ { .addr = cpu_to_be32(0x53fa8530), .val = cpu_to_be32(0x00000004), },
+ { .addr = cpu_to_be32(0x53fa85a0), .val = cpu_to_be32(0x00000004), },
+ { .addr = cpu_to_be32(0x53fa85a4), .val = cpu_to_be32(0x00000004), },
+ { .addr = cpu_to_be32(0x53fa85a8), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa85ac), .val = cpu_to_be32(0x000000e4), },
+ { .addr = cpu_to_be32(0x53fa85b0), .val = cpu_to_be32(0x00000004), },
+};
diff --git a/arch/arm/boards/karo-tx53/dcd-data-xx30.h b/arch/arm/boards/karo-tx53/dcd-data-xx30.h
new file mode 100644
index 0000000000..cb982dc2e3
--- /dev/null
+++ b/arch/arm/boards/karo-tx53/dcd-data-xx30.h
@@ -0,0 +1,144 @@
+
+#define DCD_ITEM(adr, val) cpu_to_be32(adr), cpu_to_be32(val)
+#define DCD_WR_CMD(len) cpu_to_be32(0xcc << 24 | (len) << 8 | 0x04)
+#define DCD_CHECK_CMD(a, b, c) cpu_to_be32(a), cpu_to_be32(b), cpu_to_be32(c)
+
+/*
+ * This board uses advanced features of the DCD which do not corporate
+ * well with our flash header defines. The DCD consists of commands which
+ * have the length econded into them. Normally the DCDs only have a single
+ * command (DCD_COMMAND_WRITE_TAG) which is already part of struct
+ * imx_flash_header_v2. Now this board uses multiple commands, so we cannot
+ * calculate the command length using sizeof(dcd_entry).
+ */
+
+DCD_NAME_XX30[] = {
+ DCD_ITEM(0x53fd4068, 0xffcc0fff),
+ DCD_ITEM(0x53fd406c, 0x000fffc3),
+ DCD_ITEM(0x53fd4070, 0x033c0000),
+ DCD_ITEM(0x53fd4074, 0x00000000),
+ DCD_ITEM(0x53fd4078, 0x00000000),
+ DCD_ITEM(0x53fd407c, 0x00fff033),
+ DCD_ITEM(0x53fd4080, 0x0f00030f),
+ DCD_ITEM(0x53fd4084, 0xfff00000),
+ DCD_ITEM(0x53fd4088, 0x00000000),
+ DCD_ITEM(0x53fa8174, 0x00000011),
+ DCD_ITEM(0x53fa8318, 0x00000011),
+ DCD_ITEM(0x63fd800c, 0x00000000),
+ DCD_ITEM(0x53fd4014, 0x00888944),
+ DCD_ITEM(0x53fd4018, 0x00016154),
+ DCD_ITEM(0x53fa8724, 0x04000000),
+ DCD_ITEM(0x53fa86f4, 0x00000000),
+ DCD_ITEM(0x53fa8714, 0x00000000),
+ DCD_ITEM(0x53fa86fc, 0x00000080),
+ DCD_ITEM(0x53fa8710, 0x00000000),
+ DCD_ITEM(0x53fa8708, 0x00000040),
+ DCD_ITEM(0x53fa8584, 0x00280000),
+ DCD_ITEM(0x53fa8594, 0x00280000),
+ DCD_ITEM(0x53fa8560, 0x00280000),
+ DCD_ITEM(0x53fa8554, 0x00280000),
+ DCD_ITEM(0x53fa857c, 0x00a80040),
+ DCD_ITEM(0x53fa8590, 0x00a80040),
+ DCD_ITEM(0x53fa8568, 0x00a80040),
+ DCD_ITEM(0x53fa8558, 0x00a80040),
+ DCD_ITEM(0x53fa8580, 0x00280040),
+ DCD_ITEM(0x53fa8578, 0x00280000),
+ DCD_ITEM(0x53fa8564, 0x00280040),
+ DCD_ITEM(0x53fa8570, 0x00280000),
+ DCD_ITEM(0x53fa858c, 0x000000c0),
+ DCD_ITEM(0x53fa855c, 0x000000c0),
+ DCD_ITEM(0x53fa8574, 0x00280000),
+ DCD_ITEM(0x53fa8588, 0x00280000),
+ DCD_ITEM(0x53fa86f0, 0x00280000),
+ DCD_ITEM(0x53fa8720, 0x00280000),
+ DCD_ITEM(0x53fa8718, 0x00280000),
+ DCD_ITEM(0x53fa871c, 0x00280000),
+ DCD_ITEM(0x53fa8728, 0x00280000),
+ DCD_ITEM(0x53fa872c, 0x00280000),
+ DCD_ITEM(0x63fd904c, 0x001f001f),
+ DCD_ITEM(0x63fd9050, 0x001f001f),
+ DCD_ITEM(0x63fd907c, 0x011e011e),
+ DCD_ITEM(0x63fd9080, 0x011f0120),
+ DCD_ITEM(0x63fd9088, 0x3a393d3b),
+ DCD_ITEM(0x63fd9090, 0x3f3f3f3f),
+ DCD_ITEM(0x63fd9018, 0x00011740),
+ DCD_ITEM(0x63fd9000, 0x83190000),
+ DCD_ITEM(0x63fd900c, 0x3f435316),
+ DCD_ITEM(0x63fd9010, 0xb66e0a63),
+ DCD_ITEM(0x63fd9014, 0x01ff00db),
+ DCD_ITEM(0x63fd902c, 0x000026d2),
+ DCD_ITEM(0x63fd9030, 0x00430f24),
+ DCD_ITEM(0x63fd9008, 0x1b221010),
+ DCD_ITEM(0x63fd9004, 0x00030012),
+ DCD_ITEM(0x63fd901c, 0x00008032),
+ DCD_ITEM(0x63fd901c, 0x00008033),
+ DCD_ITEM(0x63fd901c, 0x00408031),
+ DCD_ITEM(0x63fd901c, 0x055080b0),
+ DCD_ITEM(0x63fd9020, 0x00005800),
+ DCD_ITEM(0x63fd9058, 0x00011112),
+ DCD_ITEM(0x63fd90d0, 0x00000003),
+ DCD_ITEM(0x63fd901c, 0x04008010),
+ DCD_ITEM(0x63fd901c, 0x00008040),
+ DCD_ITEM(0x63fd9040, 0x0539002b),
+ DCD_CHECK_CMD(0xcf000c04, 0x63fd9040, 0x00010000),
+ DCD_WR_CMD(0x24),
+ DCD_ITEM(0x63fd901c, 0x00048033),
+ DCD_ITEM(0x63fd901c, 0x00848231),
+ DCD_ITEM(0x63fd901c, 0x00000000),
+ DCD_ITEM(0x63fd9048, 0x00000001),
+ DCD_CHECK_CMD(0xcf000c04, 0x63fd9048, 0x00000001),
+ DCD_WR_CMD(0x2c),
+ DCD_ITEM(0x63fd901c, 0x00048031),
+ DCD_ITEM(0x63fd901c, 0x00008033),
+ DCD_ITEM(0x63fd901c, 0x04008010),
+ DCD_ITEM(0x63fd901c, 0x00048033),
+ DCD_ITEM(0x63fd907c, 0x90000000),
+ DCD_CHECK_CMD(0xcf000c04, 0x63fd907c, 0x90000000),
+ DCD_WR_CMD(0x2c),
+ DCD_ITEM(0x63fd901c, 0x00008033),
+ DCD_ITEM(0x63fd901c, 0x00000000),
+ DCD_ITEM(0x63fd901c, 0x04008010),
+ DCD_ITEM(0x63fd901c, 0x00048033),
+ DCD_ITEM(0x63fd90a4, 0x00000010),
+ DCD_CHECK_CMD(0xcf000c04, 0x63fd90a4, 0x00000010),
+ DCD_WR_CMD(0x24),
+ DCD_ITEM(0x63fd901c, 0x00008033),
+ DCD_ITEM(0x63fd901c, 0x04008010),
+ DCD_ITEM(0x63fd901c, 0x00048033),
+ DCD_ITEM(0x63fd90a0, 0x00000010),
+ DCD_CHECK_CMD(0xcf000c04, 0x63fd90a0, 0x00000010),
+ DCD_WR_CMD(0x010c),
+ DCD_ITEM(0x63fd901c, 0x00008033),
+ DCD_ITEM(0x63fd901c, 0x00000000),
+ DCD_ITEM(0x53fa8004, 0x00194005),
+ DCD_ITEM(0x53fa819c, 0x00000000),
+ DCD_ITEM(0x53fa81a0, 0x00000000),
+ DCD_ITEM(0x53fa81a4, 0x00000000),
+ DCD_ITEM(0x53fa81a8, 0x00000000),
+ DCD_ITEM(0x53fa81ac, 0x00000000),
+ DCD_ITEM(0x53fa81b0, 0x00000000),
+ DCD_ITEM(0x53fa81b4, 0x00000000),
+ DCD_ITEM(0x53fa81b8, 0x00000000),
+ DCD_ITEM(0x53fa81dc, 0x00000000),
+ DCD_ITEM(0x53fa81e0, 0x00000000),
+ DCD_ITEM(0x53fa8228, 0x00000000),
+ DCD_ITEM(0x53fa822c, 0x00000000),
+ DCD_ITEM(0x53fa8230, 0x00000000),
+ DCD_ITEM(0x53fa8234, 0x00000000),
+ DCD_ITEM(0x53fa8238, 0x00000000),
+ DCD_ITEM(0x53fa84ec, 0x000000e4),
+ DCD_ITEM(0x53fa84f0, 0x000000e4),
+ DCD_ITEM(0x53fa84f4, 0x000000e4),
+ DCD_ITEM(0x53fa84f8, 0x000000e4),
+ DCD_ITEM(0x53fa84fc, 0x000000e4),
+ DCD_ITEM(0x53fa8500, 0x000000e4),
+ DCD_ITEM(0x53fa8504, 0x000000e4),
+ DCD_ITEM(0x53fa8508, 0x000000e4),
+ DCD_ITEM(0x53fa852c, 0x00000004),
+ DCD_ITEM(0x53fa8530, 0x00000004),
+ DCD_ITEM(0x53fa85a0, 0x00000004),
+ DCD_ITEM(0x53fa85a4, 0x00000004),
+ DCD_ITEM(0x53fa85a8, 0x000000e4),
+ DCD_ITEM(0x53fa85ac, 0x000000e4),
+ DCD_ITEM(0x53fa85b0, 0x00000004),
+};
diff --git a/arch/arm/boards/karo-tx53/env/init/bootargs-base b/arch/arm/boards/karo-tx53/env/init/bootargs-base
deleted file mode 100644
index d86975406e..0000000000
--- a/arch/arm/boards/karo-tx53/env/init/bootargs-base
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Base bootargs"
- exit
-fi
-
-global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/karo-tx53/env/init/config-board b/arch/arm/boards/karo-tx53/env/init/config-board
new file mode 100644
index 0000000000..3ebfac6c9b
--- /dev/null
+++ b/arch/arm/boards/karo-tx53/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=tx53
+global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/karo-tx53/env/init/hostname b/arch/arm/boards/karo-tx53/env/init/hostname
deleted file mode 100644
index 2de91305e5..0000000000
--- a/arch/arm/boards/karo-tx53/env/init/hostname
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "hostname"
- exit
-fi
-
-global.hostname=tx53
diff --git a/arch/arm/boards/karo-tx53/flash_header.c b/arch/arm/boards/karo-tx53/flash_header.c
index 9b97fab2df..5c6aa53e47 100644
--- a/arch/arm/boards/karo-tx53/flash_header.c
+++ b/arch/arm/boards/karo-tx53/flash_header.c
@@ -20,109 +20,31 @@
void __naked __flash_header_start go(void)
{
- barebox_arm_head();
+ barebox_arm_imx_fcb_head();
}
/*
* FIXME: These are the dcd values for a Ka-Ro TX53 1011 which
* is not in production. It has 1GB DDR2 memory.
*/
-struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
- { .addr = cpu_to_be32(0x53fd406c), .val = cpu_to_be32(0xffffffff), },
- { .addr = cpu_to_be32(0x53fd4070), .val = cpu_to_be32(0xffffffff), },
- { .addr = cpu_to_be32(0x53fd4074), .val = cpu_to_be32(0xffffffff), },
- { .addr = cpu_to_be32(0x53fd4078), .val = cpu_to_be32(0xffffffff), },
- { .addr = cpu_to_be32(0x53fd407c), .val = cpu_to_be32(0xffffffff), },
- { .addr = cpu_to_be32(0x53fd4080), .val = cpu_to_be32(0xffffffff), },
- { .addr = cpu_to_be32(0x53fd4088), .val = cpu_to_be32(0xffffffff), },
- { .addr = cpu_to_be32(0x53fa8174), .val = cpu_to_be32(0x00000011), },
- { .addr = cpu_to_be32(0x63fd800c), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00200040), },
- { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00200040), },
- { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00200040), },
- { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00200040), },
- { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00200040), },
- { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00200040), },
- { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00200000), },
- { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00280000), },
- { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00280000), },
- { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00280000), },
- { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00280000), },
- { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000200), },
- { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x06000000), },
- { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x36353b38), },
- { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x49434942), },
- { .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), },
- { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01350138), },
- { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x01380139), },
- { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00001710), },
- { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x84110000), },
- { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x4d5122d2), },
- { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb6f18a22), },
- { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x00c700db), },
- { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
- { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f000e), },
- { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12272000), },
- { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x00030012), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008010), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0a528030), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x03868031), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00068031), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
- { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
- { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00033332), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00448031), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008018), },
- { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
- { .addr = cpu_to_be32(0x53fa8004), .val = cpu_to_be32(0x00194005), },
- { .addr = cpu_to_be32(0x53fa819c), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa81a0), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa81a4), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa81a8), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa81ac), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa81b0), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa81b4), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa81b8), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa81dc), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa81e0), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa8228), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa822c), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa8230), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa8234), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa8238), .val = cpu_to_be32(0x00000000), },
- { .addr = cpu_to_be32(0x53fa84ec), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa84f0), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa84f4), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa84f8), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa84fc), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa8500), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa8504), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa8508), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa852c), .val = cpu_to_be32(0x00000004), },
- { .addr = cpu_to_be32(0x53fa8530), .val = cpu_to_be32(0x00000004), },
- { .addr = cpu_to_be32(0x53fa85a0), .val = cpu_to_be32(0x00000004), },
- { .addr = cpu_to_be32(0x53fa85a4), .val = cpu_to_be32(0x00000004), },
- { .addr = cpu_to_be32(0x53fa85a8), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa85ac), .val = cpu_to_be32(0x000000e4), },
- { .addr = cpu_to_be32(0x53fa85b0), .val = cpu_to_be32(0x00000004), },
-};
+#ifdef CONFIG_TX53_REV_1011
+
+#define DCD_NAME_1011 struct imx_dcd_v2_entry __dcd_entry_section dcd_entry
+
+#include "dcd-data-1011.h"
+
+#elif defined(CONFIG_TX53_REV_XX30)
+
+#define DCD_NAME_XX30 u32 __dcd_entry_section dcd_entry
+
+#include "dcd-data-xx30.h"
+
+#endif
+
+#define APP_DEST 0x71000000
-#define APP_DEST 0x70000000
+int tx53_dcdentry_size = sizeof(dcd_entry);
+void *tx53_dcd_entry = &dcd_entry;
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
@@ -142,6 +64,10 @@ struct imx_flash_header_v2 __flash_header_section flash_header = {
.dcd.header.version = DCD_VERSION,
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
+#ifdef CONFIG_TX53_REV_1011
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
+#elif defined(CONFIG_TX53_REV_XX30)
+ .dcd.command.length = cpu_to_be16(0x21c),
+#endif
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
};
diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c
new file mode 100644
index 0000000000..0ca164bda5
--- /dev/null
+++ b/arch/arm/boards/karo-tx53/lowlevel.c
@@ -0,0 +1,22 @@
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/imx5.h>
+
+#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT
+
+void __naked reset(void)
+{
+ common_reset();
+
+ /*
+ * For the TX53 rev 8030 the SDRAM setup is not stable without
+ * the proper PLL setup. It will crash once we enable the MMU,
+ * so do the PLL setup here.
+ */
+ if (IS_ENABLED(CONFIG_TX53_REV_XX30))
+ imx53_init_lowlevel(800);
+
+ board_init_lowlevel_return();
+}
+#endif
diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
index 33d06be29a..36e2bc5886 100644
--- a/arch/arm/boards/panda/lowlevel.c
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -76,16 +76,12 @@ static void noinline panda_init_lowlevel(void)
void reset(void)
{
- u32 r;
-
common_reset();
if (get_pc() > 0x80000000)
board_init_lowlevel_return();
- r = 0x4030d000;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(0x4030d000);
panda_init_lowlevel();
}
-
diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S
index a6747c2482..f9ecce1141 100644
--- a/arch/arm/boards/pcm037/lowlevel_init.S
+++ b/arch/arm/boards/pcm037/lowlevel_init.S
@@ -17,9 +17,10 @@
*
*/
-#include <mach/imx-regs.h>
+#include <mach/imx31-regs.h>
#include <mach/imx-pll.h>
#include <asm/barebox-arm-head.h>
+#include <mach/esdctl.h>
#define writel(val, reg) \
ldr r0, =reg; \
@@ -46,24 +47,30 @@ reset:
common_reset r0
- writel(0x074B0BF5, MX31_CCM_BASE_ADDR + CCM_CCMR)
+ writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR)
DELAY 0x40000
- writel(0x074B0BF5 | CCMR_MPE, MX31_CCM_BASE_ADDR + CCM_CCMR)
- writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, MX31_CCM_BASE_ADDR + CCM_CCMR)
-
- writel(PDR0_CSI_PODF(0xff1) | \
- PDR0_PER_PODF(7) | \
- PDR0_HSP_PODF(3) | \
- PDR0_NFC_PODF(5) | \
- PDR0_IPG_PODF(1) | \
- PDR0_MAX_PODF(3) | \
- PDR0_MCU_PODF(0), \
- MX31_CCM_BASE_ADDR + CCM_PDR0)
-
- writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), MX31_CCM_BASE_ADDR + CCM_MPCTL)
- writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + CCM_SPCTL)
+ writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
+ MX31_CCM_CCMR)
+ writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
+ MX31_CCM_BASE_ADDR + MX31_CCM_CCMR)
+
+ writel(MX31_PDR0_CSI_PODF(0xff1) | \
+ MX31_PDR0_PER_PODF(7) | \
+ MX31_PDR0_HSP_PODF(3) | \
+ MX31_PDR0_NFC_PODF(5) | \
+ MX31_PDR0_IPG_PODF(1) | \
+ MX31_PDR0_MAX_PODF(3) | \
+ MX31_PDR0_MCU_PODF(0), \
+ MX31_CCM_BASE_ADDR + MX31_CCM_PDR0)
+
+ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) |
+ IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd),
+ MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL)
+ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
+ IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
+ MX31_CCM_SPCTL)
/* Configure IOMUXC
* Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
@@ -96,19 +103,19 @@ clear_iomux:
#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
#define ROWS0 ESDCTL0_ROW14
#endif
- writel(0x00000004, ESDMISC)
- writel(0x006ac73a, ESDCFG0)
- writel(0x90100000 | ROWS0, ESDCTL0)
+ writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
+ writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
+ writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00)
- writel(0xa0100000 | ROWS0, ESDCTL0)
+ writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0x12344321, MX31_CSD0_BASE_ADDR)
writel(0x12344321, MX31_CSD0_BASE_ADDR)
- writel(0xb0100000 | ROWS0, ESDCTL0)
+ writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33)
writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000)
- writel(0x80226080 | ROWS0, ESDCTL0)
+ writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR)
- writel(0x0000000c, ESDMISC)
+ writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
@@ -116,18 +123,18 @@ clear_iomux:
#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
#define ROWS1 ESDCTL0_ROW14
#endif
- writel(0x006ac73a, ESDCFG1)
- writel(0x90100000 | ROWS1, ESDCTL1)
+ writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1)
+ writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00)
- writel(0xa0100000 | ROWS1, ESDCTL1)
+ writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
writel(0x12344321, MX31_CSD1_BASE_ADDR)
writel(0x12344321, MX31_CSD1_BASE_ADDR)
- writel(0xb0100000 | ROWS1, ESDCTL1)
+ writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33)
writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000)
- writel(0x80226080 | ROWS1, ESDCTL1)
+ writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR)
- writel(0x0000000c, ESDMISC)
+ writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
#endif
#ifdef CONFIG_NAND_IMX_BOOT
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index 1a1688d053..ff4089ad25 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -24,7 +24,7 @@
#include <fs.h>
#include <environment.h>
#include <usb/ulpi.h>
-#include <mach/imx-regs.h>
+#include <mach/imx31-regs.h>
#include <mach/iomux-mx31.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
@@ -96,7 +96,7 @@ static void pcm037_usb_init(void)
/* Host 2 */
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x8);
tmp |= 1 << 11;
- writel(tmp, IOMUXC_BASE + 0x8);
+ writel(tmp, MX31_IOMUXC_BASE_ADDR + 0x8);
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));
diff --git a/arch/arm/boards/pcm038/env/boot/nand-ubi b/arch/arm/boards/pcm038/env/boot/nand-ubi
index a3f748e746..67b0cb4afe 100644
--- a/arch/arm/boards/pcm038/env/boot/nand-ubi
+++ b/arch/arm/boards/pcm038/env/boot/nand-ubi
@@ -7,4 +7,4 @@ fi
global.bootm.image="/dev/nand0.kernel.bb"
#global.bootm.oftree="/env/oftree"
-bootargs-root-ubi -r root -m nand0.root
+global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs"
diff --git a/arch/arm/boards/pcm038/env/init/bootargs-base b/arch/arm/boards/pcm038/env/init/bootargs-base
deleted file mode 100644
index d86975406e..0000000000
--- a/arch/arm/boards/pcm038/env/init/bootargs-base
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Base bootargs"
- exit
-fi
-
-global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/pcm038/env/init/config-board b/arch/arm/boards/pcm038/env/init/config-board
new file mode 100644
index 0000000000..93fd41bcf1
--- /dev/null
+++ b/arch/arm/boards/pcm038/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=pcm038
+global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c
index 7ecff3afa8..2f93c3127a 100644
--- a/arch/arm/boards/pcm038/lowlevel.c
+++ b/arch/arm/boards/pcm038/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <io.h>
@@ -34,13 +34,8 @@
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
- uint32_t r;
-
- PCCR1 |= PCCR1_NFC_BAUDEN;
-
/* setup a stack to be able to call imx_nand_load_image() */
- r = STACK_BASE + STACK_SIZE - 12;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
@@ -60,10 +55,10 @@ void __bare_init __naked reset(void)
common_reset();
/* ahb lite ip interface */
- AIPI1_PSR0 = 0x20040304;
- AIPI1_PSR1 = 0xDFFBFCFB;
- AIPI2_PSR0 = 0x00000000;
- AIPI2_PSR1 = 0xFFFFFFFF;
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -71,37 +66,46 @@ void __bare_init __naked reset(void)
board_init_lowlevel_return();
/* re-program the PLL prior(!) starting the SDRAM controller */
- MPCTL0 = MPCTL0_VAL;
- SPCTL0 = SPCTL0_VAL;
- CSCR = CSCR_VAL | CSCR_UPDATE_DIS | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
+ writel(MPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_MPCTL0);
+ writel(SPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_SPCTL0);
+ writel(CSCR_VAL | MX27_CSCR_UPDATE_DIS | MX27_CSCR_MPLL_RESTART |
+ MX27_CSCR_SPLL_RESTART, MX27_CCM_BASE_ADDR + MX27_CSCR);
/*
* DDR on CSD0
*/
- writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */
-
- DSCR(3) = 0x55555555; /* Set the driving strength */
- DSCR(5) = 0x55555555;
- DSCR(6) = 0x55555555;
- DSCR(7) = 0x00005005;
- DSCR(8) = 0x15555555;
-
- writel(0x00000004, ESDMISC); /* Initial reset */
- writel(0x006ac73a, ESDCFG0);
-
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */
+ /* Enable DDR SDRAM operation */
+ writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+
+ /* Set the driving strength */
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
+ writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
+ writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
+
+ /* Initial reset */
+ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+
+ /* precharge CSD0 all banks */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0);
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
for (i = 0; i < 8; i++)
writel(0, 0xa0000f00);
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0);
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, 0xa0000033);
writeb(0xff, 0xa1000000);
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
- ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0);
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index 58b1ec9ef4..715d604726 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -18,7 +18,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <fec.h>
#include <notifier.h>
#include <mach/gpio.h>
@@ -39,6 +39,7 @@
#include <mach/devices-imx27.h>
#include <mach/iim.h>
#include <mfd/mc13xxx.h>
+#include <mach/generic.h>
#include "pll.h"
@@ -111,8 +112,8 @@ static inline uint32_t get_pll_spctl10(void)
{
uint32_t reg;
- reg = SPCTL0;
- SPCTL0 = reg;
+ reg = readl(MX27_CCM_BASE_ADDR + MX27_SPCTL0);
+ writel(reg, MX27_CCM_BASE_ADDR + MX27_SPCTL0);
return reg;
}
@@ -126,7 +127,8 @@ static int pcm038_power_init(void)
struct mc13xxx *mc13xxx = mc13xxx_get();
/* PLL registers already set to their final values? */
- if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) {
+ if (spctl0 == SPCTL0_VAL &&
+ readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) {
console_flush();
if (mc13xxx) {
mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0),
@@ -161,9 +163,9 @@ static int pcm038_power_init(void)
/* wait for required power level to run the CPU at 400 MHz */
udelay(100000);
- CSCR = CSCR_VAL_FINAL;
- PCDR0 = 0x130410c3;
- PCDR1 = 0x09030911;
+ writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR);
+ writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0);
+ writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1);
/* Clocks have changed. Notify clients */
clock_notifier_call_chain();
@@ -173,7 +175,7 @@ static int pcm038_power_init(void)
}
/* clock gating enable */
- GPCR = 0x00050f08;
+ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR);
return 0;
}
@@ -281,9 +283,6 @@ static int pcm038_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
- PCCR0 |= PCCR0_CSPI1_EN;
- PCCR1 |= PCCR1_PERCLK2_EN;
-
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_spi0(&pcm038_spi_0_data);
@@ -293,7 +292,6 @@ static int pcm038_devices_init(void)
imx27_add_nand(&nand_info);
imx27_add_fb(&pcm038_fb_data);
- PCCR0 |= PCCR0_I2C1_EN | PCCR0_I2C2_EN;
imx27_add_i2c0(NULL);
imx27_add_i2c1(NULL);
@@ -302,11 +300,8 @@ static int pcm038_devices_init(void)
*/
imx27_add_fec(&fec_info);
- switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
- case GPCR_BOOT_8BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_512:
- case GPCR_BOOT_8BIT_NAND_512:
+ switch (imx_bootsource()) {
+ case bootsource_nand:
devfs_add_partition("nand0", 0x00000, 0x80000,
DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c
index a6b6c83efa..93a183988a 100644
--- a/arch/arm/boards/pcm038/pcm970.c
+++ b/arch/arm/boards/pcm038/pcm970.c
@@ -16,7 +16,7 @@
#include <init.h>
#include <sizes.h>
#include <platform_ide.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/iomux-mx27.h>
#include <mach/weim.h>
#include <mach/gpio.h>
@@ -112,35 +112,38 @@ static void pcm970_ide_init(void)
mdelay(10);
/* Reset PCMCIA Status Change Register */
- writel(0x00000fff, PCMCIA_PSCR);
+ writel(0x00000fff, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PSCR);
mdelay(10);
/* Check PCMCIA Input Pins Register for Card Detect & Power */
- if ((readl(PCMCIA_PIPR) & ((1 << 8) | (3 << 3))) != (1 << 8)) {
+ if ((readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PIPR) &
+ ((1 << 8) | (3 << 3))) != (1 << 8)) {
printf("CompactFlash card not found. Driver not enabled.\n");
return;
}
/* Disable all interrupts */
- writel(0, PCMCIA_PER);
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PER);
/* Disable all PCMCIA banks */
for (i = 0; i < 5; i++)
- writel(0, PCMCIA_POR(i));
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(i));
/* Not use internal PCOE */
- writel(0, PCMCIA_PGCR);
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGCR);
/* Setup PCMCIA bank0 for Common memory mode */
- writel(0, PCMCIA_PBR(0));
- writel(0, PCMCIA_POFR(0));
- writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, PCMCIA_POR(0));
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PBR(0));
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POFR(0));
+ writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf,
+ MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0));
/* Clear PCMCIA General Status Register */
- writel(0x0000001f, PCMCIA_PGSR);
+ writel(0x0000001f, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGSR);
/* Make PCMCIA bank0 valid */
- writel(readl(PCMCIA_POR(0)) | (1 << 29), PCMCIA_POR(0));
+ writel(readl(MX27_PCMCIA_POR(0)) | (1 << 29),
+ MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0));
platform_device_register(&pcm970_ide_device);
}
@@ -162,7 +165,6 @@ static void pcm970_mmc_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
- PCCR0 |= PCCR0_SDHC2_EN;
imx27_add_mmc1(NULL);
}
diff --git a/arch/arm/boards/pcm038/pll.h b/arch/arm/boards/pcm038/pll.h
index a7da4a44e3..8bdb76d111 100644
--- a/arch/arm/boards/pcm038/pll.h
+++ b/arch/arm/boards/pcm038/pll.h
@@ -22,35 +22,35 @@
/* define the PLL setting we want to run the system */
/* main clock divider settings immediately after reset (at 1.25 V core supply) */
-#define CSCR_VAL (CSCR_USB_DIV(3) | \
- CSCR_SD_CNT(3) | \
- CSCR_MSHC_SEL | \
- CSCR_H264_SEL | \
- CSCR_SSI1_SEL | \
- CSCR_SSI2_SEL | \
- CSCR_SP_SEL | /* 26 MHz reference */ \
- CSCR_MCU_SEL | /* 26 MHz reference */ \
- CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \
- CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
- CSCR_FPM_EN | \
- CSCR_SPEN | \
- CSCR_MPEN)
+#define CSCR_VAL (MX27_CSCR_USB_DIV(3) | \
+ MX27_CSCR_SD_CNT(3) | \
+ MX27_CSCR_MSHC_SEL | \
+ MX27_CSCR_H264_SEL | \
+ MX27_CSCR_SSI1_SEL | \
+ MX27_CSCR_SSI2_SEL | \
+ MX27_CSCR_SP_SEL | /* 26 MHz reference */ \
+ MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \
+ MX27_CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \
+ MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
+ MX27_CSCR_FPM_EN | \
+ MX27_CSCR_SPEN | \
+ MX27_CSCR_MPEN)
/* main clock divider settings after core voltage increases to 1.45 V */
-#define CSCR_VAL_FINAL (CSCR_USB_DIV(3) | \
- CSCR_SD_CNT(3) | \
- CSCR_MSHC_SEL | \
- CSCR_H264_SEL | \
- CSCR_SSI1_SEL | \
- CSCR_SSI2_SEL | \
- CSCR_SP_SEL | /* 26 MHz reference */ \
- CSCR_MCU_SEL | /* 26 MHz reference */ \
- CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \
- CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \
- CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
- CSCR_FPM_EN | /* do not disable it! */ \
- CSCR_SPEN | \
- CSCR_MPEN)
+#define CSCR_VAL_FINAL (MX27_CSCR_USB_DIV(3) | \
+ MX27_CSCR_SD_CNT(3) | \
+ MX27_CSCR_MSHC_SEL | \
+ MX27_CSCR_H264_SEL | \
+ MX27_CSCR_SSI1_SEL | \
+ MX27_CSCR_SSI2_SEL | \
+ MX27_CSCR_SP_SEL | /* 26 MHz reference */ \
+ MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \
+ MX27_CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \
+ MX27_CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \
+ MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
+ MX27_CSCR_FPM_EN | /* do not disable it! */ \
+ MX27_CSCR_SPEN | \
+ MX27_CSCR_MPEN)
/* MPLL should provide a 399 MHz clock from the 26 MHz reference */
#define MPCTL0_VAL (IMX_PLL_PD(0) | \
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c
index 4516e9f017..06f05abef1 100644
--- a/arch/arm/boards/pcm043/lowlevel.c
+++ b/arch/arm/boards/pcm043/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
@@ -52,8 +52,7 @@ static void __bare_init __naked insdram(void)
writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
- r = STACK_BASE + STACK_SIZE - 12;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
imx_nand_load_image(_text, barebox_image_size);
@@ -66,6 +65,7 @@ void __bare_init __naked reset(void)
uint32_t r, s;
unsigned long ccm_base = MX35_CCM_BASE_ADDR;
unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR;
+ unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
@@ -110,28 +110,28 @@ void __bare_init __naked reset(void)
* End of ARM1136 init
*/
- writel(0x003F4208, ccm_base + CCM_CCMR);
+ writel(0x003F4208, ccm_base + MX35_CCM_CCMR);
/* Set MPLL , arm clock and ahb clock*/
- writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL);
- writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
+ writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL);
/* Check silicon revision and use 532MHz if >=2.1 */
r = readl(MX35_IIM_BASE_ADDR + 0x24);
if (r >= IMX35_CHIP_REVISION_2_1)
- writel(CCM_PDR0_532, ccm_base + CCM_PDR0);
+ writel(CCM_PDR0_532, ccm_base + MX35_CCM_PDR0);
else
- writel(CCM_PDR0_399, ccm_base + CCM_PDR0);
+ writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0);
- r = readl(ccm_base + CCM_CGR0);
+ r = readl(ccm_base + MX35_CCM_CGR0);
r |= 0x00300000;
- writel(r, ccm_base + CCM_CGR0);
+ writel(r, ccm_base + MX35_CCM_CGR0);
- r = readl(ccm_base + CCM_CGR1);
+ r = readl(ccm_base + MX35_CCM_CGR1);
r |= 0x00000C00;
r |= 0x00000003;
- writel(r, ccm_base + CCM_CGR1);
+ writel(r, ccm_base + MX35_CCM_CGR1);
r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
r |= 0x1000;
@@ -154,17 +154,17 @@ void __bare_init __naked reset(void)
writel(r, iomuxc_base + 0x7a4);
/* MDDR init, enable mDDR*/
- writel(0x00000304, ESDMISC); /* was 0x00000004 */
+ writel(0x00000304, esdctl_base + IMX_ESDMISC); /* was 0x00000004 */
/* set timing paramters */
- writel(0x0025541F, ESDCFG0);
+ writel(0x0025541F, esdctl_base + IMX_ESDCFG0);
/* select Precharge-All mode */
- writel(0x92220000, ESDCTL0);
+ writel(0x92220000, esdctl_base + IMX_ESDCTL0);
/* Precharge-All */
writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
/* select Load-Mode-Register mode */
- writel(0xB8001000, ESDCTL0);
+ writel(0xB8001000, esdctl_base + IMX_ESDCTL0);
/* Load reg EMR2 */
writeb(0xda, 0x84000000);
/* Load reg EMR3 */
@@ -175,18 +175,18 @@ void __bare_init __naked reset(void)
writeb(0xda, 0x80000333);
/* select Precharge-All mode */
- writel(0x92220000, ESDCTL0);
+ writel(0x92220000, esdctl_base + IMX_ESDCTL0);
/* Precharge-All */
writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
/* select Manual-Refresh mode */
- writel(0xA2220000, ESDCTL0);
+ writel(0xA2220000, esdctl_base + IMX_ESDCTL0);
/* Manual-Refresh 2 times */
writel(0x87654321, MX35_CSD0_BASE_ADDR);
writel(0x87654321, MX35_CSD0_BASE_ADDR);
/* select Load-Mode-Register mode */
- writel(0xB2220000, ESDCTL0);
+ writel(0xB2220000, esdctl_base + IMX_ESDCTL0);
/* Load reg MR -- CL3, BL8, end DLL reset */
writeb(0xda, 0x80000233);
/* Load reg EMR1 -- OCD default */
@@ -198,12 +198,12 @@ void __bare_init __naked reset(void)
* DSIZ32-bit, BL8, COL10-bit, ROW13-bit
* disable PWT & PRCT
* disable Auto-Refresh */
- writel(0x82220080, ESDCTL0);
+ writel(0x82220080, esdctl_base + IMX_ESDCTL0);
/* enable Auto-Refresh */
- writel(0x82228080, ESDCTL0);
+ writel(0x82228080, esdctl_base + IMX_ESDCTL0);
/* enable Auto-Refresh */
- writel(0x00002000, ESDCTL1);
+ writel(0x00002000, esdctl_base + IMX_ESDCTL1);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 09bc96af78..abfeaf148a 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -26,7 +26,7 @@
#include <environment.h>
#include <fs.h>
#include <sizes.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <asm/armlinux.h>
#include <mach/gpio.h>
#include <io.h>
@@ -127,7 +127,7 @@ static int imx35_devices_init(void)
led_gpio_register(&led0);
- reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
@@ -308,10 +308,10 @@ static int do_cpufreq(int argc, char *argv[])
switch (freq) {
case 399:
- writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
case 532:
- writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
index c3fc6c7e1f..b64244ca79 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -86,16 +86,12 @@ static void noinline pcm049_init_lowlevel(void)
void reset(void)
{
- u32 r;
-
common_reset();
if (get_pc() > 0x80000000)
board_init_lowlevel_return();
- r = 0x4030d000;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(0x4030d000);
pcm049_init_lowlevel();
}
-
diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
index 24b4ab8ea5..5d8693abdd 100644
--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
@@ -86,15 +86,12 @@ static noinline void pcaaxl2_init_lowlevel(void)
void reset(void)
{
- u32 r;
-
common_reset();
if (get_pc() > 0x80000000)
board_init_lowlevel_return();
- r = 0x4030d000;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(0x4030d000);
pcaaxl2_init_lowlevel();
}
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
index 3c36889e7a..8f0000f822 100644
--- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
+++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
@@ -5,7 +5,7 @@
*/
#include <config.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <asm/barebox-arm-head.h>
@@ -21,20 +21,26 @@
/*
* DDR on CSD0
*/
- writel(0x00000008, ESDMISC) /* Enable DDR SDRAM operation */
-
- writel(0x55555555, DSCR(3)) /* Set the driving strength */
- writel(0x55555555, DSCR(5))
- writel(0x55555555, DSCR(6))
- writel(0x00005005, DSCR(7))
- writel(0x15555555, DSCR(8))
-
- writel(0x00000004, ESDMISC) /* Initial reset */
- writel(0x006ac73a, ESDCFG0)
-
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */
+ /* Enable DDR SDRAM operation */
+ writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
+
+ /* Set the driving strength */
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3))
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5))
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6))
+ writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7))
+ writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8))
+
+ /* Initial reset */
+ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
+ writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
+
+ /* precharge CSD0 all banks */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xa0000f00
mov r1, #0
@@ -44,14 +50,17 @@
subs r2, #1
bne 1b
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xA0000033
mov r1, #0xda
strb r1, [r0]
ldr r0, =0xA1000000
mov r1, #0xff
strb r1, [r0]
- writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
.endm
.section ".text_bare_init","ax"
@@ -61,10 +70,10 @@ reset:
common_reset r0
/* ahb lite ip interface */
- writel(0x20040304, AIPI1_PSR0)
- writel(0xDFFBFCFB, AIPI1_PSR1)
- writel(0x00000000, AIPI2_PSR0)
- writel(0xFFFFFFFF, AIPI2_PSR1)
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
/* skip sdram initialization if we run from ram */
cmp pc, #0xa0000000
@@ -75,21 +84,26 @@ reset:
b board_init_lowlevel_return
1:
+ /* 399 MHz */
writel(IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
- IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */
+ IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0)
+ /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
writel(IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
- IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
-
- writel(CSCR_MPLL_RESTART | CSCR_SPLL_RESTART | CSCR_ARM_SRC_MPLL |
- CSCR_MCU_SEL | CSCR_SP_SEL | CSCR_FPM_EN | CSCR_MPEN |
- CSCR_SPEN | CSCR_ARM_DIV(0) | CSCR_AHB_DIV(1) | CSCR_USB_DIV(3) |
- CSCR_SD_CNT(3) | CSCR_SSI2_SEL | CSCR_SSI1_SEL | CSCR_H264_SEL |
- CSCR_MSHC_SEL, CSCR)
+ IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0)
+
+ writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
+ MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
+ MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
+ MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
+ MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
+ MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
+ MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
+ MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR)
sdram_init
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 45e59fbfd2..0b66b04e5f 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -18,7 +18,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
@@ -279,8 +279,6 @@ static int pca100_devices_init(void)
PD18_PF_I2C_CLK,
};
- PCCR0 |= PCCR0_SDHC2_EN;
-
pca100_usb_init();
/* initizalize gpios */
@@ -292,8 +290,6 @@ static int pca100_devices_init(void)
imx27_add_mmc1(NULL);
imx27_add_fb(&pca100_fb_data);
- PCCR1 |= PCCR1_PERCLK2_EN;
-
#ifdef CONFIG_USB
pca100_usb_register();
#endif
diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
index 5214394461..6d2ac98156 100644
--- a/arch/arm/boards/pm9261/init.c
+++ b/arch/arm/boards/pm9261/init.c
@@ -1,4 +1,6 @@
/*
+ * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
* Copyright (C) 2007 Sascha Hauer, Pengutronix
*
* This program is free software; you can redistribute it and/or
@@ -34,6 +36,13 @@
#include <mach/at91sam9_smc.h>
#include <mach/sam9_smc.h>
#include <dm9000.h>
+#include <linux/w1-gpio.h>
+#include <w1_mac_address.h>
+
+struct w1_gpio_platform_data w1_pdata = {
+ .pin = AT91_PIN_PA7,
+ .is_open_drain = 0,
+};
static struct atmel_nand_data nand_pdata = {
.ale = 22,
@@ -112,6 +121,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
static void __init pm_add_device_dm9000(void)
{
+ w1_local_mac_address_register(0, "ron", "w1-1-0");
/* Configure chip-select 2 (DM9000) */
sam9_smc_configure(2, &dm9000_smc_config);
diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c
index b17a90a7d1..14e821fd1b 100644
--- a/arch/arm/boards/pm9263/init.c
+++ b/arch/arm/boards/pm9263/init.c
@@ -1,4 +1,6 @@
/*
+ * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
* Copyright (C) 2007 Sascha Hauer, Pengutronix
*
* This program is free software; you can redistribute it and/or
@@ -34,6 +36,13 @@
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <mach/sam9_smc.h>
+#include <linux/w1-gpio.h>
+#include <w1_mac_address.h>
+
+struct w1_gpio_platform_data w1_pdata = {
+ .pin = AT91_PIN_PB31,
+ .is_open_drain = 0,
+};
static struct atmel_nand_data nand_pdata = {
.ale = 21,
@@ -85,6 +94,24 @@ static struct at91_ether_platform_data macb_pdata = {
.phy_addr = 0,
};
+static void pm9263_phy_init(void)
+{
+ /*
+ * PB27 enables the 50MHz oscillator for Ethernet PHY
+ * 1 - enable
+ * 0 - disable
+ */
+ at91_set_gpio_output(AT91_PIN_PB27, 1);
+ at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
+}
+
+static void pm9263_add_device_eth(void)
+{
+ w1_local_mac_address_register(0, "ron", "w1-1-0");
+ pm9263_phy_init();
+ at91_add_device_eth(0, &macb_pdata);
+}
+
static int pm9263_mem_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
@@ -95,16 +122,11 @@ mem_initcall(pm9263_mem_init);
static int pm9263_devices_init(void)
{
- /*
- * PB27 enables the 50MHz oscillator for Ethernet PHY
- * 1 - enable
- * 0 - disable
- */
- at91_set_gpio_output(AT91_PIN_PB27, 1);
- at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
+ at91_set_gpio_input(w1_pdata.pin, 0);
+ add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata);
pm_add_device_nand();
- at91_add_device_eth(0, &macb_pdata);
+ pm9263_add_device_eth();
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
diff --git a/arch/arm/boards/pm9g45/env/config b/arch/arm/boards/pm9g45/env/config
index 5f05e6f04f..18ac565d49 100644
--- a/arch/arm/boards/pm9g45/env/config
+++ b/arch/arm/boards/pm9g45/env/config
@@ -2,7 +2,8 @@
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
+ip=dhcp-barebox
+global.dhcp.vendor_id=barebox-pm9g45
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
@@ -11,16 +12,18 @@ ip=dhcp
#eth0.serverip=a.b.c.d
# can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=nand
+kernel_loc=nfs
# can be either 'net', 'nand' or 'initrd'
-rootfs_loc=nand
+rootfs_loc=net
+# can be either 'nfs', 'tftp', 'nand' or empty
+oftree_loc=nfs
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root.$rootfs_type
-#kernelimage=zImage
-kernelimage=uImage
+kernelimage=zImage
+#kernelimage=uImage
#kernelimage=Image
#kernelimage=Image.lzo
diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
index 17b38d4b59..675ebe8515 100644
--- a/arch/arm/boards/pm9g45/init.c
+++ b/arch/arm/boards/pm9g45/init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* Copyright (C) 2007 Sascha Hauer, Pengutronix
*
@@ -35,6 +35,13 @@
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <mach/sam9_smc.h>
+#include <linux/w1-gpio.h>
+#include <w1_mac_address.h>
+
+struct w1_gpio_platform_data w1_pdata = {
+ .pin = AT91_PIN_PA31,
+ .is_open_drain = 0,
+};
static struct atmel_nand_data nand_pdata = {
.ale = 21,
@@ -43,6 +50,7 @@ static struct atmel_nand_data nand_pdata = {
.rdy_pin = AT91_PIN_PD3,
.enable_pin = AT91_PIN_PC14,
.bus_width_16 = 0,
+ .on_flash_bbt = 1,
};
static struct sam9_smc_config pm_nand_smc_config = {
@@ -121,6 +129,13 @@ static void pm9g45_phy_init(void)
at91_set_gpio_value(AT91_PIN_PD2, 1);
}
+static void pm9g45_add_device_eth(void)
+{
+ w1_local_mac_address_register(0, "ron", "w1-1-0");
+ pm9g45_phy_init();
+ at91_add_device_eth(0, &macb_pdata);
+}
+
static int pm9g45_mem_init(void)
{
at91_add_device_sdram(128 * 1024 * 1024);
@@ -131,15 +146,19 @@ mem_initcall(pm9g45_mem_init);
static int pm9g45_devices_init(void)
{
+ at91_set_gpio_input(w1_pdata.pin, 0);
+ add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata);
+
pm_add_device_nand();
pm9g45_add_device_mci();
- pm9g45_phy_init();
- at91_add_device_eth(0, &macb_pdata);
+ pm9g45_add_device_eth();
pm9g45_add_device_usbh();
- devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
+ dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
+ devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x40000, DEVFS_PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100));
diff --git a/arch/arm/boards/raspberry-pi/Makefile b/arch/arm/boards/raspberry-pi/Makefile
new file mode 100644
index 0000000000..6ce5edeb27
--- /dev/null
+++ b/arch/arm/boards/raspberry-pi/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_RPI) += rpi.o
diff --git a/arch/arm/boards/raspberry-pi/config.h b/arch/arm/boards/raspberry-pi/config.h
new file mode 100644
index 0000000000..ca15136817
--- /dev/null
+++ b/arch/arm/boards/raspberry-pi/config.h
@@ -0,0 +1,4 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/freescale-mx51-pdk/env/init/bootargs-base b/arch/arm/boards/raspberry-pi/env/init/bootargs-base
index d86975406e..d86975406e 100644
--- a/arch/arm/boards/freescale-mx51-pdk/env/init/bootargs-base
+++ b/arch/arm/boards/raspberry-pi/env/init/bootargs-base
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/env/init/hostname b/arch/arm/boards/raspberry-pi/env/init/hostname
index db5b2b22ce..7e8f294357 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/env/init/hostname
+++ b/arch/arm/boards/raspberry-pi/env/init/hostname
@@ -5,4 +5,4 @@ if [ "$1" = menu ]; then
exit
fi
-global.hostname=SabreLite
+global.hostname=Raspberry-Pi
diff --git a/arch/arm/boards/raspberry-pi/rpi.c b/arch/arm/boards/raspberry-pi/rpi.c
new file mode 100644
index 0000000000..3be95ae5c4
--- /dev/null
+++ b/arch/arm/boards/raspberry-pi/rpi.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2009 Carlo Caione <carlo@carlocaione.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+
+#include <mach/core.h>
+
+static int rpi_mem_init(void)
+{
+ bcm2835_add_device_sdram(0);
+ return 0;
+}
+mem_initcall(rpi_mem_init);
+
+static int rpi_console_init(void)
+{
+ bcm2835_register_uart();
+ return 0;
+}
+console_initcall(rpi_console_init);
+
+static int rpi_devices_init(void)
+{
+ armlinux_set_architecture(MACH_TYPE_BCM2708);
+ armlinux_set_bootparams((void *)(0x00000100));
+ return 0;
+}
+
+device_initcall(rpi_devices_init);
diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S
index fabc89ea1e..cefac8481a 100644
--- a/arch/arm/boards/scb9328/lowlevel_init.S
+++ b/arch/arm/boards/scb9328/lowlevel_init.S
@@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/
-#include <mach/imx-regs.h>
+#include <mach/imx1-regs.h>
#include <asm/barebox-arm-head.h>
#define CPU200
@@ -82,13 +82,13 @@ reset:
common_reset r0
/* Change PERCLK1DIV to 14 ie 14+1 */
- writel(CFG_PCDR_VAL, PCDR)
+ writel(CFG_PCDR_VAL, MX1_CCM_BASE_ADDR + MX1_PCDR)
/* set MCU PLL Control Register 0 */
- writel(CFG_MPCTL0_VAL, MPCTL0)
+ writel(CFG_MPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_MPCTL0)
/* set mpll restart bit */
- ldr r0, =CSCR
+ ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR
ldr r1, [r0]
orr r1,r1,#(1<<21)
str r1, [r0]
@@ -104,10 +104,10 @@ reset:
bne 1b
/* set System PLL Control Register 0 */
- writel(CFG_SPCTL0_VAL, SPCTL0)
+ writel(CFG_SPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_SPCTL0)
/* set spll restart bit */
- ldr r0, =CSCR
+ ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR
ldr r1, [r0]
orr r1,r1,#(1<<22)
str r1, [r0]
@@ -122,7 +122,7 @@ reset:
subs r2,r2,#1
bne 1b
- writel(CFG_CSCR_VAL, CSCR)
+ writel(CFG_CSCR_VAL, MX1_CCM_BASE_ADDR + MX1_CSCR)
/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
*this.....
@@ -157,9 +157,12 @@ reset:
/* SDRAM Setup */
- writel(0x910a8200, SDCTL0) /* Precharge cmd, CAS = 2 */
- writel(0x0, 0x08200000) /* Issue Precharge all Command */
- writel(0xa10a8200, SDCTL0) /* Autorefresh cmd, CAS = 2 */
+ /* Precharge cmd, CAS = 2 */
+ writel(0x910a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
+ /* Issue Precharge all Command */
+ writel(0x0, 0x08200000)
+ /* Autorefresh cmd, CAS = 2 */
+ writel(0xa10a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
ldr r0, =0x08000000
ldr r1, =0x0 /* Issue AutoRefresh Command */
@@ -172,8 +175,10 @@ reset:
str r1, [r0]
str r1, [r0]
- writel(0xb10a8300, SDCTL0)
- writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */
- writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */
+ writel(0xb10a8300, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
+ /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */
+ writel(0x0, 0x08223000)
+ /* Set to Normal Mode CAS 2 */
+ writel(0x810a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
b board_init_lowlevel_return
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index c83132adc8..c70852c308 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -19,7 +19,7 @@
#include <init.h>
#include <environment.h>
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx1-regs.h>
#include <asm/armlinux.h>
#include <mach/gpio.h>
#include <mach/weim.h>
@@ -29,6 +29,7 @@
#include <fcntl.h>
#include <dm9000.h>
#include <led.h>
+#include <mach/iomux-mx1.h>
#include <mach/devices-imx1.h>
static struct dm9000_platform_data dm9000_data = {
@@ -68,8 +69,8 @@ static int scb9328_devices_init(void)
for (i = 0; i < ARRAY_SIZE(leds); i++)
led_gpio_register(&leds[i]);
-/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
- FMCR = 0x1;
+ /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
+ writel(0x1, MX1_SCM_BASE_ADDR + MX1_FMCR);
imx1_setup_eimcs(0, 0x000F2000, 0x11110d01);
imx1_setup_eimcs(1, 0x000F0a00, 0x11110601);
diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c
index 8c3d855608..77535b53f2 100644
--- a/arch/arm/boards/tqma53/board.c
+++ b/arch/arm/boards/tqma53/board.c
@@ -30,7 +30,7 @@
#include <asm/mmu.h>
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
diff --git a/arch/arm/boards/tqma53/env/init/bootargs-base b/arch/arm/boards/tqma53/env/init/bootargs-base
deleted file mode 100644
index d86975406e..0000000000
--- a/arch/arm/boards/tqma53/env/init/bootargs-base
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "Base bootargs"
- exit
-fi
-
-global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/tqma53/env/init/config-board b/arch/arm/boards/tqma53/env/init/config-board
new file mode 100644
index 0000000000..4776438315
--- /dev/null
+++ b/arch/arm/boards/tqma53/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=tqma53
+global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/tqma53/env/init/hostname b/arch/arm/boards/tqma53/env/init/hostname
deleted file mode 100644
index c56ac6a5ea..0000000000
--- a/arch/arm/boards/tqma53/env/init/hostname
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "hostname"
- exit
-fi
-
-global.hostname=tqma53
diff --git a/arch/arm/boards/versatile/versatilepb.c b/arch/arm/boards/versatile/versatilepb.c
index 5a9c0b65ec..2eb7473b74 100644
--- a/arch/arm/boards/versatile/versatilepb.c
+++ b/arch/arm/boards/versatile/versatilepb.c
@@ -47,6 +47,7 @@ mem_initcall(vpb_mem_init);
static int vpb_devices_init(void)
{
add_cfi_flash_device(DEVICE_ID_DYNAMIC, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0);
+ versatile_register_i2c();
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 6a105c6ebc..2bcade91fb 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -32,9 +32,14 @@ CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_ZLIB=y
CONFIG_CMD_BOOTM_BZLIB=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
diff --git a/arch/arm/configs/at91sam9x5ek_defconfig b/arch/arm/configs/at91sam9x5ek_defconfig
index cda360ddbb..6c3534849b 100644
--- a/arch/arm/configs/at91sam9x5ek_defconfig
+++ b/arch/arm/configs/at91sam9x5ek_defconfig
@@ -3,6 +3,7 @@ CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
+CONFIG_MMU=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_EXPERIMENTAL=y
CONFIG_MALLOC_TLSF=y
@@ -41,6 +42,7 @@ CONFIG_CMD_OFTREE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_LED=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_NET=y
@@ -51,20 +53,31 @@ CONFIG_CMD_TFTP=y
CONFIG_FS_TFTP=y
CONFIG_NET_NETCONSOLE=y
CONFIG_DRIVER_NET_MACB=y
-# CONFIG_SPI is not set
+CONFIG_DRIVER_SPI_ATMEL=y
+CONFIG_MTD_M25P80=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_MTD_DATAFLASH=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
CONFIG_UBI=y
-CONFIG_DISK=y
-CONFIG_DISK_WRITE=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_ATMEL=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_TRIGGERS=y
-CONFIG_KEYBOARD_GPIO=y
+CONFIG_EEPROM_AT24=y
+CONFIG_KEYBOARD_QT1070=y
+CONFIG_W1=y
+CONFIG_W1_MASTER_GPIO=y
+CONFIG_W1_SLAVE_DS2431=y
+CONFIG_W1_SLAVE_DS2433=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
new file mode 100644
index 0000000000..cf2b3b6825
--- /dev/null
+++ b/arch/arm/configs/clps711x_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARCH_CLPS711X=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+# CONFIG_MEMINFO is not set
+CONFIG_TEXT_BASE=0xc0780000
+CONFIG_EXPERIMENTAL=y
+CONFIG_BAUDRATE=57600
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/clep7212/env"
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+# CONFIG_SPI is not set
+CONFIG_DRIVER_CFI=y
+# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
+# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set
+CONFIG_MTD=y
+CONFIG_DISK=y
+CONFIG_DISK_WRITE=y
+CONFIG_DISK_INTF_PLATFORM_IDE=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/freescale_mx53_loco_defconfig b/arch/arm/configs/freescale_mx53_loco_defconfig
index 37aa18239e..b50b0509c3 100644
--- a/arch/arm/configs/freescale_mx53_loco_defconfig
+++ b/arch/arm/configs/freescale_mx53_loco_defconfig
@@ -53,6 +53,7 @@ CONFIG_NET_PING=y
CONFIG_CMD_TFTP=y
CONFIG_FS_TFTP=y
CONFIG_NET_NETCONSOLE=y
+CONFIG_SMSC_PHY=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_I2C=y
diff --git a/arch/arm/configs/pm9261_defconfig b/arch/arm/configs/pm9261_defconfig
index 1db16d5207..0aea2c9939 100644
--- a/arch/arm/configs/pm9261_defconfig
+++ b/arch/arm/configs/pm9261_defconfig
@@ -50,3 +50,5 @@ CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_UBI=y
+CONFIG_W1=y
+CONFIG_W1_MASTER_GPIO=y
diff --git a/arch/arm/configs/pm9263_defconfig b/arch/arm/configs/pm9263_defconfig
index 8c928946da..e223e773f0 100644
--- a/arch/arm/configs/pm9263_defconfig
+++ b/arch/arm/configs/pm9263_defconfig
@@ -35,3 +35,5 @@ CONFIG_DRIVER_NET_MACB=y
# CONFIG_SPI is not set
CONFIG_DRIVER_CFI=y
CONFIG_CFI_BUFFER_WRITE=y
+CONFIG_W1=y
+CONFIG_W1_MASTER_GPIO=y
diff --git a/arch/arm/configs/pm9g45_defconfig b/arch/arm/configs/pm9g45_defconfig
index 331f122635..d242bdc0f3 100644
--- a/arch/arm/configs/pm9g45_defconfig
+++ b/arch/arm/configs/pm9g45_defconfig
@@ -1,36 +1,52 @@
CONFIG_ARCH_AT91SAM9G45=y
CONFIG_MACH_PM9G45=y
CONFIG_AEABI=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_PBL_IMAGE=y
+CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
+CONFIG_MALLOC_TLSF=y
CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_GLOB_SORT=y
+CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pm9g45/env"
-CONFIG_POLLER=y
-CONFIG_ENABLE_DEVICE_NOISE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
+# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
CONFIG_NET_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_FS_TFTP=y
CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_MACB=y
-CONFIG_DRIVER_SPI_ATMEL=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SST25L=y
+# CONFIG_SPI is not set
CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_NAND=y
+# CONFIG_NAND_ECC_HW is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
+# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
CONFIG_UBI=y
CONFIG_DISK_ATA=y
@@ -40,7 +56,9 @@ CONFIG_USB_OHCI_AT91=y
CONFIG_USB_STORAGE=y
CONFIG_MCI=y
CONFIG_MCI_ATMEL=y
-CONFIG_EEPROM_AT25=y
+CONFIG_W1=y
+CONFIG_W1_MASTER_GPIO=y
+CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
new file mode 100644
index 0000000000..014e28c73d
--- /dev/null
+++ b/arch/arm/configs/rpi_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARCH_BCM2835=y
+CONFIG_GPIO_BCM2835=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_PROMPT="R-Pi> "
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/raspberry-pi/env"
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_PASSWD=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_MTEST_ALTERNATIVE=y
+CONFIG_CMD_BOOTM_ZLIB=y
+CONFIG_CMD_BOOTM_BZLIB=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_GPIO=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
diff --git a/arch/arm/configs/tx53stk5_defconfig b/arch/arm/configs/tx53stk5_defconfig
index 95cf460b47..e0ab9c8ccf 100644
--- a/arch/arm/configs/tx53stk5_defconfig
+++ b/arch/arm/configs/tx53stk5_defconfig
@@ -1,13 +1,16 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX53=y
CONFIG_MACH_TX53=y
+CONFIG_TX53_REV_XX30=y
CONFIG_IMX_IIM=y
CONFIG_AEABI=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
+CONFIG_PBL_IMAGE=y
+CONFIG_IMAGE_COMPRESSION_GZIP=y
CONFIG_MMU=y
-CONFIG_TEXT_BASE=0x97f00000
+CONFIG_TEXT_BASE=0x87f00000
CONFIG_MALLOC_SIZE=0x2000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
@@ -16,7 +19,6 @@ CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
-CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/karo-tx53/env"
CONFIG_RESET_SOURCE=y
@@ -36,8 +38,6 @@ CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_MTEST=y
-CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
@@ -47,6 +47,8 @@ CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
@@ -57,8 +59,6 @@ CONFIG_CMD_LED=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
-CONFIG_NET_TFTP=y
-CONFIG_NET_TFTP_PUSH=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
diff --git a/arch/arm/configs/versatilepb_defconfig b/arch/arm/configs/versatilepb_defconfig
index 87aec4d526..8daf9ae72f 100644
--- a/arch/arm/configs/versatilepb_defconfig
+++ b/arch/arm/configs/versatilepb_defconfig
@@ -32,7 +32,9 @@ CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
@@ -43,6 +45,9 @@ CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_DRIVER_NET_SMC91111=y
+CONFIG_GPIO_PL061=y
+CONFIG_I2C=y
+CONFIG_I2C_VERSATILE=y
CONFIG_FS_CRAMFS=y
CONFIG_SHA1=y
CONFIG_SHA256=y
diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig
index 2ed678961d..d8a5fb1734 100644
--- a/arch/arm/cpu/Kconfig
+++ b/arch/arm/cpu/Kconfig
@@ -8,6 +8,11 @@ config CPU_32
# which CPUs we support in the kernel image, and the compiler instruction
# optimiser behaviour.
+# ARM1176
+config CPU_ARM1176
+ bool
+ select CPU_V6
+
# ARM920T
config CPU_ARM920T
bool
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index f7ab2761ad..4b0259c15b 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,14 +1,15 @@
obj-y += cpu.o
obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o
obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
-obj-y += start.o
+obj-y += start.o setupc.o
#
# Any variants can be called as start-armxyz.S
#
obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o
obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
-obj-$(CONFIG_MMU) += mmu.o
+obj-$(CONFIG_MMU) += mmu.o cache.o
+pbl-$(CONFIG_MMU) += cache.o
obj-$(CONFIG_CPU_32v4T) += cache-armv4.o
pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o
obj-$(CONFIG_CPU_32v5) += cache-armv5.o
@@ -19,4 +20,4 @@ obj-$(CONFIG_CPU_32v7) += cache-armv7.o
pbl-$(CONFIG_CPU_32v7) += cache-armv7.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
-pbl-y += start-pbl.o
+pbl-y += start-pbl.o setupc.o
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index 22fab1455c..1d1a1e32bf 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -4,7 +4,7 @@
#define CACHE_DLINESIZE 32
.section .text.__mmu_cache_on
-ENTRY(__mmu_cache_on)
+ENTRY(v4_mmu_cache_on)
mov r12, lr
#ifdef CONFIG_MMU
mov r0, #0
@@ -21,7 +21,7 @@ ENTRY(__mmu_cache_on)
mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
#endif
mov pc, r12
-ENDPROC(__mmu_cache_on)
+ENDPROC(v4_mmu_cache_on)
__common_mmu_cache_on:
orr r0, r0, #0x000d @ Write buffer, mmu
@@ -31,8 +31,8 @@ __common_mmu_cache_on:
mrc p15, 0, r0, c1, c0, 0 @ and read it back to
sub pc, lr, r0, lsr #32 @ properly flush pipeline
-.section .text.__mmu_cache_off
-ENTRY(__mmu_cache_off)
+.section .text.v4_mmu_cache_off
+ENTRY(v4_mmu_cache_off)
#ifdef CONFIG_MMU
mrc p15, 0, r0, c1, c0
bic r0, r0, #0x000d
@@ -42,10 +42,10 @@ ENTRY(__mmu_cache_off)
mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
#endif
mov pc, lr
-ENDPROC(__mmu_cache_off)
+ENDPROC(v4_mmu_cache_off)
-.section .text.__mmu_cache_flush
-ENTRY(__mmu_cache_flush)
+.section .text.v4_mmu_cache_flush
+ENTRY(v4_mmu_cache_flush)
stmfd sp!, {r6, r11, lr}
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
@@ -76,7 +76,7 @@ no_cache_id:
mcr p15, 0, r1, c7, c6, 0 @ flush D cache
mcr p15, 0, r1, c7, c10, 4 @ drain WB
ldmfd sp!, {r6, r11, pc}
-ENDPROC(__mmu_cache_flush)
+ENDPROC(v4_mmu_cache_flush)
/*
* dma_inv_range(start, end)
@@ -91,8 +91,8 @@ ENDPROC(__mmu_cache_flush)
*
* (same as v4wb)
*/
-.section .text.__dma_inv_range
-ENTRY(__dma_inv_range)
+.section .text.v4_dma_inv_range
+ENTRY(v4_dma_inv_range)
tst r0, #CACHE_DLINESIZE - 1
bic r0, r0, #CACHE_DLINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -115,8 +115,8 @@ ENTRY(__dma_inv_range)
*
* (same as v4wb)
*/
-.section .text.__dma_clean_range
-ENTRY(__dma_clean_range)
+.section .text.v4_dma_clean_range
+ENTRY(v4_dma_clean_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #CACHE_DLINESIZE
@@ -133,8 +133,8 @@ ENTRY(__dma_clean_range)
* - start - virtual start address
* - end - virtual end address
*/
-.section .text.__dma_flush_range
-ENTRY(__dma_flush_range)
+.section .text.v4_dma_flush_range
+ENTRY(v4_dma_flush_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
add r0, r0, #CACHE_DLINESIZE
diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S
index d6ffaf10e2..4267f3e37f 100644
--- a/arch/arm/cpu/cache-armv5.S
+++ b/arch/arm/cpu/cache-armv5.S
@@ -3,8 +3,8 @@
#define CACHE_DLINESIZE 32
-.section .text.__mmu_cache_on
-ENTRY(__mmu_cache_on)
+.section .text.v5_mmu_cache_on
+ENTRY(v5_mmu_cache_on)
mov r12, lr
#ifdef CONFIG_MMU
mov r0, #0
@@ -21,7 +21,7 @@ ENTRY(__mmu_cache_on)
mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
#endif
mov pc, r12
-ENDPROC(__mmu_cache_on)
+ENDPROC(v5_mmu_cache_on)
__common_mmu_cache_on:
orr r0, r0, #0x000d @ Write buffer, mmu
@@ -31,8 +31,8 @@ __common_mmu_cache_on:
mrc p15, 0, r0, c1, c0, 0 @ and read it back to
sub pc, lr, r0, lsr #32 @ properly flush pipeline
-.section .text.__mmu_cache_off
-ENTRY(__mmu_cache_off)
+.section .text.v5_mmu_cache_off
+ENTRY(v5_mmu_cache_off)
#ifdef CONFIG_MMU
mrc p15, 0, r0, c1, c0
bic r0, r0, #0x000d
@@ -42,16 +42,16 @@ ENTRY(__mmu_cache_off)
mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
#endif
mov pc, lr
-ENDPROC(__mmu_cache_off)
+ENDPROC(v5_mmu_cache_off)
-.section .text.__mmu_cache_flush
-ENTRY(__mmu_cache_flush)
+.section .text.v5_mmu_cache_flush
+ENTRY(v5_mmu_cache_flush)
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
mcr p15, 0, r0, c7, c5, 0 @ flush I cache
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
-ENDPROC(__mmu_cache_flush)
+ENDPROC(v5_mmu_cache_flush)
/*
* dma_inv_range(start, end)
@@ -66,8 +66,8 @@ ENDPROC(__mmu_cache_flush)
*
* (same as v4wb)
*/
-.section .text.__dma_inv_range
-ENTRY(__dma_inv_range)
+.section .text.v5_dma_inv_range
+ENTRY(v5_dma_inv_range)
tst r0, #CACHE_DLINESIZE - 1
bic r0, r0, #CACHE_DLINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -90,8 +90,8 @@ ENTRY(__dma_inv_range)
*
* (same as v4wb)
*/
-.section .text.__dma_clean_range
-ENTRY(__dma_clean_range)
+.section .text.v5_dma_clean_range
+ENTRY(v5_dma_clean_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #CACHE_DLINESIZE
@@ -108,8 +108,8 @@ ENTRY(__dma_clean_range)
* - start - virtual start address
* - end - virtual end address
*/
-.section .text.__dma_flush_range
-ENTRY(__dma_flush_range)
+.section .text.v5_dma_flush_range
+ENTRY(v5_dma_flush_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
add r0, r0, #CACHE_DLINESIZE
diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S
index 02b1d3e58a..7a06751997 100644
--- a/arch/arm/cpu/cache-armv6.S
+++ b/arch/arm/cpu/cache-armv6.S
@@ -5,8 +5,8 @@
#define CACHE_LINE_SIZE 32
#define D_CACHE_LINE_SIZE 32
-.section .text.__mmu_cache_on
-ENTRY(__mmu_cache_on)
+.section .text.v6_mmu_cache_on
+ENTRY(v6_mmu_cache_on)
mov r12, lr
#ifdef CONFIG_MMU
mov r0, #0
@@ -23,7 +23,7 @@ ENTRY(__mmu_cache_on)
mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
#endif
mov pc, r12
-ENDPROC(__mmu_cache_on)
+ENDPROC(v6_mmu_cache_on)
__common_mmu_cache_on:
orr r0, r0, #0x000d @ Write buffer, mmu
@@ -34,8 +34,8 @@ __common_mmu_cache_on:
sub pc, lr, r0, lsr #32 @ properly flush pipeline
-.section .text.__mmu_cache_off
-ENTRY(__mmu_cache_off)
+.section .text.v6_mmu_cache_off
+ENTRY(v6_mmu_cache_off)
#ifdef CONFIG_MMU
mrc p15, 0, r0, c1, c0
bic r0, r0, #0x000d
@@ -46,15 +46,15 @@ ENTRY(__mmu_cache_off)
#endif
mov pc, lr
-.section .text.__mmu_cache_flush
-ENTRY(__mmu_cache_flush)
+.section .text.v6_mmu_cache_flush
+ENTRY(v6_mmu_cache_flush)
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
-ENDPROC(__mmu_cache_flush)
+ENDPROC(v6_mmu_cache_flush)
/*
* v6_dma_inv_range(start,end)
@@ -66,8 +66,8 @@ ENDPROC(__mmu_cache_flush)
* - start - virtual start address of region
* - end - virtual end address of region
*/
-.section .text.__dma_inv_range
-ENTRY(__dma_inv_range)
+.section .text.v6_dma_inv_range
+ENTRY(v6_dma_inv_range)
tst r0, #D_CACHE_LINE_SIZE - 1
bic r0, r0, #D_CACHE_LINE_SIZE - 1
#ifdef HARVARD_CACHE
@@ -94,15 +94,15 @@ ENTRY(__dma_inv_range)
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
-ENDPROC(__dma_inv_range)
+ENDPROC(v6_dma_inv_range)
/*
* v6_dma_clean_range(start,end)
* - start - virtual start address of region
* - end - virtual end address of region
*/
-.section .text.__dma_clean_range
-ENTRY(__dma_clean_range)
+.section .text.v6_dma_clean_range
+ENTRY(v6_dma_clean_range)
bic r0, r0, #D_CACHE_LINE_SIZE - 1
1:
#ifdef HARVARD_CACHE
@@ -116,15 +116,15 @@ ENTRY(__dma_clean_range)
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
-ENDPROC(__dma_clean_range)
+ENDPROC(v6_dma_clean_range)
/*
* v6_dma_flush_range(start,end)
* - start - virtual start address of region
* - end - virtual end address of region
*/
-.section .text.__dma_flush_range
-ENTRY(__dma_flush_range)
+.section .text.v6_dma_flush_range
+ENTRY(v6_dma_flush_range)
bic r0, r0, #D_CACHE_LINE_SIZE - 1
1:
#ifdef HARVARD_CACHE
@@ -138,4 +138,4 @@ ENTRY(__dma_flush_range)
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
-ENDPROC(__dma_flush_range)
+ENDPROC(v6_dma_flush_range)
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 2eba959672..2d68f27eeb 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -1,8 +1,8 @@
#include <linux/linkage.h>
#include <init.h>
-.section .text.__mmu_cache_on
-ENTRY(__mmu_cache_on)
+.section .text.v7_mmu_cache_on
+ENTRY(v7_mmu_cache_on)
stmfd sp!, {r11, lr}
mov r12, lr
#ifdef CONFIG_MMU
@@ -30,10 +30,10 @@ ENTRY(__mmu_cache_on)
mov r0, #0
mcr p15, 0, r0, c7, c5, 4 @ ISB
ldmfd sp!, {r11, pc}
-ENDPROC(__mmu_cache_on)
+ENDPROC(v7_mmu_cache_on)
-.section .text.__mmu_cache_off
-ENTRY(__mmu_cache_off)
+.section .text.v7_mmu_cache_off
+ENTRY(v7_mmu_cache_off)
mrc p15, 0, r0, c1, c0
#ifdef CONFIG_MMU
bic r0, r0, #0x000d
@@ -42,7 +42,7 @@ ENTRY(__mmu_cache_off)
#endif
mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
mov r12, lr
- bl __mmu_cache_flush
+ bl v7_mmu_cache_flush
mov r0, #0
#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
@@ -51,10 +51,10 @@ ENTRY(__mmu_cache_off)
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
mov pc, r12
-ENDPROC(__mmu_cache_off)
+ENDPROC(v7_mmu_cache_off)
-.section .text.__mmu_cache_flush
-ENTRY(__mmu_cache_flush)
+.section .text.v7_mmu_cache_flush
+ENTRY(v7_mmu_cache_flush)
stmfd sp!, {r10, lr}
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
@@ -114,7 +114,7 @@ iflush:
mcr p15, 0, r10, c7, c10, 4 @ DSB
mcr p15, 0, r10, c7, c5, 4 @ ISB
ldmfd sp!, {r10, pc}
-ENDPROC(__mmu_cache_flush)
+ENDPROC(v7_mmu_cache_flush)
/*
* cache_line_size - get the cache line size from the CSIDR register
@@ -138,8 +138,8 @@ ENDPROC(__mmu_cache_flush)
* - start - virtual start address of region
* - end - virtual end address of region
*/
-.section .text.__dma_inv_range
-ENTRY(__dma_inv_range)
+.section .text.v7_dma_inv_range
+ENTRY(v7_dma_inv_range)
dcache_line_size r2, r3
sub r3, r2, #1
tst r0, r3
@@ -156,15 +156,15 @@ ENTRY(__dma_inv_range)
blo 1b
dsb
mov pc, lr
-ENDPROC(__dma_inv_range)
+ENDPROC(v7_dma_inv_range)
/*
* v7_dma_clean_range(start,end)
* - start - virtual start address of region
* - end - virtual end address of region
*/
-.section .text.__dma_clean_range
-ENTRY(__dma_clean_range)
+.section .text.v7_dma_clean_range
+ENTRY(v7_dma_clean_range)
dcache_line_size r2, r3
sub r3, r2, #1
bic r0, r0, r3
@@ -175,15 +175,15 @@ ENTRY(__dma_clean_range)
blo 1b
dsb
mov pc, lr
-ENDPROC(__dma_clean_range)
+ENDPROC(v7_dma_clean_range)
/*
* v7_dma_flush_range(start,end)
* - start - virtual start address of region
* - end - virtual end address of region
*/
-.section .text.__dma_flush_range
-ENTRY(__dma_flush_range)
+.section .text.v7_dma_flush_range
+ENTRY(v7_dma_flush_range)
dcache_line_size r2, r3
sub r3, r2, #1
bic r0, r0, r3
@@ -194,4 +194,4 @@ ENTRY(__dma_flush_range)
blo 1b
dsb
mov pc, lr
-ENDPROC(__dma_flush_range)
+ENDPROC(v7_dma_flush_range)
diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c
new file mode 100644
index 0000000000..1254609bb6
--- /dev/null
+++ b/arch/arm/cpu/cache.c
@@ -0,0 +1,103 @@
+#include <common.h>
+#include <init.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/system_info.h>
+
+int arm_architecture;
+
+struct cache_fns {
+ void (*dma_clean_range)(unsigned long start, unsigned long end);
+ void (*dma_flush_range)(unsigned long start, unsigned long end);
+ void (*dma_inv_range)(unsigned long start, unsigned long end);
+ void (*mmu_cache_on)(void);
+ void (*mmu_cache_off)(void);
+ void (*mmu_cache_flush)(void);
+};
+
+struct cache_fns *cache_fns;
+
+#define DEFINE_CPU_FNS(arch) \
+ void arch##_dma_clean_range(unsigned long start, unsigned long end); \
+ void arch##_dma_flush_range(unsigned long start, unsigned long end); \
+ void arch##_dma_inv_range(unsigned long start, unsigned long end); \
+ void arch##_mmu_cache_on(void); \
+ void arch##_mmu_cache_off(void); \
+ void arch##_mmu_cache_flush(void); \
+ \
+ static struct cache_fns __maybe_unused cache_fns_arm##arch = { \
+ .dma_clean_range = arch##_dma_clean_range, \
+ .dma_flush_range = arch##_dma_flush_range, \
+ .dma_inv_range = arch##_dma_inv_range, \
+ .mmu_cache_on = arch##_mmu_cache_on, \
+ .mmu_cache_off = arch##_mmu_cache_off, \
+ .mmu_cache_flush = arch##_mmu_cache_flush, \
+ };
+
+DEFINE_CPU_FNS(v4)
+DEFINE_CPU_FNS(v5)
+DEFINE_CPU_FNS(v6)
+DEFINE_CPU_FNS(v7)
+
+void __dma_clean_range(unsigned long start, unsigned long end)
+{
+ cache_fns->dma_clean_range(start, end);
+}
+
+void __dma_flush_range(unsigned long start, unsigned long end)
+{
+ cache_fns->dma_flush_range(start, end);
+}
+
+void __dma_inv_range(unsigned long start, unsigned long end)
+{
+ cache_fns->dma_inv_range(start, end);
+}
+
+void __mmu_cache_on(void)
+{
+ cache_fns->mmu_cache_on();
+}
+
+void __mmu_cache_off(void)
+{
+ cache_fns->mmu_cache_off();
+}
+
+void __mmu_cache_flush(void)
+{
+ cache_fns->mmu_cache_flush();
+}
+
+int arm_set_cache_functions(void)
+{
+ switch (cpu_architecture()) {
+#ifdef CONFIG_CPU_32v4T
+ case CPU_ARCH_ARMv4T:
+ cache_fns = &cache_fns_armv4;
+ break;
+#endif
+#ifdef CONFIG_CPU_32v5
+ case CPU_ARCH_ARMv5:
+ case CPU_ARCH_ARMv5T:
+ case CPU_ARCH_ARMv5TE:
+ case CPU_ARCH_ARMv5TEJ:
+ cache_fns = &cache_fns_armv5;
+ break;
+#endif
+#ifdef CONFIG_CPU_32v6
+ case CPU_ARCH_ARMv6:
+ cache_fns = &cache_fns_armv6;
+ break;
+#endif
+#ifdef CONFIG_CPU_32v7
+ case CPU_ARCH_ARMv7:
+ cache_fns = &cache_fns_armv7;
+ break;
+#endif
+ default:
+ BUG();
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 87ba877013..2ca871fc60 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -28,6 +28,10 @@
#include <asm/mmu.h>
#include <asm/system.h>
#include <asm/memory.h>
+#include <asm/system_info.h>
+#include <asm/cputype.h>
+#include <asm/cache.h>
+#include <asm/ptrace.h>
/**
* Enable processor's instruction cache
@@ -71,20 +75,20 @@ int icache_status(void)
*/
void arch_shutdown(void)
{
+ uint32_t r;
+
#ifdef CONFIG_MMU
- /* nearly the same as below, but this could also disable
- * second level cache.
- */
mmu_disable();
-#else
- asm volatile (
- "bl __mmu_cache_flush;"
- "bl __mmu_cache_off;"
- :
- :
- : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
- );
#endif
+ flush_icache();
+ /*
+ * barebox normally does not use interrupts, but some functionalities
+ * (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
+ * disabled before exiting.
+ */
+ __asm__ __volatile__("mrs %0, cpsr" : "=r"(r));
+ r |= PSR_I_BIT;
+ __asm__ __volatile__("msr cpsr, %0" : : "r"(r));
}
#ifdef CONFIG_THUMB2_BAREBOX
@@ -112,3 +116,48 @@ static int execute_init(void)
}
postcore_initcall(execute_init);
#endif
+
+#ifdef ARM_MULTIARCH
+static int __get_cpu_architecture(void)
+{
+ int cpu_arch;
+
+ if ((read_cpuid_id() & 0x0008f000) == 0) {
+ cpu_arch = CPU_ARCH_UNKNOWN;
+ } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
+ cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
+ } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
+ cpu_arch = (read_cpuid_id() >> 16) & 7;
+ if (cpu_arch)
+ cpu_arch += CPU_ARCH_ARMv3;
+ } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
+ unsigned int mmfr0;
+
+ /* Revised CPUID format. Read the Memory Model Feature
+ * Register 0 and check for VMSAv7 or PMSAv7 */
+ asm("mrc p15, 0, %0, c0, c1, 4"
+ : "=r" (mmfr0));
+ if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
+ (mmfr0 & 0x000000f0) >= 0x00000030)
+ cpu_arch = CPU_ARCH_ARMv7;
+ else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
+ (mmfr0 & 0x000000f0) == 0x00000020)
+ cpu_arch = CPU_ARCH_ARMv6;
+ else
+ cpu_arch = CPU_ARCH_UNKNOWN;
+ } else
+ cpu_arch = CPU_ARCH_UNKNOWN;
+
+ return cpu_arch;
+}
+
+int __cpu_architecture;
+
+int __pure cpu_architecture(void)
+{
+ if(__cpu_architecture == CPU_ARCH_UNKNOWN)
+ __cpu_architecture = __get_cpu_architecture();
+
+ return __cpu_architecture;
+}
+#endif
diff --git a/arch/arm/cpu/exceptions.S b/arch/arm/cpu/exceptions.S
index 7f94f9f929..115c4e56b8 100644
--- a/arch/arm/cpu/exceptions.S
+++ b/arch/arm/cpu/exceptions.S
@@ -35,10 +35,6 @@
#define S_R0 0
#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-_STACK_START:
- .word STACK_BASE + STACK_SIZE - 4
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
@@ -48,8 +44,7 @@ _STACK_START:
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
- ldr r2, _STACK_START
- sub r2, r2, #(8) @ set base 2 words into abort stack
+ ldr r2, =abort_stack
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -80,9 +75,7 @@ _STACK_START:
.endm
.macro get_bad_stack
- ldr r13, _STACK_START
- sub r13, r13, #(8) @ reserved a couple spots in abort stack
-
+ ldr r13, =abort_stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
str lr, [r13, #4]
@@ -163,3 +156,8 @@ fiq:
1: b 1b /* irq (interrupt) */
1: b 1b /* fiq (fast interrupt) */
#endif
+
+.section .data
+.align 4
+abort_stack:
+.space 8
diff --git a/arch/arm/cpu/interrupts.c b/arch/arm/cpu/interrupts.c
index 4ed562f3dd..6e60adc43a 100644
--- a/arch/arm/cpu/interrupts.c
+++ b/arch/arm/cpu/interrupts.c
@@ -57,9 +57,9 @@ void show_regs (struct pt_regs *regs)
printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
printf ("Flags: %c%c%c%c",
- flags & CC_N_BIT ? 'N' : 'n',
- flags & CC_Z_BIT ? 'Z' : 'z',
- flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+ flags & PSR_N_BIT ? 'N' : 'n',
+ flags & PSR_Z_BIT ? 'Z' : 'z',
+ flags & PSR_C_BIT ? 'C' : 'c', flags & PSR_V_BIT ? 'V' : 'v');
printf (" IRQs %s FIQs %s Mode %s%s\n",
interrupts_enabled (regs) ? "on" : "off",
fast_interrupts_enabled (regs) ? "on" : "off",
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index e3ca722300..068e0eac1d 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -6,7 +6,9 @@
#include <asm/memory.h>
#include <asm/barebox-arm.h>
#include <asm/system.h>
+#include <asm/cache.h>
#include <memory.h>
+#include <asm/system_info.h>
#include "mmu.h"
@@ -43,13 +45,15 @@ static inline void tlb_invalidate(void)
);
}
-#ifdef CONFIG_CPU_V7
-#define PTE_FLAGS_CACHED (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE)
-#define PTE_FLAGS_UNCACHED (0)
-#else
-#define PTE_FLAGS_CACHED (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE)
-#define PTE_FLAGS_UNCACHED PTE_SMALL_AP_UNO_SRW
-#endif
+extern int arm_architecture;
+
+#define PTE_FLAGS_CACHED_V7 (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE)
+#define PTE_FLAGS_UNCACHED_V7 (0)
+#define PTE_FLAGS_CACHED_V4 (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE)
+#define PTE_FLAGS_UNCACHED_V4 PTE_SMALL_AP_UNO_SRW
+
+static uint32_t PTE_FLAGS_CACHED;
+static uint32_t PTE_FLAGS_UNCACHED;
#define PTE_MASK ((1 << 12) - 1)
@@ -226,6 +230,16 @@ static int mmu_init(void)
struct memory_bank *bank;
int i;
+ arm_set_cache_functions();
+
+ if (cpu_architecture() >= CPU_ARCH_ARMv7) {
+ PTE_FLAGS_CACHED = PTE_FLAGS_CACHED_V7;
+ PTE_FLAGS_UNCACHED = PTE_FLAGS_UNCACHED_V7;
+ } else {
+ PTE_FLAGS_CACHED = PTE_FLAGS_CACHED_V4;
+ PTE_FLAGS_UNCACHED = PTE_FLAGS_UNCACHED_V4;
+ }
+
ttb = memalign(0x10000, 0x4000);
debug("ttb: 0x%p\n", ttb);
diff --git a/arch/arm/cpu/setupc.S b/arch/arm/cpu/setupc.S
new file mode 100644
index 0000000000..9a8d54c224
--- /dev/null
+++ b/arch/arm/cpu/setupc.S
@@ -0,0 +1,34 @@
+#include <linux/linkage.h>
+
+.section .text.setupc
+
+/*
+ * setup_c: copy binary to link address, clear bss and
+ * continue executing at new address.
+ *
+ * This function does not return to the address it is
+ * called from, but to the same location in the copied
+ * binary.
+ */
+ENTRY(setup_c)
+ push {r4, r5}
+ mov r5, lr
+ bl get_runtime_offset
+ subs r4, r0, #0
+ beq 1f /* skip memcpy if already at correct address */
+ ldr r0,=_text
+ ldr r2,=__bss_start
+ sub r2, r2, r0
+ sub r1, r0, r4
+ bl memcpy /* memcpy(_text, _text - offset, __bss_start - _text) */
+1: ldr r0, =__bss_start
+ mov r1, #0
+ ldr r2, =__bss_stop
+ sub r2, r2, r0
+ bl memset /* clear bss */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 /* flush icache */
+ add lr, r5, r4 /* adjust return address to new location */
+ pop {r4, r5}
+ mov pc, lr
+ENDPROC(setup_c)
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 0467dfe832..609aedb39c 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -174,12 +174,11 @@ static void barebox_uncompress(void *compressed_start, unsigned int len)
*/
void __naked board_init_lowlevel_return(void)
{
- uint32_t r, offset;
+ uint32_t offset;
uint32_t pg_start, pg_end, pg_len;
/* Setup the stack */
- r = STACK_BASE + STACK_SIZE - 16;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 16);
/* Get offset between linked address and runtime address */
offset = get_runtime_offset();
@@ -188,43 +187,16 @@ void __naked board_init_lowlevel_return(void)
pg_end = (uint32_t)&input_data_end - offset;
pg_len = pg_end - pg_start;
- if (IS_ENABLED(CONFIG_PBL_FORCE_PIGGYDATA_COPY))
- goto copy_piggy_link;
+ if (offset && (IS_ENABLED(CONFIG_PBL_FORCE_PIGGYDATA_COPY) ||
+ region_overlap(pg_start, pg_len, TEXT_BASE, pg_len * 4))) {
+ /*
+ * copy piggydata binary to its link address
+ */
+ memcpy(&input_data, (void *)pg_start, pg_len);
+ pg_start = (uint32_t)&input_data;
+ }
- /*
- * Check if the piggydata binary will be overwritten
- * by the uncompressed binary or by the pbl relocation
- */
- if (!offset ||
- !((pg_start >= TEXT_BASE && pg_start < TEXT_BASE + pg_len * 4) ||
- ((uint32_t)_text >= pg_start && (uint32_t)_text <= pg_end)))
- goto copy_link;
-
-copy_piggy_link:
- /*
- * copy piggydata binary to its link address
- */
- memcpy(&input_data, (void *)pg_start, pg_len);
- pg_start = (uint32_t)&input_data;
-
-copy_link:
- /* relocate to link address if necessary */
- if (offset)
- memcpy((void *)_text, (void *)(_text - offset),
- __bss_start - _text);
-
- /* clear bss */
- memset(__bss_start, 0, __bss_stop - __bss_start);
-
- flush_icache();
+ setup_c();
- r = (unsigned int)&barebox_uncompress;
- /* call barebox_uncompress with its absolute address */
- __asm__ __volatile__(
- "mov r0, %1\n"
- "mov r1, %2\n"
- "mov pc, %0\n"
- :
- : "r"(r), "r"(pg_start), "r"(pg_len)
- : "r0", "r1");
+ barebox_uncompress((void *)pg_start, pg_len);
}
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 867626758d..793445a828 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -24,32 +24,19 @@
#include <asm-generic/memory_layout.h>
#include <asm/sections.h>
#include <asm/cache.h>
+#include <memory.h>
-#ifdef CONFIG_PBL_IMAGE
/*
* First function in the uncompressed image. We get here from
* the pbl.
*/
void __naked __section(.text_entry) start(void)
{
- u32 r;
-
- /* Setup the stack */
- r = STACK_BASE + STACK_SIZE - 16;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
- /* clear bss */
- memset(__bss_start, 0, __bss_stop - __bss_start);
-
- start_barebox();
-}
+#ifdef CONFIG_PBL_IMAGE
+ board_init_lowlevel_return();
#else
-
-/*
- * First function in the image without pbl support
- */
-void __naked __section(.text_entry) start(void)
-{
barebox_arm_head();
+#endif
}
/*
@@ -70,27 +57,9 @@ void __naked __bare_init reset(void)
*/
void __naked board_init_lowlevel_return(void)
{
- uint32_t r, offset;
-
- /* Setup the stack */
- r = STACK_BASE + STACK_SIZE - 16;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
-
- /* Get offset between linked address and runtime address */
- offset = get_runtime_offset();
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 16);
- /* relocate to link address if necessary */
- if (offset)
- memcpy((void *)_text, (void *)(_text - offset),
- __bss_start - _text);
+ setup_c();
- /* clear bss */
- memset(__bss_start, 0, __bss_stop - __bss_start);
-
- flush_icache();
-
- /* call start_barebox with its absolute address */
- r = (unsigned int)&start_barebox;
- __asm__ __volatile__("mov pc, %0" : : "r"(r));
+ start_barebox();
}
-#endif
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 9e17b4f5fb..993130df2d 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -38,4 +38,6 @@ void board_init_lowlevel(void);
void board_init_lowlevel_return(void);
uint32_t get_runtime_offset(void);
+void setup_c(void);
+
#endif /* _BAREBOX_ARM_H_ */
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index ff797493f7..d5877ffc44 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -6,4 +6,6 @@ static inline void flush_icache(void)
asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
}
+int arm_set_cache_functions(void);
+
#endif
diff --git a/arch/arm/include/asm/common.h b/arch/arm/include/asm/common.h
index f3a87c81c9..133bb8e1f6 100644
--- a/arch/arm/include/asm/common.h
+++ b/arch/arm/include/asm/common.h
@@ -16,4 +16,9 @@ static inline unsigned long get_pc(void)
return pc;
}
+static inline void arm_setup_stack(unsigned long top)
+{
+ __asm__ __volatile__("mov sp, %0" : : "r"(top));
+}
+
#endif /* __ASM_ARM_COMMON_H */
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
new file mode 100644
index 0000000000..f39939bd44
--- /dev/null
+++ b/arch/arm/include/asm/cputype.h
@@ -0,0 +1,100 @@
+#ifndef __ASM_ARM_CPUTYPE_H
+#define __ASM_ARM_CPUTYPE_H
+
+#include <linux/stringify.h>
+#include <linux/kernel.h>
+
+#define CPUID_ID 0
+#define CPUID_CACHETYPE 1
+#define CPUID_TCM 2
+#define CPUID_TLBTYPE 3
+#define CPUID_MPIDR 5
+
+#define CPUID_EXT_PFR0 "c1, 0"
+#define CPUID_EXT_PFR1 "c1, 1"
+#define CPUID_EXT_DFR0 "c1, 2"
+#define CPUID_EXT_AFR0 "c1, 3"
+#define CPUID_EXT_MMFR0 "c1, 4"
+#define CPUID_EXT_MMFR1 "c1, 5"
+#define CPUID_EXT_MMFR2 "c1, 6"
+#define CPUID_EXT_MMFR3 "c1, 7"
+#define CPUID_EXT_ISAR0 "c2, 0"
+#define CPUID_EXT_ISAR1 "c2, 1"
+#define CPUID_EXT_ISAR2 "c2, 2"
+#define CPUID_EXT_ISAR3 "c2, 3"
+#define CPUID_EXT_ISAR4 "c2, 4"
+#define CPUID_EXT_ISAR5 "c2, 5"
+
+extern unsigned int processor_id;
+
+#define read_cpuid(reg) \
+ ({ \
+ unsigned int __val; \
+ asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
+ : "=r" (__val) \
+ : \
+ : "cc"); \
+ __val; \
+ })
+#define read_cpuid_ext(ext_reg) \
+ ({ \
+ unsigned int __val; \
+ asm("mrc p15, 0, %0, c0, " ext_reg \
+ : "=r" (__val) \
+ : \
+ : "cc"); \
+ __val; \
+ })
+
+/*
+ * The CPU ID never changes at run time, so we might as well tell the
+ * compiler that it's constant. Use this function to read the CPU ID
+ * rather than directly reading processor_id or read_cpuid() directly.
+ */
+static inline unsigned int __attribute_const__ read_cpuid_id(void)
+{
+ return read_cpuid(CPUID_ID);
+}
+
+static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
+{
+ return read_cpuid(CPUID_CACHETYPE);
+}
+
+static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
+{
+ return read_cpuid(CPUID_TCM);
+}
+
+static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
+{
+ return read_cpuid(CPUID_MPIDR);
+}
+
+/*
+ * Intel's XScale3 core supports some v6 features (supersections, L2)
+ * but advertises itself as v5 as it does not support the v6 ISA. For
+ * this reason, we need a way to explicitly test for this type of CPU.
+ */
+#ifndef CONFIG_CPU_XSC3
+#define cpu_is_xsc3() 0
+#else
+static inline int cpu_is_xsc3(void)
+{
+ unsigned int id;
+ id = read_cpuid_id() & 0xffffe000;
+ /* It covers both Intel ID and Marvell ID */
+ if ((id == 0x69056000) || (id == 0x56056000))
+ return 1;
+
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
+#define cpu_is_xscale() 0
+#else
+#define cpu_is_xscale() 1
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index b38436930d..022d365b24 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -23,25 +23,30 @@
/*
* PSR bits
*/
-#define USR26_MODE 0x00
-#define FIQ26_MODE 0x01
-#define IRQ26_MODE 0x02
-#define SVC26_MODE 0x03
-#define USR_MODE 0x10
-#define FIQ_MODE 0x11
-#define IRQ_MODE 0x12
-#define SVC_MODE 0x13
-#define ABT_MODE 0x17
-#define UND_MODE 0x1b
-#define SYSTEM_MODE 0x1f
-#define MODE_MASK 0x1f
-#define T_BIT 0x20
-#define F_BIT 0x40
-#define I_BIT 0x80
-#define CC_V_BIT (1 << 28)
-#define CC_C_BIT (1 << 29)
-#define CC_Z_BIT (1 << 30)
-#define CC_N_BIT (1 << 31)
+#define USR26_MODE 0x00000000
+#define FIQ26_MODE 0x00000001
+#define IRQ26_MODE 0x00000002
+#define SVC26_MODE 0x00000003
+#define USR_MODE 0x00000010
+#define FIQ_MODE 0x00000011
+#define IRQ_MODE 0x00000012
+#define SVC_MODE 0x00000013
+#define ABT_MODE 0x00000017
+#define UND_MODE 0x0000001b
+#define SYSTEM_MODE 0x0000001f
+#define MODE32_BIT 0x00000010
+#define MODE_MASK 0x0000001f
+#define PSR_T_BIT 0x00000020
+#define PSR_F_BIT 0x00000040
+#define PSR_I_BIT 0x00000080
+#define PSR_A_BIT 0x00000100
+#define PSR_E_BIT 0x00000200
+#define PSR_J_BIT 0x01000000
+#define PSR_Q_BIT 0x08000000
+#define PSR_V_BIT 0x10000000
+#define PSR_C_BIT 0x20000000
+#define PSR_Z_BIT 0x40000000
+#define PSR_N_BIT 0x80000000
#define PCMASK 0
#ifndef __ASSEMBLY__
@@ -79,7 +84,7 @@ struct pt_regs {
#ifdef CONFIG_ARM_THUMB
#define thumb_mode(regs) \
- (((regs)->ARM_cpsr & T_BIT))
+ (((regs)->ARM_cpsr & PSR_T_BIT))
#else
#define thumb_mode(regs) (0)
#endif
@@ -88,13 +93,13 @@ struct pt_regs {
((regs)->ARM_cpsr & MODE_MASK)
#define interrupts_enabled(regs) \
- (!((regs)->ARM_cpsr & I_BIT))
+ (!((regs)->ARM_cpsr & PSR_I_BIT))
#define fast_interrupts_enabled(regs) \
- (!((regs)->ARM_cpsr & F_BIT))
+ (!((regs)->ARM_cpsr & PSR_F_BIT))
#define condition_codes(regs) \
- ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
+ ((regs)->ARM_cpsr & (PSR_V_BIT | PSR_C_BIT | PSR_Z_BIT | PSR_N_BIT))
/* Are the current registers suitable for user mode?
* (used to maintain security in signal handlers)
@@ -102,13 +107,14 @@ struct pt_regs {
static inline int valid_user_regs(struct pt_regs *regs)
{
if ((regs->ARM_cpsr & 0xf) == 0 &&
- (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
+ (regs->ARM_cpsr & (PSR_F_BIT | PSR_I_BIT)) == 0)
return 1;
/*
* Force CPSR to something logical...
*/
- regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
+ regs->ARM_cpsr &= (PSR_V_BIT | PSR_C_BIT | PSR_Z_BIT | PSR_N_BIT |
+ 0x10);
return 0;
}
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
new file mode 100644
index 0000000000..5b676313c0
--- /dev/null
+++ b/arch/arm/include/asm/system_info.h
@@ -0,0 +1,60 @@
+#ifndef __ASM_ARM_SYSTEM_INFO_H
+#define __ASM_ARM_SYSTEM_INFO_H
+
+#define CPU_ARCH_UNKNOWN 0
+#define CPU_ARCH_ARMv3 1
+#define CPU_ARCH_ARMv4 2
+#define CPU_ARCH_ARMv4T 3
+#define CPU_ARCH_ARMv5 4
+#define CPU_ARCH_ARMv5T 5
+#define CPU_ARCH_ARMv5TE 6
+#define CPU_ARCH_ARMv5TEJ 7
+#define CPU_ARCH_ARMv6 8
+#define CPU_ARCH_ARMv7 9
+
+#ifdef CONFIG_CPU_32v4T
+#ifdef ARM_ARCH
+#define ARM_MULTIARCH
+#else
+#define ARM_ARCH CPU_ARCH_ARMv4T
+#endif
+#endif
+
+#ifdef CONFIG_CPU_32v5
+#ifdef ARM_ARCH
+#define ARM_MULTIARCH
+#else
+#define ARM_ARCH CPU_ARCH_ARMv5
+#endif
+#endif
+
+#ifdef CONFIG_CPU_32v6
+#ifdef ARM_ARCH
+#define ARM_MULTIARCH
+#else
+#define ARM_ARCH CPU_ARCH_ARMv6
+#endif
+#endif
+
+#ifdef CONFIG_CPU_32v7
+#ifdef ARM_ARCH
+#define ARM_MULTIARCH
+#else
+#define ARM_ARCH CPU_ARCH_ARMv7
+#endif
+#endif
+
+#ifndef __ASSEMBLY__
+
+#ifdef ARM_MULTIARCH
+extern int __pure cpu_architecture(void);
+#else
+static inline int __pure cpu_architecture(void)
+{
+ return ARM_ARCH;
+}
+#endif
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_ARM_SYSTEM_INFO_H */
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index c5b76ea979..288c0b24a8 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -269,8 +269,9 @@ static int do_bootz_linux(struct image_data *data)
ret = do_bootz_linux_fdt(fd, data);
if (ret && ret != -ENXIO)
- return ret;
+ goto err_out;
+ close(fd);
return __do_bootm_linux(data, swap);
err_out:
@@ -431,6 +432,7 @@ static int do_bootm_aimage(struct image_data *data)
reset_cpu(0);
}
+ close(fd);
return __do_bootm_linux(data, 0);
err_out:
diff --git a/arch/arm/lib/bootz.c b/arch/arm/lib/bootz.c
index f394a6b0eb..f0691277d0 100644
--- a/arch/arm/lib/bootz.c
+++ b/arch/arm/lib/bootz.c
@@ -30,6 +30,7 @@ static int do_bootz(int argc, char *argv[])
u32 end;
int usemap = 0;
struct memory_bank *bank = list_first_entry(&memory_banks, struct memory_bank, list);
+ struct resource *res = NULL;
if (argc != 2)
return COMMAND_ERROR_USAGE;
@@ -83,8 +84,10 @@ static int do_bootz(int argc, char *argv[])
zimage = xmalloc(end);
} else {
zimage = (void *)bank->start + SZ_8M;
- if (bank->start + SZ_8M + end >= MALLOC_BASE) {
- printf("won't overwrite malloc space with image\n");
+ res = request_sdram_region("zimage",
+ bank->start + SZ_8M, end);
+ if (!res) {
+ printf("can't request region for kernel\n");
goto err_out1;
}
}
@@ -94,7 +97,7 @@ static int do_bootz(int argc, char *argv[])
ret = read(fd, zimage + sizeof(*header), end - sizeof(*header));
if (ret < end - sizeof(*header)) {
printf("could not read %s\n", argv[1]);
- goto err_out1;
+ goto err_out2;
}
}
@@ -113,6 +116,9 @@ static int do_bootz(int argc, char *argv[])
return 0;
+err_out2:
+ if (res)
+ release_sdram_region(res);
err_out1:
free(zimage);
err_out:
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 30225fae97..b3f18850bc 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -3,6 +3,7 @@ if ARCH_AT91
config ARCH_TEXT_BASE
hex
default 0x73f00000 if ARCH_AT91SAM9G45
+ default 0x26f00000 if ARCH_AT91SAM9X5
default 0x23f00000
config BOARDINFO
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 8cb2f57751..1a2d0fdaba 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -18,6 +18,7 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/at91rm9200_mc.h>
+#include <i2c/i2c-gpio.h>
#include <sizes.h>
#include "generic.h"
@@ -154,6 +155,33 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
+#if defined(CONFIG_I2C_GPIO)
+static struct i2c_gpio_platform_data pdata_i2c = {
+ .sda_pin = AT91_PIN_PA25,
+ .sda_is_open_drain = 1,
+ .scl_pin = AT91_PIN_PA26,
+ .scl_is_open_drain = 1,
+ .udelay = 5, /* ~100 kHz */
+};
+
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+ struct i2c_gpio_platform_data *pdata = &pdata_i2c;
+
+ i2c_register_board_info(0, devices, nr_devices);
+
+ at91_set_GPIO_periph(pdata->sda_pin, 1); /* TWD (SDA) */
+ at91_set_multi_drive(pdata->sda_pin, 1);
+
+ at91_set_GPIO_periph(pdata->scl_pin, 1); /* TWCK (SCL) */
+ at91_set_multi_drive(pdata->scl_pin, 1);
+
+ add_generic_device_res("i2c-gpio", 0, NULL, 0, pdata);
+}
+#else
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
/* --------------------------------------------------------------------
* SPI
* -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 9c9534eccf..7450ec11ae 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -20,6 +20,7 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/cpu.h>
+#include <i2c/i2c-gpio.h>
#include "generic.h"
@@ -155,6 +156,37 @@ void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
/* --------------------------------------------------------------------
+ * TWI (i2c)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_I2C_GPIO)
+static struct i2c_gpio_platform_data pdata_i2c = {
+ .sda_pin = AT91_PIN_PA23,
+ .sda_is_open_drain = 1,
+ .scl_pin = AT91_PIN_PA24,
+ .scl_is_open_drain = 1,
+ .udelay = 5, /* ~100 kHz */
+};
+
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+ struct i2c_gpio_platform_data *pdata = &pdata_i2c;
+
+ i2c_register_board_info(0, devices, nr_devices);
+
+ at91_set_GPIO_periph(pdata->sda_pin, 1); /* TWD (SDA) */
+ at91_set_multi_drive(pdata->sda_pin, 1);
+
+ at91_set_GPIO_periph(pdata->scl_pin, 1); /* TWCK (SCL) */
+ at91_set_multi_drive(pdata->scl_pin, 1);
+
+ add_generic_device_res("i2c-gpio", 0, NULL, 0, pdata);
+}
+#else
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
+/* --------------------------------------------------------------------
* SPI
* -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 0091e2dbe9..68d75c3fad 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -20,6 +20,7 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/cpu.h>
+#include <i2c/i2c-gpio.h>
#include "generic.h"
@@ -107,6 +108,36 @@ void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
/* --------------------------------------------------------------------
+ * TWI (i2c)
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_I2C_GPIO)
+static struct i2c_gpio_platform_data pdata_i2c = {
+ .sda_pin = AT91_PIN_PA7,
+ .sda_is_open_drain = 1,
+ .scl_pin = AT91_PIN_PA8,
+ .scl_is_open_drain = 1,
+ .udelay = 5, /* ~100 kHz */
+};
+
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+ struct i2c_gpio_platform_data *pdata = &pdata_i2c;
+
+ i2c_register_board_info(0, devices, nr_devices);
+
+ at91_set_GPIO_periph(pdata->sda_pin, 1); /* TWD (SDA) */
+ at91_set_multi_drive(pdata->sda_pin, 1);
+
+ at91_set_GPIO_periph(pdata->scl_pin, 1); /* TWCK (SCL) */
+ at91_set_multi_drive(pdata->scl_pin, 1);
+
+ add_generic_device_res("i2c-gpio", 0, NULL, 0, pdata);
+}
+#else
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
+/* --------------------------------------------------------------------
* SPI
* -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index e6864802b7..deffc27b1c 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -19,6 +19,7 @@
#include <mach/board.h>
#include <mach/gpio.h>
#include <mach/io.h>
+#include <i2c/i2c-gpio.h>
#include "generic.h"
@@ -157,6 +158,36 @@ void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
/* --------------------------------------------------------------------
+ * TWI (i2c)
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_I2C_GPIO)
+static struct i2c_gpio_platform_data pdata_i2c = {
+ .sda_pin = AT91_PIN_PB4,
+ .sda_is_open_drain = 1,
+ .scl_pin = AT91_PIN_PB5,
+ .scl_is_open_drain = 1,
+ .udelay = 5, /* ~100 kHz */
+};
+
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+ struct i2c_gpio_platform_data *pdata = &pdata_i2c;
+
+ i2c_register_board_info(0, devices, nr_devices);
+
+ at91_set_GPIO_periph(pdata->sda_pin, 1); /* TWD (SDA) */
+ at91_set_multi_drive(pdata->sda_pin, 1);
+
+ at91_set_GPIO_periph(pdata->scl_pin, 1); /* TWCK (SCL) */
+ at91_set_multi_drive(pdata->scl_pin, 1);
+
+ add_generic_device_res("i2c-gpio", 0, NULL, 0, pdata);
+}
+#else
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
+/* --------------------------------------------------------------------
* SPI
* -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 22b455e1a9..35cd2e722b 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -18,6 +18,7 @@
#include <mach/board.h>
#include <mach/gpio.h>
#include <mach/io.h>
+#include <i2c/i2c-gpio.h>
#include "generic.h"
@@ -132,6 +133,55 @@ void at91_add_device_nand(struct atmel_nand_data *data)
void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
+/* --------------------------------------------------------------------
+ * TWI (i2c)
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+static struct i2c_gpio_platform_data pdata_i2c0 = {
+ .sda_pin = AT91_PIN_PA20,
+ .sda_is_open_drain = 1,
+ .scl_pin = AT91_PIN_PA21,
+ .scl_is_open_drain = 1,
+ .udelay = 5, /* ~100 kHz */
+};
+
+static struct i2c_gpio_platform_data pdata_i2c1 = {
+ .sda_pin = AT91_PIN_PB10,
+ .sda_is_open_drain = 1,
+ .scl_pin = AT91_PIN_PB11,
+ .scl_is_open_drain = 1,
+ .udelay = 5, /* ~100 kHz */
+};
+
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+ struct i2c_gpio_platform_data *pdata = &pdata_i2c;
+
+ i2c_register_board_info(i2c_id, devices, nr_devices);
+
+ switch (i2c_id) {
+ case 0;
+ pdata = &pdata_i2c0;
+ break;
+ case 1;
+ pdata = &pdata_i2c1;
+ break;
+ default:
+ return;
+ }
+
+ at91_set_GPIO_periph(pdata->sda_pin, 1); /* TWD (SDA) */
+ at91_set_multi_drive(pdata->sda_pin, 1);
+
+ at91_set_GPIO_periph(pdata->scl_pin, 1); /* TWCK (SCL) */
+ at91_set_multi_drive(pdata->scl_pin, 1);
+
+ add_generic_device_res("i2c-gpio", i2c_id, NULL, 0, pdata);
+}
+#else
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
resource_size_t __init at91_configure_dbgu(void)
{
at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index c256989780..7c7d997260 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -205,6 +205,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("macb_clk", "macb0", &macb0_clk),
CLKDEV_CON_DEV_ID("macb_clk", "macb1", &macb1_clk),
CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
+ CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk),
+ CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index 26a380d2ce..14fcb1e6af 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -19,6 +19,7 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include <mach/cpu.h>
+#include <i2c/i2c-gpio.h>
#include "generic.h"
@@ -122,6 +123,68 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data)
void at91_add_device_eth(int id, struct at91_ether_platform_data *data) {}
#endif
+#if defined(CONFIG_MCI_ATMEL)
+/* Consider only one slot : slot 0 */
+void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
+{
+ resource_size_t start = ~0;
+
+ if (!data)
+ return;
+
+ /* Must have at least one usable slot */
+ if (!data->bus_width)
+ return;
+
+ /* input/irq */
+ if (data->detect_pin) {
+ at91_set_gpio_input(data->detect_pin, 1);
+ at91_set_deglitch(data->detect_pin, 1);
+ }
+ if (data->wp_pin)
+ at91_set_gpio_input(data->wp_pin, 1);
+
+ if (mmc_id == 0) { /* MCI0 */
+ start = AT91SAM9X5_BASE_MCI0;
+
+ /* CLK */
+ at91_set_A_periph(AT91_PIN_PA17, 0);
+
+ /* CMD */
+ at91_set_A_periph(AT91_PIN_PA16, 1);
+
+ /* DAT0, maybe DAT1..DAT3 */
+ at91_set_A_periph(AT91_PIN_PA15, 1);
+ if (data->bus_width == 4) {
+ at91_set_A_periph(AT91_PIN_PA18, 1);
+ at91_set_A_periph(AT91_PIN_PA19, 1);
+ at91_set_A_periph(AT91_PIN_PA20, 1);
+ }
+ } else { /* MCI1 */
+ start = AT91SAM9X5_BASE_MCI1;
+
+ /* CLK */
+ at91_set_B_periph(AT91_PIN_PA13, 0);
+
+ /* CMD */
+ at91_set_B_periph(AT91_PIN_PA12, 1);
+
+ /* DAT0, maybe DAT1..DAT3 */
+ at91_set_B_periph(AT91_PIN_PA11, 1);
+ if (data->bus_width == 4) {
+ at91_set_B_periph(AT91_PIN_PA2, 1);
+ at91_set_B_periph(AT91_PIN_PA3, 1);
+ at91_set_B_periph(AT91_PIN_PA4, 1);
+ }
+ }
+
+ add_generic_device("atmel_mci", mmc_id, NULL, start, SZ_16K,
+ IORESOURCE_MEM, data);
+}
+#else
+void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}
+#endif
+
/* --------------------------------------------------------------------
* NAND / SmartMedia
* -------------------------------------------------------------------- */
@@ -169,6 +232,125 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
+#if defined(CONFIG_I2C_GPIO)
+static struct i2c_gpio_platform_data pdata_i2c0 = {
+ .sda_pin = AT91_PIN_PA30,
+ .sda_is_open_drain = 1,
+ .scl_pin = AT91_PIN_PA31,
+ .scl_is_open_drain = 1,
+ .udelay = 5, /* ~100 kHz */
+};
+
+static struct i2c_gpio_platform_data pdata_i2c1 = {
+ .sda_pin = AT91_PIN_PC0,
+ .sda_is_open_drain = 1,
+ .scl_pin = AT91_PIN_PC1,
+ .scl_is_open_drain = 1,
+ .udelay = 5, /* ~100 kHz */
+};
+
+static struct i2c_gpio_platform_data pdata_i2c2 = {
+ .sda_pin = AT91_PIN_PB4,
+ .sda_is_open_drain = 1,
+ .scl_pin = AT91_PIN_PB5,
+ .scl_is_open_drain = 1,
+ .udelay = 5, /* ~100 kHz */
+};
+
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+ struct i2c_gpio_platform_data *pdata;
+
+ i2c_register_board_info(i2c_id, devices, nr_devices);
+
+ switch (i2c_id) {
+ case 0:
+ pdata = &pdata_i2c0;
+ break;
+ case 1:
+ pdata = &pdata_i2c1;
+ break;
+ case 2:
+ pdata = &pdata_i2c2;
+ break;
+ default:
+ return;
+ }
+
+ at91_set_GPIO_periph(pdata->sda_pin, 1); /* TWD (SDA) */
+ at91_set_multi_drive(pdata->sda_pin, 1);
+
+ at91_set_GPIO_periph(pdata->scl_pin, 1); /* TWCK (SCL) */
+ at91_set_multi_drive(pdata->scl_pin, 1);
+
+ add_generic_device_res("i2c-gpio", i2c_id, NULL, 0, pdata);
+}
+#else
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
+/* --------------------------------------------------------------------
+ * SPI
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_DRIVER_SPI_ATMEL)
+static unsigned spi0_standard_cs[4] = { AT91_PIN_PA14, AT91_PIN_PA7, AT91_PIN_PA1, AT91_PIN_PB3 };
+
+static unsigned spi1_standard_cs[4] = { AT91_PIN_PA8, AT91_PIN_PA0, AT91_PIN_PA31, AT91_PIN_PA30 };
+
+static struct at91_spi_platform_data spi_pdata[] = {
+ [0] = {
+ .chipselect = spi0_standard_cs,
+ .num_chipselect = ARRAY_SIZE(spi0_standard_cs),
+ },
+ [1] = {
+ .chipselect = spi1_standard_cs,
+ .num_chipselect = ARRAY_SIZE(spi1_standard_cs),
+ },
+};
+
+void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata)
+{
+ int i;
+ int cs_pin;
+ resource_size_t start = ~0;
+
+ BUG_ON(spi_id > 1);
+
+ if (!pdata)
+ pdata = &spi_pdata[spi_id];
+
+ for (i = 0; i < pdata->num_chipselect; i++) {
+ cs_pin = pdata->chipselect[i];
+
+ /* enable chip-select pin */
+ if (cs_pin > 0)
+ at91_set_gpio_output(cs_pin, 1);
+ }
+
+ /* Configure SPI bus(es) */
+ switch (spi_id) {
+ case 0:
+ start = AT91SAM9X5_BASE_SPI0;
+ at91_set_A_periph(AT91_PIN_PA11, 0); /* SPI0_MISO */
+ at91_set_A_periph(AT91_PIN_PA12, 0); /* SPI0_MOSI */
+ at91_set_A_periph(AT91_PIN_PA13, 0); /* SPI0_SPCK */
+ break;
+ case 1:
+ start = AT91SAM9X5_BASE_SPI1;
+ at91_set_B_periph(AT91_PIN_PA21, 0); /* SPI1_MISO */
+ at91_set_B_periph(AT91_PIN_PA22, 0); /* SPI1_MOSI */
+ at91_set_B_periph(AT91_PIN_PA23, 0); /* SPI1_SPCK */
+ break;
+ }
+
+ add_generic_device("atmel_spi", spi_id, NULL, start, SZ_16K,
+ IORESOURCE_MEM, pdata);
+}
+#else
+void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {}
+#endif
+
/* --------------------------------------------------------------------
* UART
* -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 670c73d8d8..1ce07628e9 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -21,6 +21,7 @@
#include <mach/hardware.h>
#include <sizes.h>
#include <net.h>
+#include <i2c/i2c.h>
#include <spi/spi.h>
#include <linux/mtd/mtd.h>
@@ -71,6 +72,8 @@ struct at91_ether_platform_data {
void at91_add_device_eth(int id, struct at91_ether_platform_data *data);
+void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
+
/* SDRAM */
void at91_add_device_sdram(u32 size);
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 3533bf9e3f..fa695a617c 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -22,6 +22,17 @@
/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
+#define ARCH_NR_GPIOS 256
+
+static inline int gpio_is_valid(int gpio)
+{
+ if (gpio < 1)
+ return 0;
+ if (gpio < ARCH_NR_GPIOS)
+ return 1;
+ return 0;
+}
+
#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig
new file mode 100644
index 0000000000..9d97aea2b8
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Kconfig
@@ -0,0 +1,18 @@
+if ARCH_BCM2835
+
+config ARCH_TEXT_BASE
+ hex
+ default 0x04000000 if MACH_RPI
+
+config BOARDINFO
+ default "RaspberryPi (BCM2835/ARM1176JZF-S)" if MACH_RPI
+
+choice
+ prompt "Broadcom Board type"
+
+config MACH_RPI
+ bool "RaspberryPi (BCM2835/ARM1176JZF-S)"
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-bcm2835/Makefile b/arch/arm/mach-bcm2835/Makefile
new file mode 100644
index 0000000000..820eb10ac2
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Makefile
@@ -0,0 +1 @@
+obj-y += core.o
diff --git a/arch/arm/mach-bcm2835/core.c b/arch/arm/mach-bcm2835/core.c
new file mode 100644
index 0000000000..b0fec8b008
--- /dev/null
+++ b/arch/arm/mach-bcm2835/core.c
@@ -0,0 +1,101 @@
+/*
+ * Author: Carlo Caione <carlo@carlocaione.org>
+ *
+ * Based on mach-nomadik
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <io.h>
+#include <asm/armlinux.h>
+#include <sizes.h>
+
+#include <mach/platform.h>
+#include <mach/wd.h>
+#include <mach/core.h>
+#include <linux/amba/bus.h>
+
+enum brcm_clks {
+ dummy, clk_ref_3, clk_ref_1, clks_max
+};
+
+static struct clk *clks[clks_max];
+
+static int bcm2835_clk_init(void)
+{
+ int ret;
+
+ clks[dummy] = clk_fixed("dummy", 0);
+ clks[clk_ref_3] = clk_fixed("ref3", 3 * 1000 * 1000);
+ clks[clk_ref_1] = clk_fixed("ref1", 1 * 1000 * 1000);
+
+ ret = clk_register_clkdev(clks[dummy], "apb_pclk", NULL);
+ if (ret)
+ goto clk_err;
+
+ ret = clk_register_clkdev(clks[clk_ref_3], NULL, "uart0-pl0110");
+ if (ret)
+ goto clk_err;
+
+ ret = clk_register_clkdev(clks[clk_ref_1], NULL, "bcm2835-cs");
+ if (ret)
+ goto clk_err;
+
+ return 0;
+
+clk_err:
+ return ret;
+
+}
+postcore_initcall(bcm2835_clk_init);
+
+static int bcm2835_dev_init(void)
+{
+ add_generic_device("bcm2835-gpio", 0, NULL, BCM2835_GPIO_BASE, 0xB0, IORESOURCE_MEM, NULL);
+ add_generic_device("bcm2835-cs", DEVICE_ID_SINGLE, NULL, BCM2835_ST_BASE, 0x1C, IORESOURCE_MEM, NULL);
+ return 0;
+}
+coredevice_initcall(bcm2835_dev_init);
+
+void bcm2835_register_uart(void)
+{
+ amba_apb_device_add(NULL, "uart0-pl011", 0, BCM2835_UART0_BASE, 4096, NULL, 0);
+}
+
+void bcm2835_add_device_sdram(u32 size)
+{
+ if (!size)
+ size = get_ram_size((ulong *) BCM2835_SDRAM_BASE, SZ_128M);
+
+ arm_add_mem_device("ram0", BCM2835_SDRAM_BASE, size);
+}
+#define RESET_TIMEOUT 10
+
+void __noreturn reset_cpu (unsigned long addr)
+{
+ uint32_t rstc;
+
+ rstc = readl(PM_RSTC);
+ rstc &= ~PM_RSTC_WRCFG_SET;
+ rstc |= PM_RSTC_WRCFG_FULL_RESET;
+ writel(PM_PASSWORD | RESET_TIMEOUT, PM_WDOG);
+ writel(PM_PASSWORD | rstc, PM_RSTC);
+}
+EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/arm/mach-bcm2835/include/mach/clkdev.h b/arch/arm/mach-bcm2835/include/mach/clkdev.h
new file mode 100644
index 0000000000..04b37a8980
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/boards/at91sam9260ek/lowlevel_init.S b/arch/arm/mach-bcm2835/include/mach/core.h
index 043892122c..9379af209b 100644
--- a/arch/arm/boards/at91sam9260ek/lowlevel_init.S
+++ b/arch/arm/mach-bcm2835/include/mach/core.h
@@ -1,9 +1,5 @@
/*
- * Board specific setup info
- *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * Copyright (C) 2009 Carlo Caione <carlo@carlocaione.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -17,9 +13,10 @@
*
*/
-#include <asm/barebox-arm-head.h>
+#ifndef __BCM2835_CORE_H__
+#define __BCM2835_CORE_H__
+
+void bcm2835_register_uart(void);
+void bcm2835_add_device_sdram(u32 size);
-.globl reset
-reset:
- common_reset r0
- b board_init_lowlevel_return
+#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/gpio.h b/arch/arm/mach-bcm2835/include/mach/gpio.h
new file mode 100644
index 0000000000..306ab4c9f2
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/gpio.h
@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-bcm2835/include/mach/platform.h b/arch/arm/mach-bcm2835/include/mach/platform.h
new file mode 100644
index 0000000000..e55085a75b
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/platform.h
@@ -0,0 +1,50 @@
+/*
+ * Extract from arch/arm/mach-bcm2708/include/mach/platform.h
+ *
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _BCM2835_PLATFORM_H
+#define _BCM2835_PLATFORM_H
+
+/*
+ * SDRAM
+ */
+#define BCM2835_SDRAM_BASE 0x00000000
+
+/*
+ * Definitions and addresses for the ARM CONTROL logic
+ * This file is manually generated.
+ */
+
+#define BCM2835_PERI_BASE 0x20000000
+#define BCM2835_ST_BASE (BCM2835_PERI_BASE + 0x3000) /* System Timer */
+#define BCM2835_DMA_BASE (BCM2835_PERI_BASE + 0x7000) /* DMA controller */
+#define BCM2835_ARM_BASE (BCM2835_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
+#define BCM2835_PM_BASE (BCM2835_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
+#define BCM2835_GPIO_BASE (BCM2835_PERI_BASE + 0x200000) /* GPIO */
+#define BCM2835_UART0_BASE (BCM2835_PERI_BASE + 0x201000) /* Uart 0 */
+#define BCM2835_MMCI0_BASE (BCM2835_PERI_BASE + 0x202000) /* MMC interface */
+#define BCM2835_SPI0_BASE (BCM2835_PERI_BASE + 0x204000) /* SPI0 */
+#define BCM2835_BSC0_BASE (BCM2835_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
+#define BCM2835_UART1_BASE (BCM2835_PERI_BASE + 0x215000) /* Uart 1 */
+#define BCM2835_EMMC_BASE (BCM2835_PERI_BASE + 0x300000) /* eMMC interface */
+#define BCM2835_SMI_BASE (BCM2835_PERI_BASE + 0x600000) /* SMI */
+#define BCM2835_BSC1_BASE (BCM2835_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
+#define BCM2835_USB_BASE (BCM2835_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
+#define BCM2835_MCORE_BASE (BCM2835_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
+
+#endif
+
+/* END */
diff --git a/arch/arm/mach-bcm2835/include/mach/wd.h b/arch/arm/mach-bcm2835/include/mach/wd.h
new file mode 100644
index 0000000000..ad8b762d96
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/wd.h
@@ -0,0 +1,47 @@
+/*
+ * Extract from arch/arm/mach-bcm2708/include/mach/platform.h
+ *
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _WD_H
+#define _WD_H
+
+/*
+ * Watchdog
+ */
+#define PM_RSTC (BCM2835_PM_BASE+0x1c)
+#define PM_RSTS (BCM2835_PM_BASE+0x20)
+#define PM_WDOG (BCM2835_PM_BASE+0x24)
+
+#define PM_WDOG_RESET 0000000000
+#define PM_PASSWORD 0x5a000000
+#define PM_WDOG_TIME_SET 0x000fffff
+#define PM_RSTC_WRCFG_CLR 0xffffffcf
+#define PM_RSTC_WRCFG_SET 0x00000030
+#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
+#define PM_RSTC_RESET 0x00000102
+
+#define PM_RSTS_HADPOR_SET 0x00001000
+#define PM_RSTS_HADSRH_SET 0x00000400
+#define PM_RSTS_HADSRF_SET 0x00000200
+#define PM_RSTS_HADSRQ_SET 0x00000100
+#define PM_RSTS_HADWRH_SET 0x00000040
+#define PM_RSTS_HADWRF_SET 0x00000020
+#define PM_RSTS_HADWRQ_SET 0x00000010
+#define PM_RSTS_HADDRH_SET 0x00000004
+#define PM_RSTS_HADDRF_SET 0x00000002
+#define PM_RSTS_HADDRQ_SET 0x00000001
+
+#endif
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
new file mode 100644
index 0000000000..469ca72f12
--- /dev/null
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -0,0 +1,26 @@
+if ARCH_CLPS711X
+
+choice
+ prompt "Cirrus Logic EP711x/EP721x/EP731x Board Type"
+
+config MACH_CLEP7212
+ bool "Cirrus Logic CLEP7212"
+ select MACH_HAS_LOWLEVEL_INIT
+ select MACH_DO_LOWLEVEL_INIT
+ help
+ Boards based on the Cirrus Logic 7212/7312 CPU.
+
+endchoice
+
+config BOARDINFO
+ default "Cirrus Logic CLEP7212" if MACH_CLEP7212
+
+config ARCH_TEXT_BASE
+ hex
+ default 0xc0780000 if MACH_CLEP7212
+
+config BAREBOX_MAX_IMAGE_SIZE
+ hex
+ default 0x00080000 if MACH_CLEP7212
+
+endif
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
new file mode 100644
index 0000000000..41012bc016
--- /dev/null
+++ b/arch/arm/mach-clps711x/Makefile
@@ -0,0 +1 @@
+obj-y += clock.o devices.o reset.o
diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c
new file mode 100644
index 0000000000..5cafba98e9
--- /dev/null
+++ b/arch/arm/mach-clps711x/clock.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <asm/io.h>
+#include <linux/clkdev.h>
+
+#include <mach/clps711x.h>
+
+struct clk {
+ unsigned long rate;
+};
+
+static struct clk uart_clk, bus_clk;
+
+uint64_t clocksource_read(void)
+{
+ return ~readw(TC2D);
+}
+
+static struct clocksource cs = {
+ .read = clocksource_read,
+ .mask = CLOCKSOURCE_MASK(16),
+};
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+int clk_enable(struct clk *clk)
+{
+ /* Do nothing */
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+ /* Do nothing */
+}
+EXPORT_SYMBOL(clk_disable);
+
+static int clocks_init(void)
+{
+ int osc, ext, pll, cpu, timer;
+ u32 tmp;
+
+ osc = 3686400;
+ ext = 13000000;
+
+ tmp = readl(PLLR) >> 24;
+ if (tmp)
+ pll = (osc * tmp) / 2;
+ else
+ pll = 73728000; /* Default value for old CPUs */
+
+ tmp = readl(SYSFLG2);
+ if (tmp & SYSFLG2_CKMODE) {
+ cpu = ext;
+ bus_clk.rate = cpu;
+ } else {
+ cpu = pll;
+ if (cpu >= 36864000)
+ bus_clk.rate = cpu / 2;
+ else
+ bus_clk.rate = 36864000 / 2;
+ }
+
+ uart_clk.rate = bus_clk.rate / 10;
+
+ if (tmp & SYSFLG2_CKMODE) {
+ tmp = readw(SYSCON2);
+ if (tmp & SYSCON2_OSTB)
+ timer = ext / 26;
+ else
+ timer = 541440;
+ } else
+ timer = cpu / 144;
+
+ tmp = readl(SYSCON1);
+ tmp &= ~SYSCON1_TC2M; /* Free running mode */
+ tmp |= SYSCON1_TC2S; /* High frequency source */
+ writel(tmp, SYSCON1);
+
+ clocks_calc_mult_shift(&cs.mult, &cs.shift, timer, NSEC_PER_SEC, 10);
+
+ return init_clock(&cs);
+}
+core_initcall(clocks_init);
+
+static struct clk_lookup clocks_lookups[] = {
+ CLKDEV_CON_ID("bus", &bus_clk),
+ CLKDEV_DEV_ID("clps711x_serial0", &uart_clk),
+ CLKDEV_DEV_ID("clps711x_serial1", &uart_clk),
+};
+
+static int clkdev_init(void)
+{
+ clkdev_add_table(clocks_lookups, ARRAY_SIZE(clocks_lookups));
+
+ return 0;
+}
+postcore_initcall(clkdev_init);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
new file mode 100644
index 0000000000..08f27d26be
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/io.h>
+
+#include <mach/clps711x.h>
+
+inline void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
+{
+ u32 tmp = readl(addr);
+
+ tmp &= ~(0xff << (bank * 8));
+ tmp |= val << (bank * 8);
+
+ writel(tmp, addr);
+}
+
+void clps711x_setup_memcfg(int bank, u32 val)
+{
+ switch (bank) {
+ case 0 ... 3:
+ _clps711x_setup_memcfg(bank, MEMCFG1, val);
+ break;
+ case 4 ... 7:
+ _clps711x_setup_memcfg(bank - 4, MEMCFG2, val);
+ break;
+ }
+}
+
+static struct resource uart0_resources[] = {
+ {
+ .start = UBRLCR1,
+ .end = UBRLCR1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = SYSCON1,
+ .end = SYSCON1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = SYSFLG1,
+ .end = SYSFLG1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = UARTDR1,
+ .end = UARTDR1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource uart1_resources[] = {
+ {
+ .start = UBRLCR2,
+ .end = UBRLCR2,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = SYSCON2,
+ .end = SYSCON2,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = SYSFLG2,
+ .end = SYSFLG2,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = UARTDR2,
+ .end = UARTDR2,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+void clps711x_add_uart(unsigned int id)
+{
+ switch (id) {
+ case 0:
+ add_generic_device_res("clps711x_serial", 0, uart0_resources,
+ ARRAY_SIZE(uart0_resources), NULL);
+ break;
+ case 1:
+ add_generic_device_res("clps711x_serial", 1, uart1_resources,
+ ARRAY_SIZE(uart1_resources), NULL);
+ break;
+ }
+}
diff --git a/arch/arm/mach-clps711x/include/mach/clkdev.h b/arch/arm/mach-clps711x/include/mach/clkdev.h
new file mode 100644
index 0000000000..9278209017
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
new file mode 100644
index 0000000000..048992a361
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -0,0 +1,284 @@
+/*
+ * Hardware definitions for Cirrus Logic CLPS711X
+ *
+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __MACH_CLPS711X_H
+#define __MACH_CLPS711X_H
+
+#define CS0_BASE (0x00000000)
+#define CS1_BASE (0x10000000)
+#define CS2_BASE (0x20000000)
+#define CS3_BASE (0x30000000)
+#define CS4_BASE (0x40000000)
+#define CS5_BASE (0x50000000)
+#define CS6_BASE (0x60000000)
+#define CS7_BASE (0x70000000)
+#define REGS_BASE (0x80000000)
+#define SDRAM0_BASE (0xc0000000)
+#define SDRAM1_BASE (0xd0000000)
+
+#define PADR (REGS_BASE + 0x0000)
+#define PBDR (REGS_BASE + 0x0001)
+#define PCDR (REGS_BASE + 0x0002)
+#define PDDR (REGS_BASE + 0x0003)
+#define PADDR (REGS_BASE + 0x0040)
+#define PBDDR (REGS_BASE + 0x0041)
+#define PCDDR (REGS_BASE + 0x0042)
+#define PDDDR (REGS_BASE + 0x0043)
+#define PEDR (REGS_BASE + 0x0083)
+#define PEDDR (REGS_BASE + 0x00c3)
+#define SYSCON1 (REGS_BASE + 0x0100)
+#define SYSFLG1 (REGS_BASE + 0x0140)
+#define MEMCFG1 (REGS_BASE + 0x0180)
+#define MEMCFG2 (REGS_BASE + 0x01c0)
+#define DRFPR (REGS_BASE + 0x0200)
+#define INTSR1 (REGS_BASE + 0x0240)
+#define INTMR1 (REGS_BASE + 0x0280)
+#define LCDCON (REGS_BASE + 0x02c0)
+#define TC1D (REGS_BASE + 0x0300)
+#define TC2D (REGS_BASE + 0x0340)
+#define RTCDR (REGS_BASE + 0x0380)
+#define RTCMR (REGS_BASE + 0x03c0)
+#define PMPCON (REGS_BASE + 0x0400)
+#define CODR (REGS_BASE + 0x0440)
+#define UARTDR1 (REGS_BASE + 0x0480)
+#define UBRLCR1 (REGS_BASE + 0x04c0)
+#define SYNCIO (REGS_BASE + 0x0500)
+#define PALLSW (REGS_BASE + 0x0540)
+#define PALMSW (REGS_BASE + 0x0580)
+#define STFCLR (REGS_BASE + 0x05c0)
+#define BLEOI (REGS_BASE + 0x0600)
+#define MCEOI (REGS_BASE + 0x0640)
+#define TEOI (REGS_BASE + 0x0680)
+#define TC1EOI (REGS_BASE + 0x06c0)
+#define TC2EOI (REGS_BASE + 0x0700)
+#define RTCEOI (REGS_BASE + 0x0740)
+#define UMSEOI (REGS_BASE + 0x0780)
+#define COEOI (REGS_BASE + 0x07c0)
+#define HALT (REGS_BASE + 0x0800)
+#define STDBY (REGS_BASE + 0x0840)
+
+#define FBADDR (REGS_BASE + 0x1000)
+#define SYSCON2 (REGS_BASE + 0x1100)
+#define SYSFLG2 (REGS_BASE + 0x1140)
+#define INTSR2 (REGS_BASE + 0x1240)
+#define INTMR2 (REGS_BASE + 0x1280)
+#define UARTDR2 (REGS_BASE + 0x1480)
+#define UBRLCR2 (REGS_BASE + 0x14c0)
+#define SS2DR (REGS_BASE + 0x1500)
+#define SRXEOF (REGS_BASE + 0x1600)
+#define SS2POP (REGS_BASE + 0x16c0)
+#define KBDEOI (REGS_BASE + 0x1700)
+
+#define DAIR (REGS_BASE + 0x2000)
+#define DAIDR0 (REGS_BASE + 0x2040)
+#define DAIDR1 (REGS_BASE + 0x2080)
+#define DAIDR2 (REGS_BASE + 0x20c0)
+#define DAISR (REGS_BASE + 0x2100)
+#define SYSCON3 (REGS_BASE + 0x2200)
+#define INTSR3 (REGS_BASE + 0x2240)
+#define INTMR3 (REGS_BASE + 0x2280)
+#define LEDFLSH (REGS_BASE + 0x22c0)
+#define SDCONF (REGS_BASE + 0x2300)
+#define SDRFPR (REGS_BASE + 0x2340)
+#define UNIQID (REGS_BASE + 0x2440)
+#define DAI64FS (REGS_BASE + 0x2600)
+#define PLLW (REGS_BASE + 0x2610)
+#define PLLR (REGS_BASE + 0xa5a8)
+#define RANDID0 (REGS_BASE + 0x2700)
+#define RANDID1 (REGS_BASE + 0x2704)
+#define RANDID2 (REGS_BASE + 0x2708)
+#define RANDID3 (REGS_BASE + 0x270c)
+
+/* common bits: SYSCON1 / SYSCON2 */
+#define SYSCON_UARTEN (1 << 8)
+
+#define SYSCON1_KBDSCAN(x) ((x) & 15)
+#define SYSCON1_KBDSCANMASK (15)
+#define SYSCON1_TC1M (1 << 4)
+#define SYSCON1_TC1S (1 << 5)
+#define SYSCON1_TC2M (1 << 6)
+#define SYSCON1_TC2S (1 << 7)
+#define SYSCON1_UART1EN SYSCON_UARTEN
+#define SYSCON1_BZTOG (1 << 9)
+#define SYSCON1_BZMOD (1 << 10)
+#define SYSCON1_DBGEN (1 << 11)
+#define SYSCON1_LCDEN (1 << 12)
+#define SYSCON1_CDENTX (1 << 13)
+#define SYSCON1_CDENRX (1 << 14)
+#define SYSCON1_SIREN (1 << 15)
+#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
+#define SYSCON1_ADCKSEL_MASK (3 << 16)
+#define SYSCON1_EXCKEN (1 << 18)
+#define SYSCON1_WAKEDIS (1 << 19)
+#define SYSCON1_IRTXM (1 << 20)
+
+/* common bits: SYSFLG1 / SYSFLG2 */
+#define SYSFLG_UBUSY (1 << 11)
+#define SYSFLG_URXFE (1 << 22)
+#define SYSFLG_UTXFF (1 << 23)
+
+#define SYSFLG1_MCDR (1 << 0)
+#define SYSFLG1_DCDET (1 << 1)
+#define SYSFLG1_WUDR (1 << 2)
+#define SYSFLG1_WUON (1 << 3)
+#define SYSFLG1_CTS (1 << 8)
+#define SYSFLG1_DSR (1 << 9)
+#define SYSFLG1_DCD (1 << 10)
+#define SYSFLG1_UBUSY SYSFLG_UBUSY
+#define SYSFLG1_NBFLG (1 << 12)
+#define SYSFLG1_RSTFLG (1 << 13)
+#define SYSFLG1_PFFLG (1 << 14)
+#define SYSFLG1_CLDFLG (1 << 15)
+#define SYSFLG1_URXFE SYSFLG_URXFE
+#define SYSFLG1_UTXFF SYSFLG_UTXFF
+#define SYSFLG1_CRXFE (1 << 24)
+#define SYSFLG1_CTXFF (1 << 25)
+#define SYSFLG1_SSIBUSY (1 << 26)
+#define SYSFLG1_ID (1 << 29)
+#define SYSFLG1_VERID(x) (((x) >> 30) & 3)
+#define SYSFLG1_VERID_MASK (3 << 30)
+
+#define SYSFLG2_SSRXOF (1 << 0)
+#define SYSFLG2_RESVAL (1 << 1)
+#define SYSFLG2_RESFRM (1 << 2)
+#define SYSFLG2_SS2RXFE (1 << 3)
+#define SYSFLG2_SS2TXFF (1 << 4)
+#define SYSFLG2_SS2TXUF (1 << 5)
+#define SYSFLG2_CKMODE (1 << 6)
+#define SYSFLG2_UBUSY SYSFLG_UBUSY
+#define SYSFLG2_URXFE SYSFLG_URXFE
+#define SYSFLG2_UTXFF SYSFLG_UTXFF
+
+#define LCDCON_GSEN (1 << 30)
+#define LCDCON_GSMD (1 << 31)
+
+#define SYSCON2_SERSEL (1 << 0)
+#define SYSCON2_KBD6 (1 << 1)
+#define SYSCON2_DRAMZ (1 << 2)
+#define SYSCON2_KBWEN (1 << 3)
+#define SYSCON2_SS2TXEN (1 << 4)
+#define SYSCON2_PCCARD1 (1 << 5)
+#define SYSCON2_PCCARD2 (1 << 6)
+#define SYSCON2_SS2RXEN (1 << 7)
+#define SYSCON2_UART2EN SYSCON_UARTEN
+#define SYSCON2_SS2MAEN (1 << 9)
+#define SYSCON2_OSTB (1 << 12)
+#define SYSCON2_CLKENSL (1 << 13)
+#define SYSCON2_BUZFREQ (1 << 14)
+
+/* common bits: UARTDR1 / UARTDR2 */
+#define UARTDR_FRMERR (1 << 8)
+#define UARTDR_PARERR (1 << 9)
+#define UARTDR_OVERR (1 << 10)
+
+/* common bits: UBRLCR1 / UBRLCR2 */
+#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
+#define UBRLCR_BREAK (1 << 12)
+#define UBRLCR_PRTEN (1 << 13)
+#define UBRLCR_EVENPRT (1 << 14)
+#define UBRLCR_XSTOP (1 << 15)
+#define UBRLCR_FIFOEN (1 << 16)
+#define UBRLCR_WRDLEN5 (0 << 17)
+#define UBRLCR_WRDLEN6 (1 << 17)
+#define UBRLCR_WRDLEN7 (2 << 17)
+#define UBRLCR_WRDLEN8 (3 << 17)
+#define UBRLCR_WRDLEN_MASK (3 << 17)
+
+#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8)
+#define SYNCIO_SMCKEN (1 << 13)
+#define SYNCIO_TXFRMEN (1 << 14)
+
+#define DAIR_RESERVED (0x0404)
+#define DAIR_DAIEN (1 << 16)
+#define DAIR_ECS (1 << 17)
+#define DAIR_LCTM (1 << 19)
+#define DAIR_LCRM (1 << 20)
+#define DAIR_RCTM (1 << 21)
+#define DAIR_RCRM (1 << 22)
+#define DAIR_LBM (1 << 23)
+
+#define DAIDR2_FIFOEN (1 << 15)
+#define DAIDR2_FIFOLEFT (0x0d << 16)
+#define DAIDR2_FIFORIGHT (0x11 << 16)
+
+#define DAISR_RCTS (1 << 0)
+#define DAISR_RCRS (1 << 1)
+#define DAISR_LCTS (1 << 2)
+#define DAISR_LCRS (1 << 3)
+#define DAISR_RCTU (1 << 4)
+#define DAISR_RCRO (1 << 5)
+#define DAISR_LCTU (1 << 6)
+#define DAISR_LCRO (1 << 7)
+#define DAISR_RCNF (1 << 8)
+#define DAISR_RCNE (1 << 9)
+#define DAISR_LCNF (1 << 10)
+#define DAISR_LCNE (1 << 11)
+#define DAISR_FIFO (1 << 12)
+
+#define DAI64FS_I2SF64 (1 << 0)
+#define DAI64FS_AUDIOCLKEN (1 << 1)
+#define DAI64FS_AUDIOCLKSRC (1 << 2)
+#define DAI64FS_MCLK256EN (1 << 3)
+#define DAI64FS_LOOPBACK (1 << 5)
+#define DAI64FS_AUDIV_MASK (0x7f)
+#define DAI64FS_AUDIV(x) (((x) & DAI64FS_AUDIV_MASK) << 8)
+
+#define SYSCON3_ADCCON (1 << 0)
+#define SYSCON3_CLKCTL0 (1 << 1)
+#define SYSCON3_CLKCTL1 (1 << 2)
+#define SYSCON3_DAISEL (1 << 3)
+#define SYSCON3_ADCCKNSEN (1 << 4)
+#define SYSCON3_VERSN(x) (((x) >> 5) & 7)
+#define SYSCON3_VERSN_MASK (7 << 5)
+#define SYSCON3_FASTWAKE (1 << 8)
+#define SYSCON3_DAIEN (1 << 9)
+#define SYSCON3_128FS SYSCON3_DAIEN
+#define SYSCON3_ENPD67 (1 << 10)
+
+#define SDCONF_ACTIVE (1 << 10)
+#define SDCONF_CLKCTL (1 << 9)
+#define SDCONF_WIDTH_4 (0 << 7)
+#define SDCONF_WIDTH_8 (1 << 7)
+#define SDCONF_WIDTH_16 (2 << 7)
+#define SDCONF_WIDTH_32 (3 << 7)
+#define SDCONF_SIZE_16 (0 << 5)
+#define SDCONF_SIZE_64 (1 << 5)
+#define SDCONF_SIZE_128 (2 << 5)
+#define SDCONF_SIZE_256 (3 << 5)
+#define SDCONF_CASLAT_2 (2)
+#define SDCONF_CASLAT_3 (3)
+
+#define MEMCFG_BUS_WIDTH_32 (1)
+#define MEMCFG_BUS_WIDTH_16 (0)
+#define MEMCFG_BUS_WIDTH_8 (3)
+
+#define MEMCFG_SQAEN (1 << 6)
+#define MEMCFG_CLKENB (1 << 7)
+
+#define MEMCFG_WAITSTATE_8_3 (0 << 2)
+#define MEMCFG_WAITSTATE_7_3 (1 << 2)
+#define MEMCFG_WAITSTATE_6_3 (2 << 2)
+#define MEMCFG_WAITSTATE_5_3 (3 << 2)
+#define MEMCFG_WAITSTATE_4_2 (4 << 2)
+#define MEMCFG_WAITSTATE_3_2 (5 << 2)
+#define MEMCFG_WAITSTATE_2_2 (6 << 2)
+#define MEMCFG_WAITSTATE_1_2 (7 << 2)
+#define MEMCFG_WAITSTATE_8_1 (8 << 2)
+#define MEMCFG_WAITSTATE_7_1 (9 << 2)
+#define MEMCFG_WAITSTATE_6_1 (10 << 2)
+#define MEMCFG_WAITSTATE_5_1 (11 << 2)
+#define MEMCFG_WAITSTATE_4_0 (12 << 2)
+#define MEMCFG_WAITSTATE_3_0 (13 << 2)
+#define MEMCFG_WAITSTATE_2_0 (14 << 2)
+#define MEMCFG_WAITSTATE_1_0 (15 << 2)
+
+#endif
diff --git a/arch/arm/mach-clps711x/include/mach/devices.h b/arch/arm/mach-clps711x/include/mach/devices.h
new file mode 100644
index 0000000000..18a251a1d9
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/devices.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_DEVICES_H
+#define __MACH_DEVICES_H
+
+void clps711x_setup_memcfg(int bank, u32 val);
+void clps711x_add_uart(unsigned int id);
+
+#endif
diff --git a/arch/arm/mach-clps711x/reset.c b/arch/arm/mach-clps711x/reset.c
new file mode 100644
index 0000000000..4a42ef412d
--- /dev/null
+++ b/arch/arm/mach-clps711x/reset.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+
+extern void start(void);
+
+void __noreturn reset_cpu(unsigned long addr)
+{
+ arch_shutdown();
+
+ asm("mov pc, #0");
+
+ hang();
+}
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-ep93xx/include/mach/gpio.h
index 5f1b4bc001..306ab4c9f2 100644
--- a/arch/arm/mach-ep93xx/include/mach/gpio.h
+++ b/arch/arm/mach-ep93xx/include/mach/gpio.h
@@ -1,26 +1 @@
-/*
- * Copyright (C) 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-void gpio_set_value(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_direction_input(unsigned gpio);
-
-#endif /* __ASM_ARCH_GPIO_H */
-
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index d27d4f34d5..cca839465d 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -27,7 +27,7 @@ config ARCH_TEXT_BASE
default 0x4fc00000 if MACH_MX6Q_ARM2
default 0x97f00000 if MACH_CCMX51
default 0x4fc00000 if MACH_SABRELITE
- default 0x7fe00000 if MACH_TX53
+ default 0x8fe00000 if MACH_TX53
config BOARDINFO
default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
@@ -464,11 +464,22 @@ config MACH_TQMA53_1GB_RAM
config MACH_TX53
bool "Ka-Ro TX53"
select HAVE_DEFAULT_ENVIRONMENT_NEW
+ select MACH_HAS_LOWLEVEL_INIT
help
Say Y here if you are using the Ka-Ro tx53 board
endchoice
+if MACH_TX53
+choice
+ prompt "TX53 board revision"
+config TX53_REV_1011
+ bool "1011"
+config TX53_REV_XX30
+ bool "8030 / 1030"
+endchoice
+endif
+
endif
if ARCH_IMX6
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e43f92e430..259733ece0 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,5 +1,4 @@
obj-y += clocksource.o gpio.o
-obj-$(CONFIG_RESET_SOURCE) += reset_source.o
obj-$(CONFIG_ARCH_IMX1) += imx1.o iomux-v1.o clk-imx1.o
obj-$(CONFIG_ARCH_IMX25) += imx25.o iomux-v3.o clk-imx25.o
obj-$(CONFIG_ARCH_IMX21) += imx21.o iomux-v1.o clk-imx21.o
@@ -8,11 +7,13 @@ obj-$(CONFIG_ARCH_IMX31) += imx31.o iomux-v2.o clk-imx31.o
obj-$(CONFIG_ARCH_IMX35) += imx35.o iomux-v3.o clk-imx35.o
obj-$(CONFIG_ARCH_IMX51) += imx51.o iomux-v3.o imx5.o clk-imx5.o
obj-$(CONFIG_ARCH_IMX53) += imx53.o iomux-v3.o imx5.o clk-imx5.o
+pbl-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o
obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
obj-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
pbl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o
-obj-y += devices.o
+obj-y += devices.o imx.o
obj-y += boot.o
+obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 11c688e64c..cdddbe5824 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -17,9 +17,65 @@
#include <magicvar.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/generic.h>
+
+static const char *bootsource_str[] = {
+ [bootsource_unknown] = "unknown",
+ [bootsource_nand] = "nand",
+ [bootsource_nor] = "nor",
+ [bootsource_mmc] = "mmc",
+ [bootsource_i2c] = "i2c",
+ [bootsource_spi] = "spi",
+ [bootsource_serial] = "serial",
+ [bootsource_onenand] = "onenand",
+ [bootsource_hd] = "harddisk",
+};
+
+static enum imx_bootsource bootsource;
+
+void imx_set_bootsource(enum imx_bootsource src)
+{
+ if (src >= ARRAY_SIZE(bootsource_str))
+ src = bootsource_unknown;
+
+ bootsource = src;
+
+ setenv("barebox_loc", bootsource_str[src]);
+ export("barebox_loc");
+}
+
+enum imx_bootsource imx_bootsource(void)
+{
+ return bootsource;
+}
+
+BAREBOX_MAGICVAR(barebox_loc, "The source barebox has been booted from");
+
+/* [CTRL][TYPE] */
+static const enum imx_bootsource locations[4][4] = {
+ { /* CTRL = WEIM */
+ bootsource_nor,
+ bootsource_unknown,
+ bootsource_onenand,
+ bootsource_unknown,
+ }, { /* CTRL == NAND */
+ bootsource_nand,
+ bootsource_nand,
+ bootsource_nand,
+ bootsource_nand,
+ }, { /* CTRL == ATA, (imx35 only) */
+ bootsource_unknown,
+ bootsource_unknown, /* might be p-ata */
+ bootsource_unknown,
+ bootsource_unknown,
+ }, { /* CTRL == expansion */
+ bootsource_mmc, /* note imx25 could also be: movinand, ce-ata */
+ bootsource_unknown,
+ bootsource_i2c,
+ bootsource_spi,
+ }
+};
-#if defined(CONFIG_ARCH_IMX25) || defined(CONFIG_ARCH_IMX35)
/*
* Saves the boot source media into the $barebox_loc enviroment variable
*
@@ -38,43 +94,14 @@
* Note also that I suspect that the boot source pins are only sampled at
* power up.
*/
-static int imx_25_35_boot_save_loc(void)
+int imx_25_35_boot_save_loc(unsigned int ctrl, unsigned int type)
{
const char *bareboxloc = NULL;
- uint32_t reg;
- unsigned int ctrl, type;
+ enum imx_bootsource src;
- /* [CTRL][TYPE] */
- const char *const locations[4][4] = {
- { /* CTRL = WEIM */
- "nor",
- NULL,
- "onenand",
- NULL,
- }, { /* CTRL == NAND */
- "nand",
- "nand",
- "nand",
- "nand",
- }, { /* CTRL == ATA, (imx35 only) */
- NULL,
- NULL, /* might be p-ata */
- NULL,
- NULL,
- }, { /* CTRL == expansion */
- "mmc", /* note imx25 could also be: movinand, ce-ata */
- NULL,
- "i2c",
- "spi",
- }
- };
-
- reg = readl(IMX_CCM_BASE + CCM_RCSR);
- ctrl = (reg >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3;
- type = (reg >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3;
-
- bareboxloc = locations[ctrl][type];
+ src = locations[ctrl][type];
+ imx_set_bootsource(src);
if (bareboxloc) {
setenv("barebox_loc", bareboxloc);
export("barebox_loc");
@@ -82,32 +109,112 @@ static int imx_25_35_boot_save_loc(void)
return 0;
}
-coredevice_initcall(imx_25_35_boot_save_loc);
-#endif
-#if defined(CONFIG_ARCH_IMX27)
-static int imx_27_boot_save_loc(void)
+#define IMX27_SYSCTRL_GPCR 0x18
+#define IMX27_GPCR_BOOT_SHIFT 16
+#define IMX27_GPCR_BOOT_MASK (0xf << IMX27_GPCR_BOOT_SHIFT)
+#define IMX27_GPCR_BOOT_UART_USB 0
+#define IMX27_GPCR_BOOT_8BIT_NAND_2k 2
+#define IMX27_GPCR_BOOT_16BIT_NAND_2k 3
+#define IMX27_GPCR_BOOT_16BIT_NAND_512 4
+#define IMX27_GPCR_BOOT_16BIT_CS0 5
+#define IMX27_GPCR_BOOT_32BIT_CS0 6
+#define IMX27_GPCR_BOOT_8BIT_NAND_512 7
+
+void imx_27_boot_save_loc(void __iomem *sysctrl_base)
{
- switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
- case GPCR_BOOT_UART_USB:
- setenv("barebox_loc", "serial");
+ enum imx_bootsource src;
+ uint32_t val;
+
+ val = readl(sysctrl_base + IMX27_SYSCTRL_GPCR);
+ val &= IMX27_GPCR_BOOT_MASK;
+ val >>= IMX27_GPCR_BOOT_SHIFT;
+
+ switch (val) {
+ case IMX27_GPCR_BOOT_UART_USB:
+ src = bootsource_serial;
break;
- case GPCR_BOOT_8BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_512:
- case GPCR_BOOT_8BIT_NAND_512:
- setenv("barebox_loc", "nand");
+ case IMX27_GPCR_BOOT_8BIT_NAND_2k:
+ case IMX27_GPCR_BOOT_16BIT_NAND_2k:
+ case IMX27_GPCR_BOOT_16BIT_NAND_512:
+ case IMX27_GPCR_BOOT_8BIT_NAND_512:
+ src = bootsource_nand;
break;
default:
- setenv("barebox_loc", "nor");
+ src = bootsource_nor;
break;
}
- export("barebox_loc");
+ imx_set_bootsource(src);
+}
+
+#define IMX51_SRC_SBMR 0x4
+#define IMX51_SBMR_BT_MEM_TYPE_SHIFT 7
+#define IMX51_SBMR_BT_MEM_CTL_SHIFT 0
+#define IMX51_SBMR_BMOD_SHIFT 14
+
+int imx51_boot_save_loc(void __iomem *src_base)
+{
+ enum imx_bootsource src = bootsource_unknown;
+ uint32_t reg;
+ unsigned int ctrl, type;
+
+ reg = readl(src_base + IMX51_SRC_SBMR);
+
+ switch ((reg >> IMX51_SBMR_BMOD_SHIFT) & 0x3) {
+ case 0:
+ case 2:
+ /* internal boot */
+ ctrl = (reg >> IMX51_SBMR_BT_MEM_CTL_SHIFT) & 0x3;
+ type = (reg >> IMX51_SBMR_BT_MEM_TYPE_SHIFT) & 0x3;
+
+ src = locations[ctrl][type];
+ break;
+ case 1:
+ /* reserved */
+ src = bootsource_unknown;
+ break;
+ case 3:
+ src = bootsource_serial;
+ break;
+
+ }
+
+ imx_set_bootsource(src);
return 0;
}
-coredevice_initcall(imx_27_boot_save_loc);
-#endif
-BAREBOX_MAGICVAR(barebox_loc, "The source barebox has been booted from");
+#define IMX53_SRC_SBMR 0x4
+int imx53_boot_save_loc(void __iomem *src_base)
+{
+ enum imx_bootsource src = bootsource_unknown;
+ uint32_t cfg1 = readl(src_base + IMX53_SRC_SBMR) & 0xff;
+
+ switch (cfg1 >> 4) {
+ case 2:
+ src = bootsource_hd;
+ break;
+ case 3:
+ if (cfg1 & (1 << 3))
+ src = bootsource_spi;
+ else
+ src = bootsource_i2c;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ src = bootsource_mmc;
+ break;
+ default:
+ break;
+ }
+
+ if (cfg1 & (1 << 7))
+ src = bootsource_nand;
+
+ imx_set_bootsource(src);
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
index 45e9c6643f..0d04a92f36 100644
--- a/arch/arm/mach-imx/clk-imx1.c
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -96,9 +96,18 @@ static int imx1_ccm_probe(struct device_d *dev)
return 0;
}
+static __maybe_unused struct of_device_id imx1_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx1-ccm",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d imx1_ccm_driver = {
.probe = imx1_ccm_probe,
.name = "imx1-ccm",
+ .of_compatible = DRV_OF_COMPAT(imx1_ccm_dt_ids),
};
static int imx1_ccm_init(void)
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index 69aaa9e6ad..9e7af816a2 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -47,7 +47,7 @@
enum imx21_clks {
ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
- per2, per3, per4, usb_div, nfc_div, clk_max
+ per2, per3, per4, usb_div, nfc_div, lcdc_per_gate, clk_max
};
static struct clk *clks[clk_max];
@@ -70,6 +70,16 @@ static int imx21_ccm_probe(struct device_d *dev)
base = dev_request_mem_region(dev, 0);
+ writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
+ (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
+ (1 << 13) | (1 << 14) | (1 << 19) | (1 << 22) |
+ (1 << 24) | (1 << 26) | (1 << 30),
+ base + CCM_PCCR0);
+
+ writel((1 << 23) | (1 << 24) | (1 << 25) | (1 << 26) | (1 << 27) |
+ (1 << 28) | (1 << 29) | (1 << 30) | (1 << 31),
+ base + CCM_PCCR1);
+
clks[ckil] = clk_fixed("ckil", lref);
clks[ckih] = clk_fixed("ckih", href);
clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
@@ -88,6 +98,7 @@ static int imx21_ccm_probe(struct device_d *dev)
clks[per4] = imx_clk_divider("per4", "mpll", base + CCM_PCDR1, 24, 6);
clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 26, 3);
clks[nfc_div] = imx_clk_divider("nfc_div", "ipg", base + CCM_PCDR0, 12, 4);
+ clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3", base + CCM_PCCR0, 18);
clkdev_add_physbase(clks[per1], MX21_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1], MX21_GPT2_BASE_ADDR, NULL);
@@ -98,18 +109,27 @@ static int imx21_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[per1], MX21_UART4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2], MX21_CSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2], MX21_CSPI2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per2], MX21_CSPI3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX21_I2C_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[per3], MX21_CSPI3_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[per3], MX21_LCDC_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[lcdc_per_gate], MX21_LCDC_BASE_ADDR, NULL);
return 0;
}
+static __maybe_unused struct of_device_id imx21_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx21-ccm",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d imx21_ccm_driver = {
.probe = imx21_ccm_probe,
.name = "imx21-ccm",
+ .of_compatible = DRV_OF_COMPAT(imx21_ccm_dt_ids),
};
static int imx21_ccm_init(void)
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 3b9588ced5..38f15a66ab 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -55,7 +55,7 @@ enum mx25_clks {
per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
- clk_max
+ lcdc_per_gate, clk_max
};
static struct clk *clks[clk_max];
@@ -76,9 +76,19 @@ static int imx25_ccm_probe(struct device_d *dev)
base = dev_request_mem_region(dev, 0);
- writel(0x10e88578, base + CCM_CGCR0);
- writel(0x0478e1e0, base + CCM_CGCR0);
- writel(0x0007c400, base + CCM_CGCR0);
+ writel((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 9) |
+ (1 << 10) | (1 << 15) | (1 << 19) | (1 << 21) | (1 << 22) |
+ (1 << 23) | (1 << 24) | (1 << 28),
+ base + CCM_CGCR0);
+
+ writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) |
+ (1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) |
+ (1 << 26) | (1 << 29) | (1 << 31),
+ base + CCM_CGCR1);
+
+ writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) |
+ (1 << 15) | (1 << 16) | (1 << 17) | (1 << 18),
+ base + CCM_CGCR2);
clks[dummy] = clk_fixed("dummy", 0);
clks[osc] = clk_fixed("osc", 24000000);
@@ -122,6 +132,7 @@ static int imx25_ccm_probe(struct device_d *dev)
clks[per13] = imx_clk_divider("per13", "per13_sel", base + CCM_PCDR3, 8, 6);
clks[per14] = imx_clk_divider("per14", "per14_sel", base + CCM_PCDR3, 16, 6);
clks[per15] = imx_clk_divider("per15", "per15_sel", base + CCM_PCDR3, 24, 6);
+ clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per7", base + CCM_CGCR0, 7);
clkdev_add_physbase(clks[per15], MX25_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART2_BASE_ADDR, NULL);
@@ -138,13 +149,23 @@ static int imx25_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[lcdc_per_gate], MX25_LCDC_BASE_ADDR, NULL);
return 0;
}
+static __maybe_unused struct of_device_id imx25_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx25-ccm",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d imx25_ccm_driver = {
.probe = imx25_ccm_probe,
.name = "imx25-ccm",
+ .of_compatible = DRV_OF_COMPAT(imx25_ccm_dt_ids),
};
static int imx25_ccm_init(void)
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index abfde0fd62..222d2a6ebc 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -7,6 +7,7 @@
#include <linux/err.h>
#include <mach/imx27-regs.h>
#include <mach/generic.h>
+#include <mach/revision.h>
#include "clk.h"
@@ -26,10 +27,73 @@
#define CCM_PMCOUNT 0x30
#define CCM_WKGDCTL 0x34
+#define PCCR0_SSI2_EN (1 << 0)
+#define PCCR0_SSI1_EN (1 << 1)
+#define PCCR0_SLCDC_EN (1 << 2)
+#define PCCR0_SDHC3_EN (1 << 3)
+#define PCCR0_SDHC2_EN (1 << 4)
+#define PCCR0_SDHC1_EN (1 << 5)
+#define PCCR0_SDC_EN (1 << 6)
+#define PCCR0_SAHARA_EN (1 << 7)
+#define PCCR0_RTIC_EN (1 << 8)
+#define PCCR0_RTC_EN (1 << 9)
+#define PCCR0_PWM_EN (1 << 11)
+#define PCCR0_OWIRE_EN (1 << 12)
+#define PCCR0_MSHC_EN (1 << 13)
+#define PCCR0_LCDC_EN (1 << 14)
+#define PCCR0_KPP_EN (1 << 15)
+#define PCCR0_IIM_EN (1 << 16)
+#define PCCR0_I2C2_EN (1 << 17)
+#define PCCR0_I2C1_EN (1 << 18)
+#define PCCR0_GPT6_EN (1 << 19)
+#define PCCR0_GPT5_EN (1 << 20)
+#define PCCR0_GPT4_EN (1 << 21)
+#define PCCR0_GPT3_EN (1 << 22)
+#define PCCR0_GPT2_EN (1 << 23)
+#define PCCR0_GPT1_EN (1 << 24)
+#define PCCR0_GPIO_EN (1 << 25)
+#define PCCR0_FEC_EN (1 << 26)
+#define PCCR0_EMMA_EN (1 << 27)
+#define PCCR0_DMA_EN (1 << 28)
+#define PCCR0_CSPI3_EN (1 << 29)
+#define PCCR0_CSPI2_EN (1 << 30)
+#define PCCR0_CSPI1_EN (1 << 31)
+
+#define PCCR1_MSHC_BAUDEN (1 << 2)
+#define PCCR1_NFC_BAUDEN (1 << 3)
+#define PCCR1_SSI2_BAUDEN (1 << 4)
+#define PCCR1_SSI1_BAUDEN (1 << 5)
+#define PCCR1_H264_BAUDEN (1 << 6)
+#define PCCR1_PERCLK4_EN (1 << 7)
+#define PCCR1_PERCLK3_EN (1 << 8)
+#define PCCR1_PERCLK2_EN (1 << 9)
+#define PCCR1_PERCLK1_EN (1 << 10)
+#define PCCR1_HCLK_USB (1 << 11)
+#define PCCR1_HCLK_SLCDC (1 << 12)
+#define PCCR1_HCLK_SAHARA (1 << 13)
+#define PCCR1_HCLK_RTIC (1 << 14)
+#define PCCR1_HCLK_LCDC (1 << 15)
+#define PCCR1_HCLK_H264 (1 << 16)
+#define PCCR1_HCLK_FEC (1 << 17)
+#define PCCR1_HCLK_EMMA (1 << 18)
+#define PCCR1_HCLK_EMI (1 << 19)
+#define PCCR1_HCLK_DMA (1 << 20)
+#define PCCR1_HCLK_CSI (1 << 21)
+#define PCCR1_HCLK_BROM (1 << 22)
+#define PCCR1_HCLK_ATA (1 << 23)
+#define PCCR1_WDT_EN (1 << 24)
+#define PCCR1_USB_EN (1 << 25)
+#define PCCR1_UART6_EN (1 << 26)
+#define PCCR1_UART5_EN (1 << 27)
+#define PCCR1_UART4_EN (1 << 28)
+#define PCCR1_UART3_EN (1 << 29)
+#define PCCR1_UART2_EN (1 << 30)
+#define PCCR1_UART1_EN (1 << 31)
+
enum mx27_clks {
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
per2_div, per3_div, per4_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div,
- clko_en, clk_max
+ clko_en, lcdc_per_gate, clk_max
};
static struct clk *clks[clk_max];
@@ -72,18 +136,18 @@ static int imx27_ccm_probe(struct device_d *dev)
base = dev_request_mem_region(dev, 0);
writel(PCCR0_SDHC3_EN | PCCR0_SDHC2_EN | PCCR0_SDHC1_EN |
- PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_IIM_EN | PCCR0_I2C2_EN |
- PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN | PCCR0_GPT4_EN |
- PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN | PCCR0_GPIO_EN |
- PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN | PCCR0_CSPI1_EN,
+ PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_LCDC_EN | PCCR0_IIM_EN |
+ PCCR0_I2C2_EN | PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN |
+ PCCR0_GPT4_EN | PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN |
+ PCCR0_GPIO_EN | PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN |
+ PCCR0_CSPI1_EN,
base + CCM_PCCR0);
- writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK3_EN |
- PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN | PCCR1_HCLK_USB |
- PCCR1_HCLK_FEC | PCCR1_HCLK_EMI | PCCR1_WDT_EN | PCCR1_USB_EN |
- PCCR1_UART6_EN | PCCR1_UART5_EN | PCCR1_UART4_EN |
- PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN,
- base + CCM_PCCR1);
+ writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN |
+ PCCR1_HCLK_USB | PCCR1_HCLK_LCDC | PCCR1_HCLK_FEC | PCCR1_HCLK_EMI |
+ PCCR1_WDT_EN | PCCR1_USB_EN | PCCR1_UART6_EN | PCCR1_UART5_EN |
+ PCCR1_UART4_EN | PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN,
+ base + CCM_PCCR1);
clks[dummy] = clk_fixed("dummy", 0);
clks[ckih] = clk_fixed("ckih", 26000000);
@@ -92,7 +156,7 @@ static int imx27_ccm_probe(struct device_d *dev)
clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0);
clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
- if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0) {
+ if (imx_silicon_revision() >= IMX_CHIP_REV_2_0) {
clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 8, 2);
clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
} else {
@@ -110,11 +174,12 @@ static int imx27_ccm_probe(struct device_d *dev)
ARRAY_SIZE(cpu_sel_clks));
clks[clko_sel] = imx_clk_mux("clko_sel", base + CCM_CCSR, 0, 5, clko_sel_clks,
ARRAY_SIZE(clko_sel_clks));
- if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0)
+ if (imx_silicon_revision() >= IMX_CHIP_REV_2_0)
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 12, 2);
else
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3);
clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3);
+ clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3_div", base + CCM_PCCR1, 7);
clkdev_add_physbase(clks[per1_div], MX27_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT2_BASE_ADDR, NULL);
@@ -136,15 +201,24 @@ static int imx27_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[per3_div], MX27_LCDC_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[lcdc_per_gate], MX27_LCDC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL);
return 0;
}
+static __maybe_unused struct of_device_id imx27_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx27-ccm",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d imx27_ccm_driver = {
.probe = imx27_ccm_probe,
.name = "imx27-ccm",
+ .of_compatible = DRV_OF_COMPAT(imx27_ccm_dt_ids),
};
static int imx27_ccm_init(void)
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index cf8963a326..aa1b652ddd 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -121,9 +121,18 @@ static int imx31_ccm_probe(struct device_d *dev)
return 0;
}
+static __maybe_unused struct of_device_id imx31_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx31-ccm",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d imx31_ccm_driver = {
.probe = imx31_ccm_probe,
.name = "imx31-ccm",
+ .of_compatible = DRV_OF_COMPAT(imx31_ccm_dt_ids),
};
static int imx31_ccm_init(void)
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index dfa75614fa..5b5a9e7882 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -174,9 +174,18 @@ static int imx35_ccm_probe(struct device_d *dev)
return 0;
}
+static __maybe_unused struct of_device_id imx35_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx35-ccm",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d imx35_ccm_driver = {
.probe = imx35_ccm_probe,
.name = "imx35-ccm",
+ .of_compatible = DRV_OF_COMPAT(imx35_ccm_dt_ids),
};
static int imx35_ccm_init(void)
diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
index 365fcb3338..050842d103 100644
--- a/arch/arm/mach-imx/clk-imx5.c
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -13,7 +13,8 @@
#include <io.h>
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
+#include <mach/imx53-regs.h>
#include "clk.h"
@@ -233,9 +234,18 @@ static int imx51_ccm_probe(struct device_d *dev)
return 0;
}
+static __maybe_unused struct of_device_id imx51_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx51-ccm",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d imx51_ccm_driver = {
.probe = imx51_ccm_probe,
.name = "imx51-ccm",
+ .of_compatible = DRV_OF_COMPAT(imx51_ccm_dt_ids),
};
static int imx51_ccm_init(void)
@@ -285,9 +295,18 @@ static int imx53_ccm_probe(struct device_d *dev)
return 0;
}
+static __maybe_unused struct of_device_id imx53_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx53-ccm",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d imx53_ccm_driver = {
.probe = imx53_ccm_probe,
.name = "imx53-ccm",
+ .of_compatible = DRV_OF_COMPAT(imx53_ccm_dt_ids),
};
static int imx53_ccm_init(void)
diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
index 19a8bc6836..a1da47a959 100644
--- a/arch/arm/mach-imx/clk-imx6.c
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -294,9 +294,18 @@ static int imx6_ccm_probe(struct device_d *dev)
return 0;
}
+static __maybe_unused struct of_device_id imx6_ccm_dt_ids[] = {
+ {
+ .compatible = "fsl,imx6-ccm",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d imx6_ccm_driver = {
.probe = imx6_ccm_probe,
.name = "imx6-ccm",
+ .of_compatible = DRV_OF_COMPAT(imx6_ccm_dt_ids),
};
static int imx6_ccm_init(void)
diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
index 69072698c4..7e087c1789 100644
--- a/arch/arm/mach-imx/clk-pllv2.c
+++ b/arch/arm/mach-imx/clk-pllv2.c
@@ -17,7 +17,6 @@
#include <io.h>
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/imx-regs.h>
#include <malloc.h>
#include <asm-generic/div64.h>
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index a99eec56a3..e337e87f13 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -17,7 +17,6 @@
#include <io.h>
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/imx-regs.h>
#include <malloc.h>
#include <clock.h>
#include <asm-generic/div64.h>
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 3d79950697..0f30082e1f 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -19,6 +19,12 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
return clk_mux(name, reg, shift, width, parents, num_parents);
}
+static inline struct clk *imx_clk_gate(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_gate(name, parent, reg, shift);
+}
+
struct clk *imx_clk_pllv1(const char *name, const char *parent,
void __iomem *base);
diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c
index 69a688c09d..e18685ec29 100644
--- a/arch/arm/mach-imx/clocksource.c
+++ b/arch/arm/mach-imx/clocksource.c
@@ -32,7 +32,6 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <notifier.h>
-#include <mach/imx-regs.h>
#include <io.h>
/* Part 1: Registers */
@@ -108,18 +107,6 @@ static int imx_gpt_probe(struct device_d *dev)
/* setup GP Timer 1 */
writel(TCTL_SWR, timer_base + GPT_TCTL);
-#ifdef CONFIG_ARCH_IMX21
- PCCR1 |= PCCR1_GPT1_EN;
-#endif
-#ifdef CONFIG_ARCH_IMX27
- PCCR0 |= PCCR0_GPT1_EN;
- PCCR1 |= PCCR1_PERCLK1_EN;
-#endif
-#ifdef CONFIG_ARCH_IMX25
- writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 19),
- IMX_CCM_BASE + CCM_CGCR1);
-#endif
-
for (i = 0; i < 100; i++)
writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */
@@ -179,40 +166,3 @@ static int imx_gpt_init(void)
return platform_driver_register(&imx_gpt_driver);
}
coredevice_initcall(imx_gpt_init);
-
-/*
- * Watchdog Registers
- */
-#ifdef CONFIG_ARCH_IMX1
-#define WDOG_WCR 0x00 /* Watchdog Control Register */
-#define WDOG_WSR 0x04 /* Watchdog Service Register */
-#define WDOG_WSTR 0x08 /* Watchdog Status Register */
-#define WDOG_WCR_WDE (1 << 0)
-#else
-#define WDOG_WCR 0x00 /* Watchdog Control Register */
-#define WDOG_WSR 0x02 /* Watchdog Service Register */
-#define WDOG_WSTR 0x04 /* Watchdog Status Register */
-#define WDOG_WCR_WDE (1 << 2)
-#endif
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void __noreturn reset_cpu (unsigned long addr)
-{
- void __iomem *wdt = IOMEM(IMX_WDT_BASE);
-
- /* Disable watchdog and set Time-Out field to 0 */
- writew(0x0, wdt + WDOG_WCR);
-
- /* Write Service Sequence */
- writew(0x5555, wdt + WDOG_WSR);
- writew(0xaaaa, wdt + WDOG_WSR);
-
- /* Enable watchdog */
- writew(WDOG_WCR_WDE, wdt + WDOG_WCR);
-
- while (1);
- /*NOTREACHED*/
-}
-EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 9fde84f1a1..4ee4e6cc8d 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -8,9 +8,14 @@ static inline struct device_d *imx_add_device(char *name, int id, void *base, in
IORESOURCE_MEM, pdata);
}
-struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata)
+struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata)
{
- return imx_add_device("fec_imx", -1, base, 0x1000, pdata);
+ return imx_add_device("imx27-fec", -1, base, 0x1000, pdata);
+}
+
+struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata)
+{
+ return imx_add_device("imx6-fec", -1, base, 0x1000, pdata);
}
struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata)
@@ -23,9 +28,14 @@ struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata
return imx_add_device("i2c-fsl", id, base, 0x1000, pdata);
}
-struct device_d *imx_add_uart(void *base, int id)
+struct device_d *imx_add_uart_imx1(void *base, int id)
+{
+ return imx_add_device("imx1-uart", id, base, 0x1000, NULL);
+}
+
+struct device_d *imx_add_uart_imx21(void *base, int id)
{
- return imx_add_device("imx_serial", id, base, 0x1000, NULL);
+ return imx_add_device("imx21-uart", id, base, 0x1000, NULL);
}
struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata)
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index a5909923f6..2e9e475fed 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -17,7 +17,11 @@
#include <linux/mtd/nand.h>
#include <mach/imx-nand.h>
#include <mach/generic.h>
-#include <mach/imx-regs.h>
+#include <mach/imx21-regs.h>
+#include <mach/imx25-regs.h>
+#include <mach/imx27-regs.h>
+#include <mach/imx31-regs.h>
+#include <mach/imx35-regs.h>
static void __bare_init noinline imx_nandboot_wait_op_done(void *regs)
{
@@ -116,7 +120,13 @@ static void __bare_init __memcpy32(void *trg, const void *src, int size)
static int __maybe_unused is_pagesize_2k(void)
{
#ifdef CONFIG_ARCH_IMX21
- if (readl(IMX_SYSTEM_CTL_BASE + 0x14) & (1 << 5))
+ if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
+ return 1;
+ else
+ return 0;
+#endif
+#if defined(CONFIG_ARCH_IMX25)
+ if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8))
return 1;
else
return 0;
@@ -128,13 +138,13 @@ static int __maybe_unused is_pagesize_2k(void)
return 0;
#endif
#ifdef CONFIG_ARCH_IMX31
- if (readl(IMX_CCM_BASE + CCM_RCSR) & RCSR_NFMS)
+ if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS)
return 1;
else
return 0;
#endif
-#if defined(CONFIG_ARCH_IMX35) || defined(CONFIG_ARCH_IMX25)
- if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 8))
+#if defined(CONFIG_ARCH_IMX35)
+ if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8))
return 1;
else
return 0;
@@ -163,7 +173,21 @@ void __bare_init imx_nand_load_image(void *dest, int size)
blocksize = 16 * 1024;
}
- base = (void __iomem *)IMX_NFC_BASE;
+#ifdef CONFIG_ARCH_IMX21
+ base = (void __iomem *)MX21_NFC_BASE_ADDR;
+#endif
+#ifdef CONFIG_ARCH_IMX25
+ base = (void __iomem *)MX25_NFC_BASE_ADDR;
+#endif
+#ifdef CONFIG_ARCH_IMX27
+ base = (void __iomem *)MX27_NFC_BASE_ADDR;
+#endif
+#ifdef CONFIG_ARCH_IMX31
+ base = (void __iomem *)MX31_NFC_BASE_ADDR;
+#endif
+#ifdef CONFIG_ARCH_IMX35
+ base = (void __iomem *)MX35_NFC_BASE_ADDR;
+#endif
if (nfc_is_v21()) {
regs = base + 0x1e00;
spare0 = base + 0x1000;
diff --git a/arch/arm/mach-imx/gpio.c b/arch/arm/mach-imx/gpio.c
index 6c88948da0..1bf4100964 100644
--- a/arch/arm/mach-imx/gpio.c
+++ b/arch/arm/mach-imx/gpio.c
@@ -23,7 +23,6 @@
#include <common.h>
#include <errno.h>
#include <io.h>
-#include <mach/imx-regs.h>
#include <gpio.h>
#include <init.h>
@@ -137,6 +136,7 @@ static int imx_gpio_probe(struct device_d *dev)
imxgpio->chip.base = of_alias_get_id(dev->device_node, "gpio");
if (imxgpio->chip.base < 0)
return imxgpio->chip.base;
+ imxgpio->chip.base *= 32;
} else {
imxgpio->chip.base = dev->id * 32;
}
diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c
new file mode 100644
index 0000000000..85d10cf4e7
--- /dev/null
+++ b/arch/arm/mach-imx/imx-bbu-internal.c
@@ -0,0 +1,543 @@
+/*
+ * imx-bbu-internal.c - i.MX specific update functions for internal boot
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define IMX_INTERNAL_NAND_BBU
+
+#include <common.h>
+#include <malloc.h>
+#include <bbu.h>
+#include <filetype.h>
+#include <errno.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <sizes.h>
+#include <linux/mtd/mtd-abi.h>
+#include <linux/stat.h>
+#include <ioctl.h>
+#include <mach/bbu.h>
+#include <mach/imx-flash-header.h>
+
+#define FLASH_HEADER_OFFSET_MMC 0x400
+
+#define IMX_INTERNAL_FLAG_NAND (1 << 0)
+#define IMX_INTERNAL_FLAG_KEEP_DOSPART (1 << 1)
+
+struct imx_internal_bbu_handler {
+ struct bbu_handler handler;
+ const void *dcd;
+ int dcdsize;
+ unsigned long app_dest;
+ unsigned long flash_header_offset;
+ size_t device_size;
+ unsigned long flags;
+};
+
+/*
+ * Actually write an image to the target device, eventually keeping a
+ * DOS partition table on the device
+ */
+static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler,
+ struct bbu_data *data, void *buf, int image_len)
+{
+ int fd, ret;
+
+ fd = open(data->devicefile, O_RDWR | O_CREAT);
+ if (fd < 0)
+ return fd;
+
+ if (imx_handler->flags & IMX_INTERNAL_FLAG_KEEP_DOSPART) {
+ void *mbr = xzalloc(512);
+
+ debug("%s: reading DOS partition table in order to keep it\n");
+
+ ret = read(fd, mbr, 512);
+ if (ret < 0) {
+ free(mbr);
+ goto err_close;
+ }
+
+ memcpy(buf + 0x1b8, mbr + 0x1b8, 0x48);
+ free(buf);
+
+ ret = lseek(fd, 0, SEEK_SET);
+ if (ret)
+ goto err_close;
+ }
+
+ ret = write(fd, buf, image_len);
+ if (ret < 0)
+ goto err_close;
+
+ ret = 0;
+
+err_close:
+ close(fd);
+
+ return ret;
+}
+
+/*
+ * Update barebox on a v1 type internal boot (i.MX25, i.MX35, i.MX51)
+ *
+ * This constructs a DCD header, adds the specific DCD data and writes
+ * the resulting image to the device. Currently this handles MMC/SD
+ * devices.
+ */
+static int imx_bbu_internal_v1_update(struct bbu_handler *handler, struct bbu_data *data)
+{
+ struct imx_internal_bbu_handler *imx_handler =
+ container_of(handler, struct imx_internal_bbu_handler, handler);
+ struct imx_flash_header *flash_header;
+ unsigned long flash_header_offset = imx_handler->flash_header_offset;
+ u32 *dcd_image_size;
+ void *imx_pre_image;
+ int imx_pre_image_size = 0x2000;
+ int ret, image_len;
+ void *buf;
+
+ if (file_detect_type(data->image) != filetype_arm_barebox) {
+ if (!bbu_force(data, "Not an ARM barebox image"))
+ return -EINVAL;
+ }
+
+ ret = bbu_confirm(data);
+ if (ret)
+ return ret;
+
+ printf("updating to %s\n", data->devicefile);
+
+ imx_pre_image = xzalloc(imx_pre_image_size);
+ flash_header = imx_pre_image + flash_header_offset;
+
+ flash_header->app_code_jump_vector = imx_handler->app_dest + 0x1000;
+ flash_header->app_code_barker = APP_CODE_BARKER;
+ flash_header->app_code_csf = 0;
+ flash_header->dcd_ptr_ptr = imx_handler->app_dest + flash_header_offset +
+ offsetof(struct imx_flash_header, dcd);
+ flash_header->super_root_key = 0;
+ flash_header->dcd = imx_handler->app_dest + flash_header_offset +
+ offsetof(struct imx_flash_header, dcd_barker);
+ flash_header->app_dest = imx_handler->app_dest;
+ flash_header->dcd_barker = DCD_BARKER;
+ flash_header->dcd_block_len = imx_handler->dcdsize;
+
+ memcpy((void *)flash_header + sizeof(*flash_header), imx_handler->dcd, imx_handler->dcdsize);
+
+ dcd_image_size = (imx_pre_image + flash_header_offset + sizeof(*flash_header) + imx_handler->dcdsize);
+
+ *dcd_image_size = ALIGN(imx_pre_image_size + data->len, 4096);
+
+ /* Create a buffer containing header and image data */
+ image_len = data->len + imx_pre_image_size;
+ buf = xzalloc(image_len);
+ memcpy(buf, imx_pre_image, imx_pre_image_size);
+ memcpy(buf + imx_pre_image_size, data->image, data->len);
+
+ ret = imx_bbu_write_device(imx_handler, data, buf, image_len);
+
+ free(buf);
+
+ free(imx_pre_image);
+
+ return ret;
+}
+
+#define DBBT_MAGIC 0x44424254
+#define FCB_MAGIC 0x20424346
+
+/*
+ * Write an image to NAND. This creates a FCB header and a DBBT (Discovered Bad
+ * Block Table). The DBBT is initialized with the bad blocks known from the mtd
+ * layer.
+ */
+static int imx_bbu_internal_v2_write_nand_dbbt(struct imx_internal_bbu_handler *imx_handler,
+ struct bbu_data *data, void *image, int image_len)
+{
+ struct mtd_info_user meminfo;
+ int fd;
+ struct stat s;
+ int size_available, size_need;
+ int ret;
+ uint32_t *ptr, *num_bb, *bb;
+ uint64_t offset;
+ int block = 0, len, now, blocksize;
+
+ ret = stat(data->devicefile, &s);
+ if (ret)
+ return ret;
+
+ size_available = s.st_size;
+
+ fd = open(data->devicefile, O_RDWR);
+ if (fd < 0)
+ return fd;
+
+ ret = ioctl(fd, MEMGETINFO, &meminfo);
+ if (ret)
+ goto out;
+
+ blocksize = meminfo.erasesize;
+
+ ptr = image + 0x4;
+ *ptr++ = FCB_MAGIC; /* FCB */
+ *ptr++ = 1; /* FCB version */
+
+ ptr = image + 0x78; /* DBBT start page */
+ *ptr = 4;
+
+ ptr = image + 4 * 2048 + 4;
+ *ptr++ = DBBT_MAGIC; /* DBBT */
+ *ptr = 1; /* DBBT version */
+
+ ptr = (u32*)(image + 0x2010);
+ /*
+ * This is marked as reserved in the i.MX53 reference manual, but
+ * must be != 0. Otherwise the ROM ignores the DBBT
+ */
+ *ptr = 1;
+
+ ptr = (u32*)(image + 0x4004); /* start of DBBT */
+ num_bb = ptr;
+ bb = ptr + 1;
+ offset = 0;
+
+ size_need = data->len + 0x8000;
+
+ /*
+ * Collect bad blocks and construct DBBT
+ */
+ while (size_need > 0) {
+ ret = ioctl(fd, MEMGETBADBLOCK, &offset);
+ if (ret < 0)
+ goto out;
+
+ if (ret) {
+ if (!offset) {
+ printf("1st block is bad. This is not supported\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ debug("bad block at 0x%08llx\n", offset);
+ *num_bb += 1;
+ if (*num_bb == 425) {
+ /* Maximum number of bad blocks the ROM supports */
+ printf("maximum number of bad blocks reached\n");
+ ret = -ENOSPC;
+ goto out;
+ }
+ *bb++ = block;
+ offset += blocksize;
+ block++;
+ continue;
+ }
+ size_need -= blocksize;
+ size_available -= blocksize;
+ offset += blocksize;
+ block++;
+
+ if (size_available < 0) {
+ printf("device is too small");
+ ret = -ENOSPC;
+ goto out;
+ }
+ }
+
+ debug("total image size: 0x%08x. Space needed including bad blocks: 0x%08x\n",
+ data->len + 0x8000,
+ data->len + 0x8000 + *num_bb * blocksize);
+
+ if (data->len + 0x8000 + *num_bb * blocksize > imx_handler->device_size) {
+ printf("needed space (0x%08x) exceeds partition space (0x%08x)\n",
+ data->len + 0x8000 + *num_bb * blocksize,
+ imx_handler->device_size);
+ ret = -ENOSPC;
+ goto out;
+ }
+
+ len = data->len + 0x8000;
+ offset = 0;
+
+ /*
+ * Write image to NAND skipping bad blocks
+ */
+ while (len > 0) {
+ now = min(len, blocksize);
+
+ ret = ioctl(fd, MEMGETBADBLOCK, &offset);
+ if (ret < 0)
+ goto out;
+
+ if (ret) {
+ ret = lseek(fd, offset + blocksize, SEEK_SET);
+ if (ret < 0)
+ goto out;
+ offset += blocksize;
+ continue;
+ }
+
+ debug("writing %d bytes at 0x%08llx\n", now, offset);
+
+ ret = erase(fd, blocksize, offset);
+ if (ret)
+ goto out;
+
+ ret = write(fd, image, now);
+ if (ret < 0)
+ goto out;
+
+ len -= now;
+ image += now;
+ offset += now;
+ }
+
+ ret = 0;
+
+out:
+ close(fd);
+
+ return ret;
+}
+
+/*
+ * Update barebox on a v2 type internal boot (i.MX53)
+ *
+ * This constructs a DCD header, adds the specific DCD data and writes
+ * the resulting image to the device. Currently this handles MMC/SD
+ * and NAND devices.
+ */
+static int imx_bbu_internal_v2_update(struct bbu_handler *handler, struct bbu_data *data)
+{
+ struct imx_internal_bbu_handler *imx_handler =
+ container_of(handler, struct imx_internal_bbu_handler, handler);
+ struct imx_flash_header_v2 *flash_header;
+ unsigned long flash_header_offset = imx_handler->flash_header_offset;
+ void *imx_pre_image;
+ int imx_pre_image_size;
+ int ret, image_len;
+ void *buf;
+
+ if (file_detect_type(data->image) != filetype_arm_barebox) {
+ if (!bbu_force(data, "Not an ARM barebox image"))
+ return -EINVAL;
+ }
+
+ ret = bbu_confirm(data);
+ if (ret)
+ return ret;
+
+ printf("updating to %s\n", data->devicefile);
+
+ if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND)
+ /* NAND needs additional space for the DBBT */
+ imx_pre_image_size = 0x8000;
+ else
+ imx_pre_image_size = 0x2000;
+
+ imx_pre_image = xzalloc(imx_pre_image_size);
+ flash_header = imx_pre_image + flash_header_offset;
+
+ flash_header->header.tag = IVT_HEADER_TAG;
+ flash_header->header.length = cpu_to_be16(32);
+ flash_header->header.version = IVT_VERSION;
+
+ flash_header->entry = imx_handler->app_dest + imx_pre_image_size;
+ flash_header->dcd_ptr = imx_handler->app_dest + flash_header_offset +
+ offsetof(struct imx_flash_header_v2, dcd);
+ flash_header->boot_data_ptr = imx_handler->app_dest +
+ flash_header_offset + offsetof(struct imx_flash_header_v2, boot_data);
+ flash_header->self = imx_handler->app_dest + flash_header_offset;
+
+ flash_header->boot_data.start = imx_handler->app_dest;
+ flash_header->boot_data.size = ALIGN(imx_pre_image_size + data->len, 4096);;
+
+ flash_header->dcd.header.tag = DCD_HEADER_TAG;
+ flash_header->dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) +
+ imx_handler->dcdsize);
+ flash_header->dcd.header.version = DCD_VERSION;
+
+ /* Add dcd data */
+ memcpy((void *)flash_header + sizeof(*flash_header), imx_handler->dcd, imx_handler->dcdsize);
+
+ /* Create a buffer containing header and image data */
+ image_len = data->len + imx_pre_image_size;
+ buf = xzalloc(image_len);
+ memcpy(buf, imx_pre_image, imx_pre_image_size);
+ memcpy(buf + imx_pre_image_size, data->image, data->len);
+
+ if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND) {
+ ret = imx_bbu_internal_v2_write_nand_dbbt(imx_handler, data, buf,
+ image_len);
+ goto out_free_buf;
+ }
+
+ ret = imx_bbu_write_device(imx_handler, data, buf, image_len);
+
+out_free_buf:
+ free(buf);
+
+ free(imx_pre_image);
+ return ret;
+}
+
+/*
+ * On the i.MX53 the dcd data can contain several commands. Each of them must
+ * have its length encoded into it. We can't express that during compile time,
+ * so use this function if you are using multiple dcd commands and wish to
+ * concatenate them together to a single dcd table with the correct sizes for
+ * each command.
+ */
+void *imx53_bbu_internal_concat_dcd_table(struct dcd_table *table, int num_entries)
+{
+ int i;
+ unsigned int dcdsize = 0, pos = 0;
+ void *dcdptr;
+
+ for (i = 0; i < num_entries; i++)
+ dcdsize += table[i].size;
+
+ dcdptr = xmalloc(dcdsize);
+
+ for (i = 0; i < num_entries; i++) {
+ u32 *current = dcdptr + pos;
+ memcpy(current, table[i].data, table[i].size);
+ *current |= cpu_to_be32(table[i].size << 8);
+ pos += table[i].size;
+ }
+
+ return dcdptr;
+}
+
+static struct imx_internal_bbu_handler *__init_handler(const char *name, char *devicefile,
+ unsigned long flags)
+{
+ struct imx_internal_bbu_handler *imx_handler;
+ struct bbu_handler *handler;
+
+ imx_handler = xzalloc(sizeof(*imx_handler));
+ handler = &imx_handler->handler;
+ handler->devicefile = devicefile;
+ handler->name = name;
+ handler->flags = flags;
+
+ return imx_handler;
+}
+
+static int __register_handler(struct imx_internal_bbu_handler *imx_handler)
+{
+ int ret;
+
+ ret = bbu_register_handler(&imx_handler->handler);
+ if (ret)
+ free(imx_handler);
+
+ return ret;
+}
+
+/*
+ * Register a i.MX51 internal boot update handler for MMC/SD
+ */
+int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+ unsigned long flags, struct imx_dcd_entry *dcd, int dcdsize)
+{
+ struct imx_internal_bbu_handler *imx_handler;
+
+ imx_handler = __init_handler(name, devicefile, flags);
+ imx_handler->dcd = dcd;
+ imx_handler->dcdsize = dcdsize;
+ imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
+ imx_handler->app_dest = 0x90000000;
+ imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART;
+ imx_handler->handler.handler = imx_bbu_internal_v1_update;
+
+ return __register_handler(imx_handler);
+}
+
+#define DCD_WR_CMD(len) cpu_to_be32(0xcc << 24 | (((len) & 0xffff) << 8) | 0x04)
+
+static int imx53_bbu_internal_init_dcd(struct imx_internal_bbu_handler *imx_handler,
+ void *dcd, int dcdsize)
+{
+ uint32_t *dcd32 = dcd;
+
+ /*
+ * The DCD data we have compiled in does not have a DCD_WR_CMD at
+ * the beginning. Instead it is contained in struct imx_flash_header_v2.
+ * This is necessary to generate the DCD size at compile time. If
+ * we are passed such a DCD data here, prepend a DCD_WR_CMD.
+ */
+ if ((*dcd32 & 0xff0000ff) != DCD_WR_CMD(0)) {
+ __be32 *buf;
+
+ debug("%s: dcd does not have a DCD_WR_CMD. Prepending one\n");
+
+ buf = xmalloc(dcdsize + sizeof(__be32));
+
+ *buf = DCD_WR_CMD(dcdsize + sizeof(__be32));
+ memcpy(&buf[1], dcd, dcdsize);
+
+ imx_handler->dcd = buf;
+ imx_handler->dcdsize = dcdsize + sizeof(__be32);
+ } else {
+ debug("%s: dcd already has a DCD_WR_CMD. Using original dcd data\n");
+
+ imx_handler->dcd = dcd;
+ imx_handler->dcdsize = dcdsize;
+ }
+
+ return 0;
+}
+
+/*
+ * Register a i.MX53 internal boot update handler for MMC/SD
+ */
+int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+ unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize)
+{
+ struct imx_internal_bbu_handler *imx_handler;
+
+ imx_handler = __init_handler(name, devicefile, flags);
+ imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize);
+ imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
+ imx_handler->app_dest = 0x70000000;
+ imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART;
+ imx_handler->handler.handler = imx_bbu_internal_v2_update;
+
+ return __register_handler(imx_handler);
+}
+
+/*
+ * Register a i.MX53 internal boot update handler for NAND
+ */
+int imx53_bbu_internal_nand_register_handler(const char *name,
+ unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
+ int partition_size)
+{
+ struct imx_internal_bbu_handler *imx_handler;
+
+ imx_handler = __init_handler(name, NULL, flags);
+ imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize);
+ imx_handler->flash_header_offset = 0x400;
+ imx_handler->app_dest = 0x70000000;
+ imx_handler->handler.handler = imx_bbu_internal_v2_update;
+ imx_handler->flags = IMX_INTERNAL_FLAG_NAND;
+ imx_handler->handler.devicefile = "/dev/nand0";
+ imx_handler->device_size = partition_size;
+
+ return __register_handler(imx_handler);
+}
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
new file mode 100644
index 0000000000..d36f3d9443
--- /dev/null
+++ b/arch/arm/mach-imx/imx.c
@@ -0,0 +1,31 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <mach/revision.h>
+
+static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN;
+
+int imx_silicon_revision(void)
+{
+ return __imx_silicon_revision;
+}
+
+void imx_set_silicon_revision(const char *soc, int revision)
+{
+ __imx_silicon_revision = revision;
+
+ printf("detected %s revision %d.%d\n", soc,
+ (revision >> 4) & 0xf,
+ revision & 0xf);
+}
diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index 790e4535d7..18901ea6d0 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -14,8 +14,34 @@
#include <common.h>
#include <init.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/imx1-regs.h>
#include <mach/weim.h>
+#include <mach/iomux-v1.h>
+#include <reset_source.h>
+
+#define MX1_RSR MX1_SCM_BASE_ADDR
+#define RSR_EXR (1 << 0)
+#define RSR_WDR (1 << 1)
+
+static void imx1_detect_reset_source(void)
+{
+ u32 val = readl((void *)MX1_RSR) & 0x3;
+
+ switch (val) {
+ case RSR_EXR:
+ set_reset_source(RESET_RST);
+ return;
+ case RSR_WDR:
+ set_reset_source(RESET_WDG);
+ return;
+ case 0:
+ set_reset_source(RESET_POR);
+ return;
+ default:
+ /* else keep the default 'unknown' state */
+ return;
+ }
+}
void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
{
@@ -25,12 +51,16 @@ void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
static int imx1_init(void)
{
+ imx_iomuxv1_init((void *)MX1_GPIO1_BASE_ADDR);
+ imx1_detect_reset_source();
+
add_generic_device("imx1-ccm", 0, NULL, MX1_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpt", 0, NULL, MX1_TIM1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 0, NULL, MX1_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 1, NULL, MX1_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 2, NULL, MX1_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 3, NULL, MX1_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx1-wdt", 0, NULL, MX1_WDT_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index 7ed0809760..cddf3c088e 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -14,8 +14,9 @@
#include <common.h>
#include <init.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/imx21-regs.h>
#include <mach/weim.h>
+#include <mach/iomux-v1.h>
void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
{
@@ -23,16 +24,10 @@ void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower)
writel(lower, MX21_EIM_BASE_ADDR + 4 + cs * 8);
}
-int imx_silicon_revision(void)
-{
- // Known values:
- // 0x101D101D : mask set ID 0M55B
- // 0x201D101D : mask set ID 1M55B or M55B
- return CID;
-}
-
static int imx21_init(void)
{
+ imx_iomuxv1_init((void *)MX21_GPIO1_BASE_ADDR);
+
add_generic_device("imx21-ccm", 0, NULL, MX21_CCM_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpt", 0, NULL, MX21_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 0, NULL, MX21_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
@@ -41,6 +36,7 @@ static int imx21_init(void)
add_generic_device("imx-gpio", 3, NULL, MX21_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 4, NULL, MX21_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 5, NULL, MX21_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx21-wdt", 0, NULL, MX21_WDOG_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 5e6532a8f9..3bd95c146a 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -13,10 +13,11 @@
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <mach/iim.h>
#include <io.h>
#include <mach/weim.h>
+#include <mach/generic.h>
#include <sizes.h>
void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
@@ -58,6 +59,12 @@ static struct imx_iim_platform_data imx25_iim_pdata = {
static int imx25_init(void)
{
+ uint32_t val;
+
+ val = readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR);
+ imx_25_35_boot_save_loc((val >> MX25_CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
+ (val >> MX25_CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
+
add_generic_device("imx_iim", 0, NULL, MX25_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, &imx25_iim_pdata);
@@ -67,6 +74,7 @@ static int imx25_init(void)
add_generic_device("imx31-gpio", 1, NULL, MX25_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 2, NULL, MX25_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 3, NULL, MX25_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx21-wdt", 0, NULL, MX25_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index 8116e6f932..a0a510f5ab 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -12,15 +12,40 @@
*/
#include <common.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/weim.h>
+#include <mach/iomux-v1.h>
#include <sizes.h>
+#include <mach/revision.h>
+#include <mach/generic.h>
#include <init.h>
#include <io.h>
-int imx_silicon_revision(void)
+static int imx27_silicon_revision(void)
{
- return CID >> 28;
+ uint32_t val;
+ int rev;
+
+ val = readl(MX27_SYSCTRL_BASE_ADDR);
+
+ switch (val >> 28) {
+ case 0:
+ rev = IMX_CHIP_REV_1_0;
+ break;
+ case 1:
+ rev = IMX_CHIP_REV_2_0;
+ break;
+ case 2:
+ rev = IMX_CHIP_REV_2_1;
+ break;
+ default:
+ rev = IMX_CHIP_REV_UNKNOWN;
+ break;
+ }
+
+ imx_set_silicon_revision("i.MX27", rev);
+
+ return 0;
}
void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
@@ -73,6 +98,11 @@ static void imx27_init_max(void)
static int imx27_init(void)
{
+ imx27_silicon_revision();
+ imx_27_boot_save_loc((void *)MX27_SYSCTRL_BASE_ADDR);
+
+ imx_iomuxv1_init((void *)MX27_GPIO1_BASE_ADDR);
+
add_generic_device("imx_iim", 0, NULL, MX27_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
@@ -86,6 +116,7 @@ static int imx27_init(void)
add_generic_device("imx1-gpio", 3, NULL, MX27_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 4, NULL, MX27_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx1-gpio", 5, NULL, MX27_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
+ add_generic_device("imx21-wdt", 0, NULL, MX27_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index 90eee0a209..b2f0724bd1 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -15,7 +15,7 @@
#include <init.h>
#include <sizes.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/imx31-regs.h>
#include <mach/weim.h>
void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
@@ -31,11 +31,13 @@ static int imx31_init(void)
add_generic_device("imx_iim", 0, NULL, MX31_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-iomux", 0, NULL, MX31_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-ccm", 0, NULL, MX31_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX31_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 0, NULL, MX31_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 1, NULL, MX31_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx21-wdt", 0, NULL, MX31_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 722dd4c38c..737eb3a3a8 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -16,8 +16,9 @@
#include <init.h>
#include <io.h>
#include <mach/weim.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/iim.h>
+#include <mach/revision.h>
#include <mach/generic.h>
void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
@@ -28,14 +29,14 @@ void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
writel(additional, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x8);
}
-int imx_silicon_revision()
+static void imx35_silicon_revision(void)
{
uint32_t reg;
reg = readl(MX35_IIM_BASE_ADDR + IIM_SREV);
/* 0×00 = TO 1.0, First silicon */
reg += IMX_CHIP_REV_1_0;
- return (reg & 0xFF);
+ imx_set_silicon_revision("i.MX35", reg & 0xFF);
}
/*
@@ -58,14 +59,24 @@ core_initcall(imx35_l2_fix);
static int imx35_init(void)
{
+ uint32_t val;
+
+ imx35_silicon_revision();
+
+ val = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
+ imx_25_35_boot_save_loc((val >> MX35_CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
+ (val >> MX35_CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
+
add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx-iomuxv3", 0, NULL, MX35_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx35-ccm", 0, NULL, MX35_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX35_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 0, NULL, MX35_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 1, NULL, MX35_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx-gpio", 2, NULL, MX35_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx21-wdt", 0, NULL, MX35_WDOG_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 8709c43ac2..f5a867be3f 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -17,69 +17,58 @@
#include <environment.h>
#include <io.h>
#include <mach/imx5.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
+#include <mach/revision.h>
#include <mach/clock-imx51_53.h>
+#include <mach/generic.h>
#define SI_REV 0x48
-static u32 mx51_silicon_revision;
-static char *mx51_rev_string = "unknown";
-
-int imx_silicon_revision(void)
-{
- return mx51_silicon_revision;
-}
-
-static int query_silicon_revision(void)
+static int imx51_silicon_revision(void)
{
void __iomem *rom = MX51_IROM_BASE_ADDR;
+ u32 mx51_silicon_revision;
u32 rev;
rev = readl(rom + SI_REV);
switch (rev) {
case 0x1:
mx51_silicon_revision = IMX_CHIP_REV_1_0;
- mx51_rev_string = "1.0";
break;
case 0x2:
mx51_silicon_revision = IMX_CHIP_REV_1_1;
- mx51_rev_string = "1.1";
break;
case 0x10:
mx51_silicon_revision = IMX_CHIP_REV_2_0;
- mx51_rev_string = "2.0";
break;
case 0x20:
mx51_silicon_revision = IMX_CHIP_REV_3_0;
- mx51_rev_string = "3.0";
break;
default:
mx51_silicon_revision = 0;
}
- return 0;
-}
-core_initcall(query_silicon_revision);
-
-static int imx51_print_silicon_rev(void)
-{
- printf("detected i.MX51 rev %s\n", mx51_rev_string);
+ imx_set_silicon_revision("i.MX51", mx51_silicon_revision);
return 0;
}
-device_initcall(imx51_print_silicon_rev);
static int imx51_init(void)
{
+ imx51_silicon_revision();
+ imx51_boot_save_loc((void *)MX51_SRC_BASE_ADDR);
+
add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx-iomuxv3", 0, NULL, MX51_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx51-ccm", 0, NULL, MX51_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX51_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX51_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 1, NULL, MX51_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 2, NULL, MX51_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 3, NULL, MX51_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx21-wdt", 0, NULL, MX51_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
@@ -104,73 +93,6 @@ postcore_initcall(imx51_init);
* power up.
*/
-#define SRC_SBMR 0x4
-#define SBMR_BT_MEM_TYPE_SHIFT 7
-#define SBMR_BT_MEM_CTL_SHIFT 0
-#define SBMR_BMOD_SHIFT 14
-
-static int imx51_boot_save_loc(void)
-{
- const char *bareboxloc = NULL;
- uint32_t reg;
- unsigned int ctrl, type;
-
- /* [CTRL][TYPE] */
- const char *const locations[4][4] = {
- { /* CTRL = WEIM */
- "nor",
- NULL,
- "onenand",
- NULL,
- }, { /* CTRL == NAND */
- "nand",
- "nand",
- "nand",
- "nand",
- }, { /* CTRL == reserved */
- NULL,
- NULL,
- NULL,
- NULL,
- }, { /* CTRL == expansion */
- "mmc",
- NULL,
- "i2c",
- "spi",
- }
- };
-
- reg = readl(MX51_SRC_BASE_ADDR + SRC_SBMR);
-
- switch ((reg >> SBMR_BMOD_SHIFT) & 0x3) {
- case 0:
- case 2:
- /* internal boot */
- ctrl = (reg >> SBMR_BT_MEM_CTL_SHIFT) & 0x3;
- type = (reg >> SBMR_BT_MEM_TYPE_SHIFT) & 0x3;
-
- bareboxloc = locations[ctrl][type];
- break;
- case 1:
- /* reserved */
- bareboxloc = "unknown";
- break;
- case 3:
- bareboxloc = "serial";
- break;
-
- }
-
- if (bareboxloc) {
- setenv("barebox_loc", bareboxloc);
- export("barebox_loc");
- }
-
- return 0;
-}
-
-coredevice_initcall(imx51_boot_save_loc);
-
#define setup_pll_800(base) imx5_setup_pll((base), 800, (( 8 << 4) + ((1 - 1) << 0)), ( 3 - 1), 1)
#define setup_pll_665(base) imx5_setup_pll((base), 665, (( 6 << 4) + ((1 - 1) << 0)), (96 - 1), 89)
#define setup_pll_600(base) imx5_setup_pll((base), 600, (( 6 << 4) + ((1 - 1) << 0)), ( 4 - 1), 1)
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 88b4274fd5..e424e7d903 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -17,59 +17,48 @@
#include <notifier.h>
#include <sizes.h>
#include <mach/imx5.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
+#include <mach/revision.h>
#include <mach/clock-imx51_53.h>
+#include <mach/generic.h>
#define SI_REV 0x48
-static u32 mx53_silicon_revision;
-static char *mx53_rev_string = "unknown";
-
-int imx_silicon_revision(void)
-{
- return mx53_silicon_revision;
-}
-
-static int query_silicon_revision(void)
+static int imx53_silicon_revision(void)
{
void __iomem *rom = MX53_IROM_BASE_ADDR;
u32 rev;
+ u32 mx53_silicon_revision;
rev = readl(rom + SI_REV);
switch (rev) {
case 0x10:
mx53_silicon_revision = IMX_CHIP_REV_1_0;
- mx53_rev_string = "1.0";
break;
case 0x20:
mx53_silicon_revision = IMX_CHIP_REV_2_0;
- mx53_rev_string = "2.0";
break;
case 0x21:
mx53_silicon_revision = IMX_CHIP_REV_2_1;
- mx53_rev_string = "2.1";
break;
default:
mx53_silicon_revision = 0;
}
- return 0;
-}
-core_initcall(query_silicon_revision);
-
-static int imx53_print_silicon_rev(void)
-{
- printf("detected i.MX53 rev %s\n", mx53_rev_string);
+ imx_set_silicon_revision("i.MX53", mx53_silicon_revision);
return 0;
}
-device_initcall(imx53_print_silicon_rev);
static int imx53_init(void)
{
+ imx53_silicon_revision();
+ imx53_boot_save_loc((void *)MX53_SRC_BASE_ADDR);
+
add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
+ add_generic_device("imx-iomuxv3", 0, NULL, MX53_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx53-ccm", 0, NULL, MX53_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, 0X53fa0000, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX53_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
@@ -79,6 +68,7 @@ static int imx53_init(void)
add_generic_device("imx31-gpio", 4, NULL, MX53_GPIO5_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 5, NULL, MX53_GPIO6_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 6, NULL, MX53_GPIO7_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx21-wdt", 0, NULL, MX53_WDOG1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
@@ -203,6 +193,8 @@ void imx53_init_lowlevel(unsigned int cpufreq_mhz)
writel(0xffffffff, ccm + MX5_CCM_CCGR6);
writel(0xffffffff, ccm + MX53_CCM_CCGR7);
- clock_notifier_call_chain();
+ if (!IS_ENABLED(__PBL__))
+ clock_notifier_call_chain();
+
writel(0, ccm + MX5_CCM_CCDR);
}
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index a5ec36471e..c9eec5ab75 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -54,6 +54,7 @@ void imx6_init_lowlevel(void)
static int imx6_init(void)
{
+ add_generic_device("imx-iomuxv3", 0, NULL, MX6_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx6-ccm", 0, NULL, MX6_CCM_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, 0x02098000, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
@@ -63,6 +64,7 @@ static int imx6_init(void)
add_generic_device("imx31-gpio", 4, NULL, MX6_GPIO5_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 5, NULL, MX6_GPIO6_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 6, NULL, MX6_GPIO7_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx21-wdt", 0, NULL, MX6_WDOG1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h
new file mode 100644
index 0000000000..f9ec1cc0af
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/bbu.h
@@ -0,0 +1,51 @@
+#ifndef __MACH_BBU_H
+#define __MACH_BBU_H
+
+#include <bbu.h>
+
+struct imx_dcd_entry;
+struct imx_dcd_v2_entry;
+
+#ifdef CONFIG_BAREBOX_UPDATE
+
+int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+ unsigned long flags, struct imx_dcd_entry *, int dcdsize);
+
+int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+ unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize);
+
+int imx53_bbu_internal_nand_register_handler(const char *name,
+ unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize,
+ int partition_size);
+
+#else
+
+static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+ unsigned long flags, struct imx_dcd_entry *dcd, int dcdsize)
+{
+ return -ENOSYS;
+}
+
+static inline int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+ unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize)
+{
+ return -ENOSYS;
+}
+
+static inline int imx53_bbu_internal_nand_register_handler(const char *name,
+ unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
+ int partition_size)
+{
+ return -ENOSYS;
+}
+
+#endif
+
+struct dcd_table {
+ void *data;
+ unsigned int size;
+};
+
+void *imx53_bbu_internal_concat_dcd_table(struct dcd_table *table, int num_entries);
+
+#endif
diff --git a/arch/arm/mach-imx/include/mach/devices-imx1.h b/arch/arm/mach-imx/include/mach/devices-imx1.h
index c73113cf64..391c1a9c8e 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx1.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx1.h
@@ -2,10 +2,10 @@
static inline struct device_d *imx1_add_uart0(void)
{
- return imx_add_uart((void *)MX1_UART1_BASE_ADDR, 0);
+ return imx_add_uart_imx1((void *)MX1_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx1_add_uart1(void)
{
- return imx_add_uart((void *)MX1_UART2_BASE_ADDR, 1);
+ return imx_add_uart_imx1((void *)MX1_UART2_BASE_ADDR, 1);
}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx21.h b/arch/arm/mach-imx/include/mach/devices-imx21.h
index 31c5f8c17b..ad7ee5ed02 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx21.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx21.h
@@ -3,22 +3,22 @@
static inline struct device_d *imx21_add_uart0(void)
{
- return imx_add_uart((void *)MX21_UART1_BASE_ADDR, 0);
+ return imx_add_uart_imx21((void *)MX21_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx21_add_uart1(void)
{
- return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 1);
+ return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx21_add_uart2(void)
{
- return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 2);
+ return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 2);
}
static inline struct device_d *imx21_add_uart3(void)
{
- return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 3);
+ return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 3);
}
static inline struct device_d *imx21_add_nand(struct imx_nand_platform_data *pdata)
diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h
index 86cda35a43..a655be9564 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx25.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx25.h
@@ -33,27 +33,27 @@ static inline struct device_d *imx25_add_spi2(struct spi_imx_master *pdata)
static inline struct device_d *imx25_add_uart0(void)
{
- return imx_add_uart((void *)MX25_UART1_BASE_ADDR, 0);
+ return imx_add_uart_imx21((void *)MX25_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx25_add_uart1(void)
{
- return imx_add_uart((void *)MX25_UART2_BASE_ADDR, 1);
+ return imx_add_uart_imx21((void *)MX25_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx25_add_uart2(void)
{
- return imx_add_uart((void *)MX25_UART3_BASE_ADDR, 2);
+ return imx_add_uart_imx21((void *)MX25_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx25_add_uart3(void)
{
- return imx_add_uart((void *)MX25_UART4_BASE_ADDR, 3);
+ return imx_add_uart_imx21((void *)MX25_UART4_BASE_ADDR, 3);
}
static inline struct device_d *imx25_add_uart4(void)
{
- return imx_add_uart((void *)MX25_UART5_BASE_ADDR, 4);
+ return imx_add_uart_imx21((void *)MX25_UART5_BASE_ADDR, 4);
}
static inline struct device_d *imx25_add_nand(struct imx_nand_platform_data *pdata)
@@ -68,7 +68,7 @@ static inline struct device_d *imx25_add_fb(struct imx_fb_platform_data *pdata)
static inline struct device_d *imx25_add_fec(struct fec_platform_data *pdata)
{
- return imx_add_fec((void *)MX25_FEC_BASE_ADDR, pdata);
+ return imx_add_fec_imx27((void *)MX25_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx25_add_mmc0(struct esdhc_platform_data *pdata)
diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h
index 2799343e59..79da93531d 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx27.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx27.h
@@ -23,22 +23,22 @@ static inline struct device_d *imx27_add_i2c1(struct i2c_platform_data *pdata)
static inline struct device_d *imx27_add_uart0(void)
{
- return imx_add_uart((void *)MX27_UART1_BASE_ADDR, 0);
+ return imx_add_uart_imx21((void *)MX27_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx27_add_uart1(void)
{
- return imx_add_uart((void *)MX27_UART2_BASE_ADDR, 1);
+ return imx_add_uart_imx21((void *)MX27_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx27_add_uart2(void)
{
- return imx_add_uart((void *)MX27_UART3_BASE_ADDR, 2);
+ return imx_add_uart_imx21((void *)MX27_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx27_add_uart3(void)
{
- return imx_add_uart((void *)MX27_UART4_BASE_ADDR, 3);
+ return imx_add_uart_imx21((void *)MX27_UART4_BASE_ADDR, 3);
}
static inline struct device_d *imx27_add_nand(struct imx_nand_platform_data *pdata)
@@ -53,7 +53,7 @@ static inline struct device_d *imx27_add_fb(struct imx_fb_platform_data *pdata)
static inline struct device_d *imx27_add_fec(struct fec_platform_data *pdata)
{
- return imx_add_fec((void *)MX27_FEC_BASE_ADDR, pdata);
+ return imx_add_fec_imx27((void *)MX27_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx27_add_mmc0(void *pdata)
diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h
index d45e4e1027..fe719301ad 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx31.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx31.h
@@ -1,5 +1,5 @@
-#include <mach/imx-regs.h>
+#include <mach/imx31-regs.h>
#include <mach/devices.h>
static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata)
@@ -19,27 +19,27 @@ static inline struct device_d *imx31_add_spi2(struct spi_imx_master *pdata)
static inline struct device_d *imx31_add_uart0(void)
{
- return imx_add_uart((void *)MX31_UART1_BASE_ADDR, 0);
+ return imx_add_uart_imx21((void *)MX31_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx31_add_uart1(void)
{
- return imx_add_uart((void *)MX31_UART2_BASE_ADDR, 1);
+ return imx_add_uart_imx21((void *)MX31_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx31_add_uart2(void)
{
- return imx_add_uart((void *)MX31_UART3_BASE_ADDR, 2);
+ return imx_add_uart_imx21((void *)MX31_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx31_add_uart3(void)
{
- return imx_add_uart((void *)MX31_UART4_BASE_ADDR, 3);
+ return imx_add_uart_imx21((void *)MX31_UART4_BASE_ADDR, 3);
}
static inline struct device_d *imx31_add_uart4(void)
{
- return imx_add_uart((void *)MX31_UART5_BASE_ADDR, 4);
+ return imx_add_uart_imx21((void *)MX31_UART5_BASE_ADDR, 4);
}
static inline struct device_d *imx31_add_nand(struct imx_nand_platform_data *pdata)
diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h
index 27c49e7161..912c41872e 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx35.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx35.h
@@ -28,17 +28,17 @@ static inline struct device_d *imx35_add_spi(struct spi_imx_master *pdata)
static inline struct device_d *imx35_add_uart0(void)
{
- return imx_add_uart((void *)MX35_UART1_BASE_ADDR, 0);
+ return imx_add_uart_imx21((void *)MX35_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx35_add_uart1(void)
{
- return imx_add_uart((void *)MX35_UART2_BASE_ADDR, 1);
+ return imx_add_uart_imx21((void *)MX35_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx35_add_uart2(void)
{
- return imx_add_uart((void *)MX35_UART3_BASE_ADDR, 2);
+ return imx_add_uart_imx21((void *)MX35_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata)
@@ -53,7 +53,7 @@ static inline struct device_d *imx35_add_fb(struct imx_ipu_fb_platform_data *pda
static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata)
{
- return imx_add_fec((void *)MX35_FEC_BASE_ADDR, pdata);
+ return imx_add_fec_imx27((void *)MX35_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx35_add_mmc0(struct esdhc_platform_data *pdata)
diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h
index 4b35c96e21..8ee3c17478 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx51.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx51.h
@@ -29,22 +29,22 @@ static inline struct device_d *imx51_add_i2c1(struct i2c_platform_data *pdata)
static inline struct device_d *imx51_add_uart0(void)
{
- return imx_add_uart((void *)MX51_UART1_BASE_ADDR, 0);
+ return imx_add_uart_imx21((void *)MX51_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx51_add_uart1(void)
{
- return imx_add_uart((void *)MX51_UART2_BASE_ADDR, 1);
+ return imx_add_uart_imx21((void *)MX51_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx51_add_uart2(void)
{
- return imx_add_uart((void *)MX51_UART3_BASE_ADDR, 2);
+ return imx_add_uart_imx21((void *)MX51_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx51_add_fec(struct fec_platform_data *pdata)
{
- return imx_add_fec((void *)MX51_MXC_FEC_BASE_ADDR, pdata);
+ return imx_add_fec_imx27((void *)MX51_MXC_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx51_add_mmc0(struct esdhc_platform_data *pdata)
diff --git a/arch/arm/mach-imx/include/mach/devices-imx53.h b/arch/arm/mach-imx/include/mach/devices-imx53.h
index 54d7b27be1..5f967eaac2 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx53.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx53.h
@@ -23,22 +23,22 @@ static inline struct device_d *imx53_add_i2c1(struct i2c_platform_data *pdata)
static inline struct device_d *imx53_add_uart0(void)
{
- return imx_add_uart((void *)MX53_UART1_BASE_ADDR, 0);
+ return imx_add_uart_imx21((void *)MX53_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx53_add_uart1(void)
{
- return imx_add_uart((void *)MX53_UART2_BASE_ADDR, 1);
+ return imx_add_uart_imx21((void *)MX53_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx53_add_uart2(void)
{
- return imx_add_uart((void *)MX53_UART3_BASE_ADDR, 2);
+ return imx_add_uart_imx21((void *)MX53_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx53_add_fec(struct fec_platform_data *pdata)
{
- return imx_add_fec((void *)MX53_FEC_BASE_ADDR, pdata);
+ return imx_add_fec_imx27((void *)MX53_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx53_add_mmc0(struct esdhc_platform_data *pdata)
diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h
index c73e4888ed..f8282e7fca 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx6.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx6.h
@@ -2,22 +2,22 @@
static inline struct device_d *imx6_add_uart0(void)
{
- return imx_add_uart((void *)MX6_UART1_BASE_ADDR, 0);
+ return imx_add_uart_imx21((void *)MX6_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx6_add_uart1(void)
{
- return imx_add_uart((void *)MX6_UART2_BASE_ADDR, 1);
+ return imx_add_uart_imx21((void *)MX6_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx6_add_uart2(void)
{
- return imx_add_uart((void *)MX6_UART3_BASE_ADDR, 2);
+ return imx_add_uart_imx21((void *)MX6_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx6_add_uart3(void)
{
- return imx_add_uart((void *)MX6_UART4_BASE_ADDR, 3);
+ return imx_add_uart_imx21((void *)MX6_UART4_BASE_ADDR, 3);
}
static inline struct device_d *imx6_add_mmc0(struct esdhc_platform_data *pdata)
@@ -42,7 +42,7 @@ static inline struct device_d *imx6_add_mmc3(struct esdhc_platform_data *pdata)
static inline struct device_d *imx6_add_fec(struct fec_platform_data *pdata)
{
- return imx_add_fec((void *)MX6_ENET_BASE_ADDR, pdata);
+ return imx_add_fec_imx6((void *)MX6_ENET_BASE_ADDR, pdata);
}
static inline struct device_d *imx6_add_spi0(struct spi_imx_master *pdata)
diff --git a/arch/arm/mach-imx/include/mach/devices.h b/arch/arm/mach-imx/include/mach/devices.h
index da9164616e..f7824f5406 100644
--- a/arch/arm/mach-imx/include/mach/devices.h
+++ b/arch/arm/mach-imx/include/mach/devices.h
@@ -8,10 +8,12 @@
#include <mach/imx-ipu-fb.h>
#include <mach/esdhc.h>
-struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata);
+struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata);
+struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata);
struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata);
struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata);
-struct device_d *imx_add_uart(void *base, int id);
+struct device_d *imx_add_uart_imx1(void *base, int id);
+struct device_d *imx_add_uart_imx21(void *base, int id);
struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata);
struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata);
struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata);
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 10c8b9bd8e..8124c870e9 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -1,10 +1,10 @@
/* SDRAM Controller registers */
-#define ESDCTL0 (IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0 */
-#define ESDCFG0 (IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */
-#define ESDCTL1 (IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1 */
-#define ESDCFG1 (IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */
-#define ESDMISC (IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register */
+#define IMX_ESDCTL0 0x00 /* Enhanced SDRAM Control Register 0 */
+#define IMX_ESDCFG0 0x04 /* Enhanced SDRAM Configuration Register 0 */
+#define IMX_ESDCTL1 0x08 /* Enhanced SDRAM Control Register 1 */
+#define IMX_ESDCFG1 0x0C /* Enhanced SDRAM Configuration Register 1 */
+#define IMX_ESDMISC 0x10 /* Enhanced SDRAM Miscellanious Register */
#define ESDCTL0_SDE (1 << 31)
#define ESDCTL0_SMODE_NORMAL (0 << 28)
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 99f301205c..39bb7e351e 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -1,10 +1,29 @@
-int imx_silicon_revision(void);
-#define IMX27_CHIP_REVISION_1_0 0
-#define IMX27_CHIP_REVISION_2_0 1
-
u64 imx_uid(void);
+enum imx_bootsource {
+ bootsource_unknown,
+ bootsource_nand,
+ bootsource_nor,
+ bootsource_mmc,
+ bootsource_i2c,
+ bootsource_spi,
+ bootsource_serial,
+ bootsource_onenand,
+ bootsource_hd,
+};
+
+enum imx_bootsource imx_bootsource(void);
+void imx_set_bootsource(enum imx_bootsource src);
+
+int imx_25_35_boot_save_loc(unsigned int ctrl, unsigned int type);
+void imx_27_boot_save_loc(void __iomem *sysctrl_base);
+int imx51_boot_save_loc(void __iomem *src_base);
+int imx53_boot_save_loc(void __iomem *src_base);
+
+/* There's a off-by-one betweem the gpio bank number and the gpiochip */
+/* range e.g. GPIO_1_5 is gpio 5 under linux */
+#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
#ifdef CONFIG_ARCH_IMX1
#define cpu_is_mx1() (1)
diff --git a/arch/arm/mach-imx/include/mach/gpio.h b/arch/arm/mach-imx/include/mach/gpio.h
index 0ebc3f939f..489ae2cf09 100644
--- a/arch/arm/mach-imx/include/mach/gpio.h
+++ b/arch/arm/mach-imx/include/mach/gpio.h
@@ -1,11 +1,8 @@
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
+#include <asm-generic/gpio.h>
+
void imx_gpio_mode(int gpio_mode);
-void gpio_set_value(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_direction_input(unsigned gpio);
#endif /* __ASM_ARCH_GPIO_H */
-
diff --git a/arch/arm/mach-imx/include/mach/imx-flash-header.h b/arch/arm/mach-imx/include/mach/imx-flash-header.h
index a51d4736fa..9a351ad74a 100644
--- a/arch/arm/mach-imx/include/mach/imx-flash-header.h
+++ b/arch/arm/mach-imx/include/mach/imx-flash-header.h
@@ -120,7 +120,9 @@ struct imx_dcd_command {
struct imx_dcd {
struct imx_ivt_header header;
+#ifndef IMX_INTERNAL_NAND_BBU
struct imx_dcd_command command;
+#endif
};
struct imx_boot_data {
@@ -144,4 +146,37 @@ struct imx_flash_header_v2 {
struct imx_dcd dcd;
};
+/*
+ * A variant of the standard barebox header in the i.MX FCB
+ * format. Needed for i.MX53 NAND boot
+ */
+static inline void barebox_arm_imx_fcb_head(void)
+{
+ __asm__ __volatile__ (
+ ".arm\n"
+ " b 1f\n"
+ ".word 0x20424346\n" /* FCB */
+ ".word 0x1\n"
+#ifdef CONFIG_THUMB2_BAREBOX
+ "1: adr r9, 1f + 1\n"
+ " bx r9\n"
+ ".thumb\n"
+ "1:\n"
+ "bl reset\n"
+#else
+ "1: b reset\n"
+ ".word 0x0\n"
+ ".word 0x0\n"
+#endif
+ ".word 0x0\n"
+ ".word 0x0\n"
+
+ ".asciz \"barebox\"\n"
+ ".word _text\n" /* text base. If copied there,
+ * barebox can skip relocation
+ */
+ ".word _barebox_image_size\n" /* image size to copy */
+ );
+}
+
#endif /* __MACH_FLASH_HEADER_H */
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
deleted file mode 100644
index 235bac3b82..0000000000
--- a/arch/arm/mach-imx/include/mach/imx-regs.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _IMX_REGS_H
-#define _IMX_REGS_H
-
-/* ------------------------------------------------------------------------
- * Motorola IMX system registers
- * ------------------------------------------------------------------------
- */
-
-# ifndef __ASSEMBLY__
-# define __REG(x) (*((volatile u32 *)(x)))
-# define __REG16(x) (*(volatile u16 *)(x))
-# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-# define __REG(x) (x)
-# define __REG16(x) (x)
-# define __REG2(x,y) ((x)+(y))
-#endif
-
-#ifdef CONFIG_ARCH_IMX1
-# include <mach/imx1-regs.h>
-#elif defined CONFIG_ARCH_IMX21
-# include <mach/imx21-regs.h>
-#elif defined CONFIG_ARCH_IMX27
-# include <mach/imx27-regs.h>
-#elif defined CONFIG_ARCH_IMX31
-# include <mach/imx31-regs.h>
-#elif defined CONFIG_ARCH_IMX35
-# include <mach/imx35-regs.h>
-#elif defined CONFIG_ARCH_IMX25
-# include <mach/imx25-regs.h>
-#elif defined CONFIG_ARCH_IMX51
-# include <mach/imx51-regs.h>
-#elif defined CONFIG_ARCH_IMX53
-# include <mach/imx53-regs.h>
-#elif defined CONFIG_ARCH_IMX6
-# include <mach/imx6-regs.h>
-#else
-# error "unknown i.MX soc type"
-#endif
-
-/* There's a off-by-one betweem the gpio bank number and the gpiochip */
-/* range e.g. GPIO_1_5 is gpio 5 under linux */
-#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
-
-#define GPIO_PIN_MASK 0x1f
-
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-
-#define GPIO_OUT (1 << 8)
-#define GPIO_IN (0 << 8)
-#define GPIO_PUEN (1 << 9)
-
-#define GPIO_PF (1 << 10)
-#define GPIO_AF (1 << 11)
-
-#define GPIO_OCR_SHIFT 12
-#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
-#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
-#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
-#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
-#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
-
-#define GPIO_AOUT_SHIFT 14
-#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
-
-#define GPIO_BOUT_SHIFT 16
-#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
-
-#define GPIO_GIUS (1<<16)
-
-/* silicon revisions */
-#define IMX_CHIP_REV_1_0 0x10
-#define IMX_CHIP_REV_1_1 0x11
-#define IMX_CHIP_REV_1_2 0x12
-#define IMX_CHIP_REV_1_3 0x13
-#define IMX_CHIP_REV_2_0 0x20
-#define IMX_CHIP_REV_2_1 0x21
-#define IMX_CHIP_REV_2_2 0x22
-#define IMX_CHIP_REV_2_3 0x23
-#define IMX_CHIP_REV_3_0 0x30
-#define IMX_CHIP_REV_3_1 0x31
-#define IMX_CHIP_REV_3_2 0x32
-
-#endif /* _IMX_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h
index cb60c84d31..df6ede5b24 100644
--- a/arch/arm/mach-imx/include/mach/imx1-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx1-regs.h
@@ -59,161 +59,25 @@
#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
-/* FIXME: get rid of these */
-#define IMX_TIM1_BASE MX1_CCM_BASE_ADDR
-#define IMX_WDT_BASE MX1_WDT_BASE_ADDR
-#define IMX_GPIO_BASE MX1_GPIO_BASE_ADDR
-
-/* SYSCTRL Registers */
-#define SIDR __REG(MX1_SCM_BASE_ADDR + 0x4) /* Silicon ID Register */
-#define FMCR __REG(MX1_SCM_BASE_ADDR + 0x8) /* Function Multiplex Control Register */
-#define GPCR __REG(MX1_SCM_BASE_ADDR + 0xC) /* Function Multiplex Control Register */
-
-/* SDRAM controller registers */
-
-#define SDCTL0 __REG(MX1_SDRAMC_BASE_ADDR) /* SDRAM 0 Control Register */
-#define SDCTL1 __REG(MX1_SDRAMC_BASE_ADDR + 0x4) /* SDRAM 1 Control Register */
-#define SDMISC __REG(MX1_SDRAMC_BASE_ADDR + 0x14) /* Miscellaneous Register */
-#define SDRST __REG(MX1_SDRAMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */
-
-/* PLL registers */
-#define CSCR __REG(MX1_CCM_BASE_ADDR) /* Clock Source Control Register */
-#define MPCTL0 __REG(MX1_CCM_BASE_ADDR + 0x4) /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x8) /* MCU PLL and System Clock Register 1 */
-#define SPCTL0 __REG(MX1_CCM_BASE_ADDR + 0xc) /* System PLL Control Register 0 */
-#define SPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
-#define PCDR __REG(MX1_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Divider Register */
-
-#define CSCR_MPLL_RESTART (1<<21)
-
-/* assignements for GPIO alternate/primary functions */
-
-/* FIXME: This list is not completed. The correct directions are
- * missing on some (many) pins
- */
-#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
-#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
-#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
-#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
-#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
-#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
-#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
-#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
-#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
-#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
-#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
-#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
-#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
-#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
-#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
-#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
-#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
-#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
-#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
-#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
-#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
-#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
-#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
-#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
-#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
-#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
-#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
-#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
-#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
-#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
-#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
-#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
-#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
-#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
-#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
-#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
-#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
-#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
-#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
-#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
-#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
-#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
-#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
-#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
-#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
-#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
-#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
-#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
-#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
-#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
-#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
-#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
-#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
-#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
-#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
-#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
-#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
-#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
-#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
-#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
-#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
-#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
-#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
-#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
-#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
-#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
-#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
-#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
-#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
-#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
-#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
-#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
-#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
-#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
-#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
-#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
-#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
-#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
-#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
-#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
-#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
-#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
-#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
-#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
-#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
-#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
-#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
-#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
-#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
-#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
-#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
-#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
-#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
-#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
-#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
-#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
-#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
-#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
-#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
-#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
-#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
-#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
-#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
-#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
-#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
-#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
-#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
-#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
-#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
-#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
-#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
-#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
-#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
-#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
-#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
-#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
-#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
-#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
-#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
-#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
-#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
-#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
-#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
-#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
+/* SYSCTRL Registers (base MX1_SCM_BASE_ADDR) */
+#define MX1_SIDR 0x4 /* Silicon ID Register */
+#define MX1_FMCR 0x8 /* Function Multiplex Control Register */
+#define MX1_GPCR 0xC /* Function Multiplex Control Register */
+
+/* SDRAM controller registers (base MX1_SDRAMC_BASE_ADDR) */
+#define MX1_SDCTL0 0x0 /* SDRAM 0 Control Register */
+#define MX1_SDCTL1 0x4 /* SDRAM 1 Control Register */
+#define MX1_SDMISC 0x14 /* Miscellaneous Register */
+#define MX1_SDRST 0x18 /* SDRAM Reset Register */
+
+/* PLL registers (base MX1_CCM_BASE_ADDR) */
+#define MX1_CSCR 0x0 /* Clock Source Control Register */
+#define MX1_MPCTL0 0x4 /* MCU PLL Control Register 0 */
+#define MX1_MPCTL1 0x8 /* MCU PLL and System Clock Register 1 */
+#define MX1_SPCTL0 0xc /* System PLL Control Register 0 */
+#define MX1_SPCTL1 0x10 /* System PLL Control Register 1 */
+#define MX1_PCDR 0x20 /* Peripheral Clock Divider Register */
+
+#define MX1_CSCR_MPLL_RESTART (1<<21)
#endif /* _IMX1_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h
index 9952b8bd1f..1c4b5507d3 100644
--- a/arch/arm/mach-imx/include/mach/imx21-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx21-regs.h
@@ -71,76 +71,70 @@
#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
-/* FIXME: Get rid of these */
-#define IMX_GPIO_BASE MX21_GPIO_BASE_ADDR
-#define IMX_TIM1_BASE MX21_GPT1_BASE_ADDR
-#define IMX_WDT_BASE MX21_WDOG_BASE_ADDR
-#define IMX_SYSTEM_CTL_BASE MX21_SYSCTRL_BASE_ADDR
-
-/* AIPI */
-#define AIPI1_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x00)
-#define AIPI1_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x04)
-#define AIPI2_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x00)
-#define AIPI2_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x04)
-
-/* System Control */
-#define SUID0 __REG(MX21_SYSCTRL_BASE_ADDR + 0x4) /* Silicon ID Register (12 bytes) */
-#define SUID1 __REG(MX21_SYSCTRL_BASE_ADDR + 0x8) /* Silicon ID Register (12 bytes) */
-#define CID __REG(MX21_SYSCTRL_BASE_ADDR + 0xC) /* Silicon ID Register (12 bytes) */
-#define FMCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */
-#define GPCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */
-#define WBCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */
-#define DSCR(x) __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
-
-#define GPCR_BOOT_SHIFT 16
-#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
-#define GPCR_BOOT_UART_USB 0
-#define GPCR_BOOT_8BIT_NAND_2k 2
-#define GPCR_BOOT_16BIT_NAND_2k 3
-#define GPCR_BOOT_16BIT_NAND_512 4
-#define GPCR_BOOT_16BIT_CS0 5
-#define GPCR_BOOT_32BIT_CS0 6
-#define GPCR_BOOT_8BIT_NAND_512 7
-
-/* SDRAM Controller registers bitfields */
-#define SDCTL0 __REG(MX21_X_MEMC_BASE_ADDR + 0x00) /* SDRAM 0 Control Register */
-#define SDCTL1 __REG(MX21_X_MEMC_BASE_ADDR + 0x04) /* SDRAM 0 Control Register */
-#define SDRST __REG(MX21_X_MEMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */
-#define SDMISC __REG(MX21_X_MEMC_BASE_ADDR + 0x14) /* SDRAM Miscellaneous Register */
-
-/* PLL registers */
-#define CSCR __REG(MX21_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */
-#define MPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */
-#define SPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */
-#define SPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
-#define OSC26MCTL __REG(MX21_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */
-#define PCDR0 __REG(MX21_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */
-#define PCDR1 __REG(MX21_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */
-#define PCCR0 __REG(MX21_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */
-#define PCCR1 __REG(MX21_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */
-#define CCSR __REG(MX21_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */
-
-#define CSCR_MPEN (1 << 0)
-#define CSCR_SPEN (1 << 1)
-#define CSCR_FPM_EN (1 << 2)
-#define CSCR_OSC26M_DIS (1 << 3)
-#define CSCR_OSC26M_DIV1P5 (1 << 4)
-#define CSCR_MCU_SEL (1 << 16)
-#define CSCR_SP_SEL (1 << 17)
-#define CSCR_SD_CNT(d) (((d) & 0x3) << 24)
-#define CSCR_USB_DIV(d) (((d) & 0x7) << 26)
-#define CSCR_PRESC(d) (((d) & 0x7) << 29)
-
-#define MPCTL1_BRMO (1 << 6)
-#define MPCTL1_LF (1 << 15)
-
-#define PCCR0_PERCLK3_EN (1 << 18)
-#define PCCR0_NFC_EN (1 << 19)
-#define PCCR0_HCLK_LCDC_EN (1 << 26)
-
-#define PCCR1_GPT1_EN (1 << 25)
-
-#define CCSR_32K_SR (1 << 15)
+/* AIPI (base MX21_AIPI_BASE_ADDR) */
+#define MX21_AIPI1_PSR0 0x00
+#define MX21_AIPI1_PSR1 0x04
+#define MX21_AIPI2_PSR0 (0x20000 + 0x00)
+#define MX21_AIPI2_PSR1 (0x20000 + 0x04)
+
+/* System Control (base: MX21_SYSCTRL_BASE_ADDR) */
+#define MX21_SUID0 0x4 /* Silicon ID Register (12 bytes) */
+#define MX21_SUID1 0x8 /* Silicon ID Register (12 bytes) */
+#define MX21_CID 0xC /* Silicon ID Register (12 bytes) */
+#define MX21_FMCR 0x14 /* Function Multeplexing Control Register */
+#define MX21_GPCR 0x18 /* Global Peripheral Control Register */
+#define MX21_WBCR 0x1C /* Well Bias Control Register */
+#define MX21_DSCR(x) 0x1C + ((x) << 2) /* Driving Strength Control Register 1 - 13 */
+
+#define MX21_GPCR_BOOT_SHIFT 16
+#define MX21_GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
+#define MX21_GPCR_BOOT_UART_USB 0
+#define MX21_GPCR_BOOT_8BIT_NAND_2k 2
+#define MX21_GPCR_BOOT_16BIT_NAND_2k 3
+#define MX21_GPCR_BOOT_16BIT_NAND_512 4
+#define MX21_GPCR_BOOT_16BIT_CS0 5
+#define MX21_GPCR_BOOT_32BIT_CS0 6
+#define MX21_GPCR_BOOT_8BIT_NAND_512 7
+
+/* SDRAM Controller registers bitfields (base: MX21_X_MEMC_BASE_ADDR) */
+#define MX21_SDCTL0 0x00 /* SDRAM 0 Control Register */
+#define MX21_SDCTL1 0x04 /* SDRAM 0 Control Register */
+#define MX21_SDRST 0x18 /* SDRAM Reset Register */
+#define MX21_SDMISC 0x14 /* SDRAM Miscellaneous Register */
+
+/* PLL registers (base: MX21_CCM_BASE_ADDR) */
+#define MX21_CSCR 0x00 /* Clock Source Control Register */
+#define MX21_MPCTL0 0x04 /* MCU PLL Control Register 0 */
+#define MX21_MPCTL1 0x08 /* MCU PLL Control Register 1 */
+#define MX21_SPCTL0 0x0c /* System PLL Control Register 0 */
+#define MX21_SPCTL1 0x10 /* System PLL Control Register 1 */
+#define MX21_OSC26MCTL 0x14 /* Oscillator 26M Register */
+#define MX21_PCDR0 0x18 /* Peripheral Clock Divider Register 0 */
+#define MX21_PCDR1 0x1c /* Peripheral Clock Divider Register 1 */
+#define MX21_PCCR0 0x20 /* Peripheral Clock Control Register 0 */
+#define MX21_PCCR1 0x24 /* Peripheral Clock Control Register 1 */
+#define MX21_CCSR 0x28 /* Clock Control Status Register */
+
+#define MX21_CSCR_MPEN (1 << 0)
+#define MX21_CSCR_SPEN (1 << 1)
+#define MX21_CSCR_FPM_EN (1 << 2)
+#define MX21_CSCR_OSC26M_DIS (1 << 3)
+#define MX21_CSCR_OSC26M_DIV1P5 (1 << 4)
+#define MX21_CSCR_MCU_SEL (1 << 16)
+#define MX21_CSCR_SP_SEL (1 << 17)
+#define MX21_CSCR_SD_CNT(d) (((d) & 0x3) << 24)
+#define MX21_CSCR_USB_DIV(d) (((d) & 0x7) << 26)
+#define MX21_CSCR_PRESC(d) (((d) & 0x7) << 29)
+
+#define MX21_MPCTL1_BRMO (1 << 6)
+#define MX21_MPCTL1_LF (1 << 15)
+
+#define MX21_PCCR0_PERCLK3_EN (1 << 18)
+#define MX21_PCCR0_NFC_EN (1 << 19)
+#define MX21_PCCR0_HCLK_LCDC_EN (1 << 26)
+
+#define MX21_PCCR1_GPT1_EN (1 << 25)
+
+#define MX21_CCSR_32K_SR (1 << 15)
#endif /* _IMX21_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
index 0bf6e119e0..b8ae45a787 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -76,46 +76,39 @@
#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
#define MX25_CSI_BASE_ADDR 0x53ff8000
-/* FIXME: Get rid of these */
-#define IMX_TIM1_BASE MX25_GPT1_BASE_ADDR
-#define IMX_IOMUXC_BASE MX25_IOMUXC_BASE_ADDR
-#define IMX_WDT_BASE MX25_WDOG_BASE_ADDR
-#define IMX_CCM_BASE MX25_CCM_BASE_ADDR
-#define IMX_ESD_BASE MX25_ESDCTL_BASE_ADDR
-
/*
* Clock Controller Module (CCM)
*/
-#define CCM_MPCTL 0x00
-#define CCM_UPCTL 0x04
-#define CCM_CCTL 0x08
-#define CCM_CGCR0 0x0C
-#define CCM_CGCR1 0x10
-#define CCM_CGCR2 0x14
-#define CCM_PCDR0 0x18
-#define CCM_PCDR1 0x1C
-#define CCM_PCDR2 0x20
-#define CCM_PCDR3 0x24
-#define CCM_RCSR 0x28
-#define CCM_CRDR 0x2C
-#define CCM_DCVR0 0x30
-#define CCM_DCVR1 0x34
-#define CCM_DCVR2 0x38
-#define CCM_DCVR3 0x3c
-#define CCM_LTR0 0x40
-#define CCM_LTR1 0x44
-#define CCM_LTR2 0x48
-#define CCM_LTR3 0x4c
-
-#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
-#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
-#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
-#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
-#define PDR0_AUTO_CON (1 << 0)
-#define PDR0_PER_SEL (1 << 26)
-
-#define CCM_RCSR_MEM_CTRL_SHIFT 30
-#define CCM_RCSR_MEM_TYPE_SHIFT 28
+#define MX25_CCM_MPCTL 0x00
+#define MX25_CCM_UPCTL 0x04
+#define MX25_CCM_CCTL 0x08
+#define MX25_CCM_CGCR0 0x0C
+#define MX25_CCM_CGCR1 0x10
+#define MX25_CCM_CGCR2 0x14
+#define MX25_CCM_PCDR0 0x18
+#define MX25_CCM_PCDR1 0x1C
+#define MX25_CCM_PCDR2 0x20
+#define MX25_CCM_PCDR3 0x24
+#define MX25_CCM_RCSR 0x28
+#define MX25_CCM_CRDR 0x2C
+#define MX25_CCM_DCVR0 0x30
+#define MX25_CCM_DCVR1 0x34
+#define MX25_CCM_DCVR2 0x38
+#define MX25_CCM_DCVR3 0x3c
+#define MX25_CCM_LTR0 0x40
+#define MX25_CCM_LTR1 0x44
+#define MX25_CCM_LTR2 0x48
+#define MX25_CCM_LTR3 0x4c
+
+#define MX25_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
+#define MX25_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
+#define MX25_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
+#define MX25_PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
+#define MX25_PDR0_AUTO_CON (1 << 0)
+#define MX25_PDR0_PER_SEL (1 << 26)
+
+#define MX25_CCM_RCSR_MEM_CTRL_SHIFT 30
+#define MX25_CCM_RCSR_MEM_TYPE_SHIFT 28
/*
* Adresses and ranges of the external chip select lines
@@ -139,14 +132,4 @@
#define MX25_ESDCTL_BASE_ADDR 0xb8001000
#define MX25_WEIM_BASE_ADDR 0xb8002000
-/*
- * Watchdog Registers
- */
-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
-#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
-
-/* important definition of some bits of WCR */
-#define WCR_WDE 0x04
-
#endif /* __ASM_ARCH_MX25_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index 5db1a3c3eb..90b4614bdf 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -86,7 +86,7 @@
#define MX27_X_MEMC_BASE_ADDR 0xd8000000
#define MX27_X_MEMC_SIZE SZ_1M
#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
-#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
+#define MX27_ESDCTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
@@ -101,181 +101,65 @@
/* IRAM */
#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
-/* FIXME: get rid of these */
-#define IMX_GPIO_BASE MX27_GPIO_BASE_ADDR
-#define IMX_NFC_BASE MX27_NFC_BASE_ADDR
-#define IMX_WDT_BASE MX27_WDOG_BASE_ADDR
-#define IMX_ESD_BASE MX27_SDRAMC_BASE_ADDR
-
-#define PCMCIA_PIPR (MX27_PCMCIA_CTL_BASE_ADDR + 0x00)
-#define PCMCIA_PSCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x04)
-#define PCMCIA_PER (MX27_PCMCIA_CTL_BASE_ADDR + 0x08)
-#define PCMCIA_PBR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x0c + ((x) << 2))
-#define PCMCIA_POR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x28 + ((x) << 2))
-#define PCMCIA_POFR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x44 + ((x) << 2))
-#define PCMCIA_PGCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x60)
-#define PCMCIA_PGSR (MX27_PCMCIA_CTL_BASE_ADDR + 0x64)
-
-/* AIPI */
-#define AIPI1_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x00)
-#define AIPI1_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x04)
-#define AIPI2_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x00)
-#define AIPI2_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x04)
-
-/* System Control */
-#define CID __REG(MX27_SYSCTRL_BASE_ADDR + 0x0) /* Chip ID Register */
-#define FMCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */
-#define GPCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */
-#define WBCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */
-#define DSCR(x) __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
-
-#define GPCR_BOOT_SHIFT 16
-#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
-#define GPCR_BOOT_UART_USB 0
-#define GPCR_BOOT_8BIT_NAND_2k 2
-#define GPCR_BOOT_16BIT_NAND_2k 3
-#define GPCR_BOOT_16BIT_NAND_512 4
-#define GPCR_BOOT_16BIT_CS0 5
-#define GPCR_BOOT_32BIT_CS0 6
-#define GPCR_BOOT_8BIT_NAND_512 7
+/* PCMCIA (base: MX27_PCMCIA_CTL_BASE_ADDR) */
+#define MX27_PCMCIA_PIPR 0x00
+#define MX27_PCMCIA_PSCR 0x04
+#define MX27_PCMCIA_PER 0x08
+#define MX27_PCMCIA_PBR(x) (0x0c + ((x) << 2))
+#define MX27_PCMCIA_POR(x) (0x28 + ((x) << 2))
+#define MX27_PCMCIA_POFR(x) (0x44 + ((x) << 2))
+#define MX27_PCMCIA_PGCR 0x60
+#define MX27_PCMCIA_PGSR 0x64
+
+/* AIPI (base: MX27_AIPI_BASE_ADDR) */
+#define MX27_AIPI1_PSR0 0x00
+#define MX27_AIPI1_PSR1 0x04
+#define MX27_AIPI2_PSR0 (0x20000 + 0x00)
+#define MX27_AIPI2_PSR1 (0x20000 + 0x04)
+
+/* System Control (base: MX27_SYSCTRL_BASE_ADDR) */
+#define MX27_CID 0x0 /* Chip ID Register */
+#define MX27_FMCR 0x14 /* Function Multeplexing Control Register */
+#define MX27_GPCR 0x18 /* Global Peripheral Control Register */
+#define MX27_WBCR 0x1C /* Well Bias Control Register */
+#define MX27_DSCR(x) (0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
#include "esdctl.h"
-/* PLL registers */
-#define CSCR __REG(MX27_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */
-#define MPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */
-#define SPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */
-#define SPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
-#define OSC26MCTL __REG(MX27_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */
-#define PCDR0 __REG(MX27_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */
-#define PCDR1 __REG(MX27_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */
-#define PCCR0 __REG(MX27_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */
-#define PCCR1 __REG(MX27_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */
-#define CCSR __REG(MX27_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */
-
-#define CSCR_MPEN (1 << 0)
-#define CSCR_SPEN (1 << 1)
-#define CSCR_FPM_EN (1 << 2)
-#define CSCR_OSC26M_DIS (1 << 3)
-#define CSCR_OSC26M_DIV1P5 (1 << 4)
-#define CSCR_AHB_DIV(d) (((d) & 0x3) << 8)
-#define CSCR_ARM_DIV(d) (((d) & 0x3) << 12)
-#define CSCR_ARM_SRC_MPLL (1 << 15)
-#define CSCR_MCU_SEL (1 << 16)
-#define CSCR_SP_SEL (1 << 17)
-#define CSCR_MPLL_RESTART (1 << 18)
-#define CSCR_SPLL_RESTART (1 << 19)
-#define CSCR_MSHC_SEL (1 << 20)
-#define CSCR_H264_SEL (1 << 21)
-#define CSCR_SSI1_SEL (1 << 22)
-#define CSCR_SSI2_SEL (1 << 23)
-#define CSCR_SD_CNT(d) (((d) & 0x3) << 24)
-#define CSCR_USB_DIV(d) (((d) & 0x7) << 28)
-#define CSCR_UPDATE_DIS (1 << 31)
-
-#define MPCTL1_BRMO (1 << 6)
-#define MPCTL1_LF (1 << 15)
-
-#define PCCR0_SSI2_EN (1 << 0)
-#define PCCR0_SSI1_EN (1 << 1)
-#define PCCR0_SLCDC_EN (1 << 2)
-#define PCCR0_SDHC3_EN (1 << 3)
-#define PCCR0_SDHC2_EN (1 << 4)
-#define PCCR0_SDHC1_EN (1 << 5)
-#define PCCR0_SDC_EN (1 << 6)
-#define PCCR0_SAHARA_EN (1 << 7)
-#define PCCR0_RTIC_EN (1 << 8)
-#define PCCR0_RTC_EN (1 << 9)
-#define PCCR0_PWM_EN (1 << 11)
-#define PCCR0_OWIRE_EN (1 << 12)
-#define PCCR0_MSHC_EN (1 << 13)
-#define PCCR0_LCDC_EN (1 << 14)
-#define PCCR0_KPP_EN (1 << 15)
-#define PCCR0_IIM_EN (1 << 16)
-#define PCCR0_I2C2_EN (1 << 17)
-#define PCCR0_I2C1_EN (1 << 18)
-#define PCCR0_GPT6_EN (1 << 19)
-#define PCCR0_GPT5_EN (1 << 20)
-#define PCCR0_GPT4_EN (1 << 21)
-#define PCCR0_GPT3_EN (1 << 22)
-#define PCCR0_GPT2_EN (1 << 23)
-#define PCCR0_GPT1_EN (1 << 24)
-#define PCCR0_GPIO_EN (1 << 25)
-#define PCCR0_FEC_EN (1 << 26)
-#define PCCR0_EMMA_EN (1 << 27)
-#define PCCR0_DMA_EN (1 << 28)
-#define PCCR0_CSPI3_EN (1 << 29)
-#define PCCR0_CSPI2_EN (1 << 30)
-#define PCCR0_CSPI1_EN (1 << 31)
-
-#define PCCR1_MSHC_BAUDEN (1 << 2)
-#define PCCR1_NFC_BAUDEN (1 << 3)
-#define PCCR1_SSI2_BAUDEN (1 << 4)
-#define PCCR1_SSI1_BAUDEN (1 << 5)
-#define PCCR1_H264_BAUDEN (1 << 6)
-#define PCCR1_PERCLK4_EN (1 << 7)
-#define PCCR1_PERCLK3_EN (1 << 8)
-#define PCCR1_PERCLK2_EN (1 << 9)
-#define PCCR1_PERCLK1_EN (1 << 10)
-#define PCCR1_HCLK_USB (1 << 11)
-#define PCCR1_HCLK_SLCDC (1 << 12)
-#define PCCR1_HCLK_SAHARA (1 << 13)
-#define PCCR1_HCLK_RTIC (1 << 14)
-#define PCCR1_HCLK_LCDC (1 << 15)
-#define PCCR1_HCLK_H264 (1 << 16)
-#define PCCR1_HCLK_FEC (1 << 17)
-#define PCCR1_HCLK_EMMA (1 << 18)
-#define PCCR1_HCLK_EMI (1 << 19)
-#define PCCR1_HCLK_DMA (1 << 20)
-#define PCCR1_HCLK_CSI (1 << 21)
-#define PCCR1_HCLK_BROM (1 << 22)
-#define PCCR1_HCLK_ATA (1 << 23)
-#define PCCR1_WDT_EN (1 << 24)
-#define PCCR1_USB_EN (1 << 25)
-#define PCCR1_UART6_EN (1 << 26)
-#define PCCR1_UART5_EN (1 << 27)
-#define PCCR1_UART4_EN (1 << 28)
-#define PCCR1_UART3_EN (1 << 29)
-#define PCCR1_UART2_EN (1 << 30)
-#define PCCR1_UART1_EN (1 << 31)
-
-#define CCSR_32K_SR (1 << 15)
-
-/* SDRAM Controller registers bitfields */
-#define ESDCTL_PRCT(x) (((x) & 3f) << 0)
-#define ESDCTL_BL (1 << 7)
-#define ESDCTL_FP (1 << 8)
-#define ESDCTL_PWDT(x) (((x) & 3) << 10)
-#define ESDCTL_SREFR(x) (((x) & 7) << 13)
-#define ESDCTL_DSIZ_16_UPPER (0 << 16)
-#define ESDCTL_DSIZ_16_LOWER (0 << 16)
-#define ESDCTL_DSIZ_32 (0 << 16)
-#define ESDCTL_COL8 (0 << 20)
-#define ESDCTL_COL9 (1 << 20)
-#define ESDCTL_COL10 (2 << 20)
-#define ESDCTL_ROW11 (0 << 24)
-#define ESDCTL_ROW12 (1 << 24)
-#define ESDCTL_ROW13 (2 << 24)
-#define ESDCTL_ROW14 (3 << 24)
-#define ESDCTL_ROW15 (4 << 24)
-#define ESDCTL_SP (1 << 27)
-#define ESDCTL_SMODE_NORMAL (0 << 28)
-#define ESDCTL_SMODE_PRECHAGRE (1 << 28)
-#define ESDCTL_SMODE_AUTO_REF (2 << 28)
-#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
-#define ESDCTL_SMODE_MAN_REF (4 << 28)
-#define ESDCTL_SDE (1 << 31)
-
-#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
-#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
-#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
-#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
-#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
-#define ESDCFG_TWR (1 << 15)
-#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
-#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
-#define ESDCFG_TWTR (1 << 20)
-#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
+/* PLL registers (base: MX27_CCM_BASE_ADDR) */
+#define MX27_CSCR 0x00 /* Clock Source Control Register */
+#define MX27_MPCTL0 0x04 /* MCU PLL Control Register 0 */
+#define MX27_MPCTL1 0x08 /* MCU PLL Control Register 1 */
+#define MX27_SPCTL0 0x0c /* System PLL Control Register 0 */
+#define MX27_SPCTL1 0x10 /* System PLL Control Register 1 */
+#define MX27_OSC26MCTL 0x14 /* Oscillator 26M Register */
+#define MX27_PCDR0 0x18 /* Peripheral Clock Divider Register 0 */
+#define MX27_PCDR1 0x1c /* Peripheral Clock Divider Register 1 */
+#define MX27_PCCR0 0x20 /* Peripheral Clock Control Register 0 */
+#define MX27_PCCR1 0x24 /* Peripheral Clock Control Register 1 */
+#define MX27_CCSR 0x28 /* Clock Control Status Register */
+
+#define MX27_CSCR_MPEN (1 << 0)
+#define MX27_CSCR_SPEN (1 << 1)
+#define MX27_CSCR_FPM_EN (1 << 2)
+#define MX27_CSCR_OSC26M_DIS (1 << 3)
+#define MX27_CSCR_OSC26M_DIV1P5 (1 << 4)
+#define MX27_CSCR_AHB_DIV(d) (((d) & 0x3) << 8)
+#define MX27_CSCR_ARM_DIV(d) (((d) & 0x3) << 12)
+#define MX27_CSCR_ARM_SRC_MPLL (1 << 15)
+#define MX27_CSCR_MCU_SEL (1 << 16)
+#define MX27_CSCR_SP_SEL (1 << 17)
+#define MX27_CSCR_MPLL_RESTART (1 << 18)
+#define MX27_CSCR_SPLL_RESTART (1 << 19)
+#define MX27_CSCR_MSHC_SEL (1 << 20)
+#define MX27_CSCR_H264_SEL (1 << 21)
+#define MX27_CSCR_SSI1_SEL (1 << 22)
+#define MX27_CSCR_SSI2_SEL (1 << 23)
+#define MX27_CSCR_SD_CNT(d) (((d) & 0x3) << 24)
+#define MX27_CSCR_USB_DIV(d) (((d) & 0x7) << 28)
+#define MX27_CSCR_UPDATE_DIS (1 << 31)
+
+#define MX27_MPCTL1_BRMO (1 << 6)
+#define MX27_MPCTL1_LF (1 << 15)
#endif /* _IMX27_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h
index 57f65dad1e..f641fe6129 100644
--- a/arch/arm/mach-imx/include/mach/imx31-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx31-regs.h
@@ -130,105 +130,61 @@
#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
-/* FIXME: Get rid of these */
-#define IMX_TIM1_BASE MX31_GPT1_BASE_ADDR
-#define IMX_WDT_BASE MX31_WDOG_BASE_ADDR
-#define IMX_ESD_BASE MX31_ESDCTL_BASE_ADDR
-#define IMX_NFC_BASE MX31_NFC_BASE_ADDR
-#define IOMUXC_BASE MX31_IOMUXC_BASE_ADDR
-
/*
* Clock Controller Module (CCM)
*/
-#define CCM_CCMR 0x00
-#define CCM_PDR0 0x04
-#define CCM_PDR1 0x08
-#define CCM_RCSR 0x0c
-#define CCM_MPCTL 0x10
-#define CCM_UPCTL 0x14
-#define CCM_SPCTL 0x18
-#define CCM_COSR 0x1C
-
-/*
- * ?????????????
- */
-#define CCMR_MDS (1 << 7)
-#define CCMR_SBYCS (1 << 4)
-#define CCMR_MPE (1 << 3)
-#define CCMR_PRCS_MASK (3 << 1)
-#define CCMR_FPM (1 << 1)
-#define CCMR_CKIH (2 << 1)
-
-#define RCSR_NFMS (1 << 30)
-
-/*
- * ?????????????
- */
-#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
-#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
-#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
-#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
-#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
-#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
-#define PDR0_MCU_PODF(x) ((x) & 0x7)
-
-#include "esdctl.h"
-
-/*
- * ???????????
- */
-#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
-#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
-#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
+#define MX31_CCM_CCMR 0x00
+#define MX31_CCM_PDR0 0x04
+#define MX31_CCM_PDR1 0x08
+#define MX31_CCM_RCSR 0x0c
+#define MX31_CCM_MPCTL 0x10
+#define MX31_CCM_UPCTL 0x14
+#define MX31_CCM_SPCTL 0x18
+#define MX31_CCM_COSR 0x1C
+
+#define MX31_CCMR_MDS (1 << 7)
+#define MX31_CCMR_SBYCS (1 << 4)
+#define MX31_CCMR_MPE (1 << 3)
+#define MX31_CCMR_PRCS_MASK (3 << 1)
+#define MX31_CCMR_FPM (1 << 1)
+#define MX31_CCMR_CKIH (2 << 1)
+
+#define MX31_RCSR_NFMS (1 << 30)
+
+#define MX31_PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
+#define MX31_PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
+#define MX31_PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
+#define MX31_PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
+#define MX31_PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
+#define MX31_PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
+#define MX31_PDR0_MCU_PODF(x) ((x) & 0x7)
+
+#define MX31_IOMUXC_GPR (IOMUXC_BASE + 0x8)
+#define MX31_IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
+#define MX31_IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
/*
* Signal Multiplexing (IOMUX)
*/
/* bits in the SW_MUX_CTL registers */
-#define MUX_CTL_OUT_GPIO_DR (0 << 4)
-#define MUX_CTL_OUT_FUNC (1 << 4)
-#define MUX_CTL_OUT_ALT1 (2 << 4)
-#define MUX_CTL_OUT_ALT2 (3 << 4)
-#define MUX_CTL_OUT_ALT3 (4 << 4)
-#define MUX_CTL_OUT_ALT4 (5 << 4)
-#define MUX_CTL_OUT_ALT5 (6 << 4)
-#define MUX_CTL_OUT_ALT6 (7 << 4)
-#define MUX_CTL_IN_NONE (0 << 0)
-#define MUX_CTL_IN_GPIO (1 << 0)
-#define MUX_CTL_IN_FUNC (2 << 0)
-#define MUX_CTL_IN_ALT1 (4 << 0)
-#define MUX_CTL_IN_ALT2 (8 << 0)
-
-#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
-#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
-#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
-#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
-
-/* Register offsets based on IOMUXC_BASE */
-/* 0x00 .. 0x7b */
-#define MUX_CTL_RTS1 0x7c
-#define MUX_CTL_CTS1 0x7d
-#define MUX_CTL_DTR_DCE1 0x7e
-#define MUX_CTL_DSR_DCE1 0x7f
-#define MUX_CTL_CSPI2_SCLK 0x80
-#define MUX_CTL_CSPI2_SPI_RDY 0x81
-#define MUX_CTL_RXD1 0x82
-#define MUX_CTL_TXD1 0x83
-#define MUX_CTL_CSPI2_MISO 0x84
-/* 0x85 .. 0x8a */
-#define MUX_CTL_CSPI2_MOSI 0x8b
-
-/* The modes a specific pin can be in
- * these macros can be used in mx31_gpio_mux() and have the form
- * MUX_[contact name]__[pin function]
- */
-#define MUX_RXD1_UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
-#define MUX_TXD1_UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
-#define MUX_RTS1_UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
-#define MUX_RTS1_UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
-
-#define MUX_CSPI2_MOSI_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
-#define MUX_CSPI2_MISO_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
+#define MX31_MUX_CTL_OUT_GPIO_DR (0 << 4)
+#define MX31_MUX_CTL_OUT_FUNC (1 << 4)
+#define MX31_MUX_CTL_OUT_ALT1 (2 << 4)
+#define MX31_MUX_CTL_OUT_ALT2 (3 << 4)
+#define MX31_MUX_CTL_OUT_ALT3 (4 << 4)
+#define MX31_MUX_CTL_OUT_ALT4 (5 << 4)
+#define MX31_MUX_CTL_OUT_ALT5 (6 << 4)
+#define MX31_MUX_CTL_OUT_ALT6 (7 << 4)
+#define MX31_MUX_CTL_IN_NONE (0 << 0)
+#define MX31_MUX_CTL_IN_GPIO (1 << 0)
+#define MX31_MUX_CTL_IN_FUNC (2 << 0)
+#define MX31_MUX_CTL_IN_ALT1 (4 << 0)
+#define MX31_MUX_CTL_IN_ALT2 (8 << 0)
+
+#define MX31_MUX_CTL_FUNC (MX31_MUX_CTL_OUT_FUNC | MX31_MUX_CTL_IN_FUNC)
+#define MX31_MUX_CTL_ALT1 (MX31_MUX_CTL_OUT_ALT1 | MX31_MUX_CTL_IN_ALT1)
+#define MX31_MUX_CTL_ALT2 (MX31_MUX_CTL_OUT_ALT2 | MX31_MUX_CTL_IN_ALT2)
+#define MX31_MUX_CTL_GPIO (MX31_MUX_CTL_OUT_GPIO_DR | MX31_MUX_CTL_IN_GPIO)
#endif /* __ASM_ARCH_MX31_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 19f6389b95..bbfde2339a 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -130,47 +130,39 @@
#define MX35_NFC_BASE_ADDR 0xbb000000
#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
-/* FIXME: Get rid of these */
-#define IMX_WDT_BASE MX35_WDOG_BASE_ADDR
-#define IMX_TIM1_BASE MX35_GPT1_BASE_ADDR
-#define IMX_ESD_BASE MX35_ESDCTL_BASE_ADDR
-#define IMX_IOMUXC_BASE MX35_IOMUXC_BASE_ADDR
-#define IMX_CCM_BASE MX35_CCM_BASE_ADDR
-#define IMX_NFC_BASE MX35_NFC_BASE_ADDR
-
/*
* Clock Controller Module (CCM)
*/
-#define CCM_CCMR 0x00
-#define CCM_PDR0 0x04
-#define CCM_PDR1 0x08
-#define CCM_PDR2 0x0C
-#define CCM_PDR3 0x10
-#define CCM_PDR4 0x14
-#define CCM_RCSR 0x18
-#define CCM_MPCTL 0x1C
-#define CCM_PPCTL 0x20
-#define CCM_ACMR 0x24
-#define CCM_COSR 0x28
-#define CCM_CGR0 0x2C
-#define CCM_CGR1 0x30
-#define CCM_CGR2 0x34
-#define CCM_CGR3 0x38
-
-#define CCM_CGR0_CSPI1_SHIFT 10
-#define CCM_CGR1_FEC_SHIFT 0
-#define CCM_CGR1_I2C1_SHIFT 10
-#define CCM_CGR1_SDHC1_SHIFT 26
-#define CCM_CGR2_USB_SHIFT 22
-
-#define CCM_RCSR_MEM_CTRL_SHIFT 25
-#define CCM_RCSR_MEM_TYPE_SHIFT 23
-
-#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
-#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
-#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
-#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
-#define PDR0_AUTO_CON (1 << 0)
-#define PDR0_PER_SEL (1 << 26)
+#define MX35_CCM_CCMR 0x00
+#define MX35_CCM_PDR0 0x04
+#define MX35_CCM_PDR1 0x08
+#define MX35_CCM_PDR2 0x0C
+#define MX35_CCM_PDR3 0x10
+#define MX35_CCM_PDR4 0x14
+#define MX35_CCM_RCSR 0x18
+#define MX35_CCM_MPCTL 0x1C
+#define MX35_CCM_PPCTL 0x20
+#define MX35_CCM_ACMR 0x24
+#define MX35_CCM_COSR 0x28
+#define MX35_CCM_CGR0 0x2C
+#define MX35_CCM_CGR1 0x30
+#define MX35_CCM_CGR2 0x34
+#define MX35_CCM_CGR3 0x38
+
+#define MX35_CCM_CGR0_CSPI1_SHIFT 10
+#define MX35_CCM_CGR1_FEC_SHIFT 0
+#define MX35_CCM_CGR1_I2C1_SHIFT 10
+#define MX35_CCM_CGR1_SDHC1_SHIFT 26
+#define MX35_CCM_CGR2_USB_SHIFT 22
+
+#define MX35_CCM_RCSR_MEM_CTRL_SHIFT 25
+#define MX35_CCM_RCSR_MEM_TYPE_SHIFT 23
+
+#define MX35_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
+#define MX35_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
+#define MX35_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
+#define MX35_PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
+#define MX35_PDR0_AUTO_CON (1 << 0)
+#define MX35_PDR0_PER_SEL (1 << 26)
#endif /* __ASM_ARCH_MX35_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h
index c451004ecc..8eb74cdb7a 100644
--- a/arch/arm/mach-imx/include/mach/imx51-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx51-regs.h
@@ -1,10 +1,6 @@
#ifndef __MACH_IMX51_REGS_H
#define __MACH_IMX51_REGS_H
-#define IMX_TIM1_BASE 0x73fa0000
-#define IMX_WDT_BASE 0x73f98000
-#define IMX_IOMUXC_BASE 0x73fa8000
-
/* WEIM registers */
#define WEIM_CSxGCR1(n) (((n) * 0x18) + 0x00)
#define WEIM_CSxGCR2(n) (((n) * 0x18) + 0x04)
diff --git a/arch/arm/mach-imx/include/mach/imx53-regs.h b/arch/arm/mach-imx/include/mach/imx53-regs.h
index e57d1abdd0..8025e97720 100644
--- a/arch/arm/mach-imx/include/mach/imx53-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx53-regs.h
@@ -1,10 +1,6 @@
#ifndef __MACH_IMX53_REGS_H
#define __MACH_IMX53_REGS_H
-#define IMX_TIM1_BASE 0X53FA0000
-#define IMX_WDT_BASE 0X53F98000
-#define IMX_IOMUXC_BASE 0X53FA8000
-
#define MX53_IROM_BASE_ADDR 0x0
/*
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index eca4fa663a..716e6b4f25 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -1,10 +1,6 @@
#ifndef __MACH_IMX6_REGS_H
#define __MACH_IMX6_REGS_H
-#define IMX_TIM1_BASE 0x02098000
-#define IMX_WDT_BASE 0x020bc000
-#define IMX_IOMUXC_BASE 0x020e0000
-
#define MX6_AIPS1_ARB_BASE_ADDR 0x02000000
#define MX6_AIPS2_ARB_BASE_ADDR 0x02100000
@@ -12,8 +8,6 @@
#define MX6_ATZ1_BASE_ADDR MX6_AIPS1_ARB_BASE_ADDR
#define MX6_ATZ2_BASE_ADDR MX6_AIPS2_ARB_BASE_ADDR
-#define IPU_CTRL_BASE_ADDR 0x02400000
-
/* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */
#define MX6_SPDIF_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x04000)
#define MX6_ECSPI1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x08000)
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx1.h b/arch/arm/mach-imx/include/mach/iomux-mx1.h
new file mode 100644
index 0000000000..51317d35d5
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-mx1.h
@@ -0,0 +1,135 @@
+#ifndef __MACH_IOMUX_MX1_H
+#define __MACH_IOMUX_MX1_H
+
+#include <mach/iomux-v1.h>
+
+/*
+ * FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
+#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
+#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
+#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
+#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
+#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
+#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
+#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
+#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
+#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
+#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
+#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
+#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
+#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
+#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
+#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
+#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
+#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
+#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
+#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
+#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
+#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
+#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
+#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
+#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
+#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
+#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
+#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
+#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
+#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
+#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
+#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
+#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
+#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
+#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
+#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
+#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
+#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
+#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
+#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
+#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
+#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
+#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
+#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
+#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
+#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
+#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
+#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
+#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
+#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
+#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
+#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
+#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
+#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
+#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
+#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
+#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
+#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
+#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
+#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
+#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
+#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
+#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
+#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
+#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
+#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
+#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
+#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
+#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
+#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
+#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
+#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
+#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
+#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
+#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
+#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
+#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
+#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
+#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
+#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
+#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
+#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
+#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
+#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
+#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
+#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
+#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
+#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
+#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
+#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
+#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
+#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
+#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
+#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
+#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
+#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
+#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
+#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
+#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
+#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
+#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
+#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
+#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
+#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
+#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
+#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
+#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
+#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
+#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
+#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
+#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
+#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
+#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
+#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
+#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
+#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
+#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
+#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
+#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
+#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
+#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
+#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
+#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
+
+#endif /* __MACH_IOMUX_MX1_H */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx21.h b/arch/arm/mach-imx/include/mach/iomux-mx21.h
index 482c4f2513..203190d1d7 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx21.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx21.h
@@ -13,6 +13,7 @@
#ifndef __MACH_IOMUX_MX21_H__
#define __MACH_IOMUX_MX21_H__
+#include <mach/iomux-v1.h>
#include <mach/iomux-mx2x.h>
/* Primary GPIO pin functions */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h
index ff9d6573fa..7d2496708e 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx27.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx27.h
@@ -15,6 +15,7 @@
#ifndef __MACH_IOMUX_MX27_H__
#define __MACH_IOMUX_MX27_H__
+#include <mach/iomux-v1.h>
#include <mach/iomux-mx2x.h>
/* Primary GPIO pin functions */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx35.h b/arch/arm/mach-imx/include/mach/iomux-mx35.h
index 331b070647..30b94e3b00 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx35.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx35.h
@@ -667,7 +667,7 @@
#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4 0, NO_PAD_CTRL)
+#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL)
#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/mach-imx/include/mach/iomux-v1.h b/arch/arm/mach-imx/include/mach/iomux-v1.h
new file mode 100644
index 0000000000..55fbcdb94e
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-v1.h
@@ -0,0 +1,48 @@
+#ifndef __MACH_IOMUX_V1_H__
+#define __MACH_IOMUX_V1_H__
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+
+#define GPIO_OUT (1 << 8)
+#define GPIO_IN (0 << 8)
+#define GPIO_PUEN (1 << 9)
+
+#define GPIO_PF (1 << 10)
+#define GPIO_AF (1 << 11)
+
+#define GPIO_OCR_SHIFT 12
+#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT 14
+#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT 16
+#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
+
+#define GPIO_GIUS (1 << 16)
+
+void imx_iomuxv1_init(void __iomem *base);
+
+#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/mach-imx/include/mach/revision.h b/arch/arm/mach-imx/include/mach/revision.h
new file mode 100644
index 0000000000..bc6f20a3fb
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/revision.h
@@ -0,0 +1,22 @@
+#ifndef __MACH_REVISION_H__
+#define __MACH_REVISION_H__
+
+/* silicon revisions */
+#define IMX_CHIP_REV_1_0 0x10
+#define IMX_CHIP_REV_1_1 0x11
+#define IMX_CHIP_REV_1_2 0x12
+#define IMX_CHIP_REV_1_3 0x13
+#define IMX_CHIP_REV_2_0 0x20
+#define IMX_CHIP_REV_2_1 0x21
+#define IMX_CHIP_REV_2_2 0x22
+#define IMX_CHIP_REV_2_3 0x23
+#define IMX_CHIP_REV_3_0 0x30
+#define IMX_CHIP_REV_3_1 0x31
+#define IMX_CHIP_REV_3_2 0x32
+#define IMX_CHIP_REV_UNKNOWN 0xff
+
+int imx_silicon_revision(void);
+
+void imx_set_silicon_revision(const char *soc, int revision);
+
+#endif /* __MACH_REVISION_H__ */
diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
index f2dfdb3ffd..f8f90615c6 100644
--- a/arch/arm/mach-imx/iomux-v1.c
+++ b/arch/arm/mach-imx/iomux-v1.c
@@ -1,5 +1,6 @@
#include <common.h>
-#include <mach/imx-regs.h>
+#include <io.h>
+#include <mach/iomux-v1.h>
/*
* GPIO Module and I/O Multiplexer
@@ -8,23 +9,25 @@
* i.MX1 and i.MXL: 0 <= x <= 3
* i.MX27 : 0 <= x <= 5
*/
-#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8)
-#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8)
-#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8)
-#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 7) << 8)
-#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 7) << 8)
-#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 7) << 8)
-#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 7) << 8)
-#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 7) << 8)
-#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 7) << 8)
-#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 7) << 8)
-#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 7) << 8)
-#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 7) << 8)
-#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 7) << 8)
-#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 7) << 8)
-#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 7) << 8)
-#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 7) << 8)
-#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 7) << 8)
+#define DDIR 0x00
+#define OCR1 0x04
+#define OCR2 0x08
+#define ICONFA1 0x0c
+#define ICONFA2 0x10
+#define ICONFB1 0x14
+#define ICONFB2 0x18
+#define DR 0x1c
+#define GIUS 0x20
+#define SSR 0x24
+#define ICR1 0x28
+#define ICR2 0x2c
+#define IMR 0x30
+#define ISR 0x34
+#define GPR 0x38
+#define SWR 0x3c
+#define PUEN 0x40
+
+static void __iomem *iomuxv1_base;
void imx_gpio_mode(int gpio_mode)
{
@@ -33,55 +36,81 @@ void imx_gpio_mode(int gpio_mode)
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
- unsigned int tmp;
+ void __iomem *portbase = iomuxv1_base + port * 0x100;
+ uint32_t val;
+
+ if (!iomuxv1_base)
+ return;
/* Pullup enable */
- if(gpio_mode & GPIO_PUEN)
- PUEN(port) |= (1 << pin);
+ val = readl(portbase + PUEN);
+ if (gpio_mode & GPIO_PUEN)
+ val |= (1 << pin);
else
- PUEN(port) &= ~(1 << pin);
+ val &= ~(1 << pin);
+ writel(val, portbase + PUEN);
/* Data direction */
- if(gpio_mode & GPIO_OUT)
- DDIR(port) |= 1 << pin;
+ val = readl(portbase + DDIR);
+ if (gpio_mode & GPIO_OUT)
+ val |= 1 << pin;
else
- DDIR(port) &= ~(1 << pin);
+ val &= ~(1 << pin);
+ writel(val, portbase + DDIR);
/* Primary / alternate function */
- if(gpio_mode & GPIO_AF)
- GPR(port) |= (1 << pin);
+ val = readl(portbase + GPR);
+ if (gpio_mode & GPIO_AF)
+ val |= (1 << pin);
else
- GPR(port) &= ~(1 << pin);
+ val &= ~(1 << pin);
+ writel(val, portbase + GPR);
/* use as gpio? */
- if(!(gpio_mode & (GPIO_PF | GPIO_AF)))
- GIUS(port) |= (1 << pin);
+ val = readl(portbase + GIUS);
+ if (!(gpio_mode & (GPIO_PF | GPIO_AF)))
+ val |= (1 << pin);
else
- GIUS(port) &= ~(1 << pin);
+ val &= ~(1 << pin);
+ writel(val, portbase + GIUS);
/* Output / input configuration */
if (pin < 16) {
- tmp = OCR1(port);
- tmp &= ~(3 << (pin * 2));
- tmp |= (ocr << (pin * 2));
- OCR1(port) = tmp;
+ val = readl(portbase + OCR1);
+ val &= ~(3 << (pin * 2));
+ val |= (ocr << (pin * 2));
+ writel(val, portbase + OCR1);
+
+ val = readl(portbase + ICONFA1);
+ val &= ~(3 << (pin * 2));
+ val |= aout << (pin * 2);
+ writel(val, portbase + ICONFA1);
- ICONFA1(port) &= ~(3 << (pin * 2));
- ICONFA1(port) |= aout << (pin * 2);
- ICONFB1(port) &= ~(3 << (pin * 2));
- ICONFB1(port) |= bout << (pin * 2);
+ val = readl(portbase + ICONFB1);
+ val &= ~(3 << (pin * 2));
+ val |= bout << (pin * 2);
+ writel(val, portbase + ICONFB1);
} else {
pin -= 16;
- tmp = OCR2(port);
- tmp &= ~(3 << (pin * 2));
- tmp |= (ocr << (pin * 2));
- OCR2(port) = tmp;
+ val = readl(portbase + OCR2);
+ val &= ~(3 << (pin * 2));
+ val |= (ocr << (pin * 2));
+ writel(val, portbase + OCR2);
- ICONFA2(port) &= ~(3 << (pin * 2));
- ICONFA2(port) |= aout << (pin * 2);
- ICONFB2(port) &= ~(3 << (pin * 2));
- ICONFB2(port) |= bout << (pin * 2);
+ val = readl(portbase + ICONFA2);
+ val &= ~(3 << (pin * 2));
+ val |= aout << (pin * 2);
+ writel(val, portbase + ICONFA2);
+
+ val = readl(portbase + ICONFB2);
+ val &= ~(3 << (pin * 2));
+ val |= bout << (pin * 2);
+ writel(val, portbase + ICONFB2);
}
}
+void imx_iomuxv1_init(void __iomem *base)
+{
+ iomuxv1_base = base;
+}
diff --git a/arch/arm/mach-imx/iomux-v2.c b/arch/arm/mach-imx/iomux-v2.c
index 08af54c4c7..dbbb8a26fd 100644
--- a/arch/arm/mach-imx/iomux-v2.c
+++ b/arch/arm/mach-imx/iomux-v2.c
@@ -16,19 +16,22 @@
#include <common.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <init.h>
#include <mach/iomux-mx31.h>
/*
* IOMUX register (base) addresses
*/
-#define IOMUXINT_OBS1 (IOMUXC_BASE + 0x000)
-#define IOMUXINT_OBS2 (IOMUXC_BASE + 0x004)
-#define IOMUXGPR (IOMUXC_BASE + 0x008)
-#define IOMUXSW_MUX_CTL (IOMUXC_BASE + 0x00C)
-#define IOMUXSW_PAD_CTL (IOMUXC_BASE + 0x154)
+#define IOMUXINT_OBS1 0x000
+#define IOMUXINT_OBS2 0x004
+#define IOMUXGPR 0x008
+#define IOMUXSW_MUX_CTL 0x00C
+#define IOMUXSW_PAD_CTL 0x154
#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
+
+static void __iomem *base;
+
/*
* set the mode for a IOMUX pin.
*/
@@ -37,7 +40,10 @@ int imx_iomux_mode(unsigned int pin_mode)
u32 field, l, mode, ret = 0;
void __iomem *reg;
- reg = (void *)(IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK));
+ if (!base)
+ return -EINVAL;
+
+ reg = base + IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
field = pin_mode & 0x3;
mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
@@ -61,8 +67,11 @@ void imx_iomux_set_pad(enum iomux_pins pin, u32 config)
u32 field, l;
void __iomem *reg;
+ if (!base)
+ return;
+
pin &= IOMUX_PADNUM_MASK;
- reg = (void *)(IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4);
+ reg = base + IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
field = (pin + 2) % 3;
pr_debug("%s: reg offset = 0x%x, field = %d\n",
@@ -83,14 +92,51 @@ void imx_iomux_set_gpr(enum iomux_gp_func gp, int en)
{
u32 l;
- l = readl(IOMUXGPR);
+ if (!base)
+ return;
+
+ l = readl(base + IOMUXGPR);
if (en)
l |= gp;
else
l &= ~gp;
- writel(l, IOMUXGPR);
+ writel(l, base + IOMUXGPR);
}
EXPORT_SYMBOL(mxc_iomux_set_gpr);
+static int imx_iomux_probe(struct device_d *dev)
+{
+ base = dev_request_mem_region(dev, 0);
+
+ return 0;
+}
+static __maybe_unused struct of_device_id imx_iomux_dt_ids[] = {
+ {
+ .compatible = "fsl,imx31-iomux",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_device_id imx_iomux_ids[] = {
+ {
+ .name = "imx31-iomux",
+ }, {
+ /* sentinel */
+ },
+};
+
+static struct driver_d imx_iomux_driver = {
+ .name = "imx-iomuxv2",
+ .probe = imx_iomux_probe,
+ .of_compatible = DRV_OF_COMPAT(imx_iomux_dt_ids),
+ .id_table = imx_iomux_ids,
+};
+
+static int imx_iomux_init(void)
+{
+ return platform_driver_register(&imx_iomux_driver);
+}
+postcore_initcall(imx_iomux_init);
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index 948b610b10..8a6064da6c 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -15,11 +15,11 @@
*
*/
#include <common.h>
+#include <init.h>
#include <io.h>
#include <mach/iomux-v3.h>
-#include <mach/imx-regs.h>
-static void __iomem *base = (void *)IMX_IOMUXC_BASE;
+static void __iomem *base;
/*
* configures a single pad in the iomuxer
@@ -33,6 +33,9 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+ if (!base)
+ return -EINVAL;
+
debug("%s: mux 0x%08x -> 0x%04x pad: 0x%08x -> 0x%04x sel_inp: 0x%08x -> 0x%04x\n",
__func__, mux_mode, mux_ctrl_ofs, pad_ctrl, pad_ctrl_ofs, sel_input,
sel_input_ofs);
@@ -66,3 +69,39 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
return 0;
}
EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
+
+static int imx_iomux_probe(struct device_d *dev)
+{
+ base = dev_request_mem_region(dev, 0);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id imx_iomux_dt_ids[] = {
+ {
+ .compatible = "fsl,imx35-iomux",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_device_id imx_iomux_ids[] = {
+ {
+ .name = "imx35-iomux",
+ }, {
+ /* sentinel */
+ },
+};
+
+static struct driver_d imx_iomux_driver = {
+ .name = "imx-iomuxv3",
+ .probe = imx_iomux_probe,
+ .of_compatible = DRV_OF_COMPAT(imx_iomux_dt_ids),
+ .id_table = imx_iomux_ids,
+};
+
+static int imx_iomux_init(void)
+{
+ return platform_driver_register(&imx_iomux_driver);
+}
+postcore_initcall(imx_iomux_init);
diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c
index fff9a12379..f298a36046 100644
--- a/arch/arm/mach-imx/nand.c
+++ b/arch/arm/mach-imx/nand.c
@@ -12,20 +12,23 @@
*/
#include <common.h>
-#include <mach/imx-regs.h>
+#include <mach/generic.h>
+#include <mach/imx21-regs.h>
+#include <mach/imx25-regs.h>
+#include <mach/imx27-regs.h>
+#include <mach/imx35-regs.h>
#include <io.h>
-#if defined(CONFIG_ARCH_IMX35) || defined (CONFIG_ARCH_IMX25)
-
#define RCSR_NFC_FMS (1 << 8)
#define RCSR_NFC_4K (1 << 9)
#define RCSR_NFC_16BIT_SEL (1 << 14)
-void imx_nand_set_layout(int writesize, int datawidth)
+static __maybe_unused void imx25_35_nand_set_layout(void __iomem *reg_rcsr,
+ int writesize, int datawidth)
{
unsigned int rcsr;
- rcsr = readl(IMX_CCM_BASE + CCM_RCSR);
+ rcsr = readl(reg_rcsr);
switch (writesize) {
case 512:
@@ -52,19 +55,18 @@ void imx_nand_set_layout(int writesize, int datawidth)
break;
}
- writel(rcsr, IMX_CCM_BASE + CCM_RCSR);
+ writel(rcsr, reg_rcsr);
}
-#elif defined(CONFIG_ARCH_IMX21) || defined (CONFIG_ARCH_IMX27)
-
#define FMCR_NF_FMS (1 << 5)
#define FMCR_NF_16BIT_SEL (1 << 4)
-void imx_nand_set_layout(int writesize, int datawidth)
+static __maybe_unused void imx21_27_nand_set_layout(void __iomem *reg_fmcr,
+ int writesize, int datawidth)
{
unsigned int fmcr;
- fmcr = FMCR;
+ fmcr = readl(reg_fmcr);
switch (writesize) {
case 512:
@@ -88,23 +90,29 @@ void imx_nand_set_layout(int writesize, int datawidth)
break;
}
- FMCR = fmcr;
-}
-
-#elif defined CONFIG_ARCH_IMX51 || defined CONFIG_ARCH_IMX53
-
-void imx_nand_set_layout(int writesize, int datawidth)
-{
- /* Just silence the compiler warning below. On i.MX51 we don't
- * have external boot.
- */
+ writel(fmcr, reg_fmcr);
}
-#else
-#warning using empty imx_nand_set_layout(). NAND flash will not work properly if not booting from it
-
void imx_nand_set_layout(int writesize, int datawidth)
{
-}
-
+#ifdef CONFIG_ARCH_IMX21
+ if (cpu_is_mx21())
+ imx21_27_nand_set_layout((void *)(MX21_SYSCTRL_BASE_ADDR +
+ 0x14), writesize, datawidth);
#endif
+#ifdef CONFIG_ARCH_IMX27
+ if (cpu_is_mx27())
+ imx21_27_nand_set_layout((void *)(MX27_SYSCTRL_BASE_ADDR +
+ 0x14), writesize, datawidth);
+#endif
+#ifdef CONFIG_ARCH_IMX25
+ if (cpu_is_mx25())
+ imx25_35_nand_set_layout((void *)MX25_CCM_BASE_ADDR +
+ MX25_CCM_RCSR, writesize, datawidth);
+#endif
+#ifdef CONFIG_ARCH_IMX35
+ if (cpu_is_mx35())
+ imx25_35_nand_set_layout((void *)MX35_CCM_BASE_ADDR +
+ MX35_CCM_RCSR, writesize, datawidth);
+#endif
+}
diff --git a/arch/arm/mach-imx/reset_source.c b/arch/arm/mach-imx/reset_source.c
deleted file mode 100644
index e7b2a906c5..0000000000
--- a/arch/arm/mach-imx/reset_source.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * (C) Copyright 2012 Juergen Beisert - <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <init.h>
-#include <io.h>
-#include <reset_source.h>
-#include <mach/imx-regs.h>
-
-#ifdef CONFIG_ARCH_IMX1
-# define IMX_RESET_SRC_WDOG (1 << 1)
-# define IMX_RESET_SRC_HRDRESET (1 << 0)
-/* let the compiler sort out useless code on this arch */
-# define IMX_RESET_SRC_WARMSTART 0
-# define IMX_RESET_SRC_COLDSTART 0
-#else
- /* WRSR checked for i.MX25, i.MX27, i.MX31, i.MX35 and i.MX51 */
-# define WDOG_WRSR 0x04
- /* valid for i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 */
-# define IMX_RESET_SRC_WARMSTART (1 << 0)
- /* valid for i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 */
-# define IMX_RESET_SRC_WDOG (1 << 1)
- /* valid for i.MX27, i.MX31, always '0' on i.MX25, i.MX35, i.MX51 */
-# define IMX_RESET_SRC_HRDRESET (1 << 3)
- /* valid for i.MX27, i.MX31, always '0' on i.MX25, i.MX35, i.MX51 */
-# define IMX_RESET_SRC_COLDSTART (1 << 4)
-#endif
-
-static unsigned read_detection_register(void)
-{
-#ifdef CONFIG_ARCH_IMX1
- return readl(IMX_SYSCTRL_BASE);
-#else
- return readw(IMX_WDT_BASE + WDOG_WRSR);
-#endif
-}
-
-static int imx_detect_reset_source(void)
-{
- unsigned reg = read_detection_register();
-
- if (reg & IMX_RESET_SRC_COLDSTART) {
- set_reset_source(RESET_POR);
- return 0;
- }
-
- if (reg & (IMX_RESET_SRC_HRDRESET | IMX_RESET_SRC_WARMSTART)) {
- set_reset_source(RESET_RST);
- return 0;
- }
-
- if (reg & IMX_RESET_SRC_WDOG) {
- set_reset_source(RESET_WDG);
- return 0;
- }
-
- /* else keep the default 'unknown' state */
- return 0;
-}
-
-device_initcall(imx_detect_reset_source);
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h
index 1e575fa0c4..4e7c8fe87e 100644
--- a/arch/arm/mach-mxs/include/mach/gpio.h
+++ b/arch/arm/mach-mxs/include/mach/gpio.h
@@ -25,10 +25,8 @@
# include <mach/iomux-imx28.h>
#endif
+#include <asm-generic/gpio.h>
+
void imx_gpio_mode(uint32_t);
-void gpio_set_value(unsigned, int);
-int gpio_direction_input(unsigned);
-int gpio_direction_output(unsigned, int);
-int gpio_get_value(unsigned);
#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-nomadik/8815.c b/arch/arm/mach-nomadik/8815.c
index 81c5ce16d8..c5cac580d2 100644
--- a/arch/arm/mach-nomadik/8815.c
+++ b/arch/arm/mach-nomadik/8815.c
@@ -29,6 +29,10 @@ static struct clk st8815_clk_48 = {
.rate = 48 * 1000 * 1000,
};
+static struct clk st8815_clk_2_4 = {
+ .rate = 2400000,
+};
+
static struct clk st8815_dummy;
void st8815_add_device_sdram(u32 size)
@@ -38,6 +42,7 @@ void st8815_add_device_sdram(u32 size)
static struct clk_lookup clocks_lookups[] = {
CLKDEV_CON_ID("apb_pclk", &st8815_dummy),
+ CLKDEV_CON_ID("nomadik_mtu", &st8815_clk_2_4),
CLKDEV_DEV_ID("uart-pl0110", &st8815_clk_48),
CLKDEV_DEV_ID("uart-pl0111", &st8815_clk_48),
};
diff --git a/arch/arm/mach-nomadik/include/mach/mtu.h b/arch/arm/mach-nomadik/include/mach/mtu.h
deleted file mode 100644
index 9095d86a5a..0000000000
--- a/arch/arm/mach-nomadik/include/mach/mtu.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __ASM_ARCH_MTU_H
-#define __ASM_ARCH_MTU_H
-
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-
-#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
-#define MTU_RIS 0x04 /* Raw interrupt status */
-#define MTU_MIS 0x08 /* Masked interrupt status */
-#define MTU_ICR 0x0C /* Interrupt clear register */
-
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
-#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
-
-#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
-#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
-
-
-/* bits for the control register */
-#define MTU_CRn_ENA 0x80
-#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK 0x0c
-#define MTU_CRn_PRESCALE_1 0x00
-#define MTU_CRn_PRESCALE_16 0x04
-#define MTU_CRn_PRESCALE_256 0x08
-#define MTU_CRn_32BITS 0x02
-#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
-
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR 0xff0
-#define MTU_ITOP 0xff4
-
-#define MTU_PERIPH_ID0 0xfe0
-#define MTU_PERIPH_ID1 0xfe4
-#define MTU_PERIPH_ID2 0xfe8
-#define MTU_PERIPH_ID3 0xfeC
-
-#define MTU_PCELL0 0xff0
-#define MTU_PCELL1 0xff4
-#define MTU_PCELL2 0xff8
-#define MTU_PCELL3 0xffC
-
-#endif /* __ASM_ARCH_MTU_H */
diff --git a/arch/arm/mach-nomadik/include/mach/timex.h b/arch/arm/mach-nomadik/include/mach/timex.h
deleted file mode 100644
index b2b41faa1b..0000000000
--- a/arch/arm/mach-nomadik/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-#define CLOCK_TICK_RATE 2400000
-
-#endif
diff --git a/arch/arm/mach-nomadik/timer.c b/arch/arm/mach-nomadik/timer.c
index becd36357a..0b8dc866eb 100644
--- a/arch/arm/mach-nomadik/timer.c
+++ b/arch/arm/mach-nomadik/timer.c
@@ -10,55 +10,16 @@
*/
#include <common.h>
#include <init.h>
-#include <clock.h>
#include <io.h>
#include <mach/hardware.h>
-#include <mach/mtu.h>
-#include <mach/timex.h>
/* Initial value for SRC control register: all timers use MXTAL/8 source */
#define SRC_CR_INIT_MASK 0x00007fff
#define SRC_CR_INIT_VAL 0x2aaa8000
-static u32 nmdk_cycle; /* write-once */
-static __iomem void *mtu_base;
-
-/*
- * clocksource: the MTU device is a decrementing counters, so we negate
- * the value being read.
- */
-static uint64_t nmdk_read_timer(void)
-{
- return nmdk_cycle - readl(mtu_base + MTU_VAL(0));
-}
-
-static struct clocksource nmdk_clksrc = {
- .read = nmdk_read_timer,
- .shift = 20,
- .mask = CLOCKSOURCE_MASK(32),
-};
-
-static void nmdk_timer_reset(void)
-{
- u32 cr;
-
- writel(0, mtu_base + MTU_CR(0)); /* off */
-
- /* configure load and background-load, and fire it up */
- writel(nmdk_cycle, mtu_base + MTU_LR(0));
- writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
- cr = MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS;
- writel(cr, mtu_base + MTU_CR(0));
- writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
-}
-
-static int nmdk_timer_init(void)
+static int st8815_timer_init(void)
{
u32 src_cr;
- unsigned long rate;
-
- rate = CLOCK_TICK_RATE; /* 2.4MHz */
- nmdk_cycle = (rate + 1000 / 2) / 1000;
/* Configure timer sources in "system reset controller" ctrl reg */
src_cr = readl(NOMADIK_SRC_BASE);
@@ -66,16 +27,7 @@ static int nmdk_timer_init(void)
src_cr |= SRC_CR_INIT_VAL;
writel(src_cr, NOMADIK_SRC_BASE);
- /* Save global pointer to mtu, used by functions above */
- mtu_base = (void *)NOMADIK_MTU0_BASE;
-
- /* Init the timer and register clocksource */
- nmdk_timer_reset();
-
- nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
-
- init_clock(&nmdk_clksrc);
-
+ add_generic_device("nomadik_mtu", DEVICE_ID_SINGLE, NULL, NOMADIK_MTU0_BASE, 0x1000, IORESOURCE_MEM, NULL);
return 0;
}
-core_initcall(nmdk_timer_init);
+coredevice_initcall(st8815_timer_init);
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index f752bc7986..3a6d50cd81 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -23,6 +23,7 @@ pbl-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
+pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-$(CONFIG_SHELL_NONE) += xload.o
obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
diff --git a/arch/arm/mach-omap/gpio.c b/arch/arm/mach-omap/gpio.c
index 376e9a7d55..49ffbda503 100644
--- a/arch/arm/mach-omap/gpio.c
+++ b/arch/arm/mach-omap/gpio.c
@@ -133,7 +133,7 @@ static int omap_gpio_probe(struct device_d *dev)
omapgpio = xzalloc(sizeof(*omapgpio));
omapgpio->base = dev_request_mem_region(dev, 0);
omapgpio->chip.ops = &omap_gpio_ops;
- omapgpio->chip.base = -1;
+ omapgpio->chip.base = dev->id * 32;
omapgpio->chip.ngpio = 32;
omapgpio->chip.dev = dev;
gpiochip_add(&omapgpio->chip);
diff --git a/arch/arm/mach-omap/include/mach/gpio.h b/arch/arm/mach-omap/include/mach/gpio.h
index 79bf4485b9..306ab4c9f2 100644
--- a/arch/arm/mach-omap/include/mach/gpio.h
+++ b/arch/arm/mach-omap/include/mach/gpio.h
@@ -1,42 +1 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * This work is derived from the linux 2.6.27 kernel source
- * To fetch, use the kernel repository
- * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
- * Use the v2.6.27 tag.
- *
- * Below is the original's header including its copyright
- *
- * linux/arch/arm/plat-omap/gpio.c
- *
- * Support functions for OMAP GPIO
- *
- * Copyright (C) 2003-2005 Nokia Corporation
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef _GPIO_H
-#define _GPIO_H
-
-void gpio_set_value(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_direction_input(unsigned gpio);
-
-#endif /* _GPIO_H_ */
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 5028e9a9e6..1e1308ec6a 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -512,21 +512,23 @@ const struct gpmc_config omap3_nand_cfg = {
.size = GPMC_SIZE_16M,
};
+#ifndef __PBL__
static int omap3_gpio_init(void)
{
add_generic_device("omap-gpio", 0, NULL, 0x48310000,
- 0x100, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 1, NULL, 0x49050000,
- 0x100, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 2, NULL, 0x49052000,
- 0x100, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 3, NULL, 0x49054000,
- 0x100, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 4, NULL, 0x49056000,
- 0x100, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 5, NULL, 0x49058000,
- 0x100, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
return 0;
}
coredevice_initcall(omap3_gpio_init);
+#endif
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index a159dfcb7e..d7771bf543 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -484,11 +484,27 @@ enum omap_boot_src omap4_bootsrc(void)
return OMAP_BOOTSRC_UNKNOWN;
}
+#define GPIO_MASK 0x1f
+
+static void __iomem *omap4_get_gpio_base(unsigned gpio)
+{
+ void __iomem *base;
+
+ if (gpio < 32)
+ base = (void *)0x4a310000;
+ else
+ base = (void *)(0x48053000 + ((gpio & ~GPIO_MASK) << 8));
+
+ return base;
+}
+
#define I2C_SLAVE 0x12
noinline int omap4_scale_vcores(unsigned vsel0_pin)
{
+ void __iomem *base;
unsigned int rev = omap4_revision();
+ u32 val = 0;
/* For VC bypass only VCOREx_CGF_FORCE is necessary and
* VCOREx_CFG_VOLTAGE changes can be discarded
@@ -510,8 +526,17 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
* VSEL1 is grounded on board. So the following selects
* VSEL1 = 0 and VSEL0 = 1
*/
- gpio_direction_output(vsel0_pin, 0);
- gpio_set_value(vsel0_pin, 1);
+ base = omap4_get_gpio_base(vsel0_pin);
+
+ val = 1 << (vsel0_pin & GPIO_MASK);
+ writel(val, base + 0x190);
+
+ val = readl(base + 0x134);
+ val &= ~(1 << (vsel0_pin & GPIO_MASK));
+ writel(val, base + 0x134);
+
+ val = 1 << (vsel0_pin & GPIO_MASK);
+ writel(val, base + 0x194);
}
/* set VCORE1 force VSEL */
@@ -576,17 +601,17 @@ const struct gpmc_config omap4_nand_cfg = {
static int omap4_gpio_init(void)
{
add_generic_device("omap-gpio", 0, NULL, 0x4a310100,
- 0x1000, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 1, NULL, 0x48055100,
- 0x1000, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 2, NULL, 0x48057100,
- 0x1000, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 3, NULL, 0x48059100,
- 0x1000, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 4, NULL, 0x4805b100,
- 0x1000, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 5, NULL, 0x4805d100,
- 0x1000, IORESOURCE_MEM, NULL);
+ 0xf00, IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index 7312f5e89b..3a4d910001 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -175,6 +175,7 @@ config S3C_SDRAM_INIT
config S3C_NAND_BOOT
bool
prompt "Booting from NAND"
+ depends on ARCH_S3C24xx
select MTD
select NAND
select NAND_S3C24XX
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 0ffe3705ef..46393e1725 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -7,4 +7,5 @@ pbl-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o mem-s3c64xx.o
obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
+pbl-$(CONFIG_ARCH_S5PCxx) += mem-s5pcxx.o
obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/include/mach/gpio.h b/arch/arm/mach-samsung/include/mach/gpio.h
index 2b4569547e..9e64a841b6 100644
--- a/arch/arm/mach-samsung/include/mach/gpio.h
+++ b/arch/arm/mach-samsung/include/mach/gpio.h
@@ -23,10 +23,8 @@
# include <mach/iomux-s5pcxx.h>
#endif
-void gpio_set_value(unsigned, int);
-int gpio_direction_input(unsigned);
-int gpio_direction_output(unsigned, int);
-int gpio_get_value(unsigned);
+#include <asm-generic/gpio.h>
+
void s3c_gpio_mode(unsigned);
#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 5c75e11e98..8aca2a19e3 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -26,6 +26,7 @@
#include <init.h>
#include <clock.h>
#include <debug_ll.h>
+#include <sizes.h>
#include <linux/clkdev.h>
#include <linux/clk.h>
@@ -182,6 +183,12 @@ void versatile_register_uart(unsigned id)
amba_apb_device_add(NULL, "uart-pl011", id, start, 4096, NULL, 0);
}
+void versatile_register_i2c(void)
+{
+ add_generic_device("versatile-i2c", DEVICE_ID_DYNAMIC, NULL,
+ VERSATILE_I2C_BASE, SZ_4K, IORESOURCE_MEM, NULL);
+}
+
void __noreturn reset_cpu (unsigned long ignored)
{
u32 val;
@@ -196,3 +203,13 @@ void __noreturn reset_cpu (unsigned long ignored)
while(1);
}
EXPORT_SYMBOL(reset_cpu);
+
+static int versatile_init(void)
+{
+ amba_apb_device_add(NULL, "pl061_gpio", 0, 0x101e4000, 4096, NULL, 0);
+ amba_apb_device_add(NULL, "pl061_gpio", 1, 0x101e5000, 4096, NULL, 0);
+ amba_apb_device_add(NULL, "pl061_gpio", 2, 0x101e6000, 4096, NULL, 0);
+ amba_apb_device_add(NULL, "pl061_gpio", 3, 0x101e7000, 4096, NULL, 0);
+ return 0;
+}
+coredevice_initcall(versatile_init);
diff --git a/arch/arm/mach-versatile/include/mach/gpio.h b/arch/arm/mach-versatile/include/mach/gpio.h
new file mode 100644
index 0000000000..306ab4c9f2
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/gpio.h
@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-versatile/include/mach/init.h b/arch/arm/mach-versatile/include/mach/init.h
index 878cde0370..b40e4f90b0 100644
--- a/arch/arm/mach-versatile/include/mach/init.h
+++ b/arch/arm/mach-versatile/include/mach/init.h
@@ -4,5 +4,6 @@
void versatile_add_sdram(u32 size);
void versatile_register_uart(unsigned id);
+void versatile_register_i2c(void);
#endif
diff --git a/arch/arm/pbl/.gitignore b/arch/arm/pbl/.gitignore
index 3384d8b3c1..d71bb7c286 100644
--- a/arch/arm/pbl/.gitignore
+++ b/arch/arm/pbl/.gitignore
@@ -3,3 +3,4 @@ piggy.lzo
zbarebox
zbarebox.bin
zbarebox.lds
+zbarebox.map
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 87c48ed693..608f19bda1 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -566,7 +566,6 @@ do { \
#define __read_64bit_c0_split(source, sel) \
({ \
unsigned long long __val; \
- unsigned long __flags; \
\
if (sel == 0) \
__asm__ __volatile__( \
@@ -592,8 +591,6 @@ do { \
#define __write_64bit_c0_split(source, sel, val) \
do { \
- unsigned long __flags; \
- \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
diff --git a/arch/nios2/lib/longlong.h b/arch/nios2/lib/longlong.h
index 4ab928efad..12716828ad 100644
--- a/arch/nios2/lib/longlong.h
+++ b/arch/nios2/lib/longlong.h
@@ -11,7 +11,7 @@
* useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
-
+ */
/* You have to define the following before including this file:
UWtype -- An unsigned type, default type for operations (typically a "word")
diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile
index c0aa8c6ed2..596c8f8309 100644
--- a/arch/sandbox/Makefile
+++ b/arch/sandbox/Makefile
@@ -39,10 +39,13 @@ archprepare: maketools
PHONY += maketools
-SDL_LIBS-$(CONFIG_DRIVER_VIDEO_SDL) := $(shell pkg-config sdl --libs)
+ifeq ($(CONFIG_DRIVER_VIDEO_SDL),y)
+SDL_LIBS := $(shell pkg-config sdl --libs)
+endif
+
cmd_barebox__ = $(CC) -o $@ -Wl,-T,$(barebox-lds) \
-Wl,--start-group $(barebox-common) -Wl,--end-group \
- -lrt -lpthread $(SDL_LIBS-y)
+ -lrt -lpthread $(SDL_LIBS)
common-y += $(BOARD) arch/sandbox/os/
diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c
index 0dedfe19f4..36c8d622b6 100644
--- a/arch/sandbox/os/common.c
+++ b/arch/sandbox/os/common.c
@@ -311,11 +311,6 @@ int main(int argc, char *argv[])
case 'i':
break;
case 'e':
- sprintf(str, "env%d", envno);
- ret = add_image(optarg, str);
- if (ret)
- exit(1);
- envno++;
break;
case 'O':
fd = open(optarg, O_WRONLY);
@@ -376,6 +371,13 @@ int main(int argc, char *argv[])
exit(1);
fdno++;
break;
+ case 'e':
+ sprintf(str, "env%d", envno);
+ ret = add_image(optarg, str);
+ if (ret)
+ exit(1);
+ envno++;
+ break;
default:
break;
}
@@ -401,7 +403,7 @@ static void print_usage(const char *prgname)
"Usage: %s [OPTIONS]\n"
"Start barebox.\n\n"
"Options:\n\n"
-" -m, "
+" -m, --malloc=<size> Start sandbox with a specified malloc-space size in bytes.\n"
" -i, --image=<file> Map an image file to barebox. This option can be given\n"
" multiple times. The files will show up as\n"
" /dev/fd0 ... /dev/fdx under barebox.\n"
@@ -434,6 +436,10 @@ static void print_usage(const char *prgname)
*
* Options can be:
*
+ * -m, --malloc=\<size\>
+ *
+ * Start sandbox with a specified malloc-space \<size\> in bytes.
+ *
* -i \<file\>
*
* Map a \<file\> to barebox. This option can be given multiple times. The \<file\>s