diff options
Diffstat (limited to 'arch')
197 files changed, 3895 insertions, 959 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9d3f5b2ca7..a683c9c866 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -113,6 +113,15 @@ config ARCH_IMX select WATCHDOG_IMX_RESET_SOURCE select HAS_DEBUG_LL +config ARCH_LAYERSCAPE + bool "NXP Layerscape based" + select GPIOLIB + select HAS_DEBUG_LL + select HAVE_PBL_MULTI_IMAGES + select COMMON_CLK + select CLKDEV_LOOKUP + select COMMON_CLK_OF_PROVIDER + config ARCH_MVEBU bool "Marvell EBU platforms" select COMMON_CLK @@ -198,6 +207,16 @@ config ARCH_S3C64xx select CPU_V6 select GENERIC_GPIO +config ARCH_STM32MP1 + bool "ST stm32mp1xx" + select CPU_V7 + select HAVE_PBL_MULTI_IMAGES + select CLKDEV_LOOKUP + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select HAS_DEBUG_LL + select HAVE_CLK + config ARCH_VERSATILE bool "ARM Versatile boards (ARM926EJ-S)" select GPIOLIB @@ -266,31 +285,33 @@ config ARCH_QEMU endchoice -source arch/arm/cpu/Kconfig -source arch/arm/mach-at91/Kconfig -source arch/arm/mach-bcm283x/Kconfig -source arch/arm/mach-clps711x/Kconfig -source arch/arm/mach-davinci/Kconfig -source arch/arm/mach-digic/Kconfig -source arch/arm/mach-ep93xx/Kconfig -source arch/arm/mach-highbank/Kconfig -source arch/arm/mach-imx/Kconfig -source arch/arm/mach-mxs/Kconfig -source arch/arm/mach-mvebu/Kconfig -source arch/arm/mach-netx/Kconfig -source arch/arm/mach-nomadik/Kconfig -source arch/arm/mach-omap/Kconfig -source arch/arm/mach-pxa/Kconfig -source arch/arm/mach-rockchip/Kconfig -source arch/arm/mach-samsung/Kconfig -source arch/arm/mach-socfpga/Kconfig -source arch/arm/mach-versatile/Kconfig -source arch/arm/mach-vexpress/Kconfig -source arch/arm/mach-tegra/Kconfig -source arch/arm/mach-uemd/Kconfig -source arch/arm/mach-zynq/Kconfig -source arch/arm/mach-qemu/Kconfig -source arch/arm/mach-zynqmp/Kconfig +source "arch/arm/cpu/Kconfig" +source "arch/arm/mach-at91/Kconfig" +source "arch/arm/mach-bcm283x/Kconfig" +source "arch/arm/mach-clps711x/Kconfig" +source "arch/arm/mach-davinci/Kconfig" +source "arch/arm/mach-digic/Kconfig" +source "arch/arm/mach-ep93xx/Kconfig" +source "arch/arm/mach-highbank/Kconfig" +source "arch/arm/mach-imx/Kconfig" +source "arch/arm/mach-layerscape/Kconfig" +source "arch/arm/mach-mxs/Kconfig" +source "arch/arm/mach-mvebu/Kconfig" +source "arch/arm/mach-netx/Kconfig" +source "arch/arm/mach-nomadik/Kconfig" +source "arch/arm/mach-omap/Kconfig" +source "arch/arm/mach-pxa/Kconfig" +source "arch/arm/mach-rockchip/Kconfig" +source "arch/arm/mach-samsung/Kconfig" +source "arch/arm/mach-socfpga/Kconfig" +source "arch/arm/mach-stm32mp1/Kconfig" +source "arch/arm/mach-versatile/Kconfig" +source "arch/arm/mach-vexpress/Kconfig" +source "arch/arm/mach-tegra/Kconfig" +source "arch/arm/mach-uemd/Kconfig" +source "arch/arm/mach-zynq/Kconfig" +source "arch/arm/mach-qemu/Kconfig" +source "arch/arm/mach-zynqmp/Kconfig" config ARM_ASM_UNIFIED bool diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6b5f21a7a9..0daaff2a07 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -87,6 +87,7 @@ machine-$(CONFIG_ARCH_DIGIC) := digic machine-$(CONFIG_ARCH_EP93XX) := ep93xx machine-$(CONFIG_ARCH_HIGHBANK) := highbank machine-$(CONFIG_ARCH_IMX) := imx +machine-$(CONFIG_ARCH_LAYERSCAPE) := layerscape machine-$(CONFIG_ARCH_MXS) := mxs machine-$(CONFIG_ARCH_MVEBU) := mvebu machine-$(CONFIG_ARCH_NOMADIK) := nomadik @@ -96,6 +97,7 @@ machine-$(CONFIG_ARCH_PXA) := pxa machine-$(CONFIG_ARCH_ROCKCHIP) := rockchip machine-$(CONFIG_ARCH_SAMSUNG) := samsung machine-$(CONFIG_ARCH_SOCFPGA) := socfpga +machine-$(CONFIG_ARCH_STM32MP1) := stm32mp1 machine-$(CONFIG_ARCH_VERSATILE) := versatile machine-$(CONFIG_ARCH_VEXPRESS) := vexpress machine-$(CONFIG_ARCH_TEGRA) := tegra @@ -258,6 +260,7 @@ imxcfg-$(CONFIG_MACH_FREESCALE_MX35_3STACK) += $(boarddir)/freescale-mx35-3ds/fl imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX25) += $(boarddir)/eukrea_cpuimx25/flash-header.imxcfg imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX35) += $(boarddir)/eukrea_cpuimx35/flash-header.imxcfg imxcfg-$(CONFIG_MACH_PCM043) += $(boarddir)/phytec-phycore-imx35/flash-header.imxcfg +imxcfg-$(CONFIG_MACH_KINDLE3) += $(boarddir)/kindle3/flash-header.imxcfg ifneq ($(imxcfg-y),) CFG_barebox.imximg := $(imxcfg-y) KBUILD_IMAGE := barebox.imximg diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index c5dc41526b..91f17374c9 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ +obj-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2/ obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += technexion-pico-hobbit/ obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ @@ -156,9 +157,12 @@ obj-$(CONFIG_MACH_QEMU_VIRT64) += qemu-virt64/ obj-$(CONFIG_MACH_WARP7) += element14-warp7/ obj-$(CONFIG_MACH_VF610_TWR) += freescale-vf610-twr/ obj-$(CONFIG_MACH_XILINX_ZCU104) += xilinx-zcu104/ +obj-$(CONFIG_MACH_ZII_COMMON) += zii-common/ obj-$(CONFIG_MACH_ZII_RDU1) += zii-imx51-rdu1/ obj-$(CONFIG_MACH_ZII_RDU2) += zii-imx6q-rdu2/ obj-$(CONFIG_MACH_ZII_IMX8MQ_DEV) += zii-imx8mq-dev/ obj-$(CONFIG_MACH_ZII_VF610_DEV) += zii-vf610-dev/ obj-$(CONFIG_MACH_ZII_IMX7D_RPU2) += zii-imx7d-rpu2/ obj-$(CONFIG_MACH_WAGO_PFC_AM35XX) += wago-pfc-am35xx/ +obj-$(CONFIG_MACH_LS1046ARDB) += ls1046ardb/ +obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/
\ No newline at end of file diff --git a/arch/arm/boards/animeo_ip/lowlevel.c b/arch/arm/boards/animeo_ip/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/animeo_ip/lowlevel.c +++ b/arch/arm/boards/animeo_ip/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c index c76d04b905..2a93428462 100644 --- a/arch/arm/boards/archosg9/lowlevel.c +++ b/arch/arm/boards/archosg9/lowlevel.c @@ -66,9 +66,9 @@ static noinline void archosg9_init_lowlevel(void) omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); } -void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap4_save_bootinfo(data); + omap4_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c index a5c9058552..030c3dbf04 100644 --- a/arch/arm/boards/at91rm9200ek/lowlevel.c +++ b/arch/arm/boards/at91rm9200ek/lowlevel.c @@ -21,7 +21,7 @@ void static inline access_sdram(void) writel(0x00000000, AT91_CHIPSELECT_1); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { u32 r; int i; diff --git a/arch/arm/boards/at91sam9260ek/lowlevel.c b/arch/arm/boards/at91sam9260ek/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/at91sam9260ek/lowlevel.c +++ b/arch/arm/boards/at91sam9260ek/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c index 33aa9430dc..0d7f6d6590 100644 --- a/arch/arm/boards/at91sam9261ek/lowlevel_init.c +++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c @@ -117,7 +117,7 @@ static void __bare_init at91sam9261ek_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c index 478ff11e1d..1d83cdf0bf 100644 --- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c +++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/hardware.h> #include <mach/at91sam9_ddrsdr.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c b/arch/arm/boards/at91sam9m10ihd/lowlevel.c index d5940b987a..4ccbb93557 100644 --- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c +++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9g45.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c b/arch/arm/boards/at91sam9n12ek/lowlevel.c index 47079336e6..f57e439b9e 100644 --- a/arch/arm/boards/at91sam9n12ek/lowlevel.c +++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index 7770bcb7cf..cf3c4ebd0c 100644 --- a/arch/arm/boards/avnet-zedboard/lowlevel.c +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c @@ -27,7 +27,7 @@ #define PLL_DDR_LOCK (1 << 1) #define PLL_IO_LOCK (1 << 2) -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { /* open sesame */ writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK); diff --git a/arch/arm/boards/canon-a1100/lowlevel.c b/arch/arm/boards/canon-a1100/lowlevel.c index 5f4297ea4c..744ce59eaa 100644 --- a/arch/arm/boards/canon-a1100/lowlevel.c +++ b/arch/arm/boards/canon-a1100/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/chumby_falconwing/lowlevel.c b/arch/arm/boards/chumby_falconwing/lowlevel.c index bfc76cc7d4..50bacc620f 100644 --- a/arch/arm/boards/chumby_falconwing/lowlevel.c +++ b/arch/arm/boards/chumby_falconwing/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm.h> #include <mach/imx23-regs.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(IMX_MEMORY_BASE, SZ_64M, NULL); diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c index ac715065f1..231329025b 100644 --- a/arch/arm/boards/clep7212/lowlevel.c +++ b/arch/arm/boards/clep7212/lowlevel.c @@ -20,7 +20,7 @@ # define CLPS711X_CPU_PLL_MULT 40 #endif -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c index c94cb355e2..e4ccbdb2a3 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c +++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c @@ -26,6 +26,8 @@ #include <asm/armlinux.h> +#include "hwdetect.h" + enum board_type { BOARD_ID_CFA10036 = 0, BOARD_ID_CFA10037 = 1, diff --git a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c index 3c7248ef65..50dbcdc150 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c +++ b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm.h> #include <mach/imx28-regs.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2d) { arm_cpu_lowlevel_init(); barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, NULL); diff --git a/arch/arm/boards/dss11/lowlevel.c b/arch/arm/boards/dss11/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/dss11/lowlevel.c +++ b/arch/arm/boards/dss11/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 7ae8a18e06..555dd44445 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -30,7 +30,7 @@ #include <asm-generic/memory_layout.h> #include <asm/system.h> -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r; register uint32_t loops = 0x20000; diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index aca77a7fbf..be78b48bd0 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -30,7 +30,7 @@ #include <asm-generic/memory_layout.h> #include <asm/system.h> -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r, s; unsigned long ccm_base = MX35_CCM_BASE_ADDR; diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c index ad89076329..e09f58e29c 100644 --- a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c @@ -3,7 +3,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { imx5_cpu_lowlevel_init(); arm_setup_stack(0x20000000 - 16); diff --git a/arch/arm/boards/freescale-mx23-evk/lowlevel.c b/arch/arm/boards/freescale-mx23-evk/lowlevel.c index b260f3a7fa..13c7435cd6 100644 --- a/arch/arm/boards/freescale-mx23-evk/lowlevel.c +++ b/arch/arm/boards/freescale-mx23-evk/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm.h> #include <mach/imx23-regs.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(IMX_MEMORY_BASE, SZ_32M, NULL); diff --git a/arch/arm/boards/freescale-mx53-smd/lowlevel.c b/arch/arm/boards/freescale-mx53-smd/lowlevel.c index 88c461da73..c929d274f2 100644 --- a/arch/arm/boards/freescale-mx53-smd/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-smd/lowlevel.c @@ -4,7 +4,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { imx5_cpu_lowlevel_init(); arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); diff --git a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c b/arch/arm/boards/friendlyarm-mini6410/lowlevel.c index 665c31b324..ccbdd13795 100644 --- a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c +++ b/arch/arm/boards/friendlyarm-mini6410/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm-head.h> #include <mach/s3c-iomap.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL); diff --git a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c index 4b9ba87d70..17a7cf1591 100644 --- a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c +++ b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c @@ -53,7 +53,8 @@ static inline void __bare_init debug_led(int led, bool state) #define ADDR_V210_SDMMC_BASE 0xD0037488 #define ADDR_CopySDMMCtoMem 0xD0037F98 -int __bare_init s5p_irom_load_mmc(void *dest, uint32_t start_block, uint16_t block_count) +static int __bare_init s5p_irom_load_mmc(void *dest, uint32_t start_block, + uint16_t block_count) { typedef uint32_t (*func_t) (int32_t, uint32_t, uint16_t, uint32_t*, int8_t); uint32_t chbase = readl(ADDR_V210_SDMMC_BASE); @@ -78,7 +79,7 @@ static __bare_init bool load_stage2(void *dest, size_t size) return s5p_irom_load_mmc(dest, 1, (size+ 511) / 512); } -void __bare_init barebox_arm_reset_vector(void) +void __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c b/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c index 665c31b324..ccbdd13795 100644 --- a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c +++ b/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm-head.h> #include <mach/s3c-iomap.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL); diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c index e066a43dbe..39179c83d8 100644 --- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c +++ b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c @@ -21,6 +21,8 @@ #include <mach/s3c-generic.h> #include <mach/iomux.h> +#include "tiny6410.h" + static const unsigned tiny6410_pin_usage[] = { /* UART0 */ GPA2_GPIO | GPIO_IN | ENABLE_PU, /* CTS not connected */ diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index 66d76ae795..e84ae2c415 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -158,9 +158,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad #define UNALIGNED_ACCESS_ENABLE #define LOW_INT_LATENCY_ENABLE -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - u32 r0, r1; void *iomuxc_base = (void *)MX35_IOMUXC_BASE_ADDR; int i; diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index 98512a976c..6c22784599 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -32,7 +32,7 @@ #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r; int i; diff --git a/arch/arm/boards/haba-knx/lowlevel.c b/arch/arm/boards/haba-knx/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/haba-knx/lowlevel.c +++ b/arch/arm/boards/haba-knx/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/highbank/lowlevel.c b/arch/arm/boards/highbank/lowlevel.c index 83f4c7ad15..6363ec96df 100644 --- a/arch/arm/boards/highbank/lowlevel.c +++ b/arch/arm/boards/highbank/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm.h> #include <asm/system_info.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0x00000000, SZ_512M, NULL); diff --git a/arch/arm/boards/imx233-olinuxino/lowlevel.c b/arch/arm/boards/imx233-olinuxino/lowlevel.c index 5f36c17e52..07a2a0e293 100644 --- a/arch/arm/boards/imx233-olinuxino/lowlevel.c +++ b/arch/arm/boards/imx233-olinuxino/lowlevel.c @@ -115,7 +115,7 @@ static const uint32_t pad_setup[] = { /* Fine-tune the DRAM configuration. */ -void imx23_olinuxino_adjust_memory_params(uint32_t *dram_vals) +static void imx23_olinuxino_adjust_memory_params(uint32_t *dram_vals) { /* Enable Auto Precharge. */ dram_vals[3] |= 1 << 8; diff --git a/arch/arm/boards/karo-tx51/lowlevel.c b/arch/arm/boards/karo-tx51/lowlevel.c index ad89076329..e09f58e29c 100644 --- a/arch/arm/boards/karo-tx51/lowlevel.c +++ b/arch/arm/boards/karo-tx51/lowlevel.c @@ -3,7 +3,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { imx5_cpu_lowlevel_init(); arm_setup_stack(0x20000000 - 16); diff --git a/arch/arm/boards/kindle3/kindle3.c b/arch/arm/boards/kindle3/kindle3.c index e06b3d70ce..1d966ff55a 100644 --- a/arch/arm/boards/kindle3/kindle3.c +++ b/arch/arm/boards/kindle3/kindle3.c @@ -86,7 +86,7 @@ BAREBOX_MAGICVAR_NAMED(global_atags_revision16, global.board.revision16, /* The Kindle3 Kernel expects two custom ATAGs, ATAG_REVISION16 describing * the board and ATAG_SERIAL16 to identify the individual device. */ -struct tag *kindle3_append_atags(struct tag *params) +static struct tag *kindle3_append_atags(struct tag *params) { params = setup_16char_tag(params, ATAG_SERIAL16, get_env_16char_tag("global.board.serial16")); @@ -152,6 +152,7 @@ static int kindle3_devices_init(void) } device_initcall(kindle3_devices_init); +#define FIVEWAY_PAD_CTL (PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_DVS) static iomux_v3_cfg_t kindle3_pads[] = { /* UART1 */ MX35_PAD_RXD1__UART1_RXD_MUX, @@ -183,12 +184,11 @@ static iomux_v3_cfg_t kindle3_pads[] = { MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY, /* fiveway device: up, down, left, right, select */ - MX35_PAD_ATA_DATA14__GPIO2_27, - MX35_PAD_ATA_DATA15__GPIO2_28, - MX35_PAD_TX5_RX0__GPIO1_10, - MX35_PAD_ATA_BUFF_EN__GPIO2_30, - IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, - PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_DVS), + IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, FIVEWAY_PAD_CTL), + IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, FIVEWAY_PAD_CTL), + IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, FIVEWAY_PAD_CTL), + IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, FIVEWAY_PAD_CTL), + IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, FIVEWAY_PAD_CTL), /* Volume keys: up, down */ MX35_PAD_SCKR__GPIO1_4, diff --git a/arch/arm/boards/kindle3/lowlevel.c b/arch/arm/boards/kindle3/lowlevel.c index 58e6318f65..689767f8d6 100644 --- a/arch/arm/boards/kindle3/lowlevel.c +++ b/arch/arm/boards/kindle3/lowlevel.c @@ -31,7 +31,7 @@ #include <asm-generic/memory_layout.h> #include <asm/system.h> -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r, s; unsigned long ccm_base = MX35_CCM_BASE_ADDR; diff --git a/arch/arm/boards/ls1046ardb/Makefile b/arch/arm/boards/ls1046ardb/Makefile new file mode 100644 index 0000000000..03ac4ecca3 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/Makefile @@ -0,0 +1,4 @@ +lwl-y += lowlevel.o +obj-y += board.o +lwl-y += start.o +bbenv-y += defaultenv-ls1046ardb diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c new file mode 100644 index 0000000000..483040957e --- /dev/null +++ b/arch/arm/boards/ls1046ardb/board.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <init.h> +#include <envfs.h> +#include <asm/memory.h> +#include <linux/sizes.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <asm/system.h> + +static int rdb_mem_init(void) +{ + if (!of_machine_is_compatible("fsl,ls1046a-rdb")) + return 0; + + arm_add_mem_device("ram0", 0x80000000, 0x80000000); + arm_add_mem_device("ram1", 0x880000000, 3ULL * SZ_2G); + + printf("Current EL: %d\n", current_el()); + + return 0; +} +mem_initcall(rdb_mem_init); + +static int rdb_postcore_init(void) +{ + if (!of_machine_is_compatible("fsl,ls1046a-rdb")) + return 0; + + defaultenv_append_directory(defaultenv_ls1046ardb); + + return 0; +} + +postcore_initcall(rdb_postcore_init); diff --git a/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth4.mode b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth4.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth4.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth5.mode b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth5.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth5.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth6.mode b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth6.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth6.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth7.mode b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth7.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth7.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c new file mode 100644 index 0000000000..6de16063a7 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/lowlevel.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <debug_ll.h> +#include <ddr_spd.h> +#include <platform_data/mmc-esdhc-imx.h> +#include <i2c/i2c-early.h> +#include <soc/fsl/fsl_ddr_sdram.h> +#include <soc/fsl/immap_lsch2.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/syscounter.h> +#include <asm/cache.h> +#include <mach/errata.h> +#include <mach/lowlevel.h> +#include <mach/xload.h> +#include <mach/layerscape.h> + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, + {2, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,}, + {2, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,}, + {1, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, + {1, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,}, + {1, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,}, + {} +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + +static void ddr_board_options(memctl_options_t *popts, + struct dimm_params *pdimm, + struct fsl_ddr_controller *c) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + unsigned long ddr_freq; + + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = c->ddr_freq / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + popts->data_bus_width = 0; /* 64-bit data bus */ + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR4_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR4_CDR_ODT_80ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x61; +} + +extern char __dtb_fsl_ls1046a_rdb_start[]; + +static struct spd_eeprom spd_eeprom[] = { + { + /* filled during runtime */ + }, +}; + +static struct dimm_params dimm_params[] = { + { + /* filled during runtime */ + }, +}; + +static struct fsl_ddr_controller ddrc[] = { + { + .dimm_slots_per_ctrl = ARRAY_SIZE(dimm_params), + .spd_installed_dimms = spd_eeprom, + .dimm_params = dimm_params, + .memctl_opts.ddrtype = SDRAM_TYPE_DDR4, + .base = IOMEM(LSCH2_DDR_ADDR), + .ddr_freq = LS1046A_DDR_FREQ, + .erratum_A008511 = 1, + .erratum_A009803 = 1, + .erratum_A010165 = 1, + .erratum_A009801 = 1, + .erratum_A009942 = 1, + .chip_selects_per_ctrl = 4, + .board_options = ddr_board_options, + }, +}; + +static struct fsl_ddr_info ls1046a_info = { + .num_ctrls = ARRAY_SIZE(ddrc), + .c = ddrc, +}; + +static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize) +{ + unsigned long membase = LS1046A_DDR_SDRAM_BASE; + struct fsl_i2c *i2c; + int ret; + + if (get_pc() >= membase) { + if (memsize + membase >= 0x100000000) + memsize = 0x100000000 - membase; + + barebox_arm_entry(membase, 0x80000000 - SZ_1M * 67, + __dtb_fsl_ls1046a_rdb_start); + } + + arm_cpu_lowlevel_init(); + debug_ll_init(); + ls1046a_init_lowlevel(); + + i2c = ls1046_i2c_init(IOMEM(LSCH2_I2C1_BASE_ADDR)); + ret = spd_read_eeprom(i2c, i2c_fsl_xfer, 0x51, &spd_eeprom); + if (ret) { + pr_err("Cannot read SPD EEPROM: %d\n", ret); + goto err; + } + + memsize = fsl_ddr_sdram(&ls1046a_info); + + ls1046a_errata_post_ddr(); + + ls1046a_esdhc_start_image(memsize, 0, 0); + +err: + pr_err("Booting failed\n"); + + while (1); +} + +void ls1046ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2); + +__noreturn void ls1046ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2) +{ + relocate_to_current_adr(); + setup_c(); + + ls1046ardb_r_entry(r0); +} diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg new file mode 100644 index 0000000000..5478217524 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg @@ -0,0 +1,22 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg new file mode 100644 index 0000000000..735d46c9f9 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg @@ -0,0 +1,26 @@ +#QSPI clk +0957015c 40100000 +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff +#Change endianness +09550000 000f400c diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg new file mode 100644 index 0000000000..ccedf87e84 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150012 0e000000 00000000 00000000 +11335559 40000012 60040000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003000 00000096 00000001 diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg new file mode 100644 index 0000000000..7b9be0ad3f --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150010 0e000000 00000000 00000000 +11335559 40005012 40025000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003101 00000096 00000001 diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg new file mode 100644 index 0000000000..d3b152282f --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150012 0e000000 00000000 00000000 +11335559 40005012 60040000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003101 00000096 00000001 diff --git a/arch/arm/boards/ls1046ardb/start.S b/arch/arm/boards/ls1046ardb/start.S new file mode 100644 index 0000000000..466782b278 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/start.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <linux/linkage.h> +#include <asm/barebox-arm64.h> + +#define STACK_TOP 0x10020000 + +ENTRY_PROC(start_ls1046ardb) + mov x3, #STACK_TOP + mov sp, x3 + b ls1046ardb_entry +ENTRY_PROC_END(start_ls1046ardb) diff --git a/arch/arm/boards/lubbock/lowlevel.c b/arch/arm/boards/lubbock/lowlevel.c index 1c52b3e36b..abf9e7a98a 100644 --- a/arch/arm/boards/lubbock/lowlevel.c +++ b/arch/arm/boards/lubbock/lowlevel.c @@ -169,7 +169,7 @@ static inline void pxa2xx_dram_init(void) } } -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { unsigned long pssr = PSPR; unsigned long pc = get_pc(); diff --git a/arch/arm/boards/mainstone/lowlevel.c b/arch/arm/boards/mainstone/lowlevel.c index 89839415d4..31f9d76513 100644 --- a/arch/arm/boards/mainstone/lowlevel.c +++ b/arch/arm/boards/mainstone/lowlevel.c @@ -241,7 +241,7 @@ static inline void pxa2xx_dram_init(void) } } -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { unsigned long pssr = PSPR; unsigned long pc = get_pc(); diff --git a/arch/arm/boards/mioa701/lowlevel.c b/arch/arm/boards/mioa701/lowlevel.c index bfb8bad1cc..ee0546ea63 100644 --- a/arch/arm/boards/mioa701/lowlevel.c +++ b/arch/arm/boards/mioa701/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0xa0000000, SZ_64M, NULL); diff --git a/arch/arm/boards/module-mb7707/lowlevel.c b/arch/arm/boards/module-mb7707/lowlevel.c index 0258be6e4b..055e432c1c 100644 --- a/arch/arm/boards/module-mb7707/lowlevel.c +++ b/arch/arm/boards/module-mb7707/lowlevel.c @@ -26,7 +26,7 @@ #define MB7707_SRAM_BASE 0x40000000 #define MB7707_SRAM_SIZE SZ_128M -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/mx31moboard/lowlevel.c b/arch/arm/boards/mx31moboard/lowlevel.c index 02b7ab3c7a..c93f76265c 100644 --- a/arch/arm/boards/mx31moboard/lowlevel.c +++ b/arch/arm/boards/mx31moboard/lowlevel.c @@ -102,7 +102,7 @@ static noinline __noreturn void mx31moboard_startup(void) } -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/nhk8815/lowlevel.c b/arch/arm/boards/nhk8815/lowlevel.c index 33a785fee0..a9ccf1fff5 100644 --- a/arch/arm/boards/nhk8815/lowlevel.c +++ b/arch/arm/boards/nhk8815/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0x0, SZ_64M, NULL); diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index ffbe14836f..6451e5d414 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -89,7 +89,7 @@ static void nxp_imx8mq_evk_sram_setup(void) */ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2) { - arm_cpu_lowlevel_init(); + imx8mq_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c index 318bb9aeb1..fb99ea9278 100644 --- a/arch/arm/boards/omap343xdsp/lowlevel.c +++ b/arch/arm/boards/omap343xdsp/lowlevel.c @@ -548,9 +548,9 @@ static int sdp343x_board_init(void) return 0; } -void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap3_save_bootinfo(data); + omap3_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c index d8a1b9f61d..e06ece2560 100644 --- a/arch/arm/boards/omap3evm/lowlevel.c +++ b/arch/arm/boards/omap3evm/lowlevel.c @@ -161,9 +161,9 @@ static int omap3_evm_board_init(void) return 0; } -void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap3_save_bootinfo(data); + omap3_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c index 005485ba45..006fb627dd 100644 --- a/arch/arm/boards/panda/lowlevel.c +++ b/arch/arm/boards/panda/lowlevel.c @@ -79,9 +79,9 @@ static void noinline panda_init_lowlevel(void) omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1210); } -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap4_save_bootinfo(data); + omap4_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c index 1e96c0893f..09994e4492 100644 --- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c @@ -77,7 +77,7 @@ static void sdram_init(int sdram) MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); } -void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram) +static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram) { unsigned long r; diff --git a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c index 27b56b1e0c..54d8eaaddf 100644 --- a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c @@ -48,7 +48,7 @@ struct sdrc_config { /********************************************************************* * init_sdram_ddr() - Init DDR controller. *********************************************************************/ -void init_sdram_ddr(void) +static void init_sdram_ddr(void) { /* reset sdrc controller */ writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG)); @@ -67,7 +67,7 @@ void init_sdram_ddr(void) /********************************************************************* * config_sdram_ddr() - Init DDR on dev board. *********************************************************************/ -void config_sdram_ddr(u8 cs, u8 cfg) +static void config_sdram_ddr(u8 cs, u8 cfg) { writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs)); @@ -252,9 +252,9 @@ static int pcaal1_board_init(void) return 0; } -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap3_save_bootinfo(data); + omap3_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c index 170ca6896b..c49c4ca841 100644 --- a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c @@ -89,9 +89,9 @@ static noinline void pcaaxl2_init_lowlevel(void) sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ } -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap4_save_bootinfo(data); + omap4_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c index a3ba1c05dd..19296e5dac 100644 --- a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c @@ -31,7 +31,7 @@ #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r; volatile int v; diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c index 5e2f335efa..6bfa0acce3 100644 --- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c @@ -35,7 +35,7 @@ #define CCM_PDR0_399 0x00011000 #define CCM_PDR0_532 0x00001000 -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r, s; unsigned long ccm_base = MX35_CCM_BASE_ADDR; diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c index 02297adb95..6511dae9d4 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c @@ -139,9 +139,9 @@ static void noinline pcm049_init_lowlevel(void) sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */ } -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap4_save_bootinfo(data); + omap4_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index cfee13f3e7..e42e7a6fcc 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -83,7 +83,7 @@ static void phytec_imx8mq_som_sram_setup(void) */ ENTRY_FUNCTION(start_phytec_phycore_imx8mq, r0, r1, r2) { - arm_cpu_lowlevel_init(); + imx8mq_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c index 0ab34b0db6..7127d39943 100644 --- a/arch/arm/boards/pm9261/lowlevel_init.c +++ b/arch/arm/boards/pm9261/lowlevel_init.c @@ -111,7 +111,7 @@ static void __bare_init pm9261_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c index 32850b2981..daeb183831 100644 --- a/arch/arm/boards/pm9263/lowlevel_init.c +++ b/arch/arm/boards/pm9263/lowlevel_init.c @@ -132,7 +132,7 @@ static void __bare_init pm9263_board_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/pm9g45/lowlevel.c b/arch/arm/boards/pm9g45/lowlevel.c index 67454bde26..12cf950685 100644 --- a/arch/arm/boards/pm9g45/lowlevel.c +++ b/arch/arm/boards/pm9g45/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/qemu-virt64/lowlevel.c b/arch/arm/boards/qemu-virt64/lowlevel.c index a60c4b0426..629e2e9f6e 100644 --- a/arch/arm/boards/qemu-virt64/lowlevel.c +++ b/arch/arm/boards/qemu-virt64/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm.h> #include <asm/system_info.h> -void barebox_arm_reset_vector(void) +void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); arm_setup_stack(0x40000000 + SZ_2G - SZ_16K); diff --git a/arch/arm/boards/qil-a926x/lowlevel.c b/arch/arm/boards/qil-a926x/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/qil-a926x/lowlevel.c +++ b/arch/arm/boards/qil-a926x/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c index 60cea7f8e9..bc877f853a 100644 --- a/arch/arm/boards/raspberry-pi/rpi-common.c +++ b/arch/arm/boards/raspberry-pi/rpi-common.c @@ -197,6 +197,8 @@ const struct rpi_model rpi_models_new_scheme[] = { RPI_MODEL(BCM2835_BOARD_REV_ZERO_W, "Zero W", rpi_b_plus_init), RPI_MODEL(BCM2837B0_BOARD_REV_3B_PLUS, "Model 3 B+", rpi_b_plus_init ), RPI_MODEL(BCM2837B0_BOARD_REV_3A_PLUS, "Nodel 3 A+", rpi_b_plus_init), + RPI_MODEL(0xf, "Unknown model", NULL), + RPI_MODEL(BCM2837B0_BOARD_REV_CM3_PLUS, "Compute Module 3+", NULL), }; static int rpi_board_rev = 0; diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c index b791f2a03c..0e25270142 100644 --- a/arch/arm/boards/sama5d3_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c index b791f2a03c..0e25270142 100644 --- a/arch/arm/boards/sama5d3xek/lowlevel.c +++ b/arch/arm/boards/sama5d3xek/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c b/arch/arm/boards/sama5d4_xplained/lowlevel.c index b791f2a03c..0e25270142 100644 --- a/arch/arm/boards/sama5d4_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c index b791f2a03c..0e25270142 100644 --- a/arch/arm/boards/sama5d4ek/lowlevel.c +++ b/arch/arm/boards/sama5d4ek/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/stm32mp157c-dk2/Makefile b/arch/arm/boards/stm32mp157c-dk2/Makefile new file mode 100644 index 0000000000..092c31d6b2 --- /dev/null +++ b/arch/arm/boards/stm32mp157c-dk2/Makefile @@ -0,0 +1,2 @@ +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c new file mode 100644 index 0000000000..cbfe21db6a --- /dev/null +++ b/arch/arm/boards/stm32mp157c-dk2/board.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <linux/sizes.h> +#include <init.h> +#include <asm/memory.h> +#include <mach/stm32.h> + +static int dk2_postcore_init(void) +{ + if (!of_machine_is_compatible("st,stm32mp157c-dk2")) + return 0; + + arm_add_mem_device("ram0", STM32_DDR_BASE, SZ_512M); + + return 0; +} +mem_initcall(dk2_postcore_init); diff --git a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c new file mode 100644 index 0000000000..b8e5959bef --- /dev/null +++ b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/stm32.h> +#include <debug_ll.h> + +extern char __dtb_stm32mp157c_dk2_start[]; + +ENTRY_FUNCTION(start_stm32mp157c_dk2, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_stm32mp157c_dk2_start + get_runtime_offset(); + + barebox_arm_entry(STM32_DDR_BASE, SZ_512M, fdt); +} diff --git a/arch/arm/boards/telit-evk-pro3/lowlevel.c b/arch/arm/boards/telit-evk-pro3/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/telit-evk-pro3/lowlevel.c +++ b/arch/arm/boards/telit-evk-pro3/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c +++ b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c index 8566d27a0a..868df9d6c8 100644 --- a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c +++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c @@ -118,7 +118,7 @@ static void __bare_init tny_a9263_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/tqmls1046a/Makefile b/arch/arm/boards/tqmls1046a/Makefile new file mode 100644 index 0000000000..851a5dcb3d --- /dev/null +++ b/arch/arm/boards/tqmls1046a/Makefile @@ -0,0 +1,3 @@ +lwl-y += lowlevel.o start.o +obj-y += board.o +bbenv-y += defaultenv-tqmls1046a diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c new file mode 100644 index 0000000000..5d6d5ad62c --- /dev/null +++ b/arch/arm/boards/tqmls1046a/board.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <init.h> +#include <envfs.h> +#include <asm/memory.h> +#include <linux/sizes.h> +#include <linux/clk.h> +#include <linux/clkdev.h> + +static int tqmls1046a_mem_init(void) +{ + if (!of_machine_is_compatible("tqc,tqmls1046a")) + return 0; + + arm_add_mem_device("ram0", 0x80000000, SZ_2G); + + return 0; +} +mem_initcall(tqmls1046a_mem_init); + +static int tqmls1046a_postcore_init(void) +{ + if (!of_machine_is_compatible("tqc,tqmls1046a")) + return 0; + + defaultenv_append_directory(defaultenv_tqmls1046a); + + return 0; +} + +postcore_initcall(tqmls1046a_postcore_init); diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth4.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth4.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth4.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth5.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth5.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth5.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth6.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth6.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth6.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth7.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth7.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth7.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c new file mode 100644 index 0000000000..044d6a418d --- /dev/null +++ b/arch/arm/boards/tqmls1046a/lowlevel.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <debug_ll.h> +#include <platform_data/mmc-esdhc-imx.h> +#include <soc/fsl/fsl_ddr_sdram.h> +#include <soc/fsl/immap_lsch2.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/syscounter.h> +#include <asm/cache.h> +#include <mach/errata.h> +#include <mach/lowlevel.h> +#include <mach/xload.h> +#include <mach/layerscape.h> + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {1, 2100, 0, 8, 9, 0x09080806, 0x07060606,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static void ddr_board_options(memctl_options_t *popts, + struct dimm_params *pdimm, + struct fsl_ddr_controller *c) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + unsigned long ddr_freq; + + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* + * Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = c->ddr_freq / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + popts->data_bus_width = 0; /* 64-bit data bus */ + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR4_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR4_CDR_ODT_60ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x61; +} + +static struct dimm_params dimm_params[] = { + { + .n_ranks = 1, + .rank_density = 2147483648u, + .capacity = 2147483648u, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .bank_addr_bits = 2, + .bank_group_bits = 0, + .edc_config = 2, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 833, + .tckmax_ps = 1900, + .caslat_x = 0x000DFA00, // + .taa_ps = 13320, + .trcd_ps = 13320, + .trp_ps = 13320, + .tras_ps = 32000, + .trc_ps = 45320, + .trfc1_ps = 260000, + .trfc2_ps = 160000, + .trfc4_ps = 110000, + .tfaw_ps = 21000, + .trrds_ps = 3300, + .trrdl_ps = 4900, + .tccdl_ps = 5000, + .trfc_slr_ps = 3500000, + .refresh_rate_ps = 7800000, + }, +}; + +static struct fsl_ddr_controller ddrc[] = { + { + .dimm_slots_per_ctrl = ARRAY_SIZE(dimm_params), + .dimm_params = dimm_params, + .memctl_opts.ddrtype = SDRAM_TYPE_DDR4, + .base = IOMEM(LSCH2_DDR_ADDR), + .ddr_freq = LS1046A_DDR_FREQ, + .erratum_A008511 = 1, + .erratum_A009803 = 1, + .erratum_A010165 = 1, + .erratum_A009801 = 1, + .erratum_A009942 = 1, + .chip_selects_per_ctrl = 4, + .board_options = ddr_board_options, + }, +}; + +static struct fsl_ddr_info ls1046a_info = { + .num_ctrls = ARRAY_SIZE(ddrc), + .c = ddrc, +}; + +extern char __dtb_fsl_tqmls1046a_mbls10xxa_start[]; + +static noinline __noreturn void tqmls1046a_r_entry(unsigned long memsize) +{ + unsigned long membase = LS1046A_DDR_SDRAM_BASE; + + if (get_pc() >= membase) { + if (memsize + membase >= 0x100000000) + memsize = 0x100000000 - membase; + + barebox_arm_entry(membase, 0x80000000, + __dtb_fsl_tqmls1046a_mbls10xxa_start); + } + + arm_cpu_lowlevel_init(); + debug_ll_init(); + ls1046a_init_lowlevel(); + + memsize = fsl_ddr_sdram(&ls1046a_info); + + ls1046a_errata_post_ddr(); + + ls1046a_esdhc_start_image(memsize, 0, 0); + + pr_err("Booting failed\n"); + + while (1); +} + +void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned long r2); + +__noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned long r2) +{ + relocate_to_current_adr(); + setup_c(); + + tqmls1046a_r_entry(r0); +} diff --git a/arch/arm/boards/tqmls1046a/start.S b/arch/arm/boards/tqmls1046a/start.S new file mode 100644 index 0000000000..12b785af54 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/start.S @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <linux/linkage.h> +#include <asm/barebox-arm64.h> + +#define STACK_TOP 0x10020000 + +ENTRY_PROC(start_tqmls1046a) + mov x3, #STACK_TOP + mov sp, x3 + b tqmls1046a_entry +ENTRY_PROC_END(start_tqmls1046a) + diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg new file mode 100644 index 0000000000..32865ca2d0 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg @@ -0,0 +1,33 @@ +#Configure QSPI clock +0957015c 40100000 +#Configure Scratch register +09570600 00000000 +09570604 40010000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009c +0957041c 0000009c +09570420 0000009c +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link (errata A-010477) +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#PEX gen3 equalization preset values (errata A-008851) +894008bc 01000000 +89400154 47474747 +89400158 47474747 +894008bc 00000000 +895008bc 01000000 +89500154 47474747 +89500158 47474747 +895008bc 00000000 +896008bc 01000000 +89600154 47474747 +89600158 47474747 +896008bc 00000000 diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg new file mode 100644 index 0000000000..7ac1398123 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg @@ -0,0 +1,35 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009c +0957041c 0000009c +09570420 0000009c +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link (errata A-010477) +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#PEX gen3 equalization preset values (errata A-008851) +894008bc 01000000 +89400154 47474747 +89400158 47474747 +894008bc 00000000 +895008bc 01000000 +89500154 47474747 +89500158 47474747 +895008bc 00000000 +896008bc 01000000 +89600154 47474747 +89600158 47474747 +896008bc 00000000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg new file mode 100644 index 0000000000..6c72d001c3 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg @@ -0,0 +1,84 @@ +# RCW values +# 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00] +# 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110] +# 8: 9 - MEM_PLL_CFG : 0 [0x0 / 0b00] +# 10: 15 - MEM_PLL_RAT : 20 [0x14 / 0b010100] +# 24: 25 - CGA_PLL1_CFG : 0 [0x0 / 0b00] +# 26: 31 - CGA_PLL1_RAT : 16 [0x10 / 0b010000] +# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00] +# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110] +# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000] +# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011] +# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001] +# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11] +# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11] +# 168:169 - SRDS_PLL_PD_S1 : 0 [0x0 / 0b00] +# 170:171 - SRDS_PLL_PD_S2 : 0 [0x0 / 0b00] +# 176:177 - SRDS_DIV_PEX_S1 : 1 [0x1 / 0b01] +# 178:179 - SRDS_DIV_PEX_S2 : 1 [0x1 / 0b01] +# 186:187 - DDR_REFCLK_SEL : 0 [0x0 / 0b00] +# 188:188 - SRDS_REFCLK_SEL_S1 : 0 [0x0 / 0b0] +# 189:189 - SRDS_REFCLK_SEL_S2 : 0 [0x0 / 0b0] +# 190:191 - DDR_FDBK_MULT : 2 [0x2 / 0b10] +# 192:195 - PBI_SRC : 6 [0x6 / 0b0110] +# 201:201 - BOOT_HO : 0 [0x0 / 0b0] +# 202:202 - SB_EN : 0 [0x0 / 0b0] +# 203:211 - IFC_MODE : 64 [0x40 / 0b001000000] +# 224:226 - HWA_CGA_M1_CLK_SEL : 6 [0x6 / 0b110] +# 230:231 - DRAM_LAT : 1 [0x1 / 0b01] +# 232:232 - DDR_RATE : 0 [0x0 / 0b0] +# 234:234 - DDR_RSV0 : 0 [0x0 / 0b0] +# 242:242 - SYS_PLL_SPD : 0 [0x0 / 0b0] +# 243:243 - MEM_PLL_SPD : 0 [0x0 / 0b0] +# 244:244 - CGA_PLL1_SPD : 0 [0x0 / 0b0] +# 245:245 - CGA_PLL2_SPD : 0 [0x0 / 0b0] +# 264:266 - HOST_AGT_PEX : 0 [0x0 / 0b000] +# 288:295 - GP_INFO1 : 0 [0x00 / 0b00000000] +# 299:319 - GP_INFO2 : 0 [0x00000 / 0b000000000000000000000] +# 354:356 - UART_EXT : 0 [0x0 / 0b000] +# 357:359 - IRQ_EXT : 0 [0x0 / 0b000] +# 360:362 - SPI_EXT : 0 [0x0 / 0b000] +# 363:365 - SDHC_EXT : 0 [0x0 / 0b000] +# 366:368 - UART_BASE : 5 [0x5 / 0b101] +# 369:369 - ASLEEP : 0 [0x0 / 0b0] +# 370:370 - RTC : 0 [0x0 / 0b0] +# 371:371 - SDHC_BASE : 0 [0x0 / 0b0] +# 372:372 - IRQ_OUT : 1 [0x1 / 0b1] +# 373:381 - IRQ_BASE : 0 [0x00 / 0b000000000] +# 382:383 - SPI_BASE : 0 [0x0 / 0b00] +# 384:386 - IFC_GRP_A_EXT : 1 [0x1 / 0b001] +# 393:395 - IFC_GRP_D_EXT : 0 [0x0 / 0b000] +# 396:398 - IFC_GRP_E1_EXT : 0 [0x0 / 0b000] +# 399:401 - IFC_GRP_F_EXT : 1 [0x1 / 0b001] +# 405:405 - IFC_GRP_E1_BASE : 0 [0x0 / 0b0] +# 407:407 - IFC_GRP_D_BASE : 0 [0x0 / 0b0] +# 412:413 - IFC_GRP_A_BASE : 0 [0x0 / 0b00] +# 415:415 - IFC_A_22_24 : 0 [0x0 / 0b0] +# 416:418 - EC1 : 0 [0x0 / 0b000] +# 419:421 - EC2 : 0 [0x0 / 0b000] +# 422:423 - LVDD_VSEL : 1 [0x1 / 0b01] +# 424:424 - I2C_IPGCLK_SEL : 0 [0x0 / 0b0] +# 425:425 - EM1 : 0 [0x0 / 0b0] +# 426:426 - EM2 : 0 [0x0 / 0b0] +# 427:427 - EMI2_DMODE : 1 [0x1 / 0b1] +# 428:428 - EMI2_CMODE : 0 [0x0 / 0b0] +# 429:429 - USB_DRVVBUS : 0 [0x0 / 0b0] +# 430:430 - USB_PWRFAULT : 0 [0x0 / 0b0] +# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01] +# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10] +# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1] +# 439:440 - EVDD_VSEL : 0 [0x0 / 0b00] +# 441:443 - IIC2_BASE : 0 [0x0 / 0b000] +# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0] +# 445:447 - IIC2_EXT : 2 [0x2 / 0b010] +# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000] +# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001] + + +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c140010 0e000000 00000000 00000000 +33335559 f0005002 60040000 c1000000 +00000000 00000000 00000000 00028800 +20004000 01103202 00000096 00000001 diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg new file mode 100644 index 0000000000..395c75c7d0 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg @@ -0,0 +1,84 @@ +# RCW values +# 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00] +# 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110] +# 8: 9 - MEM_PLL_CFG : 0 [0x0 / 0b00] +# 10: 15 - MEM_PLL_RAT : 20 [0x14 / 0b010100] +# 24: 25 - CGA_PLL1_CFG : 0 [0x0 / 0b00] +# 26: 31 - CGA_PLL1_RAT : 16 [0x10 / 0b010000] +# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00] +# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110] +# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000] +# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011] +# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001] +# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11] +# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11] +# 168:169 - SRDS_PLL_PD_S1 : 0 [0x0 / 0b00] +# 170:171 - SRDS_PLL_PD_S2 : 0 [0x0 / 0b00] +# 176:177 - SRDS_DIV_PEX_S1 : 1 [0x1 / 0b01] +# 178:179 - SRDS_DIV_PEX_S2 : 1 [0x1 / 0b01] +# 186:187 - DDR_REFCLK_SEL : 0 [0x0 / 0b00] +# 188:188 - SRDS_REFCLK_SEL_S1 : 0 [0x0 / 0b0] +# 189:189 - SRDS_REFCLK_SEL_S2 : 0 [0x0 / 0b0] +# 190:191 - DDR_FDBK_MULT : 2 [0x2 / 0b10] +# 192:195 - PBI_SRC : 4 [0x4 / 0b0100] +# 201:201 - BOOT_HO : 0 [0x0 / 0b0] +# 202:202 - SB_EN : 0 [0x0 / 0b0] +# 203:211 - IFC_MODE : 37 [0x25 / 0b000100101] +# 224:226 - HWA_CGA_M1_CLK_SEL : 6 [0x6 / 0b110] +# 230:231 - DRAM_LAT : 1 [0x1 / 0b01] +# 232:232 - DDR_RATE : 0 [0x0 / 0b0] +# 234:234 - DDR_RSV0 : 0 [0x0 / 0b0] +# 242:242 - SYS_PLL_SPD : 0 [0x0 / 0b0] +# 243:243 - MEM_PLL_SPD : 0 [0x0 / 0b0] +# 244:244 - CGA_PLL1_SPD : 0 [0x0 / 0b0] +# 245:245 - CGA_PLL2_SPD : 0 [0x0 / 0b0] +# 264:266 - HOST_AGT_PEX : 0 [0x0 / 0b000] +# 288:295 - GP_INFO1 : 0 [0x00 / 0b00000000] +# 299:319 - GP_INFO2 : 0 [0x00000 / 0b000000000000000000000] +# 354:356 - UART_EXT : 0 [0x0 / 0b000] +# 357:359 - IRQ_EXT : 0 [0x0 / 0b000] +# 360:362 - SPI_EXT : 0 [0x0 / 0b000] +# 363:365 - SDHC_EXT : 0 [0x0 / 0b000] +# 366:368 - UART_BASE : 5 [0x5 / 0b101] +# 369:369 - ASLEEP : 0 [0x0 / 0b0] +# 370:370 - RTC : 0 [0x0 / 0b0] +# 371:371 - SDHC_BASE : 0 [0x0 / 0b0] +# 372:372 - IRQ_OUT : 1 [0x1 / 0b1] +# 373:381 - IRQ_BASE : 0 [0x00 / 0b000000000] +# 382:383 - SPI_BASE : 0 [0x0 / 0b00] +# 384:386 - IFC_GRP_A_EXT : 1 [0x1 / 0b001] +# 393:395 - IFC_GRP_D_EXT : 0 [0x0 / 0b000] +# 396:398 - IFC_GRP_E1_EXT : 0 [0x0 / 0b000] +# 399:401 - IFC_GRP_F_EXT : 1 [0x1 / 0b001] +# 405:405 - IFC_GRP_E1_BASE : 0 [0x0 / 0b0] +# 407:407 - IFC_GRP_D_BASE : 0 [0x0 / 0b0] +# 412:413 - IFC_GRP_A_BASE : 0 [0x0 / 0b00] +# 415:415 - IFC_A_22_24 : 0 [0x0 / 0b0] +# 416:418 - EC1 : 0 [0x0 / 0b000] +# 419:421 - EC2 : 0 [0x0 / 0b000] +# 422:423 - LVDD_VSEL : 1 [0x1 / 0b01] +# 424:424 - I2C_IPGCLK_SEL : 0 [0x0 / 0b0] +# 425:425 - EM1 : 0 [0x0 / 0b0] +# 426:426 - EM2 : 0 [0x0 / 0b0] +# 427:427 - EMI2_DMODE : 1 [0x1 / 0b1] +# 428:428 - EMI2_CMODE : 0 [0x0 / 0b0] +# 429:429 - USB_DRVVBUS : 0 [0x0 / 0b0] +# 430:430 - USB_PWRFAULT : 0 [0x0 / 0b0] +# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01] +# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10] +# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1] +# 439:440 - EVDD_VSEL : 0 [0x0 / 0b00] +# 441:443 - IIC2_BASE : 0 [0x0 / 0b000] +# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0] +# 445:447 - IIC2_EXT : 2 [0x2 / 0b010] +# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000] +# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001] + + +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c140010 0e000000 00000000 00000000 +33335559 f0005002 40025000 c1000000 +00000000 00000000 00000000 00028800 +20004000 01103202 00000096 00000001 diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg new file mode 100644 index 0000000000..4ef6d576ed --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg @@ -0,0 +1,84 @@ +# RCW values +# 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00] +# 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110] +# 8: 9 - MEM_PLL_CFG : 0 [0x0 / 0b00] +# 10: 15 - MEM_PLL_RAT : 20 [0x14 / 0b010100] +# 24: 25 - CGA_PLL1_CFG : 0 [0x0 / 0b00] +# 26: 31 - CGA_PLL1_RAT : 16 [0x10 / 0b010000] +# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00] +# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110] +# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000] +# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011] +# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001] +# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11] +# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11] +# 168:169 - SRDS_PLL_PD_S1 : 0 [0x0 / 0b00] +# 170:171 - SRDS_PLL_PD_S2 : 0 [0x0 / 0b00] +# 176:177 - SRDS_DIV_PEX_S1 : 1 [0x1 / 0b01] +# 178:179 - SRDS_DIV_PEX_S2 : 1 [0x1 / 0b01] +# 186:187 - DDR_REFCLK_SEL : 0 [0x0 / 0b00] +# 188:188 - SRDS_REFCLK_SEL_S1 : 0 [0x0 / 0b0] +# 189:189 - SRDS_REFCLK_SEL_S2 : 0 [0x0 / 0b0] +# 190:191 - DDR_FDBK_MULT : 2 [0x2 / 0b10] +# 192:195 - PBI_SRC : 6 [0x6 / 0b0110] +# 201:201 - BOOT_HO : 0 [0x0 / 0b0] +# 202:202 - SB_EN : 0 [0x0 / 0b0] +# 203:211 - IFC_MODE : 64 [0x40 / 0b001000000] +# 224:226 - HWA_CGA_M1_CLK_SEL : 6 [0x6 / 0b110] +# 230:231 - DRAM_LAT : 1 [0x1 / 0b01] +# 232:232 - DDR_RATE : 0 [0x0 / 0b0] +# 234:234 - DDR_RSV0 : 0 [0x0 / 0b0] +# 242:242 - SYS_PLL_SPD : 0 [0x0 / 0b0] +# 243:243 - MEM_PLL_SPD : 0 [0x0 / 0b0] +# 244:244 - CGA_PLL1_SPD : 0 [0x0 / 0b0] +# 245:245 - CGA_PLL2_SPD : 0 [0x0 / 0b0] +# 264:266 - HOST_AGT_PEX : 0 [0x0 / 0b000] +# 288:295 - GP_INFO1 : 0 [0x00 / 0b00000000] +# 299:319 - GP_INFO2 : 0 [0x00000 / 0b000000000000000000000] +# 354:356 - UART_EXT : 0 [0x0 / 0b000] +# 357:359 - IRQ_EXT : 0 [0x0 / 0b000] +# 360:362 - SPI_EXT : 0 [0x0 / 0b000] +# 363:365 - SDHC_EXT : 0 [0x0 / 0b000] +# 366:368 - UART_BASE : 5 [0x5 / 0b101] +# 369:369 - ASLEEP : 0 [0x0 / 0b0] +# 370:370 - RTC : 0 [0x0 / 0b0] +# 371:371 - SDHC_BASE : 0 [0x0 / 0b0] +# 372:372 - IRQ_OUT : 1 [0x1 / 0b1] +# 373:381 - IRQ_BASE : 0 [0x00 / 0b000000000] +# 382:383 - SPI_BASE : 0 [0x0 / 0b00] +# 384:386 - IFC_GRP_A_EXT : 1 [0x1 / 0b001] +# 393:395 - IFC_GRP_D_EXT : 0 [0x0 / 0b000] +# 396:398 - IFC_GRP_E1_EXT : 0 [0x0 / 0b000] +# 399:401 - IFC_GRP_F_EXT : 1 [0x1 / 0b001] +# 405:405 - IFC_GRP_E1_BASE : 0 [0x0 / 0b0] +# 407:407 - IFC_GRP_D_BASE : 0 [0x0 / 0b0] +# 412:413 - IFC_GRP_A_BASE : 0 [0x0 / 0b00] +# 415:415 - IFC_A_22_24 : 0 [0x0 / 0b0] +# 416:418 - EC1 : 0 [0x0 / 0b000] +# 419:421 - EC2 : 0 [0x0 / 0b000] +# 422:423 - LVDD_VSEL : 1 [0x1 / 0b01] +# 424:424 - I2C_IPGCLK_SEL : 0 [0x0 / 0b0] +# 425:425 - EM1 : 0 [0x0 / 0b0] +# 426:426 - EM2 : 0 [0x0 / 0b0] +# 427:427 - EMI2_DMODE : 1 [0x1 / 0b1] +# 428:428 - EMI2_CMODE : 0 [0x0 / 0b0] +# 429:429 - USB_DRVVBUS : 0 [0x0 / 0b0] +# 430:430 - USB_PWRFAULT : 0 [0x0 / 0b0] +# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01] +# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10] +# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1] +# 439:440 - EVDD_VSEL : 2 [0x2 / 0b10] +# 441:443 - IIC2_BASE : 0 [0x0 / 0b000] +# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0] +# 445:447 - IIC2_EXT : 1 [0x1 / 0b001] +# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000] +# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001] + + +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c140010 0e000000 00000000 00000000 +33335559 f0005002 60040000 c1000000 +00000000 00000000 00000000 00028800 +20004000 01103301 00000096 00000001 diff --git a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c +++ b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c index a7dd2b2ada..b362fcf7d4 100644 --- a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c +++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c @@ -122,7 +122,7 @@ static void __bare_init usb_a9263_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/versatile/lowlevel.c b/arch/arm/boards/versatile/lowlevel.c index 33a785fee0..a9ccf1fff5 100644 --- a/arch/arm/boards/versatile/lowlevel.c +++ b/arch/arm/boards/versatile/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0x0, SZ_64M, NULL); diff --git a/arch/arm/boards/virt2real/lowlevel.c b/arch/arm/boards/virt2real/lowlevel.c index 8ec3d04fef..264ebee893 100644 --- a/arch/arm/boards/virt2real/lowlevel.c +++ b/arch/arm/boards/virt2real/lowlevel.c @@ -26,7 +26,7 @@ #define VIRT2REAL_SRAM_BASE 0x82000000 #define VIRT2REAL_SRAM_SIZE SZ_16M -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/zii-common/Makefile b/arch/arm/boards/zii-common/Makefile new file mode 100644 index 0000000000..fcc5cdf97d --- /dev/null +++ b/arch/arm/boards/zii-common/Makefile @@ -0,0 +1 @@ +obj-y += board.o switch-cmd.o pn-fixup.o diff --git a/arch/arm/boards/zii-common/board.c b/arch/arm/boards/zii-common/board.c new file mode 100644 index 0000000000..20ec64d2d4 --- /dev/null +++ b/arch/arm/boards/zii-common/board.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2019 Zodiac Inflight Innovation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <globalvar.h> +#include <init.h> +#include <fs.h> + +static int rdu_networkconfig(void) +{ + static char *rdu_netconfig; + struct device_d *sp_dev; + + if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && + !of_machine_is_compatible("zii,imx6qp-zii-rdu2") && + !of_machine_is_compatible("zii,imx51-rdu1")) + return 0; + + sp_dev = get_device_by_name("sp"); + if (!sp_dev) { + pr_warn("no sp device found, network config not available!\n"); + return -ENODEV; + } + + rdu_netconfig = basprintf("ip=%s:::%s::eth0:", + dev_get_param(sp_dev, "ipaddr"), + dev_get_param(sp_dev, "netmask")); + + globalvar_add_simple_string("linux.bootargs.rdu_network", + &rdu_netconfig); + + return 0; +} +late_initcall(rdu_networkconfig); + +#define I210_CFGWORD_PCIID_157B 0x157b1a11 +static int rdu_i210_invm(void) +{ + int fd; + u32 val; + + if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && + !of_machine_is_compatible("zii,imx6qp-zii-rdu2") && + !of_machine_is_compatible("zii,imx8mq-ultra")) + return 0; + + fd = open("/dev/e1000-invm0", O_RDWR); + if (fd < 0) { + pr_err("could not open e1000 iNVM device!\n"); + return fd; + } + + pread(fd, &val, sizeof(val), 0); + if (val == I210_CFGWORD_PCIID_157B) { + pr_debug("i210 already programmed correctly\n"); + return 0; + } + + val = I210_CFGWORD_PCIID_157B; + pwrite(fd, &val, sizeof(val), 0); + + return 0; +} +late_initcall(rdu_i210_invm); diff --git a/arch/arm/boards/zii-common/pn-fixup.c b/arch/arm/boards/zii-common/pn-fixup.c new file mode 100644 index 0000000000..a665199917 --- /dev/null +++ b/arch/arm/boards/zii-common/pn-fixup.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2019 Zodiac Inflight Innovation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <linux/nvmem-consumer.h> + +#include "pn-fixup.h" + +char *zii_read_part_number(const char *cell_name, size_t cell_size) +{ + struct device_node *np; + + np = of_find_node_by_name(NULL, "device-info"); + if (!np) { + pr_warn("No device information found\n"); + return ERR_PTR(-ENOENT); + } + + return nvmem_cell_get_and_read(np, cell_name, cell_size); +} diff --git a/arch/arm/boards/zii-common/pn-fixup.h b/arch/arm/boards/zii-common/pn-fixup.h new file mode 100644 index 0000000000..39b848bd00 --- /dev/null +++ b/arch/arm/boards/zii-common/pn-fixup.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2019 Zodiac Inflight Innovation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ZII_PN_FIXUP__ +#define __ZII_PN_FIXUP__ + +struct zii_pn_fixup { + const char *pn; + void (*callback) (const struct zii_pn_fixup *fixup); +}; + +char *zii_read_part_number(const char *, size_t); +/** + * __zii_process_fixups - Process array of ZII part number based fixups + * + * @__fixups: Array of part number base fixups + * @__cell_name: Name of the NVMEM cell containing the part number + * @__cell_size: Size of the NVMEM cell containing the part number + * + * NOTE: Keeping this code as a marcro allows us to avoid restricting + * the type of __fixups to an array of struct zii_pn_fixup. This is + * really convenient becuase it allows us to do things like + * + * struct zii_foo_fixup { + * struct zii_pn_fixup parent; + * type1 custom_field_1 + * type2 custom_field_2 + * ... + * }; + * + * ... + * + * const struct zii_foo_fixup foo_fixups[] = { + * { fixup1 }, + * { fixup2 }, + * { fixup3 }, + * }; + * + * ... + * + * __zii_process_fixups(foo_fixups, "blah", BLAH_LENGTH); + * + * which allows us to have the most compact definition of array of + * fixups + */ +#define __zii_process_fixups(__fixups, __cell_name, __cell_size) \ + do { \ + char *__pn = zii_read_part_number(__cell_name, \ + __cell_size); \ + const struct zii_pn_fixup *__fixup; \ + unsigned int __i; \ + bool __match_found = false; \ + \ + if (WARN_ON(IS_ERR(__pn))) \ + break; \ + \ + for (__i = 0; __i < ARRAY_SIZE(__fixups); __i++) { \ + __fixup = \ + (const struct zii_pn_fixup *) &__fixups[__i]; \ + \ + if (strstr(__pn, __fixup->pn)) { \ + pr_debug("%s->%pS\n", __func__, \ + __fixup->callback); \ + __match_found = true; \ + __fixup->callback(__fixup); \ + } \ + } \ + if (!__match_found) \ + pr_err("No config fixups found for P/N %s!\n", __pn); \ + free(__pn); \ + } while (0) + +#define DDS_PART_NUMBER_SIZE 15 +#define LRU_PART_NUMBER_SIZE 15 + +#define zii_process_dds_fixups(_fixups) \ + __zii_process_fixups(_fixups, "dds-part-number", DDS_PART_NUMBER_SIZE) + +#define zii_process_lru_fixups(_fixups) \ + __zii_process_fixups(_fixups, "lru-part-number", LRU_PART_NUMBER_SIZE) + +#endif /* __ZII_PN_FIXUP__ */ diff --git a/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c b/arch/arm/boards/zii-common/switch-cmd.c index bdba46fb36..30438053a1 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c +++ b/arch/arm/boards/zii-common/switch-cmd.c @@ -11,19 +11,16 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <common.h> #include <command.h> +#include <common.h> #include <i2c/i2c.h> +#include <linux/mfd/rave-sp.h> -static int do_rave_switch_reset(int argc, char *argv[]) +static int do_rdu2_switch_reset(void) { struct i2c_client client; u8 reg; - if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && - !of_machine_is_compatible("zii,imx6qp-zii-rdu2")) - return -ENODEV; - client.adapter = i2c_get_adapter(1); if (!client.adapter) return -ENODEV; @@ -42,8 +39,35 @@ static int do_rave_switch_reset(int argc, char *argv[]) return 0; } +static int do_rdu1_switch_reset(void) +{ + struct device_d *sp_dev = get_device_by_name("sp"); + struct rave_sp *sp = sp_dev->priv; + u8 cmd[] = { + [0] = RAVE_SP_CMD_RESET_ETH_SWITCH, + [1] = 0 + }; + + if (IS_ENABLED(CONFIG_RAVE_SP_CORE)) + return rave_sp_exec(sp, cmd, sizeof(cmd), NULL, 0); + else + return -ENODEV; +} + +static int do_rave_switch_reset(int argc, char *argv[]) +{ + if (of_machine_is_compatible("zii,imx6q-zii-rdu2") || + of_machine_is_compatible("zii,imx6qp-zii-rdu2")) + return do_rdu2_switch_reset(); + + if (of_machine_is_compatible("zii,imx51-rdu1")) + return do_rdu1_switch_reset(); + + return -ENODEV; +} + BAREBOX_CMD_START(rave_reset_switch) .cmd = do_rave_switch_reset, - BAREBOX_CMD_DESC("reset ethernet switch on RDU2") + BAREBOX_CMD_DESC("reset ethernet switch on RDU") BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP) BAREBOX_CMD_END diff --git a/arch/arm/boards/zii-imx6q-rdu2/Makefile b/arch/arm/boards/zii-imx6q-rdu2/Makefile index 10dfba3a3c..c6285362f2 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/Makefile +++ b/arch/arm/boards/zii-imx6q-rdu2/Makefile @@ -1,3 +1,3 @@ -obj-y += board.o switch-cmd.o +obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-rdu2 diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c index 6352f49c5a..6adb0b1c6f 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/board.c +++ b/arch/arm/boards/zii-imx6q-rdu2/board.c @@ -23,6 +23,30 @@ #include <mach/imx6.h> #include <net.h> #include <linux/nvmem-consumer.h> +#include "../zii-common/pn-fixup.h" + +enum rdu2_lcd_interface_type { + IT_SINGLE_LVDS, + IT_DUAL_LVDS, + IT_EDP +}; + +enum rdu2_lvds_busformat { + BF_NONE, + BF_JEIDA, + BF_SPWG +}; + +#define RDU2_LRU_FLAG_EGALAX BIT(0) +#define RDU2_LRU_FLAG_NO_FEC BIT(1) + +struct rdu2_lru_fixup { + struct zii_pn_fixup fixup; + unsigned int flags; + enum rdu2_lcd_interface_type type; + enum rdu2_lvds_busformat bus_format; + const char *compatible; +}; #define RDU2_DAC1_RESET IMX_GPIO_NR(1, 0) #define RDU2_DAC2_RESET IMX_GPIO_NR(1, 2) @@ -190,31 +214,254 @@ static int rdu2_ethernet_init(void) } late_initcall(rdu2_ethernet_init); -#define I210_CFGWORD_PCIID_157B 0x157b1a11 -static int rdu2_i210_invm(void) +static int rdu2_fixup_egalax_ts(struct device_node *root, void *context) { - int fd; - u32 val; + struct device_node *np; - if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && - !of_machine_is_compatible("zii,imx6qp-zii-rdu2")) - return 0; + /* + * The 32" unit has a EETI eGalax touchscreen instead of the + * Synaptics RMI4 found on other units. + */ + pr_info("Enabling eGalax touchscreen instead of RMI4\n"); - fd = open("/dev/e1000-invm0", O_RDWR); - if (fd < 0) { - pr_err("could not open e1000 iNVM device!\n"); - return fd; + np = of_find_compatible_node(root, NULL, "syna,rmi4-i2c"); + if (!np) + return -ENODEV; + + of_device_disable(np); + + np = of_find_compatible_node(root, NULL, "eeti,exc3000"); + if (!np) + return -ENODEV; + + of_device_enable(np); + of_property_write_u32(np->parent, "clock-frequency", 200000); + + + return 0; +} + +static int rdu2_fixup_dsa(struct device_node *root, void *context) +{ + struct device_node *switch_np, *np; + phandle i210_handle; + + /* + * The 12.1" unit has no FEC connection, so we need to rewrite + * the i210 port into the CPU port and delete the FEC port, + * which is part of the common setup. + */ + pr_info("Rewriting i210 switch port into CPU port\n"); + + switch_np = of_find_compatible_node(root, NULL, "marvell,mv88e6085"); + if (!switch_np) + return -ENODEV; + + np = of_find_node_by_name(switch_np, "port@2"); + if (!np) + return -ENODEV; + + of_delete_node(np); + + np = of_find_node_by_name(root, "i210@0"); + if (!np) + return -ENODEV; + + i210_handle = of_node_create_phandle(np); + + np = of_find_node_by_name(switch_np, "port@0"); + if (!np) + return -ENODEV; + + of_property_write_u32(np, "ethernet", i210_handle); + of_property_write_string(np, "label", "cpu"); + + return 0; +} + +static int rdu2_fixup_edp(struct device_node *root) +{ + const bool kernel_fixup = root != NULL; + struct device_node *np; + + if (kernel_fixup) { + /* + * Kernel DT fixup needs this additional step + */ + pr_info("Found eDP display, enabling parallel output " + "and eDP bridge.\n"); + np = of_find_compatible_node(root, NULL, + "fsl,imx-parallel-display"); + if (!np) + return -ENODEV; + + of_device_enable(np); } - pread(fd, &val, sizeof(val), 0); - if (val == I210_CFGWORD_PCIID_157B) { - pr_debug("i210 already programmed correctly\n"); - return 0; + np = of_find_compatible_node(root, NULL, "toshiba,tc358767"); + if (!np) + return -ENODEV; + + of_device_enable(np); + + return 0; +} + +static int rdu2_fixup_lvds(struct device_node *root, + const struct rdu2_lru_fixup *fixup) +{ + const bool kernel_fixup = root != NULL; + struct device_node *np; + + /* + * LVDS panels need the correct compatible + */ + pr_info("Found LVDS display, enabling %s channel LDB and " + "panel with compatible \"%s\".\n", + fixup->type == IT_DUAL_LVDS ? "dual" : "single", + fixup->compatible); + /* + * LVDS panels need the correct timings + */ + np = of_find_node_by_name(root, "panel"); + if (!np) + return -ENODEV; + + if (kernel_fixup) { + of_device_enable(np); + of_property_write_string(np, "compatible", fixup->compatible); + } else { + struct device_node *child, *tmp; + + of_device_enable_and_register(np); + /* + * Delete all mode entries, which aren't suited for the + * current display + */ + np = of_find_node_by_name(np, "display-timings"); + if (!np) + return -ENODEV; + + for_each_child_of_node_safe(np, tmp, child) { + if (!of_device_is_compatible(child, + fixup->compatible)) + of_delete_node(child); + } } + /* + * enable LDB channel 0 and set correct interface mode + */ + np = of_find_compatible_node(root, NULL, "fsl,imx6q-ldb"); + if (!np) + return -ENODEV; + + if (kernel_fixup) + of_device_enable(np); + else + of_device_enable_and_register(np); + + if (fixup->type == IT_DUAL_LVDS) + of_set_property(np, "fsl,dual-channel", NULL, 0, 1); + + np = of_find_node_by_name(np, "lvds-channel@0"); + if (!np) + return -ENODEV; + + of_device_enable(np); + + if (!kernel_fixup) { + of_property_write_string(np, "fsl,data-mapping", + fixup->bus_format == BF_SPWG ? + "spwg" : "jeida"); + } + + return 0; +} + +static int rdu2_fixup_display(struct device_node *root, void *context) +{ + const struct rdu2_lru_fixup *fixup = context; + /* + * If the panel is eDP, just enable the parallel output and + * eDP bridge + */ + if (fixup->type == IT_EDP) + return rdu2_fixup_edp(root); + + return rdu2_fixup_lvds(root, context); +} + +static void rdu2_lru_fixup(const struct zii_pn_fixup *context) +{ + const struct rdu2_lru_fixup *fixup = + container_of(context, struct rdu2_lru_fixup, fixup); + + WARN_ON(rdu2_fixup_display(NULL, (void *)context)); + of_register_fixup(rdu2_fixup_display, (void *)context); + + if (fixup->flags & RDU2_LRU_FLAG_EGALAX) + of_register_fixup(rdu2_fixup_egalax_ts, NULL); + + if (fixup->flags & RDU2_LRU_FLAG_NO_FEC) + of_register_fixup(rdu2_fixup_dsa, NULL); +} + +#define RDU2_LRU_FIXUP(__pn, __flags, __panel) \ + { \ + { __pn, rdu2_lru_fixup }, \ + __flags, \ + __panel \ + } + +#define RDU2_PANEL_10P1 IT_SINGLE_LVDS, BF_SPWG, "innolux,g121i1-l01" +#define RDU2_PANEL_11P6 IT_EDP, BF_NONE, NULL +#define RDU2_PANEL_12P1 IT_SINGLE_LVDS, BF_SPWG, "nec,nl12880bc20-05" +#define RDU2_PANEL_13P3 IT_DUAL_LVDS, BF_JEIDA, "auo,g133han01" +#define RDU2_PANEL_15P6 IT_DUAL_LVDS, BF_SPWG, "nlt,nl192108ac18-02d" +#define RDU2_PANEL_18P5 IT_DUAL_LVDS, BF_SPWG, "auo,g185han01" +#define RDU2_PANEL_32P0 IT_DUAL_LVDS, BF_SPWG, "auo,p320hvn03" + +static const struct rdu2_lru_fixup rdu2_lru_fixups[] = { + RDU2_LRU_FIXUP("00-5122-01", RDU2_LRU_FLAG_NO_FEC, RDU2_PANEL_12P1), + RDU2_LRU_FIXUP("00-5122-02", RDU2_LRU_FLAG_NO_FEC, RDU2_PANEL_12P1), + RDU2_LRU_FIXUP("00-5120-01", 0, RDU2_PANEL_10P1), + RDU2_LRU_FIXUP("00-5120-02", 0, RDU2_PANEL_10P1), + RDU2_LRU_FIXUP("00-5120-51", 0, RDU2_PANEL_10P1), + RDU2_LRU_FIXUP("00-5120-52", 0, RDU2_PANEL_10P1), + RDU2_LRU_FIXUP("00-5123-01", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-02", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-03", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-51", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-52", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-53", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5124-01", 0, RDU2_PANEL_13P3), + RDU2_LRU_FIXUP("00-5124-02", 0, RDU2_PANEL_13P3), + RDU2_LRU_FIXUP("00-5124-03", 0, RDU2_PANEL_13P3), + RDU2_LRU_FIXUP("00-5124-53", 0, RDU2_PANEL_13P3), + RDU2_LRU_FIXUP("00-5127-01", 0, RDU2_PANEL_15P6), + RDU2_LRU_FIXUP("00-5127-02", 0, RDU2_PANEL_15P6), + RDU2_LRU_FIXUP("00-5127-03", 0, RDU2_PANEL_15P6), + RDU2_LRU_FIXUP("00-5127-53", 0, RDU2_PANEL_15P6), + RDU2_LRU_FIXUP("00-5125-01", 0, RDU2_PANEL_18P5), + RDU2_LRU_FIXUP("00-5125-02", 0, RDU2_PANEL_18P5), + RDU2_LRU_FIXUP("00-5125-03", 0, RDU2_PANEL_18P5), + RDU2_LRU_FIXUP("00-5125-53", 0, RDU2_PANEL_18P5), + RDU2_LRU_FIXUP("00-5132-01", RDU2_LRU_FLAG_EGALAX, RDU2_PANEL_32P0), + RDU2_LRU_FIXUP("00-5132-02", RDU2_LRU_FLAG_EGALAX, RDU2_PANEL_32P0), +}; + +/* + * This initcall needs to be executed before coredevices, so we have a chance + * to fix up the internal DT with the correct display information. + */ +static int rdu2_process_fixups(void) +{ + if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && + !of_machine_is_compatible("zii,imx6qp-zii-rdu2")) + return 0; - val = I210_CFGWORD_PCIID_157B; - pwrite(fd, &val, sizeof(val), 0); + zii_process_lru_fixups(rdu2_lru_fixups); return 0; } -late_initcall(rdu2_i210_invm); +postmmu_initcall(rdu2_process_fixups); diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 059e4c9efd..0fd2ddfca5 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -145,7 +145,7 @@ ENTRY_FUNCTION(start_zii_imx8mq_dev, r0, r1, r2) unsigned int system_type; void *fdt; - arm_cpu_lowlevel_init(); + imx8mq_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c index a8fa1ef61f..1296f70317 100644 --- a/arch/arm/boards/zii-vf610-dev/board.c +++ b/arch/arm/boards/zii-vf610-dev/board.c @@ -123,6 +123,7 @@ static int zii_vf610_dev_set_hostname(void) const char *hostname; } boards[] = { { "zii,vf610spu3", "spu3" }, + { "zii,vf610spb4", "spb4" }, { "zii,vf610cfu1", "cfu1" }, { "zii,vf610dev-b", "dev-rev-b" }, { "zii,vf610dev-c", "dev-rev-c" }, @@ -168,7 +169,8 @@ static int zii_vf610_register_emmc_bbu(void) int ret; if (!of_machine_is_compatible("zii,vf610spu3") && - !of_machine_is_compatible("zii,vf610cfu1")) + !of_machine_is_compatible("zii,vf610cfu1") && + !of_machine_is_compatible("zii,vf610spb4")) return 0; ret = vf610_bbu_internal_mmcboot_register_handler("eMMC", diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c index d19318026c..79588ac381 100644 --- a/arch/arm/boards/zii-vf610-dev/lowlevel.c +++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c @@ -41,6 +41,7 @@ enum zii_platform_vf610_type { ZII_PLATFORM_VF610_SSMB_SPU3 = 0x03, ZII_PLATFORM_VF610_CFU1 = 0x04, ZII_PLATFORM_VF610_DEV_REV_C = 0x05, + ZII_PLATFORM_VF610_SPB4 = 0x06, }; static unsigned int get_system_type(void) @@ -77,7 +78,8 @@ extern char __dtb_vf610_zii_dev_rev_b_start[]; extern char __dtb_vf610_zii_dev_rev_c_start[]; extern char __dtb_vf610_zii_cfu1_start[]; extern char __dtb_vf610_zii_ssmb_spu3_start[]; -extern char __dtb_vf610_zii_scu4_aib_rev_c_start[]; +extern char __dtb_vf610_zii_scu4_aib_start[]; +extern char __dtb_vf610_zii_spb4_start[]; ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) { @@ -121,7 +123,7 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) fdt = __dtb_vf610_zii_dev_rev_b_start; break; case ZII_PLATFORM_VF610_SCU4_AIB: - fdt = __dtb_vf610_zii_scu4_aib_rev_c_start; + fdt = __dtb_vf610_zii_scu4_aib_start; break; case ZII_PLATFORM_VF610_DEV_REV_C: fdt = __dtb_vf610_zii_dev_rev_c_start; @@ -132,6 +134,9 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) case ZII_PLATFORM_VF610_SSMB_SPU3: fdt = __dtb_vf610_zii_ssmb_spu3_start; break; + case ZII_PLATFORM_VF610_SPB4: + fdt = __dtb_vf610_zii_spb4_start; + break; } vf610_barebox_entry(fdt + get_runtime_offset()); diff --git a/arch/arm/boards/zylonite/lowlevel.c b/arch/arm/boards/zylonite/lowlevel.c index 9f1aa6641c..5b95d879fa 100644 --- a/arch/arm/boards/zylonite/lowlevel.c +++ b/arch/arm/boards/zylonite/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0x80000000, SZ_64M, NULL); diff --git a/arch/arm/configs/kindle-mx50_defconfig b/arch/arm/configs/kindle-mx50_defconfig index 31bfc9c06b..95b505fda2 100644 --- a/arch/arm/configs/kindle-mx50_defconfig +++ b/arch/arm/configs/kindle-mx50_defconfig @@ -4,8 +4,8 @@ CONFIG_MACH_KINDLE_MX50=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y +CONFIG_IMAGE_COMPRESSION_XZKERN=y CONFIG_MMU=y -CONFIG_MMU_EARLY=y CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y @@ -13,7 +13,6 @@ CONFIG_RELOCATABLE=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y -CONFIG_FLEXIBLE_BOOTARGS=y CONFIG_BOOTM_SHOW_TYPE=y CONFIG_BOOTM_VERBOSE=y CONFIG_BOOTM_INITRD=y @@ -24,47 +23,42 @@ CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_MEMINFO=y -CONFIG_CMD_BOOT=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOADY=y CONFIG_CMD_RESET=y -CONFIG_CMD_AUTOMOUNT=y CONFIG_CMD_EXPORT=y -CONFIG_CMD_GLOBAL=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y CONFIG_CMD_DETECT=y CONFIG_CMD_FLASH=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y CONFIG_CMD_USBGADGET=y -CONFIG_CMD_OF_DUMP=y CONFIG_CMD_OFTREE=y CONFIG_OFDEVICE=y -CONFIG_OF_GPIO=y CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_MTD=y -CONFIG_MTD_WRITE=y CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_USB=y CONFIG_USB_HOST=y CONFIG_USB_IMX_CHIPIDEA=y CONFIG_USB_EHCI=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DRIVER_ARC=y CONFIG_USB_GADGET_SERIAL=y CONFIG_USB_GADGET_FASTBOOT=y CONFIG_MCI=y -CONFIG_MCI_INFO=y -CONFIG_MCI_WRITE=y +CONFIG_MCI_STARTUP=y CONFIG_MCI_MMC_BOOT_PARTITIONS=y CONFIG_MCI_IMX_ESDHC=y -CONFIG_PINCTRL=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED=y CONFIG_GENERIC_PHY=y CONFIG_USB_NOP_XCEIV=y -CONFIG_FS_AUTOMOUNT=y -CONFIG_IMAGE_COMPRESSION_XZKERN=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/kindle3_defconfig b/arch/arm/configs/kindle3_defconfig index a4e08dfad0..98691c3a81 100644 --- a/arch/arm/configs/kindle3_defconfig +++ b/arch/arm/configs/kindle3_defconfig @@ -2,7 +2,6 @@ CONFIG_ARCH_IMX=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x30000 CONFIG_MACH_KINDLE3=y CONFIG_IMX_IIM=y -CONFIG_ARCH_IMX_USBLOADER=y CONFIG_AEABI=y CONFIG_ARM_BOARD_APPEND_ATAG=y CONFIG_ARM_BOARD_PREPEND_ATAG=y @@ -10,6 +9,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_PBL_IMAGE=y CONFIG_PBL_RELOCATABLE=y CONFIG_IMAGE_COMPRESSION_XZKERN=y +CONFIG_MMU=y CONFIG_MALLOC_SIZE=0x2000000 CONFIG_MALLOC_TLSF=y CONFIG_RELOCATABLE=y @@ -64,3 +64,4 @@ CONFIG_FS_EXT4=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y +CONFIG_ARCH_IMX_USBLOADER=y diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig new file mode 100644 index 0000000000..dadbcc214c --- /dev/null +++ b/arch/arm/configs/layerscape_defconfig @@ -0,0 +1,111 @@ +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_MACH_LS1046ARDB=y +CONFIG_MACH_TQMLS1046A=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_BOOTM_VERBOSE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BOOTM_OFTREE=y +CONFIG_BOOTM_OFTREE_UIMAGE=y +CONFIG_BLSPEC=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_PBL_CONSOLE=y +CONFIG_PARTITION_DISK_EFI=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_RESET_SOURCE=y +CONFIG_DEBUG_LL=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MMC_EXTCSD=y +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_MENUTREE=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LED=y +CONFIG_CMD_SPI=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_WD=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_NET_FSL_FMAN=y +CONFIG_DP83867_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_NET_DSA_MV88E6XXX=y +CONFIG_I2C=y +CONFIG_I2C_IMX=y +CONFIG_MCI=y +CONFIG_MCI_MMC_BOOT_PARTITIONS=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y +CONFIG_EEPROM_AT25=y +CONFIG_EEPROM_AT24=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_IMX=y +CONFIG_NVMEM=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/stm32mp1_defconfig b/arch/arm/configs/stm32mp1_defconfig new file mode 100644 index 0000000000..2922ce3632 --- /dev/null +++ b/arch/arm/configs/stm32mp1_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARCH_STM32MP1=y +CONFIG_MACH_STM32MP157C_DK2=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_ARM_BOARD_APPEND_ATAG=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_PSCI=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_BOOTM_VERBOSE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BOOTM_OFTREE=y +CONFIG_BOOTM_OFTREE_UIMAGE=y +CONFIG_BLSPEC=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_PBL_CONSOLE=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_POLLER=y +CONFIG_RESET_SOURCE=y +CONFIG_DEBUG_INITCALLS=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_ARM_MMUINFO=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_MENUTREE=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_STM32=y +CONFIG_DRIVER_NET_DESIGNWARE=y +CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y +CONFIG_AT803X_PHY=y +CONFIG_MICREL_PHY=y +# CONFIG_SPI is not set +# CONFIG_PINCTRL is not set +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_CRC8=y diff --git a/arch/arm/crypto/sha1_glue.c b/arch/arm/crypto/sha1_glue.c index cc032f6af2..6a0e482aaa 100644 --- a/arch/arm/crypto/sha1_glue.c +++ b/arch/arm/crypto/sha1_glue.c @@ -63,7 +63,7 @@ static int __sha1_update(struct sha1_state *sctx, const u8 *data, } -int sha1_update_arm(struct digest *desc, const void *data, +static int sha1_update_arm(struct digest *desc, const void *data, unsigned long len) { struct sha1_state *sctx = digest_ctx(desc); @@ -79,8 +79,6 @@ int sha1_update_arm(struct digest *desc, const void *data, res = __sha1_update(sctx, data, len, partial); return res; } -EXPORT_SYMBOL_GPL(sha1_update_arm); - /* Add padding and return the message digest. */ static int sha1_final(struct digest *desc, u8 *out) diff --git a/arch/arm/crypto/sha256_glue.c b/arch/arm/crypto/sha256_glue.c index d8a72a2cb9..2bb7122aab 100644 --- a/arch/arm/crypto/sha256_glue.c +++ b/arch/arm/crypto/sha256_glue.c @@ -26,7 +26,7 @@ void sha256_block_data_order(u32 *digest, const void *data, unsigned int num_blks); -int sha256_init(struct digest *desc) +static int sha256_init(struct digest *desc) { struct sha256_state *sctx = digest_ctx(desc); @@ -43,7 +43,7 @@ int sha256_init(struct digest *desc) return 0; } -int sha224_init(struct digest *desc) +static int sha224_init(struct digest *desc) { struct sha256_state *sctx = digest_ctx(desc); @@ -60,7 +60,7 @@ int sha224_init(struct digest *desc) return 0; } -int __sha256_update(struct digest *desc, const u8 *data, unsigned int len, +static int __sha256_update(struct digest *desc, const u8 *data, unsigned int len, unsigned int partial) { struct sha256_state *sctx = digest_ctx(desc); @@ -86,7 +86,7 @@ int __sha256_update(struct digest *desc, const u8 *data, unsigned int len, return 0; } -int sha256_update(struct digest *desc, const void *data, +static int sha256_update(struct digest *desc, const void *data, unsigned long len) { struct sha256_state *sctx = digest_ctx(desc); @@ -150,24 +150,6 @@ static int sha224_final(struct digest *desc, u8 *out) return 0; } -int sha256_export(struct digest *desc, void *out) -{ - struct sha256_state *sctx = digest_ctx(desc); - - memcpy(out, sctx, sizeof(*sctx)); - - return 0; -} - -int sha256_import(struct digest *desc, const void *in) -{ - struct sha256_state *sctx = digest_ctx(desc); - - memcpy(sctx, in, sizeof(*sctx)); - - return 0; -} - static struct digest_algo sha224 = { .base = { .name = "sha224", diff --git a/arch/arm/crypto/sha256_glue.h b/arch/arm/crypto/sha256_glue.h deleted file mode 100644 index 0312f4ffe8..0000000000 --- a/arch/arm/crypto/sha256_glue.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _CRYPTO_SHA256_GLUE_H -#define _CRYPTO_SHA256_GLUE_H - -#include <linux/crypto.h> -#include <crypto/sha.h> - -extern struct shash_alg sha256_neon_algs[2]; - -extern int sha256_init(struct shash_desc *desc); - -extern int sha224_init(struct shash_desc *desc); - -extern int __sha256_update(struct shash_desc *desc, const u8 *data, - unsigned int len, unsigned int partial); - -extern int sha256_update(struct shash_desc *desc, const u8 *data, - unsigned int len); - -extern int sha256_export(struct shash_desc *desc, void *out); - -extern int sha256_import(struct shash_desc *desc, const void *in); - -#endif /* _CRYPTO_SHA256_GLUE_H */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f989df6b0c..1c6129816d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -89,6 +89,7 @@ pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o \ imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \ imx6q-h100.dtb.o +pbl-dtb-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2.dtb.o pbl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o pbl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o pbl-dtb-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o @@ -123,7 +124,8 @@ pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \ vf610-zii-dev-rev-c.dtb.o \ vf610-zii-cfu1.dtb.o \ vf610-zii-ssmb-spu3.dtb.o \ - vf610-zii-scu4-aib-rev-c.dtb.o + vf610-zii-scu4-aib.dtb.o \ + vf610-zii-spb4.dtb.o pbl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o @@ -131,5 +133,7 @@ pbl-dtb-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o pbl-dtb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o +pbl-dtb-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o +pbl-dtb-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo diff --git a/arch/arm/dts/am335x-afi-gf.dts b/arch/arm/dts/am335x-afi-gf.dts index d0860b8905..961fe2e241 100644 --- a/arch/arm/dts/am335x-afi-gf.dts +++ b/arch/arm/dts/am335x-afi-gf.dts @@ -367,10 +367,6 @@ status = "okay"; }; -&phy_sel { - rmii-clock-ext; -}; - &am33xx_pinmux { dcan0_pins: pinmux_dcan0_pins { pinctrl-single,pins = < diff --git a/arch/arm/dts/am335x-baltos-minimal.dts b/arch/arm/dts/am335x-baltos-minimal.dts index f939cf6406..137c177b2f 100644 --- a/arch/arm/dts/am335x-baltos-minimal.dts +++ b/arch/arm/dts/am335x-baltos-minimal.dts @@ -423,10 +423,6 @@ dual_emac_res_vlan = <2>; }; -&phy_sel { - rmii-clock-ext = <1>; -}; - &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dtsi b/arch/arm/dts/am335x-phytec-phycard-som.dtsi index 2320ca1807..1d45d60dc0 100644 --- a/arch/arm/dts/am335x-phytec-phycard-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycard-som.dtsi @@ -128,10 +128,6 @@ }; }; -&phy_sel { - rmii-clock-ext; -}; - &cpsw_emac0 { phy-handle = <&phy0>; phy-mode = "rmii"; diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi index 0601f5ab7b..ae3f70acdd 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi @@ -250,10 +250,6 @@ }; }; -&phy_sel { - rmii-clock-ext; -}; - &cpsw_emac0 { phy-handle = <&phy0>; phy-mode = "rmii"; diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi index 4d0a913988..0325c81346 100644 --- a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi @@ -207,10 +207,6 @@ }; }; -&phy_sel { - rmii-clock-ext; -}; - &cpsw_emac0 { phy-handle = <&phy0>; phy-mode = "rgmii"; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts new file mode 100644 index 0000000000..e16948bc8a --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <arm64/freescale/fsl-ls1046a-rdb.dts> + +/ { + chosen { + stdout-path = &duart0; + + environment { + compatible = "barebox,environment"; + device-path = &environment_sd; + }; + }; + + aliases { + mmc0 = &esdhc; + }; +}; + +&esdhc { + #address-cells = <1>; + #size-cells = <1>; + + environment_sd: partition@200000 { + label = "barebox-environment"; + reg = <0x200000 0x20000>; + }; +}; + +&fman0 { + ethernet@e0000 { + status = "disabled"; + }; + + ethernet@e2000 { + status = "disabled"; + }; + + ethernet@e4000 { + phy-mode = "rgmii-id"; + }; + + ethernet@e6000 { + phy-mode = "rgmii-id"; + }; + + ethernet@e8000 { + }; + + ethernet@ea000 { + }; + + ethernet@f0000 { + }; + + ethernet@f2000 { + }; + + mdio@fc000 { + }; + + mdio@fd000 { + }; + + mdio@e1000 { + status = "disabled"; + }; + + mdio@e3000 { + status = "disabled"; + }; + + mdio@e5000 { + status = "disabled"; + }; + + mdio@e7000 { + status = "disabled"; + }; + + mdio@e9000 { + status = "disabled"; + }; + + mdio@eb000 { + status = "disabled"; + }; + + mdio@f1000 { + status = "disabled"; + }; + + mdio@f3000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts new file mode 100644 index 0000000000..f21479eef8 --- /dev/null +++ b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for TQMLS1046A SoM on MBLS10xxA from TQ + * + * Copyright 2018 TQ-Systems GmbH + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +#include "fsl-tqmls1046a.dtsi" + +/ { + model = "TQ TQMLS1046A SoM on MBLS10xxA board"; + compatible = "tqc,tqmls1046a", "fsl,ls1046a"; + + aliases { + serial0 = &duart0; + serial1 = &duart1; + mmc0 = &esdhc; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + gpio-keys,name = "gpio-keys"; + poll-interval = <100>; + autorepeat; + + button0 { + label = "button0"; + gpios = <&gpioexp3 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F1>; + }; + + button1 { + label = "button1"; + gpios = <&gpioexp3 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F2>; + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + gpios = <&gpioexp3 13 GPIO_ACTIVE_LOW>; + label = "led:user"; + linux,default-trigger = "heartbeat"; + }; + }; + +}; + + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9544"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + gpioexp1: pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioexp2: pca9555@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioexp3: pca9555@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + }; +}; + +&usb1 { + dr_mode = "otg"; +}; + +#include <arm64/freescale/fsl-ls1046-post.dtsi> +#include <dt-bindings/net/ti-dp83867.h> + +&fman0 { + status = "okay"; + + ethernet@e0000 { + status = "disabled"; + }; + + ethernet@e2000 { + phy-handle = <&qsgmii1_phy2>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + phy-mode = "rgmii-id"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + phy-mode = "rgmii-id"; + }; + + ethernet@e8000 { + status = "disabled"; + }; + + ethernet@ea000 { + phy-handle = <&qsgmii2_phy2>; + phy-connection-type = "sgmii"; + }; + + ethernet@f0000 { + phy-handle = <&qsgmii1_phy1>; + phy-connection-type = "sgmii"; + }; + + ethernet@f2000 { + phy-handle = <&qsgmii2_phy1>; + phy-connection-type = "sgmii"; + }; + + mdio@e1000 { + status = "disabled"; + }; + + mdio@e3000 { + status = "disabled"; + }; + + mdio@e5000 { + status = "disabled"; + }; + + mdio@e7000 { + status = "disabled"; + }; + + mdio@e9000 { + status = "disabled"; + }; + + mdio@eb000 { + status = "disabled"; + }; + + mdio@f1000 { + status = "disabled"; + }; + + mdio@f3000 { + status = "disabled"; + }; + + mdio@fc000 { + rgmii_phy1: ethernet-phy@0e { + reg = <0x0e>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + }; + + qsgmii1_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + qsgmii1_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + }; + + mdio@fd000 { + rgmii_phy2: ethernet-phy@0c { + reg = <0x0c>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + }; + + qsgmii2_phy1: ethernet-phy@00 { + reg = <0x00>; + }; + + qsgmii2_phy2: ethernet-phy@01 { + reg = <0x01>; + }; + }; +}; diff --git a/arch/arm/dts/fsl-tqmls1046a.dtsi b/arch/arm/dts/fsl-tqmls1046a.dtsi new file mode 100644 index 0000000000..4717e66857 --- /dev/null +++ b/arch/arm/dts/fsl-tqmls1046a.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for LS1046A based SoM of TQ + * + * Copyright 2018 TQ-Systems GmbH + */ + +#include <arm64/freescale/fsl-ls1046a.dtsi> + +&i2c0 { + status = "okay"; + + temp-sensor@18 { + compatible = "jc42"; + reg = <0x18>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + }; +}; + +&qspi { + num-cs = <2>; + bus-num = <0>; + status = "okay"; + + qflash0: mx66u51235f@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <108000000>; + reg = <0>; + }; + + qflash1: mx66u51235f@1 { + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <108000000>; + compatible = "jedec,spi-nor"; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index aba86a3ec1..f0bba2e098 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -86,23 +86,6 @@ }; }; -&fec { - phy-handle = <ðphy>; - phy-reset-duration = <10>; /* in msecs */ - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - reg = <3>; - - txc-skew-ps = <1680>; - rxc-skew-ps = <1860>; - }; - }; -}; - &gpmi { partitions { compatible = "fixed-partitions"; diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi index fea219f1e1..bfc75ba606 100644 --- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi @@ -49,6 +49,11 @@ }; }; + device-info { + nvmem-cells = <&lru_part_number>; + nvmem-cell-names = "lru-part-number"; + }; + aliases { ethernet0 = &fec; ethernet1 = &i210; @@ -59,8 +64,96 @@ */ switch-eeprom = &switch; }; -}; + panel { + compatible = "simple-panel"; + /* Timings for all supported panels, the correct one is enabled + * after the board data has been retrieved from the environment + * controller + */ + + display-timings { + innolux-g121i1-l01 { + compatible = "innolux,g121i1-l01"; + + hback-porch = <79>; + hfront-porch = <80>; + hactive = <1280>; + hsync-len = <1>; + vback-porch = <11>; + vfront-porch = <11>; + vactive = <800>; + vsync-len = <1>; + clock-frequency = <71000000>; + }; + nec-nl12880bc20-05 { + compatible = "nec,nl12880bc20-05"; + + hback-porch = <100>; + hfront-porch = <30>; + hactive = <1280>; + hsync-len = <30>; + vback-porch = <11>; + vfront-porch = <5>; + vactive = <800>; + vsync-len = <7>; + clock-frequency = <71000000>; + }; + auo-g133han01 { + compatible = "auo,g133han01"; + + hback-porch = <88>; + hfront-porch = <58>; + hactive = <1920>; + hsync-len = <42>; + vback-porch = <14>; + vfront-porch = <8>; + vactive = <1080>; + vsync-len = <14>; + clock-frequency = <141200000>; + }; + auo-g185han01 { + compatible = "auo,g185han01"; + + hback-porch = <44>; + hfront-porch = <60>; + hactive = <1920>; + hsync-len = <24>; + vback-porch = <5>; + vfront-porch = <10>; + vactive = <1080>; + vsync-len = <5>; + clock-frequency = <144000000>; + }; + nlt-nl192108ac18-02d { + compatible = "nlt,nl192108ac18-02d"; + + hback-porch = <120>; + hfront-porch = <100>; + hactive = <1920>; + hsync-len = <60>; + vback-porch = <10>; + vfront-porch = <30>; + vactive = <1080>; + vsync-len = <5>; + clock-frequency = <148350000>; + }; + auo-p320hvn03 { + compatible = "auo,p320hvn03"; + + hback-porch = <50>; + hfront-porch = <50>; + hactive = <1920>; + hsync-len = <40>; + vback-porch = <17>; + vfront-porch = <17>; + vactive = <1080>; + vsync-len = <11>; + clock-frequency = <148500000>; + }; + }; + }; +}; &uart4 { rave-sp { @@ -73,6 +166,11 @@ }; eeprom@a4 { + lru_part_number: lru-part-number@21 { + reg = <0x21 15>; + read-only; + }; + boot_source: boot-source@83 { reg = <0x83 1>; }; @@ -110,12 +208,38 @@ nvmem-cell-names = "mac-address"; }; +&i2c1 { + edp-bridge@68 { + pinctrl-0 = <&pinctrl_tc358767>, <&pinctrl_disp0>; + + ports { + port@1 { + reg = <1>; + + tc358767_in: endpoint { + remote-endpoint = <&disp0_out>; + }; + }; + }; + }; +}; + &i2c2 { temp-sense@48 { barebox,sensor-name = "Temp Sensor 1"; }; }; +&ipu1_di0_disp0 { + remote-endpoint = <&tc358767_in>; +}; + +&ldb { + lvds-channel@0 { + fsl,data-width = <24>; + }; +}; + &i210 { nvmem-cells = <&mac_address_1>; nvmem-cell-names = "mac-address"; diff --git a/arch/arm/dts/imx8mq-phytec-phycore-som.dts b/arch/arm/dts/imx8mq-phytec-phycore-som.dts index de8ed1873f..736c007f49 100644 --- a/arch/arm/dts/imx8mq-phytec-phycore-som.dts +++ b/arch/arm/dts/imx8mq-phytec-phycore-som.dts @@ -205,6 +205,13 @@ }; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < @@ -325,4 +332,10 @@ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; }; diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index d6a4c715bd..d1d8bdaa0e 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -16,7 +16,6 @@ gpio4 = &gpio5; mmc0 = &usdhc1; mmc1 = &usdhc2; - spi0 = &ecspi1; }; thermal-zones { @@ -113,136 +112,6 @@ reg = <0x30390000 0x10000>; #reset-cells = <1>; }; - - gpc: gpc@303a0000 { - compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc"; - reg = <0x303a0000 0x10000>; - #power-domain-cells = <1>; - - interrupt-controller; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - /* - * As per comment in ATF source code: - * - * PCIE1 and PCIE2 share the - * same reset signal, if we power - * down PCIE2, PCIE1 will be held - * in reset too. - * - * So instead of creating two - * separate power domains for - * PCIE1 and PCIE2. We create - * a link between 1 and 10 and - * use what was supposed to be - * domain 1 as a shared PCIE - * power domain powering both - * PCIE1 and PCIE2 at the same - * time - */ - pgc_pcie_phy: gpc_power_domain@1 { - #power-domain-cells = <0>; - reg = <1>; - power-domains = <&pgc_pcie2_phy>; - }; - - pgc_otg1: power-domain@2 { - #power-domain-cells = <0>; - reg = <2>; - }; - - pgc_otg2: power-domain@3 { - #power-domain-cells = <0>; - reg = <3>; - }; - - pgc_pcie2_phy: gpc_power_domain@10 { - #power-domain-cells = <0>; - reg = <10>; - }; - }; - }; - }; - - bus@30800000 { - ecspi1: ecspi@30820000 { - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, - <&clk IMX8MQ_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - - usb_dwc3_0: usb@38100000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38100000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb3_phy0>, <&usb3_phy0>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg1>; - status = "disabled"; - }; - - usb3_phy0: phy@381f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x381f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb_dwc3_1: usb@38200000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38200000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb3_phy1>, <&usb3_phy1>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg2>; - status = "disabled"; - }; - - usb3_phy1: phy@382f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x382f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; }; pcie0: pcie@33800000 { @@ -266,7 +135,7 @@ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie_phy>; + power-domains = <&pgc_pcie1>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; @@ -295,7 +164,7 @@ <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie_phy>; + power-domains = <&pgc_pcie1>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts new file mode 100644 index 0000000000..741284a444 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com>. + */ + +/dts-v1/; + +#include "stm32mp157c.dtsi" +#include <arm/stm32mp157c.dtsi> +#include <arm/stm32mp157-pinctrl.dtsi> + +/ { + model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; + compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sram: sram@10050000 { + compatible = "mmio-sram"; + reg = <0x10050000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10050000 0x10000>; + + dma_pool: dma_pool@0 { + reg = <0x0 0x10000>; + pool; + }; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts new file mode 100644 index 0000000000..7565cabc3d --- /dev/null +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com>. + */ + +/dts-v1/; + +#include "stm32mp157a-dk1.dts" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; + compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; +}; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi new file mode 100644 index 0000000000..fa0d00ff02 --- /dev/null +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -0,0 +1,7 @@ + +/ { + clocks { + /* Needed to let barebox find the clock nodes */ + compatible = "simple-bus"; + }; +}; diff --git a/arch/arm/dts/vf610-zii-scu4-aib-rev-c.dts b/arch/arm/dts/vf610-zii-scu4-aib-rev-c.dts deleted file mode 100644 index 12c2568bcc..0000000000 --- a/arch/arm/dts/vf610-zii-scu4-aib-rev-c.dts +++ /dev/null @@ -1,459 +0,0 @@ -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include <arm/vf610-zii-dev.dtsi> - -#include "vf610-zii-dev.dtsi" - -/ { - model = "ZII VF610 SCU4 AIB, Rev C"; - compatible = "zii,vf610scu4-aib-c", "zii,vf610dev", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP0,115200n8"; - }; - - gpio-leds { - debug { - gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - }; - }; - - mdio-mux { - compatible = "mdio-mux-gpio"; - pinctrl-0 = <&pinctrl_mdio_mux>; - pinctrl-names = "default"; - gpios = <&gpio4 4 GPIO_ACTIVE_HIGH - &gpio4 5 GPIO_ACTIVE_HIGH - &gpio3 30 GPIO_ACTIVE_HIGH - &gpio3 31 GPIO_ACTIVE_HIGH>; - mdio-parent-bus = <&mdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio_mux_1: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio_mux_2: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio_mux_4: mdio@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio_mux_8: mdio@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - spi2 { - compatible = "spi-gpio"; - pinctrl-0 = <&pinctrl_dspi2>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - gpio-sck = <&gpio2 3 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio2 2 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio2 1 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - at93c46d@0 { - compatible = "atmel,at93c46d"; - #address-cells = <0>; - #size-cells = <0>; - reg = <0>; - spi-max-frequency = <500000>; - spi-cs-high; - data-size = <16>; - select-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&dspi0 { - pinctrl-0 = <&pinctrl_dspi0>, <&pinctrl_dspi0_cs_4_5>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; - - m25p128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-0"; - reg = <0x0 0x01000000>; - }; - }; - - m25p128@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-1"; - reg = <0x0 0x01000000>; - }; - }; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - status = "okay"; -}; - -&fec0 { - status = "disabled"; -}; - -&i2c0 { - /* Reset Signals */ - gpio5: pca9505@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* Board Revision */ - gpio6: pca9505@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c1 { - /* Wireless 2 */ - gpio8: pca9554@18 { - compatible = "nxp,pca9557"; - reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* Wireless 1 */ - gpio7: pca9554@24 { - compatible = "nxp,pca9554"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* AIB voltage monitor */ - adt7411@4a { - compatible = "adi,adt7411"; - reg = <0x4a>; - }; -}; - -&i2c2 { - /* FIB voltage monitor */ - adt7411@4a { - compatible = "adi,adt7411"; - reg = <0x4a>; - }; - - lm75_swb { - compatible = "national,lm75"; - reg = <0x4e>; - }; - - lm75_swa { - compatible = "national,lm75"; - reg = <0x4f>; - }; - - /* FIB Nameplate */ - at24c08@57 { - compatible = "atmel,24c08"; - reg = <0x57>; - }; - - tca9548@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - sff0: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - sff1: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - sff2: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - sff3: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - sff4: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - }; - }; - - - tca9548@71 { - compatible = "nxp,pca9548"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - sff5: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - sff6: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - sff7: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - sff8: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - sff9: at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - }; - }; -}; - -&uart1 { - linux,rs485-enabled-at-boot-time; - pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_rts>; -}; - -&uart2 { - linux,rs485-enabled-at-boot-time; - pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart2_rts>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpo_public>; - - - pinctrl_gpo_public: gpopubgrp { - fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x2062 - VF610_PAD_PTE3__GPIO_108 0x2062 - VF610_PAD_PTE4__GPIO_109 0x2062 - VF610_PAD_PTE5__GPIO_110 0x2062 - VF610_PAD_PTE6__GPIO_111 0x2062 - >; - }; - - pinctrl_dspi0_cs_4_5: dspi0grp-cs-4-5 { - fsl,pins = < - VF610_PAD_PTB13__DSPI0_CS4 0x1182 - VF610_PAD_PTB12__DSPI0_CS5 0x1182 - >; - }; - - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - VF610_PAD_PTA30__I2C3_SCL 0x37ff - VF610_PAD_PTA31__I2C3_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTB26__GPIO_96 0x31c2 - >; - }; - - pinctrl_uart1_rts: uart1grp-rts { - fsl,pins = < - VF610_PAD_PTB25__UART1_RTS 0x2062 - >; - }; - - pinctrl_uart2_rts: uart2grp-rts { - fsl,pins = < - VF610_PAD_PTD2__UART2_RTS 0x2062 - >; - }; - - pinctrl_mdio_mux: pinctrl-mdio-mux { - fsl,pins = < - VF610_PAD_PTE27__GPIO_132 0x31c2 - VF610_PAD_PTE28__GPIO_133 0x31c2 - VF610_PAD_PTE21__GPIO_126 0x31c2 - VF610_PAD_PTE22__GPIO_127 0x31c2 - >; - }; -}; diff --git a/arch/arm/dts/vf610-zii-scu4-aib.dts b/arch/arm/dts/vf610-zii-scu4-aib.dts new file mode 100644 index 0000000000..abe9e14fd7 --- /dev/null +++ b/arch/arm/dts/vf610-zii-scu4-aib.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright (C) 2016-2018 Zodiac Inflight Innovations + +#include <arm/vf610-zii-scu4-aib.dts> + +#include "vf610-zii-dev.dtsi" + +/ { + aliases { + /* + * NVMEM device corresponding to EEPROM attached to + * the switch shares DT node with it, so we use that + * fact to create a desirable naming + */ + switch0-eeprom = &switch0; + switch1-eeprom = &switch1; + switch2-eeprom = &switch2; + switch3-eeprom = &switch3; + }; +}; diff --git a/arch/arm/dts/vf610-zii-spb4.dts b/arch/arm/dts/vf610-zii-spb4.dts new file mode 100644 index 0000000000..e7d35d0e69 --- /dev/null +++ b/arch/arm/dts/vf610-zii-spb4.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "vf610-zii-spb4.dtsi" + +#include "vf610-zii-dev.dtsi" + +/ { + aliases { + /* + * NVMEM device corresponding to EEPROM attached to + * the switch shared DT node with it, so we use that + * fact to create a desirable naming + */ + switch-eeprom = &switch0; + }; +}; diff --git a/arch/arm/dts/vf610-zii-spb4.dtsi b/arch/arm/dts/vf610-zii-spb4.dtsi new file mode 100644 index 0000000000..f618ca45ee --- /dev/null +++ b/arch/arm/dts/vf610-zii-spb4.dtsi @@ -0,0 +1,365 @@ +/* + * This is a copy of DTS file from Linux. Remove it once the same file + * is availible via dts/src/arm + */ + +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SPB4 board + * + * SPB - Seat Power Box + * + * Copyright (C) 2019 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include <arm/vf610.dtsi> + +/ { + model = "ZII VF610 SPB4 Board"; + compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + max-brightness = <1>; + }; + }; + + reg_vcc_3v3_mcu: regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-sdio; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + eeprom-length = <65536>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_1"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_3"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_4"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_5"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_6"; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio6: pca9505@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + at24c04@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&snvsrtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&wdoga5 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTE2__GPIO_107 0x31c2 + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + VF610_PAD_PTA30__UART3_TX 0x21a2 + VF610_PAD_PTA31__UART3_RX 0x21a1 + >; + }; +}; diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h index 4d0da6c491..5c6205c815 100644 --- a/arch/arm/include/asm/barebox-arm-head.h +++ b/arch/arm/include/asm/barebox-arm-head.h @@ -7,6 +7,7 @@ void arm_cpu_lowlevel_init(void); void cortex_a7_lowlevel_init(void); +void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2); /* * 32 bytes at this offset is reserved in the barebox head for board/SoC diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 45eeb6e62c..ef9cb98bf0 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -126,6 +126,30 @@ static inline unsigned long get_cntpct(void) return cntpct; } +#else +static inline void set_cntfrq(unsigned long cntfrq) +{ + asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (cntfrq)); +} + +static inline unsigned int get_cntfrq(void) +{ + unsigned int val; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); + + return val; +} + +static inline unsigned long long get_cntpct(void) +{ + unsigned long long cval; + + isb(); + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); + + return cval; +} #endif static inline unsigned int get_cr(void) diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S index 53c9ce0fe6..300671bb51 100644 --- a/arch/arm/lib/pbl.lds.S +++ b/arch/arm/lib/pbl.lds.S @@ -80,12 +80,16 @@ SECTIONS .dynsym : { *(.dynsym) } .__dynsym_end : { *(.__dynsym_end) } + pbl_code_size = . - BASE; + . = ALIGN(4); .__bss_start : { *(.__bss_start) } .bss : { *(.bss*) } .__bss_stop : { *(.__bss_stop) } _end = .; + pbl_memory_size = . - BASE; + . = ALIGN(4); __piggydata_start = .; .piggydata : { @@ -95,6 +99,8 @@ SECTIONS .image_end : { *(.__image_end) } + pbl_image_size = . - BASE; + _barebox_image_size = __image_end - BASE; _barebox_pbl_size = __bss_start - BASE; } diff --git a/arch/arm/lib32/semihosting.c b/arch/arm/lib32/semihosting.c index a7351961dc..9fc3b6b62c 100644 --- a/arch/arm/lib32/semihosting.c +++ b/arch/arm/lib32/semihosting.c @@ -21,6 +21,7 @@ #include <common.h> #include <command.h> #include <fcntl.h> +#include <asm/semihosting.h> #ifndef O_BINARY #define O_BINARY 0 @@ -153,7 +154,7 @@ int semihosting_isatty(int fd) } EXPORT_SYMBOL(semihosting_isatty); -int semihosting_seek(int fd, off_t pos) +int semihosting_seek(int fd, loff_t pos) { struct __packed { uint32_t fd; diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile index 4c0019fabe..5068431342 100644 --- a/arch/arm/lib64/Makefile +++ b/arch/arm/lib64/Makefile @@ -6,4 +6,4 @@ obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o string.o extra-y += barebox.lds obj-pbl-y += runtime-offset.o -pbl-y += div0.o +pbl-y += div0.o pbl.o diff --git a/arch/arm/lib64/pbl.c b/arch/arm/lib64/pbl.c new file mode 100644 index 0000000000..0cef08e4d2 --- /dev/null +++ b/arch/arm/lib64/pbl.c @@ -0,0 +1,17 @@ +#include <asm/system.h> +#include <clock.h> +#include <common.h> + +void udelay(unsigned long us) +{ + unsigned long cntfrq = get_cntfrq(); + unsigned long ticks = (us * cntfrq) / 1000000; + unsigned long start = get_cntpct(); + + while ((long)(start + ticks - get_cntpct()) > 0); +} + +void mdelay(unsigned long ms) +{ + udelay(ms * 1000); +} diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index e4f6cb6751..6db961b807 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -166,6 +166,7 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_BOARD_REV_ZERO_W 0x0c #define BCM2837B0_BOARD_REV_3B_PLUS 0x0d #define BCM2837B0_BOARD_REV_3A_PLUS 0x0e +#define BCM2837B0_BOARD_REV_CM3_PLUS 0x10 struct bcm2835_mbox_tag_get_board_rev { struct bcm2835_mbox_tag_hdr tag_hdr; diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c index 4d6403b92e..2c5137c582 100644 --- a/arch/arm/mach-clps711x/clock.c +++ b/arch/arm/mach-clps711x/clock.c @@ -71,9 +71,9 @@ static __init int clps711x_clk_init(void) clks[CLPS711X_CLK_BUS] = clk_fixed("bus", f_bus); clks[CLPS711X_CLK_UART] = clk_fixed("uart", f_uart); clks[CLPS711X_CLK_TIMERREF] = clk_fixed("timer_ref", f_timer_ref); - clks[CLPS711X_CLK_TIMER1] = clk_divider_table("timer1", "timer_ref", + clks[CLPS711X_CLK_TIMER1] = clk_divider_table("timer1", "timer_ref", 0, IOMEM(SYSCON1), 5, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl)); - clks[CLPS711X_CLK_TIMER2] = clk_divider_table("timer2", "timer_ref", + clks[CLPS711X_CLK_TIMER2] = clk_divider_table("timer2", "timer_ref", 0, IOMEM(SYSCON1), 7, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl)); clkdev_add_physbase(clks[CLPS711X_CLK_UART], UARTDR1, NULL); diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c index 69574317bd..8eacc70018 100644 --- a/arch/arm/mach-clps711x/devices.c +++ b/arch/arm/mach-clps711x/devices.c @@ -15,6 +15,7 @@ #include <asm/memory.h> #include <mach/clps711x.h> +#include <mach/devices.h> static int clps711x_mem_init(void) { diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index 0c87152032..20477f83e6 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c @@ -18,6 +18,7 @@ #include <errno.h> #include <init.h> #include <io.h> +#include <gpio.h> #include <mach/ep93xx-regs.h> #define EP93XX_GPIO_NUM_PORTS 8 diff --git a/arch/arm/mach-ep93xx/led.c b/arch/arm/mach-ep93xx/led.c index a415bce0d7..47e24cd6ed 100644 --- a/arch/arm/mach-ep93xx/led.c +++ b/arch/arm/mach-ep93xx/led.c @@ -20,6 +20,8 @@ #include <io.h> #include <mach/ep93xx-regs.h> +#include "led.h" + #define GREEN_LED_POS 0x01 #define RED_LED_POS 0x02 diff --git a/arch/arm/mach-highbank/reset.c b/arch/arm/mach-highbank/reset.c index b60f34452e..d73a0a76a5 100644 --- a/arch/arm/mach-highbank/reset.c +++ b/arch/arm/mach-highbank/reset.c @@ -21,7 +21,7 @@ static void __noreturn highbank_restart_soc(struct restart_handler *rst) hang(); } -void __noreturn highbank_poweroff(struct poweroff_handler *handler) +static void __noreturn highbank_poweroff(struct poweroff_handler *handler) { shutdown_barebox(); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index f3f3a49339..c4e7500e8f 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -431,16 +431,21 @@ config MACH_VF610_TWR bool "Freescale VF610 Tower Board" select ARCH_VF610 +config MACH_ZII_COMMON + bool + config MACH_ZII_RDU1 bool "ZII i.MX51 RDU1" select ARCH_IMX51 select MACH_FREESCALE_MX51_PDK_POWER select CRC8 + select MACH_ZII_COMMON config MACH_ZII_RDU2 bool "ZII i.MX6Q(+) RDU2" select ARCH_IMX6 select MCI_IMX_ESDHC_PBL + select MACH_ZII_COMMON config MACH_ZII_IMX8MQ_DEV bool "ZII i.MX8MQ based devices" diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index f0d009dfd2..aa6e050e94 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -12,10 +12,24 @@ * GNU General Public License for more details. */ +#include <common.h> #include <asm/barebox-arm-head.h> #include <asm/errata.h> #include <linux/types.h> +#include <linux/bitops.h> #include <mach/generic.h> +#include <mach/imx7-regs.h> +#include <mach/imx8mq-regs.h> +#include <common.h> +#include <io.h> +#include <asm/syscounter.h> +#include <asm/system.h> + +static inline void imx_cpu_timer_init(void __iomem *syscnt) +{ + set_cntfrq(syscnt_get_cntfrq(syscnt)); + syscnt_enable(syscnt); +} #ifdef CONFIG_CPU_32 void imx5_cpu_lowlevel_init(void) @@ -47,10 +61,19 @@ void imx6ul_cpu_lowlevel_init(void) void imx7_cpu_lowlevel_init(void) { arm_cpu_lowlevel_init(); + imx_cpu_timer_init(IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR)); } void vf610_cpu_lowlevel_init(void) { arm_cpu_lowlevel_init(); } +#else +void imx8mq_cpu_lowlevel_init(void) +{ + arm_cpu_lowlevel_init(); + + if (current_el() == 3) + imx_cpu_timer_init(IOMEM(MX8MQ_SYSCNT_CTRL_BASE_ADDR)); +} #endif diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index 745a129b23..c4d61aa786 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -134,8 +134,8 @@ static noinline void __bare_init imx_nandboot_get_page(void *regs, int v1, imx_nandboot_send_page(regs, v1, NFC_OUTPUT, pagesize_2k); } -void __bare_init imx_nand_load_image(void *dest, int v1, int size, void __iomem *base, - int pagesize_2k) +static void __bare_init imx_nand_load_image(void *dest, int v1, int size, + void __iomem *base, int pagesize_2k) { u32 tmp, page, block, blocksize, pagesize, badblocks; int bbt = 0; @@ -239,44 +239,30 @@ void __bare_init imx_nand_load_image(void *dest, int v1, int size, void __iomem } } -void BARE_INIT_FUNCTION(imx21_nand_load_image)(void *dest, int size, - void __iomem *base, int pagesize_2k) -{ - imx_nand_load_image(dest, 1, size, base, pagesize_2k); -} - -void BARE_INIT_FUNCTION(imx25_nand_load_image)(void *dest, int size, +static void BARE_INIT_FUNCTION(imx25_nand_load_image)(void *dest, int size, void __iomem *base, int pagesize_2k) { imx_nand_load_image(dest, 0, size, base, pagesize_2k); } -void BARE_INIT_FUNCTION(imx27_nand_load_image)(void *dest, int size, +static void BARE_INIT_FUNCTION(imx27_nand_load_image)(void *dest, int size, void __iomem *base, int pagesize_2k) { imx_nand_load_image(dest, 1, size, base, pagesize_2k); } -void BARE_INIT_FUNCTION(imx31_nand_load_image)(void *dest, int size, +static void BARE_INIT_FUNCTION(imx31_nand_load_image)(void *dest, int size, void __iomem *base, int pagesize_2k) { imx_nand_load_image(dest, 1, size, base, pagesize_2k); } -void BARE_INIT_FUNCTION(imx35_nand_load_image)(void *dest, int size, +static void BARE_INIT_FUNCTION(imx35_nand_load_image)(void *dest, int size, void __iomem *base, int pagesize_2k) { imx_nand_load_image(dest, 0, size, base, pagesize_2k); } -static inline int imx21_pagesize_2k(void) -{ - if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) - return 1; - else - return 0; -} - static inline int imx25_pagesize_2k(void) { if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8)) @@ -318,7 +304,7 @@ static inline int imx35_pagesize_2k(void) #define DEFINE_EXTERNAL_NAND_ENTRY(soc) \ \ -void __noreturn BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont) \ +static void __noreturn BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont) \ (void *boarddata) \ { \ unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ @@ -389,9 +375,6 @@ void __noreturn BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external) \ fn((void *)boarddata); \ } -#ifdef BROKEN -DEFINE_EXTERNAL_NAND_ENTRY(21) -#endif DEFINE_EXTERNAL_NAND_ENTRY(25) DEFINE_EXTERNAL_NAND_ENTRY(27) DEFINE_EXTERNAL_NAND_ENTRY(31) diff --git a/arch/arm/mach-imx/imx-bbu-external-nand.c b/arch/arm/mach-imx/imx-bbu-external-nand.c index 52622ac4cb..fa43d2e8dc 100644 --- a/arch/arm/mach-imx/imx-bbu-external-nand.c +++ b/arch/arm/mach-imx/imx-bbu-external-nand.c @@ -40,7 +40,7 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ int size_available, size_need; int ret; uint32_t num_bb = 0, bbt = 0; - uint64_t offset = 0; + loff_t offset = 0; int block = 0, len, now, blocksize; void *image = data->image; @@ -147,10 +147,12 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ goto out; if (ret) { - ret = lseek(fd, offset + blocksize, SEEK_SET); - if (ret < 0) - goto out; offset += blocksize; + if (lseek(fd, offset, SEEK_SET) != offset) { + ret = -errno; + goto out; + } + continue; } diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index 188369fe34..a563b3bc29 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -207,7 +207,7 @@ static int imx_bbu_internal_v2_write_nand_dbbt(struct imx_internal_bbu_handler * int size_available, size_need; int ret; uint32_t *ptr, *num_bb, *bb; - uint64_t offset; + loff_t offset; int block = 0, len, now, blocksize; int dbbt_start_page = 4; int firmware_start_page = 12; @@ -330,10 +330,12 @@ static int imx_bbu_internal_v2_write_nand_dbbt(struct imx_internal_bbu_handler * goto out; if (ret) { - ret = lseek(fd, offset + blocksize, SEEK_SET); - if (ret < 0) - goto out; offset += blocksize; + if (lseek(fd, offset, SEEK_SET) != offset) { + ret = -errno; + goto out; + } + continue; } diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c index ff2a828c7d..d875bf44f1 100644 --- a/arch/arm/mach-imx/imx7.c +++ b/arch/arm/mach-imx/imx7.c @@ -57,39 +57,6 @@ void imx7_init_lowlevel(void) writel(0, aips3 + 0x50); } -#define SC_CNTCR 0x0 -#define SC_CNTSR 0x4 -#define SC_CNTCV1 0x8 -#define SC_CNTCV2 0xc -#define SC_CNTFID0 0x20 -#define SC_CNTFID1 0x24 -#define SC_CNTFID2 0x28 -#define SC_counterid 0xfcc - -#define SC_CNTCR_ENABLE (1 << 0) -#define SC_CNTCR_HDBG (1 << 1) -#define SC_CNTCR_FREQ0 (1 << 8) -#define SC_CNTCR_FREQ1 (1 << 9) - -static int imx7_timer_init(void) -{ - void __iomem *sctr = IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR); - unsigned long val, freq; - - freq = 8000000; - asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); - - writel(freq, sctr + SC_CNTFID0); - - /* Enable system counter */ - val = readl(sctr + SC_CNTCR); - val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); - val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; - writel(val, sctr + SC_CNTCR); - - return 0; -} - #define CSU_NUM_REGS 64 #define CSU_INIT_SEC_LEVEL0 0x00FF00FF @@ -186,8 +153,6 @@ int imx7_init(void) imx7_init_csu(); - imx7_timer_init(); - imx7_boot_save_loc(); psci_set_ops(&imx7_psci_ops); diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c index 3f6b433a57..089344528d 100644 --- a/arch/arm/mach-imx/imx8mq.c +++ b/arch/arm/mach-imx/imx8mq.c @@ -27,28 +27,6 @@ #define FSL_SIP_BUILDINFO 0xC2000003 #define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 -static int imx8mq_init_syscnt_frequency(void) -{ - if (!cpu_is_mx8mq()) - return 0; - - if (current_el() == 3) { - void __iomem *syscnt = IOMEM(MX8MQ_SYSCNT_CTRL_BASE_ADDR); - /* - * Update with accurate clock frequency - */ - set_cntfrq(syscnt_get_cntfrq(syscnt)); - syscnt_enable(syscnt); - } - - return 0; -} -/* - * This call needs to happen before timer driver gets probed and - * requests its update frequency via cntfrq_el0 - */ -core_initcall(imx8mq_init_syscnt_frequency); - int imx8mq_init(void) { void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR); diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index be58da4da2..ac066e3f17 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -58,6 +58,7 @@ void imx6_cpu_lowlevel_init(void); void imx6ul_cpu_lowlevel_init(void); void imx7_cpu_lowlevel_init(void); void vf610_cpu_lowlevel_init(void); +void imx8mq_cpu_lowlevel_init(void); /* There's a off-by-one betweem the gpio bank number and the gpiochip */ /* range e.g. GPIO_1_5 is gpio 5 under linux */ diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig new file mode 100644 index 0000000000..3a44f3fea1 --- /dev/null +++ b/arch/arm/mach-layerscape/Kconfig @@ -0,0 +1,21 @@ +if ARCH_LAYERSCAPE + +config ARCH_LS1046 + select CPU_V8 + select SYS_SUPPORTS_64BIT_KERNEL + bool + +config MACH_LS1046ARDB + bool "QorIQ LS1046A Reference Design Board" + select ARCH_LS1046 + select DDR_SPD + select MCI_IMX_ESDHC_PBL + select I2C_IMX_EARLY + select DDR_FSL + select DDR_FSL_DDR4 + +config MACH_TQMLS1046A + bool "TQ TQMLS1046A Board" + select ARCH_LS1046 + +endif diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile new file mode 100644 index 0000000000..269839254b --- /dev/null +++ b/arch/arm/mach-layerscape/Makefile @@ -0,0 +1,4 @@ +obj- := __dummy__.o +lwl-y += lowlevel.o errata.o +lwl-$(CONFIG_ARCH_LS1046) += lowlevel-ls1046a.o +obj-y += icid.o diff --git a/arch/arm/mach-layerscape/errata.c b/arch/arm/mach-layerscape/errata.c new file mode 100644 index 0000000000..4f4b759ddb --- /dev/null +++ b/arch/arm/mach-layerscape/errata.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <io.h> +#include <soc/fsl/immap_lsch2.h> +#include <soc/fsl/fsl_ddr_sdram.h> +#include <asm/system.h> +#include <mach/errata.h> +#include <mach/lowlevel.h> + +#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set) +#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear) + +static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) +{ + scfg_clrsetbits32(scfg + offset / 4, + 0x7f << 9, + SCFG_USB_PCSTXSWINGFULL << 9); +} + +static void erratum_a008997_ls1046a(void) +{ + u32 __iomem *scfg = (u32 __iomem *)LSCH2_SCFG_ADDR; + + set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1); + set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); + set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); +} + +#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ + out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ + out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ + out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ + out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) + +static void erratum_a009007_ls1046a(void) +{ + void __iomem *usb_phy = IOMEM(SCFG_USB_PHY1); + + PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); + usb_phy = (void __iomem *)SCFG_USB_PHY2; + PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); + + usb_phy = (void __iomem *)SCFG_USB_PHY3; + PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); +} + +static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) +{ + scfg_clrsetbits32(scfg + offset / 4, 0xf << 6, SCFG_USB_TXVREFTUNE << 6); +} + +static void erratum_a009008_ls1046a(void) +{ + u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR); + + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); + set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); +} + +static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset) +{ + scfg_clrbits32(scfg + offset / 4, SCFG_USB_SQRXTUNE_MASK << 23); +} + +static void erratum_a009798_ls1046a(void) +{ + u32 __iomem *scfg = IOMEM(LSCH2_SCFG_ADDR); + + set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1); + set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2); + set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3); +} + +static void erratum_a008850_early(void) +{ + /* part 1 of 2 */ + struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR); + struct ccsr_ddr __iomem *ddr = IOMEM(LSCH2_DDR_ADDR); + + /* Skip if running at lower exception level */ + if (current_el() < 3) + return; + + /* disables propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + /* disable the re-ordering in DDRC */ + ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); +} + +/* erratum_a009942_check_cpo */ + +void ls1046a_errata(void) +{ + erratum_a008850_early(); + erratum_a009008_ls1046a(); + erratum_a009798_ls1046a(); + erratum_a008997_ls1046a(); + erratum_a009007_ls1046a(); +} + +static void erratum_a008850_post(void) +{ + /* part 2 of 2 */ + struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR); + struct ccsr_ddr __iomem *ddr = IOMEM(LSCH2_DDR_ADDR); + u32 tmp; + + /* Skip if running at lower exception level */ + if (current_el() < 3) + return; + + /* enable propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + /* enable the re-ordering in DDRC */ + tmp = ddr_in32(&ddr->eor); + tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); + ddr_out32(&ddr->eor, tmp); +} + +/* + * This additional workaround of A009942 checks the condition to determine if + * the CPO value set by the existing A009942 workaround needs to be updated. + * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with + * expected optimal value, the optimal value is highly board dependent. + */ +static void erratum_a009942_check_cpo(void) +{ + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(LSCH2_DDR_ADDR); + u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal; + u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; + u32 cpo_max = cpo_min; + u32 sdram_cfg, i, tmp, lanes, ddr_type; + bool update_cpo = false, has_ecc = false; + + sdram_cfg = ddr_in32(&ddr->sdram_cfg); + if (sdram_cfg & SDRAM_CFG_32_BE) + lanes = 4; + else if (sdram_cfg & SDRAM_CFG_16_BE) + lanes = 2; + else + lanes = 8; + + if (sdram_cfg & SDRAM_CFG_ECC_EN) + has_ecc = true; + + /* determine the maximum and minimum CPO values */ + for (i = 9; i < 9 + lanes / 2; i++) { + cpo = ddr_in32(&ddr->debug[i]); + cpo_e = cpo >> 24; + cpo_o = (cpo >> 8) & 0xff; + tmp = min(cpo_e, cpo_o); + if (tmp < cpo_min) + cpo_min = tmp; + tmp = max(cpo_e, cpo_o); + if (tmp > cpo_max) + cpo_max = tmp; + } + + if (has_ecc) { + cpo = ddr_in32(&ddr->debug[13]); + cpo = cpo >> 24; + if (cpo < cpo_min) + cpo_min = cpo; + if (cpo > cpo_max) + cpo_max = cpo; + } + + cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; + cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27; + debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal, + cpo_target); + debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min); + + ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> + SDRAM_CFG_SDRAM_TYPE_SHIFT; + if (ddr_type == SDRAM_TYPE_DDR4) + update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false; + else if (ddr_type == SDRAM_TYPE_DDR3) + update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false; + + if (update_cpo) { + printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal); + printf("in <board>/ddr.c to optimize cpo\n"); + } +} + +void ls1046a_errata_post_ddr(void) +{ + erratum_a008850_post(); + erratum_a009942_check_cpo(); +} diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c new file mode 100644 index 0000000000..2326d7e67a --- /dev/null +++ b/arch/arm/mach-layerscape/icid.c @@ -0,0 +1,243 @@ +#include <common.h> +#include <io.h> +#include <init.h> +#include <soc/fsl/immap_lsch2.h> +#include <soc/fsl/fsl_qbman.h> +#include <soc/fsl/fsl_fman.h> + +/* + * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices + * are not hardwired and are programmed by sw. There are a limited number + * of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, PCI, + * and DPAA1 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * -set a iommu-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt + * for more info on the iommu-map definition) + * + * -DPAA1 + * - Stream ids for DPAA1 use are reserved for future usecase. + * + */ + + +#define FSL_INVALID_STREAM_ID 0 + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9 +#define FSL_DEBUG_STREAM_ID 10 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 11 +#define FSL_PEX_STREAM_ID_END 26 + +/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END 63 + +struct icid_id_table { + const char *compat; + u32 id; + u32 reg; + phys_addr_t compat_addr; + phys_addr_t reg_addr; +}; + +struct fman_icid_id_table { + u32 port_id; + u32 icid; +}; + +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \ + { \ + .compat = name, \ + .id = idA, \ + .reg = regA, \ + .compat_addr = compataddr, \ + .reg_addr = addr, \ + } + +#define SET_SCFG_ICID(compat, streamid, name, compataddr) \ + SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ + offsetof(struct ccsr_scfg, name) + LSCH2_SCFG_ADDR, \ + compataddr) + +#define SET_USB_ICID(usb_num, compat, streamid) \ + SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ + LSCH2_XHCI_USB##usb_num##_ADDR) + +#define SET_SATA_ICID(compat, streamid) \ + SET_SCFG_ICID(compat, streamid, sata_icid,\ + LSCH2_HCI_BASE_ADDR) + +#define SET_SDHC_ICID(streamid) \ + SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\ + LSCH2_ESDHC_ADDR) + +#define QMAN_CQSIDR_REG 0x20a80 + +#define SET_QDMA_ICID(compat, streamid) \ + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ + LSCH2_QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ + LSCH2_QDMA_BASE_ADDR), \ + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ + LSCH2_QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ + LSCH2_QDMA_BASE_ADDR) + +#define SET_EDMA_ICID(streamid) \ + SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ + LSCH2_EDMA_BASE_ADDR) + +#define SET_ETR_ICID(streamid) \ + SET_SCFG_ICID(NULL, streamid, etr_icid, 0) + +#define SET_DEBUG_ICID(streamid) \ + SET_SCFG_ICID(NULL, streamid, debug_icid, 0) + +#define SET_QE_ICID(streamid) \ + SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\ + LSCH2_QE_BASE_ADDR) + +#define SET_QMAN_ICID(streamid) \ + SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ + offsetof(struct ccsr_qman, liodnr) + \ + LSCH2_QMAN_ADDR, \ + LSCH2_QMAN_ADDR) + +#define SET_BMAN_ICID(streamid) \ + SET_ICID_ENTRY("fsl,bman", streamid, streamid, \ + offsetof(struct ccsr_bman, liodnr) + \ + LSCH2_BMAN_ADDR, \ + LSCH2_BMAN_ADDR) + +#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ + { .port_id = (_port_id), .icid = (streamid) } + +#define SET_SEC_QI_ICID(streamid) \ + SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \ + 0, offsetof(ccsr_sec_t, qilcr_ls) + \ + LSCH2_SEC_ADDR, \ + LSCH2_SEC_ADDR) + +#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ + SET_ICID_ENTRY( \ + (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ + (FSL_SEC_JR##jr_num##_OFFSET == \ + SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ + ? NULL \ + : "fsl,sec-v4.0-job-ring"), \ + streamid, \ + (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \ + LSCH2_SEC_ADDR, \ + FSL_SEC_JR##jr_num##_BASE_ADDR) + +#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \ + LSCH2_SEC_ADDR, 0) + +#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ + LSCH2_SEC_ADDR, 0) + +static struct icid_id_table icid_tbl_ls1046a[] = { + SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START), + SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1), + + SET_SDHC_ICID(FSL_SDHC_STREAM_ID), + + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID), + + SET_SATA_ICID("fsl,ls1046a-ahci", FSL_SATA_STREAM_ID), + SET_QDMA_ICID("fsl,ls1046a-qdma", FSL_QDMA_STREAM_ID), + SET_EDMA_ICID(FSL_EDMA_STREAM_ID), + SET_ETR_ICID(FSL_ETR_STREAM_ID), + SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID), +}; + +static struct fman_icid_id_table fman_icid_tbl_ls1046a[] = { + /* port id, icid */ + SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END), +}; + +static void set_icid(struct icid_id_table *tbl, int size) +{ + int i; + + for (i = 0; i < size; i++) + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); +} + +static void set_fman_icids(struct fman_icid_id_table *tbl, int size) +{ + int i; + struct ccsr_fman *fm = (void *)LSCH2_FM1_ADDR; + + for (i = 0; i < size; i++) { + out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1], + tbl[i].icid); + } +} + +static int set_icids(void) +{ + if (!of_machine_is_compatible("fsl,ls1046a")) + return 0; + + /* setup general icid offsets */ + set_icid(icid_tbl_ls1046a, ARRAY_SIZE(icid_tbl_ls1046a)); + + set_fman_icids(fman_icid_tbl_ls1046a, ARRAY_SIZE(fman_icid_tbl_ls1046a)); + + return 0; +} +postcore_initcall(set_icids);
\ No newline at end of file diff --git a/arch/arm/mach-layerscape/include/mach/debug_ll.h b/arch/arm/mach-layerscape/include/mach/debug_ll.h new file mode 100644 index 0000000000..2658a4a7c9 --- /dev/null +++ b/arch/arm/mach-layerscape/include/mach/debug_ll.h @@ -0,0 +1,34 @@ +#ifndef __INCLUDE_ARCH_DEBUG_LL_H__ +#define __INCLUDE_ARCH_DEBUG_LL_H__ + +#include <io.h> +#include <soc/fsl/immap_lsch2.h> + +#define __LS_UART_BASE(num) LSCH2_NS16550_COM##num +#define LS_UART_BASE(num) __LS_UART_BASE(num) + +static inline uint8_t debug_ll_read_reg(int reg) +{ + void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT)); + + return readb(base + reg); +} + +static inline void debug_ll_write_reg(int reg, uint8_t val) +{ + void __iomem *base = IOMEM(LS_UART_BASE(CONFIG_DEBUG_LAYERSCAPE_UART_PORT)); + + writeb(val, base + reg); +} + +#include <debug_ll/ns16550.h> + +static inline void debug_ll_init(void) +{ + uint16_t divisor; + + divisor = debug_ll_ns16550_calc_divisor(300000000); + debug_ll_ns16550_init(divisor); +} + +#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */ diff --git a/arch/arm/mach-layerscape/include/mach/errata.h b/arch/arm/mach-layerscape/include/mach/errata.h new file mode 100644 index 0000000000..bdefa22172 --- /dev/null +++ b/arch/arm/mach-layerscape/include/mach/errata.h @@ -0,0 +1,7 @@ +#ifndef __MACH_ERRATA_H +#define __MACH_ERRATA_H + +void ls1046a_errata(void); +void ls1046a_errata_post_ddr(void); + +#endif /* __MACH_ERRATA_H */ diff --git a/arch/arm/mach-layerscape/include/mach/layerscape.h b/arch/arm/mach-layerscape/include/mach/layerscape.h new file mode 100644 index 0000000000..55e0b7bc96 --- /dev/null +++ b/arch/arm/mach-layerscape/include/mach/layerscape.h @@ -0,0 +1,7 @@ +#ifndef __MACH_LAYERSCAPE_H +#define __MACH_LAYERSCAPE_H + +#define LS1046A_DDR_SDRAM_BASE 0x80000000 +#define LS1046A_DDR_FREQ 2100000000 + +#endif /* __MACH_LAYERSCAPE_H */ diff --git a/arch/arm/mach-layerscape/include/mach/lowlevel.h b/arch/arm/mach-layerscape/include/mach/lowlevel.h new file mode 100644 index 0000000000..0f5f0f3aad --- /dev/null +++ b/arch/arm/mach-layerscape/include/mach/lowlevel.h @@ -0,0 +1,7 @@ +#ifndef __MACH_LOWLEVEL_H +#define __MACH_LOWLEVEL_H + +void ls1046a_init_lowlevel(void); +void ls1046a_init_l2_latency(void); + +#endif /* __MACH_LOWLEVEL_H */ diff --git a/arch/arm/mach-layerscape/include/mach/xload.h b/arch/arm/mach-layerscape/include/mach/xload.h new file mode 100644 index 0000000000..fedd36e020 --- /dev/null +++ b/arch/arm/mach-layerscape/include/mach/xload.h @@ -0,0 +1,6 @@ +#ifndef __MACH_XLOAD_H +#define __MACH_XLOAD_H + +int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2); + +#endif /* __MACH_XLOAD_H */ diff --git a/arch/arm/mach-layerscape/lowlevel-ls1046a.c b/arch/arm/mach-layerscape/lowlevel-ls1046a.c new file mode 100644 index 0000000000..32f825ec25 --- /dev/null +++ b/arch/arm/mach-layerscape/lowlevel-ls1046a.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <io.h> +#include <asm/syscounter.h> +#include <asm/system.h> +#include <mach/errata.h> +#include <mach/lowlevel.h> +#include <soc/fsl/immap_lsch2.h> +#include <soc/fsl/fsl_immap.h> + +enum csu_cslx_access { + CSU_NS_SUP_R = 0x08, + CSU_NS_SUP_W = 0x80, + CSU_NS_SUP_RW = 0x88, + CSU_NS_USER_R = 0x04, + CSU_NS_USER_W = 0x40, + CSU_NS_USER_RW = 0x44, + CSU_S_SUP_R = 0x02, + CSU_S_SUP_W = 0x20, + CSU_S_SUP_RW = 0x22, + CSU_S_USER_R = 0x01, + CSU_S_USER_W = 0x10, + CSU_S_USER_RW = 0x11, + CSU_ALL_RW = 0xff, +}; + +struct csu_ns_dev { + unsigned long ind; + uint32_t val; +}; + +enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB1, + CSU_CSLX_QM_BM_SWPORTAL, + CSU_CSLX_PCIE3 = 16, + CSU_CSLX_PCIE3_IO, + CSU_CSLX_USB3 = 20, + CSU_CSLX_USB2, + CSU_CSLX_PFE = 23, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI1 = 41, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_IFC = 45, + CSU_CSLX_I2C1, + CSU_CSLX_USB_2, + CSU_CSLX_I2C3 = 48, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_SCFG, + CSU_CSLX_FM = 66, + CSU_CSLX_SEC5_5, + CSU_CSLX_BM, + CSU_CSLX_QM, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_IIC4 = 77, + CSU_CSLX_WDT4, + CSU_CSLX_WDT3, + CSU_CSLX_ESDHC2 = 80, + CSU_CSLX_WDT5 = 81, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, + CSU_CSLX_FTM2 = 86, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_DSCR = 121, +}; + +static struct csu_ns_dev ns_dev[] = { + {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, + {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, + {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, + {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, + {CSU_CSLX_OCRAM, CSU_ALL_RW}, + {CSU_CSLX_GIC, CSU_ALL_RW}, + {CSU_CSLX_PCIE1, CSU_ALL_RW}, + {CSU_CSLX_OCRAM2, CSU_ALL_RW}, + {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, + {CSU_CSLX_PCIE2, CSU_ALL_RW}, + {CSU_CSLX_SATA, CSU_ALL_RW}, + {CSU_CSLX_USB1, CSU_ALL_RW}, + {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, + {CSU_CSLX_PCIE3, CSU_ALL_RW}, + {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, + {CSU_CSLX_USB3, CSU_ALL_RW}, + {CSU_CSLX_USB2, CSU_ALL_RW}, + {CSU_CSLX_PFE, CSU_ALL_RW}, + {CSU_CSLX_SERDES, CSU_ALL_RW}, + {CSU_CSLX_QDMA, CSU_ALL_RW}, + {CSU_CSLX_LPUART2, CSU_ALL_RW}, + {CSU_CSLX_LPUART1, CSU_ALL_RW}, + {CSU_CSLX_LPUART4, CSU_ALL_RW}, + {CSU_CSLX_LPUART3, CSU_ALL_RW}, + {CSU_CSLX_LPUART6, CSU_ALL_RW}, + {CSU_CSLX_LPUART5, CSU_ALL_RW}, + {CSU_CSLX_DSPI1, CSU_ALL_RW}, + {CSU_CSLX_QSPI, CSU_ALL_RW}, + {CSU_CSLX_ESDHC, CSU_ALL_RW}, + {CSU_CSLX_IFC, CSU_ALL_RW}, + {CSU_CSLX_I2C1, CSU_ALL_RW}, + {CSU_CSLX_I2C3, CSU_ALL_RW}, + {CSU_CSLX_I2C2, CSU_ALL_RW}, + {CSU_CSLX_DUART2, CSU_ALL_RW}, + {CSU_CSLX_DUART1, CSU_ALL_RW}, + {CSU_CSLX_WDT2, CSU_ALL_RW}, + {CSU_CSLX_WDT1, CSU_ALL_RW}, + {CSU_CSLX_EDMA, CSU_ALL_RW}, + {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, + {CSU_CSLX_DDR, CSU_ALL_RW}, + {CSU_CSLX_QUICC, CSU_ALL_RW}, + {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, + {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, + {CSU_CSLX_SFP, CSU_ALL_RW}, + {CSU_CSLX_TMU, CSU_ALL_RW}, + {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, + {CSU_CSLX_SCFG, CSU_ALL_RW}, + {CSU_CSLX_FM, CSU_ALL_RW}, + {CSU_CSLX_SEC5_5, CSU_ALL_RW}, + {CSU_CSLX_BM, CSU_ALL_RW}, + {CSU_CSLX_QM, CSU_ALL_RW}, + {CSU_CSLX_GPIO2, CSU_ALL_RW}, + {CSU_CSLX_GPIO1, CSU_ALL_RW}, + {CSU_CSLX_GPIO4, CSU_ALL_RW}, + {CSU_CSLX_GPIO3, CSU_ALL_RW}, + {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, + {CSU_CSLX_CSU, CSU_ALL_RW}, + {CSU_CSLX_IIC4, CSU_ALL_RW}, + {CSU_CSLX_WDT4, CSU_ALL_RW}, + {CSU_CSLX_WDT3, CSU_ALL_RW}, + {CSU_CSLX_ESDHC2, CSU_ALL_RW}, + {CSU_CSLX_WDT5, CSU_ALL_RW}, + {CSU_CSLX_SAI2, CSU_ALL_RW}, + {CSU_CSLX_SAI1, CSU_ALL_RW}, + {CSU_CSLX_SAI4, CSU_ALL_RW}, + {CSU_CSLX_SAI3, CSU_ALL_RW}, + {CSU_CSLX_FTM2, CSU_ALL_RW}, + {CSU_CSLX_FTM1, CSU_ALL_RW}, + {CSU_CSLX_FTM4, CSU_ALL_RW}, + {CSU_CSLX_FTM3, CSU_ALL_RW}, + {CSU_CSLX_FTM6, CSU_ALL_RW}, + {CSU_CSLX_FTM5, CSU_ALL_RW}, + {CSU_CSLX_FTM8, CSU_ALL_RW}, + {CSU_CSLX_FTM7, CSU_ALL_RW}, + {CSU_CSLX_DSCR, CSU_ALL_RW}, +}; + +static void set_devices_ns_access(unsigned long index, u16 val) +{ + u32 *base = IOMEM(LSCH2_CSU_ADDR); + u32 *reg; + uint32_t tmp; + + reg = base + index / 2; + tmp = in_be32(reg); + if (index % 2 == 0) { + tmp &= 0x0000ffff; + tmp |= val << 16; + } else { + tmp &= 0xffff0000; + tmp |= val; + } + + out_be32(reg, tmp); +} + +static void init_csu(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ns_dev); i++) + set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val); +} + +void ls1046a_init_lowlevel(void) +{ + struct ccsr_cci400 __iomem *cci = IOMEM(LSCH2_CCI400_ADDR); + struct ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR); + + init_csu(); + ls1046a_init_l2_latency(); + set_cntfrq(25000000); + syscnt_enable(IOMEM(LSCH2_SYS_COUNTER_ADDR)); + + /* Make SEC reads and writes snoopable */ + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP | + SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A53 core cluster) + */ + if (current_el() == 3) { + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + } + + ls1046a_errata(); +} diff --git a/arch/arm/mach-layerscape/lowlevel.S b/arch/arm/mach-layerscape/lowlevel.S new file mode 100644 index 0000000000..adb3e54367 --- /dev/null +++ b/arch/arm/mach-layerscape/lowlevel.S @@ -0,0 +1,18 @@ +#include <linux/linkage.h> + +.section .text.ls1046a_init_l2_latency +ENTRY(ls1046a_init_l2_latency) + /* Initialize the L2 RAM latency */ + mrs x1, S3_1_c11_c0_2 + mov x0, #0x1C7 + /* Clear L2 Tag RAM latency and L2 Data RAM latency */ + bic x1, x1, x0 + /* Set L2 data ram latency bits [2:0] */ + orr x1, x1, #0x2 + /* set L2 tag ram latency bits [8:6] */ + orr x1, x1, #0x80 + msr S3_1_c11_c0_2, x1 + isb + + ret +ENDPROC(ls1046a_init_l2_latency); diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c index 83aeb41ae2..6b4fa8b889 100644 --- a/arch/arm/mach-mvebu/common.c +++ b/arch/arm/mach-mvebu/common.c @@ -25,6 +25,7 @@ #include <mach/socid.h> #include <asm/barebox-arm.h> #include <asm/memory.h> +#include <mach/lowlevel.h> /* * The different SoC headers containing register definitions (mach/dove-regs.h, diff --git a/arch/arm/mach-mvebu/include/mach/bbu.h b/arch/arm/mach-mvebu/include/mach/bbu.h index a06db2b144..f23c3269c0 100644 --- a/arch/arm/mach-mvebu/include/mach/bbu.h +++ b/arch/arm/mach-mvebu/include/mach/bbu.h @@ -3,7 +3,7 @@ int mvebu_bbu_flash_register_handler(const char *name, char *devicefile, int version, bool isdefault); #else -int mvebu_bbu_flash_register_handler(const char *name, +static inline int mvebu_bbu_flash_register_handler(const char *name, char *devicefile, int version, bool isdefault) { diff --git a/arch/arm/mach-mxs/mem-init.c b/arch/arm/mach-mxs/mem-init.c index 568db81302..44785c2bfc 100644 --- a/arch/arm/mach-mxs/mem-init.c +++ b/arch/arm/mach-mxs/mem-init.c @@ -30,8 +30,8 @@ #define MXS_BLOCK_SFTRST (1 << 31) #define MXS_BLOCK_CLKGATE (1 << 30) -int mxs_early_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned - int timeout) +static int mxs_early_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, + unsigned int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == mask) @@ -42,8 +42,8 @@ int mxs_early_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned return !timeout; } -int mxs_early_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned - int timeout) +static int mxs_early_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, + unsigned int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == 0) @@ -54,7 +54,7 @@ int mxs_early_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned return !timeout; } -int mxs_early_reset_block(struct mxs_register_32 *reg) +static int mxs_early_reset_block(struct mxs_register_32 *reg) { /* Clear SFTRST */ writel(MXS_BLOCK_SFTRST, ®->reg_clr); diff --git a/arch/arm/mach-mxs/power.c b/arch/arm/mach-mxs/power.c index 74c5479f3e..6febf5dbaa 100644 --- a/arch/arm/mach-mxs/power.c +++ b/arch/arm/mach-mxs/power.c @@ -14,6 +14,7 @@ #include <stmp-device.h> #include <errno.h> #include <mach/imx-regs.h> +#include <mach/power.h> #define POWER_CTRL (IMX_POWER_BASE + 0x0) #define POWER_CTRL_CLKGATE 0x40000000 diff --git a/arch/arm/mach-mxs/usb-imx23.c b/arch/arm/mach-mxs/usb-imx23.c index e626396f9d..d9a54b66f8 100644 --- a/arch/arm/mach-mxs/usb-imx23.c +++ b/arch/arm/mach-mxs/usb-imx23.c @@ -17,6 +17,7 @@ #include <io.h> #include <mach/imx23-regs.h> #include <mach/power.h> +#include <mach/usb.h> #define USBPHY_PWD (IMX_USBPHY_BASE + 0x0) diff --git a/arch/arm/mach-mxs/usb-imx28.c b/arch/arm/mach-mxs/usb-imx28.c index a87d4f6cbc..a4e1bdb280 100644 --- a/arch/arm/mach-mxs/usb-imx28.c +++ b/arch/arm/mach-mxs/usb-imx28.c @@ -18,6 +18,7 @@ #include <io.h> #include <errno.h> #include <mach/imx28-regs.h> +#include <mach/usb.h> #define POWER_CTRL (IMX_POWER_BASE + 0x0) #define POWER_CTRL_CLKGATE 0x40000000 diff --git a/arch/arm/mach-netx/clocksource.c b/arch/arm/mach-netx/clocksource.c index 263547242e..1eb977d3c9 100644 --- a/arch/arm/mach-netx/clocksource.c +++ b/arch/arm/mach-netx/clocksource.c @@ -23,7 +23,7 @@ #include <clock.h> #include <mach/netx-regs.h> -uint64_t netx_clocksource_read(void) +static uint64_t netx_clocksource_read(void) { return GPIO_REG(GPIO_COUNTER_CURRENT(0)); } diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index 6c3b953d1f..450226d2cc 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -20,6 +20,7 @@ #include <io.h> #include <restart.h> #include <mach/netx-regs.h> +#include <mach/netx-xc.h> #include "eth_firmware.h" struct fw_header { @@ -115,7 +116,7 @@ int loadxc(int xcno) return 0; } -int do_loadxc(int argc, char *argv[]) +static int do_loadxc(int argc, char *argv[]) { int xcno; diff --git a/arch/arm/mach-nomadik/8815.c b/arch/arm/mach-nomadik/8815.c index dc1bcd2bcd..9f9c0342b4 100644 --- a/arch/arm/mach-nomadik/8815.c +++ b/arch/arm/mach-nomadik/8815.c @@ -18,6 +18,7 @@ #include <init.h> #include <linux/clkdev.h> #include <mach/hardware.h> +#include <mach/board.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <linux/amba/bus.h> diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index 49ca0ee157..e9228809f0 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -193,7 +193,7 @@ config MACH_WAGO_PFC_AM35XX endif -source arch/arm/boards/phytec-som-am335x/Kconfig +source "arch/arm/boards/phytec-som-am335x/Kconfig" choice prompt "Select OMAP board" diff --git a/arch/arm/mach-omap/omap4_twl6030_mmc.c b/arch/arm/mach-omap/omap4_twl6030_mmc.c index 155add6ea1..67a9a5d6b5 100644 --- a/arch/arm/mach-omap/omap4_twl6030_mmc.c +++ b/arch/arm/mach-omap/omap4_twl6030_mmc.c @@ -17,6 +17,7 @@ #include <io.h> #include <mfd/twl6030.h> +#include <mach/omap4_twl6030_mmc.h> /* MMC voltage */ #define OMAP4_CONTROL_PBIASLITE 0x4A100600 diff --git a/arch/arm/mach-pxa/clocksource.c b/arch/arm/mach-pxa/clocksource.c index c941f154d4..5a890acb3c 100644 --- a/arch/arm/mach-pxa/clocksource.c +++ b/arch/arm/mach-pxa/clocksource.c @@ -22,7 +22,7 @@ #define OSCR 0x40A00010 -uint64_t pxa_clocksource_read(void) +static uint64_t pxa_clocksource_read(void) { return readl(OSCR); } diff --git a/arch/arm/mach-pxa/common.c b/arch/arm/mach-pxa/common.c index c0281d69ef..f2648f4687 100644 --- a/arch/arm/mach-pxa/common.c +++ b/arch/arm/mach-pxa/common.c @@ -29,8 +29,6 @@ #define OWER_WME (1 << 0) /* Watch-dog Match Enable */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ -extern void pxa_clear_reset_source(void); - static void __noreturn pxa_restart_soc(struct restart_handler *rst) { /* Clear last reset source */ diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c index 7dd6ac0648..ebda6bbe2a 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/mach-pxa/gpio.c @@ -12,6 +12,7 @@ #include <common.h> #include <errno.h> +#include <gpio.h> #include <mach/gpio.h> #include <asm/io.h> diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index 902d11ddfc..d968a11880 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -46,6 +46,10 @@ #ifdef __ASSEMBLY__ #define __REG(x) (x) +#else + +void pxa_clear_reset_source(void); + #endif #endif /* !__MACH_HARDWARE_H */ diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig index a2ddabf589..fa1a3ddcc4 100644 --- a/arch/arm/mach-samsung/Kconfig +++ b/arch/arm/mach-samsung/Kconfig @@ -73,7 +73,7 @@ config MACH_A9M2410DEV endchoice -source arch/arm/boards/friendlyarm-mini2440/Kconfig +source "arch/arm/boards/friendlyarm-mini2440/Kconfig" endmenu @@ -106,7 +106,7 @@ endchoice menu "Board specific settings" -source arch/arm/boards/friendlyarm-tiny6410/Kconfig +source "arch/arm/boards/friendlyarm-tiny6410/Kconfig" endmenu diff --git a/arch/arm/mach-samsung/clocks-s3c64xx.c b/arch/arm/mach-samsung/clocks-s3c64xx.c index cf7d0716fe..3c13f52d2e 100644 --- a/arch/arm/mach-samsung/clocks-s3c64xx.c +++ b/arch/arm/mach-samsung/clocks-s3c64xx.c @@ -322,7 +322,7 @@ void s3c_set_hsmmc_clk(int id, int src, unsigned div) writel(readl(S3C_SCLK_GATE) | S3C_SCLK_GATE_MMC(id), S3C_SCLK_GATE); } -int s3c64xx_dump_clocks(void) +static int s3c64xx_dump_clocks(void) { printf("refclk: %7d kHz\n", S3C64XX_CLOCK_REFERENCE / 1000); printf("apll: %7d kHz\n", s3c_get_apllclk() / 1000); diff --git a/arch/arm/mach-samsung/clocks-s5pcxx.c b/arch/arm/mach-samsung/clocks-s5pcxx.c index 1f4790bc07..4a1574bd89 100644 --- a/arch/arm/mach-samsung/clocks-s5pcxx.c +++ b/arch/arm/mach-samsung/clocks-s5pcxx.c @@ -38,7 +38,7 @@ uint32_t s3c_get_mpllclk(void) return m * ((S5PCXX_CLOCK_REFERENCE) / (p << s)); } -uint32_t s3c_get_apllclk(void) +static uint32_t s3c_get_apllclk(void) { uint32_t m, p, s; uint32_t reg = readl(S5P_xPLL_CON + S5P_APLL); @@ -84,7 +84,7 @@ unsigned s3c_get_uart_clk(unsigned src) { return (src & 1) ? s3c_get_uart_clk_uclk1() : s3c_get_pclk(); } -int s5pcxx_dump_clocks(void) +static int s5pcxx_dump_clocks(void) { printf("refclk: %7d kHz\n", S5PCXX_CLOCK_REFERENCE / 1000); printf("apll: %7d kHz\n", s3c_get_apllclk() / 1000); diff --git a/arch/arm/mach-stm32mp1/Kconfig b/arch/arm/mach-stm32mp1/Kconfig new file mode 100644 index 0000000000..cc7cf23cfb --- /dev/null +++ b/arch/arm/mach-stm32mp1/Kconfig @@ -0,0 +1,10 @@ +if ARCH_STM32MP1 + +config ARCH_STM32MP1157 + bool + +config MACH_STM32MP157C_DK2 + select ARCH_STM32MP1157 + bool "STM32MP157C-DK2 board" + +endif diff --git a/arch/arm/mach-stm32mp1/Makefile b/arch/arm/mach-stm32mp1/Makefile new file mode 100644 index 0000000000..16a218658a --- /dev/null +++ b/arch/arm/mach-stm32mp1/Makefile @@ -0,0 +1 @@ +obj- := __dummy__.o diff --git a/arch/arm/mach-stm32mp1/include/mach/debug_ll.h b/arch/arm/mach-stm32mp1/include/mach/debug_ll.h new file mode 100644 index 0000000000..99fedb91fe --- /dev/null +++ b/arch/arm/mach-stm32mp1/include/mach/debug_ll.h @@ -0,0 +1,28 @@ +#ifndef __MACH_STM32MP1_DEBUG_LL_H +#define __MACH_STM32MP1_DEBUG_LL_H + +#include <io.h> +#include <mach/stm32.h> + +#define DEBUG_LL_UART_ADDR STM32_UART4_BASE + +#define CR1_OFFSET 0x00 +#define CR3_OFFSET 0x08 +#define BRR_OFFSET 0x0c +#define ISR_OFFSET 0x1c +#define ICR_OFFSET 0x20 +#define RDR_OFFSET 0x24 +#define TDR_OFFSET 0x28 + +#define USART_ISR_TXE BIT(7) + +static inline void PUTC_LL(int c) +{ + void __iomem *base = IOMEM(DEBUG_LL_UART_ADDR); + + writel(c, base + TDR_OFFSET); + + while ((readl(base + ISR_OFFSET) & USART_ISR_TXE) == 0); +} + +#endif /* __MACH_STM32MP1_DEBUG_LL_H */ diff --git a/arch/arm/mach-stm32mp1/include/mach/stm32.h b/arch/arm/mach-stm32mp1/include/mach/stm32.h new file mode 100644 index 0000000000..f9bdb788b9 --- /dev/null +++ b/arch/arm/mach-stm32mp1/include/mach/stm32.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef _MACH_STM32_H_ +#define _MACH_STM32_H_ + +/* + * Peripheral memory map + */ +#define STM32_RCC_BASE 0x50000000 +#define STM32_PWR_BASE 0x50001000 +#define STM32_DBGMCU_BASE 0x50081000 +#define STM32_BSEC_BASE 0x5C005000 +#define STM32_TZC_BASE 0x5C006000 +#define STM32_ETZPC_BASE 0x5C007000 +#define STM32_TAMP_BASE 0x5C00A000 + +#define STM32_USART1_BASE 0x5C000000 +#define STM32_USART2_BASE 0x4000E000 +#define STM32_USART3_BASE 0x4000F000 +#define STM32_UART4_BASE 0x40010000 +#define STM32_UART5_BASE 0x40011000 +#define STM32_USART6_BASE 0x44003000 +#define STM32_UART7_BASE 0x40018000 +#define STM32_UART8_BASE 0x40019000 + +#define STM32_SYSRAM_BASE 0x2FFC0000 +#define STM32_SYSRAM_SIZE SZ_256K + +#define STM32_DDR_BASE 0xC0000000 +#define STM32_DDR_SIZE SZ_1G + +#endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index 3c5cced455..95172cff8c 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig @@ -23,6 +23,6 @@ config MACH_VERSATILEPB_ARM1176 endchoice -source arch/arm/boards/versatile/Kconfig +source "arch/arm/boards/versatile/Kconfig" endif diff --git a/arch/arm/pbl/Makefile b/arch/arm/pbl/Makefile index 2c28f56034..5d7e85b373 100644 --- a/arch/arm/pbl/Makefile +++ b/arch/arm/pbl/Makefile @@ -31,7 +31,7 @@ $(obj)/zbarebox.S: $(obj)/zbarebox FORCE $(call if_changed,disasm) PBL_CPPFLAGS += -fdata-sections -ffunction-sections -LDFLAGS_zbarebox := -Map $(obj)/zbarebox.map --gc-sections --no-dynamic-linker +LDFLAGS_zbarebox := -Map $(obj)/zbarebox.map --gc-sections ifdef CONFIG_PBL_RELOCATABLE LDFLAGS_zbarebox += -pie else diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index eab9452de9..a4070cfe32 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -109,12 +109,12 @@ config MACH_MIPS_XBURST select GPIOLIB endchoice -source arch/mips/mach-malta/Kconfig -source arch/mips/mach-ar231x/Kconfig -source arch/mips/mach-ath79/Kconfig -source arch/mips/mach-bcm47xx/Kconfig -source arch/mips/mach-loongson/Kconfig -source arch/mips/mach-xburst/Kconfig +source "arch/mips/mach-malta/Kconfig" +source "arch/mips/mach-ar231x/Kconfig" +source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-bcm47xx/Kconfig" +source "arch/mips/mach-loongson/Kconfig" +source "arch/mips/mach-xburst/Kconfig" endmenu diff --git a/arch/mips/lib/pbl.lds.S b/arch/mips/lib/pbl.lds.S index 1f0285dd6f..f1752ec720 100644 --- a/arch/mips/lib/pbl.lds.S +++ b/arch/mips/lib/pbl.lds.S @@ -38,6 +38,8 @@ SECTIONS . = ALIGN(4); .data : { *(.data*) } + pbl_code_size = . - HEAD_TEXT_BASE; + . = ALIGN(4); __piggydata_start = .; .piggydata : { @@ -45,9 +47,12 @@ SECTIONS } __piggydata_end = .; + pbl_image_size = . - HEAD_TEXT_BASE; + . = ALIGN(4); __bss_start = .; .bss : { *(.bss*) } __bss_stop = .; + pbl_memory_size = . - HEAD_TEXT_BASE; _end = .; } diff --git a/arch/mips/mach-ath79/art.c b/arch/mips/mach-ath79/art.c index 984d087363..2a2099e9f5 100644 --- a/arch/mips/mach-ath79/art.c +++ b/arch/mips/mach-ath79/art.c @@ -44,8 +44,8 @@ static int art_read_mac(struct device_d *dev, const char *file) fd = open_and_lseek(file, O_RDONLY, AR93000_EPPROM_OFFSET); if (fd < 0) { dev_err(dev, "Failed to open eeprom path %s %d\n", - file, fd); - return fd; + file, -errno); + return -errno; } rbytes = read_full(fd, &eeprom, sizeof(eeprom)); diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index 7a45ced7cd..798f342fa4 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -18,5 +18,5 @@ config ARCH_MPC85XX bool "Freescale MPC85xx" endchoice -source arch/ppc/mach-mpc5xxx/Kconfig -source arch/ppc/mach-mpc85xx/Kconfig +source "arch/ppc/mach-mpc5xxx/Kconfig" +source "arch/ppc/mach-mpc85xx/Kconfig" diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c435cc8a31..16c3eecce6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -62,7 +62,7 @@ config BUILTIN_DTB_NAME string "DTB to build into the barebox image" depends on BUILTIN_DTB -source arch/riscv/mach-erizo/Kconfig +source "arch/riscv/mach-erizo/Kconfig" endmenu diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3f91585d02..1793055ae0 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -95,5 +95,5 @@ choice endchoice -source arch/x86/boot/Kconfig -source arch/x86/mach-i386/Kconfig +source "arch/x86/boot/Kconfig" +source "arch/x86/mach-i386/Kconfig" |