diff options
Diffstat (limited to 'arch')
79 files changed, 423 insertions, 368 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3b486f7b8b..cdc22efdeb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -412,12 +412,3 @@ config ARM_PSCI_DEBUG Only use for debugging. endmenu - -source common/Kconfig -source commands/Kconfig -source net/Kconfig -source drivers/Kconfig -source fs/Kconfig -source lib/Kconfig -source crypto/Kconfig -source firmware/Kconfig diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c index f12a0b9652..b115c4a954 100644 --- a/arch/arm/boards/a9m2440/a9m2410dev.c +++ b/arch/arm/boards/a9m2440/a9m2410dev.c @@ -28,6 +28,8 @@ #include <mach/s3c-busctl.h> #include <mach/s3c24xx-gpio.h> +#include "baseboards.h" + /** * Initialize the CPU to be able to work with the a9m2410dev evaluation board */ diff --git a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c index 9777d15dfe..a199e4da1c 100644 --- a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c +++ b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c @@ -29,7 +29,7 @@ #include <mach/cyclone5-scan-manager.h> -static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] +static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, @@ -57,7 +57,7 @@ static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0 0x00001000, }; -static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] +static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x000C0300, 0x10040000, @@ -115,7 +115,7 @@ static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1 0x00000080, }; -static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] +static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x80040100, 0x00000000, @@ -149,7 +149,7 @@ static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2 0x00000800, }; -static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] +static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0C420D80, 0x082000FF, diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c index 822c3d8ee6..36dbc55b96 100644 --- a/arch/arm/boards/altera-socdk/lowlevel.c +++ b/arch/arm/boards/altera-socdk/lowlevel.c @@ -1,3 +1,5 @@ +#define SECT(name) __attribute__((section("socfpga_socdk_" #name))) name + #include "sdram_config.h" #include "pinmux_config.c" #include "pll_config.h" diff --git a/arch/arm/boards/altera-socdk/pinmux_config.c b/arch/arm/boards/altera-socdk/pinmux_config.c index ff784bbecf..8bdaaedb80 100644 --- a/arch/arm/boards/altera-socdk/pinmux_config.c +++ b/arch/arm/boards/altera-socdk/pinmux_config.c @@ -30,7 +30,7 @@ #include <common.h> /* pin MUX configuration data */ -static unsigned long sys_mgr_init_table[] = { +static unsigned long SECT(sys_mgr_init_table)[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c index 6531383807..c9011b2e21 100644 --- a/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c +++ b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c @@ -28,7 +28,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ static const uint32_t ac_rom_init_size = 36; -static const uint32_t ac_rom_init[36] = { +static const uint32_t SECT(ac_rom_init)[36] = { 0x20700000, 0x20780000, 0x10080431, diff --git a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg index 400a870154..9e8dce5877 100644 --- a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg +++ b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg @@ -1,3 +1,4 @@ soc imx6 loadaddr 0x00907000 +max_load_size 0x11000 dcdofs 0x400 diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c index 9a814cba79..6153de9005 100644 --- a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c +++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c @@ -29,7 +29,7 @@ #include <mach/cyclone5-scan-manager.h> -static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -56,7 +56,7 @@ static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0 0x00001000, }; -static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x000C0300, 0x300C0000, 0x300000C0, @@ -113,7 +113,7 @@ static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1 0x00000080, }; -static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, @@ -146,7 +146,7 @@ static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2 0x00000800, }; -static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0CC20D80, 0x0C3000FF, 0x0A804001, diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c index 3f12ae806f..ed2d4a72a5 100644 --- a/arch/arm/boards/ebv-socrates/lowlevel.c +++ b/arch/arm/boards/ebv-socrates/lowlevel.c @@ -1,3 +1,5 @@ +#define SECT(name) __attribute__((section("ebv_socrates_" #name))) name + #include "sdram_config.h" #include "pinmux_config.c" #include "pll_config.h" diff --git a/arch/arm/boards/ebv-socrates/pinmux_config.c b/arch/arm/boards/ebv-socrates/pinmux_config.c index faa3122466..89e6b33c86 100644 --- a/arch/arm/boards/ebv-socrates/pinmux_config.c +++ b/arch/arm/boards/ebv-socrates/pinmux_config.c @@ -30,7 +30,7 @@ #include <common.h> /* pin MUX configuration data */ -static unsigned long sys_mgr_init_table[] = { +static unsigned long SECT(sys_mgr_init_table)[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ @@ -238,4 +238,4 @@ static unsigned long sys_mgr_init_table[] = { 0, /* SPIM1USEFPGA */ 0, /* USB0USEFPGA */ 0 /* SPIM0USEFPGA */ -};
\ No newline at end of file +}; diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c index 5b5196ad77..c52da56b79 100644 --- a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c +++ b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c @@ -1,5 +1,5 @@ static const uint32_t ac_rom_init_size = 36; -static const uint32_t ac_rom_init[36] = +static const uint32_t SECT(ac_rom_init)[36] = { 0x20700000, 0x20780000, diff --git a/arch/arm/boards/guf-vincell/flash-header.imxcfg b/arch/arm/boards/guf-vincell/flash-header.imxcfg index bb0c318b7b..8bfb5d0508 100644 --- a/arch/arm/boards/guf-vincell/flash-header.imxcfg +++ b/arch/arm/boards/guf-vincell/flash-header.imxcfg @@ -1,3 +1,130 @@ +loadaddr 0x71000000 soc imx53 -loadaddr 0xf8020000 dcdofs 0x400 + +//============================================================================= +//init script for i.MX53 DDR3 +//============================================================================= + +//============================================================================= +// Enable all clocks (they are disabled by ROM code) +//============================================================================= + +//============================================================================= +// IOMUX +//============================================================================= +//DDR IO TYPE: +wm 32 0x53fa8724 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE +wm 32 0x53fa86fc 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE + +//CLOCK: +wm 32 0x53fa8578 0x00300000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 +wm 32 0x53fa8570 0x00300000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 + +//ADDRESS: +wm 32 0x53fa8574 0x00300000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS +wm 32 0x53fa8588 0x00300000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS +wm 32 0x53fa86f0 0x00300000 // IOMUXC_SW_PAD_CTL_GRP_ADDDS + +//Control: +wm 32 0x53fa856c 0x00300040 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET +wm 32 0x53fa8580 0x00300040 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 +wm 32 0x53fa8564 0x00300040 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 +wm 32 0x53fa8720 0x00300000 // IOMUXC_SW_PAD_CTL_GRP_CTLDS + +//Data Strobes: +wm 32 0x53fa86f4 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL +wm 32 0x53fa857c 0x00300040 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 +wm 32 0x53fa8590 0x00300040 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 +wm 32 0x53fa8568 0x00300040 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 +wm 32 0x53fa8558 0x00300040 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 + +//Data: +wm 32 0x53fa8714 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE +wm 32 0x53fa8718 0x00300000 // IOMUXC_SW_PAD_CTL_GRP_B0DS +wm 32 0x53fa871c 0x00300000 // IOMUXC_SW_PAD_CTL_GRP_B1DS +wm 32 0x53fa8728 0x00300000 // IOMUXC_SW_PAD_CTL_GRP_B2DS +wm 32 0x53fa872c 0x00300000 // IOMUXC_SW_PAD_CTL_GRP_B3DS + +wm 32 0x53fa8584 0x00300000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 +wm 32 0x53fa8594 0x00300000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 +wm 32 0x53fa8560 0x00300000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 +wm 32 0x53fa8554 0x00300000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 + + +//============================================================================= +// DDR Controller Registers +//============================================================================= +// Manufacturer: Micron +// Device Part Number: MT41J128M16HA-15E +// Clock Freq.: 400MHz +// Density per CS in Gb: 4 +// Chip Selects used: 1 +// Number of Banks: 8 +// Row address: 14 +// Column address: 10 +// Data bus width 32 +//============================================================================= +wm 32 0x63fd901c 0x00008000 //ESDSCR, set the Configuration request bit during MMDC set up + +//============================================================================= +// Calibration setup. +//============================================================================= +wm 32 0x63fd9040 0x05390003 // ZQHWCTRL, enable both one-time & periodic HW ZQ calibration. + +// For target board, may need to run write leveling calibration to fine tune these settings. +wm 32 0x63fd904c 0x00000000 //WLDECTRL0 +wm 32 0x63fd9050 0x00000000 //WLDECTRL1 + +////Read DQS Gating calibration +wm 32 0x63fd907c 0x01320135 // DGCTRL0 +wm 32 0x63fd9080 0x01370137 // DGCTRL1 + +//Read calibration +wm 32 0x63fd9088 0x3a413c3f // RDDLCTL + +//Write calibration +wm 32 0x63fd9090 0x49434b43 // WRDLCTL + +// Complete calibration by forced measurement: +wm 32 0x63fd90F8 0x00000800 // MUR +//============================================================================= +// Calibration setup end +//============================================================================= + +//MMDC init: +wm 32 0x63fd9004 0x0002002D // ESDPDC +wm 32 0x63fd9008 0x00333030 // ESDOTC +wm 32 0x63fd900c 0x3F435333 // ESDCFG0 +wm 32 0x63fd9010 0xB5058B63 // ESDCFG1 +wm 32 0x63fd9014 0x01FF00DB // ESDCFG2 + +//MDMISC: RALAT kept to the high level of 5. +//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: +//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 +//b. Small performence improvment +wm 32 0x63fd9018 0x00011740 // ESDMISC +wm 32 0x63fd902c 0x000026D2 // ESDRWD +wm 32 0x63fd9030 0x00430E21 // ESDOR +wm 32 0x63fd9000 0x83190000 // ESDCTL + +//Mode register writes +wm 32 0x63fd901c 0x02008032 // ESDSCR, MR2 write, CS0 +wm 32 0x63fd901c 0x00008033 // ESDSCR, MR3 write, CS0 +wm 32 0x63fd901c 0x00448031 // ESDSCR, MR1 write, CS0 +wm 32 0x63fd901c 0x15208030 // ESDSCR, MR0write, CS0 +wm 32 0x63fd901c 0x04008040 // ESDSCR, ZQ calibration command sent to device on CS0 + +//wm 32 0x63fd901c 0x0200803A // ESDSCR, MR2 write, CS1 +//wm 32 0x63fd901c 0x0000803B // ESDSCR, MR3 write, CS1 +//wm 32 0x63fd901c 0x00448039 // ESDSCR, MR1 write, CS1 +//wm 32 0x63fd901c 0x15208038 // ESDSCR, MR0write, CS1 +//wm 32 0x63fd901c 0x04008048 // ESDSCR, ZQ calibration command sent to device on CS1 + +wm 32 0x63fd9020 0x00001800 // ESDREF + +wm 32 0x63fd9058 0x00033337 // ODTCTRL + +wm 32 0x63fd901c 0x00000000 // MMDC0_ESDSCR, clear this register (especially the configuration bit as initialization is complete) + +wm 32 0x53fa8004 0x00194005 // For TO2 only, increase LDO for VDIG_PLL to 1.3V diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c index 0d2216f265..715e8b386f 100644 --- a/arch/arm/boards/guf-vincell/lowlevel.c +++ b/arch/arm/boards/guf-vincell/lowlevel.c @@ -12,130 +12,14 @@ #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> #include <asm/cache.h> -#include <mach/xload.h> - -#define IOMUX_PADCTL_DDRI_DDR (1 << 9) - -#define IOMUX_PADCTL_DDRDSE(x) ((x) << 19) -#define IOMUX_PADCTL_DDRSEL(x) ((x) << 25) - -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x554 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x558 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x560 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 0x564 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x568 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 0x570 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x574 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 0x578 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x57c -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 0x580 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x588 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x590 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x594 -#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x584 -#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x6f0 -#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x6f4 -#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x6fc -#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x710 -#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x714 -#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x718 -#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x71c -#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x720 -#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x724 -#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x728 -#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x72c - - -static void configure_dram_iomux(void) -{ - void __iomem *iomux = (void *)MX53_IOMUXC_BASE_ADDR; - u32 r1, r2, r4, r5, r6; - - /* define the INPUT mode for DRAM_D[31:0] */ - writel(0, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRMODE); - - /* - * define the INPUT mode for SDQS[3:0] - * (Freescale's documentation suggests DDR-mode for the - * control line, but their source actually uses CMOS) - */ - writel(IOMUX_PADCTL_DDRI_DDR, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL); - - r1 = IOMUX_PADCTL_DDRDSE(5); - r2 = IOMUX_PADCTL_DDRDSE(5) | PAD_CTL_PUE; - r4 = IOMUX_PADCTL_DDRSEL(2); - r5 = IOMUX_PADCTL_DDRDSE(5) | PAD_CTL_PKE | PAD_CTL_PUE | IOMUX_PADCTL_DDRI_DDR | PAD_CTL_PUS_47K_UP; - r6 = IOMUX_PADCTL_DDRDSE(4); - - /* - * this will adisable the Pull/Keeper for DRAM_x pins EXCEPT, - * for DRAM_SDQS[3:0] and DRAM_SDODT[1:0] - */ - writel(0, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRPKE); - - /* set global drive strength for all DRAM_x pins */ - writel(r4, iomux + IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE); - - /* set data dqs dqm drive strength */ - writel(r6, iomux + IOMUXC_SW_PAD_CTL_GRP_B0DS); - writel(r6, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0); - writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0); - - writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_B1DS); - writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1); - writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1); - - writel(r6, iomux + IOMUXC_SW_PAD_CTL_GRP_B2DS); - writel(r6, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2); - writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2); - - writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_B3DS); - writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3); - writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3); - - /* SDCLK pad drive strength control options */ - writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0); - writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1); - - /* Control and addr bus pad drive strength control options */ - writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS); - writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS); - writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_ADDDS); - writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_CTLDS); - writel(r2, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0); - writel(r2, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1); - - /* - * enable hysteresis on input pins - * (Freescale's documentation suggests that enable hysteresis - * would be better, but their source-code doesn't) - */ - writel(PAD_CTL_HYS, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRHYS); -} - -static void disable_watchdog(void) -{ - /* - * configure WDOG to generate external reset on trigger - * and disable power down counter - */ - writew(0x38, MX53_WDOG1_BASE_ADDR); - writew(0x0, MX53_WDOG1_BASE_ADDR + 8); - writew(0x38, MX53_WDOG2_BASE_ADDR); - writew(0x0, MX53_WDOG2_BASE_ADDR + 8); -} extern char __dtb_imx53_guf_vincell_lt_start[]; extern char __dtb_imx53_guf_vincell_start[]; -static noinline void imx53_guf_vincell_init(int is_lt) +static noinline void imx53_guf_vincell_init(void *fdt) { void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR; void __iomem *uart = IOMEM(MX53_UART2_BASE_ADDR); - void *fdt; - u32 r; - enum bootsource src; - int instance; arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); @@ -151,29 +35,10 @@ static noinline void imx53_guf_vincell_init(int is_lt) pbl_set_putc(imx_uart_putc, uart); pr_debug("GuF Vincell\n"); - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (!(r > 0x70000000 && r < 0xf0000000)) { - disable_watchdog(); - configure_dram_iomux(); - imx_esdctlv4_init(); - - imx53_get_boot_source(&src, &instance); - - if (src == BOOTSOURCE_NAND && - IS_ENABLED(CONFIG_MACH_GUF_VINCELL_XLOAD)) - imx53_nand_start_image(); - } - - if (is_lt) - fdt = __dtb_imx53_guf_vincell_lt_start; - else - fdt = __dtb_imx53_guf_vincell_start; - imx53_barebox_entry(fdt); } -static void __imx53_guf_vincell_init(int is_lt) +static noinline void __imx53_guf_vincell_init(void *fdt) { arm_early_mmu_cache_invalidate(); imx5_cpu_lowlevel_init(); @@ -181,15 +46,19 @@ static void __imx53_guf_vincell_init(int is_lt) setup_c(); barrier(); - imx53_guf_vincell_init(is_lt); + imx53_guf_vincell_init(fdt); } ENTRY_FUNCTION(start_imx53_guf_vincell_lt, r0, r1, r2) { - __imx53_guf_vincell_init(1); + void *fdt = __dtb_imx53_guf_vincell_lt_start + get_runtime_offset(); + + __imx53_guf_vincell_init(fdt); } ENTRY_FUNCTION(start_imx53_guf_vincell, r0, r1, r2) { - __imx53_guf_vincell_init(0); + void *fdt = __dtb_imx53_guf_vincell_start + get_runtime_offset(); + + __imx53_guf_vincell_init(fdt); } diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr.h b/arch/arm/boards/nxp-imx8mq-evk/ddr.h index 2c25e3f98c..8f494ae7a2 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddr.h +++ b/arch/arm/boards/nxp-imx8mq-evk/ddr.h @@ -19,6 +19,7 @@ #define ddr_cfg_phy nxp_imx8mq_evk_ddr_cfg_phy void nxp_imx8mq_evk_ddr_init(void); +void nxp_imx8mq_evk_ddr_cfg_phy(void); #define FW_1D_IMAGE imx_lpddr4_pmu_train_1d_imem_bin, \ imx_lpddr4_pmu_train_1d_dmem_bin diff --git a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg index a12c28fceb..aff8321b9a 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg +++ b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg @@ -1,4 +1,5 @@ soc imx8mq loadaddr 0x007E1000 +max_load_size 0x3F000 dcdofs 0x400 diff --git a/arch/arm/boards/phytec-som-am335x/board.c b/arch/arm/boards/phytec-som-am335x/board.c index 8c24f2b332..441d56348c 100644 --- a/arch/arm/boards/phytec-som-am335x/board.c +++ b/arch/arm/boards/phytec-som-am335x/board.c @@ -73,7 +73,7 @@ static const char *eth_names[ETH_COUNT] = {"mac0", "mac1"}; static int physom_devices_init(void) { struct state *state; - u8 mac[6]; + uint8_t mac[6]; int state_ret; int state_i; @@ -130,7 +130,7 @@ static int physom_devices_init(void) for (state_i = 0; state_i < 2; state_i++) { state_ret = state_read_mac(state, eth_names[state_i], &mac[0]); - if (state_ret == 6) + if (!state_ret && is_valid_ether_addr(&mac[0])) eth_register_ethaddr(state_i, mac); } } diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index 4079bc9de1..38a2ef641e 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -99,8 +99,17 @@ static unsigned int get_module_rev(void) static int ksz8081_phy_fixup(struct phy_device *phydev) { + /* + * 0x8100 default + * 0x0080 RMII 50 MHz clock mode + * 0x0010 LED Mode 1 + */ phy_write(phydev, 0x1f, 0x8190); - phy_write(phydev, 0x16, 0x202); + /* + * 0x0002 Override strap-in for RMII mode + * This should be default but after reset we occasionally read 0x0001 + */ + phy_write(phydev, 0x16, 0x2); return 0; } diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 05f918f6c9..9d81c278ca 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -116,4 +116,5 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false); -PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_256mb, imx6ull_phytec_phycore_som, SZ_256M, false); +PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_256mb, imx6ull_phytec_phycore_som_lc, SZ_256M, false); +PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_512mb, imx6ull_phytec_phycore_som, SZ_512M, false); diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c index b7ce0ad425..650b26ce7d 100644 --- a/arch/arm/boards/raspberry-pi/rpi-common.c +++ b/arch/arm/boards/raspberry-pi/rpi-common.c @@ -176,6 +176,7 @@ const struct rpi_model rpi_models_new_scheme[] = { RPI_MODEL(BCM2836_BOARD_REV_2_B, "2 Model B", rpi_b_plus_init), RPI_MODEL(BCM2837_BOARD_REV_3_B, "3 Model B", rpi_b_plus_init), RPI_MODEL(BCM2835_BOARD_REV_ZERO, "Zero", rpi_b_plus_init), + RPI_MODEL(BCM2835_BOARD_REV_ZERO_W, "Zero W", rpi_b_plus_init), }; static int rpi_board_rev = 0; diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c index 9cedc74e07..b3da58f71f 100644 --- a/arch/arm/boards/reflex-achilles/lowlevel.c +++ b/arch/arm/boards/reflex-achilles/lowlevel.c @@ -74,18 +74,17 @@ static noinline void achilles_start(void) arria10_start_image(barebox); } +ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K - 32); + achilles_start(); +} + ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2) { void *fdt; - if (get_pc() > ARRIA10_OCRAM_ADDR) { - arm_cpu_lowlevel_init(); - - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K - 32); - - achilles_start(); - } - fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset(); barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); diff --git a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg index 33621117d4..68cb08e200 100644 --- a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg +++ b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg @@ -1,3 +1,4 @@ loadaddr 0x00907000 soc imx6 +max_load_size 0x11000 dcdofs 0x400 diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c index d5098055ff..7caed2ee31 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c +++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c @@ -29,7 +29,7 @@ #include <mach/cyclone5-scan-manager.h> -static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -56,7 +56,7 @@ static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0 0x00001000, }; -static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x00100000, 0x10040000, 0x100000C0, @@ -113,7 +113,7 @@ static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1 0x00000080, }; -static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c index deac0e9cb2..46f6477a0f 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c +++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c @@ -1,3 +1,5 @@ +#define SECT(name) __attribute__((section("terasic_de0_nano_soc_" #name))) name + #include "sdram_config.h" #include "pinmux_config.c" #include "pll_config.h" diff --git a/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c index fd37608acb..1fc530debe 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c +++ b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c @@ -29,7 +29,7 @@ #include <common.h> -unsigned long sys_mgr_init_table[] = { +unsigned long SECT(sys_mgr_init_table)[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c index fe0764b0ce..8044477e01 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c +++ b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c @@ -28,7 +28,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ static const uint32_t ac_rom_init_size = 36; -static const uint32_t ac_rom_init[36] = +static const uint32_t SECT(ac_rom_init)[36] = { 0x20700000, 0x20780000, diff --git a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c index 9367b0d110..c2ccc46d9b 100644 --- a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c +++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c @@ -29,7 +29,7 @@ #include <mach/cyclone5-scan-manager.h> -static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -56,7 +56,7 @@ static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0 0x00001000, }; -static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x00100000, 0x300C0000, 0x300000C0, @@ -113,7 +113,7 @@ static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1 0x00000080, }; -static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, @@ -146,7 +146,7 @@ static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2 0x00000800, }; -static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { +static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0C420D80, 0x082000FF, 0x0A804001, diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c index 1dd7940aeb..585c786598 100644 --- a/arch/arm/boards/terasic-sockit/lowlevel.c +++ b/arch/arm/boards/terasic-sockit/lowlevel.c @@ -1,3 +1,5 @@ +#define SECT(name) __attribute__((section("terasic_sockit_" #name))) name + #include "sdram_config.h" #include "pinmux_config.c" #include "pll_config.h" diff --git a/arch/arm/boards/terasic-sockit/pinmux_config.c b/arch/arm/boards/terasic-sockit/pinmux_config.c index bcf27dbe1e..9a1316d0df 100644 --- a/arch/arm/boards/terasic-sockit/pinmux_config.c +++ b/arch/arm/boards/terasic-sockit/pinmux_config.c @@ -29,7 +29,7 @@ #include <common.h> -static unsigned long sys_mgr_init_table[] = { +static unsigned long SECT(sys_mgr_init_table)[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c index fe0764b0ce..8044477e01 100644 --- a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c +++ b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c @@ -28,7 +28,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ static const uint32_t ac_rom_init_size = 36; -static const uint32_t ac_rom_init[36] = +static const uint32_t SECT(ac_rom_init)[36] = { 0x20700000, 0x20780000, diff --git a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg index 400a870154..a4abe197e4 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg +++ b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg @@ -1,3 +1,4 @@ soc imx6 loadaddr 0x00907000 +max_load_size 0x31000 dcdofs 0x400 diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index bf84dfa9f8..64b202b9dc 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -7,7 +7,6 @@ CONFIG_MACH_FREESCALE_MX51_PDK=y CONFIG_MACH_CCMX53=y CONFIG_MACH_FREESCALE_MX53_LOCO=y CONFIG_MACH_GUF_VINCELL=y -CONFIG_MACH_GUF_VINCELL_XLOAD=y CONFIG_MACH_TQMA53=y CONFIG_MACH_FREESCALE_MX53_VMX53=y CONFIG_MACH_TX53=y diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index 3a50bae8f2..d9688ca29c 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -59,6 +59,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_LED=y CONFIG_CMD_SPI=y CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_WD=y CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_FIRMWARELOAD=y CONFIG_CMD_OF_NODE=y @@ -73,15 +74,22 @@ CONFIG_OF_BAREBOX_ENV_IN_FS=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_NET_DESIGNWARE=y CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_MTD_NAND_DENALI=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_CADENCE_QUADSPI=y CONFIG_MCI=y CONFIG_MCI_DW=y -CONFIG_MFD_MC13XXX=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_GPIO_OF=y CONFIG_LED_TRIGGERS=y CONFIG_EEPROM_AT25=y CONFIG_KEYBOARD_GPIO=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_DW=y CONFIG_GPIO_DESIGNWARE=y CONFIG_FIRMWARE_ALTERA_SOCFPGA=y CONFIG_FS_EXT4=y diff --git a/arch/arm/cpu/interrupts.c b/arch/arm/cpu/interrupts.c index 73f023bd71..b9b91f3153 100644 --- a/arch/arm/cpu/interrupts.c +++ b/arch/arm/cpu/interrupts.c @@ -28,6 +28,14 @@ #include <asm/unwind.h> #include <init.h> +/* Avoid missing prototype warning, called from assembly */ +void do_undefined_instruction (struct pt_regs *pt_regs); +void do_software_interrupt (struct pt_regs *pt_regs); +void do_prefetch_abort (struct pt_regs *pt_regs); +void do_data_abort (struct pt_regs *pt_regs); +void do_fiq (struct pt_regs *pt_regs); +void do_irq (struct pt_regs *pt_regs); + /** * Display current register set content * @param[in] regs Guess what diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c index f6f0c9d095..e8475d2e47 100644 --- a/arch/arm/cpu/interrupts_64.c +++ b/arch/arm/cpu/interrupts_64.c @@ -25,6 +25,16 @@ #include <asm/system.h> #include <asm/esr.h> +/* Avoid missing prototype warning, called from assembly */ +void do_bad_sync (struct pt_regs *pt_regs); +void do_bad_irq (struct pt_regs *pt_regs); +void do_bad_fiq (struct pt_regs *pt_regs); +void do_bad_error (struct pt_regs *pt_regs); +void do_fiq (struct pt_regs *pt_regs); +void do_irq (struct pt_regs *pt_regs); +void do_error (struct pt_regs *pt_regs); +void do_sync(struct pt_regs *pt_regs, unsigned int esr, unsigned long far); + static const char *esr_class_str[] = { [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c index 69d1b20718..99ddd5a441 100644 --- a/arch/arm/cpu/mmu_64.c +++ b/arch/arm/cpu/mmu_64.c @@ -19,6 +19,7 @@ #define pr_fmt(fmt) "mmu: " fmt #include <common.h> +#include <dma.h> #include <dma-dir.h> #include <init.h> #include <mmu.h> diff --git a/arch/arm/cpu/psci.c b/arch/arm/cpu/psci.c index 1c8197aa3f..c4c8c64cbe 100644 --- a/arch/arm/cpu/psci.c +++ b/arch/arm/cpu/psci.c @@ -156,6 +156,10 @@ static unsigned long psci_system_reset(void) restart_machine(); } +/* Avoid missing prototype warning, called from assembly */ +void psci_entry(u32 r0, u32 r1, u32 r2, u32 r3, u32 r4, u32 r5, u32 r6, + struct arm_smccc_res *res); + void psci_entry(u32 r0, u32 r1, u32 r2, u32 r3, u32 r4, u32 r5, u32 r6, struct arm_smccc_res *res) { @@ -209,6 +213,9 @@ static int of_psci_fixup(struct device_node *root, void *unused) return 0; } +/* Avoid missing prototype warning, called from assembly */ +int psci_cpu_entry_c(void); + int psci_cpu_entry_c(void) { void (*entry)(u32 context); diff --git a/arch/arm/cpu/sections.c b/arch/arm/cpu/sections.c index ab08ebf42e..a53236d900 100644 --- a/arch/arm/cpu/sections.c +++ b/arch/arm/cpu/sections.c @@ -10,4 +10,3 @@ char __bss_start[0] __attribute__((section(".__bss_start"))); char __bss_stop[0] __attribute__((section(".__bss_stop"))); char __image_start[0] __attribute__((section(".__image_start"))); char __image_end[0] __attribute__((section(".__image_end"))); -uint32_t __image_end_marker[1] __attribute__((section(".__image_end_marker"))) = { 0xdeadbeef }; diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c index 6fad30adab..633c9e8c83 100644 --- a/arch/arm/cpu/sm.c +++ b/arch/arm/cpu/sm.c @@ -94,7 +94,7 @@ static unsigned long get_gicc_base_address(void) #define GICD_IGROUPRn 0x0080 -int armv7_init_nonsec(void) +static int armv7_init_nonsec(void) { void __iomem *gicd = IOMEM(get_gicd_base_address()); unsigned itlinesnr, i; diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c index a79d64eaa6..768fa9e1b2 100644 --- a/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c @@ -34,6 +34,8 @@ #include <debug_ll.h> +#include "entry.h" + unsigned long arm_stack_top; static unsigned long arm_barebox_size; static void *barebox_boarddata; @@ -231,12 +233,16 @@ __noreturn void barebox_non_pbl_start(unsigned long membase, #ifndef CONFIG_PBL_IMAGE +void start(void); + void NAKED __section(.text_entry) start(void) { barebox_arm_head(); } #else + +void start(unsigned long membase, unsigned long memsize, void *boarddata); /* * First function in the uncompressed image. We get here from * the pbl. The stack already has been set up by the pbl. diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c index 048bca0c95..e52716557b 100644 --- a/arch/arm/cpu/uncompress.c +++ b/arch/arm/cpu/uncompress.c @@ -34,9 +34,14 @@ #include <debug_ll.h> +#include "entry.h" + unsigned long free_mem_ptr; unsigned long free_mem_end_ptr; +extern unsigned char input_data[]; +extern unsigned char input_data_end[]; + void __noreturn barebox_multi_pbl_start(unsigned long membase, unsigned long memsize, void *boarddata) { @@ -44,11 +49,11 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase, void __noreturn (*barebox)(unsigned long, unsigned long, void *); unsigned long endmem = membase + memsize; unsigned long barebox_base; - uint32_t *image_end; - void *pg_start; + void *pg_start, *pg_end; unsigned long pc = get_pc(); - image_end = (void *)__image_end_marker + global_variable_offset(); + pg_start = input_data + global_variable_offset(); + pg_end = input_data_end + global_variable_offset(); if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) { /* @@ -62,14 +67,7 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase, relocate_to_adr(membase); } - /* - * image_end is the image_end_marker defined above. It is the last location - * in the executable. Right after the executable the build process adds - * the size of the appended compressed binary followed by the compressed - * binary itself. - */ - pg_start = image_end + 2; - pg_len = *(image_end + 1); + pg_len = pg_end - pg_start; uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4)); if (IS_ENABLED(CONFIG_RELOCATABLE)) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 503d9b18f9..c08b35a101 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -63,6 +63,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6dl-phytec-phycore-som-nand.dtb.o \ imx6dl-phytec-phycore-som-emmc.dtb.o \ imx6ul-phytec-phycore-som.dtb.o \ + imx6ull-phytec-phycore-som-lc.dtb.o \ imx6ull-phytec-phycore-som.dtb.o pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts index 73f7dbe9a6..6d1876702d 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts @@ -39,3 +39,11 @@ &usdhc1 { status = "okay"; }; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi index 2504c9729d..d829fdd6fb 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -89,6 +89,20 @@ status = "disabled"; }; +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + dr_mode = "otg"; + disable-over-current; + status = "disabled"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -163,6 +177,12 @@ >; }; + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts new file mode 100644 index 0000000000..94a7830756 --- /dev/null +++ b/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller <s.riedmueller@phytec.de> + */ + +/dts-v1/; + +#include <arm/imx6ull.dtsi> +#include "imx6ul-phytec-phycore-som.dtsi" + +/ { + model = "Phytec phyCORE-i.MX6 ULL SOM low-cost"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull"; +}; + +&fec1 { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts index de04132a02..4d73010131 100644 --- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts +++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts @@ -39,3 +39,11 @@ &usdhc1 { status = "okay"; }; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts index 176e06df12..e94a321999 100644 --- a/arch/arm/dts/socfpga_arria10_achilles.dts +++ b/arch/arm/dts/socfpga_arria10_achilles.dts @@ -242,3 +242,7 @@ reg-io-width = <4>; status = "okay"; }; + +&watchdog1 { + status = "okay"; +}; diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h index c0c749ae34..e065b479e3 100644 --- a/arch/arm/include/asm/barebox-arm.h +++ b/arch/arm/include/asm/barebox-arm.h @@ -85,6 +85,8 @@ static inline void boarddata_create(void *adr, u32 machine) u32 barebox_arm_machine(void); +unsigned long arm_mem_ramoops_get(void); + struct barebox_arm_boarddata_compressed_dtb { #define BAREBOX_ARM_BOARDDATA_COMPRESSED_DTB_MAGIC 0x7b66bcbd u32 magic; diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index 99833ac5b4..417808bfcc 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h @@ -56,5 +56,6 @@ void __dma_inv_range(unsigned long, unsigned long); void mmu_early_enable(unsigned long membase, unsigned long memsize, unsigned long ttb); +void mmu_early_disable(void); #endif /* __ASM_MMU_H */ diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 7fbd8d9b6f..042e0cef70 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -23,6 +23,8 @@ struct pt_regs { unsigned long regs[31]; }; +void show_regs(struct pt_regs *); + #endif /* __ASSEMBLY__ */ #else /* CONFIG_CPU_64 */ diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h index b4659256cc..8ab01f2b71 100644 --- a/arch/arm/include/asm/sections.h +++ b/arch/arm/include/asm/sections.h @@ -11,7 +11,6 @@ extern char __dynsym_start[]; extern char __dynsym_end[]; extern char __exceptions_start[]; extern char __exceptions_stop[]; -extern uint32_t __image_end_marker[]; #endif diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S index ddc65bbf45..53c9ce0fe6 100644 --- a/arch/arm/lib/pbl.lds.S +++ b/arch/arm/lib/pbl.lds.S @@ -36,6 +36,8 @@ SECTIONS { . = BASE; + .image_start : { *(.__image_start) } + PRE_IMAGE . = ALIGN(4); @@ -91,9 +93,7 @@ SECTIONS } __piggydata_end = .; - . = ALIGN(4); - .image_end : { *(.__image_end_marker) } - __image_end = .; + .image_end : { *(.__image_end) } _barebox_image_size = __image_end - BASE; _barebox_pbl_size = __bss_start - BASE; diff --git a/arch/arm/lib32/unwind.c b/arch/arm/lib32/unwind.c index fd4b0b22cb..02fae3c253 100644 --- a/arch/arm/lib32/unwind.c +++ b/arch/arm/lib32/unwind.c @@ -62,9 +62,9 @@ static void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame) { #ifdef CONFIG_KALLSYMS - printk("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from); + pr_warning("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from); #else - printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from); + pr_warning("Function entered at [<%08lx>] from [<%08lx>]\n", where, from); #endif } diff --git a/arch/arm/lib64/stacktrace.c b/arch/arm/lib64/stacktrace.c index b8352c1454..4391188446 100644 --- a/arch/arm/lib64/stacktrace.c +++ b/arch/arm/lib64/stacktrace.c @@ -11,6 +11,7 @@ #include <common.h> #include <asm/stacktrace.h> +#include <asm/unwind.h> #define THREAD_SIZE 16384 @@ -45,7 +46,7 @@ int unwind_frame(struct stackframe *frame) return 0; } -void dump_backtrace_entry(unsigned long where, unsigned long from) +static void dump_backtrace_entry(unsigned long where, unsigned long from) { #ifdef CONFIG_KALLSYMS printf("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 7a895c2689..b101e61d22 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -538,6 +538,7 @@ config MACH_AT91SAM9X5EK config MACH_MICROCHIP_KSZ9477_EVB bool "Microchip EVB-KSZ9477 Evaluation Kit" + depends on ARCH_SAMA5D3 select OFDEVICE select COMMON_CLK_OF_PROVIDER help diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 0d1ac074e3..76b573f85f 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -133,6 +133,8 @@ struct bcm2835_mbox_tag_hdr { #define BCM2837_BOARD_REV_3_B 0x8 /* Zero */ #define BCM2835_BOARD_REV_ZERO 0x9 +/* Zero W */ +#define BCM2835_BOARD_REV_ZERO_W 0xc /* * 0x2..0xf from: diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index edfc851138..d9b60053db 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -190,6 +190,7 @@ config ARCH_VF610 select ARCH_HAS_FEC_IMX select CPU_V7 select PINCTRL + select OFDEVICE select OFTREE select COMMON_CLK select COMMON_CLK_OF_PROVIDER @@ -284,15 +285,6 @@ config MACH_GUF_VINCELL bool "Garz-Fricke Vincell" select ARCH_IMX53 -config MACH_GUF_VINCELL_XLOAD - depends on MACH_GUF_VINCELL - bool "Garz-Fricke Vincell NAND xload support" - help - The Vincell initializes SDRAM from board code. This normally limits - the image size to the size of the SoC internal SRAM. Enable this - option to be able to use bigger images when booting from NAND. Images - built with this option are no longer bootable from USB though. - config MACH_TQMA53 bool "TQ i.MX53 TQMa53" select ARCH_IMX53 diff --git a/arch/arm/mach-imx/imx50.c b/arch/arm/mach-imx/imx50.c index 4fd5481670..b76e3794e3 100644 --- a/arch/arm/mach-imx/imx50.c +++ b/arch/arm/mach-imx/imx50.c @@ -86,7 +86,7 @@ int imx50_devices_init(void) return 0; } -void imx50_init_lowlevel_early(unsigned int cpufreq_mhz) +static void imx50_init_lowlevel_early(unsigned int cpufreq_mhz) { void __iomem *ccm = IOMEM(MX50_CCM_BASE_ADDR); u32 r; diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index dc537941a7..be58da4da2 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -19,6 +19,7 @@ void vf610_boot_save_loc(void); void imx8_boot_save_loc(void); void imx25_get_boot_source(enum bootsource *src, int *instance); +void imx27_get_boot_source(enum bootsource *src, int *instance); void imx35_get_boot_source(enum bootsource *src, int *instance); void imx51_get_boot_source(enum bootsource *src, int *instance); void imx53_get_boot_source(enum bootsource *src, int *instance); diff --git a/arch/arm/mach-imx/include/mach/imx-header.h b/arch/arm/mach-imx/include/mach/imx-header.h index 05f1669318..50584bb24b 100644 --- a/arch/arm/mach-imx/include/mach/imx-header.h +++ b/arch/arm/mach-imx/include/mach/imx-header.h @@ -96,6 +96,7 @@ struct config_data { uint32_t image_load_addr; uint32_t image_dcd_offset; uint32_t image_size; + uint32_t max_load_size; uint32_t load_size; char *outfile; char *srkfile; diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c index f298a36046..7574fe80b2 100644 --- a/arch/arm/mach-imx/nand.c +++ b/arch/arm/mach-imx/nand.c @@ -17,6 +17,7 @@ #include <mach/imx25-regs.h> #include <mach/imx27-regs.h> #include <mach/imx35-regs.h> +#include <mach/imx-nand.h> #include <io.h> #define RCSR_NFC_FMS (1 << 8) diff --git a/arch/arm/mach-imx/usb-imx6.c b/arch/arm/mach-imx/usb-imx6.c index 5e3df10e44..4236bcb772 100644 --- a/arch/arm/mach-imx/usb-imx6.c +++ b/arch/arm/mach-imx/usb-imx6.c @@ -20,6 +20,7 @@ #include <common.h> #include <io.h> #include <mach/imx6-regs.h> +#include <mach/usb.h> #define SET 0x4 #define CLR 0x8 @@ -33,7 +34,6 @@ #define USB_UH1_USBCMD 0x340 #define USB_CMD_RUNSTOP (1 << 0) -#define USB_CMD_RESET (1 << 1) #define USB_OVER_CUR_DIS (1 << 7) #define USBPHY_CTRL_SFTRST (1 << 31) diff --git a/arch/arm/mach-imx/xload-common.c b/arch/arm/mach-imx/xload-common.c index 13cd612d3c..c5727eba38 100644 --- a/arch/arm/mach-imx/xload-common.c +++ b/arch/arm/mach-imx/xload-common.c @@ -5,25 +5,6 @@ int imx_image_size(void) { - uint32_t *image_end = (void *)__image_end; - uint32_t payload_len, pbl_len, imx_header_len, sizep; - void *pg_start; - - pg_start = image_end + 1; - /* i.MX header is 4k */ - imx_header_len = SZ_4K; - - /* The length of the PBL image */ - pbl_len = __image_end - _text; - - sizep = 4; - - /* The length of the payload is appended directly behind the PBL */ - payload_len = *(image_end); - - pr_debug("%s: payload_len: 0x%08x pbl_len: 0x%08x\n", - __func__, payload_len, pbl_len); - - return imx_header_len + pbl_len + sizep + payload_len; + return barebox_image_size + SZ_4K; } diff --git a/arch/arm/mach-omap/am33xx_bbu_emmc.c b/arch/arm/mach-omap/am33xx_bbu_emmc.c index 1fd7222ddc..29e13de778 100644 --- a/arch/arm/mach-omap/am33xx_bbu_emmc.c +++ b/arch/arm/mach-omap/am33xx_bbu_emmc.c @@ -18,6 +18,7 @@ #include <fs.h> #include <fcntl.h> #include <filetype.h> +#include <mach/bbu.h> #define PART_TABLE_SIZE 66 #define PART_TABLE_OFFSET 0x1BE diff --git a/arch/arm/mach-omap/am33xx_bbu_nand.c b/arch/arm/mach-omap/am33xx_bbu_nand.c index 6fc6e7e40f..4c1a28d37e 100644 --- a/arch/arm/mach-omap/am33xx_bbu_nand.c +++ b/arch/arm/mach-omap/am33xx_bbu_nand.c @@ -22,6 +22,7 @@ #include <fcntl.h> #include <libfile.h> #include <filetype.h> +#include <mach/bbu.h> struct nand_bbu_handler { struct bbu_handler bbu_handler; diff --git a/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c index 03477dbaf1..7d2ef1f0f2 100644 --- a/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c +++ b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c @@ -20,6 +20,7 @@ #include <fs.h> #include <fcntl.h> #include <linux/stat.h> +#include <mach/bbu.h> /* * AM35xx, AM33xx chips use big endian MLO for SPI NOR flash diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c index ad735cb216..e63e93601e 100644 --- a/arch/arm/mach-omap/am33xx_clock.c +++ b/arch/arm/mach-omap/am33xx_clock.c @@ -15,6 +15,7 @@ #include <common.h> #include <asm/io.h> #include <mach/am33xx-clock.h> +#include <mach/am33xx-generic.h> #include <asm-generic/div64.h> #define PRCM_MOD_EN 0x2 diff --git a/arch/arm/mach-samsung/clocks-s3c24xx.c b/arch/arm/mach-samsung/clocks-s3c24xx.c index 13e68678e1..34b38f345c 100644 --- a/arch/arm/mach-samsung/clocks-s3c24xx.c +++ b/arch/arm/mach-samsung/clocks-s3c24xx.c @@ -109,15 +109,6 @@ uint32_t s3c_get_pclk(void) } /** - * Calculate the UCLK frequency used by the USB host device - * @return Current frequency in Hz - */ -uint32_t s3c24_get_uclk(void) -{ - return s3c_get_upllclk(); -} - -/** * Return correct UART frequency based on the UCON register */ unsigned s3c_get_uart_clk(unsigned src) @@ -137,7 +128,7 @@ unsigned s3c_get_uart_clk(unsigned src) /** * Show the user the current clock settings */ -int s3c24xx_dump_clocks(void) +static int s3c24xx_dump_clocks(void) { printf("refclk: %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000); printf("mpll: %7d kHz\n", s3c_get_mpllclk() / 1000); diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h index f9c6d91b5b..52642ee81f 100644 --- a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h +++ b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h @@ -52,4 +52,6 @@ struct s3c24x0_nand_platform_data { * @brief Basic declaration to use the s3c24x0 NAND driver */ +void nand_boot(void); + #endif /* MACH_S3C24XX_NAND_H */ diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 65097b676a..3d8fc8ba42 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -21,6 +21,7 @@ config ARCH_SOCFPGA_CYCLONE5 select HAVE_PBL_MULTI_IMAGES select OFDEVICE if !ARCH_SOCFPGA_XLOAD select OFTREE if !ARCH_SOCFPGA_XLOAD + select GPIOLIB if !ARCH_SOCFPGA_XLOAD config ARCH_SOCFPGA_ARRIA10 bool diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c index e5ecb0f1b8..9b58c452d4 100644 --- a/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c @@ -221,7 +221,7 @@ static int check_test_mem(int start) #endif // TEST_SIZE -static void set_failing_group_stage(uint32_t group, uint32_t stage, uint32_t substage) +static void SECT(set_failing_group_stage)(uint32_t group, uint32_t stage, uint32_t substage) { if (gbl->error_stage == CAL_STAGE_NIL) { gbl->error_substage = substage; @@ -313,7 +313,7 @@ static void initialize(void) } } -static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) +static void SECT(set_rank_and_odt_mask)(uint32_t rank, uint32_t odt_mode) { uint32_t odt_mask_0 = 0; uint32_t odt_mask_1 = 0; @@ -485,7 +485,7 @@ static inline void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase) } -static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, uint32_t phase) +static void SECT(scc_mgr_set_dqs_en_phase_all_ranks)(uint32_t read_group, uint32_t phase) { uint32_t r; uint32_t update_scan_chains; @@ -513,7 +513,7 @@ static inline void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t } -static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, uint32_t phase) +static void SECT(scc_mgr_set_dqdqs_output_phase_all_ranks)(uint32_t write_group, uint32_t phase) { uint32_t r; uint32_t update_scan_chains; @@ -541,7 +541,7 @@ static inline void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay) } -static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, uint32_t delay) +static void SECT(scc_mgr_set_dqs_en_delay_all_ranks)(uint32_t read_group, uint32_t delay) { uint32_t r; @@ -562,7 +562,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, uint32_t del } } -static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay) +static void SECT(scc_mgr_set_oct_out1_delay)(uint32_t write_group, uint32_t delay) { uint32_t read_group; @@ -581,7 +581,7 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay) } -static void scc_mgr_set_oct_out2_delay(uint32_t write_group, uint32_t delay) +static void SECT(scc_mgr_set_oct_out2_delay)(uint32_t write_group, uint32_t delay) { uint32_t read_group; @@ -692,7 +692,7 @@ static inline void scc_mgr_set_dm_in_delay(uint32_t write_group, uint32_t dm, ui WRITE_SCC_DM_IO_IN_DELAY(dm, delay); } -static inline void scc_mgr_set_dm_bypass(uint32_t write_group, uint32_t dm, uint32_t bypass) +static inline void SECT(scc_mgr_set_dm_bypass)(uint32_t write_group, uint32_t dm, uint32_t bypass) { // Load the setting in the SCC manager WRITE_SCC_DM_BYPASS(dm, bypass); @@ -700,7 +700,7 @@ static inline void scc_mgr_set_dm_bypass(uint32_t write_group, uint32_t dm, uint //USER Zero all DQS config // TODO: maybe rename to scc_mgr_zero_dqs_config (or something) -static void scc_mgr_zero_all(void) +static void SECT(scc_mgr_zero_all)(void) { uint32_t i, r; @@ -735,7 +735,7 @@ static void scc_mgr_zero_all(void) } } -static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode) +static void SECT(scc_set_bypass_mode)(uint32_t write_group, uint32_t mode) { // mode = 0 : Do NOT bypass - Half Rate Mode // mode = 1 : Bypass - Full Rate Mode @@ -763,7 +763,7 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode) } // Moving up to avoid warnings -static void scc_mgr_load_dqs_for_write_group(uint32_t write_group) +static void SECT(scc_mgr_load_dqs_for_write_group)(uint32_t write_group) { uint32_t read_group; @@ -780,7 +780,7 @@ static void scc_mgr_load_dqs_for_write_group(uint32_t write_group) } } -static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, int32_t out_only) +static void SECT(scc_mgr_zero_group)(uint32_t write_group, uint32_t test_begin, int32_t out_only) { uint32_t i, r; @@ -861,7 +861,7 @@ static void scc_mgr_load_dm(uint32_t dm) //USER apply and load a particular input delay for the DQ pins in a group //USER group_bgn is the index of the first dq pin (in the write group) -static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group, uint32_t group_bgn, +static void SECT(scc_mgr_apply_group_dq_in_delay)(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t i, p; @@ -874,7 +874,7 @@ static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group, uint32_t group //USER apply and load a particular output delay for the DQ pins in a group -static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group, uint32_t group_bgn, +static void SECT(scc_mgr_apply_group_dq_out1_delay)(uint32_t write_group, uint32_t group_bgn, uint32_t delay1) { uint32_t i, p; @@ -887,7 +887,7 @@ static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group, uint32_t gro //USER apply and load a particular output delay for the DM pins in a group -static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group, uint32_t delay1) +static void SECT(scc_mgr_apply_group_dm_out1_delay)(uint32_t write_group, uint32_t delay1) { uint32_t i; @@ -898,7 +898,7 @@ static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group, uint32_t del } //USER apply and load delay on both DQS and OCT out1 -static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group, uint32_t delay) +static void SECT(scc_mgr_apply_group_dqs_io_and_oct_out1)(uint32_t write_group, uint32_t delay) { scc_mgr_set_dqs_out1_delay(write_group, delay); scc_mgr_load_dqs_io(); @@ -910,7 +910,7 @@ static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group, uint32 //USER set delay on both DQS and OCT out1 by incrementally changing //USER the settings one dtap at a time towards the target value, to avoid //USER breaking the lock of the DLL/PLL on the memory device. -static void scc_mgr_set_group_dqs_io_and_oct_out1_gradual(uint32_t write_group, uint32_t delay) +static void SECT(scc_mgr_set_group_dqs_io_and_oct_out1_gradual)(uint32_t write_group, uint32_t delay) { uint32_t d = READ_SCC_DQS_IO_OUT1_DELAY(); @@ -934,7 +934,7 @@ static void scc_mgr_set_group_dqs_io_and_oct_out1_gradual(uint32_t write_group, //USER apply a delay to the entire output side: DQ, DM, DQS, OCT -static void scc_mgr_apply_group_all_out_delay(uint32_t write_group, uint32_t group_bgn, +static void SECT(scc_mgr_apply_group_all_out_delay)(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { //USER dq shift @@ -951,7 +951,7 @@ static void scc_mgr_apply_group_all_out_delay(uint32_t write_group, uint32_t gro } //USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks -static void scc_mgr_apply_group_all_out_delay_all_ranks(uint32_t write_group, uint32_t group_bgn, +static void SECT(scc_mgr_apply_group_all_out_delay_all_ranks)(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t r; @@ -968,7 +968,7 @@ static void scc_mgr_apply_group_all_out_delay_all_ranks(uint32_t write_group, ui //USER apply a delay to the entire output side: DQ, DM, DQS, OCT -static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, uint32_t group_bgn, +static void SECT(scc_mgr_apply_group_all_out_delay_add)(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t i, p, new_delay; @@ -1046,7 +1046,7 @@ static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, uint32_t } //USER apply a delay to the entire output side (DQ, DM, DQS, OCT) and to all ranks -static void scc_mgr_apply_group_all_out_delay_add_all_ranks(uint32_t write_group, +static void SECT(scc_mgr_apply_group_all_out_delay_add_all_ranks)(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t r; @@ -1067,7 +1067,7 @@ static inline void scc_mgr_spread_out2_delay_all_ranks(uint32_t write_group, uin // optimization used to recover some slots in ddr3 inst_rom // could be applied to other protocols if we wanted to -static void set_jump_as_return(void) +static void SECT(set_jump_as_return)(void) { // to save space, we replace return with jump to special shared RETURN instruction // so we set the counter to large value so that we always jump @@ -1077,7 +1077,7 @@ static void set_jump_as_return(void) } // should always use constants as argument to ensure all computations are performed at compile time -static inline void delay_for_n_mem_clocks(const uint32_t clocks) +static inline void SECT(delay_for_n_mem_clocks)(const uint32_t clocks) { uint32_t afi_clocks; uint8_t inner; @@ -1145,7 +1145,7 @@ static inline void delay_for_n_mem_clocks(const uint32_t clocks) } // should always use constants as argument to ensure all computations are performed at compile time -static inline void delay_for_n_ns(const uint32_t nanoseconds) +static inline void SECT(delay_for_n_ns)(const uint32_t nanoseconds) { delay_for_n_mem_clocks((1000 * nanoseconds) / (1000000 / AFI_CLK_FREQ) * AFI_RATE_RATIO); } @@ -1161,7 +1161,7 @@ static void rw_mgr_rdimm_initialize(void) { } -static void rw_mgr_mem_initialize(void) +static void SECT(rw_mgr_mem_initialize)(void) { uint32_t r; @@ -1273,7 +1273,7 @@ static void rw_mgr_mem_dll_lock_wait(void) //USER At the end of calibration we have to program the user settings in, and //USER hand off the memory to the user. -static void rw_mgr_mem_handoff(void) +static void SECT(rw_mgr_mem_handoff)(void) { uint32_t r; @@ -1325,7 +1325,7 @@ static void rw_mgr_mem_handoff(void) } //USER performs a guaranteed read on the patterns we are going to use during a read test to ensure memory works -static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, uint32_t group, +static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns)(uint32_t rank_bgn, uint32_t group, uint32_t num_tries, t_btfld * bit_chk, uint32_t all_ranks) { @@ -1387,7 +1387,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn, uint3 return (*bit_chk == param->read_correct_mask); } -static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks(uint32_t group, +static uint32_t SECT(rw_mgr_mem_calibrate_read_test_patterns_all_ranks)(uint32_t group, uint32_t num_tries, t_btfld * bit_chk) { @@ -1410,7 +1410,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks(uint32_t group } //USER load up the patterns we are going to use during a read test -static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn, uint32_t all_ranks) +static void SECT(rw_mgr_mem_calibrate_read_load_patterns)(uint32_t rank_bgn, uint32_t all_ranks) { uint32_t r; uint32_t rank_end = @@ -1445,7 +1445,7 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn, uint32_t set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); } -static inline void rw_mgr_mem_calibrate_read_load_patterns_all_ranks(void) +static inline void SECT(rw_mgr_mem_calibrate_read_load_patterns_all_ranks)(void) { rw_mgr_mem_calibrate_read_load_patterns(0, 1); } @@ -1564,7 +1564,7 @@ static inline void rw_mgr_mem_calibrate_read_load_patterns_all_ranks(void) //USER try a read and see if it returns correct data back. has dummy reads inserted into the mix //USER used to align dqs enable. has more thorough checks than the regular read test. -static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group, +static uint32_t SECT(rw_mgr_mem_calibrate_read_test)(uint32_t rank_bgn, uint32_t group, uint32_t num_tries, uint32_t all_correct, t_btfld * bit_chk, uint32_t all_groups, uint32_t all_ranks) @@ -1651,7 +1651,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group } } -static inline uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group, uint32_t num_tries, +static inline uint32_t SECT(rw_mgr_mem_calibrate_read_test_all_ranks)(uint32_t group, uint32_t num_tries, uint32_t all_correct, t_btfld * bit_chk, uint32_t all_groups) @@ -1660,7 +1660,7 @@ static inline uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group, 1); } -static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t * v) +static void SECT(rw_mgr_incr_vfifo)(uint32_t grp, uint32_t * v) { //USER fiddle with FIFO if (HARD_PHY) { @@ -1691,7 +1691,7 @@ static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t * v) } //Used in quick cal to properly loop through the duplicated VFIFOs in AV QDRII/RLDRAM -static inline void rw_mgr_incr_vfifo_all(uint32_t grp, uint32_t * v) +static inline void SECT(rw_mgr_incr_vfifo_all)(uint32_t grp, uint32_t * v) { #if VFIFO_CONTROL_WIDTH_PER_DQS == 1 rw_mgr_incr_vfifo(grp, v); @@ -1706,7 +1706,7 @@ static inline void rw_mgr_incr_vfifo_all(uint32_t grp, uint32_t * v) #endif } -static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t * v) +static void SECT(rw_mgr_decr_vfifo)(uint32_t grp, uint32_t * v) { uint32_t i; @@ -1722,7 +1722,7 @@ static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t * v) // Navid's version -static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) +static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase)(uint32_t grp) { uint32_t i, d, v, p; uint32_t max_working_cnt; @@ -2415,7 +2415,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) #else // Val's original version -static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) +static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase)(uint32_t grp) { uint32_t i, j, v, d; uint32_t min_working_d, max_working_cnt; @@ -2532,7 +2532,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) #endif // Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different dq_in_delay values -static inline uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(uint32_t +static inline uint32_t SECT(rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay)(uint32_t write_group, uint32_t read_group, @@ -2584,7 +2584,7 @@ static inline uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_ #if NEWVERSION_RDDESKEW -static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t write_group, +static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint32_t write_group, uint32_t read_group, uint32_t test_bgn, uint32_t use_read_test, uint32_t update_fom) { @@ -2902,7 +2902,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr #else -static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t grp, +static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_center)(uint32_t rank_bgn, uint32_t grp, uint32_t test_bgn, uint32_t use_read_test) { uint32_t i, p, d; @@ -3037,7 +3037,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t gr #if NEWVERSION_GW //USER VFIFO Calibration -- Full Calibration -static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, uint32_t test_bgn) +static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t read_group, uint32_t test_bgn) { uint32_t p, d, rank_bgn, sr; uint32_t dtaps_per_ptap; @@ -3201,7 +3201,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, uint32_t test_bg #else //USER VFIFO Calibration -- Full Calibration -static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t g, uint32_t test_bgn) +static uint32_t SECT(rw_mgr_mem_calibrate_vfifo)(uint32_t g, uint32_t test_bgn) { uint32_t p, rank_bgn, sr; uint32_t grp_calibrated; @@ -3272,7 +3272,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t g, uint32_t test_bgn) #endif //USER VFIFO Calibration -- Read Deskew Calibration after write deskew -static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group, uint32_t test_bgn) +static uint32_t SECT(rw_mgr_mem_calibrate_vfifo_end)(uint32_t read_group, uint32_t test_bgn) { uint32_t rank_bgn, sr; uint32_t grp_calibrated; @@ -3323,7 +3323,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group, uint32_t tes //USER Calibrate LFIFO to find smallest read latency -static uint32_t rw_mgr_mem_calibrate_lfifo(void) +static uint32_t SECT(rw_mgr_mem_calibrate_lfifo)(void) { uint32_t found_one; t_btfld bit_chk; @@ -3381,7 +3381,7 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void) //USER two variants are provided. one that just tests a write pattern and another that //USER tests datamask functionality. -static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group, uint32_t test_dm) +static void SECT(rw_mgr_mem_calibrate_write_test_issue)(uint32_t group, uint32_t test_dm) { uint32_t mcc_instruction; uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) @@ -3486,7 +3486,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group, uint32_t test_ //USER Test writes, can check for a single bit pass or multiple bit pass -static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, uint32_t write_group, +static uint32_t SECT(rw_mgr_mem_calibrate_write_test)(uint32_t rank_bgn, uint32_t write_group, uint32_t use_dm, uint32_t all_correct, t_btfld * bit_chk, uint32_t all_ranks) { @@ -3552,7 +3552,7 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, uint32_t writ } } -static inline uint32_t rw_mgr_mem_calibrate_write_test_all_ranks(uint32_t write_group, +static inline uint32_t SECT(rw_mgr_mem_calibrate_write_test_all_ranks)(uint32_t write_group, uint32_t use_dm, uint32_t all_correct, t_btfld * bit_chk) @@ -3565,7 +3565,7 @@ static inline uint32_t rw_mgr_mem_calibrate_write_test_all_ranks(uint32_t write_ #if NEWVERSION_WL //USER Write Levelling -- Full Calibration -static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) +static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn) { uint32_t p, d; @@ -3805,7 +3805,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) #else //USER Write Levelling -- Full Calibration -static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) +static uint32_t SECT(rw_mgr_mem_calibrate_wlevel)(uint32_t g, uint32_t test_bgn) { uint32_t p, d; t_btfld bit_chk; @@ -3934,7 +3934,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) #if NEWVERSION_WRDESKEW -static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t write_group, +static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint32_t write_group, uint32_t test_bgn) { uint32_t i, p, min_index; @@ -4307,7 +4307,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w #else // !NEWVERSION_WRDESKEW -static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t write_group, +static uint32_t SECT(rw_mgr_mem_calibrate_writes_center)(uint32_t rank_bgn, uint32_t write_group, uint32_t test_bgn) { uint32_t i, p, d; @@ -4488,7 +4488,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w //USER calibrate the write operations -static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g, uint32_t test_bgn) +static uint32_t SECT(rw_mgr_mem_calibrate_writes)(uint32_t rank_bgn, uint32_t g, uint32_t test_bgn) { reg_file_set_stage(CAL_STAGE_WRITES); @@ -4509,7 +4509,7 @@ static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g, uint3 } //USER precharge all banks and activate row 0 in bank "000..." and bank "111..." -static void mem_precharge_and_activate(void) +static void SECT(mem_precharge_and_activate)(void) { uint32_t r; @@ -4540,7 +4540,7 @@ static void mem_precharge_and_activate(void) //USER Configure various memory related parameters. -static void mem_config(void) +static void SECT(mem_config)(void) { uint32_t rlat, wlat; uint32_t rw_wl_nop_cycles; @@ -4629,7 +4629,7 @@ static void mem_config(void) //USER Set VFIFO and LFIFO to instant-on settings in skip calibration mode -static void mem_skip_calibrate(void) +static void SECT(mem_skip_calibrate)(void) { uint32_t vfifo_offset; uint32_t i, j, r; @@ -4707,7 +4707,7 @@ static void mem_skip_calibrate(void) //USER Memory calibration entry point -static uint32_t mem_calibrate(void) +static uint32_t SECT(mem_calibrate)(void) { uint32_t i; uint32_t rank_bgn, sr; @@ -4914,7 +4914,7 @@ static uint32_t mem_calibrate(void) return 1; } -static uint32_t run_mem_calibrate(void) +static uint32_t SECT(run_mem_calibrate)(void) { uint32_t pass; @@ -5011,7 +5011,7 @@ static uint32_t run_mem_calibrate(void) } -static void hc_initialize_rom_data(void) +static void SECT(hc_initialize_rom_data)(void) { uint32_t i; @@ -5026,7 +5026,7 @@ static void hc_initialize_rom_data(void) } } -static void initialize_reg_file(void) +static void SECT(initialize_reg_file)(void) { // Initialize the register file with the correct data IOWR_32DIRECT(REG_FILE_SIGNATURE, 0, REG_FILE_INIT_SEQ_SIGNATURE); @@ -5038,7 +5038,7 @@ static void initialize_reg_file(void) IOWR_32DIRECT(REG_FILE_DEBUG2, 0, 0); } -static void initialize_hps_phy(void) +static void SECT(initialize_hps_phy)(void) { // These may need to be included also: // wrap_back_en (false) @@ -5131,7 +5131,7 @@ static void initialize_tracking(void) IOWR_32DIRECT(REG_FILE_TRK_RFSH, 0, concatenated_refresh); } -static int socfpga_mem_calibration(void) +static int SECT(socfpga_mem_calibration)(void) { param_t my_param; gbl_t my_gbl; diff --git a/arch/arm/mach-socfpga/include/mach/lowlevel.h b/arch/arm/mach-socfpga/include/mach/lowlevel.h index 01463bb877..03a2ea6435 100644 --- a/arch/arm/mach-socfpga/include/mach/lowlevel.h +++ b/arch/arm/mach-socfpga/include/mach/lowlevel.h @@ -13,7 +13,7 @@ #include <mach/pll_config.h> #include <mach/cyclone5-sequencer.c> -static void __noreturn start_socfpga_c5_common(uint32_t size, void *fdt_blob) +static noinline void SECT(start_socfpga_c5_common)(uint32_t size, void *fdt_blob) { void *fdt; @@ -32,7 +32,7 @@ static void __noreturn start_socfpga_c5_common(uint32_t size, void *fdt_blob) start_socfpga_c5_common(memory_size, __dtb_##fdt_name##_start); \ } -static noinline void start_socfpga_c5_xload_common(uint32_t size) +static noinline void SECT(start_socfpga_c5_xload_common)(uint32_t size) { struct socfpga_io_config io_config; int ret; diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 6233614e19..c9b5512c0a 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -64,11 +64,3 @@ config BFIN_BOOT_FLASH16 blackfin is strapped to boot from 16bit wide flash via boot ROM endchoice - -source common/Kconfig -source commands/Kconfig -source net/Kconfig -source drivers/Kconfig -source fs/Kconfig -source lib/Kconfig -source crypto/Kconfig diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 524375a81a..7c40991cab 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -353,11 +353,3 @@ config MIPS_OPTIMIZED_STRING_FUNCTIONS increase your binary size. endmenu - -source common/Kconfig -source commands/Kconfig -source net/Kconfig -source drivers/Kconfig -source fs/Kconfig -source lib/Kconfig -source crypto/Kconfig diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 3342e0eafd..6338dc174d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -12,7 +12,7 @@ endif CPPFLAGS += -D__MIPS__ -fno-strict-aliasing -fno-merge-constants cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ +cflags-y += -Wall -Wstrict-prototypes \ -Wno-uninitialized -Wno-format -Wno-main ifdef CONFIG_32BIT diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig index 199540ba74..c7c13a464b 100644 --- a/arch/nios2/Kconfig +++ b/arch/nios2/Kconfig @@ -27,11 +27,3 @@ config EARLY_PRINTF bool "Enable early printf functions" endmenu - -source common/Kconfig -source commands/Kconfig -source net/Kconfig -source drivers/Kconfig -source fs/Kconfig -source lib/Kconfig -source crypto/Kconfig diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index 2a8abf0ff8..32d23029d8 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -27,11 +27,3 @@ config GENERIC select OPENRISC endchoice - -source common/Kconfig -source commands/Kconfig -source net/Kconfig -source drivers/Kconfig -source fs/Kconfig -source lib/Kconfig -source crypto/Kconfig diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index 97e6c00689..7a45ced7cd 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -20,10 +20,3 @@ endchoice source arch/ppc/mach-mpc5xxx/Kconfig source arch/ppc/mach-mpc85xx/Kconfig -source common/Kconfig -source commands/Kconfig -source net/Kconfig -source drivers/Kconfig -source fs/Kconfig -source lib/Kconfig -source crypto/Kconfig diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 3f1cefb837..5227cb624f 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -15,11 +15,3 @@ config LINUX config ARCH_LINUX bool - -source common/Kconfig -source commands/Kconfig -source net/Kconfig -source drivers/Kconfig -source fs/Kconfig -source lib/Kconfig -source crypto/Kconfig diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 52ccf4894f..3f91585d02 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -97,11 +97,3 @@ endchoice source arch/x86/boot/Kconfig source arch/x86/mach-i386/Kconfig - -source common/Kconfig -source commands/Kconfig -source net/Kconfig -source drivers/Kconfig -source fs/Kconfig -source lib/Kconfig -source crypto/Kconfig |