diff options
Diffstat (limited to 'arch')
62 files changed, 973 insertions, 180 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3eada5b80f..af4cb59496 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -135,7 +135,15 @@ config CMD_ARM_CPUINFO default y help Say yes here to get a cpuinfo command to show some - information about the cp15 registers + CPU information using the cp15 registers + +config CMD_ARM_MMUINFO + bool "mmuinfo command" + depends on CPU_V7 + default n + help + Say yes here to get a mmuinfo command to show some + MMU and cache information using the cp15 registers config CPU_V7_DCACHE_SKIP bool "Skip DCache Invalidate" diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c index 38f28be9c5..b40713d33b 100644 --- a/arch/arm/boards/chumby_falconwing/falconwing.c +++ b/arch/arm/boards/chumby_falconwing/falconwing.c @@ -316,7 +316,7 @@ static void falconwing_init_usb(void) /* bring USB hub out of reset */ gpio_direction_output(GPIO_USB_HUB_RESET, 1); - imx_usb_phy_enable(); + imx23_usb_phy_enable(); add_generic_usb_ehci_device(-1, IMX_USB_BASE, NULL); } diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c index 3cc7a72252..35c114dad0 100644 --- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c +++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c @@ -53,6 +53,11 @@ struct imx_nand_platform_data nand_info = { }; static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, /* FEC */ MX51_PAD_DISP2_DAT1__FEC_RX_ER, MX51_PAD_DISP2_DAT15__FEC_TDATA0, @@ -141,12 +146,8 @@ static int eukrea_cpuimx51_console_init(void) imx51_init_lowlevel(800); - writel(0, 0x73fa8228); - writel(0, 0x73fa822c); - writel(0, 0x73fa8230); - writel(0, 0x73fa8234); - imx51_add_uart0(); + return 0; } diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c index 9168ed8823..1283e1769a 100644 --- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c +++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c @@ -22,17 +22,18 @@ #include <init.h> #include <mci.h> #include <io.h> +#include <net.h> #include <mach/clock.h> #include <mach/imx-regs.h> #include <mach/iomux-imx28.h> #include <mach/mci.h> +#include <mach/fb.h> +#include <mach/ocotp.h> #include <asm/armlinux.h> #include <asm/mmu.h> -#include <mach/fb.h> - #include <generated/mach-types.h> #define MX28EVK_FEC_PHY_RESET_GPIO 141 @@ -118,6 +119,27 @@ static struct mxs_mci_platform_data mci_pdata = { }; /* fec */ +static void mx28_evk_get_ethaddr(void) +{ + u8 mac_ocotp[3], mac[6]; + int ret; + + ret = mxs_ocotp_read(mac_ocotp, 3, 0); + if (ret != 3) { + pr_err("Reading MAC from OCOTP failed!\n"); + return; + } + + mac[0] = 0x00; + mac[1] = 0x04; + mac[2] = 0x9f; + mac[3] = mac_ocotp[2]; + mac[4] = mac_ocotp[1]; + mac[5] = mac_ocotp[0]; + + eth_register_ethaddr(0, mac); +} + static void __init mx28_evk_fec_reset(void) { mdelay(1); @@ -208,6 +230,10 @@ static int mx28_evk_devices_init(void) add_generic_device("stmfb", 0, NULL, IMX_FB_BASE, 4096, IORESOURCE_MEM, &mx28_evk_fb_pdata); + add_generic_device("ocotp", 0, NULL, IMX_OCOTP_BASE, 0, + IORESOURCE_MEM, NULL); + mx28_evk_get_ethaddr(); /* must be after registering ocotp */ + imx_enable_enetclk(); mx28_evk_fec_reset(); add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0, diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c index 0bb2ffed29..3a568d051f 100644 --- a/arch/arm/boards/freescale-mx51-pdk/board.c +++ b/arch/arm/boards/freescale-mx51-pdk/board.c @@ -48,6 +48,12 @@ static struct fec_platform_data fec_info = { }; static iomux_v3_cfg_t f3s_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + /* FEC */ MX51_PAD_EIM_EB2__FEC_MDIO, MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_EIM_CS2__FEC_RDATA2, @@ -246,6 +252,7 @@ static int f3s_devices_init(void) imx51_iim_register_fec_ethaddr(); imx51_add_fec(&fec_info); imx51_add_mmc0(NULL); + imx51_add_mmc1(NULL); armlinux_set_bootparams((void *)0x90000100); armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); @@ -268,12 +275,8 @@ static int f3s_console_init(void) { mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); - writel(0, 0x73fa8228); - writel(0, 0x73fa822c); - writel(0, 0x73fa8230); - writel(0, 0x73fa8234); - imx51_add_uart0(); + return 0; } diff --git a/arch/arm/configs/at91sam9m10g45ek_defconfig b/arch/arm/configs/at91sam9m10g45ek_defconfig index b72e964d7f..e22f80a9d7 100644 --- a/arch/arm/configs/at91sam9m10g45ek_defconfig +++ b/arch/arm/configs/at91sam9m10g45ek_defconfig @@ -1,5 +1,4 @@ CONFIG_ARCH_AT91SAM9G45=y -CONFIG_MACH_AT91SAM9M10G45EK=y CONFIG_AEABI=y # CONFIG_CMD_ARM_CPUINFO is not set CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y @@ -75,3 +74,4 @@ CONFIG_LED_TRIGGERS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/eukrea_cpuimx25_defconfig b/arch/arm/configs/eukrea_cpuimx25_defconfig index 94ae6700e3..f7207e8b89 100644 --- a/arch/arm/configs/eukrea_cpuimx25_defconfig +++ b/arch/arm/configs/eukrea_cpuimx25_defconfig @@ -8,6 +8,7 @@ CONFIG_MMU=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_MALLOC_SIZE=0x800000 CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y CONFIG_LONGHELP=y CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig index a888765d99..880beb6f19 100644 --- a/arch/arm/configs/eukrea_cpuimx35_defconfig +++ b/arch/arm/configs/eukrea_cpuimx35_defconfig @@ -9,6 +9,7 @@ CONFIG_MMU=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_MALLOC_SIZE=0x800000 CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y CONFIG_LONGHELP=y CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y diff --git a/arch/arm/configs/eukrea_cpuimx51_defconfig b/arch/arm/configs/eukrea_cpuimx51_defconfig index f6fd7bcb37..7261796b33 100644 --- a/arch/arm/configs/eukrea_cpuimx51_defconfig +++ b/arch/arm/configs/eukrea_cpuimx51_defconfig @@ -7,6 +7,7 @@ CONFIG_MMU=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_MALLOC_SIZE=0x2000000 CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y CONFIG_LONGHELP=y CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y diff --git a/arch/arm/configs/usb_a9260_defconfig b/arch/arm/configs/usb_a9260_defconfig index 85e7878207..a9574c497e 100644 --- a/arch/arm/configs/usb_a9260_defconfig +++ b/arch/arm/configs/usb_a9260_defconfig @@ -6,6 +6,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_MMU=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y CONFIG_PROMPT="USB-9G20:" CONFIG_LONGHELP=y CONFIG_GLOB=y diff --git a/arch/arm/configs/usb_a9263_128mib_defconfig b/arch/arm/configs/usb_a9263_128mib_defconfig index 23bc3d7fb7..d31057fcdb 100644 --- a/arch/arm/configs/usb_a9263_128mib_defconfig +++ b/arch/arm/configs/usb_a9263_128mib_defconfig @@ -1,12 +1,13 @@ CONFIG_ARCH_AT91SAM9263=y CONFIG_MACH_USB_A9263=y +CONFIG_AT91_HAVE_SRAM_128M=y CONFIG_AEABI=y # CONFIG_CMD_ARM_CPUINFO is not set -CONFIG_AT91_HAVE_SRAM_128M=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_MMU=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y CONFIG_PROMPT="USB-9263:" CONFIG_LONGHELP=y CONFIG_GLOB=y diff --git a/arch/arm/configs/usb_a9263_defconfig b/arch/arm/configs/usb_a9263_defconfig index 96ea3e1879..b57c300167 100644 --- a/arch/arm/configs/usb_a9263_defconfig +++ b/arch/arm/configs/usb_a9263_defconfig @@ -6,6 +6,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_MMU=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y CONFIG_PROMPT="USB-9263:" CONFIG_LONGHELP=y CONFIG_GLOB=y @@ -22,7 +23,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/usb-a926x/env" CONFIG_CMD_EDIT=y CONFIG_CMD_SLEEP=y CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y CONFIG_CMD_EXPORT=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_READLINE=y diff --git a/arch/arm/configs/usb_a9g20_128mib_defconfig b/arch/arm/configs/usb_a9g20_128mib_defconfig index c25d7dec57..6b02342f9f 100644 --- a/arch/arm/configs/usb_a9g20_128mib_defconfig +++ b/arch/arm/configs/usb_a9g20_128mib_defconfig @@ -1,12 +1,13 @@ CONFIG_ARCH_AT91SAM9G20=y CONFIG_MACH_USB_A9G20=y +CONFIG_AT91_HAVE_SRAM_128M=y CONFIG_AEABI=y # CONFIG_CMD_ARM_CPUINFO is not set -CONFIG_AT91_HAVE_SRAM_128M=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_MMU=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y CONFIG_PROMPT="USB-9G20:" CONFIG_LONGHELP=y CONFIG_GLOB=y diff --git a/arch/arm/configs/usb_a9g20_defconfig b/arch/arm/configs/usb_a9g20_defconfig index d645adb618..30bf380458 100644 --- a/arch/arm/configs/usb_a9g20_defconfig +++ b/arch/arm/configs/usb_a9g20_defconfig @@ -6,6 +6,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_MMU=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y CONFIG_PROMPT="USB-9G20:" CONFIG_LONGHELP=y CONFIG_GLOB=y diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index e30ae1cc1f..93a34a9ff1 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -7,6 +7,7 @@ obj-y += start.o # Any variants can be called as start-armxyz.S # obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o +obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o obj-$(CONFIG_MMU) += mmu.o obj-$(CONFIG_CPU_32v4T) += cache-armv4.o obj-$(CONFIG_CPU_32v5) += cache-armv5.o diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index c19f9311cd..55b07a46d1 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -299,11 +299,9 @@ void *dma_alloc_coherent(size_t size) size = PAGE_ALIGN(size); ret = xmemalign(4096, size); -#ifdef CONFIG_MMU dma_inv_range((unsigned long)ret, (unsigned long)ret + size); remap_range(ret, size, PTE_FLAGS_UNCACHED); -#endif return ret; } @@ -320,9 +318,7 @@ void *phys_to_virt(unsigned long phys) void dma_free_coherent(void *mem, size_t size) { -#ifdef CONFIG_MMU remap_range(mem, size, PTE_FLAGS_CACHED); -#endif free(mem); } diff --git a/arch/arm/cpu/mmuinfo.c b/arch/arm/cpu/mmuinfo.c new file mode 100644 index 0000000000..6bea34ed50 --- /dev/null +++ b/arch/arm/cpu/mmuinfo.c @@ -0,0 +1,111 @@ +/* + * mmuinfo.c - Show MMU/cache information from cp15 registers + * + * Copyright (c) Jan Luebbe <j.luebbe@pengutronix.de>, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +static char *inner_attr[] = { + "0b000 Non-cacheable", + "0b001 Strongly-ordered", + "0b010 (reserved)", + "0b011 Device", + "0b100 (reserved)", + "0b101 Write-Back, Write-Allocate", + "0b110 Write-Through", + "0b111 Write-Back, no Write-Allocate", +}; + +static char *outer_attr[] = { + "0b00 Non-cacheable", + "0b01 Write-Back, Write-Allocate", + "0b10 Write-Through, no Write-Allocate", + "0b11 Write-Back, no Write-Allocate", +}; + +static void decode_par(unsigned long par) +{ + printf(" Physical Address [31:12]: 0x%08lx\n", par & 0xFFFFF000); + printf(" Reserved [11]: 0x%lx\n", (par >> 11) & 0x1); + printf(" Not Outer Shareable [10]: 0x%lx\n", (par >> 10) & 0x1); + printf(" Non-Secure [9]: 0x%lx\n", (par >> 9) & 0x1); + printf(" Impl. def. [8]: 0x%lx\n", (par >> 8) & 0x1); + printf(" Shareable [7]: 0x%lx\n", (par >> 7) & 0x1); + printf(" Inner mem. attr. [6:4]: 0x%lx (%s)\n", (par >> 4) & 0x7, + inner_attr[(par >> 4) & 0x7]); + printf(" Outer mem. attr. [3:2]: 0x%lx (%s)\n", (par >> 2) & 0x3, + outer_attr[(par >> 2) & 0x3]); + printf(" SuperSection [1]: 0x%lx\n", (par >> 1) & 0x1); + printf(" Failure [0]: 0x%lx\n", (par >> 0) & 0x1); +} + +static int do_mmuinfo(int argc, char *argv[]) +{ + unsigned long addr = 0, priv_read, priv_write; + + if (argc < 2) + return COMMAND_ERROR_USAGE; + + addr = strtoul_suffix(argv[1], NULL, 0); + + __asm__ __volatile__( + "mcr p15, 0, %0, c7, c8, 0 @ write VA to PA translation (priv read)\n" + : + : "r" (addr) + : "memory"); + + __asm__ __volatile__( + "mrc p15, 0, %0, c7, c4, 0 @ read PAR\n" + : "=r" (priv_read) + : + : "memory"); + + __asm__ __volatile__( + "mcr p15, 0, %0, c7, c8, 1 @ write VA to PA translation (priv write)\n" + : + : "r" (addr) + : "memory"); + + __asm__ __volatile__( + "mrc p15, 0, %0, c7, c4, 0 @ read PAR\n" + : "=r" (priv_write) + : + : "memory"); + + printf("PAR result for 0x%08lx: \n", addr); + printf(" privileged read: 0x%08lx\n", priv_read); + decode_par(priv_read); + printf(" privileged write: 0x%08lx\n", priv_write); + decode_par(priv_write); + + return 0; +} + +BAREBOX_CMD_HELP_START(mmuinfo) +BAREBOX_CMD_HELP_USAGE("mmuinfo <address>\n") +BAREBOX_CMD_HELP_SHORT("Show MMU/cache information for an address.\n") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(mmuinfo) + .cmd = do_mmuinfo, + .usage = "mmuinfo <address>", + BAREBOX_CMD_HELP(cmd_mmuinfo_help) +BAREBOX_CMD_END diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h new file mode 100644 index 0000000000..cb9cd1b4ea --- /dev/null +++ b/arch/arm/include/asm/dma.h @@ -0,0 +1,8 @@ +/* + * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#include <asm/mmu.h> diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index f5ae7a823a..a66da8c0a8 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h @@ -1,9 +1,12 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H -#include <asm/pgtable.h> -#include <malloc.h> +#include <common.h> #include <errno.h> +#include <malloc.h> +#include <xfuncs.h> + +#include <asm/pgtable.h> #define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT) #define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED) @@ -23,6 +26,12 @@ static inline void setup_dma_coherent(unsigned long offset) { } +#define dma_alloc dma_alloc +static inline void *dma_alloc(size_t size) +{ + return xmemalign(64, ALIGN(size, 64)); +} + #ifdef CONFIG_MMU void *dma_alloc_coherent(size_t size); void dma_free_coherent(void *mem, size_t size); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 564e2fe92d..3d84d63e43 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -517,7 +517,7 @@ menu "i.MX specific settings " config IMX_CLKO bool "clko command" - depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX35 || ARCH_IMX25 + depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX35 || ARCH_IMX25 || ARCH_IMX51 help The i.MX SoCs have a Pin which can output different reference frequencies. Say y here if you want to have the clko command which lets you select the diff --git a/arch/arm/mach-imx/clko.c b/arch/arm/mach-imx/clko.c index 0e4fbcc57f..aeafaa9c41 100644 --- a/arch/arm/mach-imx/clko.c +++ b/arch/arm/mach-imx/clko.c @@ -6,15 +6,18 @@ static int do_clko(int argc, char *argv[]) { - int opt, div = 0, src = -2, ret; + int opt, div = 0, src = -2, num = 1, ret; - while((opt = getopt(argc, argv, "d:s:")) > 0) { + while((opt = getopt(argc, argv, "n:d:s:")) > 0) { switch(opt) { + case 'n': + num = simple_strtoul(optarg, NULL, 0); + break; case 'd': div = simple_strtoul(optarg, NULL, 0); break; case 's': - src = simple_strtoul(optarg, NULL, 0); + src = simple_strtol(optarg, NULL, 0); break; } } @@ -23,17 +26,19 @@ static int do_clko(int argc, char *argv[]) return COMMAND_ERROR_USAGE; if (src == -1) { - imx_clko_set_src(-1); + imx_clko_set_src(num, -1); return 0; } if (src != -2) - imx_clko_set_src(src); + imx_clko_set_src(num, src); if (div != 0) { - ret = imx_clko_set_div(div); - if (ret != div) - printf("limited divider to %d\n", ret); + ret = imx_clko_set_div(num, div); + if (ret < 0) + printf("CLKO-line %i not supported.\n", num); + else if (ret != div) + printf("Divider limited to %d.\n", ret); } return 0; @@ -42,7 +47,8 @@ static int do_clko(int argc, char *argv[]) static __maybe_unused char cmd_clko_help[] = "Usage: clko [OPTION]...\n" "Route different signals to the i.MX clko pin\n" -" -d <div> Divider\n" +" -n <num> Number of CLKO-line (Default 1)\n" +" -d <div> Divider\n" " -s <source> Clock select. See Ref. Manual for valid sources. Use -1\n" " for disabling clock output\n"; diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index 4f5895c2a5..4e77ece7f3 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -38,7 +38,7 @@ #include <io.h> #define GPT(x) __REG(IMX_TIM1_BASE + (x)) -#define timer_base (IMX_TIM1_BASE) +#define timer_base IOMEM(IMX_TIM1_BASE) static uint64_t imx_clocksource_read(void) { @@ -120,15 +120,17 @@ core_initcall(clocksource_init); */ void __noreturn reset_cpu (unsigned long addr) { + void __iomem *wdt = IOMEM(IMX_WDT_BASE); + /* Disable watchdog and set Time-Out field to 0 */ - writew(0x0, IMX_WDT_BASE + WDOG_WCR); + writew(0x0, wdt + WDOG_WCR); /* Write Service Sequence */ - writew(0x5555, IMX_WDT_BASE + WDOG_WSR); - writew(0xaaaa, IMX_WDT_BASE + WDOG_WSR); + writew(0x5555, wdt + WDOG_WSR); + writew(0xaaaa, wdt + WDOG_WSR); /* Enable watchdog */ - writew(WDOG_WCR_WDE, IMX_WDT_BASE + WDOG_WCR); + writew(WDOG_WCR_WDE, wdt + WDOG_WCR); while (1); /*NOTREACHED*/ diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c index f2ace8aa0f..0da8ea062b 100644 --- a/arch/arm/mach-imx/iim.c +++ b/arch/arm/mach-imx/iim.c @@ -84,7 +84,7 @@ static int do_fuse_sense(void __iomem *reg_base, unsigned int bank, } static ssize_t imx_iim_cdev_read(struct cdev *cdev, void *buf, size_t count, - ulong offset, ulong flags) + loff_t offset, ulong flags) { ulong size, i; struct iim_priv *priv = cdev->priv; @@ -94,7 +94,7 @@ static ssize_t imx_iim_cdev_read(struct cdev *cdev, void *buf, size_t count, if ((sense_param = dev_get_param(cdev->dev, "explicit_sense_enable"))) explicit_sense = simple_strtoul(sense_param, NULL, 0); - size = min((ulong)count, priv->banksize - offset); + size = min((loff_t)count, priv->banksize - offset); if (explicit_sense) { for (i = 0; i < size; i++) { int row_val; @@ -176,7 +176,7 @@ out: #endif /* CONFIG_IMX_IIM_FUSE_BLOW */ static ssize_t imx_iim_cdev_write(struct cdev *cdev, const void *buf, size_t count, - ulong offset, ulong flags) + loff_t offset, ulong flags) { ulong size, i; struct iim_priv *priv = cdev->priv; @@ -186,7 +186,7 @@ static ssize_t imx_iim_cdev_write(struct cdev *cdev, const void *buf, size_t cou if ((write_param = dev_get_param(cdev->dev, "permanent_write_enable"))) blow_enable = simple_strtoul(write_param, NULL, 0); - size = min((ulong)count, priv->banksize - offset); + size = min((loff_t)count, priv->banksize - offset); #ifdef CONFIG_IMX_IIM_FUSE_BLOW if (blow_enable) { for (i = 0; i < size; i++) { diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h index 10821782fe..050b7f8921 100644 --- a/arch/arm/mach-imx/include/mach/clock.h +++ b/arch/arm/mach-imx/include/mach/clock.h @@ -30,9 +30,11 @@ ulong imx_get_lcdclk(void); ulong imx_get_i2cclk(void); ulong imx_get_mmcclk(void); ulong imx_get_cspiclk(void); +ulong imx_get_ipgclk(void); +ulong imx_get_usbclk(void); -int imx_clko_set_div(int div); -void imx_clko_set_src(int src); +int imx_clko_set_div(int num, int div); +void imx_clko_set_src(int num, int src); void imx_dump_clocks(void); diff --git a/arch/arm/mach-imx/speed-imx21.c b/arch/arm/mach-imx/speed-imx21.c index 6ab1dca3f3..4729583693 100644 --- a/arch/arm/mach-imx/speed-imx21.c +++ b/arch/arm/mach-imx/speed-imx21.c @@ -16,6 +16,7 @@ */ #include <common.h> +#include <asm-generic/errno.h> #include <mach/imx-regs.h> #include <mach/generic.h> #include <mach/clock.h> @@ -162,9 +163,13 @@ void imx_dump_clocks(void) * Returns the new divider (which may be smaller * than the desired one) */ -int imx_clko_set_div(int div) +int imx_clko_set_div(int num, int div) { ulong pcdr; + + if (num != 1) + return -ENODEV; + div--; div &= 0x7; @@ -178,11 +183,11 @@ int imx_clko_set_div(int div) /* * Set the clock source for the CLKO pin */ -void imx_clko_set_src(int src) +void imx_clko_set_src(int num, int src) { unsigned long ccsr; - if (src < 0) { + if (src < 0 || num != 1) { return; } diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c index f6dcacb71b..ed14113f76 100644 --- a/arch/arm/mach-imx/speed-imx25.c +++ b/arch/arm/mach-imx/speed-imx25.c @@ -1,4 +1,5 @@ #include <common.h> +#include <asm-generic/errno.h> #include <mach/imx-regs.h> #include <io.h> #include <mach/clock.h> @@ -111,10 +112,13 @@ void imx_dump_clocks(void) * the new divider (which may be smaller * than the desired one) */ -int imx_clko_set_div(int div) +int imx_clko_set_div(int num, int div) { unsigned long mcr = readl(IMX_CCM_BASE + 0x64); + if (num != 1) + return -ENODEV; + div -= 1; div &= 0x3f; @@ -129,10 +133,13 @@ int imx_clko_set_div(int div) /* * Set the clock source for the CLKO pin */ -void imx_clko_set_src(int src) +void imx_clko_set_src(int num, int src) { unsigned long mcr = readl(IMX_CCM_BASE + 0x64); + if (num != 1) + return; + if (src < 0) { mcr &= ~(1 << 30); writel(mcr, IMX_CCM_BASE + 0x64); diff --git a/arch/arm/mach-imx/speed-imx27.c b/arch/arm/mach-imx/speed-imx27.c index aba50976f6..644fd0462a 100644 --- a/arch/arm/mach-imx/speed-imx27.c +++ b/arch/arm/mach-imx/speed-imx27.c @@ -16,6 +16,7 @@ */ #include <common.h> +#include <asm-generic/errno.h> #include <mach/imx-regs.h> #include <mach/generic.h> #include <mach/clock.h> @@ -189,9 +190,13 @@ void imx_dump_clocks(void) * the new divider (which may be smaller * than the desired one) */ -int imx_clko_set_div(int div) +int imx_clko_set_div(int num, int div) { ulong pcdr; + + if (num != 1) + return -ENODEV; + div--; div &= 0x7; @@ -205,10 +210,13 @@ int imx_clko_set_div(int div) /* * Set the clock source for the CLKO pin */ -void imx_clko_set_src(int src) +void imx_clko_set_src(int num, int src) { unsigned long ccsr; + if (num != 1) + return; + if (src < 0) { PCDR0 &= ~(1 << 25); return; diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c index 1e1c39ff82..684dc14262 100644 --- a/arch/arm/mach-imx/speed-imx35.c +++ b/arch/arm/mach-imx/speed-imx35.c @@ -16,6 +16,7 @@ */ #include <common.h> +#include <asm-generic/errno.h> #include <mach/imx-regs.h> #include <io.h> #include <mach/clock.h> @@ -84,7 +85,7 @@ unsigned long imx_get_ahbclk(void) return fref / aad->ahb; } -static unsigned long imx_get_ipgclk(void) +unsigned long imx_get_ipgclk(void) { ulong clk = imx_get_ahbclk(); @@ -203,10 +204,13 @@ void imx_dump_clocks(void) * the new divider (which may be smaller * than the desired one) */ -int imx_clko_set_div(int div) +int imx_clko_set_div(int num, int div) { unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR); + if (num != 1) + return -ENODEV; + div -= 1; div &= 0x3f; @@ -221,10 +225,13 @@ int imx_clko_set_div(int div) /* * Set the clock source for the CLKO pin */ -void imx_clko_set_src(int src) +void imx_clko_set_src(int num, int src) { unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR); + if (num != 1) + return; + if (src < 0) { cosr &= ~(1 << 5); writel(cosr, IMX_CCM_BASE + CCM_COSR); diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c index 8d1ecf3e40..87fbc75313 100644 --- a/arch/arm/mach-imx/speed-imx51.c +++ b/arch/arm/mach-imx/speed-imx51.c @@ -1,12 +1,19 @@ #include <common.h> #include <io.h> #include <asm-generic/div64.h> +#include <asm-generic/errno.h> #include <mach/imx51-regs.h> +#include <mach/clock.h> #include <mach/clock-imx51_53.h> static u32 ccm_readl(u32 ofs) { - return readl(MX51_CCM_BASE_ADDR + ofs); + return readl(IOMEM(MX51_CCM_BASE_ADDR) + ofs); +} + +static void ccm_writel(u32 val, u32 ofs) +{ + writel(val, MX51_CCM_BASE_ADDR + ofs); } static unsigned long ckil_get_rate(void) @@ -142,7 +149,7 @@ unsigned long imx_get_uartclk(void) return parent_rate / (prediv * podf); } -static unsigned long imx_get_ahbclk(void) +unsigned long imx_get_ahbclk(void) { u32 reg, div; @@ -221,6 +228,70 @@ unsigned long imx_get_usbclk(void) return rate / (prediv * podf); } +/* + * Set the divider of the CLKO pin. Returns + * the new divider (which may be smaller + * than the desired one) + */ +int imx_clko_set_div(int num, int div) +{ + u32 ccosr = ccm_readl(MX5_CCM_CCOSR); + + div--; + + switch (num) { + case 1: + div &= 0x7; + ccosr &= ~(0x7 << 4); + ccosr |= div << 4; + ccm_writel(ccosr, MX5_CCM_CCOSR); + break; + case 2: + div &= 0x7; + ccosr &= ~(0x7 << 21); + ccosr |= div << 21; + ccm_writel(ccosr, MX5_CCM_CCOSR); + break; + default: + return -ENODEV; + } + + return div + 1; +} + +/* + * Set the clock source for the CLKO pin + */ +void imx_clko_set_src(int num, int src) +{ + u32 ccosr = ccm_readl(MX5_CCM_CCOSR); + + switch (num) { + case 1: + if (src < 0) { + ccosr &= ~(1 << 7); + break; + } + ccosr &= ~0xf; + ccosr |= src & 0xf; + ccosr |= 1 << 7; + break; + case 2: + if (src < 0) { + ccosr &= ~(1 << 24); + break; + } + ccosr &= ~(0x1f << 16); + ccosr |= (src & 0x1f) << 16; + ccosr |= 1 << 24; + break; + default: + return; + } + + ccm_writel(ccosr, MX5_CCM_CCOSR); +} + void imx_dump_clocks(void) { printf("pll1: %ld\n", pll1_main_get_rate()); diff --git a/arch/arm/mach-imx/speed-imx53.c b/arch/arm/mach-imx/speed-imx53.c index 634341e738..653dae33b6 100644 --- a/arch/arm/mach-imx/speed-imx53.c +++ b/arch/arm/mach-imx/speed-imx53.c @@ -2,6 +2,7 @@ #include <io.h> #include <asm-generic/div64.h> #include <mach/imx-regs.h> +#include <mach/clock.h> #include "mach/clock-imx51_53.h" static u32 ccm_readl(u32 ofs) @@ -139,7 +140,7 @@ unsigned long imx_get_uartclk(void) return parent_rate / (prediv * podf); } -static unsigned long imx_get_ahbclk(void) +unsigned long imx_get_ahbclk(void) { u32 reg, div; diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 3348a3cef7..9ce7c7a1bd 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -61,6 +61,7 @@ config MACH_TX28 config MACH_MX28EVK bool "mx28-evk" + select MXS_OCOTP help Say Y here if you are using the Freescale i.MX28-EVK board @@ -80,6 +81,17 @@ config MXS_OCOTP internal view). Don't use register offsets here, the SET, CLR and TGL registers are not mapped! +config MXS_OCOTP_WRITABLE + bool "OCOTP write support" + depends on MXS_OCOTP + help + Enable this option to add writing to OCOTP. + Warning: blown bits can not be unblown. Use with care. + + Before being actually able to blow the bits, you need to explicitely + enable writing: + ocotp0.permanent_write_enable=1 + endmenu menu "Board specific settings " diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 172d928128..9a42a5f176 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -1,5 +1,5 @@ -obj-y += imx.o iomux-imx.o reset-imx.o +obj-y += imx.o iomux-imx.o power.o obj-$(CONFIG_DRIVER_VIDEO_STM) += imx_lcd_clk.o -obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o clocksource-imx23.o usb.o -obj-$(CONFIG_ARCH_IMX28) += speed-imx28.o clocksource-imx28.o +obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o clocksource-imx23.o usb-imx23.o soc-imx23.o +obj-$(CONFIG_ARCH_IMX28) += speed-imx28.o clocksource-imx28.o usb-imx28.o soc-imx28.o obj-$(CONFIG_MXS_OCOTP) += ocotp.o diff --git a/arch/arm/mach-mxs/include/mach/clock-imx23.h b/arch/arm/mach-mxs/include/mach/clock-imx23.h index 723f343566..4f20e09d3d 100644 --- a/arch/arm/mach-mxs/include/mach/clock-imx23.h +++ b/arch/arm/mach-mxs/include/mach/clock-imx23.h @@ -18,6 +18,7 @@ unsigned imx_get_emiclk(void); unsigned imx_get_ioclk(void); unsigned imx_get_armclk(void); unsigned imx_get_hclk(void); +unsigned imx_set_hclk(unsigned); unsigned imx_get_xclk(void); unsigned imx_get_sspclk(unsigned); unsigned imx_set_sspclk(unsigned, unsigned, int); diff --git a/arch/arm/mach-mxs/include/mach/clock-imx28.h b/arch/arm/mach-mxs/include/mach/clock-imx28.h index 45fb043ac4..613c97b916 100644 --- a/arch/arm/mach-mxs/include/mach/clock-imx28.h +++ b/arch/arm/mach-mxs/include/mach/clock-imx28.h @@ -18,6 +18,7 @@ unsigned imx_get_emiclk(void); unsigned imx_get_ioclk(unsigned); unsigned imx_get_armclk(void); unsigned imx_get_hclk(void); +unsigned imx_set_hclk(unsigned); unsigned imx_get_xclk(void); unsigned imx_get_sspclk(unsigned); unsigned imx_set_sspclk(unsigned, unsigned, int); diff --git a/arch/arm/mach-mxs/include/mach/imx28-regs.h b/arch/arm/mach-mxs/include/mach/imx28-regs.h index 9a2052c159..900990a381 100644 --- a/arch/arm/mach-mxs/include/mach/imx28-regs.h +++ b/arch/arm/mach-mxs/include/mach/imx28-regs.h @@ -29,9 +29,11 @@ #define IMX_SSP2_BASE 0x80014000 #define IMX_SSP3_BASE 0x80016000 #define IMX_IOMUXC_BASE 0x80018000 +#define IMX_DIGCTL_BASE 0x8001c000 #define IMX_OCOTP_BASE 0x8002c000 #define IMX_FB_BASE 0x80030000 #define IMX_CCM_BASE 0x80040000 +#define IMX_POWER_BASE 0x80044000 #define IMX_WDT_BASE 0x80056000 #define IMX_I2C0_BASE 0x80058000 #define IMX_I2C1_BASE 0x8005a000 @@ -42,6 +44,9 @@ #define IMX_UART3_BASE 0x80070000 #define IMX_UART4_BASE 0x80072000 #define IMX_DBGUART_BASE 0x80074000 +#define IMX_USBPHY0_BASE 0x8007c000 +#define IMX_USBPHY1_BASE 0x8007e000 +#define IMX_USB_BASE 0x80080000 #define IMX_FEC0_BASE 0x800F0000 #define IMX_FEC1_BASE 0x800F4000 diff --git a/arch/arm/mach-mxs/include/mach/power.h b/arch/arm/mach-mxs/include/mach/power.h new file mode 100644 index 0000000000..f429b3c31c --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/power.h @@ -0,0 +1,8 @@ +#ifndef __MACH_POWER_H +#define __MACH_POWER_H + +void imx_power_prepare_usbphy(void); +int imx_get_vddio(void); +int imx_set_vddio(int); + +#endif /* __MACH_POWER_H */ diff --git a/arch/arm/mach-mxs/include/mach/usb.h b/arch/arm/mach-mxs/include/mach/usb.h index af7d885cb3..2d31b0d0f2 100644 --- a/arch/arm/mach-mxs/include/mach/usb.h +++ b/arch/arm/mach-mxs/include/mach/usb.h @@ -1,6 +1,9 @@ #ifndef __MACH_USB_H #define __MACH_USB_H -int imx_usb_phy_enable(void); +int imx23_usb_phy_enable(void); + +int imx28_usb_phy0_enable(void); +int imx28_usb_phy1_enable(void); #endif /* __MACH_USB_H */ diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c index 38f9ffde16..78244028b9 100644 --- a/arch/arm/mach-mxs/ocotp.c +++ b/arch/arm/mach-mxs/ocotp.c @@ -25,27 +25,45 @@ #include <mach/generic.h> #include <mach/ocotp.h> #include <mach/imx-regs.h> +#include <mach/clock-imx28.h> +#include <mach/power.h> #define DRIVERNAME "ocotp" -#define OCOTP_WORD_OFFSET 0x20 +#define OCOTP_CTRL 0x0 +# define OCOTP_CTRL_ADDR_MASK 0x3f +# define OCOTP_CTRL_BUSY (1 << 8) +# define OCOTP_CTRL_ERROR (1 << 9) +# define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) +# define OCOTP_CTRL_WR_UNLOCK 0x3e770000 + +#define OCOTP_DATA 0x10 -#define BM_OCOTP_CTRL_BUSY (1 << 8) -#define BM_OCOTP_CTRL_ERROR (1 << 9) -#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) +#define OCOTP_WORD_OFFSET 0x20 struct ocotp_priv { struct cdev cdev; void __iomem *base; }; +static int mxs_ocotp_wait_busy(struct ocotp_priv *priv) +{ + uint64_t start = get_time_ns(); + + /* check both BUSY and ERROR cleared */ + while (readl(priv->base + OCOTP_CTRL) & (OCOTP_CTRL_BUSY | OCOTP_CTRL_ERROR)) + if (is_timeout(start, MSECOND)) + return -ETIMEDOUT; + + return 0; +} + static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count, - ulong offset, ulong flags) + loff_t offset, ulong flags) { struct ocotp_priv *priv = cdev->priv; void __iomem *base = priv->base; - size_t size = min((ulong)count, cdev->size - offset); - uint64_t start; + size_t size = min((loff_t)count, cdev->size - offset); int i; /* @@ -54,25 +72,20 @@ static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count, */ /* try to clear ERROR bit */ - writel(BM_OCOTP_CTRL_ERROR, base + BIT_CLR); + writel(OCOTP_CTRL_ERROR, base + OCOTP_CTRL + BIT_CLR); - /* check both BUSY and ERROR cleared */ - start = get_time_ns(); - while (readl(base) & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) - if (is_timeout(start, MSECOND)) - return -ETIMEDOUT; + if (mxs_ocotp_wait_busy(priv)) + return -ETIMEDOUT; /* open OCOTP banks for read */ - writel(BM_OCOTP_CTRL_RD_BANK_OPEN, base + BIT_SET); + writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_SET); /* approximately wait 32 hclk cycles */ udelay(1); /* poll BUSY bit becoming cleared */ - start = get_time_ns(); - while (readl(base) & BM_OCOTP_CTRL_BUSY) - if (is_timeout(start, MSECOND)) - return -ETIMEDOUT; + if (mxs_ocotp_wait_busy(priv)) + return -ETIMEDOUT; for (i = 0; i < size; i++) /* When reading bytewise, we need to hop over the SET/CLR/TGL regs */ @@ -80,16 +93,107 @@ static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count, (((i + offset) & 0xfc) << 2) + ((i + offset) & 3)); /* close banks for power saving */ - writel(BM_OCOTP_CTRL_RD_BANK_OPEN, base + BIT_CLR); + writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_CLR); return size; } +static ssize_t mxs_ocotp_cdev_write(struct cdev *cdev, const void *buf, size_t count, + loff_t offset, ulong flags) +{ + struct ocotp_priv *priv = cdev->priv; + void __iomem *base = priv->base; + const char *write_param; + unsigned int write_enabled = 0; + unsigned long old_hclk, aligned_offset; + int old_vddio, num_words, num_bytes, i, ret = 0; + u8 *work_buf; + u32 reg; + + write_param = dev_get_param(cdev->dev, "permanent_write_enable"); + if (write_param) + write_enabled = simple_strtoul(write_param, NULL, 0); + + if (!write_param || !write_enabled) + return -EPERM; + + /* we can only work on u32, so calc some helpers */ + aligned_offset = offset & ~3UL; + num_words = DIV_ROUND_UP(offset - aligned_offset + count, 4); + num_bytes = num_words << 2; + + /* read in all words which will be modified */ + work_buf = xmalloc(num_bytes); + + i = mxs_ocotp_cdev_read(cdev, work_buf, num_bytes, aligned_offset, 0); + if (i != num_bytes) { + ret = -ENXIO; + goto free_mem; + } + + /* modify read words with to be written data */ + for (i = 0; i < count; i++) + work_buf[offset - aligned_offset + i] |= ((u8 *)buf)[i]; + + /* prepare system for OTP write */ + old_hclk = imx_get_hclk(); + old_vddio = imx_get_vddio(); + + imx_set_hclk(24000000); + imx_set_vddio(2800000); + + writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_CLR); + + if (mxs_ocotp_wait_busy(priv)) { + ret = -ETIMEDOUT; + goto restore_system; + } + + /* write word for word via data register */ + for (i = 0; i < num_words; i++) { + reg = readl(base + OCOTP_CTRL) & ~OCOTP_CTRL_ADDR_MASK; + reg |= OCOTP_CTRL_WR_UNLOCK | ((aligned_offset >> 2) + i); + writel(reg, base + OCOTP_CTRL); + + writel(((u32 *)work_buf)[i], base + OCOTP_DATA); + + if (mxs_ocotp_wait_busy(priv)) { + ret = -ETIMEDOUT; + goto restore_system; + } + + mdelay(2); + } + +restore_system: + imx_set_vddio(old_vddio); + imx_set_hclk(old_hclk); +free_mem: + free(work_buf); + + return ret; +} + static struct file_operations mxs_ocotp_ops = { .read = mxs_ocotp_cdev_read, .lseek = dev_lseek_default, }; +static int mxs_ocotp_write_enable_set(struct device_d *dev, struct param_d *param, + const char *val) +{ + unsigned long write_enable; + + if (!val) + return -EINVAL; + + write_enable = simple_strtoul(val, NULL, 0); + if (write_enable > 1) + return -EINVAL; + + return dev_param_set_generic(dev, param, write_enable ? "1" : "0"); +} + static int mxs_ocotp_probe(struct device_d *dev) { int err; @@ -106,6 +210,18 @@ static int mxs_ocotp_probe(struct device_d *dev) if (err < 0) return err; + if (IS_ENABLED(CONFIG_MXS_OCOTP_WRITABLE)) { + mxs_ocotp_ops.write = mxs_ocotp_cdev_write; + + err = dev_add_param(dev, "permanent_write_enable", + mxs_ocotp_write_enable_set, NULL, 0); + if (err < 0) + return err; + err = dev_set_param(dev, "permanent_write_enable", "0"); + if (err < 0) + return err; + } + return 0; } diff --git a/arch/arm/mach-mxs/power.c b/arch/arm/mach-mxs/power.c new file mode 100644 index 0000000000..f4d0b9e3e6 --- /dev/null +++ b/arch/arm/mach-mxs/power.c @@ -0,0 +1,84 @@ +/* + * i.MX28 power related functions + * + * Copyright 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> + * Copyright (C) 2012 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <common.h> +#include <io.h> +#include <errno.h> +#include <mach/imx-regs.h> + +#define POWER_CTRL (IMX_POWER_BASE + 0x0) +#define POWER_CTRL_CLKGATE 0x40000000 + +#define POWER_VDDIOCTRL (IMX_POWER_BASE + 0x60) + +#define POWER_STS (IMX_POWER_BASE + 0xc0) +#define POWER_STS_VBUSVALID 0x00000002 +#define POWER_STS_BVALID 0x00000004 +#define POWER_STS_AVALID 0x00000008 + +#define POWER_DEBUG (IMX_POWER_BASE + 0x110) +#define POWER_DEBUG_BVALIDPIOLOCK 0x00000002 +#define POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +#define POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 + +#define TRG_MASK 0x1f + +int imx_get_vddio(void) +{ + u32 val; + + val = readl(POWER_VDDIOCTRL) & TRG_MASK; + if (val > 0x10) + val = 0x10; + + return 2800000 + val * 50000; +} + +int imx_set_vddio(int new_voltage_uV) +{ + u32 reg, val; + + if (new_voltage_uV < 2800000 || new_voltage_uV > 3600000) + return -EINVAL; + + val = (new_voltage_uV - 2800000) / 50000; + reg = readl(POWER_VDDIOCTRL) & ~TRG_MASK; + writel(reg | val, POWER_VDDIOCTRL); + + /* + * Wait for power to become stable. We just wait, because DC_OK can + * only detect rising voltages for DCDC. For all other cases, bootlets + * also do simple waiting, although horribly nested. We just take the + * maximum value of all cases from the bootlets and then add some. + */ + mdelay(30); + + return 2800000 + val * 50000; +} + +void imx_power_prepare_usbphy(void) +{ + u32 reg; + + /* + * Set these bits so that we can force the OTG bits high + * so the ARC core operates properly + */ + writel(POWER_CTRL_CLKGATE, POWER_CTRL + BIT_CLR); + + writel(POWER_DEBUG_VBUSVALIDPIOLOCK | + POWER_DEBUG_AVALIDPIOLOCK | + POWER_DEBUG_BVALIDPIOLOCK, POWER_DEBUG + BIT_SET); + + reg = readl(POWER_STS); + reg |= POWER_STS_BVALID | POWER_STS_AVALID | POWER_STS_VBUSVALID; + writel(reg, POWER_STS); +} diff --git a/arch/arm/mach-mxs/reset-imx.c b/arch/arm/mach-mxs/reset-imx.c deleted file mode 100644 index cfb3548f2a..0000000000 --- a/arch/arm/mach-mxs/reset-imx.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * (C) Copyright 2010 Juergen Beisert - Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <init.h> -#include <notifier.h> -#include <mach/imx-regs.h> -#include <io.h> - -#define HW_RTC_CTRL 0x000 -# define BM_RTC_CTRL_WATCHDOGEN (1 << 4) -#define HW_RTC_CTRL_SET 0x004 -#define HW_RTC_CTRL_CLR 0x008 -#define HW_RTC_CTRL_TOG 0x00C - -#define HW_RTC_WATCHDOG 0x050 -#define HW_RTC_WATCHDOG_SET 0x054 -#define HW_RTC_WATCHDOG_CLR 0x058 -#define HW_RTC_WATCHDOG_TOG 0x05C - -#define WDOG_COUNTER_RATE 1000 /* 1 kHz clock */ - -#define HW_RTC_PERSISTENT1 0x070 -# define BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER 0x80000000 -#define HW_RTC_PERSISTENT1_SET 0x074 -#define HW_RTC_PERSISTENT1_CLR 0x078 -#define HW_RTC_PERSISTENT1_TOG 0x07C - -/* - * Reset the cpu by setting up the watchdog timer and let it time out - * - * TODO There is a much easier way to reset the CPU: Refer bit 2 in - * the HW_CLKCTRL_RESET register, data sheet page 106/4-30 - */ -void __noreturn reset_cpu (unsigned long addr) -{ - writel(WDOG_COUNTER_RATE, IMX_WDT_BASE + HW_RTC_WATCHDOG); - writel(BM_RTC_CTRL_WATCHDOGEN, IMX_WDT_BASE + HW_RTC_CTRL_SET); - writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER, IMX_WDT_BASE + HW_RTC_PERSISTENT1); - - while (1) - ; - /*NOTREACHED*/ -} -EXPORT_SYMBOL(reset_cpu); diff --git a/arch/arm/mach-mxs/soc-imx23.c b/arch/arm/mach-mxs/soc-imx23.c new file mode 100644 index 0000000000..6819b3cf2e --- /dev/null +++ b/arch/arm/mach-mxs/soc-imx23.c @@ -0,0 +1,37 @@ +/* + * (c) 2012 Juergen Beisert <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Collection of some SoC specific functions + */ + +#include <common.h> +#include <init.h> +#include <mach/imx-regs.h> +#include <io.h> + +#define HW_CLKCTRL_RESET 0x120 +# define HW_CLKCTRL_RESET_CHIP (1 << 1) + +/* Reset the full i.MX23 SoC via a chipset feature */ +void __noreturn reset_cpu(unsigned long addr) +{ + u32 reg; + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_RESET); + writel(reg | HW_CLKCTRL_RESET_CHIP, IMX_CCM_BASE + HW_CLKCTRL_RESET); + + while (1) + ; + /*NOTREACHED*/ +} +EXPORT_SYMBOL(reset_cpu); diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c new file mode 100644 index 0000000000..a181b759cb --- /dev/null +++ b/arch/arm/mach-mxs/soc-imx28.c @@ -0,0 +1,37 @@ +/* + * (c) 2012 Juergen Beisert <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Collection of some SoC specific functions + */ + +#include <common.h> +#include <init.h> +#include <mach/imx-regs.h> +#include <io.h> + +#define HW_CLKCTRL_RESET 0x1e0 +# define HW_CLKCTRL_RESET_CHIP (1 << 1) + +/* Reset the full i.MX28 SoC via a chipset feature */ +void __noreturn reset_cpu(unsigned long addr) +{ + u32 reg; + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_RESET); + writel(reg | HW_CLKCTRL_RESET_CHIP, IMX_CCM_BASE + HW_CLKCTRL_RESET); + + while (1) + ; + /*NOTREACHED*/ +} +EXPORT_SYMBOL(reset_cpu); diff --git a/arch/arm/mach-mxs/speed-imx23.c b/arch/arm/mach-mxs/speed-imx23.c index b10c78643c..f41b9bc75a 100644 --- a/arch/arm/mach-mxs/speed-imx23.c +++ b/arch/arm/mach-mxs/speed-imx23.c @@ -184,12 +184,34 @@ unsigned imx_get_hclk(void) if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) { rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; - rate >>= 5U; /* / 32 */ + rate = DIV_ROUND_UP(rate, 32); } else - rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; + rate = DIV_ROUND_UP(rate, + readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f); return rate * 1000; } +unsigned imx_set_hclk(unsigned nc) +{ + unsigned root_rate = imx_get_armclk(); + unsigned reg, div; + + div = DIV_ROUND_UP(root_rate, nc); + if ((div == 0) || (div >= 32)) + return 0; + + if ((root_rate < nc) && (root_rate == 64000000)) + div = 3; + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & ~0x3f; + writel(reg | div, IMX_CCM_BASE + HW_CLKCTRL_HBUS); + + while (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & (1 << 31)) + ; + + return imx_get_hclk(); +} + /* * Source of UART, debug UART, audio, PWM, dri, timer, digctl */ diff --git a/arch/arm/mach-mxs/speed-imx28.c b/arch/arm/mach-mxs/speed-imx28.c index 67cdbdf81d..2641fb6fb2 100644 --- a/arch/arm/mach-mxs/speed-imx28.c +++ b/arch/arm/mach-mxs/speed-imx28.c @@ -251,12 +251,34 @@ unsigned imx_get_hclk(void) if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) { rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; - rate /= 32; + rate = DIV_ROUND_UP(rate, 32); } else - rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; + rate = DIV_ROUND_UP(rate, + readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f); return rate * 1000; } +unsigned imx_set_hclk(unsigned nc) +{ + unsigned root_rate = imx_get_armclk(); + unsigned reg, div; + + div = DIV_ROUND_UP(root_rate, nc); + if ((div == 0) || (div >= 32)) + return 0; + + if ((root_rate < nc) && (root_rate == 64000000)) + div = 3; + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & ~0x3f; + writel(reg | div, IMX_CCM_BASE + HW_CLKCTRL_HBUS); + + while (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & (1 << 31)) + ; + + return imx_get_hclk(); +} + /* * Source of UART, debug UART, audio, PWM, dri, timer, digctl */ diff --git a/arch/arm/mach-mxs/usb.c b/arch/arm/mach-mxs/usb-imx23.c index b7a93769b7..9aaf4bca18 100644 --- a/arch/arm/mach-mxs/usb.c +++ b/arch/arm/mach-mxs/usb-imx23.c @@ -1,5 +1,5 @@ /* - * i.MX23/28 USBPHY setup + * i.MX23 USBPHY setup * * Copyright 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> * @@ -20,19 +20,7 @@ #include <common.h> #include <io.h> #include <mach/imx-regs.h> - -#define POWER_CTRL (IMX_POWER_BASE + 0x0) -#define POWER_CTRL_CLKGATE 0x40000000 - -#define POWER_STS (IMX_POWER_BASE + 0xc0) -#define POWER_STS_VBUSVALID 0x00000002 -#define POWER_STS_BVALID 0x00000004 -#define POWER_STS_AVALID 0x00000008 - -#define POWER_DEBUG (IMX_POWER_BASE + 0x110) -#define POWER_DEBUG_BVALIDPIOLOCK 0x00000002 -#define POWER_DEBUG_AVALIDPIOLOCK 0x00000004 -#define POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 +#include <mach/power.h> #define USBPHY_PWD (IMX_USBPHY_BASE + 0x0) @@ -49,23 +37,9 @@ #define SET 0x4 #define CLR 0x8 -int imx_usb_phy_enable(void) +int imx23_usb_phy_enable(void) { - u32 reg; - - /* - * Set these bits so that we can force the OTG bits high - * so the ARC core operates properly - */ - writel(POWER_CTRL_CLKGATE, POWER_CTRL + CLR); - - writel(POWER_DEBUG_VBUSVALIDPIOLOCK | - POWER_DEBUG_AVALIDPIOLOCK | - POWER_DEBUG_BVALIDPIOLOCK, POWER_DEBUG + SET); - - reg = readl(POWER_STS); - reg |= POWER_STS_BVALID | POWER_STS_AVALID | POWER_STS_VBUSVALID; - writel(reg, POWER_STS); + imx_power_prepare_usbphy(); /* Reset USBPHY module */ writel(USBPHY_CTRL_SFTRST, USBPHY_CTRL + SET); @@ -89,4 +63,3 @@ int imx_usb_phy_enable(void) return 0; } - diff --git a/arch/arm/mach-mxs/usb-imx28.c b/arch/arm/mach-mxs/usb-imx28.c new file mode 100644 index 0000000000..61d59c3616 --- /dev/null +++ b/arch/arm/mach-mxs/usb-imx28.c @@ -0,0 +1,101 @@ +/* + * i.MX28 USBPHY setup + * + * Copyright 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <common.h> +#include <io.h> +#include <errno.h> +#include <mach/imx-regs.h> + +#define POWER_CTRL (IMX_POWER_BASE + 0x0) +#define POWER_CTRL_CLKGATE 0x40000000 + +#define POWER_STS (IMX_POWER_BASE + 0xc0) +#define POWER_STS_VBUSVALID 0x00000002 +#define POWER_STS_BVALID 0x00000004 +#define POWER_STS_AVALID 0x00000008 + +#define POWER_DEBUG (IMX_POWER_BASE + 0x110) +#define POWER_DEBUG_BVALIDPIOLOCK 0x00000002 +#define POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +#define POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 + +#define USBPHY_PWD 0x0 + +#define USBPHY_CTRL 0x30 +#define USBPHY_CTRL_SFTRST (1 << 31) +#define USBPHY_CTRL_CLKGATE (1 << 30) +#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) +#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) + +#define CLK_PLL0CTRL0 (IMX_CCM_BASE + 0x0) +#define CLK_PLL1CTRL0 (IMX_CCM_BASE + 0x20) +#define PLLCTRL0_EN_USB_CLKS (1 << 18) + +#define DIGCTRL_CTRL (IMX_DIGCTL_BASE + 0x0) +#define DIGCTL_CTRL_USB0_CLKGATE (1 << 2) +#define DIGCTL_CTRL_USB1_CLKGATE (1 << 16) + +#define SET 0x4 +#define CLR 0x8 + +static void imx28_usb_phy_reset(void __iomem *phybase) +{ + /* Reset USBPHY module */ + writel(USBPHY_CTRL_SFTRST, phybase + USBPHY_CTRL + SET); + udelay(10); + writel(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST, + phybase + USBPHY_CTRL + CLR); +} + +static void imx28_usb_phy_enable(void __iomem *phybase) +{ + /* Power up the PHY */ + writel(0, phybase + USBPHY_PWD); + + writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1, + phybase + USBPHY_CTRL + SET); +} + +int imx28_usb_phy0_enable(void) +{ + imx28_usb_phy_reset((void *)IMX_USBPHY0_BASE); + + /* Turn on the USB clocks */ + writel(PLLCTRL0_EN_USB_CLKS, CLK_PLL0CTRL0 + SET); + + writel(DIGCTL_CTRL_USB0_CLKGATE, DIGCTRL_CTRL + CLR); + + imx28_usb_phy_enable((void *)IMX_USBPHY0_BASE); + + return 0; +} + +int imx28_usb_phy1_enable(void) +{ + imx28_usb_phy_reset((void *)IMX_USBPHY1_BASE); + + /* Turn on the USB clocks */ + writel(PLLCTRL0_EN_USB_CLKS, CLK_PLL1CTRL0 + SET); + + writel(DIGCTL_CTRL_USB1_CLKGATE, DIGCTRL_CTRL + CLR); + + imx28_usb_phy_enable((void *)IMX_USBPHY1_BASE); + + return 0; +} diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index cdcb2f8e5d..623ddfb394 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -268,7 +268,10 @@ static __inline__ int find_next_zero_bit(void *addr, int size, int offset) return result + ffz(tmp); } +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/hweight.h> static __inline__ int ext2_set_bit(int nr, volatile void *addr) diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h new file mode 100644 index 0000000000..27d269f491 --- /dev/null +++ b/arch/blackfin/include/asm/dma.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __ASM_DMA_H +#define __ASM_DMA_H + +/* empty */ + +#endif /* __ASM_DMA_H */ diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile index 2f7731824b..cefb4dc89f 100644 --- a/arch/blackfin/lib/Makefile +++ b/arch/blackfin/lib/Makefile @@ -8,6 +8,7 @@ obj-y += smulsi3_highpart.o obj-y += umodsi3.o obj-y += lshrdi3.o obj-y += ashldi3.o +obj-y += ashrdi3.o obj-y += divsi3.o obj-y += modsi3.o obj-y += cpu.o diff --git a/arch/blackfin/lib/ashrdi3.c b/arch/blackfin/lib/ashrdi3.c new file mode 100644 index 0000000000..b5b351e82e --- /dev/null +++ b/arch/blackfin/lib/ashrdi3.c @@ -0,0 +1,36 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include "gcclib.h" + +#ifdef CONFIG_ARITHMETIC_OPS_L1 +DItype __ashrdi3(DItype u, word_type b)__attribute__((l1_text)); +#endif + +DItype __ashrdi3(DItype u, word_type b) +{ + DIunion w; + word_type bm; + DIunion uu; + + if (b == 0) + return u; + + uu.ll = u; + + bm = (sizeof(SItype) * BITS_PER_UNIT) - b; + if (bm <= 0) { + /* w.s.high = 1..1 or 0..0 */ + w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1); + w.s.low = uu.s.high >> -bm; + } else { + USItype carries = (USItype) uu.s.high << bm; + w.s.high = uu.s.high >> b; + w.s.low = ((USItype) uu.s.low >> b) | carries; + } + + return w.ll; +} diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 001ebf2e72..bf1ac6e58a 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -28,5 +28,8 @@ #define _ASM_MIPS_BITOPS_H_ #include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> #endif /* _ASM_MIPS_BITOPS_H_ */ diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h new file mode 100644 index 0000000000..27d269f491 --- /dev/null +++ b/arch/mips/include/asm/dma.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __ASM_DMA_H +#define __ASM_DMA_H + +/* empty */ + +#endif /* __ASM_DMA_H */ diff --git a/arch/nios2/include/asm/bitops.h b/arch/nios2/include/asm/bitops.h index ab0e3d5ff7..07128451c1 100644 --- a/arch/nios2/include/asm/bitops.h +++ b/arch/nios2/include/asm/bitops.h @@ -1,4 +1,9 @@ #ifndef _ASM_BITOPS_H #define _ASM_BITOPS_H +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> + #endif /* _ASM_BITOPS_H */ diff --git a/arch/nios2/include/asm/dma-mapping.h b/arch/nios2/include/asm/dma-mapping.h index 5b70f4cead..9819a973e7 100644 --- a/arch/nios2/include/asm/dma-mapping.h +++ b/arch/nios2/include/asm/dma-mapping.h @@ -1,8 +1,12 @@ #ifndef __ASM_NIOS2_DMA_MAPPING_H #define __ASM_NIOS2_DMA_MAPPING_H +#include <common.h> +#include <xfuncs.h> + #include <asm/cache.h> + /* dma_alloc_coherent() return cache-line aligned allocation which is mapped * to uncached io region. * @@ -22,4 +26,10 @@ static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) return (void *)(*handle | IO_REGION_BASE); } +#define dma_alloc dma_alloc +static inline void *dma_alloc(size_t size) +{ + return xmemalign(DCACHE_LINE_SIZE, ALIGN(size, DCACHE_LINE_SIZE)); +} + #endif /* __ASM_NIOS2_DMA_MAPPING_H */ diff --git a/arch/nios2/include/asm/dma.h b/arch/nios2/include/asm/dma.h new file mode 100644 index 0000000000..8f709d2dbf --- /dev/null +++ b/arch/nios2/include/asm/dma.h @@ -0,0 +1,8 @@ +/* + * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#include <asm/dma-mapping.h> diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile index fd8bbbf4d7..1f4b1755d4 100644 --- a/arch/openrisc/Makefile +++ b/arch/openrisc/Makefile @@ -1,5 +1,7 @@ CPPFLAGS += -D__OR1K__ -ffixed-r10 -mhard-mul -mhard-div +LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) + board-$(CONFIG_GENERIC) := generic KALLSYMS += --symbol-prefix=_ @@ -18,4 +20,6 @@ common-y += $(BOARD) common-y += arch/openrisc/lib/ common-y += arch/openrisc/cpu/ +common-y += $(LIBGCC) + lds-y += arch/openrisc/cpu/barebox.lds diff --git a/arch/openrisc/include/asm/dma.h b/arch/openrisc/include/asm/dma.h new file mode 100644 index 0000000000..27d269f491 --- /dev/null +++ b/arch/openrisc/include/asm/dma.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __ASM_DMA_H +#define __ASM_DMA_H + +/* empty */ + +#endif /* __ASM_DMA_H */ diff --git a/arch/ppc/include/asm/dma.h b/arch/ppc/include/asm/dma.h new file mode 100644 index 0000000000..27d269f491 --- /dev/null +++ b/arch/ppc/include/asm/dma.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __ASM_DMA_H +#define __ASM_DMA_H + +/* empty */ + +#endif /* __ASM_DMA_H */ diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c index 90a97413b7..96fa100011 100644 --- a/arch/sandbox/board/hostfile.c +++ b/arch/sandbox/board/hostfile.c @@ -34,7 +34,7 @@ struct hf_priv { struct hf_platform_data *pdata; }; -static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, ulong offset, ulong flags) +static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, loff_t offset, ulong flags) { struct hf_platform_data *hf = cdev->priv; int fd = hf->fd; @@ -45,7 +45,7 @@ static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, ulong offset, return linux_read(fd, buf, count); } -static ssize_t hf_write(struct cdev *cdev, const void *buf, size_t count, ulong offset, ulong flags) +static ssize_t hf_write(struct cdev *cdev, const void *buf, size_t count, loff_t offset, ulong flags) { struct hf_platform_data *hf = cdev->priv; int fd = hf->fd; diff --git a/arch/sandbox/include/asm/dma.h b/arch/sandbox/include/asm/dma.h new file mode 100644 index 0000000000..459536779e --- /dev/null +++ b/arch/sandbox/include/asm/dma.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __ASM_DMA_H +#define __ASM_DMA_H + +/* empty*/ + +#endif /* __ASM_DMA_H */ diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index b43afa3f99..830b1a5510 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -27,6 +27,11 @@ #ifndef _ASM_X86_BITOPS_H_ #define _ASM_X86_BITOPS_H_ -/* nothing special yet */ +#define BITS_PER_LONG 32 + +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffs.h> #endif /* _ASM_X86_BITOPS_H_ */ diff --git a/arch/x86/include/asm/dma.h b/arch/x86/include/asm/dma.h new file mode 100644 index 0000000000..27d269f491 --- /dev/null +++ b/arch/x86/include/asm/dma.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __ASM_DMA_H +#define __ASM_DMA_H + +/* empty */ + +#endif /* __ASM_DMA_H */ |