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-rw-r--r--arch/architecture.dox175
-rw-r--r--arch/arm/boards/a9m2410/a9m2410.c68
-rw-r--r--arch/arm/boards/a9m2440/a9m2440.c79
-rw-r--r--arch/arm/boards/beagle/board.c31
-rw-r--r--arch/arm/boards/ccxmx51/ccxmx51.dox7
-rw-r--r--arch/arm/boards/chumby_falconwing/falconwing.c138
-rw-r--r--arch/arm/boards/edb93xx/edb93xx.dox108
-rw-r--r--arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox11
-rw-r--r--arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.dox4
-rw-r--r--arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.dox4
-rw-r--r--arch/arm/boards/freescale-mx21-ads/imx21ads.dox5
-rw-r--r--arch/arm/boards/freescale-mx23-evk/mx23-evk.c32
-rw-r--r--arch/arm/boards/freescale-mx27-ads/imx27ads.dox5
-rw-r--r--arch/arm/boards/freescale-mx35-3ds/3stack.dox4
-rw-r--r--arch/arm/boards/freescale-mx51-babbage/mx51-pdk.dox4
-rw-r--r--arch/arm/boards/freescale-mx53-qsb/mx53-pdk.dox4
-rw-r--r--arch/arm/boards/freescale-mx53-smd/mx53-smd.dox4
-rw-r--r--arch/arm/boards/friendlyarm-mini2440/mini2440.c159
-rw-r--r--arch/arm/boards/guf-cupid/cupid.dox9
-rw-r--r--arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c59
-rw-r--r--arch/arm/boards/karo-tx28/tx28.c52
-rw-r--r--arch/arm/boards/karo-tx51/tx51.dox50
-rw-r--r--arch/arm/boards/module-mb7707/module-mb7707.dox29
-rw-r--r--arch/arm/boards/mx31moboard/mx31moboard.dox10
-rw-r--r--arch/arm/boards/netx/netx.dox9
-rw-r--r--arch/arm/boards/omap343xdsp/board.c26
-rw-r--r--arch/arm/boards/phytec-phycard-imx27/pca100.dox8
-rw-r--r--arch/arm/boards/phytec-phycard-omap3/pca-a-l1.dox16
-rw-r--r--arch/arm/boards/phytec-phycore-imx27/pcm038.dox9
-rw-r--r--arch/arm/boards/phytec-phycore-imx31/pcm037.dox11
-rw-r--r--arch/arm/boards/phytec-phycore-imx35/pcm043.dox28
-rw-r--r--arch/arm/boards/qil-a926x/qil-a9260.dox22
-rw-r--r--arch/arm/boards/scb9328/scb9328.dox9
-rw-r--r--arch/arm/boards/tny-a926x/tny-a9263.dox33
-rw-r--r--arch/arm/boards/tny-a926x/tny-a9g20-lpw.dox37
-rw-r--r--arch/arm/boards/toshiba-ac100/toshiba-ac100.dox37
-rw-r--r--arch/arm/boards/usb-a926x/usb-a9263.dox30
-rw-r--r--arch/arm/boards/usb-a926x/usb-a9g20-lpw.dox33
-rw-r--r--arch/arm/boards/virt2real/virt2real.dox41
-rw-r--r--arch/arm/mach-arm.dox67
-rw-r--r--arch/arm/mach-davinci/mach-davinci.dox7
-rw-r--r--arch/arm/mach-omap/arch-omap.dox96
-rw-r--r--arch/arm/mach-samsung/lowlevel-s3c24x0.S8
-rw-r--r--arch/arm/mach-samsung/mem-s3c24x0.c57
-rw-r--r--arch/blackfin/boards/ipe337/ipe337.dox10
-rw-r--r--arch/blackfin/mach-bf.dox9
-rw-r--r--arch/mips/boards/dlink-dir-320/dlink-dir-320.dox38
-rw-r--r--arch/mips/boards/loongson-ls1b/loongson_ls1b.dox47
-rw-r--r--arch/mips/boards/qemu-malta/qemu-malta.dox20
-rw-r--r--arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox46
-rw-r--r--arch/mips/boards/tplink-mr3020/tplink-mr3020.dox64
-rw-r--r--arch/mips/mach-bcm47xx/mach-bcm47xx.dox7
-rw-r--r--arch/mips/mach-loongson/mach-loongson.dox7
-rw-r--r--arch/mips/mach-malta/mach-malta.dox7
-rw-r--r--arch/mips/mach-mips.dox69
-rw-r--r--arch/mips/mach-xburst/mach-xburst.dox7
-rw-r--r--arch/ppc/boards/pcm030/pcm030.dox8
-rw-r--r--arch/ppc/mach-ppc.dox9
-rw-r--r--arch/sandbox/os/common.c55
-rw-r--r--arch/x86/boards/x86_generic/generic_pc.c34
-rw-r--r--arch/x86/boot/bioscall.S4
-rw-r--r--arch/x86/lib/bios_disk.S3
-rw-r--r--arch/x86/lib/linux_start.S3
-rw-r--r--arch/x86/mach-x86.dox128
64 files changed, 0 insertions, 2210 deletions
diff --git a/arch/architecture.dox b/arch/architecture.dox
deleted file mode 100644
index 2d2cf05aa7..0000000000
--- a/arch/architecture.dox
+++ /dev/null
@@ -1,175 +0,0 @@
-/** @page dev_architecture Integrate a new architecture (ARCH)
-
-@section linker_scripts Rules for the generic Linker Script File
-
-Never include an object file by name directly! Linker Script Files defines the
-layout, not the content. Content is defined in objecfiles instead.
-
-Don't rely on the given object file order to create your binary @a barebox! This
-may work, but is not relyable in all cases (and its a very bad style)!
-
-For the special case some layout contraints exists, use specific section
-naming instead. Refer @ref reset_code how to define this specific section.
-
-@section reset_code Bring it up: The Reset Code
-
-The way a CPU wakes up after reset is very specific to its architecture.
-
-For example the ARM architecture starts its reset code at address 0x0000000,
-the x86 architecture at 0x000FFFF0, PowerPC at 0x00000100 or 0xFFFFF100.
-
-So for the special reset code on all architectures it must be located at
-architecture specific locations within the binary @a barebox image.
-
-All reset code uses section ".text_entry" for its localisation within the
-binary @a barebox image. Its up to the linker script file to use this section name
-to find the right place in whatever environment and @a barebox sizes.
-
-@code
- .section ".text_entry","ax"
-@endcode
-
-@section arch_files List of changes
-
- - create a new subdirectory in /arch
-TODO
-
-*/
-
-/** @page dev_cpu Integrate a new CPU (MACH)
-
-Features required for every CPU:
-
- - clocksource
- - CPU reset function
-
-@section time_keeping Time keeping
-
-In @a barebox we are using the clocksource mechanism from the Linux Kernel.
-This makes it fairly easy to add timer functionality for a new board or
-architecture.
-
-Apart from initialization there is only one function to be registerd:
-clocksource_read(). This function returns the current value of a free running
-counter. Other functions like udelay() and get_time_ns() are derived from this
-function. The only thing you have to implement is a clocksource driver and
-to register it at runtime.
-
-@code
-static uint64_t mycpu_clocksource_read(void)
-{
- TODO
-}
-
-static struct clocksource cs = {
- .read = mycpu_clocksource_read,
- .mask = 0xffffffff,
- .shift = 10,
-};
-
-....
- init_clock(&cs);
-....
-@endcode
-
-See arch/arm/mach-imx/clocksource.c for an example. clocksource drivers from
-the Linux Kernel can be used nearly 1:1, except for the register accesses.
-
-Note: For clocksources the __lshrdi3 symbol is needed. You can find the
-function for your architecture in the Linux Kernel or a libc of your choice.
-
-@note @a barebox expects an upward counting counter!
-
-@section reset_function Reset function
-
-TODO
-
-@li @subpage dev_arm_mach
-@li @subpage dev_bf_mach
-@li @subpage dev_mips_mach
-@li @subpage dev_ppc_mach
-@li @subpage dev_x86_mach
-
-*/
-
-/** @page io_access_functions I/O access functions
-
-List of functions to be used for hardware register access (I/O).
-
-@section native_access Native IN/OUT access
-
-@note Native means: It uses the same endianess than the CPU.
-
-@subsection single_native_access Single access of various width
-
-The following functions are intended to be used for a single I/O access.
-
-To read a byte (8 bit) from a specific I/O address:
-@code
-uint8_t readb(unsigned long)
-@endcode
-
-To read a word (16 bit) from a specific I/O address:
-@code
-uint16_t readw(unsigned long)
-@endcode
-
-To read a long word (32 bit) from a specific I/O address:
-@code
-uint32_t readl(unsigned long)
-@endcode
-
-To write a byte (8 bit) into a specific I/O address:
-@code
-void writeb(uint8_t val, unsigned long)
-@endcode
-
-To write a word (16 bit) into a specific I/O address:
-@code
-void writew(uint16_t val, unsigned long)
-@endcode
-
-To write a long word (32 bit) into a specific I/O address:
-@code
-void writel(uint32_t val, unsigned long)
-@endcode
-
-@subsection string_native_access String native access of various width
-
-The following functions are intended to be used for string based I/O access.
-
-To read a string of bytes (8 bit) from one specific I/O address:
-@code
-void readsb(const void __iomem *addr, void *mem_buffer, int byte_count);
-@endcode
-
-To read a string of words (16 bit) from one specific I/O address:
-@code
-void readsw(const void __iomem *addr, void *mem_buffer, int word_count);
-@endcode
-
-To read a string of long words (32 bit) from one specific I/O address:
-@code
-void readsl(const void __iomem *addr, void *mem_buffer, int long_count);
-@endcode
-
-To write a string of bytes (8 bit) to one specific I/O address:
-@code
-void writesb(void __iomem *addr, const void *mem_buffer, int byte_count);
-@endcode
-
-To write a string of words (16 bit) to one specific I/O address:
-@code
-void writesw(void __iomem *addr, const void *mem_buffer, int word_count);
-@endcode
-
-To write a string of long words (32 bit) to one specific I/O address:
-@code
-void writesl(void __iomem *addr, const void *mem_buffer, int long_count);
-@endcode
-
-@section special_access Special IN/OUT access
-
-TBD
-
-*/
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index 943b7709bf..44cf51b212 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -14,12 +14,6 @@
*
*/
-/**
- * @file
- * @brief a9m2410 Specific Board Initialization routines
- *
- */
-
#include <common.h>
#include <driver.h>
#include <init.h>
@@ -154,65 +148,3 @@ static int a9m2410_console_init(void)
}
console_initcall(a9m2410_console_init);
-
-/** @page a9m2410 DIGI's a9m2410
-
-This CPU card is based on a Samsung S3C2410 CPU. The card is shipped with:
-
-- S3C2410\@200 MHz (ARM920T/ARMv4T)
-- 12MHz crystal reference
-- SDRAM 32 MiB
- - Samsung K4M563233E-EE1H
- - 2M x 32Bit x 4 Banks Mobile SDRAM
- - 90 pin FBGA
- - CL3\@133MHz, CL2\@100MHz (CAS/RAS delay 19ns)
- - four banks
- - 32 bit data bits
- - row address size is 11
- - Row cycle time: 69ns
- - collumn address size is 9 bits
- - Extended temperature range (-25C...85C)
- - 64ms refresh period (4k)
-- NAND Flash 32 MiB
- - Samsung KM29U256T
- - 32MiB 3,3V 8-bit
- - ID: 0xEC, 0x75, 0x??, 0xBD
- - 30ns/40ns/20ns
-- I2C interface, 100KHz and 400KHz
- - Real Time Clock
- - Dallas DS1337
- - address 0x68
- - EEPROM
- - ST M24LC64
- - address 0x50
- - 16bit addressing
-- LCD interface
-- Touch Screen interface
-- Camera interface
-- I2S interface
-- AC97 Audio-CODEC interface
-- SD card interface
-- 3 serial RS232 interfaces
-- Host and device USB interface, USB1.1 compliant
-- Ethernet interface
- - 10Mbps, Cirrus Logic, CS8900A (on the CPU card) or
- - 10/100Mbps, SMSC 91C111 (on the baseboard)
-- SPI interface
-- JTAG interface
-
-How to get the binary image:
-
-Using the default configuration:
-
-@code
-make ARCH=arm a9m2410_defconfig
-@endcode
-
-Build the binary image:
-
-@code
-make ARCH=arm CROSS_COMPILE=armv4compiler
-@endcode
-
-@note replace the armv4compiler with your ARM v4 cross compiler.
-*/
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index faac38a4e3..587baf6cfd 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -14,12 +14,6 @@
*
*/
-/**
- * @file
- * @brief a9m2440 Specific Board Initialization routines
- *
- */
-
#include <common.h>
#include <driver.h>
#include <init.h>
@@ -161,76 +155,3 @@ static int a9m2440_console_init(void)
}
console_initcall(a9m2440_console_init);
-
-/** @page a9m2440 DIGI's a9m2440
-
-This CPU card is based on a Samsung S3C2440 CPU. The card is shipped with:
-
-- S3C2440\@400 MHz or 533 MHz (ARM920T/ARMv4T)
-- 16.9344 MHz crystal reference
-- SDRAM 32/64/128 MiB
- - Samsung K4M563233E-EE1H (one or two devices for 32 MiB or 64 MiB)
- - 2M x 32bit x 4 Banks Mobile SDRAM
- - CL2\@100 MHz (CAS/RAS delay 19ns)
- - 105 MHz max
- - collumn address size is 9 bits
- - Row cycle time: 69ns
- - Samsung K4M513233C-DG75 (one or two devices for 64 MiB or 128 MiB)
- - 4M x 32bit x 4 Banks Mobile SDRAM
- - CL2\@100MHz (CAS/RAS delay 18ns)
- - 111 MHz max
- - collumn address size is 9 bits
- - Row cycle time: 63ns
- - 64ms refresh period (4k)
- - 90 pin FBGA
- - 32 bit data bits
- - Extended temperature range (-25C...85C)
-- NAND Flash 32/64/128 MiB
- - Samsung KM29U512T (NAND01GW3A0AN6)
- - 64 MiB 3,3V 8-bit
- - ID: 0xEC, 0x76, 0x??, 0xBD
- - Samsung KM29U256T
- - 32 MiB 3,3V 8-bit
- - ID: 0xEC, 0x75, 0x??, 0xBD
- - ST Micro
- - 128 MiB 3,3V 8-bit
- - ID: 0x20, 0x79
- - 30ns/40ns/20ns
-- I2C interface, 100 KHz and 400 KHz
- - Real Time Clock
- - Dallas DS1337
- - address 0x68
- - EEPROM
- - ST M24LC64
- - address 0x50
- - 16bit addressing
-- LCD interface
-- Touch Screen interface
-- Camera interface
-- I2S interface
-- AC97 Audio-CODEC interface
-- SD card interface
-- 3 serial RS232 interfaces
-- Host and device USB interface, USB1.1 compliant
-- Ethernet interface
- - 10Mbps, Cirrus Logic, CS8900A (on the CPU card)
-- SPI interface
-- JTAG interface
-
-How to get the binary image:
-
-Using the default configuration:
-
-@code
-make ARCH=arm a9m2440_defconfig
-@endcode
-
-Build the binary image:
-
-@code
-make ARCH=arm CROSS_COMPILE=armv4compiler
-@endcode
-
-@note replace the armv4compiler with your ARM v4 cross compiler.
-
-*/
diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c
index 1899b1d846..4054960581 100644
--- a/arch/arm/boards/beagle/board.c
+++ b/arch/arm/boards/beagle/board.c
@@ -15,37 +15,6 @@
*
*/
-/**
- * @file
- * @brief Beagle Specific Board Initialization routines
- */
-
-/**
- * @page ti_beagle Texas Instruments Beagle Board
- *
- * Beagle Board from Texas Instruments as described here:
- * http://www.beagleboard.org
- *
- * This board is based on OMAP3530.
- * More on OMAP3530 (including documentation can be found here):
- * http://focus.ti.com/docs/prod/folders/print/omap3530.html
- *
- * This file provides initialization in two stages:
- * @li boot time initialization - do basics required to get SDRAM working.
- * This is run from SRAM - so no case constructs and global vars can be used.
- * @li run time initialization - this is for the rest of the initializations
- * such as flash, uart etc.
- *
- * Boot time initialization includes:
- * @li SDRAM initialization.
- * @li Pin Muxing relevant for Beagle.
- *
- * Run time initialization includes
- * @li serial @ref serial_ns16550.c driver device definition
- *
- * Originally from arch/arm/boards/omap/board-sdp343x.c
- */
-
#include <common.h>
#include <console.h>
#include <init.h>
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.dox b/arch/arm/boards/ccxmx51/ccxmx51.dox
deleted file mode 100644
index cc28e8d66a..0000000000
--- a/arch/arm/boards/ccxmx51/ccxmx51.dox
+++ /dev/null
@@ -1,7 +0,0 @@
-/** @page ccxmx51 Digi ConnectCore board
-
-This boards is based on a Freescale i.MX51 CPU. The board is shipped with:
-- Up to 8 GB NAND Flash.
-- Up to 512 MB DDR2 RAM.
-
-*/
diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c
index 77581f668f..2e5fca5f50 100644
--- a/arch/arm/boards/chumby_falconwing/falconwing.c
+++ b/arch/arm/boards/chumby_falconwing/falconwing.c
@@ -318,141 +318,3 @@ static int falconwing_console_init(void)
}
console_initcall(falconwing_console_init);
-
-/** @page chumbyone Chumby Industrie's Falconwing
-
-This device is also known as "chumby one" (http://www.chumby.com/)
-
-This CPU card is based on a Freescale i.MX23 CPU. The card is shipped with:
-
-- 64 MiB synchronous dynamic RAM (DDR type)
-
-Memory layout when @b barebox is running:
-
-- 0x40000000 start of SDRAM
-- 0x40000100 start of kernel's boot parameters
- - below malloc area: stack area
- - below barebox: malloc area
-- 0x42000000 start of @b barebox
-
-@section get_falconwing_binary How to get the bootloader binary image:
-
-Using the default configuration:
-
-@verbatim
-make ARCH=arm chumbyone_defconfig
-@endverbatim
-
-Build the bootloader binary image:
-
-@verbatim
-make ARCH=arm CROSS_COMPILE=armv5compiler
-@endverbatim
-
-@note replace the armv5compiler with your ARM v5 cross compiler.
-
-@section setup_falconwing How to prepare an MCI card to boot the "chumby one" with barebox
-
-- Create four primary partitions on the MCI card
- - the first one for the bootlets (about 256 kiB)
- - the second one for the persistant environment (size is up to you, at least 256k)
- - the third one for the kernel (2 MiB ... 4 MiB in size)
- - the 4th one for the root filesystem which can fill the rest of the available space
-
-- Mark the first partition with the partition ID "53" and copy the bootlets
- into this partition (currently not part of @b barebox!).
-
-- Copy the default @b barebox environment into the second partition (no filesystem required).
-
-- Copy the kernel into the third partition (no filesystem required).
-
-- Create the root filesystem in the 4th partition. You may copy an image into this
- partition or you can do it in the classic way: mkfs on it, mount it and copy
- all required data and programs into it.
-
-@section gpio_falconwing Available GPIOs
-
-The Falconwing uses some GPIOs to control various features. With the regular
-GPIO commands these features can be controlled at @a barebox's runtime.
-
-<table width="100%" border="1" cellspacing="1" cellpadding="3">
- <tr>
- <td>No</td>
- <td>Direction</td>
- <td>Function</td>
- <td>Reset</td>
- <td>Set</td>
- </tr>
- <tr>
- <td>8</td>
- <td>Output</td>
- <td>Switch Audio Amplifier</td>
- <td>Off</td>
- <td>On</td>
- </tr>
- <tr>
- <td>11</td>
- <td>Input</td>
- <td>Head Phone Detection</td>
- <td>TBD</td>
- <td>TBD</td>
- </tr>
- <tr>
- <td>14</td>
- <td>Input</td>
- <td>Unused (J113)</td>
- <td>User</td>
- <td>User</td>
- </tr>
- <tr>
- <td>15</td>
- <td>Input</td>
- <td>Unused (J114)</td>
- <td>User</td>
- <td>User</td>
- </tr>
- <tr>
- <td>26</td>
- <td>Output</td>
- <td>USB Power</td>
- <td>TBD</td>
- <td>TBD</td>
- </tr>
- <tr>
- <td>27</td>
- <td>Input</td>
- <td>Display Connected</td>
- <td>Display<br>Attached</td>
- <td>Display<br>Disconnected</td>
- </tr>
- <tr>
- <td>29</td>
- <td>Output</td>
- <td>USB HUB Reset</td>
- <td>TBD</td>
- <td>TBD</td>
- </tr>
- <tr>
- <td>50</td>
- <td>Output</td>
- <td>Display Reset</td>
- <td>Display<br>Reset</td>
- <td>Display<br>Running</td>
- </tr>
- <tr>
- <td>60</td>
- <td>Output</td>
- <td>Display Backlight</td>
- <td>Backlight<br>Off</td>
- <td>Backlight<br>On (100 %)</td>
- </tr>
- <tr>
- <td>62</td>
- <td>Input</td>
- <td>Bend</td>
- <td>Not pressed</td>
- <td>Pressed</td>
- </tr>
-</table>
-
-*/
diff --git a/arch/arm/boards/edb93xx/edb93xx.dox b/arch/arm/boards/edb93xx/edb93xx.dox
deleted file mode 100644
index 3964d55367..0000000000
--- a/arch/arm/boards/edb93xx/edb93xx.dox
+++ /dev/null
@@ -1,108 +0,0 @@
-/** @page edb9301 Cirrus Logic EDB9301
-
-This boards is based on a Cirrus Logic EP9301 CPU. The board is shipped with:
-
-- 16MiB NOR type Flash Memory
-- 32MiB synchronous dynamic RAM on CS3
-- 128kiB serial EEPROM
-- MII 10/100 Ethernet PHY
-- Stereo audio codec
-
-*/
-
-/** @page edb9302 Cirrus Logic EDB9302
-
-This board is based on a Cirrus Logic EP9302 CPU. The board is shipped with:
-
-- 16MiB NOR type Flash Memory
-- 32MiB synchronous dynamic RAM on CS3
-- 128kiB serial EEPROM
-- MII 10/100 Ethernet PHY
-- Stereo audio codec
-
-*/
-
-/** @page edb9302a Cirrus Logic EDB9302A
-
-This board is based on a Cirrus Logic EP9302 CPU. The board is shipped with:
-
-- 16MiB NOR type Flash Memory
-- 32MiB synchronous dynamic RAM on CS0
-- 512kiB serial EEPROM
-- MII 10/100 Ethernet PHY
-- Stereo audio codec
-
-*/
-
-/** @page edb9307 Cirrus Logic EDB9307
-
-This board is based on a Cirrus Logic EP9307 CPU. The board is shipped with:
-
-- 32MiB NOR type Flash Memory
-- 64MiB synchronous dynamic RAM on CS3
-- 512kiB asynchronous SRAM
-- 128kiB serial EEPROM
-- MII 10/100 Ethernet PHY
-- Stereo audio codec
-- Real-Time Clock
-- IR receiver
-
-*/
-
-/** @page edb9307a Cirrus Logic EDB9307A
-
-This board is based on a Cirrus Logic EP9307 CPU. The board is shipped with:
-
-- 32MiB NOR type Flash Memory
-- 64MiB synchronous dynamic RAM on CS0
-- 512kiB serial EEPROM
-- MII 10/100 Ethernet PHY
-- Stereo audio codec
-- Real-Time Clock
-- IR receiver
-
-*/
-
-/** @page edb9312 Cirrus Logic EDB9312
-
-This board is based on a Cirrus Logic EP9312 CPU. The board is shipped with:
-
-- 32MiB NOR type Flash Memory
-- 64MiB synchronous dynamic RAM on CS3
-- 512kiB asynchronous SRAM
-- 128kiB serial EEPROM
-- MII 10/100 Ethernet PHY
-- Stereo audio codec
-- Real-Time Clock
-- IR receiver
-
-*/
-
-/** @page edb9315 Cirrus Logic EDB9315
-
-This board is based on a Cirrus Logic EP9315 CPU. The board is shipped with:
-
-- 32MiB NOR type Flash Memory
-- 64MiB synchronous dynamic RAM on CS3
-- 512kiB asynchronous SRAM
-- 128kiB serial EEPROM
-- MII 10/100 Ethernet PHY
-- Stereo audio codec
-- Real-Time Clock
-- IR receiver
-
-*/
-
-/** @page edb9315a Cirrus Logic EDB9315A
-
-This board is based on a Cirrus Logic EP9315 CPU. The board is shipped with:
-
-- 32MiB NOR type Flash Memory
-- 64MiB synchronous dynamic RAM on CS0
-- 128kiB serial EEPROM
-- MII 10/100 Ethernet PHY
-- Stereo audio codec
-- Real-Time Clock
-- IR receiver
-
-*/ \ No newline at end of file
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox
deleted file mode 100644
index 6c2bfede22..0000000000
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox
+++ /dev/null
@@ -1,11 +0,0 @@
-/** @page eukrea_cpuimx27 Eukrea's CPUIMX27
-
-This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with:
-
-- up to 64MiB NOR type Flash Memory
-- up to 256MiB synchronous dynamic RAM
-- up to 512MiB NAND type Flash Memory
-- MII 10/100 ethernet PHY
-- optional 16554 Quad UART on CS3
-
-*/
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.dox b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.dox
deleted file mode 100644
index cbdf69db35..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.dox
+++ /dev/null
@@ -1,4 +0,0 @@
-/** @page eukrea_cpuimx35 Eukrea's CPUIMX35
-
-
-*/
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.dox b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.dox
deleted file mode 100644
index 0f35e174ba..0000000000
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.dox
+++ /dev/null
@@ -1,4 +0,0 @@
-/** @page eukrea_cpuimx51 Eukrea's CPUIMX51
-
-
-*/
diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.dox b/arch/arm/boards/freescale-mx21-ads/imx21ads.dox
deleted file mode 100644
index 9f11ffaa6e..0000000000
--- a/arch/arm/boards/freescale-mx21-ads/imx21ads.dox
+++ /dev/null
@@ -1,5 +0,0 @@
-/** @page imx21ads Freescale i.MX21ads
-
-This is the Freescale evaluation board for the i.MX21 Processor
-
-*/
diff --git a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
index 1eae37722c..9f13fac6dd 100644
--- a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
+++ b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
@@ -144,35 +144,3 @@ static int mx23_evk_console_init(void)
}
console_initcall(mx23_evk_console_init);
-
-/** @page mx23_evk Freescale's i.MX23 evaluation kit
-
-This CPU card is based on an i.MX23 CPU. The card is shipped with:
-
-- 32 MiB synchronous dynamic RAM (mobile DDR type)
-- ENC28j60 based network (over SPI)
-
-Memory layout when @b barebox is running:
-
-- 0x40000000 start of SDRAM
-- 0x40000100 start of kernel's boot parameters
- - below malloc area: stack area
- - below barebox: malloc area
-- 0x41000000 start of @b barebox
-
-@section get_imx23evk_binary How to get the bootloader binary image:
-
-Using the default configuration:
-
-@verbatim
-make ARCH=arm imx23evk_defconfig
-@endverbatim
-
-Build the bootloader binary image:
-
-@verbatim
-make ARCH=arm CROSS_COMPILE=armv5compiler
-@endverbatim
-
-@note replace the armv5compiler with your ARM v5 cross compiler.
-*/
diff --git a/arch/arm/boards/freescale-mx27-ads/imx27ads.dox b/arch/arm/boards/freescale-mx27-ads/imx27ads.dox
deleted file mode 100644
index e14d8e3fab..0000000000
--- a/arch/arm/boards/freescale-mx27-ads/imx27ads.dox
+++ /dev/null
@@ -1,5 +0,0 @@
-/** @page imx27ads Freescale i.MX27ads
-
-This is the Freescale evaluation board for the i.MX27 Processor
-
-*/
diff --git a/arch/arm/boards/freescale-mx35-3ds/3stack.dox b/arch/arm/boards/freescale-mx35-3ds/3stack.dox
deleted file mode 100644
index 15c5b6e1ff..0000000000
--- a/arch/arm/boards/freescale-mx35-3ds/3stack.dox
+++ /dev/null
@@ -1,4 +0,0 @@
-/** @page the3stack Freescale MX35 3-Stack Board
-
-
-*/
diff --git a/arch/arm/boards/freescale-mx51-babbage/mx51-pdk.dox b/arch/arm/boards/freescale-mx51-babbage/mx51-pdk.dox
deleted file mode 100644
index d9ea823e5c..0000000000
--- a/arch/arm/boards/freescale-mx51-babbage/mx51-pdk.dox
+++ /dev/null
@@ -1,4 +0,0 @@
-/** @page board_babage Freescale i.MX51 PDK (Babbage) Board
-
-
-*/
diff --git a/arch/arm/boards/freescale-mx53-qsb/mx53-pdk.dox b/arch/arm/boards/freescale-mx53-qsb/mx53-pdk.dox
deleted file mode 100644
index 3a2c84fc3f..0000000000
--- a/arch/arm/boards/freescale-mx53-qsb/mx53-pdk.dox
+++ /dev/null
@@ -1,4 +0,0 @@
-/** @page board_loco Freescale i.MX53 PDK (Loco) Board
-
-
-*/
diff --git a/arch/arm/boards/freescale-mx53-smd/mx53-smd.dox b/arch/arm/boards/freescale-mx53-smd/mx53-smd.dox
deleted file mode 100644
index 19605088f6..0000000000
--- a/arch/arm/boards/freescale-mx53-smd/mx53-smd.dox
+++ /dev/null
@@ -1,4 +0,0 @@
-/** @page board_loco Freescale i.MX53 SMD Board
-
-
-*/
diff --git a/arch/arm/boards/friendlyarm-mini2440/mini2440.c b/arch/arm/boards/friendlyarm-mini2440/mini2440.c
index 86e22ad131..4034de5a52 100644
--- a/arch/arm/boards/friendlyarm-mini2440/mini2440.c
+++ b/arch/arm/boards/friendlyarm-mini2440/mini2440.c
@@ -16,12 +16,6 @@
*
*/
-/**
- * @file
- * @brief mini2440 Specific Board Initialization routines
- *
- */
-
#include <common.h>
#include <driver.h>
#include <init.h>
@@ -338,156 +332,3 @@ static int mini2440_console_init(void)
}
console_initcall(mini2440_console_init);
-
-/** @page mini2440 FriendlyARM's mini2440
-
-This system is based on a Samsung S3C2440 CPU. The card is shipped with:
-
-- S3C2440\@400 MHz or 533 MHz (ARM920T/ARMv4T)
-- 12 MHz crystal reference
-- 32.768 kHz crystal reference
-- SDRAM 64 MiB (one bank only)
- - HY57V561620 (two devices for 64 MiB to form a 32 bit bus)
- - 4M x 16bit x 4 Banks Mobile SDRAM
- - 8192 refresh cycles / 64 ms
- - CL2\@100 MHz
- - 133 MHz max
- - collumn address size is 9 bits
- - row address size is 13 bits
- - MT48LC16M16 (two devices for 64 MiB to form a 32 bit bus)
- - 4M x 16bit x 4 Banks Mobile SDRAM
- - commercial & industrial type
- - 8192 refresh cycles / 64 ms
- - CL2\@100 MHz
- - 133 MHz max
- - collumn address size is 9 bits
- - row address size is 13 bits
-- NAND Flash 128MiB...1GiB
- - K9Fxx08
-- NOR Flash (up to 22 address lines available)
- - AM29LV160DB, 2 MiB
- - SST39VF1601, 2 MiB
- - 16 bit data bus
-- SD card interface, 3.3V (fixed voltage)
-- Host and device USB interface, USB1.1 compliant
-- UDA1341TS Audio
-- DM9000 Ethernet interface
- - uses CS#4
- - uses EINT7
- - 16 bit data bus
-- I2C interface, 100 KHz and 400 KHz
- - EEPROM
- - ST M24C08
- - address 0x50
-- Speaker on GPB0 ("low" = inactive)
-- LCD interface
-- Touch Screen interface
-- Camera interface
-- I2S interface
-- AC97 Audio-CODEC interface
-- three serial RS232 interfaces (one with level converter)
-- SPI interface
-- JTAG interface
-
-How to get the binary image:
-
-Using the default configuration:
-
-@code
-make ARCH=arm mini2440_defconfig
-@endcode
-
-Build the binary image:
-
-@code
-make ARCH=arm CROSS_COMPILE=armv4compiler
-@endcode
-
-@note replace the armv4compiler with your ARM v4 cross compiler.
-
-How to bring in \a barebox ?
-
-First run it as a second stage bootloader. There are two known working ways to
-do so:
-
-One way is to use the "device firmware update" feature of the 'supervivi'.
- - connect a terminal application to the mini2440's serial connector
- - switch S2 to 'boot from NOR' to boot into 'supervivi'
- - connect your host to the usb device connector on the mini2440
- - switch on your mini2440
- - in 'supervivi' type q (command line) then:
-@code
-load ram 0x31000000 \<barebox-size\> u
-@endcode
- - use a tool for DFU update (for example from openkomo) to transfer the 'barebox.bin' binary
- - then in 'supervivi' just run
-@code
-go 0x31000000
-@endcode
-
-A second way is to use any kind of JTAG adapter. For this case I'm using the
-'JTAKkey tiny' from Amontec and OpenOCD. First you need an adapter for this
-kind of Dongle as it uses a 20 pin connector with 2.54 mm grid, and the
-mini2440 uses a 10 pin connector with 2 mm grid.
-
-@code
- Amontec JTAGkey tiny mini2440
- -------------------------------------------------------
- VREF 1 2 n.c. VREF 1 2 VREF
- TRST_N 3 4 GND TRST_N 3 4 SRST_N
- TDI 5 6 GND TDI 5 6 TDO
- TMS 7 8 GND TMS 7 8 GND
- TCK 9 10 GND TCK 9 10 GND
- n.c. 11 12 GND
- TDO 13 14 GND
- SRST_N 15 16 GND
- n.c. 17 18 GND
- n.c. 19 20 GND
-@endcode
-
-Create a simple board description file. I did it this way:
-
-@code
-source [find interface/jtagkey-tiny.cfg]
-source [find target/samsung_s3c2440.cfg]
-
-adapter_khz 12000
-@endcode
-
-And then the following steps:
- - connect a terminal application to the mini2440's serial connector
- - connect the mini2440 to a working network
- - switch S2 to boot from NOR to boot into 'supervivi'
- - switch on your mini2440
- - run the OpenOCD daemon configured with the file shown above
- - connect to the OpenOCD daemon via 'telnet'.
- - run the following commands to download @a barebox into your target
-@code
-> halt
-> load_image \<path to the 'barebox.bin'\> 0x31000000 bin
-> resume 0x31000000
-@endcode
-
-Now @a barebox is starting from an already initialized CPU and SDRAM (done by
-'supervivi').
-
-Change to your terminal console and configure the network first. Adapt the
-following settings to your network:
-@code
-eth0.ipaddr=192.168.1.240
-eth0.netmask=255.255.255.0
-eth0.gateway=192.168.23.2
-eth0.serverip=192.168.1.7
-eth0.ethaddr=00:04:f3:00:06:35
-@endcode
-
-A 'ping' to your TFTP server should bring a "...is alive" message now.
-
-We are ready now to program @a barebox into the NAND flash:
-
-@code
-erase /dev/nand0.barebox.bb
-tftp barebox.bin /dev/nand0.barebox.bb
-@endcode
-
-*/
diff --git a/arch/arm/boards/guf-cupid/cupid.dox b/arch/arm/boards/guf-cupid/cupid.dox
deleted file mode 100644
index 45f0e0cc22..0000000000
--- a/arch/arm/boards/guf-cupid/cupid.dox
+++ /dev/null
@@ -1,9 +0,0 @@
-/** @page board_cupid Garz+Fricke Cupid
-
-This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with:
-
-- 256MiB Nand flash
-- 128MiB synchronous dynamic RAM
-
-
-*/
diff --git a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c
index fae4d91469..fa95d72339 100644
--- a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c
+++ b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c
@@ -143,62 +143,3 @@ static int imx23_olinuxino_console_init(void)
}
console_initcall(imx23_olinuxino_console_init);
-
-/** @page olinuxino Olimex.ltd's i.MX23 evaluation kit
-
-This CPU card is based on an i.MX23 CPU. The card is shipped with:
-
-- 64 MiB synchronous dynamic RAM (mobile DDR type)
-
-
-Memory layout when @b barebox is running:
-
-- 0x40000000 start of SDRAM
-- 0x40000100 start of kernel's boot parameters
- - below malloc area: stack area
- - below barebox: malloc area
-- 0x42000000 start of @b barebox
-
-@section get_imx23_olinuxino_binary How to get the bootloader binary image:
-
-Using the default configuration:
-
-@verbatim
-make ARCH=arm imx23_olinuxino_defconfig
-@endverbatim
-
-Build the bootloader binary image:
-
-@verbatim
-make ARCH=arm CROSS_COMPILE=armv5compiler
-@endverbatim
-
-@note replace the armv5compiler with your ARM v5 cross compiler.
-
-@section imx233-olinuxino How to prepare an MCI card to boot
-the imx233-olinuxino with barebox
-
-- Create four primary partitions on the MCI card
- - the first one for the bootlets (about 256 kiB)
- - the second one for the persistant environment
- (size is up to you, at least 256k)
- - the third one for the kernel (2 MiB ... 4 MiB in size)
- - the 4th one for the root filesystem which can fill the
- rest of the available space
-
-- Mark the first partition with the partition ID "53" and copy the bootlets
- into this partition (currently not part of @b barebox!).
-
-- @b barebox expect device tree blob file imx23-olinuxino.dtb
- into directory env/oftree. At compile time, copy blob file into directory
- arch/arm/boards/imx233-olinuxino/env/oftree/.
-
-- Copy the default @b barebox environment into the second partition
- (no filesystem required).
-
-- Copy the kernel into the third partition (no filesystem required).
-
-- Create the root filesystem in the 4th partition. You may copy an
- image into this partition or you can do it in the classic way:
- mkfs on it, mount it and copy all required data and programs into it.
-*/
diff --git a/arch/arm/boards/karo-tx28/tx28.c b/arch/arm/boards/karo-tx28/tx28.c
index 3fb1fe9177..26dbc00790 100644
--- a/arch/arm/boards/karo-tx28/tx28.c
+++ b/arch/arm/boards/karo-tx28/tx28.c
@@ -99,55 +99,3 @@ static int tx28_devices_init(void)
}
device_initcall(tx28_devices_init);
-
-/**
-@page tx28 KARO's TX28 CPU module
-
-@section tx28_cpu_card The CPU module
-
-http://www.karo-electronics.de/
-
-This CPU card is based on a Freescale i.MX28 CPU. The card is shipped with:
-
-- 128 MiB synchronous dynamic RAM (DDR2 type), 200 MHz support
-- 128 MiB NAND K9F1G08U0A (3.3V type)
-- PCA9554 GPIO expander
-- DS1339 RTC
-- LAN8710 Phy
-
-@section tx28_basboards Supported baseboards
-
-Supported baseboards are:
-- KARO's Starterkit 5
-
-@section tx28_stk5_howto How to get barebox for 'KARO's Starterkit 5'
-
-Using the default configuration:
-
-@verbatim
-make ARCH=arm tx28stk5_defconfig
-@endverbatim
-
-Build the binary image:
-
-@verbatim
-make ARCH=arm CROSS_COMPILE=armv5compiler
-@endverbatim
-
-@note replace the armv5compiler with your ARM v5 cross compiler.
-
-@note To use the result, you also need the following resources from Freescale:
-- the 'bootlets' archive
-- the 'elftosb2' encryption tool
-- in the case you want to start @b barebox from an attached SD card the
- 'sdimage' tool from Freescale's 'uuc' archive.
-
-@section tx28_mlayout Memory layout when barebox is running:
-
-- 0x40000000 start of SDRAM
-- 0x40000100 start of kernel's boot parameters
- - below malloc area: stack area
- - below barebox: malloc area
-- 0x47000000 start of @b barebox
-
-*/
diff --git a/arch/arm/boards/karo-tx51/tx51.dox b/arch/arm/boards/karo-tx51/tx51.dox
deleted file mode 100644
index 08268e0576..0000000000
--- a/arch/arm/boards/karo-tx51/tx51.dox
+++ /dev/null
@@ -1,50 +0,0 @@
-/**
-@page tx51 KARO's TX51 CPU module
-
-@section tx51_cpu_card The CPU module
-
-http://www.karo-electronics.de/
-
-This CPU card is based on a Freescale i.MX51 CPU. The card is shipped with:
-
-- 128 MiB synchronous dynamic RAM (DDR2 type), 200 MHz support
-- 128 MiB NAND K9F1G08U0A (3.3V type)
-- DS1339 RTC
-- LAN8700 Phy
-
-@section tx51_baseboards Supported baseboards
-
-Supported baseboards are:
-- KARO's Starterkit 5 (currently only SD1, FEC implemented but non-working)
-
-@section tx28_stk5_howto How to get barebox for 'KARO's Starterkit 5'
-
-Using the default configuration:
-
-@verbatim
-make ARCH=arm tx51tk5_defconfig
-@endverbatim
-
-Build the binary image:
-
-@verbatim
-make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi-
-@endverbatim
-
-@note replace the arm-linux-gnueabi with your ARM v7 cross compiler.
-
-@note To use the result, you also need the following resources from Freescale:
-- the 'bootlets' archive
-- the 'elftosb2' encryption tool
-- in the case you want to start @b barebox from an attached SD card the
- 'sdimage' tool from Freescale's 'uuc' archive.
-
-@section tx28_mlayout Memory layout when barebox is running:
-
-- 0x90000000 start of SDRAM
-- 0x90000100 start of kernel's boot parameters
- - below malloc area: stack area
- - below barebox: malloc area
-- 0x97f00000 start of @b barebox
-
-*/
diff --git a/arch/arm/boards/module-mb7707/module-mb7707.dox b/arch/arm/boards/module-mb7707/module-mb7707.dox
deleted file mode 100644
index c0dbc8a602..0000000000
--- a/arch/arm/boards/module-mb7707/module-mb7707.dox
+++ /dev/null
@@ -1,29 +0,0 @@
-/** @page module-mb7707 MB 77.07 board
-
-The board uses MBOOT as bootloader.
-
-Barebox mini-howto:
-
-1. Connect to the boards's UART (38400 8N1);
-
-2. Turn board's power on;
-
-3. Wait 'Hit any key (in 2 sec) to skip autoload...' prompt and press the space key;
-
-4. Compile zbarebox.bin image and upload it to the board via tftp
-@verbatim
- MBOOT # tftpboot zbarebox.bin
- greth: greth_halt
- TFTP Using GRETH_10/100 device
- TFTP params: server 192.168.0.1 our_ip 192.168.0.7
- TFTP params: filename 'zbarebox.bin' load_address 0x40100000
- TFTP Loading: ################
- TFTP done
-@endverbatim
-
-5. Run barebox
-@verbatim
- MBOOT # go 0x40100000
-@endverbatim
-
-*/
diff --git a/arch/arm/boards/mx31moboard/mx31moboard.dox b/arch/arm/boards/mx31moboard/mx31moboard.dox
deleted file mode 100644
index 41c8bbb828..0000000000
--- a/arch/arm/boards/mx31moboard/mx31moboard.dox
+++ /dev/null
@@ -1,10 +0,0 @@
-/** @page mx31moboard EPFL mx31moboard
-
-This CPU card is based on a Freescale i.MX31 CPU. The card is shipped with:
-
-- 32MiB NOR type Flash Memory
-- 128MiB LPDDR
-- A least one SD slot
-- A least one USB host (H2)
-
-*/
diff --git a/arch/arm/boards/netx/netx.dox b/arch/arm/boards/netx/netx.dox
deleted file mode 100644
index e22c5e8554..0000000000
--- a/arch/arm/boards/netx/netx.dox
+++ /dev/null
@@ -1,9 +0,0 @@
-/** @page netx Hilscher's NetX card family
-
-This CPU card is based on a Hilscher's NetX ARM CPU. The card is shipped
-in various incarnations:
-
-Specific to this CPU is, it does not require any setup code to bring the
-SDRAM up and working. This is done in a pre bootloader.
-
-*/ \ No newline at end of file
diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c
index 8329ace483..1b1cb79212 100644
--- a/arch/arm/boards/omap343xdsp/board.c
+++ b/arch/arm/boards/omap343xdsp/board.c
@@ -15,32 +15,6 @@
*
*/
-/**
- * @file
- * @brief SDP3430 Specific Board Initialization routines
- */
-
-/**
- * @page ti_SDP3430 Texas Instruments SDP3430
- *
- * SDP3430 from Texas Instruments as described here:
- * http://www.ti.com/omap3430_devplatform
- * This file provides initialization in two stages:
- * @li boot time initialization - do basics required to get SDRAM working.
- * This is run from SRAM - so no case constructs and global vars can be used.
- * @li run time initialization - this is for the rest of the initializations
- * such as flash, uart etc.
- *
- * Boot time initialization includes:
- * @li SDRAM initialization.
- * @li Pin Muxing relevant for SDP3430.
- *
- * Run time initialization includes
- * @li serial @ref serial_ns16550.c driver device definition
- *
- * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
- */
-
#include <common.h>
#include <console.h>
#include <init.h>
diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.dox b/arch/arm/boards/phytec-phycard-imx27/pca100.dox
deleted file mode 100644
index 9b17674a21..0000000000
--- a/arch/arm/boards/phytec-phycard-imx27/pca100.dox
+++ /dev/null
@@ -1,8 +0,0 @@
-/** @page pcm038 Phytec's phyCORE-i.MX27
-
-This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with:
-
-- up to 32MiB NOR type Flash Memory
-- 32MiB synchronous dynamic RAM
-
-*/
diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.dox b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.dox
deleted file mode 100644
index d93c57499b..0000000000
--- a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.dox
+++ /dev/null
@@ -1,16 +0,0 @@
-/** @page phycard-a-l1 Phytec's phyCARD-A-L1 (OMAP35xx)
-
-This phyCARD is based on a Texas Instruments OMAP35xx CPU.
-The card is shipped with:
-
-- 256MiB DDR-RAM
-- 256MiB NAND Flash Memory
-- SMSC9221 ethernet controller
-- USB-host interface
-- USB-OTG interface
-- LVDS camera interface
-- LVDS display interface
-- TPS65023 Power-Managmanet IC
-- 4kB I2C EEPROM
-
-*/
diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm038.dox b/arch/arm/boards/phytec-phycore-imx27/pcm038.dox
deleted file mode 100644
index 85177d2eb1..0000000000
--- a/arch/arm/boards/phytec-phycore-imx27/pcm038.dox
+++ /dev/null
@@ -1,9 +0,0 @@
-/** @page pcm038 Phytec's phyCORE-i.MX27
-
-This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with:
-
-- up to 64MB NOR Flash Memory
-- up to 1GB NAND Flash Memory
-- up to 256MB DRAM
-
-*/
diff --git a/arch/arm/boards/phytec-phycore-imx31/pcm037.dox b/arch/arm/boards/phytec-phycore-imx31/pcm037.dox
deleted file mode 100644
index b2afdd6acd..0000000000
--- a/arch/arm/boards/phytec-phycore-imx31/pcm037.dox
+++ /dev/null
@@ -1,11 +0,0 @@
-/** @page pcm037 Phytec's phyCORE-i.MX31
-
-This CPU card is based on a Freescale i.MX31 CPU. The card is shipped with:
-
-- up to 64MiB NOR type Flash Memory
-- up to 2MiB static RAM
-- 64MiB NAND type Flash Memory
-- SMSC 9217 network controller
-- 128MiB synchronous dynamic RAM
-
-*/
diff --git a/arch/arm/boards/phytec-phycore-imx35/pcm043.dox b/arch/arm/boards/phytec-phycore-imx35/pcm043.dox
deleted file mode 100644
index c6715fffcf..0000000000
--- a/arch/arm/boards/phytec-phycore-imx35/pcm043.dox
+++ /dev/null
@@ -1,28 +0,0 @@
-/** @page pcm043 Phytec's phyCORE-i.MX35
-
-This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with:
-
-
-FIXME:
-- up to 64 MiB NOR type Flash Memory
-- up to 2 MiB static RAM
-- 1 GiB or 2 GiB NAND type Flash Memory
- - Micron NAND 1 GiB 3,3V 8-bit
- - 256 kiB block size
- - ? kiB page size
- - Manufacturer ID: 0x2c
- - Device ID: 0xd3
- - Samsung K9K8G08, 1 GiB
- - 128 kiB block size
- - 2 kiB page size
- - Manufacturer ID: ?
- - Device ID: ?
- - ST NAND08G, 1 GiB
- - 128 kiB block size
- - 2 kiB page size
- - Manufacturer ID: ?
- - Device ID: ?
-- 128MiB synchronous dynamic RAM
-
-
-*/
diff --git a/arch/arm/boards/qil-a926x/qil-a9260.dox b/arch/arm/boards/qil-a926x/qil-a9260.dox
deleted file mode 100644
index da5c197b34..0000000000
--- a/arch/arm/boards/qil-a926x/qil-a9260.dox
+++ /dev/null
@@ -1,22 +0,0 @@
-/**
-@page qil-a9260 Calao-systems QIL-A9260
-
-@section qil-a9260 The CPU module
-
-http://www.calao-systems.com
-
-This CPU module is based on an Atmel AT91SAM9260 CPU. The card is shipped with:
-
-- 64MiB or 128MiB SDRAM (3.3V)
-- 256MiB NAND type Flash Memory (3.3V)
-- 64Kib SPI EEPROM
-- RMII 10/100 ethernet PHY
-- Real Time Clock
-- micro SD socket
-
-@section mob-qil-a9xxx Supported development board
-
-Supported development board is:
-- MOB-QIL-A9xxx
-
-*/
diff --git a/arch/arm/boards/scb9328/scb9328.dox b/arch/arm/boards/scb9328/scb9328.dox
deleted file mode 100644
index 75bc7c8c1a..0000000000
--- a/arch/arm/boards/scb9328/scb9328.dox
+++ /dev/null
@@ -1,9 +0,0 @@
-/** @page scb9328 Synertronixx's scb9328
-
-This CPU card is based on a Freescale i.MX1 CPU. The card is shipped with:
-
-- up to 16MiB NOR type Flash Memory
-- 16MiB synchronous dynamic RAM
-- DM9000 network controller
-
-*/
diff --git a/arch/arm/boards/tny-a926x/tny-a9263.dox b/arch/arm/boards/tny-a926x/tny-a9263.dox
deleted file mode 100644
index 68fcdd109c..0000000000
--- a/arch/arm/boards/tny-a926x/tny-a9263.dox
+++ /dev/null
@@ -1,33 +0,0 @@
-/**
-@page tny-a9263 Calao-systems TNY-A9263
-
-@section tny-a9263 The CPU module
-
-http://www.calao-systems.com
-
-This CPU module is based on an Atmel AT91SAM9263 CPU. The module is shipped with:
-
-- 64MiB SDRAM (3.3V)
-- 256MiB NAND type Flash Memory (3.3V)
-- USB device port
-- Top expansion connector for daughter boards (GPS, WIFI/BT, GPRS, 3G, ZigBee, MBUS, ...)
-- Bottom expansion connector for development boards
-
-@section mob-tny-a9xxx-md2 Supported development board
-
-Supported development board is:
-- MOB-TNY-A9xxx-MD2
-
-@section tny-db-boards Supported daughter boards
-
-Supported daughter boards are:
-- DAB-GPI2-CXX
-- DAB-GPS
-- DAB-GPRS
-- DAB-HSDPA
-- DAB-WLAN-BT
-- DAB-ZIGBEE
-- DAB-MBUS
-- DAB-KNX-RF
-
-*/
diff --git a/arch/arm/boards/tny-a926x/tny-a9g20-lpw.dox b/arch/arm/boards/tny-a926x/tny-a9g20-lpw.dox
deleted file mode 100644
index e0021070b3..0000000000
--- a/arch/arm/boards/tny-a926x/tny-a9g20-lpw.dox
+++ /dev/null
@@ -1,37 +0,0 @@
-/**
-@page tny-a9g20-lpw Calao-systems TNY-A9G20-LPW
-
-@section tny-a9g20-lpw The CPU module
-
-http://www.calao-systems.com
-
-This CPU module is based on an Atmel AT91SAM9G20 CPU. The module is shipped with:
-
-- 64MiB Low Power SDRAM (1.8V)
-- 256MiB NAND type Flash Memory (1.8V)
-- Real Time Clock (I2C)
-- Micro SD socket
-- USB device port
-- JTAG connector
-- Top expansion connector for daughter boards (GPS, WIFI/BT, GPRS, 3G, ZigBee, MBUS, ...)
-- Bottom expansion connector for development boards
-
-@section mob-tny-a9xxx-md2 Supported development board
-
-Supported development board is:
-- MOB-TNY-A9xxx-MD2
-
-@section tny-db-boards Supported daughter boards
-
-Supported daughter boards are:
-- DAB-GPI2-CXX
-- DAB-GPS
-- DAB-GPRS
-- DAB-HSDPA
-- DAB-WLAN-BT
-- DAB-ZIGBEE
-- DAB-MBUS
-- DAB-KNX-RF
-
-
-*/
diff --git a/arch/arm/boards/toshiba-ac100/toshiba-ac100.dox b/arch/arm/boards/toshiba-ac100/toshiba-ac100.dox
deleted file mode 100644
index 7c50f3c1d9..0000000000
--- a/arch/arm/boards/toshiba-ac100/toshiba-ac100.dox
+++ /dev/null
@@ -1,37 +0,0 @@
-/** @page toshiba-ac100 Toshiba AC100
-
-Toshiba AC100 is a Tegra2-based netbook.
-
-The netbook has
-@li NVidia Tegra 250 SoC;
-@li 512 MiB DDR2 RAM;
-@li 8 GiB internal e-MMC Flash Memory (some models have 32 GiB);
-@li RS232 serial interface (LV-TTL levels on the board!);
-@li SD card slot;
-@li 2xUSB interface (miniUSB-B and USB-A connectors);
-@li 10" LCD display (1024x600);
-@li HDMI-interface;
-@li touchpad and keyboard connected via I2C; the ENE KB926QF keyboard controller is used;
-@li web camera;
-@li some models have 3G-modem.
-
-U-Boot master branch is working on AC100, but there's no support for the keyboard or the display.
-
-barebox-toshiba-ac100 mini-howto:
-
-1. Connect to the netbook's UART (see http://pecourt.ovh.org/wiki-tegra/doku.php?id=hardware);
-
-2. Start U-Boot loader. See http://ac100.grandou.net/uboot and http://ac100.grandou.net/swarren_brain_dump for details.
-
-3. If you use U-Boot with turned on display support, then switch to serial console:
-@verbatim
- Tegra2 (ac100) # setenv stdout serial
-@endverbatim
-
-4. Upload barebox.bin via Ymodem and start it:
-@verbatim
- Tegra2 (ac100) # loady 0x01f00000
- Tegra2 (ac100) # go 0x01f00000
-@endverbatim
-
-*/
diff --git a/arch/arm/boards/usb-a926x/usb-a9263.dox b/arch/arm/boards/usb-a926x/usb-a9263.dox
deleted file mode 100644
index 380a8e2d3d..0000000000
--- a/arch/arm/boards/usb-a926x/usb-a9263.dox
+++ /dev/null
@@ -1,30 +0,0 @@
-/**
-@page usb-a9263 Calao-systems USB-A9263
-
-@section usb-a9263 The CPU card
-
-http://www.calao-systems.com
-
-This CPU card is based on an Atmel AT91SAM9263 CPU. The card is shipped with:
-
-- 64MiB or 128MiB SDRAM (3.3V)
-- 256MiB NAND type Flash Memory (3.3V)
-- Ethernet 10/100M
-- USB Host port 2.0 (FS)
-- USB device port (FS)
-- Top expansion connector for expansion boards (GPS, WIFI/BT, GPRS, 3G, ZigBee, MBUS, ...)
-- Bottom expansion connector for development boards
-
-@section usb-db-boards Supported daughter boards
-
-Supported daughter boards are:
-- DAB-GPI2-CXX
-- DAB-GPS
-- DAB-GPRS
-- DAB-HSDPA
-- DAB-WLAN-BT
-- DAB-ZIGBEE
-- DAB-MBUS
-- DAB-KNX-RF
-
-*/
diff --git a/arch/arm/boards/usb-a926x/usb-a9g20-lpw.dox b/arch/arm/boards/usb-a926x/usb-a9g20-lpw.dox
deleted file mode 100644
index 024a3cedda..0000000000
--- a/arch/arm/boards/usb-a926x/usb-a9g20-lpw.dox
+++ /dev/null
@@ -1,33 +0,0 @@
-/**
-@page usb-a9g20-lpw Calao-systems USB-A9G20-LPW
-
-@section usb-a9g20-lpw The CPU card
-
-http://www.calao-systems.com
-
-This CPU card is based on an Atmel AT91SAM9G20 CPU. The card is shipped with:
-
-- 64MiB or 128MiB SDRAM (1.8V)
-- 256MiB NAND type Flash Memory (1.8V)
-- Ethernet 10/100M
-- USB Host port 2.0 (FS)
-- USB device port (FS)
-- Micro SD socket
-- JTAG connector
-- RTC with battery backup
-- Top expansion connector for daughter boards (GPS, WIFI/BT, GPRS, 3G, ZigBee, MBUS, ...)
-- Bottom expansion connector for development boards
-
-@section usb-db-boards Supported daughter boards
-
-Supported daughter boards are:
-- DAB-GPI2-CXX
-- DAB-GPS
-- DAB-GPRS
-- DAB-HSDPA
-- DAB-WLAN-BT
-- DAB-ZIGBEE
-- DAB-MBUS
-- DAB-KNX-RF
-
-*/
diff --git a/arch/arm/boards/virt2real/virt2real.dox b/arch/arm/boards/virt2real/virt2real.dox
deleted file mode 100644
index fc383216ec..0000000000
--- a/arch/arm/boards/virt2real/virt2real.dox
+++ /dev/null
@@ -1,41 +0,0 @@
-/** @page virt2real virt2real board
-
-virt2real is a is a miniature board for creation of WiFi
-or internet controllable smart devices.
-
-The board has
-@li TI DaVinchi DM365 running at 300 MHz
-@li 128 MiB DDR2 SDRAM;
-@li 256 MiB NAND Flash Memory;
-@li 2 x UART serial interfaces;
-@li 2 x Ethernet interfaces;
-@li 1 x USB interface;
-@li microSD card slot.
-
-The board uses U-Boot as bootloader.
-
-Barebox mini-howto:
-
-1. Connect to the boards's UART0 (115200 8N1);
-Use J2.2 (GND), J2.4 (UART0_TXD), J2.6(UART0_RXD) pins.
-
-2. Turn board's power on;
-
-3. Wait 'Hit any key to stop autoboot' prompt and press the space key.
-
-4. Upload barebox.bin via Ymodem
-@verbatim
- virt2real ># loady
-@endverbatim
-
-5. Run barebox
-@verbatim
- virt2real ># go 0x82000000
-@endverbatim
-
-virt2real links:
-@li http://virt2real.com/
-@li http://wiki.virt2real.ru/
-@li https://github.com/virt2real
-
-*/
diff --git a/arch/arm/mach-arm.dox b/arch/arm/mach-arm.dox
deleted file mode 100644
index 1d2de48df2..0000000000
--- a/arch/arm/mach-arm.dox
+++ /dev/null
@@ -1,67 +0,0 @@
-/* This document is intended to provide the developer with information
- * how to integrate a new CPU (MACH) into this part of the barebox tree
- */
-
-/** @page dev_arm_mach ARM based CPU (MACH) into the tree
-
-FIXME
-
-@section mach_arm_reset What's happens when the reset signal is gone
-
-@note Code running immediately after reset runs at an address it is not linked
- to: "runtime address != link address". You should only use branches and
- do not refer to fixed data. This implies the use of assembler code only.
-
-The ARM CPU starts at lable \<reset\> in one of the corresponding start-*.S
-files. After some basic hardware setup it can call a function
-\<arch_init_lowlevel\> if not disabled. This call is intended to give all
-developers a chance to use a standard reset vector file, but also do some
-special things required only on their specific CPU.
-
-After handling some MMU related things \<board_init_lowlevel\> can be called (if
-not disabled). This is a board specific function for SDRAM setup for example.
-As its board specific, your can do whatever you need to bring your board up.
-
-In the case the boot happens from NAND flash memory, further steps are required.
-Most of the known processor devices are reading the first few blocks from the
-NAND flash memory into some kind of internal SRAM. This small part must be able
-to initialize the SDRAM controller and to read the remaining rest of the
-barebox binary from the NAND flash memory prior returning from \<board_init_lowlevel\>.
-
-When \<board_init_lowlevel\> returns it will be assumed there is now a working
-RAM that can be used for all further steps.
-
-Next step is relocation of @a barebox itself (if not already done). It gets copied
-to RAM and the last assembler instruction is a jump into start_barebox(). This
-target address is the first C instruction in barebox. At this point of time:\n
-"runtime address == link address".
-
-@section mach_arm_files List of changes
-
-Lets call the new MACH new_cpu.
-
- - create a new subdirectory in /arch/arm/mach-new_cpu
- - create a new subdirectory in /arch/arm/mach-new_cpu/include
- - add CPU specific definitions into /arch/arm/mach-new_cpu/include
- - add /arch/arm/mach-new_cpu/Kconfig
- - add /arch/arm/mach-new_cpu/Makfile
- - add other CPU specific code into /arch/arm/mach-new_cpu/
- - modify /arch/arm/Kconfig
- - modify /arch/arm/Makfile
-
-@section mach_arm_architecures Architectures using ARM processors
-For details on specific architectures:
-
-@subsection mach_arm_omap_info OMAP CPUs
-
-@li @subpage dev_davinci_arch
-
-@li @subpage dev_omap_arch
-
-@subsection mach_arm_s3c24xx_info S3C24XX CPUs
-
-@li @subpage dev_s3c24xx_arch
-
-TODO add more details
-
-*/
diff --git a/arch/arm/mach-davinci/mach-davinci.dox b/arch/arm/mach-davinci/mach-davinci.dox
deleted file mode 100644
index 789eacc42a..0000000000
--- a/arch/arm/mach-davinci/mach-davinci.dox
+++ /dev/null
@@ -1,7 +0,0 @@
-/** @page dev_davinci_arch TI DaVinci in barebox
-
-@section davinci_boards DaVinci-based boards
-
-@li @subpage virt2real
-
-*/
diff --git a/arch/arm/mach-omap/arch-omap.dox b/arch/arm/mach-omap/arch-omap.dox
deleted file mode 100644
index 8c2b47d5a8..0000000000
--- a/arch/arm/mach-omap/arch-omap.dox
+++ /dev/null
@@ -1,96 +0,0 @@
-/* This document is intended to provide the developer with information
- * how to integrate a new OMAP Architecture into this part of the barebox tree
- */
-
-/** @page dev_omap_arch Texas Instrument's OMAP Platforms in barebox
-
-This document highlights some of the factors for supporting Texas Instrument's OMAP platforms in @a barebox.
-
-@par Table of Contents
-@li @ref omap_boards
-@li @ref omap_code_arch
-@li @ref mach_omap
-@li @ref asm_arm
-@li @ref board_omap
-@li @ref omap_boot
-@li @ref board_boot
-
-@section omap_boards Boards using OMAP processors
-
-@li @subpage ti_SDP3430
-@li @subpage ti_beagle
-
-@section omap_arch Documentation for OMAP Architectures files
-
-@li @subpage arch/arm/mach-omap/omap3_generic.c
-
-@section omap_code_arch How is barebox OMAP specific architecture code organized?
-
-To understand the architecture of @a barebox source code for OMAP processors, we need to understand a bit on OMAP itself.
-
-A typical Texas Instrument's Open Multimedia Application Processor (OMAP) solution is built around ARM core with multiple on-the-silicon peripherals. It also has a TI Digital Signal Processor(DSP) and few hardware accelerators to cater to computing intensive applications such as encoder/decoders. See http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&navigationId=11988&contentId=4638 for further details.
-
-Essentially, OMAP is modular with on-silicon peripherals being reused across multiple OMAP versions. @a Barebox code organization is driven by this fact.
-
-Motivation for code organization is driven from:
-@li Clear distinction between architecture and board features.
-@li Code should be re-usable accross OMAP variants AND board variants.
-
-Code is Organized into three main directories:
-@li arch/arm/mach-omap -contains files for ALL peripherals which are present on board with very few exceptions. We will come to these exceptions in later sections.
-@li include/asm-arm/arch-omap - contains files for ALL OMAP on-silicon peripherals. No Board specific files here please!
-@li arch/arm/boards/omap - contains files for ALL boards using OMAP processors.
-
-@section mach_omap arch/arm/mach-omap directory guidelines
-It is rather simple: All common peripherals should be isolated as separate driver libraries as far as possible. Exceptions such as clock configuration code may be isolated by the following naming convention: omapX_function_name.[cS], where X belongs to the OMAP variant. The exception is for devices who have existing code locations - potentially drivers/i2c/busses and the like.
-
-All basic devices you'd like to register should be put here with postcore_initcall from architecture files
-
-@section asm_arm include/asm-arm/arch-omap directory guidelines
-All OMAP common headers are located here. Where we have to incorporate a OMAP variant specific header, add a omapX_function_name.h.
-@warning Do not add board specific header files/information here. Put them in mach-omap.
-
-include/asm-arm/arch-omap/silicon.h contains includes for omapX-silicon.h which defines the base addresses for the peripherals on that platform. the usual convention is to use
-@code
-#define OMAP_SOMETHING_BASE
-@endcode
-to allow re-use.
-
-@section board_omap arch/arm/boards/omap directory guidelines
-All Board specific files go here. In u-boot, we always had to use common config file which is shared by other drivers to get serial, ethernet baseaddress etc.. we can easily use the device_d structure to handle it with @a barebox. This is more like programming for Linux kernel - it is pretty easy.
-Each specific board file has board-XYZ.c and potentially and equivalent h file.
-
-We'd potentially use device_initcall and console_initcalls as required.
-
-@section omap_boot The OMAP boot path
-The normal flow is to look for arch_init_lowlevel in the required code. This would be the first function to be called after the ARM common code boots up(arch/arm/cpu/start-arm.S), the job of boot code on OMAP platform would be to preventing watchdog timer from kicking in and spoiling all the fun, setup OMAP clocks to the high performance mode, do other architecture specific initializations. There could be some additional stuff we may need to do based on the specific OMAP we support including setting up a usable interrupt vector table etc - some parts of the code may be desired to be in C code (to let normal humans understand without being an asm junkie), in such a case, @a barebox's stack setup is not ready yet, and we may need to setup a temporary SRAM based stack prior to execution. Some things to keep in mind while handling booting code, we might be executing in eXecute In Place (XIP) mode and that only an SRAM stack is setup. Using global variables or using constructs that create function jump tables is doomed to fail as the required area might not be writable or may not be even initialized. So code in this area tends to use lots of if conditions and local variables. Having C code doing the fun part is easy to maintain, so it is advisable to push as much as possible to C functions where possible.
-
-The responsibility of arch_init_lowlevel and related calls is to setup OMAP. No board specific initializations are to be done here.
-
-Once this is past, the code returns back to arm common code (cpu/start-arm.S). Here Instruction and Data caches are disabled. The execution proceeds to normal board initialization.
-
-@section board_boot The board boot path
-Every Board in OMAP platform can potentially define a board_init and enable defconfig in arch/arm/configs directory. The responsibility here is to setup OMAP for board configurations - this includes SDRAM configuration and pin muxing configuration.
-
-Once this is complete, @a barebox boot process proceeds by calling init functions and finally entering shell prompt
-
-board-XYZ file may potentially register every device it is interested in. You can check out how the code is organized in other board directories also, esentially, the method is as simple as:
-@code
-static struct device_d my_little_device = {
- .name = "driver_name",
- .id = "some_unique_id",
- .platform_data = &any_driver_specific_data,
- .type = Type_of_device,
- };
-static int my_board_devices_init(void) {
- /* Do Blah Blah Blah */
- return platform_device_register(&my_little_device);
-}
-
-device_initcall(my_board_devices_init);
-@endcode
-
-You may probably be interested in calling console_initcall to get a console.. Modify arch/arm/boards/omap/Kconfig to add your OMAP board, create a defconfig, do a make C=2 to enable sparse warnings, you can potentially have a binary done in no time! if you remember to put doxygen comments in your code, you can do a make docs and get the documentation done too..
-
-
-*/
diff --git a/arch/arm/mach-samsung/lowlevel-s3c24x0.S b/arch/arm/mach-samsung/lowlevel-s3c24x0.S
index e2efd86e8c..52079ffc7b 100644
--- a/arch/arm/mach-samsung/lowlevel-s3c24x0.S
+++ b/arch/arm/mach-samsung/lowlevel-s3c24x0.S
@@ -31,14 +31,6 @@ s3c24x0_disable_wd:
str r1, [r0]
mov pc, lr
-/**
-@page dev_s3c24xx_wd_handling Watchdog handling
-
-The watchdog must be disabled very early, because if it resets the system
-it is still active and will continue to reset the system. So, call this
-routine very early in your board_init_lowlevel routine.
-*/
-
/*
* S3C2410 PLL configuration
* -------------------------
diff --git a/arch/arm/mach-samsung/mem-s3c24x0.c b/arch/arm/mach-samsung/mem-s3c24x0.c
index d40db14ff2..db61c63b64 100644
--- a/arch/arm/mach-samsung/mem-s3c24x0.c
+++ b/arch/arm/mach-samsung/mem-s3c24x0.c
@@ -80,60 +80,3 @@ void s3c24xx_disable_second_sdram_bank(void)
writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
}
-
-/**
-
-@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in barebox
-
-@section s3c24xx_boards Boards using S3C24xx Processors
-
-@li @subpage arch/arm/boards/a9m2410/a9m2410.c
-@li @subpage arch/arm/boards/a9m2440/a9m2440.c
-
-@section s3c24xx_arch Documentation for S3C24xx Architectures Files
-
-@li @subpage arch/arm/mach-s3c24xx/generic.c
-
-@section s3c24xx_mem_map SDRAM Memory Map
-
-SDRAM starts at address 0x3000.0000 up to the available amount of connected
-SDRAM memory. Physically this CPU can handle up to 256MiB (two areas with
-up to 128MiB each).
-
-@subsection s3c24xx_mem_generic_map Generic Map
-- 0x0000.0000 Start of the internal SRAM when booting from NAND flash memory or CS signal to a NOR flash memory.
-- 0x0800.0000 Start of I/O space.
-- 0x3000.0000 Start of SDRAM area.
- - 0x3000.0100 Start of the TAG list area.
- - 0x3000.8000 Start of the linux kernel (physical address).
-- 0x4000.0000 Start of internal SRAM, when booting from NOR flash memory
-- 0x4800.0000 Start of the internal I/O area
-
-@section s3c24xx_asm_arm include/asm-arm/arch-s3c24xx directory guidelines
-All S3C24xx common headers are located here.
-
-@note Do not add board specific header files/information here.
-*/
-
-/** @page dev_s3c24xx_mach Samsung's S3C24xx based platforms
-
-@par barebox Map
-
-The location of the @a barebox itself depends on the available amount of
-installed SDRAM memory:
-
-- 0x30fc.0000 Start of @a barebox when 16MiB SDRAM is available
-- 0x31fc.0000 Start of @a barebox when 32MiB SDRAM is available
-- 0x33fc.0000 Start of @a barebox when 64MiB SDRAM is available
-
-Adjust the @p CONFIG_TEXT_BASE/CONFIG_ARCH_TEXT_BASE symbol in accordance to
-the available memory.
-
-@note The RAM based filesystem and the stack resides always below the
-@a barebox start address.
-
-@li @subpage dev_s3c24xx_wd_handling
-@li @subpage dev_s3c24xx_pll_handling
-@li @subpage dev_s3c24xx_sdram_handling
-@li @subpage dev_s3c24xx_nandboot_handling
-*/
diff --git a/arch/blackfin/boards/ipe337/ipe337.dox b/arch/blackfin/boards/ipe337/ipe337.dox
deleted file mode 100644
index 4d7925af94..0000000000
--- a/arch/blackfin/boards/ipe337/ipe337.dox
+++ /dev/null
@@ -1,10 +0,0 @@
-/** @page ipe337 ipe337
-
-This CPU card is based on an Analog Device Blackfin CPU. The card is shipped
-with:
-
-- 32MiB NOR type Flash Memory
-- 128MiB synchronous dynamic RAM
-- SMSC9xxx network controller
-
-*/ \ No newline at end of file
diff --git a/arch/blackfin/mach-bf.dox b/arch/blackfin/mach-bf.dox
deleted file mode 100644
index 4b3a3c12ea..0000000000
--- a/arch/blackfin/mach-bf.dox
+++ /dev/null
@@ -1,9 +0,0 @@
-/* This document is intended to provide the developer with information
- * how to integrate a new CPU (MACH) into this part of the barebox tree
- */
-
-/** @page dev_bf_mach Blackfin based CPU (MACH) into the tree
-
-FIXME
-
-*/
diff --git a/arch/mips/boards/dlink-dir-320/dlink-dir-320.dox b/arch/mips/boards/dlink-dir-320/dlink-dir-320.dox
deleted file mode 100644
index d0f5869340..0000000000
--- a/arch/mips/boards/dlink-dir-320/dlink-dir-320.dox
+++ /dev/null
@@ -1,38 +0,0 @@
-/** @page dlink_dir_320 D-Link DIR-320 wireless router
-
-The router has
-@li BCM5354 SoC;
-@li 32 MiB SDRAM;
-@li 4 MiB NOR type Flash Memory;
-@li RS232 serial interface (LV-TTL levels on board!);
-@li 1xUSB interface;
-@li 4 + 1 ethernet interfaces;
-@li 802.11b/g (WiFi) interface;
-@li JTAG interface;
-@li 5 LEDs;
-@li 2 buttons.
-
-The router uses CFE as firmware.
-
-Barebox can be started from CFE using tftp.
-You must setup tftp-server on host 192.168.0.1.
-Put your barebox.bin to tftp-server directory
-(usual /tftpboot or /srv/tftp).
-Connect your DIR-320 to your tftp-server network via
-one of four <LAN> sockets.
-
-Next, setup network on DIR-320 and run barebox.bin, e.g.:
-@verbatim
-CFE> ifconfig eth0 -addr=192.168.0.99
-CFE> boot -tftp -addr=a0800000 -raw 192.168.0.1:barebox.bin
-@endverbatim
-
-DIR-320 links:
-@li http://www.dlink.com.au/products/?pid=768
-@li http://wiki.openwrt.org/toh/d-link/dir-320
-
-CFE links:
-@li http://www.broadcom.com/support/communications_processors/downloads.php#cfe
-@li http://www.linux-mips.org/wiki/CFE
-
-*/
diff --git a/arch/mips/boards/loongson-ls1b/loongson_ls1b.dox b/arch/mips/boards/loongson-ls1b/loongson_ls1b.dox
deleted file mode 100644
index f96a3f88d1..0000000000
--- a/arch/mips/boards/loongson-ls1b/loongson_ls1b.dox
+++ /dev/null
@@ -1,47 +0,0 @@
-/** @page loongson_ls1b Loongson LS1B demo board
-
-The LS1B is a development board made by Loongson Technology Corp. Ltd.
-
-The board has
-@li Loongson LS1B SoC 250 MHz;
-@li 64 MiB SDRAM;
-@li 512 KiB SPI boot ROM;
-@li 128M x 8 Bit NAND Flash Memory;
-@li 2 x RS232 serial interfaces (DB9 connectors);
-@li 2 x Ethernet interfaces;
-@li 4 x USB interfaces;
-@li microSD card slot;
-@li LCD display (480x272);
-@li audio controller;
-@li beeper;
-@li buttons;
-@li EJTAG 10-pin connector.
-
-The board uses PMON2000 as bootloader.
-
-Barebox mini-howto:
-
-1. Connect to the boards's UART2;
-
-2. Turn board's power on;
-
-3. Wait 'Press <Enter> to execute loading image' prompt and press the space key.
-
-4. Upload zbarebox.bin via Ymodem
-@verbatim
- PMON> ymodem base=0xa0200000
-@endverbatim
-
-5. Run barebox
-@verbatim
- PMON> g -e 0xa0200000
-@endverbatim
-
-Loongson links:
-@li http://en.wikipedia.org/wiki/Loongson
-@li http://www.linux-mips.org/wiki/Loongson
-@li https://github.com/loongson-gz
-@li http://www.linux-mips.org/wiki/PMON_2000
-@li http://www.opsycon.se/PMON2000/Main
-
-*/
diff --git a/arch/mips/boards/qemu-malta/qemu-malta.dox b/arch/mips/boards/qemu-malta/qemu-malta.dox
deleted file mode 100644
index bf10244585..0000000000
--- a/arch/mips/boards/qemu-malta/qemu-malta.dox
+++ /dev/null
@@ -1,20 +0,0 @@
-/** @page qemu_malta QEmu malta emulated board
-
-Specific to this emulated board is, it does not require any setup code to bring the SDRAM and RS232 up.
-
-Emulator run string:
-@verbatim
-qemu-system-mips -nodefaults -M malta -m 256 -nographic -serial stdio -monitor null -bios barebox-flash-image
-@endverbatim
-
-Also you can use GXemul:
-@verbatim
-gxemul -Q -x -e maltabe -M 256 0xbfc00000:barebox-flash-image
-@endverbatim
-
-Links:
-@li http://www.linux-mips.org/wiki/Mips_Malta
-@li http://www.qemu.org/
-@li http://gxemul.sourceforge.net/
-
-*/
diff --git a/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox b/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
deleted file mode 100644
index 5ec819462b..0000000000
--- a/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
+++ /dev/null
@@ -1,46 +0,0 @@
-/** @page ritmix-rzx50 Ritmix RZX-50 game console
-
-Ritmix RZX-50 is a portable game console for the Russian market.
-
-The portable game console has
-@li Ingenic JZ4755 SoC;
-@li 64 MiB SDRAM;
-@li 4 GiB microSDHC card / 4 GiB NAND type Flash Memory;
-@li RS232 serial interface (LV-TTL levels on the board!);
-@li LCD display (480x272);
-@li Video out interface;
-@li 1xUSB interface;
-@li buttons.
-
-The game console uses U-Boot 1.1.6 as bootloader.
-
-barebox-rzx50 mini-howto:
-
-1. Connect to the game console's UART (see. http://a320.emulate.su/2012/01/19/uart-na-ritmix-rzx-50/);
-
-2. Unblock U-Boot console (see. http://a320.emulate.su/2012/01/25/rzx-50-dostup-k-konsoli-u-boot/); Please note that U-Boot's Zmodem support does not work;
-
-3. Boot Ritmix linux and login;
-
-4. Upload barebox.bin via Zmodem
-@verbatim
- # cd /tmp
- # rz
-@endverbatim
-
-5. Write barebox to onboard flash
-@verbatim
- # dd if=barebox.bin of=/dev/mmcblk0 seek=1048576 bs=1 count=262144
-@endverbatim
-
-6. Reboot RZX-50, next in U-Boot console start barebox:
-@verbatim
- CETUS # msc read 0xa0800000 0x100000 0x40000; g a0800000
-@endverbatim
-
-Ritmix RZX-50 links:
-@li http://www.ritmixrussia.ru/products/252/entertainment/game/rzx-50
-@li ftp://ftp.ingenic.cn/2soc/4755/JZ4755_ds.pdf
-@li ftp://ftp.ingenic.cn/3sw/01linux/01loader/u-boot/u-boot-1.1.6-jz-20110719-r1728-add-jz4770.patch.bz2
-
-*/
diff --git a/arch/mips/boards/tplink-mr3020/tplink-mr3020.dox b/arch/mips/boards/tplink-mr3020/tplink-mr3020.dox
deleted file mode 100644
index 16fe4653d8..0000000000
--- a/arch/mips/boards/tplink-mr3020/tplink-mr3020.dox
+++ /dev/null
@@ -1,64 +0,0 @@
-/** @page tplink-mr3020 TP-LINK MR3020 wireless router
-
-The router has
-@li Atheros ar9331 SoC;
-@li 32 MiB SDRAM;
-@li 4 MiB NOR type SPI Flash Memory;
-@li RS232 serial interface (LV-TTL levels on board!);
-@li 1 USB interface;
-@li 1 Ethernet interfaces;
-@li 802.11b/g/n (WiFi) interface;
-@li LEDs & buttons.
-
-The router uses U-Boot 1.1.4 as firmware.
-
-Barebox can be started from U-Boot using tftp.
-But you have to encode barebox image in a very special way.
-
-First obtain 'lzma' and 'mktplinkfw' utilities.
-
-The 'lzma' utility can be obtained in Debian/Ubuntu
-distro by installing lzma package.
-
-The 'mktplinkfw' utility can be obtained from openwrt, e.g.:
-
-@verbatim
-$ OWRTPREF=https://raw.githubusercontent.com/mirrors/openwrt/master
-$ curl -OL $OWRTPREF/tools/firmware-utils/src/mktplinkfw.c \
- -OL $OWRTPREF/tools/firmware-utils/src/md5.c \
- -OL $OWRTPREF/tools/firmware-utils/src/md5.h
-$ cc -o mktplinkfw mktplinkfw.c md5.c
-@endverbatim
-
-To convert your barebox.bin to U-Boot-loadable image (6F01A8C0.img)
-use this command sequence:
-
-@verbatim
-$ lzma -c -k barebox.bin > barebox.lzma
-$ ./FW/mktplinkfw -c -H 0x07200103 -W 1 -N TL-WR720N-v3 \
- -s -F 4Mlzma -k barebox.lzma -o 6F01A8C0.img
-@endverbatim
-
-You must setup tftp-server on host 192.168.0.1.
-Put your 6F01A8C0.img to tftp-server directory
-(usual /tftpboot or /srv/tftp).
-Connect your board to your tftp-server network via Ethernet.
-
-Next, setup network on MR3020 and run 6F01A8C0.img, e.g.:
-@verbatim
-hornet> set ipaddr 192.168.0.2
-hornet> set serverip 192.168.0.1
-hornet> tftpboot 0x81000000 6F01A8C0.img
-hornet> bootm 0x81000000
-@endverbatim
-
-TP-LINK MR3020 links:
-@li http://www.tp-link.com/en/products/details/?model=TL-MR3020
-@li http://wiki.openwrt.org/toh/tp-link/tl-mr3020
-@li https://wikidevi.com/wiki/TP-LINK_TL-MR3020
-
-See also:
-@li http://www.eeboard.com/wp-content/uploads/downloads/2013/08/AR9331.pdf
-@li http://squonk42.github.io/TL-WR703N/
-
-*/
diff --git a/arch/mips/mach-bcm47xx/mach-bcm47xx.dox b/arch/mips/mach-bcm47xx/mach-bcm47xx.dox
deleted file mode 100644
index 04ccf03fcb..0000000000
--- a/arch/mips/mach-bcm47xx/mach-bcm47xx.dox
+++ /dev/null
@@ -1,7 +0,0 @@
-/** @page dev_bcm47xx_mach BCM47xx in barebox
-
-@section bcm47xx_boards BCM47xx-based boards
-
-@li @subpage dlink_dir_320
-
-*/
diff --git a/arch/mips/mach-loongson/mach-loongson.dox b/arch/mips/mach-loongson/mach-loongson.dox
deleted file mode 100644
index 7838ce5a85..0000000000
--- a/arch/mips/mach-loongson/mach-loongson.dox
+++ /dev/null
@@ -1,7 +0,0 @@
-/** @page dev_loongson_mach Loongson in barebox
-
-@section loongson_boards Loongson-based boards
-
-@li @subpage loongson_ls1b
-
-*/
diff --git a/arch/mips/mach-malta/mach-malta.dox b/arch/mips/mach-malta/mach-malta.dox
deleted file mode 100644
index 85351e10b7..0000000000
--- a/arch/mips/mach-malta/mach-malta.dox
+++ /dev/null
@@ -1,7 +0,0 @@
-/** @page dev_malta_mach MIPS Malta in barebox
-
-@section malta_boards MIPS Malta boards
-
-@li @subpage qemu_malta
-
-*/
diff --git a/arch/mips/mach-mips.dox b/arch/mips/mach-mips.dox
deleted file mode 100644
index 1002b16e9e..0000000000
--- a/arch/mips/mach-mips.dox
+++ /dev/null
@@ -1,69 +0,0 @@
-/* This document is intended to provide the developer with information
- * how to integrate a new CPU (MACH) into this part of the barebox tree
- */
-
-/** @page dev_mips_mach MIPS based CPU (MACH) into the tree
-
-@section mach_mips_reset What's happens when the reset signal is gone
-
-Barebox normally must be linked to RAM region, cached region KSEG0 is preferred.
-This make possible to run fast (because cache used) and skip MMU support.
-
-After reset MIPS CPU starting to fetch instructions from 0xBFC00000.
-
-@note Code running immediately after reset runs at an address it is not linked
- to: "runtime address != link address". You should only use branches and
- do not refer to fixed data. This implies the use of assembler code only.
- After MIPS CPU reset cache and MMU are in random state. They are unusable.
-
-barebox MIPS initialisation sequence:
-
- * set the CP0 STATUS register to some known and sensible state.
-Now you can load and store reliably in uncached space.
-
- * call a function \<mach_init_lowlevel\> (if not disabled).
-do some special things required only on specific CPU
- (e. g. init RAM controller, disable watchdog)
-
- * call a function \<board_init_lowlevel\> (if not disable).
-do some special things required only on specific board
- (e. g. setup GPIO to required state).
-
- ** It is desirable to have some debug code to make some contact
- with the outside world from assembler code
-(e.g. debug_ll-like functions to write to rs232 console).
-
- * check integrity of barebox RAM execute location;
- * copy barebox to RAM execute location;
-
- * configure cache;
-
- * setup stack;
-
- ** after this point you can call a standard C routine.
-
- * setup exception vectors in RAM;
- * setup CP0 STATUS to switch exception vector address to RAM;
-
- * call start_barebox()
-
-Further reading:
- * Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006
-ISBN-13: 978-0120884216
-
-@subsection mach_mips_malta_info Malta boards
-
-@li @subpage dev_malta_mach
-
-@subsection mach_bcm47xx_info BCM47xx-based boards
-
-@li @subpage dev_bcm47xx_mach
-
-@subsection mach_loongson_info Loongson-based boards
-
-@li @subpage dev_loongson_mach
-
-@subsection mach_xburst_info XBurst-based boards
-
-@li @subpage dev_xburst_mach
-*/
diff --git a/arch/mips/mach-xburst/mach-xburst.dox b/arch/mips/mach-xburst/mach-xburst.dox
deleted file mode 100644
index 052c05e7ae..0000000000
--- a/arch/mips/mach-xburst/mach-xburst.dox
+++ /dev/null
@@ -1,7 +0,0 @@
-/** @page dev_xburst_mach XBurst in barebox
-
-@section xburst_boards XBurst-based boards
-
-@li @subpage ritmix-rzx50
-
-*/
diff --git a/arch/ppc/boards/pcm030/pcm030.dox b/arch/ppc/boards/pcm030/pcm030.dox
deleted file mode 100644
index b9ada839f2..0000000000
--- a/arch/ppc/boards/pcm030/pcm030.dox
+++ /dev/null
@@ -1,8 +0,0 @@
-/** @page pcm030 Phytec's phyCORE-MPC5200B-tiny
-
-This CPU card is based on a Freescale MPC5200B CPU. The card is shipped with:
-
-- up to 16MiB NOR type Flash Memory
-- 64MiB synchronous dynamic RAM
-
-*/
diff --git a/arch/ppc/mach-ppc.dox b/arch/ppc/mach-ppc.dox
deleted file mode 100644
index f7191b9988..0000000000
--- a/arch/ppc/mach-ppc.dox
+++ /dev/null
@@ -1,9 +0,0 @@
-/* This document is intended to provide the developer with information
- * how to integrate a new CPU (MACH) into this part of the barebox tree
- */
-
-/** @page dev_ppc_mach PowerPC based CPU into the tree
-
-FIXME
-
-*/
diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c
index 36c8d622b6..412393811e 100644
--- a/arch/sandbox/os/common.c
+++ b/arch/sandbox/os/common.c
@@ -18,10 +18,6 @@
*
*/
-/**
- * @file
- * @brief Common wrapper functions between barebox and the host
- */
/*
* These are host includes. Never include any barebox header
* files here...
@@ -421,54 +417,3 @@ static void print_usage(const char *prgname)
prgname
);
}
-
-/**
- * @page barebox_simul barebox Simulator
- *
- * barebox can be run as a simulator on your host to check and debug new non
- * hardware related features.
- *
- * @section simu_build How to build barebox for simulation
- *
- * @section simu_run How to run barebox simulator
- *
- * $ barebox [\<OPTIONS\>]
- *
- * Options can be:
- *
- * -m, --malloc=\<size\>
- *
- * Start sandbox with a specified malloc-space \<size\> in bytes.
- *
- * -i \<file\>
- *
- * Map a \<file\> to barebox. This option can be given multiple times. The \<file\>s
- * will show up as /dev/fd0 ... /dev/fdx in the barebox simulator.
- *
- * -e \<file\>
- *
- * Map \<file\> to barebox. With this option \<file\>s are mapped as /dev/env0 ...
- * /dev/envx and thus are used as default environment. A clean file generated
- * with dd will do to get started with an empty environment
- *
- * -O \<file\>
- *
- * Register \<file\> as a console capable of doing stdout. \<file\> can be a
- * regular file or a fifo.
- *
- * -I \<file\>
- *
- * Register \<file\> as a console capable of doing stdin. \<file\> can be a regular
- * file or a fifo.
- *
- * -x, --xres \<res\>
- *
- * Specify SDL width
- *
- * -y, --yres \<res\>
- *
- * Specify SDL height
- *
- * @section simu_dbg How to debug barebox simulator
- *
- */
diff --git a/arch/x86/boards/x86_generic/generic_pc.c b/arch/x86/boards/x86_generic/generic_pc.c
index 5560efc889..482889f2d9 100644
--- a/arch/x86/boards/x86_generic/generic_pc.c
+++ b/arch/x86/boards/x86_generic/generic_pc.c
@@ -14,11 +14,6 @@
*
*/
-/**
- * @file
- * @brief Generic PC support to let barebox acting as a boot loader
- */
-
#include <common.h>
#include <types.h>
#include <driver.h>
@@ -34,32 +29,3 @@ static int devices_init(void)
return 0;
}
device_initcall(devices_init);
-
-/** @page generic_pc Generic PC based bootloader
-
-This platform acts as a generic PC based bootloader. It depends on at least
-one boot media that is connected locally (no network boot) and can be
-handled by the regular BIOS (any kind of hard disks for example).
-
-The created @a barebox image can be used to boot a standard x86 bzImage
-Linux kernel.
-
-Refer section @ref x86_bootloader_preparations how to do so.
-
-How to get the binary image:
-
-Using the default configuration:
-
-@code
-make ARCH=x86 generic_defconfig
-@endcode
-
-Build the binary image:
-
-@code
-make ARCH=x86 CROSS_COMPILE=x86compiler
-@endcode
-
-@note replace the 'x86compiler' with your x86 (cross) compiler.
-
-*/
diff --git a/arch/x86/boot/bioscall.S b/arch/x86/boot/bioscall.S
index 84d2577eb6..e60072992b 100644
--- a/arch/x86/boot/bioscall.S
+++ b/arch/x86/boot/bioscall.S
@@ -13,8 +13,6 @@
* touching registers they shouldn't be.
*/
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
.file "bioscall.S"
.code16
.section .boot.text.intcall, "ax"
@@ -95,5 +93,3 @@ die:
hlt
jmp die
.size die, .-die
-
-#endif /* DOXYGEN_SHOULD_SKIP_THIS */
diff --git a/arch/x86/lib/bios_disk.S b/arch/x86/lib/bios_disk.S
index 121f440be5..cce33e67af 100644
--- a/arch/x86/lib/bios_disk.S
+++ b/arch/x86/lib/bios_disk.S
@@ -26,7 +26,6 @@
* space below 0x10000
*/
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
/*
* int bios_disk_rw_int13_extensions (int ah, int drive, void *dap)
*
@@ -69,5 +68,3 @@ bios_disk_rw_int13_extensions:
popl %ebp
ret
-
-#endif
diff --git a/arch/x86/lib/linux_start.S b/arch/x86/lib/linux_start.S
index f74e4e9c47..b9489b8e50 100644
--- a/arch/x86/lib/linux_start.S
+++ b/arch/x86/lib/linux_start.S
@@ -30,7 +30,6 @@
* void bios_start_linux(unsigned segment)
*
*/
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
.section .boot.text.bios_start_linux, "ax"
.code32
@@ -67,5 +66,3 @@ setup_seg:
.word 0
.code32
-
-#endif
diff --git a/arch/x86/mach-x86.dox b/arch/x86/mach-x86.dox
deleted file mode 100644
index 661e905bac..0000000000
--- a/arch/x86/mach-x86.dox
+++ /dev/null
@@ -1,128 +0,0 @@
-/* This document is intended to provide the developer with information
- * how to integrate a new CPU (MACH) into this part of the barebox tree
- */
-
-/** @page dev_x86_mach barebox on x86 at runtime
-
-@section mach_x86_memory_layout barebox's memory layout (BIOS based)
-
-@a barebox uses the following memory layout at runtime when it still depends
-on some kind of BIOS function:
-
-@verbatim
- Addresses
-------------------------
-
- seg:off flat
-
-xxxx:xxxx 0x01xxxxxx end of barebox's malloc area
- . .
-xxxx:xxxx 0x01000000 start of barebox's malloc area
- . .
- . . (used while loading a Linux kernel of type 'bzImage')
- . .
-xxxx:xxxx 0x00100000 start of extended memory and malloc area
- . .
- . . (the big hole)
- . .
-9000:ffff 0x0009ffff end of expected real mode memory
- . .
- . . (used while loading a Linux kernel of type 'bzImage')
- . .
-9000:0000 0x00090000 end of used lower real mode memory
- . .
- . .
- . . Flat mode stack (about 32 kiB)
- . . bss
- . . Data
- . . Text
-0000:7e00 0x00007e00 Real and flat mode barebox code
-0000:7c00 0x00007c00 MBR initial boot loader code
-0000:7a00 0x00007a00 location of the indirect sector (while booting only)
- below: real mode stack
-@endverbatim
-
-@note The start address of 0x0000:7c000 is a fixed one, defined by the BIOS.
-So, for a BIOS based @a barebox this address can't be changed.
-
-While the @a barebox code is runnung in flat mode, all interrupts are disabled.
-But in the CPU only. All other interrupt settings are still valid. This is
-required to be able to call real mode code from inside @a barebox flat mode
-code. Thats why not the PIC is touched nor the IDT.
-
-@todo Add some notes about drive numbers used by the BIOS. They may change
-if one change orders in the BIOS setup. Drive orders and numbers may be
-different at BIOS runtime and Linux runtime! But these numbers are required
-at BIOS runtime for booting and the persistant environment storage.
-
-@attention Currently there is a 4 GiB limit for the disk sizes!
-
-@section mach_x86_image_layout barebox's image layout
-
-@a barebox's binary image layout
-
-@verbatim
- Offset Content
-
- 0x?????
- . 32 bit barebox code
- .
- . 16 bit bootstrap code, BIOS calling code
- 0x00400
- 0x003ff
- . indirect sector
- 0x00200
- 0x001ff
- . MBR
- 0x00000
-@endverbatim
-
-The "indirect sector" is a free area in the image where the sector information
-gets stored when this image will be written to a boot media. This information
-is required to load all parts of the image from the boot media at runtime.
-
-The image gets installed in two ways onto the boot media, depending on the
-need for a persistant storage.
-
-@subsection mach_x86_drive_layout_wops barebox's boot media layout without persistant storage
-
-In this case @a barebox's persistant storage is anywhere:
-
-@verbatim
- Sector Content
----------------------------
- X start of first partition
- .
- ? end of the binary image
- . 32 bit barebox code
- 2 16 bit bootstrap code, BIOS calling code
- 1 indirect sector
- 0 MBR, Partition table, boot code
-@endverbatim
-
-@subsection mach_x86_drive_layout_wps barebox's boot media layout with persistant storage
-
-@a barebox's persistant storage is part of the boot media (more
-space required in front of the first partition) and interferes with the
-boot loader image itself:
-
-@verbatim
- Sector Content
----------------------------
- X start of first partition
- .
- n+? end of the binary image
- . 32 bit barebox code
- n+2 16 bit bootstrap code, BIOS calling code
- n+1 indirect sector
- n end of persistant environment storage
- .
- 1 start of persistant environment storage
- 0 MBR, Partition table, boot code
-@endverbatim
-
-The information where the persistant storage is located is also stored into
-the MBR at specific locations by @p setupmbr. The @a barebox runtime will use
-it to load and store all environment relevant data.
-
-*/