diff options
Diffstat (limited to 'arch')
64 files changed, 1775 insertions, 435 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 30f4c299f1..b2fea4a40f 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -1,4 +1,5 @@ # keep sorted by CONFIG_* macro name. +obj-$(CONFIG_MACH_ADVANTECH_ROM_742X) += advantech-mx6/ obj-$(CONFIG_MACH_AFI_GF) += afi-gf/ obj-$(CONFIG_MACH_ANIMEO_IP) += animeo_ip/ obj-$(CONFIG_MACH_ARCHOSG9) += archosg9/ diff --git a/arch/arm/boards/advantech-mx6/Makefile b/arch/arm/boards/advantech-mx6/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/advantech-mx6/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/advantech-mx6/board.c b/arch/arm/boards/advantech-mx6/board.c new file mode 100644 index 0000000000..4a30a845f1 --- /dev/null +++ b/arch/arm/boards/advantech-mx6/board.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <init.h> +#include <platform_data/eth-fec.h> +#include <bootsource.h> +#include <mach/bbu.h> + +static int ar8035_phy_fixup(struct phy_device *dev) +{ + u16 val; + + /* Ar803x phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(dev, 0xd, 0x3); + phy_write(dev, 0xe, 0x805d); + phy_write(dev, 0xd, 0x4003); + + val = phy_read(dev, 0xe); + phy_write(dev, 0xe, val & ~BIT(8)); + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(dev, 0xd, 0x7); + phy_write(dev, 0xe, 0x8016); + phy_write(dev, 0xd, 0x4007); + + val = phy_read(dev, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(dev, 0xe, val); + + /* introduce tx clock delay */ + phy_write(dev, 0x1d, 0x5); + val = phy_read(dev, 0x1e); + val |= 0x0100; + phy_write(dev, 0x1e, val); + + return 0; +} + +static int advantech_mx6_devices_init(void) +{ + int ret; + char *environment_path, *envdev; + + if (!of_machine_is_compatible("advantech,imx6dl-rom-7421")) + return 0; + + phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup); + + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + environment_path = basprintf("/chosen/environment-sd%d", + bootsource_get_instance() + 1); + if (bootsource_get_instance() + 1 == 4) + envdev = "eMMC"; + else if (bootsource_get_instance() + 1 == 2) + envdev = "microSD"; + else + envdev = "MMC"; + break; + case BOOTSOURCE_SPI: + envdev = "SPI"; + environment_path = basprintf("/chosen/environment-spi"); + break; + default: + environment_path = basprintf("/chosen/environment-sd4"); + envdev = "MMC"; + break; + } + + if (environment_path) { + ret = of_device_enable_path(environment_path); + if (ret < 0) + pr_warn("Failed to enable env partition '%s' (%d)\n", + environment_path, ret); + free(environment_path); + } + + pr_notice("Using environment in %s\n", envdev); + + imx6_bbu_internal_mmc_register_handler("mmc3", "/dev/mmc3", + BBU_HANDLER_FLAG_DEFAULT); + + return 0; +} +device_initcall(advantech_mx6_devices_init); diff --git a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg new file mode 100644 index 0000000000..996ecc708d --- /dev/null +++ b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg @@ -0,0 +1,66 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +wm 32 0x020e0774 0x000C0000 +wm 32 0x020e0754 0x00000000 +wm 32 0x020e04ac 0x00000030 +wm 32 0x020e04b0 0x00000030 +wm 32 0x020e0464 0x00000030 +wm 32 0x020e0490 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0494 0x00000030 +wm 32 0x020e04a0 0x00000000 +wm 32 0x020e04b4 0x00000030 +wm 32 0x020e04b8 0x00000030 +wm 32 0x020e076c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e04bc 0x00000030 +wm 32 0x020e04c0 0x00000030 +wm 32 0x020e04c4 0x00000030 +wm 32 0x020e04c8 0x00000030 +wm 32 0x020e0760 0x00020000 +wm 32 0x020e0764 0x00000030 +wm 32 0x020e0770 0x00000030 +wm 32 0x020e0778 0x00000030 +wm 32 0x020e077c 0x00000030 +wm 32 0x020e0470 0x00000030 +wm 32 0x020e0474 0x00000030 +wm 32 0x020e0478 0x00000030 +wm 32 0x020e047c 0x00000030 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b080c 0x001F001F +wm 32 0x021b0810 0x001F001F +wm 32 0x021b083c 0x42480248 +wm 32 0x021b0840 0x022C0234 +wm 32 0x021b0848 0x3E404244 +wm 32 0x021b0850 0x30302C30 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b0004 0x0002002D +wm 32 0x021b0008 0x00333030 +wm 32 0x021b000c 0x3F435333 +wm 32 0x021b0010 0xB68E8B63 +wm 32 0x021b0014 0x01FF00DB +wm 32 0x021b0018 0x00001740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x00431023 +wm 32 0x021b0040 0x00000017 +wm 32 0x021b0000 0x83190000 +wm 32 0x021b001c 0x04008032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x05208030 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b0004 0x0002556D +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 +wm 32 0x020e0010 0xF00000CF +wm 32 0x020e0018 0x007F007F +wm 32 0x020e001c 0x007F007F diff --git a/arch/arm/boards/advantech-mx6/lowlevel.c b/arch/arm/boards/advantech-mx6/lowlevel.c new file mode 100644 index 0000000000..8921cd4dd8 --- /dev/null +++ b/arch/arm/boards/advantech-mx6/lowlevel.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <debug_ll.h> +#include <common.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <image-metadata.h> +#include <mach/generic.h> +#include <mach/esdctl.h> +#include <mach/iomux-mx6.h> +#include <linux/sizes.h> + +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +static inline void setup_uart(void) +{ + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + imx6_ungate_all_peripherals(); + + imx_setup_pad(iomuxbase, MX6Q_PAD_CSI0_DAT10__UART1_TXD); + + imx6_uart_setup_ll(); + + putc_ll('>'); +} + +extern char __dtb_imx6dl_advantech_rom_7421_start[]; + +ENTRY_FUNCTION(start_advantech_imx6dl_rom_7421, r0, r1, r2) +{ + imx6_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + imx6q_barebox_entry(__dtb_imx6dl_advantech_rom_7421_start); +} diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c index 043a93461b..d93c940e3d 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/board.c +++ b/arch/arm/boards/datamodul-edm-qmx6/board.c @@ -132,7 +132,7 @@ static int realq7_device_init(void) } break; default: - case BOOTSOURCE_SPI: + case BOOTSOURCE_SPI_NOR: of_device_enable_path("/chosen/environment-spi"); break; } diff --git a/arch/arm/boards/dfi-fs700-m60/board.c b/arch/arm/boards/dfi-fs700-m60/board.c index bef4612d9e..2cb8e3106f 100644 --- a/arch/arm/boards/dfi-fs700-m60/board.c +++ b/arch/arm/boards/dfi-fs700-m60/board.c @@ -105,7 +105,7 @@ static int dfi_fs700_m60_init(void) phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup); - if (bootsource_get() == BOOTSOURCE_SPI) + if (bootsource_get() == BOOTSOURCE_SPI_NOR) flag_spi |= BBU_HANDLER_FLAG_DEFAULT; else flag_mmc |= BBU_HANDLER_FLAG_DEFAULT; diff --git a/arch/arm/boards/freescale-vf610-twr/lowlevel.c b/arch/arm/boards/freescale-vf610-twr/lowlevel.c index deabe4e371..8fec9f4b91 100644 --- a/arch/arm/boards/freescale-vf610-twr/lowlevel.c +++ b/arch/arm/boards/freescale-vf610-twr/lowlevel.c @@ -3,6 +3,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> +#include <mach/esdctl.h> #include <mach/vf610-regs.h> #include <mach/clock-vf610.h> #include <mach/iomux-vf610.h> @@ -13,27 +14,21 @@ static inline void setup_uart(void) void __iomem *iomuxbase = IOMEM(VF610_IOMUXC_BASE_ADDR); vf610_ungate_all_peripherals(); - - /* - * VF610_PAD_PTB4__UART1_TX - */ - writel(VF610_UART_PAD_CTRL | (2 << 20), iomuxbase + 0x0068); - writel(0, iomuxbase + 0x0380); - + vf610_setup_pad(iomuxbase, VF610_PAD_PTB4__UART1_TX); vf610_uart_setup_ll(); + + putc_ll('>'); } extern char __dtb_vf610_twr_start[]; ENTRY_FUNCTION(start_vf610_twr, r0, r1, r2) { - void *fdt; vf610_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); - fdt = __dtb_vf610_twr_start + get_runtime_offset(); - barebox_arm_entry(0x80000000, SZ_128M, fdt); + vf610_barebox_entry(__dtb_vf610_twr_start + get_runtime_offset()); } diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index 717a22963a..34a0fe4183 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -28,6 +28,7 @@ #include <gpio.h> #include <init.h> #include <of.h> +#include <i2c/i2c.h> #include <mach/bbu.h> #include <platform_data/eth-fec.h> #include <mfd/imx6q-iomuxc-gpr.h> @@ -51,6 +52,14 @@ #define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11) +#define DA9062_I2C_ADDRESS 0x58 + +#define DA9062_BUCK1_CFG 0x9e +#define DA9062_BUCK2_CFG 0x9d +#define DA9062_BUCK3_CFG 0xa0 +#define DA9062_BUCK4_CFG 0x9f +#define DA9062_BUCKx_MODE_SYNCHRONOUS (2 << 6) + static void phyflex_err006282_workaround(void) { /* @@ -66,7 +75,7 @@ static void phyflex_err006282_workaround(void) mdelay(2); gpio_set_value(MX6_PHYFLEX_ERR006282, 0); - if (cpu_is_mx6q() || cpu_is_mx6d()) + if (cpu_is_mx6q() || cpu_is_mx6d() || cpu_is_mx6qp() || cpu_is_mx6dp()) mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD); else if (cpu_is_mx6dl() || cpu_is_mx6s()) mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11); @@ -96,6 +105,45 @@ int ksz8081_phy_fixup(struct phy_device *phydev) return 0; } +static int phycore_da9062_setup_buck_mode(void) +{ + struct i2c_adapter *adapter = NULL; + struct i2c_client client; + unsigned char value; + int bus = 0; + int ret; + + adapter = i2c_get_adapter(bus); + if (!adapter) + return -ENODEV; + + client.adapter = adapter; + client.addr = DA9062_I2C_ADDRESS; + + value = DA9062_BUCKx_MODE_SYNCHRONOUS; + + ret = i2c_write_reg(&client, DA9062_BUCK1_CFG, &value, 1); + if (ret != 1) + goto err_out; + + ret = i2c_write_reg(&client, DA9062_BUCK2_CFG, &value, 1); + if (ret != 1) + goto err_out; + + ret = i2c_write_reg(&client, DA9062_BUCK3_CFG, &value, 1); + if (ret != 1) + goto err_out; + + ret = i2c_write_reg(&client, DA9062_BUCK4_CFG, &value, 1); + if (ret != 1) + goto err_out; + + return 0; + +err_out: + return ret; +} + static int physom_imx6_devices_init(void) { int ret; @@ -125,8 +173,12 @@ static int physom_imx6_devices_init(void) } else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") + || of_machine_is_compatible("phytec,imx6qp-pcm058-nand") || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { + if (phycore_da9062_setup_buck_mode()) + pr_err("Setting PMIC BUCK mode failed\n"); + barebox_set_hostname("phyCORE-i.MX6"); default_environment_path = "/chosen/environment-spinor"; default_envdev = "SPI NOR flash"; @@ -152,7 +204,7 @@ static int physom_imx6_devices_init(void) environment_path = basprintf("/chosen/environment-nand"); envdev = "NAND flash"; break; - case BOOTSOURCE_SPI: + case BOOTSOURCE_SPI_NOR: environment_path = basprintf("/chosen/environment-spinor"); envdev = "SPI NOR flash"; break; @@ -184,7 +236,8 @@ static int physom_imx6_devices_init(void) defaultenv_append_directory(defaultenv_physom_imx6); /* Overwrite file /env/init/automount */ - if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") + if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand") + || of_machine_is_compatible("phytec,imx6q-pcm058-nand") || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc new file mode 100644 index 0000000000..7ba1d0d0cf --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc @@ -0,0 +1,5 @@ +#!/bin/sh + +global.bootm.image="/mnt/emmc/zImage" +global.bootm.oftree="/mnt/emmc/oftree" +global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2 rootwait rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc new file mode 100644 index 0000000000..f0d019c3ee --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ -f /mnt/mmc3/android ]; then + # configure here the android specific stuff + global linux.bootargs.sec="selinux=0 enforcing=0" +fi + +global.bootm.image="/mnt/mmc3/zImage" +global.bootm.oftree="/mnt/mmc3/oftree" +global.linux.bootargs.dyn.root="root=/dev/mmcblk3p2 rootwait rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc index 332fc26ad0..3e175122dd 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc @@ -1,5 +1,10 @@ #!/bin/sh -global.bootm.image="/mnt/mmc/linuximage" +if [ -f /mnt/mmc/android ]; then + # configure here the android specific stuff + global linux.bootargs.sec="selinux=0 enforcing=0" +fi + +global.bootm.image="/mnt/mmc/zImage" global.bootm.oftree="/mnt/mmc/oftree" global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand index a23aa21cc7..0c2b1cbe4c 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand @@ -1,5 +1,12 @@ #!/bin/sh -global.bootm.image="/dev/nand0.kernel.bb" -global.bootm.oftree="/dev/nand0.oftree.bb" +[ ! -e /dev/nand0.root.ubi ] && ubiattach /dev/nand0.root + +if [ -e /dev/nand0.root.ubi.system ]; then + # configure here the android specific stuff + global linux.bootargs.sec="selinux=0 enforcing=0" +fi + +global.bootm.image="/dev/nand0.root.ubi.kernel" +global.bootm.oftree="/dev/nand0.root.ubi.oftree" global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount index 4b223d8037..fea64d627e 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount @@ -7,3 +7,8 @@ automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' mkdir -p /mnt/mmc automount -d /mnt/mmc 'mmc2.probe=1 && [ -e /dev/mmc2.0 ] && mount /dev/mmc2.0 /mnt/mmc' + +if [ -e /dev/mmc3 ]; then + mkdir -p /mnt/mmc3 + automount -d /mnt/mmc3 'mmc3.probe=1 && [ -e /dev/mmc3.0 ] && mount /dev/mmc3.0 /mnt/mmc3' +fi diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg new file mode 100644 index 0000000000..bf95d0f6ae --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x8c929b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x84190000 + +#include "flash-header-phytec-pcm058dl.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg new file mode 100644 index 0000000000..bf85f0a19c --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x555A7955 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x831A0000 + +#include "flash-header-phytec-pcm058qp.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h new file mode 100644 index 0000000000..6e7b740a6f --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h @@ -0,0 +1,112 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +/* NOC setup */ +wm 32 0x00bb0008 0x00000000 +wm 32 0x00bb000c 0x2891E41A +wm 32 0x00bb0038 0x00000564 +wm 32 0x00bb0014 0x00000040 +wm 32 0x00bb0028 0x00000020 +wm 32 0x00bb002c 0x00000020 + +wm 32 0x020e0798 0x000C0000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00000028 +wm 32 0x020e05b0 0x00000028 +wm 32 0x020e0524 0x00000028 +wm 32 0x020e051c 0x00000028 +wm 32 0x020e0518 0x00000028 +wm 32 0x020e050c 0x00000028 +wm 32 0x020e05b8 0x00000028 +wm 32 0x020e05c0 0x00000028 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e0788 0x00000028 +wm 32 0x020e0794 0x00000028 +wm 32 0x020e079c 0x00000028 +wm 32 0x020e07a0 0x00000028 +wm 32 0x020e07a4 0x00000028 +wm 32 0x020e07a8 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e05ac 0x00000028 +wm 32 0x020e05b4 0x00000028 +wm 32 0x020e0528 0x00000028 +wm 32 0x020e0520 0x00000028 +wm 32 0x020e0514 0x00000028 +wm 32 0x020e0510 0x00000028 +wm 32 0x020e05bc 0x00000028 +wm 32 0x020e05c4 0x00000028 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b080c 0x00140014 +wm 32 0x021b0810 0x00230018 +wm 32 0x021b480c 0x000A001E +wm 32 0x021b4810 0x000A0015 +wm 32 0x021b083c 0x43080314 +wm 32 0x021b0840 0x02680300 +wm 32 0x021b483c 0x430C0318 +wm 32 0x021b4840 0x03000254 +wm 32 0x021b0848 0x3A323234 +wm 32 0x021b4848 0x3E3C3242 +wm 32 0x021b0850 0x2A2E3632 +wm 32 0x021b4850 0x3C323E34 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x09444040 + +SETUP_MDCFG0 + +wm 32 0x021b0010 0xFF328F64 +wm 32 0x021b0014 0x01FF00DB +wm 32 0x021b0018 0x00011740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x003F1023 + +SETUP_MDASP_MDCTL + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x00048039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0020 0x00007800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b0890 0x00400c58 +wm 32 0x021b0400 0x14420000 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 +wm 32 0x020e0010 0xf00000ff +wm 32 0x020e0018 0x007F007F +wm 32 0x020e001c 0x007F007F +wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg index 156eea971e..7b64e5d2fd 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x565c9b85 + wm 32 0x021b000c 0x41447525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000027; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg index e76867004a..04c489d7e8 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x8c929b85 + wm 32 0x021b000c 0x2d307525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000017; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h index 405529ddf8..b0f3faa0b7 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h @@ -74,7 +74,7 @@ wm 32 MX6_MMDC_P0_MDOTC 0x09444040 SETUP_MDCFG0 -wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64 +wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8b64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff0124 wm 32 MX6_MMDC_P0_MDMISC 0x00091740 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg index 26fe2b2f7d..ebe5a968b1 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x3c409b85 + wm 32 0x021b000c 0x2D307525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x0000000B; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg index babb0dfe24..5f1585a40b 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x3c409b85 + wm 32 0x021b000c 0x2D307525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x0000000F; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg index 6a46cd958f..5ff3ec69d7 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x565c9b85 + wm 32 0x021b000c 0x41447525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000017; \ diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 12c3cfa642..f9d70c7450 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -107,8 +107,10 @@ PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank, imx6dl_phytec_phyboard_sub PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank, imx6q_phytec_phyboard_subra, SZ_1G, false); PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_1gib, imx6dl_phytec_phycore_som_nand, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib, imx6qp_phytec_phycore_som_nand, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c index 22ffdf85ea..6b9c719c6d 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c +++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c @@ -284,13 +284,13 @@ static noinline void rdu2_sram_setup(void) relocate_to_current_adr(); setup_c(); - if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0) + if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP) write_regs(imx6qp_dcd, ARRAY_SIZE(imx6qp_dcd)); else write_regs(imx6q_dcd, ARRAY_SIZE(imx6q_dcd)); imx6_get_boot_source(&bootsrc, &instance); - if (bootsrc == BOOTSOURCE_SPI) + if (bootsrc == BOOTSOURCE_SPI_NOR) imx6_spi_start_image(0); else imx6_esdhc_start_image(instance); @@ -304,10 +304,10 @@ ENTRY_FUNCTION(start_imx6_zii_rdu2, r0, r1, r2) * When still running in SRAM, we need to setup the DRAM now and load * the remaining image. */ - if (get_pc() < MX6_MMDC_PORT0_BASE_ADDR) + if (get_pc() < MX6_MMDC_PORT01_BASE_ADDR) rdu2_sram_setup(); - if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0) + if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP) imx6q_barebox_entry(__dtb_imx6qp_zii_rdu2_start + get_runtime_offset()); else diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c index c6663c1415..f3d67501ab 100644 --- a/arch/arm/boards/zii-vf610-dev/lowlevel.c +++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c @@ -18,6 +18,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> +#include <mach/esdctl.h> #include <mach/vf610-regs.h> #include <mach/clock-vf610.h> #include <mach/iomux-vf610.h> @@ -133,5 +134,5 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) break; } - barebox_arm_entry(0x80000000, SZ_512M, fdt + get_runtime_offset()); + vf610_barebox_entry(fdt + get_runtime_offset()); } diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 426bc04651..8aef9d6ef6 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -32,16 +32,21 @@ CONFIG_MACH_UDOO=y CONFIG_MACH_VARISCITE_MX6=y CONFIG_MACH_GW_VENTANA=y CONFIG_MACH_CM_FX6=y +CONFIG_MACH_ADVANTECH_ROM_742X=y +CONFIG_MACH_WARP7=y +CONFIG_MACH_VF610_TWR=y +CONFIG_MACH_ZII_RDU2=y +CONFIG_MACH_ZII_VF610_DEV=y CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y +CONFIG_MACH_FREESCALE_MX7_SABRESD=y +CONFIG_MACH_NXP_IMX6ULL_EVK=y CONFIG_IMX_IIM=y CONFIG_IMX_IIM_FUSE_BLOW=y -CONFIG_IMX_OCOTP=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y CONFIG_ARM_PSCI=y CONFIG_MMU=y -CONFIG_TEXT_BASE=0x0 CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y @@ -164,6 +169,7 @@ CONFIG_DRIVER_VIDEO_EDID=y CONFIG_MCI=y CONFIG_MCI_MMC_BOOT_PARTITIONS=y CONFIG_MCI_IMX_ESDHC=y +CONFIG_MFD_DA9063=y CONFIG_MFD_MC34704=y CONFIG_MFD_MC9SDZ60=y CONFIG_MFD_STMPE=y diff --git a/arch/arm/configs/omap3530_beagle_defconfig b/arch/arm/configs/omap3530_beagle_defconfig index b454cf2b4d..cf79148559 100644 --- a/arch/arm/configs/omap3530_beagle_defconfig +++ b/arch/arm/configs/omap3530_beagle_defconfig @@ -5,7 +5,6 @@ CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y CONFIG_MMU=y -CONFIG_TEXT_BASE=0x0 CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y @@ -26,7 +25,6 @@ CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_RESET_SOURCE=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_OMAP_UART_PORT=3 -CONFIG_DEBUG_INITCALLS=y CONFIG_CMD_DMESG=y CONFIG_LONGHELP=y CONFIG_CMD_IOMEM=y diff --git a/arch/arm/configs/omap3530_beagle_xload_defconfig b/arch/arm/configs/omap3530_beagle_xload_defconfig index d36aaf3199..2105c0b9d4 100644 --- a/arch/arm/configs/omap3530_beagle_xload_defconfig +++ b/arch/arm/configs/omap3530_beagle_xload_defconfig @@ -8,7 +8,6 @@ CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y CONFIG_MMU=y -CONFIG_TEXT_BASE=0x0 CONFIG_STACK_SIZE=0xc00 CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_DUMMY=y @@ -18,7 +17,6 @@ CONFIG_SHELL_NONE=y # CONFIG_ERRNO_MESSAGES is not set # CONFIG_TIMESTAMP is not set CONFIG_CONSOLE_SIMPLE=y -CONFIG_OFDEVICE=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y # CONFIG_SPI is not set @@ -36,7 +34,6 @@ CONFIG_MCI=y CONFIG_MCI_STARTUP=y # CONFIG_MCI_WRITE is not set CONFIG_MCI_OMAP_HSMMC=y -# CONFIG_PINCTRL is not set # CONFIG_FS_RAMFS is not set # CONFIG_FS_DEVFS is not set CONFIG_FS_FAT=y diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c index 00ce3efb2f..51fe7ed988 100644 --- a/arch/arm/cpu/common.c +++ b/arch/arm/cpu/common.c @@ -85,6 +85,7 @@ void relocate_to_current_adr(void) unsigned long *fixup = (unsigned long *)(rel->r_offset + offset); *fixup = *fixup + r + offset; + rel->r_offset += offset; } else { putc_ll('>'); puthex_ll(rel->r_info); diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c index 68fff892e8..64bd942ad7 100644 --- a/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c @@ -144,13 +144,11 @@ __noreturn void barebox_non_pbl_start(unsigned long membase, unsigned long endmem = membase + memsize; unsigned long malloc_start, malloc_end; unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE; - - if (IS_ENABLED(CONFIG_RELOCATABLE)) { - unsigned long barebox_base = arm_mem_barebox_image(membase, - endmem, - barebox_size); + unsigned long barebox_base = arm_mem_barebox_image(membase, + endmem, + barebox_size); + if (IS_ENABLED(CONFIG_RELOCATABLE)) relocate_to_adr(barebox_base); - } setup_c(); @@ -160,8 +158,7 @@ __noreturn void barebox_non_pbl_start(unsigned long membase, arm_stack_top = arm_mem_stack_top(membase, endmem); arm_barebox_size = barebox_size; - malloc_end = arm_mem_barebox_image(membase, endmem, - arm_barebox_size); + malloc_end = barebox_base; if (IS_ENABLED(CONFIG_MMU_EARLY)) { unsigned long ttb = arm_mem_ttb(membase, endmem); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e60e0ea0c6..b69592e64e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -7,6 +7,7 @@ endif # created. obj- += dummy.o +pbl-dtb-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o pbl-dtb-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o pbl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o pbl-dtb-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o @@ -57,6 +58,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6dl-phytec-phyboard-subra.dtb.o \ imx6q-phytec-phycore-som-nand.dtb.o \ imx6q-phytec-phycore-som-emmc.dtb.o \ + imx6qp-phytec-phycore-som-nand.dtb.o \ imx6dl-phytec-phycore-som-nand.dtb.o \ imx6dl-phytec-phycore-som-emmc.dtb.o \ imx6ul-phytec-phycore-som.dtb.o \ diff --git a/arch/arm/dts/imx6dl-advantech-rom-7421.dts b/arch/arm/dts/imx6dl-advantech-rom-7421.dts new file mode 100755 index 0000000000..1d5fd89264 --- /dev/null +++ b/arch/arm/dts/imx6dl-advantech-rom-7421.dts @@ -0,0 +1,225 @@ +/* + * Copyright(c) 2018 Christoph Fritz <chf.fritz@googlemail.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <arm/imx6dl.dtsi> +#include "imx6dl.dtsi" + +/ { + model = "Advantech i.MX6 ROM-7421"; + compatible = "advantech,imx6dl-rom-7421", "fsl,imx6dl"; + + chosen { + stdout-path = &uart1; + + environment-sd2 { /* Micro SD */ + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-sd4 { /* eMMC */ + compatible = "barebox,environment"; + device-path = &usdhc4, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-spi { /* spi nor */ + compatible = "barebox,environment"; + device-path = &ecspi1, "partname:barebox-environment"; + status = "disabled"; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + status = "okay"; + + flash: m25p80@0 { + compatible = "m25p80"; + spi-max-frequency = <20000000>; + reg = <0>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + fsl,magic-packet; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usdhc2 { /* Micro SD */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + cd-gpios = <&gpio2 0 0>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc3 { /* SD Card */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio2 1 0>; + en-gpios = <&gpio2 2 0>; + wp-gpios = <&gpio2 3 0>; + status = "okay"; +}; + +&usdhc4 { /* eMMC */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0A0B1 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts index bffee5f154..7e4a5aba2a 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts @@ -41,6 +41,14 @@ status = "okay"; }; +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + &usdhc1 { status = "okay"; diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts index 1b66fdabc6..ffcbdc2134 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts @@ -36,6 +36,14 @@ status = "okay"; }; +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + &usdhc1 { status = "okay"; diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi index a6ea7b5cce..63dd966b87 100644 --- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi +++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi @@ -145,18 +145,8 @@ }; partition@420000 { - label = "oftree"; - reg = <0x420000 0x20000>; - }; - - partition@440000 { - label = "kernel"; - reg = <0x440000 0x800000>; - }; - - partition@C40000 { label = "root"; - reg = <0xC40000 0x0>; + reg = <0x420000 0x0>; }; }; diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts index ecc5aa38e1..6e12b26d38 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts @@ -40,6 +40,14 @@ status = "okay"; }; +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + &usdhc1 { status = "okay"; diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts index 9ad7eda740..d9e37b7fca 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts @@ -45,6 +45,14 @@ status = "okay"; }; +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + &usdhc1 { status = "okay"; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index 7cc8be1951..8bb9ec8db7 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -115,18 +115,8 @@ }; partition@500000 { - label = "oftree"; - reg = <0x500000 0x100000>; - }; - - partition@600000 { - label = "kernel"; - reg = <0x600000 0x800000>; - }; - - partition@e00000 { label = "root"; - reg = <0xe00000 0x0>; + reg = <0x500000 0x0>; }; }; diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi index c492b2ea47..ec14415398 100644 --- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi @@ -32,6 +32,34 @@ device-path = &gpmi, "partname:barebox-environment"; status = "disabled"; }; + + environment-spinor { + compatible = "barebox,environment"; + device-path = &flash, "partname:barebox-environment"; + status = "disabled"; + }; + }; + + reg_usbh1_vbus: regulator-usbh1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: regulator-usbotg { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; @@ -42,8 +70,8 @@ cs-gpios = <&gpio3 19 0>; status = "disabled"; - flash: m25p80@0 { - compatible = "m25p80"; + flash: flash@0 { + compatible = "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; status = "disabled"; @@ -112,18 +140,8 @@ }; partition@500000 { - label = "oftree"; - reg = <0x500000 0x100000>; - }; - - partition@600000 { - label = "kernel"; - reg = <0x600000 0x800000>; - }; - - partition@e00000 { label = "root"; - reg = <0xe00000 0x0>; + reg = <0x500000 0x0>; }; }; @@ -151,104 +169,118 @@ }; &iomuxc { - pinctrl-names = "default"; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; - imx6qdl-phytec-phycore-som { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x80000000 + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x80000000 - >; - }; + pinctrl_gpmi_nand: gpmigrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 + MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; - pinctrl_gpmi_nand: gpmigrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 - MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_usbh1_vbus: usbh1vbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1 + >; + }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 /* CD */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + pinctrl_usbotg_vbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1 >; - }; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 /* CD */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; }; }; @@ -262,6 +294,20 @@ status = "okay"; }; +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + disable-over-current; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usbotg_vbus>; + disable-over-current; + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; diff --git a/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts new file mode 100644 index 0000000000..c2756142b5 --- /dev/null +++ b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016 Phytec Messtechnik GmbH + * Author: Christian Hemp <c.hemp@phytec.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include <arm/imx6qp.dtsi> +#include "imx6qdl-phytec-phycore-som.dtsi" + +/ { + model = "Phytec phyCORE-i.MX6 Quad with NAND"; + compatible = "phytec,imx6qp-pcm058-nand", "fsl,imx6qp"; +}; + +&ecspi1 { + status = "okay"; +}; + +&eeprom { + status = "okay"; +}; + +ðphy { + max-speed = <1000>; +}; + +&fec { + status = "okay"; +}; + +&flash { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; diff --git a/arch/arm/dts/vf610-ddrmc.dtsi b/arch/arm/dts/vf610-ddrmc.dtsi new file mode 100644 index 0000000000..772131ec28 --- /dev/null +++ b/arch/arm/dts/vf610-ddrmc.dtsi @@ -0,0 +1,15 @@ +/* + * Include file to switch board DTS form using hardcoded memory node + * to dynamic memory size detection based on DDR controller settings + */ + +/ { + /delete-node/ memory; +}; + +&aips1 { + ddrmc@400ae000 { + compatible = "fsl,vf610-ddrmc"; + reg = <0x400ae000 0x1000>; + }; +}; diff --git a/arch/arm/dts/vf610-twr.dts b/arch/arm/dts/vf610-twr.dts index 5947fdbdaa..2456ade5f5 100644 --- a/arch/arm/dts/vf610-twr.dts +++ b/arch/arm/dts/vf610-twr.dts @@ -8,6 +8,7 @@ */ #include <arm/vf610-twr.dts> +#include "vf610-ddrmc.dtsi" &usbdev0 { status = "disabled"; diff --git a/arch/arm/dts/vf610-zii-dev.dtsi b/arch/arm/dts/vf610-zii-dev.dtsi index 4bf81451a6..dc16280bc3 100644 --- a/arch/arm/dts/vf610-zii-dev.dtsi +++ b/arch/arm/dts/vf610-zii-dev.dtsi @@ -40,7 +40,9 @@ n * copy, modify, merge, publish, distribute, sublicense, and/or * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. - */ +*/ + +#include "vf610-ddrmc.dtsi" / { audio_ext: mclk_osc { diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h index fa673a63a7..4803237116 100644 --- a/arch/arm/include/asm/barebox-arm.h +++ b/arch/arm/include/asm/barebox-arm.h @@ -114,8 +114,7 @@ static inline unsigned long arm_mem_ttb(unsigned long membase, unsigned long endmem) { endmem = arm_mem_stack(membase, endmem); - endmem &= ~(SZ_16K - 1); - endmem -= SZ_16K; + endmem = ALIGN_DOWN(endmem, SZ_16K) - SZ_16K; return endmem; } @@ -138,7 +137,7 @@ static inline unsigned long arm_mem_ramoops(unsigned long membase, endmem = arm_mem_ttb(membase, endmem); #ifdef CONFIG_FS_PSTORE_RAMOOPS endmem -= CONFIG_FS_PSTORE_RAMOOPS_SIZE; - endmem &= ~(SZ_4K - 1); /* Align to 4K */ + endmem = ALIGN_DOWN(endmem, SZ_4K); #endif return endmem; @@ -151,9 +150,7 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase, endmem = arm_mem_ramoops(membase, endmem); if (IS_ENABLED(CONFIG_RELOCATABLE)) { - endmem -= size; - endmem &= ~(SZ_1M - 1); - return endmem; + return ALIGN_DOWN(endmem - size, SZ_1M); } else { if (TEXT_BASE >= membase && TEXT_BASE < endmem) return TEXT_BASE; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 9052a94ea0..e6956acbdb 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -393,6 +393,11 @@ config MACH_CM_FX6 bool "CM FX6" select ARCH_IMX6 +config MACH_ADVANTECH_ROM_742X + bool "Advantech ROM 742X" + select ARCH_IMX6 + select ARM_USE_COMPRESSED_DTB + config MACH_WARP7 bool "NXP i.MX7: element 14 WaRP7 Board" select ARCH_IMX7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 8ec846ccef..160ed4b084 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_IMX6) += imx6.o usb-imx6.o CFLAGS_imx6.o := -march=armv7-a lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o obj-$(CONFIG_ARCH_IMX7) += imx7.o +obj-$(CONFIG_ARCH_VF610) += vf610.o obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_IMX_OCOTP) += ocotp.o diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index 72597f5e2d..22cf08e6ad 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -15,6 +15,7 @@ #include <bootsource.h> #include <environment.h> #include <init.h> +#include <linux/bitfield.h> #include <magicvar.h> #include <io.h> @@ -26,6 +27,21 @@ #include <mach/imx53-regs.h> #include <mach/imx6-regs.h> #include <mach/imx7-regs.h> +#include <mach/vf610-regs.h> + + +static void +imx_boot_save_loc(void (*get_boot_source)(enum bootsource *, int *)) +{ + enum bootsource src = BOOTSOURCE_UNKNOWN; + int instance = BOOTSOURCE_INSTANCE_UNKNOWN; + + get_boot_source(&src, &instance); + + bootsource_set(src); + bootsource_set_instance(instance); +} + /* [CTRL][TYPE] */ static const enum bootsource locations[4][4] = { @@ -91,13 +107,7 @@ void imx25_get_boot_source(enum bootsource *src, int *instance) void imx25_boot_save_loc(void) { - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - - imx25_get_boot_source(&src, &instance); - - bootsource_set(src); - bootsource_set_instance(instance); + imx_boot_save_loc(imx25_get_boot_source); } void imx35_get_boot_source(enum bootsource *src, int *instance) @@ -112,13 +122,7 @@ void imx35_get_boot_source(enum bootsource *src, int *instance) void imx35_boot_save_loc(void) { - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - - imx35_get_boot_source(&src, &instance); - - bootsource_set(src); - bootsource_set_instance(instance); + imx_boot_save_loc(imx35_get_boot_source); } #define IMX27_SYSCTRL_GPCR 0x18 @@ -159,13 +163,7 @@ void imx27_get_boot_source(enum bootsource *src, int *instance) void imx27_boot_save_loc(void) { - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - - imx27_get_boot_source(&src, &instance); - - bootsource_set(src); - bootsource_set_instance(instance); + imx_boot_save_loc(imx27_get_boot_source); } #define IMX51_SRC_SBMR 0x4 @@ -203,36 +201,82 @@ void imx51_get_boot_source(enum bootsource *src, int *instance) void imx51_boot_save_loc(void) { - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; + imx_boot_save_loc(imx51_get_boot_source); +} - imx51_get_boot_source(&src, &instance); +#define IMX53_SRC_SBMR 0x4 +#define SRC_SBMR_BMOD GENMASK(25, 24) +#define IMX53_BMOD_SERIAL 0b11 + +#define __BOOT_CFG(n, m, l) GENMASK((m) + ((n) - 1) * 8, \ + (l) + ((n) - 1) * 8) +#define BOOT_CFG1(m, l) __BOOT_CFG(1, m, l) +#define BOOT_CFG2(m, l) __BOOT_CFG(2, m, l) +#define BOOT_CFG3(m, l) __BOOT_CFG(3, m, l) +#define BOOT_CFG4(m, l) __BOOT_CFG(4, m, l) + +#define ___BOOT_CFG(n, i) __BOOT_CFG(n, i, i) +#define __MAKE_BOOT_CFG_BITS(idx) \ + enum { \ + BOOT_CFG##idx##_0 = ___BOOT_CFG(idx, 0), \ + BOOT_CFG##idx##_1 = ___BOOT_CFG(idx, 1), \ + BOOT_CFG##idx##_2 = ___BOOT_CFG(idx, 2), \ + BOOT_CFG##idx##_3 = ___BOOT_CFG(idx, 3), \ + BOOT_CFG##idx##_4 = ___BOOT_CFG(idx, 4), \ + BOOT_CFG##idx##_5 = ___BOOT_CFG(idx, 5), \ + BOOT_CFG##idx##_6 = ___BOOT_CFG(idx, 6), \ + BOOT_CFG##idx##_7 = ___BOOT_CFG(idx, 7), \ + }; - bootsource_set(src); - bootsource_set_instance(instance); +__MAKE_BOOT_CFG_BITS(1) +__MAKE_BOOT_CFG_BITS(2) +__MAKE_BOOT_CFG_BITS(4) +#undef __MAKE_BOOT_CFG +#undef ___BOOT_CFG + + +static unsigned int imx53_get_bmod(uint32_t r) +{ + return FIELD_GET(SRC_SBMR_BMOD, r); +} + +static int imx53_bootsource_internal(uint32_t r) +{ + return FIELD_GET(BOOT_CFG1(7, 4), r); +} + +static int imx53_port_select(uint32_t r) +{ + return FIELD_GET(BOOT_CFG3(5, 4), r); +} + +static bool imx53_bootsource_nand(uint32_t r) +{ + return FIELD_GET(BOOT_CFG1_7, r); +} + +static enum bootsource imx53_bootsource_serial_rom(uint32_t r) +{ + return BOOT_CFG1(r, 3) ? BOOTSOURCE_SPI : BOOTSOURCE_I2C; } -#define IMX53_SRC_SBMR 0x4 void imx53_get_boot_source(enum bootsource *src, int *instance) { void __iomem *src_base = IOMEM(MX53_SRC_BASE_ADDR); uint32_t cfg1 = readl(src_base + IMX53_SRC_SBMR); - if (((cfg1 >> 24) & 0x3) == 0x3) { + if (imx53_get_bmod(cfg1) == IMX53_BMOD_SERIAL) { *src = BOOTSOURCE_USB; *instance = 0; return; } - switch ((cfg1 & 0xff) >> 4) { + switch (imx53_bootsource_internal(cfg1)) { case 2: *src = BOOTSOURCE_HD; break; case 3: - if (cfg1 & (1 << 3)) - *src = BOOTSOURCE_SPI; - else - *src = BOOTSOURCE_I2C; + *src = imx53_bootsource_serial_rom(cfg1); break; case 4: case 5: @@ -241,18 +285,16 @@ void imx53_get_boot_source(enum bootsource *src, int *instance) *src = BOOTSOURCE_MMC; break; default: + if (imx53_bootsource_nand(cfg1)) + *src = BOOTSOURCE_NAND; break; } - if (cfg1 & (1 << 7)) - *src = BOOTSOURCE_NAND; - - switch (*src) { case BOOTSOURCE_MMC: case BOOTSOURCE_SPI: case BOOTSOURCE_I2C: - *instance = (cfg1 >> 20) & 0x3; + *instance = imx53_port_select(cfg1); break; default: *instance = 0; @@ -273,123 +315,206 @@ void imx53_boot_save_loc(void) #define IMX6_SRC_SBMR1 0x04 #define IMX6_SRC_SBMR2 0x1c +#define IMX6_BMOD_SERIAL 0b01 +#define IMX6_BMOD_RESERVED 0b11 +#define IMX6_BMOD_FUSES 0b00 +#define BT_FUSE_SEL BIT(4) + +static bool imx6_bootsource_reserved(uint32_t sbmr2) +{ + return imx53_get_bmod(sbmr2) == IMX6_BMOD_RESERVED; +} + +static bool imx6_bootsource_serial(uint32_t sbmr2) +{ + return imx53_get_bmod(sbmr2) == IMX6_BMOD_SERIAL || + /* + * If boot from fuses is selected and fuses are not + * programmed by setting BT_FUSE_SEL, ROM code will + * fallback to serial mode + */ + (imx53_get_bmod(sbmr2) == IMX6_BMOD_FUSES && + !(sbmr2 & BT_FUSE_SEL)); +} + +static int __imx6_bootsource_serial_rom(uint32_t r) +{ + return FIELD_GET(BOOT_CFG4(2, 0), r); +} + +/* + * Serial ROM bootsource on i.MX6 are as follows: + * + * 000 - ECSPI-1 + * 001 - ECSPI-2 + * 010 - ECSPI-3 + * 011 - ECSPI-4 + * 100 - ECSPI-5 + * 101 - I2C1 + * 110 - I2C2 + * 111 - I2C3 + * + * There's no single bit that would tell us we are booting from I2C or + * SPI, so we just have to compare the "source" agains the value for + * I2C1 for both: calculating bootsource and boot instance. + */ +#define IMX6_BOOTSOURCE_SERIAL_ROM_I2C1 0b101 + +static enum bootsource imx6_bootsource_serial_rom(uint32_t sbmr) +{ + const int source = __imx6_bootsource_serial_rom(sbmr); + + return source < IMX6_BOOTSOURCE_SERIAL_ROM_I2C1 ? + BOOTSOURCE_SPI_NOR : BOOTSOURCE_I2C; +} + +static int imx6_boot_instance_serial_rom(uint32_t sbmr) +{ + const int source = __imx6_bootsource_serial_rom(sbmr); + + if (source < IMX6_BOOTSOURCE_SERIAL_ROM_I2C1) + return source; + + return source - IMX6_BOOTSOURCE_SERIAL_ROM_I2C1; +} + +static int imx6_boot_instance_mmc(uint32_t r) +{ + return FIELD_GET(BOOT_CFG2(4, 3), r); +} void imx6_get_boot_source(enum bootsource *src, int *instance) { void __iomem *src_base = IOMEM(MX6_SRC_BASE_ADDR); uint32_t sbmr1 = readl(src_base + IMX6_SRC_SBMR1); uint32_t sbmr2 = readl(src_base + IMX6_SRC_SBMR2); - uint32_t boot_cfg_4_2_0; - int boot_mode; - /* BMOD[1:0] */ - boot_mode = (sbmr2 >> 24) & 0x3; + if (imx6_bootsource_reserved(sbmr2)) + return; - switch (boot_mode) { - case 0: /* Fuses, fall through */ - case 2: /* internal boot */ - goto internal_boot; - case 1: /* Serial Downloader */ + if (imx6_bootsource_serial(sbmr2)) { *src = BOOTSOURCE_SERIAL; - break; - case 3: /* reserved */ - break; - }; - - return; - -internal_boot: + return; + } - /* BOOT_CFG1[7:4] */ - switch ((sbmr1 >> 4) & 0xf) { + switch (imx53_bootsource_internal(sbmr1)) { case 2: *src = BOOTSOURCE_HD; break; case 3: - /* BOOT_CFG4[2:0] */ - boot_cfg_4_2_0 = (sbmr1 >> 24) & 0x7; - - if (boot_cfg_4_2_0 > 4) { - *src = BOOTSOURCE_I2C; - *instance = boot_cfg_4_2_0 - 5; - } else { - *src = BOOTSOURCE_SPI; - *instance = boot_cfg_4_2_0; - } + *src = imx6_bootsource_serial_rom(sbmr1); + *instance = imx6_boot_instance_serial_rom(sbmr1); break; case 4: case 5: case 6: case 7: *src = BOOTSOURCE_MMC; - - /* BOOT_CFG2[4:3] */ - *instance = (sbmr1 >> 11) & 0x3; + *instance = imx6_boot_instance_mmc(sbmr1); break; default: + if (imx53_bootsource_nand(sbmr1)) + *src = BOOTSOURCE_NAND; break; } - - /* BOOT_CFG1[7:0] */ - if (sbmr1 & (1 << 7)) - *src = BOOTSOURCE_NAND; - - return; } void imx6_boot_save_loc(void) { - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - - imx6_get_boot_source(&src, &instance); - - bootsource_set(src); - bootsource_set_instance(instance); + imx_boot_save_loc(imx6_get_boot_source); } #define IMX7_SRC_SBMR1 0x58 #define IMX7_SRC_SBMR2 0x70 +/* + * Re-defined to match the naming in reference manual + */ +#define BOOT_CFG(m, l) BOOT_CFG1(m, l) + +#define IMX_BOOT_SW_INFO_POINTER_ADDR 0x000001E8 +#define IMX_BOOT_SW_INFO_BDT_SD 0x1 + +static unsigned int imx7_bootsource_internal(uint32_t r) +{ + return FIELD_GET(BOOT_CFG(15, 12), r); +} + +static int imx7_boot_instance_spi_nor(uint32_t r) +{ + return FIELD_GET(BOOT_CFG(11, 9), r); +} + +static int imx7_boot_instance_mmc(uint32_t r) +{ + return FIELD_GET(BOOT_CFG(11, 10), r); +} + +struct imx_boot_sw_info { + uint8_t reserved_1; + uint8_t boot_device_instance; + uint8_t boot_device_type; + uint8_t reserved_2; + uint32_t frequency_hz[4]; /* Various frequencies (ARM, AXI, + * DDR, etc.). Not used */ + uint32_t reserved_3[3]; +} __packed; + void imx7_get_boot_source(enum bootsource *src, int *instance) { void __iomem *src_base = IOMEM(MX7_SRC_BASE_ADDR); uint32_t sbmr1 = readl(src_base + IMX7_SRC_SBMR1); uint32_t sbmr2 = readl(src_base + IMX7_SRC_SBMR2); - int boot_mode; - /* BMOD[1:0] */ - boot_mode = (sbmr2 >> 24) & 0x3; - - switch (boot_mode) { - case 0: /* Fuses, fall through */ - case 2: /* internal boot */ - goto internal_boot; - case 1: /* Serial Downloader */ - *src = BOOTSOURCE_SERIAL; - break; - case 3: /* reserved */ - break; - }; + if (imx6_bootsource_reserved(sbmr2)) + return; - return; + if (imx6_bootsource_serial(sbmr2)) { + /* + * On i.MX7 ROM code will try to bood from uSDHC1 + * before entering serial mode. It doesn't seem to be + * reflected in the contents of SBMR1 in any way when + * that happens, so we check "Boot_SW_Info" structure + * (per 6.6.14 Boot information for software) to see + * if that really happened. + * + * FIXME: This behaviour can be inhibited by + * DISABLE_SDMMC_MFG, but location of that fuse + * doesn't seem to be documented anywhere. Once that + * is known it should be taken into account here. + */ + const struct imx_boot_sw_info *info; + + info = (const void *)readl(IMX_BOOT_SW_INFO_POINTER_ADDR); + + if (info->boot_device_type == IMX_BOOT_SW_INFO_BDT_SD) { + *src = BOOTSOURCE_MMC; + /* + * We are expecting to only ever boot from + * uSDHC1 here + */ + WARN_ON(*instance = info->boot_device_instance); + return; + } -internal_boot: + *src = BOOTSOURCE_SERIAL; + return; + } - switch ((sbmr1 >> 12) & 0xf) { + switch (imx7_bootsource_internal(sbmr1)) { case 1: case 2: *src = BOOTSOURCE_MMC; - *instance = (sbmr1 >> 10 & 0x3); + *instance = imx7_boot_instance_mmc(sbmr1); break; case 3: *src = BOOTSOURCE_NAND; break; - case 4: + case 6: *src = BOOTSOURCE_SPI_NOR, - *instance = (sbmr1 >> 9 & 0x7); + *instance = imx7_boot_instance_spi_nor(sbmr1); break; - case 6: + case 4: *src = BOOTSOURCE_SPI; /* Really: qspi */ break; case 5: @@ -398,21 +523,103 @@ internal_boot: default: break; } +} - /* BOOT_CFG1[7:0] */ - if (sbmr1 & (1 << 7)) - *src = BOOTSOURCE_NAND; +void imx7_boot_save_loc(void) +{ + imx_boot_save_loc(imx7_get_boot_source); +} - return; +static int vf610_boot_instance_spi(uint32_t r) +{ + return FIELD_GET(BOOT_CFG1_1, r); } -void imx7_boot_save_loc(void) +static int vf610_boot_instance_nor(uint32_t r) { - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; + return FIELD_GET(BOOT_CFG1_3, r); +} + +/* + * Vybrid's Serial ROM boot sources (BOOT_CFG4[2:0]) are as follows: + * + * 000 - SPI0 + * 001 - SPI1 + * 010 - SPI2 + * 011 - SPI3 + * 100 - I2C0 + * 101 - I2C1 + * 110 - I2C2 + * 111 - I2C3 + * + * Which we can neatly divide in two halves and use MSb to detect if + * bootsource is I2C or SPI EEPROM and 2 LSbs directly as boot + * insance. + */ +static enum bootsource vf610_bootsource_serial_rom(uint32_t r) +{ + return FIELD_GET(BOOT_CFG4_2, r) ? BOOTSOURCE_I2C : BOOTSOURCE_SPI_NOR; +} - imx7_get_boot_source(&src, &instance); +static int vf610_boot_instance_serial_rom(uint32_t r) +{ + return __imx6_bootsource_serial_rom(r) & 0b11; +} - bootsource_set(src); - bootsource_set_instance(instance); +static int vf610_boot_instance_can(uint32_t r) +{ + return FIELD_GET(BOOT_CFG1_0, r); +} + +static int vf610_boot_instance_mmc(uint32_t r) +{ + return FIELD_GET(BOOT_CFG2_3, r); +} + +void vf610_get_boot_source(enum bootsource *src, int *instance) +{ + void __iomem *src_base = IOMEM(VF610_SRC_BASE_ADDR); + uint32_t sbmr1 = readl(src_base + IMX6_SRC_SBMR1); + uint32_t sbmr2 = readl(src_base + IMX6_SRC_SBMR2); + + if (imx6_bootsource_reserved(sbmr2)) + return; + + if (imx6_bootsource_serial(sbmr2)) { + *src = BOOTSOURCE_SERIAL; + return; + } + + switch (imx53_bootsource_internal(sbmr1)) { + case 0: + *src = BOOTSOURCE_SPI; /* Really: qspi */ + *instance = vf610_boot_instance_spi(sbmr1); + break; + case 1: + *src = BOOTSOURCE_NOR; + *instance = vf610_boot_instance_nor(sbmr1); + break; + case 2: + *src = vf610_bootsource_serial_rom(sbmr1); + *instance = vf610_boot_instance_serial_rom(sbmr1); + break; + case 3: + *src = BOOTSOURCE_CAN; + *instance = vf610_boot_instance_can(sbmr1); + break; + case 6: + case 7: + *src = BOOTSOURCE_MMC; + *instance = vf610_boot_instance_mmc(sbmr1); + break; + default: + if (imx53_bootsource_nand(sbmr1)) + *src = BOOTSOURCE_NAND; + break; + } +} + +void vf610_boot_save_loc(void) +{ + imx_boot_save_loc(vf610_get_boot_source); } diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 1eebc77b63..c1680d5ff8 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -37,6 +37,7 @@ #include <mach/imx51-regs.h> #include <mach/imx53-regs.h> #include <mach/imx6-regs.h> +#include <mach/vf610-ddrmc.h> struct imx_esdctl_data { unsigned long base0; @@ -75,12 +76,9 @@ static inline unsigned long imx_v1_sdram_size(void __iomem *esdctlbase, int num) if (ctlval & (1 << 17)) width = 4; - size = (1 << cols) * (1 << rows) * banks * width; + size = memory_sdram_size(cols, rows, banks, width); - if (size > SZ_64M) - size = SZ_64M; - - return size; + return min_t(unsigned long, size, SZ_64M); } /* @@ -103,12 +101,9 @@ static inline unsigned long imx_v2_sdram_size(void __iomem *esdctlbase, int num) if ((ctlval & ESDCTL0_DSIZ_MASK) == ESDCTL0_DSIZ_31_0) width = 4; - size = (1 << cols) * (1 << rows) * banks * width; - - if (size > SZ_256M) - size = SZ_256M; + size = memory_sdram_size(cols, rows, banks, width); - return size; + return min_t(unsigned long, size, SZ_256M); } /* @@ -120,13 +115,10 @@ static inline unsigned long imx_v3_sdram_size(void __iomem *esdctlbase, int num) size = imx_v2_sdram_size(esdctlbase, num); - if (readl(esdctlbase + IMX_ESDMISC) & (1 << 6)) + if (readl(esdctlbase + IMX_ESDMISC) & ESDMISC_DDR2_8_BANK) size *= 2; - if (size > SZ_256M) - size = SZ_256M; - - return size; + return min_t(unsigned long, size, SZ_256M); } /* @@ -136,7 +128,6 @@ static inline unsigned long imx_v4_sdram_size(void __iomem *esdctlbase, int cs) { u32 ctlval = readl(esdctlbase + ESDCTL_V4_ESDCTL0); u32 esdmisc = readl(esdctlbase + ESDCTL_V4_ESDMISC); - unsigned long size; int rows, cols, width = 2, banks = 8; if (cs == 0 && !(ctlval & ESDCTL_V4_ESDCTLx_SDE0)) @@ -162,20 +153,17 @@ static inline unsigned long imx_v4_sdram_size(void __iomem *esdctlbase, int cs) if (esdmisc & ESDCTL_V4_ESDMISC_BANKS_4) banks = 4; - size = (1 << cols) * (1 << rows) * banks * width; - - return size; + return memory_sdram_size(cols, rows, banks, width); } /* * MMDC - found on i.MX6 */ -static inline u64 imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs) +static inline u64 __imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs) { u32 ctlval = readl(mmdcbase + MDCTL); u32 mdmisc = readl(mmdcbase + MDMISC); - u64 size; int rows, cols, width = 2, banks = 8; if (cs == 0 && !(ctlval & MMDCx_MDCTL_SDE0)) @@ -201,9 +189,7 @@ static inline u64 imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs) if (mdmisc & MMDCx_MDMISC_DDR_4_BANKS) banks = 4; - size = (u64)(1 << cols) * (1 << rows) * banks * width; - - return size; + return memory_sdram_size(cols, rows, banks, width); } static void add_mem(unsigned long base0, unsigned long size0, @@ -286,7 +272,7 @@ static void imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data */ #define IMX6_MAX_SDRAM_SIZE 0xF0000000 -static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +static inline resource_size_t imx6_mmdc_sdram_size(void __iomem *mmdcbase) { /* * It is possible to have a configuration in which both chip @@ -296,14 +282,41 @@ static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) * IMX6_MAX_SDRAM_SIZE bytes of memory available. */ - u64 size_cs0 = imx6_mmdc_sdram_size(mmdcbase, 0); - u64 size_cs1 = imx6_mmdc_sdram_size(mmdcbase, 1); + u64 size_cs0 = __imx6_mmdc_sdram_size(mmdcbase, 0); + u64 size_cs1 = __imx6_mmdc_sdram_size(mmdcbase, 1); u64 total = size_cs0 + size_cs1; resource_size_t size = min(total, (u64)IMX6_MAX_SDRAM_SIZE); + return size; +} + +static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ + arm_add_mem_device("ram0", data->base0, + imx6_mmdc_sdram_size(mmdcbase)); +} + +static inline resource_size_t vf610_ddrmc_sdram_size(void __iomem *ddrmc) +{ + const u32 cr01 = readl(ddrmc + DDRMC_CR(1)); + const u32 cr73 = readl(ddrmc + DDRMC_CR(73)); + const u32 cr78 = readl(ddrmc + DDRMC_CR(78)); + + unsigned int rows, cols, width, banks; + + rows = DDRMC_CR01_MAX_ROW_REG(cr01) - DDRMC_CR73_ROW_DIFF(cr73); + cols = DDRMC_CR01_MAX_COL_REG(cr01) - DDRMC_CR73_COL_DIFF(cr73); + banks = 1 << (3 - DDRMC_CR73_BANK_DIFF(cr73)); + width = (cr78 & DDRMC_CR78_REDUC) ? sizeof(u8) : sizeof(u16); + + return memory_sdram_size(cols, rows, banks, width); +} + +static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ arm_add_mem_device("ram0", data->base0, - size); + vf610_ddrmc_sdram_size(mmdcbase)); } static int imx_esdctl_probe(struct device_d *dev) @@ -373,15 +386,20 @@ static __maybe_unused struct imx_esdctl_data imx53_data = { }; static __maybe_unused struct imx_esdctl_data imx6q_data = { - .base0 = MX6_MMDC_PORT0_BASE_ADDR, + .base0 = MX6_MMDC_PORT01_BASE_ADDR, .add_mem = imx6_mmdc_add_mem, }; static __maybe_unused struct imx_esdctl_data imx6ul_data = { - .base0 = 0x80000000, + .base0 = MX6_MMDC_PORT0_BASE_ADDR, .add_mem = imx6_mmdc_add_mem, }; +static __maybe_unused struct imx_esdctl_data vf610_data = { + .base0 = VF610_RAM_BASE_ADDR, + .add_mem = vf610_ddrmc_add_mem, +}; + static struct platform_device_id imx_esdctl_ids[] = { #ifdef CONFIG_ARCH_IMX1 { @@ -441,6 +459,9 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = { .compatible = "fsl,imx6q-mmdc", .data = &imx6q_data }, { + .compatible = "fsl,vf610-ddrmc", + .data = &vf610_data + }, { /* sentinel */ } }; @@ -498,9 +519,9 @@ void __noreturn imx1_barebox_entry(void *boarddata) unsigned long base, size; upper_or_coalesced_range(MX1_CSD0_BASE_ADDR, - imx_v1_sdram_size((void *)MX1_SDRAMC_BASE_ADDR, 0), + imx_v1_sdram_size(IOMEM(MX1_SDRAMC_BASE_ADDR), 0), MX1_CSD1_BASE_ADDR, - imx_v1_sdram_size((void *)MX1_SDRAMC_BASE_ADDR, 1), + imx_v1_sdram_size(IOMEM(MX1_SDRAMC_BASE_ADDR), 1), &base, &size); barebox_arm_entry(base, size, boarddata); @@ -511,9 +532,9 @@ void __noreturn imx25_barebox_entry(void *boarddata) unsigned long base, size; upper_or_coalesced_range(MX25_CSD0_BASE_ADDR, - imx_v2_sdram_size((void *)MX25_ESDCTL_BASE_ADDR, 0), + imx_v2_sdram_size(IOMEM(MX25_ESDCTL_BASE_ADDR), 0), MX25_CSD1_BASE_ADDR, - imx_v2_sdram_size((void *)MX25_ESDCTL_BASE_ADDR, 1), + imx_v2_sdram_size(IOMEM(MX25_ESDCTL_BASE_ADDR), 1), &base, &size); barebox_arm_entry(base, size, boarddata); @@ -523,12 +544,12 @@ void __noreturn imx27_barebox_entry(void *boarddata) { unsigned long base, size; - imx_esdctl_v2_disable_default((void *)MX27_ESDCTL_BASE_ADDR); + imx_esdctl_v2_disable_default(IOMEM(MX27_ESDCTL_BASE_ADDR)); upper_or_coalesced_range(MX27_CSD0_BASE_ADDR, - imx_v2_sdram_size((void *)MX27_ESDCTL_BASE_ADDR, 0), + imx_v2_sdram_size(IOMEM(MX27_ESDCTL_BASE_ADDR), 0), MX27_CSD1_BASE_ADDR, - imx_v2_sdram_size((void *)MX27_ESDCTL_BASE_ADDR, 1), + imx_v2_sdram_size(IOMEM(MX27_ESDCTL_BASE_ADDR), 1), &base, &size); barebox_arm_entry(base, size, boarddata); @@ -538,12 +559,12 @@ void __noreturn imx31_barebox_entry(void *boarddata) { unsigned long base, size; - imx_esdctl_v2_disable_default((void *)MX31_ESDCTL_BASE_ADDR); + imx_esdctl_v2_disable_default(IOMEM(MX31_ESDCTL_BASE_ADDR)); upper_or_coalesced_range(MX31_CSD0_BASE_ADDR, - imx_v2_sdram_size((void *)MX31_ESDCTL_BASE_ADDR, 0), + imx_v2_sdram_size(IOMEM(MX31_ESDCTL_BASE_ADDR), 0), MX31_CSD1_BASE_ADDR, - imx_v2_sdram_size((void *)MX31_ESDCTL_BASE_ADDR, 1), + imx_v2_sdram_size(IOMEM(MX31_ESDCTL_BASE_ADDR), 1), &base, &size); barebox_arm_entry(base, size, boarddata); @@ -553,12 +574,12 @@ void __noreturn imx35_barebox_entry(void *boarddata) { unsigned long base, size; - imx_esdctl_v2_disable_default((void *)MX35_ESDCTL_BASE_ADDR); + imx_esdctl_v2_disable_default(IOMEM(MX35_ESDCTL_BASE_ADDR)); upper_or_coalesced_range(MX35_CSD0_BASE_ADDR, - imx_v2_sdram_size((void *)MX35_ESDCTL_BASE_ADDR, 0), + imx_v2_sdram_size(IOMEM(MX35_ESDCTL_BASE_ADDR), 0), MX35_CSD1_BASE_ADDR, - imx_v2_sdram_size((void *)MX35_ESDCTL_BASE_ADDR, 1), + imx_v2_sdram_size(IOMEM(MX35_ESDCTL_BASE_ADDR), 1), &base, &size); barebox_arm_entry(base, size, boarddata); @@ -569,9 +590,9 @@ void __noreturn imx51_barebox_entry(void *boarddata) unsigned long base, size; upper_or_coalesced_range(MX51_CSD0_BASE_ADDR, - imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 0), + imx_v3_sdram_size(IOMEM(MX51_ESDCTL_BASE_ADDR), 0), MX51_CSD1_BASE_ADDR, - imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 1), + imx_v3_sdram_size(IOMEM(MX51_ESDCTL_BASE_ADDR), 1), &base, &size); barebox_arm_entry(base, size, boarddata); @@ -582,32 +603,35 @@ void __noreturn imx53_barebox_entry(void *boarddata) unsigned long base, size; upper_or_coalesced_range(MX53_CSD0_BASE_ADDR, - imx_v4_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 0), + imx_v4_sdram_size(IOMEM(MX53_ESDCTL_BASE_ADDR), 0), MX53_CSD1_BASE_ADDR, - imx_v4_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 1), + imx_v4_sdram_size(IOMEM(MX53_ESDCTL_BASE_ADDR), 1), &base, &size); barebox_arm_entry(base, size, boarddata); } -void __noreturn imx6q_barebox_entry(void *boarddata) +static void __noreturn +imx6_barebox_entry(unsigned long membase, void *boarddata) { - u64 size_cs0 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 0); - u64 size_cs1 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 1); - u64 total = size_cs0 + size_cs1; - - resource_size_t size = min(total, (u64)IMX6_MAX_SDRAM_SIZE); + barebox_arm_entry(membase, + imx6_mmdc_sdram_size(IOMEM(MX6_MMDC_P0_BASE_ADDR)), + boarddata); +} - barebox_arm_entry(0x10000000, size, boarddata); +void __noreturn imx6q_barebox_entry(void *boarddata) +{ + imx6_barebox_entry(MX6_MMDC_PORT01_BASE_ADDR, boarddata); } void __noreturn imx6ul_barebox_entry(void *boarddata) { - u64 size_cs0 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 0); - u64 size_cs1 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 1); - u64 total = size_cs0 + size_cs1; - - resource_size_t size = min(total, (u64)IMX6_MAX_SDRAM_SIZE); + imx6_barebox_entry(MX6_MMDC_PORT0_BASE_ADDR, boarddata); +} - barebox_arm_entry(0x80000000, size, boarddata); +void __noreturn vf610_barebox_entry(void *boarddata) +{ + barebox_arm_entry(VF610_RAM_BASE_ADDR, + vf610_ddrmc_sdram_size(IOMEM(VF610_DDR_BASE_ADDR)), + boarddata); } diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 9400105c66..1b4c1b3df1 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -14,8 +14,10 @@ #include <common.h> #include <of.h> #include <init.h> +#include <io.h> #include <mach/revision.h> #include <mach/generic.h> +#include <mach/reset-reason.h> static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN; @@ -28,7 +30,10 @@ void imx_set_silicon_revision(const char *soc, int revision) { __imx_silicon_revision = revision; - pr_info("detected %s revision %d.%d\n", soc, + if (revision == IMX_CHIP_REV_UNKNOWN) + pr_info("detected %s revision unknown\n", soc); + else + pr_info("detected %s revision %d.%d\n", soc, (revision >> 4) & 0xf, revision & 0xf); } @@ -114,7 +119,7 @@ static int imx_init(void) else if (cpu_is_mx7()) ret = imx7_init(); else if (cpu_is_vf610()) - ret = 0; + ret = vf610_init(); else return -EINVAL; @@ -147,3 +152,46 @@ static int imx_init(void) return ret; } postcore_initcall(imx_init); + +const struct imx_reset_reason imx_reset_reasons[] = { + { IMX_SRC_SRSR_IPP_RESET, RESET_POR, 0 }, + { IMX_SRC_SRSR_WDOG1_RESET, RESET_WDG, 0 }, + { IMX_SRC_SRSR_JTAG_RESET, RESET_JTAG, 0 }, + { IMX_SRC_SRSR_JTAG_SW_RESET, RESET_JTAG, 0 }, + { IMX_SRC_SRSR_WARM_BOOT, RESET_RST, 0 }, + { /* sentinel */ } +}; + +void imx_set_reset_reason(void __iomem *srsr, + const struct imx_reset_reason *reasons) +{ + enum reset_src_type type = RESET_UKWN; + const u32 reg = readl(srsr); + int i, instance = 0; + + /* + * SRSR register captures ALL reset event that occured since + * POR, so we need to clear it to make sure we only caputre + * the latest one. + */ + writel(reg, srsr); + + for (i = 0; reasons[i].mask; i++) { + if (reg & reasons[i].mask) { + type = reasons[i].type; + instance = reasons[i].instance; + break; + } + } + + /* + * Report this with above default priority in order to make + * sure we'll always override info from watchdog driver. + */ + reset_source_set_priority(type, + RESET_SOURCE_DEFAULT_PRIORITY + 1); + reset_source_set_instance(type, instance); + + pr_info("i.MX reset reason %s (SRSR: 0x%08x)\n", + reset_source_name(), reg); +} diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index ffe6a7c651..ec8cdd868b 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -21,6 +21,7 @@ #include <mach/revision.h> #include <mach/clock-imx51_53.h> #include <mach/generic.h> +#include <mach/reset-reason.h> #define IIM_SREV 0x24 @@ -43,7 +44,7 @@ static int imx51_silicon_revision(void) static void imx51_ipu_mipi_setup(void) { - void __iomem *hsc_addr = (void __iomem *)MX51_MIPI_HSC_BASE_ADDR; + void __iomem *hsc_addr = IOMEM(MX51_MIPI_HSC_BASE_ADDR); u32 val; /* setup MIPI module to legacy mode */ @@ -57,7 +58,10 @@ static void imx51_ipu_mipi_setup(void) int imx51_init(void) { + void __iomem *src = IOMEM(MX51_SRC_BASE_ADDR); + imx_set_silicon_revision("i.MX51", imx51_silicon_revision()); + imx_set_reset_reason(src + IMX_SRC_SRSR, imx_reset_reasons); imx51_boot_save_loc(); add_generic_device("imx51-esdctl", 0, NULL, MX51_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); imx51_ipu_mipi_setup(); @@ -97,7 +101,7 @@ int imx51_devices_init(void) */ static void imx51_setup_pll800_bug(void) { - void __iomem *base = (void *)MX51_PLL1_BASE_ADDR; + void __iomem *base = IOMEM(MX51_PLL1_BASE_ADDR); u32 dp_config; volatile int i; @@ -132,7 +136,7 @@ static void imx51_setup_pll800_bug(void) void imx51_init_lowlevel(unsigned int cpufreq_mhz) { - void __iomem *ccm = (void __iomem *)MX51_CCM_BASE_ADDR; + void __iomem *ccm = IOMEM(MX51_CCM_BASE_ADDR); u32 r; int rev = imx51_silicon_revision(); @@ -167,30 +171,30 @@ void imx51_init_lowlevel(unsigned int cpufreq_mhz) switch (cpufreq_mhz) { case 600: - imx5_setup_pll_600((void __iomem *)MX51_PLL1_BASE_ADDR); + imx5_setup_pll_600(IOMEM(MX51_PLL1_BASE_ADDR)); break; default: /* Default maximum 800MHz */ if (rev <= IMX_CHIP_REV_3_0) imx51_setup_pll800_bug(); else - imx5_setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR); + imx5_setup_pll_800(IOMEM(MX51_PLL1_BASE_ADDR)); break; } - imx5_setup_pll_665((void __iomem *)MX51_PLL3_BASE_ADDR); + imx5_setup_pll_665(IOMEM(MX51_PLL3_BASE_ADDR)); /* Switch peripheral to PLL 3 */ writel(0x000010C0, ccm + MX5_CCM_CBCMR); writel(0x13239145, ccm + MX5_CCM_CBCDR); - imx5_setup_pll_665((void __iomem *)MX51_PLL2_BASE_ADDR); + imx5_setup_pll_665(IOMEM(MX51_PLL2_BASE_ADDR)); /* Switch peripheral to PLL2 */ writel(0x19239145, ccm + MX5_CCM_CBCDR); writel(0x000020C0, ccm + MX5_CCM_CBCMR); - imx5_setup_pll_216((void __iomem *)MX51_PLL3_BASE_ADDR); + imx5_setup_pll_216(IOMEM(MX51_PLL3_BASE_ADDR)); /* Set the platform clock dividers */ writel(0x00000125, MX51_ARM_BASE_ADDR + 0x14); diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c index 2758f1bbcf..56f1bda75e 100644 --- a/arch/arm/mach-imx/imx53.c +++ b/arch/arm/mach-imx/imx53.c @@ -21,6 +21,7 @@ #include <mach/revision.h> #include <mach/clock-imx51_53.h> #include <mach/generic.h> +#include <mach/reset-reason.h> #define SI_REV 0x48 @@ -52,7 +53,10 @@ static int imx53_silicon_revision(void) int imx53_init(void) { + void __iomem *src = IOMEM(MX53_SRC_BASE_ADDR); + imx53_silicon_revision(); + imx_set_reset_reason(src + IMX_SRC_SRSR, imx_reset_reasons); imx53_boot_save_loc(); add_generic_device("imx53-esdctl", 0, NULL, MX53_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 14a1cba5a4..eaf9f2e413 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -16,9 +16,11 @@ #include <io.h> #include <linux/sizes.h> #include <mfd/imx6q-iomuxc-gpr.h> +#include <mach/clock-imx6.h> #include <mach/imx6.h> #include <mach/generic.h> #include <mach/revision.h> +#include <mach/reset-reason.h> #include <mach/imx6-anadig.h> #include <mach/imx6-regs.h> #include <mach/generic.h> @@ -44,6 +46,11 @@ static void imx6_init_lowlevel(void) void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR; bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q; bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D; + uint32_t val_480; + uint32_t val_528; + uint32_t periph_sel_1; + uint32_t periph_sel_2; + uint32_t reg; /* * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -68,32 +75,38 @@ static void imx6_init_lowlevel(void) /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs * to make sure PFD is working right, otherwise, PFDs may * not output clock after reset, MX6DL and MX6SL have added 396M pfd - * workaround in ROM code, as bus clock need it + * workaround in ROM code, as bus clock need it. + * Don't reset PLL2 PFD0 / PLL2 PFD2 if is's used by periph_clk. */ if (is_imx6q || is_imx6d) { - writel(BM_ANADIG_PFD_480_PFD3_CLKGATE | - BM_ANADIG_PFD_480_PFD2_CLKGATE | - BM_ANADIG_PFD_480_PFD1_CLKGATE | - BM_ANADIG_PFD_480_PFD0_CLKGATE, - MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET); - writel(BM_ANADIG_PFD_528_PFD3_CLKGATE | - BM_ANADIG_PFD_528_PFD2_CLKGATE | - BM_ANADIG_PFD_528_PFD1_CLKGATE | - BM_ANADIG_PFD_528_PFD0_CLKGATE, - MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET); - - writel(BM_ANADIG_PFD_480_PFD3_CLKGATE | - BM_ANADIG_PFD_480_PFD2_CLKGATE | - BM_ANADIG_PFD_480_PFD1_CLKGATE | - BM_ANADIG_PFD_480_PFD0_CLKGATE, - MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR); - writel(BM_ANADIG_PFD_528_PFD3_CLKGATE | - BM_ANADIG_PFD_528_PFD2_CLKGATE | - BM_ANADIG_PFD_528_PFD1_CLKGATE | - BM_ANADIG_PFD_528_PFD0_CLKGATE, - MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR); - } + val_480 = BM_ANADIG_PFD_480_PFD3_CLKGATE | + BM_ANADIG_PFD_480_PFD2_CLKGATE | + BM_ANADIG_PFD_480_PFD1_CLKGATE | + BM_ANADIG_PFD_480_PFD0_CLKGATE; + + val_528 = BM_ANADIG_PFD_528_PFD3_CLKGATE | + BM_ANADIG_PFD_528_PFD1_CLKGATE; + + reg = readl(MXC_CCM_CBCMR); + periph_sel_1 = (reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; + + periph_sel_2 = (reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET; + + if ((periph_sel_1 != 0x2) && (periph_sel_2 != 0x2)) + val_528 |= BM_ANADIG_PFD_528_PFD0_CLKGATE; + + if ((periph_sel_1 != 0x1) && (periph_sel_2 != 0x1) + && (periph_sel_1 != 0x3) && (periph_sel_2 != 0x3)) + val_528 |= BM_ANADIG_PFD_528_PFD2_CLKGATE; + + writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET); + writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET); + writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR); + writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR); + } } static void imx6_setup_ipu_qos(void) @@ -147,10 +160,37 @@ static void imx6ul_enet_clk_init(void) writel(val, gprbase + IOMUXC_GPR1); } +int imx6_cpu_type(void) +{ + static int cpu_type = -1; + + if (!cpu_is_mx6()) + return 0; + + if (cpu_type < 0) + cpu_type = __imx6_cpu_type(); + + return cpu_type; +} + +int imx6_cpu_revision(void) +{ + static int soc_revision = -1; + + if (!cpu_is_mx6()) + return 0; + + if (soc_revision < 0) + soc_revision = __imx6_cpu_revision(); + + return soc_revision; +} + int imx6_init(void) { const char *cputypestr; u32 mx6_silicon_revision; + void __iomem *src = IOMEM(MX6_SRC_BASE_ADDR); imx6_init_lowlevel(); @@ -160,16 +200,16 @@ int imx6_init(void) switch (imx6_cpu_type()) { case IMX6_CPUTYPE_IMX6Q: - if (mx6_silicon_revision >= IMX_CHIP_REV_2_0) - cputypestr = "i.MX6 Quad Plus"; - else - cputypestr = "i.MX6 Quad"; + cputypestr = "i.MX6 Quad"; + break; + case IMX6_CPUTYPE_IMX6QP: + cputypestr = "i.MX6 Quad Plus"; break; case IMX6_CPUTYPE_IMX6D: - if (mx6_silicon_revision >= IMX_CHIP_REV_2_0) - cputypestr = "i.MX6 Dual Plus"; - else - cputypestr = "i.MX6 Dual"; + cputypestr = "i.MX6 Dual"; + break; + case IMX6_CPUTYPE_IMX6DP: + cputypestr = "i.MX6 Dual Plus"; break; case IMX6_CPUTYPE_IMX6DL: cputypestr = "i.MX6 DualLite"; @@ -195,7 +235,7 @@ int imx6_init(void) } imx_set_silicon_revision(cputypestr, mx6_silicon_revision); - + imx_set_reset_reason(src + IMX_SRC_SRSR, imx_reset_reasons); imx6_setup_ipu_qos(); imx6ul_enet_clk_init(); diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c index 4eef99c872..e49baf6f77 100644 --- a/arch/arm/mach-imx/imx7.c +++ b/arch/arm/mach-imx/imx7.c @@ -19,6 +19,7 @@ #include <mach/imx7.h> #include <mach/generic.h> #include <mach/revision.h> +#include <mach/reset-reason.h> #include <mach/imx7-regs.h> void imx7_init_lowlevel(void) @@ -167,10 +168,21 @@ static struct psci_ops imx7_psci_ops = { .cpu_off = imx7_cpu_off, }; +static const struct imx_reset_reason imx7_reset_reasons[] = { + { IMX_SRC_SRSR_IPP_RESET, RESET_POR, 0 }, + { IMX_SRC_SRSR_WDOG1_RESET, RESET_WDG, 0 }, + { IMX_SRC_SRSR_JTAG_RESET, RESET_JTAG, 0 }, + { IMX_SRC_SRSR_JTAG_SW_RESET, RESET_JTAG, 0 }, + { IMX_SRC_SRSR_WDOG3_RESET, RESET_WDG, 1 }, + { IMX_SRC_SRSR_WDOG4_RESET, RESET_WDG, 2 }, + { IMX_SRC_SRSR_TEMPSENSE_RESET, RESET_THERM, 0 }, + { /* sentinel */ } +}; + int imx7_init(void) { const char *cputypestr; - u32 imx7_silicon_revision; + void __iomem *src = IOMEM(MX7_SRC_BASE_ADDR); imx7_init_lowlevel(); @@ -180,8 +192,6 @@ int imx7_init(void) imx7_boot_save_loc(); - imx7_silicon_revision = imx7_cpu_revision(); - psci_set_ops(&imx7_psci_ops); switch (imx7_cpu_type()) { @@ -196,7 +206,8 @@ int imx7_init(void) break; } - imx_set_silicon_revision(cputypestr, imx7_silicon_revision); + imx_set_silicon_revision(cputypestr, imx7_cpu_revision()); + imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons); return 0; } diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h index 66dcc8974c..117e2bbad5 100644 --- a/arch/arm/mach-imx/include/mach/esdctl.h +++ b/arch/arm/mach-imx/include/mach/esdctl.h @@ -48,6 +48,7 @@ #define ESDMISC_MDDR_MDIS 0x00000010 #define ESDMISC_LHD 0x00000020 #define ESDMISC_SDRAMRDY 0x80000000 +#define ESDMISC_DDR2_8_BANK BIT(6) #define ESDCFGx_tXP_MASK 0x00600000 #define ESDCFGx_tXP_1 0x00000000 @@ -137,6 +138,7 @@ void __noreturn imx51_barebox_entry(void *boarddata); void __noreturn imx53_barebox_entry(void *boarddata); void __noreturn imx6q_barebox_entry(void *boarddata); void __noreturn imx6ul_barebox_entry(void *boarddata); +void __noreturn vf610_barebox_entry(void *boarddata); void imx_esdctl_disable(void); #endif diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index f68dc875b0..ad9d9cb022 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -15,6 +15,7 @@ void imx51_boot_save_loc(void); void imx53_boot_save_loc(void); void imx6_boot_save_loc(void); void imx7_boot_save_loc(void); +void vf610_boot_save_loc(void); void imx25_get_boot_source(enum bootsource *src, int *instance); void imx35_get_boot_source(enum bootsource *src, int *instance); @@ -22,6 +23,7 @@ void imx51_get_boot_source(enum bootsource *src, int *instance); void imx53_get_boot_source(enum bootsource *src, int *instance); void imx6_get_boot_source(enum bootsource *src, int *instance); void imx7_get_boot_source(enum bootsource *src, int *instance); +void vf610_get_boot_source(enum bootsource *src, int *instance); int imx1_init(void); int imx21_init(void); @@ -34,6 +36,7 @@ int imx51_init(void); int imx53_init(void); int imx6_init(void); int imx7_init(void); +int vf610_init(void); int imx1_devices_init(void); int imx21_devices_init(void); diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index ac2aa2109f..1ba22b5bc6 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -117,6 +117,8 @@ #define MX6_SATA_BASE_ADDR 0x02200000 -#define MX6_MMDC_PORT0_BASE_ADDR 0x10000000 +#define MX6_MMDC_PORT01_BASE_ADDR 0x10000000 +#define MX6_MMDC_PORT0_BASE_ADDR 0x80000000 + #endif /* __MACH_IMX6_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h index 6b08e6a521..5701bd480c 100644 --- a/arch/arm/mach-imx/include/mach/imx6.h +++ b/arch/arm/mach-imx/include/mach/imx6.h @@ -16,7 +16,9 @@ void __noreturn imx6_pm_stby_poweroff(void); #define IMX6_CPUTYPE_IMX6DL 0x261 #define IMX6_CPUTYPE_IMX6SX 0x462 #define IMX6_CPUTYPE_IMX6D 0x263 +#define IMX6_CPUTYPE_IMX6DP 0x1263 #define IMX6_CPUTYPE_IMX6Q 0x463 +#define IMX6_CPUTYPE_IMX6QP 0x1463 #define IMX6_CPUTYPE_IMX6UL 0x164 #define IMX6_CPUTYPE_IMX6ULL 0x165 @@ -33,36 +35,51 @@ static inline int scu_get_core_count(void) return (ncores & 0x03) + 1; } -static inline int __imx6_cpu_type(void) +#define SI_REV_CPUTYPE(s) (((s) >> 16) & 0xff) +#define SI_REV_MAJOR(s) (((s) >> 8) & 0xf) +#define SI_REV_MINOR(s) ((s) & 0xf) + +static inline uint32_t __imx6_read_si_rev(void) { - uint32_t val; - - val = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV); - val = (val >> 16) & 0xff; - /* non-MX6-standard SI_REV reg offset for MX6SL */ - if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && - val < (IMX6_CPUTYPE_IMX6S & 0xff)) { - uint32_t tmp; - tmp = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV); - tmp = (tmp >> 16) & 0xff; - if ((IMX6_CPUTYPE_IMX6SL & 0xff) == tmp) - /* intentionally skip scu_get_core_count() for MX6SL */ - return IMX6_CPUTYPE_IMX6SL; - } + uint32_t si_rev; + uint32_t cpu_type; + + si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV); + cpu_type = SI_REV_CPUTYPE(si_rev); - val |= scu_get_core_count() << 8; + if (cpu_type >= 0x61 && cpu_type <= 0x65) + return si_rev; - return val; + /* try non-MX6-standard SI_REV reg offset for MX6SL */ + si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV); + cpu_type = SI_REV_CPUTYPE(si_rev); + + if (si_rev == 0x60) + return si_rev; + + return 0; } -static inline int imx6_cpu_type(void) +static inline int __imx6_cpu_type(void) { - if (!cpu_is_mx6()) - return 0; + uint32_t si_rev = __imx6_read_si_rev(); + uint32_t cpu_type = SI_REV_CPUTYPE(si_rev); + + /* intentionally skip scu_get_core_count() for MX6SL */ + if (cpu_type == IMX6_CPUTYPE_IMX6SL) + return IMX6_CPUTYPE_IMX6SL; - return __imx6_cpu_type(); + cpu_type |= scu_get_core_count() << 8; + + if ((cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) && + SI_REV_MAJOR(si_rev) >= 1) + cpu_type |= 0x1000; + + return cpu_type; } +int imx6_cpu_type(void); + #define DEFINE_MX6_CPU_TYPE(str, type) \ static inline int cpu_mx6_is_##str(void) \ { \ @@ -76,10 +93,19 @@ static inline int imx6_cpu_type(void) return cpu_mx6_is_##str(); \ } +/* + * Below are defined: + * + * cpu_is_mx6s(), cpu_is_mx6dl(), cpu_is_mx6q(), cpu_is_mx6qp(), cpu_is_mx6d(), + * cpu_is_mx6dp(), cpu_is_mx6sx(), cpu_is_mx6sl(), cpu_is_mx6ul(), + * cpu_is_mx6ull() + */ DEFINE_MX6_CPU_TYPE(mx6s, IMX6_CPUTYPE_IMX6S); DEFINE_MX6_CPU_TYPE(mx6dl, IMX6_CPUTYPE_IMX6DL); DEFINE_MX6_CPU_TYPE(mx6q, IMX6_CPUTYPE_IMX6Q); +DEFINE_MX6_CPU_TYPE(mx6qp, IMX6_CPUTYPE_IMX6QP); DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D); +DEFINE_MX6_CPU_TYPE(mx6dp, IMX6_CPUTYPE_IMX6DP); DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX); DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL); DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL); @@ -87,27 +113,15 @@ DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL); static inline int __imx6_cpu_revision(void) { - uint32_t rev; - uint32_t si_rev_offset = IMX6_ANATOP_SI_REV; + uint32_t si_rev = __imx6_read_si_rev(); u8 major_part, minor_part; - if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && cpu_mx6_is_mx6sl()) - si_rev_offset = IMX6SL_ANATOP_SI_REV; - - rev = readl(MX6_ANATOP_BASE_ADDR + si_rev_offset); - - major_part = (rev >> 8) & 0xf; - minor_part = rev & 0xf; + major_part = (si_rev >> 8) & 0xf; + minor_part = si_rev & 0xf; return ((major_part + 1) << 4) | minor_part; } -static inline int imx6_cpu_revision(void) -{ - if (!cpu_is_mx6()) - return 0; - - return __imx6_cpu_revision(); -} +int imx6_cpu_revision(void); #endif /* __MACH_IMX6_H */ diff --git a/arch/arm/mach-imx/include/mach/reset-reason.h b/arch/arm/mach-imx/include/mach/reset-reason.h new file mode 100644 index 0000000000..0f644a8c1d --- /dev/null +++ b/arch/arm/mach-imx/include/mach/reset-reason.h @@ -0,0 +1,37 @@ +#ifndef __MACH_RESET_REASON_H__ +#define __MACH_RESET_REASON_H__ + +#include <reset_source.h> + +#define IMX_SRC_SRSR_IPP_RESET BIT(0) +#define IMX_SRC_SRSR_CSU_RESET BIT(2) +#define IMX_SRC_SRSR_IPP_USER_RESET BIT(3) +#define IMX_SRC_SRSR_WDOG1_RESET BIT(4) +#define IMX_SRC_SRSR_JTAG_RESET BIT(5) +#define IMX_SRC_SRSR_JTAG_SW_RESET BIT(6) +#define IMX_SRC_SRSR_WDOG3_RESET BIT(7) +#define IMX_SRC_SRSR_WDOG4_RESET BIT(8) +#define IMX_SRC_SRSR_TEMPSENSE_RESET BIT(9) +#define IMX_SRC_SRSR_WARM_BOOT BIT(16) + +#define IMX_SRC_SRSR 0x008 +#define IMX7_SRC_SRSR 0x05c + +#define VF610_SRC_SRSR_SW_RST BIT(18) +#define VF610_SRC_SRSR_RESETB BIT(7) +#define VF610_SRC_SRSR_JTAG_RST BIT(5) +#define VF610_SRC_SRSR_WDOG_M4 BIT(4) +#define VF610_SRC_SRSR_WDOG_A5 BIT(3) +#define VF610_SRC_SRSR_POR_RST BIT(0) + +struct imx_reset_reason { + uint32_t mask; + enum reset_src_type type; + int instance; +}; + +void imx_set_reset_reason(void __iomem *, const struct imx_reset_reason *); + +extern const struct imx_reset_reason imx_reset_reasons[]; + +#endif /* __MACH_RESET_REASON_H__ */ diff --git a/arch/arm/mach-imx/include/mach/vf610-ddrmc.h b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h new file mode 100644 index 0000000000..07feb036e5 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h @@ -0,0 +1,18 @@ +#ifndef __MACH_DDRMC_H +#define __MACH_DDRMC_H + +#include <mach/vf610-regs.h> + + +#define DDRMC_CR(x) ((x) * 4) + +#define DDRMC_CR01_MAX_COL_REG(reg) (((reg) >> 8) & 0b01111) +#define DDRMC_CR01_MAX_ROW_REG(reg) (((reg) >> 0) & 0b11111) +#define DDRMC_CR73_COL_DIFF(reg) (((reg) >> 16) & 0b00111) +#define DDRMC_CR73_ROW_DIFF(reg) (((reg) >> 8) & 0b00011) +#define DDRMC_CR73_BANK_DIFF(reg) (((reg) >> 0) & 0b00011) + +#define DDRMC_CR78_REDUC BIT(8) + + +#endif /* __MACH_MMDC_H */ diff --git a/arch/arm/mach-imx/include/mach/vf610-regs.h b/arch/arm/mach-imx/include/mach/vf610-regs.h index 8be220b68c..416b457aff 100644 --- a/arch/arm/mach-imx/include/mach/vf610-regs.h +++ b/arch/arm/mach-imx/include/mach/vf610-regs.h @@ -13,6 +13,8 @@ #define VF610_AIPS0_BASE_ADDR 0x40000000 #define VF610_AIPS1_BASE_ADDR 0x40080000 +#define VF610_RAM_BASE_ADDR 0x80000000 + /* AIPS 0 */ #define VF610_MSCM_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001000) #define VF610_MSCM_IR_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001800) @@ -107,4 +109,7 @@ #define VF610_MSCM_IRSPRC_CP0_EN 1 #define VF610_MSCM_IRSPRC_NUM 112 +#define VF610_MSCM_CPxCOUNT 0x00c +#define VF610_MSCM_CPxCFG1 0x014 + #endif diff --git a/arch/arm/mach-imx/include/mach/vf610.h b/arch/arm/mach-imx/include/mach/vf610.h new file mode 100644 index 0000000000..6d00d2e457 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/vf610.h @@ -0,0 +1,51 @@ +#ifndef __MACH_VF610_H +#define __MACH_VF610_H + +#include <io.h> +#include <mach/generic.h> +#include <mach/vf610-regs.h> +#include <mach/revision.h> + +#define VF610_CPUTYPE_VFx10 0x010 + +#define VF610_CPUTYPE_VF610 0x610 +#define VF610_CPUTYPE_VF600 0x600 +#define VF610_CPUTYPE_VF510 0x510 +#define VF610_CPUTYPE_VF500 0x500 + +#define VF610_ROM_VERSION_OFFSET 0x80 + +static inline int __vf610_cpu_type(void) +{ + void __iomem *mscm = IOMEM(VF610_MSCM_BASE_ADDR); + const u32 cpxcount = readl(mscm + VF610_MSCM_CPxCOUNT); + const u32 cpxcfg1 = readl(mscm + VF610_MSCM_CPxCFG1); + int cpu_type; + + cpu_type = cpxcount ? VF610_CPUTYPE_VF600 : VF610_CPUTYPE_VF500; + + return cpxcfg1 ? cpu_type | VF610_CPUTYPE_VFx10 : cpu_type; +} + +static inline int vf610_cpu_type(void) +{ + if (!cpu_is_vf610()) + return 0; + + return __vf610_cpu_type(); +} + +static inline int vf610_cpu_revision(void) +{ + if (!cpu_is_vf610()) + return IMX_CHIP_REV_UNKNOWN; + + /* + * There doesn't seem to be a documented way of retreiving + * silicon revision on VFxxx cpus, so we just report Mask ROM + * version instead + */ + return readl(VF610_ROM_VERSION_OFFSET) & 0xff; +} + +#endif diff --git a/arch/arm/mach-imx/vf610.c b/arch/arm/mach-imx/vf610.c new file mode 100644 index 0000000000..c535716c10 --- /dev/null +++ b/arch/arm/mach-imx/vf610.c @@ -0,0 +1,59 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <init.h> +#include <common.h> +#include <io.h> +#include <linux/sizes.h> +#include <mach/generic.h> +#include <mach/revision.h> +#include <mach/vf610.h> +#include <mach/reset-reason.h> + +static const struct imx_reset_reason vf610_reset_reasons[] = { + { VF610_SRC_SRSR_POR_RST, RESET_POR, 0 }, + { VF610_SRC_SRSR_WDOG_A5, RESET_WDG, 0 }, + { VF610_SRC_SRSR_WDOG_M4, RESET_WDG, 1 }, + { VF610_SRC_SRSR_JTAG_RST, RESET_JTAG, 0 }, + { VF610_SRC_SRSR_RESETB, RESET_EXT, 0 }, + { VF610_SRC_SRSR_SW_RST, RESET_RST, 0 }, + { /* sentinel */ } +}; + +int vf610_init(void) +{ + const char *cputypestr; + void __iomem *src = IOMEM(VF610_SRC_BASE_ADDR); + + switch (vf610_cpu_type()) { + case VF610_CPUTYPE_VF610: + cputypestr = "VF610"; + break; + case VF610_CPUTYPE_VF600: + cputypestr = "VF600"; + break; + case VF610_CPUTYPE_VF510: + cputypestr = "VF510"; + break; + case VF610_CPUTYPE_VF500: + cputypestr = "VF500"; + break; + default: + cputypestr = "unknown VFxxx"; + break; + } + + imx_set_silicon_revision(cputypestr, vf610_cpu_revision()); + imx_set_reset_reason(src + IMX_SRC_SRSR, vf610_reset_reasons); + return 0; +} diff --git a/arch/arm/mach-imx/xload.c b/arch/arm/mach-imx/xload.c index 16d56ab288..921e9ade20 100644 --- a/arch/arm/mach-imx/xload.c +++ b/arch/arm/mach-imx/xload.c @@ -24,7 +24,7 @@ static __noreturn int imx_xload(void) pr_info("booting from MMC\n"); buf = bootstrap_read_disk("disk0.0", "fat"); break; - case BOOTSOURCE_SPI: + case BOOTSOURCE_SPI_NOR: pr_info("booting from SPI\n"); buf = bootstrap_read_devfs("dataflash0", false, SZ_256K, SZ_1M, SZ_1M); |